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i40e: Fix an incorrect OEM version string
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e.h
CommitLineData
7daa6bf3
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
88eee9bc 4 * Copyright(c) 2013 - 2015 Intel Corporation.
7daa6bf3
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
7daa6bf3
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_H_
28#define _I40E_H_
29
30#include <net/tcp.h>
8144f0f7 31#include <net/udp.h>
7daa6bf3
JB		 32#include <linux/types.h>
33#include <linux/errno.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/aer.h>
37#include <linux/netdevice.h>
38#include <linux/ioport.h>
2bc7ee8a 39#include <linux/iommu.h>
7daa6bf3
JB		 40#include <linux/slab.h>
41#include <linux/list.h>
42#include <linux/string.h>
43#include <linux/in.h>
44#include <linux/ip.h>
45#include <linux/tcp.h>
46#include <linux/sctp.h>
47#include <linux/pkt_sched.h>
48#include <linux/ipv6.h>
7daa6bf3
JB		 49#include <net/checksum.h>
50#include <net/ip6_checksum.h>
51#include <linux/ethtool.h>
52#include <linux/if_vlan.h>
51616018 53#include <linux/if_bridge.h>
beb0dff1
JK		 54#include <linux/clocksource.h>
55#include <linux/net_tstamp.h>
56#include <linux/ptp_clock_kernel.h>
7daa6bf3
JB		 57#include "i40e_type.h"
58#include "i40e_prototype.h"
38e00438
VD		 59#ifdef I40E_FCOE
60#include "i40e_fcoe.h"
61#endif
7daa6bf3
JB		 62#include "i40e_virtchnl.h"
63#include "i40e_virtchnl_pf.h"
64#include "i40e_txrx.h"
4e3b35b0 65#include "i40e_dcb.h"
7daa6bf3
JB		 66
67/* Useful i40e defaults */
68#define I40E_BASE_PF_SEID 16
69#define I40E_BASE_VSI_SEID 512
70#define I40E_BASE_VEB_SEID 288
71#define I40E_MAX_VEB 16
72
73#define I40E_MAX_NUM_DESCRIPTORS 4096
232f4706 74#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
7daa6bf3
JB		 75#define I40E_DEFAULT_NUM_DESCRIPTORS 512
76#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
77#define I40E_MIN_NUM_DESCRIPTORS 64
78#define I40E_MIN_MSIX 2
79#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
505682cd 80#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */
e25d00b8
ASJ		 81/* max 16 qps */
82#define i40e_default_queues_per_vmdq(pf) \
83 (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
7daa6bf3
JB		 84#define I40E_DEFAULT_QUEUES_PER_VF 4
85#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
e25d00b8
ASJ		 86#define i40e_pf_get_max_q_per_tc(pf) \
87 (((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
7daa6bf3
JB		 88#define I40E_FDIR_RING 0
89#define I40E_FDIR_RING_COUNT 32
38e00438
VD		 90#ifdef I40E_FCOE
91#define I40E_DEFAULT_FCOE 8 /* default number of QPs for FCoE */
92#define I40E_MINIMUM_FCOE 1 /* minimum number of QPs for FCoE */
93#endif /* I40E_FCOE */
7daa6bf3 94#define I40E_MAX_AQ_BUF_SIZE 4096
07574897 95#define I40E_AQ_LEN 256
628f096d 96#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
7daa6bf3
JB		 97#define I40E_MAX_USER_PRIORITY 8
98#define I40E_DEFAULT_MSG_ENABLE 4
23527308 99#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
fba52e21 100#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
7daa6bf3 101
7e45ab44 102/* Ethtool Private Flags */
41a1d04b 103#define I40E_PRIV_FLAGS_NPAR_FLAG BIT(0)
9ac77266 104#define I40E_PRIV_FLAGS_LINKPOLL_FLAG BIT(1)
ef17178c 105#define I40E_PRIV_FLAGS_FD_ATR BIT(2)
1cdfd88f 106#define I40E_PRIV_FLAGS_VEB_STATS BIT(3)
7e45ab44 107
7daa6bf3 108#define I40E_NVM_VERSION_LO_SHIFT 0
fe310704 109#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
ff80301e
JB		 110#define I40E_NVM_VERSION_HI_SHIFT 12
111#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
2efaad86 112#define I40E_OEM_VER_BUILD_MASK 0xffff
f0b44440 113#define I40E_OEM_VER_PATCH_MASK 0xff
2efaad86
CW		 114#define I40E_OEM_VER_BUILD_SHIFT 8
115#define I40E_OEM_VER_SHIFT 24
fe310704
AS		 116
117/* The values in here are decimal coded as hex as is the case in the NVM map*/
118#define I40E_CURRENT_NVM_VERSION_HI 0x2
ff80301e 119#define I40E_CURRENT_NVM_VERSION_LO 0x40
fe310704 120
7daa6bf3
JB		 121/* magic for getting defines into strings */
122#define STRINGIFY(foo) #foo
123#define XSTRINGIFY(bar) STRINGIFY(bar)
124
7daa6bf3
JB		 125#define I40E_RX_DESC(R, i) \
126 ((ring_is_16byte_desc_enabled(R)) \
127 ? (union i40e_32byte_rx_desc *) \
128 (&(((union i40e_16byte_rx_desc *)((R)->desc))[i])) \
129 : (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])))
130#define I40E_TX_DESC(R, i) \
131 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
132#define I40E_TX_CTXTDESC(R, i) \
133 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
134#define I40E_TX_FDIRDESC(R, i) \
135 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
136
137/* default to trying for four seconds */
138#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
139
140/* driver state flags */
141enum i40e_state_t {
142 __I40E_TESTING,
143 __I40E_CONFIG_BUSY,
144 __I40E_CONFIG_DONE,
145 __I40E_DOWN,
146 __I40E_NEEDS_RESTART,
147 __I40E_SERVICE_SCHED,
148 __I40E_ADMINQ_EVENT_PENDING,
149 __I40E_MDD_EVENT_PENDING,
150 __I40E_VFLR_EVENT_PENDING,
151 __I40E_RESET_RECOVERY_PENDING,
152 __I40E_RESET_INTR_RECEIVED,
153 __I40E_REINIT_REQUESTED,
154 __I40E_PF_RESET_REQUESTED,
155 __I40E_CORE_RESET_REQUESTED,
156 __I40E_GLOBAL_RESET_REQUESTED,
7823fe34 157 __I40E_EMP_RESET_REQUESTED,
9df42d1a 158 __I40E_EMP_RESET_INTR_RECEIVED,
7daa6bf3 159 __I40E_FILTER_OVERFLOW_PROMISC,
9007bccd 160 __I40E_SUSPENDED,
9ce34f02 161 __I40E_PTP_TX_IN_PROGRESS,
4eb3f768 162 __I40E_BAD_EEPROM,
b5d06f05 163 __I40E_DOWN_REQUESTED,
1e1be8f6 164 __I40E_FD_FLUSH_REQUESTED,
a316f651 165 __I40E_RESET_FAILED,
69129dc3 166 __I40E_PORT_TX_SUSPENDED,
3ba9bcb4 167 __I40E_VF_DISABLE,
7daa6bf3
JB		 168};
169
170enum i40e_interrupt_policy {
171 I40E_INTERRUPT_BEST_CASE,
172 I40E_INTERRUPT_MEDIUM,
173 I40E_INTERRUPT_LOWEST
174};
175
176struct i40e_lump_tracking {
177 u16 num_entries;
178 u16 search_hint;
179 u16 list[0];
180#define I40E_PILE_VALID_BIT 0x8000
181};
182
183#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
55a5e60b
ASJ		 184#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
185#define I40E_FDIR_BUFFER_FULL_MARGIN 10
12957388 186#define I40E_FDIR_BUFFER_HEAD_ROOM 32
04294e38 187#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
55a5e60b 188
b29e13bb
MW		 189#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
190
433c47de
ASJ		 191enum i40e_fd_stat_idx {
192 I40E_FD_STAT_ATR,
193 I40E_FD_STAT_SB,
60ccd45c 194 I40E_FD_STAT_ATR_TUNNEL,
433c47de
ASJ		 195 I40E_FD_STAT_PF_COUNT
196};
197#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
198#define I40E_FD_ATR_STAT_IDX(pf_id) \
199 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
200#define I40E_FD_SB_STAT_IDX(pf_id) \
201 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
60ccd45c
ASJ		 202#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
203 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
433c47de 204
17a73f6b
JG		 205struct i40e_fdir_filter {
206 struct hlist_node fdir_node;
207 /* filter ipnut set */
208 u8 flow_type;
209 u8 ip4_proto;
04b73bd7 210 /* TX packet view of src and dst */
17a73f6b
JG		 211 __be32 dst_ip[4];
212 __be32 src_ip[4];
213 __be16 src_port;
214 __be16 dst_port;
215 __be32 sctp_v_tag;
216 /* filter control */
7daa6bf3
JB		 217 u16 q_index;
218 u8 flex_off;
219 u8 pctype;
220 u16 dest_vsi;
221 u8 dest_ctl;
222 u8 fd_status;
223 u16 cnt_index;
224 u32 fd_id;
7daa6bf3
JB		 225};
226
4e3b35b0
NP		 227#define I40E_ETH_P_LLDP 0x88cc
228
7daa6bf3
JB		 229#define I40E_DCB_PRIO_TYPE_STRICT 0
230#define I40E_DCB_PRIO_TYPE_ETS 1
231#define I40E_DCB_STRICT_PRIO_CREDITS 127
232#define I40E_MAX_USER_PRIORITY 8
233/* DCB per TC information data structure */
234struct i40e_tc_info {
235 u16 qoffset; /* Queue offset from base queue */
236 u16 qcount; /* Total Queues */
237 u8 netdev_tc; /* Netdev TC index if netdev associated */
238};
239
240/* TC configuration data structure */
241struct i40e_tc_configuration {
242 u8 numtc; /* Total number of enabled TCs */
243 u8 enabled_tc; /* TC map */
244 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
245};
246
247/* struct that defines the Ethernet device */
248struct i40e_pf {
249 struct pci_dev *pdev;
250 struct i40e_hw hw;
251 unsigned long state;
7daa6bf3 252 struct msix_entry *msix_entries;
7daa6bf3
JB		 253 bool fc_autoneg_status;
254
255 u16 eeprom_version;
b40c82e6 256 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
7daa6bf3
JB		 257 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
258 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
b40c82e6
JK		 259 u16 num_req_vfs; /* num VFs requested for this VF */
260 u16 num_vf_qps; /* num queue pairs per VF */
38e00438 261#ifdef I40E_FCOE
b40c82e6 262 u16 num_fcoe_qps; /* num fcoe queues this PF has set up */
38e00438
VD		 263 u16 num_fcoe_msix; /* num queue vectors per fcoe pool */
264#endif /* I40E_FCOE */
b40c82e6
JK		 265 u16 num_lan_qps; /* num lan queues this PF has set up */
266 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
f8ff1464 267 int queues_left; /* queues left unclaimed */
7daa6bf3
JB		 268 u16 rss_size; /* num queues in the RSS array */
269 u16 rss_size_max; /* HW defined max RSS queues */
270 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
505682cd 271 u16 num_alloc_vsi; /* num VSIs this driver supports */
7daa6bf3 272 u8 atr_sample_rate;
8e2773ae 273 bool wol_en;
7daa6bf3 274
17a73f6b
JG		 275 struct hlist_head fdir_filter_list;
276 u16 fdir_pf_active_filters;
1e1be8f6 277 unsigned long fd_flush_timestamp;
60793f4a 278 u32 fd_flush_cnt;
1e1be8f6
ASJ		 279 u32 fd_add_err;
280 u32 fd_atr_cnt;
281 u32 fd_tcp_rule;
17a73f6b 282
a1c9a9d9
JK		 283#ifdef CONFIG_I40E_VXLAN
284 __be16 vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
285 u16 pending_vxlan_bitmap;
286
287#endif
7daa6bf3
JB		 288 enum i40e_interrupt_policy int_policy;
289 u16 rx_itr_default;
290 u16 tx_itr_default;
71e6163a 291 u32 msg_enable;
b294ac70 292 char int_name[I40E_INT_NAME_STR_LEN];
7daa6bf3 293 u16 adminq_work_limit; /* num of admin receive queue desc to process */
21536717
SN		 294 unsigned long service_timer_period;
295 unsigned long service_timer_previous;
7daa6bf3
JB		 296 struct timer_list service_timer;
297 struct work_struct service_task;
298
299 u64 flags;
41a1d04b
JB		 300#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
301#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
302#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
303#define I40E_FLAG_RX_1BUF_ENABLED BIT_ULL(4)
304#define I40E_FLAG_RX_PS_ENABLED BIT_ULL(5)
305#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
306#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
307#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
308#define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
d502ce01 309#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
38e00438 310#ifdef I40E_FCOE
41a1d04b 311#define I40E_FLAG_FCOE_ENABLED BIT_ULL(11)
38e00438 312#endif /* I40E_FCOE */
41a1d04b
JB		 313#define I40E_FLAG_16BYTE_RX_DESC_ENABLED BIT_ULL(13)
314#define I40E_FLAG_CLEAN_ADMINQ BIT_ULL(14)
315#define I40E_FLAG_FILTER_SYNC BIT_ULL(15)
316#define I40E_FLAG_PROCESS_MDD_EVENT BIT_ULL(17)
317#define I40E_FLAG_PROCESS_VFLR_EVENT BIT_ULL(18)
318#define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19)
319#define I40E_FLAG_DCB_ENABLED BIT_ULL(20)
320#define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21)
321#define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22)
322#define I40E_FLAG_PTP BIT_ULL(25)
323#define I40E_FLAG_MFP_ENABLED BIT_ULL(26)
a1c9a9d9 324#ifdef CONFIG_I40E_VXLAN
41a1d04b 325#define I40E_FLAG_VXLAN_FILTER_SYNC BIT_ULL(27)
a1c9a9d9 326#endif
41a1d04b
JB		 327#define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)
328#define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
d502ce01
ASJ		 329#define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31)
330#define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32)
331#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33)
332#define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34)
333#define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35)
d1a8d275 334#define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37)
d502ce01 335#define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38)
9ac77266 336#define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39)
fc60861e 337#define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)
3fced535 338#define I40E_FLAG_NO_PCI_LINK_CHECK BIT_ULL(42)
7daa6bf3 339
61dade7e
ASJ		 340 /* tracks features that get auto disabled by errors */
341 u64 auto_disable_flags;
342
38e00438
VD		 343#ifdef I40E_FCOE
344 struct i40e_fcoe fcoe;
345
346#endif /* I40E_FCOE */
7daa6bf3
JB		 347 bool stat_offsets_loaded;
348 struct i40e_hw_port_stats stats;
349 struct i40e_hw_port_stats stats_offsets;
350 u32 tx_timeout_count;
351 u32 tx_timeout_recovery_level;
352 unsigned long tx_timeout_last_recovery;
810b3ae4 353 u32 tx_sluggish_count;
7daa6bf3
JB		 354 u32 hw_csum_rx_error;
355 u32 led_status;
356 u16 corer_count; /* Core reset count */
357 u16 globr_count; /* Global reset count */
358 u16 empr_count; /* EMP reset count */
359 u16 pfr_count; /* PF reset count */
cd92e72f 360 u16 sw_int_count; /* SW interrupt count */
7daa6bf3
JB		 361
362 struct mutex switch_mutex;
363 u16 lan_vsi; /* our default LAN VSI */
364 u16 lan_veb; /* initial relay, if exists */
365#define I40E_NO_VEB 0xffff
366#define I40E_NO_VSI 0xffff
367 u16 next_vsi; /* Next unallocated VSI - 0-based! */
368 struct i40e_vsi **vsi;
369 struct i40e_veb *veb[I40E_MAX_VEB];
370
371 struct i40e_lump_tracking *qp_pile;
372 struct i40e_lump_tracking *irq_pile;
373
374 /* switch config info */
375 u16 pf_seid;
376 u16 main_vsi_seid;
377 u16 mac_seid;
7daa6bf3
JB		 378 struct kobject *switch_kobj;
379#ifdef CONFIG_DEBUG_FS
380 struct dentry *i40e_dbg_pf;
381#endif /* CONFIG_DEBUG_FS */
92faef85 382 bool cur_promisc;
7daa6bf3 383
93cd765b
ASJ		 384 u16 instance; /* A unique number per i40e_pf instance in the system */
385
7daa6bf3
JB		 386 /* sr-iov config info */
387 struct i40e_vf *vf;
388 int num_alloc_vfs; /* actual number of VFs allocated */
389 u32 vf_aq_requests;
390
391 /* DCBx/DCBNL capability for PF that indicates
392 * whether DCBx is managed by firmware or host
393 * based agent (LLDPAD). Also, indicates what
394 * flavor of DCBx protocol (IEEE/CEE) is supported
395 * by the device. For now we're supporting IEEE
396 * mode only.
397 */
398 u16 dcbx_cap;
399
400 u32 fcoe_hmc_filt_num;
401 u32 fcoe_hmc_cntx_num;
402 struct i40e_filter_control_settings filter_settings;
beb0dff1
JK		 403
404 struct ptp_clock *ptp_clock;
405 struct ptp_clock_info ptp_caps;
406 struct sk_buff *ptp_tx_skb;
beb0dff1 407 struct hwtstamp_config tstamp_config;
beb0dff1
JK		 408 unsigned long last_rx_ptp_check;
409 spinlock_t tmreg_lock; /* Used to protect the device time registers. */
410 u64 ptp_base_adj;
411 u32 tx_hwtstamp_timeouts;
412 u32 rx_hwtstamp_cleared;
413 bool ptp_tx;
414 bool ptp_rx;
e157ea30 415 u16 rss_table_size;
f4492db1
GR		 416 /* These are only valid in NPAR modes */
417 u32 npar_max_bw;
418 u32 npar_min_bw;
2ac8b675
SN		 419
420 u32 ioremap_len;
3487b6c3 421 u32 fd_inv;
7daa6bf3
JB		 422};
423
424struct i40e_mac_filter {
425 struct list_head list;
426 u8 macaddr[ETH_ALEN];
427#define I40E_VLAN_ANY -1
428 s16 vlan;
429 u8 counter; /* number of instances of this filter */
430 bool is_vf; /* filter belongs to a VF */
431 bool is_netdev; /* filter belongs to a netdev */
432 bool changed; /* filter needs to be sync'd to the HW */
6252c7e4 433 bool is_laa; /* filter is a Locally Administered Address */
7daa6bf3
JB		 434};
435
436struct i40e_veb {
437 struct i40e_pf *pf;
438 u16 idx;
439 u16 veb_idx; /* index of VEB parent */
440 u16 seid;
441 u16 uplink_seid;
442 u16 stats_idx; /* index of VEB parent */
443 u8 enabled_tc;
51616018 444 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
7daa6bf3
JB		 445 u16 flags;
446 u16 bw_limit;
447 u8 bw_max_quanta;
448 bool is_abs_credits;
449 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
450 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
451 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
452 struct kobject *kobj;
453 bool stat_offsets_loaded;
454 struct i40e_eth_stats stats;
455 struct i40e_eth_stats stats_offsets;
fe860afb
NP		 456 struct i40e_veb_tc_stats tc_stats;
457 struct i40e_veb_tc_stats tc_stats_offsets;
7daa6bf3
JB		 458};
459
460/* struct that defines a VSI, associated with a dev */
461struct i40e_vsi {
462 struct net_device *netdev;
463 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
464 bool netdev_registered;
465 bool stat_offsets_loaded;
466
467 u32 current_netdev_flags;
468 unsigned long state;
41a1d04b
JB		 469#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
470#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
7daa6bf3
JB		 471 unsigned long flags;
472
21659035
KP		 473 /* Per VSI lock to protect elements/list (MAC filter) */
474 spinlock_t mac_filter_list_lock;
7daa6bf3
JB		 475 struct list_head mac_filter_list;
476
477 /* VSI stats */
478 struct rtnl_link_stats64 net_stats;
479 struct rtnl_link_stats64 net_stats_offsets;
480 struct i40e_eth_stats eth_stats;
481 struct i40e_eth_stats eth_stats_offsets;
38e00438
VD		 482#ifdef I40E_FCOE
483 struct i40e_fcoe_stats fcoe_stats;
484 struct i40e_fcoe_stats fcoe_stats_offsets;
485 bool fcoe_stat_offsets_loaded;
486#endif
7daa6bf3
JB		 487 u32 tx_restart;
488 u32 tx_busy;
2fc3d715 489 u64 tx_linearize;
7daa6bf3
JB		 490 u32 rx_buf_failed;
491 u32 rx_page_failed;
492
9f65e15b
AD		 493 /* These are containers of ring pointers, allocated at run-time */
494 struct i40e_ring **rx_rings;
495 struct i40e_ring **tx_rings;
7daa6bf3
JB		 496
497 u16 work_limit;
498 /* high bit set means dynamic, use accessor routines to read/write.
499 * hardware only supports 2us resolution for the ITR registers.
500 * these values always store the USER setting, and must be converted
501 * before programming to a register.
502 */
503 u16 rx_itr_setting;
504 u16 tx_itr_setting;
ac26fc13 505 u16 int_rate_limit; /* value in usecs */
7daa6bf3 506
5db4cb59 507 u16 rss_table_size;
66ddcffb 508 u16 rss_size;
5db4cb59 509
7daa6bf3
JB		 510 u16 max_frame;
511 u16 rx_hdr_len;
512 u16 rx_buf_len;
513 u8 dtype;
514
515 /* List of q_vectors allocated to this VSI */
493fb300 516 struct i40e_q_vector **q_vectors;
7daa6bf3
JB		 517 int num_q_vectors;
518 int base_vector;
63741846 519 bool irqs_ready;
7daa6bf3
JB		 520
521 u16 seid; /* HW index of this VSI (absolute index) */
522 u16 id; /* VSI number */
523 u16 uplink_seid;
524
525 u16 base_queue; /* vsi's first queue in hw array */
526 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
9a3bd2f1 527 u16 req_queue_pairs; /* User requested queue pairs */
7daa6bf3
JB		 528 u16 num_queue_pairs; /* Used tx and rx pairs */
529 u16 num_desc;
530 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
531 u16 vf_id; /* Virtual function ID for SRIOV VSIs */
532
533 struct i40e_tc_configuration tc_config;
534 struct i40e_aqc_vsi_properties_data info;
535
536 /* VSI BW limit (absolute across all TCs) */
537 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
538 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
539
540 /* Relative TC credits across VSIs */
541 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
542 /* TC BW limit credits within VSI */
543 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
544 /* TC BW limit max quanta within VSI */
545 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
546
547 struct i40e_pf *back; /* Backreference to associated PF */
548 u16 idx; /* index in pf->vsi[] */
549 u16 veb_idx; /* index of VEB parent */
550 struct kobject *kobj; /* sysfs object */
c156f856 551 bool current_isup; /* Sync 'link up' logging */
7daa6bf3
JB		 552
553 /* VSI specific handlers */
554 irqreturn_t (*irq_handler)(int irq, void *data);
88eee9bc
CW		 555
556 /* current rxnfc data */
557 struct ethtool_rxnfc rxnfc; /* current rss hash opts */
7daa6bf3
JB		 558} ____cacheline_internodealigned_in_smp;
559
560struct i40e_netdev_priv {
561 struct i40e_vsi *vsi;
562};
563
564/* struct that defines an interrupt vector */
565struct i40e_q_vector {
566 struct i40e_vsi *vsi;
567
568 u16 v_idx; /* index in the vsi->q_vector array. */
569 u16 reg_idx; /* register index of the interrupt */
570
571 struct napi_struct napi;
572
573 struct i40e_ring_container rx;
574 struct i40e_ring_container tx;
575
576 u8 num_ringpairs; /* total number of ring pairs in vector */
577
7daa6bf3 578 cpumask_t affinity_mask;
493fb300 579 struct rcu_head rcu; /* to avoid race with update stats on free */
b294ac70 580 char name[I40E_INT_NAME_STR_LEN];
8e0764b4 581 bool arm_wb_state;
ee2319cf
JB		 582#define ITR_COUNTDOWN_START 100
583 u8 itr_countdown; /* when 0 should adjust ITR */
7daa6bf3
JB		 584} ____cacheline_internodealigned_in_smp;
585
586/* lan device */
587struct i40e_device {
588 struct list_head list;
589 struct i40e_pf *pf;
590};
591
592/**
6dec1017 593 * i40e_nvm_version_str - format the NVM version strings
7daa6bf3
JB		 594 * @hw: ptr to the hardware info
595 **/
6dec1017 596static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
7daa6bf3
JB		 597{
598 static char buf[32];
2efaad86
CW		 599 u32 full_ver;
600 u8 ver, patch;
601 u16 build;
602
603 full_ver = hw->nvm.oem_ver;
604 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
605 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT)
606 & I40E_OEM_VER_BUILD_MASK);
607 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
7daa6bf3
JB		 608
609 snprintf(buf, sizeof(buf),
f0b44440 610 "%x.%02x 0x%x %d.%d.%d",
ff80301e
JB		 611 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
612 I40E_NVM_VERSION_HI_SHIFT,
613 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
614 I40E_NVM_VERSION_LO_SHIFT,
2efaad86 615 hw->nvm.eetrack, ver, build, patch);
7daa6bf3
JB		 616
617 return buf;
618}
619
620/**
621 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
622 * @netdev: the corresponding netdev
623 *
624 * Return the PF struct for the given netdev
625 **/
626static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
627{
628 struct i40e_netdev_priv *np = netdev_priv(netdev);
629 struct i40e_vsi *vsi = np->vsi;
630
631 return vsi->back;
632}
633
634static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
635 irqreturn_t (*irq_handler)(int, void *))
636{
637 vsi->irq_handler = irq_handler;
638}
639
640/**
641 * i40e_rx_is_programming_status - check for programming status descriptor
642 * @qw: the first quad word of the program status descriptor
643 *
644 * The value of in the descriptor length field indicate if this
645 * is a programming status descriptor for flow director or FCoE
646 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
647 * it is a packet descriptor.
648 **/
649static inline bool i40e_rx_is_programming_status(u64 qw)
650{
651 return I40E_RX_PROG_STATUS_DESC_LENGTH ==
652 (qw >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT);
653}
654
082def10
ASJ		 655/**
656 * i40e_get_fd_cnt_all - get the total FD filter space available
b40c82e6 657 * @pf: pointer to the PF struct
082def10
ASJ		 658 **/
659static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
660{
661 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
662}
663
7daa6bf3
JB		 664/* needed by i40e_ethtool.c */
665int i40e_up(struct i40e_vsi *vsi);
666void i40e_down(struct i40e_vsi *vsi);
667extern const char i40e_driver_name[];
668extern const char i40e_driver_version_str[];
23326186 669void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
7daa6bf3 670void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags);
fdf0e0bf 671struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
7daa6bf3
JB		 672void i40e_update_stats(struct i40e_vsi *vsi);
673void i40e_update_eth_stats(struct i40e_vsi *vsi);
674struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
675int i40e_fetch_switch_configuration(struct i40e_pf *pf,
676 bool printconfig);
677
17a73f6b 678int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
7daa6bf3 679 struct i40e_pf *pf, bool add);
17a73f6b
JG		 680int i40e_add_del_fdir(struct i40e_vsi *vsi,
681 struct i40e_fdir_filter *input, bool add);
55a5e60b 682void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
04294e38
ASJ		 683u32 i40e_get_current_fd_count(struct i40e_pf *pf);
684u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
685u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
686u32 i40e_get_global_fd_count(struct i40e_pf *pf);
7c3c288b 687bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
7daa6bf3
JB		 688void i40e_set_ethtool_ops(struct net_device *netdev);
689struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
690 u8 *macaddr, s16 vlan,
691 bool is_vf, bool is_netdev);
692void i40e_del_filter(struct i40e_vsi *vsi, u8 *macaddr, s16 vlan,
693 bool is_vf, bool is_netdev);
30e2561b 694int i40e_sync_vsi_filters(struct i40e_vsi *vsi, bool grab_rtnl);
7daa6bf3
JB		 695struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
696 u16 uplink, u32 param1);
697int i40e_vsi_release(struct i40e_vsi *vsi);
698struct i40e_vsi *i40e_vsi_lookup(struct i40e_pf *pf, enum i40e_vsi_type type,
699 struct i40e_vsi *start_vsi);
38e00438
VD		 700#ifdef I40E_FCOE
701void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
702 struct i40e_vsi_context *ctxt,
703 u8 enabled_tc, bool is_add);
704#endif
fc18eaa0 705int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool enable);
f8ff1464 706int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
7daa6bf3
JB		 707struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
708 u16 downlink_seid, u8 enabled_tc);
709void i40e_veb_release(struct i40e_veb *veb);
710
4e3b35b0 711int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
7daa6bf3
JB		 712i40e_status i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
713void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
714void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
715void i40e_pf_reset_stats(struct i40e_pf *pf);
716#ifdef CONFIG_DEBUG_FS
717void i40e_dbg_pf_init(struct i40e_pf *pf);
718void i40e_dbg_pf_exit(struct i40e_pf *pf);
719void i40e_dbg_init(void);
720void i40e_dbg_exit(void);
721#else
722static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
723static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
724static inline void i40e_dbg_init(void) {}
725static inline void i40e_dbg_exit(void) {}
726#endif /* CONFIG_DEBUG_FS*/
02d109be
JB		 727/**
728 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
729 * @vsi: pointer to a vsi
730 * @vector: enable a particular Hw Interrupt vector, without base_vector
731 **/
732static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
733{
734 struct i40e_pf *pf = vsi->back;
735 struct i40e_hw *hw = &pf->hw;
736 u32 val;
737
738 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
739 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
740 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
741 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
742 /* skip the flush */
743}
744
5c2cebda 745void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector);
2ef28cfb 746void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
116a57d4 747void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
38e00438
VD		 748#ifdef I40E_FCOE
749struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
750 struct net_device *netdev,
751 struct rtnl_link_stats64 *storage);
752int i40e_set_mac(struct net_device *netdev, void *p);
753void i40e_set_rx_mode(struct net_device *netdev);
754#endif
7daa6bf3 755int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
38e00438
VD		 756#ifdef I40E_FCOE
757void i40e_tx_timeout(struct net_device *netdev);
758int i40e_vlan_rx_add_vid(struct net_device *netdev,
759 __always_unused __be16 proto, u16 vid);
760int i40e_vlan_rx_kill_vid(struct net_device *netdev,
761 __always_unused __be16 proto, u16 vid);
762#endif
96664483 763int i40e_open(struct net_device *netdev);
6c167f58 764int i40e_vsi_open(struct i40e_vsi *vsi);
7daa6bf3
JB		 765void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
766int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid);
767int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid);
768struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
769 bool is_vf, bool is_netdev);
770bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
771struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
772 bool is_vf, bool is_netdev);
38e00438 773#ifdef I40E_FCOE
38e00438
VD		 774int i40e_close(struct net_device *netdev);
775int i40e_setup_tc(struct net_device *netdev, u8 tc);
776void i40e_netpoll(struct net_device *netdev);
777int i40e_fcoe_enable(struct net_device *netdev);
778int i40e_fcoe_disable(struct net_device *netdev);
779int i40e_fcoe_vsi_init(struct i40e_vsi *vsi, struct i40e_vsi_context *ctxt);
780u8 i40e_get_fcoe_tc_map(struct i40e_pf *pf);
781void i40e_fcoe_config_netdev(struct net_device *netdev, struct i40e_vsi *vsi);
782void i40e_fcoe_vsi_setup(struct i40e_pf *pf);
21364bcf 783void i40e_init_pf_fcoe(struct i40e_pf *pf);
38e00438
VD		 784int i40e_fcoe_setup_ddp_resources(struct i40e_vsi *vsi);
785void i40e_fcoe_free_ddp_resources(struct i40e_vsi *vsi);
786int i40e_fcoe_handle_offload(struct i40e_ring *rx_ring,
787 union i40e_rx_desc *rx_desc,
788 struct sk_buff *skb);
789void i40e_fcoe_handle_status(struct i40e_ring *rx_ring,
790 union i40e_rx_desc *rx_desc, u8 prog_id);
791#endif /* I40E_FCOE */
7daa6bf3 792void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
4e3b35b0
NP		 793#ifdef CONFIG_I40E_DCB
794void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
750fcbcf 795 struct i40e_dcbx_config *old_cfg,
4e3b35b0
NP		 796 struct i40e_dcbx_config *new_cfg);
797void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
798void i40e_dcbnl_setup(struct i40e_vsi *vsi);
799bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
800 struct i40e_dcbx_config *old_cfg,
801 struct i40e_dcbx_config *new_cfg);
802#endif /* CONFIG_I40E_DCB */
beb0dff1
JK		 803void i40e_ptp_rx_hang(struct i40e_vsi *vsi);
804void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
805void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
806void i40e_ptp_set_increment(struct i40e_pf *pf);
807int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
808int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
809void i40e_ptp_init(struct i40e_pf *pf);
810void i40e_ptp_stop(struct i40e_pf *pf);
51616018 811int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
f4492db1
GR		 812i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf);
813i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf);
814i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf);
c156f856 815void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
7daa6bf3 816#endif /* _I40E_H_ */
Linux kernel - Deliverables
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