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7daa6bf3 JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
88eee9bc | 4 | * Copyright(c) 2013 - 2015 Intel Corporation. |
7daa6bf3 JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
7daa6bf3 JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
27 | #ifndef _I40E_H_ | |
28 | #define _I40E_H_ | |
29 | ||
30 | #include <net/tcp.h> | |
8144f0f7 | 31 | #include <net/udp.h> |
7daa6bf3 JB |
32 | #include <linux/types.h> |
33 | #include <linux/errno.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/aer.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/ioport.h> | |
2bc7ee8a | 39 | #include <linux/iommu.h> |
7daa6bf3 JB |
40 | #include <linux/slab.h> |
41 | #include <linux/list.h> | |
42 | #include <linux/string.h> | |
43 | #include <linux/in.h> | |
44 | #include <linux/ip.h> | |
7daa6bf3 JB |
45 | #include <linux/sctp.h> |
46 | #include <linux/pkt_sched.h> | |
47 | #include <linux/ipv6.h> | |
7daa6bf3 JB |
48 | #include <net/checksum.h> |
49 | #include <net/ip6_checksum.h> | |
50 | #include <linux/ethtool.h> | |
51 | #include <linux/if_vlan.h> | |
51616018 | 52 | #include <linux/if_bridge.h> |
beb0dff1 JK |
53 | #include <linux/clocksource.h> |
54 | #include <linux/net_tstamp.h> | |
55 | #include <linux/ptp_clock_kernel.h> | |
7daa6bf3 JB |
56 | #include "i40e_type.h" |
57 | #include "i40e_prototype.h" | |
38e00438 VD |
58 | #ifdef I40E_FCOE |
59 | #include "i40e_fcoe.h" | |
60 | #endif | |
7daa6bf3 JB |
61 | #include "i40e_virtchnl.h" |
62 | #include "i40e_virtchnl_pf.h" | |
63 | #include "i40e_txrx.h" | |
4e3b35b0 | 64 | #include "i40e_dcb.h" |
7daa6bf3 JB |
65 | |
66 | /* Useful i40e defaults */ | |
67 | #define I40E_BASE_PF_SEID 16 | |
68 | #define I40E_BASE_VSI_SEID 512 | |
69 | #define I40E_BASE_VEB_SEID 288 | |
70 | #define I40E_MAX_VEB 16 | |
71 | ||
72 | #define I40E_MAX_NUM_DESCRIPTORS 4096 | |
232f4706 | 73 | #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) |
7daa6bf3 JB |
74 | #define I40E_DEFAULT_NUM_DESCRIPTORS 512 |
75 | #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 | |
76 | #define I40E_MIN_NUM_DESCRIPTORS 64 | |
77 | #define I40E_MIN_MSIX 2 | |
78 | #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ | |
505682cd | 79 | #define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */ |
e25d00b8 ASJ |
80 | /* max 16 qps */ |
81 | #define i40e_default_queues_per_vmdq(pf) \ | |
82 | (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1) | |
7daa6bf3 JB |
83 | #define I40E_DEFAULT_QUEUES_PER_VF 4 |
84 | #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ | |
e25d00b8 ASJ |
85 | #define i40e_pf_get_max_q_per_tc(pf) \ |
86 | (((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64) | |
7daa6bf3 JB |
87 | #define I40E_FDIR_RING 0 |
88 | #define I40E_FDIR_RING_COUNT 32 | |
38e00438 VD |
89 | #ifdef I40E_FCOE |
90 | #define I40E_DEFAULT_FCOE 8 /* default number of QPs for FCoE */ | |
91 | #define I40E_MINIMUM_FCOE 1 /* minimum number of QPs for FCoE */ | |
92 | #endif /* I40E_FCOE */ | |
7daa6bf3 | 93 | #define I40E_MAX_AQ_BUF_SIZE 4096 |
07574897 | 94 | #define I40E_AQ_LEN 256 |
628f096d | 95 | #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ |
7daa6bf3 JB |
96 | #define I40E_MAX_USER_PRIORITY 8 |
97 | #define I40E_DEFAULT_MSG_ENABLE 4 | |
23527308 | 98 | #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 |
fba52e21 | 99 | #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) |
7daa6bf3 | 100 | |
7e45ab44 | 101 | /* Ethtool Private Flags */ |
41a1d04b | 102 | #define I40E_PRIV_FLAGS_NPAR_FLAG BIT(0) |
9ac77266 | 103 | #define I40E_PRIV_FLAGS_LINKPOLL_FLAG BIT(1) |
ef17178c | 104 | #define I40E_PRIV_FLAGS_FD_ATR BIT(2) |
1cdfd88f | 105 | #define I40E_PRIV_FLAGS_VEB_STATS BIT(3) |
827de392 | 106 | #define I40E_PRIV_FLAGS_PS BIT(4) |
7e45ab44 | 107 | |
7daa6bf3 | 108 | #define I40E_NVM_VERSION_LO_SHIFT 0 |
fe310704 | 109 | #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) |
ff80301e JB |
110 | #define I40E_NVM_VERSION_HI_SHIFT 12 |
111 | #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) | |
2efaad86 | 112 | #define I40E_OEM_VER_BUILD_MASK 0xffff |
f0b44440 | 113 | #define I40E_OEM_VER_PATCH_MASK 0xff |
2efaad86 CW |
114 | #define I40E_OEM_VER_BUILD_SHIFT 8 |
115 | #define I40E_OEM_VER_SHIFT 24 | |
fe310704 AS |
116 | |
117 | /* The values in here are decimal coded as hex as is the case in the NVM map*/ | |
118 | #define I40E_CURRENT_NVM_VERSION_HI 0x2 | |
ff80301e | 119 | #define I40E_CURRENT_NVM_VERSION_LO 0x40 |
fe310704 | 120 | |
7daa6bf3 JB |
121 | /* magic for getting defines into strings */ |
122 | #define STRINGIFY(foo) #foo | |
123 | #define XSTRINGIFY(bar) STRINGIFY(bar) | |
124 | ||
7daa6bf3 JB |
125 | #define I40E_RX_DESC(R, i) \ |
126 | ((ring_is_16byte_desc_enabled(R)) \ | |
127 | ? (union i40e_32byte_rx_desc *) \ | |
128 | (&(((union i40e_16byte_rx_desc *)((R)->desc))[i])) \ | |
129 | : (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))) | |
130 | #define I40E_TX_DESC(R, i) \ | |
131 | (&(((struct i40e_tx_desc *)((R)->desc))[i])) | |
132 | #define I40E_TX_CTXTDESC(R, i) \ | |
133 | (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) | |
134 | #define I40E_TX_FDIRDESC(R, i) \ | |
135 | (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) | |
136 | ||
137 | /* default to trying for four seconds */ | |
138 | #define I40E_TRY_LINK_TIMEOUT (4 * HZ) | |
139 | ||
140 | /* driver state flags */ | |
141 | enum i40e_state_t { | |
142 | __I40E_TESTING, | |
143 | __I40E_CONFIG_BUSY, | |
144 | __I40E_CONFIG_DONE, | |
145 | __I40E_DOWN, | |
146 | __I40E_NEEDS_RESTART, | |
147 | __I40E_SERVICE_SCHED, | |
148 | __I40E_ADMINQ_EVENT_PENDING, | |
149 | __I40E_MDD_EVENT_PENDING, | |
150 | __I40E_VFLR_EVENT_PENDING, | |
151 | __I40E_RESET_RECOVERY_PENDING, | |
152 | __I40E_RESET_INTR_RECEIVED, | |
153 | __I40E_REINIT_REQUESTED, | |
154 | __I40E_PF_RESET_REQUESTED, | |
155 | __I40E_CORE_RESET_REQUESTED, | |
156 | __I40E_GLOBAL_RESET_REQUESTED, | |
7823fe34 | 157 | __I40E_EMP_RESET_REQUESTED, |
9df42d1a | 158 | __I40E_EMP_RESET_INTR_RECEIVED, |
7daa6bf3 | 159 | __I40E_FILTER_OVERFLOW_PROMISC, |
9007bccd | 160 | __I40E_SUSPENDED, |
9ce34f02 | 161 | __I40E_PTP_TX_IN_PROGRESS, |
4eb3f768 | 162 | __I40E_BAD_EEPROM, |
b5d06f05 | 163 | __I40E_DOWN_REQUESTED, |
1e1be8f6 | 164 | __I40E_FD_FLUSH_REQUESTED, |
a316f651 | 165 | __I40E_RESET_FAILED, |
69129dc3 | 166 | __I40E_PORT_TX_SUSPENDED, |
3ba9bcb4 | 167 | __I40E_VF_DISABLE, |
7daa6bf3 JB |
168 | }; |
169 | ||
170 | enum i40e_interrupt_policy { | |
171 | I40E_INTERRUPT_BEST_CASE, | |
172 | I40E_INTERRUPT_MEDIUM, | |
173 | I40E_INTERRUPT_LOWEST | |
174 | }; | |
175 | ||
176 | struct i40e_lump_tracking { | |
177 | u16 num_entries; | |
178 | u16 search_hint; | |
179 | u16 list[0]; | |
180 | #define I40E_PILE_VALID_BIT 0x8000 | |
181 | }; | |
182 | ||
183 | #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 | |
55a5e60b ASJ |
184 | #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 |
185 | #define I40E_FDIR_BUFFER_FULL_MARGIN 10 | |
12957388 | 186 | #define I40E_FDIR_BUFFER_HEAD_ROOM 32 |
04294e38 | 187 | #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) |
55a5e60b | 188 | |
b29e13bb | 189 | #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) |
e69ff813 | 190 | #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) |
b29e13bb | 191 | |
433c47de ASJ |
192 | enum i40e_fd_stat_idx { |
193 | I40E_FD_STAT_ATR, | |
194 | I40E_FD_STAT_SB, | |
60ccd45c | 195 | I40E_FD_STAT_ATR_TUNNEL, |
433c47de ASJ |
196 | I40E_FD_STAT_PF_COUNT |
197 | }; | |
198 | #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) | |
199 | #define I40E_FD_ATR_STAT_IDX(pf_id) \ | |
200 | (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) | |
201 | #define I40E_FD_SB_STAT_IDX(pf_id) \ | |
202 | (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) | |
60ccd45c ASJ |
203 | #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ |
204 | (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) | |
433c47de | 205 | |
17a73f6b JG |
206 | struct i40e_fdir_filter { |
207 | struct hlist_node fdir_node; | |
208 | /* filter ipnut set */ | |
209 | u8 flow_type; | |
210 | u8 ip4_proto; | |
04b73bd7 | 211 | /* TX packet view of src and dst */ |
17a73f6b JG |
212 | __be32 dst_ip[4]; |
213 | __be32 src_ip[4]; | |
214 | __be16 src_port; | |
215 | __be16 dst_port; | |
216 | __be32 sctp_v_tag; | |
217 | /* filter control */ | |
7daa6bf3 JB |
218 | u16 q_index; |
219 | u8 flex_off; | |
220 | u8 pctype; | |
221 | u16 dest_vsi; | |
222 | u8 dest_ctl; | |
223 | u8 fd_status; | |
224 | u16 cnt_index; | |
225 | u32 fd_id; | |
7daa6bf3 JB |
226 | }; |
227 | ||
4e3b35b0 NP |
228 | #define I40E_ETH_P_LLDP 0x88cc |
229 | ||
7daa6bf3 JB |
230 | #define I40E_DCB_PRIO_TYPE_STRICT 0 |
231 | #define I40E_DCB_PRIO_TYPE_ETS 1 | |
232 | #define I40E_DCB_STRICT_PRIO_CREDITS 127 | |
233 | #define I40E_MAX_USER_PRIORITY 8 | |
234 | /* DCB per TC information data structure */ | |
235 | struct i40e_tc_info { | |
236 | u16 qoffset; /* Queue offset from base queue */ | |
237 | u16 qcount; /* Total Queues */ | |
238 | u8 netdev_tc; /* Netdev TC index if netdev associated */ | |
239 | }; | |
240 | ||
241 | /* TC configuration data structure */ | |
242 | struct i40e_tc_configuration { | |
243 | u8 numtc; /* Total number of enabled TCs */ | |
244 | u8 enabled_tc; /* TC map */ | |
245 | struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; | |
246 | }; | |
247 | ||
6a899024 SA |
248 | struct i40e_udp_port_config { |
249 | __be16 index; | |
250 | u8 type; | |
251 | }; | |
252 | ||
7daa6bf3 JB |
253 | /* struct that defines the Ethernet device */ |
254 | struct i40e_pf { | |
255 | struct pci_dev *pdev; | |
256 | struct i40e_hw hw; | |
257 | unsigned long state; | |
7daa6bf3 | 258 | struct msix_entry *msix_entries; |
7daa6bf3 JB |
259 | bool fc_autoneg_status; |
260 | ||
261 | u16 eeprom_version; | |
b40c82e6 | 262 | u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ |
7daa6bf3 JB |
263 | u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ |
264 | u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ | |
b40c82e6 JK |
265 | u16 num_req_vfs; /* num VFs requested for this VF */ |
266 | u16 num_vf_qps; /* num queue pairs per VF */ | |
38e00438 | 267 | #ifdef I40E_FCOE |
b40c82e6 | 268 | u16 num_fcoe_qps; /* num fcoe queues this PF has set up */ |
38e00438 VD |
269 | u16 num_fcoe_msix; /* num queue vectors per fcoe pool */ |
270 | #endif /* I40E_FCOE */ | |
b40c82e6 JK |
271 | u16 num_lan_qps; /* num lan queues this PF has set up */ |
272 | u16 num_lan_msix; /* num queue vectors for the base PF vsi */ | |
f8ff1464 | 273 | int queues_left; /* queues left unclaimed */ |
acd65448 | 274 | u16 alloc_rss_size; /* allocated RSS queues */ |
7daa6bf3 JB |
275 | u16 rss_size_max; /* HW defined max RSS queues */ |
276 | u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ | |
505682cd | 277 | u16 num_alloc_vsi; /* num VSIs this driver supports */ |
7daa6bf3 | 278 | u8 atr_sample_rate; |
8e2773ae | 279 | bool wol_en; |
7daa6bf3 | 280 | |
17a73f6b JG |
281 | struct hlist_head fdir_filter_list; |
282 | u16 fdir_pf_active_filters; | |
1e1be8f6 | 283 | unsigned long fd_flush_timestamp; |
60793f4a | 284 | u32 fd_flush_cnt; |
1e1be8f6 ASJ |
285 | u32 fd_add_err; |
286 | u32 fd_atr_cnt; | |
287 | u32 fd_tcp_rule; | |
17a73f6b | 288 | |
6a899024 SA |
289 | struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; |
290 | u16 pending_udp_bitmap; | |
a1c9a9d9 | 291 | |
7daa6bf3 JB |
292 | enum i40e_interrupt_policy int_policy; |
293 | u16 rx_itr_default; | |
294 | u16 tx_itr_default; | |
71e6163a | 295 | u32 msg_enable; |
b294ac70 | 296 | char int_name[I40E_INT_NAME_STR_LEN]; |
7daa6bf3 | 297 | u16 adminq_work_limit; /* num of admin receive queue desc to process */ |
21536717 SN |
298 | unsigned long service_timer_period; |
299 | unsigned long service_timer_previous; | |
7daa6bf3 JB |
300 | struct timer_list service_timer; |
301 | struct work_struct service_task; | |
302 | ||
303 | u64 flags; | |
41a1d04b JB |
304 | #define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1) |
305 | #define I40E_FLAG_MSI_ENABLED BIT_ULL(2) | |
306 | #define I40E_FLAG_MSIX_ENABLED BIT_ULL(3) | |
307 | #define I40E_FLAG_RX_1BUF_ENABLED BIT_ULL(4) | |
308 | #define I40E_FLAG_RX_PS_ENABLED BIT_ULL(5) | |
309 | #define I40E_FLAG_RSS_ENABLED BIT_ULL(6) | |
310 | #define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7) | |
311 | #define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8) | |
312 | #define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9) | |
d502ce01 | 313 | #define I40E_FLAG_IWARP_ENABLED BIT_ULL(10) |
38e00438 | 314 | #ifdef I40E_FCOE |
41a1d04b | 315 | #define I40E_FLAG_FCOE_ENABLED BIT_ULL(11) |
38e00438 | 316 | #endif /* I40E_FCOE */ |
41a1d04b JB |
317 | #define I40E_FLAG_16BYTE_RX_DESC_ENABLED BIT_ULL(13) |
318 | #define I40E_FLAG_CLEAN_ADMINQ BIT_ULL(14) | |
319 | #define I40E_FLAG_FILTER_SYNC BIT_ULL(15) | |
320 | #define I40E_FLAG_PROCESS_MDD_EVENT BIT_ULL(17) | |
321 | #define I40E_FLAG_PROCESS_VFLR_EVENT BIT_ULL(18) | |
322 | #define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19) | |
323 | #define I40E_FLAG_DCB_ENABLED BIT_ULL(20) | |
324 | #define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21) | |
325 | #define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22) | |
326 | #define I40E_FLAG_PTP BIT_ULL(25) | |
327 | #define I40E_FLAG_MFP_ENABLED BIT_ULL(26) | |
6a899024 | 328 | #define I40E_FLAG_UDP_FILTER_SYNC BIT_ULL(27) |
41a1d04b JB |
329 | #define I40E_FLAG_PORT_ID_VALID BIT_ULL(28) |
330 | #define I40E_FLAG_DCB_CAPABLE BIT_ULL(29) | |
d502ce01 ASJ |
331 | #define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31) |
332 | #define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32) | |
333 | #define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33) | |
334 | #define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34) | |
335 | #define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35) | |
d1a8d275 | 336 | #define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37) |
d502ce01 | 337 | #define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38) |
9ac77266 | 338 | #define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39) |
fc60861e | 339 | #define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40) |
6a899024 | 340 | #define I40E_FLAG_GENEVE_OFFLOAD_CAPABLE BIT_ULL(41) |
3fced535 | 341 | #define I40E_FLAG_NO_PCI_LINK_CHECK BIT_ULL(42) |
48b1804e | 342 | #define I40E_FLAG_100M_SGMII_CAPABLE BIT_ULL(43) |
b499ffb0 | 343 | #define I40E_FLAG_PF_MAC BIT_ULL(50) |
7daa6bf3 | 344 | |
61dade7e ASJ |
345 | /* tracks features that get auto disabled by errors */ |
346 | u64 auto_disable_flags; | |
347 | ||
38e00438 VD |
348 | #ifdef I40E_FCOE |
349 | struct i40e_fcoe fcoe; | |
350 | ||
351 | #endif /* I40E_FCOE */ | |
7daa6bf3 JB |
352 | bool stat_offsets_loaded; |
353 | struct i40e_hw_port_stats stats; | |
354 | struct i40e_hw_port_stats stats_offsets; | |
355 | u32 tx_timeout_count; | |
356 | u32 tx_timeout_recovery_level; | |
357 | unsigned long tx_timeout_last_recovery; | |
810b3ae4 | 358 | u32 tx_sluggish_count; |
7daa6bf3 JB |
359 | u32 hw_csum_rx_error; |
360 | u32 led_status; | |
361 | u16 corer_count; /* Core reset count */ | |
362 | u16 globr_count; /* Global reset count */ | |
363 | u16 empr_count; /* EMP reset count */ | |
364 | u16 pfr_count; /* PF reset count */ | |
cd92e72f | 365 | u16 sw_int_count; /* SW interrupt count */ |
7daa6bf3 JB |
366 | |
367 | struct mutex switch_mutex; | |
368 | u16 lan_vsi; /* our default LAN VSI */ | |
369 | u16 lan_veb; /* initial relay, if exists */ | |
370 | #define I40E_NO_VEB 0xffff | |
371 | #define I40E_NO_VSI 0xffff | |
372 | u16 next_vsi; /* Next unallocated VSI - 0-based! */ | |
373 | struct i40e_vsi **vsi; | |
374 | struct i40e_veb *veb[I40E_MAX_VEB]; | |
375 | ||
376 | struct i40e_lump_tracking *qp_pile; | |
377 | struct i40e_lump_tracking *irq_pile; | |
378 | ||
379 | /* switch config info */ | |
380 | u16 pf_seid; | |
381 | u16 main_vsi_seid; | |
382 | u16 mac_seid; | |
7daa6bf3 JB |
383 | struct kobject *switch_kobj; |
384 | #ifdef CONFIG_DEBUG_FS | |
385 | struct dentry *i40e_dbg_pf; | |
386 | #endif /* CONFIG_DEBUG_FS */ | |
92faef85 | 387 | bool cur_promisc; |
7daa6bf3 | 388 | |
93cd765b ASJ |
389 | u16 instance; /* A unique number per i40e_pf instance in the system */ |
390 | ||
7daa6bf3 JB |
391 | /* sr-iov config info */ |
392 | struct i40e_vf *vf; | |
393 | int num_alloc_vfs; /* actual number of VFs allocated */ | |
394 | u32 vf_aq_requests; | |
395 | ||
396 | /* DCBx/DCBNL capability for PF that indicates | |
397 | * whether DCBx is managed by firmware or host | |
398 | * based agent (LLDPAD). Also, indicates what | |
399 | * flavor of DCBx protocol (IEEE/CEE) is supported | |
400 | * by the device. For now we're supporting IEEE | |
401 | * mode only. | |
402 | */ | |
403 | u16 dcbx_cap; | |
404 | ||
405 | u32 fcoe_hmc_filt_num; | |
406 | u32 fcoe_hmc_cntx_num; | |
407 | struct i40e_filter_control_settings filter_settings; | |
beb0dff1 JK |
408 | |
409 | struct ptp_clock *ptp_clock; | |
410 | struct ptp_clock_info ptp_caps; | |
411 | struct sk_buff *ptp_tx_skb; | |
beb0dff1 | 412 | struct hwtstamp_config tstamp_config; |
beb0dff1 JK |
413 | unsigned long last_rx_ptp_check; |
414 | spinlock_t tmreg_lock; /* Used to protect the device time registers. */ | |
415 | u64 ptp_base_adj; | |
416 | u32 tx_hwtstamp_timeouts; | |
417 | u32 rx_hwtstamp_cleared; | |
418 | bool ptp_tx; | |
419 | bool ptp_rx; | |
acd65448 | 420 | u16 rss_table_size; /* HW RSS table size */ |
f4492db1 GR |
421 | /* These are only valid in NPAR modes */ |
422 | u32 npar_max_bw; | |
423 | u32 npar_min_bw; | |
2ac8b675 SN |
424 | |
425 | u32 ioremap_len; | |
3487b6c3 | 426 | u32 fd_inv; |
7daa6bf3 JB |
427 | }; |
428 | ||
429 | struct i40e_mac_filter { | |
430 | struct list_head list; | |
431 | u8 macaddr[ETH_ALEN]; | |
432 | #define I40E_VLAN_ANY -1 | |
433 | s16 vlan; | |
434 | u8 counter; /* number of instances of this filter */ | |
435 | bool is_vf; /* filter belongs to a VF */ | |
436 | bool is_netdev; /* filter belongs to a netdev */ | |
437 | bool changed; /* filter needs to be sync'd to the HW */ | |
6252c7e4 | 438 | bool is_laa; /* filter is a Locally Administered Address */ |
7daa6bf3 JB |
439 | }; |
440 | ||
441 | struct i40e_veb { | |
442 | struct i40e_pf *pf; | |
443 | u16 idx; | |
444 | u16 veb_idx; /* index of VEB parent */ | |
445 | u16 seid; | |
446 | u16 uplink_seid; | |
447 | u16 stats_idx; /* index of VEB parent */ | |
448 | u8 enabled_tc; | |
51616018 | 449 | u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ |
7daa6bf3 JB |
450 | u16 flags; |
451 | u16 bw_limit; | |
452 | u8 bw_max_quanta; | |
453 | bool is_abs_credits; | |
454 | u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; | |
455 | u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; | |
456 | u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; | |
457 | struct kobject *kobj; | |
458 | bool stat_offsets_loaded; | |
459 | struct i40e_eth_stats stats; | |
460 | struct i40e_eth_stats stats_offsets; | |
fe860afb NP |
461 | struct i40e_veb_tc_stats tc_stats; |
462 | struct i40e_veb_tc_stats tc_stats_offsets; | |
7daa6bf3 JB |
463 | }; |
464 | ||
465 | /* struct that defines a VSI, associated with a dev */ | |
466 | struct i40e_vsi { | |
467 | struct net_device *netdev; | |
468 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
469 | bool netdev_registered; | |
470 | bool stat_offsets_loaded; | |
471 | ||
472 | u32 current_netdev_flags; | |
473 | unsigned long state; | |
41a1d04b JB |
474 | #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) |
475 | #define I40E_VSI_FLAG_VEB_OWNER BIT(1) | |
7daa6bf3 JB |
476 | unsigned long flags; |
477 | ||
21659035 KP |
478 | /* Per VSI lock to protect elements/list (MAC filter) */ |
479 | spinlock_t mac_filter_list_lock; | |
7daa6bf3 JB |
480 | struct list_head mac_filter_list; |
481 | ||
482 | /* VSI stats */ | |
483 | struct rtnl_link_stats64 net_stats; | |
484 | struct rtnl_link_stats64 net_stats_offsets; | |
485 | struct i40e_eth_stats eth_stats; | |
486 | struct i40e_eth_stats eth_stats_offsets; | |
38e00438 VD |
487 | #ifdef I40E_FCOE |
488 | struct i40e_fcoe_stats fcoe_stats; | |
489 | struct i40e_fcoe_stats fcoe_stats_offsets; | |
490 | bool fcoe_stat_offsets_loaded; | |
491 | #endif | |
7daa6bf3 JB |
492 | u32 tx_restart; |
493 | u32 tx_busy; | |
2fc3d715 | 494 | u64 tx_linearize; |
164c9f54 | 495 | u64 tx_force_wb; |
7daa6bf3 JB |
496 | u32 rx_buf_failed; |
497 | u32 rx_page_failed; | |
498 | ||
9f65e15b AD |
499 | /* These are containers of ring pointers, allocated at run-time */ |
500 | struct i40e_ring **rx_rings; | |
501 | struct i40e_ring **tx_rings; | |
7daa6bf3 JB |
502 | |
503 | u16 work_limit; | |
504 | /* high bit set means dynamic, use accessor routines to read/write. | |
505 | * hardware only supports 2us resolution for the ITR registers. | |
506 | * these values always store the USER setting, and must be converted | |
507 | * before programming to a register. | |
508 | */ | |
509 | u16 rx_itr_setting; | |
510 | u16 tx_itr_setting; | |
ac26fc13 | 511 | u16 int_rate_limit; /* value in usecs */ |
7daa6bf3 | 512 | |
acd65448 HZ |
513 | u16 rss_table_size; /* HW RSS table size */ |
514 | u16 rss_size; /* Allocated RSS queues */ | |
28c5869f HZ |
515 | u8 *rss_hkey_user; /* User configured hash keys */ |
516 | u8 *rss_lut_user; /* User configured lookup table entries */ | |
5db4cb59 | 517 | |
7daa6bf3 JB |
518 | u16 max_frame; |
519 | u16 rx_hdr_len; | |
520 | u16 rx_buf_len; | |
521 | u8 dtype; | |
522 | ||
523 | /* List of q_vectors allocated to this VSI */ | |
493fb300 | 524 | struct i40e_q_vector **q_vectors; |
7daa6bf3 JB |
525 | int num_q_vectors; |
526 | int base_vector; | |
63741846 | 527 | bool irqs_ready; |
7daa6bf3 JB |
528 | |
529 | u16 seid; /* HW index of this VSI (absolute index) */ | |
530 | u16 id; /* VSI number */ | |
531 | u16 uplink_seid; | |
532 | ||
533 | u16 base_queue; /* vsi's first queue in hw array */ | |
534 | u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ | |
9a3bd2f1 | 535 | u16 req_queue_pairs; /* User requested queue pairs */ |
7daa6bf3 JB |
536 | u16 num_queue_pairs; /* Used tx and rx pairs */ |
537 | u16 num_desc; | |
538 | enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ | |
539 | u16 vf_id; /* Virtual function ID for SRIOV VSIs */ | |
540 | ||
541 | struct i40e_tc_configuration tc_config; | |
542 | struct i40e_aqc_vsi_properties_data info; | |
543 | ||
544 | /* VSI BW limit (absolute across all TCs) */ | |
545 | u16 bw_limit; /* VSI BW Limit (0 = disabled) */ | |
546 | u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ | |
547 | ||
548 | /* Relative TC credits across VSIs */ | |
549 | u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; | |
550 | /* TC BW limit credits within VSI */ | |
551 | u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; | |
552 | /* TC BW limit max quanta within VSI */ | |
553 | u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; | |
554 | ||
555 | struct i40e_pf *back; /* Backreference to associated PF */ | |
556 | u16 idx; /* index in pf->vsi[] */ | |
557 | u16 veb_idx; /* index of VEB parent */ | |
558 | struct kobject *kobj; /* sysfs object */ | |
c156f856 | 559 | bool current_isup; /* Sync 'link up' logging */ |
7daa6bf3 JB |
560 | |
561 | /* VSI specific handlers */ | |
562 | irqreturn_t (*irq_handler)(int irq, void *data); | |
88eee9bc CW |
563 | |
564 | /* current rxnfc data */ | |
565 | struct ethtool_rxnfc rxnfc; /* current rss hash opts */ | |
7daa6bf3 JB |
566 | } ____cacheline_internodealigned_in_smp; |
567 | ||
568 | struct i40e_netdev_priv { | |
569 | struct i40e_vsi *vsi; | |
570 | }; | |
571 | ||
572 | /* struct that defines an interrupt vector */ | |
573 | struct i40e_q_vector { | |
574 | struct i40e_vsi *vsi; | |
575 | ||
576 | u16 v_idx; /* index in the vsi->q_vector array. */ | |
577 | u16 reg_idx; /* register index of the interrupt */ | |
578 | ||
579 | struct napi_struct napi; | |
580 | ||
581 | struct i40e_ring_container rx; | |
582 | struct i40e_ring_container tx; | |
583 | ||
584 | u8 num_ringpairs; /* total number of ring pairs in vector */ | |
585 | ||
9c6c1259 KP |
586 | #define I40E_Q_VECTOR_HUNG_DETECT 0 /* Bit Index for hung detection logic */ |
587 | unsigned long hung_detected; /* Set/Reset for hung_detection logic */ | |
588 | ||
7daa6bf3 | 589 | cpumask_t affinity_mask; |
493fb300 | 590 | struct rcu_head rcu; /* to avoid race with update stats on free */ |
b294ac70 | 591 | char name[I40E_INT_NAME_STR_LEN]; |
8e0764b4 | 592 | bool arm_wb_state; |
ee2319cf JB |
593 | #define ITR_COUNTDOWN_START 100 |
594 | u8 itr_countdown; /* when 0 should adjust ITR */ | |
7daa6bf3 JB |
595 | } ____cacheline_internodealigned_in_smp; |
596 | ||
597 | /* lan device */ | |
598 | struct i40e_device { | |
599 | struct list_head list; | |
600 | struct i40e_pf *pf; | |
601 | }; | |
602 | ||
603 | /** | |
6dec1017 | 604 | * i40e_nvm_version_str - format the NVM version strings |
7daa6bf3 JB |
605 | * @hw: ptr to the hardware info |
606 | **/ | |
6dec1017 | 607 | static inline char *i40e_nvm_version_str(struct i40e_hw *hw) |
7daa6bf3 JB |
608 | { |
609 | static char buf[32]; | |
2efaad86 CW |
610 | u32 full_ver; |
611 | u8 ver, patch; | |
612 | u16 build; | |
613 | ||
614 | full_ver = hw->nvm.oem_ver; | |
615 | ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); | |
4eeb1fff JB |
616 | build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & |
617 | I40E_OEM_VER_BUILD_MASK); | |
2efaad86 | 618 | patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); |
7daa6bf3 JB |
619 | |
620 | snprintf(buf, sizeof(buf), | |
f0b44440 | 621 | "%x.%02x 0x%x %d.%d.%d", |
ff80301e JB |
622 | (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> |
623 | I40E_NVM_VERSION_HI_SHIFT, | |
624 | (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> | |
625 | I40E_NVM_VERSION_LO_SHIFT, | |
2efaad86 | 626 | hw->nvm.eetrack, ver, build, patch); |
7daa6bf3 JB |
627 | |
628 | return buf; | |
629 | } | |
630 | ||
631 | /** | |
632 | * i40e_netdev_to_pf: Retrieve the PF struct for given netdev | |
633 | * @netdev: the corresponding netdev | |
634 | * | |
635 | * Return the PF struct for the given netdev | |
636 | **/ | |
637 | static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) | |
638 | { | |
639 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
640 | struct i40e_vsi *vsi = np->vsi; | |
641 | ||
642 | return vsi->back; | |
643 | } | |
644 | ||
645 | static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, | |
646 | irqreturn_t (*irq_handler)(int, void *)) | |
647 | { | |
648 | vsi->irq_handler = irq_handler; | |
649 | } | |
650 | ||
651 | /** | |
652 | * i40e_rx_is_programming_status - check for programming status descriptor | |
653 | * @qw: the first quad word of the program status descriptor | |
654 | * | |
655 | * The value of in the descriptor length field indicate if this | |
656 | * is a programming status descriptor for flow director or FCoE | |
657 | * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise | |
658 | * it is a packet descriptor. | |
659 | **/ | |
660 | static inline bool i40e_rx_is_programming_status(u64 qw) | |
661 | { | |
662 | return I40E_RX_PROG_STATUS_DESC_LENGTH == | |
663 | (qw >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT); | |
664 | } | |
665 | ||
082def10 ASJ |
666 | /** |
667 | * i40e_get_fd_cnt_all - get the total FD filter space available | |
b40c82e6 | 668 | * @pf: pointer to the PF struct |
082def10 ASJ |
669 | **/ |
670 | static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) | |
671 | { | |
672 | return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; | |
673 | } | |
674 | ||
7daa6bf3 JB |
675 | /* needed by i40e_ethtool.c */ |
676 | int i40e_up(struct i40e_vsi *vsi); | |
677 | void i40e_down(struct i40e_vsi *vsi); | |
678 | extern const char i40e_driver_name[]; | |
679 | extern const char i40e_driver_version_str[]; | |
23326186 | 680 | void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); |
7daa6bf3 | 681 | void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags); |
043dd650 HZ |
682 | int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); |
683 | int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); | |
fdf0e0bf | 684 | struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); |
7daa6bf3 JB |
685 | void i40e_update_stats(struct i40e_vsi *vsi); |
686 | void i40e_update_eth_stats(struct i40e_vsi *vsi); | |
687 | struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); | |
688 | int i40e_fetch_switch_configuration(struct i40e_pf *pf, | |
689 | bool printconfig); | |
690 | ||
17a73f6b | 691 | int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet, |
7daa6bf3 | 692 | struct i40e_pf *pf, bool add); |
17a73f6b JG |
693 | int i40e_add_del_fdir(struct i40e_vsi *vsi, |
694 | struct i40e_fdir_filter *input, bool add); | |
55a5e60b | 695 | void i40e_fdir_check_and_reenable(struct i40e_pf *pf); |
04294e38 ASJ |
696 | u32 i40e_get_current_fd_count(struct i40e_pf *pf); |
697 | u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); | |
698 | u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); | |
699 | u32 i40e_get_global_fd_count(struct i40e_pf *pf); | |
7c3c288b | 700 | bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); |
7daa6bf3 JB |
701 | void i40e_set_ethtool_ops(struct net_device *netdev); |
702 | struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, | |
703 | u8 *macaddr, s16 vlan, | |
704 | bool is_vf, bool is_netdev); | |
705 | void i40e_del_filter(struct i40e_vsi *vsi, u8 *macaddr, s16 vlan, | |
706 | bool is_vf, bool is_netdev); | |
17652c63 | 707 | int i40e_sync_vsi_filters(struct i40e_vsi *vsi); |
7daa6bf3 JB |
708 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, |
709 | u16 uplink, u32 param1); | |
710 | int i40e_vsi_release(struct i40e_vsi *vsi); | |
711 | struct i40e_vsi *i40e_vsi_lookup(struct i40e_pf *pf, enum i40e_vsi_type type, | |
712 | struct i40e_vsi *start_vsi); | |
38e00438 VD |
713 | #ifdef I40E_FCOE |
714 | void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, | |
715 | struct i40e_vsi_context *ctxt, | |
716 | u8 enabled_tc, bool is_add); | |
717 | #endif | |
fc18eaa0 | 718 | int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool enable); |
f8ff1464 | 719 | int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); |
7daa6bf3 JB |
720 | struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, |
721 | u16 downlink_seid, u8 enabled_tc); | |
722 | void i40e_veb_release(struct i40e_veb *veb); | |
723 | ||
4e3b35b0 | 724 | int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); |
4eeb1fff | 725 | int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); |
7daa6bf3 JB |
726 | void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); |
727 | void i40e_vsi_reset_stats(struct i40e_vsi *vsi); | |
728 | void i40e_pf_reset_stats(struct i40e_pf *pf); | |
729 | #ifdef CONFIG_DEBUG_FS | |
730 | void i40e_dbg_pf_init(struct i40e_pf *pf); | |
731 | void i40e_dbg_pf_exit(struct i40e_pf *pf); | |
732 | void i40e_dbg_init(void); | |
733 | void i40e_dbg_exit(void); | |
734 | #else | |
735 | static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} | |
736 | static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} | |
737 | static inline void i40e_dbg_init(void) {} | |
738 | static inline void i40e_dbg_exit(void) {} | |
739 | #endif /* CONFIG_DEBUG_FS*/ | |
02d109be JB |
740 | /** |
741 | * i40e_irq_dynamic_enable - Enable default interrupt generation settings | |
742 | * @vsi: pointer to a vsi | |
743 | * @vector: enable a particular Hw Interrupt vector, without base_vector | |
744 | **/ | |
745 | static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) | |
746 | { | |
747 | struct i40e_pf *pf = vsi->back; | |
748 | struct i40e_hw *hw = &pf->hw; | |
749 | u32 val; | |
750 | ||
751 | val = I40E_PFINT_DYN_CTLN_INTENA_MASK | | |
752 | I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | | |
753 | (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); | |
754 | wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); | |
755 | /* skip the flush */ | |
756 | } | |
757 | ||
5c2cebda | 758 | void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector); |
2ef28cfb | 759 | void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); |
116a57d4 | 760 | void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); |
38e00438 VD |
761 | #ifdef I40E_FCOE |
762 | struct rtnl_link_stats64 *i40e_get_netdev_stats_struct( | |
763 | struct net_device *netdev, | |
764 | struct rtnl_link_stats64 *storage); | |
765 | int i40e_set_mac(struct net_device *netdev, void *p); | |
766 | void i40e_set_rx_mode(struct net_device *netdev); | |
767 | #endif | |
7daa6bf3 | 768 | int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); |
38e00438 VD |
769 | #ifdef I40E_FCOE |
770 | void i40e_tx_timeout(struct net_device *netdev); | |
771 | int i40e_vlan_rx_add_vid(struct net_device *netdev, | |
772 | __always_unused __be16 proto, u16 vid); | |
773 | int i40e_vlan_rx_kill_vid(struct net_device *netdev, | |
774 | __always_unused __be16 proto, u16 vid); | |
775 | #endif | |
96664483 | 776 | int i40e_open(struct net_device *netdev); |
6c167f58 | 777 | int i40e_vsi_open(struct i40e_vsi *vsi); |
7daa6bf3 JB |
778 | void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); |
779 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid); | |
780 | int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid); | |
781 | struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr, | |
782 | bool is_vf, bool is_netdev); | |
b36e9ab5 MW |
783 | int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr, |
784 | bool is_vf, bool is_netdev); | |
7daa6bf3 JB |
785 | bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); |
786 | struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr, | |
787 | bool is_vf, bool is_netdev); | |
38e00438 | 788 | #ifdef I40E_FCOE |
38e00438 VD |
789 | int i40e_close(struct net_device *netdev); |
790 | int i40e_setup_tc(struct net_device *netdev, u8 tc); | |
791 | void i40e_netpoll(struct net_device *netdev); | |
792 | int i40e_fcoe_enable(struct net_device *netdev); | |
793 | int i40e_fcoe_disable(struct net_device *netdev); | |
794 | int i40e_fcoe_vsi_init(struct i40e_vsi *vsi, struct i40e_vsi_context *ctxt); | |
795 | u8 i40e_get_fcoe_tc_map(struct i40e_pf *pf); | |
796 | void i40e_fcoe_config_netdev(struct net_device *netdev, struct i40e_vsi *vsi); | |
797 | void i40e_fcoe_vsi_setup(struct i40e_pf *pf); | |
21364bcf | 798 | void i40e_init_pf_fcoe(struct i40e_pf *pf); |
38e00438 VD |
799 | int i40e_fcoe_setup_ddp_resources(struct i40e_vsi *vsi); |
800 | void i40e_fcoe_free_ddp_resources(struct i40e_vsi *vsi); | |
801 | int i40e_fcoe_handle_offload(struct i40e_ring *rx_ring, | |
802 | union i40e_rx_desc *rx_desc, | |
803 | struct sk_buff *skb); | |
804 | void i40e_fcoe_handle_status(struct i40e_ring *rx_ring, | |
805 | union i40e_rx_desc *rx_desc, u8 prog_id); | |
806 | #endif /* I40E_FCOE */ | |
7daa6bf3 | 807 | void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); |
4e3b35b0 NP |
808 | #ifdef CONFIG_I40E_DCB |
809 | void i40e_dcbnl_flush_apps(struct i40e_pf *pf, | |
750fcbcf | 810 | struct i40e_dcbx_config *old_cfg, |
4e3b35b0 NP |
811 | struct i40e_dcbx_config *new_cfg); |
812 | void i40e_dcbnl_set_all(struct i40e_vsi *vsi); | |
813 | void i40e_dcbnl_setup(struct i40e_vsi *vsi); | |
814 | bool i40e_dcb_need_reconfig(struct i40e_pf *pf, | |
815 | struct i40e_dcbx_config *old_cfg, | |
816 | struct i40e_dcbx_config *new_cfg); | |
817 | #endif /* CONFIG_I40E_DCB */ | |
beb0dff1 JK |
818 | void i40e_ptp_rx_hang(struct i40e_vsi *vsi); |
819 | void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); | |
820 | void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); | |
821 | void i40e_ptp_set_increment(struct i40e_pf *pf); | |
822 | int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); | |
823 | int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); | |
824 | void i40e_ptp_init(struct i40e_pf *pf); | |
825 | void i40e_ptp_stop(struct i40e_pf *pf); | |
51616018 | 826 | int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); |
f4492db1 GR |
827 | i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf); |
828 | i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf); | |
829 | i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf); | |
c156f856 | 830 | void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); |
7daa6bf3 | 831 | #endif /* _I40E_H_ */ |