i40e/i40evf: Fix RSS rx-flow-hash configuration through ethtool
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e.h
CommitLineData
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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
88eee9bc 4 * Copyright(c) 2013 - 2015 Intel Corporation.
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5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
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15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
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17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_H_
28#define _I40E_H_
29
30#include <net/tcp.h>
8144f0f7 31#include <net/udp.h>
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32#include <linux/types.h>
33#include <linux/errno.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/aer.h>
37#include <linux/netdevice.h>
38#include <linux/ioport.h>
2bc7ee8a 39#include <linux/iommu.h>
7daa6bf3
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40#include <linux/slab.h>
41#include <linux/list.h>
42#include <linux/string.h>
43#include <linux/in.h>
44#include <linux/ip.h>
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45#include <linux/sctp.h>
46#include <linux/pkt_sched.h>
47#include <linux/ipv6.h>
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48#include <net/checksum.h>
49#include <net/ip6_checksum.h>
50#include <linux/ethtool.h>
51#include <linux/if_vlan.h>
51616018 52#include <linux/if_bridge.h>
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53#include <linux/clocksource.h>
54#include <linux/net_tstamp.h>
55#include <linux/ptp_clock_kernel.h>
7daa6bf3
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56#include "i40e_type.h"
57#include "i40e_prototype.h"
38e00438
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58#ifdef I40E_FCOE
59#include "i40e_fcoe.h"
60#endif
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61#include "i40e_virtchnl.h"
62#include "i40e_virtchnl_pf.h"
63#include "i40e_txrx.h"
4e3b35b0 64#include "i40e_dcb.h"
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65
66/* Useful i40e defaults */
67#define I40E_BASE_PF_SEID 16
68#define I40E_BASE_VSI_SEID 512
69#define I40E_BASE_VEB_SEID 288
70#define I40E_MAX_VEB 16
71
72#define I40E_MAX_NUM_DESCRIPTORS 4096
232f4706 73#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
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74#define I40E_DEFAULT_NUM_DESCRIPTORS 512
75#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
76#define I40E_MIN_NUM_DESCRIPTORS 64
77#define I40E_MIN_MSIX 2
78#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
505682cd 79#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */
e25d00b8
ASJ
80/* max 16 qps */
81#define i40e_default_queues_per_vmdq(pf) \
82 (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
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83#define I40E_DEFAULT_QUEUES_PER_VF 4
84#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
e25d00b8
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85#define i40e_pf_get_max_q_per_tc(pf) \
86 (((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
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87#define I40E_FDIR_RING 0
88#define I40E_FDIR_RING_COUNT 32
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89#ifdef I40E_FCOE
90#define I40E_DEFAULT_FCOE 8 /* default number of QPs for FCoE */
91#define I40E_MINIMUM_FCOE 1 /* minimum number of QPs for FCoE */
92#endif /* I40E_FCOE */
7daa6bf3 93#define I40E_MAX_AQ_BUF_SIZE 4096
07574897 94#define I40E_AQ_LEN 256
628f096d 95#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
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96#define I40E_MAX_USER_PRIORITY 8
97#define I40E_DEFAULT_MSG_ENABLE 4
23527308 98#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
fba52e21 99#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
7daa6bf3 100
7e45ab44 101/* Ethtool Private Flags */
41a1d04b 102#define I40E_PRIV_FLAGS_NPAR_FLAG BIT(0)
9ac77266 103#define I40E_PRIV_FLAGS_LINKPOLL_FLAG BIT(1)
ef17178c 104#define I40E_PRIV_FLAGS_FD_ATR BIT(2)
1cdfd88f 105#define I40E_PRIV_FLAGS_VEB_STATS BIT(3)
827de392 106#define I40E_PRIV_FLAGS_PS BIT(4)
7e45ab44 107
7daa6bf3 108#define I40E_NVM_VERSION_LO_SHIFT 0
fe310704 109#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
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110#define I40E_NVM_VERSION_HI_SHIFT 12
111#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
2efaad86 112#define I40E_OEM_VER_BUILD_MASK 0xffff
f0b44440 113#define I40E_OEM_VER_PATCH_MASK 0xff
2efaad86
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114#define I40E_OEM_VER_BUILD_SHIFT 8
115#define I40E_OEM_VER_SHIFT 24
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116
117/* The values in here are decimal coded as hex as is the case in the NVM map*/
118#define I40E_CURRENT_NVM_VERSION_HI 0x2
ff80301e 119#define I40E_CURRENT_NVM_VERSION_LO 0x40
fe310704 120
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121/* magic for getting defines into strings */
122#define STRINGIFY(foo) #foo
123#define XSTRINGIFY(bar) STRINGIFY(bar)
124
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125#define I40E_RX_DESC(R, i) \
126 ((ring_is_16byte_desc_enabled(R)) \
127 ? (union i40e_32byte_rx_desc *) \
128 (&(((union i40e_16byte_rx_desc *)((R)->desc))[i])) \
129 : (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])))
130#define I40E_TX_DESC(R, i) \
131 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
132#define I40E_TX_CTXTDESC(R, i) \
133 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
134#define I40E_TX_FDIRDESC(R, i) \
135 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
136
137/* default to trying for four seconds */
138#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
139
140/* driver state flags */
141enum i40e_state_t {
142 __I40E_TESTING,
143 __I40E_CONFIG_BUSY,
144 __I40E_CONFIG_DONE,
145 __I40E_DOWN,
146 __I40E_NEEDS_RESTART,
147 __I40E_SERVICE_SCHED,
148 __I40E_ADMINQ_EVENT_PENDING,
149 __I40E_MDD_EVENT_PENDING,
150 __I40E_VFLR_EVENT_PENDING,
151 __I40E_RESET_RECOVERY_PENDING,
152 __I40E_RESET_INTR_RECEIVED,
153 __I40E_REINIT_REQUESTED,
154 __I40E_PF_RESET_REQUESTED,
155 __I40E_CORE_RESET_REQUESTED,
156 __I40E_GLOBAL_RESET_REQUESTED,
7823fe34 157 __I40E_EMP_RESET_REQUESTED,
9df42d1a 158 __I40E_EMP_RESET_INTR_RECEIVED,
7daa6bf3 159 __I40E_FILTER_OVERFLOW_PROMISC,
9007bccd 160 __I40E_SUSPENDED,
9ce34f02 161 __I40E_PTP_TX_IN_PROGRESS,
4eb3f768 162 __I40E_BAD_EEPROM,
b5d06f05 163 __I40E_DOWN_REQUESTED,
1e1be8f6 164 __I40E_FD_FLUSH_REQUESTED,
a316f651 165 __I40E_RESET_FAILED,
69129dc3 166 __I40E_PORT_TX_SUSPENDED,
3ba9bcb4 167 __I40E_VF_DISABLE,
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168};
169
170enum i40e_interrupt_policy {
171 I40E_INTERRUPT_BEST_CASE,
172 I40E_INTERRUPT_MEDIUM,
173 I40E_INTERRUPT_LOWEST
174};
175
176struct i40e_lump_tracking {
177 u16 num_entries;
178 u16 search_hint;
179 u16 list[0];
180#define I40E_PILE_VALID_BIT 0x8000
181};
182
183#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
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184#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
185#define I40E_FDIR_BUFFER_FULL_MARGIN 10
12957388 186#define I40E_FDIR_BUFFER_HEAD_ROOM 32
04294e38 187#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
55a5e60b 188
b29e13bb 189#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
e69ff813 190#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
b29e13bb 191
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192enum i40e_fd_stat_idx {
193 I40E_FD_STAT_ATR,
194 I40E_FD_STAT_SB,
60ccd45c 195 I40E_FD_STAT_ATR_TUNNEL,
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196 I40E_FD_STAT_PF_COUNT
197};
198#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
199#define I40E_FD_ATR_STAT_IDX(pf_id) \
200 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
201#define I40E_FD_SB_STAT_IDX(pf_id) \
202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
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203#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
433c47de 205
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JG
206struct i40e_fdir_filter {
207 struct hlist_node fdir_node;
208 /* filter ipnut set */
209 u8 flow_type;
210 u8 ip4_proto;
04b73bd7 211 /* TX packet view of src and dst */
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JG
212 __be32 dst_ip[4];
213 __be32 src_ip[4];
214 __be16 src_port;
215 __be16 dst_port;
216 __be32 sctp_v_tag;
217 /* filter control */
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218 u16 q_index;
219 u8 flex_off;
220 u8 pctype;
221 u16 dest_vsi;
222 u8 dest_ctl;
223 u8 fd_status;
224 u16 cnt_index;
225 u32 fd_id;
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226};
227
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NP
228#define I40E_ETH_P_LLDP 0x88cc
229
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230#define I40E_DCB_PRIO_TYPE_STRICT 0
231#define I40E_DCB_PRIO_TYPE_ETS 1
232#define I40E_DCB_STRICT_PRIO_CREDITS 127
233#define I40E_MAX_USER_PRIORITY 8
234/* DCB per TC information data structure */
235struct i40e_tc_info {
236 u16 qoffset; /* Queue offset from base queue */
237 u16 qcount; /* Total Queues */
238 u8 netdev_tc; /* Netdev TC index if netdev associated */
239};
240
241/* TC configuration data structure */
242struct i40e_tc_configuration {
243 u8 numtc; /* Total number of enabled TCs */
244 u8 enabled_tc; /* TC map */
245 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
246};
247
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SA
248struct i40e_udp_port_config {
249 __be16 index;
250 u8 type;
251};
252
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253/* struct that defines the Ethernet device */
254struct i40e_pf {
255 struct pci_dev *pdev;
256 struct i40e_hw hw;
257 unsigned long state;
7daa6bf3 258 struct msix_entry *msix_entries;
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259 bool fc_autoneg_status;
260
261 u16 eeprom_version;
b40c82e6 262 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
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263 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
264 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
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265 u16 num_req_vfs; /* num VFs requested for this VF */
266 u16 num_vf_qps; /* num queue pairs per VF */
38e00438 267#ifdef I40E_FCOE
b40c82e6 268 u16 num_fcoe_qps; /* num fcoe queues this PF has set up */
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269 u16 num_fcoe_msix; /* num queue vectors per fcoe pool */
270#endif /* I40E_FCOE */
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271 u16 num_lan_qps; /* num lan queues this PF has set up */
272 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
f8ff1464 273 int queues_left; /* queues left unclaimed */
acd65448 274 u16 alloc_rss_size; /* allocated RSS queues */
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275 u16 rss_size_max; /* HW defined max RSS queues */
276 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
505682cd 277 u16 num_alloc_vsi; /* num VSIs this driver supports */
7daa6bf3 278 u8 atr_sample_rate;
8e2773ae 279 bool wol_en;
7daa6bf3 280
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JG
281 struct hlist_head fdir_filter_list;
282 u16 fdir_pf_active_filters;
1e1be8f6 283 unsigned long fd_flush_timestamp;
60793f4a 284 u32 fd_flush_cnt;
1e1be8f6
ASJ
285 u32 fd_add_err;
286 u32 fd_atr_cnt;
287 u32 fd_tcp_rule;
17a73f6b 288
6a899024
SA
289 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
290 u16 pending_udp_bitmap;
a1c9a9d9 291
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JB
292 enum i40e_interrupt_policy int_policy;
293 u16 rx_itr_default;
294 u16 tx_itr_default;
71e6163a 295 u32 msg_enable;
b294ac70 296 char int_name[I40E_INT_NAME_STR_LEN];
7daa6bf3 297 u16 adminq_work_limit; /* num of admin receive queue desc to process */
21536717
SN
298 unsigned long service_timer_period;
299 unsigned long service_timer_previous;
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300 struct timer_list service_timer;
301 struct work_struct service_task;
302
303 u64 flags;
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JB
304#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
305#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
306#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
307#define I40E_FLAG_RX_1BUF_ENABLED BIT_ULL(4)
308#define I40E_FLAG_RX_PS_ENABLED BIT_ULL(5)
309#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
310#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
311#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
312#define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
d502ce01 313#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
38e00438 314#ifdef I40E_FCOE
41a1d04b 315#define I40E_FLAG_FCOE_ENABLED BIT_ULL(11)
38e00438 316#endif /* I40E_FCOE */
41a1d04b
JB
317#define I40E_FLAG_16BYTE_RX_DESC_ENABLED BIT_ULL(13)
318#define I40E_FLAG_CLEAN_ADMINQ BIT_ULL(14)
319#define I40E_FLAG_FILTER_SYNC BIT_ULL(15)
320#define I40E_FLAG_PROCESS_MDD_EVENT BIT_ULL(17)
321#define I40E_FLAG_PROCESS_VFLR_EVENT BIT_ULL(18)
322#define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19)
323#define I40E_FLAG_DCB_ENABLED BIT_ULL(20)
324#define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21)
325#define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22)
326#define I40E_FLAG_PTP BIT_ULL(25)
327#define I40E_FLAG_MFP_ENABLED BIT_ULL(26)
6a899024 328#define I40E_FLAG_UDP_FILTER_SYNC BIT_ULL(27)
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JB
329#define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)
330#define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
d502ce01
ASJ
331#define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31)
332#define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32)
333#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33)
334#define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34)
335#define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35)
d1a8d275 336#define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37)
d502ce01 337#define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38)
9ac77266 338#define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39)
fc60861e 339#define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)
6a899024 340#define I40E_FLAG_GENEVE_OFFLOAD_CAPABLE BIT_ULL(41)
3fced535 341#define I40E_FLAG_NO_PCI_LINK_CHECK BIT_ULL(42)
b499ffb0 342#define I40E_FLAG_PF_MAC BIT_ULL(50)
7daa6bf3 343
61dade7e
ASJ
344 /* tracks features that get auto disabled by errors */
345 u64 auto_disable_flags;
346
38e00438
VD
347#ifdef I40E_FCOE
348 struct i40e_fcoe fcoe;
349
350#endif /* I40E_FCOE */
7daa6bf3
JB
351 bool stat_offsets_loaded;
352 struct i40e_hw_port_stats stats;
353 struct i40e_hw_port_stats stats_offsets;
354 u32 tx_timeout_count;
355 u32 tx_timeout_recovery_level;
356 unsigned long tx_timeout_last_recovery;
810b3ae4 357 u32 tx_sluggish_count;
7daa6bf3
JB
358 u32 hw_csum_rx_error;
359 u32 led_status;
360 u16 corer_count; /* Core reset count */
361 u16 globr_count; /* Global reset count */
362 u16 empr_count; /* EMP reset count */
363 u16 pfr_count; /* PF reset count */
cd92e72f 364 u16 sw_int_count; /* SW interrupt count */
7daa6bf3
JB
365
366 struct mutex switch_mutex;
367 u16 lan_vsi; /* our default LAN VSI */
368 u16 lan_veb; /* initial relay, if exists */
369#define I40E_NO_VEB 0xffff
370#define I40E_NO_VSI 0xffff
371 u16 next_vsi; /* Next unallocated VSI - 0-based! */
372 struct i40e_vsi **vsi;
373 struct i40e_veb *veb[I40E_MAX_VEB];
374
375 struct i40e_lump_tracking *qp_pile;
376 struct i40e_lump_tracking *irq_pile;
377
378 /* switch config info */
379 u16 pf_seid;
380 u16 main_vsi_seid;
381 u16 mac_seid;
7daa6bf3
JB
382 struct kobject *switch_kobj;
383#ifdef CONFIG_DEBUG_FS
384 struct dentry *i40e_dbg_pf;
385#endif /* CONFIG_DEBUG_FS */
92faef85 386 bool cur_promisc;
7daa6bf3 387
93cd765b
ASJ
388 u16 instance; /* A unique number per i40e_pf instance in the system */
389
7daa6bf3
JB
390 /* sr-iov config info */
391 struct i40e_vf *vf;
392 int num_alloc_vfs; /* actual number of VFs allocated */
393 u32 vf_aq_requests;
394
395 /* DCBx/DCBNL capability for PF that indicates
396 * whether DCBx is managed by firmware or host
397 * based agent (LLDPAD). Also, indicates what
398 * flavor of DCBx protocol (IEEE/CEE) is supported
399 * by the device. For now we're supporting IEEE
400 * mode only.
401 */
402 u16 dcbx_cap;
403
404 u32 fcoe_hmc_filt_num;
405 u32 fcoe_hmc_cntx_num;
406 struct i40e_filter_control_settings filter_settings;
beb0dff1
JK
407
408 struct ptp_clock *ptp_clock;
409 struct ptp_clock_info ptp_caps;
410 struct sk_buff *ptp_tx_skb;
beb0dff1 411 struct hwtstamp_config tstamp_config;
beb0dff1
JK
412 unsigned long last_rx_ptp_check;
413 spinlock_t tmreg_lock; /* Used to protect the device time registers. */
414 u64 ptp_base_adj;
415 u32 tx_hwtstamp_timeouts;
416 u32 rx_hwtstamp_cleared;
417 bool ptp_tx;
418 bool ptp_rx;
acd65448 419 u16 rss_table_size; /* HW RSS table size */
f4492db1
GR
420 /* These are only valid in NPAR modes */
421 u32 npar_max_bw;
422 u32 npar_min_bw;
2ac8b675
SN
423
424 u32 ioremap_len;
3487b6c3 425 u32 fd_inv;
7daa6bf3
JB
426};
427
428struct i40e_mac_filter {
429 struct list_head list;
430 u8 macaddr[ETH_ALEN];
431#define I40E_VLAN_ANY -1
432 s16 vlan;
433 u8 counter; /* number of instances of this filter */
434 bool is_vf; /* filter belongs to a VF */
435 bool is_netdev; /* filter belongs to a netdev */
436 bool changed; /* filter needs to be sync'd to the HW */
6252c7e4 437 bool is_laa; /* filter is a Locally Administered Address */
7daa6bf3
JB
438};
439
440struct i40e_veb {
441 struct i40e_pf *pf;
442 u16 idx;
443 u16 veb_idx; /* index of VEB parent */
444 u16 seid;
445 u16 uplink_seid;
446 u16 stats_idx; /* index of VEB parent */
447 u8 enabled_tc;
51616018 448 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
7daa6bf3
JB
449 u16 flags;
450 u16 bw_limit;
451 u8 bw_max_quanta;
452 bool is_abs_credits;
453 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
454 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
455 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
456 struct kobject *kobj;
457 bool stat_offsets_loaded;
458 struct i40e_eth_stats stats;
459 struct i40e_eth_stats stats_offsets;
fe860afb
NP
460 struct i40e_veb_tc_stats tc_stats;
461 struct i40e_veb_tc_stats tc_stats_offsets;
7daa6bf3
JB
462};
463
464/* struct that defines a VSI, associated with a dev */
465struct i40e_vsi {
466 struct net_device *netdev;
467 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
468 bool netdev_registered;
469 bool stat_offsets_loaded;
470
471 u32 current_netdev_flags;
472 unsigned long state;
41a1d04b
JB
473#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
474#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
7daa6bf3
JB
475 unsigned long flags;
476
21659035
KP
477 /* Per VSI lock to protect elements/list (MAC filter) */
478 spinlock_t mac_filter_list_lock;
7daa6bf3
JB
479 struct list_head mac_filter_list;
480
481 /* VSI stats */
482 struct rtnl_link_stats64 net_stats;
483 struct rtnl_link_stats64 net_stats_offsets;
484 struct i40e_eth_stats eth_stats;
485 struct i40e_eth_stats eth_stats_offsets;
38e00438
VD
486#ifdef I40E_FCOE
487 struct i40e_fcoe_stats fcoe_stats;
488 struct i40e_fcoe_stats fcoe_stats_offsets;
489 bool fcoe_stat_offsets_loaded;
490#endif
7daa6bf3
JB
491 u32 tx_restart;
492 u32 tx_busy;
2fc3d715 493 u64 tx_linearize;
164c9f54 494 u64 tx_force_wb;
7daa6bf3
JB
495 u32 rx_buf_failed;
496 u32 rx_page_failed;
497
9f65e15b
AD
498 /* These are containers of ring pointers, allocated at run-time */
499 struct i40e_ring **rx_rings;
500 struct i40e_ring **tx_rings;
7daa6bf3
JB
501
502 u16 work_limit;
503 /* high bit set means dynamic, use accessor routines to read/write.
504 * hardware only supports 2us resolution for the ITR registers.
505 * these values always store the USER setting, and must be converted
506 * before programming to a register.
507 */
508 u16 rx_itr_setting;
509 u16 tx_itr_setting;
ac26fc13 510 u16 int_rate_limit; /* value in usecs */
7daa6bf3 511
acd65448
HZ
512 u16 rss_table_size; /* HW RSS table size */
513 u16 rss_size; /* Allocated RSS queues */
28c5869f
HZ
514 u8 *rss_hkey_user; /* User configured hash keys */
515 u8 *rss_lut_user; /* User configured lookup table entries */
5db4cb59 516
7daa6bf3
JB
517 u16 max_frame;
518 u16 rx_hdr_len;
519 u16 rx_buf_len;
520 u8 dtype;
521
522 /* List of q_vectors allocated to this VSI */
493fb300 523 struct i40e_q_vector **q_vectors;
7daa6bf3
JB
524 int num_q_vectors;
525 int base_vector;
63741846 526 bool irqs_ready;
7daa6bf3
JB
527
528 u16 seid; /* HW index of this VSI (absolute index) */
529 u16 id; /* VSI number */
530 u16 uplink_seid;
531
532 u16 base_queue; /* vsi's first queue in hw array */
533 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
9a3bd2f1 534 u16 req_queue_pairs; /* User requested queue pairs */
7daa6bf3
JB
535 u16 num_queue_pairs; /* Used tx and rx pairs */
536 u16 num_desc;
537 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
538 u16 vf_id; /* Virtual function ID for SRIOV VSIs */
539
540 struct i40e_tc_configuration tc_config;
541 struct i40e_aqc_vsi_properties_data info;
542
543 /* VSI BW limit (absolute across all TCs) */
544 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
545 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
546
547 /* Relative TC credits across VSIs */
548 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
549 /* TC BW limit credits within VSI */
550 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
551 /* TC BW limit max quanta within VSI */
552 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
553
554 struct i40e_pf *back; /* Backreference to associated PF */
555 u16 idx; /* index in pf->vsi[] */
556 u16 veb_idx; /* index of VEB parent */
557 struct kobject *kobj; /* sysfs object */
c156f856 558 bool current_isup; /* Sync 'link up' logging */
7daa6bf3
JB
559
560 /* VSI specific handlers */
561 irqreturn_t (*irq_handler)(int irq, void *data);
88eee9bc
CW
562
563 /* current rxnfc data */
564 struct ethtool_rxnfc rxnfc; /* current rss hash opts */
7daa6bf3
JB
565} ____cacheline_internodealigned_in_smp;
566
567struct i40e_netdev_priv {
568 struct i40e_vsi *vsi;
569};
570
571/* struct that defines an interrupt vector */
572struct i40e_q_vector {
573 struct i40e_vsi *vsi;
574
575 u16 v_idx; /* index in the vsi->q_vector array. */
576 u16 reg_idx; /* register index of the interrupt */
577
578 struct napi_struct napi;
579
580 struct i40e_ring_container rx;
581 struct i40e_ring_container tx;
582
583 u8 num_ringpairs; /* total number of ring pairs in vector */
584
9c6c1259
KP
585#define I40E_Q_VECTOR_HUNG_DETECT 0 /* Bit Index for hung detection logic */
586 unsigned long hung_detected; /* Set/Reset for hung_detection logic */
587
7daa6bf3 588 cpumask_t affinity_mask;
493fb300 589 struct rcu_head rcu; /* to avoid race with update stats on free */
b294ac70 590 char name[I40E_INT_NAME_STR_LEN];
8e0764b4 591 bool arm_wb_state;
ee2319cf
JB
592#define ITR_COUNTDOWN_START 100
593 u8 itr_countdown; /* when 0 should adjust ITR */
7daa6bf3
JB
594} ____cacheline_internodealigned_in_smp;
595
596/* lan device */
597struct i40e_device {
598 struct list_head list;
599 struct i40e_pf *pf;
600};
601
602/**
6dec1017 603 * i40e_nvm_version_str - format the NVM version strings
7daa6bf3
JB
604 * @hw: ptr to the hardware info
605 **/
6dec1017 606static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
7daa6bf3
JB
607{
608 static char buf[32];
2efaad86
CW
609 u32 full_ver;
610 u8 ver, patch;
611 u16 build;
612
613 full_ver = hw->nvm.oem_ver;
614 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
4eeb1fff
JB
615 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
616 I40E_OEM_VER_BUILD_MASK);
2efaad86 617 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
7daa6bf3
JB
618
619 snprintf(buf, sizeof(buf),
f0b44440 620 "%x.%02x 0x%x %d.%d.%d",
ff80301e
JB
621 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
622 I40E_NVM_VERSION_HI_SHIFT,
623 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
624 I40E_NVM_VERSION_LO_SHIFT,
2efaad86 625 hw->nvm.eetrack, ver, build, patch);
7daa6bf3
JB
626
627 return buf;
628}
629
630/**
631 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
632 * @netdev: the corresponding netdev
633 *
634 * Return the PF struct for the given netdev
635 **/
636static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
637{
638 struct i40e_netdev_priv *np = netdev_priv(netdev);
639 struct i40e_vsi *vsi = np->vsi;
640
641 return vsi->back;
642}
643
644static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
645 irqreturn_t (*irq_handler)(int, void *))
646{
647 vsi->irq_handler = irq_handler;
648}
649
650/**
651 * i40e_rx_is_programming_status - check for programming status descriptor
652 * @qw: the first quad word of the program status descriptor
653 *
654 * The value of in the descriptor length field indicate if this
655 * is a programming status descriptor for flow director or FCoE
656 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
657 * it is a packet descriptor.
658 **/
659static inline bool i40e_rx_is_programming_status(u64 qw)
660{
661 return I40E_RX_PROG_STATUS_DESC_LENGTH ==
662 (qw >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT);
663}
664
082def10
ASJ
665/**
666 * i40e_get_fd_cnt_all - get the total FD filter space available
b40c82e6 667 * @pf: pointer to the PF struct
082def10
ASJ
668 **/
669static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
670{
671 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
672}
673
7daa6bf3
JB
674/* needed by i40e_ethtool.c */
675int i40e_up(struct i40e_vsi *vsi);
676void i40e_down(struct i40e_vsi *vsi);
677extern const char i40e_driver_name[];
678extern const char i40e_driver_version_str[];
23326186 679void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
7daa6bf3 680void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags);
043dd650
HZ
681int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
682int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
fdf0e0bf 683struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
7daa6bf3
JB
684void i40e_update_stats(struct i40e_vsi *vsi);
685void i40e_update_eth_stats(struct i40e_vsi *vsi);
686struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
687int i40e_fetch_switch_configuration(struct i40e_pf *pf,
688 bool printconfig);
689
17a73f6b 690int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
7daa6bf3 691 struct i40e_pf *pf, bool add);
17a73f6b
JG
692int i40e_add_del_fdir(struct i40e_vsi *vsi,
693 struct i40e_fdir_filter *input, bool add);
55a5e60b 694void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
04294e38
ASJ
695u32 i40e_get_current_fd_count(struct i40e_pf *pf);
696u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
697u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
698u32 i40e_get_global_fd_count(struct i40e_pf *pf);
7c3c288b 699bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
7daa6bf3
JB
700void i40e_set_ethtool_ops(struct net_device *netdev);
701struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
702 u8 *macaddr, s16 vlan,
703 bool is_vf, bool is_netdev);
704void i40e_del_filter(struct i40e_vsi *vsi, u8 *macaddr, s16 vlan,
705 bool is_vf, bool is_netdev);
17652c63 706int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
7daa6bf3
JB
707struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
708 u16 uplink, u32 param1);
709int i40e_vsi_release(struct i40e_vsi *vsi);
710struct i40e_vsi *i40e_vsi_lookup(struct i40e_pf *pf, enum i40e_vsi_type type,
711 struct i40e_vsi *start_vsi);
38e00438
VD
712#ifdef I40E_FCOE
713void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
714 struct i40e_vsi_context *ctxt,
715 u8 enabled_tc, bool is_add);
716#endif
fc18eaa0 717int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool enable);
f8ff1464 718int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
7daa6bf3
JB
719struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
720 u16 downlink_seid, u8 enabled_tc);
721void i40e_veb_release(struct i40e_veb *veb);
722
4e3b35b0 723int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
4eeb1fff 724int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
7daa6bf3
JB
725void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
726void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
727void i40e_pf_reset_stats(struct i40e_pf *pf);
728#ifdef CONFIG_DEBUG_FS
729void i40e_dbg_pf_init(struct i40e_pf *pf);
730void i40e_dbg_pf_exit(struct i40e_pf *pf);
731void i40e_dbg_init(void);
732void i40e_dbg_exit(void);
733#else
734static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
735static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
736static inline void i40e_dbg_init(void) {}
737static inline void i40e_dbg_exit(void) {}
738#endif /* CONFIG_DEBUG_FS*/
02d109be
JB
739/**
740 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
741 * @vsi: pointer to a vsi
742 * @vector: enable a particular Hw Interrupt vector, without base_vector
743 **/
744static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
745{
746 struct i40e_pf *pf = vsi->back;
747 struct i40e_hw *hw = &pf->hw;
748 u32 val;
749
750 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
751 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
752 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
753 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
754 /* skip the flush */
755}
756
5c2cebda 757void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector);
2ef28cfb 758void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
116a57d4 759void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
38e00438
VD
760#ifdef I40E_FCOE
761struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
762 struct net_device *netdev,
763 struct rtnl_link_stats64 *storage);
764int i40e_set_mac(struct net_device *netdev, void *p);
765void i40e_set_rx_mode(struct net_device *netdev);
766#endif
7daa6bf3 767int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
38e00438
VD
768#ifdef I40E_FCOE
769void i40e_tx_timeout(struct net_device *netdev);
770int i40e_vlan_rx_add_vid(struct net_device *netdev,
771 __always_unused __be16 proto, u16 vid);
772int i40e_vlan_rx_kill_vid(struct net_device *netdev,
773 __always_unused __be16 proto, u16 vid);
774#endif
96664483 775int i40e_open(struct net_device *netdev);
6c167f58 776int i40e_vsi_open(struct i40e_vsi *vsi);
7daa6bf3
JB
777void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
778int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid);
779int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid);
780struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
781 bool is_vf, bool is_netdev);
b36e9ab5
MW
782int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
783 bool is_vf, bool is_netdev);
7daa6bf3
JB
784bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
785struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
786 bool is_vf, bool is_netdev);
38e00438 787#ifdef I40E_FCOE
38e00438
VD
788int i40e_close(struct net_device *netdev);
789int i40e_setup_tc(struct net_device *netdev, u8 tc);
790void i40e_netpoll(struct net_device *netdev);
791int i40e_fcoe_enable(struct net_device *netdev);
792int i40e_fcoe_disable(struct net_device *netdev);
793int i40e_fcoe_vsi_init(struct i40e_vsi *vsi, struct i40e_vsi_context *ctxt);
794u8 i40e_get_fcoe_tc_map(struct i40e_pf *pf);
795void i40e_fcoe_config_netdev(struct net_device *netdev, struct i40e_vsi *vsi);
796void i40e_fcoe_vsi_setup(struct i40e_pf *pf);
21364bcf 797void i40e_init_pf_fcoe(struct i40e_pf *pf);
38e00438
VD
798int i40e_fcoe_setup_ddp_resources(struct i40e_vsi *vsi);
799void i40e_fcoe_free_ddp_resources(struct i40e_vsi *vsi);
800int i40e_fcoe_handle_offload(struct i40e_ring *rx_ring,
801 union i40e_rx_desc *rx_desc,
802 struct sk_buff *skb);
803void i40e_fcoe_handle_status(struct i40e_ring *rx_ring,
804 union i40e_rx_desc *rx_desc, u8 prog_id);
805#endif /* I40E_FCOE */
7daa6bf3 806void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
4e3b35b0
NP
807#ifdef CONFIG_I40E_DCB
808void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
750fcbcf 809 struct i40e_dcbx_config *old_cfg,
4e3b35b0
NP
810 struct i40e_dcbx_config *new_cfg);
811void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
812void i40e_dcbnl_setup(struct i40e_vsi *vsi);
813bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
814 struct i40e_dcbx_config *old_cfg,
815 struct i40e_dcbx_config *new_cfg);
816#endif /* CONFIG_I40E_DCB */
beb0dff1
JK
817void i40e_ptp_rx_hang(struct i40e_vsi *vsi);
818void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
819void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
820void i40e_ptp_set_increment(struct i40e_pf *pf);
821int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
822int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
823void i40e_ptp_init(struct i40e_pf *pf);
824void i40e_ptp_stop(struct i40e_pf *pf);
51616018 825int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
f4492db1
GR
826i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf);
827i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf);
828i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf);
c156f856 829void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
7daa6bf3 830#endif /* _I40E_H_ */
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