Merge tag 'libnvdimm-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm...
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e.h
CommitLineData
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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
40d72a50 4 * Copyright(c) 2013 - 2016 Intel Corporation.
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5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
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17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_H_
28#define _I40E_H_
29
30#include <net/tcp.h>
8144f0f7 31#include <net/udp.h>
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32#include <linux/types.h>
33#include <linux/errno.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/aer.h>
37#include <linux/netdevice.h>
38#include <linux/ioport.h>
2bc7ee8a 39#include <linux/iommu.h>
7daa6bf3
JB
40#include <linux/slab.h>
41#include <linux/list.h>
42#include <linux/string.h>
43#include <linux/in.h>
44#include <linux/ip.h>
7daa6bf3
JB
45#include <linux/sctp.h>
46#include <linux/pkt_sched.h>
47#include <linux/ipv6.h>
7daa6bf3
JB
48#include <net/checksum.h>
49#include <net/ip6_checksum.h>
50#include <linux/ethtool.h>
51#include <linux/if_vlan.h>
51616018 52#include <linux/if_bridge.h>
beb0dff1
JK
53#include <linux/clocksource.h>
54#include <linux/net_tstamp.h>
55#include <linux/ptp_clock_kernel.h>
7daa6bf3
JB
56#include "i40e_type.h"
57#include "i40e_prototype.h"
38e00438
VD
58#ifdef I40E_FCOE
59#include "i40e_fcoe.h"
60#endif
e3219ce6 61#include "i40e_client.h"
7daa6bf3
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62#include "i40e_virtchnl.h"
63#include "i40e_virtchnl_pf.h"
64#include "i40e_txrx.h"
4e3b35b0 65#include "i40e_dcb.h"
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66
67/* Useful i40e defaults */
7daa6bf3
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68#define I40E_MAX_VEB 16
69
70#define I40E_MAX_NUM_DESCRIPTORS 4096
232f4706 71#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
7daa6bf3
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72#define I40E_DEFAULT_NUM_DESCRIPTORS 512
73#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
74#define I40E_MIN_NUM_DESCRIPTORS 64
75#define I40E_MIN_MSIX 2
76#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
505682cd 77#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */
e25d00b8
ASJ
78/* max 16 qps */
79#define i40e_default_queues_per_vmdq(pf) \
80 (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
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81#define I40E_DEFAULT_QUEUES_PER_VF 4
82#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
e25d00b8
ASJ
83#define i40e_pf_get_max_q_per_tc(pf) \
84 (((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
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85#define I40E_FDIR_RING 0
86#define I40E_FDIR_RING_COUNT 32
38e00438
VD
87#ifdef I40E_FCOE
88#define I40E_DEFAULT_FCOE 8 /* default number of QPs for FCoE */
89#define I40E_MINIMUM_FCOE 1 /* minimum number of QPs for FCoE */
90#endif /* I40E_FCOE */
7daa6bf3 91#define I40E_MAX_AQ_BUF_SIZE 4096
07574897 92#define I40E_AQ_LEN 256
628f096d 93#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
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94#define I40E_MAX_USER_PRIORITY 8
95#define I40E_DEFAULT_MSG_ENABLE 4
23527308 96#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
fba52e21 97#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
7daa6bf3 98
7e45ab44 99/* Ethtool Private Flags */
b5569892
ASJ
100#define I40E_PRIV_FLAGS_MFP_FLAG BIT(0)
101#define I40E_PRIV_FLAGS_LINKPOLL_FLAG BIT(1)
102#define I40E_PRIV_FLAGS_FD_ATR BIT(2)
103#define I40E_PRIV_FLAGS_VEB_STATS BIT(3)
104#define I40E_PRIV_FLAGS_HW_ATR_EVICT BIT(4)
105#define I40E_PRIV_FLAGS_TRUE_PROMISC_SUPPORT BIT(5)
7e45ab44 106
7daa6bf3 107#define I40E_NVM_VERSION_LO_SHIFT 0
fe310704 108#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
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109#define I40E_NVM_VERSION_HI_SHIFT 12
110#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
2efaad86 111#define I40E_OEM_VER_BUILD_MASK 0xffff
f0b44440 112#define I40E_OEM_VER_PATCH_MASK 0xff
2efaad86
CW
113#define I40E_OEM_VER_BUILD_SHIFT 8
114#define I40E_OEM_VER_SHIFT 24
06c0e39b
KS
115#define I40E_PHY_DEBUG_ALL \
116 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
117 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
fe310704
AS
118
119/* The values in here are decimal coded as hex as is the case in the NVM map*/
120#define I40E_CURRENT_NVM_VERSION_HI 0x2
ff80301e 121#define I40E_CURRENT_NVM_VERSION_LO 0x40
fe310704 122
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JB
123/* magic for getting defines into strings */
124#define STRINGIFY(foo) #foo
125#define XSTRINGIFY(bar) STRINGIFY(bar)
126
7daa6bf3 127#define I40E_RX_DESC(R, i) \
bec60fc4 128 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
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129#define I40E_TX_DESC(R, i) \
130 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
131#define I40E_TX_CTXTDESC(R, i) \
132 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
133#define I40E_TX_FDIRDESC(R, i) \
134 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
135
136/* default to trying for four seconds */
137#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
138
f1bbad33
NP
139/**
140 * i40e_is_mac_710 - Return true if MAC is X710/XL710
141 * @hw: ptr to the hardware info
142 **/
143static inline bool i40e_is_mac_710(struct i40e_hw *hw)
144{
145 if ((hw->mac.type == I40E_MAC_X710) ||
146 (hw->mac.type == I40E_MAC_XL710))
147 return true;
148
149 return false;
150}
151
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152/* driver state flags */
153enum i40e_state_t {
154 __I40E_TESTING,
155 __I40E_CONFIG_BUSY,
156 __I40E_CONFIG_DONE,
157 __I40E_DOWN,
158 __I40E_NEEDS_RESTART,
159 __I40E_SERVICE_SCHED,
160 __I40E_ADMINQ_EVENT_PENDING,
161 __I40E_MDD_EVENT_PENDING,
162 __I40E_VFLR_EVENT_PENDING,
163 __I40E_RESET_RECOVERY_PENDING,
164 __I40E_RESET_INTR_RECEIVED,
165 __I40E_REINIT_REQUESTED,
166 __I40E_PF_RESET_REQUESTED,
167 __I40E_CORE_RESET_REQUESTED,
168 __I40E_GLOBAL_RESET_REQUESTED,
7823fe34 169 __I40E_EMP_RESET_REQUESTED,
9df42d1a 170 __I40E_EMP_RESET_INTR_RECEIVED,
7daa6bf3 171 __I40E_FILTER_OVERFLOW_PROMISC,
9007bccd 172 __I40E_SUSPENDED,
9ce34f02 173 __I40E_PTP_TX_IN_PROGRESS,
4eb3f768 174 __I40E_BAD_EEPROM,
b5d06f05 175 __I40E_DOWN_REQUESTED,
1e1be8f6 176 __I40E_FD_FLUSH_REQUESTED,
a316f651 177 __I40E_RESET_FAILED,
69129dc3 178 __I40E_PORT_TX_SUSPENDED,
3ba9bcb4 179 __I40E_VF_DISABLE,
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180};
181
182enum i40e_interrupt_policy {
183 I40E_INTERRUPT_BEST_CASE,
184 I40E_INTERRUPT_MEDIUM,
185 I40E_INTERRUPT_LOWEST
186};
187
188struct i40e_lump_tracking {
189 u16 num_entries;
190 u16 search_hint;
191 u16 list[0];
192#define I40E_PILE_VALID_BIT 0x8000
e3219ce6 193#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
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194};
195
196#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
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197#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
198#define I40E_FDIR_BUFFER_FULL_MARGIN 10
12957388 199#define I40E_FDIR_BUFFER_HEAD_ROOM 32
04294e38 200#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
55a5e60b 201
b29e13bb 202#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
e69ff813 203#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
c4e1868c 204#define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
b29e13bb 205
433c47de
ASJ
206enum i40e_fd_stat_idx {
207 I40E_FD_STAT_ATR,
208 I40E_FD_STAT_SB,
60ccd45c 209 I40E_FD_STAT_ATR_TUNNEL,
433c47de
ASJ
210 I40E_FD_STAT_PF_COUNT
211};
212#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
213#define I40E_FD_ATR_STAT_IDX(pf_id) \
214 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
215#define I40E_FD_SB_STAT_IDX(pf_id) \
216 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
60ccd45c
ASJ
217#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
218 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
433c47de 219
17a73f6b
JG
220struct i40e_fdir_filter {
221 struct hlist_node fdir_node;
222 /* filter ipnut set */
223 u8 flow_type;
224 u8 ip4_proto;
04b73bd7 225 /* TX packet view of src and dst */
17a73f6b
JG
226 __be32 dst_ip[4];
227 __be32 src_ip[4];
228 __be16 src_port;
229 __be16 dst_port;
230 __be32 sctp_v_tag;
231 /* filter control */
7daa6bf3
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232 u16 q_index;
233 u8 flex_off;
234 u8 pctype;
235 u16 dest_vsi;
236 u8 dest_ctl;
237 u8 fd_status;
238 u16 cnt_index;
239 u32 fd_id;
7daa6bf3
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240};
241
4e3b35b0
NP
242#define I40E_ETH_P_LLDP 0x88cc
243
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244#define I40E_DCB_PRIO_TYPE_STRICT 0
245#define I40E_DCB_PRIO_TYPE_ETS 1
246#define I40E_DCB_STRICT_PRIO_CREDITS 127
7daa6bf3
JB
247/* DCB per TC information data structure */
248struct i40e_tc_info {
249 u16 qoffset; /* Queue offset from base queue */
250 u16 qcount; /* Total Queues */
251 u8 netdev_tc; /* Netdev TC index if netdev associated */
252};
253
254/* TC configuration data structure */
255struct i40e_tc_configuration {
256 u8 numtc; /* Total number of enabled TCs */
257 u8 enabled_tc; /* TC map */
258 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
259};
260
6a899024
SA
261struct i40e_udp_port_config {
262 __be16 index;
263 u8 type;
264};
265
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266/* struct that defines the Ethernet device */
267struct i40e_pf {
268 struct pci_dev *pdev;
269 struct i40e_hw hw;
270 unsigned long state;
7daa6bf3 271 struct msix_entry *msix_entries;
7daa6bf3
JB
272 bool fc_autoneg_status;
273
274 u16 eeprom_version;
b40c82e6 275 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
7daa6bf3
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276 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
277 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
b40c82e6
JK
278 u16 num_req_vfs; /* num VFs requested for this VF */
279 u16 num_vf_qps; /* num queue pairs per VF */
38e00438 280#ifdef I40E_FCOE
b40c82e6 281 u16 num_fcoe_qps; /* num fcoe queues this PF has set up */
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VD
282 u16 num_fcoe_msix; /* num queue vectors per fcoe pool */
283#endif /* I40E_FCOE */
b40c82e6
JK
284 u16 num_lan_qps; /* num lan queues this PF has set up */
285 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
a70e407f 286 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
e3219ce6
ASJ
287 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
288 int iwarp_base_vector;
f8ff1464 289 int queues_left; /* queues left unclaimed */
acd65448 290 u16 alloc_rss_size; /* allocated RSS queues */
7daa6bf3
JB
291 u16 rss_size_max; /* HW defined max RSS queues */
292 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
505682cd 293 u16 num_alloc_vsi; /* num VSIs this driver supports */
7daa6bf3 294 u8 atr_sample_rate;
8e2773ae 295 bool wol_en;
7daa6bf3 296
17a73f6b
JG
297 struct hlist_head fdir_filter_list;
298 u16 fdir_pf_active_filters;
1e1be8f6 299 unsigned long fd_flush_timestamp;
60793f4a 300 u32 fd_flush_cnt;
1e1be8f6
ASJ
301 u32 fd_add_err;
302 u32 fd_atr_cnt;
303 u32 fd_tcp_rule;
17a73f6b 304
6a899024
SA
305 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
306 u16 pending_udp_bitmap;
a1c9a9d9 307
7daa6bf3
JB
308 enum i40e_interrupt_policy int_policy;
309 u16 rx_itr_default;
310 u16 tx_itr_default;
71e6163a 311 u32 msg_enable;
b294ac70 312 char int_name[I40E_INT_NAME_STR_LEN];
7daa6bf3 313 u16 adminq_work_limit; /* num of admin receive queue desc to process */
21536717
SN
314 unsigned long service_timer_period;
315 unsigned long service_timer_previous;
7daa6bf3
JB
316 struct timer_list service_timer;
317 struct work_struct service_task;
318
319 u64 flags;
41a1d04b
JB
320#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
321#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
322#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
41a1d04b
JB
323#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
324#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
325#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
326#define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
d502ce01 327#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
38e00438 328#ifdef I40E_FCOE
41a1d04b 329#define I40E_FLAG_FCOE_ENABLED BIT_ULL(11)
38e00438 330#endif /* I40E_FCOE */
41a1d04b
JB
331#define I40E_FLAG_CLEAN_ADMINQ BIT_ULL(14)
332#define I40E_FLAG_FILTER_SYNC BIT_ULL(15)
e3219ce6 333#define I40E_FLAG_SERVICE_CLIENT_REQUESTED BIT_ULL(16)
41a1d04b
JB
334#define I40E_FLAG_PROCESS_MDD_EVENT BIT_ULL(17)
335#define I40E_FLAG_PROCESS_VFLR_EVENT BIT_ULL(18)
336#define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19)
337#define I40E_FLAG_DCB_ENABLED BIT_ULL(20)
338#define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21)
339#define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22)
340#define I40E_FLAG_PTP BIT_ULL(25)
341#define I40E_FLAG_MFP_ENABLED BIT_ULL(26)
6a899024 342#define I40E_FLAG_UDP_FILTER_SYNC BIT_ULL(27)
41a1d04b
JB
343#define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)
344#define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
d502ce01
ASJ
345#define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31)
346#define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32)
347#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33)
348#define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34)
349#define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35)
d1a8d275 350#define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37)
d502ce01 351#define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38)
9ac77266 352#define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39)
fc60861e 353#define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)
6a899024 354#define I40E_FLAG_GENEVE_OFFLOAD_CAPABLE BIT_ULL(41)
3fced535 355#define I40E_FLAG_NO_PCI_LINK_CHECK BIT_ULL(42)
48b1804e 356#define I40E_FLAG_100M_SGMII_CAPABLE BIT_ULL(43)
8eed76fa 357#define I40E_FLAG_RESTART_AUTONEG BIT_ULL(44)
f1bbad33
NP
358#define I40E_FLAG_NO_DCB_SUPPORT BIT_ULL(45)
359#define I40E_FLAG_USE_SET_LLDP_MIB BIT_ULL(46)
360#define I40E_FLAG_STOP_FW_LLDP BIT_ULL(47)
31b606d0 361#define I40E_FLAG_HAVE_10GBASET_PHY BIT_ULL(48)
b499ffb0 362#define I40E_FLAG_PF_MAC BIT_ULL(50)
b5569892 363#define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT_ULL(51)
7daa6bf3 364
61dade7e
ASJ
365 /* tracks features that get auto disabled by errors */
366 u64 auto_disable_flags;
367
38e00438
VD
368#ifdef I40E_FCOE
369 struct i40e_fcoe fcoe;
370
371#endif /* I40E_FCOE */
7daa6bf3
JB
372 bool stat_offsets_loaded;
373 struct i40e_hw_port_stats stats;
374 struct i40e_hw_port_stats stats_offsets;
375 u32 tx_timeout_count;
376 u32 tx_timeout_recovery_level;
377 unsigned long tx_timeout_last_recovery;
810b3ae4 378 u32 tx_sluggish_count;
7daa6bf3
JB
379 u32 hw_csum_rx_error;
380 u32 led_status;
381 u16 corer_count; /* Core reset count */
382 u16 globr_count; /* Global reset count */
383 u16 empr_count; /* EMP reset count */
384 u16 pfr_count; /* PF reset count */
cd92e72f 385 u16 sw_int_count; /* SW interrupt count */
7daa6bf3
JB
386
387 struct mutex switch_mutex;
388 u16 lan_vsi; /* our default LAN VSI */
389 u16 lan_veb; /* initial relay, if exists */
390#define I40E_NO_VEB 0xffff
391#define I40E_NO_VSI 0xffff
392 u16 next_vsi; /* Next unallocated VSI - 0-based! */
393 struct i40e_vsi **vsi;
394 struct i40e_veb *veb[I40E_MAX_VEB];
395
396 struct i40e_lump_tracking *qp_pile;
397 struct i40e_lump_tracking *irq_pile;
398
399 /* switch config info */
400 u16 pf_seid;
401 u16 main_vsi_seid;
402 u16 mac_seid;
7daa6bf3
JB
403 struct kobject *switch_kobj;
404#ifdef CONFIG_DEBUG_FS
405 struct dentry *i40e_dbg_pf;
406#endif /* CONFIG_DEBUG_FS */
92faef85 407 bool cur_promisc;
7daa6bf3 408
93cd765b
ASJ
409 u16 instance; /* A unique number per i40e_pf instance in the system */
410
7daa6bf3
JB
411 /* sr-iov config info */
412 struct i40e_vf *vf;
413 int num_alloc_vfs; /* actual number of VFs allocated */
414 u32 vf_aq_requests;
1d0a4ada 415 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
7daa6bf3
JB
416
417 /* DCBx/DCBNL capability for PF that indicates
418 * whether DCBx is managed by firmware or host
419 * based agent (LLDPAD). Also, indicates what
420 * flavor of DCBx protocol (IEEE/CEE) is supported
421 * by the device. For now we're supporting IEEE
422 * mode only.
423 */
424 u16 dcbx_cap;
425
426 u32 fcoe_hmc_filt_num;
427 u32 fcoe_hmc_cntx_num;
428 struct i40e_filter_control_settings filter_settings;
beb0dff1
JK
429
430 struct ptp_clock *ptp_clock;
431 struct ptp_clock_info ptp_caps;
432 struct sk_buff *ptp_tx_skb;
beb0dff1 433 struct hwtstamp_config tstamp_config;
beb0dff1
JK
434 unsigned long last_rx_ptp_check;
435 spinlock_t tmreg_lock; /* Used to protect the device time registers. */
436 u64 ptp_base_adj;
437 u32 tx_hwtstamp_timeouts;
438 u32 rx_hwtstamp_cleared;
439 bool ptp_tx;
440 bool ptp_rx;
acd65448 441 u16 rss_table_size; /* HW RSS table size */
f4492db1
GR
442 /* These are only valid in NPAR modes */
443 u32 npar_max_bw;
444 u32 npar_min_bw;
2ac8b675
SN
445
446 u32 ioremap_len;
3487b6c3 447 u32 fd_inv;
31b606d0 448 u16 phy_led_val;
7daa6bf3
JB
449};
450
c3c7ea27
MW
451enum i40e_filter_state {
452 I40E_FILTER_INVALID = 0, /* Invalid state */
453 I40E_FILTER_NEW, /* New, not sent to FW yet */
454 I40E_FILTER_ACTIVE, /* Added to switch by FW */
455 I40E_FILTER_FAILED, /* Rejected by FW */
456 I40E_FILTER_REMOVE, /* To be removed */
457/* There is no 'removed' state; the filter struct is freed */
458};
7daa6bf3
JB
459struct i40e_mac_filter {
460 struct list_head list;
461 u8 macaddr[ETH_ALEN];
462#define I40E_VLAN_ANY -1
463 s16 vlan;
464 u8 counter; /* number of instances of this filter */
465 bool is_vf; /* filter belongs to a VF */
466 bool is_netdev; /* filter belongs to a netdev */
c3c7ea27 467 enum i40e_filter_state state;
7daa6bf3
JB
468};
469
470struct i40e_veb {
471 struct i40e_pf *pf;
472 u16 idx;
473 u16 veb_idx; /* index of VEB parent */
474 u16 seid;
475 u16 uplink_seid;
476 u16 stats_idx; /* index of VEB parent */
477 u8 enabled_tc;
51616018 478 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
7daa6bf3
JB
479 u16 flags;
480 u16 bw_limit;
481 u8 bw_max_quanta;
482 bool is_abs_credits;
483 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
484 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
485 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
486 struct kobject *kobj;
487 bool stat_offsets_loaded;
488 struct i40e_eth_stats stats;
489 struct i40e_eth_stats stats_offsets;
fe860afb
NP
490 struct i40e_veb_tc_stats tc_stats;
491 struct i40e_veb_tc_stats tc_stats_offsets;
7daa6bf3
JB
492};
493
494/* struct that defines a VSI, associated with a dev */
495struct i40e_vsi {
496 struct net_device *netdev;
497 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
498 bool netdev_registered;
499 bool stat_offsets_loaded;
500
501 u32 current_netdev_flags;
502 unsigned long state;
41a1d04b
JB
503#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
504#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
7daa6bf3
JB
505 unsigned long flags;
506
21659035
KP
507 /* Per VSI lock to protect elements/list (MAC filter) */
508 spinlock_t mac_filter_list_lock;
7daa6bf3
JB
509 struct list_head mac_filter_list;
510
511 /* VSI stats */
512 struct rtnl_link_stats64 net_stats;
513 struct rtnl_link_stats64 net_stats_offsets;
514 struct i40e_eth_stats eth_stats;
515 struct i40e_eth_stats eth_stats_offsets;
38e00438
VD
516#ifdef I40E_FCOE
517 struct i40e_fcoe_stats fcoe_stats;
518 struct i40e_fcoe_stats fcoe_stats_offsets;
519 bool fcoe_stat_offsets_loaded;
520#endif
7daa6bf3
JB
521 u32 tx_restart;
522 u32 tx_busy;
2fc3d715 523 u64 tx_linearize;
164c9f54 524 u64 tx_force_wb;
dd353109 525 u64 tx_lost_interrupt;
7daa6bf3
JB
526 u32 rx_buf_failed;
527 u32 rx_page_failed;
528
9f65e15b
AD
529 /* These are containers of ring pointers, allocated at run-time */
530 struct i40e_ring **rx_rings;
531 struct i40e_ring **tx_rings;
7daa6bf3 532
c3c7ea27
MW
533 u32 active_filters;
534 u32 promisc_threshold;
535
7daa6bf3 536 u16 work_limit;
ac26fc13 537 u16 int_rate_limit; /* value in usecs */
7daa6bf3 538
acd65448
HZ
539 u16 rss_table_size; /* HW RSS table size */
540 u16 rss_size; /* Allocated RSS queues */
28c5869f
HZ
541 u8 *rss_hkey_user; /* User configured hash keys */
542 u8 *rss_lut_user; /* User configured lookup table entries */
5db4cb59 543
7daa6bf3 544 u16 max_frame;
7daa6bf3 545 u16 rx_buf_len;
7daa6bf3
JB
546
547 /* List of q_vectors allocated to this VSI */
493fb300 548 struct i40e_q_vector **q_vectors;
7daa6bf3
JB
549 int num_q_vectors;
550 int base_vector;
63741846 551 bool irqs_ready;
7daa6bf3
JB
552
553 u16 seid; /* HW index of this VSI (absolute index) */
554 u16 id; /* VSI number */
555 u16 uplink_seid;
556
557 u16 base_queue; /* vsi's first queue in hw array */
558 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
9a3bd2f1 559 u16 req_queue_pairs; /* User requested queue pairs */
7daa6bf3
JB
560 u16 num_queue_pairs; /* Used tx and rx pairs */
561 u16 num_desc;
562 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
a1b5a24f 563 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
7daa6bf3
JB
564
565 struct i40e_tc_configuration tc_config;
566 struct i40e_aqc_vsi_properties_data info;
567
568 /* VSI BW limit (absolute across all TCs) */
569 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
570 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
571
572 /* Relative TC credits across VSIs */
573 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
574 /* TC BW limit credits within VSI */
575 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
576 /* TC BW limit max quanta within VSI */
577 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
578
579 struct i40e_pf *back; /* Backreference to associated PF */
580 u16 idx; /* index in pf->vsi[] */
581 u16 veb_idx; /* index of VEB parent */
582 struct kobject *kobj; /* sysfs object */
c156f856 583 bool current_isup; /* Sync 'link up' logging */
7daa6bf3 584
e3219ce6
ASJ
585 void *priv; /* client driver data reference. */
586
7daa6bf3
JB
587 /* VSI specific handlers */
588 irqreturn_t (*irq_handler)(int irq, void *data);
88eee9bc
CW
589
590 /* current rxnfc data */
591 struct ethtool_rxnfc rxnfc; /* current rss hash opts */
7daa6bf3
JB
592} ____cacheline_internodealigned_in_smp;
593
594struct i40e_netdev_priv {
595 struct i40e_vsi *vsi;
596};
597
598/* struct that defines an interrupt vector */
599struct i40e_q_vector {
600 struct i40e_vsi *vsi;
601
602 u16 v_idx; /* index in the vsi->q_vector array. */
603 u16 reg_idx; /* register index of the interrupt */
604
605 struct napi_struct napi;
606
607 struct i40e_ring_container rx;
608 struct i40e_ring_container tx;
609
610 u8 num_ringpairs; /* total number of ring pairs in vector */
611
9c6c1259
KP
612#define I40E_Q_VECTOR_HUNG_DETECT 0 /* Bit Index for hung detection logic */
613 unsigned long hung_detected; /* Set/Reset for hung_detection logic */
614
7daa6bf3 615 cpumask_t affinity_mask;
493fb300 616 struct rcu_head rcu; /* to avoid race with update stats on free */
b294ac70 617 char name[I40E_INT_NAME_STR_LEN];
8e0764b4 618 bool arm_wb_state;
ee2319cf
JB
619#define ITR_COUNTDOWN_START 100
620 u8 itr_countdown; /* when 0 should adjust ITR */
7daa6bf3
JB
621} ____cacheline_internodealigned_in_smp;
622
623/* lan device */
624struct i40e_device {
625 struct list_head list;
626 struct i40e_pf *pf;
627};
628
629/**
6dec1017 630 * i40e_nvm_version_str - format the NVM version strings
7daa6bf3
JB
631 * @hw: ptr to the hardware info
632 **/
6dec1017 633static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
7daa6bf3
JB
634{
635 static char buf[32];
2efaad86
CW
636 u32 full_ver;
637 u8 ver, patch;
638 u16 build;
639
640 full_ver = hw->nvm.oem_ver;
641 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
4eeb1fff
JB
642 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
643 I40E_OEM_VER_BUILD_MASK);
2efaad86 644 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
7daa6bf3
JB
645
646 snprintf(buf, sizeof(buf),
f0b44440 647 "%x.%02x 0x%x %d.%d.%d",
ff80301e
JB
648 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
649 I40E_NVM_VERSION_HI_SHIFT,
650 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
651 I40E_NVM_VERSION_LO_SHIFT,
2efaad86 652 hw->nvm.eetrack, ver, build, patch);
7daa6bf3
JB
653
654 return buf;
655}
656
657/**
658 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
659 * @netdev: the corresponding netdev
660 *
661 * Return the PF struct for the given netdev
662 **/
663static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
664{
665 struct i40e_netdev_priv *np = netdev_priv(netdev);
666 struct i40e_vsi *vsi = np->vsi;
667
668 return vsi->back;
669}
670
671static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
672 irqreturn_t (*irq_handler)(int, void *))
673{
674 vsi->irq_handler = irq_handler;
675}
676
677/**
678 * i40e_rx_is_programming_status - check for programming status descriptor
679 * @qw: the first quad word of the program status descriptor
680 *
681 * The value of in the descriptor length field indicate if this
682 * is a programming status descriptor for flow director or FCoE
683 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
684 * it is a packet descriptor.
685 **/
686static inline bool i40e_rx_is_programming_status(u64 qw)
687{
688 return I40E_RX_PROG_STATUS_DESC_LENGTH ==
689 (qw >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT);
690}
691
082def10
ASJ
692/**
693 * i40e_get_fd_cnt_all - get the total FD filter space available
b40c82e6 694 * @pf: pointer to the PF struct
082def10
ASJ
695 **/
696static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
697{
698 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
699}
700
7daa6bf3
JB
701/* needed by i40e_ethtool.c */
702int i40e_up(struct i40e_vsi *vsi);
703void i40e_down(struct i40e_vsi *vsi);
704extern const char i40e_driver_name[];
705extern const char i40e_driver_version_str[];
23326186 706void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
7daa6bf3 707void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags);
043dd650
HZ
708int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
709int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
fdf0e0bf 710struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
7daa6bf3
JB
711void i40e_update_stats(struct i40e_vsi *vsi);
712void i40e_update_eth_stats(struct i40e_vsi *vsi);
713struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
714int i40e_fetch_switch_configuration(struct i40e_pf *pf,
715 bool printconfig);
716
17a73f6b 717int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
7daa6bf3 718 struct i40e_pf *pf, bool add);
17a73f6b
JG
719int i40e_add_del_fdir(struct i40e_vsi *vsi,
720 struct i40e_fdir_filter *input, bool add);
55a5e60b 721void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
04294e38
ASJ
722u32 i40e_get_current_fd_count(struct i40e_pf *pf);
723u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
724u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
725u32 i40e_get_global_fd_count(struct i40e_pf *pf);
7c3c288b 726bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
7daa6bf3
JB
727void i40e_set_ethtool_ops(struct net_device *netdev);
728struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
729 u8 *macaddr, s16 vlan,
730 bool is_vf, bool is_netdev);
731void i40e_del_filter(struct i40e_vsi *vsi, u8 *macaddr, s16 vlan,
732 bool is_vf, bool is_netdev);
17652c63 733int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
7daa6bf3
JB
734struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
735 u16 uplink, u32 param1);
736int i40e_vsi_release(struct i40e_vsi *vsi);
737struct i40e_vsi *i40e_vsi_lookup(struct i40e_pf *pf, enum i40e_vsi_type type,
738 struct i40e_vsi *start_vsi);
38e00438
VD
739#ifdef I40E_FCOE
740void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
741 struct i40e_vsi_context *ctxt,
742 u8 enabled_tc, bool is_add);
743#endif
e3219ce6
ASJ
744void i40e_service_event_schedule(struct i40e_pf *pf);
745void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
746 u8 *msg, u16 len);
747
fc18eaa0 748int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool enable);
f8ff1464 749int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
7daa6bf3
JB
750struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
751 u16 downlink_seid, u8 enabled_tc);
752void i40e_veb_release(struct i40e_veb *veb);
753
4e3b35b0 754int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
4eeb1fff 755int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
7daa6bf3
JB
756void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
757void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
758void i40e_pf_reset_stats(struct i40e_pf *pf);
759#ifdef CONFIG_DEBUG_FS
760void i40e_dbg_pf_init(struct i40e_pf *pf);
761void i40e_dbg_pf_exit(struct i40e_pf *pf);
762void i40e_dbg_init(void);
763void i40e_dbg_exit(void);
764#else
765static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
766static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
767static inline void i40e_dbg_init(void) {}
768static inline void i40e_dbg_exit(void) {}
769#endif /* CONFIG_DEBUG_FS*/
e3219ce6
ASJ
770/* needed by client drivers */
771int i40e_lan_add_device(struct i40e_pf *pf);
772int i40e_lan_del_device(struct i40e_pf *pf);
773void i40e_client_subtask(struct i40e_pf *pf);
774void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
775void i40e_notify_client_of_netdev_open(struct i40e_vsi *vsi);
776void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
777void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
778void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
779int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id,
780 enum i40e_client_type type);
02d109be
JB
781/**
782 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
783 * @vsi: pointer to a vsi
784 * @vector: enable a particular Hw Interrupt vector, without base_vector
785 **/
786static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
787{
788 struct i40e_pf *pf = vsi->back;
789 struct i40e_hw *hw = &pf->hw;
790 u32 val;
791
40d72a50
JB
792 /* definitely clear the PBA here, as this function is meant to
793 * clean out all previous interrupts AND enable the interrupt
794 */
02d109be
JB
795 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
796 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
797 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
798 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
799 /* skip the flush */
800}
801
2ef28cfb 802void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
40d72a50 803void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba);
38e00438
VD
804#ifdef I40E_FCOE
805struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
806 struct net_device *netdev,
807 struct rtnl_link_stats64 *storage);
808int i40e_set_mac(struct net_device *netdev, void *p);
809void i40e_set_rx_mode(struct net_device *netdev);
810#endif
7daa6bf3 811int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
38e00438
VD
812#ifdef I40E_FCOE
813void i40e_tx_timeout(struct net_device *netdev);
814int i40e_vlan_rx_add_vid(struct net_device *netdev,
815 __always_unused __be16 proto, u16 vid);
816int i40e_vlan_rx_kill_vid(struct net_device *netdev,
817 __always_unused __be16 proto, u16 vid);
818#endif
96664483 819int i40e_open(struct net_device *netdev);
08ca3874 820int i40e_close(struct net_device *netdev);
6c167f58 821int i40e_vsi_open(struct i40e_vsi *vsi);
7daa6bf3
JB
822void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
823int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid);
824int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid);
825struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
826 bool is_vf, bool is_netdev);
b36e9ab5
MW
827int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
828 bool is_vf, bool is_netdev);
7daa6bf3
JB
829bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
830struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
831 bool is_vf, bool is_netdev);
38e00438 832#ifdef I40E_FCOE
16e5cc64
JF
833int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
834 struct tc_to_netdev *tc);
38e00438
VD
835void i40e_netpoll(struct net_device *netdev);
836int i40e_fcoe_enable(struct net_device *netdev);
837int i40e_fcoe_disable(struct net_device *netdev);
838int i40e_fcoe_vsi_init(struct i40e_vsi *vsi, struct i40e_vsi_context *ctxt);
839u8 i40e_get_fcoe_tc_map(struct i40e_pf *pf);
840void i40e_fcoe_config_netdev(struct net_device *netdev, struct i40e_vsi *vsi);
841void i40e_fcoe_vsi_setup(struct i40e_pf *pf);
21364bcf 842void i40e_init_pf_fcoe(struct i40e_pf *pf);
38e00438
VD
843int i40e_fcoe_setup_ddp_resources(struct i40e_vsi *vsi);
844void i40e_fcoe_free_ddp_resources(struct i40e_vsi *vsi);
845int i40e_fcoe_handle_offload(struct i40e_ring *rx_ring,
846 union i40e_rx_desc *rx_desc,
847 struct sk_buff *skb);
848void i40e_fcoe_handle_status(struct i40e_ring *rx_ring,
849 union i40e_rx_desc *rx_desc, u8 prog_id);
850#endif /* I40E_FCOE */
7daa6bf3 851void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
4e3b35b0
NP
852#ifdef CONFIG_I40E_DCB
853void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
750fcbcf 854 struct i40e_dcbx_config *old_cfg,
4e3b35b0
NP
855 struct i40e_dcbx_config *new_cfg);
856void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
857void i40e_dcbnl_setup(struct i40e_vsi *vsi);
858bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
859 struct i40e_dcbx_config *old_cfg,
860 struct i40e_dcbx_config *new_cfg);
861#endif /* CONFIG_I40E_DCB */
beb0dff1
JK
862void i40e_ptp_rx_hang(struct i40e_vsi *vsi);
863void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
864void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
865void i40e_ptp_set_increment(struct i40e_pf *pf);
866int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
867int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
868void i40e_ptp_init(struct i40e_pf *pf);
869void i40e_ptp_stop(struct i40e_pf *pf);
51616018 870int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
f4492db1
GR
871i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf);
872i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf);
873i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf);
c156f856 874void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
7daa6bf3 875#endif /* _I40E_H_ */
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