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i40e: For VF reset (VFR and VFLR) add some more delay
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_adminq.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_status.h"
28#include "i40e_type.h"
29#include "i40e_register.h"
30#include "i40e_adminq.h"
31#include "i40e_prototype.h"
32
af28eec9
SH		 33static void i40e_resume_aq(struct i40e_hw *hw);
34
c9296ad2
SN		 35/**
36 * i40e_is_nvm_update_op - return true if this is an NVM update operation
37 * @desc: API request descriptor
38 **/
39static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
40{
cd552cb4
SN		 41 return (desc->opcode == cpu_to_le16(i40e_aqc_opc_nvm_erase)) ||
42 (desc->opcode == cpu_to_le16(i40e_aqc_opc_nvm_update));
c9296ad2
SN		 43}
44
56a62fc8
JB		 45/**
46 * i40e_adminq_init_regs - Initialize AdminQ registers
47 * @hw: pointer to the hardware structure
48 *
49 * This assumes the alloc_asq and alloc_arq functions have already been called
50 **/
51static void i40e_adminq_init_regs(struct i40e_hw *hw)
52{
53 /* set head and tail registers in our local struct */
e7f2e4b9 54 if (i40e_is_vf(hw)) {
56a62fc8
JB		 55 hw->aq.asq.tail = I40E_VF_ATQT1;
56 hw->aq.asq.head = I40E_VF_ATQH1;
17e6a845 57 hw->aq.asq.len = I40E_VF_ATQLEN1;
87dc3464
SN		 58 hw->aq.asq.bal = I40E_VF_ATQBAL1;
59 hw->aq.asq.bah = I40E_VF_ATQBAH1;
56a62fc8
JB		 60 hw->aq.arq.tail = I40E_VF_ARQT1;
61 hw->aq.arq.head = I40E_VF_ARQH1;
17e6a845 62 hw->aq.arq.len = I40E_VF_ARQLEN1;
87dc3464
SN		 63 hw->aq.arq.bal = I40E_VF_ARQBAL1;
64 hw->aq.arq.bah = I40E_VF_ARQBAH1;
56a62fc8
JB		 65 } else {
66 hw->aq.asq.tail = I40E_PF_ATQT;
67 hw->aq.asq.head = I40E_PF_ATQH;
17e6a845 68 hw->aq.asq.len = I40E_PF_ATQLEN;
87dc3464
SN		 69 hw->aq.asq.bal = I40E_PF_ATQBAL;
70 hw->aq.asq.bah = I40E_PF_ATQBAH;
56a62fc8
JB		 71 hw->aq.arq.tail = I40E_PF_ARQT;
72 hw->aq.arq.head = I40E_PF_ARQH;
17e6a845 73 hw->aq.arq.len = I40E_PF_ARQLEN;
87dc3464
SN		 74 hw->aq.arq.bal = I40E_PF_ARQBAL;
75 hw->aq.arq.bah = I40E_PF_ARQBAH;
56a62fc8
JB		 76 }
77}
78
79/**
80 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
81 * @hw: pointer to the hardware structure
82 **/
83static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
84{
85 i40e_status ret_code;
56a62fc8 86
90bb776a 87 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
56a62fc8
JB		 88 i40e_mem_atq_ring,
89 (hw->aq.num_asq_entries *
90 sizeof(struct i40e_aq_desc)),
91 I40E_ADMINQ_DESC_ALIGNMENT);
92 if (ret_code)
93 return ret_code;
94
90bb776a 95 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
56a62fc8
JB		 96 (hw->aq.num_asq_entries *
97 sizeof(struct i40e_asq_cmd_details)));
98 if (ret_code) {
90bb776a 99 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
56a62fc8
JB		 100 return ret_code;
101 }
102
56a62fc8
JB		 103 return ret_code;
104}
105
106/**
107 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
108 * @hw: pointer to the hardware structure
109 **/
110static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
111{
112 i40e_status ret_code;
113
90bb776a 114 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
56a62fc8
JB		 115 i40e_mem_arq_ring,
116 (hw->aq.num_arq_entries *
117 sizeof(struct i40e_aq_desc)),
118 I40E_ADMINQ_DESC_ALIGNMENT);
56a62fc8
JB		 119
120 return ret_code;
121}
122
123/**
124 * i40e_free_adminq_asq - Free Admin Queue send rings
125 * @hw: pointer to the hardware structure
126 *
127 * This assumes the posted send buffers have already been cleaned
128 * and de-allocated
129 **/
130static void i40e_free_adminq_asq(struct i40e_hw *hw)
131{
90bb776a 132 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
56a62fc8
JB		 133}
134
135/**
136 * i40e_free_adminq_arq - Free Admin Queue receive rings
137 * @hw: pointer to the hardware structure
138 *
139 * This assumes the posted receive buffers have already been cleaned
140 * and de-allocated
141 **/
142static void i40e_free_adminq_arq(struct i40e_hw *hw)
143{
90bb776a 144 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
56a62fc8
JB		 145}
146
147/**
148 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
98d44381 149 * @hw: pointer to the hardware structure
56a62fc8
JB		 150 **/
151static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
152{
153 i40e_status ret_code;
154 struct i40e_aq_desc *desc;
56a62fc8
JB		 155 struct i40e_dma_mem *bi;
156 int i;
157
158 /* We'll be allocating the buffer info memory first, then we can
159 * allocate the mapped buffers for the event processing
160 */
161
162 /* buffer_info structures do not need alignment */
90bb776a
DC		 163 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
164 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
56a62fc8
JB		 165 if (ret_code)
166 goto alloc_arq_bufs;
90bb776a 167 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
56a62fc8
JB		 168
169 /* allocate the mapped buffers */
170 for (i = 0; i < hw->aq.num_arq_entries; i++) {
171 bi = &hw->aq.arq.r.arq_bi[i];
172 ret_code = i40e_allocate_dma_mem(hw, bi,
173 i40e_mem_arq_buf,
174 hw->aq.arq_buf_size,
175 I40E_ADMINQ_DESC_ALIGNMENT);
176 if (ret_code)
177 goto unwind_alloc_arq_bufs;
178
179 /* now configure the descriptors for use */
180 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
181
182 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
183 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
184 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
185 desc->opcode = 0;
186 /* This is in accordance with Admin queue design, there is no
187 * register for buffer size configuration
188 */
189 desc->datalen = cpu_to_le16((u16)bi->size);
190 desc->retval = 0;
191 desc->cookie_high = 0;
192 desc->cookie_low = 0;
193 desc->params.external.addr_high =
194 cpu_to_le32(upper_32_bits(bi->pa));
195 desc->params.external.addr_low =
196 cpu_to_le32(lower_32_bits(bi->pa));
197 desc->params.external.param0 = 0;
198 desc->params.external.param1 = 0;
199 }
200
201alloc_arq_bufs:
202 return ret_code;
203
204unwind_alloc_arq_bufs:
205 /* don't try to free the one that failed... */
206 i--;
207 for (; i >= 0; i--)
208 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
90bb776a 209 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
56a62fc8
JB		 210
211 return ret_code;
212}
213
214/**
215 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
98d44381 216 * @hw: pointer to the hardware structure
56a62fc8
JB		 217 **/
218static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
219{
220 i40e_status ret_code;
56a62fc8
JB		 221 struct i40e_dma_mem *bi;
222 int i;
223
224 /* No mapped memory needed yet, just the buffer info structures */
90bb776a
DC		 225 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
226 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
56a62fc8
JB		 227 if (ret_code)
228 goto alloc_asq_bufs;
90bb776a 229 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
56a62fc8
JB		 230
231 /* allocate the mapped buffers */
232 for (i = 0; i < hw->aq.num_asq_entries; i++) {
233 bi = &hw->aq.asq.r.asq_bi[i];
234 ret_code = i40e_allocate_dma_mem(hw, bi,
235 i40e_mem_asq_buf,
236 hw->aq.asq_buf_size,
237 I40E_ADMINQ_DESC_ALIGNMENT);
238 if (ret_code)
239 goto unwind_alloc_asq_bufs;
240 }
241alloc_asq_bufs:
242 return ret_code;
243
244unwind_alloc_asq_bufs:
245 /* don't try to free the one that failed... */
246 i--;
247 for (; i >= 0; i--)
248 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
90bb776a 249 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
56a62fc8
JB		 250
251 return ret_code;
252}
253
254/**
255 * i40e_free_arq_bufs - Free receive queue buffer info elements
98d44381 256 * @hw: pointer to the hardware structure
56a62fc8
JB		 257 **/
258static void i40e_free_arq_bufs(struct i40e_hw *hw)
259{
56a62fc8
JB		 260 int i;
261
90bb776a 262 /* free descriptors */
56a62fc8
JB		 263 for (i = 0; i < hw->aq.num_arq_entries; i++)
264 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
265
90bb776a
DC		 266 /* free the descriptor memory */
267 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
268
269 /* free the dma header */
270 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
56a62fc8
JB		 271}
272
273/**
274 * i40e_free_asq_bufs - Free send queue buffer info elements
98d44381 275 * @hw: pointer to the hardware structure
56a62fc8
JB		 276 **/
277static void i40e_free_asq_bufs(struct i40e_hw *hw)
278{
56a62fc8
JB		 279 int i;
280
281 /* only unmap if the address is non-NULL */
282 for (i = 0; i < hw->aq.num_asq_entries; i++)
283 if (hw->aq.asq.r.asq_bi[i].pa)
284 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
285
90bb776a
DC		 286 /* free the buffer info list */
287 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
288
289 /* free the descriptor memory */
290 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
291
292 /* free the dma header */
293 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
56a62fc8
JB		 294}
295
296/**
297 * i40e_config_asq_regs - configure ASQ registers
98d44381 298 * @hw: pointer to the hardware structure
56a62fc8
JB		 299 *
300 * Configure base address and length registers for the transmit queue
301 **/
e03af1e1 302static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
56a62fc8 303{
e03af1e1
KK		 304 i40e_status ret_code = 0;
305 u32 reg = 0;
306
80a977e7
MK		 307 /* Clear Head and Tail */
308 wr32(hw, hw->aq.asq.head, 0);
309 wr32(hw, hw->aq.asq.tail, 0);
310
87dc3464
SN		 311 /* set starting point */
312 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
313 I40E_PF_ATQLEN_ATQENABLE_MASK));
314 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
315 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
e03af1e1
KK		 316
317 /* Check one register to verify that config was applied */
87dc3464 318 reg = rd32(hw, hw->aq.asq.bal);
e03af1e1
KK		 319 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
320 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
321
322 return ret_code;
56a62fc8
JB		 323}
324
325/**
326 * i40e_config_arq_regs - ARQ register configuration
98d44381 327 * @hw: pointer to the hardware structure
56a62fc8
JB		 328 *
329 * Configure base address and length registers for the receive (event queue)
330 **/
e03af1e1 331static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
56a62fc8 332{
e03af1e1
KK		 333 i40e_status ret_code = 0;
334 u32 reg = 0;
335
80a977e7
MK		 336 /* Clear Head and Tail */
337 wr32(hw, hw->aq.arq.head, 0);
338 wr32(hw, hw->aq.arq.tail, 0);
339
87dc3464
SN		 340 /* set starting point */
341 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
342 I40E_PF_ARQLEN_ARQENABLE_MASK));
343 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
344 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
56a62fc8
JB		 345
346 /* Update tail in the HW to post pre-allocated buffers */
347 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
e03af1e1
KK		 348
349 /* Check one register to verify that config was applied */
87dc3464 350 reg = rd32(hw, hw->aq.arq.bal);
e03af1e1
KK		 351 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
352 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
353
354 return ret_code;
56a62fc8
JB		 355}
356
357/**
358 * i40e_init_asq - main initialization routine for ASQ
98d44381 359 * @hw: pointer to the hardware structure
56a62fc8
JB		 360 *
361 * This is the main initialization routine for the Admin Send Queue
362 * Prior to calling this function, drivers *MUST* set the following fields
363 * in the hw->aq structure:
364 * - hw->aq.num_asq_entries
365 * - hw->aq.arq_buf_size
366 *
367 * Do *NOT* hold the lock when calling this as the memory allocation routines
368 * called are not going to be atomic context safe
369 **/
370static i40e_status i40e_init_asq(struct i40e_hw *hw)
371{
372 i40e_status ret_code = 0;
373
374 if (hw->aq.asq.count > 0) {
375 /* queue already initialized */
376 ret_code = I40E_ERR_NOT_READY;
377 goto init_adminq_exit;
378 }
379
380 /* verify input for valid configuration */
381 if ((hw->aq.num_asq_entries == 0) ||
382 (hw->aq.asq_buf_size == 0)) {
383 ret_code = I40E_ERR_CONFIG;
384 goto init_adminq_exit;
385 }
386
387 hw->aq.asq.next_to_use = 0;
388 hw->aq.asq.next_to_clean = 0;
389 hw->aq.asq.count = hw->aq.num_asq_entries;
390
391 /* allocate the ring memory */
392 ret_code = i40e_alloc_adminq_asq_ring(hw);
393 if (ret_code)
394 goto init_adminq_exit;
395
396 /* allocate buffers in the rings */
397 ret_code = i40e_alloc_asq_bufs(hw);
398 if (ret_code)
399 goto init_adminq_free_rings;
400
401 /* initialize base registers */
e03af1e1
KK		 402 ret_code = i40e_config_asq_regs(hw);
403 if (ret_code)
404 goto init_adminq_free_rings;
56a62fc8
JB		 405
406 /* success! */
407 goto init_adminq_exit;
408
409init_adminq_free_rings:
410 i40e_free_adminq_asq(hw);
411
412init_adminq_exit:
413 return ret_code;
414}
415
416/**
417 * i40e_init_arq - initialize ARQ
98d44381 418 * @hw: pointer to the hardware structure
56a62fc8
JB		 419 *
420 * The main initialization routine for the Admin Receive (Event) Queue.
421 * Prior to calling this function, drivers *MUST* set the following fields
422 * in the hw->aq structure:
423 * - hw->aq.num_asq_entries
424 * - hw->aq.arq_buf_size
425 *
426 * Do *NOT* hold the lock when calling this as the memory allocation routines
427 * called are not going to be atomic context safe
428 **/
429static i40e_status i40e_init_arq(struct i40e_hw *hw)
430{
431 i40e_status ret_code = 0;
432
433 if (hw->aq.arq.count > 0) {
434 /* queue already initialized */
435 ret_code = I40E_ERR_NOT_READY;
436 goto init_adminq_exit;
437 }
438
439 /* verify input for valid configuration */
440 if ((hw->aq.num_arq_entries == 0) ||
441 (hw->aq.arq_buf_size == 0)) {
442 ret_code = I40E_ERR_CONFIG;
443 goto init_adminq_exit;
444 }
445
446 hw->aq.arq.next_to_use = 0;
447 hw->aq.arq.next_to_clean = 0;
448 hw->aq.arq.count = hw->aq.num_arq_entries;
449
450 /* allocate the ring memory */
451 ret_code = i40e_alloc_adminq_arq_ring(hw);
452 if (ret_code)
453 goto init_adminq_exit;
454
455 /* allocate buffers in the rings */
456 ret_code = i40e_alloc_arq_bufs(hw);
457 if (ret_code)
458 goto init_adminq_free_rings;
459
460 /* initialize base registers */
e03af1e1
KK		 461 ret_code = i40e_config_arq_regs(hw);
462 if (ret_code)
463 goto init_adminq_free_rings;
56a62fc8
JB		 464
465 /* success! */
466 goto init_adminq_exit;
467
468init_adminq_free_rings:
469 i40e_free_adminq_arq(hw);
470
471init_adminq_exit:
472 return ret_code;
473}
474
475/**
476 * i40e_shutdown_asq - shutdown the ASQ
98d44381 477 * @hw: pointer to the hardware structure
56a62fc8
JB		 478 *
479 * The main shutdown routine for the Admin Send Queue
480 **/
481static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
482{
483 i40e_status ret_code = 0;
484
485 if (hw->aq.asq.count == 0)
486 return I40E_ERR_NOT_READY;
487
488 /* Stop firmware AdminQ processing */
17e6a845
SN		 489 wr32(hw, hw->aq.asq.head, 0);
490 wr32(hw, hw->aq.asq.tail, 0);
491 wr32(hw, hw->aq.asq.len, 0);
4346940b
SN		 492 wr32(hw, hw->aq.asq.bal, 0);
493 wr32(hw, hw->aq.asq.bah, 0);
56a62fc8
JB		 494
495 /* make sure lock is available */
496 mutex_lock(&hw->aq.asq_mutex);
497
498 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
499
500 /* free ring buffers */
501 i40e_free_asq_bufs(hw);
56a62fc8
JB		 502
503 mutex_unlock(&hw->aq.asq_mutex);
504
505 return ret_code;
506}
507
508/**
509 * i40e_shutdown_arq - shutdown ARQ
98d44381 510 * @hw: pointer to the hardware structure
56a62fc8
JB		 511 *
512 * The main shutdown routine for the Admin Receive Queue
513 **/
514static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
515{
516 i40e_status ret_code = 0;
517
518 if (hw->aq.arq.count == 0)
519 return I40E_ERR_NOT_READY;
520
521 /* Stop firmware AdminQ processing */
17e6a845
SN		 522 wr32(hw, hw->aq.arq.head, 0);
523 wr32(hw, hw->aq.arq.tail, 0);
524 wr32(hw, hw->aq.arq.len, 0);
4346940b
SN		 525 wr32(hw, hw->aq.arq.bal, 0);
526 wr32(hw, hw->aq.arq.bah, 0);
56a62fc8
JB		 527
528 /* make sure lock is available */
529 mutex_lock(&hw->aq.arq_mutex);
530
531 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
532
533 /* free ring buffers */
534 i40e_free_arq_bufs(hw);
56a62fc8
JB		 535
536 mutex_unlock(&hw->aq.arq_mutex);
537
538 return ret_code;
539}
540
541/**
542 * i40e_init_adminq - main initialization routine for Admin Queue
98d44381 543 * @hw: pointer to the hardware structure
56a62fc8
JB		 544 *
545 * Prior to calling this function, drivers *MUST* set the following fields
546 * in the hw->aq structure:
547 * - hw->aq.num_asq_entries
548 * - hw->aq.num_arq_entries
549 * - hw->aq.arq_buf_size
550 * - hw->aq.asq_buf_size
551 **/
552i40e_status i40e_init_adminq(struct i40e_hw *hw)
553{
56a62fc8 554 i40e_status ret_code;
d4946cf5
SN		 555 u16 eetrack_lo, eetrack_hi;
556 int retry = 0;
56a62fc8
JB		 557
558 /* verify input for valid configuration */
559 if ((hw->aq.num_arq_entries == 0) ||
560 (hw->aq.num_asq_entries == 0) ||
561 (hw->aq.arq_buf_size == 0) ||
562 (hw->aq.asq_buf_size == 0)) {
563 ret_code = I40E_ERR_CONFIG;
564 goto init_adminq_exit;
565 }
566
567 /* initialize locks */
568 mutex_init(&hw->aq.asq_mutex);
569 mutex_init(&hw->aq.arq_mutex);
570
571 /* Set up register offsets */
572 i40e_adminq_init_regs(hw);
573
09c4e56b
KK		 574 /* setup ASQ command write back timeout */
575 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
576
56a62fc8
JB		 577 /* allocate the ASQ */
578 ret_code = i40e_init_asq(hw);
579 if (ret_code)
580 goto init_adminq_destroy_locks;
581
582 /* allocate the ARQ */
583 ret_code = i40e_init_arq(hw);
584 if (ret_code)
585 goto init_adminq_free_asq;
586
d4946cf5
SN		 587 /* There are some cases where the firmware may not be quite ready
588 * for AdminQ operations, so we retry the AdminQ setup a few times
589 * if we see timeouts in this first AQ call.
590 */
591 do {
592 ret_code = i40e_aq_get_firmware_version(hw,
593 &hw->aq.fw_maj_ver,
594 &hw->aq.fw_min_ver,
7edf810c 595 &hw->aq.fw_build,
d4946cf5
SN		 596 &hw->aq.api_maj_ver,
597 &hw->aq.api_min_ver,
598 NULL);
599 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
600 break;
601 retry++;
602 msleep(100);
603 i40e_resume_aq(hw);
604 } while (retry < 10);
605 if (ret_code != I40E_SUCCESS)
56a62fc8
JB		 606 goto init_adminq_free_arq;
607
981b7545 608 /* get the NVM version info */
4f651a5b
SN		 609 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,
610 &hw->nvm.version);
56a62fc8
JB		 611 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
612 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
613 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
614
7e612411 615 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
981b7545
SN		 616 ret_code = I40E_ERR_FIRMWARE_API_VERSION;
617 goto init_adminq_free_arq;
618 }
619
ff2ff3b4
SN		 620 /* pre-emptive resource lock release */
621 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
0f52958b
SN		 622 hw->aq.nvm_release_on_done = false;
623 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
ff2ff3b4 624
56a62fc8
JB		 625 ret_code = i40e_aq_set_hmc_resource_profile(hw,
626 I40E_HMC_PROFILE_DEFAULT,
627 0,
628 NULL);
629 ret_code = 0;
630
631 /* success! */
632 goto init_adminq_exit;
633
634init_adminq_free_arq:
635 i40e_shutdown_arq(hw);
636init_adminq_free_asq:
637 i40e_shutdown_asq(hw);
638init_adminq_destroy_locks:
639
640init_adminq_exit:
641 return ret_code;
642}
643
644/**
645 * i40e_shutdown_adminq - shutdown routine for the Admin Queue
98d44381 646 * @hw: pointer to the hardware structure
56a62fc8
JB		 647 **/
648i40e_status i40e_shutdown_adminq(struct i40e_hw *hw)
649{
650 i40e_status ret_code = 0;
651
e1860d8f
ASJ		 652 if (i40e_check_asq_alive(hw))
653 i40e_aq_queue_shutdown(hw, true);
654
56a62fc8
JB		 655 i40e_shutdown_asq(hw);
656 i40e_shutdown_arq(hw);
657
658 /* destroy the locks */
659
660 return ret_code;
661}
662
663/**
664 * i40e_clean_asq - cleans Admin send queue
98d44381 665 * @hw: pointer to the hardware structure
56a62fc8
JB		 666 *
667 * returns the number of free desc
668 **/
669static u16 i40e_clean_asq(struct i40e_hw *hw)
670{
671 struct i40e_adminq_ring *asq = &(hw->aq.asq);
672 struct i40e_asq_cmd_details *details;
673 u16 ntc = asq->next_to_clean;
674 struct i40e_aq_desc desc_cb;
675 struct i40e_aq_desc *desc;
676
677 desc = I40E_ADMINQ_DESC(*asq, ntc);
678 details = I40E_ADMINQ_DETAILS(*asq, ntc);
679 while (rd32(hw, hw->aq.asq.head) != ntc) {
80a977e7
MK		 680 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
681 "%s: ntc %d head %d.\n", __func__, ntc,
682 rd32(hw, hw->aq.asq.head));
683
56a62fc8
JB		 684 if (details->callback) {
685 I40E_ADMINQ_CALLBACK cb_func =
686 (I40E_ADMINQ_CALLBACK)details->callback;
687 desc_cb = *desc;
688 cb_func(hw, &desc_cb);
689 }
a63fa1cd
MW		 690 memset(desc, 0, sizeof(*desc));
691 memset(details, 0, sizeof(*details));
56a62fc8
JB		 692 ntc++;
693 if (ntc == asq->count)
694 ntc = 0;
695 desc = I40E_ADMINQ_DESC(*asq, ntc);
696 details = I40E_ADMINQ_DETAILS(*asq, ntc);
697 }
698
699 asq->next_to_clean = ntc;
700
701 return I40E_DESC_UNUSED(asq);
702}
703
704/**
705 * i40e_asq_done - check if FW has processed the Admin Send Queue
706 * @hw: pointer to the hw struct
707 *
708 * Returns true if the firmware has processed all descriptors on the
709 * admin send queue. Returns false if there are still requests pending.
710 **/
af28eec9 711static bool i40e_asq_done(struct i40e_hw *hw)
56a62fc8
JB		 712{
713 /* AQ designers suggest use of head for better
714 * timing reliability than DD bit
715 */
922680b9 716 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
56a62fc8
JB		 717
718}
719
720/**
721 * i40e_asq_send_command - send command to Admin Queue
722 * @hw: pointer to the hw struct
723 * @desc: prefilled descriptor describing the command (non DMA mem)
724 * @buff: buffer to use for indirect commands
725 * @buff_size: size of buffer for indirect commands
922680b9 726 * @cmd_details: pointer to command details structure
56a62fc8
JB		 727 *
728 * This is the main send command driver routine for the Admin Queue send
729 * queue. It runs the queue, cleans the queue, etc
730 **/
731i40e_status i40e_asq_send_command(struct i40e_hw *hw,
732 struct i40e_aq_desc *desc,
733 void *buff, /* can be NULL */
734 u16 buff_size,
735 struct i40e_asq_cmd_details *cmd_details)
736{
737 i40e_status status = 0;
738 struct i40e_dma_mem *dma_buff = NULL;
739 struct i40e_asq_cmd_details *details;
740 struct i40e_aq_desc *desc_on_ring;
741 bool cmd_completed = false;
742 u16 retval = 0;
80a977e7
MK		 743 u32 val = 0;
744
745 val = rd32(hw, hw->aq.asq.head);
746 if (val >= hw->aq.num_asq_entries) {
747 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
748 "AQTX: head overrun at %d\n", val);
749 status = I40E_ERR_QUEUE_EMPTY;
750 goto asq_send_command_exit;
751 }
56a62fc8
JB		 752
753 if (hw->aq.asq.count == 0) {
754 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
755 "AQTX: Admin queue not initialized.\n");
756 status = I40E_ERR_QUEUE_EMPTY;
757 goto asq_send_command_exit;
758 }
759
760 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
761 if (cmd_details) {
d7595a22 762 *details = *cmd_details;
56a62fc8
JB		 763
764 /* If the cmd_details are defined copy the cookie. The
765 * cpu_to_le32 is not needed here because the data is ignored
766 * by the FW, only used by the driver
767 */
768 if (details->cookie) {
769 desc->cookie_high =
770 cpu_to_le32(upper_32_bits(details->cookie));
771 desc->cookie_low =
772 cpu_to_le32(lower_32_bits(details->cookie));
773 }
774 } else {
775 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
776 }
777
778 /* clear requested flags and then set additional flags if defined */
779 desc->flags &= ~cpu_to_le16(details->flags_dis);
780 desc->flags |= cpu_to_le16(details->flags_ena);
781
782 mutex_lock(&hw->aq.asq_mutex);
783
784 if (buff_size > hw->aq.asq_buf_size) {
785 i40e_debug(hw,
786 I40E_DEBUG_AQ_MESSAGE,
787 "AQTX: Invalid buffer size: %d.\n",
788 buff_size);
789 status = I40E_ERR_INVALID_SIZE;
790 goto asq_send_command_error;
791 }
792
793 if (details->postpone && !details->async) {
794 i40e_debug(hw,
795 I40E_DEBUG_AQ_MESSAGE,
796 "AQTX: Async flag not set along with postpone flag");
797 status = I40E_ERR_PARAM;
798 goto asq_send_command_error;
799 }
800
801 /* call clean and check queue available function to reclaim the
802 * descriptors that were processed by FW, the function returns the
803 * number of desc available
804 */
805 /* the clean function called here could be called in a separate thread
806 * in case of asynchronous completions
807 */
808 if (i40e_clean_asq(hw) == 0) {
809 i40e_debug(hw,
810 I40E_DEBUG_AQ_MESSAGE,
811 "AQTX: Error queue is full.\n");
812 status = I40E_ERR_ADMIN_QUEUE_FULL;
813 goto asq_send_command_error;
814 }
815
816 /* initialize the temp desc pointer with the right desc */
817 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
818
819 /* if the desc is available copy the temp desc to the right place */
d7595a22 820 *desc_on_ring = *desc;
56a62fc8
JB		 821
822 /* if buff is not NULL assume indirect command */
823 if (buff != NULL) {
824 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
825 /* copy the user buff into the respective DMA buff */
826 memcpy(dma_buff->va, buff, buff_size);
827 desc_on_ring->datalen = cpu_to_le16(buff_size);
828
829 /* Update the address values in the desc with the pa value
830 * for respective buffer
831 */
832 desc_on_ring->params.external.addr_high =
833 cpu_to_le32(upper_32_bits(dma_buff->pa));
834 desc_on_ring->params.external.addr_low =
835 cpu_to_le32(lower_32_bits(dma_buff->pa));
836 }
837
838 /* bump the tail */
66d90e7d 839 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
f905dd62
SN		 840 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
841 buff, buff_size);
56a62fc8
JB		 842 (hw->aq.asq.next_to_use)++;
843 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
844 hw->aq.asq.next_to_use = 0;
845 if (!details->postpone)
846 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
847
848 /* if cmd_details are not defined or async flag is not set,
849 * we need to wait for desc write back
850 */
851 if (!details->async && !details->postpone) {
852 u32 total_delay = 0;
56a62fc8
JB		 853
854 do {
855 /* AQ designers suggest use of head for better
856 * timing reliability than DD bit
857 */
858 if (i40e_asq_done(hw))
859 break;
0db4e162
KK		 860 usleep_range(1000, 2000);
861 total_delay++;
ec9a7db7 862 } while (total_delay < hw->aq.asq_cmd_timeout);
56a62fc8
JB		 863 }
864
865 /* if ready, copy the desc back to temp */
866 if (i40e_asq_done(hw)) {
d7595a22 867 *desc = *desc_on_ring;
56a62fc8
JB		 868 if (buff != NULL)
869 memcpy(buff, dma_buff->va, buff_size);
870 retval = le16_to_cpu(desc->retval);
871 if (retval != 0) {
872 i40e_debug(hw,
873 I40E_DEBUG_AQ_MESSAGE,
874 "AQTX: Command completed with error 0x%X.\n",
875 retval);
66d90e7d 876
56a62fc8
JB		 877 /* strip off FW internal code */
878 retval &= 0xff;
879 }
880 cmd_completed = true;
881 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
882 status = 0;
883 else
884 status = I40E_ERR_ADMIN_QUEUE_ERROR;
885 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
886 }
887
e3effd73
SN		 888 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
889 "AQTX: desc and buffer writeback:\n");
f905dd62 890 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
66d90e7d 891
56a62fc8
JB		 892 /* update the error if time out occurred */
893 if ((!cmd_completed) &&
894 (!details->async && !details->postpone)) {
895 i40e_debug(hw,
896 I40E_DEBUG_AQ_MESSAGE,
897 "AQTX: Writeback timeout.\n");
898 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
899 }
900
901asq_send_command_error:
902 mutex_unlock(&hw->aq.asq_mutex);
903asq_send_command_exit:
904 return status;
905}
906
907/**
908 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
909 * @desc: pointer to the temp descriptor (non DMA mem)
910 * @opcode: the opcode can be used to decide which flags to turn off or on
911 *
912 * Fill the desc with default values
913 **/
914void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
915 u16 opcode)
916{
917 /* zero out the desc */
918 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
919 desc->opcode = cpu_to_le16(opcode);
ab954cba 920 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
56a62fc8
JB		 921}
922
923/**
924 * i40e_clean_arq_element
925 * @hw: pointer to the hw struct
926 * @e: event info from the receive descriptor, includes any buffers
927 * @pending: number of events that could be left to process
928 *
929 * This function cleans one Admin Receive Queue element and returns
930 * the contents through e. It can also return how many events are
931 * left to process through 'pending'
932 **/
933i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
934 struct i40e_arq_event_info *e,
935 u16 *pending)
936{
937 i40e_status ret_code = 0;
938 u16 ntc = hw->aq.arq.next_to_clean;
939 struct i40e_aq_desc *desc;
940 struct i40e_dma_mem *bi;
941 u16 desc_idx;
942 u16 datalen;
943 u16 flags;
944 u16 ntu;
945
946 /* take the lock before we start messing with the ring */
947 mutex_lock(&hw->aq.arq_mutex);
948
949 /* set next_to_use to head */
950 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
951 if (ntu == ntc) {
952 /* nothing to do - shouldn't need to update ring's values */
56a62fc8
JB		 953 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
954 goto clean_arq_element_out;
955 }
956
957 /* now clean the next descriptor */
958 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
959 desc_idx = ntc;
56a62fc8
JB		 960
961 flags = le16_to_cpu(desc->flags);
962 if (flags & I40E_AQ_FLAG_ERR) {
963 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
964 hw->aq.arq_last_status =
965 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
966 i40e_debug(hw,
967 I40E_DEBUG_AQ_MESSAGE,
968 "AQRX: Event received with error 0x%X.\n",
969 hw->aq.arq_last_status);
56a62fc8
JB		 970 }
971
77813d0a
KK		 972 e->desc = *desc;
973 datalen = le16_to_cpu(desc->datalen);
1001dc37
MW		 974 e->msg_len = min(datalen, e->buf_len);
975 if (e->msg_buf != NULL && (e->msg_len != 0))
77813d0a 976 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
1001dc37 977 e->msg_len);
77813d0a 978
66d90e7d 979 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
f905dd62
SN		 980 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
981 hw->aq.arq_buf_size);
66d90e7d 982
56a62fc8
JB		 983 /* Restore the original datalen and buffer address in the desc,
984 * FW updates datalen to indicate the event message
985 * size
986 */
987 bi = &hw->aq.arq.r.arq_bi[ntc];
90077773
MW		 988 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
989
990 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
991 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
992 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
56a62fc8
JB		 993 desc->datalen = cpu_to_le16((u16)bi->size);
994 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
995 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
996
997 /* set tail = the last cleaned desc index. */
998 wr32(hw, hw->aq.arq.tail, ntc);
999 /* ntc is updated to tail + 1 */
1000 ntc++;
1001 if (ntc == hw->aq.num_arq_entries)
1002 ntc = 0;
1003 hw->aq.arq.next_to_clean = ntc;
1004 hw->aq.arq.next_to_use = ntu;
1005
1006clean_arq_element_out:
1007 /* Set pending if needed, unlock and return */
1008 if (pending != NULL)
1009 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
1010 mutex_unlock(&hw->aq.arq_mutex);
1011
cd552cb4 1012 if (i40e_is_nvm_update_op(&e->desc)) {
cd552cb4
SN		 1013 if (hw->aq.nvm_release_on_done) {
1014 i40e_release_nvm(hw);
1015 hw->aq.nvm_release_on_done = false;
1016 }
1017 }
1018
56a62fc8
JB		 1019 return ret_code;
1020}
1021
af28eec9 1022static void i40e_resume_aq(struct i40e_hw *hw)
56a62fc8 1023{
56a62fc8
JB		 1024 /* Registers are reset after PF reset */
1025 hw->aq.asq.next_to_use = 0;
1026 hw->aq.asq.next_to_clean = 0;
1027
1028 i40e_config_asq_regs(hw);
56a62fc8
JB		 1029
1030 hw->aq.arq.next_to_use = 0;
1031 hw->aq.arq.next_to_clean = 0;
1032
1033 i40e_config_arq_regs(hw);
56a62fc8 1034}
Linux kernel - Deliverables
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