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i40e/i40evf: Bump i40e to 1.3.46 and i40evf to 1.3.33
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
f1abd7db 4 * Copyright(c) 2013 - 2015 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e
SN		 46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
ab60085e
SN		 50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
5960d33f 53 case I40E_DEV_ID_10G_BASE_T:
bc5166b9 54 case I40E_DEV_ID_10G_BASE_T4:
ae24b409 55 case I40E_DEV_ID_20G_KR2:
48a3b512 56 case I40E_DEV_ID_20G_KR2_A:
56a62fc8
JB		 57 hw->mac.type = I40E_MAC_XL710;
58 break;
87e6c1d7
ASJ		 59 case I40E_DEV_ID_SFP_X722:
60 case I40E_DEV_ID_1G_BASE_T_X722:
61 case I40E_DEV_ID_10G_BASE_T_X722:
62 hw->mac.type = I40E_MAC_X722;
63 break;
64 case I40E_DEV_ID_X722_VF:
65 case I40E_DEV_ID_X722_VF_HV:
66 hw->mac.type = I40E_MAC_X722_VF;
67 break;
ab60085e
SN		 68 case I40E_DEV_ID_VF:
69 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 70 hw->mac.type = I40E_MAC_VF;
71 break;
72 default:
73 hw->mac.type = I40E_MAC_GENERIC;
74 break;
75 }
76 } else {
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
78 }
79
80 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
82 return status;
83}
84
f1c7e72e
SN		 85/**
86 * i40e_aq_str - convert AQ err code to a string
87 * @hw: pointer to the HW structure
88 * @aq_err: the AQ error code to convert
89 **/
4e68adfe 90const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
f1c7e72e
SN		 91{
92 switch (aq_err) {
93 case I40E_AQ_RC_OK:
94 return "OK";
95 case I40E_AQ_RC_EPERM:
96 return "I40E_AQ_RC_EPERM";
97 case I40E_AQ_RC_ENOENT:
98 return "I40E_AQ_RC_ENOENT";
99 case I40E_AQ_RC_ESRCH:
100 return "I40E_AQ_RC_ESRCH";
101 case I40E_AQ_RC_EINTR:
102 return "I40E_AQ_RC_EINTR";
103 case I40E_AQ_RC_EIO:
104 return "I40E_AQ_RC_EIO";
105 case I40E_AQ_RC_ENXIO:
106 return "I40E_AQ_RC_ENXIO";
107 case I40E_AQ_RC_E2BIG:
108 return "I40E_AQ_RC_E2BIG";
109 case I40E_AQ_RC_EAGAIN:
110 return "I40E_AQ_RC_EAGAIN";
111 case I40E_AQ_RC_ENOMEM:
112 return "I40E_AQ_RC_ENOMEM";
113 case I40E_AQ_RC_EACCES:
114 return "I40E_AQ_RC_EACCES";
115 case I40E_AQ_RC_EFAULT:
116 return "I40E_AQ_RC_EFAULT";
117 case I40E_AQ_RC_EBUSY:
118 return "I40E_AQ_RC_EBUSY";
119 case I40E_AQ_RC_EEXIST:
120 return "I40E_AQ_RC_EEXIST";
121 case I40E_AQ_RC_EINVAL:
122 return "I40E_AQ_RC_EINVAL";
123 case I40E_AQ_RC_ENOTTY:
124 return "I40E_AQ_RC_ENOTTY";
125 case I40E_AQ_RC_ENOSPC:
126 return "I40E_AQ_RC_ENOSPC";
127 case I40E_AQ_RC_ENOSYS:
128 return "I40E_AQ_RC_ENOSYS";
129 case I40E_AQ_RC_ERANGE:
130 return "I40E_AQ_RC_ERANGE";
131 case I40E_AQ_RC_EFLUSHED:
132 return "I40E_AQ_RC_EFLUSHED";
133 case I40E_AQ_RC_BAD_ADDR:
134 return "I40E_AQ_RC_BAD_ADDR";
135 case I40E_AQ_RC_EMODE:
136 return "I40E_AQ_RC_EMODE";
137 case I40E_AQ_RC_EFBIG:
138 return "I40E_AQ_RC_EFBIG";
139 }
140
141 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
142 return hw->err_str;
143}
144
145/**
146 * i40e_stat_str - convert status err code to a string
147 * @hw: pointer to the HW structure
148 * @stat_err: the status error code to convert
149 **/
4e68adfe 150const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
f1c7e72e
SN		 151{
152 switch (stat_err) {
153 case 0:
154 return "OK";
155 case I40E_ERR_NVM:
156 return "I40E_ERR_NVM";
157 case I40E_ERR_NVM_CHECKSUM:
158 return "I40E_ERR_NVM_CHECKSUM";
159 case I40E_ERR_PHY:
160 return "I40E_ERR_PHY";
161 case I40E_ERR_CONFIG:
162 return "I40E_ERR_CONFIG";
163 case I40E_ERR_PARAM:
164 return "I40E_ERR_PARAM";
165 case I40E_ERR_MAC_TYPE:
166 return "I40E_ERR_MAC_TYPE";
167 case I40E_ERR_UNKNOWN_PHY:
168 return "I40E_ERR_UNKNOWN_PHY";
169 case I40E_ERR_LINK_SETUP:
170 return "I40E_ERR_LINK_SETUP";
171 case I40E_ERR_ADAPTER_STOPPED:
172 return "I40E_ERR_ADAPTER_STOPPED";
173 case I40E_ERR_INVALID_MAC_ADDR:
174 return "I40E_ERR_INVALID_MAC_ADDR";
175 case I40E_ERR_DEVICE_NOT_SUPPORTED:
176 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
177 case I40E_ERR_MASTER_REQUESTS_PENDING:
178 return "I40E_ERR_MASTER_REQUESTS_PENDING";
179 case I40E_ERR_INVALID_LINK_SETTINGS:
180 return "I40E_ERR_INVALID_LINK_SETTINGS";
181 case I40E_ERR_AUTONEG_NOT_COMPLETE:
182 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
183 case I40E_ERR_RESET_FAILED:
184 return "I40E_ERR_RESET_FAILED";
185 case I40E_ERR_SWFW_SYNC:
186 return "I40E_ERR_SWFW_SYNC";
187 case I40E_ERR_NO_AVAILABLE_VSI:
188 return "I40E_ERR_NO_AVAILABLE_VSI";
189 case I40E_ERR_NO_MEMORY:
190 return "I40E_ERR_NO_MEMORY";
191 case I40E_ERR_BAD_PTR:
192 return "I40E_ERR_BAD_PTR";
193 case I40E_ERR_RING_FULL:
194 return "I40E_ERR_RING_FULL";
195 case I40E_ERR_INVALID_PD_ID:
196 return "I40E_ERR_INVALID_PD_ID";
197 case I40E_ERR_INVALID_QP_ID:
198 return "I40E_ERR_INVALID_QP_ID";
199 case I40E_ERR_INVALID_CQ_ID:
200 return "I40E_ERR_INVALID_CQ_ID";
201 case I40E_ERR_INVALID_CEQ_ID:
202 return "I40E_ERR_INVALID_CEQ_ID";
203 case I40E_ERR_INVALID_AEQ_ID:
204 return "I40E_ERR_INVALID_AEQ_ID";
205 case I40E_ERR_INVALID_SIZE:
206 return "I40E_ERR_INVALID_SIZE";
207 case I40E_ERR_INVALID_ARP_INDEX:
208 return "I40E_ERR_INVALID_ARP_INDEX";
209 case I40E_ERR_INVALID_FPM_FUNC_ID:
210 return "I40E_ERR_INVALID_FPM_FUNC_ID";
211 case I40E_ERR_QP_INVALID_MSG_SIZE:
212 return "I40E_ERR_QP_INVALID_MSG_SIZE";
213 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
214 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
215 case I40E_ERR_INVALID_FRAG_COUNT:
216 return "I40E_ERR_INVALID_FRAG_COUNT";
217 case I40E_ERR_QUEUE_EMPTY:
218 return "I40E_ERR_QUEUE_EMPTY";
219 case I40E_ERR_INVALID_ALIGNMENT:
220 return "I40E_ERR_INVALID_ALIGNMENT";
221 case I40E_ERR_FLUSHED_QUEUE:
222 return "I40E_ERR_FLUSHED_QUEUE";
223 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
224 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
225 case I40E_ERR_INVALID_IMM_DATA_SIZE:
226 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
227 case I40E_ERR_TIMEOUT:
228 return "I40E_ERR_TIMEOUT";
229 case I40E_ERR_OPCODE_MISMATCH:
230 return "I40E_ERR_OPCODE_MISMATCH";
231 case I40E_ERR_CQP_COMPL_ERROR:
232 return "I40E_ERR_CQP_COMPL_ERROR";
233 case I40E_ERR_INVALID_VF_ID:
234 return "I40E_ERR_INVALID_VF_ID";
235 case I40E_ERR_INVALID_HMCFN_ID:
236 return "I40E_ERR_INVALID_HMCFN_ID";
237 case I40E_ERR_BACKING_PAGE_ERROR:
238 return "I40E_ERR_BACKING_PAGE_ERROR";
239 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
240 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
241 case I40E_ERR_INVALID_PBLE_INDEX:
242 return "I40E_ERR_INVALID_PBLE_INDEX";
243 case I40E_ERR_INVALID_SD_INDEX:
244 return "I40E_ERR_INVALID_SD_INDEX";
245 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
246 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
247 case I40E_ERR_INVALID_SD_TYPE:
248 return "I40E_ERR_INVALID_SD_TYPE";
249 case I40E_ERR_MEMCPY_FAILED:
250 return "I40E_ERR_MEMCPY_FAILED";
251 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
252 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
253 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
254 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
255 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
256 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
257 case I40E_ERR_SRQ_ENABLED:
258 return "I40E_ERR_SRQ_ENABLED";
259 case I40E_ERR_ADMIN_QUEUE_ERROR:
260 return "I40E_ERR_ADMIN_QUEUE_ERROR";
261 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
262 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
263 case I40E_ERR_BUF_TOO_SHORT:
264 return "I40E_ERR_BUF_TOO_SHORT";
265 case I40E_ERR_ADMIN_QUEUE_FULL:
266 return "I40E_ERR_ADMIN_QUEUE_FULL";
267 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
268 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
269 case I40E_ERR_BAD_IWARP_CQE:
270 return "I40E_ERR_BAD_IWARP_CQE";
271 case I40E_ERR_NVM_BLANK_MODE:
272 return "I40E_ERR_NVM_BLANK_MODE";
273 case I40E_ERR_NOT_IMPLEMENTED:
274 return "I40E_ERR_NOT_IMPLEMENTED";
275 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
276 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
277 case I40E_ERR_DIAG_TEST_FAILED:
278 return "I40E_ERR_DIAG_TEST_FAILED";
279 case I40E_ERR_NOT_READY:
280 return "I40E_ERR_NOT_READY";
281 case I40E_NOT_SUPPORTED:
282 return "I40E_NOT_SUPPORTED";
283 case I40E_ERR_FIRMWARE_API_VERSION:
284 return "I40E_ERR_FIRMWARE_API_VERSION";
285 }
286
287 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
288 return hw->err_str;
289}
290
56a62fc8
JB		 291/**
292 * i40e_debug_aq
293 * @hw: debug mask related to admin queue
98d44381
JK		 294 * @mask: debug mask
295 * @desc: pointer to admin queue descriptor
56a62fc8 296 * @buffer: pointer to command buffer
f905dd62 297 * @buf_len: max length of buffer
56a62fc8
JB		 298 *
299 * Dumps debug log about adminq command with descriptor contents.
300 **/
301void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
f905dd62 302 void *buffer, u16 buf_len)
56a62fc8
JB		 303{
304 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
f905dd62 305 u16 len = le16_to_cpu(aq_desc->datalen);
37a2973a
SN		 306 u8 *buf = (u8 *)buffer;
307 u16 i = 0;
56a62fc8
JB		 308
309 if ((!(mask & hw->debug_mask)) || (desc == NULL))
310 return;
311
312 i40e_debug(hw, mask,
313 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
f1abd7db
PSJ		 314 le16_to_cpu(aq_desc->opcode),
315 le16_to_cpu(aq_desc->flags),
316 le16_to_cpu(aq_desc->datalen),
317 le16_to_cpu(aq_desc->retval));
56a62fc8 318 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 319 le32_to_cpu(aq_desc->cookie_high),
320 le32_to_cpu(aq_desc->cookie_low));
56a62fc8 321 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 322 le32_to_cpu(aq_desc->params.internal.param0),
323 le32_to_cpu(aq_desc->params.internal.param1));
56a62fc8 324 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 325 le32_to_cpu(aq_desc->params.external.addr_high),
326 le32_to_cpu(aq_desc->params.external.addr_low));
56a62fc8
JB		 327
328 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
56a62fc8 329 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
f905dd62
SN		 330 if (buf_len < len)
331 len = buf_len;
37a2973a
SN		 332 /* write the full 16-byte chunks */
333 for (i = 0; i < (len - 16); i += 16)
334 i40e_debug(hw, mask,
335 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
336 i, buf[i], buf[i + 1], buf[i + 2],
337 buf[i + 3], buf[i + 4], buf[i + 5],
338 buf[i + 6], buf[i + 7], buf[i + 8],
339 buf[i + 9], buf[i + 10], buf[i + 11],
340 buf[i + 12], buf[i + 13], buf[i + 14],
341 buf[i + 15]);
342 /* write whatever's left over without overrunning the buffer */
343 if (i < len) {
344 char d_buf[80];
345 int j = 0;
346
347 memset(d_buf, 0, sizeof(d_buf));
348 j += sprintf(d_buf, "\t0x%04X ", i);
349 while (i < len)
350 j += sprintf(&d_buf[j], " %02X", buf[i++]);
351 i40e_debug(hw, mask, "%s\n", d_buf);
56a62fc8 352 }
56a62fc8
JB		 353 }
354}
355
e1860d8f
ASJ		 356/**
357 * i40e_check_asq_alive
358 * @hw: pointer to the hw struct
359 *
360 * Returns true if Queue is enabled else false.
361 **/
362bool i40e_check_asq_alive(struct i40e_hw *hw)
363{
8b833b4f
KS		 364 if (hw->aq.asq.len)
365 return !!(rd32(hw, hw->aq.asq.len) &
366 I40E_PF_ATQLEN_ATQENABLE_MASK);
367 else
368 return false;
e1860d8f
ASJ		 369}
370
371/**
372 * i40e_aq_queue_shutdown
373 * @hw: pointer to the hw struct
374 * @unloading: is the driver unloading itself
375 *
376 * Tell the Firmware that we're shutting down the AdminQ and whether
377 * or not the driver is unloading as well.
378 **/
379i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
380 bool unloading)
381{
382 struct i40e_aq_desc desc;
383 struct i40e_aqc_queue_shutdown *cmd =
384 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
385 i40e_status status;
386
387 i40e_fill_default_direct_cmd_desc(&desc,
388 i40e_aqc_opc_queue_shutdown);
389
390 if (unloading)
391 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
392 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
393
394 return status;
395}
396
e50c8d6d
ASJ		 397/**
398 * i40e_aq_get_set_rss_lut
399 * @hw: pointer to the hardware structure
400 * @vsi_id: vsi fw index
401 * @pf_lut: for PF table set true, for VSI table set false
402 * @lut: pointer to the lut buffer provided by the caller
403 * @lut_size: size of the lut buffer
404 * @set: set true to set the table, false to get the table
405 *
406 * Internal function to get or set RSS look up table
407 **/
408static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
409 u16 vsi_id, bool pf_lut,
410 u8 *lut, u16 lut_size,
411 bool set)
412{
413 i40e_status status;
414 struct i40e_aq_desc desc;
415 struct i40e_aqc_get_set_rss_lut *cmd_resp =
416 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
417
418 if (set)
419 i40e_fill_default_direct_cmd_desc(&desc,
420 i40e_aqc_opc_set_rss_lut);
421 else
422 i40e_fill_default_direct_cmd_desc(&desc,
423 i40e_aqc_opc_get_rss_lut);
424
425 /* Indirect command */
426 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
427 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
428
429 cmd_resp->vsi_id =
430 cpu_to_le16((u16)((vsi_id <<
431 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
432 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
433 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
434
435 if (pf_lut)
436 cmd_resp->flags |= cpu_to_le16((u16)
437 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
438 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
439 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
440 else
441 cmd_resp->flags |= cpu_to_le16((u16)
442 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
443 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
444 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
445
e50c8d6d
ASJ		 446 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
447
448 return status;
449}
450
451/**
452 * i40e_aq_get_rss_lut
453 * @hw: pointer to the hardware structure
454 * @vsi_id: vsi fw index
455 * @pf_lut: for PF table set true, for VSI table set false
456 * @lut: pointer to the lut buffer provided by the caller
457 * @lut_size: size of the lut buffer
458 *
459 * get the RSS lookup table, PF or VSI type
460 **/
461i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
462 bool pf_lut, u8 *lut, u16 lut_size)
463{
464 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
465 false);
466}
467
468/**
469 * i40e_aq_set_rss_lut
470 * @hw: pointer to the hardware structure
471 * @vsi_id: vsi fw index
472 * @pf_lut: for PF table set true, for VSI table set false
473 * @lut: pointer to the lut buffer provided by the caller
474 * @lut_size: size of the lut buffer
475 *
476 * set the RSS lookup table, PF or VSI type
477 **/
478i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
479 bool pf_lut, u8 *lut, u16 lut_size)
480{
481 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
482}
483
484/**
485 * i40e_aq_get_set_rss_key
486 * @hw: pointer to the hw struct
487 * @vsi_id: vsi fw index
488 * @key: pointer to key info struct
489 * @set: set true to set the key, false to get the key
490 *
491 * get the RSS key per VSI
492 **/
493static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
494 u16 vsi_id,
495 struct i40e_aqc_get_set_rss_key_data *key,
496 bool set)
497{
498 i40e_status status;
499 struct i40e_aq_desc desc;
500 struct i40e_aqc_get_set_rss_key *cmd_resp =
501 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
502 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
503
504 if (set)
505 i40e_fill_default_direct_cmd_desc(&desc,
506 i40e_aqc_opc_set_rss_key);
507 else
508 i40e_fill_default_direct_cmd_desc(&desc,
509 i40e_aqc_opc_get_rss_key);
510
511 /* Indirect command */
512 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
513 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
514
515 cmd_resp->vsi_id =
516 cpu_to_le16((u16)((vsi_id <<
517 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
518 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
519 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
e50c8d6d
ASJ		 520
521 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
522
523 return status;
524}
525
526/**
527 * i40e_aq_get_rss_key
528 * @hw: pointer to the hw struct
529 * @vsi_id: vsi fw index
530 * @key: pointer to key info struct
531 *
532 **/
533i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
534 u16 vsi_id,
535 struct i40e_aqc_get_set_rss_key_data *key)
536{
537 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
538}
539
540/**
541 * i40e_aq_set_rss_key
542 * @hw: pointer to the hw struct
543 * @vsi_id: vsi fw index
544 * @key: pointer to key info struct
545 *
546 * set the RSS key per VSI
547 **/
548i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
549 u16 vsi_id,
550 struct i40e_aqc_get_set_rss_key_data *key)
551{
552 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
553}
554
206812b5
JB		 555/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
556 * hardware to a bit-field that can be used by SW to more easily determine the
557 * packet type.
558 *
559 * Macros are used to shorten the table lines and make this table human
560 * readable.
561 *
562 * We store the PTYPE in the top byte of the bit field - this is just so that
563 * we can check that the table doesn't have a row missing, as the index into
564 * the table should be the PTYPE.
565 *
566 * Typical work flow:
567 *
568 * IF NOT i40e_ptype_lookup[ptype].known
569 * THEN
570 * Packet is unknown
571 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
572 * Use the rest of the fields to look at the tunnels, inner protocols, etc
573 * ELSE
574 * Use the enum i40e_rx_l2_ptype to decode the packet type
575 * ENDIF
576 */
577
578/* macro to make the table lines short */
579#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
580 { PTYPE, \
581 1, \
582 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
583 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
584 I40E_RX_PTYPE_##OUTER_FRAG, \
585 I40E_RX_PTYPE_TUNNEL_##T, \
586 I40E_RX_PTYPE_TUNNEL_END_##TE, \
587 I40E_RX_PTYPE_##TEF, \
588 I40E_RX_PTYPE_INNER_PROT_##I, \
589 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
590
591#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
592 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
593
594/* shorter macros makes the table fit but are terse */
595#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
596#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
597#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
598
599/* Lookup table mapping the HW PTYPE to the bit field for decoding */
600struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
601 /* L2 Packet types */
602 I40E_PTT_UNUSED_ENTRY(0),
603 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
604 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
605 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
606 I40E_PTT_UNUSED_ENTRY(4),
607 I40E_PTT_UNUSED_ENTRY(5),
608 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
609 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
610 I40E_PTT_UNUSED_ENTRY(8),
611 I40E_PTT_UNUSED_ENTRY(9),
612 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
613 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
614 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
615 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
616 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
617 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
618 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
619 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
620 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
621 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
622 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
623 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
624
625 /* Non Tunneled IPv4 */
626 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
627 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
628 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
629 I40E_PTT_UNUSED_ENTRY(25),
630 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
631 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
632 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
633
634 /* IPv4 --> IPv4 */
635 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(32),
639 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
642
643 /* IPv4 --> IPv6 */
644 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(39),
648 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
651
652 /* IPv4 --> GRE/NAT */
653 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
654
655 /* IPv4 --> GRE/NAT --> IPv4 */
656 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(47),
660 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
663
664 /* IPv4 --> GRE/NAT --> IPv6 */
665 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(54),
669 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
672
673 /* IPv4 --> GRE/NAT --> MAC */
674 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
675
676 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
677 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
678 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
679 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
680 I40E_PTT_UNUSED_ENTRY(62),
681 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
682 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
683 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
684
685 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
686 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
687 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
688 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
689 I40E_PTT_UNUSED_ENTRY(69),
690 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
691 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
692 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
693
694 /* IPv4 --> GRE/NAT --> MAC/VLAN */
695 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
696
697 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
698 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
699 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
700 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
701 I40E_PTT_UNUSED_ENTRY(77),
702 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
703 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
704 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
705
706 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
707 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
708 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
709 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
710 I40E_PTT_UNUSED_ENTRY(84),
711 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
712 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
713 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
714
715 /* Non Tunneled IPv6 */
716 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
717 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
718 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
719 I40E_PTT_UNUSED_ENTRY(91),
720 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
721 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
722 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
723
724 /* IPv6 --> IPv4 */
725 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(98),
729 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
732
733 /* IPv6 --> IPv6 */
734 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(105),
738 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
741
742 /* IPv6 --> GRE/NAT */
743 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
744
745 /* IPv6 --> GRE/NAT -> IPv4 */
746 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
747 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
748 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
749 I40E_PTT_UNUSED_ENTRY(113),
750 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
751 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
752 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
753
754 /* IPv6 --> GRE/NAT -> IPv6 */
755 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
756 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
757 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(120),
759 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
760 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
761 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
762
763 /* IPv6 --> GRE/NAT -> MAC */
764 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
765
766 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
767 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
768 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
769 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
770 I40E_PTT_UNUSED_ENTRY(128),
771 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
772 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
773 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
774
775 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
776 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
777 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
778 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
779 I40E_PTT_UNUSED_ENTRY(135),
780 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
781 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
782 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
783
784 /* IPv6 --> GRE/NAT -> MAC/VLAN */
785 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
786
787 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
788 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
789 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
790 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
791 I40E_PTT_UNUSED_ENTRY(143),
792 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
793 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
794 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
795
796 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
797 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
798 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
799 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
800 I40E_PTT_UNUSED_ENTRY(150),
801 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
802 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
803 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
804
805 /* unused entries */
806 I40E_PTT_UNUSED_ENTRY(154),
807 I40E_PTT_UNUSED_ENTRY(155),
808 I40E_PTT_UNUSED_ENTRY(156),
809 I40E_PTT_UNUSED_ENTRY(157),
810 I40E_PTT_UNUSED_ENTRY(158),
811 I40E_PTT_UNUSED_ENTRY(159),
812
813 I40E_PTT_UNUSED_ENTRY(160),
814 I40E_PTT_UNUSED_ENTRY(161),
815 I40E_PTT_UNUSED_ENTRY(162),
816 I40E_PTT_UNUSED_ENTRY(163),
817 I40E_PTT_UNUSED_ENTRY(164),
818 I40E_PTT_UNUSED_ENTRY(165),
819 I40E_PTT_UNUSED_ENTRY(166),
820 I40E_PTT_UNUSED_ENTRY(167),
821 I40E_PTT_UNUSED_ENTRY(168),
822 I40E_PTT_UNUSED_ENTRY(169),
823
824 I40E_PTT_UNUSED_ENTRY(170),
825 I40E_PTT_UNUSED_ENTRY(171),
826 I40E_PTT_UNUSED_ENTRY(172),
827 I40E_PTT_UNUSED_ENTRY(173),
828 I40E_PTT_UNUSED_ENTRY(174),
829 I40E_PTT_UNUSED_ENTRY(175),
830 I40E_PTT_UNUSED_ENTRY(176),
831 I40E_PTT_UNUSED_ENTRY(177),
832 I40E_PTT_UNUSED_ENTRY(178),
833 I40E_PTT_UNUSED_ENTRY(179),
834
835 I40E_PTT_UNUSED_ENTRY(180),
836 I40E_PTT_UNUSED_ENTRY(181),
837 I40E_PTT_UNUSED_ENTRY(182),
838 I40E_PTT_UNUSED_ENTRY(183),
839 I40E_PTT_UNUSED_ENTRY(184),
840 I40E_PTT_UNUSED_ENTRY(185),
841 I40E_PTT_UNUSED_ENTRY(186),
842 I40E_PTT_UNUSED_ENTRY(187),
843 I40E_PTT_UNUSED_ENTRY(188),
844 I40E_PTT_UNUSED_ENTRY(189),
845
846 I40E_PTT_UNUSED_ENTRY(190),
847 I40E_PTT_UNUSED_ENTRY(191),
848 I40E_PTT_UNUSED_ENTRY(192),
849 I40E_PTT_UNUSED_ENTRY(193),
850 I40E_PTT_UNUSED_ENTRY(194),
851 I40E_PTT_UNUSED_ENTRY(195),
852 I40E_PTT_UNUSED_ENTRY(196),
853 I40E_PTT_UNUSED_ENTRY(197),
854 I40E_PTT_UNUSED_ENTRY(198),
855 I40E_PTT_UNUSED_ENTRY(199),
856
857 I40E_PTT_UNUSED_ENTRY(200),
858 I40E_PTT_UNUSED_ENTRY(201),
859 I40E_PTT_UNUSED_ENTRY(202),
860 I40E_PTT_UNUSED_ENTRY(203),
861 I40E_PTT_UNUSED_ENTRY(204),
862 I40E_PTT_UNUSED_ENTRY(205),
863 I40E_PTT_UNUSED_ENTRY(206),
864 I40E_PTT_UNUSED_ENTRY(207),
865 I40E_PTT_UNUSED_ENTRY(208),
866 I40E_PTT_UNUSED_ENTRY(209),
867
868 I40E_PTT_UNUSED_ENTRY(210),
869 I40E_PTT_UNUSED_ENTRY(211),
870 I40E_PTT_UNUSED_ENTRY(212),
871 I40E_PTT_UNUSED_ENTRY(213),
872 I40E_PTT_UNUSED_ENTRY(214),
873 I40E_PTT_UNUSED_ENTRY(215),
874 I40E_PTT_UNUSED_ENTRY(216),
875 I40E_PTT_UNUSED_ENTRY(217),
876 I40E_PTT_UNUSED_ENTRY(218),
877 I40E_PTT_UNUSED_ENTRY(219),
878
879 I40E_PTT_UNUSED_ENTRY(220),
880 I40E_PTT_UNUSED_ENTRY(221),
881 I40E_PTT_UNUSED_ENTRY(222),
882 I40E_PTT_UNUSED_ENTRY(223),
883 I40E_PTT_UNUSED_ENTRY(224),
884 I40E_PTT_UNUSED_ENTRY(225),
885 I40E_PTT_UNUSED_ENTRY(226),
886 I40E_PTT_UNUSED_ENTRY(227),
887 I40E_PTT_UNUSED_ENTRY(228),
888 I40E_PTT_UNUSED_ENTRY(229),
889
890 I40E_PTT_UNUSED_ENTRY(230),
891 I40E_PTT_UNUSED_ENTRY(231),
892 I40E_PTT_UNUSED_ENTRY(232),
893 I40E_PTT_UNUSED_ENTRY(233),
894 I40E_PTT_UNUSED_ENTRY(234),
895 I40E_PTT_UNUSED_ENTRY(235),
896 I40E_PTT_UNUSED_ENTRY(236),
897 I40E_PTT_UNUSED_ENTRY(237),
898 I40E_PTT_UNUSED_ENTRY(238),
899 I40E_PTT_UNUSED_ENTRY(239),
900
901 I40E_PTT_UNUSED_ENTRY(240),
902 I40E_PTT_UNUSED_ENTRY(241),
903 I40E_PTT_UNUSED_ENTRY(242),
904 I40E_PTT_UNUSED_ENTRY(243),
905 I40E_PTT_UNUSED_ENTRY(244),
906 I40E_PTT_UNUSED_ENTRY(245),
907 I40E_PTT_UNUSED_ENTRY(246),
908 I40E_PTT_UNUSED_ENTRY(247),
909 I40E_PTT_UNUSED_ENTRY(248),
910 I40E_PTT_UNUSED_ENTRY(249),
911
912 I40E_PTT_UNUSED_ENTRY(250),
913 I40E_PTT_UNUSED_ENTRY(251),
914 I40E_PTT_UNUSED_ENTRY(252),
915 I40E_PTT_UNUSED_ENTRY(253),
916 I40E_PTT_UNUSED_ENTRY(254),
917 I40E_PTT_UNUSED_ENTRY(255)
918};
919
56a62fc8
JB		 920/**
921 * i40e_init_shared_code - Initialize the shared code
922 * @hw: pointer to hardware structure
923 *
924 * This assigns the MAC type and PHY code and inits the NVM.
925 * Does not touch the hardware. This function must be called prior to any
926 * other function in the shared code. The i40e_hw structure should be
927 * memset to 0 prior to calling this function. The following fields in
928 * hw structure should be filled in prior to calling this function:
929 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
930 * subsystem_vendor_id, and revision_id
931 **/
932i40e_status i40e_init_shared_code(struct i40e_hw *hw)
933{
934 i40e_status status = 0;
5fb11d76 935 u32 port, ari, func_rid;
56a62fc8 936
56a62fc8
JB		 937 i40e_set_mac_type(hw);
938
939 switch (hw->mac.type) {
940 case I40E_MAC_XL710:
87e6c1d7 941 case I40E_MAC_X722:
56a62fc8
JB		 942 break;
943 default:
944 return I40E_ERR_DEVICE_NOT_SUPPORTED;
56a62fc8
JB		 945 }
946
af89d26c
SN		 947 hw->phy.get_link_info = true;
948
5fb11d76
SN		 949 /* Determine port number and PF number*/
950 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
951 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
952 hw->port = (u8)port;
953 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
954 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
955 func_rid = rd32(hw, I40E_PF_FUNC_RID);
956 if (ari)
957 hw->pf_id = (u8)(func_rid & 0xff);
5f9116ac 958 else
5fb11d76 959 hw->pf_id = (u8)(func_rid & 0x7);
5f9116ac 960
07f89be8
AS		 961 if (hw->mac.type == I40E_MAC_X722)
962 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
963
56a62fc8
JB		 964 status = i40e_init_nvm(hw);
965 return status;
966}
967
968/**
969 * i40e_aq_mac_address_read - Retrieve the MAC addresses
970 * @hw: pointer to the hw struct
971 * @flags: a return indicator of what addresses were added to the addr store
972 * @addrs: the requestor's mac addr store
973 * @cmd_details: pointer to command details structure or NULL
974 **/
975static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
976 u16 *flags,
977 struct i40e_aqc_mac_address_read_data *addrs,
978 struct i40e_asq_cmd_details *cmd_details)
979{
980 struct i40e_aq_desc desc;
981 struct i40e_aqc_mac_address_read *cmd_data =
982 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
983 i40e_status status;
984
985 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
986 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
987
988 status = i40e_asq_send_command(hw, &desc, addrs,
989 sizeof(*addrs), cmd_details);
990 *flags = le16_to_cpu(cmd_data->command_flags);
991
992 return status;
993}
994
995/**
996 * i40e_aq_mac_address_write - Change the MAC addresses
997 * @hw: pointer to the hw struct
998 * @flags: indicates which MAC to be written
999 * @mac_addr: address to write
1000 * @cmd_details: pointer to command details structure or NULL
1001 **/
1002i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
1003 u16 flags, u8 *mac_addr,
1004 struct i40e_asq_cmd_details *cmd_details)
1005{
1006 struct i40e_aq_desc desc;
1007 struct i40e_aqc_mac_address_write *cmd_data =
1008 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1009 i40e_status status;
1010
1011 i40e_fill_default_direct_cmd_desc(&desc,
1012 i40e_aqc_opc_mac_address_write);
1013 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 1014 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
1015 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
1016 ((u32)mac_addr[3] << 16) |
1017 ((u32)mac_addr[4] << 8) |
1018 mac_addr[5]);
56a62fc8
JB		 1019
1020 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1021
1022 return status;
1023}
1024
1025/**
1026 * i40e_get_mac_addr - get MAC address
1027 * @hw: pointer to the HW structure
1028 * @mac_addr: pointer to MAC address
1029 *
1030 * Reads the adapter's MAC address from register
1031 **/
1032i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1033{
1034 struct i40e_aqc_mac_address_read_data addrs;
1035 i40e_status status;
1036 u16 flags = 0;
1037
1038 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1039
1040 if (flags & I40E_AQC_LAN_ADDR_VALID)
6995b36c 1041 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
56a62fc8
JB		 1042
1043 return status;
1044}
1045
1f224ad2
NP		 1046/**
1047 * i40e_get_port_mac_addr - get Port MAC address
1048 * @hw: pointer to the HW structure
1049 * @mac_addr: pointer to Port MAC address
1050 *
1051 * Reads the adapter's Port MAC address
1052 **/
1053i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1054{
1055 struct i40e_aqc_mac_address_read_data addrs;
1056 i40e_status status;
1057 u16 flags = 0;
1058
1059 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1060 if (status)
1061 return status;
1062
1063 if (flags & I40E_AQC_PORT_ADDR_VALID)
6995b36c 1064 ether_addr_copy(mac_addr, addrs.port_mac);
1f224ad2
NP		 1065 else
1066 status = I40E_ERR_INVALID_MAC_ADDR;
1067
1068 return status;
1069}
1070
351499ab
MJ		 1071/**
1072 * i40e_pre_tx_queue_cfg - pre tx queue configure
1073 * @hw: pointer to the HW structure
b40c82e6 1074 * @queue: target PF queue index
351499ab
MJ		 1075 * @enable: state change request
1076 *
1077 * Handles hw requirement to indicate intention to enable
1078 * or disable target queue.
1079 **/
1080void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1081{
dfb699f9 1082 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 1083 u32 reg_block = 0;
dfb699f9 1084 u32 reg_val;
351499ab 1085
24a768cf 1086 if (abs_queue_idx >= 128) {
351499ab 1087 reg_block = abs_queue_idx / 128;
24a768cf
CP		 1088 abs_queue_idx %= 128;
1089 }
351499ab
MJ		 1090
1091 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1092 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1093 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1094
1095 if (enable)
1096 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1097 else
1098 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1099
1100 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1101}
38e00438
VD		 1102#ifdef I40E_FCOE
1103
1104/**
1105 * i40e_get_san_mac_addr - get SAN MAC address
1106 * @hw: pointer to the HW structure
1107 * @mac_addr: pointer to SAN MAC address
1108 *
1109 * Reads the adapter's SAN MAC address from NVM
1110 **/
1111i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1112{
1113 struct i40e_aqc_mac_address_read_data addrs;
1114 i40e_status status;
1115 u16 flags = 0;
1116
1117 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1118 if (status)
1119 return status;
1120
1121 if (flags & I40E_AQC_SAN_ADDR_VALID)
6995b36c 1122 ether_addr_copy(mac_addr, addrs.pf_san_mac);
38e00438
VD		 1123 else
1124 status = I40E_ERR_INVALID_MAC_ADDR;
1125
1126 return status;
1127}
1128#endif
351499ab 1129
18f680c6
KK		 1130/**
1131 * i40e_read_pba_string - Reads part number string from EEPROM
1132 * @hw: pointer to hardware structure
1133 * @pba_num: stores the part number string from the EEPROM
1134 * @pba_num_size: part number string buffer length
1135 *
1136 * Reads the part number string from the EEPROM.
1137 **/
1138i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1139 u32 pba_num_size)
1140{
1141 i40e_status status = 0;
1142 u16 pba_word = 0;
1143 u16 pba_size = 0;
1144 u16 pba_ptr = 0;
1145 u16 i = 0;
1146
1147 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1148 if (status || (pba_word != 0xFAFA)) {
1149 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1150 return status;
1151 }
1152
1153 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1154 if (status) {
1155 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1156 return status;
1157 }
1158
1159 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1160 if (status) {
1161 hw_dbg(hw, "Failed to read PBA Block size.\n");
1162 return status;
1163 }
1164
1165 /* Subtract one to get PBA word count (PBA Size word is included in
1166 * total size)
1167 */
1168 pba_size--;
1169 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1170 hw_dbg(hw, "Buffer to small for PBA data.\n");
1171 return I40E_ERR_PARAM;
1172 }
1173
1174 for (i = 0; i < pba_size; i++) {
1175 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1176 if (status) {
1177 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1178 return status;
1179 }
1180
1181 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1182 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1183 }
1184 pba_num[(pba_size * 2)] = '\0';
1185
1186 return status;
1187}
1188
be405eb0
JB		 1189/**
1190 * i40e_get_media_type - Gets media type
1191 * @hw: pointer to the hardware structure
1192 **/
1193static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1194{
1195 enum i40e_media_type media;
1196
1197 switch (hw->phy.link_info.phy_type) {
1198 case I40E_PHY_TYPE_10GBASE_SR:
1199 case I40E_PHY_TYPE_10GBASE_LR:
124ed15b
CS		 1200 case I40E_PHY_TYPE_1000BASE_SX:
1201 case I40E_PHY_TYPE_1000BASE_LX:
be405eb0
JB		 1202 case I40E_PHY_TYPE_40GBASE_SR4:
1203 case I40E_PHY_TYPE_40GBASE_LR4:
1204 media = I40E_MEDIA_TYPE_FIBER;
1205 break;
1206 case I40E_PHY_TYPE_100BASE_TX:
1207 case I40E_PHY_TYPE_1000BASE_T:
1208 case I40E_PHY_TYPE_10GBASE_T:
1209 media = I40E_MEDIA_TYPE_BASET;
1210 break;
1211 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1212 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1213 case I40E_PHY_TYPE_10GBASE_CR1:
1214 case I40E_PHY_TYPE_40GBASE_CR4:
1215 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
180204c7
CS		 1216 case I40E_PHY_TYPE_40GBASE_AOC:
1217 case I40E_PHY_TYPE_10GBASE_AOC:
be405eb0
JB		 1218 media = I40E_MEDIA_TYPE_DA;
1219 break;
1220 case I40E_PHY_TYPE_1000BASE_KX:
1221 case I40E_PHY_TYPE_10GBASE_KX4:
1222 case I40E_PHY_TYPE_10GBASE_KR:
1223 case I40E_PHY_TYPE_40GBASE_KR4:
ae24b409 1224 case I40E_PHY_TYPE_20GBASE_KR2:
be405eb0
JB		 1225 media = I40E_MEDIA_TYPE_BACKPLANE;
1226 break;
1227 case I40E_PHY_TYPE_SGMII:
1228 case I40E_PHY_TYPE_XAUI:
1229 case I40E_PHY_TYPE_XFI:
1230 case I40E_PHY_TYPE_XLAUI:
1231 case I40E_PHY_TYPE_XLPPI:
1232 default:
1233 media = I40E_MEDIA_TYPE_UNKNOWN;
1234 break;
1235 }
1236
1237 return media;
1238}
1239
7134f9ce 1240#define I40E_PF_RESET_WAIT_COUNT_A0 200
8af580df 1241#define I40E_PF_RESET_WAIT_COUNT 200
56a62fc8
JB		 1242/**
1243 * i40e_pf_reset - Reset the PF
1244 * @hw: pointer to the hardware structure
1245 *
1246 * Assuming someone else has triggered a global reset,
1247 * assure the global reset is complete and then reset the PF
1248 **/
1249i40e_status i40e_pf_reset(struct i40e_hw *hw)
1250{
7134f9ce 1251 u32 cnt = 0;
42794bd8 1252 u32 cnt1 = 0;
56a62fc8
JB		 1253 u32 reg = 0;
1254 u32 grst_del;
1255
1256 /* Poll for Global Reset steady state in case of recent GRST.
1257 * The grst delay value is in 100ms units, and we'll wait a
1258 * couple counts longer to be sure we don't just miss the end.
1259 */
de78fc5a
SN		 1260 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1261 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1262 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
22e05bd6 1263 for (cnt = 0; cnt < grst_del + 10; cnt++) {
56a62fc8
JB		 1264 reg = rd32(hw, I40E_GLGEN_RSTAT);
1265 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1266 break;
1267 msleep(100);
1268 }
1269 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1270 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 1271 return I40E_ERR_RESET_FAILED;
1272 }
1273
1274 /* Now Wait for the FW to be ready */
1275 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1276 reg = rd32(hw, I40E_GLNVM_ULD);
1277 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1278 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1279 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1280 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1281 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1282 break;
1283 }
1284 usleep_range(10000, 20000);
1285 }
1286 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1287 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1288 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1289 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 1290 return I40E_ERR_RESET_FAILED;
1291 }
1292
56a62fc8
JB		 1293 /* If there was a Global Reset in progress when we got here,
1294 * we don't need to do the PF Reset
1295 */
7134f9ce
JB		 1296 if (!cnt) {
1297 if (hw->revision_id == 0)
1298 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1299 else
1300 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 1301 reg = rd32(hw, I40E_PFGEN_CTRL);
1302 wr32(hw, I40E_PFGEN_CTRL,
1303 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 1304 for (; cnt; cnt--) {
56a62fc8
JB		 1305 reg = rd32(hw, I40E_PFGEN_CTRL);
1306 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1307 break;
1308 usleep_range(1000, 2000);
1309 }
1310 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1311 hw_dbg(hw, "PF reset polling failed to complete.\n");
1312 return I40E_ERR_RESET_FAILED;
1313 }
1314 }
1315
1316 i40e_clear_pxe_mode(hw);
922680b9 1317
56a62fc8
JB		 1318 return 0;
1319}
1320
838d41d9
SN		 1321/**
1322 * i40e_clear_hw - clear out any left over hw state
1323 * @hw: pointer to the hw struct
1324 *
1325 * Clear queues and interrupts, typically called at init time,
1326 * but after the capabilities have been found so we know how many
1327 * queues and msix vectors have been allocated.
1328 **/
1329void i40e_clear_hw(struct i40e_hw *hw)
1330{
1331 u32 num_queues, base_queue;
1332 u32 num_pf_int;
1333 u32 num_vf_int;
1334 u32 num_vfs;
1335 u32 i, j;
1336 u32 val;
1337 u32 eol = 0x7ff;
1338
b40c82e6 1339 /* get number of interrupts, queues, and VFs */
838d41d9
SN		 1340 val = rd32(hw, I40E_GLPCI_CNF2);
1341 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1342 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1343 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1344 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1345
1346 val = rd32(hw, I40E_PFLAN_QALLOC);
1347 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1348 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1349 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1350 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1351 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1352 num_queues = (j - base_queue) + 1;
1353 else
1354 num_queues = 0;
1355
1356 val = rd32(hw, I40E_PF_VT_PFALLOC);
1357 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1358 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1359 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1360 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1361 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1362 num_vfs = (j - i) + 1;
1363 else
1364 num_vfs = 0;
1365
1366 /* stop all the interrupts */
1367 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1368 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1369 for (i = 0; i < num_pf_int - 2; i++)
1370 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1371
1372 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1373 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1374 wr32(hw, I40E_PFINT_LNKLST0, val);
1375 for (i = 0; i < num_pf_int - 2; i++)
1376 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1377 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1378 for (i = 0; i < num_vfs; i++)
1379 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1380 for (i = 0; i < num_vf_int - 2; i++)
1381 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1382
1383 /* warn the HW of the coming Tx disables */
1384 for (i = 0; i < num_queues; i++) {
1385 u32 abs_queue_idx = base_queue + i;
1386 u32 reg_block = 0;
1387
1388 if (abs_queue_idx >= 128) {
1389 reg_block = abs_queue_idx / 128;
1390 abs_queue_idx %= 128;
1391 }
1392
1393 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1394 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1395 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1396 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1397
1398 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1399 }
1400 udelay(400);
1401
1402 /* stop all the queues */
1403 for (i = 0; i < num_queues; i++) {
1404 wr32(hw, I40E_QINT_TQCTL(i), 0);
1405 wr32(hw, I40E_QTX_ENA(i), 0);
1406 wr32(hw, I40E_QINT_RQCTL(i), 0);
1407 wr32(hw, I40E_QRX_ENA(i), 0);
1408 }
1409
1410 /* short wait for all queue disables to settle */
1411 udelay(50);
1412}
1413
56a62fc8
JB		 1414/**
1415 * i40e_clear_pxe_mode - clear pxe operations mode
1416 * @hw: pointer to the hw struct
1417 *
1418 * Make sure all PXE mode settings are cleared, including things
1419 * like descriptor fetch/write-back mode.
1420 **/
1421void i40e_clear_pxe_mode(struct i40e_hw *hw)
1422{
1423 u32 reg;
1424
c9b9b0ae
SN		 1425 if (i40e_check_asq_alive(hw))
1426 i40e_aq_clear_pxe_mode(hw, NULL);
1427
56a62fc8
JB		 1428 /* Clear single descriptor fetch/write-back mode */
1429 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 1430
1431 if (hw->revision_id == 0) {
1432 /* As a work around clear PXE_MODE instead of setting it */
1433 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1434 } else {
1435 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1436 }
56a62fc8
JB		 1437}
1438
0556a9e3
JB		 1439/**
1440 * i40e_led_is_mine - helper to find matching led
1441 * @hw: pointer to the hw struct
1442 * @idx: index into GPIO registers
1443 *
1444 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1445 */
1446static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1447{
1448 u32 gpio_val = 0;
1449 u32 port;
1450
1451 if (!hw->func_caps.led[idx])
1452 return 0;
1453
1454 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1455 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1456 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1457
1458 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1459 * if it is not our port then ignore
1460 */
1461 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1462 (port != hw->port))
1463 return 0;
1464
1465 return gpio_val;
1466}
1467
b84d5cd8
MJ		 1468#define I40E_COMBINED_ACTIVITY 0xA
1469#define I40E_FILTER_ACTIVITY 0xE
0556a9e3 1470#define I40E_LINK_ACTIVITY 0xC
b84d5cd8
MJ		 1471#define I40E_MAC_ACTIVITY 0xD
1472#define I40E_LED0 22
0556a9e3 1473
56a62fc8
JB		 1474/**
1475 * i40e_led_get - return current on/off mode
1476 * @hw: pointer to the hw struct
1477 *
1478 * The value returned is the 'mode' field as defined in the
1479 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1480 * values are variations of possible behaviors relating to
1481 * blink, link, and wire.
1482 **/
1483u32 i40e_led_get(struct i40e_hw *hw)
1484{
b84d5cd8 1485 u32 current_mode = 0;
56a62fc8 1486 u32 mode = 0;
56a62fc8
JB		 1487 int i;
1488
0556a9e3
JB		 1489 /* as per the documentation GPIO 22-29 are the LED
1490 * GPIO pins named LED0..LED7
1491 */
1492 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1493 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1494
0556a9e3 1495 if (!gpio_val)
56a62fc8
JB		 1496 continue;
1497
b84d5cd8
MJ		 1498 /* ignore gpio LED src mode entries related to the activity
1499 * LEDs
1500 */
1501 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1502 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1503 switch (current_mode) {
1504 case I40E_COMBINED_ACTIVITY:
1505 case I40E_FILTER_ACTIVITY:
1506 case I40E_MAC_ACTIVITY:
1507 continue;
1508 default:
1509 break;
1510 }
1511
0556a9e3
JB		 1512 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1513 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 1514 break;
1515 }
1516
1517 return mode;
1518}
1519
1520/**
1521 * i40e_led_set - set new on/off mode
1522 * @hw: pointer to the hw struct
0556a9e3
JB		 1523 * @mode: 0=off, 0xf=on (else see manual for mode details)
1524 * @blink: true if the LED should blink when on, false if steady
1525 *
1526 * if this function is used to turn on the blink it should
1527 * be used to disable the blink when restoring the original state.
56a62fc8 1528 **/
0556a9e3 1529void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1530{
b84d5cd8 1531 u32 current_mode = 0;
56a62fc8
JB		 1532 int i;
1533
0556a9e3
JB		 1534 if (mode & 0xfffffff0)
1535 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1536
0556a9e3
JB		 1537 /* as per the documentation GPIO 22-29 are the LED
1538 * GPIO pins named LED0..LED7
1539 */
1540 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1541 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1542
0556a9e3 1543 if (!gpio_val)
56a62fc8
JB		 1544 continue;
1545
b84d5cd8
MJ		 1546 /* ignore gpio LED src mode entries related to the activity
1547 * LEDs
1548 */
1549 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1550 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1551 switch (current_mode) {
1552 case I40E_COMBINED_ACTIVITY:
1553 case I40E_FILTER_ACTIVITY:
1554 case I40E_MAC_ACTIVITY:
1555 continue;
1556 default:
1557 break;
1558 }
1559
56a62fc8 1560 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1561 /* this & is a bit of paranoia, but serves as a range check */
1562 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1563 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1564
1565 if (mode == I40E_LINK_ACTIVITY)
1566 blink = false;
1567
9be00d67 1568 if (blink)
41a1d04b 1569 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
9be00d67 1570 else
41a1d04b 1571 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
0556a9e3 1572
56a62fc8 1573 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1574 break;
56a62fc8
JB		 1575 }
1576}
1577
1578/* Admin command wrappers */
56a62fc8 1579
8109e123
CS		 1580/**
1581 * i40e_aq_get_phy_capabilities
1582 * @hw: pointer to the hw struct
1583 * @abilities: structure for PHY capabilities to be filled
1584 * @qualified_modules: report Qualified Modules
1585 * @report_init: report init capabilities (active are default)
1586 * @cmd_details: pointer to command details structure or NULL
1587 *
1588 * Returns the various PHY abilities supported on the Port.
1589 **/
1590i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1591 bool qualified_modules, bool report_init,
1592 struct i40e_aq_get_phy_abilities_resp *abilities,
1593 struct i40e_asq_cmd_details *cmd_details)
1594{
1595 struct i40e_aq_desc desc;
1596 i40e_status status;
1597 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1598
1599 if (!abilities)
1600 return I40E_ERR_PARAM;
1601
1602 i40e_fill_default_direct_cmd_desc(&desc,
1603 i40e_aqc_opc_get_phy_abilities);
1604
1605 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1606 if (abilities_size > I40E_AQ_LARGE_BUF)
1607 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1608
1609 if (qualified_modules)
1610 desc.params.external.param0 |=
1611 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1612
1613 if (report_init)
1614 desc.params.external.param0 |=
1615 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1616
1617 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1618 cmd_details);
1619
1620 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1621 status = I40E_ERR_UNKNOWN_PHY;
1622
3ac67d7b
KS		 1623 if (report_init)
1624 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1625
8109e123
CS		 1626 return status;
1627}
1628
c56999f9
CS		 1629/**
1630 * i40e_aq_set_phy_config
1631 * @hw: pointer to the hw struct
1632 * @config: structure with PHY configuration to be set
1633 * @cmd_details: pointer to command details structure or NULL
1634 *
1635 * Set the various PHY configuration parameters
1636 * supported on the Port.One or more of the Set PHY config parameters may be
1637 * ignored in an MFP mode as the PF may not have the privilege to set some
1638 * of the PHY Config parameters. This status will be indicated by the
1639 * command response.
1640 **/
1641enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1642 struct i40e_aq_set_phy_config *config,
1643 struct i40e_asq_cmd_details *cmd_details)
1644{
1645 struct i40e_aq_desc desc;
1646 struct i40e_aq_set_phy_config *cmd =
1647 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1648 enum i40e_status_code status;
1649
1650 if (!config)
1651 return I40E_ERR_PARAM;
1652
1653 i40e_fill_default_direct_cmd_desc(&desc,
1654 i40e_aqc_opc_set_phy_config);
1655
1656 *cmd = *config;
1657
1658 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1659
1660 return status;
1661}
1662
1663/**
1664 * i40e_set_fc
1665 * @hw: pointer to the hw struct
1666 *
1667 * Set the requested flow control mode using set_phy_config.
1668 **/
1669enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1670 bool atomic_restart)
1671{
1672 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1673 struct i40e_aq_get_phy_abilities_resp abilities;
1674 struct i40e_aq_set_phy_config config;
1675 enum i40e_status_code status;
1676 u8 pause_mask = 0x0;
1677
1678 *aq_failures = 0x0;
1679
1680 switch (fc_mode) {
1681 case I40E_FC_FULL:
1682 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1683 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1684 break;
1685 case I40E_FC_RX_PAUSE:
1686 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1687 break;
1688 case I40E_FC_TX_PAUSE:
1689 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1690 break;
1691 default:
1692 break;
1693 }
1694
1695 /* Get the current phy config */
1696 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1697 NULL);
1698 if (status) {
1699 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1700 return status;
1701 }
1702
1703 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1704 /* clear the old pause settings */
1705 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1706 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1707 /* set the new abilities */
1708 config.abilities |= pause_mask;
1709 /* If the abilities have changed, then set the new config */
1710 if (config.abilities != abilities.abilities) {
1711 /* Auto restart link so settings take effect */
1712 if (atomic_restart)
1713 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1714 /* Copy over all the old settings */
1715 config.phy_type = abilities.phy_type;
1716 config.link_speed = abilities.link_speed;
1717 config.eee_capability = abilities.eee_capability;
1718 config.eeer = abilities.eeer_val;
1719 config.low_power_ctrl = abilities.d3_lpan;
1720 status = i40e_aq_set_phy_config(hw, &config, NULL);
1721
1722 if (status)
1723 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1724 }
1725 /* Update the link info */
0a862b43 1726 status = i40e_update_link_info(hw);
c56999f9
CS		 1727 if (status) {
1728 /* Wait a little bit (on 40G cards it sometimes takes a really
1729 * long time for link to come back from the atomic reset)
1730 * and try once more
1731 */
1732 msleep(1000);
0a862b43 1733 status = i40e_update_link_info(hw);
c56999f9
CS		 1734 }
1735 if (status)
1736 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1737
1738 return status;
1739}
1740
c9b9b0ae
SN		 1741/**
1742 * i40e_aq_clear_pxe_mode
1743 * @hw: pointer to the hw struct
1744 * @cmd_details: pointer to command details structure or NULL
1745 *
1746 * Tell the firmware that the driver is taking over from PXE
1747 **/
1748i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1749 struct i40e_asq_cmd_details *cmd_details)
1750{
1751 i40e_status status;
1752 struct i40e_aq_desc desc;
1753 struct i40e_aqc_clear_pxe *cmd =
1754 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1755
1756 i40e_fill_default_direct_cmd_desc(&desc,
1757 i40e_aqc_opc_clear_pxe_mode);
1758
1759 cmd->rx_cnt = 0x2;
1760
1761 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1762
1763 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1764
1765 return status;
1766}
1767
56a62fc8
JB		 1768/**
1769 * i40e_aq_set_link_restart_an
1770 * @hw: pointer to the hw struct
1ac978af 1771 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1772 * @cmd_details: pointer to command details structure or NULL
1773 *
1774 * Sets up the link and restarts the Auto-Negotiation over the link.
1775 **/
1776i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1777 bool enable_link,
1778 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1779{
1780 struct i40e_aq_desc desc;
1781 struct i40e_aqc_set_link_restart_an *cmd =
1782 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1783 i40e_status status;
1784
1785 i40e_fill_default_direct_cmd_desc(&desc,
1786 i40e_aqc_opc_set_link_restart_an);
1787
1788 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1789 if (enable_link)
1790 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1791 else
1792 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1793
1794 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1795
1796 return status;
1797}
1798
1799/**
1800 * i40e_aq_get_link_info
1801 * @hw: pointer to the hw struct
1802 * @enable_lse: enable/disable LinkStatusEvent reporting
1803 * @link: pointer to link status structure - optional
1804 * @cmd_details: pointer to command details structure or NULL
1805 *
1806 * Returns the link status of the adapter.
1807 **/
1808i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1809 bool enable_lse, struct i40e_link_status *link,
1810 struct i40e_asq_cmd_details *cmd_details)
1811{
1812 struct i40e_aq_desc desc;
1813 struct i40e_aqc_get_link_status *resp =
1814 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1815 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1816 i40e_status status;
c56999f9 1817 bool tx_pause, rx_pause;
56a62fc8
JB		 1818 u16 command_flags;
1819
1820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1821
1822 if (enable_lse)
1823 command_flags = I40E_AQ_LSE_ENABLE;
1824 else
1825 command_flags = I40E_AQ_LSE_DISABLE;
1826 resp->command_flags = cpu_to_le16(command_flags);
1827
1828 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1829
1830 if (status)
1831 goto aq_get_link_info_exit;
1832
1833 /* save off old link status information */
c36bd4a7 1834 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1835
1836 /* update link status */
1837 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1838 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1839 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1840 hw_link_info->link_info = resp->link_info;
1841 hw_link_info->an_info = resp->an_info;
1842 hw_link_info->ext_info = resp->ext_info;
639dc377 1843 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1844 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1845 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1846
c56999f9
CS		 1847 /* update fc info */
1848 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1849 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1850 if (tx_pause & rx_pause)
1851 hw->fc.current_mode = I40E_FC_FULL;
1852 else if (tx_pause)
1853 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1854 else if (rx_pause)
1855 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1856 else
1857 hw->fc.current_mode = I40E_FC_NONE;
1858
6bb3f23c
NP		 1859 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1860 hw_link_info->crc_enable = true;
1861 else
1862 hw_link_info->crc_enable = false;
56a62fc8
JB		 1863
1864 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1865 hw_link_info->lse_enable = true;
1866 else
1867 hw_link_info->lse_enable = false;
1868
088c4ee3
CS		 1869 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1870 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1871 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1872
56a62fc8
JB		 1873 /* save link status information */
1874 if (link)
d7595a22 1875 *link = *hw_link_info;
56a62fc8
JB		 1876
1877 /* flag cleared so helper functions don't call AQ again */
1878 hw->phy.get_link_info = false;
1879
1880aq_get_link_info_exit:
1881 return status;
1882}
1883
7e2453fe
JB		 1884/**
1885 * i40e_aq_set_phy_int_mask
1886 * @hw: pointer to the hw struct
1887 * @mask: interrupt mask to be set
1888 * @cmd_details: pointer to command details structure or NULL
1889 *
1890 * Set link interrupt mask.
1891 **/
1892i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1893 u16 mask,
1894 struct i40e_asq_cmd_details *cmd_details)
1895{
1896 struct i40e_aq_desc desc;
1897 struct i40e_aqc_set_phy_int_mask *cmd =
1898 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1899 i40e_status status;
1900
1901 i40e_fill_default_direct_cmd_desc(&desc,
1902 i40e_aqc_opc_set_phy_int_mask);
1903
1904 cmd->event_mask = cpu_to_le16(mask);
1905
1906 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1907
1908 return status;
1909}
1910
56a62fc8
JB		 1911/**
1912 * i40e_aq_add_vsi
1913 * @hw: pointer to the hw struct
98d44381 1914 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1915 * @cmd_details: pointer to command details structure or NULL
1916 *
1917 * Add a VSI context to the hardware.
1918**/
1919i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1920 struct i40e_vsi_context *vsi_ctx,
1921 struct i40e_asq_cmd_details *cmd_details)
1922{
1923 struct i40e_aq_desc desc;
1924 struct i40e_aqc_add_get_update_vsi *cmd =
1925 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1926 struct i40e_aqc_add_get_update_vsi_completion *resp =
1927 (struct i40e_aqc_add_get_update_vsi_completion *)
1928 &desc.params.raw;
1929 i40e_status status;
1930
1931 i40e_fill_default_direct_cmd_desc(&desc,
1932 i40e_aqc_opc_add_vsi);
1933
1934 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1935 cmd->connection_type = vsi_ctx->connection_type;
1936 cmd->vf_id = vsi_ctx->vf_num;
1937 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1938
1939 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1940
1941 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1942 sizeof(vsi_ctx->info), cmd_details);
1943
1944 if (status)
1945 goto aq_add_vsi_exit;
1946
1947 vsi_ctx->seid = le16_to_cpu(resp->seid);
1948 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1949 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1950 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1951
1952aq_add_vsi_exit:
1953 return status;
1954}
1955
1956/**
1957 * i40e_aq_set_vsi_unicast_promiscuous
1958 * @hw: pointer to the hw struct
1959 * @seid: vsi number
1960 * @set: set unicast promiscuous enable/disable
1961 * @cmd_details: pointer to command details structure or NULL
1962 **/
1963i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1964 u16 seid, bool set,
1965 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1966{
1967 struct i40e_aq_desc desc;
1968 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1969 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1970 i40e_status status;
1971 u16 flags = 0;
1972
1973 i40e_fill_default_direct_cmd_desc(&desc,
1974 i40e_aqc_opc_set_vsi_promiscuous_modes);
1975
1976 if (set)
1977 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1978
1979 cmd->promiscuous_flags = cpu_to_le16(flags);
1980
1981 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1982
1983 cmd->seid = cpu_to_le16(seid);
1984 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1985
1986 return status;
1987}
1988
1989/**
1990 * i40e_aq_set_vsi_multicast_promiscuous
1991 * @hw: pointer to the hw struct
1992 * @seid: vsi number
1993 * @set: set multicast promiscuous enable/disable
1994 * @cmd_details: pointer to command details structure or NULL
1995 **/
1996i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1997 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1998{
1999 struct i40e_aq_desc desc;
2000 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2001 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2002 i40e_status status;
2003 u16 flags = 0;
2004
2005 i40e_fill_default_direct_cmd_desc(&desc,
2006 i40e_aqc_opc_set_vsi_promiscuous_modes);
2007
2008 if (set)
2009 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2010
2011 cmd->promiscuous_flags = cpu_to_le16(flags);
2012
2013 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2014
2015 cmd->seid = cpu_to_le16(seid);
2016 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2017
2018 return status;
2019}
2020
2021/**
2022 * i40e_aq_set_vsi_broadcast
2023 * @hw: pointer to the hw struct
2024 * @seid: vsi number
2025 * @set_filter: true to set filter, false to clear filter
2026 * @cmd_details: pointer to command details structure or NULL
2027 *
2028 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2029 **/
2030i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2031 u16 seid, bool set_filter,
2032 struct i40e_asq_cmd_details *cmd_details)
2033{
2034 struct i40e_aq_desc desc;
2035 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2036 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2037 i40e_status status;
2038
2039 i40e_fill_default_direct_cmd_desc(&desc,
2040 i40e_aqc_opc_set_vsi_promiscuous_modes);
2041
2042 if (set_filter)
2043 cmd->promiscuous_flags
2044 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2045 else
2046 cmd->promiscuous_flags
2047 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2048
2049 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2050 cmd->seid = cpu_to_le16(seid);
2051 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2052
2053 return status;
2054}
2055
2056/**
2057 * i40e_get_vsi_params - get VSI configuration info
2058 * @hw: pointer to the hw struct
98d44381 2059 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2060 * @cmd_details: pointer to command details structure or NULL
2061 **/
2062i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2063 struct i40e_vsi_context *vsi_ctx,
2064 struct i40e_asq_cmd_details *cmd_details)
2065{
2066 struct i40e_aq_desc desc;
f5ac8579
SN		 2067 struct i40e_aqc_add_get_update_vsi *cmd =
2068 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 2069 struct i40e_aqc_add_get_update_vsi_completion *resp =
2070 (struct i40e_aqc_add_get_update_vsi_completion *)
2071 &desc.params.raw;
2072 i40e_status status;
2073
2074 i40e_fill_default_direct_cmd_desc(&desc,
2075 i40e_aqc_opc_get_vsi_parameters);
2076
f5ac8579 2077 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2078
2079 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 2080
2081 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2082 sizeof(vsi_ctx->info), NULL);
2083
2084 if (status)
2085 goto aq_get_vsi_params_exit;
2086
2087 vsi_ctx->seid = le16_to_cpu(resp->seid);
2088 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2089 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2090 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2091
2092aq_get_vsi_params_exit:
2093 return status;
2094}
2095
2096/**
2097 * i40e_aq_update_vsi_params
2098 * @hw: pointer to the hw struct
98d44381 2099 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2100 * @cmd_details: pointer to command details structure or NULL
2101 *
2102 * Update a VSI context.
2103 **/
2104i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2105 struct i40e_vsi_context *vsi_ctx,
2106 struct i40e_asq_cmd_details *cmd_details)
2107{
2108 struct i40e_aq_desc desc;
f5ac8579
SN		 2109 struct i40e_aqc_add_get_update_vsi *cmd =
2110 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 2111 i40e_status status;
2112
2113 i40e_fill_default_direct_cmd_desc(&desc,
2114 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 2115 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2116
2117 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 2118
2119 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2120 sizeof(vsi_ctx->info), cmd_details);
2121
2122 return status;
2123}
2124
2125/**
2126 * i40e_aq_get_switch_config
2127 * @hw: pointer to the hardware structure
2128 * @buf: pointer to the result buffer
2129 * @buf_size: length of input buffer
2130 * @start_seid: seid to start for the report, 0 == beginning
2131 * @cmd_details: pointer to command details structure or NULL
2132 *
2133 * Fill the buf with switch configuration returned from AdminQ command
2134 **/
2135i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2136 struct i40e_aqc_get_switch_config_resp *buf,
2137 u16 buf_size, u16 *start_seid,
2138 struct i40e_asq_cmd_details *cmd_details)
2139{
2140 struct i40e_aq_desc desc;
2141 struct i40e_aqc_switch_seid *scfg =
2142 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2143 i40e_status status;
2144
2145 i40e_fill_default_direct_cmd_desc(&desc,
2146 i40e_aqc_opc_get_switch_config);
2147 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2148 if (buf_size > I40E_AQ_LARGE_BUF)
2149 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2150 scfg->seid = cpu_to_le16(*start_seid);
2151
2152 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2153 *start_seid = le16_to_cpu(scfg->seid);
2154
2155 return status;
2156}
2157
2158/**
2159 * i40e_aq_get_firmware_version
2160 * @hw: pointer to the hw struct
2161 * @fw_major_version: firmware major version
2162 * @fw_minor_version: firmware minor version
7edf810c 2163 * @fw_build: firmware build number
56a62fc8
JB		 2164 * @api_major_version: major queue version
2165 * @api_minor_version: minor queue version
2166 * @cmd_details: pointer to command details structure or NULL
2167 *
2168 * Get the firmware version from the admin queue commands
2169 **/
2170i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2171 u16 *fw_major_version, u16 *fw_minor_version,
7edf810c 2172 u32 *fw_build,
56a62fc8
JB		 2173 u16 *api_major_version, u16 *api_minor_version,
2174 struct i40e_asq_cmd_details *cmd_details)
2175{
2176 struct i40e_aq_desc desc;
2177 struct i40e_aqc_get_version *resp =
2178 (struct i40e_aqc_get_version *)&desc.params.raw;
2179 i40e_status status;
2180
2181 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2182
2183 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2184
2185 if (!status) {
7edf810c 2186 if (fw_major_version)
56a62fc8 2187 *fw_major_version = le16_to_cpu(resp->fw_major);
7edf810c 2188 if (fw_minor_version)
56a62fc8 2189 *fw_minor_version = le16_to_cpu(resp->fw_minor);
7edf810c
SN		 2190 if (fw_build)
2191 *fw_build = le32_to_cpu(resp->fw_build);
2192 if (api_major_version)
56a62fc8 2193 *api_major_version = le16_to_cpu(resp->api_major);
7edf810c 2194 if (api_minor_version)
56a62fc8
JB		 2195 *api_minor_version = le16_to_cpu(resp->api_minor);
2196 }
2197
2198 return status;
2199}
2200
2201/**
2202 * i40e_aq_send_driver_version
2203 * @hw: pointer to the hw struct
56a62fc8
JB		 2204 * @dv: driver's major, minor version
2205 * @cmd_details: pointer to command details structure or NULL
2206 *
2207 * Send the driver version to the firmware
2208 **/
2209i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2210 struct i40e_driver_version *dv,
2211 struct i40e_asq_cmd_details *cmd_details)
2212{
2213 struct i40e_aq_desc desc;
2214 struct i40e_aqc_driver_version *cmd =
2215 (struct i40e_aqc_driver_version *)&desc.params.raw;
2216 i40e_status status;
9d2f98e1 2217 u16 len;
56a62fc8
JB		 2218
2219 if (dv == NULL)
2220 return I40E_ERR_PARAM;
2221
2222 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2223
3b38cd17 2224 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
56a62fc8
JB		 2225 cmd->driver_major_ver = dv->major_version;
2226 cmd->driver_minor_ver = dv->minor_version;
2227 cmd->driver_build_ver = dv->build_version;
2228 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 2229
2230 len = 0;
2231 while (len < sizeof(dv->driver_string) &&
2232 (dv->driver_string[len] < 0x80) &&
2233 dv->driver_string[len])
2234 len++;
2235 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2236 len, cmd_details);
56a62fc8
JB		 2237
2238 return status;
2239}
2240
2241/**
2242 * i40e_get_link_status - get status of the HW network link
2243 * @hw: pointer to the hw struct
a72a5abc 2244 * @link_up: pointer to bool (true/false = linkup/linkdown)
56a62fc8 2245 *
a72a5abc
JB		 2246 * Variable link_up true if link is up, false if link is down.
2247 * The variable link_up is invalid if returned value of status != 0
56a62fc8
JB		 2248 *
2249 * Side effect: LinkStatusEvent reporting becomes enabled
2250 **/
a72a5abc 2251i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
56a62fc8
JB		 2252{
2253 i40e_status status = 0;
56a62fc8
JB		 2254
2255 if (hw->phy.get_link_info) {
0a862b43 2256 status = i40e_update_link_info(hw);
56a62fc8
JB		 2257
2258 if (status)
a72a5abc
JB		 2259 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2260 status);
56a62fc8
JB		 2261 }
2262
a72a5abc 2263 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
56a62fc8 2264
a72a5abc 2265 return status;
56a62fc8
JB		 2266}
2267
0a862b43
CS		 2268/**
2269 * i40e_updatelink_status - update status of the HW network link
2270 * @hw: pointer to the hw struct
2271 **/
2272i40e_status i40e_update_link_info(struct i40e_hw *hw)
2273{
2274 struct i40e_aq_get_phy_abilities_resp abilities;
2275 i40e_status status = 0;
2276
2277 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2278 if (status)
2279 return status;
2280
8589af70
CW		 2281 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2282 status = i40e_aq_get_phy_capabilities(hw, false, false,
2283 &abilities, NULL);
2284 if (status)
2285 return status;
0a862b43 2286
8589af70
CW		 2287 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2288 sizeof(hw->phy.link_info.module_type));
2289 }
0a862b43
CS		 2290
2291 return status;
2292}
2293
56a62fc8
JB		 2294/**
2295 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2296 * @hw: pointer to the hw struct
2297 * @uplink_seid: the MAC or other gizmo SEID
2298 * @downlink_seid: the VSI SEID
2299 * @enabled_tc: bitmap of TCs to be enabled
2300 * @default_port: true for default port VSI, false for control port
e1c51b95 2301 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 2302 * @veb_seid: pointer to where to put the resulting VEB SEID
2303 * @cmd_details: pointer to command details structure or NULL
2304 *
2305 * This asks the FW to add a VEB between the uplink and downlink
2306 * elements. If the uplink SEID is 0, this will be a floating VEB.
2307 **/
2308i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2309 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 2310 bool default_port, bool enable_l2_filtering,
2311 u16 *veb_seid,
56a62fc8
JB		 2312 struct i40e_asq_cmd_details *cmd_details)
2313{
2314 struct i40e_aq_desc desc;
2315 struct i40e_aqc_add_veb *cmd =
2316 (struct i40e_aqc_add_veb *)&desc.params.raw;
2317 struct i40e_aqc_add_veb_completion *resp =
2318 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2319 i40e_status status;
2320 u16 veb_flags = 0;
2321
2322 /* SEIDs need to either both be set or both be 0 for floating VEB */
2323 if (!!uplink_seid != !!downlink_seid)
2324 return I40E_ERR_PARAM;
2325
2326 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2327
2328 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2329 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2330 cmd->enable_tcs = enabled_tc;
2331 if (!uplink_seid)
2332 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2333 if (default_port)
2334 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2335 else
2336 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 2337
2338 if (enable_l2_filtering)
2339 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2340
56a62fc8
JB		 2341 cmd->veb_flags = cpu_to_le16(veb_flags);
2342
2343 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2344
2345 if (!status && veb_seid)
2346 *veb_seid = le16_to_cpu(resp->veb_seid);
2347
2348 return status;
2349}
2350
2351/**
2352 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2353 * @hw: pointer to the hw struct
2354 * @veb_seid: the SEID of the VEB to query
2355 * @switch_id: the uplink switch id
98d44381 2356 * @floating: set to true if the VEB is floating
56a62fc8
JB		 2357 * @statistic_index: index of the stats counter block for this VEB
2358 * @vebs_used: number of VEB's used by function
98d44381 2359 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 2360 * @cmd_details: pointer to command details structure or NULL
2361 *
2362 * This retrieves the parameters for a particular VEB, specified by
2363 * uplink_seid, and returns them to the caller.
2364 **/
2365i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2366 u16 veb_seid, u16 *switch_id,
2367 bool *floating, u16 *statistic_index,
2368 u16 *vebs_used, u16 *vebs_free,
2369 struct i40e_asq_cmd_details *cmd_details)
2370{
2371 struct i40e_aq_desc desc;
2372 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2373 (struct i40e_aqc_get_veb_parameters_completion *)
2374 &desc.params.raw;
2375 i40e_status status;
2376
2377 if (veb_seid == 0)
2378 return I40E_ERR_PARAM;
2379
2380 i40e_fill_default_direct_cmd_desc(&desc,
2381 i40e_aqc_opc_get_veb_parameters);
2382 cmd_resp->seid = cpu_to_le16(veb_seid);
2383
2384 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2385 if (status)
2386 goto get_veb_exit;
2387
2388 if (switch_id)
2389 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2390 if (statistic_index)
2391 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2392 if (vebs_used)
2393 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2394 if (vebs_free)
2395 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2396 if (floating) {
2397 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
6995b36c 2398
56a62fc8
JB		 2399 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2400 *floating = true;
2401 else
2402 *floating = false;
2403 }
2404
2405get_veb_exit:
2406 return status;
2407}
2408
2409/**
2410 * i40e_aq_add_macvlan
2411 * @hw: pointer to the hw struct
2412 * @seid: VSI for the mac address
2413 * @mv_list: list of macvlans to be added
2414 * @count: length of the list
2415 * @cmd_details: pointer to command details structure or NULL
2416 *
2417 * Add MAC/VLAN addresses to the HW filtering
2418 **/
2419i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2420 struct i40e_aqc_add_macvlan_element_data *mv_list,
2421 u16 count, struct i40e_asq_cmd_details *cmd_details)
2422{
2423 struct i40e_aq_desc desc;
2424 struct i40e_aqc_macvlan *cmd =
2425 (struct i40e_aqc_macvlan *)&desc.params.raw;
2426 i40e_status status;
2427 u16 buf_size;
2428
2429 if (count == 0 || !mv_list || !hw)
2430 return I40E_ERR_PARAM;
2431
1efc80ee 2432 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2433
2434 /* prep the rest of the request */
2435 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2436 cmd->num_addresses = cpu_to_le16(count);
2437 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2438 cmd->seid[1] = 0;
2439 cmd->seid[2] = 0;
2440
2441 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2442 if (buf_size > I40E_AQ_LARGE_BUF)
2443 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2444
2445 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2446 cmd_details);
2447
2448 return status;
2449}
2450
2451/**
2452 * i40e_aq_remove_macvlan
2453 * @hw: pointer to the hw struct
2454 * @seid: VSI for the mac address
2455 * @mv_list: list of macvlans to be removed
2456 * @count: length of the list
2457 * @cmd_details: pointer to command details structure or NULL
2458 *
2459 * Remove MAC/VLAN addresses from the HW filtering
2460 **/
2461i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2462 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2463 u16 count, struct i40e_asq_cmd_details *cmd_details)
2464{
2465 struct i40e_aq_desc desc;
2466 struct i40e_aqc_macvlan *cmd =
2467 (struct i40e_aqc_macvlan *)&desc.params.raw;
2468 i40e_status status;
2469 u16 buf_size;
2470
2471 if (count == 0 || !mv_list || !hw)
2472 return I40E_ERR_PARAM;
2473
1efc80ee 2474 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2475
2476 /* prep the rest of the request */
2477 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2478 cmd->num_addresses = cpu_to_le16(count);
2479 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2480 cmd->seid[1] = 0;
2481 cmd->seid[2] = 0;
2482
2483 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2484 if (buf_size > I40E_AQ_LARGE_BUF)
2485 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2486
2487 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2488 cmd_details);
2489
2490 return status;
2491}
2492
56a62fc8
JB		 2493/**
2494 * i40e_aq_send_msg_to_vf
2495 * @hw: pointer to the hardware structure
b40c82e6 2496 * @vfid: VF id to send msg
98d44381
JK		 2497 * @v_opcode: opcodes for VF-PF communication
2498 * @v_retval: return error code
56a62fc8
JB		 2499 * @msg: pointer to the msg buffer
2500 * @msglen: msg length
2501 * @cmd_details: pointer to command details
2502 *
2503 * send msg to vf
2504 **/
2505i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2506 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2507 struct i40e_asq_cmd_details *cmd_details)
2508{
2509 struct i40e_aq_desc desc;
2510 struct i40e_aqc_pf_vf_message *cmd =
2511 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2512 i40e_status status;
2513
2514 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2515 cmd->id = cpu_to_le32(vfid);
2516 desc.cookie_high = cpu_to_le32(v_opcode);
2517 desc.cookie_low = cpu_to_le32(v_retval);
2518 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2519 if (msglen) {
2520 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2521 I40E_AQ_FLAG_RD));
2522 if (msglen > I40E_AQ_LARGE_BUF)
2523 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2524 desc.datalen = cpu_to_le16(msglen);
2525 }
2526 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2527
2528 return status;
2529}
2530
9fee9db5
SN		 2531/**
2532 * i40e_aq_debug_read_register
2533 * @hw: pointer to the hw struct
2534 * @reg_addr: register address
2535 * @reg_val: register value
2536 * @cmd_details: pointer to command details structure or NULL
2537 *
2538 * Read the register using the admin queue commands
2539 **/
2540i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
7b115dd0 2541 u32 reg_addr, u64 *reg_val,
9fee9db5
SN		 2542 struct i40e_asq_cmd_details *cmd_details)
2543{
2544 struct i40e_aq_desc desc;
2545 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2546 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2547 i40e_status status;
2548
2549 if (reg_val == NULL)
2550 return I40E_ERR_PARAM;
2551
7b115dd0 2552 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
9fee9db5
SN		 2553
2554 cmd_resp->address = cpu_to_le32(reg_addr);
2555
2556 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2557
2558 if (!status) {
7b115dd0
JB		 2559 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2560 (u64)le32_to_cpu(cmd_resp->value_low);
9fee9db5
SN		 2561 }
2562
2563 return status;
2564}
2565
53db45cd
SN		 2566/**
2567 * i40e_aq_debug_write_register
2568 * @hw: pointer to the hw struct
2569 * @reg_addr: register address
2570 * @reg_val: register value
2571 * @cmd_details: pointer to command details structure or NULL
2572 *
2573 * Write to a register using the admin queue commands
2574 **/
2575i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2576 u32 reg_addr, u64 reg_val,
2577 struct i40e_asq_cmd_details *cmd_details)
2578{
2579 struct i40e_aq_desc desc;
2580 struct i40e_aqc_debug_reg_read_write *cmd =
2581 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2582 i40e_status status;
2583
2584 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2585
2586 cmd->address = cpu_to_le32(reg_addr);
2587 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2588 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2589
2590 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2591
2592 return status;
2593}
2594
56a62fc8
JB		 2595/**
2596 * i40e_aq_set_hmc_resource_profile
2597 * @hw: pointer to the hw struct
2598 * @profile: type of profile the HMC is to be set as
2599 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2600 * @cmd_details: pointer to command details structure or NULL
2601 *
2602 * set the HMC profile of the device.
2603 **/
2604i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2605 enum i40e_aq_hmc_profile profile,
2606 u8 pe_vf_enabled_count,
2607 struct i40e_asq_cmd_details *cmd_details)
2608{
2609 struct i40e_aq_desc desc;
2610 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2611 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2612 i40e_status status;
2613
2614 i40e_fill_default_direct_cmd_desc(&desc,
2615 i40e_aqc_opc_set_hmc_resource_profile);
2616
2617 cmd->pm_profile = (u8)profile;
2618 cmd->pe_vf_enabled = pe_vf_enabled_count;
2619
2620 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2621
2622 return status;
2623}
2624
2625/**
2626 * i40e_aq_request_resource
2627 * @hw: pointer to the hw struct
2628 * @resource: resource id
2629 * @access: access type
2630 * @sdp_number: resource number
2631 * @timeout: the maximum time in ms that the driver may hold the resource
2632 * @cmd_details: pointer to command details structure or NULL
2633 *
2634 * requests common resource using the admin queue commands
2635 **/
2636i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2637 enum i40e_aq_resources_ids resource,
2638 enum i40e_aq_resource_access_type access,
2639 u8 sdp_number, u64 *timeout,
2640 struct i40e_asq_cmd_details *cmd_details)
2641{
2642 struct i40e_aq_desc desc;
2643 struct i40e_aqc_request_resource *cmd_resp =
2644 (struct i40e_aqc_request_resource *)&desc.params.raw;
2645 i40e_status status;
2646
2647 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2648
2649 cmd_resp->resource_id = cpu_to_le16(resource);
2650 cmd_resp->access_type = cpu_to_le16(access);
2651 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2652
2653 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2654 /* The completion specifies the maximum time in ms that the driver
2655 * may hold the resource in the Timeout field.
2656 * If the resource is held by someone else, the command completes with
2657 * busy return value and the timeout field indicates the maximum time
2658 * the current owner of the resource has to free it.
2659 */
2660 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2661 *timeout = le32_to_cpu(cmd_resp->timeout);
2662
2663 return status;
2664}
2665
2666/**
2667 * i40e_aq_release_resource
2668 * @hw: pointer to the hw struct
2669 * @resource: resource id
2670 * @sdp_number: resource number
2671 * @cmd_details: pointer to command details structure or NULL
2672 *
2673 * release common resource using the admin queue commands
2674 **/
2675i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2676 enum i40e_aq_resources_ids resource,
2677 u8 sdp_number,
2678 struct i40e_asq_cmd_details *cmd_details)
2679{
2680 struct i40e_aq_desc desc;
2681 struct i40e_aqc_request_resource *cmd =
2682 (struct i40e_aqc_request_resource *)&desc.params.raw;
2683 i40e_status status;
2684
2685 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2686
2687 cmd->resource_id = cpu_to_le16(resource);
2688 cmd->resource_number = cpu_to_le32(sdp_number);
2689
2690 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2691
2692 return status;
2693}
2694
2695/**
2696 * i40e_aq_read_nvm
2697 * @hw: pointer to the hw struct
2698 * @module_pointer: module pointer location in words from the NVM beginning
2699 * @offset: byte offset from the module beginning
2700 * @length: length of the section to be read (in bytes from the offset)
2701 * @data: command buffer (size [bytes] = length)
2702 * @last_command: tells if this is the last command in a series
2703 * @cmd_details: pointer to command details structure or NULL
2704 *
2705 * Read the NVM using the admin queue commands
2706 **/
2707i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2708 u32 offset, u16 length, void *data,
2709 bool last_command,
2710 struct i40e_asq_cmd_details *cmd_details)
2711{
2712 struct i40e_aq_desc desc;
2713 struct i40e_aqc_nvm_update *cmd =
2714 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2715 i40e_status status;
2716
2717 /* In offset the highest byte must be zeroed. */
2718 if (offset & 0xFF000000) {
2719 status = I40E_ERR_PARAM;
2720 goto i40e_aq_read_nvm_exit;
2721 }
2722
2723 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2724
2725 /* If this is the last command in a series, set the proper flag. */
2726 if (last_command)
2727 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2728 cmd->module_pointer = module_pointer;
2729 cmd->offset = cpu_to_le32(offset);
2730 cmd->length = cpu_to_le16(length);
2731
2732 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2733 if (length > I40E_AQ_LARGE_BUF)
2734 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2735
2736 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2737
2738i40e_aq_read_nvm_exit:
2739 return status;
2740}
2741
cd552cb4
SN		 2742/**
2743 * i40e_aq_erase_nvm
2744 * @hw: pointer to the hw struct
2745 * @module_pointer: module pointer location in words from the NVM beginning
2746 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2747 * @length: length of the section to be erased (expressed in 4 KB)
2748 * @last_command: tells if this is the last command in a series
2749 * @cmd_details: pointer to command details structure or NULL
2750 *
2751 * Erase the NVM sector using the admin queue commands
2752 **/
2753i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2754 u32 offset, u16 length, bool last_command,
2755 struct i40e_asq_cmd_details *cmd_details)
2756{
2757 struct i40e_aq_desc desc;
2758 struct i40e_aqc_nvm_update *cmd =
2759 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2760 i40e_status status;
2761
2762 /* In offset the highest byte must be zeroed. */
2763 if (offset & 0xFF000000) {
2764 status = I40E_ERR_PARAM;
2765 goto i40e_aq_erase_nvm_exit;
2766 }
2767
2768 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2769
2770 /* If this is the last command in a series, set the proper flag. */
2771 if (last_command)
2772 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2773 cmd->module_pointer = module_pointer;
2774 cmd->offset = cpu_to_le32(offset);
2775 cmd->length = cpu_to_le16(length);
2776
2777 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2778
2779i40e_aq_erase_nvm_exit:
2780 return status;
2781}
2782
56a62fc8
JB		 2783#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2784#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2785#define I40E_DEV_FUNC_CAP_NPAR 0x03
2786#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2787#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2788#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2789#define I40E_DEV_FUNC_CAP_VF 0x13
2790#define I40E_DEV_FUNC_CAP_VMDQ 0x14
2791#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2792#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2793#define I40E_DEV_FUNC_CAP_VSI 0x17
2794#define I40E_DEV_FUNC_CAP_DCB 0x18
2795#define I40E_DEV_FUNC_CAP_FCOE 0x21
63d7e5a4 2796#define I40E_DEV_FUNC_CAP_ISCSI 0x22
56a62fc8
JB		 2797#define I40E_DEV_FUNC_CAP_RSS 0x40
2798#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2799#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2800#define I40E_DEV_FUNC_CAP_MSIX 0x43
2801#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2802#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2803#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
c78b953e 2804#define I40E_DEV_FUNC_CAP_FLEX10 0xF1
56a62fc8
JB		 2805#define I40E_DEV_FUNC_CAP_CEM 0xF2
2806#define I40E_DEV_FUNC_CAP_IWARP 0x51
2807#define I40E_DEV_FUNC_CAP_LED 0x61
2808#define I40E_DEV_FUNC_CAP_SDP 0x62
2809#define I40E_DEV_FUNC_CAP_MDIO 0x63
73b23402 2810#define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
56a62fc8
JB		 2811
2812/**
2813 * i40e_parse_discover_capabilities
2814 * @hw: pointer to the hw struct
2815 * @buff: pointer to a buffer containing device/function capability records
2816 * @cap_count: number of capability records in the list
2817 * @list_type_opc: type of capabilities list to parse
2818 *
2819 * Parse the device/function capabilities list.
2820 **/
2821static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2822 u32 cap_count,
2823 enum i40e_admin_queue_opc list_type_opc)
2824{
2825 struct i40e_aqc_list_capabilities_element_resp *cap;
9fee9db5 2826 u32 valid_functions, num_functions;
56a62fc8
JB		 2827 u32 number, logical_id, phys_id;
2828 struct i40e_hw_capabilities *p;
c78b953e 2829 u8 major_rev;
56a62fc8
JB		 2830 u32 i = 0;
2831 u16 id;
2832
2833 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2834
2835 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 2836 p = &hw->dev_caps;
56a62fc8 2837 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 2838 p = &hw->func_caps;
56a62fc8
JB		 2839 else
2840 return;
2841
2842 for (i = 0; i < cap_count; i++, cap++) {
2843 id = le16_to_cpu(cap->id);
2844 number = le32_to_cpu(cap->number);
2845 logical_id = le32_to_cpu(cap->logical_id);
2846 phys_id = le32_to_cpu(cap->phys_id);
c78b953e 2847 major_rev = cap->major_rev;
56a62fc8
JB		 2848
2849 switch (id) {
2850 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2851 p->switch_mode = number;
2852 break;
2853 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2854 p->management_mode = number;
2855 break;
2856 case I40E_DEV_FUNC_CAP_NPAR:
2857 p->npar_enable = number;
2858 break;
2859 case I40E_DEV_FUNC_CAP_OS2BMC:
2860 p->os2bmc = number;
2861 break;
2862 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2863 p->valid_functions = number;
2864 break;
2865 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2866 if (number == 1)
2867 p->sr_iov_1_1 = true;
2868 break;
2869 case I40E_DEV_FUNC_CAP_VF:
2870 p->num_vfs = number;
2871 p->vf_base_id = logical_id;
2872 break;
2873 case I40E_DEV_FUNC_CAP_VMDQ:
2874 if (number == 1)
2875 p->vmdq = true;
2876 break;
2877 case I40E_DEV_FUNC_CAP_802_1_QBG:
2878 if (number == 1)
2879 p->evb_802_1_qbg = true;
2880 break;
2881 case I40E_DEV_FUNC_CAP_802_1_QBH:
2882 if (number == 1)
2883 p->evb_802_1_qbh = true;
2884 break;
2885 case I40E_DEV_FUNC_CAP_VSI:
2886 p->num_vsis = number;
2887 break;
2888 case I40E_DEV_FUNC_CAP_DCB:
2889 if (number == 1) {
2890 p->dcb = true;
2891 p->enabled_tcmap = logical_id;
2892 p->maxtc = phys_id;
2893 }
2894 break;
2895 case I40E_DEV_FUNC_CAP_FCOE:
2896 if (number == 1)
2897 p->fcoe = true;
2898 break;
63d7e5a4
NP		 2899 case I40E_DEV_FUNC_CAP_ISCSI:
2900 if (number == 1)
2901 p->iscsi = true;
2902 break;
56a62fc8
JB		 2903 case I40E_DEV_FUNC_CAP_RSS:
2904 p->rss = true;
e157ea30 2905 p->rss_table_size = number;
56a62fc8
JB		 2906 p->rss_table_entry_width = logical_id;
2907 break;
2908 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2909 p->num_rx_qp = number;
2910 p->base_queue = phys_id;
2911 break;
2912 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2913 p->num_tx_qp = number;
2914 p->base_queue = phys_id;
2915 break;
2916 case I40E_DEV_FUNC_CAP_MSIX:
2917 p->num_msix_vectors = number;
2918 break;
2919 case I40E_DEV_FUNC_CAP_MSIX_VF:
2920 p->num_msix_vectors_vf = number;
2921 break;
c78b953e
PO		 2922 case I40E_DEV_FUNC_CAP_FLEX10:
2923 if (major_rev == 1) {
2924 if (number == 1) {
2925 p->flex10_enable = true;
2926 p->flex10_capable = true;
2927 }
2928 } else {
2929 /* Capability revision >= 2 */
2930 if (number & 1)
2931 p->flex10_enable = true;
2932 if (number & 2)
2933 p->flex10_capable = true;
2934 }
2935 p->flex10_mode = logical_id;
2936 p->flex10_status = phys_id;
56a62fc8
JB		 2937 break;
2938 case I40E_DEV_FUNC_CAP_CEM:
2939 if (number == 1)
2940 p->mgmt_cem = true;
2941 break;
2942 case I40E_DEV_FUNC_CAP_IWARP:
2943 if (number == 1)
2944 p->iwarp = true;
2945 break;
2946 case I40E_DEV_FUNC_CAP_LED:
2947 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2948 p->led[phys_id] = true;
2949 break;
2950 case I40E_DEV_FUNC_CAP_SDP:
2951 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2952 p->sdp[phys_id] = true;
2953 break;
2954 case I40E_DEV_FUNC_CAP_MDIO:
2955 if (number == 1) {
2956 p->mdio_port_num = phys_id;
2957 p->mdio_port_mode = logical_id;
2958 }
2959 break;
2960 case I40E_DEV_FUNC_CAP_IEEE_1588:
2961 if (number == 1)
2962 p->ieee_1588 = true;
2963 break;
2964 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2965 p->fd = true;
2966 p->fd_filters_guaranteed = number;
2967 p->fd_filters_best_effort = logical_id;
2968 break;
73b23402
KS		 2969 case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
2970 p->wr_csr_prot = (u64)number;
2971 p->wr_csr_prot |= (u64)logical_id << 32;
2972 break;
56a62fc8
JB		 2973 default:
2974 break;
2975 }
2976 }
2977
f18ae100
VD		 2978 if (p->fcoe)
2979 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
2980
566bb85d
VD		 2981 /* Software override ensuring FCoE is disabled if npar or mfp
2982 * mode because it is not supported in these modes.
2983 */
c78b953e 2984 if (p->npar_enable || p->flex10_enable)
566bb85d
VD		 2985 p->fcoe = false;
2986
9fee9db5
SN		 2987 /* count the enabled ports (aka the "not disabled" ports) */
2988 hw->num_ports = 0;
2989 for (i = 0; i < 4; i++) {
2990 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2991 u64 port_cfg = 0;
2992
2993 /* use AQ read to get the physical register offset instead
2994 * of the port relative offset
2995 */
2996 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2997 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2998 hw->num_ports++;
2999 }
3000
3001 valid_functions = p->valid_functions;
3002 num_functions = 0;
3003 while (valid_functions) {
3004 if (valid_functions & 1)
3005 num_functions++;
3006 valid_functions >>= 1;
3007 }
3008
3009 /* partition id is 1-based, and functions are evenly spread
3010 * across the ports as partitions
3011 */
3012 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3013 hw->num_partitions = num_functions / hw->num_ports;
3014
56a62fc8
JB		 3015 /* additional HW specific goodies that might
3016 * someday be HW version specific
3017 */
3018 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3019}
3020
3021/**
3022 * i40e_aq_discover_capabilities
3023 * @hw: pointer to the hw struct
3024 * @buff: a virtual buffer to hold the capabilities
3025 * @buff_size: Size of the virtual buffer
3026 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3027 * @list_type_opc: capabilities type to discover - pass in the command opcode
3028 * @cmd_details: pointer to command details structure or NULL
3029 *
3030 * Get the device capabilities descriptions from the firmware
3031 **/
3032i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3033 void *buff, u16 buff_size, u16 *data_size,
3034 enum i40e_admin_queue_opc list_type_opc,
3035 struct i40e_asq_cmd_details *cmd_details)
3036{
3037 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 3038 struct i40e_aq_desc desc;
8fb905b3 3039 i40e_status status = 0;
56a62fc8
JB		 3040
3041 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3042
3043 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3044 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3045 status = I40E_ERR_PARAM;
3046 goto exit;
3047 }
3048
3049 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3050
3051 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3052 if (buff_size > I40E_AQ_LARGE_BUF)
3053 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3054
3055 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3056 *data_size = le16_to_cpu(desc.datalen);
3057
3058 if (status)
3059 goto exit;
3060
3061 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3062 list_type_opc);
3063
3064exit:
3065 return status;
3066}
3067
cd552cb4
SN		 3068/**
3069 * i40e_aq_update_nvm
3070 * @hw: pointer to the hw struct
3071 * @module_pointer: module pointer location in words from the NVM beginning
3072 * @offset: byte offset from the module beginning
3073 * @length: length of the section to be written (in bytes from the offset)
3074 * @data: command buffer (size [bytes] = length)
3075 * @last_command: tells if this is the last command in a series
3076 * @cmd_details: pointer to command details structure or NULL
3077 *
3078 * Update the NVM using the admin queue commands
3079 **/
3080i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3081 u32 offset, u16 length, void *data,
3082 bool last_command,
3083 struct i40e_asq_cmd_details *cmd_details)
3084{
3085 struct i40e_aq_desc desc;
3086 struct i40e_aqc_nvm_update *cmd =
3087 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3088 i40e_status status;
3089
3090 /* In offset the highest byte must be zeroed. */
3091 if (offset & 0xFF000000) {
3092 status = I40E_ERR_PARAM;
3093 goto i40e_aq_update_nvm_exit;
3094 }
3095
3096 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3097
3098 /* If this is the last command in a series, set the proper flag. */
3099 if (last_command)
3100 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3101 cmd->module_pointer = module_pointer;
3102 cmd->offset = cpu_to_le32(offset);
3103 cmd->length = cpu_to_le16(length);
3104
3105 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3106 if (length > I40E_AQ_LARGE_BUF)
3107 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3108
3109 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3110
3111i40e_aq_update_nvm_exit:
3112 return status;
3113}
3114
56a62fc8
JB		 3115/**
3116 * i40e_aq_get_lldp_mib
3117 * @hw: pointer to the hw struct
3118 * @bridge_type: type of bridge requested
3119 * @mib_type: Local, Remote or both Local and Remote MIBs
3120 * @buff: pointer to a user supplied buffer to store the MIB block
3121 * @buff_size: size of the buffer (in bytes)
3122 * @local_len : length of the returned Local LLDP MIB
3123 * @remote_len: length of the returned Remote LLDP MIB
3124 * @cmd_details: pointer to command details structure or NULL
3125 *
3126 * Requests the complete LLDP MIB (entire packet).
3127 **/
3128i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3129 u8 mib_type, void *buff, u16 buff_size,
3130 u16 *local_len, u16 *remote_len,
3131 struct i40e_asq_cmd_details *cmd_details)
3132{
3133 struct i40e_aq_desc desc;
3134 struct i40e_aqc_lldp_get_mib *cmd =
3135 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3136 struct i40e_aqc_lldp_get_mib *resp =
3137 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3138 i40e_status status;
3139
3140 if (buff_size == 0 || !buff)
3141 return I40E_ERR_PARAM;
3142
3143 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3144 /* Indirect Command */
3145 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3146
3147 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3148 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3149 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3150
3151 desc.datalen = cpu_to_le16(buff_size);
3152
3153 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3154 if (buff_size > I40E_AQ_LARGE_BUF)
3155 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3156
3157 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3158 if (!status) {
3159 if (local_len != NULL)
3160 *local_len = le16_to_cpu(resp->local_len);
3161 if (remote_len != NULL)
3162 *remote_len = le16_to_cpu(resp->remote_len);
3163 }
3164
3165 return status;
3166}
3167
3168/**
3169 * i40e_aq_cfg_lldp_mib_change_event
3170 * @hw: pointer to the hw struct
3171 * @enable_update: Enable or Disable event posting
3172 * @cmd_details: pointer to command details structure or NULL
3173 *
3174 * Enable or Disable posting of an event on ARQ when LLDP MIB
3175 * associated with the interface changes
3176 **/
3177i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3178 bool enable_update,
3179 struct i40e_asq_cmd_details *cmd_details)
3180{
3181 struct i40e_aq_desc desc;
3182 struct i40e_aqc_lldp_update_mib *cmd =
3183 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3184 i40e_status status;
3185
3186 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3187
3188 if (!enable_update)
3189 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3190
3191 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3192
3193 return status;
3194}
3195
3196/**
3197 * i40e_aq_stop_lldp
3198 * @hw: pointer to the hw struct
3199 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3200 * @cmd_details: pointer to command details structure or NULL
3201 *
3202 * Stop or Shutdown the embedded LLDP Agent
3203 **/
3204i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3205 struct i40e_asq_cmd_details *cmd_details)
3206{
3207 struct i40e_aq_desc desc;
3208 struct i40e_aqc_lldp_stop *cmd =
3209 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3210 i40e_status status;
3211
3212 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3213
3214 if (shutdown_agent)
3215 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3216
3217 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3218
3219 return status;
3220}
3221
3222/**
3223 * i40e_aq_start_lldp
3224 * @hw: pointer to the hw struct
3225 * @cmd_details: pointer to command details structure or NULL
3226 *
3227 * Start the embedded LLDP Agent on all ports.
3228 **/
3229i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3230 struct i40e_asq_cmd_details *cmd_details)
3231{
3232 struct i40e_aq_desc desc;
3233 struct i40e_aqc_lldp_start *cmd =
3234 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3235 i40e_status status;
3236
3237 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3238
3239 cmd->command = I40E_AQ_LLDP_AGENT_START;
3240
3241 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3242
3243 return status;
3244}
3245
9fa61dd2
NP		 3246/**
3247 * i40e_aq_get_cee_dcb_config
3248 * @hw: pointer to the hw struct
3249 * @buff: response buffer that stores CEE operational configuration
3250 * @buff_size: size of the buffer passed
3251 * @cmd_details: pointer to command details structure or NULL
3252 *
3253 * Get CEE DCBX mode operational configuration from firmware
3254 **/
3255i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3256 void *buff, u16 buff_size,
3257 struct i40e_asq_cmd_details *cmd_details)
3258{
3259 struct i40e_aq_desc desc;
3260 i40e_status status;
3261
3262 if (buff_size == 0 || !buff)
3263 return I40E_ERR_PARAM;
3264
3265 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3266
3267 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3268 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3269 cmd_details);
3270
3271 return status;
3272}
3273
a1c9a9d9
JK		 3274/**
3275 * i40e_aq_add_udp_tunnel
3276 * @hw: pointer to the hw struct
3277 * @udp_port: the UDP port to add
3278 * @header_len: length of the tunneling header length in DWords
3279 * @protocol_index: protocol index type
98d44381 3280 * @filter_index: pointer to filter index
a1c9a9d9
JK		 3281 * @cmd_details: pointer to command details structure or NULL
3282 **/
3283i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 3284 u16 udp_port, u8 protocol_index,
3285 u8 *filter_index,
a1c9a9d9
JK		 3286 struct i40e_asq_cmd_details *cmd_details)
3287{
3288 struct i40e_aq_desc desc;
3289 struct i40e_aqc_add_udp_tunnel *cmd =
3290 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3291 struct i40e_aqc_del_udp_tunnel_completion *resp =
3292 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3293 i40e_status status;
3294
3295 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3296
3297 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 3298 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 3299
3300 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3301
65d13461 3302 if (!status && filter_index)
a1c9a9d9
JK		 3303 *filter_index = resp->index;
3304
3305 return status;
3306}
3307
3308/**
3309 * i40e_aq_del_udp_tunnel
3310 * @hw: pointer to the hw struct
3311 * @index: filter index
3312 * @cmd_details: pointer to command details structure or NULL
3313 **/
3314i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3315 struct i40e_asq_cmd_details *cmd_details)
3316{
3317 struct i40e_aq_desc desc;
3318 struct i40e_aqc_remove_udp_tunnel *cmd =
3319 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3320 i40e_status status;
3321
3322 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3323
3324 cmd->index = index;
3325
3326 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3327
3328 return status;
3329}
3330
56a62fc8
JB		 3331/**
3332 * i40e_aq_delete_element - Delete switch element
3333 * @hw: pointer to the hw struct
3334 * @seid: the SEID to delete from the switch
3335 * @cmd_details: pointer to command details structure or NULL
3336 *
3337 * This deletes a switch element from the switch.
3338 **/
3339i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3340 struct i40e_asq_cmd_details *cmd_details)
3341{
3342 struct i40e_aq_desc desc;
3343 struct i40e_aqc_switch_seid *cmd =
3344 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3345 i40e_status status;
3346
3347 if (seid == 0)
3348 return I40E_ERR_PARAM;
3349
3350 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3351
3352 cmd->seid = cpu_to_le16(seid);
3353
3354 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3355
3356 return status;
3357}
3358
afb3ff0d
NP		 3359/**
3360 * i40e_aq_dcb_updated - DCB Updated Command
3361 * @hw: pointer to the hw struct
3362 * @cmd_details: pointer to command details structure or NULL
3363 *
3364 * EMP will return when the shared RPB settings have been
3365 * recomputed and modified. The retval field in the descriptor
3366 * will be set to 0 when RPB is modified.
3367 **/
3368i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3369 struct i40e_asq_cmd_details *cmd_details)
3370{
3371 struct i40e_aq_desc desc;
3372 i40e_status status;
3373
3374 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3375
3376 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3377
3378 return status;
3379}
3380
56a62fc8
JB		 3381/**
3382 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3383 * @hw: pointer to the hw struct
3384 * @seid: seid for the physical port/switching component/vsi
3385 * @buff: Indirect buffer to hold data parameters and response
3386 * @buff_size: Indirect buffer size
3387 * @opcode: Tx scheduler AQ command opcode
3388 * @cmd_details: pointer to command details structure or NULL
3389 *
3390 * Generic command handler for Tx scheduler AQ commands
3391 **/
3392static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3393 void *buff, u16 buff_size,
3394 enum i40e_admin_queue_opc opcode,
3395 struct i40e_asq_cmd_details *cmd_details)
3396{
3397 struct i40e_aq_desc desc;
3398 struct i40e_aqc_tx_sched_ind *cmd =
3399 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3400 i40e_status status;
3401 bool cmd_param_flag = false;
3402
3403 switch (opcode) {
3404 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3405 case i40e_aqc_opc_configure_vsi_tc_bw:
3406 case i40e_aqc_opc_enable_switching_comp_ets:
3407 case i40e_aqc_opc_modify_switching_comp_ets:
3408 case i40e_aqc_opc_disable_switching_comp_ets:
3409 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3410 case i40e_aqc_opc_configure_switching_comp_bw_config:
3411 cmd_param_flag = true;
3412 break;
3413 case i40e_aqc_opc_query_vsi_bw_config:
3414 case i40e_aqc_opc_query_vsi_ets_sla_config:
3415 case i40e_aqc_opc_query_switching_comp_ets_config:
3416 case i40e_aqc_opc_query_port_ets_config:
3417 case i40e_aqc_opc_query_switching_comp_bw_config:
3418 cmd_param_flag = false;
3419 break;
3420 default:
3421 return I40E_ERR_PARAM;
3422 }
3423
3424 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3425
3426 /* Indirect command */
3427 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3428 if (cmd_param_flag)
3429 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3430 if (buff_size > I40E_AQ_LARGE_BUF)
3431 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3432
3433 desc.datalen = cpu_to_le16(buff_size);
3434
3435 cmd->vsi_seid = cpu_to_le16(seid);
3436
3437 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3438
3439 return status;
3440}
3441
6b192891
MW		 3442/**
3443 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3444 * @hw: pointer to the hw struct
3445 * @seid: VSI seid
3446 * @credit: BW limit credits (0 = disabled)
3447 * @max_credit: Max BW limit credits
3448 * @cmd_details: pointer to command details structure or NULL
3449 **/
3450i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3451 u16 seid, u16 credit, u8 max_credit,
3452 struct i40e_asq_cmd_details *cmd_details)
3453{
3454 struct i40e_aq_desc desc;
3455 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3456 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3457 i40e_status status;
3458
3459 i40e_fill_default_direct_cmd_desc(&desc,
3460 i40e_aqc_opc_configure_vsi_bw_limit);
3461
3462 cmd->vsi_seid = cpu_to_le16(seid);
3463 cmd->credit = cpu_to_le16(credit);
3464 cmd->max_credit = max_credit;
3465
3466 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3467
3468 return status;
3469}
3470
56a62fc8
JB		 3471/**
3472 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3473 * @hw: pointer to the hw struct
3474 * @seid: VSI seid
3475 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3476 * @cmd_details: pointer to command details structure or NULL
3477 **/
3478i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3479 u16 seid,
3480 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3481 struct i40e_asq_cmd_details *cmd_details)
3482{
3483 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3484 i40e_aqc_opc_configure_vsi_tc_bw,
3485 cmd_details);
3486}
3487
afb3ff0d
NP		 3488/**
3489 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3490 * @hw: pointer to the hw struct
3491 * @seid: seid of the switching component connected to Physical Port
3492 * @ets_data: Buffer holding ETS parameters
3493 * @cmd_details: pointer to command details structure or NULL
3494 **/
3495i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3496 u16 seid,
3497 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3498 enum i40e_admin_queue_opc opcode,
3499 struct i40e_asq_cmd_details *cmd_details)
3500{
3501 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3502 sizeof(*ets_data), opcode, cmd_details);
3503}
3504
3505/**
3506 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3507 * @hw: pointer to the hw struct
3508 * @seid: seid of the switching component
3509 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3510 * @cmd_details: pointer to command details structure or NULL
3511 **/
3512i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3513 u16 seid,
3514 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3515 struct i40e_asq_cmd_details *cmd_details)
3516{
3517 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3518 i40e_aqc_opc_configure_switching_comp_bw_config,
3519 cmd_details);
3520}
3521
56a62fc8
JB		 3522/**
3523 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3524 * @hw: pointer to the hw struct
3525 * @seid: seid of the VSI
3526 * @bw_data: Buffer to hold VSI BW configuration
3527 * @cmd_details: pointer to command details structure or NULL
3528 **/
3529i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3530 u16 seid,
3531 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3532 struct i40e_asq_cmd_details *cmd_details)
3533{
3534 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3535 i40e_aqc_opc_query_vsi_bw_config,
3536 cmd_details);
3537}
3538
3539/**
3540 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3541 * @hw: pointer to the hw struct
3542 * @seid: seid of the VSI
3543 * @bw_data: Buffer to hold VSI BW configuration per TC
3544 * @cmd_details: pointer to command details structure or NULL
3545 **/
3546i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3547 u16 seid,
3548 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3549 struct i40e_asq_cmd_details *cmd_details)
3550{
3551 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3552 i40e_aqc_opc_query_vsi_ets_sla_config,
3553 cmd_details);
3554}
3555
3556/**
3557 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3558 * @hw: pointer to the hw struct
3559 * @seid: seid of the switching component
3560 * @bw_data: Buffer to hold switching component's per TC BW config
3561 * @cmd_details: pointer to command details structure or NULL
3562 **/
3563i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3564 u16 seid,
3565 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3566 struct i40e_asq_cmd_details *cmd_details)
3567{
3568 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3569 i40e_aqc_opc_query_switching_comp_ets_config,
3570 cmd_details);
3571}
3572
3573/**
3574 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3575 * @hw: pointer to the hw struct
3576 * @seid: seid of the VSI or switching component connected to Physical Port
3577 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3578 * @cmd_details: pointer to command details structure or NULL
3579 **/
3580i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3581 u16 seid,
3582 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3583 struct i40e_asq_cmd_details *cmd_details)
3584{
3585 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3586 i40e_aqc_opc_query_port_ets_config,
3587 cmd_details);
3588}
3589
3590/**
3591 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3592 * @hw: pointer to the hw struct
3593 * @seid: seid of the switching component
3594 * @bw_data: Buffer to hold switching component's BW configuration
3595 * @cmd_details: pointer to command details structure or NULL
3596 **/
3597i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3598 u16 seid,
3599 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3600 struct i40e_asq_cmd_details *cmd_details)
3601{
3602 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3603 i40e_aqc_opc_query_switching_comp_bw_config,
3604 cmd_details);
3605}
3606
3607/**
3608 * i40e_validate_filter_settings
3609 * @hw: pointer to the hardware structure
3610 * @settings: Filter control settings
3611 *
3612 * Check and validate the filter control settings passed.
3613 * The function checks for the valid filter/context sizes being
3614 * passed for FCoE and PE.
3615 *
3616 * Returns 0 if the values passed are valid and within
3617 * range else returns an error.
3618 **/
3619static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3620 struct i40e_filter_control_settings *settings)
3621{
3622 u32 fcoe_cntx_size, fcoe_filt_size;
3623 u32 pe_cntx_size, pe_filt_size;
467d729a 3624 u32 fcoe_fmax;
56a62fc8
JB		 3625 u32 val;
3626
3627 /* Validate FCoE settings passed */
3628 switch (settings->fcoe_filt_num) {
3629 case I40E_HASH_FILTER_SIZE_1K:
3630 case I40E_HASH_FILTER_SIZE_2K:
3631 case I40E_HASH_FILTER_SIZE_4K:
3632 case I40E_HASH_FILTER_SIZE_8K:
3633 case I40E_HASH_FILTER_SIZE_16K:
3634 case I40E_HASH_FILTER_SIZE_32K:
3635 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3636 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3637 break;
3638 default:
3639 return I40E_ERR_PARAM;
3640 }
3641
3642 switch (settings->fcoe_cntx_num) {
3643 case I40E_DMA_CNTX_SIZE_512:
3644 case I40E_DMA_CNTX_SIZE_1K:
3645 case I40E_DMA_CNTX_SIZE_2K:
3646 case I40E_DMA_CNTX_SIZE_4K:
3647 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3648 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3649 break;
3650 default:
3651 return I40E_ERR_PARAM;
3652 }
3653
3654 /* Validate PE settings passed */
3655 switch (settings->pe_filt_num) {
3656 case I40E_HASH_FILTER_SIZE_1K:
3657 case I40E_HASH_FILTER_SIZE_2K:
3658 case I40E_HASH_FILTER_SIZE_4K:
3659 case I40E_HASH_FILTER_SIZE_8K:
3660 case I40E_HASH_FILTER_SIZE_16K:
3661 case I40E_HASH_FILTER_SIZE_32K:
3662 case I40E_HASH_FILTER_SIZE_64K:
3663 case I40E_HASH_FILTER_SIZE_128K:
3664 case I40E_HASH_FILTER_SIZE_256K:
3665 case I40E_HASH_FILTER_SIZE_512K:
3666 case I40E_HASH_FILTER_SIZE_1M:
3667 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3668 pe_filt_size <<= (u32)settings->pe_filt_num;
3669 break;
3670 default:
3671 return I40E_ERR_PARAM;
3672 }
3673
3674 switch (settings->pe_cntx_num) {
3675 case I40E_DMA_CNTX_SIZE_512:
3676 case I40E_DMA_CNTX_SIZE_1K:
3677 case I40E_DMA_CNTX_SIZE_2K:
3678 case I40E_DMA_CNTX_SIZE_4K:
3679 case I40E_DMA_CNTX_SIZE_8K:
3680 case I40E_DMA_CNTX_SIZE_16K:
3681 case I40E_DMA_CNTX_SIZE_32K:
3682 case I40E_DMA_CNTX_SIZE_64K:
3683 case I40E_DMA_CNTX_SIZE_128K:
3684 case I40E_DMA_CNTX_SIZE_256K:
3685 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3686 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3687 break;
3688 default:
3689 return I40E_ERR_PARAM;
3690 }
3691
3692 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3693 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3694 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3695 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3696 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3697 return I40E_ERR_INVALID_SIZE;
3698
56a62fc8
JB		 3699 return 0;
3700}
3701
3702/**
3703 * i40e_set_filter_control
3704 * @hw: pointer to the hardware structure
3705 * @settings: Filter control settings
3706 *
3707 * Set the Queue Filters for PE/FCoE and enable filters required
3708 * for a single PF. It is expected that these settings are programmed
3709 * at the driver initialization time.
3710 **/
3711i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3712 struct i40e_filter_control_settings *settings)
3713{
3714 i40e_status ret = 0;
3715 u32 hash_lut_size = 0;
3716 u32 val;
3717
3718 if (!settings)
3719 return I40E_ERR_PARAM;
3720
3721 /* Validate the input settings */
3722 ret = i40e_validate_filter_settings(hw, settings);
3723 if (ret)
3724 return ret;
3725
3726 /* Read the PF Queue Filter control register */
3727 val = rd32(hw, I40E_PFQF_CTL_0);
3728
3729 /* Program required PE hash buckets for the PF */
3730 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3731 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3732 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3733 /* Program required PE contexts for the PF */
3734 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3735 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3736 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3737
3738 /* Program required FCoE hash buckets for the PF */
3739 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3740 val |= ((u32)settings->fcoe_filt_num <<
3741 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3742 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3743 /* Program required FCoE DDP contexts for the PF */
3744 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3745 val |= ((u32)settings->fcoe_cntx_num <<
3746 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3747 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3748
3749 /* Program Hash LUT size for the PF */
3750 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3751 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3752 hash_lut_size = 1;
3753 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3754 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3755
3756 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3757 if (settings->enable_fdir)
3758 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3759 if (settings->enable_ethtype)
3760 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3761 if (settings->enable_macvlan)
3762 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3763
3764 wr32(hw, I40E_PFQF_CTL_0, val);
3765
3766 return 0;
3767}
afb3ff0d
NP		 3768
3769/**
3770 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3771 * @hw: pointer to the hw struct
3772 * @mac_addr: MAC address to use in the filter
3773 * @ethtype: Ethertype to use in the filter
3774 * @flags: Flags that needs to be applied to the filter
3775 * @vsi_seid: seid of the control VSI
3776 * @queue: VSI queue number to send the packet to
3777 * @is_add: Add control packet filter if True else remove
3778 * @stats: Structure to hold information on control filter counts
3779 * @cmd_details: pointer to command details structure or NULL
3780 *
3781 * This command will Add or Remove control packet filter for a control VSI.
3782 * In return it will update the total number of perfect filter count in
3783 * the stats member.
3784 **/
3785i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3786 u8 *mac_addr, u16 ethtype, u16 flags,
3787 u16 vsi_seid, u16 queue, bool is_add,
3788 struct i40e_control_filter_stats *stats,
3789 struct i40e_asq_cmd_details *cmd_details)
3790{
3791 struct i40e_aq_desc desc;
3792 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3793 (struct i40e_aqc_add_remove_control_packet_filter *)
3794 &desc.params.raw;
3795 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3796 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3797 &desc.params.raw;
3798 i40e_status status;
3799
3800 if (vsi_seid == 0)
3801 return I40E_ERR_PARAM;
3802
3803 if (is_add) {
3804 i40e_fill_default_direct_cmd_desc(&desc,
3805 i40e_aqc_opc_add_control_packet_filter);
3806 cmd->queue = cpu_to_le16(queue);
3807 } else {
3808 i40e_fill_default_direct_cmd_desc(&desc,
3809 i40e_aqc_opc_remove_control_packet_filter);
3810 }
3811
3812 if (mac_addr)
6995b36c 3813 ether_addr_copy(cmd->mac, mac_addr);
afb3ff0d
NP		 3814
3815 cmd->etype = cpu_to_le16(ethtype);
3816 cmd->flags = cpu_to_le16(flags);
3817 cmd->seid = cpu_to_le16(vsi_seid);
3818
3819 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3820
3821 if (!status && stats) {
3822 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3823 stats->etype_used = le16_to_cpu(resp->etype_used);
3824 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3825 stats->etype_free = le16_to_cpu(resp->etype_free);
3826 }
3827
3828 return status;
3829}
3830
e7358f54
ASJ		 3831/**
3832 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3833 * @hw: pointer to the hw struct
3834 * @seid: VSI seid to add ethertype filter from
3835 **/
3836#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3837void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
3838 u16 seid)
3839{
3840 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
3841 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
3842 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
3843 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
3844 i40e_status status;
3845
3846 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
3847 seid, 0, true, NULL,
3848 NULL);
3849 if (status)
3850 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
3851}
3852
f4492db1
GR		 3853/**
3854 * i40e_aq_alternate_read
3855 * @hw: pointer to the hardware structure
3856 * @reg_addr0: address of first dword to be read
3857 * @reg_val0: pointer for data read from 'reg_addr0'
3858 * @reg_addr1: address of second dword to be read
3859 * @reg_val1: pointer for data read from 'reg_addr1'
3860 *
3861 * Read one or two dwords from alternate structure. Fields are indicated
3862 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3863 * is not passed then only register at 'reg_addr0' is read.
3864 *
3865 **/
37a2973a
SN		 3866static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
3867 u32 reg_addr0, u32 *reg_val0,
3868 u32 reg_addr1, u32 *reg_val1)
f4492db1
GR		 3869{
3870 struct i40e_aq_desc desc;
3871 struct i40e_aqc_alternate_write *cmd_resp =
3872 (struct i40e_aqc_alternate_write *)&desc.params.raw;
3873 i40e_status status;
3874
3875 if (!reg_val0)
3876 return I40E_ERR_PARAM;
3877
3878 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
3879 cmd_resp->address0 = cpu_to_le32(reg_addr0);
3880 cmd_resp->address1 = cpu_to_le32(reg_addr1);
3881
3882 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3883
3884 if (!status) {
3885 *reg_val0 = le32_to_cpu(cmd_resp->data0);
3886
3887 if (reg_val1)
3888 *reg_val1 = le32_to_cpu(cmd_resp->data1);
3889 }
3890
3891 return status;
3892}
3893
2fd75f31
NP		 3894/**
3895 * i40e_aq_resume_port_tx
3896 * @hw: pointer to the hardware structure
3897 * @cmd_details: pointer to command details structure or NULL
3898 *
3899 * Resume port's Tx traffic
3900 **/
3901i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3902 struct i40e_asq_cmd_details *cmd_details)
3903{
3904 struct i40e_aq_desc desc;
3905 i40e_status status;
3906
3907 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3908
3909 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3910
3911 return status;
3912}
3913
d4dfb81a
CS		 3914/**
3915 * i40e_set_pci_config_data - store PCI bus info
3916 * @hw: pointer to hardware structure
3917 * @link_status: the link status word from PCI config space
3918 *
3919 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3920 **/
3921void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3922{
3923 hw->bus.type = i40e_bus_type_pci_express;
3924
3925 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3926 case PCI_EXP_LNKSTA_NLW_X1:
3927 hw->bus.width = i40e_bus_width_pcie_x1;
3928 break;
3929 case PCI_EXP_LNKSTA_NLW_X2:
3930 hw->bus.width = i40e_bus_width_pcie_x2;
3931 break;
3932 case PCI_EXP_LNKSTA_NLW_X4:
3933 hw->bus.width = i40e_bus_width_pcie_x4;
3934 break;
3935 case PCI_EXP_LNKSTA_NLW_X8:
3936 hw->bus.width = i40e_bus_width_pcie_x8;
3937 break;
3938 default:
3939 hw->bus.width = i40e_bus_width_unknown;
3940 break;
3941 }
3942
3943 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3944 case PCI_EXP_LNKSTA_CLS_2_5GB:
3945 hw->bus.speed = i40e_bus_speed_2500;
3946 break;
3947 case PCI_EXP_LNKSTA_CLS_5_0GB:
3948 hw->bus.speed = i40e_bus_speed_5000;
3949 break;
3950 case PCI_EXP_LNKSTA_CLS_8_0GB:
3951 hw->bus.speed = i40e_bus_speed_8000;
3952 break;
3953 default:
3954 hw->bus.speed = i40e_bus_speed_unknown;
3955 break;
3956 }
3957}
f4492db1 3958
3169c323
JB		 3959/**
3960 * i40e_aq_debug_dump
3961 * @hw: pointer to the hardware structure
3962 * @cluster_id: specific cluster to dump
3963 * @table_id: table id within cluster
3964 * @start_index: index of line in the block to read
3965 * @buff_size: dump buffer size
3966 * @buff: dump buffer
3967 * @ret_buff_size: actual buffer size returned
3968 * @ret_next_table: next block to read
3969 * @ret_next_index: next index to read
3970 *
3971 * Dump internal FW/HW data for debug purposes.
3972 *
3973 **/
3974i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
3975 u8 table_id, u32 start_index, u16 buff_size,
3976 void *buff, u16 *ret_buff_size,
3977 u8 *ret_next_table, u32 *ret_next_index,
3978 struct i40e_asq_cmd_details *cmd_details)
3979{
3980 struct i40e_aq_desc desc;
3981 struct i40e_aqc_debug_dump_internals *cmd =
3982 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3983 struct i40e_aqc_debug_dump_internals *resp =
3984 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3985 i40e_status status;
3986
3987 if (buff_size == 0 || !buff)
3988 return I40E_ERR_PARAM;
3989
3990 i40e_fill_default_direct_cmd_desc(&desc,
3991 i40e_aqc_opc_debug_dump_internals);
3992 /* Indirect Command */
3993 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3994 if (buff_size > I40E_AQ_LARGE_BUF)
3995 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3996
3997 cmd->cluster_id = cluster_id;
3998 cmd->table_id = table_id;
3999 cmd->idx = cpu_to_le32(start_index);
4000
4001 desc.datalen = cpu_to_le16(buff_size);
4002
4003 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4004 if (!status) {
4005 if (ret_buff_size)
4006 *ret_buff_size = le16_to_cpu(desc.datalen);
4007 if (ret_next_table)
4008 *ret_next_table = resp->table_id;
4009 if (ret_next_index)
4010 *ret_next_index = le32_to_cpu(resp->idx);
4011 }
4012
4013 return status;
4014}
4015
f4492db1
GR		 4016/**
4017 * i40e_read_bw_from_alt_ram
4018 * @hw: pointer to the hardware structure
4019 * @max_bw: pointer for max_bw read
4020 * @min_bw: pointer for min_bw read
4021 * @min_valid: pointer for bool that is true if min_bw is a valid value
4022 * @max_valid: pointer for bool that is true if max_bw is a valid value
4023 *
4024 * Read bw from the alternate ram for the given pf
4025 **/
4026i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4027 u32 *max_bw, u32 *min_bw,
4028 bool *min_valid, bool *max_valid)
4029{
4030 i40e_status status;
4031 u32 max_bw_addr, min_bw_addr;
4032
4033 /* Calculate the address of the min/max bw registers */
4034 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4035 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4036 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4037 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4038 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4039 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4040
4041 /* Read the bandwidths from alt ram */
4042 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4043 min_bw_addr, min_bw);
4044
4045 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4046 *min_valid = true;
4047 else
4048 *min_valid = false;
4049
4050 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4051 *max_valid = true;
4052 else
4053 *max_valid = false;
4054
4055 return status;
4056}
4057
4058/**
4059 * i40e_aq_configure_partition_bw
4060 * @hw: pointer to the hardware structure
4061 * @bw_data: Buffer holding valid pfs and bw limits
4062 * @cmd_details: pointer to command details
4063 *
4064 * Configure partitions guaranteed/max bw
4065 **/
4066i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4067 struct i40e_aqc_configure_partition_bw_data *bw_data,
4068 struct i40e_asq_cmd_details *cmd_details)
4069{
4070 i40e_status status;
4071 struct i40e_aq_desc desc;
4072 u16 bwd_size = sizeof(*bw_data);
4073
4074 i40e_fill_default_direct_cmd_desc(&desc,
4075 i40e_aqc_opc_configure_partition_bw);
4076
4077 /* Indirect command */
4078 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4079 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4080
4081 if (bwd_size > I40E_AQ_LARGE_BUF)
4082 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4083
4084 desc.datalen = cpu_to_le16(bwd_size);
4085
4086 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4087 cmd_details);
4088
4089 return status;
4090}
Linux kernel - Deliverables
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