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i40e: Resume Port Tx after DCB event
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e
SN		 46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
ab60085e
SN		 50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
5960d33f 53 case I40E_DEV_ID_10G_BASE_T:
56a62fc8
JB		 54 hw->mac.type = I40E_MAC_XL710;
55 break;
ab60085e
SN		 56 case I40E_DEV_ID_VF:
57 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 58 hw->mac.type = I40E_MAC_VF;
59 break;
60 default:
61 hw->mac.type = I40E_MAC_GENERIC;
62 break;
63 }
64 } else {
65 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
66 }
67
68 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
69 hw->mac.type, status);
70 return status;
71}
72
73/**
74 * i40e_debug_aq
75 * @hw: debug mask related to admin queue
98d44381
JK		 76 * @mask: debug mask
77 * @desc: pointer to admin queue descriptor
56a62fc8 78 * @buffer: pointer to command buffer
f905dd62 79 * @buf_len: max length of buffer
56a62fc8
JB		 80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
f905dd62 84 void *buffer, u16 buf_len)
56a62fc8
JB		 85{
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
f905dd62 87 u16 len = le16_to_cpu(aq_desc->datalen);
56a62fc8
JB		 88 u8 *aq_buffer = (u8 *)buffer;
89 u32 data[4];
90 u32 i = 0;
91
92 if ((!(mask & hw->debug_mask)) || (desc == NULL))
93 return;
94
95 i40e_debug(hw, mask,
96 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
97 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
98 aq_desc->retval);
99 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
100 aq_desc->cookie_high, aq_desc->cookie_low);
101 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
102 aq_desc->params.internal.param0,
103 aq_desc->params.internal.param1);
104 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
105 aq_desc->params.external.addr_high,
106 aq_desc->params.external.addr_low);
107
108 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
109 memset(data, 0, sizeof(data));
110 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
f905dd62
SN		 111 if (buf_len < len)
112 len = buf_len;
113 for (i = 0; i < len; i++) {
56a62fc8
JB		 114 data[((i % 16) / 4)] |=
115 ((u32)aq_buffer[i]) << (8 * (i % 4));
116 if ((i % 16) == 15) {
117 i40e_debug(hw, mask,
118 "\t0x%04X %08X %08X %08X %08X\n",
119 i - 15, data[0], data[1], data[2],
120 data[3]);
121 memset(data, 0, sizeof(data));
122 }
123 }
124 if ((i % 16) != 0)
125 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
126 i - (i % 16), data[0], data[1], data[2],
127 data[3]);
128 }
129}
130
e1860d8f
ASJ		 131/**
132 * i40e_check_asq_alive
133 * @hw: pointer to the hw struct
134 *
135 * Returns true if Queue is enabled else false.
136 **/
137bool i40e_check_asq_alive(struct i40e_hw *hw)
138{
8b833b4f
KS		 139 if (hw->aq.asq.len)
140 return !!(rd32(hw, hw->aq.asq.len) &
141 I40E_PF_ATQLEN_ATQENABLE_MASK);
142 else
143 return false;
e1860d8f
ASJ		 144}
145
146/**
147 * i40e_aq_queue_shutdown
148 * @hw: pointer to the hw struct
149 * @unloading: is the driver unloading itself
150 *
151 * Tell the Firmware that we're shutting down the AdminQ and whether
152 * or not the driver is unloading as well.
153 **/
154i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
155 bool unloading)
156{
157 struct i40e_aq_desc desc;
158 struct i40e_aqc_queue_shutdown *cmd =
159 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
160 i40e_status status;
161
162 i40e_fill_default_direct_cmd_desc(&desc,
163 i40e_aqc_opc_queue_shutdown);
164
165 if (unloading)
166 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
167 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
168
169 return status;
170}
171
206812b5
JB		 172/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
173 * hardware to a bit-field that can be used by SW to more easily determine the
174 * packet type.
175 *
176 * Macros are used to shorten the table lines and make this table human
177 * readable.
178 *
179 * We store the PTYPE in the top byte of the bit field - this is just so that
180 * we can check that the table doesn't have a row missing, as the index into
181 * the table should be the PTYPE.
182 *
183 * Typical work flow:
184 *
185 * IF NOT i40e_ptype_lookup[ptype].known
186 * THEN
187 * Packet is unknown
188 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
189 * Use the rest of the fields to look at the tunnels, inner protocols, etc
190 * ELSE
191 * Use the enum i40e_rx_l2_ptype to decode the packet type
192 * ENDIF
193 */
194
195/* macro to make the table lines short */
196#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
197 { PTYPE, \
198 1, \
199 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
200 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
201 I40E_RX_PTYPE_##OUTER_FRAG, \
202 I40E_RX_PTYPE_TUNNEL_##T, \
203 I40E_RX_PTYPE_TUNNEL_END_##TE, \
204 I40E_RX_PTYPE_##TEF, \
205 I40E_RX_PTYPE_INNER_PROT_##I, \
206 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
207
208#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
209 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
210
211/* shorter macros makes the table fit but are terse */
212#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
213#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
214#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
215
216/* Lookup table mapping the HW PTYPE to the bit field for decoding */
217struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
218 /* L2 Packet types */
219 I40E_PTT_UNUSED_ENTRY(0),
220 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
222 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
223 I40E_PTT_UNUSED_ENTRY(4),
224 I40E_PTT_UNUSED_ENTRY(5),
225 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
226 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
227 I40E_PTT_UNUSED_ENTRY(8),
228 I40E_PTT_UNUSED_ENTRY(9),
229 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
230 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
231 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
238 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241
242 /* Non Tunneled IPv4 */
243 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
246 I40E_PTT_UNUSED_ENTRY(25),
247 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
248 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
249 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
250
251 /* IPv4 --> IPv4 */
252 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
253 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
254 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
255 I40E_PTT_UNUSED_ENTRY(32),
256 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
257 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
258 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
259
260 /* IPv4 --> IPv6 */
261 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
262 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
263 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
264 I40E_PTT_UNUSED_ENTRY(39),
265 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
266 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
267 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
268
269 /* IPv4 --> GRE/NAT */
270 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
271
272 /* IPv4 --> GRE/NAT --> IPv4 */
273 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
274 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
275 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
276 I40E_PTT_UNUSED_ENTRY(47),
277 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
278 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
279 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
280
281 /* IPv4 --> GRE/NAT --> IPv6 */
282 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
283 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
284 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
285 I40E_PTT_UNUSED_ENTRY(54),
286 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
287 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
288 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
289
290 /* IPv4 --> GRE/NAT --> MAC */
291 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
292
293 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
294 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
295 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
296 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
297 I40E_PTT_UNUSED_ENTRY(62),
298 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
299 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
300 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
301
302 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
303 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
304 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
305 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
306 I40E_PTT_UNUSED_ENTRY(69),
307 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
308 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
309 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
310
311 /* IPv4 --> GRE/NAT --> MAC/VLAN */
312 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
313
314 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
315 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
316 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
317 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
318 I40E_PTT_UNUSED_ENTRY(77),
319 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
320 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
321 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
322
323 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
324 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
325 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
326 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
327 I40E_PTT_UNUSED_ENTRY(84),
328 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
329 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
330 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
331
332 /* Non Tunneled IPv6 */
333 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
334 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
335 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
336 I40E_PTT_UNUSED_ENTRY(91),
337 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
338 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
339 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
340
341 /* IPv6 --> IPv4 */
342 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
343 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
344 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
345 I40E_PTT_UNUSED_ENTRY(98),
346 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
347 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
348 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
349
350 /* IPv6 --> IPv6 */
351 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
352 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
353 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
354 I40E_PTT_UNUSED_ENTRY(105),
355 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
356 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
357 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
358
359 /* IPv6 --> GRE/NAT */
360 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
361
362 /* IPv6 --> GRE/NAT -> IPv4 */
363 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
364 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
365 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
366 I40E_PTT_UNUSED_ENTRY(113),
367 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
368 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
369 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
370
371 /* IPv6 --> GRE/NAT -> IPv6 */
372 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
373 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
374 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
375 I40E_PTT_UNUSED_ENTRY(120),
376 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
377 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
378 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
379
380 /* IPv6 --> GRE/NAT -> MAC */
381 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
382
383 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
384 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
385 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
386 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
387 I40E_PTT_UNUSED_ENTRY(128),
388 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
389 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
390 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
391
392 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
393 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
394 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
395 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
396 I40E_PTT_UNUSED_ENTRY(135),
397 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
398 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
399 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
400
401 /* IPv6 --> GRE/NAT -> MAC/VLAN */
402 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
403
404 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
405 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
406 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
407 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
408 I40E_PTT_UNUSED_ENTRY(143),
409 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
410 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
411 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
412
413 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
414 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
415 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
416 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
417 I40E_PTT_UNUSED_ENTRY(150),
418 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
419 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
420 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
421
422 /* unused entries */
423 I40E_PTT_UNUSED_ENTRY(154),
424 I40E_PTT_UNUSED_ENTRY(155),
425 I40E_PTT_UNUSED_ENTRY(156),
426 I40E_PTT_UNUSED_ENTRY(157),
427 I40E_PTT_UNUSED_ENTRY(158),
428 I40E_PTT_UNUSED_ENTRY(159),
429
430 I40E_PTT_UNUSED_ENTRY(160),
431 I40E_PTT_UNUSED_ENTRY(161),
432 I40E_PTT_UNUSED_ENTRY(162),
433 I40E_PTT_UNUSED_ENTRY(163),
434 I40E_PTT_UNUSED_ENTRY(164),
435 I40E_PTT_UNUSED_ENTRY(165),
436 I40E_PTT_UNUSED_ENTRY(166),
437 I40E_PTT_UNUSED_ENTRY(167),
438 I40E_PTT_UNUSED_ENTRY(168),
439 I40E_PTT_UNUSED_ENTRY(169),
440
441 I40E_PTT_UNUSED_ENTRY(170),
442 I40E_PTT_UNUSED_ENTRY(171),
443 I40E_PTT_UNUSED_ENTRY(172),
444 I40E_PTT_UNUSED_ENTRY(173),
445 I40E_PTT_UNUSED_ENTRY(174),
446 I40E_PTT_UNUSED_ENTRY(175),
447 I40E_PTT_UNUSED_ENTRY(176),
448 I40E_PTT_UNUSED_ENTRY(177),
449 I40E_PTT_UNUSED_ENTRY(178),
450 I40E_PTT_UNUSED_ENTRY(179),
451
452 I40E_PTT_UNUSED_ENTRY(180),
453 I40E_PTT_UNUSED_ENTRY(181),
454 I40E_PTT_UNUSED_ENTRY(182),
455 I40E_PTT_UNUSED_ENTRY(183),
456 I40E_PTT_UNUSED_ENTRY(184),
457 I40E_PTT_UNUSED_ENTRY(185),
458 I40E_PTT_UNUSED_ENTRY(186),
459 I40E_PTT_UNUSED_ENTRY(187),
460 I40E_PTT_UNUSED_ENTRY(188),
461 I40E_PTT_UNUSED_ENTRY(189),
462
463 I40E_PTT_UNUSED_ENTRY(190),
464 I40E_PTT_UNUSED_ENTRY(191),
465 I40E_PTT_UNUSED_ENTRY(192),
466 I40E_PTT_UNUSED_ENTRY(193),
467 I40E_PTT_UNUSED_ENTRY(194),
468 I40E_PTT_UNUSED_ENTRY(195),
469 I40E_PTT_UNUSED_ENTRY(196),
470 I40E_PTT_UNUSED_ENTRY(197),
471 I40E_PTT_UNUSED_ENTRY(198),
472 I40E_PTT_UNUSED_ENTRY(199),
473
474 I40E_PTT_UNUSED_ENTRY(200),
475 I40E_PTT_UNUSED_ENTRY(201),
476 I40E_PTT_UNUSED_ENTRY(202),
477 I40E_PTT_UNUSED_ENTRY(203),
478 I40E_PTT_UNUSED_ENTRY(204),
479 I40E_PTT_UNUSED_ENTRY(205),
480 I40E_PTT_UNUSED_ENTRY(206),
481 I40E_PTT_UNUSED_ENTRY(207),
482 I40E_PTT_UNUSED_ENTRY(208),
483 I40E_PTT_UNUSED_ENTRY(209),
484
485 I40E_PTT_UNUSED_ENTRY(210),
486 I40E_PTT_UNUSED_ENTRY(211),
487 I40E_PTT_UNUSED_ENTRY(212),
488 I40E_PTT_UNUSED_ENTRY(213),
489 I40E_PTT_UNUSED_ENTRY(214),
490 I40E_PTT_UNUSED_ENTRY(215),
491 I40E_PTT_UNUSED_ENTRY(216),
492 I40E_PTT_UNUSED_ENTRY(217),
493 I40E_PTT_UNUSED_ENTRY(218),
494 I40E_PTT_UNUSED_ENTRY(219),
495
496 I40E_PTT_UNUSED_ENTRY(220),
497 I40E_PTT_UNUSED_ENTRY(221),
498 I40E_PTT_UNUSED_ENTRY(222),
499 I40E_PTT_UNUSED_ENTRY(223),
500 I40E_PTT_UNUSED_ENTRY(224),
501 I40E_PTT_UNUSED_ENTRY(225),
502 I40E_PTT_UNUSED_ENTRY(226),
503 I40E_PTT_UNUSED_ENTRY(227),
504 I40E_PTT_UNUSED_ENTRY(228),
505 I40E_PTT_UNUSED_ENTRY(229),
506
507 I40E_PTT_UNUSED_ENTRY(230),
508 I40E_PTT_UNUSED_ENTRY(231),
509 I40E_PTT_UNUSED_ENTRY(232),
510 I40E_PTT_UNUSED_ENTRY(233),
511 I40E_PTT_UNUSED_ENTRY(234),
512 I40E_PTT_UNUSED_ENTRY(235),
513 I40E_PTT_UNUSED_ENTRY(236),
514 I40E_PTT_UNUSED_ENTRY(237),
515 I40E_PTT_UNUSED_ENTRY(238),
516 I40E_PTT_UNUSED_ENTRY(239),
517
518 I40E_PTT_UNUSED_ENTRY(240),
519 I40E_PTT_UNUSED_ENTRY(241),
520 I40E_PTT_UNUSED_ENTRY(242),
521 I40E_PTT_UNUSED_ENTRY(243),
522 I40E_PTT_UNUSED_ENTRY(244),
523 I40E_PTT_UNUSED_ENTRY(245),
524 I40E_PTT_UNUSED_ENTRY(246),
525 I40E_PTT_UNUSED_ENTRY(247),
526 I40E_PTT_UNUSED_ENTRY(248),
527 I40E_PTT_UNUSED_ENTRY(249),
528
529 I40E_PTT_UNUSED_ENTRY(250),
530 I40E_PTT_UNUSED_ENTRY(251),
531 I40E_PTT_UNUSED_ENTRY(252),
532 I40E_PTT_UNUSED_ENTRY(253),
533 I40E_PTT_UNUSED_ENTRY(254),
534 I40E_PTT_UNUSED_ENTRY(255)
535};
536
537
56a62fc8
JB		 538/**
539 * i40e_init_shared_code - Initialize the shared code
540 * @hw: pointer to hardware structure
541 *
542 * This assigns the MAC type and PHY code and inits the NVM.
543 * Does not touch the hardware. This function must be called prior to any
544 * other function in the shared code. The i40e_hw structure should be
545 * memset to 0 prior to calling this function. The following fields in
546 * hw structure should be filled in prior to calling this function:
547 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
548 * subsystem_vendor_id, and revision_id
549 **/
550i40e_status i40e_init_shared_code(struct i40e_hw *hw)
551{
552 i40e_status status = 0;
553 u32 reg;
554
56a62fc8
JB		 555 i40e_set_mac_type(hw);
556
557 switch (hw->mac.type) {
558 case I40E_MAC_XL710:
559 break;
560 default:
561 return I40E_ERR_DEVICE_NOT_SUPPORTED;
56a62fc8
JB		 562 }
563
af89d26c
SN		 564 hw->phy.get_link_info = true;
565
566 /* Determine port number */
567 reg = rd32(hw, I40E_PFGEN_PORTNUM);
568 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
569 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
570 hw->port = (u8)reg;
571
5f9116ac
SN		 572 /* Determine the PF number based on the PCI fn */
573 reg = rd32(hw, I40E_GLPCI_CAPSUP);
574 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
575 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
576 else
577 hw->pf_id = (u8)hw->bus.func;
578
56a62fc8
JB		 579 status = i40e_init_nvm(hw);
580 return status;
581}
582
583/**
584 * i40e_aq_mac_address_read - Retrieve the MAC addresses
585 * @hw: pointer to the hw struct
586 * @flags: a return indicator of what addresses were added to the addr store
587 * @addrs: the requestor's mac addr store
588 * @cmd_details: pointer to command details structure or NULL
589 **/
590static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
591 u16 *flags,
592 struct i40e_aqc_mac_address_read_data *addrs,
593 struct i40e_asq_cmd_details *cmd_details)
594{
595 struct i40e_aq_desc desc;
596 struct i40e_aqc_mac_address_read *cmd_data =
597 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
598 i40e_status status;
599
600 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
601 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
602
603 status = i40e_asq_send_command(hw, &desc, addrs,
604 sizeof(*addrs), cmd_details);
605 *flags = le16_to_cpu(cmd_data->command_flags);
606
607 return status;
608}
609
610/**
611 * i40e_aq_mac_address_write - Change the MAC addresses
612 * @hw: pointer to the hw struct
613 * @flags: indicates which MAC to be written
614 * @mac_addr: address to write
615 * @cmd_details: pointer to command details structure or NULL
616 **/
617i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
618 u16 flags, u8 *mac_addr,
619 struct i40e_asq_cmd_details *cmd_details)
620{
621 struct i40e_aq_desc desc;
622 struct i40e_aqc_mac_address_write *cmd_data =
623 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
624 i40e_status status;
625
626 i40e_fill_default_direct_cmd_desc(&desc,
627 i40e_aqc_opc_mac_address_write);
628 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 629 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
630 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
631 ((u32)mac_addr[3] << 16) |
632 ((u32)mac_addr[4] << 8) |
633 mac_addr[5]);
56a62fc8
JB		 634
635 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
636
637 return status;
638}
639
640/**
641 * i40e_get_mac_addr - get MAC address
642 * @hw: pointer to the HW structure
643 * @mac_addr: pointer to MAC address
644 *
645 * Reads the adapter's MAC address from register
646 **/
647i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
648{
649 struct i40e_aqc_mac_address_read_data addrs;
650 i40e_status status;
651 u16 flags = 0;
652
653 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
654
655 if (flags & I40E_AQC_LAN_ADDR_VALID)
656 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
657
658 return status;
659}
660
1f224ad2
NP		 661/**
662 * i40e_get_port_mac_addr - get Port MAC address
663 * @hw: pointer to the HW structure
664 * @mac_addr: pointer to Port MAC address
665 *
666 * Reads the adapter's Port MAC address
667 **/
668i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
669{
670 struct i40e_aqc_mac_address_read_data addrs;
671 i40e_status status;
672 u16 flags = 0;
673
674 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
675 if (status)
676 return status;
677
678 if (flags & I40E_AQC_PORT_ADDR_VALID)
679 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
680 else
681 status = I40E_ERR_INVALID_MAC_ADDR;
682
683 return status;
684}
685
351499ab
MJ		 686/**
687 * i40e_pre_tx_queue_cfg - pre tx queue configure
688 * @hw: pointer to the HW structure
689 * @queue: target pf queue index
690 * @enable: state change request
691 *
692 * Handles hw requirement to indicate intention to enable
693 * or disable target queue.
694 **/
695void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
696{
dfb699f9 697 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 698 u32 reg_block = 0;
dfb699f9 699 u32 reg_val;
351499ab 700
24a768cf 701 if (abs_queue_idx >= 128) {
351499ab 702 reg_block = abs_queue_idx / 128;
24a768cf
CP		 703 abs_queue_idx %= 128;
704 }
351499ab
MJ		 705
706 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
707 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
708 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
709
710 if (enable)
711 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
712 else
713 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
714
715 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
716}
38e00438
VD		 717#ifdef I40E_FCOE
718
719/**
720 * i40e_get_san_mac_addr - get SAN MAC address
721 * @hw: pointer to the HW structure
722 * @mac_addr: pointer to SAN MAC address
723 *
724 * Reads the adapter's SAN MAC address from NVM
725 **/
726i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
727{
728 struct i40e_aqc_mac_address_read_data addrs;
729 i40e_status status;
730 u16 flags = 0;
731
732 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
733 if (status)
734 return status;
735
736 if (flags & I40E_AQC_SAN_ADDR_VALID)
737 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
738 else
739 status = I40E_ERR_INVALID_MAC_ADDR;
740
741 return status;
742}
743#endif
351499ab 744
be405eb0
JB		 745/**
746 * i40e_get_media_type - Gets media type
747 * @hw: pointer to the hardware structure
748 **/
749static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
750{
751 enum i40e_media_type media;
752
753 switch (hw->phy.link_info.phy_type) {
754 case I40E_PHY_TYPE_10GBASE_SR:
755 case I40E_PHY_TYPE_10GBASE_LR:
124ed15b
CS		 756 case I40E_PHY_TYPE_1000BASE_SX:
757 case I40E_PHY_TYPE_1000BASE_LX:
be405eb0
JB		 758 case I40E_PHY_TYPE_40GBASE_SR4:
759 case I40E_PHY_TYPE_40GBASE_LR4:
760 media = I40E_MEDIA_TYPE_FIBER;
761 break;
762 case I40E_PHY_TYPE_100BASE_TX:
763 case I40E_PHY_TYPE_1000BASE_T:
764 case I40E_PHY_TYPE_10GBASE_T:
765 media = I40E_MEDIA_TYPE_BASET;
766 break;
767 case I40E_PHY_TYPE_10GBASE_CR1_CU:
768 case I40E_PHY_TYPE_40GBASE_CR4_CU:
769 case I40E_PHY_TYPE_10GBASE_CR1:
770 case I40E_PHY_TYPE_40GBASE_CR4:
771 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
772 media = I40E_MEDIA_TYPE_DA;
773 break;
774 case I40E_PHY_TYPE_1000BASE_KX:
775 case I40E_PHY_TYPE_10GBASE_KX4:
776 case I40E_PHY_TYPE_10GBASE_KR:
777 case I40E_PHY_TYPE_40GBASE_KR4:
778 media = I40E_MEDIA_TYPE_BACKPLANE;
779 break;
780 case I40E_PHY_TYPE_SGMII:
781 case I40E_PHY_TYPE_XAUI:
782 case I40E_PHY_TYPE_XFI:
783 case I40E_PHY_TYPE_XLAUI:
784 case I40E_PHY_TYPE_XLPPI:
785 default:
786 media = I40E_MEDIA_TYPE_UNKNOWN;
787 break;
788 }
789
790 return media;
791}
792
7134f9ce 793#define I40E_PF_RESET_WAIT_COUNT_A0 200
d0ff5687 794#define I40E_PF_RESET_WAIT_COUNT 100
56a62fc8
JB		 795/**
796 * i40e_pf_reset - Reset the PF
797 * @hw: pointer to the hardware structure
798 *
799 * Assuming someone else has triggered a global reset,
800 * assure the global reset is complete and then reset the PF
801 **/
802i40e_status i40e_pf_reset(struct i40e_hw *hw)
803{
7134f9ce 804 u32 cnt = 0;
42794bd8 805 u32 cnt1 = 0;
56a62fc8
JB		 806 u32 reg = 0;
807 u32 grst_del;
808
809 /* Poll for Global Reset steady state in case of recent GRST.
810 * The grst delay value is in 100ms units, and we'll wait a
811 * couple counts longer to be sure we don't just miss the end.
812 */
813 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
814 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 815 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 816 reg = rd32(hw, I40E_GLGEN_RSTAT);
817 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
818 break;
819 msleep(100);
820 }
821 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
822 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 823 return I40E_ERR_RESET_FAILED;
824 }
825
826 /* Now Wait for the FW to be ready */
827 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
828 reg = rd32(hw, I40E_GLNVM_ULD);
829 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
830 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
831 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
832 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
833 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
834 break;
835 }
836 usleep_range(10000, 20000);
837 }
838 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
839 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
840 hw_dbg(hw, "wait for FW Reset complete timedout\n");
841 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 842 return I40E_ERR_RESET_FAILED;
843 }
844
56a62fc8
JB		 845 /* If there was a Global Reset in progress when we got here,
846 * we don't need to do the PF Reset
847 */
7134f9ce
JB		 848 if (!cnt) {
849 if (hw->revision_id == 0)
850 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
851 else
852 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 853 reg = rd32(hw, I40E_PFGEN_CTRL);
854 wr32(hw, I40E_PFGEN_CTRL,
855 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 856 for (; cnt; cnt--) {
56a62fc8
JB		 857 reg = rd32(hw, I40E_PFGEN_CTRL);
858 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
859 break;
860 usleep_range(1000, 2000);
861 }
862 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
863 hw_dbg(hw, "PF reset polling failed to complete.\n");
864 return I40E_ERR_RESET_FAILED;
865 }
866 }
867
868 i40e_clear_pxe_mode(hw);
922680b9 869
56a62fc8
JB		 870 return 0;
871}
872
838d41d9
SN		 873/**
874 * i40e_clear_hw - clear out any left over hw state
875 * @hw: pointer to the hw struct
876 *
877 * Clear queues and interrupts, typically called at init time,
878 * but after the capabilities have been found so we know how many
879 * queues and msix vectors have been allocated.
880 **/
881void i40e_clear_hw(struct i40e_hw *hw)
882{
883 u32 num_queues, base_queue;
884 u32 num_pf_int;
885 u32 num_vf_int;
886 u32 num_vfs;
887 u32 i, j;
888 u32 val;
889 u32 eol = 0x7ff;
890
891 /* get number of interrupts, queues, and vfs */
892 val = rd32(hw, I40E_GLPCI_CNF2);
893 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
894 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
895 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
896 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
897
898 val = rd32(hw, I40E_PFLAN_QALLOC);
899 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
900 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
901 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
902 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
903 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
904 num_queues = (j - base_queue) + 1;
905 else
906 num_queues = 0;
907
908 val = rd32(hw, I40E_PF_VT_PFALLOC);
909 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
910 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
911 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
912 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
913 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
914 num_vfs = (j - i) + 1;
915 else
916 num_vfs = 0;
917
918 /* stop all the interrupts */
919 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
920 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
921 for (i = 0; i < num_pf_int - 2; i++)
922 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
923
924 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
925 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
926 wr32(hw, I40E_PFINT_LNKLST0, val);
927 for (i = 0; i < num_pf_int - 2; i++)
928 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
929 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
930 for (i = 0; i < num_vfs; i++)
931 wr32(hw, I40E_VPINT_LNKLST0(i), val);
932 for (i = 0; i < num_vf_int - 2; i++)
933 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
934
935 /* warn the HW of the coming Tx disables */
936 for (i = 0; i < num_queues; i++) {
937 u32 abs_queue_idx = base_queue + i;
938 u32 reg_block = 0;
939
940 if (abs_queue_idx >= 128) {
941 reg_block = abs_queue_idx / 128;
942 abs_queue_idx %= 128;
943 }
944
945 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
946 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
947 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
948 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
949
950 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
951 }
952 udelay(400);
953
954 /* stop all the queues */
955 for (i = 0; i < num_queues; i++) {
956 wr32(hw, I40E_QINT_TQCTL(i), 0);
957 wr32(hw, I40E_QTX_ENA(i), 0);
958 wr32(hw, I40E_QINT_RQCTL(i), 0);
959 wr32(hw, I40E_QRX_ENA(i), 0);
960 }
961
962 /* short wait for all queue disables to settle */
963 udelay(50);
964}
965
56a62fc8
JB		 966/**
967 * i40e_clear_pxe_mode - clear pxe operations mode
968 * @hw: pointer to the hw struct
969 *
970 * Make sure all PXE mode settings are cleared, including things
971 * like descriptor fetch/write-back mode.
972 **/
973void i40e_clear_pxe_mode(struct i40e_hw *hw)
974{
975 u32 reg;
976
c9b9b0ae
SN		 977 if (i40e_check_asq_alive(hw))
978 i40e_aq_clear_pxe_mode(hw, NULL);
979
56a62fc8
JB		 980 /* Clear single descriptor fetch/write-back mode */
981 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 982
983 if (hw->revision_id == 0) {
984 /* As a work around clear PXE_MODE instead of setting it */
985 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
986 } else {
987 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
988 }
56a62fc8
JB		 989}
990
0556a9e3
JB		 991/**
992 * i40e_led_is_mine - helper to find matching led
993 * @hw: pointer to the hw struct
994 * @idx: index into GPIO registers
995 *
996 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
997 */
998static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
999{
1000 u32 gpio_val = 0;
1001 u32 port;
1002
1003 if (!hw->func_caps.led[idx])
1004 return 0;
1005
1006 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1007 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1008 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1009
1010 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1011 * if it is not our port then ignore
1012 */
1013 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1014 (port != hw->port))
1015 return 0;
1016
1017 return gpio_val;
1018}
1019
1020#define I40E_LED0 22
1021#define I40E_LINK_ACTIVITY 0xC
1022
56a62fc8
JB		 1023/**
1024 * i40e_led_get - return current on/off mode
1025 * @hw: pointer to the hw struct
1026 *
1027 * The value returned is the 'mode' field as defined in the
1028 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1029 * values are variations of possible behaviors relating to
1030 * blink, link, and wire.
1031 **/
1032u32 i40e_led_get(struct i40e_hw *hw)
1033{
56a62fc8 1034 u32 mode = 0;
56a62fc8
JB		 1035 int i;
1036
0556a9e3
JB		 1037 /* as per the documentation GPIO 22-29 are the LED
1038 * GPIO pins named LED0..LED7
1039 */
1040 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1041 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1042
0556a9e3 1043 if (!gpio_val)
56a62fc8
JB		 1044 continue;
1045
0556a9e3
JB		 1046 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1047 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 1048 break;
1049 }
1050
1051 return mode;
1052}
1053
1054/**
1055 * i40e_led_set - set new on/off mode
1056 * @hw: pointer to the hw struct
0556a9e3
JB		 1057 * @mode: 0=off, 0xf=on (else see manual for mode details)
1058 * @blink: true if the LED should blink when on, false if steady
1059 *
1060 * if this function is used to turn on the blink it should
1061 * be used to disable the blink when restoring the original state.
56a62fc8 1062 **/
0556a9e3 1063void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1064{
56a62fc8
JB		 1065 int i;
1066
0556a9e3
JB		 1067 if (mode & 0xfffffff0)
1068 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1069
0556a9e3
JB		 1070 /* as per the documentation GPIO 22-29 are the LED
1071 * GPIO pins named LED0..LED7
1072 */
1073 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1074 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1075
0556a9e3 1076 if (!gpio_val)
56a62fc8
JB		 1077 continue;
1078
56a62fc8 1079 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1080 /* this & is a bit of paranoia, but serves as a range check */
1081 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1082 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1083
1084 if (mode == I40E_LINK_ACTIVITY)
1085 blink = false;
1086
1087 gpio_val |= (blink ? 1 : 0) <<
1088 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1089
56a62fc8 1090 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1091 break;
56a62fc8
JB		 1092 }
1093}
1094
1095/* Admin command wrappers */
56a62fc8 1096
8109e123
CS		 1097/**
1098 * i40e_aq_get_phy_capabilities
1099 * @hw: pointer to the hw struct
1100 * @abilities: structure for PHY capabilities to be filled
1101 * @qualified_modules: report Qualified Modules
1102 * @report_init: report init capabilities (active are default)
1103 * @cmd_details: pointer to command details structure or NULL
1104 *
1105 * Returns the various PHY abilities supported on the Port.
1106 **/
1107i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1108 bool qualified_modules, bool report_init,
1109 struct i40e_aq_get_phy_abilities_resp *abilities,
1110 struct i40e_asq_cmd_details *cmd_details)
1111{
1112 struct i40e_aq_desc desc;
1113 i40e_status status;
1114 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1115
1116 if (!abilities)
1117 return I40E_ERR_PARAM;
1118
1119 i40e_fill_default_direct_cmd_desc(&desc,
1120 i40e_aqc_opc_get_phy_abilities);
1121
1122 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1123 if (abilities_size > I40E_AQ_LARGE_BUF)
1124 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1125
1126 if (qualified_modules)
1127 desc.params.external.param0 |=
1128 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1129
1130 if (report_init)
1131 desc.params.external.param0 |=
1132 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1133
1134 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1135 cmd_details);
1136
1137 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1138 status = I40E_ERR_UNKNOWN_PHY;
1139
1140 return status;
1141}
1142
c56999f9
CS		 1143/**
1144 * i40e_aq_set_phy_config
1145 * @hw: pointer to the hw struct
1146 * @config: structure with PHY configuration to be set
1147 * @cmd_details: pointer to command details structure or NULL
1148 *
1149 * Set the various PHY configuration parameters
1150 * supported on the Port.One or more of the Set PHY config parameters may be
1151 * ignored in an MFP mode as the PF may not have the privilege to set some
1152 * of the PHY Config parameters. This status will be indicated by the
1153 * command response.
1154 **/
1155enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1156 struct i40e_aq_set_phy_config *config,
1157 struct i40e_asq_cmd_details *cmd_details)
1158{
1159 struct i40e_aq_desc desc;
1160 struct i40e_aq_set_phy_config *cmd =
1161 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1162 enum i40e_status_code status;
1163
1164 if (!config)
1165 return I40E_ERR_PARAM;
1166
1167 i40e_fill_default_direct_cmd_desc(&desc,
1168 i40e_aqc_opc_set_phy_config);
1169
1170 *cmd = *config;
1171
1172 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1173
1174 return status;
1175}
1176
1177/**
1178 * i40e_set_fc
1179 * @hw: pointer to the hw struct
1180 *
1181 * Set the requested flow control mode using set_phy_config.
1182 **/
1183enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1184 bool atomic_restart)
1185{
1186 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1187 struct i40e_aq_get_phy_abilities_resp abilities;
1188 struct i40e_aq_set_phy_config config;
1189 enum i40e_status_code status;
1190 u8 pause_mask = 0x0;
1191
1192 *aq_failures = 0x0;
1193
1194 switch (fc_mode) {
1195 case I40E_FC_FULL:
1196 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1197 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1198 break;
1199 case I40E_FC_RX_PAUSE:
1200 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1201 break;
1202 case I40E_FC_TX_PAUSE:
1203 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1204 break;
1205 default:
1206 break;
1207 }
1208
1209 /* Get the current phy config */
1210 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1211 NULL);
1212 if (status) {
1213 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1214 return status;
1215 }
1216
1217 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1218 /* clear the old pause settings */
1219 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1220 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1221 /* set the new abilities */
1222 config.abilities |= pause_mask;
1223 /* If the abilities have changed, then set the new config */
1224 if (config.abilities != abilities.abilities) {
1225 /* Auto restart link so settings take effect */
1226 if (atomic_restart)
1227 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1228 /* Copy over all the old settings */
1229 config.phy_type = abilities.phy_type;
1230 config.link_speed = abilities.link_speed;
1231 config.eee_capability = abilities.eee_capability;
1232 config.eeer = abilities.eeer_val;
1233 config.low_power_ctrl = abilities.d3_lpan;
1234 status = i40e_aq_set_phy_config(hw, &config, NULL);
1235
1236 if (status)
1237 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1238 }
1239 /* Update the link info */
1240 status = i40e_update_link_info(hw, true);
1241 if (status) {
1242 /* Wait a little bit (on 40G cards it sometimes takes a really
1243 * long time for link to come back from the atomic reset)
1244 * and try once more
1245 */
1246 msleep(1000);
1247 status = i40e_update_link_info(hw, true);
1248 }
1249 if (status)
1250 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1251
1252 return status;
1253}
1254
c9b9b0ae
SN		 1255/**
1256 * i40e_aq_clear_pxe_mode
1257 * @hw: pointer to the hw struct
1258 * @cmd_details: pointer to command details structure or NULL
1259 *
1260 * Tell the firmware that the driver is taking over from PXE
1261 **/
1262i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1263 struct i40e_asq_cmd_details *cmd_details)
1264{
1265 i40e_status status;
1266 struct i40e_aq_desc desc;
1267 struct i40e_aqc_clear_pxe *cmd =
1268 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1269
1270 i40e_fill_default_direct_cmd_desc(&desc,
1271 i40e_aqc_opc_clear_pxe_mode);
1272
1273 cmd->rx_cnt = 0x2;
1274
1275 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1276
1277 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1278
1279 return status;
1280}
1281
56a62fc8
JB		 1282/**
1283 * i40e_aq_set_link_restart_an
1284 * @hw: pointer to the hw struct
1ac978af 1285 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1286 * @cmd_details: pointer to command details structure or NULL
1287 *
1288 * Sets up the link and restarts the Auto-Negotiation over the link.
1289 **/
1290i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1291 bool enable_link,
1292 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1293{
1294 struct i40e_aq_desc desc;
1295 struct i40e_aqc_set_link_restart_an *cmd =
1296 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1297 i40e_status status;
1298
1299 i40e_fill_default_direct_cmd_desc(&desc,
1300 i40e_aqc_opc_set_link_restart_an);
1301
1302 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1303 if (enable_link)
1304 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1305 else
1306 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1307
1308 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1309
1310 return status;
1311}
1312
1313/**
1314 * i40e_aq_get_link_info
1315 * @hw: pointer to the hw struct
1316 * @enable_lse: enable/disable LinkStatusEvent reporting
1317 * @link: pointer to link status structure - optional
1318 * @cmd_details: pointer to command details structure or NULL
1319 *
1320 * Returns the link status of the adapter.
1321 **/
1322i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1323 bool enable_lse, struct i40e_link_status *link,
1324 struct i40e_asq_cmd_details *cmd_details)
1325{
1326 struct i40e_aq_desc desc;
1327 struct i40e_aqc_get_link_status *resp =
1328 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1329 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1330 i40e_status status;
c56999f9 1331 bool tx_pause, rx_pause;
56a62fc8
JB		 1332 u16 command_flags;
1333
1334 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1335
1336 if (enable_lse)
1337 command_flags = I40E_AQ_LSE_ENABLE;
1338 else
1339 command_flags = I40E_AQ_LSE_DISABLE;
1340 resp->command_flags = cpu_to_le16(command_flags);
1341
1342 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1343
1344 if (status)
1345 goto aq_get_link_info_exit;
1346
1347 /* save off old link status information */
c36bd4a7 1348 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1349
1350 /* update link status */
1351 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1352 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1353 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1354 hw_link_info->link_info = resp->link_info;
1355 hw_link_info->an_info = resp->an_info;
1356 hw_link_info->ext_info = resp->ext_info;
639dc377 1357 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1358 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1359 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1360
c56999f9
CS		 1361 /* update fc info */
1362 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1363 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1364 if (tx_pause & rx_pause)
1365 hw->fc.current_mode = I40E_FC_FULL;
1366 else if (tx_pause)
1367 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1368 else if (rx_pause)
1369 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1370 else
1371 hw->fc.current_mode = I40E_FC_NONE;
1372
6bb3f23c
NP		 1373 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1374 hw_link_info->crc_enable = true;
1375 else
1376 hw_link_info->crc_enable = false;
56a62fc8
JB		 1377
1378 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1379 hw_link_info->lse_enable = true;
1380 else
1381 hw_link_info->lse_enable = false;
1382
1383 /* save link status information */
1384 if (link)
d7595a22 1385 *link = *hw_link_info;
56a62fc8
JB		 1386
1387 /* flag cleared so helper functions don't call AQ again */
1388 hw->phy.get_link_info = false;
1389
1390aq_get_link_info_exit:
1391 return status;
1392}
1393
8109e123
CS		 1394/**
1395 * i40e_update_link_info
1396 * @hw: pointer to the hw struct
1397 * @enable_lse: enable/disable LinkStatusEvent reporting
1398 *
1399 * Returns the link status of the adapter
1400 **/
1401i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse)
1402{
1403 struct i40e_aq_get_phy_abilities_resp abilities;
1404 i40e_status status;
1405
1406 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1407 if (status)
1408 return status;
1409
1410 status = i40e_aq_get_phy_capabilities(hw, false, false,
1411 &abilities, NULL);
1412 if (status)
1413 return status;
1414
1415 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1416 hw->phy.link_info.an_enabled = true;
1417 else
1418 hw->phy.link_info.an_enabled = false;
1419
1420 return status;
1421}
1422
7e2453fe
JB		 1423/**
1424 * i40e_aq_set_phy_int_mask
1425 * @hw: pointer to the hw struct
1426 * @mask: interrupt mask to be set
1427 * @cmd_details: pointer to command details structure or NULL
1428 *
1429 * Set link interrupt mask.
1430 **/
1431i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1432 u16 mask,
1433 struct i40e_asq_cmd_details *cmd_details)
1434{
1435 struct i40e_aq_desc desc;
1436 struct i40e_aqc_set_phy_int_mask *cmd =
1437 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1438 i40e_status status;
1439
1440 i40e_fill_default_direct_cmd_desc(&desc,
1441 i40e_aqc_opc_set_phy_int_mask);
1442
1443 cmd->event_mask = cpu_to_le16(mask);
1444
1445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1446
1447 return status;
1448}
1449
56a62fc8
JB		 1450/**
1451 * i40e_aq_add_vsi
1452 * @hw: pointer to the hw struct
98d44381 1453 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1454 * @cmd_details: pointer to command details structure or NULL
1455 *
1456 * Add a VSI context to the hardware.
1457**/
1458i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1459 struct i40e_vsi_context *vsi_ctx,
1460 struct i40e_asq_cmd_details *cmd_details)
1461{
1462 struct i40e_aq_desc desc;
1463 struct i40e_aqc_add_get_update_vsi *cmd =
1464 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1465 struct i40e_aqc_add_get_update_vsi_completion *resp =
1466 (struct i40e_aqc_add_get_update_vsi_completion *)
1467 &desc.params.raw;
1468 i40e_status status;
1469
1470 i40e_fill_default_direct_cmd_desc(&desc,
1471 i40e_aqc_opc_add_vsi);
1472
1473 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1474 cmd->connection_type = vsi_ctx->connection_type;
1475 cmd->vf_id = vsi_ctx->vf_num;
1476 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1477
1478 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1479
1480 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1481 sizeof(vsi_ctx->info), cmd_details);
1482
1483 if (status)
1484 goto aq_add_vsi_exit;
1485
1486 vsi_ctx->seid = le16_to_cpu(resp->seid);
1487 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1488 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1489 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1490
1491aq_add_vsi_exit:
1492 return status;
1493}
1494
1495/**
1496 * i40e_aq_set_vsi_unicast_promiscuous
1497 * @hw: pointer to the hw struct
1498 * @seid: vsi number
1499 * @set: set unicast promiscuous enable/disable
1500 * @cmd_details: pointer to command details structure or NULL
1501 **/
1502i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1503 u16 seid, bool set,
1504 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1505{
1506 struct i40e_aq_desc desc;
1507 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1508 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1509 i40e_status status;
1510 u16 flags = 0;
1511
1512 i40e_fill_default_direct_cmd_desc(&desc,
1513 i40e_aqc_opc_set_vsi_promiscuous_modes);
1514
1515 if (set)
1516 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1517
1518 cmd->promiscuous_flags = cpu_to_le16(flags);
1519
1520 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1521
1522 cmd->seid = cpu_to_le16(seid);
1523 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1524
1525 return status;
1526}
1527
1528/**
1529 * i40e_aq_set_vsi_multicast_promiscuous
1530 * @hw: pointer to the hw struct
1531 * @seid: vsi number
1532 * @set: set multicast promiscuous enable/disable
1533 * @cmd_details: pointer to command details structure or NULL
1534 **/
1535i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1536 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1537{
1538 struct i40e_aq_desc desc;
1539 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1540 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1541 i40e_status status;
1542 u16 flags = 0;
1543
1544 i40e_fill_default_direct_cmd_desc(&desc,
1545 i40e_aqc_opc_set_vsi_promiscuous_modes);
1546
1547 if (set)
1548 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1549
1550 cmd->promiscuous_flags = cpu_to_le16(flags);
1551
1552 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1553
1554 cmd->seid = cpu_to_le16(seid);
1555 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1556
1557 return status;
1558}
1559
1560/**
1561 * i40e_aq_set_vsi_broadcast
1562 * @hw: pointer to the hw struct
1563 * @seid: vsi number
1564 * @set_filter: true to set filter, false to clear filter
1565 * @cmd_details: pointer to command details structure or NULL
1566 *
1567 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1568 **/
1569i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1570 u16 seid, bool set_filter,
1571 struct i40e_asq_cmd_details *cmd_details)
1572{
1573 struct i40e_aq_desc desc;
1574 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1575 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1576 i40e_status status;
1577
1578 i40e_fill_default_direct_cmd_desc(&desc,
1579 i40e_aqc_opc_set_vsi_promiscuous_modes);
1580
1581 if (set_filter)
1582 cmd->promiscuous_flags
1583 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1584 else
1585 cmd->promiscuous_flags
1586 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1587
1588 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1589 cmd->seid = cpu_to_le16(seid);
1590 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1591
1592 return status;
1593}
1594
1595/**
1596 * i40e_get_vsi_params - get VSI configuration info
1597 * @hw: pointer to the hw struct
98d44381 1598 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1599 * @cmd_details: pointer to command details structure or NULL
1600 **/
1601i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1602 struct i40e_vsi_context *vsi_ctx,
1603 struct i40e_asq_cmd_details *cmd_details)
1604{
1605 struct i40e_aq_desc desc;
f5ac8579
SN		 1606 struct i40e_aqc_add_get_update_vsi *cmd =
1607 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1608 struct i40e_aqc_add_get_update_vsi_completion *resp =
1609 (struct i40e_aqc_add_get_update_vsi_completion *)
1610 &desc.params.raw;
1611 i40e_status status;
1612
1613 i40e_fill_default_direct_cmd_desc(&desc,
1614 i40e_aqc_opc_get_vsi_parameters);
1615
f5ac8579 1616 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1617
1618 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 1619
1620 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1621 sizeof(vsi_ctx->info), NULL);
1622
1623 if (status)
1624 goto aq_get_vsi_params_exit;
1625
1626 vsi_ctx->seid = le16_to_cpu(resp->seid);
1627 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1628 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1629 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1630
1631aq_get_vsi_params_exit:
1632 return status;
1633}
1634
1635/**
1636 * i40e_aq_update_vsi_params
1637 * @hw: pointer to the hw struct
98d44381 1638 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1639 * @cmd_details: pointer to command details structure or NULL
1640 *
1641 * Update a VSI context.
1642 **/
1643i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1644 struct i40e_vsi_context *vsi_ctx,
1645 struct i40e_asq_cmd_details *cmd_details)
1646{
1647 struct i40e_aq_desc desc;
f5ac8579
SN		 1648 struct i40e_aqc_add_get_update_vsi *cmd =
1649 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1650 i40e_status status;
1651
1652 i40e_fill_default_direct_cmd_desc(&desc,
1653 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 1654 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1655
1656 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1657
1658 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1659 sizeof(vsi_ctx->info), cmd_details);
1660
1661 return status;
1662}
1663
1664/**
1665 * i40e_aq_get_switch_config
1666 * @hw: pointer to the hardware structure
1667 * @buf: pointer to the result buffer
1668 * @buf_size: length of input buffer
1669 * @start_seid: seid to start for the report, 0 == beginning
1670 * @cmd_details: pointer to command details structure or NULL
1671 *
1672 * Fill the buf with switch configuration returned from AdminQ command
1673 **/
1674i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1675 struct i40e_aqc_get_switch_config_resp *buf,
1676 u16 buf_size, u16 *start_seid,
1677 struct i40e_asq_cmd_details *cmd_details)
1678{
1679 struct i40e_aq_desc desc;
1680 struct i40e_aqc_switch_seid *scfg =
1681 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1682 i40e_status status;
1683
1684 i40e_fill_default_direct_cmd_desc(&desc,
1685 i40e_aqc_opc_get_switch_config);
1686 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1687 if (buf_size > I40E_AQ_LARGE_BUF)
1688 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1689 scfg->seid = cpu_to_le16(*start_seid);
1690
1691 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1692 *start_seid = le16_to_cpu(scfg->seid);
1693
1694 return status;
1695}
1696
1697/**
1698 * i40e_aq_get_firmware_version
1699 * @hw: pointer to the hw struct
1700 * @fw_major_version: firmware major version
1701 * @fw_minor_version: firmware minor version
1702 * @api_major_version: major queue version
1703 * @api_minor_version: minor queue version
1704 * @cmd_details: pointer to command details structure or NULL
1705 *
1706 * Get the firmware version from the admin queue commands
1707 **/
1708i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1709 u16 *fw_major_version, u16 *fw_minor_version,
1710 u16 *api_major_version, u16 *api_minor_version,
1711 struct i40e_asq_cmd_details *cmd_details)
1712{
1713 struct i40e_aq_desc desc;
1714 struct i40e_aqc_get_version *resp =
1715 (struct i40e_aqc_get_version *)&desc.params.raw;
1716 i40e_status status;
1717
1718 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1719
1720 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1721
1722 if (!status) {
1723 if (fw_major_version != NULL)
1724 *fw_major_version = le16_to_cpu(resp->fw_major);
1725 if (fw_minor_version != NULL)
1726 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1727 if (api_major_version != NULL)
1728 *api_major_version = le16_to_cpu(resp->api_major);
1729 if (api_minor_version != NULL)
1730 *api_minor_version = le16_to_cpu(resp->api_minor);
1731 }
1732
1733 return status;
1734}
1735
1736/**
1737 * i40e_aq_send_driver_version
1738 * @hw: pointer to the hw struct
56a62fc8
JB		 1739 * @dv: driver's major, minor version
1740 * @cmd_details: pointer to command details structure or NULL
1741 *
1742 * Send the driver version to the firmware
1743 **/
1744i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1745 struct i40e_driver_version *dv,
1746 struct i40e_asq_cmd_details *cmd_details)
1747{
1748 struct i40e_aq_desc desc;
1749 struct i40e_aqc_driver_version *cmd =
1750 (struct i40e_aqc_driver_version *)&desc.params.raw;
1751 i40e_status status;
9d2f98e1 1752 u16 len;
56a62fc8
JB		 1753
1754 if (dv == NULL)
1755 return I40E_ERR_PARAM;
1756
1757 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1758
1759 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1760 cmd->driver_major_ver = dv->major_version;
1761 cmd->driver_minor_ver = dv->minor_version;
1762 cmd->driver_build_ver = dv->build_version;
1763 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 1764
1765 len = 0;
1766 while (len < sizeof(dv->driver_string) &&
1767 (dv->driver_string[len] < 0x80) &&
1768 dv->driver_string[len])
1769 len++;
1770 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1771 len, cmd_details);
56a62fc8
JB		 1772
1773 return status;
1774}
1775
1776/**
1777 * i40e_get_link_status - get status of the HW network link
1778 * @hw: pointer to the hw struct
1779 *
1780 * Returns true if link is up, false if link is down.
1781 *
1782 * Side effect: LinkStatusEvent reporting becomes enabled
1783 **/
1784bool i40e_get_link_status(struct i40e_hw *hw)
1785{
1786 i40e_status status = 0;
1787 bool link_status = false;
1788
1789 if (hw->phy.get_link_info) {
1790 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1791
1792 if (status)
1793 goto i40e_get_link_status_exit;
1794 }
1795
1796 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1797
1798i40e_get_link_status_exit:
1799 return link_status;
1800}
1801
1802/**
1803 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1804 * @hw: pointer to the hw struct
1805 * @uplink_seid: the MAC or other gizmo SEID
1806 * @downlink_seid: the VSI SEID
1807 * @enabled_tc: bitmap of TCs to be enabled
1808 * @default_port: true for default port VSI, false for control port
e1c51b95 1809 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 1810 * @veb_seid: pointer to where to put the resulting VEB SEID
1811 * @cmd_details: pointer to command details structure or NULL
1812 *
1813 * This asks the FW to add a VEB between the uplink and downlink
1814 * elements. If the uplink SEID is 0, this will be a floating VEB.
1815 **/
1816i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1817 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 1818 bool default_port, bool enable_l2_filtering,
1819 u16 *veb_seid,
56a62fc8
JB		 1820 struct i40e_asq_cmd_details *cmd_details)
1821{
1822 struct i40e_aq_desc desc;
1823 struct i40e_aqc_add_veb *cmd =
1824 (struct i40e_aqc_add_veb *)&desc.params.raw;
1825 struct i40e_aqc_add_veb_completion *resp =
1826 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1827 i40e_status status;
1828 u16 veb_flags = 0;
1829
1830 /* SEIDs need to either both be set or both be 0 for floating VEB */
1831 if (!!uplink_seid != !!downlink_seid)
1832 return I40E_ERR_PARAM;
1833
1834 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1835
1836 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1837 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1838 cmd->enable_tcs = enabled_tc;
1839 if (!uplink_seid)
1840 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1841 if (default_port)
1842 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1843 else
1844 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1845
1846 if (enable_l2_filtering)
1847 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1848
56a62fc8
JB		 1849 cmd->veb_flags = cpu_to_le16(veb_flags);
1850
1851 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1852
1853 if (!status && veb_seid)
1854 *veb_seid = le16_to_cpu(resp->veb_seid);
1855
1856 return status;
1857}
1858
1859/**
1860 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1861 * @hw: pointer to the hw struct
1862 * @veb_seid: the SEID of the VEB to query
1863 * @switch_id: the uplink switch id
98d44381 1864 * @floating: set to true if the VEB is floating
56a62fc8
JB		 1865 * @statistic_index: index of the stats counter block for this VEB
1866 * @vebs_used: number of VEB's used by function
98d44381 1867 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 1868 * @cmd_details: pointer to command details structure or NULL
1869 *
1870 * This retrieves the parameters for a particular VEB, specified by
1871 * uplink_seid, and returns them to the caller.
1872 **/
1873i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1874 u16 veb_seid, u16 *switch_id,
1875 bool *floating, u16 *statistic_index,
1876 u16 *vebs_used, u16 *vebs_free,
1877 struct i40e_asq_cmd_details *cmd_details)
1878{
1879 struct i40e_aq_desc desc;
1880 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1881 (struct i40e_aqc_get_veb_parameters_completion *)
1882 &desc.params.raw;
1883 i40e_status status;
1884
1885 if (veb_seid == 0)
1886 return I40E_ERR_PARAM;
1887
1888 i40e_fill_default_direct_cmd_desc(&desc,
1889 i40e_aqc_opc_get_veb_parameters);
1890 cmd_resp->seid = cpu_to_le16(veb_seid);
1891
1892 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1893 if (status)
1894 goto get_veb_exit;
1895
1896 if (switch_id)
1897 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1898 if (statistic_index)
1899 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1900 if (vebs_used)
1901 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1902 if (vebs_free)
1903 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1904 if (floating) {
1905 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1906 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1907 *floating = true;
1908 else
1909 *floating = false;
1910 }
1911
1912get_veb_exit:
1913 return status;
1914}
1915
1916/**
1917 * i40e_aq_add_macvlan
1918 * @hw: pointer to the hw struct
1919 * @seid: VSI for the mac address
1920 * @mv_list: list of macvlans to be added
1921 * @count: length of the list
1922 * @cmd_details: pointer to command details structure or NULL
1923 *
1924 * Add MAC/VLAN addresses to the HW filtering
1925 **/
1926i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1927 struct i40e_aqc_add_macvlan_element_data *mv_list,
1928 u16 count, struct i40e_asq_cmd_details *cmd_details)
1929{
1930 struct i40e_aq_desc desc;
1931 struct i40e_aqc_macvlan *cmd =
1932 (struct i40e_aqc_macvlan *)&desc.params.raw;
1933 i40e_status status;
1934 u16 buf_size;
1935
1936 if (count == 0 || !mv_list || !hw)
1937 return I40E_ERR_PARAM;
1938
1939 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1940
1941 /* prep the rest of the request */
1942 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1943 cmd->num_addresses = cpu_to_le16(count);
1944 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1945 cmd->seid[1] = 0;
1946 cmd->seid[2] = 0;
1947
1948 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1949 if (buf_size > I40E_AQ_LARGE_BUF)
1950 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1951
1952 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1953 cmd_details);
1954
1955 return status;
1956}
1957
1958/**
1959 * i40e_aq_remove_macvlan
1960 * @hw: pointer to the hw struct
1961 * @seid: VSI for the mac address
1962 * @mv_list: list of macvlans to be removed
1963 * @count: length of the list
1964 * @cmd_details: pointer to command details structure or NULL
1965 *
1966 * Remove MAC/VLAN addresses from the HW filtering
1967 **/
1968i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1969 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1970 u16 count, struct i40e_asq_cmd_details *cmd_details)
1971{
1972 struct i40e_aq_desc desc;
1973 struct i40e_aqc_macvlan *cmd =
1974 (struct i40e_aqc_macvlan *)&desc.params.raw;
1975 i40e_status status;
1976 u16 buf_size;
1977
1978 if (count == 0 || !mv_list || !hw)
1979 return I40E_ERR_PARAM;
1980
1981 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1982
1983 /* prep the rest of the request */
1984 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1985 cmd->num_addresses = cpu_to_le16(count);
1986 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1987 cmd->seid[1] = 0;
1988 cmd->seid[2] = 0;
1989
1990 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1991 if (buf_size > I40E_AQ_LARGE_BUF)
1992 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1993
1994 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1995 cmd_details);
1996
1997 return status;
1998}
1999
56a62fc8
JB		 2000/**
2001 * i40e_aq_send_msg_to_vf
2002 * @hw: pointer to the hardware structure
2003 * @vfid: vf id to send msg
98d44381
JK		 2004 * @v_opcode: opcodes for VF-PF communication
2005 * @v_retval: return error code
56a62fc8
JB		 2006 * @msg: pointer to the msg buffer
2007 * @msglen: msg length
2008 * @cmd_details: pointer to command details
2009 *
2010 * send msg to vf
2011 **/
2012i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2013 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2014 struct i40e_asq_cmd_details *cmd_details)
2015{
2016 struct i40e_aq_desc desc;
2017 struct i40e_aqc_pf_vf_message *cmd =
2018 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2019 i40e_status status;
2020
2021 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2022 cmd->id = cpu_to_le32(vfid);
2023 desc.cookie_high = cpu_to_le32(v_opcode);
2024 desc.cookie_low = cpu_to_le32(v_retval);
2025 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2026 if (msglen) {
2027 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2028 I40E_AQ_FLAG_RD));
2029 if (msglen > I40E_AQ_LARGE_BUF)
2030 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2031 desc.datalen = cpu_to_le16(msglen);
2032 }
2033 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2034
2035 return status;
2036}
2037
53db45cd
SN		 2038/**
2039 * i40e_aq_debug_write_register
2040 * @hw: pointer to the hw struct
2041 * @reg_addr: register address
2042 * @reg_val: register value
2043 * @cmd_details: pointer to command details structure or NULL
2044 *
2045 * Write to a register using the admin queue commands
2046 **/
2047i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2048 u32 reg_addr, u64 reg_val,
2049 struct i40e_asq_cmd_details *cmd_details)
2050{
2051 struct i40e_aq_desc desc;
2052 struct i40e_aqc_debug_reg_read_write *cmd =
2053 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2054 i40e_status status;
2055
2056 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2057
2058 cmd->address = cpu_to_le32(reg_addr);
2059 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2060 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2061
2062 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2063
2064 return status;
2065}
2066
56a62fc8
JB		 2067/**
2068 * i40e_aq_set_hmc_resource_profile
2069 * @hw: pointer to the hw struct
2070 * @profile: type of profile the HMC is to be set as
2071 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2072 * @cmd_details: pointer to command details structure or NULL
2073 *
2074 * set the HMC profile of the device.
2075 **/
2076i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2077 enum i40e_aq_hmc_profile profile,
2078 u8 pe_vf_enabled_count,
2079 struct i40e_asq_cmd_details *cmd_details)
2080{
2081 struct i40e_aq_desc desc;
2082 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2083 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2084 i40e_status status;
2085
2086 i40e_fill_default_direct_cmd_desc(&desc,
2087 i40e_aqc_opc_set_hmc_resource_profile);
2088
2089 cmd->pm_profile = (u8)profile;
2090 cmd->pe_vf_enabled = pe_vf_enabled_count;
2091
2092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2093
2094 return status;
2095}
2096
2097/**
2098 * i40e_aq_request_resource
2099 * @hw: pointer to the hw struct
2100 * @resource: resource id
2101 * @access: access type
2102 * @sdp_number: resource number
2103 * @timeout: the maximum time in ms that the driver may hold the resource
2104 * @cmd_details: pointer to command details structure or NULL
2105 *
2106 * requests common resource using the admin queue commands
2107 **/
2108i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2109 enum i40e_aq_resources_ids resource,
2110 enum i40e_aq_resource_access_type access,
2111 u8 sdp_number, u64 *timeout,
2112 struct i40e_asq_cmd_details *cmd_details)
2113{
2114 struct i40e_aq_desc desc;
2115 struct i40e_aqc_request_resource *cmd_resp =
2116 (struct i40e_aqc_request_resource *)&desc.params.raw;
2117 i40e_status status;
2118
2119 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2120
2121 cmd_resp->resource_id = cpu_to_le16(resource);
2122 cmd_resp->access_type = cpu_to_le16(access);
2123 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2124
2125 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2126 /* The completion specifies the maximum time in ms that the driver
2127 * may hold the resource in the Timeout field.
2128 * If the resource is held by someone else, the command completes with
2129 * busy return value and the timeout field indicates the maximum time
2130 * the current owner of the resource has to free it.
2131 */
2132 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2133 *timeout = le32_to_cpu(cmd_resp->timeout);
2134
2135 return status;
2136}
2137
2138/**
2139 * i40e_aq_release_resource
2140 * @hw: pointer to the hw struct
2141 * @resource: resource id
2142 * @sdp_number: resource number
2143 * @cmd_details: pointer to command details structure or NULL
2144 *
2145 * release common resource using the admin queue commands
2146 **/
2147i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2148 enum i40e_aq_resources_ids resource,
2149 u8 sdp_number,
2150 struct i40e_asq_cmd_details *cmd_details)
2151{
2152 struct i40e_aq_desc desc;
2153 struct i40e_aqc_request_resource *cmd =
2154 (struct i40e_aqc_request_resource *)&desc.params.raw;
2155 i40e_status status;
2156
2157 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2158
2159 cmd->resource_id = cpu_to_le16(resource);
2160 cmd->resource_number = cpu_to_le32(sdp_number);
2161
2162 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2163
2164 return status;
2165}
2166
2167/**
2168 * i40e_aq_read_nvm
2169 * @hw: pointer to the hw struct
2170 * @module_pointer: module pointer location in words from the NVM beginning
2171 * @offset: byte offset from the module beginning
2172 * @length: length of the section to be read (in bytes from the offset)
2173 * @data: command buffer (size [bytes] = length)
2174 * @last_command: tells if this is the last command in a series
2175 * @cmd_details: pointer to command details structure or NULL
2176 *
2177 * Read the NVM using the admin queue commands
2178 **/
2179i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2180 u32 offset, u16 length, void *data,
2181 bool last_command,
2182 struct i40e_asq_cmd_details *cmd_details)
2183{
2184 struct i40e_aq_desc desc;
2185 struct i40e_aqc_nvm_update *cmd =
2186 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2187 i40e_status status;
2188
2189 /* In offset the highest byte must be zeroed. */
2190 if (offset & 0xFF000000) {
2191 status = I40E_ERR_PARAM;
2192 goto i40e_aq_read_nvm_exit;
2193 }
2194
2195 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2196
2197 /* If this is the last command in a series, set the proper flag. */
2198 if (last_command)
2199 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2200 cmd->module_pointer = module_pointer;
2201 cmd->offset = cpu_to_le32(offset);
2202 cmd->length = cpu_to_le16(length);
2203
2204 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2205 if (length > I40E_AQ_LARGE_BUF)
2206 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2207
2208 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2209
2210i40e_aq_read_nvm_exit:
2211 return status;
2212}
2213
cd552cb4
SN		 2214/**
2215 * i40e_aq_erase_nvm
2216 * @hw: pointer to the hw struct
2217 * @module_pointer: module pointer location in words from the NVM beginning
2218 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2219 * @length: length of the section to be erased (expressed in 4 KB)
2220 * @last_command: tells if this is the last command in a series
2221 * @cmd_details: pointer to command details structure or NULL
2222 *
2223 * Erase the NVM sector using the admin queue commands
2224 **/
2225i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2226 u32 offset, u16 length, bool last_command,
2227 struct i40e_asq_cmd_details *cmd_details)
2228{
2229 struct i40e_aq_desc desc;
2230 struct i40e_aqc_nvm_update *cmd =
2231 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2232 i40e_status status;
2233
2234 /* In offset the highest byte must be zeroed. */
2235 if (offset & 0xFF000000) {
2236 status = I40E_ERR_PARAM;
2237 goto i40e_aq_erase_nvm_exit;
2238 }
2239
2240 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2241
2242 /* If this is the last command in a series, set the proper flag. */
2243 if (last_command)
2244 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2245 cmd->module_pointer = module_pointer;
2246 cmd->offset = cpu_to_le32(offset);
2247 cmd->length = cpu_to_le16(length);
2248
2249 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2250
2251i40e_aq_erase_nvm_exit:
2252 return status;
2253}
2254
56a62fc8
JB		 2255#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2256#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2257#define I40E_DEV_FUNC_CAP_NPAR 0x03
2258#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2259#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2260#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2261#define I40E_DEV_FUNC_CAP_VF 0x13
2262#define I40E_DEV_FUNC_CAP_VMDQ 0x14
2263#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2264#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2265#define I40E_DEV_FUNC_CAP_VSI 0x17
2266#define I40E_DEV_FUNC_CAP_DCB 0x18
2267#define I40E_DEV_FUNC_CAP_FCOE 0x21
2268#define I40E_DEV_FUNC_CAP_RSS 0x40
2269#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2270#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2271#define I40E_DEV_FUNC_CAP_MSIX 0x43
2272#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2273#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2274#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2275#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2276#define I40E_DEV_FUNC_CAP_CEM 0xF2
2277#define I40E_DEV_FUNC_CAP_IWARP 0x51
2278#define I40E_DEV_FUNC_CAP_LED 0x61
2279#define I40E_DEV_FUNC_CAP_SDP 0x62
2280#define I40E_DEV_FUNC_CAP_MDIO 0x63
2281
2282/**
2283 * i40e_parse_discover_capabilities
2284 * @hw: pointer to the hw struct
2285 * @buff: pointer to a buffer containing device/function capability records
2286 * @cap_count: number of capability records in the list
2287 * @list_type_opc: type of capabilities list to parse
2288 *
2289 * Parse the device/function capabilities list.
2290 **/
2291static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2292 u32 cap_count,
2293 enum i40e_admin_queue_opc list_type_opc)
2294{
2295 struct i40e_aqc_list_capabilities_element_resp *cap;
2296 u32 number, logical_id, phys_id;
2297 struct i40e_hw_capabilities *p;
56a62fc8
JB		 2298 u32 i = 0;
2299 u16 id;
2300
2301 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2302
2303 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 2304 p = &hw->dev_caps;
56a62fc8 2305 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 2306 p = &hw->func_caps;
56a62fc8
JB		 2307 else
2308 return;
2309
2310 for (i = 0; i < cap_count; i++, cap++) {
2311 id = le16_to_cpu(cap->id);
2312 number = le32_to_cpu(cap->number);
2313 logical_id = le32_to_cpu(cap->logical_id);
2314 phys_id = le32_to_cpu(cap->phys_id);
2315
2316 switch (id) {
2317 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2318 p->switch_mode = number;
2319 break;
2320 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2321 p->management_mode = number;
2322 break;
2323 case I40E_DEV_FUNC_CAP_NPAR:
2324 p->npar_enable = number;
2325 break;
2326 case I40E_DEV_FUNC_CAP_OS2BMC:
2327 p->os2bmc = number;
2328 break;
2329 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2330 p->valid_functions = number;
2331 break;
2332 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2333 if (number == 1)
2334 p->sr_iov_1_1 = true;
2335 break;
2336 case I40E_DEV_FUNC_CAP_VF:
2337 p->num_vfs = number;
2338 p->vf_base_id = logical_id;
2339 break;
2340 case I40E_DEV_FUNC_CAP_VMDQ:
2341 if (number == 1)
2342 p->vmdq = true;
2343 break;
2344 case I40E_DEV_FUNC_CAP_802_1_QBG:
2345 if (number == 1)
2346 p->evb_802_1_qbg = true;
2347 break;
2348 case I40E_DEV_FUNC_CAP_802_1_QBH:
2349 if (number == 1)
2350 p->evb_802_1_qbh = true;
2351 break;
2352 case I40E_DEV_FUNC_CAP_VSI:
2353 p->num_vsis = number;
2354 break;
2355 case I40E_DEV_FUNC_CAP_DCB:
2356 if (number == 1) {
2357 p->dcb = true;
2358 p->enabled_tcmap = logical_id;
2359 p->maxtc = phys_id;
2360 }
2361 break;
2362 case I40E_DEV_FUNC_CAP_FCOE:
2363 if (number == 1)
2364 p->fcoe = true;
2365 break;
2366 case I40E_DEV_FUNC_CAP_RSS:
2367 p->rss = true;
e157ea30 2368 p->rss_table_size = number;
56a62fc8
JB		 2369 p->rss_table_entry_width = logical_id;
2370 break;
2371 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2372 p->num_rx_qp = number;
2373 p->base_queue = phys_id;
2374 break;
2375 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2376 p->num_tx_qp = number;
2377 p->base_queue = phys_id;
2378 break;
2379 case I40E_DEV_FUNC_CAP_MSIX:
2380 p->num_msix_vectors = number;
2381 break;
2382 case I40E_DEV_FUNC_CAP_MSIX_VF:
2383 p->num_msix_vectors_vf = number;
2384 break;
2385 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2386 if (number == 1)
2387 p->mfp_mode_1 = true;
2388 break;
2389 case I40E_DEV_FUNC_CAP_CEM:
2390 if (number == 1)
2391 p->mgmt_cem = true;
2392 break;
2393 case I40E_DEV_FUNC_CAP_IWARP:
2394 if (number == 1)
2395 p->iwarp = true;
2396 break;
2397 case I40E_DEV_FUNC_CAP_LED:
2398 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2399 p->led[phys_id] = true;
2400 break;
2401 case I40E_DEV_FUNC_CAP_SDP:
2402 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2403 p->sdp[phys_id] = true;
2404 break;
2405 case I40E_DEV_FUNC_CAP_MDIO:
2406 if (number == 1) {
2407 p->mdio_port_num = phys_id;
2408 p->mdio_port_mode = logical_id;
2409 }
2410 break;
2411 case I40E_DEV_FUNC_CAP_IEEE_1588:
2412 if (number == 1)
2413 p->ieee_1588 = true;
2414 break;
2415 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2416 p->fd = true;
2417 p->fd_filters_guaranteed = number;
2418 p->fd_filters_best_effort = logical_id;
2419 break;
2420 default:
2421 break;
2422 }
2423 }
2424
566bb85d
VD		 2425 /* Software override ensuring FCoE is disabled if npar or mfp
2426 * mode because it is not supported in these modes.
2427 */
2428 if (p->npar_enable || p->mfp_mode_1)
2429 p->fcoe = false;
2430
56a62fc8
JB		 2431 /* additional HW specific goodies that might
2432 * someday be HW version specific
2433 */
2434 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2435}
2436
2437/**
2438 * i40e_aq_discover_capabilities
2439 * @hw: pointer to the hw struct
2440 * @buff: a virtual buffer to hold the capabilities
2441 * @buff_size: Size of the virtual buffer
2442 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2443 * @list_type_opc: capabilities type to discover - pass in the command opcode
2444 * @cmd_details: pointer to command details structure or NULL
2445 *
2446 * Get the device capabilities descriptions from the firmware
2447 **/
2448i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2449 void *buff, u16 buff_size, u16 *data_size,
2450 enum i40e_admin_queue_opc list_type_opc,
2451 struct i40e_asq_cmd_details *cmd_details)
2452{
2453 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 2454 struct i40e_aq_desc desc;
8fb905b3 2455 i40e_status status = 0;
56a62fc8
JB		 2456
2457 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2458
2459 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2460 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2461 status = I40E_ERR_PARAM;
2462 goto exit;
2463 }
2464
2465 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2466
2467 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2468 if (buff_size > I40E_AQ_LARGE_BUF)
2469 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2470
2471 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2472 *data_size = le16_to_cpu(desc.datalen);
2473
2474 if (status)
2475 goto exit;
2476
2477 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2478 list_type_opc);
2479
2480exit:
2481 return status;
2482}
2483
cd552cb4
SN		 2484/**
2485 * i40e_aq_update_nvm
2486 * @hw: pointer to the hw struct
2487 * @module_pointer: module pointer location in words from the NVM beginning
2488 * @offset: byte offset from the module beginning
2489 * @length: length of the section to be written (in bytes from the offset)
2490 * @data: command buffer (size [bytes] = length)
2491 * @last_command: tells if this is the last command in a series
2492 * @cmd_details: pointer to command details structure or NULL
2493 *
2494 * Update the NVM using the admin queue commands
2495 **/
2496i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2497 u32 offset, u16 length, void *data,
2498 bool last_command,
2499 struct i40e_asq_cmd_details *cmd_details)
2500{
2501 struct i40e_aq_desc desc;
2502 struct i40e_aqc_nvm_update *cmd =
2503 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2504 i40e_status status;
2505
2506 /* In offset the highest byte must be zeroed. */
2507 if (offset & 0xFF000000) {
2508 status = I40E_ERR_PARAM;
2509 goto i40e_aq_update_nvm_exit;
2510 }
2511
2512 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2513
2514 /* If this is the last command in a series, set the proper flag. */
2515 if (last_command)
2516 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2517 cmd->module_pointer = module_pointer;
2518 cmd->offset = cpu_to_le32(offset);
2519 cmd->length = cpu_to_le16(length);
2520
2521 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2522 if (length > I40E_AQ_LARGE_BUF)
2523 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2524
2525 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2526
2527i40e_aq_update_nvm_exit:
2528 return status;
2529}
2530
56a62fc8
JB		 2531/**
2532 * i40e_aq_get_lldp_mib
2533 * @hw: pointer to the hw struct
2534 * @bridge_type: type of bridge requested
2535 * @mib_type: Local, Remote or both Local and Remote MIBs
2536 * @buff: pointer to a user supplied buffer to store the MIB block
2537 * @buff_size: size of the buffer (in bytes)
2538 * @local_len : length of the returned Local LLDP MIB
2539 * @remote_len: length of the returned Remote LLDP MIB
2540 * @cmd_details: pointer to command details structure or NULL
2541 *
2542 * Requests the complete LLDP MIB (entire packet).
2543 **/
2544i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2545 u8 mib_type, void *buff, u16 buff_size,
2546 u16 *local_len, u16 *remote_len,
2547 struct i40e_asq_cmd_details *cmd_details)
2548{
2549 struct i40e_aq_desc desc;
2550 struct i40e_aqc_lldp_get_mib *cmd =
2551 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2552 struct i40e_aqc_lldp_get_mib *resp =
2553 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2554 i40e_status status;
2555
2556 if (buff_size == 0 || !buff)
2557 return I40E_ERR_PARAM;
2558
2559 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2560 /* Indirect Command */
2561 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2562
2563 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2564 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2565 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2566
2567 desc.datalen = cpu_to_le16(buff_size);
2568
2569 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2570 if (buff_size > I40E_AQ_LARGE_BUF)
2571 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2572
2573 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2574 if (!status) {
2575 if (local_len != NULL)
2576 *local_len = le16_to_cpu(resp->local_len);
2577 if (remote_len != NULL)
2578 *remote_len = le16_to_cpu(resp->remote_len);
2579 }
2580
2581 return status;
2582}
2583
2584/**
2585 * i40e_aq_cfg_lldp_mib_change_event
2586 * @hw: pointer to the hw struct
2587 * @enable_update: Enable or Disable event posting
2588 * @cmd_details: pointer to command details structure or NULL
2589 *
2590 * Enable or Disable posting of an event on ARQ when LLDP MIB
2591 * associated with the interface changes
2592 **/
2593i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2594 bool enable_update,
2595 struct i40e_asq_cmd_details *cmd_details)
2596{
2597 struct i40e_aq_desc desc;
2598 struct i40e_aqc_lldp_update_mib *cmd =
2599 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2600 i40e_status status;
2601
2602 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2603
2604 if (!enable_update)
2605 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2606
2607 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2608
2609 return status;
2610}
2611
2612/**
2613 * i40e_aq_stop_lldp
2614 * @hw: pointer to the hw struct
2615 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2616 * @cmd_details: pointer to command details structure or NULL
2617 *
2618 * Stop or Shutdown the embedded LLDP Agent
2619 **/
2620i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2621 struct i40e_asq_cmd_details *cmd_details)
2622{
2623 struct i40e_aq_desc desc;
2624 struct i40e_aqc_lldp_stop *cmd =
2625 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2626 i40e_status status;
2627
2628 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2629
2630 if (shutdown_agent)
2631 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2632
2633 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2634
2635 return status;
2636}
2637
2638/**
2639 * i40e_aq_start_lldp
2640 * @hw: pointer to the hw struct
2641 * @cmd_details: pointer to command details structure or NULL
2642 *
2643 * Start the embedded LLDP Agent on all ports.
2644 **/
2645i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2646 struct i40e_asq_cmd_details *cmd_details)
2647{
2648 struct i40e_aq_desc desc;
2649 struct i40e_aqc_lldp_start *cmd =
2650 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2651 i40e_status status;
2652
2653 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2654
2655 cmd->command = I40E_AQ_LLDP_AGENT_START;
2656
2657 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2658
2659 return status;
2660}
2661
a1c9a9d9
JK		 2662/**
2663 * i40e_aq_add_udp_tunnel
2664 * @hw: pointer to the hw struct
2665 * @udp_port: the UDP port to add
2666 * @header_len: length of the tunneling header length in DWords
2667 * @protocol_index: protocol index type
98d44381 2668 * @filter_index: pointer to filter index
a1c9a9d9
JK		 2669 * @cmd_details: pointer to command details structure or NULL
2670 **/
2671i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 2672 u16 udp_port, u8 protocol_index,
2673 u8 *filter_index,
a1c9a9d9
JK		 2674 struct i40e_asq_cmd_details *cmd_details)
2675{
2676 struct i40e_aq_desc desc;
2677 struct i40e_aqc_add_udp_tunnel *cmd =
2678 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2679 struct i40e_aqc_del_udp_tunnel_completion *resp =
2680 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2681 i40e_status status;
2682
2683 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2684
2685 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 2686 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 2687
2688 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2689
2690 if (!status)
2691 *filter_index = resp->index;
2692
2693 return status;
2694}
2695
2696/**
2697 * i40e_aq_del_udp_tunnel
2698 * @hw: pointer to the hw struct
2699 * @index: filter index
2700 * @cmd_details: pointer to command details structure or NULL
2701 **/
2702i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2703 struct i40e_asq_cmd_details *cmd_details)
2704{
2705 struct i40e_aq_desc desc;
2706 struct i40e_aqc_remove_udp_tunnel *cmd =
2707 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2708 i40e_status status;
2709
2710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2711
2712 cmd->index = index;
2713
2714 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2715
2716 return status;
2717}
2718
56a62fc8
JB		 2719/**
2720 * i40e_aq_delete_element - Delete switch element
2721 * @hw: pointer to the hw struct
2722 * @seid: the SEID to delete from the switch
2723 * @cmd_details: pointer to command details structure or NULL
2724 *
2725 * This deletes a switch element from the switch.
2726 **/
2727i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2728 struct i40e_asq_cmd_details *cmd_details)
2729{
2730 struct i40e_aq_desc desc;
2731 struct i40e_aqc_switch_seid *cmd =
2732 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2733 i40e_status status;
2734
2735 if (seid == 0)
2736 return I40E_ERR_PARAM;
2737
2738 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2739
2740 cmd->seid = cpu_to_le16(seid);
2741
2742 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2743
2744 return status;
2745}
2746
afb3ff0d
NP		 2747/**
2748 * i40e_aq_dcb_updated - DCB Updated Command
2749 * @hw: pointer to the hw struct
2750 * @cmd_details: pointer to command details structure or NULL
2751 *
2752 * EMP will return when the shared RPB settings have been
2753 * recomputed and modified. The retval field in the descriptor
2754 * will be set to 0 when RPB is modified.
2755 **/
2756i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2757 struct i40e_asq_cmd_details *cmd_details)
2758{
2759 struct i40e_aq_desc desc;
2760 i40e_status status;
2761
2762 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2763
2764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2765
2766 return status;
2767}
2768
56a62fc8
JB		 2769/**
2770 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2771 * @hw: pointer to the hw struct
2772 * @seid: seid for the physical port/switching component/vsi
2773 * @buff: Indirect buffer to hold data parameters and response
2774 * @buff_size: Indirect buffer size
2775 * @opcode: Tx scheduler AQ command opcode
2776 * @cmd_details: pointer to command details structure or NULL
2777 *
2778 * Generic command handler for Tx scheduler AQ commands
2779 **/
2780static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2781 void *buff, u16 buff_size,
2782 enum i40e_admin_queue_opc opcode,
2783 struct i40e_asq_cmd_details *cmd_details)
2784{
2785 struct i40e_aq_desc desc;
2786 struct i40e_aqc_tx_sched_ind *cmd =
2787 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2788 i40e_status status;
2789 bool cmd_param_flag = false;
2790
2791 switch (opcode) {
2792 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2793 case i40e_aqc_opc_configure_vsi_tc_bw:
2794 case i40e_aqc_opc_enable_switching_comp_ets:
2795 case i40e_aqc_opc_modify_switching_comp_ets:
2796 case i40e_aqc_opc_disable_switching_comp_ets:
2797 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2798 case i40e_aqc_opc_configure_switching_comp_bw_config:
2799 cmd_param_flag = true;
2800 break;
2801 case i40e_aqc_opc_query_vsi_bw_config:
2802 case i40e_aqc_opc_query_vsi_ets_sla_config:
2803 case i40e_aqc_opc_query_switching_comp_ets_config:
2804 case i40e_aqc_opc_query_port_ets_config:
2805 case i40e_aqc_opc_query_switching_comp_bw_config:
2806 cmd_param_flag = false;
2807 break;
2808 default:
2809 return I40E_ERR_PARAM;
2810 }
2811
2812 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2813
2814 /* Indirect command */
2815 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2816 if (cmd_param_flag)
2817 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2818 if (buff_size > I40E_AQ_LARGE_BUF)
2819 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2820
2821 desc.datalen = cpu_to_le16(buff_size);
2822
2823 cmd->vsi_seid = cpu_to_le16(seid);
2824
2825 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2826
2827 return status;
2828}
2829
6b192891
MW		 2830/**
2831 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2832 * @hw: pointer to the hw struct
2833 * @seid: VSI seid
2834 * @credit: BW limit credits (0 = disabled)
2835 * @max_credit: Max BW limit credits
2836 * @cmd_details: pointer to command details structure or NULL
2837 **/
2838i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2839 u16 seid, u16 credit, u8 max_credit,
2840 struct i40e_asq_cmd_details *cmd_details)
2841{
2842 struct i40e_aq_desc desc;
2843 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2844 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2845 i40e_status status;
2846
2847 i40e_fill_default_direct_cmd_desc(&desc,
2848 i40e_aqc_opc_configure_vsi_bw_limit);
2849
2850 cmd->vsi_seid = cpu_to_le16(seid);
2851 cmd->credit = cpu_to_le16(credit);
2852 cmd->max_credit = max_credit;
2853
2854 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2855
2856 return status;
2857}
2858
56a62fc8
JB		 2859/**
2860 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2861 * @hw: pointer to the hw struct
2862 * @seid: VSI seid
2863 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2864 * @cmd_details: pointer to command details structure or NULL
2865 **/
2866i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2867 u16 seid,
2868 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2869 struct i40e_asq_cmd_details *cmd_details)
2870{
2871 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2872 i40e_aqc_opc_configure_vsi_tc_bw,
2873 cmd_details);
2874}
2875
afb3ff0d
NP		 2876/**
2877 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2878 * @hw: pointer to the hw struct
2879 * @seid: seid of the switching component connected to Physical Port
2880 * @ets_data: Buffer holding ETS parameters
2881 * @cmd_details: pointer to command details structure or NULL
2882 **/
2883i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2884 u16 seid,
2885 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2886 enum i40e_admin_queue_opc opcode,
2887 struct i40e_asq_cmd_details *cmd_details)
2888{
2889 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2890 sizeof(*ets_data), opcode, cmd_details);
2891}
2892
2893/**
2894 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2895 * @hw: pointer to the hw struct
2896 * @seid: seid of the switching component
2897 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2898 * @cmd_details: pointer to command details structure or NULL
2899 **/
2900i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2901 u16 seid,
2902 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2903 struct i40e_asq_cmd_details *cmd_details)
2904{
2905 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2906 i40e_aqc_opc_configure_switching_comp_bw_config,
2907 cmd_details);
2908}
2909
56a62fc8
JB		 2910/**
2911 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2912 * @hw: pointer to the hw struct
2913 * @seid: seid of the VSI
2914 * @bw_data: Buffer to hold VSI BW configuration
2915 * @cmd_details: pointer to command details structure or NULL
2916 **/
2917i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2918 u16 seid,
2919 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2920 struct i40e_asq_cmd_details *cmd_details)
2921{
2922 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2923 i40e_aqc_opc_query_vsi_bw_config,
2924 cmd_details);
2925}
2926
2927/**
2928 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2929 * @hw: pointer to the hw struct
2930 * @seid: seid of the VSI
2931 * @bw_data: Buffer to hold VSI BW configuration per TC
2932 * @cmd_details: pointer to command details structure or NULL
2933 **/
2934i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2935 u16 seid,
2936 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2937 struct i40e_asq_cmd_details *cmd_details)
2938{
2939 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2940 i40e_aqc_opc_query_vsi_ets_sla_config,
2941 cmd_details);
2942}
2943
2944/**
2945 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2946 * @hw: pointer to the hw struct
2947 * @seid: seid of the switching component
2948 * @bw_data: Buffer to hold switching component's per TC BW config
2949 * @cmd_details: pointer to command details structure or NULL
2950 **/
2951i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2952 u16 seid,
2953 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2954 struct i40e_asq_cmd_details *cmd_details)
2955{
2956 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2957 i40e_aqc_opc_query_switching_comp_ets_config,
2958 cmd_details);
2959}
2960
2961/**
2962 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2963 * @hw: pointer to the hw struct
2964 * @seid: seid of the VSI or switching component connected to Physical Port
2965 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2966 * @cmd_details: pointer to command details structure or NULL
2967 **/
2968i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2969 u16 seid,
2970 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2971 struct i40e_asq_cmd_details *cmd_details)
2972{
2973 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2974 i40e_aqc_opc_query_port_ets_config,
2975 cmd_details);
2976}
2977
2978/**
2979 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2980 * @hw: pointer to the hw struct
2981 * @seid: seid of the switching component
2982 * @bw_data: Buffer to hold switching component's BW configuration
2983 * @cmd_details: pointer to command details structure or NULL
2984 **/
2985i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2986 u16 seid,
2987 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2988 struct i40e_asq_cmd_details *cmd_details)
2989{
2990 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2991 i40e_aqc_opc_query_switching_comp_bw_config,
2992 cmd_details);
2993}
2994
2995/**
2996 * i40e_validate_filter_settings
2997 * @hw: pointer to the hardware structure
2998 * @settings: Filter control settings
2999 *
3000 * Check and validate the filter control settings passed.
3001 * The function checks for the valid filter/context sizes being
3002 * passed for FCoE and PE.
3003 *
3004 * Returns 0 if the values passed are valid and within
3005 * range else returns an error.
3006 **/
3007static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3008 struct i40e_filter_control_settings *settings)
3009{
3010 u32 fcoe_cntx_size, fcoe_filt_size;
3011 u32 pe_cntx_size, pe_filt_size;
467d729a 3012 u32 fcoe_fmax;
56a62fc8
JB		 3013 u32 val;
3014
3015 /* Validate FCoE settings passed */
3016 switch (settings->fcoe_filt_num) {
3017 case I40E_HASH_FILTER_SIZE_1K:
3018 case I40E_HASH_FILTER_SIZE_2K:
3019 case I40E_HASH_FILTER_SIZE_4K:
3020 case I40E_HASH_FILTER_SIZE_8K:
3021 case I40E_HASH_FILTER_SIZE_16K:
3022 case I40E_HASH_FILTER_SIZE_32K:
3023 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3024 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3025 break;
3026 default:
3027 return I40E_ERR_PARAM;
3028 }
3029
3030 switch (settings->fcoe_cntx_num) {
3031 case I40E_DMA_CNTX_SIZE_512:
3032 case I40E_DMA_CNTX_SIZE_1K:
3033 case I40E_DMA_CNTX_SIZE_2K:
3034 case I40E_DMA_CNTX_SIZE_4K:
3035 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3036 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3037 break;
3038 default:
3039 return I40E_ERR_PARAM;
3040 }
3041
3042 /* Validate PE settings passed */
3043 switch (settings->pe_filt_num) {
3044 case I40E_HASH_FILTER_SIZE_1K:
3045 case I40E_HASH_FILTER_SIZE_2K:
3046 case I40E_HASH_FILTER_SIZE_4K:
3047 case I40E_HASH_FILTER_SIZE_8K:
3048 case I40E_HASH_FILTER_SIZE_16K:
3049 case I40E_HASH_FILTER_SIZE_32K:
3050 case I40E_HASH_FILTER_SIZE_64K:
3051 case I40E_HASH_FILTER_SIZE_128K:
3052 case I40E_HASH_FILTER_SIZE_256K:
3053 case I40E_HASH_FILTER_SIZE_512K:
3054 case I40E_HASH_FILTER_SIZE_1M:
3055 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3056 pe_filt_size <<= (u32)settings->pe_filt_num;
3057 break;
3058 default:
3059 return I40E_ERR_PARAM;
3060 }
3061
3062 switch (settings->pe_cntx_num) {
3063 case I40E_DMA_CNTX_SIZE_512:
3064 case I40E_DMA_CNTX_SIZE_1K:
3065 case I40E_DMA_CNTX_SIZE_2K:
3066 case I40E_DMA_CNTX_SIZE_4K:
3067 case I40E_DMA_CNTX_SIZE_8K:
3068 case I40E_DMA_CNTX_SIZE_16K:
3069 case I40E_DMA_CNTX_SIZE_32K:
3070 case I40E_DMA_CNTX_SIZE_64K:
3071 case I40E_DMA_CNTX_SIZE_128K:
3072 case I40E_DMA_CNTX_SIZE_256K:
3073 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3074 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3075 break;
3076 default:
3077 return I40E_ERR_PARAM;
3078 }
3079
3080 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3081 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3082 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3083 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3084 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3085 return I40E_ERR_INVALID_SIZE;
3086
56a62fc8
JB		 3087 return 0;
3088}
3089
3090/**
3091 * i40e_set_filter_control
3092 * @hw: pointer to the hardware structure
3093 * @settings: Filter control settings
3094 *
3095 * Set the Queue Filters for PE/FCoE and enable filters required
3096 * for a single PF. It is expected that these settings are programmed
3097 * at the driver initialization time.
3098 **/
3099i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3100 struct i40e_filter_control_settings *settings)
3101{
3102 i40e_status ret = 0;
3103 u32 hash_lut_size = 0;
3104 u32 val;
3105
3106 if (!settings)
3107 return I40E_ERR_PARAM;
3108
3109 /* Validate the input settings */
3110 ret = i40e_validate_filter_settings(hw, settings);
3111 if (ret)
3112 return ret;
3113
3114 /* Read the PF Queue Filter control register */
3115 val = rd32(hw, I40E_PFQF_CTL_0);
3116
3117 /* Program required PE hash buckets for the PF */
3118 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3119 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3120 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3121 /* Program required PE contexts for the PF */
3122 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3123 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3124 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3125
3126 /* Program required FCoE hash buckets for the PF */
3127 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3128 val |= ((u32)settings->fcoe_filt_num <<
3129 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3130 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3131 /* Program required FCoE DDP contexts for the PF */
3132 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3133 val |= ((u32)settings->fcoe_cntx_num <<
3134 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3135 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3136
3137 /* Program Hash LUT size for the PF */
3138 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3139 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3140 hash_lut_size = 1;
3141 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3142 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3143
3144 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3145 if (settings->enable_fdir)
3146 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3147 if (settings->enable_ethtype)
3148 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3149 if (settings->enable_macvlan)
3150 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3151
3152 wr32(hw, I40E_PFQF_CTL_0, val);
3153
3154 return 0;
3155}
afb3ff0d
NP		 3156
3157/**
3158 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3159 * @hw: pointer to the hw struct
3160 * @mac_addr: MAC address to use in the filter
3161 * @ethtype: Ethertype to use in the filter
3162 * @flags: Flags that needs to be applied to the filter
3163 * @vsi_seid: seid of the control VSI
3164 * @queue: VSI queue number to send the packet to
3165 * @is_add: Add control packet filter if True else remove
3166 * @stats: Structure to hold information on control filter counts
3167 * @cmd_details: pointer to command details structure or NULL
3168 *
3169 * This command will Add or Remove control packet filter for a control VSI.
3170 * In return it will update the total number of perfect filter count in
3171 * the stats member.
3172 **/
3173i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3174 u8 *mac_addr, u16 ethtype, u16 flags,
3175 u16 vsi_seid, u16 queue, bool is_add,
3176 struct i40e_control_filter_stats *stats,
3177 struct i40e_asq_cmd_details *cmd_details)
3178{
3179 struct i40e_aq_desc desc;
3180 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3181 (struct i40e_aqc_add_remove_control_packet_filter *)
3182 &desc.params.raw;
3183 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3184 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3185 &desc.params.raw;
3186 i40e_status status;
3187
3188 if (vsi_seid == 0)
3189 return I40E_ERR_PARAM;
3190
3191 if (is_add) {
3192 i40e_fill_default_direct_cmd_desc(&desc,
3193 i40e_aqc_opc_add_control_packet_filter);
3194 cmd->queue = cpu_to_le16(queue);
3195 } else {
3196 i40e_fill_default_direct_cmd_desc(&desc,
3197 i40e_aqc_opc_remove_control_packet_filter);
3198 }
3199
3200 if (mac_addr)
3201 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3202
3203 cmd->etype = cpu_to_le16(ethtype);
3204 cmd->flags = cpu_to_le16(flags);
3205 cmd->seid = cpu_to_le16(vsi_seid);
3206
3207 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3208
3209 if (!status && stats) {
3210 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3211 stats->etype_used = le16_to_cpu(resp->etype_used);
3212 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3213 stats->etype_free = le16_to_cpu(resp->etype_free);
3214 }
3215
3216 return status;
3217}
3218
2fd75f31
NP		 3219/**
3220 * i40e_aq_resume_port_tx
3221 * @hw: pointer to the hardware structure
3222 * @cmd_details: pointer to command details structure or NULL
3223 *
3224 * Resume port's Tx traffic
3225 **/
3226i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3227 struct i40e_asq_cmd_details *cmd_details)
3228{
3229 struct i40e_aq_desc desc;
3230 i40e_status status;
3231
3232 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3233
3234 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3235
3236 return status;
3237}
3238
d4dfb81a
CS		 3239/**
3240 * i40e_set_pci_config_data - store PCI bus info
3241 * @hw: pointer to hardware structure
3242 * @link_status: the link status word from PCI config space
3243 *
3244 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3245 **/
3246void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3247{
3248 hw->bus.type = i40e_bus_type_pci_express;
3249
3250 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3251 case PCI_EXP_LNKSTA_NLW_X1:
3252 hw->bus.width = i40e_bus_width_pcie_x1;
3253 break;
3254 case PCI_EXP_LNKSTA_NLW_X2:
3255 hw->bus.width = i40e_bus_width_pcie_x2;
3256 break;
3257 case PCI_EXP_LNKSTA_NLW_X4:
3258 hw->bus.width = i40e_bus_width_pcie_x4;
3259 break;
3260 case PCI_EXP_LNKSTA_NLW_X8:
3261 hw->bus.width = i40e_bus_width_pcie_x8;
3262 break;
3263 default:
3264 hw->bus.width = i40e_bus_width_unknown;
3265 break;
3266 }
3267
3268 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3269 case PCI_EXP_LNKSTA_CLS_2_5GB:
3270 hw->bus.speed = i40e_bus_speed_2500;
3271 break;
3272 case PCI_EXP_LNKSTA_CLS_5_0GB:
3273 hw->bus.speed = i40e_bus_speed_5000;
3274 break;
3275 case PCI_EXP_LNKSTA_CLS_8_0GB:
3276 hw->bus.speed = i40e_bus_speed_8000;
3277 break;
3278 default:
3279 hw->bus.speed = i40e_bus_speed_unknown;
3280 break;
3281 }
3282}
Linux kernel - Deliverables
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