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i40e/i40evf: initialize context descriptor
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e
SN		 46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
ab60085e
SN		 50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
56a62fc8
JB		 53 hw->mac.type = I40E_MAC_XL710;
54 break;
ab60085e
SN		 55 case I40E_DEV_ID_VF:
56 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 57 hw->mac.type = I40E_MAC_VF;
58 break;
59 default:
60 hw->mac.type = I40E_MAC_GENERIC;
61 break;
62 }
63 } else {
64 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
65 }
66
67 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
68 hw->mac.type, status);
69 return status;
70}
71
72/**
73 * i40e_debug_aq
74 * @hw: debug mask related to admin queue
98d44381
JK		 75 * @mask: debug mask
76 * @desc: pointer to admin queue descriptor
56a62fc8
JB		 77 * @buffer: pointer to command buffer
78 *
79 * Dumps debug log about adminq command with descriptor contents.
80 **/
81void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
82 void *buffer)
83{
84 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
85 u8 *aq_buffer = (u8 *)buffer;
86 u32 data[4];
87 u32 i = 0;
88
89 if ((!(mask & hw->debug_mask)) || (desc == NULL))
90 return;
91
92 i40e_debug(hw, mask,
93 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
94 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
95 aq_desc->retval);
96 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
97 aq_desc->cookie_high, aq_desc->cookie_low);
98 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
99 aq_desc->params.internal.param0,
100 aq_desc->params.internal.param1);
101 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
102 aq_desc->params.external.addr_high,
103 aq_desc->params.external.addr_low);
104
105 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
106 memset(data, 0, sizeof(data));
107 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
108 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
109 data[((i % 16) / 4)] |=
110 ((u32)aq_buffer[i]) << (8 * (i % 4));
111 if ((i % 16) == 15) {
112 i40e_debug(hw, mask,
113 "\t0x%04X %08X %08X %08X %08X\n",
114 i - 15, data[0], data[1], data[2],
115 data[3]);
116 memset(data, 0, sizeof(data));
117 }
118 }
119 if ((i % 16) != 0)
120 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
121 i - (i % 16), data[0], data[1], data[2],
122 data[3]);
123 }
124}
125
e1860d8f
ASJ		 126/**
127 * i40e_check_asq_alive
128 * @hw: pointer to the hw struct
129 *
130 * Returns true if Queue is enabled else false.
131 **/
132bool i40e_check_asq_alive(struct i40e_hw *hw)
133{
8b833b4f
KS		 134 if (hw->aq.asq.len)
135 return !!(rd32(hw, hw->aq.asq.len) &
136 I40E_PF_ATQLEN_ATQENABLE_MASK);
137 else
138 return false;
e1860d8f
ASJ		 139}
140
141/**
142 * i40e_aq_queue_shutdown
143 * @hw: pointer to the hw struct
144 * @unloading: is the driver unloading itself
145 *
146 * Tell the Firmware that we're shutting down the AdminQ and whether
147 * or not the driver is unloading as well.
148 **/
149i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
150 bool unloading)
151{
152 struct i40e_aq_desc desc;
153 struct i40e_aqc_queue_shutdown *cmd =
154 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
155 i40e_status status;
156
157 i40e_fill_default_direct_cmd_desc(&desc,
158 i40e_aqc_opc_queue_shutdown);
159
160 if (unloading)
161 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
162 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
163
164 return status;
165}
166
206812b5
JB		 167/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
168 * hardware to a bit-field that can be used by SW to more easily determine the
169 * packet type.
170 *
171 * Macros are used to shorten the table lines and make this table human
172 * readable.
173 *
174 * We store the PTYPE in the top byte of the bit field - this is just so that
175 * we can check that the table doesn't have a row missing, as the index into
176 * the table should be the PTYPE.
177 *
178 * Typical work flow:
179 *
180 * IF NOT i40e_ptype_lookup[ptype].known
181 * THEN
182 * Packet is unknown
183 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
184 * Use the rest of the fields to look at the tunnels, inner protocols, etc
185 * ELSE
186 * Use the enum i40e_rx_l2_ptype to decode the packet type
187 * ENDIF
188 */
189
190/* macro to make the table lines short */
191#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
192 { PTYPE, \
193 1, \
194 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
195 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
196 I40E_RX_PTYPE_##OUTER_FRAG, \
197 I40E_RX_PTYPE_TUNNEL_##T, \
198 I40E_RX_PTYPE_TUNNEL_END_##TE, \
199 I40E_RX_PTYPE_##TEF, \
200 I40E_RX_PTYPE_INNER_PROT_##I, \
201 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
202
203#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
204 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
205
206/* shorter macros makes the table fit but are terse */
207#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
208#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
209#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
210
211/* Lookup table mapping the HW PTYPE to the bit field for decoding */
212struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
213 /* L2 Packet types */
214 I40E_PTT_UNUSED_ENTRY(0),
215 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
216 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
217 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
218 I40E_PTT_UNUSED_ENTRY(4),
219 I40E_PTT_UNUSED_ENTRY(5),
220 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
222 I40E_PTT_UNUSED_ENTRY(8),
223 I40E_PTT_UNUSED_ENTRY(9),
224 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
225 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
226 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
227 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
228 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
229 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
230 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236
237 /* Non Tunneled IPv4 */
238 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
241 I40E_PTT_UNUSED_ENTRY(25),
242 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
243 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
244 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
245
246 /* IPv4 --> IPv4 */
247 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
248 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
249 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
250 I40E_PTT_UNUSED_ENTRY(32),
251 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
252 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
253 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
254
255 /* IPv4 --> IPv6 */
256 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
257 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
258 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
259 I40E_PTT_UNUSED_ENTRY(39),
260 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
261 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
262 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
263
264 /* IPv4 --> GRE/NAT */
265 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
266
267 /* IPv4 --> GRE/NAT --> IPv4 */
268 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
269 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
270 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
271 I40E_PTT_UNUSED_ENTRY(47),
272 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
273 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
274 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
275
276 /* IPv4 --> GRE/NAT --> IPv6 */
277 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
278 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
279 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
280 I40E_PTT_UNUSED_ENTRY(54),
281 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
282 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
283 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
284
285 /* IPv4 --> GRE/NAT --> MAC */
286 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
287
288 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
289 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
290 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
291 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
292 I40E_PTT_UNUSED_ENTRY(62),
293 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
294 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
295 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
296
297 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
298 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
299 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
300 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
301 I40E_PTT_UNUSED_ENTRY(69),
302 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
303 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
304 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
305
306 /* IPv4 --> GRE/NAT --> MAC/VLAN */
307 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
308
309 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
310 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
311 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
312 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
313 I40E_PTT_UNUSED_ENTRY(77),
314 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
315 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
316 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
317
318 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
319 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
320 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
321 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
322 I40E_PTT_UNUSED_ENTRY(84),
323 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
324 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
325 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
326
327 /* Non Tunneled IPv6 */
328 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
329 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
330 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
331 I40E_PTT_UNUSED_ENTRY(91),
332 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
333 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
334 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
335
336 /* IPv6 --> IPv4 */
337 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
338 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
339 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
340 I40E_PTT_UNUSED_ENTRY(98),
341 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
342 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
343 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
344
345 /* IPv6 --> IPv6 */
346 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
347 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
348 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
349 I40E_PTT_UNUSED_ENTRY(105),
350 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
351 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
352 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
353
354 /* IPv6 --> GRE/NAT */
355 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
356
357 /* IPv6 --> GRE/NAT -> IPv4 */
358 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
359 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
360 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
361 I40E_PTT_UNUSED_ENTRY(113),
362 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
363 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
364 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
365
366 /* IPv6 --> GRE/NAT -> IPv6 */
367 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
368 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
369 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
370 I40E_PTT_UNUSED_ENTRY(120),
371 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
372 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
373 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
374
375 /* IPv6 --> GRE/NAT -> MAC */
376 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
377
378 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
379 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
380 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
381 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
382 I40E_PTT_UNUSED_ENTRY(128),
383 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
384 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
385 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
386
387 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
388 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
389 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
390 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
391 I40E_PTT_UNUSED_ENTRY(135),
392 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
393 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
394 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
395
396 /* IPv6 --> GRE/NAT -> MAC/VLAN */
397 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
398
399 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
400 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
401 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
402 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
403 I40E_PTT_UNUSED_ENTRY(143),
404 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
405 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
406 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
407
408 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
409 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
410 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
411 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
412 I40E_PTT_UNUSED_ENTRY(150),
413 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
414 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
415 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
416
417 /* unused entries */
418 I40E_PTT_UNUSED_ENTRY(154),
419 I40E_PTT_UNUSED_ENTRY(155),
420 I40E_PTT_UNUSED_ENTRY(156),
421 I40E_PTT_UNUSED_ENTRY(157),
422 I40E_PTT_UNUSED_ENTRY(158),
423 I40E_PTT_UNUSED_ENTRY(159),
424
425 I40E_PTT_UNUSED_ENTRY(160),
426 I40E_PTT_UNUSED_ENTRY(161),
427 I40E_PTT_UNUSED_ENTRY(162),
428 I40E_PTT_UNUSED_ENTRY(163),
429 I40E_PTT_UNUSED_ENTRY(164),
430 I40E_PTT_UNUSED_ENTRY(165),
431 I40E_PTT_UNUSED_ENTRY(166),
432 I40E_PTT_UNUSED_ENTRY(167),
433 I40E_PTT_UNUSED_ENTRY(168),
434 I40E_PTT_UNUSED_ENTRY(169),
435
436 I40E_PTT_UNUSED_ENTRY(170),
437 I40E_PTT_UNUSED_ENTRY(171),
438 I40E_PTT_UNUSED_ENTRY(172),
439 I40E_PTT_UNUSED_ENTRY(173),
440 I40E_PTT_UNUSED_ENTRY(174),
441 I40E_PTT_UNUSED_ENTRY(175),
442 I40E_PTT_UNUSED_ENTRY(176),
443 I40E_PTT_UNUSED_ENTRY(177),
444 I40E_PTT_UNUSED_ENTRY(178),
445 I40E_PTT_UNUSED_ENTRY(179),
446
447 I40E_PTT_UNUSED_ENTRY(180),
448 I40E_PTT_UNUSED_ENTRY(181),
449 I40E_PTT_UNUSED_ENTRY(182),
450 I40E_PTT_UNUSED_ENTRY(183),
451 I40E_PTT_UNUSED_ENTRY(184),
452 I40E_PTT_UNUSED_ENTRY(185),
453 I40E_PTT_UNUSED_ENTRY(186),
454 I40E_PTT_UNUSED_ENTRY(187),
455 I40E_PTT_UNUSED_ENTRY(188),
456 I40E_PTT_UNUSED_ENTRY(189),
457
458 I40E_PTT_UNUSED_ENTRY(190),
459 I40E_PTT_UNUSED_ENTRY(191),
460 I40E_PTT_UNUSED_ENTRY(192),
461 I40E_PTT_UNUSED_ENTRY(193),
462 I40E_PTT_UNUSED_ENTRY(194),
463 I40E_PTT_UNUSED_ENTRY(195),
464 I40E_PTT_UNUSED_ENTRY(196),
465 I40E_PTT_UNUSED_ENTRY(197),
466 I40E_PTT_UNUSED_ENTRY(198),
467 I40E_PTT_UNUSED_ENTRY(199),
468
469 I40E_PTT_UNUSED_ENTRY(200),
470 I40E_PTT_UNUSED_ENTRY(201),
471 I40E_PTT_UNUSED_ENTRY(202),
472 I40E_PTT_UNUSED_ENTRY(203),
473 I40E_PTT_UNUSED_ENTRY(204),
474 I40E_PTT_UNUSED_ENTRY(205),
475 I40E_PTT_UNUSED_ENTRY(206),
476 I40E_PTT_UNUSED_ENTRY(207),
477 I40E_PTT_UNUSED_ENTRY(208),
478 I40E_PTT_UNUSED_ENTRY(209),
479
480 I40E_PTT_UNUSED_ENTRY(210),
481 I40E_PTT_UNUSED_ENTRY(211),
482 I40E_PTT_UNUSED_ENTRY(212),
483 I40E_PTT_UNUSED_ENTRY(213),
484 I40E_PTT_UNUSED_ENTRY(214),
485 I40E_PTT_UNUSED_ENTRY(215),
486 I40E_PTT_UNUSED_ENTRY(216),
487 I40E_PTT_UNUSED_ENTRY(217),
488 I40E_PTT_UNUSED_ENTRY(218),
489 I40E_PTT_UNUSED_ENTRY(219),
490
491 I40E_PTT_UNUSED_ENTRY(220),
492 I40E_PTT_UNUSED_ENTRY(221),
493 I40E_PTT_UNUSED_ENTRY(222),
494 I40E_PTT_UNUSED_ENTRY(223),
495 I40E_PTT_UNUSED_ENTRY(224),
496 I40E_PTT_UNUSED_ENTRY(225),
497 I40E_PTT_UNUSED_ENTRY(226),
498 I40E_PTT_UNUSED_ENTRY(227),
499 I40E_PTT_UNUSED_ENTRY(228),
500 I40E_PTT_UNUSED_ENTRY(229),
501
502 I40E_PTT_UNUSED_ENTRY(230),
503 I40E_PTT_UNUSED_ENTRY(231),
504 I40E_PTT_UNUSED_ENTRY(232),
505 I40E_PTT_UNUSED_ENTRY(233),
506 I40E_PTT_UNUSED_ENTRY(234),
507 I40E_PTT_UNUSED_ENTRY(235),
508 I40E_PTT_UNUSED_ENTRY(236),
509 I40E_PTT_UNUSED_ENTRY(237),
510 I40E_PTT_UNUSED_ENTRY(238),
511 I40E_PTT_UNUSED_ENTRY(239),
512
513 I40E_PTT_UNUSED_ENTRY(240),
514 I40E_PTT_UNUSED_ENTRY(241),
515 I40E_PTT_UNUSED_ENTRY(242),
516 I40E_PTT_UNUSED_ENTRY(243),
517 I40E_PTT_UNUSED_ENTRY(244),
518 I40E_PTT_UNUSED_ENTRY(245),
519 I40E_PTT_UNUSED_ENTRY(246),
520 I40E_PTT_UNUSED_ENTRY(247),
521 I40E_PTT_UNUSED_ENTRY(248),
522 I40E_PTT_UNUSED_ENTRY(249),
523
524 I40E_PTT_UNUSED_ENTRY(250),
525 I40E_PTT_UNUSED_ENTRY(251),
526 I40E_PTT_UNUSED_ENTRY(252),
527 I40E_PTT_UNUSED_ENTRY(253),
528 I40E_PTT_UNUSED_ENTRY(254),
529 I40E_PTT_UNUSED_ENTRY(255)
530};
531
532
56a62fc8
JB		 533/**
534 * i40e_init_shared_code - Initialize the shared code
535 * @hw: pointer to hardware structure
536 *
537 * This assigns the MAC type and PHY code and inits the NVM.
538 * Does not touch the hardware. This function must be called prior to any
539 * other function in the shared code. The i40e_hw structure should be
540 * memset to 0 prior to calling this function. The following fields in
541 * hw structure should be filled in prior to calling this function:
542 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
543 * subsystem_vendor_id, and revision_id
544 **/
545i40e_status i40e_init_shared_code(struct i40e_hw *hw)
546{
547 i40e_status status = 0;
548 u32 reg;
549
56a62fc8
JB		 550 i40e_set_mac_type(hw);
551
552 switch (hw->mac.type) {
553 case I40E_MAC_XL710:
554 break;
555 default:
556 return I40E_ERR_DEVICE_NOT_SUPPORTED;
557 break;
558 }
559
af89d26c
SN		 560 hw->phy.get_link_info = true;
561
562 /* Determine port number */
563 reg = rd32(hw, I40E_PFGEN_PORTNUM);
564 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
565 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
566 hw->port = (u8)reg;
567
5f9116ac
SN		 568 /* Determine the PF number based on the PCI fn */
569 reg = rd32(hw, I40E_GLPCI_CAPSUP);
570 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
571 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
572 else
573 hw->pf_id = (u8)hw->bus.func;
574
56a62fc8
JB		 575 status = i40e_init_nvm(hw);
576 return status;
577}
578
579/**
580 * i40e_aq_mac_address_read - Retrieve the MAC addresses
581 * @hw: pointer to the hw struct
582 * @flags: a return indicator of what addresses were added to the addr store
583 * @addrs: the requestor's mac addr store
584 * @cmd_details: pointer to command details structure or NULL
585 **/
586static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
587 u16 *flags,
588 struct i40e_aqc_mac_address_read_data *addrs,
589 struct i40e_asq_cmd_details *cmd_details)
590{
591 struct i40e_aq_desc desc;
592 struct i40e_aqc_mac_address_read *cmd_data =
593 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
594 i40e_status status;
595
596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
597 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
598
599 status = i40e_asq_send_command(hw, &desc, addrs,
600 sizeof(*addrs), cmd_details);
601 *flags = le16_to_cpu(cmd_data->command_flags);
602
603 return status;
604}
605
606/**
607 * i40e_aq_mac_address_write - Change the MAC addresses
608 * @hw: pointer to the hw struct
609 * @flags: indicates which MAC to be written
610 * @mac_addr: address to write
611 * @cmd_details: pointer to command details structure or NULL
612 **/
613i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
614 u16 flags, u8 *mac_addr,
615 struct i40e_asq_cmd_details *cmd_details)
616{
617 struct i40e_aq_desc desc;
618 struct i40e_aqc_mac_address_write *cmd_data =
619 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
620 i40e_status status;
621
622 i40e_fill_default_direct_cmd_desc(&desc,
623 i40e_aqc_opc_mac_address_write);
624 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 625 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
626 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
627 ((u32)mac_addr[3] << 16) |
628 ((u32)mac_addr[4] << 8) |
629 mac_addr[5]);
56a62fc8
JB		 630
631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
632
633 return status;
634}
635
636/**
637 * i40e_get_mac_addr - get MAC address
638 * @hw: pointer to the HW structure
639 * @mac_addr: pointer to MAC address
640 *
641 * Reads the adapter's MAC address from register
642 **/
643i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
644{
645 struct i40e_aqc_mac_address_read_data addrs;
646 i40e_status status;
647 u16 flags = 0;
648
649 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
650
651 if (flags & I40E_AQC_LAN_ADDR_VALID)
652 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
653
654 return status;
655}
656
351499ab
MJ		 657/**
658 * i40e_pre_tx_queue_cfg - pre tx queue configure
659 * @hw: pointer to the HW structure
660 * @queue: target pf queue index
661 * @enable: state change request
662 *
663 * Handles hw requirement to indicate intention to enable
664 * or disable target queue.
665 **/
666void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
667{
dfb699f9 668 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 669 u32 reg_block = 0;
dfb699f9 670 u32 reg_val;
351499ab
MJ		 671
672 if (abs_queue_idx >= 128)
673 reg_block = abs_queue_idx / 128;
674
675 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
676 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
677 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
678
679 if (enable)
680 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
681 else
682 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
683
684 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
685}
686
be405eb0
JB		 687/**
688 * i40e_get_media_type - Gets media type
689 * @hw: pointer to the hardware structure
690 **/
691static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
692{
693 enum i40e_media_type media;
694
695 switch (hw->phy.link_info.phy_type) {
696 case I40E_PHY_TYPE_10GBASE_SR:
697 case I40E_PHY_TYPE_10GBASE_LR:
698 case I40E_PHY_TYPE_40GBASE_SR4:
699 case I40E_PHY_TYPE_40GBASE_LR4:
700 media = I40E_MEDIA_TYPE_FIBER;
701 break;
702 case I40E_PHY_TYPE_100BASE_TX:
703 case I40E_PHY_TYPE_1000BASE_T:
704 case I40E_PHY_TYPE_10GBASE_T:
705 media = I40E_MEDIA_TYPE_BASET;
706 break;
707 case I40E_PHY_TYPE_10GBASE_CR1_CU:
708 case I40E_PHY_TYPE_40GBASE_CR4_CU:
709 case I40E_PHY_TYPE_10GBASE_CR1:
710 case I40E_PHY_TYPE_40GBASE_CR4:
711 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
712 media = I40E_MEDIA_TYPE_DA;
713 break;
714 case I40E_PHY_TYPE_1000BASE_KX:
715 case I40E_PHY_TYPE_10GBASE_KX4:
716 case I40E_PHY_TYPE_10GBASE_KR:
717 case I40E_PHY_TYPE_40GBASE_KR4:
718 media = I40E_MEDIA_TYPE_BACKPLANE;
719 break;
720 case I40E_PHY_TYPE_SGMII:
721 case I40E_PHY_TYPE_XAUI:
722 case I40E_PHY_TYPE_XFI:
723 case I40E_PHY_TYPE_XLAUI:
724 case I40E_PHY_TYPE_XLPPI:
725 default:
726 media = I40E_MEDIA_TYPE_UNKNOWN;
727 break;
728 }
729
730 return media;
731}
732
7134f9ce 733#define I40E_PF_RESET_WAIT_COUNT_A0 200
d0ff5687 734#define I40E_PF_RESET_WAIT_COUNT 100
56a62fc8
JB		 735/**
736 * i40e_pf_reset - Reset the PF
737 * @hw: pointer to the hardware structure
738 *
739 * Assuming someone else has triggered a global reset,
740 * assure the global reset is complete and then reset the PF
741 **/
742i40e_status i40e_pf_reset(struct i40e_hw *hw)
743{
7134f9ce 744 u32 cnt = 0;
42794bd8 745 u32 cnt1 = 0;
56a62fc8
JB		 746 u32 reg = 0;
747 u32 grst_del;
748
749 /* Poll for Global Reset steady state in case of recent GRST.
750 * The grst delay value is in 100ms units, and we'll wait a
751 * couple counts longer to be sure we don't just miss the end.
752 */
753 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
754 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 755 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 756 reg = rd32(hw, I40E_GLGEN_RSTAT);
757 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
758 break;
759 msleep(100);
760 }
761 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
762 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 763 return I40E_ERR_RESET_FAILED;
764 }
765
766 /* Now Wait for the FW to be ready */
767 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
768 reg = rd32(hw, I40E_GLNVM_ULD);
769 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
770 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
771 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
772 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
773 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
774 break;
775 }
776 usleep_range(10000, 20000);
777 }
778 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
779 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
780 hw_dbg(hw, "wait for FW Reset complete timedout\n");
781 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 782 return I40E_ERR_RESET_FAILED;
783 }
784
56a62fc8
JB		 785 /* If there was a Global Reset in progress when we got here,
786 * we don't need to do the PF Reset
787 */
7134f9ce
JB		 788 if (!cnt) {
789 if (hw->revision_id == 0)
790 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
791 else
792 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 793 reg = rd32(hw, I40E_PFGEN_CTRL);
794 wr32(hw, I40E_PFGEN_CTRL,
795 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 796 for (; cnt; cnt--) {
56a62fc8
JB		 797 reg = rd32(hw, I40E_PFGEN_CTRL);
798 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
799 break;
800 usleep_range(1000, 2000);
801 }
802 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
803 hw_dbg(hw, "PF reset polling failed to complete.\n");
804 return I40E_ERR_RESET_FAILED;
805 }
806 }
807
808 i40e_clear_pxe_mode(hw);
922680b9 809
56a62fc8
JB		 810 return 0;
811}
812
838d41d9
SN		 813/**
814 * i40e_clear_hw - clear out any left over hw state
815 * @hw: pointer to the hw struct
816 *
817 * Clear queues and interrupts, typically called at init time,
818 * but after the capabilities have been found so we know how many
819 * queues and msix vectors have been allocated.
820 **/
821void i40e_clear_hw(struct i40e_hw *hw)
822{
823 u32 num_queues, base_queue;
824 u32 num_pf_int;
825 u32 num_vf_int;
826 u32 num_vfs;
827 u32 i, j;
828 u32 val;
829 u32 eol = 0x7ff;
830
831 /* get number of interrupts, queues, and vfs */
832 val = rd32(hw, I40E_GLPCI_CNF2);
833 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
834 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
835 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
836 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
837
838 val = rd32(hw, I40E_PFLAN_QALLOC);
839 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
840 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
841 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
842 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
843 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
844 num_queues = (j - base_queue) + 1;
845 else
846 num_queues = 0;
847
848 val = rd32(hw, I40E_PF_VT_PFALLOC);
849 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
850 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
851 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
852 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
853 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
854 num_vfs = (j - i) + 1;
855 else
856 num_vfs = 0;
857
858 /* stop all the interrupts */
859 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
860 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
861 for (i = 0; i < num_pf_int - 2; i++)
862 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
863
864 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
865 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
866 wr32(hw, I40E_PFINT_LNKLST0, val);
867 for (i = 0; i < num_pf_int - 2; i++)
868 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
869 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
870 for (i = 0; i < num_vfs; i++)
871 wr32(hw, I40E_VPINT_LNKLST0(i), val);
872 for (i = 0; i < num_vf_int - 2; i++)
873 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
874
875 /* warn the HW of the coming Tx disables */
876 for (i = 0; i < num_queues; i++) {
877 u32 abs_queue_idx = base_queue + i;
878 u32 reg_block = 0;
879
880 if (abs_queue_idx >= 128) {
881 reg_block = abs_queue_idx / 128;
882 abs_queue_idx %= 128;
883 }
884
885 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
886 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
887 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
888 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
889
890 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
891 }
892 udelay(400);
893
894 /* stop all the queues */
895 for (i = 0; i < num_queues; i++) {
896 wr32(hw, I40E_QINT_TQCTL(i), 0);
897 wr32(hw, I40E_QTX_ENA(i), 0);
898 wr32(hw, I40E_QINT_RQCTL(i), 0);
899 wr32(hw, I40E_QRX_ENA(i), 0);
900 }
901
902 /* short wait for all queue disables to settle */
903 udelay(50);
904}
905
56a62fc8
JB		 906/**
907 * i40e_clear_pxe_mode - clear pxe operations mode
908 * @hw: pointer to the hw struct
909 *
910 * Make sure all PXE mode settings are cleared, including things
911 * like descriptor fetch/write-back mode.
912 **/
913void i40e_clear_pxe_mode(struct i40e_hw *hw)
914{
915 u32 reg;
916
c9b9b0ae
SN		 917 if (i40e_check_asq_alive(hw))
918 i40e_aq_clear_pxe_mode(hw, NULL);
919
56a62fc8
JB		 920 /* Clear single descriptor fetch/write-back mode */
921 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 922
923 if (hw->revision_id == 0) {
924 /* As a work around clear PXE_MODE instead of setting it */
925 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
926 } else {
927 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
928 }
56a62fc8
JB		 929}
930
0556a9e3
JB		 931/**
932 * i40e_led_is_mine - helper to find matching led
933 * @hw: pointer to the hw struct
934 * @idx: index into GPIO registers
935 *
936 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
937 */
938static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
939{
940 u32 gpio_val = 0;
941 u32 port;
942
943 if (!hw->func_caps.led[idx])
944 return 0;
945
946 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
947 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
948 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
949
950 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
951 * if it is not our port then ignore
952 */
953 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
954 (port != hw->port))
955 return 0;
956
957 return gpio_val;
958}
959
960#define I40E_LED0 22
961#define I40E_LINK_ACTIVITY 0xC
962
56a62fc8
JB		 963/**
964 * i40e_led_get - return current on/off mode
965 * @hw: pointer to the hw struct
966 *
967 * The value returned is the 'mode' field as defined in the
968 * GPIO register definitions: 0x0 = off, 0xf = on, and other
969 * values are variations of possible behaviors relating to
970 * blink, link, and wire.
971 **/
972u32 i40e_led_get(struct i40e_hw *hw)
973{
56a62fc8 974 u32 mode = 0;
56a62fc8
JB		 975 int i;
976
0556a9e3
JB		 977 /* as per the documentation GPIO 22-29 are the LED
978 * GPIO pins named LED0..LED7
979 */
980 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
981 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 982
0556a9e3 983 if (!gpio_val)
56a62fc8
JB		 984 continue;
985
0556a9e3
JB		 986 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
987 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 988 break;
989 }
990
991 return mode;
992}
993
994/**
995 * i40e_led_set - set new on/off mode
996 * @hw: pointer to the hw struct
0556a9e3
JB		 997 * @mode: 0=off, 0xf=on (else see manual for mode details)
998 * @blink: true if the LED should blink when on, false if steady
999 *
1000 * if this function is used to turn on the blink it should
1001 * be used to disable the blink when restoring the original state.
56a62fc8 1002 **/
0556a9e3 1003void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1004{
56a62fc8
JB		 1005 int i;
1006
0556a9e3
JB		 1007 if (mode & 0xfffffff0)
1008 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1009
0556a9e3
JB		 1010 /* as per the documentation GPIO 22-29 are the LED
1011 * GPIO pins named LED0..LED7
1012 */
1013 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1014 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1015
0556a9e3 1016 if (!gpio_val)
56a62fc8
JB		 1017 continue;
1018
56a62fc8 1019 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1020 /* this & is a bit of paranoia, but serves as a range check */
1021 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1022 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1023
1024 if (mode == I40E_LINK_ACTIVITY)
1025 blink = false;
1026
1027 gpio_val |= (blink ? 1 : 0) <<
1028 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1029
56a62fc8 1030 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1031 break;
56a62fc8
JB		 1032 }
1033}
1034
1035/* Admin command wrappers */
56a62fc8 1036
c9b9b0ae
SN		 1037/**
1038 * i40e_aq_clear_pxe_mode
1039 * @hw: pointer to the hw struct
1040 * @cmd_details: pointer to command details structure or NULL
1041 *
1042 * Tell the firmware that the driver is taking over from PXE
1043 **/
1044i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1045 struct i40e_asq_cmd_details *cmd_details)
1046{
1047 i40e_status status;
1048 struct i40e_aq_desc desc;
1049 struct i40e_aqc_clear_pxe *cmd =
1050 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1051
1052 i40e_fill_default_direct_cmd_desc(&desc,
1053 i40e_aqc_opc_clear_pxe_mode);
1054
1055 cmd->rx_cnt = 0x2;
1056
1057 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1058
1059 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1060
1061 return status;
1062}
1063
56a62fc8
JB		 1064/**
1065 * i40e_aq_set_link_restart_an
1066 * @hw: pointer to the hw struct
1ac978af 1067 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1068 * @cmd_details: pointer to command details structure or NULL
1069 *
1070 * Sets up the link and restarts the Auto-Negotiation over the link.
1071 **/
1072i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1073 bool enable_link,
1074 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1075{
1076 struct i40e_aq_desc desc;
1077 struct i40e_aqc_set_link_restart_an *cmd =
1078 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1079 i40e_status status;
1080
1081 i40e_fill_default_direct_cmd_desc(&desc,
1082 i40e_aqc_opc_set_link_restart_an);
1083
1084 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1085 if (enable_link)
1086 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1087 else
1088 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1089
1090 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1091
1092 return status;
1093}
1094
1095/**
1096 * i40e_aq_get_link_info
1097 * @hw: pointer to the hw struct
1098 * @enable_lse: enable/disable LinkStatusEvent reporting
1099 * @link: pointer to link status structure - optional
1100 * @cmd_details: pointer to command details structure or NULL
1101 *
1102 * Returns the link status of the adapter.
1103 **/
1104i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1105 bool enable_lse, struct i40e_link_status *link,
1106 struct i40e_asq_cmd_details *cmd_details)
1107{
1108 struct i40e_aq_desc desc;
1109 struct i40e_aqc_get_link_status *resp =
1110 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1111 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1112 i40e_status status;
1113 u16 command_flags;
1114
1115 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1116
1117 if (enable_lse)
1118 command_flags = I40E_AQ_LSE_ENABLE;
1119 else
1120 command_flags = I40E_AQ_LSE_DISABLE;
1121 resp->command_flags = cpu_to_le16(command_flags);
1122
1123 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1124
1125 if (status)
1126 goto aq_get_link_info_exit;
1127
1128 /* save off old link status information */
c36bd4a7 1129 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1130
1131 /* update link status */
1132 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1133 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1134 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1135 hw_link_info->link_info = resp->link_info;
1136 hw_link_info->an_info = resp->an_info;
1137 hw_link_info->ext_info = resp->ext_info;
639dc377 1138 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1139 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1140 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1141
1142 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1143 hw_link_info->crc_enable = true;
1144 else
1145 hw_link_info->crc_enable = false;
56a62fc8
JB		 1146
1147 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1148 hw_link_info->lse_enable = true;
1149 else
1150 hw_link_info->lse_enable = false;
1151
1152 /* save link status information */
1153 if (link)
d7595a22 1154 *link = *hw_link_info;
56a62fc8
JB		 1155
1156 /* flag cleared so helper functions don't call AQ again */
1157 hw->phy.get_link_info = false;
1158
1159aq_get_link_info_exit:
1160 return status;
1161}
1162
1163/**
1164 * i40e_aq_add_vsi
1165 * @hw: pointer to the hw struct
98d44381 1166 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1167 * @cmd_details: pointer to command details structure or NULL
1168 *
1169 * Add a VSI context to the hardware.
1170**/
1171i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1172 struct i40e_vsi_context *vsi_ctx,
1173 struct i40e_asq_cmd_details *cmd_details)
1174{
1175 struct i40e_aq_desc desc;
1176 struct i40e_aqc_add_get_update_vsi *cmd =
1177 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1178 struct i40e_aqc_add_get_update_vsi_completion *resp =
1179 (struct i40e_aqc_add_get_update_vsi_completion *)
1180 &desc.params.raw;
1181 i40e_status status;
1182
1183 i40e_fill_default_direct_cmd_desc(&desc,
1184 i40e_aqc_opc_add_vsi);
1185
1186 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1187 cmd->connection_type = vsi_ctx->connection_type;
1188 cmd->vf_id = vsi_ctx->vf_num;
1189 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1190
1191 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1192
1193 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1194 sizeof(vsi_ctx->info), cmd_details);
1195
1196 if (status)
1197 goto aq_add_vsi_exit;
1198
1199 vsi_ctx->seid = le16_to_cpu(resp->seid);
1200 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1201 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1202 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1203
1204aq_add_vsi_exit:
1205 return status;
1206}
1207
1208/**
1209 * i40e_aq_set_vsi_unicast_promiscuous
1210 * @hw: pointer to the hw struct
1211 * @seid: vsi number
1212 * @set: set unicast promiscuous enable/disable
1213 * @cmd_details: pointer to command details structure or NULL
1214 **/
1215i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1216 u16 seid, bool set,
1217 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1218{
1219 struct i40e_aq_desc desc;
1220 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1221 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1222 i40e_status status;
1223 u16 flags = 0;
1224
1225 i40e_fill_default_direct_cmd_desc(&desc,
1226 i40e_aqc_opc_set_vsi_promiscuous_modes);
1227
1228 if (set)
1229 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1230
1231 cmd->promiscuous_flags = cpu_to_le16(flags);
1232
1233 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1234
1235 cmd->seid = cpu_to_le16(seid);
1236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1237
1238 return status;
1239}
1240
1241/**
1242 * i40e_aq_set_vsi_multicast_promiscuous
1243 * @hw: pointer to the hw struct
1244 * @seid: vsi number
1245 * @set: set multicast promiscuous enable/disable
1246 * @cmd_details: pointer to command details structure or NULL
1247 **/
1248i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1249 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1250{
1251 struct i40e_aq_desc desc;
1252 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1253 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1254 i40e_status status;
1255 u16 flags = 0;
1256
1257 i40e_fill_default_direct_cmd_desc(&desc,
1258 i40e_aqc_opc_set_vsi_promiscuous_modes);
1259
1260 if (set)
1261 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1262
1263 cmd->promiscuous_flags = cpu_to_le16(flags);
1264
1265 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1266
1267 cmd->seid = cpu_to_le16(seid);
1268 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1269
1270 return status;
1271}
1272
1273/**
1274 * i40e_aq_set_vsi_broadcast
1275 * @hw: pointer to the hw struct
1276 * @seid: vsi number
1277 * @set_filter: true to set filter, false to clear filter
1278 * @cmd_details: pointer to command details structure or NULL
1279 *
1280 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1281 **/
1282i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1283 u16 seid, bool set_filter,
1284 struct i40e_asq_cmd_details *cmd_details)
1285{
1286 struct i40e_aq_desc desc;
1287 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1288 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1289 i40e_status status;
1290
1291 i40e_fill_default_direct_cmd_desc(&desc,
1292 i40e_aqc_opc_set_vsi_promiscuous_modes);
1293
1294 if (set_filter)
1295 cmd->promiscuous_flags
1296 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1297 else
1298 cmd->promiscuous_flags
1299 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1300
1301 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1302 cmd->seid = cpu_to_le16(seid);
1303 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1304
1305 return status;
1306}
1307
1308/**
1309 * i40e_get_vsi_params - get VSI configuration info
1310 * @hw: pointer to the hw struct
98d44381 1311 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1312 * @cmd_details: pointer to command details structure or NULL
1313 **/
1314i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1315 struct i40e_vsi_context *vsi_ctx,
1316 struct i40e_asq_cmd_details *cmd_details)
1317{
1318 struct i40e_aq_desc desc;
f5ac8579
SN		 1319 struct i40e_aqc_add_get_update_vsi *cmd =
1320 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1321 struct i40e_aqc_add_get_update_vsi_completion *resp =
1322 (struct i40e_aqc_add_get_update_vsi_completion *)
1323 &desc.params.raw;
1324 i40e_status status;
1325
1326 i40e_fill_default_direct_cmd_desc(&desc,
1327 i40e_aqc_opc_get_vsi_parameters);
1328
f5ac8579 1329 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1330
1331 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 1332
1333 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1334 sizeof(vsi_ctx->info), NULL);
1335
1336 if (status)
1337 goto aq_get_vsi_params_exit;
1338
1339 vsi_ctx->seid = le16_to_cpu(resp->seid);
1340 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1341 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1342 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1343
1344aq_get_vsi_params_exit:
1345 return status;
1346}
1347
1348/**
1349 * i40e_aq_update_vsi_params
1350 * @hw: pointer to the hw struct
98d44381 1351 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1352 * @cmd_details: pointer to command details structure or NULL
1353 *
1354 * Update a VSI context.
1355 **/
1356i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1357 struct i40e_vsi_context *vsi_ctx,
1358 struct i40e_asq_cmd_details *cmd_details)
1359{
1360 struct i40e_aq_desc desc;
f5ac8579
SN		 1361 struct i40e_aqc_add_get_update_vsi *cmd =
1362 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1363 i40e_status status;
1364
1365 i40e_fill_default_direct_cmd_desc(&desc,
1366 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 1367 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1368
1369 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1370
1371 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1372 sizeof(vsi_ctx->info), cmd_details);
1373
1374 return status;
1375}
1376
1377/**
1378 * i40e_aq_get_switch_config
1379 * @hw: pointer to the hardware structure
1380 * @buf: pointer to the result buffer
1381 * @buf_size: length of input buffer
1382 * @start_seid: seid to start for the report, 0 == beginning
1383 * @cmd_details: pointer to command details structure or NULL
1384 *
1385 * Fill the buf with switch configuration returned from AdminQ command
1386 **/
1387i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1388 struct i40e_aqc_get_switch_config_resp *buf,
1389 u16 buf_size, u16 *start_seid,
1390 struct i40e_asq_cmd_details *cmd_details)
1391{
1392 struct i40e_aq_desc desc;
1393 struct i40e_aqc_switch_seid *scfg =
1394 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1395 i40e_status status;
1396
1397 i40e_fill_default_direct_cmd_desc(&desc,
1398 i40e_aqc_opc_get_switch_config);
1399 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1400 if (buf_size > I40E_AQ_LARGE_BUF)
1401 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1402 scfg->seid = cpu_to_le16(*start_seid);
1403
1404 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1405 *start_seid = le16_to_cpu(scfg->seid);
1406
1407 return status;
1408}
1409
1410/**
1411 * i40e_aq_get_firmware_version
1412 * @hw: pointer to the hw struct
1413 * @fw_major_version: firmware major version
1414 * @fw_minor_version: firmware minor version
1415 * @api_major_version: major queue version
1416 * @api_minor_version: minor queue version
1417 * @cmd_details: pointer to command details structure or NULL
1418 *
1419 * Get the firmware version from the admin queue commands
1420 **/
1421i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1422 u16 *fw_major_version, u16 *fw_minor_version,
1423 u16 *api_major_version, u16 *api_minor_version,
1424 struct i40e_asq_cmd_details *cmd_details)
1425{
1426 struct i40e_aq_desc desc;
1427 struct i40e_aqc_get_version *resp =
1428 (struct i40e_aqc_get_version *)&desc.params.raw;
1429 i40e_status status;
1430
1431 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1432
1433 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1434
1435 if (!status) {
1436 if (fw_major_version != NULL)
1437 *fw_major_version = le16_to_cpu(resp->fw_major);
1438 if (fw_minor_version != NULL)
1439 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1440 if (api_major_version != NULL)
1441 *api_major_version = le16_to_cpu(resp->api_major);
1442 if (api_minor_version != NULL)
1443 *api_minor_version = le16_to_cpu(resp->api_minor);
1444 }
1445
1446 return status;
1447}
1448
1449/**
1450 * i40e_aq_send_driver_version
1451 * @hw: pointer to the hw struct
56a62fc8
JB		 1452 * @dv: driver's major, minor version
1453 * @cmd_details: pointer to command details structure or NULL
1454 *
1455 * Send the driver version to the firmware
1456 **/
1457i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1458 struct i40e_driver_version *dv,
1459 struct i40e_asq_cmd_details *cmd_details)
1460{
1461 struct i40e_aq_desc desc;
1462 struct i40e_aqc_driver_version *cmd =
1463 (struct i40e_aqc_driver_version *)&desc.params.raw;
1464 i40e_status status;
9d2f98e1 1465 u16 len;
56a62fc8
JB		 1466
1467 if (dv == NULL)
1468 return I40E_ERR_PARAM;
1469
1470 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1471
1472 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1473 cmd->driver_major_ver = dv->major_version;
1474 cmd->driver_minor_ver = dv->minor_version;
1475 cmd->driver_build_ver = dv->build_version;
1476 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 1477
1478 len = 0;
1479 while (len < sizeof(dv->driver_string) &&
1480 (dv->driver_string[len] < 0x80) &&
1481 dv->driver_string[len])
1482 len++;
1483 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1484 len, cmd_details);
56a62fc8
JB		 1485
1486 return status;
1487}
1488
1489/**
1490 * i40e_get_link_status - get status of the HW network link
1491 * @hw: pointer to the hw struct
1492 *
1493 * Returns true if link is up, false if link is down.
1494 *
1495 * Side effect: LinkStatusEvent reporting becomes enabled
1496 **/
1497bool i40e_get_link_status(struct i40e_hw *hw)
1498{
1499 i40e_status status = 0;
1500 bool link_status = false;
1501
1502 if (hw->phy.get_link_info) {
1503 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1504
1505 if (status)
1506 goto i40e_get_link_status_exit;
1507 }
1508
1509 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1510
1511i40e_get_link_status_exit:
1512 return link_status;
1513}
1514
1515/**
1516 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1517 * @hw: pointer to the hw struct
1518 * @uplink_seid: the MAC or other gizmo SEID
1519 * @downlink_seid: the VSI SEID
1520 * @enabled_tc: bitmap of TCs to be enabled
1521 * @default_port: true for default port VSI, false for control port
e1c51b95 1522 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 1523 * @veb_seid: pointer to where to put the resulting VEB SEID
1524 * @cmd_details: pointer to command details structure or NULL
1525 *
1526 * This asks the FW to add a VEB between the uplink and downlink
1527 * elements. If the uplink SEID is 0, this will be a floating VEB.
1528 **/
1529i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1530 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 1531 bool default_port, bool enable_l2_filtering,
1532 u16 *veb_seid,
56a62fc8
JB		 1533 struct i40e_asq_cmd_details *cmd_details)
1534{
1535 struct i40e_aq_desc desc;
1536 struct i40e_aqc_add_veb *cmd =
1537 (struct i40e_aqc_add_veb *)&desc.params.raw;
1538 struct i40e_aqc_add_veb_completion *resp =
1539 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1540 i40e_status status;
1541 u16 veb_flags = 0;
1542
1543 /* SEIDs need to either both be set or both be 0 for floating VEB */
1544 if (!!uplink_seid != !!downlink_seid)
1545 return I40E_ERR_PARAM;
1546
1547 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1548
1549 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1550 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1551 cmd->enable_tcs = enabled_tc;
1552 if (!uplink_seid)
1553 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1554 if (default_port)
1555 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1556 else
1557 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1558
1559 if (enable_l2_filtering)
1560 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1561
56a62fc8
JB		 1562 cmd->veb_flags = cpu_to_le16(veb_flags);
1563
1564 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1565
1566 if (!status && veb_seid)
1567 *veb_seid = le16_to_cpu(resp->veb_seid);
1568
1569 return status;
1570}
1571
1572/**
1573 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1574 * @hw: pointer to the hw struct
1575 * @veb_seid: the SEID of the VEB to query
1576 * @switch_id: the uplink switch id
98d44381 1577 * @floating: set to true if the VEB is floating
56a62fc8
JB		 1578 * @statistic_index: index of the stats counter block for this VEB
1579 * @vebs_used: number of VEB's used by function
98d44381 1580 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 1581 * @cmd_details: pointer to command details structure or NULL
1582 *
1583 * This retrieves the parameters for a particular VEB, specified by
1584 * uplink_seid, and returns them to the caller.
1585 **/
1586i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1587 u16 veb_seid, u16 *switch_id,
1588 bool *floating, u16 *statistic_index,
1589 u16 *vebs_used, u16 *vebs_free,
1590 struct i40e_asq_cmd_details *cmd_details)
1591{
1592 struct i40e_aq_desc desc;
1593 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1594 (struct i40e_aqc_get_veb_parameters_completion *)
1595 &desc.params.raw;
1596 i40e_status status;
1597
1598 if (veb_seid == 0)
1599 return I40E_ERR_PARAM;
1600
1601 i40e_fill_default_direct_cmd_desc(&desc,
1602 i40e_aqc_opc_get_veb_parameters);
1603 cmd_resp->seid = cpu_to_le16(veb_seid);
1604
1605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1606 if (status)
1607 goto get_veb_exit;
1608
1609 if (switch_id)
1610 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1611 if (statistic_index)
1612 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1613 if (vebs_used)
1614 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1615 if (vebs_free)
1616 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1617 if (floating) {
1618 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1619 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1620 *floating = true;
1621 else
1622 *floating = false;
1623 }
1624
1625get_veb_exit:
1626 return status;
1627}
1628
1629/**
1630 * i40e_aq_add_macvlan
1631 * @hw: pointer to the hw struct
1632 * @seid: VSI for the mac address
1633 * @mv_list: list of macvlans to be added
1634 * @count: length of the list
1635 * @cmd_details: pointer to command details structure or NULL
1636 *
1637 * Add MAC/VLAN addresses to the HW filtering
1638 **/
1639i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1640 struct i40e_aqc_add_macvlan_element_data *mv_list,
1641 u16 count, struct i40e_asq_cmd_details *cmd_details)
1642{
1643 struct i40e_aq_desc desc;
1644 struct i40e_aqc_macvlan *cmd =
1645 (struct i40e_aqc_macvlan *)&desc.params.raw;
1646 i40e_status status;
1647 u16 buf_size;
1648
1649 if (count == 0 || !mv_list || !hw)
1650 return I40E_ERR_PARAM;
1651
1652 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1653
1654 /* prep the rest of the request */
1655 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1656 cmd->num_addresses = cpu_to_le16(count);
1657 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1658 cmd->seid[1] = 0;
1659 cmd->seid[2] = 0;
1660
1661 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1662 if (buf_size > I40E_AQ_LARGE_BUF)
1663 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1664
1665 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1666 cmd_details);
1667
1668 return status;
1669}
1670
1671/**
1672 * i40e_aq_remove_macvlan
1673 * @hw: pointer to the hw struct
1674 * @seid: VSI for the mac address
1675 * @mv_list: list of macvlans to be removed
1676 * @count: length of the list
1677 * @cmd_details: pointer to command details structure or NULL
1678 *
1679 * Remove MAC/VLAN addresses from the HW filtering
1680 **/
1681i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1682 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1683 u16 count, struct i40e_asq_cmd_details *cmd_details)
1684{
1685 struct i40e_aq_desc desc;
1686 struct i40e_aqc_macvlan *cmd =
1687 (struct i40e_aqc_macvlan *)&desc.params.raw;
1688 i40e_status status;
1689 u16 buf_size;
1690
1691 if (count == 0 || !mv_list || !hw)
1692 return I40E_ERR_PARAM;
1693
1694 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1695
1696 /* prep the rest of the request */
1697 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1698 cmd->num_addresses = cpu_to_le16(count);
1699 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1700 cmd->seid[1] = 0;
1701 cmd->seid[2] = 0;
1702
1703 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1704 if (buf_size > I40E_AQ_LARGE_BUF)
1705 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1706
1707 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1708 cmd_details);
1709
1710 return status;
1711}
1712
56a62fc8
JB		 1713/**
1714 * i40e_aq_send_msg_to_vf
1715 * @hw: pointer to the hardware structure
1716 * @vfid: vf id to send msg
98d44381
JK		 1717 * @v_opcode: opcodes for VF-PF communication
1718 * @v_retval: return error code
56a62fc8
JB		 1719 * @msg: pointer to the msg buffer
1720 * @msglen: msg length
1721 * @cmd_details: pointer to command details
1722 *
1723 * send msg to vf
1724 **/
1725i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1726 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1727 struct i40e_asq_cmd_details *cmd_details)
1728{
1729 struct i40e_aq_desc desc;
1730 struct i40e_aqc_pf_vf_message *cmd =
1731 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1732 i40e_status status;
1733
1734 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1735 cmd->id = cpu_to_le32(vfid);
1736 desc.cookie_high = cpu_to_le32(v_opcode);
1737 desc.cookie_low = cpu_to_le32(v_retval);
1738 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1739 if (msglen) {
1740 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1741 I40E_AQ_FLAG_RD));
1742 if (msglen > I40E_AQ_LARGE_BUF)
1743 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1744 desc.datalen = cpu_to_le16(msglen);
1745 }
1746 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1747
1748 return status;
1749}
1750
1751/**
1752 * i40e_aq_set_hmc_resource_profile
1753 * @hw: pointer to the hw struct
1754 * @profile: type of profile the HMC is to be set as
1755 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1756 * @cmd_details: pointer to command details structure or NULL
1757 *
1758 * set the HMC profile of the device.
1759 **/
1760i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1761 enum i40e_aq_hmc_profile profile,
1762 u8 pe_vf_enabled_count,
1763 struct i40e_asq_cmd_details *cmd_details)
1764{
1765 struct i40e_aq_desc desc;
1766 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1767 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1768 i40e_status status;
1769
1770 i40e_fill_default_direct_cmd_desc(&desc,
1771 i40e_aqc_opc_set_hmc_resource_profile);
1772
1773 cmd->pm_profile = (u8)profile;
1774 cmd->pe_vf_enabled = pe_vf_enabled_count;
1775
1776 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1777
1778 return status;
1779}
1780
1781/**
1782 * i40e_aq_request_resource
1783 * @hw: pointer to the hw struct
1784 * @resource: resource id
1785 * @access: access type
1786 * @sdp_number: resource number
1787 * @timeout: the maximum time in ms that the driver may hold the resource
1788 * @cmd_details: pointer to command details structure or NULL
1789 *
1790 * requests common resource using the admin queue commands
1791 **/
1792i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1793 enum i40e_aq_resources_ids resource,
1794 enum i40e_aq_resource_access_type access,
1795 u8 sdp_number, u64 *timeout,
1796 struct i40e_asq_cmd_details *cmd_details)
1797{
1798 struct i40e_aq_desc desc;
1799 struct i40e_aqc_request_resource *cmd_resp =
1800 (struct i40e_aqc_request_resource *)&desc.params.raw;
1801 i40e_status status;
1802
1803 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1804
1805 cmd_resp->resource_id = cpu_to_le16(resource);
1806 cmd_resp->access_type = cpu_to_le16(access);
1807 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1808
1809 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1810 /* The completion specifies the maximum time in ms that the driver
1811 * may hold the resource in the Timeout field.
1812 * If the resource is held by someone else, the command completes with
1813 * busy return value and the timeout field indicates the maximum time
1814 * the current owner of the resource has to free it.
1815 */
1816 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1817 *timeout = le32_to_cpu(cmd_resp->timeout);
1818
1819 return status;
1820}
1821
1822/**
1823 * i40e_aq_release_resource
1824 * @hw: pointer to the hw struct
1825 * @resource: resource id
1826 * @sdp_number: resource number
1827 * @cmd_details: pointer to command details structure or NULL
1828 *
1829 * release common resource using the admin queue commands
1830 **/
1831i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1832 enum i40e_aq_resources_ids resource,
1833 u8 sdp_number,
1834 struct i40e_asq_cmd_details *cmd_details)
1835{
1836 struct i40e_aq_desc desc;
1837 struct i40e_aqc_request_resource *cmd =
1838 (struct i40e_aqc_request_resource *)&desc.params.raw;
1839 i40e_status status;
1840
1841 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1842
1843 cmd->resource_id = cpu_to_le16(resource);
1844 cmd->resource_number = cpu_to_le32(sdp_number);
1845
1846 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1847
1848 return status;
1849}
1850
1851/**
1852 * i40e_aq_read_nvm
1853 * @hw: pointer to the hw struct
1854 * @module_pointer: module pointer location in words from the NVM beginning
1855 * @offset: byte offset from the module beginning
1856 * @length: length of the section to be read (in bytes from the offset)
1857 * @data: command buffer (size [bytes] = length)
1858 * @last_command: tells if this is the last command in a series
1859 * @cmd_details: pointer to command details structure or NULL
1860 *
1861 * Read the NVM using the admin queue commands
1862 **/
1863i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1864 u32 offset, u16 length, void *data,
1865 bool last_command,
1866 struct i40e_asq_cmd_details *cmd_details)
1867{
1868 struct i40e_aq_desc desc;
1869 struct i40e_aqc_nvm_update *cmd =
1870 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1871 i40e_status status;
1872
1873 /* In offset the highest byte must be zeroed. */
1874 if (offset & 0xFF000000) {
1875 status = I40E_ERR_PARAM;
1876 goto i40e_aq_read_nvm_exit;
1877 }
1878
1879 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1880
1881 /* If this is the last command in a series, set the proper flag. */
1882 if (last_command)
1883 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1884 cmd->module_pointer = module_pointer;
1885 cmd->offset = cpu_to_le32(offset);
1886 cmd->length = cpu_to_le16(length);
1887
1888 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1889 if (length > I40E_AQ_LARGE_BUF)
1890 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1891
1892 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1893
1894i40e_aq_read_nvm_exit:
1895 return status;
1896}
1897
1898#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1899#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1900#define I40E_DEV_FUNC_CAP_NPAR 0x03
1901#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1902#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1903#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1904#define I40E_DEV_FUNC_CAP_VF 0x13
1905#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1906#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1907#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1908#define I40E_DEV_FUNC_CAP_VSI 0x17
1909#define I40E_DEV_FUNC_CAP_DCB 0x18
1910#define I40E_DEV_FUNC_CAP_FCOE 0x21
1911#define I40E_DEV_FUNC_CAP_RSS 0x40
1912#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1913#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1914#define I40E_DEV_FUNC_CAP_MSIX 0x43
1915#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1916#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1917#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1918#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1919#define I40E_DEV_FUNC_CAP_CEM 0xF2
1920#define I40E_DEV_FUNC_CAP_IWARP 0x51
1921#define I40E_DEV_FUNC_CAP_LED 0x61
1922#define I40E_DEV_FUNC_CAP_SDP 0x62
1923#define I40E_DEV_FUNC_CAP_MDIO 0x63
1924
1925/**
1926 * i40e_parse_discover_capabilities
1927 * @hw: pointer to the hw struct
1928 * @buff: pointer to a buffer containing device/function capability records
1929 * @cap_count: number of capability records in the list
1930 * @list_type_opc: type of capabilities list to parse
1931 *
1932 * Parse the device/function capabilities list.
1933 **/
1934static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1935 u32 cap_count,
1936 enum i40e_admin_queue_opc list_type_opc)
1937{
1938 struct i40e_aqc_list_capabilities_element_resp *cap;
1939 u32 number, logical_id, phys_id;
1940 struct i40e_hw_capabilities *p;
56a62fc8
JB		 1941 u32 i = 0;
1942 u16 id;
1943
1944 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1945
1946 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 1947 p = &hw->dev_caps;
56a62fc8 1948 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 1949 p = &hw->func_caps;
56a62fc8
JB		 1950 else
1951 return;
1952
1953 for (i = 0; i < cap_count; i++, cap++) {
1954 id = le16_to_cpu(cap->id);
1955 number = le32_to_cpu(cap->number);
1956 logical_id = le32_to_cpu(cap->logical_id);
1957 phys_id = le32_to_cpu(cap->phys_id);
1958
1959 switch (id) {
1960 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1961 p->switch_mode = number;
1962 break;
1963 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1964 p->management_mode = number;
1965 break;
1966 case I40E_DEV_FUNC_CAP_NPAR:
1967 p->npar_enable = number;
1968 break;
1969 case I40E_DEV_FUNC_CAP_OS2BMC:
1970 p->os2bmc = number;
1971 break;
1972 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1973 p->valid_functions = number;
1974 break;
1975 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1976 if (number == 1)
1977 p->sr_iov_1_1 = true;
1978 break;
1979 case I40E_DEV_FUNC_CAP_VF:
1980 p->num_vfs = number;
1981 p->vf_base_id = logical_id;
1982 break;
1983 case I40E_DEV_FUNC_CAP_VMDQ:
1984 if (number == 1)
1985 p->vmdq = true;
1986 break;
1987 case I40E_DEV_FUNC_CAP_802_1_QBG:
1988 if (number == 1)
1989 p->evb_802_1_qbg = true;
1990 break;
1991 case I40E_DEV_FUNC_CAP_802_1_QBH:
1992 if (number == 1)
1993 p->evb_802_1_qbh = true;
1994 break;
1995 case I40E_DEV_FUNC_CAP_VSI:
1996 p->num_vsis = number;
1997 break;
1998 case I40E_DEV_FUNC_CAP_DCB:
1999 if (number == 1) {
2000 p->dcb = true;
2001 p->enabled_tcmap = logical_id;
2002 p->maxtc = phys_id;
2003 }
2004 break;
2005 case I40E_DEV_FUNC_CAP_FCOE:
2006 if (number == 1)
2007 p->fcoe = true;
2008 break;
2009 case I40E_DEV_FUNC_CAP_RSS:
2010 p->rss = true;
e157ea30 2011 p->rss_table_size = number;
56a62fc8
JB		 2012 p->rss_table_entry_width = logical_id;
2013 break;
2014 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2015 p->num_rx_qp = number;
2016 p->base_queue = phys_id;
2017 break;
2018 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2019 p->num_tx_qp = number;
2020 p->base_queue = phys_id;
2021 break;
2022 case I40E_DEV_FUNC_CAP_MSIX:
2023 p->num_msix_vectors = number;
2024 break;
2025 case I40E_DEV_FUNC_CAP_MSIX_VF:
2026 p->num_msix_vectors_vf = number;
2027 break;
2028 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2029 if (number == 1)
2030 p->mfp_mode_1 = true;
2031 break;
2032 case I40E_DEV_FUNC_CAP_CEM:
2033 if (number == 1)
2034 p->mgmt_cem = true;
2035 break;
2036 case I40E_DEV_FUNC_CAP_IWARP:
2037 if (number == 1)
2038 p->iwarp = true;
2039 break;
2040 case I40E_DEV_FUNC_CAP_LED:
2041 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2042 p->led[phys_id] = true;
2043 break;
2044 case I40E_DEV_FUNC_CAP_SDP:
2045 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2046 p->sdp[phys_id] = true;
2047 break;
2048 case I40E_DEV_FUNC_CAP_MDIO:
2049 if (number == 1) {
2050 p->mdio_port_num = phys_id;
2051 p->mdio_port_mode = logical_id;
2052 }
2053 break;
2054 case I40E_DEV_FUNC_CAP_IEEE_1588:
2055 if (number == 1)
2056 p->ieee_1588 = true;
2057 break;
2058 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2059 p->fd = true;
2060 p->fd_filters_guaranteed = number;
2061 p->fd_filters_best_effort = logical_id;
2062 break;
2063 default:
2064 break;
2065 }
2066 }
2067
566bb85d
VD		 2068 /* Software override ensuring FCoE is disabled if npar or mfp
2069 * mode because it is not supported in these modes.
2070 */
2071 if (p->npar_enable || p->mfp_mode_1)
2072 p->fcoe = false;
2073
56a62fc8
JB		 2074 /* additional HW specific goodies that might
2075 * someday be HW version specific
2076 */
2077 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2078}
2079
2080/**
2081 * i40e_aq_discover_capabilities
2082 * @hw: pointer to the hw struct
2083 * @buff: a virtual buffer to hold the capabilities
2084 * @buff_size: Size of the virtual buffer
2085 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2086 * @list_type_opc: capabilities type to discover - pass in the command opcode
2087 * @cmd_details: pointer to command details structure or NULL
2088 *
2089 * Get the device capabilities descriptions from the firmware
2090 **/
2091i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2092 void *buff, u16 buff_size, u16 *data_size,
2093 enum i40e_admin_queue_opc list_type_opc,
2094 struct i40e_asq_cmd_details *cmd_details)
2095{
2096 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 2097 struct i40e_aq_desc desc;
8fb905b3 2098 i40e_status status = 0;
56a62fc8
JB		 2099
2100 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2101
2102 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2103 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2104 status = I40E_ERR_PARAM;
2105 goto exit;
2106 }
2107
2108 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2109
2110 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2111 if (buff_size > I40E_AQ_LARGE_BUF)
2112 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2113
2114 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2115 *data_size = le16_to_cpu(desc.datalen);
2116
2117 if (status)
2118 goto exit;
2119
2120 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2121 list_type_opc);
2122
2123exit:
2124 return status;
2125}
2126
2127/**
2128 * i40e_aq_get_lldp_mib
2129 * @hw: pointer to the hw struct
2130 * @bridge_type: type of bridge requested
2131 * @mib_type: Local, Remote or both Local and Remote MIBs
2132 * @buff: pointer to a user supplied buffer to store the MIB block
2133 * @buff_size: size of the buffer (in bytes)
2134 * @local_len : length of the returned Local LLDP MIB
2135 * @remote_len: length of the returned Remote LLDP MIB
2136 * @cmd_details: pointer to command details structure or NULL
2137 *
2138 * Requests the complete LLDP MIB (entire packet).
2139 **/
2140i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2141 u8 mib_type, void *buff, u16 buff_size,
2142 u16 *local_len, u16 *remote_len,
2143 struct i40e_asq_cmd_details *cmd_details)
2144{
2145 struct i40e_aq_desc desc;
2146 struct i40e_aqc_lldp_get_mib *cmd =
2147 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2148 struct i40e_aqc_lldp_get_mib *resp =
2149 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2150 i40e_status status;
2151
2152 if (buff_size == 0 || !buff)
2153 return I40E_ERR_PARAM;
2154
2155 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2156 /* Indirect Command */
2157 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2158
2159 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2160 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2161 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2162
2163 desc.datalen = cpu_to_le16(buff_size);
2164
2165 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2166 if (buff_size > I40E_AQ_LARGE_BUF)
2167 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2168
2169 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2170 if (!status) {
2171 if (local_len != NULL)
2172 *local_len = le16_to_cpu(resp->local_len);
2173 if (remote_len != NULL)
2174 *remote_len = le16_to_cpu(resp->remote_len);
2175 }
2176
2177 return status;
2178}
2179
2180/**
2181 * i40e_aq_cfg_lldp_mib_change_event
2182 * @hw: pointer to the hw struct
2183 * @enable_update: Enable or Disable event posting
2184 * @cmd_details: pointer to command details structure or NULL
2185 *
2186 * Enable or Disable posting of an event on ARQ when LLDP MIB
2187 * associated with the interface changes
2188 **/
2189i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2190 bool enable_update,
2191 struct i40e_asq_cmd_details *cmd_details)
2192{
2193 struct i40e_aq_desc desc;
2194 struct i40e_aqc_lldp_update_mib *cmd =
2195 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2196 i40e_status status;
2197
2198 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2199
2200 if (!enable_update)
2201 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2202
2203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2204
2205 return status;
2206}
2207
2208/**
2209 * i40e_aq_stop_lldp
2210 * @hw: pointer to the hw struct
2211 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2212 * @cmd_details: pointer to command details structure or NULL
2213 *
2214 * Stop or Shutdown the embedded LLDP Agent
2215 **/
2216i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2217 struct i40e_asq_cmd_details *cmd_details)
2218{
2219 struct i40e_aq_desc desc;
2220 struct i40e_aqc_lldp_stop *cmd =
2221 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2222 i40e_status status;
2223
2224 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2225
2226 if (shutdown_agent)
2227 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2228
2229 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2230
2231 return status;
2232}
2233
2234/**
2235 * i40e_aq_start_lldp
2236 * @hw: pointer to the hw struct
2237 * @cmd_details: pointer to command details structure or NULL
2238 *
2239 * Start the embedded LLDP Agent on all ports.
2240 **/
2241i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2242 struct i40e_asq_cmd_details *cmd_details)
2243{
2244 struct i40e_aq_desc desc;
2245 struct i40e_aqc_lldp_start *cmd =
2246 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2247 i40e_status status;
2248
2249 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2250
2251 cmd->command = I40E_AQ_LLDP_AGENT_START;
2252
2253 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2254
2255 return status;
2256}
2257
a1c9a9d9
JK		 2258/**
2259 * i40e_aq_add_udp_tunnel
2260 * @hw: pointer to the hw struct
2261 * @udp_port: the UDP port to add
2262 * @header_len: length of the tunneling header length in DWords
2263 * @protocol_index: protocol index type
98d44381 2264 * @filter_index: pointer to filter index
a1c9a9d9
JK		 2265 * @cmd_details: pointer to command details structure or NULL
2266 **/
2267i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 2268 u16 udp_port, u8 protocol_index,
2269 u8 *filter_index,
a1c9a9d9
JK		 2270 struct i40e_asq_cmd_details *cmd_details)
2271{
2272 struct i40e_aq_desc desc;
2273 struct i40e_aqc_add_udp_tunnel *cmd =
2274 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2275 struct i40e_aqc_del_udp_tunnel_completion *resp =
2276 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2277 i40e_status status;
2278
2279 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2280
2281 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 2282 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 2283
2284 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2285
2286 if (!status)
2287 *filter_index = resp->index;
2288
2289 return status;
2290}
2291
2292/**
2293 * i40e_aq_del_udp_tunnel
2294 * @hw: pointer to the hw struct
2295 * @index: filter index
2296 * @cmd_details: pointer to command details structure or NULL
2297 **/
2298i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2299 struct i40e_asq_cmd_details *cmd_details)
2300{
2301 struct i40e_aq_desc desc;
2302 struct i40e_aqc_remove_udp_tunnel *cmd =
2303 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2304 i40e_status status;
2305
2306 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2307
2308 cmd->index = index;
2309
2310 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2311
2312 return status;
2313}
2314
56a62fc8
JB		 2315/**
2316 * i40e_aq_delete_element - Delete switch element
2317 * @hw: pointer to the hw struct
2318 * @seid: the SEID to delete from the switch
2319 * @cmd_details: pointer to command details structure or NULL
2320 *
2321 * This deletes a switch element from the switch.
2322 **/
2323i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2324 struct i40e_asq_cmd_details *cmd_details)
2325{
2326 struct i40e_aq_desc desc;
2327 struct i40e_aqc_switch_seid *cmd =
2328 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2329 i40e_status status;
2330
2331 if (seid == 0)
2332 return I40E_ERR_PARAM;
2333
2334 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2335
2336 cmd->seid = cpu_to_le16(seid);
2337
2338 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2339
2340 return status;
2341}
2342
afb3ff0d
NP		 2343/**
2344 * i40e_aq_dcb_updated - DCB Updated Command
2345 * @hw: pointer to the hw struct
2346 * @cmd_details: pointer to command details structure or NULL
2347 *
2348 * EMP will return when the shared RPB settings have been
2349 * recomputed and modified. The retval field in the descriptor
2350 * will be set to 0 when RPB is modified.
2351 **/
2352i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2353 struct i40e_asq_cmd_details *cmd_details)
2354{
2355 struct i40e_aq_desc desc;
2356 i40e_status status;
2357
2358 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2359
2360 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2361
2362 return status;
2363}
2364
56a62fc8
JB		 2365/**
2366 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2367 * @hw: pointer to the hw struct
2368 * @seid: seid for the physical port/switching component/vsi
2369 * @buff: Indirect buffer to hold data parameters and response
2370 * @buff_size: Indirect buffer size
2371 * @opcode: Tx scheduler AQ command opcode
2372 * @cmd_details: pointer to command details structure or NULL
2373 *
2374 * Generic command handler for Tx scheduler AQ commands
2375 **/
2376static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2377 void *buff, u16 buff_size,
2378 enum i40e_admin_queue_opc opcode,
2379 struct i40e_asq_cmd_details *cmd_details)
2380{
2381 struct i40e_aq_desc desc;
2382 struct i40e_aqc_tx_sched_ind *cmd =
2383 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2384 i40e_status status;
2385 bool cmd_param_flag = false;
2386
2387 switch (opcode) {
2388 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2389 case i40e_aqc_opc_configure_vsi_tc_bw:
2390 case i40e_aqc_opc_enable_switching_comp_ets:
2391 case i40e_aqc_opc_modify_switching_comp_ets:
2392 case i40e_aqc_opc_disable_switching_comp_ets:
2393 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2394 case i40e_aqc_opc_configure_switching_comp_bw_config:
2395 cmd_param_flag = true;
2396 break;
2397 case i40e_aqc_opc_query_vsi_bw_config:
2398 case i40e_aqc_opc_query_vsi_ets_sla_config:
2399 case i40e_aqc_opc_query_switching_comp_ets_config:
2400 case i40e_aqc_opc_query_port_ets_config:
2401 case i40e_aqc_opc_query_switching_comp_bw_config:
2402 cmd_param_flag = false;
2403 break;
2404 default:
2405 return I40E_ERR_PARAM;
2406 }
2407
2408 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2409
2410 /* Indirect command */
2411 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2412 if (cmd_param_flag)
2413 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2414 if (buff_size > I40E_AQ_LARGE_BUF)
2415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2416
2417 desc.datalen = cpu_to_le16(buff_size);
2418
2419 cmd->vsi_seid = cpu_to_le16(seid);
2420
2421 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2422
2423 return status;
2424}
2425
6b192891
MW		 2426/**
2427 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2428 * @hw: pointer to the hw struct
2429 * @seid: VSI seid
2430 * @credit: BW limit credits (0 = disabled)
2431 * @max_credit: Max BW limit credits
2432 * @cmd_details: pointer to command details structure or NULL
2433 **/
2434i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2435 u16 seid, u16 credit, u8 max_credit,
2436 struct i40e_asq_cmd_details *cmd_details)
2437{
2438 struct i40e_aq_desc desc;
2439 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2440 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2441 i40e_status status;
2442
2443 i40e_fill_default_direct_cmd_desc(&desc,
2444 i40e_aqc_opc_configure_vsi_bw_limit);
2445
2446 cmd->vsi_seid = cpu_to_le16(seid);
2447 cmd->credit = cpu_to_le16(credit);
2448 cmd->max_credit = max_credit;
2449
2450 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2451
2452 return status;
2453}
2454
56a62fc8
JB		 2455/**
2456 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2457 * @hw: pointer to the hw struct
2458 * @seid: VSI seid
2459 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2460 * @cmd_details: pointer to command details structure or NULL
2461 **/
2462i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2463 u16 seid,
2464 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2465 struct i40e_asq_cmd_details *cmd_details)
2466{
2467 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2468 i40e_aqc_opc_configure_vsi_tc_bw,
2469 cmd_details);
2470}
2471
afb3ff0d
NP		 2472/**
2473 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2474 * @hw: pointer to the hw struct
2475 * @seid: seid of the switching component connected to Physical Port
2476 * @ets_data: Buffer holding ETS parameters
2477 * @cmd_details: pointer to command details structure or NULL
2478 **/
2479i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2480 u16 seid,
2481 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2482 enum i40e_admin_queue_opc opcode,
2483 struct i40e_asq_cmd_details *cmd_details)
2484{
2485 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2486 sizeof(*ets_data), opcode, cmd_details);
2487}
2488
2489/**
2490 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2491 * @hw: pointer to the hw struct
2492 * @seid: seid of the switching component
2493 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2494 * @cmd_details: pointer to command details structure or NULL
2495 **/
2496i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2497 u16 seid,
2498 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2499 struct i40e_asq_cmd_details *cmd_details)
2500{
2501 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2502 i40e_aqc_opc_configure_switching_comp_bw_config,
2503 cmd_details);
2504}
2505
56a62fc8
JB		 2506/**
2507 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2508 * @hw: pointer to the hw struct
2509 * @seid: seid of the VSI
2510 * @bw_data: Buffer to hold VSI BW configuration
2511 * @cmd_details: pointer to command details structure or NULL
2512 **/
2513i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2514 u16 seid,
2515 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2516 struct i40e_asq_cmd_details *cmd_details)
2517{
2518 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2519 i40e_aqc_opc_query_vsi_bw_config,
2520 cmd_details);
2521}
2522
2523/**
2524 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2525 * @hw: pointer to the hw struct
2526 * @seid: seid of the VSI
2527 * @bw_data: Buffer to hold VSI BW configuration per TC
2528 * @cmd_details: pointer to command details structure or NULL
2529 **/
2530i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2531 u16 seid,
2532 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2533 struct i40e_asq_cmd_details *cmd_details)
2534{
2535 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2536 i40e_aqc_opc_query_vsi_ets_sla_config,
2537 cmd_details);
2538}
2539
2540/**
2541 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2542 * @hw: pointer to the hw struct
2543 * @seid: seid of the switching component
2544 * @bw_data: Buffer to hold switching component's per TC BW config
2545 * @cmd_details: pointer to command details structure or NULL
2546 **/
2547i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2548 u16 seid,
2549 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2550 struct i40e_asq_cmd_details *cmd_details)
2551{
2552 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2553 i40e_aqc_opc_query_switching_comp_ets_config,
2554 cmd_details);
2555}
2556
2557/**
2558 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2559 * @hw: pointer to the hw struct
2560 * @seid: seid of the VSI or switching component connected to Physical Port
2561 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2562 * @cmd_details: pointer to command details structure or NULL
2563 **/
2564i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2565 u16 seid,
2566 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2567 struct i40e_asq_cmd_details *cmd_details)
2568{
2569 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2570 i40e_aqc_opc_query_port_ets_config,
2571 cmd_details);
2572}
2573
2574/**
2575 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2576 * @hw: pointer to the hw struct
2577 * @seid: seid of the switching component
2578 * @bw_data: Buffer to hold switching component's BW configuration
2579 * @cmd_details: pointer to command details structure or NULL
2580 **/
2581i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2582 u16 seid,
2583 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2584 struct i40e_asq_cmd_details *cmd_details)
2585{
2586 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2587 i40e_aqc_opc_query_switching_comp_bw_config,
2588 cmd_details);
2589}
2590
2591/**
2592 * i40e_validate_filter_settings
2593 * @hw: pointer to the hardware structure
2594 * @settings: Filter control settings
2595 *
2596 * Check and validate the filter control settings passed.
2597 * The function checks for the valid filter/context sizes being
2598 * passed for FCoE and PE.
2599 *
2600 * Returns 0 if the values passed are valid and within
2601 * range else returns an error.
2602 **/
2603static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2604 struct i40e_filter_control_settings *settings)
2605{
2606 u32 fcoe_cntx_size, fcoe_filt_size;
2607 u32 pe_cntx_size, pe_filt_size;
467d729a 2608 u32 fcoe_fmax;
56a62fc8
JB		 2609 u32 val;
2610
2611 /* Validate FCoE settings passed */
2612 switch (settings->fcoe_filt_num) {
2613 case I40E_HASH_FILTER_SIZE_1K:
2614 case I40E_HASH_FILTER_SIZE_2K:
2615 case I40E_HASH_FILTER_SIZE_4K:
2616 case I40E_HASH_FILTER_SIZE_8K:
2617 case I40E_HASH_FILTER_SIZE_16K:
2618 case I40E_HASH_FILTER_SIZE_32K:
2619 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2620 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2621 break;
2622 default:
2623 return I40E_ERR_PARAM;
2624 }
2625
2626 switch (settings->fcoe_cntx_num) {
2627 case I40E_DMA_CNTX_SIZE_512:
2628 case I40E_DMA_CNTX_SIZE_1K:
2629 case I40E_DMA_CNTX_SIZE_2K:
2630 case I40E_DMA_CNTX_SIZE_4K:
2631 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2632 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2633 break;
2634 default:
2635 return I40E_ERR_PARAM;
2636 }
2637
2638 /* Validate PE settings passed */
2639 switch (settings->pe_filt_num) {
2640 case I40E_HASH_FILTER_SIZE_1K:
2641 case I40E_HASH_FILTER_SIZE_2K:
2642 case I40E_HASH_FILTER_SIZE_4K:
2643 case I40E_HASH_FILTER_SIZE_8K:
2644 case I40E_HASH_FILTER_SIZE_16K:
2645 case I40E_HASH_FILTER_SIZE_32K:
2646 case I40E_HASH_FILTER_SIZE_64K:
2647 case I40E_HASH_FILTER_SIZE_128K:
2648 case I40E_HASH_FILTER_SIZE_256K:
2649 case I40E_HASH_FILTER_SIZE_512K:
2650 case I40E_HASH_FILTER_SIZE_1M:
2651 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2652 pe_filt_size <<= (u32)settings->pe_filt_num;
2653 break;
2654 default:
2655 return I40E_ERR_PARAM;
2656 }
2657
2658 switch (settings->pe_cntx_num) {
2659 case I40E_DMA_CNTX_SIZE_512:
2660 case I40E_DMA_CNTX_SIZE_1K:
2661 case I40E_DMA_CNTX_SIZE_2K:
2662 case I40E_DMA_CNTX_SIZE_4K:
2663 case I40E_DMA_CNTX_SIZE_8K:
2664 case I40E_DMA_CNTX_SIZE_16K:
2665 case I40E_DMA_CNTX_SIZE_32K:
2666 case I40E_DMA_CNTX_SIZE_64K:
2667 case I40E_DMA_CNTX_SIZE_128K:
2668 case I40E_DMA_CNTX_SIZE_256K:
2669 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2670 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2671 break;
2672 default:
2673 return I40E_ERR_PARAM;
2674 }
2675
2676 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2677 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2678 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2679 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2680 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2681 return I40E_ERR_INVALID_SIZE;
2682
56a62fc8
JB		 2683 return 0;
2684}
2685
2686/**
2687 * i40e_set_filter_control
2688 * @hw: pointer to the hardware structure
2689 * @settings: Filter control settings
2690 *
2691 * Set the Queue Filters for PE/FCoE and enable filters required
2692 * for a single PF. It is expected that these settings are programmed
2693 * at the driver initialization time.
2694 **/
2695i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2696 struct i40e_filter_control_settings *settings)
2697{
2698 i40e_status ret = 0;
2699 u32 hash_lut_size = 0;
2700 u32 val;
2701
2702 if (!settings)
2703 return I40E_ERR_PARAM;
2704
2705 /* Validate the input settings */
2706 ret = i40e_validate_filter_settings(hw, settings);
2707 if (ret)
2708 return ret;
2709
2710 /* Read the PF Queue Filter control register */
2711 val = rd32(hw, I40E_PFQF_CTL_0);
2712
2713 /* Program required PE hash buckets for the PF */
2714 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2715 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2716 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2717 /* Program required PE contexts for the PF */
2718 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2719 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2720 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2721
2722 /* Program required FCoE hash buckets for the PF */
2723 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2724 val |= ((u32)settings->fcoe_filt_num <<
2725 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2726 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2727 /* Program required FCoE DDP contexts for the PF */
2728 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2729 val |= ((u32)settings->fcoe_cntx_num <<
2730 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2731 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2732
2733 /* Program Hash LUT size for the PF */
2734 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2735 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2736 hash_lut_size = 1;
2737 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2738 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2739
2740 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2741 if (settings->enable_fdir)
2742 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2743 if (settings->enable_ethtype)
2744 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2745 if (settings->enable_macvlan)
2746 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2747
2748 wr32(hw, I40E_PFQF_CTL_0, val);
2749
2750 return 0;
2751}
afb3ff0d
NP		 2752
2753/**
2754 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2755 * @hw: pointer to the hw struct
2756 * @mac_addr: MAC address to use in the filter
2757 * @ethtype: Ethertype to use in the filter
2758 * @flags: Flags that needs to be applied to the filter
2759 * @vsi_seid: seid of the control VSI
2760 * @queue: VSI queue number to send the packet to
2761 * @is_add: Add control packet filter if True else remove
2762 * @stats: Structure to hold information on control filter counts
2763 * @cmd_details: pointer to command details structure or NULL
2764 *
2765 * This command will Add or Remove control packet filter for a control VSI.
2766 * In return it will update the total number of perfect filter count in
2767 * the stats member.
2768 **/
2769i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
2770 u8 *mac_addr, u16 ethtype, u16 flags,
2771 u16 vsi_seid, u16 queue, bool is_add,
2772 struct i40e_control_filter_stats *stats,
2773 struct i40e_asq_cmd_details *cmd_details)
2774{
2775 struct i40e_aq_desc desc;
2776 struct i40e_aqc_add_remove_control_packet_filter *cmd =
2777 (struct i40e_aqc_add_remove_control_packet_filter *)
2778 &desc.params.raw;
2779 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
2780 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
2781 &desc.params.raw;
2782 i40e_status status;
2783
2784 if (vsi_seid == 0)
2785 return I40E_ERR_PARAM;
2786
2787 if (is_add) {
2788 i40e_fill_default_direct_cmd_desc(&desc,
2789 i40e_aqc_opc_add_control_packet_filter);
2790 cmd->queue = cpu_to_le16(queue);
2791 } else {
2792 i40e_fill_default_direct_cmd_desc(&desc,
2793 i40e_aqc_opc_remove_control_packet_filter);
2794 }
2795
2796 if (mac_addr)
2797 memcpy(cmd->mac, mac_addr, ETH_ALEN);
2798
2799 cmd->etype = cpu_to_le16(ethtype);
2800 cmd->flags = cpu_to_le16(flags);
2801 cmd->seid = cpu_to_le16(vsi_seid);
2802
2803 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2804
2805 if (!status && stats) {
2806 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
2807 stats->etype_used = le16_to_cpu(resp->etype_used);
2808 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
2809 stats->etype_free = le16_to_cpu(resp->etype_free);
2810 }
2811
2812 return status;
2813}
2814
d4dfb81a
CS		 2815/**
2816 * i40e_set_pci_config_data - store PCI bus info
2817 * @hw: pointer to hardware structure
2818 * @link_status: the link status word from PCI config space
2819 *
2820 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2821 **/
2822void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2823{
2824 hw->bus.type = i40e_bus_type_pci_express;
2825
2826 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2827 case PCI_EXP_LNKSTA_NLW_X1:
2828 hw->bus.width = i40e_bus_width_pcie_x1;
2829 break;
2830 case PCI_EXP_LNKSTA_NLW_X2:
2831 hw->bus.width = i40e_bus_width_pcie_x2;
2832 break;
2833 case PCI_EXP_LNKSTA_NLW_X4:
2834 hw->bus.width = i40e_bus_width_pcie_x4;
2835 break;
2836 case PCI_EXP_LNKSTA_NLW_X8:
2837 hw->bus.width = i40e_bus_width_pcie_x8;
2838 break;
2839 default:
2840 hw->bus.width = i40e_bus_width_unknown;
2841 break;
2842 }
2843
2844 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2845 case PCI_EXP_LNKSTA_CLS_2_5GB:
2846 hw->bus.speed = i40e_bus_speed_2500;
2847 break;
2848 case PCI_EXP_LNKSTA_CLS_5_0GB:
2849 hw->bus.speed = i40e_bus_speed_5000;
2850 break;
2851 case PCI_EXP_LNKSTA_CLS_8_0GB:
2852 hw->bus.speed = i40e_bus_speed_8000;
2853 break;
2854 default:
2855 hw->bus.speed = i40e_bus_speed_unknown;
2856 break;
2857 }
2858}
Linux kernel - Deliverables
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