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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net...
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e
SN		 45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_SFP_X710:
47 case I40E_DEV_ID_QEMU:
48 case I40E_DEV_ID_KX_A:
49 case I40E_DEV_ID_KX_B:
50 case I40E_DEV_ID_KX_C:
51 case I40E_DEV_ID_KX_D:
52 case I40E_DEV_ID_QSFP_A:
53 case I40E_DEV_ID_QSFP_B:
54 case I40E_DEV_ID_QSFP_C:
56a62fc8
JB		 55 hw->mac.type = I40E_MAC_XL710;
56 break;
ab60085e
SN		 57 case I40E_DEV_ID_VF:
58 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 59 hw->mac.type = I40E_MAC_VF;
60 break;
61 default:
62 hw->mac.type = I40E_MAC_GENERIC;
63 break;
64 }
65 } else {
66 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
67 }
68
69 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
70 hw->mac.type, status);
71 return status;
72}
73
74/**
75 * i40e_debug_aq
76 * @hw: debug mask related to admin queue
98d44381
JK		 77 * @mask: debug mask
78 * @desc: pointer to admin queue descriptor
56a62fc8
JB		 79 * @buffer: pointer to command buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer)
85{
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u8 *aq_buffer = (u8 *)buffer;
88 u32 data[4];
89 u32 i = 0;
90
91 if ((!(mask & hw->debug_mask)) || (desc == NULL))
92 return;
93
94 i40e_debug(hw, mask,
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
97 aq_desc->retval);
98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc->cookie_high, aq_desc->cookie_low);
100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc->params.internal.param0,
102 aq_desc->params.internal.param1);
103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc->params.external.addr_high,
105 aq_desc->params.external.addr_low);
106
107 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
108 memset(data, 0, sizeof(data));
109 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
110 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
111 data[((i % 16) / 4)] |=
112 ((u32)aq_buffer[i]) << (8 * (i % 4));
113 if ((i % 16) == 15) {
114 i40e_debug(hw, mask,
115 "\t0x%04X %08X %08X %08X %08X\n",
116 i - 15, data[0], data[1], data[2],
117 data[3]);
118 memset(data, 0, sizeof(data));
119 }
120 }
121 if ((i % 16) != 0)
122 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
123 i - (i % 16), data[0], data[1], data[2],
124 data[3]);
125 }
126}
127
e1860d8f
ASJ		 128/**
129 * i40e_check_asq_alive
130 * @hw: pointer to the hw struct
131 *
132 * Returns true if Queue is enabled else false.
133 **/
134bool i40e_check_asq_alive(struct i40e_hw *hw)
135{
136 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
137}
138
139/**
140 * i40e_aq_queue_shutdown
141 * @hw: pointer to the hw struct
142 * @unloading: is the driver unloading itself
143 *
144 * Tell the Firmware that we're shutting down the AdminQ and whether
145 * or not the driver is unloading as well.
146 **/
147i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
148 bool unloading)
149{
150 struct i40e_aq_desc desc;
151 struct i40e_aqc_queue_shutdown *cmd =
152 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
153 i40e_status status;
154
155 i40e_fill_default_direct_cmd_desc(&desc,
156 i40e_aqc_opc_queue_shutdown);
157
158 if (unloading)
159 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
160 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
161
162 return status;
163}
164
206812b5
JB		 165/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
166 * hardware to a bit-field that can be used by SW to more easily determine the
167 * packet type.
168 *
169 * Macros are used to shorten the table lines and make this table human
170 * readable.
171 *
172 * We store the PTYPE in the top byte of the bit field - this is just so that
173 * we can check that the table doesn't have a row missing, as the index into
174 * the table should be the PTYPE.
175 *
176 * Typical work flow:
177 *
178 * IF NOT i40e_ptype_lookup[ptype].known
179 * THEN
180 * Packet is unknown
181 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
182 * Use the rest of the fields to look at the tunnels, inner protocols, etc
183 * ELSE
184 * Use the enum i40e_rx_l2_ptype to decode the packet type
185 * ENDIF
186 */
187
188/* macro to make the table lines short */
189#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
190 { PTYPE, \
191 1, \
192 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
193 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
194 I40E_RX_PTYPE_##OUTER_FRAG, \
195 I40E_RX_PTYPE_TUNNEL_##T, \
196 I40E_RX_PTYPE_TUNNEL_END_##TE, \
197 I40E_RX_PTYPE_##TEF, \
198 I40E_RX_PTYPE_INNER_PROT_##I, \
199 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
200
201#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
202 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
203
204/* shorter macros makes the table fit but are terse */
205#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
206#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
207#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
208
209/* Lookup table mapping the HW PTYPE to the bit field for decoding */
210struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
211 /* L2 Packet types */
212 I40E_PTT_UNUSED_ENTRY(0),
213 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
214 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
215 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
216 I40E_PTT_UNUSED_ENTRY(4),
217 I40E_PTT_UNUSED_ENTRY(5),
218 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
219 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
220 I40E_PTT_UNUSED_ENTRY(8),
221 I40E_PTT_UNUSED_ENTRY(9),
222 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
223 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
224 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
225 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
226 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
227 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
228 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
229 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
230 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234
235 /* Non Tunneled IPv4 */
236 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
238 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
239 I40E_PTT_UNUSED_ENTRY(25),
240 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
241 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
242 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
243
244 /* IPv4 --> IPv4 */
245 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
246 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
247 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
248 I40E_PTT_UNUSED_ENTRY(32),
249 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
250 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
251 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
252
253 /* IPv4 --> IPv6 */
254 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
255 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
256 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
257 I40E_PTT_UNUSED_ENTRY(39),
258 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
259 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
260 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
261
262 /* IPv4 --> GRE/NAT */
263 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
264
265 /* IPv4 --> GRE/NAT --> IPv4 */
266 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
267 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
268 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
269 I40E_PTT_UNUSED_ENTRY(47),
270 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
271 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
272 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
273
274 /* IPv4 --> GRE/NAT --> IPv6 */
275 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
276 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
277 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
278 I40E_PTT_UNUSED_ENTRY(54),
279 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
280 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
281 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
282
283 /* IPv4 --> GRE/NAT --> MAC */
284 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
285
286 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
287 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
288 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
289 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
290 I40E_PTT_UNUSED_ENTRY(62),
291 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
292 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
293 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
294
295 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
296 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
297 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
298 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
299 I40E_PTT_UNUSED_ENTRY(69),
300 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
301 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
302 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
303
304 /* IPv4 --> GRE/NAT --> MAC/VLAN */
305 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
306
307 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
308 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
309 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
310 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
311 I40E_PTT_UNUSED_ENTRY(77),
312 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
313 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
314 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
315
316 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
317 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
318 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
319 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
320 I40E_PTT_UNUSED_ENTRY(84),
321 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
322 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
323 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
324
325 /* Non Tunneled IPv6 */
326 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
327 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
328 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
329 I40E_PTT_UNUSED_ENTRY(91),
330 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
331 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
332 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
333
334 /* IPv6 --> IPv4 */
335 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
336 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
337 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
338 I40E_PTT_UNUSED_ENTRY(98),
339 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
340 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
341 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
342
343 /* IPv6 --> IPv6 */
344 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
345 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
346 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
347 I40E_PTT_UNUSED_ENTRY(105),
348 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
349 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
350 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
351
352 /* IPv6 --> GRE/NAT */
353 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
354
355 /* IPv6 --> GRE/NAT -> IPv4 */
356 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
357 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
358 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
359 I40E_PTT_UNUSED_ENTRY(113),
360 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
361 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
362 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
363
364 /* IPv6 --> GRE/NAT -> IPv6 */
365 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
366 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
367 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
368 I40E_PTT_UNUSED_ENTRY(120),
369 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
370 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
371 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
372
373 /* IPv6 --> GRE/NAT -> MAC */
374 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
375
376 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
377 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
378 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
379 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
380 I40E_PTT_UNUSED_ENTRY(128),
381 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
382 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
383 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
384
385 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
386 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
387 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
388 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
389 I40E_PTT_UNUSED_ENTRY(135),
390 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
391 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
392 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
393
394 /* IPv6 --> GRE/NAT -> MAC/VLAN */
395 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
396
397 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
398 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
399 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
400 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
401 I40E_PTT_UNUSED_ENTRY(143),
402 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
403 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
404 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
405
406 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
407 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
408 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
409 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
410 I40E_PTT_UNUSED_ENTRY(150),
411 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
412 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
413 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
414
415 /* unused entries */
416 I40E_PTT_UNUSED_ENTRY(154),
417 I40E_PTT_UNUSED_ENTRY(155),
418 I40E_PTT_UNUSED_ENTRY(156),
419 I40E_PTT_UNUSED_ENTRY(157),
420 I40E_PTT_UNUSED_ENTRY(158),
421 I40E_PTT_UNUSED_ENTRY(159),
422
423 I40E_PTT_UNUSED_ENTRY(160),
424 I40E_PTT_UNUSED_ENTRY(161),
425 I40E_PTT_UNUSED_ENTRY(162),
426 I40E_PTT_UNUSED_ENTRY(163),
427 I40E_PTT_UNUSED_ENTRY(164),
428 I40E_PTT_UNUSED_ENTRY(165),
429 I40E_PTT_UNUSED_ENTRY(166),
430 I40E_PTT_UNUSED_ENTRY(167),
431 I40E_PTT_UNUSED_ENTRY(168),
432 I40E_PTT_UNUSED_ENTRY(169),
433
434 I40E_PTT_UNUSED_ENTRY(170),
435 I40E_PTT_UNUSED_ENTRY(171),
436 I40E_PTT_UNUSED_ENTRY(172),
437 I40E_PTT_UNUSED_ENTRY(173),
438 I40E_PTT_UNUSED_ENTRY(174),
439 I40E_PTT_UNUSED_ENTRY(175),
440 I40E_PTT_UNUSED_ENTRY(176),
441 I40E_PTT_UNUSED_ENTRY(177),
442 I40E_PTT_UNUSED_ENTRY(178),
443 I40E_PTT_UNUSED_ENTRY(179),
444
445 I40E_PTT_UNUSED_ENTRY(180),
446 I40E_PTT_UNUSED_ENTRY(181),
447 I40E_PTT_UNUSED_ENTRY(182),
448 I40E_PTT_UNUSED_ENTRY(183),
449 I40E_PTT_UNUSED_ENTRY(184),
450 I40E_PTT_UNUSED_ENTRY(185),
451 I40E_PTT_UNUSED_ENTRY(186),
452 I40E_PTT_UNUSED_ENTRY(187),
453 I40E_PTT_UNUSED_ENTRY(188),
454 I40E_PTT_UNUSED_ENTRY(189),
455
456 I40E_PTT_UNUSED_ENTRY(190),
457 I40E_PTT_UNUSED_ENTRY(191),
458 I40E_PTT_UNUSED_ENTRY(192),
459 I40E_PTT_UNUSED_ENTRY(193),
460 I40E_PTT_UNUSED_ENTRY(194),
461 I40E_PTT_UNUSED_ENTRY(195),
462 I40E_PTT_UNUSED_ENTRY(196),
463 I40E_PTT_UNUSED_ENTRY(197),
464 I40E_PTT_UNUSED_ENTRY(198),
465 I40E_PTT_UNUSED_ENTRY(199),
466
467 I40E_PTT_UNUSED_ENTRY(200),
468 I40E_PTT_UNUSED_ENTRY(201),
469 I40E_PTT_UNUSED_ENTRY(202),
470 I40E_PTT_UNUSED_ENTRY(203),
471 I40E_PTT_UNUSED_ENTRY(204),
472 I40E_PTT_UNUSED_ENTRY(205),
473 I40E_PTT_UNUSED_ENTRY(206),
474 I40E_PTT_UNUSED_ENTRY(207),
475 I40E_PTT_UNUSED_ENTRY(208),
476 I40E_PTT_UNUSED_ENTRY(209),
477
478 I40E_PTT_UNUSED_ENTRY(210),
479 I40E_PTT_UNUSED_ENTRY(211),
480 I40E_PTT_UNUSED_ENTRY(212),
481 I40E_PTT_UNUSED_ENTRY(213),
482 I40E_PTT_UNUSED_ENTRY(214),
483 I40E_PTT_UNUSED_ENTRY(215),
484 I40E_PTT_UNUSED_ENTRY(216),
485 I40E_PTT_UNUSED_ENTRY(217),
486 I40E_PTT_UNUSED_ENTRY(218),
487 I40E_PTT_UNUSED_ENTRY(219),
488
489 I40E_PTT_UNUSED_ENTRY(220),
490 I40E_PTT_UNUSED_ENTRY(221),
491 I40E_PTT_UNUSED_ENTRY(222),
492 I40E_PTT_UNUSED_ENTRY(223),
493 I40E_PTT_UNUSED_ENTRY(224),
494 I40E_PTT_UNUSED_ENTRY(225),
495 I40E_PTT_UNUSED_ENTRY(226),
496 I40E_PTT_UNUSED_ENTRY(227),
497 I40E_PTT_UNUSED_ENTRY(228),
498 I40E_PTT_UNUSED_ENTRY(229),
499
500 I40E_PTT_UNUSED_ENTRY(230),
501 I40E_PTT_UNUSED_ENTRY(231),
502 I40E_PTT_UNUSED_ENTRY(232),
503 I40E_PTT_UNUSED_ENTRY(233),
504 I40E_PTT_UNUSED_ENTRY(234),
505 I40E_PTT_UNUSED_ENTRY(235),
506 I40E_PTT_UNUSED_ENTRY(236),
507 I40E_PTT_UNUSED_ENTRY(237),
508 I40E_PTT_UNUSED_ENTRY(238),
509 I40E_PTT_UNUSED_ENTRY(239),
510
511 I40E_PTT_UNUSED_ENTRY(240),
512 I40E_PTT_UNUSED_ENTRY(241),
513 I40E_PTT_UNUSED_ENTRY(242),
514 I40E_PTT_UNUSED_ENTRY(243),
515 I40E_PTT_UNUSED_ENTRY(244),
516 I40E_PTT_UNUSED_ENTRY(245),
517 I40E_PTT_UNUSED_ENTRY(246),
518 I40E_PTT_UNUSED_ENTRY(247),
519 I40E_PTT_UNUSED_ENTRY(248),
520 I40E_PTT_UNUSED_ENTRY(249),
521
522 I40E_PTT_UNUSED_ENTRY(250),
523 I40E_PTT_UNUSED_ENTRY(251),
524 I40E_PTT_UNUSED_ENTRY(252),
525 I40E_PTT_UNUSED_ENTRY(253),
526 I40E_PTT_UNUSED_ENTRY(254),
527 I40E_PTT_UNUSED_ENTRY(255)
528};
529
530
56a62fc8
JB		 531/**
532 * i40e_init_shared_code - Initialize the shared code
533 * @hw: pointer to hardware structure
534 *
535 * This assigns the MAC type and PHY code and inits the NVM.
536 * Does not touch the hardware. This function must be called prior to any
537 * other function in the shared code. The i40e_hw structure should be
538 * memset to 0 prior to calling this function. The following fields in
539 * hw structure should be filled in prior to calling this function:
540 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
541 * subsystem_vendor_id, and revision_id
542 **/
543i40e_status i40e_init_shared_code(struct i40e_hw *hw)
544{
545 i40e_status status = 0;
546 u32 reg;
547
56a62fc8
JB		 548 i40e_set_mac_type(hw);
549
550 switch (hw->mac.type) {
551 case I40E_MAC_XL710:
552 break;
553 default:
554 return I40E_ERR_DEVICE_NOT_SUPPORTED;
555 break;
556 }
557
af89d26c
SN		 558 hw->phy.get_link_info = true;
559
560 /* Determine port number */
561 reg = rd32(hw, I40E_PFGEN_PORTNUM);
562 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
563 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
564 hw->port = (u8)reg;
565
5f9116ac
SN		 566 /* Determine the PF number based on the PCI fn */
567 reg = rd32(hw, I40E_GLPCI_CAPSUP);
568 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
569 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
570 else
571 hw->pf_id = (u8)hw->bus.func;
572
56a62fc8
JB		 573 status = i40e_init_nvm(hw);
574 return status;
575}
576
577/**
578 * i40e_aq_mac_address_read - Retrieve the MAC addresses
579 * @hw: pointer to the hw struct
580 * @flags: a return indicator of what addresses were added to the addr store
581 * @addrs: the requestor's mac addr store
582 * @cmd_details: pointer to command details structure or NULL
583 **/
584static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
585 u16 *flags,
586 struct i40e_aqc_mac_address_read_data *addrs,
587 struct i40e_asq_cmd_details *cmd_details)
588{
589 struct i40e_aq_desc desc;
590 struct i40e_aqc_mac_address_read *cmd_data =
591 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
592 i40e_status status;
593
594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
595 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
596
597 status = i40e_asq_send_command(hw, &desc, addrs,
598 sizeof(*addrs), cmd_details);
599 *flags = le16_to_cpu(cmd_data->command_flags);
600
601 return status;
602}
603
604/**
605 * i40e_aq_mac_address_write - Change the MAC addresses
606 * @hw: pointer to the hw struct
607 * @flags: indicates which MAC to be written
608 * @mac_addr: address to write
609 * @cmd_details: pointer to command details structure or NULL
610 **/
611i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
612 u16 flags, u8 *mac_addr,
613 struct i40e_asq_cmd_details *cmd_details)
614{
615 struct i40e_aq_desc desc;
616 struct i40e_aqc_mac_address_write *cmd_data =
617 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
618 i40e_status status;
619
620 i40e_fill_default_direct_cmd_desc(&desc,
621 i40e_aqc_opc_mac_address_write);
622 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 623 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
624 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
625 ((u32)mac_addr[3] << 16) |
626 ((u32)mac_addr[4] << 8) |
627 mac_addr[5]);
56a62fc8
JB		 628
629 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
630
631 return status;
632}
633
634/**
635 * i40e_get_mac_addr - get MAC address
636 * @hw: pointer to the HW structure
637 * @mac_addr: pointer to MAC address
638 *
639 * Reads the adapter's MAC address from register
640 **/
641i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
642{
643 struct i40e_aqc_mac_address_read_data addrs;
644 i40e_status status;
645 u16 flags = 0;
646
647 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
648
649 if (flags & I40E_AQC_LAN_ADDR_VALID)
650 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
651
652 return status;
653}
654
be405eb0
JB		 655/**
656 * i40e_get_media_type - Gets media type
657 * @hw: pointer to the hardware structure
658 **/
659static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
660{
661 enum i40e_media_type media;
662
663 switch (hw->phy.link_info.phy_type) {
664 case I40E_PHY_TYPE_10GBASE_SR:
665 case I40E_PHY_TYPE_10GBASE_LR:
666 case I40E_PHY_TYPE_40GBASE_SR4:
667 case I40E_PHY_TYPE_40GBASE_LR4:
668 media = I40E_MEDIA_TYPE_FIBER;
669 break;
670 case I40E_PHY_TYPE_100BASE_TX:
671 case I40E_PHY_TYPE_1000BASE_T:
672 case I40E_PHY_TYPE_10GBASE_T:
673 media = I40E_MEDIA_TYPE_BASET;
674 break;
675 case I40E_PHY_TYPE_10GBASE_CR1_CU:
676 case I40E_PHY_TYPE_40GBASE_CR4_CU:
677 case I40E_PHY_TYPE_10GBASE_CR1:
678 case I40E_PHY_TYPE_40GBASE_CR4:
679 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
680 media = I40E_MEDIA_TYPE_DA;
681 break;
682 case I40E_PHY_TYPE_1000BASE_KX:
683 case I40E_PHY_TYPE_10GBASE_KX4:
684 case I40E_PHY_TYPE_10GBASE_KR:
685 case I40E_PHY_TYPE_40GBASE_KR4:
686 media = I40E_MEDIA_TYPE_BACKPLANE;
687 break;
688 case I40E_PHY_TYPE_SGMII:
689 case I40E_PHY_TYPE_XAUI:
690 case I40E_PHY_TYPE_XFI:
691 case I40E_PHY_TYPE_XLAUI:
692 case I40E_PHY_TYPE_XLPPI:
693 default:
694 media = I40E_MEDIA_TYPE_UNKNOWN;
695 break;
696 }
697
698 return media;
699}
700
7134f9ce
JB		 701#define I40E_PF_RESET_WAIT_COUNT_A0 200
702#define I40E_PF_RESET_WAIT_COUNT 10
56a62fc8
JB		 703/**
704 * i40e_pf_reset - Reset the PF
705 * @hw: pointer to the hardware structure
706 *
707 * Assuming someone else has triggered a global reset,
708 * assure the global reset is complete and then reset the PF
709 **/
710i40e_status i40e_pf_reset(struct i40e_hw *hw)
711{
7134f9ce 712 u32 cnt = 0;
42794bd8 713 u32 cnt1 = 0;
56a62fc8
JB		 714 u32 reg = 0;
715 u32 grst_del;
716
717 /* Poll for Global Reset steady state in case of recent GRST.
718 * The grst delay value is in 100ms units, and we'll wait a
719 * couple counts longer to be sure we don't just miss the end.
720 */
721 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
722 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 723 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 724 reg = rd32(hw, I40E_GLGEN_RSTAT);
725 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
726 break;
727 msleep(100);
728 }
729 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
730 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 731 return I40E_ERR_RESET_FAILED;
732 }
733
734 /* Now Wait for the FW to be ready */
735 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
736 reg = rd32(hw, I40E_GLNVM_ULD);
737 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
738 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
739 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
740 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
741 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
742 break;
743 }
744 usleep_range(10000, 20000);
745 }
746 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
747 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
748 hw_dbg(hw, "wait for FW Reset complete timedout\n");
749 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 750 return I40E_ERR_RESET_FAILED;
751 }
752
56a62fc8
JB		 753 /* If there was a Global Reset in progress when we got here,
754 * we don't need to do the PF Reset
755 */
7134f9ce
JB		 756 if (!cnt) {
757 if (hw->revision_id == 0)
758 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
759 else
760 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 761 reg = rd32(hw, I40E_PFGEN_CTRL);
762 wr32(hw, I40E_PFGEN_CTRL,
763 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 764 for (; cnt; cnt--) {
56a62fc8
JB		 765 reg = rd32(hw, I40E_PFGEN_CTRL);
766 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
767 break;
768 usleep_range(1000, 2000);
769 }
770 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
771 hw_dbg(hw, "PF reset polling failed to complete.\n");
772 return I40E_ERR_RESET_FAILED;
773 }
774 }
775
776 i40e_clear_pxe_mode(hw);
922680b9 777
56a62fc8
JB		 778 return 0;
779}
780
781/**
782 * i40e_clear_pxe_mode - clear pxe operations mode
783 * @hw: pointer to the hw struct
784 *
785 * Make sure all PXE mode settings are cleared, including things
786 * like descriptor fetch/write-back mode.
787 **/
788void i40e_clear_pxe_mode(struct i40e_hw *hw)
789{
790 u32 reg;
791
792 /* Clear single descriptor fetch/write-back mode */
793 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 794
795 if (hw->revision_id == 0) {
796 /* As a work around clear PXE_MODE instead of setting it */
797 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
798 } else {
799 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
800 }
56a62fc8
JB		 801}
802
0556a9e3
JB		 803/**
804 * i40e_led_is_mine - helper to find matching led
805 * @hw: pointer to the hw struct
806 * @idx: index into GPIO registers
807 *
808 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
809 */
810static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
811{
812 u32 gpio_val = 0;
813 u32 port;
814
815 if (!hw->func_caps.led[idx])
816 return 0;
817
818 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
819 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
820 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
821
822 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
823 * if it is not our port then ignore
824 */
825 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
826 (port != hw->port))
827 return 0;
828
829 return gpio_val;
830}
831
832#define I40E_LED0 22
833#define I40E_LINK_ACTIVITY 0xC
834
56a62fc8
JB		 835/**
836 * i40e_led_get - return current on/off mode
837 * @hw: pointer to the hw struct
838 *
839 * The value returned is the 'mode' field as defined in the
840 * GPIO register definitions: 0x0 = off, 0xf = on, and other
841 * values are variations of possible behaviors relating to
842 * blink, link, and wire.
843 **/
844u32 i40e_led_get(struct i40e_hw *hw)
845{
56a62fc8 846 u32 mode = 0;
56a62fc8
JB		 847 int i;
848
0556a9e3
JB		 849 /* as per the documentation GPIO 22-29 are the LED
850 * GPIO pins named LED0..LED7
851 */
852 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
853 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 854
0556a9e3 855 if (!gpio_val)
56a62fc8
JB		 856 continue;
857
0556a9e3
JB		 858 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
859 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 860 break;
861 }
862
863 return mode;
864}
865
866/**
867 * i40e_led_set - set new on/off mode
868 * @hw: pointer to the hw struct
0556a9e3
JB		 869 * @mode: 0=off, 0xf=on (else see manual for mode details)
870 * @blink: true if the LED should blink when on, false if steady
871 *
872 * if this function is used to turn on the blink it should
873 * be used to disable the blink when restoring the original state.
56a62fc8 874 **/
0556a9e3 875void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 876{
56a62fc8
JB		 877 int i;
878
0556a9e3
JB		 879 if (mode & 0xfffffff0)
880 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 881
0556a9e3
JB		 882 /* as per the documentation GPIO 22-29 are the LED
883 * GPIO pins named LED0..LED7
884 */
885 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
886 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 887
0556a9e3 888 if (!gpio_val)
56a62fc8
JB		 889 continue;
890
56a62fc8 891 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 892 /* this & is a bit of paranoia, but serves as a range check */
893 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
894 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
895
896 if (mode == I40E_LINK_ACTIVITY)
897 blink = false;
898
899 gpio_val |= (blink ? 1 : 0) <<
900 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
901
56a62fc8 902 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 903 break;
56a62fc8
JB		 904 }
905}
906
907/* Admin command wrappers */
56a62fc8
JB		 908
909/**
910 * i40e_aq_set_link_restart_an
911 * @hw: pointer to the hw struct
912 * @cmd_details: pointer to command details structure or NULL
913 *
914 * Sets up the link and restarts the Auto-Negotiation over the link.
915 **/
916i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
917 struct i40e_asq_cmd_details *cmd_details)
918{
919 struct i40e_aq_desc desc;
920 struct i40e_aqc_set_link_restart_an *cmd =
921 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
922 i40e_status status;
923
924 i40e_fill_default_direct_cmd_desc(&desc,
925 i40e_aqc_opc_set_link_restart_an);
926
927 cmd->command = I40E_AQ_PHY_RESTART_AN;
928
929 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
930
931 return status;
932}
933
934/**
935 * i40e_aq_get_link_info
936 * @hw: pointer to the hw struct
937 * @enable_lse: enable/disable LinkStatusEvent reporting
938 * @link: pointer to link status structure - optional
939 * @cmd_details: pointer to command details structure or NULL
940 *
941 * Returns the link status of the adapter.
942 **/
943i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
944 bool enable_lse, struct i40e_link_status *link,
945 struct i40e_asq_cmd_details *cmd_details)
946{
947 struct i40e_aq_desc desc;
948 struct i40e_aqc_get_link_status *resp =
949 (struct i40e_aqc_get_link_status *)&desc.params.raw;
950 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
951 i40e_status status;
952 u16 command_flags;
953
954 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
955
956 if (enable_lse)
957 command_flags = I40E_AQ_LSE_ENABLE;
958 else
959 command_flags = I40E_AQ_LSE_DISABLE;
960 resp->command_flags = cpu_to_le16(command_flags);
961
962 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
963
964 if (status)
965 goto aq_get_link_info_exit;
966
967 /* save off old link status information */
c36bd4a7 968 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 969
970 /* update link status */
971 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 972 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 973 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
974 hw_link_info->link_info = resp->link_info;
975 hw_link_info->an_info = resp->an_info;
976 hw_link_info->ext_info = resp->ext_info;
639dc377 977 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 978 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
979 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
980
981 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
982 hw_link_info->crc_enable = true;
983 else
984 hw_link_info->crc_enable = false;
56a62fc8
JB		 985
986 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
987 hw_link_info->lse_enable = true;
988 else
989 hw_link_info->lse_enable = false;
990
991 /* save link status information */
992 if (link)
d7595a22 993 *link = *hw_link_info;
56a62fc8
JB		 994
995 /* flag cleared so helper functions don't call AQ again */
996 hw->phy.get_link_info = false;
997
998aq_get_link_info_exit:
999 return status;
1000}
1001
1002/**
1003 * i40e_aq_add_vsi
1004 * @hw: pointer to the hw struct
98d44381 1005 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1006 * @cmd_details: pointer to command details structure or NULL
1007 *
1008 * Add a VSI context to the hardware.
1009**/
1010i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1011 struct i40e_vsi_context *vsi_ctx,
1012 struct i40e_asq_cmd_details *cmd_details)
1013{
1014 struct i40e_aq_desc desc;
1015 struct i40e_aqc_add_get_update_vsi *cmd =
1016 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1017 struct i40e_aqc_add_get_update_vsi_completion *resp =
1018 (struct i40e_aqc_add_get_update_vsi_completion *)
1019 &desc.params.raw;
1020 i40e_status status;
1021
1022 i40e_fill_default_direct_cmd_desc(&desc,
1023 i40e_aqc_opc_add_vsi);
1024
1025 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1026 cmd->connection_type = vsi_ctx->connection_type;
1027 cmd->vf_id = vsi_ctx->vf_num;
1028 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1029
1030 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1031 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
1032 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1033
1034 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1035 sizeof(vsi_ctx->info), cmd_details);
1036
1037 if (status)
1038 goto aq_add_vsi_exit;
1039
1040 vsi_ctx->seid = le16_to_cpu(resp->seid);
1041 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1042 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1043 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1044
1045aq_add_vsi_exit:
1046 return status;
1047}
1048
1049/**
1050 * i40e_aq_set_vsi_unicast_promiscuous
1051 * @hw: pointer to the hw struct
1052 * @seid: vsi number
1053 * @set: set unicast promiscuous enable/disable
1054 * @cmd_details: pointer to command details structure or NULL
1055 **/
1056i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1057 u16 seid, bool set,
1058 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1059{
1060 struct i40e_aq_desc desc;
1061 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1062 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1063 i40e_status status;
1064 u16 flags = 0;
1065
1066 i40e_fill_default_direct_cmd_desc(&desc,
1067 i40e_aqc_opc_set_vsi_promiscuous_modes);
1068
1069 if (set)
1070 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1071
1072 cmd->promiscuous_flags = cpu_to_le16(flags);
1073
1074 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1075
1076 cmd->seid = cpu_to_le16(seid);
1077 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1078
1079 return status;
1080}
1081
1082/**
1083 * i40e_aq_set_vsi_multicast_promiscuous
1084 * @hw: pointer to the hw struct
1085 * @seid: vsi number
1086 * @set: set multicast promiscuous enable/disable
1087 * @cmd_details: pointer to command details structure or NULL
1088 **/
1089i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1090 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1091{
1092 struct i40e_aq_desc desc;
1093 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1094 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1095 i40e_status status;
1096 u16 flags = 0;
1097
1098 i40e_fill_default_direct_cmd_desc(&desc,
1099 i40e_aqc_opc_set_vsi_promiscuous_modes);
1100
1101 if (set)
1102 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1103
1104 cmd->promiscuous_flags = cpu_to_le16(flags);
1105
1106 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1107
1108 cmd->seid = cpu_to_le16(seid);
1109 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1110
1111 return status;
1112}
1113
1114/**
1115 * i40e_aq_set_vsi_broadcast
1116 * @hw: pointer to the hw struct
1117 * @seid: vsi number
1118 * @set_filter: true to set filter, false to clear filter
1119 * @cmd_details: pointer to command details structure or NULL
1120 *
1121 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1122 **/
1123i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1124 u16 seid, bool set_filter,
1125 struct i40e_asq_cmd_details *cmd_details)
1126{
1127 struct i40e_aq_desc desc;
1128 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1129 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1130 i40e_status status;
1131
1132 i40e_fill_default_direct_cmd_desc(&desc,
1133 i40e_aqc_opc_set_vsi_promiscuous_modes);
1134
1135 if (set_filter)
1136 cmd->promiscuous_flags
1137 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1138 else
1139 cmd->promiscuous_flags
1140 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1141
1142 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1143 cmd->seid = cpu_to_le16(seid);
1144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1145
1146 return status;
1147}
1148
1149/**
1150 * i40e_get_vsi_params - get VSI configuration info
1151 * @hw: pointer to the hw struct
98d44381 1152 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1153 * @cmd_details: pointer to command details structure or NULL
1154 **/
1155i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1156 struct i40e_vsi_context *vsi_ctx,
1157 struct i40e_asq_cmd_details *cmd_details)
1158{
1159 struct i40e_aq_desc desc;
f5ac8579
SN		 1160 struct i40e_aqc_add_get_update_vsi *cmd =
1161 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1162 struct i40e_aqc_add_get_update_vsi_completion *resp =
1163 (struct i40e_aqc_add_get_update_vsi_completion *)
1164 &desc.params.raw;
1165 i40e_status status;
1166
1167 i40e_fill_default_direct_cmd_desc(&desc,
1168 i40e_aqc_opc_get_vsi_parameters);
1169
f5ac8579 1170 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1171
1172 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1173 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
1174 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1175
1176 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1177 sizeof(vsi_ctx->info), NULL);
1178
1179 if (status)
1180 goto aq_get_vsi_params_exit;
1181
1182 vsi_ctx->seid = le16_to_cpu(resp->seid);
1183 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1184 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1185 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1186
1187aq_get_vsi_params_exit:
1188 return status;
1189}
1190
1191/**
1192 * i40e_aq_update_vsi_params
1193 * @hw: pointer to the hw struct
98d44381 1194 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1195 * @cmd_details: pointer to command details structure or NULL
1196 *
1197 * Update a VSI context.
1198 **/
1199i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1200 struct i40e_vsi_context *vsi_ctx,
1201 struct i40e_asq_cmd_details *cmd_details)
1202{
1203 struct i40e_aq_desc desc;
f5ac8579
SN		 1204 struct i40e_aqc_add_get_update_vsi *cmd =
1205 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1206 i40e_status status;
1207
1208 i40e_fill_default_direct_cmd_desc(&desc,
1209 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 1210 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1211
1212 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1213 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
1214 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1215
1216 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1217 sizeof(vsi_ctx->info), cmd_details);
1218
1219 return status;
1220}
1221
1222/**
1223 * i40e_aq_get_switch_config
1224 * @hw: pointer to the hardware structure
1225 * @buf: pointer to the result buffer
1226 * @buf_size: length of input buffer
1227 * @start_seid: seid to start for the report, 0 == beginning
1228 * @cmd_details: pointer to command details structure or NULL
1229 *
1230 * Fill the buf with switch configuration returned from AdminQ command
1231 **/
1232i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1233 struct i40e_aqc_get_switch_config_resp *buf,
1234 u16 buf_size, u16 *start_seid,
1235 struct i40e_asq_cmd_details *cmd_details)
1236{
1237 struct i40e_aq_desc desc;
1238 struct i40e_aqc_switch_seid *scfg =
1239 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1240 i40e_status status;
1241
1242 i40e_fill_default_direct_cmd_desc(&desc,
1243 i40e_aqc_opc_get_switch_config);
1244 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1245 if (buf_size > I40E_AQ_LARGE_BUF)
1246 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1247 scfg->seid = cpu_to_le16(*start_seid);
1248
1249 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1250 *start_seid = le16_to_cpu(scfg->seid);
1251
1252 return status;
1253}
1254
1255/**
1256 * i40e_aq_get_firmware_version
1257 * @hw: pointer to the hw struct
1258 * @fw_major_version: firmware major version
1259 * @fw_minor_version: firmware minor version
1260 * @api_major_version: major queue version
1261 * @api_minor_version: minor queue version
1262 * @cmd_details: pointer to command details structure or NULL
1263 *
1264 * Get the firmware version from the admin queue commands
1265 **/
1266i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1267 u16 *fw_major_version, u16 *fw_minor_version,
1268 u16 *api_major_version, u16 *api_minor_version,
1269 struct i40e_asq_cmd_details *cmd_details)
1270{
1271 struct i40e_aq_desc desc;
1272 struct i40e_aqc_get_version *resp =
1273 (struct i40e_aqc_get_version *)&desc.params.raw;
1274 i40e_status status;
1275
1276 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1277
1278 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1279
1280 if (!status) {
1281 if (fw_major_version != NULL)
1282 *fw_major_version = le16_to_cpu(resp->fw_major);
1283 if (fw_minor_version != NULL)
1284 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1285 if (api_major_version != NULL)
1286 *api_major_version = le16_to_cpu(resp->api_major);
1287 if (api_minor_version != NULL)
1288 *api_minor_version = le16_to_cpu(resp->api_minor);
1289 }
1290
1291 return status;
1292}
1293
1294/**
1295 * i40e_aq_send_driver_version
1296 * @hw: pointer to the hw struct
56a62fc8
JB		 1297 * @dv: driver's major, minor version
1298 * @cmd_details: pointer to command details structure or NULL
1299 *
1300 * Send the driver version to the firmware
1301 **/
1302i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1303 struct i40e_driver_version *dv,
1304 struct i40e_asq_cmd_details *cmd_details)
1305{
1306 struct i40e_aq_desc desc;
1307 struct i40e_aqc_driver_version *cmd =
1308 (struct i40e_aqc_driver_version *)&desc.params.raw;
1309 i40e_status status;
9d2f98e1 1310 u16 len;
56a62fc8
JB		 1311
1312 if (dv == NULL)
1313 return I40E_ERR_PARAM;
1314
1315 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1316
1317 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1318 cmd->driver_major_ver = dv->major_version;
1319 cmd->driver_minor_ver = dv->minor_version;
1320 cmd->driver_build_ver = dv->build_version;
1321 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 1322
1323 len = 0;
1324 while (len < sizeof(dv->driver_string) &&
1325 (dv->driver_string[len] < 0x80) &&
1326 dv->driver_string[len])
1327 len++;
1328 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1329 len, cmd_details);
56a62fc8
JB		 1330
1331 return status;
1332}
1333
1334/**
1335 * i40e_get_link_status - get status of the HW network link
1336 * @hw: pointer to the hw struct
1337 *
1338 * Returns true if link is up, false if link is down.
1339 *
1340 * Side effect: LinkStatusEvent reporting becomes enabled
1341 **/
1342bool i40e_get_link_status(struct i40e_hw *hw)
1343{
1344 i40e_status status = 0;
1345 bool link_status = false;
1346
1347 if (hw->phy.get_link_info) {
1348 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1349
1350 if (status)
1351 goto i40e_get_link_status_exit;
1352 }
1353
1354 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1355
1356i40e_get_link_status_exit:
1357 return link_status;
1358}
1359
1360/**
1361 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1362 * @hw: pointer to the hw struct
1363 * @uplink_seid: the MAC or other gizmo SEID
1364 * @downlink_seid: the VSI SEID
1365 * @enabled_tc: bitmap of TCs to be enabled
1366 * @default_port: true for default port VSI, false for control port
e1c51b95 1367 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 1368 * @veb_seid: pointer to where to put the resulting VEB SEID
1369 * @cmd_details: pointer to command details structure or NULL
1370 *
1371 * This asks the FW to add a VEB between the uplink and downlink
1372 * elements. If the uplink SEID is 0, this will be a floating VEB.
1373 **/
1374i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1375 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 1376 bool default_port, bool enable_l2_filtering,
1377 u16 *veb_seid,
56a62fc8
JB		 1378 struct i40e_asq_cmd_details *cmd_details)
1379{
1380 struct i40e_aq_desc desc;
1381 struct i40e_aqc_add_veb *cmd =
1382 (struct i40e_aqc_add_veb *)&desc.params.raw;
1383 struct i40e_aqc_add_veb_completion *resp =
1384 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1385 i40e_status status;
1386 u16 veb_flags = 0;
1387
1388 /* SEIDs need to either both be set or both be 0 for floating VEB */
1389 if (!!uplink_seid != !!downlink_seid)
1390 return I40E_ERR_PARAM;
1391
1392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1393
1394 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1395 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1396 cmd->enable_tcs = enabled_tc;
1397 if (!uplink_seid)
1398 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1399 if (default_port)
1400 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1401 else
1402 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1403
1404 if (enable_l2_filtering)
1405 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1406
56a62fc8
JB		 1407 cmd->veb_flags = cpu_to_le16(veb_flags);
1408
1409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1410
1411 if (!status && veb_seid)
1412 *veb_seid = le16_to_cpu(resp->veb_seid);
1413
1414 return status;
1415}
1416
1417/**
1418 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1419 * @hw: pointer to the hw struct
1420 * @veb_seid: the SEID of the VEB to query
1421 * @switch_id: the uplink switch id
98d44381 1422 * @floating: set to true if the VEB is floating
56a62fc8
JB		 1423 * @statistic_index: index of the stats counter block for this VEB
1424 * @vebs_used: number of VEB's used by function
98d44381 1425 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 1426 * @cmd_details: pointer to command details structure or NULL
1427 *
1428 * This retrieves the parameters for a particular VEB, specified by
1429 * uplink_seid, and returns them to the caller.
1430 **/
1431i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1432 u16 veb_seid, u16 *switch_id,
1433 bool *floating, u16 *statistic_index,
1434 u16 *vebs_used, u16 *vebs_free,
1435 struct i40e_asq_cmd_details *cmd_details)
1436{
1437 struct i40e_aq_desc desc;
1438 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1439 (struct i40e_aqc_get_veb_parameters_completion *)
1440 &desc.params.raw;
1441 i40e_status status;
1442
1443 if (veb_seid == 0)
1444 return I40E_ERR_PARAM;
1445
1446 i40e_fill_default_direct_cmd_desc(&desc,
1447 i40e_aqc_opc_get_veb_parameters);
1448 cmd_resp->seid = cpu_to_le16(veb_seid);
1449
1450 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1451 if (status)
1452 goto get_veb_exit;
1453
1454 if (switch_id)
1455 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1456 if (statistic_index)
1457 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1458 if (vebs_used)
1459 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1460 if (vebs_free)
1461 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1462 if (floating) {
1463 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1464 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1465 *floating = true;
1466 else
1467 *floating = false;
1468 }
1469
1470get_veb_exit:
1471 return status;
1472}
1473
1474/**
1475 * i40e_aq_add_macvlan
1476 * @hw: pointer to the hw struct
1477 * @seid: VSI for the mac address
1478 * @mv_list: list of macvlans to be added
1479 * @count: length of the list
1480 * @cmd_details: pointer to command details structure or NULL
1481 *
1482 * Add MAC/VLAN addresses to the HW filtering
1483 **/
1484i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1485 struct i40e_aqc_add_macvlan_element_data *mv_list,
1486 u16 count, struct i40e_asq_cmd_details *cmd_details)
1487{
1488 struct i40e_aq_desc desc;
1489 struct i40e_aqc_macvlan *cmd =
1490 (struct i40e_aqc_macvlan *)&desc.params.raw;
1491 i40e_status status;
1492 u16 buf_size;
1493
1494 if (count == 0 || !mv_list || !hw)
1495 return I40E_ERR_PARAM;
1496
1497 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1498
1499 /* prep the rest of the request */
1500 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1501 cmd->num_addresses = cpu_to_le16(count);
1502 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1503 cmd->seid[1] = 0;
1504 cmd->seid[2] = 0;
1505
1506 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1507 if (buf_size > I40E_AQ_LARGE_BUF)
1508 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1509
1510 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1511 cmd_details);
1512
1513 return status;
1514}
1515
1516/**
1517 * i40e_aq_remove_macvlan
1518 * @hw: pointer to the hw struct
1519 * @seid: VSI for the mac address
1520 * @mv_list: list of macvlans to be removed
1521 * @count: length of the list
1522 * @cmd_details: pointer to command details structure or NULL
1523 *
1524 * Remove MAC/VLAN addresses from the HW filtering
1525 **/
1526i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1527 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1528 u16 count, struct i40e_asq_cmd_details *cmd_details)
1529{
1530 struct i40e_aq_desc desc;
1531 struct i40e_aqc_macvlan *cmd =
1532 (struct i40e_aqc_macvlan *)&desc.params.raw;
1533 i40e_status status;
1534 u16 buf_size;
1535
1536 if (count == 0 || !mv_list || !hw)
1537 return I40E_ERR_PARAM;
1538
1539 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1540
1541 /* prep the rest of the request */
1542 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1543 cmd->num_addresses = cpu_to_le16(count);
1544 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1545 cmd->seid[1] = 0;
1546 cmd->seid[2] = 0;
1547
1548 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1549 if (buf_size > I40E_AQ_LARGE_BUF)
1550 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1551
1552 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1553 cmd_details);
1554
1555 return status;
1556}
1557
56a62fc8
JB		 1558/**
1559 * i40e_aq_send_msg_to_vf
1560 * @hw: pointer to the hardware structure
1561 * @vfid: vf id to send msg
98d44381
JK		 1562 * @v_opcode: opcodes for VF-PF communication
1563 * @v_retval: return error code
56a62fc8
JB		 1564 * @msg: pointer to the msg buffer
1565 * @msglen: msg length
1566 * @cmd_details: pointer to command details
1567 *
1568 * send msg to vf
1569 **/
1570i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1571 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1572 struct i40e_asq_cmd_details *cmd_details)
1573{
1574 struct i40e_aq_desc desc;
1575 struct i40e_aqc_pf_vf_message *cmd =
1576 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1577 i40e_status status;
1578
1579 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1580 cmd->id = cpu_to_le32(vfid);
1581 desc.cookie_high = cpu_to_le32(v_opcode);
1582 desc.cookie_low = cpu_to_le32(v_retval);
1583 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1584 if (msglen) {
1585 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1586 I40E_AQ_FLAG_RD));
1587 if (msglen > I40E_AQ_LARGE_BUF)
1588 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1589 desc.datalen = cpu_to_le16(msglen);
1590 }
1591 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1592
1593 return status;
1594}
1595
1596/**
1597 * i40e_aq_set_hmc_resource_profile
1598 * @hw: pointer to the hw struct
1599 * @profile: type of profile the HMC is to be set as
1600 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1601 * @cmd_details: pointer to command details structure or NULL
1602 *
1603 * set the HMC profile of the device.
1604 **/
1605i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1606 enum i40e_aq_hmc_profile profile,
1607 u8 pe_vf_enabled_count,
1608 struct i40e_asq_cmd_details *cmd_details)
1609{
1610 struct i40e_aq_desc desc;
1611 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1612 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1613 i40e_status status;
1614
1615 i40e_fill_default_direct_cmd_desc(&desc,
1616 i40e_aqc_opc_set_hmc_resource_profile);
1617
1618 cmd->pm_profile = (u8)profile;
1619 cmd->pe_vf_enabled = pe_vf_enabled_count;
1620
1621 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1622
1623 return status;
1624}
1625
1626/**
1627 * i40e_aq_request_resource
1628 * @hw: pointer to the hw struct
1629 * @resource: resource id
1630 * @access: access type
1631 * @sdp_number: resource number
1632 * @timeout: the maximum time in ms that the driver may hold the resource
1633 * @cmd_details: pointer to command details structure or NULL
1634 *
1635 * requests common resource using the admin queue commands
1636 **/
1637i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1638 enum i40e_aq_resources_ids resource,
1639 enum i40e_aq_resource_access_type access,
1640 u8 sdp_number, u64 *timeout,
1641 struct i40e_asq_cmd_details *cmd_details)
1642{
1643 struct i40e_aq_desc desc;
1644 struct i40e_aqc_request_resource *cmd_resp =
1645 (struct i40e_aqc_request_resource *)&desc.params.raw;
1646 i40e_status status;
1647
1648 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1649
1650 cmd_resp->resource_id = cpu_to_le16(resource);
1651 cmd_resp->access_type = cpu_to_le16(access);
1652 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1653
1654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1655 /* The completion specifies the maximum time in ms that the driver
1656 * may hold the resource in the Timeout field.
1657 * If the resource is held by someone else, the command completes with
1658 * busy return value and the timeout field indicates the maximum time
1659 * the current owner of the resource has to free it.
1660 */
1661 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1662 *timeout = le32_to_cpu(cmd_resp->timeout);
1663
1664 return status;
1665}
1666
1667/**
1668 * i40e_aq_release_resource
1669 * @hw: pointer to the hw struct
1670 * @resource: resource id
1671 * @sdp_number: resource number
1672 * @cmd_details: pointer to command details structure or NULL
1673 *
1674 * release common resource using the admin queue commands
1675 **/
1676i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1677 enum i40e_aq_resources_ids resource,
1678 u8 sdp_number,
1679 struct i40e_asq_cmd_details *cmd_details)
1680{
1681 struct i40e_aq_desc desc;
1682 struct i40e_aqc_request_resource *cmd =
1683 (struct i40e_aqc_request_resource *)&desc.params.raw;
1684 i40e_status status;
1685
1686 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1687
1688 cmd->resource_id = cpu_to_le16(resource);
1689 cmd->resource_number = cpu_to_le32(sdp_number);
1690
1691 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1692
1693 return status;
1694}
1695
1696/**
1697 * i40e_aq_read_nvm
1698 * @hw: pointer to the hw struct
1699 * @module_pointer: module pointer location in words from the NVM beginning
1700 * @offset: byte offset from the module beginning
1701 * @length: length of the section to be read (in bytes from the offset)
1702 * @data: command buffer (size [bytes] = length)
1703 * @last_command: tells if this is the last command in a series
1704 * @cmd_details: pointer to command details structure or NULL
1705 *
1706 * Read the NVM using the admin queue commands
1707 **/
1708i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1709 u32 offset, u16 length, void *data,
1710 bool last_command,
1711 struct i40e_asq_cmd_details *cmd_details)
1712{
1713 struct i40e_aq_desc desc;
1714 struct i40e_aqc_nvm_update *cmd =
1715 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1716 i40e_status status;
1717
1718 /* In offset the highest byte must be zeroed. */
1719 if (offset & 0xFF000000) {
1720 status = I40E_ERR_PARAM;
1721 goto i40e_aq_read_nvm_exit;
1722 }
1723
1724 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1725
1726 /* If this is the last command in a series, set the proper flag. */
1727 if (last_command)
1728 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1729 cmd->module_pointer = module_pointer;
1730 cmd->offset = cpu_to_le32(offset);
1731 cmd->length = cpu_to_le16(length);
1732
1733 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1734 if (length > I40E_AQ_LARGE_BUF)
1735 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1736
1737 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1738
1739i40e_aq_read_nvm_exit:
1740 return status;
1741}
1742
1743#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1744#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1745#define I40E_DEV_FUNC_CAP_NPAR 0x03
1746#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1747#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1748#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1749#define I40E_DEV_FUNC_CAP_VF 0x13
1750#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1751#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1752#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1753#define I40E_DEV_FUNC_CAP_VSI 0x17
1754#define I40E_DEV_FUNC_CAP_DCB 0x18
1755#define I40E_DEV_FUNC_CAP_FCOE 0x21
1756#define I40E_DEV_FUNC_CAP_RSS 0x40
1757#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1758#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1759#define I40E_DEV_FUNC_CAP_MSIX 0x43
1760#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1761#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1762#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1763#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1764#define I40E_DEV_FUNC_CAP_CEM 0xF2
1765#define I40E_DEV_FUNC_CAP_IWARP 0x51
1766#define I40E_DEV_FUNC_CAP_LED 0x61
1767#define I40E_DEV_FUNC_CAP_SDP 0x62
1768#define I40E_DEV_FUNC_CAP_MDIO 0x63
1769
1770/**
1771 * i40e_parse_discover_capabilities
1772 * @hw: pointer to the hw struct
1773 * @buff: pointer to a buffer containing device/function capability records
1774 * @cap_count: number of capability records in the list
1775 * @list_type_opc: type of capabilities list to parse
1776 *
1777 * Parse the device/function capabilities list.
1778 **/
1779static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1780 u32 cap_count,
1781 enum i40e_admin_queue_opc list_type_opc)
1782{
1783 struct i40e_aqc_list_capabilities_element_resp *cap;
1784 u32 number, logical_id, phys_id;
1785 struct i40e_hw_capabilities *p;
1786 u32 reg_val;
1787 u32 i = 0;
1788 u16 id;
1789
1790 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1791
1792 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 1793 p = &hw->dev_caps;
56a62fc8 1794 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 1795 p = &hw->func_caps;
56a62fc8
JB		 1796 else
1797 return;
1798
1799 for (i = 0; i < cap_count; i++, cap++) {
1800 id = le16_to_cpu(cap->id);
1801 number = le32_to_cpu(cap->number);
1802 logical_id = le32_to_cpu(cap->logical_id);
1803 phys_id = le32_to_cpu(cap->phys_id);
1804
1805 switch (id) {
1806 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1807 p->switch_mode = number;
1808 break;
1809 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1810 p->management_mode = number;
1811 break;
1812 case I40E_DEV_FUNC_CAP_NPAR:
1813 p->npar_enable = number;
1814 break;
1815 case I40E_DEV_FUNC_CAP_OS2BMC:
1816 p->os2bmc = number;
1817 break;
1818 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1819 p->valid_functions = number;
1820 break;
1821 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1822 if (number == 1)
1823 p->sr_iov_1_1 = true;
1824 break;
1825 case I40E_DEV_FUNC_CAP_VF:
1826 p->num_vfs = number;
1827 p->vf_base_id = logical_id;
1828 break;
1829 case I40E_DEV_FUNC_CAP_VMDQ:
1830 if (number == 1)
1831 p->vmdq = true;
1832 break;
1833 case I40E_DEV_FUNC_CAP_802_1_QBG:
1834 if (number == 1)
1835 p->evb_802_1_qbg = true;
1836 break;
1837 case I40E_DEV_FUNC_CAP_802_1_QBH:
1838 if (number == 1)
1839 p->evb_802_1_qbh = true;
1840 break;
1841 case I40E_DEV_FUNC_CAP_VSI:
1842 p->num_vsis = number;
1843 break;
1844 case I40E_DEV_FUNC_CAP_DCB:
1845 if (number == 1) {
1846 p->dcb = true;
1847 p->enabled_tcmap = logical_id;
1848 p->maxtc = phys_id;
1849 }
1850 break;
1851 case I40E_DEV_FUNC_CAP_FCOE:
1852 if (number == 1)
1853 p->fcoe = true;
1854 break;
1855 case I40E_DEV_FUNC_CAP_RSS:
1856 p->rss = true;
1857 reg_val = rd32(hw, I40E_PFQF_CTL_0);
1858 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1859 p->rss_table_size = number;
1860 else
1861 p->rss_table_size = 128;
1862 p->rss_table_entry_width = logical_id;
1863 break;
1864 case I40E_DEV_FUNC_CAP_RX_QUEUES:
1865 p->num_rx_qp = number;
1866 p->base_queue = phys_id;
1867 break;
1868 case I40E_DEV_FUNC_CAP_TX_QUEUES:
1869 p->num_tx_qp = number;
1870 p->base_queue = phys_id;
1871 break;
1872 case I40E_DEV_FUNC_CAP_MSIX:
1873 p->num_msix_vectors = number;
1874 break;
1875 case I40E_DEV_FUNC_CAP_MSIX_VF:
1876 p->num_msix_vectors_vf = number;
1877 break;
1878 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
1879 if (number == 1)
1880 p->mfp_mode_1 = true;
1881 break;
1882 case I40E_DEV_FUNC_CAP_CEM:
1883 if (number == 1)
1884 p->mgmt_cem = true;
1885 break;
1886 case I40E_DEV_FUNC_CAP_IWARP:
1887 if (number == 1)
1888 p->iwarp = true;
1889 break;
1890 case I40E_DEV_FUNC_CAP_LED:
1891 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1892 p->led[phys_id] = true;
1893 break;
1894 case I40E_DEV_FUNC_CAP_SDP:
1895 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1896 p->sdp[phys_id] = true;
1897 break;
1898 case I40E_DEV_FUNC_CAP_MDIO:
1899 if (number == 1) {
1900 p->mdio_port_num = phys_id;
1901 p->mdio_port_mode = logical_id;
1902 }
1903 break;
1904 case I40E_DEV_FUNC_CAP_IEEE_1588:
1905 if (number == 1)
1906 p->ieee_1588 = true;
1907 break;
1908 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
1909 p->fd = true;
1910 p->fd_filters_guaranteed = number;
1911 p->fd_filters_best_effort = logical_id;
1912 break;
1913 default:
1914 break;
1915 }
1916 }
1917
1918 /* additional HW specific goodies that might
1919 * someday be HW version specific
1920 */
1921 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
1922}
1923
1924/**
1925 * i40e_aq_discover_capabilities
1926 * @hw: pointer to the hw struct
1927 * @buff: a virtual buffer to hold the capabilities
1928 * @buff_size: Size of the virtual buffer
1929 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1930 * @list_type_opc: capabilities type to discover - pass in the command opcode
1931 * @cmd_details: pointer to command details structure or NULL
1932 *
1933 * Get the device capabilities descriptions from the firmware
1934 **/
1935i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
1936 void *buff, u16 buff_size, u16 *data_size,
1937 enum i40e_admin_queue_opc list_type_opc,
1938 struct i40e_asq_cmd_details *cmd_details)
1939{
1940 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 1941 struct i40e_aq_desc desc;
8fb905b3 1942 i40e_status status = 0;
56a62fc8
JB		 1943
1944 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
1945
1946 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
1947 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
1948 status = I40E_ERR_PARAM;
1949 goto exit;
1950 }
1951
1952 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
1953
1954 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1955 if (buff_size > I40E_AQ_LARGE_BUF)
1956 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1957
1958 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1959 *data_size = le16_to_cpu(desc.datalen);
1960
1961 if (status)
1962 goto exit;
1963
1964 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
1965 list_type_opc);
1966
1967exit:
1968 return status;
1969}
1970
1971/**
1972 * i40e_aq_get_lldp_mib
1973 * @hw: pointer to the hw struct
1974 * @bridge_type: type of bridge requested
1975 * @mib_type: Local, Remote or both Local and Remote MIBs
1976 * @buff: pointer to a user supplied buffer to store the MIB block
1977 * @buff_size: size of the buffer (in bytes)
1978 * @local_len : length of the returned Local LLDP MIB
1979 * @remote_len: length of the returned Remote LLDP MIB
1980 * @cmd_details: pointer to command details structure or NULL
1981 *
1982 * Requests the complete LLDP MIB (entire packet).
1983 **/
1984i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
1985 u8 mib_type, void *buff, u16 buff_size,
1986 u16 *local_len, u16 *remote_len,
1987 struct i40e_asq_cmd_details *cmd_details)
1988{
1989 struct i40e_aq_desc desc;
1990 struct i40e_aqc_lldp_get_mib *cmd =
1991 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1992 struct i40e_aqc_lldp_get_mib *resp =
1993 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1994 i40e_status status;
1995
1996 if (buff_size == 0 || !buff)
1997 return I40E_ERR_PARAM;
1998
1999 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2000 /* Indirect Command */
2001 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2002
2003 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2004 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2005 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2006
2007 desc.datalen = cpu_to_le16(buff_size);
2008
2009 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2010 if (buff_size > I40E_AQ_LARGE_BUF)
2011 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2012
2013 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2014 if (!status) {
2015 if (local_len != NULL)
2016 *local_len = le16_to_cpu(resp->local_len);
2017 if (remote_len != NULL)
2018 *remote_len = le16_to_cpu(resp->remote_len);
2019 }
2020
2021 return status;
2022}
2023
2024/**
2025 * i40e_aq_cfg_lldp_mib_change_event
2026 * @hw: pointer to the hw struct
2027 * @enable_update: Enable or Disable event posting
2028 * @cmd_details: pointer to command details structure or NULL
2029 *
2030 * Enable or Disable posting of an event on ARQ when LLDP MIB
2031 * associated with the interface changes
2032 **/
2033i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2034 bool enable_update,
2035 struct i40e_asq_cmd_details *cmd_details)
2036{
2037 struct i40e_aq_desc desc;
2038 struct i40e_aqc_lldp_update_mib *cmd =
2039 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2040 i40e_status status;
2041
2042 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2043
2044 if (!enable_update)
2045 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2046
2047 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2048
2049 return status;
2050}
2051
2052/**
2053 * i40e_aq_stop_lldp
2054 * @hw: pointer to the hw struct
2055 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2056 * @cmd_details: pointer to command details structure or NULL
2057 *
2058 * Stop or Shutdown the embedded LLDP Agent
2059 **/
2060i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2061 struct i40e_asq_cmd_details *cmd_details)
2062{
2063 struct i40e_aq_desc desc;
2064 struct i40e_aqc_lldp_stop *cmd =
2065 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2066 i40e_status status;
2067
2068 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2069
2070 if (shutdown_agent)
2071 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2072
2073 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2074
2075 return status;
2076}
2077
2078/**
2079 * i40e_aq_start_lldp
2080 * @hw: pointer to the hw struct
2081 * @cmd_details: pointer to command details structure or NULL
2082 *
2083 * Start the embedded LLDP Agent on all ports.
2084 **/
2085i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2086 struct i40e_asq_cmd_details *cmd_details)
2087{
2088 struct i40e_aq_desc desc;
2089 struct i40e_aqc_lldp_start *cmd =
2090 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2091 i40e_status status;
2092
2093 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2094
2095 cmd->command = I40E_AQ_LLDP_AGENT_START;
2096
2097 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2098
2099 return status;
2100}
2101
a1c9a9d9
JK		 2102/**
2103 * i40e_aq_add_udp_tunnel
2104 * @hw: pointer to the hw struct
2105 * @udp_port: the UDP port to add
2106 * @header_len: length of the tunneling header length in DWords
2107 * @protocol_index: protocol index type
98d44381 2108 * @filter_index: pointer to filter index
a1c9a9d9
JK		 2109 * @cmd_details: pointer to command details structure or NULL
2110 **/
2111i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 2112 u16 udp_port, u8 protocol_index,
2113 u8 *filter_index,
a1c9a9d9
JK		 2114 struct i40e_asq_cmd_details *cmd_details)
2115{
2116 struct i40e_aq_desc desc;
2117 struct i40e_aqc_add_udp_tunnel *cmd =
2118 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2119 struct i40e_aqc_del_udp_tunnel_completion *resp =
2120 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2121 i40e_status status;
2122
2123 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2124
2125 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 2126 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 2127
2128 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2129
2130 if (!status)
2131 *filter_index = resp->index;
2132
2133 return status;
2134}
2135
2136/**
2137 * i40e_aq_del_udp_tunnel
2138 * @hw: pointer to the hw struct
2139 * @index: filter index
2140 * @cmd_details: pointer to command details structure or NULL
2141 **/
2142i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2143 struct i40e_asq_cmd_details *cmd_details)
2144{
2145 struct i40e_aq_desc desc;
2146 struct i40e_aqc_remove_udp_tunnel *cmd =
2147 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2148 i40e_status status;
2149
2150 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2151
2152 cmd->index = index;
2153
2154 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2155
2156 return status;
2157}
2158
56a62fc8
JB		 2159/**
2160 * i40e_aq_delete_element - Delete switch element
2161 * @hw: pointer to the hw struct
2162 * @seid: the SEID to delete from the switch
2163 * @cmd_details: pointer to command details structure or NULL
2164 *
2165 * This deletes a switch element from the switch.
2166 **/
2167i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2168 struct i40e_asq_cmd_details *cmd_details)
2169{
2170 struct i40e_aq_desc desc;
2171 struct i40e_aqc_switch_seid *cmd =
2172 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2173 i40e_status status;
2174
2175 if (seid == 0)
2176 return I40E_ERR_PARAM;
2177
2178 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2179
2180 cmd->seid = cpu_to_le16(seid);
2181
2182 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2183
2184 return status;
2185}
2186
afb3ff0d
NP		 2187/**
2188 * i40e_aq_dcb_updated - DCB Updated Command
2189 * @hw: pointer to the hw struct
2190 * @cmd_details: pointer to command details structure or NULL
2191 *
2192 * EMP will return when the shared RPB settings have been
2193 * recomputed and modified. The retval field in the descriptor
2194 * will be set to 0 when RPB is modified.
2195 **/
2196i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2197 struct i40e_asq_cmd_details *cmd_details)
2198{
2199 struct i40e_aq_desc desc;
2200 i40e_status status;
2201
2202 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2203
2204 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2205
2206 return status;
2207}
2208
56a62fc8
JB		 2209/**
2210 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2211 * @hw: pointer to the hw struct
2212 * @seid: seid for the physical port/switching component/vsi
2213 * @buff: Indirect buffer to hold data parameters and response
2214 * @buff_size: Indirect buffer size
2215 * @opcode: Tx scheduler AQ command opcode
2216 * @cmd_details: pointer to command details structure or NULL
2217 *
2218 * Generic command handler for Tx scheduler AQ commands
2219 **/
2220static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2221 void *buff, u16 buff_size,
2222 enum i40e_admin_queue_opc opcode,
2223 struct i40e_asq_cmd_details *cmd_details)
2224{
2225 struct i40e_aq_desc desc;
2226 struct i40e_aqc_tx_sched_ind *cmd =
2227 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2228 i40e_status status;
2229 bool cmd_param_flag = false;
2230
2231 switch (opcode) {
2232 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2233 case i40e_aqc_opc_configure_vsi_tc_bw:
2234 case i40e_aqc_opc_enable_switching_comp_ets:
2235 case i40e_aqc_opc_modify_switching_comp_ets:
2236 case i40e_aqc_opc_disable_switching_comp_ets:
2237 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2238 case i40e_aqc_opc_configure_switching_comp_bw_config:
2239 cmd_param_flag = true;
2240 break;
2241 case i40e_aqc_opc_query_vsi_bw_config:
2242 case i40e_aqc_opc_query_vsi_ets_sla_config:
2243 case i40e_aqc_opc_query_switching_comp_ets_config:
2244 case i40e_aqc_opc_query_port_ets_config:
2245 case i40e_aqc_opc_query_switching_comp_bw_config:
2246 cmd_param_flag = false;
2247 break;
2248 default:
2249 return I40E_ERR_PARAM;
2250 }
2251
2252 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2253
2254 /* Indirect command */
2255 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2256 if (cmd_param_flag)
2257 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2258 if (buff_size > I40E_AQ_LARGE_BUF)
2259 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2260
2261 desc.datalen = cpu_to_le16(buff_size);
2262
2263 cmd->vsi_seid = cpu_to_le16(seid);
2264
2265 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2266
2267 return status;
2268}
2269
6b192891
MW		 2270/**
2271 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2272 * @hw: pointer to the hw struct
2273 * @seid: VSI seid
2274 * @credit: BW limit credits (0 = disabled)
2275 * @max_credit: Max BW limit credits
2276 * @cmd_details: pointer to command details structure or NULL
2277 **/
2278i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2279 u16 seid, u16 credit, u8 max_credit,
2280 struct i40e_asq_cmd_details *cmd_details)
2281{
2282 struct i40e_aq_desc desc;
2283 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2284 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2285 i40e_status status;
2286
2287 i40e_fill_default_direct_cmd_desc(&desc,
2288 i40e_aqc_opc_configure_vsi_bw_limit);
2289
2290 cmd->vsi_seid = cpu_to_le16(seid);
2291 cmd->credit = cpu_to_le16(credit);
2292 cmd->max_credit = max_credit;
2293
2294 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2295
2296 return status;
2297}
2298
56a62fc8
JB		 2299/**
2300 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2301 * @hw: pointer to the hw struct
2302 * @seid: VSI seid
2303 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2304 * @cmd_details: pointer to command details structure or NULL
2305 **/
2306i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2307 u16 seid,
2308 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2309 struct i40e_asq_cmd_details *cmd_details)
2310{
2311 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2312 i40e_aqc_opc_configure_vsi_tc_bw,
2313 cmd_details);
2314}
2315
afb3ff0d
NP		 2316/**
2317 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2318 * @hw: pointer to the hw struct
2319 * @seid: seid of the switching component connected to Physical Port
2320 * @ets_data: Buffer holding ETS parameters
2321 * @cmd_details: pointer to command details structure or NULL
2322 **/
2323i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2324 u16 seid,
2325 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2326 enum i40e_admin_queue_opc opcode,
2327 struct i40e_asq_cmd_details *cmd_details)
2328{
2329 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2330 sizeof(*ets_data), opcode, cmd_details);
2331}
2332
2333/**
2334 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2335 * @hw: pointer to the hw struct
2336 * @seid: seid of the switching component
2337 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2338 * @cmd_details: pointer to command details structure or NULL
2339 **/
2340i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2341 u16 seid,
2342 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2343 struct i40e_asq_cmd_details *cmd_details)
2344{
2345 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2346 i40e_aqc_opc_configure_switching_comp_bw_config,
2347 cmd_details);
2348}
2349
56a62fc8
JB		 2350/**
2351 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2352 * @hw: pointer to the hw struct
2353 * @seid: seid of the VSI
2354 * @bw_data: Buffer to hold VSI BW configuration
2355 * @cmd_details: pointer to command details structure or NULL
2356 **/
2357i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2358 u16 seid,
2359 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2360 struct i40e_asq_cmd_details *cmd_details)
2361{
2362 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2363 i40e_aqc_opc_query_vsi_bw_config,
2364 cmd_details);
2365}
2366
2367/**
2368 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2369 * @hw: pointer to the hw struct
2370 * @seid: seid of the VSI
2371 * @bw_data: Buffer to hold VSI BW configuration per TC
2372 * @cmd_details: pointer to command details structure or NULL
2373 **/
2374i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2375 u16 seid,
2376 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2377 struct i40e_asq_cmd_details *cmd_details)
2378{
2379 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2380 i40e_aqc_opc_query_vsi_ets_sla_config,
2381 cmd_details);
2382}
2383
2384/**
2385 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2386 * @hw: pointer to the hw struct
2387 * @seid: seid of the switching component
2388 * @bw_data: Buffer to hold switching component's per TC BW config
2389 * @cmd_details: pointer to command details structure or NULL
2390 **/
2391i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2392 u16 seid,
2393 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2394 struct i40e_asq_cmd_details *cmd_details)
2395{
2396 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2397 i40e_aqc_opc_query_switching_comp_ets_config,
2398 cmd_details);
2399}
2400
2401/**
2402 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2403 * @hw: pointer to the hw struct
2404 * @seid: seid of the VSI or switching component connected to Physical Port
2405 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2406 * @cmd_details: pointer to command details structure or NULL
2407 **/
2408i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2409 u16 seid,
2410 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2411 struct i40e_asq_cmd_details *cmd_details)
2412{
2413 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2414 i40e_aqc_opc_query_port_ets_config,
2415 cmd_details);
2416}
2417
2418/**
2419 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2420 * @hw: pointer to the hw struct
2421 * @seid: seid of the switching component
2422 * @bw_data: Buffer to hold switching component's BW configuration
2423 * @cmd_details: pointer to command details structure or NULL
2424 **/
2425i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2426 u16 seid,
2427 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2428 struct i40e_asq_cmd_details *cmd_details)
2429{
2430 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2431 i40e_aqc_opc_query_switching_comp_bw_config,
2432 cmd_details);
2433}
2434
2435/**
2436 * i40e_validate_filter_settings
2437 * @hw: pointer to the hardware structure
2438 * @settings: Filter control settings
2439 *
2440 * Check and validate the filter control settings passed.
2441 * The function checks for the valid filter/context sizes being
2442 * passed for FCoE and PE.
2443 *
2444 * Returns 0 if the values passed are valid and within
2445 * range else returns an error.
2446 **/
2447static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2448 struct i40e_filter_control_settings *settings)
2449{
2450 u32 fcoe_cntx_size, fcoe_filt_size;
2451 u32 pe_cntx_size, pe_filt_size;
2452 u32 fcoe_fmax, pe_fmax;
2453 u32 val;
2454
2455 /* Validate FCoE settings passed */
2456 switch (settings->fcoe_filt_num) {
2457 case I40E_HASH_FILTER_SIZE_1K:
2458 case I40E_HASH_FILTER_SIZE_2K:
2459 case I40E_HASH_FILTER_SIZE_4K:
2460 case I40E_HASH_FILTER_SIZE_8K:
2461 case I40E_HASH_FILTER_SIZE_16K:
2462 case I40E_HASH_FILTER_SIZE_32K:
2463 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2464 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2465 break;
2466 default:
2467 return I40E_ERR_PARAM;
2468 }
2469
2470 switch (settings->fcoe_cntx_num) {
2471 case I40E_DMA_CNTX_SIZE_512:
2472 case I40E_DMA_CNTX_SIZE_1K:
2473 case I40E_DMA_CNTX_SIZE_2K:
2474 case I40E_DMA_CNTX_SIZE_4K:
2475 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2476 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2477 break;
2478 default:
2479 return I40E_ERR_PARAM;
2480 }
2481
2482 /* Validate PE settings passed */
2483 switch (settings->pe_filt_num) {
2484 case I40E_HASH_FILTER_SIZE_1K:
2485 case I40E_HASH_FILTER_SIZE_2K:
2486 case I40E_HASH_FILTER_SIZE_4K:
2487 case I40E_HASH_FILTER_SIZE_8K:
2488 case I40E_HASH_FILTER_SIZE_16K:
2489 case I40E_HASH_FILTER_SIZE_32K:
2490 case I40E_HASH_FILTER_SIZE_64K:
2491 case I40E_HASH_FILTER_SIZE_128K:
2492 case I40E_HASH_FILTER_SIZE_256K:
2493 case I40E_HASH_FILTER_SIZE_512K:
2494 case I40E_HASH_FILTER_SIZE_1M:
2495 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2496 pe_filt_size <<= (u32)settings->pe_filt_num;
2497 break;
2498 default:
2499 return I40E_ERR_PARAM;
2500 }
2501
2502 switch (settings->pe_cntx_num) {
2503 case I40E_DMA_CNTX_SIZE_512:
2504 case I40E_DMA_CNTX_SIZE_1K:
2505 case I40E_DMA_CNTX_SIZE_2K:
2506 case I40E_DMA_CNTX_SIZE_4K:
2507 case I40E_DMA_CNTX_SIZE_8K:
2508 case I40E_DMA_CNTX_SIZE_16K:
2509 case I40E_DMA_CNTX_SIZE_32K:
2510 case I40E_DMA_CNTX_SIZE_64K:
2511 case I40E_DMA_CNTX_SIZE_128K:
2512 case I40E_DMA_CNTX_SIZE_256K:
2513 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2514 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2515 break;
2516 default:
2517 return I40E_ERR_PARAM;
2518 }
2519
2520 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2521 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2522 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2523 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2524 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2525 return I40E_ERR_INVALID_SIZE;
2526
2527 /* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
2528 val = rd32(hw, I40E_GLHMC_PEXFMAX);
2529 pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
2530 >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
2531 if (pe_filt_size + pe_cntx_size > pe_fmax)
2532 return I40E_ERR_INVALID_SIZE;
2533
2534 return 0;
2535}
2536
2537/**
2538 * i40e_set_filter_control
2539 * @hw: pointer to the hardware structure
2540 * @settings: Filter control settings
2541 *
2542 * Set the Queue Filters for PE/FCoE and enable filters required
2543 * for a single PF. It is expected that these settings are programmed
2544 * at the driver initialization time.
2545 **/
2546i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2547 struct i40e_filter_control_settings *settings)
2548{
2549 i40e_status ret = 0;
2550 u32 hash_lut_size = 0;
2551 u32 val;
2552
2553 if (!settings)
2554 return I40E_ERR_PARAM;
2555
2556 /* Validate the input settings */
2557 ret = i40e_validate_filter_settings(hw, settings);
2558 if (ret)
2559 return ret;
2560
2561 /* Read the PF Queue Filter control register */
2562 val = rd32(hw, I40E_PFQF_CTL_0);
2563
2564 /* Program required PE hash buckets for the PF */
2565 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2566 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2567 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2568 /* Program required PE contexts for the PF */
2569 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2570 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2571 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2572
2573 /* Program required FCoE hash buckets for the PF */
2574 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2575 val |= ((u32)settings->fcoe_filt_num <<
2576 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2577 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2578 /* Program required FCoE DDP contexts for the PF */
2579 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2580 val |= ((u32)settings->fcoe_cntx_num <<
2581 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2582 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2583
2584 /* Program Hash LUT size for the PF */
2585 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2586 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2587 hash_lut_size = 1;
2588 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2589 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2590
2591 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2592 if (settings->enable_fdir)
2593 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2594 if (settings->enable_ethtype)
2595 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2596 if (settings->enable_macvlan)
2597 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2598
2599 wr32(hw, I40E_PFQF_CTL_0, val);
2600
2601 return 0;
2602}
afb3ff0d
NP		 2603
2604/**
2605 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2606 * @hw: pointer to the hw struct
2607 * @mac_addr: MAC address to use in the filter
2608 * @ethtype: Ethertype to use in the filter
2609 * @flags: Flags that needs to be applied to the filter
2610 * @vsi_seid: seid of the control VSI
2611 * @queue: VSI queue number to send the packet to
2612 * @is_add: Add control packet filter if True else remove
2613 * @stats: Structure to hold information on control filter counts
2614 * @cmd_details: pointer to command details structure or NULL
2615 *
2616 * This command will Add or Remove control packet filter for a control VSI.
2617 * In return it will update the total number of perfect filter count in
2618 * the stats member.
2619 **/
2620i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
2621 u8 *mac_addr, u16 ethtype, u16 flags,
2622 u16 vsi_seid, u16 queue, bool is_add,
2623 struct i40e_control_filter_stats *stats,
2624 struct i40e_asq_cmd_details *cmd_details)
2625{
2626 struct i40e_aq_desc desc;
2627 struct i40e_aqc_add_remove_control_packet_filter *cmd =
2628 (struct i40e_aqc_add_remove_control_packet_filter *)
2629 &desc.params.raw;
2630 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
2631 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
2632 &desc.params.raw;
2633 i40e_status status;
2634
2635 if (vsi_seid == 0)
2636 return I40E_ERR_PARAM;
2637
2638 if (is_add) {
2639 i40e_fill_default_direct_cmd_desc(&desc,
2640 i40e_aqc_opc_add_control_packet_filter);
2641 cmd->queue = cpu_to_le16(queue);
2642 } else {
2643 i40e_fill_default_direct_cmd_desc(&desc,
2644 i40e_aqc_opc_remove_control_packet_filter);
2645 }
2646
2647 if (mac_addr)
2648 memcpy(cmd->mac, mac_addr, ETH_ALEN);
2649
2650 cmd->etype = cpu_to_le16(ethtype);
2651 cmd->flags = cpu_to_le16(flags);
2652 cmd->seid = cpu_to_le16(vsi_seid);
2653
2654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2655
2656 if (!status && stats) {
2657 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
2658 stats->etype_used = le16_to_cpu(resp->etype_used);
2659 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
2660 stats->etype_free = le16_to_cpu(resp->etype_free);
2661 }
2662
2663 return status;
2664}
2665
d4dfb81a
CS		 2666/**
2667 * i40e_set_pci_config_data - store PCI bus info
2668 * @hw: pointer to hardware structure
2669 * @link_status: the link status word from PCI config space
2670 *
2671 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2672 **/
2673void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2674{
2675 hw->bus.type = i40e_bus_type_pci_express;
2676
2677 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2678 case PCI_EXP_LNKSTA_NLW_X1:
2679 hw->bus.width = i40e_bus_width_pcie_x1;
2680 break;
2681 case PCI_EXP_LNKSTA_NLW_X2:
2682 hw->bus.width = i40e_bus_width_pcie_x2;
2683 break;
2684 case PCI_EXP_LNKSTA_NLW_X4:
2685 hw->bus.width = i40e_bus_width_pcie_x4;
2686 break;
2687 case PCI_EXP_LNKSTA_NLW_X8:
2688 hw->bus.width = i40e_bus_width_pcie_x8;
2689 break;
2690 default:
2691 hw->bus.width = i40e_bus_width_unknown;
2692 break;
2693 }
2694
2695 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2696 case PCI_EXP_LNKSTA_CLS_2_5GB:
2697 hw->bus.speed = i40e_bus_speed_2500;
2698 break;
2699 case PCI_EXP_LNKSTA_CLS_5_0GB:
2700 hw->bus.speed = i40e_bus_speed_5000;
2701 break;
2702 case PCI_EXP_LNKSTA_CLS_8_0GB:
2703 hw->bus.speed = i40e_bus_speed_8000;
2704 break;
2705 default:
2706 hw->bus.speed = i40e_bus_speed_unknown;
2707 break;
2708 }
2709}
Linux kernel - Deliverables
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