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i40e/i40evf: Only offload VLAN tag if enabled
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
67be6eb2 4 * Copyright(c) 2013 - 2016 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e 46 case I40E_DEV_ID_QEMU:
ab60085e
SN		 47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
ab60085e
SN		 49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
5960d33f 52 case I40E_DEV_ID_10G_BASE_T:
bc5166b9 53 case I40E_DEV_ID_10G_BASE_T4:
ae24b409 54 case I40E_DEV_ID_20G_KR2:
48a3b512 55 case I40E_DEV_ID_20G_KR2_A:
56a62fc8
JB		 56 hw->mac.type = I40E_MAC_XL710;
57 break;
35dae51d
ASJ		 58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
87e6c1d7
ASJ		 60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
d6bf58c2 63 case I40E_DEV_ID_SFP_I_X722:
bccf4744 64 case I40E_DEV_ID_QSFP_I_X722:
87e6c1d7
ASJ		 65 hw->mac.type = I40E_MAC_X722;
66 break;
56a62fc8
JB		 67 default:
68 hw->mac.type = I40E_MAC_GENERIC;
69 break;
70 }
71 } else {
72 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
73 }
74
75 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
76 hw->mac.type, status);
77 return status;
78}
79
f1c7e72e
SN		 80/**
81 * i40e_aq_str - convert AQ err code to a string
82 * @hw: pointer to the HW structure
83 * @aq_err: the AQ error code to convert
84 **/
4e68adfe 85const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
f1c7e72e
SN		 86{
87 switch (aq_err) {
88 case I40E_AQ_RC_OK:
89 return "OK";
90 case I40E_AQ_RC_EPERM:
91 return "I40E_AQ_RC_EPERM";
92 case I40E_AQ_RC_ENOENT:
93 return "I40E_AQ_RC_ENOENT";
94 case I40E_AQ_RC_ESRCH:
95 return "I40E_AQ_RC_ESRCH";
96 case I40E_AQ_RC_EINTR:
97 return "I40E_AQ_RC_EINTR";
98 case I40E_AQ_RC_EIO:
99 return "I40E_AQ_RC_EIO";
100 case I40E_AQ_RC_ENXIO:
101 return "I40E_AQ_RC_ENXIO";
102 case I40E_AQ_RC_E2BIG:
103 return "I40E_AQ_RC_E2BIG";
104 case I40E_AQ_RC_EAGAIN:
105 return "I40E_AQ_RC_EAGAIN";
106 case I40E_AQ_RC_ENOMEM:
107 return "I40E_AQ_RC_ENOMEM";
108 case I40E_AQ_RC_EACCES:
109 return "I40E_AQ_RC_EACCES";
110 case I40E_AQ_RC_EFAULT:
111 return "I40E_AQ_RC_EFAULT";
112 case I40E_AQ_RC_EBUSY:
113 return "I40E_AQ_RC_EBUSY";
114 case I40E_AQ_RC_EEXIST:
115 return "I40E_AQ_RC_EEXIST";
116 case I40E_AQ_RC_EINVAL:
117 return "I40E_AQ_RC_EINVAL";
118 case I40E_AQ_RC_ENOTTY:
119 return "I40E_AQ_RC_ENOTTY";
120 case I40E_AQ_RC_ENOSPC:
121 return "I40E_AQ_RC_ENOSPC";
122 case I40E_AQ_RC_ENOSYS:
123 return "I40E_AQ_RC_ENOSYS";
124 case I40E_AQ_RC_ERANGE:
125 return "I40E_AQ_RC_ERANGE";
126 case I40E_AQ_RC_EFLUSHED:
127 return "I40E_AQ_RC_EFLUSHED";
128 case I40E_AQ_RC_BAD_ADDR:
129 return "I40E_AQ_RC_BAD_ADDR";
130 case I40E_AQ_RC_EMODE:
131 return "I40E_AQ_RC_EMODE";
132 case I40E_AQ_RC_EFBIG:
133 return "I40E_AQ_RC_EFBIG";
134 }
135
136 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
137 return hw->err_str;
138}
139
140/**
141 * i40e_stat_str - convert status err code to a string
142 * @hw: pointer to the HW structure
143 * @stat_err: the status error code to convert
144 **/
4e68adfe 145const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
f1c7e72e
SN		 146{
147 switch (stat_err) {
148 case 0:
149 return "OK";
150 case I40E_ERR_NVM:
151 return "I40E_ERR_NVM";
152 case I40E_ERR_NVM_CHECKSUM:
153 return "I40E_ERR_NVM_CHECKSUM";
154 case I40E_ERR_PHY:
155 return "I40E_ERR_PHY";
156 case I40E_ERR_CONFIG:
157 return "I40E_ERR_CONFIG";
158 case I40E_ERR_PARAM:
159 return "I40E_ERR_PARAM";
160 case I40E_ERR_MAC_TYPE:
161 return "I40E_ERR_MAC_TYPE";
162 case I40E_ERR_UNKNOWN_PHY:
163 return "I40E_ERR_UNKNOWN_PHY";
164 case I40E_ERR_LINK_SETUP:
165 return "I40E_ERR_LINK_SETUP";
166 case I40E_ERR_ADAPTER_STOPPED:
167 return "I40E_ERR_ADAPTER_STOPPED";
168 case I40E_ERR_INVALID_MAC_ADDR:
169 return "I40E_ERR_INVALID_MAC_ADDR";
170 case I40E_ERR_DEVICE_NOT_SUPPORTED:
171 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
172 case I40E_ERR_MASTER_REQUESTS_PENDING:
173 return "I40E_ERR_MASTER_REQUESTS_PENDING";
174 case I40E_ERR_INVALID_LINK_SETTINGS:
175 return "I40E_ERR_INVALID_LINK_SETTINGS";
176 case I40E_ERR_AUTONEG_NOT_COMPLETE:
177 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
178 case I40E_ERR_RESET_FAILED:
179 return "I40E_ERR_RESET_FAILED";
180 case I40E_ERR_SWFW_SYNC:
181 return "I40E_ERR_SWFW_SYNC";
182 case I40E_ERR_NO_AVAILABLE_VSI:
183 return "I40E_ERR_NO_AVAILABLE_VSI";
184 case I40E_ERR_NO_MEMORY:
185 return "I40E_ERR_NO_MEMORY";
186 case I40E_ERR_BAD_PTR:
187 return "I40E_ERR_BAD_PTR";
188 case I40E_ERR_RING_FULL:
189 return "I40E_ERR_RING_FULL";
190 case I40E_ERR_INVALID_PD_ID:
191 return "I40E_ERR_INVALID_PD_ID";
192 case I40E_ERR_INVALID_QP_ID:
193 return "I40E_ERR_INVALID_QP_ID";
194 case I40E_ERR_INVALID_CQ_ID:
195 return "I40E_ERR_INVALID_CQ_ID";
196 case I40E_ERR_INVALID_CEQ_ID:
197 return "I40E_ERR_INVALID_CEQ_ID";
198 case I40E_ERR_INVALID_AEQ_ID:
199 return "I40E_ERR_INVALID_AEQ_ID";
200 case I40E_ERR_INVALID_SIZE:
201 return "I40E_ERR_INVALID_SIZE";
202 case I40E_ERR_INVALID_ARP_INDEX:
203 return "I40E_ERR_INVALID_ARP_INDEX";
204 case I40E_ERR_INVALID_FPM_FUNC_ID:
205 return "I40E_ERR_INVALID_FPM_FUNC_ID";
206 case I40E_ERR_QP_INVALID_MSG_SIZE:
207 return "I40E_ERR_QP_INVALID_MSG_SIZE";
208 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
209 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
210 case I40E_ERR_INVALID_FRAG_COUNT:
211 return "I40E_ERR_INVALID_FRAG_COUNT";
212 case I40E_ERR_QUEUE_EMPTY:
213 return "I40E_ERR_QUEUE_EMPTY";
214 case I40E_ERR_INVALID_ALIGNMENT:
215 return "I40E_ERR_INVALID_ALIGNMENT";
216 case I40E_ERR_FLUSHED_QUEUE:
217 return "I40E_ERR_FLUSHED_QUEUE";
218 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
219 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
220 case I40E_ERR_INVALID_IMM_DATA_SIZE:
221 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
222 case I40E_ERR_TIMEOUT:
223 return "I40E_ERR_TIMEOUT";
224 case I40E_ERR_OPCODE_MISMATCH:
225 return "I40E_ERR_OPCODE_MISMATCH";
226 case I40E_ERR_CQP_COMPL_ERROR:
227 return "I40E_ERR_CQP_COMPL_ERROR";
228 case I40E_ERR_INVALID_VF_ID:
229 return "I40E_ERR_INVALID_VF_ID";
230 case I40E_ERR_INVALID_HMCFN_ID:
231 return "I40E_ERR_INVALID_HMCFN_ID";
232 case I40E_ERR_BACKING_PAGE_ERROR:
233 return "I40E_ERR_BACKING_PAGE_ERROR";
234 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
235 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
236 case I40E_ERR_INVALID_PBLE_INDEX:
237 return "I40E_ERR_INVALID_PBLE_INDEX";
238 case I40E_ERR_INVALID_SD_INDEX:
239 return "I40E_ERR_INVALID_SD_INDEX";
240 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
241 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
242 case I40E_ERR_INVALID_SD_TYPE:
243 return "I40E_ERR_INVALID_SD_TYPE";
244 case I40E_ERR_MEMCPY_FAILED:
245 return "I40E_ERR_MEMCPY_FAILED";
246 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
247 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
248 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
249 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
250 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
251 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
252 case I40E_ERR_SRQ_ENABLED:
253 return "I40E_ERR_SRQ_ENABLED";
254 case I40E_ERR_ADMIN_QUEUE_ERROR:
255 return "I40E_ERR_ADMIN_QUEUE_ERROR";
256 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
257 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
258 case I40E_ERR_BUF_TOO_SHORT:
259 return "I40E_ERR_BUF_TOO_SHORT";
260 case I40E_ERR_ADMIN_QUEUE_FULL:
261 return "I40E_ERR_ADMIN_QUEUE_FULL";
262 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
263 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
264 case I40E_ERR_BAD_IWARP_CQE:
265 return "I40E_ERR_BAD_IWARP_CQE";
266 case I40E_ERR_NVM_BLANK_MODE:
267 return "I40E_ERR_NVM_BLANK_MODE";
268 case I40E_ERR_NOT_IMPLEMENTED:
269 return "I40E_ERR_NOT_IMPLEMENTED";
270 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
271 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
272 case I40E_ERR_DIAG_TEST_FAILED:
273 return "I40E_ERR_DIAG_TEST_FAILED";
274 case I40E_ERR_NOT_READY:
275 return "I40E_ERR_NOT_READY";
276 case I40E_NOT_SUPPORTED:
277 return "I40E_NOT_SUPPORTED";
278 case I40E_ERR_FIRMWARE_API_VERSION:
279 return "I40E_ERR_FIRMWARE_API_VERSION";
280 }
281
282 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
283 return hw->err_str;
284}
285
56a62fc8
JB		 286/**
287 * i40e_debug_aq
288 * @hw: debug mask related to admin queue
98d44381
JK		 289 * @mask: debug mask
290 * @desc: pointer to admin queue descriptor
56a62fc8 291 * @buffer: pointer to command buffer
f905dd62 292 * @buf_len: max length of buffer
56a62fc8
JB		 293 *
294 * Dumps debug log about adminq command with descriptor contents.
295 **/
296void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
f905dd62 297 void *buffer, u16 buf_len)
56a62fc8
JB		 298{
299 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
f905dd62 300 u16 len = le16_to_cpu(aq_desc->datalen);
37a2973a
SN		 301 u8 *buf = (u8 *)buffer;
302 u16 i = 0;
56a62fc8
JB		 303
304 if ((!(mask & hw->debug_mask)) || (desc == NULL))
305 return;
306
307 i40e_debug(hw, mask,
308 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
f1abd7db
PSJ		 309 le16_to_cpu(aq_desc->opcode),
310 le16_to_cpu(aq_desc->flags),
311 le16_to_cpu(aq_desc->datalen),
312 le16_to_cpu(aq_desc->retval));
56a62fc8 313 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 314 le32_to_cpu(aq_desc->cookie_high),
315 le32_to_cpu(aq_desc->cookie_low));
56a62fc8 316 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 317 le32_to_cpu(aq_desc->params.internal.param0),
318 le32_to_cpu(aq_desc->params.internal.param1));
56a62fc8 319 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 320 le32_to_cpu(aq_desc->params.external.addr_high),
321 le32_to_cpu(aq_desc->params.external.addr_low));
56a62fc8
JB		 322
323 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
56a62fc8 324 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
f905dd62
SN		 325 if (buf_len < len)
326 len = buf_len;
37a2973a
SN		 327 /* write the full 16-byte chunks */
328 for (i = 0; i < (len - 16); i += 16)
a3524e95 329 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
37a2973a 330 /* write whatever's left over without overrunning the buffer */
a3524e95
AS		 331 if (i < len)
332 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
333 i, len - i, buf + i);
56a62fc8
JB		 334 }
335}
336
e1860d8f
ASJ		 337/**
338 * i40e_check_asq_alive
339 * @hw: pointer to the hw struct
340 *
341 * Returns true if Queue is enabled else false.
342 **/
343bool i40e_check_asq_alive(struct i40e_hw *hw)
344{
8b833b4f
KS		 345 if (hw->aq.asq.len)
346 return !!(rd32(hw, hw->aq.asq.len) &
347 I40E_PF_ATQLEN_ATQENABLE_MASK);
348 else
349 return false;
e1860d8f
ASJ		 350}
351
352/**
353 * i40e_aq_queue_shutdown
354 * @hw: pointer to the hw struct
355 * @unloading: is the driver unloading itself
356 *
357 * Tell the Firmware that we're shutting down the AdminQ and whether
358 * or not the driver is unloading as well.
359 **/
360i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
361 bool unloading)
362{
363 struct i40e_aq_desc desc;
364 struct i40e_aqc_queue_shutdown *cmd =
365 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
366 i40e_status status;
367
368 i40e_fill_default_direct_cmd_desc(&desc,
369 i40e_aqc_opc_queue_shutdown);
370
371 if (unloading)
372 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
373 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
374
375 return status;
376}
377
e50c8d6d
ASJ		 378/**
379 * i40e_aq_get_set_rss_lut
380 * @hw: pointer to the hardware structure
381 * @vsi_id: vsi fw index
382 * @pf_lut: for PF table set true, for VSI table set false
383 * @lut: pointer to the lut buffer provided by the caller
384 * @lut_size: size of the lut buffer
385 * @set: set true to set the table, false to get the table
386 *
387 * Internal function to get or set RSS look up table
388 **/
389static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
390 u16 vsi_id, bool pf_lut,
391 u8 *lut, u16 lut_size,
392 bool set)
393{
394 i40e_status status;
395 struct i40e_aq_desc desc;
396 struct i40e_aqc_get_set_rss_lut *cmd_resp =
397 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
398
399 if (set)
400 i40e_fill_default_direct_cmd_desc(&desc,
401 i40e_aqc_opc_set_rss_lut);
402 else
403 i40e_fill_default_direct_cmd_desc(&desc,
404 i40e_aqc_opc_get_rss_lut);
405
406 /* Indirect command */
407 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
408 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
409
410 cmd_resp->vsi_id =
411 cpu_to_le16((u16)((vsi_id <<
412 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
413 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
414 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
415
416 if (pf_lut)
417 cmd_resp->flags |= cpu_to_le16((u16)
418 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
419 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
421 else
422 cmd_resp->flags |= cpu_to_le16((u16)
423 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
424 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
425 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
426
e50c8d6d
ASJ		 427 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
428
429 return status;
430}
431
432/**
433 * i40e_aq_get_rss_lut
434 * @hw: pointer to the hardware structure
435 * @vsi_id: vsi fw index
436 * @pf_lut: for PF table set true, for VSI table set false
437 * @lut: pointer to the lut buffer provided by the caller
438 * @lut_size: size of the lut buffer
439 *
440 * get the RSS lookup table, PF or VSI type
441 **/
442i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
443 bool pf_lut, u8 *lut, u16 lut_size)
444{
445 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
446 false);
447}
448
449/**
450 * i40e_aq_set_rss_lut
451 * @hw: pointer to the hardware structure
452 * @vsi_id: vsi fw index
453 * @pf_lut: for PF table set true, for VSI table set false
454 * @lut: pointer to the lut buffer provided by the caller
455 * @lut_size: size of the lut buffer
456 *
457 * set the RSS lookup table, PF or VSI type
458 **/
459i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
460 bool pf_lut, u8 *lut, u16 lut_size)
461{
462 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
463}
464
465/**
466 * i40e_aq_get_set_rss_key
467 * @hw: pointer to the hw struct
468 * @vsi_id: vsi fw index
469 * @key: pointer to key info struct
470 * @set: set true to set the key, false to get the key
471 *
472 * get the RSS key per VSI
473 **/
474static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
475 u16 vsi_id,
476 struct i40e_aqc_get_set_rss_key_data *key,
477 bool set)
478{
479 i40e_status status;
480 struct i40e_aq_desc desc;
481 struct i40e_aqc_get_set_rss_key *cmd_resp =
482 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
483 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
484
485 if (set)
486 i40e_fill_default_direct_cmd_desc(&desc,
487 i40e_aqc_opc_set_rss_key);
488 else
489 i40e_fill_default_direct_cmd_desc(&desc,
490 i40e_aqc_opc_get_rss_key);
491
492 /* Indirect command */
493 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
494 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
495
496 cmd_resp->vsi_id =
497 cpu_to_le16((u16)((vsi_id <<
498 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
499 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
500 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
e50c8d6d
ASJ		 501
502 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
503
504 return status;
505}
506
507/**
508 * i40e_aq_get_rss_key
509 * @hw: pointer to the hw struct
510 * @vsi_id: vsi fw index
511 * @key: pointer to key info struct
512 *
513 **/
514i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
515 u16 vsi_id,
516 struct i40e_aqc_get_set_rss_key_data *key)
517{
518 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
519}
520
521/**
522 * i40e_aq_set_rss_key
523 * @hw: pointer to the hw struct
524 * @vsi_id: vsi fw index
525 * @key: pointer to key info struct
526 *
527 * set the RSS key per VSI
528 **/
529i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
530 u16 vsi_id,
531 struct i40e_aqc_get_set_rss_key_data *key)
532{
533 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
534}
535
206812b5
JB		 536/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
537 * hardware to a bit-field that can be used by SW to more easily determine the
538 * packet type.
539 *
540 * Macros are used to shorten the table lines and make this table human
541 * readable.
542 *
543 * We store the PTYPE in the top byte of the bit field - this is just so that
544 * we can check that the table doesn't have a row missing, as the index into
545 * the table should be the PTYPE.
546 *
547 * Typical work flow:
548 *
549 * IF NOT i40e_ptype_lookup[ptype].known
550 * THEN
551 * Packet is unknown
552 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
553 * Use the rest of the fields to look at the tunnels, inner protocols, etc
554 * ELSE
555 * Use the enum i40e_rx_l2_ptype to decode the packet type
556 * ENDIF
557 */
558
559/* macro to make the table lines short */
560#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
561 { PTYPE, \
562 1, \
563 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
564 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
565 I40E_RX_PTYPE_##OUTER_FRAG, \
566 I40E_RX_PTYPE_TUNNEL_##T, \
567 I40E_RX_PTYPE_TUNNEL_END_##TE, \
568 I40E_RX_PTYPE_##TEF, \
569 I40E_RX_PTYPE_INNER_PROT_##I, \
570 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
571
572#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
573 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
574
575/* shorter macros makes the table fit but are terse */
576#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
577#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
578#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
579
580/* Lookup table mapping the HW PTYPE to the bit field for decoding */
581struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
582 /* L2 Packet types */
583 I40E_PTT_UNUSED_ENTRY(0),
584 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
586 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
587 I40E_PTT_UNUSED_ENTRY(4),
588 I40E_PTT_UNUSED_ENTRY(5),
589 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
590 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
591 I40E_PTT_UNUSED_ENTRY(8),
592 I40E_PTT_UNUSED_ENTRY(9),
593 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
594 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
595 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
605
606 /* Non Tunneled IPv4 */
607 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
608 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
609 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
610 I40E_PTT_UNUSED_ENTRY(25),
611 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
612 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
613 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
614
615 /* IPv4 --> IPv4 */
616 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
617 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
618 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
619 I40E_PTT_UNUSED_ENTRY(32),
620 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
621 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
622 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
623
624 /* IPv4 --> IPv6 */
625 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
626 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
627 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
628 I40E_PTT_UNUSED_ENTRY(39),
629 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
630 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
631 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
632
633 /* IPv4 --> GRE/NAT */
634 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
635
636 /* IPv4 --> GRE/NAT --> IPv4 */
637 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
638 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
639 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
640 I40E_PTT_UNUSED_ENTRY(47),
641 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
642 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
643 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
644
645 /* IPv4 --> GRE/NAT --> IPv6 */
646 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
647 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
648 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
649 I40E_PTT_UNUSED_ENTRY(54),
650 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
651 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
652 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
653
654 /* IPv4 --> GRE/NAT --> MAC */
655 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
656
657 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
658 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
659 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
660 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
661 I40E_PTT_UNUSED_ENTRY(62),
662 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
663 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
664 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
665
666 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
667 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
668 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
669 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
670 I40E_PTT_UNUSED_ENTRY(69),
671 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
672 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
673 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
674
675 /* IPv4 --> GRE/NAT --> MAC/VLAN */
676 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
677
678 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
679 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
680 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
681 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
682 I40E_PTT_UNUSED_ENTRY(77),
683 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
684 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
685 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
686
687 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
688 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
689 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
690 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
691 I40E_PTT_UNUSED_ENTRY(84),
692 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
693 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
694 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
695
696 /* Non Tunneled IPv6 */
697 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
698 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
699 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
700 I40E_PTT_UNUSED_ENTRY(91),
701 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
702 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
703 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
704
705 /* IPv6 --> IPv4 */
706 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
707 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
708 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
709 I40E_PTT_UNUSED_ENTRY(98),
710 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
711 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
712 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
713
714 /* IPv6 --> IPv6 */
715 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
716 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
717 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
718 I40E_PTT_UNUSED_ENTRY(105),
719 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
720 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
721 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
722
723 /* IPv6 --> GRE/NAT */
724 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
725
726 /* IPv6 --> GRE/NAT -> IPv4 */
727 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
728 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
729 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
730 I40E_PTT_UNUSED_ENTRY(113),
731 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
732 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
733 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
734
735 /* IPv6 --> GRE/NAT -> IPv6 */
736 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
737 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
738 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
739 I40E_PTT_UNUSED_ENTRY(120),
740 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
741 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
742 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
743
744 /* IPv6 --> GRE/NAT -> MAC */
745 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
746
747 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
748 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
749 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
750 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
751 I40E_PTT_UNUSED_ENTRY(128),
752 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
753 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
754 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
755
756 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
757 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
758 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
759 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
760 I40E_PTT_UNUSED_ENTRY(135),
761 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
762 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
763 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
764
765 /* IPv6 --> GRE/NAT -> MAC/VLAN */
766 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
767
768 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
769 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
770 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
771 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
772 I40E_PTT_UNUSED_ENTRY(143),
773 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
774 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
775 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
776
777 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
778 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
779 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
780 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
781 I40E_PTT_UNUSED_ENTRY(150),
782 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
783 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
784 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
785
786 /* unused entries */
787 I40E_PTT_UNUSED_ENTRY(154),
788 I40E_PTT_UNUSED_ENTRY(155),
789 I40E_PTT_UNUSED_ENTRY(156),
790 I40E_PTT_UNUSED_ENTRY(157),
791 I40E_PTT_UNUSED_ENTRY(158),
792 I40E_PTT_UNUSED_ENTRY(159),
793
794 I40E_PTT_UNUSED_ENTRY(160),
795 I40E_PTT_UNUSED_ENTRY(161),
796 I40E_PTT_UNUSED_ENTRY(162),
797 I40E_PTT_UNUSED_ENTRY(163),
798 I40E_PTT_UNUSED_ENTRY(164),
799 I40E_PTT_UNUSED_ENTRY(165),
800 I40E_PTT_UNUSED_ENTRY(166),
801 I40E_PTT_UNUSED_ENTRY(167),
802 I40E_PTT_UNUSED_ENTRY(168),
803 I40E_PTT_UNUSED_ENTRY(169),
804
805 I40E_PTT_UNUSED_ENTRY(170),
806 I40E_PTT_UNUSED_ENTRY(171),
807 I40E_PTT_UNUSED_ENTRY(172),
808 I40E_PTT_UNUSED_ENTRY(173),
809 I40E_PTT_UNUSED_ENTRY(174),
810 I40E_PTT_UNUSED_ENTRY(175),
811 I40E_PTT_UNUSED_ENTRY(176),
812 I40E_PTT_UNUSED_ENTRY(177),
813 I40E_PTT_UNUSED_ENTRY(178),
814 I40E_PTT_UNUSED_ENTRY(179),
815
816 I40E_PTT_UNUSED_ENTRY(180),
817 I40E_PTT_UNUSED_ENTRY(181),
818 I40E_PTT_UNUSED_ENTRY(182),
819 I40E_PTT_UNUSED_ENTRY(183),
820 I40E_PTT_UNUSED_ENTRY(184),
821 I40E_PTT_UNUSED_ENTRY(185),
822 I40E_PTT_UNUSED_ENTRY(186),
823 I40E_PTT_UNUSED_ENTRY(187),
824 I40E_PTT_UNUSED_ENTRY(188),
825 I40E_PTT_UNUSED_ENTRY(189),
826
827 I40E_PTT_UNUSED_ENTRY(190),
828 I40E_PTT_UNUSED_ENTRY(191),
829 I40E_PTT_UNUSED_ENTRY(192),
830 I40E_PTT_UNUSED_ENTRY(193),
831 I40E_PTT_UNUSED_ENTRY(194),
832 I40E_PTT_UNUSED_ENTRY(195),
833 I40E_PTT_UNUSED_ENTRY(196),
834 I40E_PTT_UNUSED_ENTRY(197),
835 I40E_PTT_UNUSED_ENTRY(198),
836 I40E_PTT_UNUSED_ENTRY(199),
837
838 I40E_PTT_UNUSED_ENTRY(200),
839 I40E_PTT_UNUSED_ENTRY(201),
840 I40E_PTT_UNUSED_ENTRY(202),
841 I40E_PTT_UNUSED_ENTRY(203),
842 I40E_PTT_UNUSED_ENTRY(204),
843 I40E_PTT_UNUSED_ENTRY(205),
844 I40E_PTT_UNUSED_ENTRY(206),
845 I40E_PTT_UNUSED_ENTRY(207),
846 I40E_PTT_UNUSED_ENTRY(208),
847 I40E_PTT_UNUSED_ENTRY(209),
848
849 I40E_PTT_UNUSED_ENTRY(210),
850 I40E_PTT_UNUSED_ENTRY(211),
851 I40E_PTT_UNUSED_ENTRY(212),
852 I40E_PTT_UNUSED_ENTRY(213),
853 I40E_PTT_UNUSED_ENTRY(214),
854 I40E_PTT_UNUSED_ENTRY(215),
855 I40E_PTT_UNUSED_ENTRY(216),
856 I40E_PTT_UNUSED_ENTRY(217),
857 I40E_PTT_UNUSED_ENTRY(218),
858 I40E_PTT_UNUSED_ENTRY(219),
859
860 I40E_PTT_UNUSED_ENTRY(220),
861 I40E_PTT_UNUSED_ENTRY(221),
862 I40E_PTT_UNUSED_ENTRY(222),
863 I40E_PTT_UNUSED_ENTRY(223),
864 I40E_PTT_UNUSED_ENTRY(224),
865 I40E_PTT_UNUSED_ENTRY(225),
866 I40E_PTT_UNUSED_ENTRY(226),
867 I40E_PTT_UNUSED_ENTRY(227),
868 I40E_PTT_UNUSED_ENTRY(228),
869 I40E_PTT_UNUSED_ENTRY(229),
870
871 I40E_PTT_UNUSED_ENTRY(230),
872 I40E_PTT_UNUSED_ENTRY(231),
873 I40E_PTT_UNUSED_ENTRY(232),
874 I40E_PTT_UNUSED_ENTRY(233),
875 I40E_PTT_UNUSED_ENTRY(234),
876 I40E_PTT_UNUSED_ENTRY(235),
877 I40E_PTT_UNUSED_ENTRY(236),
878 I40E_PTT_UNUSED_ENTRY(237),
879 I40E_PTT_UNUSED_ENTRY(238),
880 I40E_PTT_UNUSED_ENTRY(239),
881
882 I40E_PTT_UNUSED_ENTRY(240),
883 I40E_PTT_UNUSED_ENTRY(241),
884 I40E_PTT_UNUSED_ENTRY(242),
885 I40E_PTT_UNUSED_ENTRY(243),
886 I40E_PTT_UNUSED_ENTRY(244),
887 I40E_PTT_UNUSED_ENTRY(245),
888 I40E_PTT_UNUSED_ENTRY(246),
889 I40E_PTT_UNUSED_ENTRY(247),
890 I40E_PTT_UNUSED_ENTRY(248),
891 I40E_PTT_UNUSED_ENTRY(249),
892
893 I40E_PTT_UNUSED_ENTRY(250),
894 I40E_PTT_UNUSED_ENTRY(251),
895 I40E_PTT_UNUSED_ENTRY(252),
896 I40E_PTT_UNUSED_ENTRY(253),
897 I40E_PTT_UNUSED_ENTRY(254),
898 I40E_PTT_UNUSED_ENTRY(255)
899};
900
56a62fc8
JB		 901/**
902 * i40e_init_shared_code - Initialize the shared code
903 * @hw: pointer to hardware structure
904 *
905 * This assigns the MAC type and PHY code and inits the NVM.
906 * Does not touch the hardware. This function must be called prior to any
907 * other function in the shared code. The i40e_hw structure should be
908 * memset to 0 prior to calling this function. The following fields in
909 * hw structure should be filled in prior to calling this function:
910 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
911 * subsystem_vendor_id, and revision_id
912 **/
913i40e_status i40e_init_shared_code(struct i40e_hw *hw)
914{
915 i40e_status status = 0;
5fb11d76 916 u32 port, ari, func_rid;
56a62fc8 917
56a62fc8
JB		 918 i40e_set_mac_type(hw);
919
920 switch (hw->mac.type) {
921 case I40E_MAC_XL710:
87e6c1d7 922 case I40E_MAC_X722:
56a62fc8
JB		 923 break;
924 default:
925 return I40E_ERR_DEVICE_NOT_SUPPORTED;
56a62fc8
JB		 926 }
927
af89d26c
SN		 928 hw->phy.get_link_info = true;
929
5fb11d76
SN		 930 /* Determine port number and PF number*/
931 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
932 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
933 hw->port = (u8)port;
934 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
935 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
936 func_rid = rd32(hw, I40E_PF_FUNC_RID);
937 if (ari)
938 hw->pf_id = (u8)(func_rid & 0xff);
5f9116ac 939 else
5fb11d76 940 hw->pf_id = (u8)(func_rid & 0x7);
5f9116ac 941
07f89be8
AS		 942 if (hw->mac.type == I40E_MAC_X722)
943 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
944
56a62fc8
JB		 945 status = i40e_init_nvm(hw);
946 return status;
947}
948
949/**
950 * i40e_aq_mac_address_read - Retrieve the MAC addresses
951 * @hw: pointer to the hw struct
952 * @flags: a return indicator of what addresses were added to the addr store
953 * @addrs: the requestor's mac addr store
954 * @cmd_details: pointer to command details structure or NULL
955 **/
956static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
957 u16 *flags,
958 struct i40e_aqc_mac_address_read_data *addrs,
959 struct i40e_asq_cmd_details *cmd_details)
960{
961 struct i40e_aq_desc desc;
962 struct i40e_aqc_mac_address_read *cmd_data =
963 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
964 i40e_status status;
965
966 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
967 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
968
969 status = i40e_asq_send_command(hw, &desc, addrs,
970 sizeof(*addrs), cmd_details);
971 *flags = le16_to_cpu(cmd_data->command_flags);
972
973 return status;
974}
975
976/**
977 * i40e_aq_mac_address_write - Change the MAC addresses
978 * @hw: pointer to the hw struct
979 * @flags: indicates which MAC to be written
980 * @mac_addr: address to write
981 * @cmd_details: pointer to command details structure or NULL
982 **/
983i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
984 u16 flags, u8 *mac_addr,
985 struct i40e_asq_cmd_details *cmd_details)
986{
987 struct i40e_aq_desc desc;
988 struct i40e_aqc_mac_address_write *cmd_data =
989 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
990 i40e_status status;
991
992 i40e_fill_default_direct_cmd_desc(&desc,
993 i40e_aqc_opc_mac_address_write);
994 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 995 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
996 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
997 ((u32)mac_addr[3] << 16) |
998 ((u32)mac_addr[4] << 8) |
999 mac_addr[5]);
56a62fc8
JB		 1000
1001 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1002
1003 return status;
1004}
1005
1006/**
1007 * i40e_get_mac_addr - get MAC address
1008 * @hw: pointer to the HW structure
1009 * @mac_addr: pointer to MAC address
1010 *
1011 * Reads the adapter's MAC address from register
1012 **/
1013i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1014{
1015 struct i40e_aqc_mac_address_read_data addrs;
1016 i40e_status status;
1017 u16 flags = 0;
1018
1019 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1020
1021 if (flags & I40E_AQC_LAN_ADDR_VALID)
6995b36c 1022 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
56a62fc8
JB		 1023
1024 return status;
1025}
1026
1f224ad2
NP		 1027/**
1028 * i40e_get_port_mac_addr - get Port MAC address
1029 * @hw: pointer to the HW structure
1030 * @mac_addr: pointer to Port MAC address
1031 *
1032 * Reads the adapter's Port MAC address
1033 **/
1034i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1035{
1036 struct i40e_aqc_mac_address_read_data addrs;
1037 i40e_status status;
1038 u16 flags = 0;
1039
1040 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1041 if (status)
1042 return status;
1043
1044 if (flags & I40E_AQC_PORT_ADDR_VALID)
6995b36c 1045 ether_addr_copy(mac_addr, addrs.port_mac);
1f224ad2
NP		 1046 else
1047 status = I40E_ERR_INVALID_MAC_ADDR;
1048
1049 return status;
1050}
1051
351499ab
MJ		 1052/**
1053 * i40e_pre_tx_queue_cfg - pre tx queue configure
1054 * @hw: pointer to the HW structure
b40c82e6 1055 * @queue: target PF queue index
351499ab
MJ		 1056 * @enable: state change request
1057 *
1058 * Handles hw requirement to indicate intention to enable
1059 * or disable target queue.
1060 **/
1061void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1062{
dfb699f9 1063 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 1064 u32 reg_block = 0;
dfb699f9 1065 u32 reg_val;
351499ab 1066
24a768cf 1067 if (abs_queue_idx >= 128) {
351499ab 1068 reg_block = abs_queue_idx / 128;
24a768cf
CP		 1069 abs_queue_idx %= 128;
1070 }
351499ab
MJ		 1071
1072 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1073 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1074 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1075
1076 if (enable)
1077 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1078 else
1079 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1080
1081 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1082}
38e00438
VD		 1083#ifdef I40E_FCOE
1084
1085/**
1086 * i40e_get_san_mac_addr - get SAN MAC address
1087 * @hw: pointer to the HW structure
1088 * @mac_addr: pointer to SAN MAC address
1089 *
1090 * Reads the adapter's SAN MAC address from NVM
1091 **/
1092i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1093{
1094 struct i40e_aqc_mac_address_read_data addrs;
1095 i40e_status status;
1096 u16 flags = 0;
1097
1098 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1099 if (status)
1100 return status;
1101
1102 if (flags & I40E_AQC_SAN_ADDR_VALID)
6995b36c 1103 ether_addr_copy(mac_addr, addrs.pf_san_mac);
38e00438
VD		 1104 else
1105 status = I40E_ERR_INVALID_MAC_ADDR;
1106
1107 return status;
1108}
1109#endif
351499ab 1110
18f680c6
KK		 1111/**
1112 * i40e_read_pba_string - Reads part number string from EEPROM
1113 * @hw: pointer to hardware structure
1114 * @pba_num: stores the part number string from the EEPROM
1115 * @pba_num_size: part number string buffer length
1116 *
1117 * Reads the part number string from the EEPROM.
1118 **/
1119i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1120 u32 pba_num_size)
1121{
1122 i40e_status status = 0;
1123 u16 pba_word = 0;
1124 u16 pba_size = 0;
1125 u16 pba_ptr = 0;
1126 u16 i = 0;
1127
1128 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1129 if (status || (pba_word != 0xFAFA)) {
1130 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1131 return status;
1132 }
1133
1134 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1135 if (status) {
1136 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1137 return status;
1138 }
1139
1140 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1141 if (status) {
1142 hw_dbg(hw, "Failed to read PBA Block size.\n");
1143 return status;
1144 }
1145
1146 /* Subtract one to get PBA word count (PBA Size word is included in
1147 * total size)
1148 */
1149 pba_size--;
1150 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1151 hw_dbg(hw, "Buffer to small for PBA data.\n");
1152 return I40E_ERR_PARAM;
1153 }
1154
1155 for (i = 0; i < pba_size; i++) {
1156 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1157 if (status) {
1158 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1159 return status;
1160 }
1161
1162 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1163 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1164 }
1165 pba_num[(pba_size * 2)] = '\0';
1166
1167 return status;
1168}
1169
be405eb0
JB		 1170/**
1171 * i40e_get_media_type - Gets media type
1172 * @hw: pointer to the hardware structure
1173 **/
1174static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1175{
1176 enum i40e_media_type media;
1177
1178 switch (hw->phy.link_info.phy_type) {
1179 case I40E_PHY_TYPE_10GBASE_SR:
1180 case I40E_PHY_TYPE_10GBASE_LR:
124ed15b
CS		 1181 case I40E_PHY_TYPE_1000BASE_SX:
1182 case I40E_PHY_TYPE_1000BASE_LX:
be405eb0
JB		 1183 case I40E_PHY_TYPE_40GBASE_SR4:
1184 case I40E_PHY_TYPE_40GBASE_LR4:
1185 media = I40E_MEDIA_TYPE_FIBER;
1186 break;
1187 case I40E_PHY_TYPE_100BASE_TX:
1188 case I40E_PHY_TYPE_1000BASE_T:
1189 case I40E_PHY_TYPE_10GBASE_T:
1190 media = I40E_MEDIA_TYPE_BASET;
1191 break;
1192 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1193 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1194 case I40E_PHY_TYPE_10GBASE_CR1:
1195 case I40E_PHY_TYPE_40GBASE_CR4:
1196 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
180204c7
CS		 1197 case I40E_PHY_TYPE_40GBASE_AOC:
1198 case I40E_PHY_TYPE_10GBASE_AOC:
be405eb0
JB		 1199 media = I40E_MEDIA_TYPE_DA;
1200 break;
1201 case I40E_PHY_TYPE_1000BASE_KX:
1202 case I40E_PHY_TYPE_10GBASE_KX4:
1203 case I40E_PHY_TYPE_10GBASE_KR:
1204 case I40E_PHY_TYPE_40GBASE_KR4:
ae24b409 1205 case I40E_PHY_TYPE_20GBASE_KR2:
be405eb0
JB		 1206 media = I40E_MEDIA_TYPE_BACKPLANE;
1207 break;
1208 case I40E_PHY_TYPE_SGMII:
1209 case I40E_PHY_TYPE_XAUI:
1210 case I40E_PHY_TYPE_XFI:
1211 case I40E_PHY_TYPE_XLAUI:
1212 case I40E_PHY_TYPE_XLPPI:
1213 default:
1214 media = I40E_MEDIA_TYPE_UNKNOWN;
1215 break;
1216 }
1217
1218 return media;
1219}
1220
7134f9ce 1221#define I40E_PF_RESET_WAIT_COUNT_A0 200
8af580df 1222#define I40E_PF_RESET_WAIT_COUNT 200
56a62fc8
JB		 1223/**
1224 * i40e_pf_reset - Reset the PF
1225 * @hw: pointer to the hardware structure
1226 *
1227 * Assuming someone else has triggered a global reset,
1228 * assure the global reset is complete and then reset the PF
1229 **/
1230i40e_status i40e_pf_reset(struct i40e_hw *hw)
1231{
7134f9ce 1232 u32 cnt = 0;
42794bd8 1233 u32 cnt1 = 0;
56a62fc8
JB		 1234 u32 reg = 0;
1235 u32 grst_del;
1236
1237 /* Poll for Global Reset steady state in case of recent GRST.
1238 * The grst delay value is in 100ms units, and we'll wait a
1239 * couple counts longer to be sure we don't just miss the end.
1240 */
de78fc5a
SN		 1241 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1242 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1243 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
4d7cec07
KS		 1244
1245 /* It can take upto 15 secs for GRST steady state.
1246 * Bump it to 16 secs max to be safe.
1247 */
1248 grst_del = grst_del * 20;
1249
1250 for (cnt = 0; cnt < grst_del; cnt++) {
56a62fc8
JB		 1251 reg = rd32(hw, I40E_GLGEN_RSTAT);
1252 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1253 break;
1254 msleep(100);
1255 }
1256 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1257 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 1258 return I40E_ERR_RESET_FAILED;
1259 }
1260
1261 /* Now Wait for the FW to be ready */
1262 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1263 reg = rd32(hw, I40E_GLNVM_ULD);
1264 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1265 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1266 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1267 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1268 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1269 break;
1270 }
1271 usleep_range(10000, 20000);
1272 }
1273 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1274 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1275 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1276 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 1277 return I40E_ERR_RESET_FAILED;
1278 }
1279
56a62fc8
JB		 1280 /* If there was a Global Reset in progress when we got here,
1281 * we don't need to do the PF Reset
1282 */
7134f9ce
JB		 1283 if (!cnt) {
1284 if (hw->revision_id == 0)
1285 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1286 else
1287 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 1288 reg = rd32(hw, I40E_PFGEN_CTRL);
1289 wr32(hw, I40E_PFGEN_CTRL,
1290 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 1291 for (; cnt; cnt--) {
56a62fc8
JB		 1292 reg = rd32(hw, I40E_PFGEN_CTRL);
1293 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1294 break;
1295 usleep_range(1000, 2000);
1296 }
1297 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1298 hw_dbg(hw, "PF reset polling failed to complete.\n");
1299 return I40E_ERR_RESET_FAILED;
1300 }
1301 }
1302
1303 i40e_clear_pxe_mode(hw);
922680b9 1304
56a62fc8
JB		 1305 return 0;
1306}
1307
838d41d9
SN		 1308/**
1309 * i40e_clear_hw - clear out any left over hw state
1310 * @hw: pointer to the hw struct
1311 *
1312 * Clear queues and interrupts, typically called at init time,
1313 * but after the capabilities have been found so we know how many
1314 * queues and msix vectors have been allocated.
1315 **/
1316void i40e_clear_hw(struct i40e_hw *hw)
1317{
1318 u32 num_queues, base_queue;
1319 u32 num_pf_int;
1320 u32 num_vf_int;
1321 u32 num_vfs;
1322 u32 i, j;
1323 u32 val;
1324 u32 eol = 0x7ff;
1325
b40c82e6 1326 /* get number of interrupts, queues, and VFs */
838d41d9
SN		 1327 val = rd32(hw, I40E_GLPCI_CNF2);
1328 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1329 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1330 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1331 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1332
272cdaf2 1333 val = rd32(hw, I40E_PFLAN_QALLOC);
838d41d9
SN		 1334 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1335 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1336 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1337 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1338 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1339 num_queues = (j - base_queue) + 1;
1340 else
1341 num_queues = 0;
1342
1343 val = rd32(hw, I40E_PF_VT_PFALLOC);
1344 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1345 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1346 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1347 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1348 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1349 num_vfs = (j - i) + 1;
1350 else
1351 num_vfs = 0;
1352
1353 /* stop all the interrupts */
1354 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1355 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1356 for (i = 0; i < num_pf_int - 2; i++)
1357 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1358
1359 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1360 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1361 wr32(hw, I40E_PFINT_LNKLST0, val);
1362 for (i = 0; i < num_pf_int - 2; i++)
1363 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1364 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1365 for (i = 0; i < num_vfs; i++)
1366 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1367 for (i = 0; i < num_vf_int - 2; i++)
1368 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1369
1370 /* warn the HW of the coming Tx disables */
1371 for (i = 0; i < num_queues; i++) {
1372 u32 abs_queue_idx = base_queue + i;
1373 u32 reg_block = 0;
1374
1375 if (abs_queue_idx >= 128) {
1376 reg_block = abs_queue_idx / 128;
1377 abs_queue_idx %= 128;
1378 }
1379
1380 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1381 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1382 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1383 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1384
1385 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1386 }
1387 udelay(400);
1388
1389 /* stop all the queues */
1390 for (i = 0; i < num_queues; i++) {
1391 wr32(hw, I40E_QINT_TQCTL(i), 0);
1392 wr32(hw, I40E_QTX_ENA(i), 0);
1393 wr32(hw, I40E_QINT_RQCTL(i), 0);
1394 wr32(hw, I40E_QRX_ENA(i), 0);
1395 }
1396
1397 /* short wait for all queue disables to settle */
1398 udelay(50);
1399}
1400
56a62fc8
JB		 1401/**
1402 * i40e_clear_pxe_mode - clear pxe operations mode
1403 * @hw: pointer to the hw struct
1404 *
1405 * Make sure all PXE mode settings are cleared, including things
1406 * like descriptor fetch/write-back mode.
1407 **/
1408void i40e_clear_pxe_mode(struct i40e_hw *hw)
1409{
1410 u32 reg;
1411
c9b9b0ae
SN		 1412 if (i40e_check_asq_alive(hw))
1413 i40e_aq_clear_pxe_mode(hw, NULL);
1414
56a62fc8
JB		 1415 /* Clear single descriptor fetch/write-back mode */
1416 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 1417
1418 if (hw->revision_id == 0) {
1419 /* As a work around clear PXE_MODE instead of setting it */
1420 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1421 } else {
1422 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1423 }
56a62fc8
JB		 1424}
1425
0556a9e3
JB		 1426/**
1427 * i40e_led_is_mine - helper to find matching led
1428 * @hw: pointer to the hw struct
1429 * @idx: index into GPIO registers
1430 *
1431 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1432 */
1433static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1434{
1435 u32 gpio_val = 0;
1436 u32 port;
1437
1438 if (!hw->func_caps.led[idx])
1439 return 0;
1440
1441 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1442 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1443 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1444
1445 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1446 * if it is not our port then ignore
1447 */
1448 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1449 (port != hw->port))
1450 return 0;
1451
1452 return gpio_val;
1453}
1454
b84d5cd8
MJ		 1455#define I40E_COMBINED_ACTIVITY 0xA
1456#define I40E_FILTER_ACTIVITY 0xE
0556a9e3 1457#define I40E_LINK_ACTIVITY 0xC
b84d5cd8
MJ		 1458#define I40E_MAC_ACTIVITY 0xD
1459#define I40E_LED0 22
0556a9e3 1460
56a62fc8
JB		 1461/**
1462 * i40e_led_get - return current on/off mode
1463 * @hw: pointer to the hw struct
1464 *
1465 * The value returned is the 'mode' field as defined in the
1466 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1467 * values are variations of possible behaviors relating to
1468 * blink, link, and wire.
1469 **/
1470u32 i40e_led_get(struct i40e_hw *hw)
1471{
b84d5cd8 1472 u32 current_mode = 0;
56a62fc8 1473 u32 mode = 0;
56a62fc8
JB		 1474 int i;
1475
0556a9e3
JB		 1476 /* as per the documentation GPIO 22-29 are the LED
1477 * GPIO pins named LED0..LED7
1478 */
1479 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1480 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1481
0556a9e3 1482 if (!gpio_val)
56a62fc8
JB		 1483 continue;
1484
b84d5cd8
MJ		 1485 /* ignore gpio LED src mode entries related to the activity
1486 * LEDs
1487 */
1488 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1489 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1490 switch (current_mode) {
1491 case I40E_COMBINED_ACTIVITY:
1492 case I40E_FILTER_ACTIVITY:
1493 case I40E_MAC_ACTIVITY:
1494 continue;
1495 default:
1496 break;
1497 }
1498
0556a9e3
JB		 1499 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1500 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 1501 break;
1502 }
1503
1504 return mode;
1505}
1506
1507/**
1508 * i40e_led_set - set new on/off mode
1509 * @hw: pointer to the hw struct
0556a9e3
JB		 1510 * @mode: 0=off, 0xf=on (else see manual for mode details)
1511 * @blink: true if the LED should blink when on, false if steady
1512 *
1513 * if this function is used to turn on the blink it should
1514 * be used to disable the blink when restoring the original state.
56a62fc8 1515 **/
0556a9e3 1516void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1517{
b84d5cd8 1518 u32 current_mode = 0;
56a62fc8
JB		 1519 int i;
1520
0556a9e3
JB		 1521 if (mode & 0xfffffff0)
1522 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1523
0556a9e3
JB		 1524 /* as per the documentation GPIO 22-29 are the LED
1525 * GPIO pins named LED0..LED7
1526 */
1527 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1528 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1529
0556a9e3 1530 if (!gpio_val)
56a62fc8
JB		 1531 continue;
1532
b84d5cd8
MJ		 1533 /* ignore gpio LED src mode entries related to the activity
1534 * LEDs
1535 */
1536 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1537 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1538 switch (current_mode) {
1539 case I40E_COMBINED_ACTIVITY:
1540 case I40E_FILTER_ACTIVITY:
1541 case I40E_MAC_ACTIVITY:
1542 continue;
1543 default:
1544 break;
1545 }
1546
56a62fc8 1547 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1548 /* this & is a bit of paranoia, but serves as a range check */
1549 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1550 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1551
1552 if (mode == I40E_LINK_ACTIVITY)
1553 blink = false;
1554
9be00d67 1555 if (blink)
41a1d04b 1556 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
9be00d67 1557 else
41a1d04b 1558 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
0556a9e3 1559
56a62fc8 1560 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1561 break;
56a62fc8
JB		 1562 }
1563}
1564
1565/* Admin command wrappers */
56a62fc8 1566
8109e123
CS		 1567/**
1568 * i40e_aq_get_phy_capabilities
1569 * @hw: pointer to the hw struct
1570 * @abilities: structure for PHY capabilities to be filled
1571 * @qualified_modules: report Qualified Modules
1572 * @report_init: report init capabilities (active are default)
1573 * @cmd_details: pointer to command details structure or NULL
1574 *
1575 * Returns the various PHY abilities supported on the Port.
1576 **/
1577i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1578 bool qualified_modules, bool report_init,
1579 struct i40e_aq_get_phy_abilities_resp *abilities,
1580 struct i40e_asq_cmd_details *cmd_details)
1581{
1582 struct i40e_aq_desc desc;
1583 i40e_status status;
1584 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1585
1586 if (!abilities)
1587 return I40E_ERR_PARAM;
1588
1589 i40e_fill_default_direct_cmd_desc(&desc,
1590 i40e_aqc_opc_get_phy_abilities);
1591
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1593 if (abilities_size > I40E_AQ_LARGE_BUF)
1594 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1595
1596 if (qualified_modules)
1597 desc.params.external.param0 |=
1598 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1599
1600 if (report_init)
1601 desc.params.external.param0 |=
1602 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1603
1604 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1605 cmd_details);
1606
1607 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1608 status = I40E_ERR_UNKNOWN_PHY;
1609
3ac67d7b
KS		 1610 if (report_init)
1611 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1612
8109e123
CS		 1613 return status;
1614}
1615
c56999f9
CS		 1616/**
1617 * i40e_aq_set_phy_config
1618 * @hw: pointer to the hw struct
1619 * @config: structure with PHY configuration to be set
1620 * @cmd_details: pointer to command details structure or NULL
1621 *
1622 * Set the various PHY configuration parameters
1623 * supported on the Port.One or more of the Set PHY config parameters may be
1624 * ignored in an MFP mode as the PF may not have the privilege to set some
1625 * of the PHY Config parameters. This status will be indicated by the
1626 * command response.
1627 **/
1628enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1629 struct i40e_aq_set_phy_config *config,
1630 struct i40e_asq_cmd_details *cmd_details)
1631{
1632 struct i40e_aq_desc desc;
1633 struct i40e_aq_set_phy_config *cmd =
1634 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1635 enum i40e_status_code status;
1636
1637 if (!config)
1638 return I40E_ERR_PARAM;
1639
1640 i40e_fill_default_direct_cmd_desc(&desc,
1641 i40e_aqc_opc_set_phy_config);
1642
1643 *cmd = *config;
1644
1645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1646
1647 return status;
1648}
1649
1650/**
1651 * i40e_set_fc
1652 * @hw: pointer to the hw struct
1653 *
1654 * Set the requested flow control mode using set_phy_config.
1655 **/
1656enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1657 bool atomic_restart)
1658{
1659 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1660 struct i40e_aq_get_phy_abilities_resp abilities;
1661 struct i40e_aq_set_phy_config config;
1662 enum i40e_status_code status;
1663 u8 pause_mask = 0x0;
1664
1665 *aq_failures = 0x0;
1666
1667 switch (fc_mode) {
1668 case I40E_FC_FULL:
1669 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1670 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1671 break;
1672 case I40E_FC_RX_PAUSE:
1673 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1674 break;
1675 case I40E_FC_TX_PAUSE:
1676 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1677 break;
1678 default:
1679 break;
1680 }
1681
1682 /* Get the current phy config */
1683 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1684 NULL);
1685 if (status) {
1686 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1687 return status;
1688 }
1689
1690 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1691 /* clear the old pause settings */
1692 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1693 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1694 /* set the new abilities */
1695 config.abilities |= pause_mask;
1696 /* If the abilities have changed, then set the new config */
1697 if (config.abilities != abilities.abilities) {
1698 /* Auto restart link so settings take effect */
1699 if (atomic_restart)
1700 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1701 /* Copy over all the old settings */
1702 config.phy_type = abilities.phy_type;
1703 config.link_speed = abilities.link_speed;
1704 config.eee_capability = abilities.eee_capability;
1705 config.eeer = abilities.eeer_val;
1706 config.low_power_ctrl = abilities.d3_lpan;
1707 status = i40e_aq_set_phy_config(hw, &config, NULL);
1708
1709 if (status)
1710 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1711 }
1712 /* Update the link info */
0a862b43 1713 status = i40e_update_link_info(hw);
c56999f9
CS		 1714 if (status) {
1715 /* Wait a little bit (on 40G cards it sometimes takes a really
1716 * long time for link to come back from the atomic reset)
1717 * and try once more
1718 */
1719 msleep(1000);
0a862b43 1720 status = i40e_update_link_info(hw);
c56999f9
CS		 1721 }
1722 if (status)
1723 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1724
1725 return status;
1726}
1727
c9b9b0ae
SN		 1728/**
1729 * i40e_aq_clear_pxe_mode
1730 * @hw: pointer to the hw struct
1731 * @cmd_details: pointer to command details structure or NULL
1732 *
1733 * Tell the firmware that the driver is taking over from PXE
1734 **/
1735i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1736 struct i40e_asq_cmd_details *cmd_details)
1737{
1738 i40e_status status;
1739 struct i40e_aq_desc desc;
1740 struct i40e_aqc_clear_pxe *cmd =
1741 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1742
1743 i40e_fill_default_direct_cmd_desc(&desc,
1744 i40e_aqc_opc_clear_pxe_mode);
1745
1746 cmd->rx_cnt = 0x2;
1747
1748 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1749
1750 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1751
1752 return status;
1753}
1754
56a62fc8
JB		 1755/**
1756 * i40e_aq_set_link_restart_an
1757 * @hw: pointer to the hw struct
1ac978af 1758 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1759 * @cmd_details: pointer to command details structure or NULL
1760 *
1761 * Sets up the link and restarts the Auto-Negotiation over the link.
1762 **/
1763i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1764 bool enable_link,
1765 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1766{
1767 struct i40e_aq_desc desc;
1768 struct i40e_aqc_set_link_restart_an *cmd =
1769 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1770 i40e_status status;
1771
1772 i40e_fill_default_direct_cmd_desc(&desc,
1773 i40e_aqc_opc_set_link_restart_an);
1774
1775 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1776 if (enable_link)
1777 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1778 else
1779 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1780
1781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1782
1783 return status;
1784}
1785
1786/**
1787 * i40e_aq_get_link_info
1788 * @hw: pointer to the hw struct
1789 * @enable_lse: enable/disable LinkStatusEvent reporting
1790 * @link: pointer to link status structure - optional
1791 * @cmd_details: pointer to command details structure or NULL
1792 *
1793 * Returns the link status of the adapter.
1794 **/
1795i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1796 bool enable_lse, struct i40e_link_status *link,
1797 struct i40e_asq_cmd_details *cmd_details)
1798{
1799 struct i40e_aq_desc desc;
1800 struct i40e_aqc_get_link_status *resp =
1801 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1802 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1803 i40e_status status;
c56999f9 1804 bool tx_pause, rx_pause;
56a62fc8
JB		 1805 u16 command_flags;
1806
1807 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1808
1809 if (enable_lse)
1810 command_flags = I40E_AQ_LSE_ENABLE;
1811 else
1812 command_flags = I40E_AQ_LSE_DISABLE;
1813 resp->command_flags = cpu_to_le16(command_flags);
1814
1815 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1816
1817 if (status)
1818 goto aq_get_link_info_exit;
1819
1820 /* save off old link status information */
c36bd4a7 1821 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1822
1823 /* update link status */
1824 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1825 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1826 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1827 hw_link_info->link_info = resp->link_info;
1828 hw_link_info->an_info = resp->an_info;
1829 hw_link_info->ext_info = resp->ext_info;
639dc377 1830 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1831 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1832 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1833
c56999f9
CS		 1834 /* update fc info */
1835 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1836 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1837 if (tx_pause & rx_pause)
1838 hw->fc.current_mode = I40E_FC_FULL;
1839 else if (tx_pause)
1840 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1841 else if (rx_pause)
1842 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1843 else
1844 hw->fc.current_mode = I40E_FC_NONE;
1845
6bb3f23c
NP		 1846 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1847 hw_link_info->crc_enable = true;
1848 else
1849 hw_link_info->crc_enable = false;
56a62fc8
JB		 1850
1851 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1852 hw_link_info->lse_enable = true;
1853 else
1854 hw_link_info->lse_enable = false;
1855
088c4ee3
CS		 1856 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1857 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1858 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1859
56a62fc8
JB		 1860 /* save link status information */
1861 if (link)
d7595a22 1862 *link = *hw_link_info;
56a62fc8
JB		 1863
1864 /* flag cleared so helper functions don't call AQ again */
1865 hw->phy.get_link_info = false;
1866
1867aq_get_link_info_exit:
1868 return status;
1869}
1870
7e2453fe
JB		 1871/**
1872 * i40e_aq_set_phy_int_mask
1873 * @hw: pointer to the hw struct
1874 * @mask: interrupt mask to be set
1875 * @cmd_details: pointer to command details structure or NULL
1876 *
1877 * Set link interrupt mask.
1878 **/
1879i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1880 u16 mask,
1881 struct i40e_asq_cmd_details *cmd_details)
1882{
1883 struct i40e_aq_desc desc;
1884 struct i40e_aqc_set_phy_int_mask *cmd =
1885 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1886 i40e_status status;
1887
1888 i40e_fill_default_direct_cmd_desc(&desc,
1889 i40e_aqc_opc_set_phy_int_mask);
1890
1891 cmd->event_mask = cpu_to_le16(mask);
1892
1893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1894
1895 return status;
1896}
1897
31b606d0
CW		 1898/**
1899 * i40e_aq_set_phy_debug
1900 * @hw: pointer to the hw struct
1901 * @cmd_flags: debug command flags
1902 * @cmd_details: pointer to command details structure or NULL
1903 *
1904 * Reset the external PHY.
1905 **/
61829026
JB		 1906i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1907 struct i40e_asq_cmd_details *cmd_details)
31b606d0
CW		 1908{
1909 struct i40e_aq_desc desc;
1910 struct i40e_aqc_set_phy_debug *cmd =
1911 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
61829026 1912 i40e_status status;
31b606d0
CW		 1913
1914 i40e_fill_default_direct_cmd_desc(&desc,
1915 i40e_aqc_opc_set_phy_debug);
1916
1917 cmd->command_flags = cmd_flags;
1918
1919 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1920
1921 return status;
1922}
1923
56a62fc8
JB		 1924/**
1925 * i40e_aq_add_vsi
1926 * @hw: pointer to the hw struct
98d44381 1927 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1928 * @cmd_details: pointer to command details structure or NULL
1929 *
1930 * Add a VSI context to the hardware.
1931**/
1932i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1933 struct i40e_vsi_context *vsi_ctx,
1934 struct i40e_asq_cmd_details *cmd_details)
1935{
1936 struct i40e_aq_desc desc;
1937 struct i40e_aqc_add_get_update_vsi *cmd =
1938 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1939 struct i40e_aqc_add_get_update_vsi_completion *resp =
1940 (struct i40e_aqc_add_get_update_vsi_completion *)
1941 &desc.params.raw;
1942 i40e_status status;
1943
1944 i40e_fill_default_direct_cmd_desc(&desc,
1945 i40e_aqc_opc_add_vsi);
1946
1947 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1948 cmd->connection_type = vsi_ctx->connection_type;
1949 cmd->vf_id = vsi_ctx->vf_num;
1950 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1951
1952 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1953
1954 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1955 sizeof(vsi_ctx->info), cmd_details);
1956
1957 if (status)
1958 goto aq_add_vsi_exit;
1959
1960 vsi_ctx->seid = le16_to_cpu(resp->seid);
1961 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1962 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1963 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1964
1965aq_add_vsi_exit:
1966 return status;
1967}
1968
1969/**
1970 * i40e_aq_set_vsi_unicast_promiscuous
1971 * @hw: pointer to the hw struct
1972 * @seid: vsi number
1973 * @set: set unicast promiscuous enable/disable
1974 * @cmd_details: pointer to command details structure or NULL
1975 **/
1976i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1977 u16 seid, bool set,
1978 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1979{
1980 struct i40e_aq_desc desc;
1981 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1982 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1983 i40e_status status;
1984 u16 flags = 0;
1985
1986 i40e_fill_default_direct_cmd_desc(&desc,
1987 i40e_aqc_opc_set_vsi_promiscuous_modes);
1988
3b120089 1989 if (set) {
56a62fc8 1990 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
3b120089
ASJ		 1991 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
1992 (hw->aq.api_maj_ver > 1))
1993 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
1994 }
56a62fc8
JB		 1995
1996 cmd->promiscuous_flags = cpu_to_le16(flags);
1997
1998 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
3b120089
ASJ		 1999 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2000 (hw->aq.api_maj_ver > 1))
2001 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
56a62fc8
JB		 2002
2003 cmd->seid = cpu_to_le16(seid);
2004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2005
2006 return status;
2007}
2008
2009/**
2010 * i40e_aq_set_vsi_multicast_promiscuous
2011 * @hw: pointer to the hw struct
2012 * @seid: vsi number
2013 * @set: set multicast promiscuous enable/disable
2014 * @cmd_details: pointer to command details structure or NULL
2015 **/
2016i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2017 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2018{
2019 struct i40e_aq_desc desc;
2020 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2021 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2022 i40e_status status;
2023 u16 flags = 0;
2024
2025 i40e_fill_default_direct_cmd_desc(&desc,
2026 i40e_aqc_opc_set_vsi_promiscuous_modes);
2027
2028 if (set)
2029 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2030
2031 cmd->promiscuous_flags = cpu_to_le16(flags);
2032
2033 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2034
2035 cmd->seid = cpu_to_le16(seid);
2036 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2037
2038 return status;
2039}
2040
2041/**
2042 * i40e_aq_set_vsi_broadcast
2043 * @hw: pointer to the hw struct
2044 * @seid: vsi number
2045 * @set_filter: true to set filter, false to clear filter
2046 * @cmd_details: pointer to command details structure or NULL
2047 *
2048 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2049 **/
2050i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2051 u16 seid, bool set_filter,
2052 struct i40e_asq_cmd_details *cmd_details)
2053{
2054 struct i40e_aq_desc desc;
2055 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2056 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2057 i40e_status status;
2058
2059 i40e_fill_default_direct_cmd_desc(&desc,
2060 i40e_aqc_opc_set_vsi_promiscuous_modes);
2061
2062 if (set_filter)
2063 cmd->promiscuous_flags
2064 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2065 else
2066 cmd->promiscuous_flags
2067 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2068
2069 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2070 cmd->seid = cpu_to_le16(seid);
2071 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2072
2073 return status;
2074}
2075
7bd6875b
KP		 2076/**
2077 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2078 * @hw: pointer to the hw struct
2079 * @seid: vsi number
2080 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2081 * @cmd_details: pointer to command details structure or NULL
2082 **/
2083i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2084 u16 seid, bool enable,
2085 struct i40e_asq_cmd_details *cmd_details)
2086{
2087 struct i40e_aq_desc desc;
2088 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2089 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2090 i40e_status status;
2091 u16 flags = 0;
2092
2093 i40e_fill_default_direct_cmd_desc(&desc,
2094 i40e_aqc_opc_set_vsi_promiscuous_modes);
2095 if (enable)
2096 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2097
2098 cmd->promiscuous_flags = cpu_to_le16(flags);
2099 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2100 cmd->seid = cpu_to_le16(seid);
2101
2102 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2103
2104 return status;
2105}
2106
56a62fc8
JB		 2107/**
2108 * i40e_get_vsi_params - get VSI configuration info
2109 * @hw: pointer to the hw struct
98d44381 2110 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2111 * @cmd_details: pointer to command details structure or NULL
2112 **/
2113i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2114 struct i40e_vsi_context *vsi_ctx,
2115 struct i40e_asq_cmd_details *cmd_details)
2116{
2117 struct i40e_aq_desc desc;
f5ac8579
SN		 2118 struct i40e_aqc_add_get_update_vsi *cmd =
2119 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 2120 struct i40e_aqc_add_get_update_vsi_completion *resp =
2121 (struct i40e_aqc_add_get_update_vsi_completion *)
2122 &desc.params.raw;
2123 i40e_status status;
2124
2125 i40e_fill_default_direct_cmd_desc(&desc,
2126 i40e_aqc_opc_get_vsi_parameters);
2127
f5ac8579 2128 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2129
2130 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 2131
2132 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2133 sizeof(vsi_ctx->info), NULL);
2134
2135 if (status)
2136 goto aq_get_vsi_params_exit;
2137
2138 vsi_ctx->seid = le16_to_cpu(resp->seid);
2139 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2140 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2141 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2142
2143aq_get_vsi_params_exit:
2144 return status;
2145}
2146
2147/**
2148 * i40e_aq_update_vsi_params
2149 * @hw: pointer to the hw struct
98d44381 2150 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2151 * @cmd_details: pointer to command details structure or NULL
2152 *
2153 * Update a VSI context.
2154 **/
2155i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2156 struct i40e_vsi_context *vsi_ctx,
2157 struct i40e_asq_cmd_details *cmd_details)
2158{
2159 struct i40e_aq_desc desc;
f5ac8579
SN		 2160 struct i40e_aqc_add_get_update_vsi *cmd =
2161 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
b6caccac
KS		 2162 struct i40e_aqc_add_get_update_vsi_completion *resp =
2163 (struct i40e_aqc_add_get_update_vsi_completion *)
2164 &desc.params.raw;
56a62fc8
JB		 2165 i40e_status status;
2166
2167 i40e_fill_default_direct_cmd_desc(&desc,
2168 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 2169 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2170
2171 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 2172
2173 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2174 sizeof(vsi_ctx->info), cmd_details);
2175
b6caccac
KS		 2176 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2177 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2178
56a62fc8
JB		 2179 return status;
2180}
2181
2182/**
2183 * i40e_aq_get_switch_config
2184 * @hw: pointer to the hardware structure
2185 * @buf: pointer to the result buffer
2186 * @buf_size: length of input buffer
2187 * @start_seid: seid to start for the report, 0 == beginning
2188 * @cmd_details: pointer to command details structure or NULL
2189 *
2190 * Fill the buf with switch configuration returned from AdminQ command
2191 **/
2192i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2193 struct i40e_aqc_get_switch_config_resp *buf,
2194 u16 buf_size, u16 *start_seid,
2195 struct i40e_asq_cmd_details *cmd_details)
2196{
2197 struct i40e_aq_desc desc;
2198 struct i40e_aqc_switch_seid *scfg =
2199 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2200 i40e_status status;
2201
2202 i40e_fill_default_direct_cmd_desc(&desc,
2203 i40e_aqc_opc_get_switch_config);
2204 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2205 if (buf_size > I40E_AQ_LARGE_BUF)
2206 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2207 scfg->seid = cpu_to_le16(*start_seid);
2208
2209 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2210 *start_seid = le16_to_cpu(scfg->seid);
2211
2212 return status;
2213}
2214
2215/**
2216 * i40e_aq_get_firmware_version
2217 * @hw: pointer to the hw struct
2218 * @fw_major_version: firmware major version
2219 * @fw_minor_version: firmware minor version
7edf810c 2220 * @fw_build: firmware build number
56a62fc8
JB		 2221 * @api_major_version: major queue version
2222 * @api_minor_version: minor queue version
2223 * @cmd_details: pointer to command details structure or NULL
2224 *
2225 * Get the firmware version from the admin queue commands
2226 **/
2227i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2228 u16 *fw_major_version, u16 *fw_minor_version,
7edf810c 2229 u32 *fw_build,
56a62fc8
JB		 2230 u16 *api_major_version, u16 *api_minor_version,
2231 struct i40e_asq_cmd_details *cmd_details)
2232{
2233 struct i40e_aq_desc desc;
2234 struct i40e_aqc_get_version *resp =
2235 (struct i40e_aqc_get_version *)&desc.params.raw;
2236 i40e_status status;
2237
2238 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2239
2240 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2241
2242 if (!status) {
7edf810c 2243 if (fw_major_version)
56a62fc8 2244 *fw_major_version = le16_to_cpu(resp->fw_major);
7edf810c 2245 if (fw_minor_version)
56a62fc8 2246 *fw_minor_version = le16_to_cpu(resp->fw_minor);
7edf810c
SN		 2247 if (fw_build)
2248 *fw_build = le32_to_cpu(resp->fw_build);
2249 if (api_major_version)
56a62fc8 2250 *api_major_version = le16_to_cpu(resp->api_major);
7edf810c 2251 if (api_minor_version)
56a62fc8
JB		 2252 *api_minor_version = le16_to_cpu(resp->api_minor);
2253 }
2254
2255 return status;
2256}
2257
2258/**
2259 * i40e_aq_send_driver_version
2260 * @hw: pointer to the hw struct
56a62fc8
JB		 2261 * @dv: driver's major, minor version
2262 * @cmd_details: pointer to command details structure or NULL
2263 *
2264 * Send the driver version to the firmware
2265 **/
2266i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2267 struct i40e_driver_version *dv,
2268 struct i40e_asq_cmd_details *cmd_details)
2269{
2270 struct i40e_aq_desc desc;
2271 struct i40e_aqc_driver_version *cmd =
2272 (struct i40e_aqc_driver_version *)&desc.params.raw;
2273 i40e_status status;
9d2f98e1 2274 u16 len;
56a62fc8
JB		 2275
2276 if (dv == NULL)
2277 return I40E_ERR_PARAM;
2278
2279 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2280
3b38cd17 2281 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
56a62fc8
JB		 2282 cmd->driver_major_ver = dv->major_version;
2283 cmd->driver_minor_ver = dv->minor_version;
2284 cmd->driver_build_ver = dv->build_version;
2285 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 2286
2287 len = 0;
2288 while (len < sizeof(dv->driver_string) &&
2289 (dv->driver_string[len] < 0x80) &&
2290 dv->driver_string[len])
2291 len++;
2292 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2293 len, cmd_details);
56a62fc8
JB		 2294
2295 return status;
2296}
2297
2298/**
2299 * i40e_get_link_status - get status of the HW network link
2300 * @hw: pointer to the hw struct
a72a5abc 2301 * @link_up: pointer to bool (true/false = linkup/linkdown)
56a62fc8 2302 *
a72a5abc
JB		 2303 * Variable link_up true if link is up, false if link is down.
2304 * The variable link_up is invalid if returned value of status != 0
56a62fc8
JB		 2305 *
2306 * Side effect: LinkStatusEvent reporting becomes enabled
2307 **/
a72a5abc 2308i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
56a62fc8
JB		 2309{
2310 i40e_status status = 0;
56a62fc8
JB		 2311
2312 if (hw->phy.get_link_info) {
0a862b43 2313 status = i40e_update_link_info(hw);
56a62fc8
JB		 2314
2315 if (status)
a72a5abc
JB		 2316 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2317 status);
56a62fc8
JB		 2318 }
2319
a72a5abc 2320 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
56a62fc8 2321
a72a5abc 2322 return status;
56a62fc8
JB		 2323}
2324
0a862b43
CS		 2325/**
2326 * i40e_updatelink_status - update status of the HW network link
2327 * @hw: pointer to the hw struct
2328 **/
2329i40e_status i40e_update_link_info(struct i40e_hw *hw)
2330{
2331 struct i40e_aq_get_phy_abilities_resp abilities;
2332 i40e_status status = 0;
2333
2334 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2335 if (status)
2336 return status;
2337
8589af70
CW		 2338 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2339 status = i40e_aq_get_phy_capabilities(hw, false, false,
2340 &abilities, NULL);
2341 if (status)
2342 return status;
0a862b43 2343
8589af70
CW		 2344 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2345 sizeof(hw->phy.link_info.module_type));
2346 }
0a862b43
CS		 2347
2348 return status;
2349}
2350
56a62fc8
JB		 2351/**
2352 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2353 * @hw: pointer to the hw struct
2354 * @uplink_seid: the MAC or other gizmo SEID
2355 * @downlink_seid: the VSI SEID
2356 * @enabled_tc: bitmap of TCs to be enabled
2357 * @default_port: true for default port VSI, false for control port
2358 * @veb_seid: pointer to where to put the resulting VEB SEID
8a187f44 2359 * @enable_stats: true to turn on VEB stats
56a62fc8
JB		 2360 * @cmd_details: pointer to command details structure or NULL
2361 *
2362 * This asks the FW to add a VEB between the uplink and downlink
2363 * elements. If the uplink SEID is 0, this will be a floating VEB.
2364 **/
2365i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2366 u16 downlink_seid, u8 enabled_tc,
8a187f44
SN		 2367 bool default_port, u16 *veb_seid,
2368 bool enable_stats,
56a62fc8
JB		 2369 struct i40e_asq_cmd_details *cmd_details)
2370{
2371 struct i40e_aq_desc desc;
2372 struct i40e_aqc_add_veb *cmd =
2373 (struct i40e_aqc_add_veb *)&desc.params.raw;
2374 struct i40e_aqc_add_veb_completion *resp =
2375 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2376 i40e_status status;
2377 u16 veb_flags = 0;
2378
2379 /* SEIDs need to either both be set or both be 0 for floating VEB */
2380 if (!!uplink_seid != !!downlink_seid)
2381 return I40E_ERR_PARAM;
2382
2383 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2384
2385 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2386 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2387 cmd->enable_tcs = enabled_tc;
2388 if (!uplink_seid)
2389 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2390 if (default_port)
2391 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2392 else
2393 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95 2394
8a187f44
SN		 2395 /* reverse logic here: set the bitflag to disable the stats */
2396 if (!enable_stats)
2397 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
e1c51b95 2398
56a62fc8
JB		 2399 cmd->veb_flags = cpu_to_le16(veb_flags);
2400
2401 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2402
2403 if (!status && veb_seid)
2404 *veb_seid = le16_to_cpu(resp->veb_seid);
2405
2406 return status;
2407}
2408
2409/**
2410 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2411 * @hw: pointer to the hw struct
2412 * @veb_seid: the SEID of the VEB to query
2413 * @switch_id: the uplink switch id
98d44381 2414 * @floating: set to true if the VEB is floating
56a62fc8
JB		 2415 * @statistic_index: index of the stats counter block for this VEB
2416 * @vebs_used: number of VEB's used by function
98d44381 2417 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 2418 * @cmd_details: pointer to command details structure or NULL
2419 *
2420 * This retrieves the parameters for a particular VEB, specified by
2421 * uplink_seid, and returns them to the caller.
2422 **/
2423i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2424 u16 veb_seid, u16 *switch_id,
2425 bool *floating, u16 *statistic_index,
2426 u16 *vebs_used, u16 *vebs_free,
2427 struct i40e_asq_cmd_details *cmd_details)
2428{
2429 struct i40e_aq_desc desc;
2430 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2431 (struct i40e_aqc_get_veb_parameters_completion *)
2432 &desc.params.raw;
2433 i40e_status status;
2434
2435 if (veb_seid == 0)
2436 return I40E_ERR_PARAM;
2437
2438 i40e_fill_default_direct_cmd_desc(&desc,
2439 i40e_aqc_opc_get_veb_parameters);
2440 cmd_resp->seid = cpu_to_le16(veb_seid);
2441
2442 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2443 if (status)
2444 goto get_veb_exit;
2445
2446 if (switch_id)
2447 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2448 if (statistic_index)
2449 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2450 if (vebs_used)
2451 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2452 if (vebs_free)
2453 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2454 if (floating) {
2455 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
6995b36c 2456
56a62fc8
JB		 2457 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2458 *floating = true;
2459 else
2460 *floating = false;
2461 }
2462
2463get_veb_exit:
2464 return status;
2465}
2466
2467/**
2468 * i40e_aq_add_macvlan
2469 * @hw: pointer to the hw struct
2470 * @seid: VSI for the mac address
2471 * @mv_list: list of macvlans to be added
2472 * @count: length of the list
2473 * @cmd_details: pointer to command details structure or NULL
2474 *
2475 * Add MAC/VLAN addresses to the HW filtering
2476 **/
2477i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2478 struct i40e_aqc_add_macvlan_element_data *mv_list,
2479 u16 count, struct i40e_asq_cmd_details *cmd_details)
2480{
2481 struct i40e_aq_desc desc;
2482 struct i40e_aqc_macvlan *cmd =
2483 (struct i40e_aqc_macvlan *)&desc.params.raw;
2484 i40e_status status;
2485 u16 buf_size;
67be6eb2 2486 int i;
56a62fc8
JB		 2487
2488 if (count == 0 || !mv_list || !hw)
2489 return I40E_ERR_PARAM;
2490
1efc80ee 2491 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2492
2493 /* prep the rest of the request */
2494 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2495 cmd->num_addresses = cpu_to_le16(count);
2496 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2497 cmd->seid[1] = 0;
2498 cmd->seid[2] = 0;
2499
67be6eb2
SN		 2500 for (i = 0; i < count; i++)
2501 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2502 mv_list[i].flags |=
2503 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2504
56a62fc8
JB		 2505 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2506 if (buf_size > I40E_AQ_LARGE_BUF)
2507 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2508
2509 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
67be6eb2 2510 cmd_details);
56a62fc8
JB		 2511
2512 return status;
2513}
2514
2515/**
2516 * i40e_aq_remove_macvlan
2517 * @hw: pointer to the hw struct
2518 * @seid: VSI for the mac address
2519 * @mv_list: list of macvlans to be removed
2520 * @count: length of the list
2521 * @cmd_details: pointer to command details structure or NULL
2522 *
2523 * Remove MAC/VLAN addresses from the HW filtering
2524 **/
2525i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2526 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2527 u16 count, struct i40e_asq_cmd_details *cmd_details)
2528{
2529 struct i40e_aq_desc desc;
2530 struct i40e_aqc_macvlan *cmd =
2531 (struct i40e_aqc_macvlan *)&desc.params.raw;
2532 i40e_status status;
2533 u16 buf_size;
2534
2535 if (count == 0 || !mv_list || !hw)
2536 return I40E_ERR_PARAM;
2537
1efc80ee 2538 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2539
2540 /* prep the rest of the request */
2541 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2542 cmd->num_addresses = cpu_to_le16(count);
2543 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2544 cmd->seid[1] = 0;
2545 cmd->seid[2] = 0;
2546
2547 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2548 if (buf_size > I40E_AQ_LARGE_BUF)
2549 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2550
2551 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2552 cmd_details);
2553
2554 return status;
2555}
2556
7bd6875b
KP		 2557/**
2558 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2559 * @hw: pointer to the hw struct
2560 * @opcode: AQ opcode for add or delete mirror rule
2561 * @sw_seid: Switch SEID (to which rule refers)
2562 * @rule_type: Rule Type (ingress/egress/VLAN)
2563 * @id: Destination VSI SEID or Rule ID
2564 * @count: length of the list
2565 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2566 * @cmd_details: pointer to command details structure or NULL
2567 * @rule_id: Rule ID returned from FW
2568 * @rule_used: Number of rules used in internal switch
2569 * @rule_free: Number of rules free in internal switch
2570 *
2571 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2572 * VEBs/VEPA elements only
2573 **/
2574static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2575 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2576 u16 count, __le16 *mr_list,
2577 struct i40e_asq_cmd_details *cmd_details,
2578 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2579{
2580 struct i40e_aq_desc desc;
2581 struct i40e_aqc_add_delete_mirror_rule *cmd =
2582 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2583 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2584 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2585 i40e_status status;
2586 u16 buf_size;
2587
2588 buf_size = count * sizeof(*mr_list);
2589
2590 /* prep the rest of the request */
2591 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2592 cmd->seid = cpu_to_le16(sw_seid);
2593 cmd->rule_type = cpu_to_le16(rule_type &
2594 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2595 cmd->num_entries = cpu_to_le16(count);
2596 /* Dest VSI for add, rule_id for delete */
2597 cmd->destination = cpu_to_le16(id);
2598 if (mr_list) {
2599 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2600 I40E_AQ_FLAG_RD));
2601 if (buf_size > I40E_AQ_LARGE_BUF)
2602 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2603 }
2604
2605 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2606 cmd_details);
2607 if (!status ||
2608 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2609 if (rule_id)
2610 *rule_id = le16_to_cpu(resp->rule_id);
2611 if (rules_used)
2612 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2613 if (rules_free)
2614 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2615 }
2616 return status;
2617}
2618
2619/**
2620 * i40e_aq_add_mirrorrule - add a mirror rule
2621 * @hw: pointer to the hw struct
2622 * @sw_seid: Switch SEID (to which rule refers)
2623 * @rule_type: Rule Type (ingress/egress/VLAN)
2624 * @dest_vsi: SEID of VSI to which packets will be mirrored
2625 * @count: length of the list
2626 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2627 * @cmd_details: pointer to command details structure or NULL
2628 * @rule_id: Rule ID returned from FW
2629 * @rule_used: Number of rules used in internal switch
2630 * @rule_free: Number of rules free in internal switch
2631 *
2632 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2633 **/
2634i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2635 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2636 struct i40e_asq_cmd_details *cmd_details,
2637 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2638{
2639 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2640 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2641 if (count == 0 || !mr_list)
2642 return I40E_ERR_PARAM;
2643 }
2644
2645 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2646 rule_type, dest_vsi, count, mr_list,
2647 cmd_details, rule_id, rules_used, rules_free);
2648}
2649
2650/**
2651 * i40e_aq_delete_mirrorrule - delete a mirror rule
2652 * @hw: pointer to the hw struct
2653 * @sw_seid: Switch SEID (to which rule refers)
2654 * @rule_type: Rule Type (ingress/egress/VLAN)
2655 * @count: length of the list
2656 * @rule_id: Rule ID that is returned in the receive desc as part of
2657 * add_mirrorrule.
2658 * @mr_list: list of mirrored VLAN IDs to be removed
2659 * @cmd_details: pointer to command details structure or NULL
2660 * @rule_used: Number of rules used in internal switch
2661 * @rule_free: Number of rules free in internal switch
2662 *
2663 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2664 **/
2665i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2666 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2667 struct i40e_asq_cmd_details *cmd_details,
2668 u16 *rules_used, u16 *rules_free)
2669{
2670 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
db077278 2671 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7bd6875b
KP		 2672 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2673 * mirroring. For other rule_type, count and rule_type should
2674 * not matter.
2675 */
2676 if (count == 0 || !mr_list)
2677 return I40E_ERR_PARAM;
2678 }
2679
2680 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2681 rule_type, rule_id, count, mr_list,
2682 cmd_details, NULL, rules_used, rules_free);
2683}
2684
56a62fc8
JB		 2685/**
2686 * i40e_aq_send_msg_to_vf
2687 * @hw: pointer to the hardware structure
b40c82e6 2688 * @vfid: VF id to send msg
98d44381
JK		 2689 * @v_opcode: opcodes for VF-PF communication
2690 * @v_retval: return error code
56a62fc8
JB		 2691 * @msg: pointer to the msg buffer
2692 * @msglen: msg length
2693 * @cmd_details: pointer to command details
2694 *
2695 * send msg to vf
2696 **/
2697i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2698 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2699 struct i40e_asq_cmd_details *cmd_details)
2700{
2701 struct i40e_aq_desc desc;
2702 struct i40e_aqc_pf_vf_message *cmd =
2703 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2704 i40e_status status;
2705
2706 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2707 cmd->id = cpu_to_le32(vfid);
2708 desc.cookie_high = cpu_to_le32(v_opcode);
2709 desc.cookie_low = cpu_to_le32(v_retval);
2710 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2711 if (msglen) {
2712 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2713 I40E_AQ_FLAG_RD));
2714 if (msglen > I40E_AQ_LARGE_BUF)
2715 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2716 desc.datalen = cpu_to_le16(msglen);
2717 }
2718 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2719
2720 return status;
2721}
2722
9fee9db5
SN		 2723/**
2724 * i40e_aq_debug_read_register
2725 * @hw: pointer to the hw struct
2726 * @reg_addr: register address
2727 * @reg_val: register value
2728 * @cmd_details: pointer to command details structure or NULL
2729 *
2730 * Read the register using the admin queue commands
2731 **/
2732i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
7b115dd0 2733 u32 reg_addr, u64 *reg_val,
9fee9db5
SN		 2734 struct i40e_asq_cmd_details *cmd_details)
2735{
2736 struct i40e_aq_desc desc;
2737 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2738 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2739 i40e_status status;
2740
2741 if (reg_val == NULL)
2742 return I40E_ERR_PARAM;
2743
7b115dd0 2744 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
9fee9db5
SN		 2745
2746 cmd_resp->address = cpu_to_le32(reg_addr);
2747
2748 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2749
2750 if (!status) {
7b115dd0
JB		 2751 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2752 (u64)le32_to_cpu(cmd_resp->value_low);
9fee9db5
SN		 2753 }
2754
2755 return status;
2756}
2757
53db45cd
SN		 2758/**
2759 * i40e_aq_debug_write_register
2760 * @hw: pointer to the hw struct
2761 * @reg_addr: register address
2762 * @reg_val: register value
2763 * @cmd_details: pointer to command details structure or NULL
2764 *
2765 * Write to a register using the admin queue commands
2766 **/
2767i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2768 u32 reg_addr, u64 reg_val,
2769 struct i40e_asq_cmd_details *cmd_details)
2770{
2771 struct i40e_aq_desc desc;
2772 struct i40e_aqc_debug_reg_read_write *cmd =
2773 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2774 i40e_status status;
2775
2776 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2777
2778 cmd->address = cpu_to_le32(reg_addr);
2779 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2780 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2781
2782 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2783
2784 return status;
2785}
2786
56a62fc8
JB		 2787/**
2788 * i40e_aq_set_hmc_resource_profile
2789 * @hw: pointer to the hw struct
2790 * @profile: type of profile the HMC is to be set as
2791 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2792 * @cmd_details: pointer to command details structure or NULL
2793 *
2794 * set the HMC profile of the device.
2795 **/
2796i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2797 enum i40e_aq_hmc_profile profile,
2798 u8 pe_vf_enabled_count,
2799 struct i40e_asq_cmd_details *cmd_details)
2800{
2801 struct i40e_aq_desc desc;
2802 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2803 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2804 i40e_status status;
2805
2806 i40e_fill_default_direct_cmd_desc(&desc,
2807 i40e_aqc_opc_set_hmc_resource_profile);
2808
2809 cmd->pm_profile = (u8)profile;
2810 cmd->pe_vf_enabled = pe_vf_enabled_count;
2811
2812 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2813
2814 return status;
2815}
2816
2817/**
2818 * i40e_aq_request_resource
2819 * @hw: pointer to the hw struct
2820 * @resource: resource id
2821 * @access: access type
2822 * @sdp_number: resource number
2823 * @timeout: the maximum time in ms that the driver may hold the resource
2824 * @cmd_details: pointer to command details structure or NULL
2825 *
2826 * requests common resource using the admin queue commands
2827 **/
2828i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2829 enum i40e_aq_resources_ids resource,
2830 enum i40e_aq_resource_access_type access,
2831 u8 sdp_number, u64 *timeout,
2832 struct i40e_asq_cmd_details *cmd_details)
2833{
2834 struct i40e_aq_desc desc;
2835 struct i40e_aqc_request_resource *cmd_resp =
2836 (struct i40e_aqc_request_resource *)&desc.params.raw;
2837 i40e_status status;
2838
2839 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2840
2841 cmd_resp->resource_id = cpu_to_le16(resource);
2842 cmd_resp->access_type = cpu_to_le16(access);
2843 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2844
2845 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2846 /* The completion specifies the maximum time in ms that the driver
2847 * may hold the resource in the Timeout field.
2848 * If the resource is held by someone else, the command completes with
2849 * busy return value and the timeout field indicates the maximum time
2850 * the current owner of the resource has to free it.
2851 */
2852 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2853 *timeout = le32_to_cpu(cmd_resp->timeout);
2854
2855 return status;
2856}
2857
2858/**
2859 * i40e_aq_release_resource
2860 * @hw: pointer to the hw struct
2861 * @resource: resource id
2862 * @sdp_number: resource number
2863 * @cmd_details: pointer to command details structure or NULL
2864 *
2865 * release common resource using the admin queue commands
2866 **/
2867i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2868 enum i40e_aq_resources_ids resource,
2869 u8 sdp_number,
2870 struct i40e_asq_cmd_details *cmd_details)
2871{
2872 struct i40e_aq_desc desc;
2873 struct i40e_aqc_request_resource *cmd =
2874 (struct i40e_aqc_request_resource *)&desc.params.raw;
2875 i40e_status status;
2876
2877 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2878
2879 cmd->resource_id = cpu_to_le16(resource);
2880 cmd->resource_number = cpu_to_le32(sdp_number);
2881
2882 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2883
2884 return status;
2885}
2886
2887/**
2888 * i40e_aq_read_nvm
2889 * @hw: pointer to the hw struct
2890 * @module_pointer: module pointer location in words from the NVM beginning
2891 * @offset: byte offset from the module beginning
2892 * @length: length of the section to be read (in bytes from the offset)
2893 * @data: command buffer (size [bytes] = length)
2894 * @last_command: tells if this is the last command in a series
2895 * @cmd_details: pointer to command details structure or NULL
2896 *
2897 * Read the NVM using the admin queue commands
2898 **/
2899i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2900 u32 offset, u16 length, void *data,
2901 bool last_command,
2902 struct i40e_asq_cmd_details *cmd_details)
2903{
2904 struct i40e_aq_desc desc;
2905 struct i40e_aqc_nvm_update *cmd =
2906 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2907 i40e_status status;
2908
2909 /* In offset the highest byte must be zeroed. */
2910 if (offset & 0xFF000000) {
2911 status = I40E_ERR_PARAM;
2912 goto i40e_aq_read_nvm_exit;
2913 }
2914
2915 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2916
2917 /* If this is the last command in a series, set the proper flag. */
2918 if (last_command)
2919 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2920 cmd->module_pointer = module_pointer;
2921 cmd->offset = cpu_to_le32(offset);
2922 cmd->length = cpu_to_le16(length);
2923
2924 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2925 if (length > I40E_AQ_LARGE_BUF)
2926 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2927
2928 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2929
2930i40e_aq_read_nvm_exit:
2931 return status;
2932}
2933
cd552cb4
SN		 2934/**
2935 * i40e_aq_erase_nvm
2936 * @hw: pointer to the hw struct
2937 * @module_pointer: module pointer location in words from the NVM beginning
2938 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2939 * @length: length of the section to be erased (expressed in 4 KB)
2940 * @last_command: tells if this is the last command in a series
2941 * @cmd_details: pointer to command details structure or NULL
2942 *
2943 * Erase the NVM sector using the admin queue commands
2944 **/
2945i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2946 u32 offset, u16 length, bool last_command,
2947 struct i40e_asq_cmd_details *cmd_details)
2948{
2949 struct i40e_aq_desc desc;
2950 struct i40e_aqc_nvm_update *cmd =
2951 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2952 i40e_status status;
2953
2954 /* In offset the highest byte must be zeroed. */
2955 if (offset & 0xFF000000) {
2956 status = I40E_ERR_PARAM;
2957 goto i40e_aq_erase_nvm_exit;
2958 }
2959
2960 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2961
2962 /* If this is the last command in a series, set the proper flag. */
2963 if (last_command)
2964 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2965 cmd->module_pointer = module_pointer;
2966 cmd->offset = cpu_to_le32(offset);
2967 cmd->length = cpu_to_le16(length);
2968
2969 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2970
2971i40e_aq_erase_nvm_exit:
2972 return status;
2973}
2974
56a62fc8
JB		 2975/**
2976 * i40e_parse_discover_capabilities
2977 * @hw: pointer to the hw struct
2978 * @buff: pointer to a buffer containing device/function capability records
2979 * @cap_count: number of capability records in the list
2980 * @list_type_opc: type of capabilities list to parse
2981 *
2982 * Parse the device/function capabilities list.
2983 **/
2984static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2985 u32 cap_count,
2986 enum i40e_admin_queue_opc list_type_opc)
2987{
2988 struct i40e_aqc_list_capabilities_element_resp *cap;
9fee9db5 2989 u32 valid_functions, num_functions;
56a62fc8
JB		 2990 u32 number, logical_id, phys_id;
2991 struct i40e_hw_capabilities *p;
c78b953e 2992 u8 major_rev;
56a62fc8
JB		 2993 u32 i = 0;
2994 u16 id;
2995
2996 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2997
2998 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 2999 p = &hw->dev_caps;
56a62fc8 3000 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 3001 p = &hw->func_caps;
56a62fc8
JB		 3002 else
3003 return;
3004
3005 for (i = 0; i < cap_count; i++, cap++) {
3006 id = le16_to_cpu(cap->id);
3007 number = le32_to_cpu(cap->number);
3008 logical_id = le32_to_cpu(cap->logical_id);
3009 phys_id = le32_to_cpu(cap->phys_id);
c78b953e 3010 major_rev = cap->major_rev;
56a62fc8
JB		 3011
3012 switch (id) {
406e734a 3013 case I40E_AQ_CAP_ID_SWITCH_MODE:
56a62fc8
JB		 3014 p->switch_mode = number;
3015 break;
406e734a 3016 case I40E_AQ_CAP_ID_MNG_MODE:
56a62fc8
JB		 3017 p->management_mode = number;
3018 break;
406e734a 3019 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
56a62fc8
JB		 3020 p->npar_enable = number;
3021 break;
406e734a 3022 case I40E_AQ_CAP_ID_OS2BMC_CAP:
56a62fc8
JB		 3023 p->os2bmc = number;
3024 break;
406e734a 3025 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
56a62fc8
JB		 3026 p->valid_functions = number;
3027 break;
406e734a 3028 case I40E_AQ_CAP_ID_SRIOV:
56a62fc8
JB		 3029 if (number == 1)
3030 p->sr_iov_1_1 = true;
3031 break;
406e734a 3032 case I40E_AQ_CAP_ID_VF:
56a62fc8
JB		 3033 p->num_vfs = number;
3034 p->vf_base_id = logical_id;
3035 break;
406e734a 3036 case I40E_AQ_CAP_ID_VMDQ:
56a62fc8
JB		 3037 if (number == 1)
3038 p->vmdq = true;
3039 break;
406e734a 3040 case I40E_AQ_CAP_ID_8021QBG:
56a62fc8
JB		 3041 if (number == 1)
3042 p->evb_802_1_qbg = true;
3043 break;
406e734a 3044 case I40E_AQ_CAP_ID_8021QBR:
56a62fc8
JB		 3045 if (number == 1)
3046 p->evb_802_1_qbh = true;
3047 break;
406e734a 3048 case I40E_AQ_CAP_ID_VSI:
56a62fc8
JB		 3049 p->num_vsis = number;
3050 break;
406e734a 3051 case I40E_AQ_CAP_ID_DCB:
56a62fc8
JB		 3052 if (number == 1) {
3053 p->dcb = true;
3054 p->enabled_tcmap = logical_id;
3055 p->maxtc = phys_id;
3056 }
3057 break;
406e734a 3058 case I40E_AQ_CAP_ID_FCOE:
56a62fc8
JB		 3059 if (number == 1)
3060 p->fcoe = true;
3061 break;
406e734a 3062 case I40E_AQ_CAP_ID_ISCSI:
63d7e5a4
NP		 3063 if (number == 1)
3064 p->iscsi = true;
3065 break;
406e734a 3066 case I40E_AQ_CAP_ID_RSS:
56a62fc8 3067 p->rss = true;
e157ea30 3068 p->rss_table_size = number;
56a62fc8
JB		 3069 p->rss_table_entry_width = logical_id;
3070 break;
406e734a 3071 case I40E_AQ_CAP_ID_RXQ:
56a62fc8
JB		 3072 p->num_rx_qp = number;
3073 p->base_queue = phys_id;
3074 break;
406e734a 3075 case I40E_AQ_CAP_ID_TXQ:
56a62fc8
JB		 3076 p->num_tx_qp = number;
3077 p->base_queue = phys_id;
3078 break;
406e734a 3079 case I40E_AQ_CAP_ID_MSIX:
56a62fc8 3080 p->num_msix_vectors = number;
453e16e8
DK		 3081 i40e_debug(hw, I40E_DEBUG_INIT,
3082 "HW Capability: MSIX vector count = %d\n",
3083 p->num_msix_vectors);
56a62fc8 3084 break;
406e734a 3085 case I40E_AQ_CAP_ID_VF_MSIX:
56a62fc8
JB		 3086 p->num_msix_vectors_vf = number;
3087 break;
406e734a 3088 case I40E_AQ_CAP_ID_FLEX10:
c78b953e
PO		 3089 if (major_rev == 1) {
3090 if (number == 1) {
3091 p->flex10_enable = true;
3092 p->flex10_capable = true;
3093 }
3094 } else {
3095 /* Capability revision >= 2 */
3096 if (number & 1)
3097 p->flex10_enable = true;
3098 if (number & 2)
3099 p->flex10_capable = true;
3100 }
3101 p->flex10_mode = logical_id;
3102 p->flex10_status = phys_id;
56a62fc8 3103 break;
406e734a 3104 case I40E_AQ_CAP_ID_CEM:
56a62fc8
JB		 3105 if (number == 1)
3106 p->mgmt_cem = true;
3107 break;
406e734a 3108 case I40E_AQ_CAP_ID_IWARP:
56a62fc8
JB		 3109 if (number == 1)
3110 p->iwarp = true;
3111 break;
406e734a 3112 case I40E_AQ_CAP_ID_LED:
56a62fc8
JB		 3113 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3114 p->led[phys_id] = true;
3115 break;
406e734a 3116 case I40E_AQ_CAP_ID_SDP:
56a62fc8
JB		 3117 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3118 p->sdp[phys_id] = true;
3119 break;
406e734a 3120 case I40E_AQ_CAP_ID_MDIO:
56a62fc8
JB		 3121 if (number == 1) {
3122 p->mdio_port_num = phys_id;
3123 p->mdio_port_mode = logical_id;
3124 }
3125 break;
406e734a 3126 case I40E_AQ_CAP_ID_1588:
56a62fc8
JB		 3127 if (number == 1)
3128 p->ieee_1588 = true;
3129 break;
406e734a 3130 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
56a62fc8
JB		 3131 p->fd = true;
3132 p->fd_filters_guaranteed = number;
3133 p->fd_filters_best_effort = logical_id;
3134 break;
406e734a 3135 case I40E_AQ_CAP_ID_WSR_PROT:
73b23402
KS		 3136 p->wr_csr_prot = (u64)number;
3137 p->wr_csr_prot |= (u64)logical_id << 32;
3138 break;
68a1c5a7
MK		 3139 case I40E_AQ_CAP_ID_NVM_MGMT:
3140 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3141 p->sec_rev_disabled = true;
3142 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3143 p->update_disabled = true;
3144 break;
56a62fc8
JB		 3145 default:
3146 break;
3147 }
3148 }
3149
f18ae100
VD		 3150 if (p->fcoe)
3151 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3152
566bb85d
VD		 3153 /* Software override ensuring FCoE is disabled if npar or mfp
3154 * mode because it is not supported in these modes.
3155 */
c78b953e 3156 if (p->npar_enable || p->flex10_enable)
566bb85d
VD		 3157 p->fcoe = false;
3158
9fee9db5
SN		 3159 /* count the enabled ports (aka the "not disabled" ports) */
3160 hw->num_ports = 0;
3161 for (i = 0; i < 4; i++) {
3162 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3163 u64 port_cfg = 0;
3164
3165 /* use AQ read to get the physical register offset instead
3166 * of the port relative offset
3167 */
3168 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3169 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3170 hw->num_ports++;
3171 }
3172
3173 valid_functions = p->valid_functions;
3174 num_functions = 0;
3175 while (valid_functions) {
3176 if (valid_functions & 1)
3177 num_functions++;
3178 valid_functions >>= 1;
3179 }
3180
3181 /* partition id is 1-based, and functions are evenly spread
3182 * across the ports as partitions
3183 */
3184 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3185 hw->num_partitions = num_functions / hw->num_ports;
3186
56a62fc8
JB		 3187 /* additional HW specific goodies that might
3188 * someday be HW version specific
3189 */
3190 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3191}
3192
3193/**
3194 * i40e_aq_discover_capabilities
3195 * @hw: pointer to the hw struct
3196 * @buff: a virtual buffer to hold the capabilities
3197 * @buff_size: Size of the virtual buffer
3198 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3199 * @list_type_opc: capabilities type to discover - pass in the command opcode
3200 * @cmd_details: pointer to command details structure or NULL
3201 *
3202 * Get the device capabilities descriptions from the firmware
3203 **/
3204i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3205 void *buff, u16 buff_size, u16 *data_size,
3206 enum i40e_admin_queue_opc list_type_opc,
3207 struct i40e_asq_cmd_details *cmd_details)
3208{
3209 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 3210 struct i40e_aq_desc desc;
8fb905b3 3211 i40e_status status = 0;
56a62fc8
JB		 3212
3213 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3214
3215 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3216 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3217 status = I40E_ERR_PARAM;
3218 goto exit;
3219 }
3220
3221 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3222
3223 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3224 if (buff_size > I40E_AQ_LARGE_BUF)
3225 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3226
3227 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3228 *data_size = le16_to_cpu(desc.datalen);
3229
3230 if (status)
3231 goto exit;
3232
3233 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3234 list_type_opc);
3235
3236exit:
3237 return status;
3238}
3239
cd552cb4
SN		 3240/**
3241 * i40e_aq_update_nvm
3242 * @hw: pointer to the hw struct
3243 * @module_pointer: module pointer location in words from the NVM beginning
3244 * @offset: byte offset from the module beginning
3245 * @length: length of the section to be written (in bytes from the offset)
3246 * @data: command buffer (size [bytes] = length)
3247 * @last_command: tells if this is the last command in a series
3248 * @cmd_details: pointer to command details structure or NULL
3249 *
3250 * Update the NVM using the admin queue commands
3251 **/
3252i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3253 u32 offset, u16 length, void *data,
3254 bool last_command,
3255 struct i40e_asq_cmd_details *cmd_details)
3256{
3257 struct i40e_aq_desc desc;
3258 struct i40e_aqc_nvm_update *cmd =
3259 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3260 i40e_status status;
3261
3262 /* In offset the highest byte must be zeroed. */
3263 if (offset & 0xFF000000) {
3264 status = I40E_ERR_PARAM;
3265 goto i40e_aq_update_nvm_exit;
3266 }
3267
3268 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3269
3270 /* If this is the last command in a series, set the proper flag. */
3271 if (last_command)
3272 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3273 cmd->module_pointer = module_pointer;
3274 cmd->offset = cpu_to_le32(offset);
3275 cmd->length = cpu_to_le16(length);
3276
3277 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3278 if (length > I40E_AQ_LARGE_BUF)
3279 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3280
3281 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3282
3283i40e_aq_update_nvm_exit:
3284 return status;
3285}
3286
56a62fc8
JB		 3287/**
3288 * i40e_aq_get_lldp_mib
3289 * @hw: pointer to the hw struct
3290 * @bridge_type: type of bridge requested
3291 * @mib_type: Local, Remote or both Local and Remote MIBs
3292 * @buff: pointer to a user supplied buffer to store the MIB block
3293 * @buff_size: size of the buffer (in bytes)
3294 * @local_len : length of the returned Local LLDP MIB
3295 * @remote_len: length of the returned Remote LLDP MIB
3296 * @cmd_details: pointer to command details structure or NULL
3297 *
3298 * Requests the complete LLDP MIB (entire packet).
3299 **/
3300i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3301 u8 mib_type, void *buff, u16 buff_size,
3302 u16 *local_len, u16 *remote_len,
3303 struct i40e_asq_cmd_details *cmd_details)
3304{
3305 struct i40e_aq_desc desc;
3306 struct i40e_aqc_lldp_get_mib *cmd =
3307 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3308 struct i40e_aqc_lldp_get_mib *resp =
3309 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3310 i40e_status status;
3311
3312 if (buff_size == 0 || !buff)
3313 return I40E_ERR_PARAM;
3314
3315 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3316 /* Indirect Command */
3317 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3318
3319 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3320 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3321 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3322
3323 desc.datalen = cpu_to_le16(buff_size);
3324
3325 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3326 if (buff_size > I40E_AQ_LARGE_BUF)
3327 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3328
3329 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3330 if (!status) {
3331 if (local_len != NULL)
3332 *local_len = le16_to_cpu(resp->local_len);
3333 if (remote_len != NULL)
3334 *remote_len = le16_to_cpu(resp->remote_len);
3335 }
3336
3337 return status;
3338}
3339
3340/**
3341 * i40e_aq_cfg_lldp_mib_change_event
3342 * @hw: pointer to the hw struct
3343 * @enable_update: Enable or Disable event posting
3344 * @cmd_details: pointer to command details structure or NULL
3345 *
3346 * Enable or Disable posting of an event on ARQ when LLDP MIB
3347 * associated with the interface changes
3348 **/
3349i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3350 bool enable_update,
3351 struct i40e_asq_cmd_details *cmd_details)
3352{
3353 struct i40e_aq_desc desc;
3354 struct i40e_aqc_lldp_update_mib *cmd =
3355 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3356 i40e_status status;
3357
3358 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3359
3360 if (!enable_update)
3361 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3362
3363 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3364
3365 return status;
3366}
3367
3368/**
3369 * i40e_aq_stop_lldp
3370 * @hw: pointer to the hw struct
3371 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3372 * @cmd_details: pointer to command details structure or NULL
3373 *
3374 * Stop or Shutdown the embedded LLDP Agent
3375 **/
3376i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3377 struct i40e_asq_cmd_details *cmd_details)
3378{
3379 struct i40e_aq_desc desc;
3380 struct i40e_aqc_lldp_stop *cmd =
3381 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3382 i40e_status status;
3383
3384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3385
3386 if (shutdown_agent)
3387 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3388
3389 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3390
3391 return status;
3392}
3393
3394/**
3395 * i40e_aq_start_lldp
3396 * @hw: pointer to the hw struct
3397 * @cmd_details: pointer to command details structure or NULL
3398 *
3399 * Start the embedded LLDP Agent on all ports.
3400 **/
3401i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3402 struct i40e_asq_cmd_details *cmd_details)
3403{
3404 struct i40e_aq_desc desc;
3405 struct i40e_aqc_lldp_start *cmd =
3406 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3407 i40e_status status;
3408
3409 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3410
3411 cmd->command = I40E_AQ_LLDP_AGENT_START;
3412
3413 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3414
3415 return status;
3416}
3417
9fa61dd2
NP		 3418/**
3419 * i40e_aq_get_cee_dcb_config
3420 * @hw: pointer to the hw struct
3421 * @buff: response buffer that stores CEE operational configuration
3422 * @buff_size: size of the buffer passed
3423 * @cmd_details: pointer to command details structure or NULL
3424 *
3425 * Get CEE DCBX mode operational configuration from firmware
3426 **/
3427i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3428 void *buff, u16 buff_size,
3429 struct i40e_asq_cmd_details *cmd_details)
3430{
3431 struct i40e_aq_desc desc;
3432 i40e_status status;
3433
3434 if (buff_size == 0 || !buff)
3435 return I40E_ERR_PARAM;
3436
3437 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3438
3439 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3440 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3441 cmd_details);
3442
3443 return status;
3444}
3445
a1c9a9d9
JK		 3446/**
3447 * i40e_aq_add_udp_tunnel
3448 * @hw: pointer to the hw struct
3449 * @udp_port: the UDP port to add
3450 * @header_len: length of the tunneling header length in DWords
3451 * @protocol_index: protocol index type
98d44381 3452 * @filter_index: pointer to filter index
a1c9a9d9
JK		 3453 * @cmd_details: pointer to command details structure or NULL
3454 **/
3455i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 3456 u16 udp_port, u8 protocol_index,
3457 u8 *filter_index,
a1c9a9d9
JK		 3458 struct i40e_asq_cmd_details *cmd_details)
3459{
3460 struct i40e_aq_desc desc;
3461 struct i40e_aqc_add_udp_tunnel *cmd =
3462 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3463 struct i40e_aqc_del_udp_tunnel_completion *resp =
3464 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3465 i40e_status status;
3466
3467 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3468
3469 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 3470 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 3471
3472 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3473
65d13461 3474 if (!status && filter_index)
a1c9a9d9
JK		 3475 *filter_index = resp->index;
3476
3477 return status;
3478}
3479
3480/**
3481 * i40e_aq_del_udp_tunnel
3482 * @hw: pointer to the hw struct
3483 * @index: filter index
3484 * @cmd_details: pointer to command details structure or NULL
3485 **/
3486i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3487 struct i40e_asq_cmd_details *cmd_details)
3488{
3489 struct i40e_aq_desc desc;
3490 struct i40e_aqc_remove_udp_tunnel *cmd =
3491 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3492 i40e_status status;
3493
3494 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3495
3496 cmd->index = index;
3497
3498 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3499
3500 return status;
3501}
3502
56a62fc8
JB		 3503/**
3504 * i40e_aq_delete_element - Delete switch element
3505 * @hw: pointer to the hw struct
3506 * @seid: the SEID to delete from the switch
3507 * @cmd_details: pointer to command details structure or NULL
3508 *
3509 * This deletes a switch element from the switch.
3510 **/
3511i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3512 struct i40e_asq_cmd_details *cmd_details)
3513{
3514 struct i40e_aq_desc desc;
3515 struct i40e_aqc_switch_seid *cmd =
3516 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3517 i40e_status status;
3518
3519 if (seid == 0)
3520 return I40E_ERR_PARAM;
3521
3522 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3523
3524 cmd->seid = cpu_to_le16(seid);
3525
3526 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3527
3528 return status;
3529}
3530
afb3ff0d
NP		 3531/**
3532 * i40e_aq_dcb_updated - DCB Updated Command
3533 * @hw: pointer to the hw struct
3534 * @cmd_details: pointer to command details structure or NULL
3535 *
3536 * EMP will return when the shared RPB settings have been
3537 * recomputed and modified. The retval field in the descriptor
3538 * will be set to 0 when RPB is modified.
3539 **/
3540i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3541 struct i40e_asq_cmd_details *cmd_details)
3542{
3543 struct i40e_aq_desc desc;
3544 i40e_status status;
3545
3546 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3547
3548 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3549
3550 return status;
3551}
3552
56a62fc8
JB		 3553/**
3554 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3555 * @hw: pointer to the hw struct
3556 * @seid: seid for the physical port/switching component/vsi
3557 * @buff: Indirect buffer to hold data parameters and response
3558 * @buff_size: Indirect buffer size
3559 * @opcode: Tx scheduler AQ command opcode
3560 * @cmd_details: pointer to command details structure or NULL
3561 *
3562 * Generic command handler for Tx scheduler AQ commands
3563 **/
3564static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3565 void *buff, u16 buff_size,
3566 enum i40e_admin_queue_opc opcode,
3567 struct i40e_asq_cmd_details *cmd_details)
3568{
3569 struct i40e_aq_desc desc;
3570 struct i40e_aqc_tx_sched_ind *cmd =
3571 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3572 i40e_status status;
3573 bool cmd_param_flag = false;
3574
3575 switch (opcode) {
3576 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3577 case i40e_aqc_opc_configure_vsi_tc_bw:
3578 case i40e_aqc_opc_enable_switching_comp_ets:
3579 case i40e_aqc_opc_modify_switching_comp_ets:
3580 case i40e_aqc_opc_disable_switching_comp_ets:
3581 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3582 case i40e_aqc_opc_configure_switching_comp_bw_config:
3583 cmd_param_flag = true;
3584 break;
3585 case i40e_aqc_opc_query_vsi_bw_config:
3586 case i40e_aqc_opc_query_vsi_ets_sla_config:
3587 case i40e_aqc_opc_query_switching_comp_ets_config:
3588 case i40e_aqc_opc_query_port_ets_config:
3589 case i40e_aqc_opc_query_switching_comp_bw_config:
3590 cmd_param_flag = false;
3591 break;
3592 default:
3593 return I40E_ERR_PARAM;
3594 }
3595
3596 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3597
3598 /* Indirect command */
3599 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3600 if (cmd_param_flag)
3601 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3602 if (buff_size > I40E_AQ_LARGE_BUF)
3603 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3604
3605 desc.datalen = cpu_to_le16(buff_size);
3606
3607 cmd->vsi_seid = cpu_to_le16(seid);
3608
3609 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3610
3611 return status;
3612}
3613
6b192891
MW		 3614/**
3615 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3616 * @hw: pointer to the hw struct
3617 * @seid: VSI seid
3618 * @credit: BW limit credits (0 = disabled)
3619 * @max_credit: Max BW limit credits
3620 * @cmd_details: pointer to command details structure or NULL
3621 **/
3622i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3623 u16 seid, u16 credit, u8 max_credit,
3624 struct i40e_asq_cmd_details *cmd_details)
3625{
3626 struct i40e_aq_desc desc;
3627 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3628 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3629 i40e_status status;
3630
3631 i40e_fill_default_direct_cmd_desc(&desc,
3632 i40e_aqc_opc_configure_vsi_bw_limit);
3633
3634 cmd->vsi_seid = cpu_to_le16(seid);
3635 cmd->credit = cpu_to_le16(credit);
3636 cmd->max_credit = max_credit;
3637
3638 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3639
3640 return status;
3641}
3642
56a62fc8
JB		 3643/**
3644 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3645 * @hw: pointer to the hw struct
3646 * @seid: VSI seid
3647 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3648 * @cmd_details: pointer to command details structure or NULL
3649 **/
3650i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3651 u16 seid,
3652 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3653 struct i40e_asq_cmd_details *cmd_details)
3654{
3655 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3656 i40e_aqc_opc_configure_vsi_tc_bw,
3657 cmd_details);
3658}
3659
afb3ff0d
NP		 3660/**
3661 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3662 * @hw: pointer to the hw struct
3663 * @seid: seid of the switching component connected to Physical Port
3664 * @ets_data: Buffer holding ETS parameters
3665 * @cmd_details: pointer to command details structure or NULL
3666 **/
3667i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3668 u16 seid,
3669 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3670 enum i40e_admin_queue_opc opcode,
3671 struct i40e_asq_cmd_details *cmd_details)
3672{
3673 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3674 sizeof(*ets_data), opcode, cmd_details);
3675}
3676
3677/**
3678 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3679 * @hw: pointer to the hw struct
3680 * @seid: seid of the switching component
3681 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3682 * @cmd_details: pointer to command details structure or NULL
3683 **/
3684i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3685 u16 seid,
3686 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3687 struct i40e_asq_cmd_details *cmd_details)
3688{
3689 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3690 i40e_aqc_opc_configure_switching_comp_bw_config,
3691 cmd_details);
3692}
3693
56a62fc8
JB		 3694/**
3695 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3696 * @hw: pointer to the hw struct
3697 * @seid: seid of the VSI
3698 * @bw_data: Buffer to hold VSI BW configuration
3699 * @cmd_details: pointer to command details structure or NULL
3700 **/
3701i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3702 u16 seid,
3703 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3704 struct i40e_asq_cmd_details *cmd_details)
3705{
3706 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3707 i40e_aqc_opc_query_vsi_bw_config,
3708 cmd_details);
3709}
3710
3711/**
3712 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3713 * @hw: pointer to the hw struct
3714 * @seid: seid of the VSI
3715 * @bw_data: Buffer to hold VSI BW configuration per TC
3716 * @cmd_details: pointer to command details structure or NULL
3717 **/
3718i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3719 u16 seid,
3720 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3721 struct i40e_asq_cmd_details *cmd_details)
3722{
3723 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3724 i40e_aqc_opc_query_vsi_ets_sla_config,
3725 cmd_details);
3726}
3727
3728/**
3729 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3730 * @hw: pointer to the hw struct
3731 * @seid: seid of the switching component
3732 * @bw_data: Buffer to hold switching component's per TC BW config
3733 * @cmd_details: pointer to command details structure or NULL
3734 **/
3735i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3736 u16 seid,
3737 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3738 struct i40e_asq_cmd_details *cmd_details)
3739{
3740 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3741 i40e_aqc_opc_query_switching_comp_ets_config,
3742 cmd_details);
3743}
3744
3745/**
3746 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3747 * @hw: pointer to the hw struct
3748 * @seid: seid of the VSI or switching component connected to Physical Port
3749 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3750 * @cmd_details: pointer to command details structure or NULL
3751 **/
3752i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3753 u16 seid,
3754 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3755 struct i40e_asq_cmd_details *cmd_details)
3756{
3757 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3758 i40e_aqc_opc_query_port_ets_config,
3759 cmd_details);
3760}
3761
3762/**
3763 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3764 * @hw: pointer to the hw struct
3765 * @seid: seid of the switching component
3766 * @bw_data: Buffer to hold switching component's BW configuration
3767 * @cmd_details: pointer to command details structure or NULL
3768 **/
3769i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3770 u16 seid,
3771 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3772 struct i40e_asq_cmd_details *cmd_details)
3773{
3774 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3775 i40e_aqc_opc_query_switching_comp_bw_config,
3776 cmd_details);
3777}
3778
3779/**
3780 * i40e_validate_filter_settings
3781 * @hw: pointer to the hardware structure
3782 * @settings: Filter control settings
3783 *
3784 * Check and validate the filter control settings passed.
3785 * The function checks for the valid filter/context sizes being
3786 * passed for FCoE and PE.
3787 *
3788 * Returns 0 if the values passed are valid and within
3789 * range else returns an error.
3790 **/
3791static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3792 struct i40e_filter_control_settings *settings)
3793{
3794 u32 fcoe_cntx_size, fcoe_filt_size;
3795 u32 pe_cntx_size, pe_filt_size;
467d729a 3796 u32 fcoe_fmax;
56a62fc8
JB		 3797 u32 val;
3798
3799 /* Validate FCoE settings passed */
3800 switch (settings->fcoe_filt_num) {
3801 case I40E_HASH_FILTER_SIZE_1K:
3802 case I40E_HASH_FILTER_SIZE_2K:
3803 case I40E_HASH_FILTER_SIZE_4K:
3804 case I40E_HASH_FILTER_SIZE_8K:
3805 case I40E_HASH_FILTER_SIZE_16K:
3806 case I40E_HASH_FILTER_SIZE_32K:
3807 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3808 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3809 break;
3810 default:
3811 return I40E_ERR_PARAM;
3812 }
3813
3814 switch (settings->fcoe_cntx_num) {
3815 case I40E_DMA_CNTX_SIZE_512:
3816 case I40E_DMA_CNTX_SIZE_1K:
3817 case I40E_DMA_CNTX_SIZE_2K:
3818 case I40E_DMA_CNTX_SIZE_4K:
3819 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3820 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3821 break;
3822 default:
3823 return I40E_ERR_PARAM;
3824 }
3825
3826 /* Validate PE settings passed */
3827 switch (settings->pe_filt_num) {
3828 case I40E_HASH_FILTER_SIZE_1K:
3829 case I40E_HASH_FILTER_SIZE_2K:
3830 case I40E_HASH_FILTER_SIZE_4K:
3831 case I40E_HASH_FILTER_SIZE_8K:
3832 case I40E_HASH_FILTER_SIZE_16K:
3833 case I40E_HASH_FILTER_SIZE_32K:
3834 case I40E_HASH_FILTER_SIZE_64K:
3835 case I40E_HASH_FILTER_SIZE_128K:
3836 case I40E_HASH_FILTER_SIZE_256K:
3837 case I40E_HASH_FILTER_SIZE_512K:
3838 case I40E_HASH_FILTER_SIZE_1M:
3839 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3840 pe_filt_size <<= (u32)settings->pe_filt_num;
3841 break;
3842 default:
3843 return I40E_ERR_PARAM;
3844 }
3845
3846 switch (settings->pe_cntx_num) {
3847 case I40E_DMA_CNTX_SIZE_512:
3848 case I40E_DMA_CNTX_SIZE_1K:
3849 case I40E_DMA_CNTX_SIZE_2K:
3850 case I40E_DMA_CNTX_SIZE_4K:
3851 case I40E_DMA_CNTX_SIZE_8K:
3852 case I40E_DMA_CNTX_SIZE_16K:
3853 case I40E_DMA_CNTX_SIZE_32K:
3854 case I40E_DMA_CNTX_SIZE_64K:
3855 case I40E_DMA_CNTX_SIZE_128K:
3856 case I40E_DMA_CNTX_SIZE_256K:
3857 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3858 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3859 break;
3860 default:
3861 return I40E_ERR_PARAM;
3862 }
3863
3864 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3865 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3866 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3867 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3868 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3869 return I40E_ERR_INVALID_SIZE;
3870
56a62fc8
JB		 3871 return 0;
3872}
3873
3874/**
3875 * i40e_set_filter_control
3876 * @hw: pointer to the hardware structure
3877 * @settings: Filter control settings
3878 *
3879 * Set the Queue Filters for PE/FCoE and enable filters required
3880 * for a single PF. It is expected that these settings are programmed
3881 * at the driver initialization time.
3882 **/
3883i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3884 struct i40e_filter_control_settings *settings)
3885{
3886 i40e_status ret = 0;
3887 u32 hash_lut_size = 0;
3888 u32 val;
3889
3890 if (!settings)
3891 return I40E_ERR_PARAM;
3892
3893 /* Validate the input settings */
3894 ret = i40e_validate_filter_settings(hw, settings);
3895 if (ret)
3896 return ret;
3897
3898 /* Read the PF Queue Filter control register */
f658137c 3899 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
56a62fc8
JB		 3900
3901 /* Program required PE hash buckets for the PF */
3902 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3903 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3904 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3905 /* Program required PE contexts for the PF */
3906 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3907 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3908 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3909
3910 /* Program required FCoE hash buckets for the PF */
3911 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3912 val |= ((u32)settings->fcoe_filt_num <<
3913 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3914 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3915 /* Program required FCoE DDP contexts for the PF */
3916 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3917 val |= ((u32)settings->fcoe_cntx_num <<
3918 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3919 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3920
3921 /* Program Hash LUT size for the PF */
3922 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3923 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3924 hash_lut_size = 1;
3925 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3926 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3927
3928 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3929 if (settings->enable_fdir)
3930 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3931 if (settings->enable_ethtype)
3932 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3933 if (settings->enable_macvlan)
3934 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3935
f658137c 3936 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
56a62fc8
JB		 3937
3938 return 0;
3939}
afb3ff0d
NP		 3940
3941/**
3942 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3943 * @hw: pointer to the hw struct
3944 * @mac_addr: MAC address to use in the filter
3945 * @ethtype: Ethertype to use in the filter
3946 * @flags: Flags that needs to be applied to the filter
3947 * @vsi_seid: seid of the control VSI
3948 * @queue: VSI queue number to send the packet to
3949 * @is_add: Add control packet filter if True else remove
3950 * @stats: Structure to hold information on control filter counts
3951 * @cmd_details: pointer to command details structure or NULL
3952 *
3953 * This command will Add or Remove control packet filter for a control VSI.
3954 * In return it will update the total number of perfect filter count in
3955 * the stats member.
3956 **/
3957i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3958 u8 *mac_addr, u16 ethtype, u16 flags,
3959 u16 vsi_seid, u16 queue, bool is_add,
3960 struct i40e_control_filter_stats *stats,
3961 struct i40e_asq_cmd_details *cmd_details)
3962{
3963 struct i40e_aq_desc desc;
3964 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3965 (struct i40e_aqc_add_remove_control_packet_filter *)
3966 &desc.params.raw;
3967 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3968 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3969 &desc.params.raw;
3970 i40e_status status;
3971
3972 if (vsi_seid == 0)
3973 return I40E_ERR_PARAM;
3974
3975 if (is_add) {
3976 i40e_fill_default_direct_cmd_desc(&desc,
3977 i40e_aqc_opc_add_control_packet_filter);
3978 cmd->queue = cpu_to_le16(queue);
3979 } else {
3980 i40e_fill_default_direct_cmd_desc(&desc,
3981 i40e_aqc_opc_remove_control_packet_filter);
3982 }
3983
3984 if (mac_addr)
6995b36c 3985 ether_addr_copy(cmd->mac, mac_addr);
afb3ff0d
NP		 3986
3987 cmd->etype = cpu_to_le16(ethtype);
3988 cmd->flags = cpu_to_le16(flags);
3989 cmd->seid = cpu_to_le16(vsi_seid);
3990
3991 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3992
3993 if (!status && stats) {
3994 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3995 stats->etype_used = le16_to_cpu(resp->etype_used);
3996 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3997 stats->etype_free = le16_to_cpu(resp->etype_free);
3998 }
3999
4000 return status;
4001}
4002
e7358f54
ASJ		 4003/**
4004 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4005 * @hw: pointer to the hw struct
4006 * @seid: VSI seid to add ethertype filter from
4007 **/
4008#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4009void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4010 u16 seid)
4011{
4012 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4013 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4014 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4015 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4016 i40e_status status;
4017
4018 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4019 seid, 0, true, NULL,
4020 NULL);
4021 if (status)
4022 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4023}
4024
f4492db1
GR		 4025/**
4026 * i40e_aq_alternate_read
4027 * @hw: pointer to the hardware structure
4028 * @reg_addr0: address of first dword to be read
4029 * @reg_val0: pointer for data read from 'reg_addr0'
4030 * @reg_addr1: address of second dword to be read
4031 * @reg_val1: pointer for data read from 'reg_addr1'
4032 *
4033 * Read one or two dwords from alternate structure. Fields are indicated
4034 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4035 * is not passed then only register at 'reg_addr0' is read.
4036 *
4037 **/
37a2973a
SN		 4038static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4039 u32 reg_addr0, u32 *reg_val0,
4040 u32 reg_addr1, u32 *reg_val1)
f4492db1
GR		 4041{
4042 struct i40e_aq_desc desc;
4043 struct i40e_aqc_alternate_write *cmd_resp =
4044 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4045 i40e_status status;
4046
4047 if (!reg_val0)
4048 return I40E_ERR_PARAM;
4049
4050 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4051 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4052 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4053
4054 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4055
4056 if (!status) {
4057 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4058
4059 if (reg_val1)
4060 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4061 }
4062
4063 return status;
4064}
4065
2fd75f31
NP		 4066/**
4067 * i40e_aq_resume_port_tx
4068 * @hw: pointer to the hardware structure
4069 * @cmd_details: pointer to command details structure or NULL
4070 *
4071 * Resume port's Tx traffic
4072 **/
4073i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4074 struct i40e_asq_cmd_details *cmd_details)
4075{
4076 struct i40e_aq_desc desc;
4077 i40e_status status;
4078
4079 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4080
4081 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4082
4083 return status;
4084}
4085
d4dfb81a
CS		 4086/**
4087 * i40e_set_pci_config_data - store PCI bus info
4088 * @hw: pointer to hardware structure
4089 * @link_status: the link status word from PCI config space
4090 *
4091 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4092 **/
4093void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4094{
4095 hw->bus.type = i40e_bus_type_pci_express;
4096
4097 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4098 case PCI_EXP_LNKSTA_NLW_X1:
4099 hw->bus.width = i40e_bus_width_pcie_x1;
4100 break;
4101 case PCI_EXP_LNKSTA_NLW_X2:
4102 hw->bus.width = i40e_bus_width_pcie_x2;
4103 break;
4104 case PCI_EXP_LNKSTA_NLW_X4:
4105 hw->bus.width = i40e_bus_width_pcie_x4;
4106 break;
4107 case PCI_EXP_LNKSTA_NLW_X8:
4108 hw->bus.width = i40e_bus_width_pcie_x8;
4109 break;
4110 default:
4111 hw->bus.width = i40e_bus_width_unknown;
4112 break;
4113 }
4114
4115 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4116 case PCI_EXP_LNKSTA_CLS_2_5GB:
4117 hw->bus.speed = i40e_bus_speed_2500;
4118 break;
4119 case PCI_EXP_LNKSTA_CLS_5_0GB:
4120 hw->bus.speed = i40e_bus_speed_5000;
4121 break;
4122 case PCI_EXP_LNKSTA_CLS_8_0GB:
4123 hw->bus.speed = i40e_bus_speed_8000;
4124 break;
4125 default:
4126 hw->bus.speed = i40e_bus_speed_unknown;
4127 break;
4128 }
4129}
f4492db1 4130
3169c323
JB		 4131/**
4132 * i40e_aq_debug_dump
4133 * @hw: pointer to the hardware structure
4134 * @cluster_id: specific cluster to dump
4135 * @table_id: table id within cluster
4136 * @start_index: index of line in the block to read
4137 * @buff_size: dump buffer size
4138 * @buff: dump buffer
4139 * @ret_buff_size: actual buffer size returned
4140 * @ret_next_table: next block to read
4141 * @ret_next_index: next index to read
4142 *
4143 * Dump internal FW/HW data for debug purposes.
4144 *
4145 **/
4146i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4147 u8 table_id, u32 start_index, u16 buff_size,
4148 void *buff, u16 *ret_buff_size,
4149 u8 *ret_next_table, u32 *ret_next_index,
4150 struct i40e_asq_cmd_details *cmd_details)
4151{
4152 struct i40e_aq_desc desc;
4153 struct i40e_aqc_debug_dump_internals *cmd =
4154 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4155 struct i40e_aqc_debug_dump_internals *resp =
4156 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4157 i40e_status status;
4158
4159 if (buff_size == 0 || !buff)
4160 return I40E_ERR_PARAM;
4161
4162 i40e_fill_default_direct_cmd_desc(&desc,
4163 i40e_aqc_opc_debug_dump_internals);
4164 /* Indirect Command */
4165 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4166 if (buff_size > I40E_AQ_LARGE_BUF)
4167 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4168
4169 cmd->cluster_id = cluster_id;
4170 cmd->table_id = table_id;
4171 cmd->idx = cpu_to_le32(start_index);
4172
4173 desc.datalen = cpu_to_le16(buff_size);
4174
4175 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4176 if (!status) {
4177 if (ret_buff_size)
4178 *ret_buff_size = le16_to_cpu(desc.datalen);
4179 if (ret_next_table)
4180 *ret_next_table = resp->table_id;
4181 if (ret_next_index)
4182 *ret_next_index = le32_to_cpu(resp->idx);
4183 }
4184
4185 return status;
4186}
4187
f4492db1
GR		 4188/**
4189 * i40e_read_bw_from_alt_ram
4190 * @hw: pointer to the hardware structure
4191 * @max_bw: pointer for max_bw read
4192 * @min_bw: pointer for min_bw read
4193 * @min_valid: pointer for bool that is true if min_bw is a valid value
4194 * @max_valid: pointer for bool that is true if max_bw is a valid value
4195 *
4196 * Read bw from the alternate ram for the given pf
4197 **/
4198i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4199 u32 *max_bw, u32 *min_bw,
4200 bool *min_valid, bool *max_valid)
4201{
4202 i40e_status status;
4203 u32 max_bw_addr, min_bw_addr;
4204
4205 /* Calculate the address of the min/max bw registers */
4206 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4207 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4208 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4209 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4210 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4211 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4212
4213 /* Read the bandwidths from alt ram */
4214 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4215 min_bw_addr, min_bw);
4216
4217 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4218 *min_valid = true;
4219 else
4220 *min_valid = false;
4221
4222 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4223 *max_valid = true;
4224 else
4225 *max_valid = false;
4226
4227 return status;
4228}
4229
4230/**
4231 * i40e_aq_configure_partition_bw
4232 * @hw: pointer to the hardware structure
4233 * @bw_data: Buffer holding valid pfs and bw limits
4234 * @cmd_details: pointer to command details
4235 *
4236 * Configure partitions guaranteed/max bw
4237 **/
4238i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4239 struct i40e_aqc_configure_partition_bw_data *bw_data,
4240 struct i40e_asq_cmd_details *cmd_details)
4241{
4242 i40e_status status;
4243 struct i40e_aq_desc desc;
4244 u16 bwd_size = sizeof(*bw_data);
4245
4246 i40e_fill_default_direct_cmd_desc(&desc,
4247 i40e_aqc_opc_configure_partition_bw);
4248
4249 /* Indirect command */
4250 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4251 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4252
4253 if (bwd_size > I40E_AQ_LARGE_BUF)
4254 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4255
4256 desc.datalen = cpu_to_le16(bwd_size);
4257
4258 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4259 cmd_details);
4260
4261 return status;
4262}
fd077cd3
CW		 4263
4264/**
4265 * i40e_read_phy_register
4266 * @hw: pointer to the HW structure
4267 * @page: registers page number
4268 * @reg: register address in the page
4269 * @phy_adr: PHY address on MDIO interface
4270 * @value: PHY register value
4271 *
4272 * Reads specified PHY register value
4273 **/
4274i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4275 u8 page, u16 reg, u8 phy_addr,
4276 u16 *value)
4277{
4278 i40e_status status = I40E_ERR_TIMEOUT;
4279 u32 command = 0;
4280 u16 retry = 1000;
4281 u8 port_num = hw->func_caps.mdio_port_num;
4282
4283 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4284 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4285 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4286 (I40E_MDIO_OPCODE_ADDRESS) |
4287 (I40E_MDIO_STCODE) |
4288 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4289 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4290 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4291 do {
4292 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4293 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4294 status = 0;
4295 break;
4296 }
4297 usleep_range(10, 20);
4298 retry--;
4299 } while (retry);
4300
4301 if (status) {
4302 i40e_debug(hw, I40E_DEBUG_PHY,
4303 "PHY: Can't write command to external PHY.\n");
4304 goto phy_read_end;
4305 }
4306
4307 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4308 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4309 (I40E_MDIO_OPCODE_READ) |
4310 (I40E_MDIO_STCODE) |
4311 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4312 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4313 status = I40E_ERR_TIMEOUT;
4314 retry = 1000;
4315 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4316 do {
4317 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4318 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4319 status = 0;
4320 break;
4321 }
4322 usleep_range(10, 20);
4323 retry--;
4324 } while (retry);
4325
4326 if (!status) {
4327 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4328 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4329 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4330 } else {
4331 i40e_debug(hw, I40E_DEBUG_PHY,
4332 "PHY: Can't read register value from external PHY.\n");
4333 }
4334
4335phy_read_end:
4336 return status;
4337}
4338
4339/**
4340 * i40e_write_phy_register
4341 * @hw: pointer to the HW structure
4342 * @page: registers page number
4343 * @reg: register address in the page
4344 * @phy_adr: PHY address on MDIO interface
4345 * @value: PHY register value
4346 *
4347 * Writes value to specified PHY register
4348 **/
4349i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4350 u8 page, u16 reg, u8 phy_addr,
4351 u16 value)
4352{
4353 i40e_status status = I40E_ERR_TIMEOUT;
4354 u32 command = 0;
4355 u16 retry = 1000;
4356 u8 port_num = hw->func_caps.mdio_port_num;
4357
4358 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4359 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4360 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4361 (I40E_MDIO_OPCODE_ADDRESS) |
4362 (I40E_MDIO_STCODE) |
4363 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4364 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4365 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4366 do {
4367 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4368 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4369 status = 0;
4370 break;
4371 }
4372 usleep_range(10, 20);
4373 retry--;
4374 } while (retry);
4375 if (status) {
4376 i40e_debug(hw, I40E_DEBUG_PHY,
4377 "PHY: Can't write command to external PHY.\n");
4378 goto phy_write_end;
4379 }
4380
4381 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4382 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4383
4384 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4385 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4386 (I40E_MDIO_OPCODE_WRITE) |
4387 (I40E_MDIO_STCODE) |
4388 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4389 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4390 status = I40E_ERR_TIMEOUT;
4391 retry = 1000;
4392 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4393 do {
4394 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4395 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4396 status = 0;
4397 break;
4398 }
4399 usleep_range(10, 20);
4400 retry--;
4401 } while (retry);
4402
4403phy_write_end:
4404 return status;
4405}
4406
4407/**
4408 * i40e_get_phy_address
4409 * @hw: pointer to the HW structure
4410 * @dev_num: PHY port num that address we want
4411 * @phy_addr: Returned PHY address
4412 *
4413 * Gets PHY address for current port
4414 **/
4415u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4416{
4417 u8 port_num = hw->func_caps.mdio_port_num;
4418 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4419
4420 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4421}
4422
4423/**
4424 * i40e_blink_phy_led
4425 * @hw: pointer to the HW structure
4426 * @time: time how long led will blinks in secs
4427 * @interval: gap between LED on and off in msecs
4428 *
4429 * Blinks PHY link LED
4430 **/
4431i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4432 u32 time, u32 interval)
4433{
4434 i40e_status status = 0;
4435 u32 i;
4436 u16 led_ctl;
4437 u16 gpio_led_port;
4438 u16 led_reg;
4439 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4440 u8 phy_addr = 0;
4441 u8 port_num;
4442
4443 i = rd32(hw, I40E_PFGEN_PORTNUM);
4444 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4445 phy_addr = i40e_get_phy_address(hw, port_num);
4446
4447 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4448 led_addr++) {
4449 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4450 led_addr, phy_addr, &led_reg);
4451 if (status)
4452 goto phy_blinking_end;
4453 led_ctl = led_reg;
4454 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4455 led_reg = 0;
4456 status = i40e_write_phy_register(hw,
4457 I40E_PHY_COM_REG_PAGE,
4458 led_addr, phy_addr,
4459 led_reg);
4460 if (status)
4461 goto phy_blinking_end;
4462 break;
4463 }
4464 }
4465
4466 if (time > 0 && interval > 0) {
4467 for (i = 0; i < time * 1000; i += interval) {
4468 status = i40e_read_phy_register(hw,
4469 I40E_PHY_COM_REG_PAGE,
4470 led_addr, phy_addr,
4471 &led_reg);
4472 if (status)
4473 goto restore_config;
4474 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4475 led_reg = 0;
4476 else
4477 led_reg = I40E_PHY_LED_MANUAL_ON;
4478 status = i40e_write_phy_register(hw,
4479 I40E_PHY_COM_REG_PAGE,
4480 led_addr, phy_addr,
4481 led_reg);
4482 if (status)
4483 goto restore_config;
4484 msleep(interval);
4485 }
4486 }
4487
4488restore_config:
4489 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4490 phy_addr, led_ctl);
4491
4492phy_blinking_end:
4493 return status;
4494}
4495
4496/**
4497 * i40e_led_get_phy - return current on/off mode
4498 * @hw: pointer to the hw struct
4499 * @led_addr: address of led register to use
4500 * @val: original value of register to use
4501 *
4502 **/
4503i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4504 u16 *val)
4505{
4506 i40e_status status = 0;
4507 u16 gpio_led_port;
4508 u8 phy_addr = 0;
4509 u16 reg_val;
4510 u16 temp_addr;
4511 u8 port_num;
4512 u32 i;
4513
4514 temp_addr = I40E_PHY_LED_PROV_REG_1;
4515 i = rd32(hw, I40E_PFGEN_PORTNUM);
4516 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4517 phy_addr = i40e_get_phy_address(hw, port_num);
4518
4519 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4520 temp_addr++) {
4521 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4522 temp_addr, phy_addr, &reg_val);
4523 if (status)
4524 return status;
4525 *val = reg_val;
4526 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4527 *led_addr = temp_addr;
4528 break;
4529 }
4530 }
4531 return status;
4532}
4533
4534/**
4535 * i40e_led_set_phy
4536 * @hw: pointer to the HW structure
4537 * @on: true or false
4538 * @mode: original val plus bit for set or ignore
4539 * Set led's on or off when controlled by the PHY
4540 *
4541 **/
4542i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4543 u16 led_addr, u32 mode)
4544{
4545 i40e_status status = 0;
4546 u16 led_ctl = 0;
4547 u16 led_reg = 0;
4548 u8 phy_addr = 0;
4549 u8 port_num;
4550 u32 i;
4551
4552 i = rd32(hw, I40E_PFGEN_PORTNUM);
4553 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4554 phy_addr = i40e_get_phy_address(hw, port_num);
4555
4556 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4557 phy_addr, &led_reg);
4558 if (status)
4559 return status;
4560 led_ctl = led_reg;
4561 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4562 led_reg = 0;
4563 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4564 led_addr, phy_addr, led_reg);
4565 if (status)
4566 return status;
4567 }
4568 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4569 led_addr, phy_addr, &led_reg);
4570 if (status)
4571 goto restore_config;
4572 if (on)
4573 led_reg = I40E_PHY_LED_MANUAL_ON;
4574 else
4575 led_reg = 0;
4576 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4577 led_addr, phy_addr, led_reg);
4578 if (status)
4579 goto restore_config;
4580 if (mode & I40E_PHY_LED_MODE_ORIG) {
4581 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4582 status = i40e_write_phy_register(hw,
4583 I40E_PHY_COM_REG_PAGE,
4584 led_addr, phy_addr, led_ctl);
4585 }
4586 return status;
4587restore_config:
4588 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4589 phy_addr, led_ctl);
4590 return status;
4591}
f658137c
SN		 4592
4593/**
4594 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4595 * @hw: pointer to the hw struct
4596 * @reg_addr: register address
4597 * @reg_val: ptr to register value
4598 * @cmd_details: pointer to command details structure or NULL
4599 *
4600 * Use the firmware to read the Rx control register,
4601 * especially useful if the Rx unit is under heavy pressure
4602 **/
4603i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4604 u32 reg_addr, u32 *reg_val,
4605 struct i40e_asq_cmd_details *cmd_details)
4606{
4607 struct i40e_aq_desc desc;
4608 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4609 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4610 i40e_status status;
4611
4612 if (!reg_val)
4613 return I40E_ERR_PARAM;
4614
4615 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4616
4617 cmd_resp->address = cpu_to_le32(reg_addr);
4618
4619 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4620
4621 if (status == 0)
4622 *reg_val = le32_to_cpu(cmd_resp->value);
4623
4624 return status;
4625}
4626
4627/**
4628 * i40e_read_rx_ctl - read from an Rx control register
4629 * @hw: pointer to the hw struct
4630 * @reg_addr: register address
4631 **/
4632u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4633{
4634 i40e_status status = 0;
4635 bool use_register;
4636 int retry = 5;
4637 u32 val = 0;
4638
4639 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4640 if (!use_register) {
4641do_retry:
4642 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4643 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4644 usleep_range(1000, 2000);
4645 retry--;
4646 goto do_retry;
4647 }
4648 }
4649
4650 /* if the AQ access failed, try the old-fashioned way */
4651 if (status || use_register)
4652 val = rd32(hw, reg_addr);
4653
4654 return val;
4655}
4656
4657/**
4658 * i40e_aq_rx_ctl_write_register
4659 * @hw: pointer to the hw struct
4660 * @reg_addr: register address
4661 * @reg_val: register value
4662 * @cmd_details: pointer to command details structure or NULL
4663 *
4664 * Use the firmware to write to an Rx control register,
4665 * especially useful if the Rx unit is under heavy pressure
4666 **/
4667i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4668 u32 reg_addr, u32 reg_val,
4669 struct i40e_asq_cmd_details *cmd_details)
4670{
4671 struct i40e_aq_desc desc;
4672 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4673 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4674 i40e_status status;
4675
4676 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4677
4678 cmd->address = cpu_to_le32(reg_addr);
4679 cmd->value = cpu_to_le32(reg_val);
4680
4681 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4682
4683 return status;
4684}
4685
4686/**
4687 * i40e_write_rx_ctl - write to an Rx control register
4688 * @hw: pointer to the hw struct
4689 * @reg_addr: register address
4690 * @reg_val: register value
4691 **/
4692void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
4693{
4694 i40e_status status = 0;
4695 bool use_register;
4696 int retry = 5;
4697
4698 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4699 if (!use_register) {
4700do_retry:
4701 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
4702 reg_val, NULL);
4703 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4704 usleep_range(1000, 2000);
4705 retry--;
4706 goto do_retry;
4707 }
4708 }
4709
4710 /* if the AQ access failed, try the old-fashioned way */
4711 if (status || use_register)
4712 wr32(hw, reg_addr, reg_val);
4713}
Linux kernel - Deliverables
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