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i40e: move nway reset
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e
SN		 46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
ab60085e
SN		 50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
56a62fc8
JB		 53 hw->mac.type = I40E_MAC_XL710;
54 break;
ab60085e
SN		 55 case I40E_DEV_ID_VF:
56 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 57 hw->mac.type = I40E_MAC_VF;
58 break;
59 default:
60 hw->mac.type = I40E_MAC_GENERIC;
61 break;
62 }
63 } else {
64 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
65 }
66
67 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
68 hw->mac.type, status);
69 return status;
70}
71
72/**
73 * i40e_debug_aq
74 * @hw: debug mask related to admin queue
98d44381
JK		 75 * @mask: debug mask
76 * @desc: pointer to admin queue descriptor
56a62fc8
JB		 77 * @buffer: pointer to command buffer
78 *
79 * Dumps debug log about adminq command with descriptor contents.
80 **/
81void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
82 void *buffer)
83{
84 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
85 u8 *aq_buffer = (u8 *)buffer;
86 u32 data[4];
87 u32 i = 0;
88
89 if ((!(mask & hw->debug_mask)) || (desc == NULL))
90 return;
91
92 i40e_debug(hw, mask,
93 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
94 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
95 aq_desc->retval);
96 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
97 aq_desc->cookie_high, aq_desc->cookie_low);
98 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
99 aq_desc->params.internal.param0,
100 aq_desc->params.internal.param1);
101 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
102 aq_desc->params.external.addr_high,
103 aq_desc->params.external.addr_low);
104
105 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
106 memset(data, 0, sizeof(data));
107 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
108 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
109 data[((i % 16) / 4)] |=
110 ((u32)aq_buffer[i]) << (8 * (i % 4));
111 if ((i % 16) == 15) {
112 i40e_debug(hw, mask,
113 "\t0x%04X %08X %08X %08X %08X\n",
114 i - 15, data[0], data[1], data[2],
115 data[3]);
116 memset(data, 0, sizeof(data));
117 }
118 }
119 if ((i % 16) != 0)
120 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
121 i - (i % 16), data[0], data[1], data[2],
122 data[3]);
123 }
124}
125
e1860d8f
ASJ		 126/**
127 * i40e_check_asq_alive
128 * @hw: pointer to the hw struct
129 *
130 * Returns true if Queue is enabled else false.
131 **/
132bool i40e_check_asq_alive(struct i40e_hw *hw)
133{
8b833b4f
KS		 134 if (hw->aq.asq.len)
135 return !!(rd32(hw, hw->aq.asq.len) &
136 I40E_PF_ATQLEN_ATQENABLE_MASK);
137 else
138 return false;
e1860d8f
ASJ		 139}
140
141/**
142 * i40e_aq_queue_shutdown
143 * @hw: pointer to the hw struct
144 * @unloading: is the driver unloading itself
145 *
146 * Tell the Firmware that we're shutting down the AdminQ and whether
147 * or not the driver is unloading as well.
148 **/
149i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
150 bool unloading)
151{
152 struct i40e_aq_desc desc;
153 struct i40e_aqc_queue_shutdown *cmd =
154 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
155 i40e_status status;
156
157 i40e_fill_default_direct_cmd_desc(&desc,
158 i40e_aqc_opc_queue_shutdown);
159
160 if (unloading)
161 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
162 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
163
164 return status;
165}
166
206812b5
JB		 167/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
168 * hardware to a bit-field that can be used by SW to more easily determine the
169 * packet type.
170 *
171 * Macros are used to shorten the table lines and make this table human
172 * readable.
173 *
174 * We store the PTYPE in the top byte of the bit field - this is just so that
175 * we can check that the table doesn't have a row missing, as the index into
176 * the table should be the PTYPE.
177 *
178 * Typical work flow:
179 *
180 * IF NOT i40e_ptype_lookup[ptype].known
181 * THEN
182 * Packet is unknown
183 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
184 * Use the rest of the fields to look at the tunnels, inner protocols, etc
185 * ELSE
186 * Use the enum i40e_rx_l2_ptype to decode the packet type
187 * ENDIF
188 */
189
190/* macro to make the table lines short */
191#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
192 { PTYPE, \
193 1, \
194 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
195 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
196 I40E_RX_PTYPE_##OUTER_FRAG, \
197 I40E_RX_PTYPE_TUNNEL_##T, \
198 I40E_RX_PTYPE_TUNNEL_END_##TE, \
199 I40E_RX_PTYPE_##TEF, \
200 I40E_RX_PTYPE_INNER_PROT_##I, \
201 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
202
203#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
204 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
205
206/* shorter macros makes the table fit but are terse */
207#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
208#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
209#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
210
211/* Lookup table mapping the HW PTYPE to the bit field for decoding */
212struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
213 /* L2 Packet types */
214 I40E_PTT_UNUSED_ENTRY(0),
215 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
216 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
217 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
218 I40E_PTT_UNUSED_ENTRY(4),
219 I40E_PTT_UNUSED_ENTRY(5),
220 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
222 I40E_PTT_UNUSED_ENTRY(8),
223 I40E_PTT_UNUSED_ENTRY(9),
224 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
225 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
226 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
227 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
228 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
229 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
230 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236
237 /* Non Tunneled IPv4 */
238 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
241 I40E_PTT_UNUSED_ENTRY(25),
242 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
243 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
244 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
245
246 /* IPv4 --> IPv4 */
247 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
248 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
249 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
250 I40E_PTT_UNUSED_ENTRY(32),
251 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
252 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
253 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
254
255 /* IPv4 --> IPv6 */
256 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
257 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
258 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
259 I40E_PTT_UNUSED_ENTRY(39),
260 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
261 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
262 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
263
264 /* IPv4 --> GRE/NAT */
265 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
266
267 /* IPv4 --> GRE/NAT --> IPv4 */
268 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
269 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
270 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
271 I40E_PTT_UNUSED_ENTRY(47),
272 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
273 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
274 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
275
276 /* IPv4 --> GRE/NAT --> IPv6 */
277 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
278 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
279 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
280 I40E_PTT_UNUSED_ENTRY(54),
281 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
282 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
283 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
284
285 /* IPv4 --> GRE/NAT --> MAC */
286 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
287
288 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
289 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
290 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
291 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
292 I40E_PTT_UNUSED_ENTRY(62),
293 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
294 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
295 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
296
297 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
298 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
299 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
300 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
301 I40E_PTT_UNUSED_ENTRY(69),
302 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
303 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
304 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
305
306 /* IPv4 --> GRE/NAT --> MAC/VLAN */
307 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
308
309 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
310 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
311 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
312 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
313 I40E_PTT_UNUSED_ENTRY(77),
314 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
315 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
316 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
317
318 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
319 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
320 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
321 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
322 I40E_PTT_UNUSED_ENTRY(84),
323 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
324 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
325 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
326
327 /* Non Tunneled IPv6 */
328 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
329 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
330 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
331 I40E_PTT_UNUSED_ENTRY(91),
332 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
333 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
334 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
335
336 /* IPv6 --> IPv4 */
337 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
338 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
339 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
340 I40E_PTT_UNUSED_ENTRY(98),
341 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
342 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
343 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
344
345 /* IPv6 --> IPv6 */
346 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
347 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
348 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
349 I40E_PTT_UNUSED_ENTRY(105),
350 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
351 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
352 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
353
354 /* IPv6 --> GRE/NAT */
355 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
356
357 /* IPv6 --> GRE/NAT -> IPv4 */
358 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
359 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
360 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
361 I40E_PTT_UNUSED_ENTRY(113),
362 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
363 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
364 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
365
366 /* IPv6 --> GRE/NAT -> IPv6 */
367 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
368 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
369 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
370 I40E_PTT_UNUSED_ENTRY(120),
371 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
372 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
373 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
374
375 /* IPv6 --> GRE/NAT -> MAC */
376 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
377
378 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
379 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
380 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
381 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
382 I40E_PTT_UNUSED_ENTRY(128),
383 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
384 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
385 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
386
387 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
388 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
389 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
390 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
391 I40E_PTT_UNUSED_ENTRY(135),
392 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
393 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
394 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
395
396 /* IPv6 --> GRE/NAT -> MAC/VLAN */
397 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
398
399 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
400 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
401 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
402 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
403 I40E_PTT_UNUSED_ENTRY(143),
404 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
405 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
406 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
407
408 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
409 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
410 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
411 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
412 I40E_PTT_UNUSED_ENTRY(150),
413 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
414 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
415 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
416
417 /* unused entries */
418 I40E_PTT_UNUSED_ENTRY(154),
419 I40E_PTT_UNUSED_ENTRY(155),
420 I40E_PTT_UNUSED_ENTRY(156),
421 I40E_PTT_UNUSED_ENTRY(157),
422 I40E_PTT_UNUSED_ENTRY(158),
423 I40E_PTT_UNUSED_ENTRY(159),
424
425 I40E_PTT_UNUSED_ENTRY(160),
426 I40E_PTT_UNUSED_ENTRY(161),
427 I40E_PTT_UNUSED_ENTRY(162),
428 I40E_PTT_UNUSED_ENTRY(163),
429 I40E_PTT_UNUSED_ENTRY(164),
430 I40E_PTT_UNUSED_ENTRY(165),
431 I40E_PTT_UNUSED_ENTRY(166),
432 I40E_PTT_UNUSED_ENTRY(167),
433 I40E_PTT_UNUSED_ENTRY(168),
434 I40E_PTT_UNUSED_ENTRY(169),
435
436 I40E_PTT_UNUSED_ENTRY(170),
437 I40E_PTT_UNUSED_ENTRY(171),
438 I40E_PTT_UNUSED_ENTRY(172),
439 I40E_PTT_UNUSED_ENTRY(173),
440 I40E_PTT_UNUSED_ENTRY(174),
441 I40E_PTT_UNUSED_ENTRY(175),
442 I40E_PTT_UNUSED_ENTRY(176),
443 I40E_PTT_UNUSED_ENTRY(177),
444 I40E_PTT_UNUSED_ENTRY(178),
445 I40E_PTT_UNUSED_ENTRY(179),
446
447 I40E_PTT_UNUSED_ENTRY(180),
448 I40E_PTT_UNUSED_ENTRY(181),
449 I40E_PTT_UNUSED_ENTRY(182),
450 I40E_PTT_UNUSED_ENTRY(183),
451 I40E_PTT_UNUSED_ENTRY(184),
452 I40E_PTT_UNUSED_ENTRY(185),
453 I40E_PTT_UNUSED_ENTRY(186),
454 I40E_PTT_UNUSED_ENTRY(187),
455 I40E_PTT_UNUSED_ENTRY(188),
456 I40E_PTT_UNUSED_ENTRY(189),
457
458 I40E_PTT_UNUSED_ENTRY(190),
459 I40E_PTT_UNUSED_ENTRY(191),
460 I40E_PTT_UNUSED_ENTRY(192),
461 I40E_PTT_UNUSED_ENTRY(193),
462 I40E_PTT_UNUSED_ENTRY(194),
463 I40E_PTT_UNUSED_ENTRY(195),
464 I40E_PTT_UNUSED_ENTRY(196),
465 I40E_PTT_UNUSED_ENTRY(197),
466 I40E_PTT_UNUSED_ENTRY(198),
467 I40E_PTT_UNUSED_ENTRY(199),
468
469 I40E_PTT_UNUSED_ENTRY(200),
470 I40E_PTT_UNUSED_ENTRY(201),
471 I40E_PTT_UNUSED_ENTRY(202),
472 I40E_PTT_UNUSED_ENTRY(203),
473 I40E_PTT_UNUSED_ENTRY(204),
474 I40E_PTT_UNUSED_ENTRY(205),
475 I40E_PTT_UNUSED_ENTRY(206),
476 I40E_PTT_UNUSED_ENTRY(207),
477 I40E_PTT_UNUSED_ENTRY(208),
478 I40E_PTT_UNUSED_ENTRY(209),
479
480 I40E_PTT_UNUSED_ENTRY(210),
481 I40E_PTT_UNUSED_ENTRY(211),
482 I40E_PTT_UNUSED_ENTRY(212),
483 I40E_PTT_UNUSED_ENTRY(213),
484 I40E_PTT_UNUSED_ENTRY(214),
485 I40E_PTT_UNUSED_ENTRY(215),
486 I40E_PTT_UNUSED_ENTRY(216),
487 I40E_PTT_UNUSED_ENTRY(217),
488 I40E_PTT_UNUSED_ENTRY(218),
489 I40E_PTT_UNUSED_ENTRY(219),
490
491 I40E_PTT_UNUSED_ENTRY(220),
492 I40E_PTT_UNUSED_ENTRY(221),
493 I40E_PTT_UNUSED_ENTRY(222),
494 I40E_PTT_UNUSED_ENTRY(223),
495 I40E_PTT_UNUSED_ENTRY(224),
496 I40E_PTT_UNUSED_ENTRY(225),
497 I40E_PTT_UNUSED_ENTRY(226),
498 I40E_PTT_UNUSED_ENTRY(227),
499 I40E_PTT_UNUSED_ENTRY(228),
500 I40E_PTT_UNUSED_ENTRY(229),
501
502 I40E_PTT_UNUSED_ENTRY(230),
503 I40E_PTT_UNUSED_ENTRY(231),
504 I40E_PTT_UNUSED_ENTRY(232),
505 I40E_PTT_UNUSED_ENTRY(233),
506 I40E_PTT_UNUSED_ENTRY(234),
507 I40E_PTT_UNUSED_ENTRY(235),
508 I40E_PTT_UNUSED_ENTRY(236),
509 I40E_PTT_UNUSED_ENTRY(237),
510 I40E_PTT_UNUSED_ENTRY(238),
511 I40E_PTT_UNUSED_ENTRY(239),
512
513 I40E_PTT_UNUSED_ENTRY(240),
514 I40E_PTT_UNUSED_ENTRY(241),
515 I40E_PTT_UNUSED_ENTRY(242),
516 I40E_PTT_UNUSED_ENTRY(243),
517 I40E_PTT_UNUSED_ENTRY(244),
518 I40E_PTT_UNUSED_ENTRY(245),
519 I40E_PTT_UNUSED_ENTRY(246),
520 I40E_PTT_UNUSED_ENTRY(247),
521 I40E_PTT_UNUSED_ENTRY(248),
522 I40E_PTT_UNUSED_ENTRY(249),
523
524 I40E_PTT_UNUSED_ENTRY(250),
525 I40E_PTT_UNUSED_ENTRY(251),
526 I40E_PTT_UNUSED_ENTRY(252),
527 I40E_PTT_UNUSED_ENTRY(253),
528 I40E_PTT_UNUSED_ENTRY(254),
529 I40E_PTT_UNUSED_ENTRY(255)
530};
531
532
56a62fc8
JB		 533/**
534 * i40e_init_shared_code - Initialize the shared code
535 * @hw: pointer to hardware structure
536 *
537 * This assigns the MAC type and PHY code and inits the NVM.
538 * Does not touch the hardware. This function must be called prior to any
539 * other function in the shared code. The i40e_hw structure should be
540 * memset to 0 prior to calling this function. The following fields in
541 * hw structure should be filled in prior to calling this function:
542 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
543 * subsystem_vendor_id, and revision_id
544 **/
545i40e_status i40e_init_shared_code(struct i40e_hw *hw)
546{
547 i40e_status status = 0;
548 u32 reg;
549
56a62fc8
JB		 550 i40e_set_mac_type(hw);
551
552 switch (hw->mac.type) {
553 case I40E_MAC_XL710:
554 break;
555 default:
556 return I40E_ERR_DEVICE_NOT_SUPPORTED;
557 break;
558 }
559
af89d26c
SN		 560 hw->phy.get_link_info = true;
561
562 /* Determine port number */
563 reg = rd32(hw, I40E_PFGEN_PORTNUM);
564 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
565 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
566 hw->port = (u8)reg;
567
5f9116ac
SN		 568 /* Determine the PF number based on the PCI fn */
569 reg = rd32(hw, I40E_GLPCI_CAPSUP);
570 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
571 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
572 else
573 hw->pf_id = (u8)hw->bus.func;
574
56a62fc8
JB		 575 status = i40e_init_nvm(hw);
576 return status;
577}
578
579/**
580 * i40e_aq_mac_address_read - Retrieve the MAC addresses
581 * @hw: pointer to the hw struct
582 * @flags: a return indicator of what addresses were added to the addr store
583 * @addrs: the requestor's mac addr store
584 * @cmd_details: pointer to command details structure or NULL
585 **/
586static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
587 u16 *flags,
588 struct i40e_aqc_mac_address_read_data *addrs,
589 struct i40e_asq_cmd_details *cmd_details)
590{
591 struct i40e_aq_desc desc;
592 struct i40e_aqc_mac_address_read *cmd_data =
593 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
594 i40e_status status;
595
596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
597 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
598
599 status = i40e_asq_send_command(hw, &desc, addrs,
600 sizeof(*addrs), cmd_details);
601 *flags = le16_to_cpu(cmd_data->command_flags);
602
603 return status;
604}
605
606/**
607 * i40e_aq_mac_address_write - Change the MAC addresses
608 * @hw: pointer to the hw struct
609 * @flags: indicates which MAC to be written
610 * @mac_addr: address to write
611 * @cmd_details: pointer to command details structure or NULL
612 **/
613i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
614 u16 flags, u8 *mac_addr,
615 struct i40e_asq_cmd_details *cmd_details)
616{
617 struct i40e_aq_desc desc;
618 struct i40e_aqc_mac_address_write *cmd_data =
619 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
620 i40e_status status;
621
622 i40e_fill_default_direct_cmd_desc(&desc,
623 i40e_aqc_opc_mac_address_write);
624 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 625 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
626 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
627 ((u32)mac_addr[3] << 16) |
628 ((u32)mac_addr[4] << 8) |
629 mac_addr[5]);
56a62fc8
JB		 630
631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
632
633 return status;
634}
635
636/**
637 * i40e_get_mac_addr - get MAC address
638 * @hw: pointer to the HW structure
639 * @mac_addr: pointer to MAC address
640 *
641 * Reads the adapter's MAC address from register
642 **/
643i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
644{
645 struct i40e_aqc_mac_address_read_data addrs;
646 i40e_status status;
647 u16 flags = 0;
648
649 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
650
651 if (flags & I40E_AQC_LAN_ADDR_VALID)
652 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
653
654 return status;
655}
656
351499ab
MJ		 657/**
658 * i40e_pre_tx_queue_cfg - pre tx queue configure
659 * @hw: pointer to the HW structure
660 * @queue: target pf queue index
661 * @enable: state change request
662 *
663 * Handles hw requirement to indicate intention to enable
664 * or disable target queue.
665 **/
666void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
667{
dfb699f9 668 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 669 u32 reg_block = 0;
dfb699f9 670 u32 reg_val;
351499ab 671
24a768cf 672 if (abs_queue_idx >= 128) {
351499ab 673 reg_block = abs_queue_idx / 128;
24a768cf
CP		 674 abs_queue_idx %= 128;
675 }
351499ab
MJ		 676
677 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
678 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
679 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
680
681 if (enable)
682 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
683 else
684 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
685
686 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
687}
688
be405eb0
JB		 689/**
690 * i40e_get_media_type - Gets media type
691 * @hw: pointer to the hardware structure
692 **/
693static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
694{
695 enum i40e_media_type media;
696
697 switch (hw->phy.link_info.phy_type) {
698 case I40E_PHY_TYPE_10GBASE_SR:
699 case I40E_PHY_TYPE_10GBASE_LR:
700 case I40E_PHY_TYPE_40GBASE_SR4:
701 case I40E_PHY_TYPE_40GBASE_LR4:
702 media = I40E_MEDIA_TYPE_FIBER;
703 break;
704 case I40E_PHY_TYPE_100BASE_TX:
705 case I40E_PHY_TYPE_1000BASE_T:
706 case I40E_PHY_TYPE_10GBASE_T:
707 media = I40E_MEDIA_TYPE_BASET;
708 break;
709 case I40E_PHY_TYPE_10GBASE_CR1_CU:
710 case I40E_PHY_TYPE_40GBASE_CR4_CU:
711 case I40E_PHY_TYPE_10GBASE_CR1:
712 case I40E_PHY_TYPE_40GBASE_CR4:
713 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
714 media = I40E_MEDIA_TYPE_DA;
715 break;
716 case I40E_PHY_TYPE_1000BASE_KX:
717 case I40E_PHY_TYPE_10GBASE_KX4:
718 case I40E_PHY_TYPE_10GBASE_KR:
719 case I40E_PHY_TYPE_40GBASE_KR4:
720 media = I40E_MEDIA_TYPE_BACKPLANE;
721 break;
722 case I40E_PHY_TYPE_SGMII:
723 case I40E_PHY_TYPE_XAUI:
724 case I40E_PHY_TYPE_XFI:
725 case I40E_PHY_TYPE_XLAUI:
726 case I40E_PHY_TYPE_XLPPI:
727 default:
728 media = I40E_MEDIA_TYPE_UNKNOWN;
729 break;
730 }
731
732 return media;
733}
734
7134f9ce 735#define I40E_PF_RESET_WAIT_COUNT_A0 200
d0ff5687 736#define I40E_PF_RESET_WAIT_COUNT 100
56a62fc8
JB		 737/**
738 * i40e_pf_reset - Reset the PF
739 * @hw: pointer to the hardware structure
740 *
741 * Assuming someone else has triggered a global reset,
742 * assure the global reset is complete and then reset the PF
743 **/
744i40e_status i40e_pf_reset(struct i40e_hw *hw)
745{
7134f9ce 746 u32 cnt = 0;
42794bd8 747 u32 cnt1 = 0;
56a62fc8
JB		 748 u32 reg = 0;
749 u32 grst_del;
750
751 /* Poll for Global Reset steady state in case of recent GRST.
752 * The grst delay value is in 100ms units, and we'll wait a
753 * couple counts longer to be sure we don't just miss the end.
754 */
755 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
756 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 757 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 758 reg = rd32(hw, I40E_GLGEN_RSTAT);
759 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
760 break;
761 msleep(100);
762 }
763 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
764 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 765 return I40E_ERR_RESET_FAILED;
766 }
767
768 /* Now Wait for the FW to be ready */
769 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
770 reg = rd32(hw, I40E_GLNVM_ULD);
771 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
772 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
773 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
774 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
775 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
776 break;
777 }
778 usleep_range(10000, 20000);
779 }
780 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
781 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
782 hw_dbg(hw, "wait for FW Reset complete timedout\n");
783 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 784 return I40E_ERR_RESET_FAILED;
785 }
786
56a62fc8
JB		 787 /* If there was a Global Reset in progress when we got here,
788 * we don't need to do the PF Reset
789 */
7134f9ce
JB		 790 if (!cnt) {
791 if (hw->revision_id == 0)
792 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
793 else
794 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 795 reg = rd32(hw, I40E_PFGEN_CTRL);
796 wr32(hw, I40E_PFGEN_CTRL,
797 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 798 for (; cnt; cnt--) {
56a62fc8
JB		 799 reg = rd32(hw, I40E_PFGEN_CTRL);
800 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
801 break;
802 usleep_range(1000, 2000);
803 }
804 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
805 hw_dbg(hw, "PF reset polling failed to complete.\n");
806 return I40E_ERR_RESET_FAILED;
807 }
808 }
809
810 i40e_clear_pxe_mode(hw);
922680b9 811
56a62fc8
JB		 812 return 0;
813}
814
838d41d9
SN		 815/**
816 * i40e_clear_hw - clear out any left over hw state
817 * @hw: pointer to the hw struct
818 *
819 * Clear queues and interrupts, typically called at init time,
820 * but after the capabilities have been found so we know how many
821 * queues and msix vectors have been allocated.
822 **/
823void i40e_clear_hw(struct i40e_hw *hw)
824{
825 u32 num_queues, base_queue;
826 u32 num_pf_int;
827 u32 num_vf_int;
828 u32 num_vfs;
829 u32 i, j;
830 u32 val;
831 u32 eol = 0x7ff;
832
833 /* get number of interrupts, queues, and vfs */
834 val = rd32(hw, I40E_GLPCI_CNF2);
835 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
836 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
837 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
838 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
839
840 val = rd32(hw, I40E_PFLAN_QALLOC);
841 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
842 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
843 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
844 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
845 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
846 num_queues = (j - base_queue) + 1;
847 else
848 num_queues = 0;
849
850 val = rd32(hw, I40E_PF_VT_PFALLOC);
851 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
852 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
853 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
854 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
855 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
856 num_vfs = (j - i) + 1;
857 else
858 num_vfs = 0;
859
860 /* stop all the interrupts */
861 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
862 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
863 for (i = 0; i < num_pf_int - 2; i++)
864 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
865
866 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
867 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
868 wr32(hw, I40E_PFINT_LNKLST0, val);
869 for (i = 0; i < num_pf_int - 2; i++)
870 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
871 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
872 for (i = 0; i < num_vfs; i++)
873 wr32(hw, I40E_VPINT_LNKLST0(i), val);
874 for (i = 0; i < num_vf_int - 2; i++)
875 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
876
877 /* warn the HW of the coming Tx disables */
878 for (i = 0; i < num_queues; i++) {
879 u32 abs_queue_idx = base_queue + i;
880 u32 reg_block = 0;
881
882 if (abs_queue_idx >= 128) {
883 reg_block = abs_queue_idx / 128;
884 abs_queue_idx %= 128;
885 }
886
887 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
888 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
889 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
890 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
891
892 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
893 }
894 udelay(400);
895
896 /* stop all the queues */
897 for (i = 0; i < num_queues; i++) {
898 wr32(hw, I40E_QINT_TQCTL(i), 0);
899 wr32(hw, I40E_QTX_ENA(i), 0);
900 wr32(hw, I40E_QINT_RQCTL(i), 0);
901 wr32(hw, I40E_QRX_ENA(i), 0);
902 }
903
904 /* short wait for all queue disables to settle */
905 udelay(50);
906}
907
56a62fc8
JB		 908/**
909 * i40e_clear_pxe_mode - clear pxe operations mode
910 * @hw: pointer to the hw struct
911 *
912 * Make sure all PXE mode settings are cleared, including things
913 * like descriptor fetch/write-back mode.
914 **/
915void i40e_clear_pxe_mode(struct i40e_hw *hw)
916{
917 u32 reg;
918
c9b9b0ae
SN		 919 if (i40e_check_asq_alive(hw))
920 i40e_aq_clear_pxe_mode(hw, NULL);
921
56a62fc8
JB		 922 /* Clear single descriptor fetch/write-back mode */
923 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 924
925 if (hw->revision_id == 0) {
926 /* As a work around clear PXE_MODE instead of setting it */
927 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
928 } else {
929 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
930 }
56a62fc8
JB		 931}
932
0556a9e3
JB		 933/**
934 * i40e_led_is_mine - helper to find matching led
935 * @hw: pointer to the hw struct
936 * @idx: index into GPIO registers
937 *
938 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
939 */
940static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
941{
942 u32 gpio_val = 0;
943 u32 port;
944
945 if (!hw->func_caps.led[idx])
946 return 0;
947
948 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
949 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
950 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
951
952 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
953 * if it is not our port then ignore
954 */
955 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
956 (port != hw->port))
957 return 0;
958
959 return gpio_val;
960}
961
962#define I40E_LED0 22
963#define I40E_LINK_ACTIVITY 0xC
964
56a62fc8
JB		 965/**
966 * i40e_led_get - return current on/off mode
967 * @hw: pointer to the hw struct
968 *
969 * The value returned is the 'mode' field as defined in the
970 * GPIO register definitions: 0x0 = off, 0xf = on, and other
971 * values are variations of possible behaviors relating to
972 * blink, link, and wire.
973 **/
974u32 i40e_led_get(struct i40e_hw *hw)
975{
56a62fc8 976 u32 mode = 0;
56a62fc8
JB		 977 int i;
978
0556a9e3
JB		 979 /* as per the documentation GPIO 22-29 are the LED
980 * GPIO pins named LED0..LED7
981 */
982 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
983 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 984
0556a9e3 985 if (!gpio_val)
56a62fc8
JB		 986 continue;
987
0556a9e3
JB		 988 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
989 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 990 break;
991 }
992
993 return mode;
994}
995
996/**
997 * i40e_led_set - set new on/off mode
998 * @hw: pointer to the hw struct
0556a9e3
JB		 999 * @mode: 0=off, 0xf=on (else see manual for mode details)
1000 * @blink: true if the LED should blink when on, false if steady
1001 *
1002 * if this function is used to turn on the blink it should
1003 * be used to disable the blink when restoring the original state.
56a62fc8 1004 **/
0556a9e3 1005void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1006{
56a62fc8
JB		 1007 int i;
1008
0556a9e3
JB		 1009 if (mode & 0xfffffff0)
1010 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1011
0556a9e3
JB		 1012 /* as per the documentation GPIO 22-29 are the LED
1013 * GPIO pins named LED0..LED7
1014 */
1015 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1016 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1017
0556a9e3 1018 if (!gpio_val)
56a62fc8
JB		 1019 continue;
1020
56a62fc8 1021 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1022 /* this & is a bit of paranoia, but serves as a range check */
1023 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1024 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1025
1026 if (mode == I40E_LINK_ACTIVITY)
1027 blink = false;
1028
1029 gpio_val |= (blink ? 1 : 0) <<
1030 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1031
56a62fc8 1032 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1033 break;
56a62fc8
JB		 1034 }
1035}
1036
1037/* Admin command wrappers */
56a62fc8 1038
8109e123
CS		 1039/**
1040 * i40e_aq_get_phy_capabilities
1041 * @hw: pointer to the hw struct
1042 * @abilities: structure for PHY capabilities to be filled
1043 * @qualified_modules: report Qualified Modules
1044 * @report_init: report init capabilities (active are default)
1045 * @cmd_details: pointer to command details structure or NULL
1046 *
1047 * Returns the various PHY abilities supported on the Port.
1048 **/
1049i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1050 bool qualified_modules, bool report_init,
1051 struct i40e_aq_get_phy_abilities_resp *abilities,
1052 struct i40e_asq_cmd_details *cmd_details)
1053{
1054 struct i40e_aq_desc desc;
1055 i40e_status status;
1056 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1057
1058 if (!abilities)
1059 return I40E_ERR_PARAM;
1060
1061 i40e_fill_default_direct_cmd_desc(&desc,
1062 i40e_aqc_opc_get_phy_abilities);
1063
1064 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1065 if (abilities_size > I40E_AQ_LARGE_BUF)
1066 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1067
1068 if (qualified_modules)
1069 desc.params.external.param0 |=
1070 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1071
1072 if (report_init)
1073 desc.params.external.param0 |=
1074 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1075
1076 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1077 cmd_details);
1078
1079 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1080 status = I40E_ERR_UNKNOWN_PHY;
1081
1082 return status;
1083}
1084
c9b9b0ae
SN		 1085/**
1086 * i40e_aq_clear_pxe_mode
1087 * @hw: pointer to the hw struct
1088 * @cmd_details: pointer to command details structure or NULL
1089 *
1090 * Tell the firmware that the driver is taking over from PXE
1091 **/
1092i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1093 struct i40e_asq_cmd_details *cmd_details)
1094{
1095 i40e_status status;
1096 struct i40e_aq_desc desc;
1097 struct i40e_aqc_clear_pxe *cmd =
1098 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1099
1100 i40e_fill_default_direct_cmd_desc(&desc,
1101 i40e_aqc_opc_clear_pxe_mode);
1102
1103 cmd->rx_cnt = 0x2;
1104
1105 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1106
1107 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1108
1109 return status;
1110}
1111
56a62fc8
JB		 1112/**
1113 * i40e_aq_set_link_restart_an
1114 * @hw: pointer to the hw struct
1ac978af 1115 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1116 * @cmd_details: pointer to command details structure or NULL
1117 *
1118 * Sets up the link and restarts the Auto-Negotiation over the link.
1119 **/
1120i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1121 bool enable_link,
1122 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1123{
1124 struct i40e_aq_desc desc;
1125 struct i40e_aqc_set_link_restart_an *cmd =
1126 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1127 i40e_status status;
1128
1129 i40e_fill_default_direct_cmd_desc(&desc,
1130 i40e_aqc_opc_set_link_restart_an);
1131
1132 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1133 if (enable_link)
1134 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1135 else
1136 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1137
1138 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1139
1140 return status;
1141}
1142
1143/**
1144 * i40e_aq_get_link_info
1145 * @hw: pointer to the hw struct
1146 * @enable_lse: enable/disable LinkStatusEvent reporting
1147 * @link: pointer to link status structure - optional
1148 * @cmd_details: pointer to command details structure or NULL
1149 *
1150 * Returns the link status of the adapter.
1151 **/
1152i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1153 bool enable_lse, struct i40e_link_status *link,
1154 struct i40e_asq_cmd_details *cmd_details)
1155{
1156 struct i40e_aq_desc desc;
1157 struct i40e_aqc_get_link_status *resp =
1158 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1159 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1160 i40e_status status;
1161 u16 command_flags;
1162
1163 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1164
1165 if (enable_lse)
1166 command_flags = I40E_AQ_LSE_ENABLE;
1167 else
1168 command_flags = I40E_AQ_LSE_DISABLE;
1169 resp->command_flags = cpu_to_le16(command_flags);
1170
1171 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1172
1173 if (status)
1174 goto aq_get_link_info_exit;
1175
1176 /* save off old link status information */
c36bd4a7 1177 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1178
1179 /* update link status */
1180 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1181 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1182 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1183 hw_link_info->link_info = resp->link_info;
1184 hw_link_info->an_info = resp->an_info;
1185 hw_link_info->ext_info = resp->ext_info;
639dc377 1186 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1187 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1188 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1189
1190 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1191 hw_link_info->crc_enable = true;
1192 else
1193 hw_link_info->crc_enable = false;
56a62fc8
JB		 1194
1195 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1196 hw_link_info->lse_enable = true;
1197 else
1198 hw_link_info->lse_enable = false;
1199
1200 /* save link status information */
1201 if (link)
d7595a22 1202 *link = *hw_link_info;
56a62fc8
JB		 1203
1204 /* flag cleared so helper functions don't call AQ again */
1205 hw->phy.get_link_info = false;
1206
1207aq_get_link_info_exit:
1208 return status;
1209}
1210
8109e123
CS		 1211/**
1212 * i40e_update_link_info
1213 * @hw: pointer to the hw struct
1214 * @enable_lse: enable/disable LinkStatusEvent reporting
1215 *
1216 * Returns the link status of the adapter
1217 **/
1218i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse)
1219{
1220 struct i40e_aq_get_phy_abilities_resp abilities;
1221 i40e_status status;
1222
1223 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1224 if (status)
1225 return status;
1226
1227 status = i40e_aq_get_phy_capabilities(hw, false, false,
1228 &abilities, NULL);
1229 if (status)
1230 return status;
1231
1232 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1233 hw->phy.link_info.an_enabled = true;
1234 else
1235 hw->phy.link_info.an_enabled = false;
1236
1237 return status;
1238}
1239
56a62fc8
JB		 1240/**
1241 * i40e_aq_add_vsi
1242 * @hw: pointer to the hw struct
98d44381 1243 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1244 * @cmd_details: pointer to command details structure or NULL
1245 *
1246 * Add a VSI context to the hardware.
1247**/
1248i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1249 struct i40e_vsi_context *vsi_ctx,
1250 struct i40e_asq_cmd_details *cmd_details)
1251{
1252 struct i40e_aq_desc desc;
1253 struct i40e_aqc_add_get_update_vsi *cmd =
1254 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1255 struct i40e_aqc_add_get_update_vsi_completion *resp =
1256 (struct i40e_aqc_add_get_update_vsi_completion *)
1257 &desc.params.raw;
1258 i40e_status status;
1259
1260 i40e_fill_default_direct_cmd_desc(&desc,
1261 i40e_aqc_opc_add_vsi);
1262
1263 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1264 cmd->connection_type = vsi_ctx->connection_type;
1265 cmd->vf_id = vsi_ctx->vf_num;
1266 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1267
1268 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1269
1270 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1271 sizeof(vsi_ctx->info), cmd_details);
1272
1273 if (status)
1274 goto aq_add_vsi_exit;
1275
1276 vsi_ctx->seid = le16_to_cpu(resp->seid);
1277 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1278 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1279 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1280
1281aq_add_vsi_exit:
1282 return status;
1283}
1284
1285/**
1286 * i40e_aq_set_vsi_unicast_promiscuous
1287 * @hw: pointer to the hw struct
1288 * @seid: vsi number
1289 * @set: set unicast promiscuous enable/disable
1290 * @cmd_details: pointer to command details structure or NULL
1291 **/
1292i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1293 u16 seid, bool set,
1294 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1295{
1296 struct i40e_aq_desc desc;
1297 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1298 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1299 i40e_status status;
1300 u16 flags = 0;
1301
1302 i40e_fill_default_direct_cmd_desc(&desc,
1303 i40e_aqc_opc_set_vsi_promiscuous_modes);
1304
1305 if (set)
1306 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1307
1308 cmd->promiscuous_flags = cpu_to_le16(flags);
1309
1310 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1311
1312 cmd->seid = cpu_to_le16(seid);
1313 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1314
1315 return status;
1316}
1317
1318/**
1319 * i40e_aq_set_vsi_multicast_promiscuous
1320 * @hw: pointer to the hw struct
1321 * @seid: vsi number
1322 * @set: set multicast promiscuous enable/disable
1323 * @cmd_details: pointer to command details structure or NULL
1324 **/
1325i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1326 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1327{
1328 struct i40e_aq_desc desc;
1329 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1330 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1331 i40e_status status;
1332 u16 flags = 0;
1333
1334 i40e_fill_default_direct_cmd_desc(&desc,
1335 i40e_aqc_opc_set_vsi_promiscuous_modes);
1336
1337 if (set)
1338 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1339
1340 cmd->promiscuous_flags = cpu_to_le16(flags);
1341
1342 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1343
1344 cmd->seid = cpu_to_le16(seid);
1345 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1346
1347 return status;
1348}
1349
1350/**
1351 * i40e_aq_set_vsi_broadcast
1352 * @hw: pointer to the hw struct
1353 * @seid: vsi number
1354 * @set_filter: true to set filter, false to clear filter
1355 * @cmd_details: pointer to command details structure or NULL
1356 *
1357 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1358 **/
1359i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1360 u16 seid, bool set_filter,
1361 struct i40e_asq_cmd_details *cmd_details)
1362{
1363 struct i40e_aq_desc desc;
1364 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1365 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1366 i40e_status status;
1367
1368 i40e_fill_default_direct_cmd_desc(&desc,
1369 i40e_aqc_opc_set_vsi_promiscuous_modes);
1370
1371 if (set_filter)
1372 cmd->promiscuous_flags
1373 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1374 else
1375 cmd->promiscuous_flags
1376 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1377
1378 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1379 cmd->seid = cpu_to_le16(seid);
1380 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1381
1382 return status;
1383}
1384
1385/**
1386 * i40e_get_vsi_params - get VSI configuration info
1387 * @hw: pointer to the hw struct
98d44381 1388 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1389 * @cmd_details: pointer to command details structure or NULL
1390 **/
1391i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1392 struct i40e_vsi_context *vsi_ctx,
1393 struct i40e_asq_cmd_details *cmd_details)
1394{
1395 struct i40e_aq_desc desc;
f5ac8579
SN		 1396 struct i40e_aqc_add_get_update_vsi *cmd =
1397 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1398 struct i40e_aqc_add_get_update_vsi_completion *resp =
1399 (struct i40e_aqc_add_get_update_vsi_completion *)
1400 &desc.params.raw;
1401 i40e_status status;
1402
1403 i40e_fill_default_direct_cmd_desc(&desc,
1404 i40e_aqc_opc_get_vsi_parameters);
1405
f5ac8579 1406 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1407
1408 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 1409
1410 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1411 sizeof(vsi_ctx->info), NULL);
1412
1413 if (status)
1414 goto aq_get_vsi_params_exit;
1415
1416 vsi_ctx->seid = le16_to_cpu(resp->seid);
1417 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1418 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1419 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1420
1421aq_get_vsi_params_exit:
1422 return status;
1423}
1424
1425/**
1426 * i40e_aq_update_vsi_params
1427 * @hw: pointer to the hw struct
98d44381 1428 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1429 * @cmd_details: pointer to command details structure or NULL
1430 *
1431 * Update a VSI context.
1432 **/
1433i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1434 struct i40e_vsi_context *vsi_ctx,
1435 struct i40e_asq_cmd_details *cmd_details)
1436{
1437 struct i40e_aq_desc desc;
f5ac8579
SN		 1438 struct i40e_aqc_add_get_update_vsi *cmd =
1439 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1440 i40e_status status;
1441
1442 i40e_fill_default_direct_cmd_desc(&desc,
1443 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 1444 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1445
1446 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1447
1448 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1449 sizeof(vsi_ctx->info), cmd_details);
1450
1451 return status;
1452}
1453
1454/**
1455 * i40e_aq_get_switch_config
1456 * @hw: pointer to the hardware structure
1457 * @buf: pointer to the result buffer
1458 * @buf_size: length of input buffer
1459 * @start_seid: seid to start for the report, 0 == beginning
1460 * @cmd_details: pointer to command details structure or NULL
1461 *
1462 * Fill the buf with switch configuration returned from AdminQ command
1463 **/
1464i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1465 struct i40e_aqc_get_switch_config_resp *buf,
1466 u16 buf_size, u16 *start_seid,
1467 struct i40e_asq_cmd_details *cmd_details)
1468{
1469 struct i40e_aq_desc desc;
1470 struct i40e_aqc_switch_seid *scfg =
1471 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1472 i40e_status status;
1473
1474 i40e_fill_default_direct_cmd_desc(&desc,
1475 i40e_aqc_opc_get_switch_config);
1476 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1477 if (buf_size > I40E_AQ_LARGE_BUF)
1478 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1479 scfg->seid = cpu_to_le16(*start_seid);
1480
1481 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1482 *start_seid = le16_to_cpu(scfg->seid);
1483
1484 return status;
1485}
1486
1487/**
1488 * i40e_aq_get_firmware_version
1489 * @hw: pointer to the hw struct
1490 * @fw_major_version: firmware major version
1491 * @fw_minor_version: firmware minor version
1492 * @api_major_version: major queue version
1493 * @api_minor_version: minor queue version
1494 * @cmd_details: pointer to command details structure or NULL
1495 *
1496 * Get the firmware version from the admin queue commands
1497 **/
1498i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1499 u16 *fw_major_version, u16 *fw_minor_version,
1500 u16 *api_major_version, u16 *api_minor_version,
1501 struct i40e_asq_cmd_details *cmd_details)
1502{
1503 struct i40e_aq_desc desc;
1504 struct i40e_aqc_get_version *resp =
1505 (struct i40e_aqc_get_version *)&desc.params.raw;
1506 i40e_status status;
1507
1508 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1509
1510 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1511
1512 if (!status) {
1513 if (fw_major_version != NULL)
1514 *fw_major_version = le16_to_cpu(resp->fw_major);
1515 if (fw_minor_version != NULL)
1516 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1517 if (api_major_version != NULL)
1518 *api_major_version = le16_to_cpu(resp->api_major);
1519 if (api_minor_version != NULL)
1520 *api_minor_version = le16_to_cpu(resp->api_minor);
1521 }
1522
1523 return status;
1524}
1525
1526/**
1527 * i40e_aq_send_driver_version
1528 * @hw: pointer to the hw struct
56a62fc8
JB		 1529 * @dv: driver's major, minor version
1530 * @cmd_details: pointer to command details structure or NULL
1531 *
1532 * Send the driver version to the firmware
1533 **/
1534i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1535 struct i40e_driver_version *dv,
1536 struct i40e_asq_cmd_details *cmd_details)
1537{
1538 struct i40e_aq_desc desc;
1539 struct i40e_aqc_driver_version *cmd =
1540 (struct i40e_aqc_driver_version *)&desc.params.raw;
1541 i40e_status status;
9d2f98e1 1542 u16 len;
56a62fc8
JB		 1543
1544 if (dv == NULL)
1545 return I40E_ERR_PARAM;
1546
1547 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1548
1549 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1550 cmd->driver_major_ver = dv->major_version;
1551 cmd->driver_minor_ver = dv->minor_version;
1552 cmd->driver_build_ver = dv->build_version;
1553 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 1554
1555 len = 0;
1556 while (len < sizeof(dv->driver_string) &&
1557 (dv->driver_string[len] < 0x80) &&
1558 dv->driver_string[len])
1559 len++;
1560 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1561 len, cmd_details);
56a62fc8
JB		 1562
1563 return status;
1564}
1565
1566/**
1567 * i40e_get_link_status - get status of the HW network link
1568 * @hw: pointer to the hw struct
1569 *
1570 * Returns true if link is up, false if link is down.
1571 *
1572 * Side effect: LinkStatusEvent reporting becomes enabled
1573 **/
1574bool i40e_get_link_status(struct i40e_hw *hw)
1575{
1576 i40e_status status = 0;
1577 bool link_status = false;
1578
1579 if (hw->phy.get_link_info) {
1580 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1581
1582 if (status)
1583 goto i40e_get_link_status_exit;
1584 }
1585
1586 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1587
1588i40e_get_link_status_exit:
1589 return link_status;
1590}
1591
1592/**
1593 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1594 * @hw: pointer to the hw struct
1595 * @uplink_seid: the MAC or other gizmo SEID
1596 * @downlink_seid: the VSI SEID
1597 * @enabled_tc: bitmap of TCs to be enabled
1598 * @default_port: true for default port VSI, false for control port
e1c51b95 1599 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 1600 * @veb_seid: pointer to where to put the resulting VEB SEID
1601 * @cmd_details: pointer to command details structure or NULL
1602 *
1603 * This asks the FW to add a VEB between the uplink and downlink
1604 * elements. If the uplink SEID is 0, this will be a floating VEB.
1605 **/
1606i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1607 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 1608 bool default_port, bool enable_l2_filtering,
1609 u16 *veb_seid,
56a62fc8
JB		 1610 struct i40e_asq_cmd_details *cmd_details)
1611{
1612 struct i40e_aq_desc desc;
1613 struct i40e_aqc_add_veb *cmd =
1614 (struct i40e_aqc_add_veb *)&desc.params.raw;
1615 struct i40e_aqc_add_veb_completion *resp =
1616 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1617 i40e_status status;
1618 u16 veb_flags = 0;
1619
1620 /* SEIDs need to either both be set or both be 0 for floating VEB */
1621 if (!!uplink_seid != !!downlink_seid)
1622 return I40E_ERR_PARAM;
1623
1624 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1625
1626 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1627 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1628 cmd->enable_tcs = enabled_tc;
1629 if (!uplink_seid)
1630 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1631 if (default_port)
1632 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1633 else
1634 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1635
1636 if (enable_l2_filtering)
1637 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1638
56a62fc8
JB		 1639 cmd->veb_flags = cpu_to_le16(veb_flags);
1640
1641 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1642
1643 if (!status && veb_seid)
1644 *veb_seid = le16_to_cpu(resp->veb_seid);
1645
1646 return status;
1647}
1648
1649/**
1650 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1651 * @hw: pointer to the hw struct
1652 * @veb_seid: the SEID of the VEB to query
1653 * @switch_id: the uplink switch id
98d44381 1654 * @floating: set to true if the VEB is floating
56a62fc8
JB		 1655 * @statistic_index: index of the stats counter block for this VEB
1656 * @vebs_used: number of VEB's used by function
98d44381 1657 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 1658 * @cmd_details: pointer to command details structure or NULL
1659 *
1660 * This retrieves the parameters for a particular VEB, specified by
1661 * uplink_seid, and returns them to the caller.
1662 **/
1663i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1664 u16 veb_seid, u16 *switch_id,
1665 bool *floating, u16 *statistic_index,
1666 u16 *vebs_used, u16 *vebs_free,
1667 struct i40e_asq_cmd_details *cmd_details)
1668{
1669 struct i40e_aq_desc desc;
1670 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1671 (struct i40e_aqc_get_veb_parameters_completion *)
1672 &desc.params.raw;
1673 i40e_status status;
1674
1675 if (veb_seid == 0)
1676 return I40E_ERR_PARAM;
1677
1678 i40e_fill_default_direct_cmd_desc(&desc,
1679 i40e_aqc_opc_get_veb_parameters);
1680 cmd_resp->seid = cpu_to_le16(veb_seid);
1681
1682 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1683 if (status)
1684 goto get_veb_exit;
1685
1686 if (switch_id)
1687 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1688 if (statistic_index)
1689 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1690 if (vebs_used)
1691 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1692 if (vebs_free)
1693 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1694 if (floating) {
1695 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1696 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1697 *floating = true;
1698 else
1699 *floating = false;
1700 }
1701
1702get_veb_exit:
1703 return status;
1704}
1705
1706/**
1707 * i40e_aq_add_macvlan
1708 * @hw: pointer to the hw struct
1709 * @seid: VSI for the mac address
1710 * @mv_list: list of macvlans to be added
1711 * @count: length of the list
1712 * @cmd_details: pointer to command details structure or NULL
1713 *
1714 * Add MAC/VLAN addresses to the HW filtering
1715 **/
1716i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1717 struct i40e_aqc_add_macvlan_element_data *mv_list,
1718 u16 count, struct i40e_asq_cmd_details *cmd_details)
1719{
1720 struct i40e_aq_desc desc;
1721 struct i40e_aqc_macvlan *cmd =
1722 (struct i40e_aqc_macvlan *)&desc.params.raw;
1723 i40e_status status;
1724 u16 buf_size;
1725
1726 if (count == 0 || !mv_list || !hw)
1727 return I40E_ERR_PARAM;
1728
1729 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1730
1731 /* prep the rest of the request */
1732 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1733 cmd->num_addresses = cpu_to_le16(count);
1734 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1735 cmd->seid[1] = 0;
1736 cmd->seid[2] = 0;
1737
1738 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1739 if (buf_size > I40E_AQ_LARGE_BUF)
1740 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1741
1742 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1743 cmd_details);
1744
1745 return status;
1746}
1747
1748/**
1749 * i40e_aq_remove_macvlan
1750 * @hw: pointer to the hw struct
1751 * @seid: VSI for the mac address
1752 * @mv_list: list of macvlans to be removed
1753 * @count: length of the list
1754 * @cmd_details: pointer to command details structure or NULL
1755 *
1756 * Remove MAC/VLAN addresses from the HW filtering
1757 **/
1758i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1759 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1760 u16 count, struct i40e_asq_cmd_details *cmd_details)
1761{
1762 struct i40e_aq_desc desc;
1763 struct i40e_aqc_macvlan *cmd =
1764 (struct i40e_aqc_macvlan *)&desc.params.raw;
1765 i40e_status status;
1766 u16 buf_size;
1767
1768 if (count == 0 || !mv_list || !hw)
1769 return I40E_ERR_PARAM;
1770
1771 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1772
1773 /* prep the rest of the request */
1774 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1775 cmd->num_addresses = cpu_to_le16(count);
1776 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1777 cmd->seid[1] = 0;
1778 cmd->seid[2] = 0;
1779
1780 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1781 if (buf_size > I40E_AQ_LARGE_BUF)
1782 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1783
1784 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1785 cmd_details);
1786
1787 return status;
1788}
1789
56a62fc8
JB		 1790/**
1791 * i40e_aq_send_msg_to_vf
1792 * @hw: pointer to the hardware structure
1793 * @vfid: vf id to send msg
98d44381
JK		 1794 * @v_opcode: opcodes for VF-PF communication
1795 * @v_retval: return error code
56a62fc8
JB		 1796 * @msg: pointer to the msg buffer
1797 * @msglen: msg length
1798 * @cmd_details: pointer to command details
1799 *
1800 * send msg to vf
1801 **/
1802i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1803 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1804 struct i40e_asq_cmd_details *cmd_details)
1805{
1806 struct i40e_aq_desc desc;
1807 struct i40e_aqc_pf_vf_message *cmd =
1808 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1809 i40e_status status;
1810
1811 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1812 cmd->id = cpu_to_le32(vfid);
1813 desc.cookie_high = cpu_to_le32(v_opcode);
1814 desc.cookie_low = cpu_to_le32(v_retval);
1815 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1816 if (msglen) {
1817 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1818 I40E_AQ_FLAG_RD));
1819 if (msglen > I40E_AQ_LARGE_BUF)
1820 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1821 desc.datalen = cpu_to_le16(msglen);
1822 }
1823 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1824
1825 return status;
1826}
1827
1828/**
1829 * i40e_aq_set_hmc_resource_profile
1830 * @hw: pointer to the hw struct
1831 * @profile: type of profile the HMC is to be set as
1832 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1833 * @cmd_details: pointer to command details structure or NULL
1834 *
1835 * set the HMC profile of the device.
1836 **/
1837i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1838 enum i40e_aq_hmc_profile profile,
1839 u8 pe_vf_enabled_count,
1840 struct i40e_asq_cmd_details *cmd_details)
1841{
1842 struct i40e_aq_desc desc;
1843 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1844 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1845 i40e_status status;
1846
1847 i40e_fill_default_direct_cmd_desc(&desc,
1848 i40e_aqc_opc_set_hmc_resource_profile);
1849
1850 cmd->pm_profile = (u8)profile;
1851 cmd->pe_vf_enabled = pe_vf_enabled_count;
1852
1853 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1854
1855 return status;
1856}
1857
1858/**
1859 * i40e_aq_request_resource
1860 * @hw: pointer to the hw struct
1861 * @resource: resource id
1862 * @access: access type
1863 * @sdp_number: resource number
1864 * @timeout: the maximum time in ms that the driver may hold the resource
1865 * @cmd_details: pointer to command details structure or NULL
1866 *
1867 * requests common resource using the admin queue commands
1868 **/
1869i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1870 enum i40e_aq_resources_ids resource,
1871 enum i40e_aq_resource_access_type access,
1872 u8 sdp_number, u64 *timeout,
1873 struct i40e_asq_cmd_details *cmd_details)
1874{
1875 struct i40e_aq_desc desc;
1876 struct i40e_aqc_request_resource *cmd_resp =
1877 (struct i40e_aqc_request_resource *)&desc.params.raw;
1878 i40e_status status;
1879
1880 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1881
1882 cmd_resp->resource_id = cpu_to_le16(resource);
1883 cmd_resp->access_type = cpu_to_le16(access);
1884 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1885
1886 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1887 /* The completion specifies the maximum time in ms that the driver
1888 * may hold the resource in the Timeout field.
1889 * If the resource is held by someone else, the command completes with
1890 * busy return value and the timeout field indicates the maximum time
1891 * the current owner of the resource has to free it.
1892 */
1893 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1894 *timeout = le32_to_cpu(cmd_resp->timeout);
1895
1896 return status;
1897}
1898
1899/**
1900 * i40e_aq_release_resource
1901 * @hw: pointer to the hw struct
1902 * @resource: resource id
1903 * @sdp_number: resource number
1904 * @cmd_details: pointer to command details structure or NULL
1905 *
1906 * release common resource using the admin queue commands
1907 **/
1908i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1909 enum i40e_aq_resources_ids resource,
1910 u8 sdp_number,
1911 struct i40e_asq_cmd_details *cmd_details)
1912{
1913 struct i40e_aq_desc desc;
1914 struct i40e_aqc_request_resource *cmd =
1915 (struct i40e_aqc_request_resource *)&desc.params.raw;
1916 i40e_status status;
1917
1918 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1919
1920 cmd->resource_id = cpu_to_le16(resource);
1921 cmd->resource_number = cpu_to_le32(sdp_number);
1922
1923 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1924
1925 return status;
1926}
1927
1928/**
1929 * i40e_aq_read_nvm
1930 * @hw: pointer to the hw struct
1931 * @module_pointer: module pointer location in words from the NVM beginning
1932 * @offset: byte offset from the module beginning
1933 * @length: length of the section to be read (in bytes from the offset)
1934 * @data: command buffer (size [bytes] = length)
1935 * @last_command: tells if this is the last command in a series
1936 * @cmd_details: pointer to command details structure or NULL
1937 *
1938 * Read the NVM using the admin queue commands
1939 **/
1940i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1941 u32 offset, u16 length, void *data,
1942 bool last_command,
1943 struct i40e_asq_cmd_details *cmd_details)
1944{
1945 struct i40e_aq_desc desc;
1946 struct i40e_aqc_nvm_update *cmd =
1947 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1948 i40e_status status;
1949
1950 /* In offset the highest byte must be zeroed. */
1951 if (offset & 0xFF000000) {
1952 status = I40E_ERR_PARAM;
1953 goto i40e_aq_read_nvm_exit;
1954 }
1955
1956 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1957
1958 /* If this is the last command in a series, set the proper flag. */
1959 if (last_command)
1960 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1961 cmd->module_pointer = module_pointer;
1962 cmd->offset = cpu_to_le32(offset);
1963 cmd->length = cpu_to_le16(length);
1964
1965 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1966 if (length > I40E_AQ_LARGE_BUF)
1967 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1968
1969 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1970
1971i40e_aq_read_nvm_exit:
1972 return status;
1973}
1974
1975#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1976#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1977#define I40E_DEV_FUNC_CAP_NPAR 0x03
1978#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1979#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1980#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1981#define I40E_DEV_FUNC_CAP_VF 0x13
1982#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1983#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1984#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1985#define I40E_DEV_FUNC_CAP_VSI 0x17
1986#define I40E_DEV_FUNC_CAP_DCB 0x18
1987#define I40E_DEV_FUNC_CAP_FCOE 0x21
1988#define I40E_DEV_FUNC_CAP_RSS 0x40
1989#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1990#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1991#define I40E_DEV_FUNC_CAP_MSIX 0x43
1992#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1993#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1994#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1995#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1996#define I40E_DEV_FUNC_CAP_CEM 0xF2
1997#define I40E_DEV_FUNC_CAP_IWARP 0x51
1998#define I40E_DEV_FUNC_CAP_LED 0x61
1999#define I40E_DEV_FUNC_CAP_SDP 0x62
2000#define I40E_DEV_FUNC_CAP_MDIO 0x63
2001
2002/**
2003 * i40e_parse_discover_capabilities
2004 * @hw: pointer to the hw struct
2005 * @buff: pointer to a buffer containing device/function capability records
2006 * @cap_count: number of capability records in the list
2007 * @list_type_opc: type of capabilities list to parse
2008 *
2009 * Parse the device/function capabilities list.
2010 **/
2011static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2012 u32 cap_count,
2013 enum i40e_admin_queue_opc list_type_opc)
2014{
2015 struct i40e_aqc_list_capabilities_element_resp *cap;
2016 u32 number, logical_id, phys_id;
2017 struct i40e_hw_capabilities *p;
56a62fc8
JB		 2018 u32 i = 0;
2019 u16 id;
2020
2021 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2022
2023 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 2024 p = &hw->dev_caps;
56a62fc8 2025 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 2026 p = &hw->func_caps;
56a62fc8
JB		 2027 else
2028 return;
2029
2030 for (i = 0; i < cap_count; i++, cap++) {
2031 id = le16_to_cpu(cap->id);
2032 number = le32_to_cpu(cap->number);
2033 logical_id = le32_to_cpu(cap->logical_id);
2034 phys_id = le32_to_cpu(cap->phys_id);
2035
2036 switch (id) {
2037 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2038 p->switch_mode = number;
2039 break;
2040 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2041 p->management_mode = number;
2042 break;
2043 case I40E_DEV_FUNC_CAP_NPAR:
2044 p->npar_enable = number;
2045 break;
2046 case I40E_DEV_FUNC_CAP_OS2BMC:
2047 p->os2bmc = number;
2048 break;
2049 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2050 p->valid_functions = number;
2051 break;
2052 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2053 if (number == 1)
2054 p->sr_iov_1_1 = true;
2055 break;
2056 case I40E_DEV_FUNC_CAP_VF:
2057 p->num_vfs = number;
2058 p->vf_base_id = logical_id;
2059 break;
2060 case I40E_DEV_FUNC_CAP_VMDQ:
2061 if (number == 1)
2062 p->vmdq = true;
2063 break;
2064 case I40E_DEV_FUNC_CAP_802_1_QBG:
2065 if (number == 1)
2066 p->evb_802_1_qbg = true;
2067 break;
2068 case I40E_DEV_FUNC_CAP_802_1_QBH:
2069 if (number == 1)
2070 p->evb_802_1_qbh = true;
2071 break;
2072 case I40E_DEV_FUNC_CAP_VSI:
2073 p->num_vsis = number;
2074 break;
2075 case I40E_DEV_FUNC_CAP_DCB:
2076 if (number == 1) {
2077 p->dcb = true;
2078 p->enabled_tcmap = logical_id;
2079 p->maxtc = phys_id;
2080 }
2081 break;
2082 case I40E_DEV_FUNC_CAP_FCOE:
2083 if (number == 1)
2084 p->fcoe = true;
2085 break;
2086 case I40E_DEV_FUNC_CAP_RSS:
2087 p->rss = true;
e157ea30 2088 p->rss_table_size = number;
56a62fc8
JB		 2089 p->rss_table_entry_width = logical_id;
2090 break;
2091 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2092 p->num_rx_qp = number;
2093 p->base_queue = phys_id;
2094 break;
2095 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2096 p->num_tx_qp = number;
2097 p->base_queue = phys_id;
2098 break;
2099 case I40E_DEV_FUNC_CAP_MSIX:
2100 p->num_msix_vectors = number;
2101 break;
2102 case I40E_DEV_FUNC_CAP_MSIX_VF:
2103 p->num_msix_vectors_vf = number;
2104 break;
2105 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2106 if (number == 1)
2107 p->mfp_mode_1 = true;
2108 break;
2109 case I40E_DEV_FUNC_CAP_CEM:
2110 if (number == 1)
2111 p->mgmt_cem = true;
2112 break;
2113 case I40E_DEV_FUNC_CAP_IWARP:
2114 if (number == 1)
2115 p->iwarp = true;
2116 break;
2117 case I40E_DEV_FUNC_CAP_LED:
2118 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2119 p->led[phys_id] = true;
2120 break;
2121 case I40E_DEV_FUNC_CAP_SDP:
2122 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2123 p->sdp[phys_id] = true;
2124 break;
2125 case I40E_DEV_FUNC_CAP_MDIO:
2126 if (number == 1) {
2127 p->mdio_port_num = phys_id;
2128 p->mdio_port_mode = logical_id;
2129 }
2130 break;
2131 case I40E_DEV_FUNC_CAP_IEEE_1588:
2132 if (number == 1)
2133 p->ieee_1588 = true;
2134 break;
2135 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2136 p->fd = true;
2137 p->fd_filters_guaranteed = number;
2138 p->fd_filters_best_effort = logical_id;
2139 break;
2140 default:
2141 break;
2142 }
2143 }
2144
566bb85d
VD		 2145 /* Software override ensuring FCoE is disabled if npar or mfp
2146 * mode because it is not supported in these modes.
2147 */
2148 if (p->npar_enable || p->mfp_mode_1)
2149 p->fcoe = false;
2150
56a62fc8
JB		 2151 /* additional HW specific goodies that might
2152 * someday be HW version specific
2153 */
2154 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2155}
2156
2157/**
2158 * i40e_aq_discover_capabilities
2159 * @hw: pointer to the hw struct
2160 * @buff: a virtual buffer to hold the capabilities
2161 * @buff_size: Size of the virtual buffer
2162 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2163 * @list_type_opc: capabilities type to discover - pass in the command opcode
2164 * @cmd_details: pointer to command details structure or NULL
2165 *
2166 * Get the device capabilities descriptions from the firmware
2167 **/
2168i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2169 void *buff, u16 buff_size, u16 *data_size,
2170 enum i40e_admin_queue_opc list_type_opc,
2171 struct i40e_asq_cmd_details *cmd_details)
2172{
2173 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 2174 struct i40e_aq_desc desc;
8fb905b3 2175 i40e_status status = 0;
56a62fc8
JB		 2176
2177 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2178
2179 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2180 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2181 status = I40E_ERR_PARAM;
2182 goto exit;
2183 }
2184
2185 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2186
2187 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2188 if (buff_size > I40E_AQ_LARGE_BUF)
2189 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2190
2191 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2192 *data_size = le16_to_cpu(desc.datalen);
2193
2194 if (status)
2195 goto exit;
2196
2197 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2198 list_type_opc);
2199
2200exit:
2201 return status;
2202}
2203
2204/**
2205 * i40e_aq_get_lldp_mib
2206 * @hw: pointer to the hw struct
2207 * @bridge_type: type of bridge requested
2208 * @mib_type: Local, Remote or both Local and Remote MIBs
2209 * @buff: pointer to a user supplied buffer to store the MIB block
2210 * @buff_size: size of the buffer (in bytes)
2211 * @local_len : length of the returned Local LLDP MIB
2212 * @remote_len: length of the returned Remote LLDP MIB
2213 * @cmd_details: pointer to command details structure or NULL
2214 *
2215 * Requests the complete LLDP MIB (entire packet).
2216 **/
2217i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2218 u8 mib_type, void *buff, u16 buff_size,
2219 u16 *local_len, u16 *remote_len,
2220 struct i40e_asq_cmd_details *cmd_details)
2221{
2222 struct i40e_aq_desc desc;
2223 struct i40e_aqc_lldp_get_mib *cmd =
2224 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2225 struct i40e_aqc_lldp_get_mib *resp =
2226 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2227 i40e_status status;
2228
2229 if (buff_size == 0 || !buff)
2230 return I40E_ERR_PARAM;
2231
2232 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2233 /* Indirect Command */
2234 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2235
2236 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2237 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2238 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2239
2240 desc.datalen = cpu_to_le16(buff_size);
2241
2242 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2243 if (buff_size > I40E_AQ_LARGE_BUF)
2244 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2245
2246 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2247 if (!status) {
2248 if (local_len != NULL)
2249 *local_len = le16_to_cpu(resp->local_len);
2250 if (remote_len != NULL)
2251 *remote_len = le16_to_cpu(resp->remote_len);
2252 }
2253
2254 return status;
2255}
2256
2257/**
2258 * i40e_aq_cfg_lldp_mib_change_event
2259 * @hw: pointer to the hw struct
2260 * @enable_update: Enable or Disable event posting
2261 * @cmd_details: pointer to command details structure or NULL
2262 *
2263 * Enable or Disable posting of an event on ARQ when LLDP MIB
2264 * associated with the interface changes
2265 **/
2266i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2267 bool enable_update,
2268 struct i40e_asq_cmd_details *cmd_details)
2269{
2270 struct i40e_aq_desc desc;
2271 struct i40e_aqc_lldp_update_mib *cmd =
2272 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2273 i40e_status status;
2274
2275 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2276
2277 if (!enable_update)
2278 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2279
2280 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2281
2282 return status;
2283}
2284
2285/**
2286 * i40e_aq_stop_lldp
2287 * @hw: pointer to the hw struct
2288 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2289 * @cmd_details: pointer to command details structure or NULL
2290 *
2291 * Stop or Shutdown the embedded LLDP Agent
2292 **/
2293i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2294 struct i40e_asq_cmd_details *cmd_details)
2295{
2296 struct i40e_aq_desc desc;
2297 struct i40e_aqc_lldp_stop *cmd =
2298 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2299 i40e_status status;
2300
2301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2302
2303 if (shutdown_agent)
2304 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2305
2306 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2307
2308 return status;
2309}
2310
2311/**
2312 * i40e_aq_start_lldp
2313 * @hw: pointer to the hw struct
2314 * @cmd_details: pointer to command details structure or NULL
2315 *
2316 * Start the embedded LLDP Agent on all ports.
2317 **/
2318i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2319 struct i40e_asq_cmd_details *cmd_details)
2320{
2321 struct i40e_aq_desc desc;
2322 struct i40e_aqc_lldp_start *cmd =
2323 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2324 i40e_status status;
2325
2326 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2327
2328 cmd->command = I40E_AQ_LLDP_AGENT_START;
2329
2330 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2331
2332 return status;
2333}
2334
a1c9a9d9
JK		 2335/**
2336 * i40e_aq_add_udp_tunnel
2337 * @hw: pointer to the hw struct
2338 * @udp_port: the UDP port to add
2339 * @header_len: length of the tunneling header length in DWords
2340 * @protocol_index: protocol index type
98d44381 2341 * @filter_index: pointer to filter index
a1c9a9d9
JK		 2342 * @cmd_details: pointer to command details structure or NULL
2343 **/
2344i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 2345 u16 udp_port, u8 protocol_index,
2346 u8 *filter_index,
a1c9a9d9
JK		 2347 struct i40e_asq_cmd_details *cmd_details)
2348{
2349 struct i40e_aq_desc desc;
2350 struct i40e_aqc_add_udp_tunnel *cmd =
2351 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2352 struct i40e_aqc_del_udp_tunnel_completion *resp =
2353 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2354 i40e_status status;
2355
2356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2357
2358 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 2359 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 2360
2361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2362
2363 if (!status)
2364 *filter_index = resp->index;
2365
2366 return status;
2367}
2368
2369/**
2370 * i40e_aq_del_udp_tunnel
2371 * @hw: pointer to the hw struct
2372 * @index: filter index
2373 * @cmd_details: pointer to command details structure or NULL
2374 **/
2375i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2376 struct i40e_asq_cmd_details *cmd_details)
2377{
2378 struct i40e_aq_desc desc;
2379 struct i40e_aqc_remove_udp_tunnel *cmd =
2380 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2381 i40e_status status;
2382
2383 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2384
2385 cmd->index = index;
2386
2387 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2388
2389 return status;
2390}
2391
56a62fc8
JB		 2392/**
2393 * i40e_aq_delete_element - Delete switch element
2394 * @hw: pointer to the hw struct
2395 * @seid: the SEID to delete from the switch
2396 * @cmd_details: pointer to command details structure or NULL
2397 *
2398 * This deletes a switch element from the switch.
2399 **/
2400i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2401 struct i40e_asq_cmd_details *cmd_details)
2402{
2403 struct i40e_aq_desc desc;
2404 struct i40e_aqc_switch_seid *cmd =
2405 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2406 i40e_status status;
2407
2408 if (seid == 0)
2409 return I40E_ERR_PARAM;
2410
2411 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2412
2413 cmd->seid = cpu_to_le16(seid);
2414
2415 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2416
2417 return status;
2418}
2419
afb3ff0d
NP		 2420/**
2421 * i40e_aq_dcb_updated - DCB Updated Command
2422 * @hw: pointer to the hw struct
2423 * @cmd_details: pointer to command details structure or NULL
2424 *
2425 * EMP will return when the shared RPB settings have been
2426 * recomputed and modified. The retval field in the descriptor
2427 * will be set to 0 when RPB is modified.
2428 **/
2429i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2430 struct i40e_asq_cmd_details *cmd_details)
2431{
2432 struct i40e_aq_desc desc;
2433 i40e_status status;
2434
2435 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2436
2437 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2438
2439 return status;
2440}
2441
56a62fc8
JB		 2442/**
2443 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2444 * @hw: pointer to the hw struct
2445 * @seid: seid for the physical port/switching component/vsi
2446 * @buff: Indirect buffer to hold data parameters and response
2447 * @buff_size: Indirect buffer size
2448 * @opcode: Tx scheduler AQ command opcode
2449 * @cmd_details: pointer to command details structure or NULL
2450 *
2451 * Generic command handler for Tx scheduler AQ commands
2452 **/
2453static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2454 void *buff, u16 buff_size,
2455 enum i40e_admin_queue_opc opcode,
2456 struct i40e_asq_cmd_details *cmd_details)
2457{
2458 struct i40e_aq_desc desc;
2459 struct i40e_aqc_tx_sched_ind *cmd =
2460 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2461 i40e_status status;
2462 bool cmd_param_flag = false;
2463
2464 switch (opcode) {
2465 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2466 case i40e_aqc_opc_configure_vsi_tc_bw:
2467 case i40e_aqc_opc_enable_switching_comp_ets:
2468 case i40e_aqc_opc_modify_switching_comp_ets:
2469 case i40e_aqc_opc_disable_switching_comp_ets:
2470 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2471 case i40e_aqc_opc_configure_switching_comp_bw_config:
2472 cmd_param_flag = true;
2473 break;
2474 case i40e_aqc_opc_query_vsi_bw_config:
2475 case i40e_aqc_opc_query_vsi_ets_sla_config:
2476 case i40e_aqc_opc_query_switching_comp_ets_config:
2477 case i40e_aqc_opc_query_port_ets_config:
2478 case i40e_aqc_opc_query_switching_comp_bw_config:
2479 cmd_param_flag = false;
2480 break;
2481 default:
2482 return I40E_ERR_PARAM;
2483 }
2484
2485 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2486
2487 /* Indirect command */
2488 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2489 if (cmd_param_flag)
2490 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2491 if (buff_size > I40E_AQ_LARGE_BUF)
2492 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2493
2494 desc.datalen = cpu_to_le16(buff_size);
2495
2496 cmd->vsi_seid = cpu_to_le16(seid);
2497
2498 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2499
2500 return status;
2501}
2502
6b192891
MW		 2503/**
2504 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2505 * @hw: pointer to the hw struct
2506 * @seid: VSI seid
2507 * @credit: BW limit credits (0 = disabled)
2508 * @max_credit: Max BW limit credits
2509 * @cmd_details: pointer to command details structure or NULL
2510 **/
2511i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2512 u16 seid, u16 credit, u8 max_credit,
2513 struct i40e_asq_cmd_details *cmd_details)
2514{
2515 struct i40e_aq_desc desc;
2516 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2517 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2518 i40e_status status;
2519
2520 i40e_fill_default_direct_cmd_desc(&desc,
2521 i40e_aqc_opc_configure_vsi_bw_limit);
2522
2523 cmd->vsi_seid = cpu_to_le16(seid);
2524 cmd->credit = cpu_to_le16(credit);
2525 cmd->max_credit = max_credit;
2526
2527 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2528
2529 return status;
2530}
2531
56a62fc8
JB		 2532/**
2533 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2534 * @hw: pointer to the hw struct
2535 * @seid: VSI seid
2536 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2537 * @cmd_details: pointer to command details structure or NULL
2538 **/
2539i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2540 u16 seid,
2541 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2542 struct i40e_asq_cmd_details *cmd_details)
2543{
2544 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2545 i40e_aqc_opc_configure_vsi_tc_bw,
2546 cmd_details);
2547}
2548
afb3ff0d
NP		 2549/**
2550 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2551 * @hw: pointer to the hw struct
2552 * @seid: seid of the switching component connected to Physical Port
2553 * @ets_data: Buffer holding ETS parameters
2554 * @cmd_details: pointer to command details structure or NULL
2555 **/
2556i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2557 u16 seid,
2558 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2559 enum i40e_admin_queue_opc opcode,
2560 struct i40e_asq_cmd_details *cmd_details)
2561{
2562 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2563 sizeof(*ets_data), opcode, cmd_details);
2564}
2565
2566/**
2567 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2568 * @hw: pointer to the hw struct
2569 * @seid: seid of the switching component
2570 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2571 * @cmd_details: pointer to command details structure or NULL
2572 **/
2573i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2574 u16 seid,
2575 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2576 struct i40e_asq_cmd_details *cmd_details)
2577{
2578 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2579 i40e_aqc_opc_configure_switching_comp_bw_config,
2580 cmd_details);
2581}
2582
56a62fc8
JB		 2583/**
2584 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2585 * @hw: pointer to the hw struct
2586 * @seid: seid of the VSI
2587 * @bw_data: Buffer to hold VSI BW configuration
2588 * @cmd_details: pointer to command details structure or NULL
2589 **/
2590i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2591 u16 seid,
2592 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2593 struct i40e_asq_cmd_details *cmd_details)
2594{
2595 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2596 i40e_aqc_opc_query_vsi_bw_config,
2597 cmd_details);
2598}
2599
2600/**
2601 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2602 * @hw: pointer to the hw struct
2603 * @seid: seid of the VSI
2604 * @bw_data: Buffer to hold VSI BW configuration per TC
2605 * @cmd_details: pointer to command details structure or NULL
2606 **/
2607i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2608 u16 seid,
2609 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2610 struct i40e_asq_cmd_details *cmd_details)
2611{
2612 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2613 i40e_aqc_opc_query_vsi_ets_sla_config,
2614 cmd_details);
2615}
2616
2617/**
2618 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2619 * @hw: pointer to the hw struct
2620 * @seid: seid of the switching component
2621 * @bw_data: Buffer to hold switching component's per TC BW config
2622 * @cmd_details: pointer to command details structure or NULL
2623 **/
2624i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2625 u16 seid,
2626 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2627 struct i40e_asq_cmd_details *cmd_details)
2628{
2629 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2630 i40e_aqc_opc_query_switching_comp_ets_config,
2631 cmd_details);
2632}
2633
2634/**
2635 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2636 * @hw: pointer to the hw struct
2637 * @seid: seid of the VSI or switching component connected to Physical Port
2638 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2639 * @cmd_details: pointer to command details structure or NULL
2640 **/
2641i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2642 u16 seid,
2643 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2644 struct i40e_asq_cmd_details *cmd_details)
2645{
2646 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2647 i40e_aqc_opc_query_port_ets_config,
2648 cmd_details);
2649}
2650
2651/**
2652 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2653 * @hw: pointer to the hw struct
2654 * @seid: seid of the switching component
2655 * @bw_data: Buffer to hold switching component's BW configuration
2656 * @cmd_details: pointer to command details structure or NULL
2657 **/
2658i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2659 u16 seid,
2660 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2661 struct i40e_asq_cmd_details *cmd_details)
2662{
2663 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2664 i40e_aqc_opc_query_switching_comp_bw_config,
2665 cmd_details);
2666}
2667
2668/**
2669 * i40e_validate_filter_settings
2670 * @hw: pointer to the hardware structure
2671 * @settings: Filter control settings
2672 *
2673 * Check and validate the filter control settings passed.
2674 * The function checks for the valid filter/context sizes being
2675 * passed for FCoE and PE.
2676 *
2677 * Returns 0 if the values passed are valid and within
2678 * range else returns an error.
2679 **/
2680static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2681 struct i40e_filter_control_settings *settings)
2682{
2683 u32 fcoe_cntx_size, fcoe_filt_size;
2684 u32 pe_cntx_size, pe_filt_size;
467d729a 2685 u32 fcoe_fmax;
56a62fc8
JB		 2686 u32 val;
2687
2688 /* Validate FCoE settings passed */
2689 switch (settings->fcoe_filt_num) {
2690 case I40E_HASH_FILTER_SIZE_1K:
2691 case I40E_HASH_FILTER_SIZE_2K:
2692 case I40E_HASH_FILTER_SIZE_4K:
2693 case I40E_HASH_FILTER_SIZE_8K:
2694 case I40E_HASH_FILTER_SIZE_16K:
2695 case I40E_HASH_FILTER_SIZE_32K:
2696 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2697 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2698 break;
2699 default:
2700 return I40E_ERR_PARAM;
2701 }
2702
2703 switch (settings->fcoe_cntx_num) {
2704 case I40E_DMA_CNTX_SIZE_512:
2705 case I40E_DMA_CNTX_SIZE_1K:
2706 case I40E_DMA_CNTX_SIZE_2K:
2707 case I40E_DMA_CNTX_SIZE_4K:
2708 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2709 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2710 break;
2711 default:
2712 return I40E_ERR_PARAM;
2713 }
2714
2715 /* Validate PE settings passed */
2716 switch (settings->pe_filt_num) {
2717 case I40E_HASH_FILTER_SIZE_1K:
2718 case I40E_HASH_FILTER_SIZE_2K:
2719 case I40E_HASH_FILTER_SIZE_4K:
2720 case I40E_HASH_FILTER_SIZE_8K:
2721 case I40E_HASH_FILTER_SIZE_16K:
2722 case I40E_HASH_FILTER_SIZE_32K:
2723 case I40E_HASH_FILTER_SIZE_64K:
2724 case I40E_HASH_FILTER_SIZE_128K:
2725 case I40E_HASH_FILTER_SIZE_256K:
2726 case I40E_HASH_FILTER_SIZE_512K:
2727 case I40E_HASH_FILTER_SIZE_1M:
2728 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2729 pe_filt_size <<= (u32)settings->pe_filt_num;
2730 break;
2731 default:
2732 return I40E_ERR_PARAM;
2733 }
2734
2735 switch (settings->pe_cntx_num) {
2736 case I40E_DMA_CNTX_SIZE_512:
2737 case I40E_DMA_CNTX_SIZE_1K:
2738 case I40E_DMA_CNTX_SIZE_2K:
2739 case I40E_DMA_CNTX_SIZE_4K:
2740 case I40E_DMA_CNTX_SIZE_8K:
2741 case I40E_DMA_CNTX_SIZE_16K:
2742 case I40E_DMA_CNTX_SIZE_32K:
2743 case I40E_DMA_CNTX_SIZE_64K:
2744 case I40E_DMA_CNTX_SIZE_128K:
2745 case I40E_DMA_CNTX_SIZE_256K:
2746 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2747 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2748 break;
2749 default:
2750 return I40E_ERR_PARAM;
2751 }
2752
2753 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2754 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2755 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2756 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2757 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2758 return I40E_ERR_INVALID_SIZE;
2759
56a62fc8
JB		 2760 return 0;
2761}
2762
2763/**
2764 * i40e_set_filter_control
2765 * @hw: pointer to the hardware structure
2766 * @settings: Filter control settings
2767 *
2768 * Set the Queue Filters for PE/FCoE and enable filters required
2769 * for a single PF. It is expected that these settings are programmed
2770 * at the driver initialization time.
2771 **/
2772i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2773 struct i40e_filter_control_settings *settings)
2774{
2775 i40e_status ret = 0;
2776 u32 hash_lut_size = 0;
2777 u32 val;
2778
2779 if (!settings)
2780 return I40E_ERR_PARAM;
2781
2782 /* Validate the input settings */
2783 ret = i40e_validate_filter_settings(hw, settings);
2784 if (ret)
2785 return ret;
2786
2787 /* Read the PF Queue Filter control register */
2788 val = rd32(hw, I40E_PFQF_CTL_0);
2789
2790 /* Program required PE hash buckets for the PF */
2791 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2792 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2793 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2794 /* Program required PE contexts for the PF */
2795 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2796 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2797 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2798
2799 /* Program required FCoE hash buckets for the PF */
2800 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2801 val |= ((u32)settings->fcoe_filt_num <<
2802 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2803 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2804 /* Program required FCoE DDP contexts for the PF */
2805 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2806 val |= ((u32)settings->fcoe_cntx_num <<
2807 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2808 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2809
2810 /* Program Hash LUT size for the PF */
2811 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2812 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2813 hash_lut_size = 1;
2814 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2815 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2816
2817 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2818 if (settings->enable_fdir)
2819 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2820 if (settings->enable_ethtype)
2821 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2822 if (settings->enable_macvlan)
2823 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2824
2825 wr32(hw, I40E_PFQF_CTL_0, val);
2826
2827 return 0;
2828}
afb3ff0d
NP		 2829
2830/**
2831 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2832 * @hw: pointer to the hw struct
2833 * @mac_addr: MAC address to use in the filter
2834 * @ethtype: Ethertype to use in the filter
2835 * @flags: Flags that needs to be applied to the filter
2836 * @vsi_seid: seid of the control VSI
2837 * @queue: VSI queue number to send the packet to
2838 * @is_add: Add control packet filter if True else remove
2839 * @stats: Structure to hold information on control filter counts
2840 * @cmd_details: pointer to command details structure or NULL
2841 *
2842 * This command will Add or Remove control packet filter for a control VSI.
2843 * In return it will update the total number of perfect filter count in
2844 * the stats member.
2845 **/
2846i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
2847 u8 *mac_addr, u16 ethtype, u16 flags,
2848 u16 vsi_seid, u16 queue, bool is_add,
2849 struct i40e_control_filter_stats *stats,
2850 struct i40e_asq_cmd_details *cmd_details)
2851{
2852 struct i40e_aq_desc desc;
2853 struct i40e_aqc_add_remove_control_packet_filter *cmd =
2854 (struct i40e_aqc_add_remove_control_packet_filter *)
2855 &desc.params.raw;
2856 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
2857 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
2858 &desc.params.raw;
2859 i40e_status status;
2860
2861 if (vsi_seid == 0)
2862 return I40E_ERR_PARAM;
2863
2864 if (is_add) {
2865 i40e_fill_default_direct_cmd_desc(&desc,
2866 i40e_aqc_opc_add_control_packet_filter);
2867 cmd->queue = cpu_to_le16(queue);
2868 } else {
2869 i40e_fill_default_direct_cmd_desc(&desc,
2870 i40e_aqc_opc_remove_control_packet_filter);
2871 }
2872
2873 if (mac_addr)
2874 memcpy(cmd->mac, mac_addr, ETH_ALEN);
2875
2876 cmd->etype = cpu_to_le16(ethtype);
2877 cmd->flags = cpu_to_le16(flags);
2878 cmd->seid = cpu_to_le16(vsi_seid);
2879
2880 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2881
2882 if (!status && stats) {
2883 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
2884 stats->etype_used = le16_to_cpu(resp->etype_used);
2885 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
2886 stats->etype_free = le16_to_cpu(resp->etype_free);
2887 }
2888
2889 return status;
2890}
2891
d4dfb81a
CS		 2892/**
2893 * i40e_set_pci_config_data - store PCI bus info
2894 * @hw: pointer to hardware structure
2895 * @link_status: the link status word from PCI config space
2896 *
2897 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2898 **/
2899void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2900{
2901 hw->bus.type = i40e_bus_type_pci_express;
2902
2903 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2904 case PCI_EXP_LNKSTA_NLW_X1:
2905 hw->bus.width = i40e_bus_width_pcie_x1;
2906 break;
2907 case PCI_EXP_LNKSTA_NLW_X2:
2908 hw->bus.width = i40e_bus_width_pcie_x2;
2909 break;
2910 case PCI_EXP_LNKSTA_NLW_X4:
2911 hw->bus.width = i40e_bus_width_pcie_x4;
2912 break;
2913 case PCI_EXP_LNKSTA_NLW_X8:
2914 hw->bus.width = i40e_bus_width_pcie_x8;
2915 break;
2916 default:
2917 hw->bus.width = i40e_bus_width_unknown;
2918 break;
2919 }
2920
2921 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2922 case PCI_EXP_LNKSTA_CLS_2_5GB:
2923 hw->bus.speed = i40e_bus_speed_2500;
2924 break;
2925 case PCI_EXP_LNKSTA_CLS_5_0GB:
2926 hw->bus.speed = i40e_bus_speed_5000;
2927 break;
2928 case PCI_EXP_LNKSTA_CLS_8_0GB:
2929 hw->bus.speed = i40e_bus_speed_8000;
2930 break;
2931 default:
2932 hw->bus.speed = i40e_bus_speed_unknown;
2933 break;
2934 }
2935}
Linux kernel - Deliverables
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