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i40e: use kernel specific defines
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_type.h"
29#include "i40e_adminq.h"
30#include "i40e_prototype.h"
31#include "i40e_virtchnl.h"
32
33/**
34 * i40e_set_mac_type - Sets MAC type
35 * @hw: pointer to the HW structure
36 *
37 * This function sets the mac type of the adapter based on the
38 * vendor ID and device ID stored in the hw structure.
39 **/
40static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
41{
42 i40e_status status = 0;
43
44 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
45 switch (hw->device_id) {
46 case I40E_SFP_XL710_DEVICE_ID:
47 case I40E_SFP_X710_DEVICE_ID:
48 case I40E_QEMU_DEVICE_ID:
49 case I40E_KX_A_DEVICE_ID:
50 case I40E_KX_B_DEVICE_ID:
51 case I40E_KX_C_DEVICE_ID:
52 case I40E_KX_D_DEVICE_ID:
53 case I40E_QSFP_A_DEVICE_ID:
54 case I40E_QSFP_B_DEVICE_ID:
55 case I40E_QSFP_C_DEVICE_ID:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_VF_DEVICE_ID:
59 case I40E_VF_HV_DEVICE_ID:
60 hw->mac.type = I40E_MAC_VF;
61 break;
62 default:
63 hw->mac.type = I40E_MAC_GENERIC;
64 break;
65 }
66 } else {
67 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
68 }
69
70 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
71 hw->mac.type, status);
72 return status;
73}
74
75/**
76 * i40e_debug_aq
77 * @hw: debug mask related to admin queue
78 * @cap: pointer to adminq command descriptor
79 * @buffer: pointer to command buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer)
85{
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u8 *aq_buffer = (u8 *)buffer;
88 u32 data[4];
89 u32 i = 0;
90
91 if ((!(mask & hw->debug_mask)) || (desc == NULL))
92 return;
93
94 i40e_debug(hw, mask,
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
97 aq_desc->retval);
98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc->cookie_high, aq_desc->cookie_low);
100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc->params.internal.param0,
102 aq_desc->params.internal.param1);
103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc->params.external.addr_high,
105 aq_desc->params.external.addr_low);
106
107 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
108 memset(data, 0, sizeof(data));
109 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
110 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
111 data[((i % 16) / 4)] |=
112 ((u32)aq_buffer[i]) << (8 * (i % 4));
113 if ((i % 16) == 15) {
114 i40e_debug(hw, mask,
115 "\t0x%04X %08X %08X %08X %08X\n",
116 i - 15, data[0], data[1], data[2],
117 data[3]);
118 memset(data, 0, sizeof(data));
119 }
120 }
121 if ((i % 16) != 0)
122 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
123 i - (i % 16), data[0], data[1], data[2],
124 data[3]);
125 }
126}
127
e1860d8f
ASJ		 128/**
129 * i40e_check_asq_alive
130 * @hw: pointer to the hw struct
131 *
132 * Returns true if Queue is enabled else false.
133 **/
134bool i40e_check_asq_alive(struct i40e_hw *hw)
135{
136 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
137}
138
139/**
140 * i40e_aq_queue_shutdown
141 * @hw: pointer to the hw struct
142 * @unloading: is the driver unloading itself
143 *
144 * Tell the Firmware that we're shutting down the AdminQ and whether
145 * or not the driver is unloading as well.
146 **/
147i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
148 bool unloading)
149{
150 struct i40e_aq_desc desc;
151 struct i40e_aqc_queue_shutdown *cmd =
152 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
153 i40e_status status;
154
155 i40e_fill_default_direct_cmd_desc(&desc,
156 i40e_aqc_opc_queue_shutdown);
157
158 if (unloading)
159 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
160 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
161
162 return status;
163}
164
165
56a62fc8
JB		 166/**
167 * i40e_init_shared_code - Initialize the shared code
168 * @hw: pointer to hardware structure
169 *
170 * This assigns the MAC type and PHY code and inits the NVM.
171 * Does not touch the hardware. This function must be called prior to any
172 * other function in the shared code. The i40e_hw structure should be
173 * memset to 0 prior to calling this function. The following fields in
174 * hw structure should be filled in prior to calling this function:
175 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
176 * subsystem_vendor_id, and revision_id
177 **/
178i40e_status i40e_init_shared_code(struct i40e_hw *hw)
179{
180 i40e_status status = 0;
181 u32 reg;
182
56a62fc8
JB		 183 i40e_set_mac_type(hw);
184
185 switch (hw->mac.type) {
186 case I40E_MAC_XL710:
187 break;
188 default:
189 return I40E_ERR_DEVICE_NOT_SUPPORTED;
190 break;
191 }
192
af89d26c
SN		 193 hw->phy.get_link_info = true;
194
195 /* Determine port number */
196 reg = rd32(hw, I40E_PFGEN_PORTNUM);
197 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
198 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
199 hw->port = (u8)reg;
200
5f9116ac
SN		 201 /* Determine the PF number based on the PCI fn */
202 reg = rd32(hw, I40E_GLPCI_CAPSUP);
203 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
204 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
205 else
206 hw->pf_id = (u8)hw->bus.func;
207
56a62fc8
JB		 208 status = i40e_init_nvm(hw);
209 return status;
210}
211
212/**
213 * i40e_aq_mac_address_read - Retrieve the MAC addresses
214 * @hw: pointer to the hw struct
215 * @flags: a return indicator of what addresses were added to the addr store
216 * @addrs: the requestor's mac addr store
217 * @cmd_details: pointer to command details structure or NULL
218 **/
219static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
220 u16 *flags,
221 struct i40e_aqc_mac_address_read_data *addrs,
222 struct i40e_asq_cmd_details *cmd_details)
223{
224 struct i40e_aq_desc desc;
225 struct i40e_aqc_mac_address_read *cmd_data =
226 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
227 i40e_status status;
228
229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
230 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
231
232 status = i40e_asq_send_command(hw, &desc, addrs,
233 sizeof(*addrs), cmd_details);
234 *flags = le16_to_cpu(cmd_data->command_flags);
235
236 return status;
237}
238
239/**
240 * i40e_aq_mac_address_write - Change the MAC addresses
241 * @hw: pointer to the hw struct
242 * @flags: indicates which MAC to be written
243 * @mac_addr: address to write
244 * @cmd_details: pointer to command details structure or NULL
245 **/
246i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
247 u16 flags, u8 *mac_addr,
248 struct i40e_asq_cmd_details *cmd_details)
249{
250 struct i40e_aq_desc desc;
251 struct i40e_aqc_mac_address_write *cmd_data =
252 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
253 i40e_status status;
254
255 i40e_fill_default_direct_cmd_desc(&desc,
256 i40e_aqc_opc_mac_address_write);
257 cmd_data->command_flags = cpu_to_le16(flags);
258 memcpy(&cmd_data->mac_sal, &mac_addr[0], 4);
259 memcpy(&cmd_data->mac_sah, &mac_addr[4], 2);
260
261 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
262
263 return status;
264}
265
266/**
267 * i40e_get_mac_addr - get MAC address
268 * @hw: pointer to the HW structure
269 * @mac_addr: pointer to MAC address
270 *
271 * Reads the adapter's MAC address from register
272 **/
273i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
274{
275 struct i40e_aqc_mac_address_read_data addrs;
276 i40e_status status;
277 u16 flags = 0;
278
279 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
280
281 if (flags & I40E_AQC_LAN_ADDR_VALID)
282 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
283
284 return status;
285}
286
be405eb0
JB		 287/**
288 * i40e_get_media_type - Gets media type
289 * @hw: pointer to the hardware structure
290 **/
291static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
292{
293 enum i40e_media_type media;
294
295 switch (hw->phy.link_info.phy_type) {
296 case I40E_PHY_TYPE_10GBASE_SR:
297 case I40E_PHY_TYPE_10GBASE_LR:
298 case I40E_PHY_TYPE_40GBASE_SR4:
299 case I40E_PHY_TYPE_40GBASE_LR4:
300 media = I40E_MEDIA_TYPE_FIBER;
301 break;
302 case I40E_PHY_TYPE_100BASE_TX:
303 case I40E_PHY_TYPE_1000BASE_T:
304 case I40E_PHY_TYPE_10GBASE_T:
305 media = I40E_MEDIA_TYPE_BASET;
306 break;
307 case I40E_PHY_TYPE_10GBASE_CR1_CU:
308 case I40E_PHY_TYPE_40GBASE_CR4_CU:
309 case I40E_PHY_TYPE_10GBASE_CR1:
310 case I40E_PHY_TYPE_40GBASE_CR4:
311 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
312 media = I40E_MEDIA_TYPE_DA;
313 break;
314 case I40E_PHY_TYPE_1000BASE_KX:
315 case I40E_PHY_TYPE_10GBASE_KX4:
316 case I40E_PHY_TYPE_10GBASE_KR:
317 case I40E_PHY_TYPE_40GBASE_KR4:
318 media = I40E_MEDIA_TYPE_BACKPLANE;
319 break;
320 case I40E_PHY_TYPE_SGMII:
321 case I40E_PHY_TYPE_XAUI:
322 case I40E_PHY_TYPE_XFI:
323 case I40E_PHY_TYPE_XLAUI:
324 case I40E_PHY_TYPE_XLPPI:
325 default:
326 media = I40E_MEDIA_TYPE_UNKNOWN;
327 break;
328 }
329
330 return media;
331}
332
7134f9ce
JB		 333#define I40E_PF_RESET_WAIT_COUNT_A0 200
334#define I40E_PF_RESET_WAIT_COUNT 10
56a62fc8
JB		 335/**
336 * i40e_pf_reset - Reset the PF
337 * @hw: pointer to the hardware structure
338 *
339 * Assuming someone else has triggered a global reset,
340 * assure the global reset is complete and then reset the PF
341 **/
342i40e_status i40e_pf_reset(struct i40e_hw *hw)
343{
7134f9ce 344 u32 cnt = 0;
42794bd8 345 u32 cnt1 = 0;
56a62fc8
JB		 346 u32 reg = 0;
347 u32 grst_del;
348
349 /* Poll for Global Reset steady state in case of recent GRST.
350 * The grst delay value is in 100ms units, and we'll wait a
351 * couple counts longer to be sure we don't just miss the end.
352 */
353 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
354 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 355 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 356 reg = rd32(hw, I40E_GLGEN_RSTAT);
357 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
358 break;
359 msleep(100);
360 }
361 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
362 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 363 return I40E_ERR_RESET_FAILED;
364 }
365
366 /* Now Wait for the FW to be ready */
367 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
368 reg = rd32(hw, I40E_GLNVM_ULD);
369 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
370 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
371 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
372 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
373 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
374 break;
375 }
376 usleep_range(10000, 20000);
377 }
378 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
379 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
380 hw_dbg(hw, "wait for FW Reset complete timedout\n");
381 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 382 return I40E_ERR_RESET_FAILED;
383 }
384
56a62fc8
JB		 385 /* If there was a Global Reset in progress when we got here,
386 * we don't need to do the PF Reset
387 */
7134f9ce
JB		 388 if (!cnt) {
389 if (hw->revision_id == 0)
390 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
391 else
392 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 393 reg = rd32(hw, I40E_PFGEN_CTRL);
394 wr32(hw, I40E_PFGEN_CTRL,
395 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 396 for (; cnt; cnt--) {
56a62fc8
JB		 397 reg = rd32(hw, I40E_PFGEN_CTRL);
398 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
399 break;
400 usleep_range(1000, 2000);
401 }
402 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
403 hw_dbg(hw, "PF reset polling failed to complete.\n");
404 return I40E_ERR_RESET_FAILED;
405 }
406 }
407
408 i40e_clear_pxe_mode(hw);
922680b9 409
56a62fc8
JB		 410 return 0;
411}
412
413/**
414 * i40e_clear_pxe_mode - clear pxe operations mode
415 * @hw: pointer to the hw struct
416 *
417 * Make sure all PXE mode settings are cleared, including things
418 * like descriptor fetch/write-back mode.
419 **/
420void i40e_clear_pxe_mode(struct i40e_hw *hw)
421{
422 u32 reg;
423
424 /* Clear single descriptor fetch/write-back mode */
425 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 426
427 if (hw->revision_id == 0) {
428 /* As a work around clear PXE_MODE instead of setting it */
429 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
430 } else {
431 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
432 }
56a62fc8
JB		 433}
434
0556a9e3
JB		 435/**
436 * i40e_led_is_mine - helper to find matching led
437 * @hw: pointer to the hw struct
438 * @idx: index into GPIO registers
439 *
440 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
441 */
442static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
443{
444 u32 gpio_val = 0;
445 u32 port;
446
447 if (!hw->func_caps.led[idx])
448 return 0;
449
450 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
451 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
452 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
453
454 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
455 * if it is not our port then ignore
456 */
457 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
458 (port != hw->port))
459 return 0;
460
461 return gpio_val;
462}
463
464#define I40E_LED0 22
465#define I40E_LINK_ACTIVITY 0xC
466
56a62fc8
JB		 467/**
468 * i40e_led_get - return current on/off mode
469 * @hw: pointer to the hw struct
470 *
471 * The value returned is the 'mode' field as defined in the
472 * GPIO register definitions: 0x0 = off, 0xf = on, and other
473 * values are variations of possible behaviors relating to
474 * blink, link, and wire.
475 **/
476u32 i40e_led_get(struct i40e_hw *hw)
477{
56a62fc8 478 u32 mode = 0;
56a62fc8
JB		 479 int i;
480
0556a9e3
JB		 481 /* as per the documentation GPIO 22-29 are the LED
482 * GPIO pins named LED0..LED7
483 */
484 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
485 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 486
0556a9e3 487 if (!gpio_val)
56a62fc8
JB		 488 continue;
489
0556a9e3
JB		 490 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
491 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 492 break;
493 }
494
495 return mode;
496}
497
498/**
499 * i40e_led_set - set new on/off mode
500 * @hw: pointer to the hw struct
0556a9e3
JB		 501 * @mode: 0=off, 0xf=on (else see manual for mode details)
502 * @blink: true if the LED should blink when on, false if steady
503 *
504 * if this function is used to turn on the blink it should
505 * be used to disable the blink when restoring the original state.
56a62fc8 506 **/
0556a9e3 507void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 508{
56a62fc8
JB		 509 int i;
510
0556a9e3
JB		 511 if (mode & 0xfffffff0)
512 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 513
0556a9e3
JB		 514 /* as per the documentation GPIO 22-29 are the LED
515 * GPIO pins named LED0..LED7
516 */
517 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
518 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 519
0556a9e3 520 if (!gpio_val)
56a62fc8
JB		 521 continue;
522
56a62fc8 523 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 524 /* this & is a bit of paranoia, but serves as a range check */
525 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
526 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
527
528 if (mode == I40E_LINK_ACTIVITY)
529 blink = false;
530
531 gpio_val |= (blink ? 1 : 0) <<
532 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
533
56a62fc8 534 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 535 break;
56a62fc8
JB		 536 }
537}
538
539/* Admin command wrappers */
56a62fc8
JB		 540
541/**
542 * i40e_aq_set_link_restart_an
543 * @hw: pointer to the hw struct
544 * @cmd_details: pointer to command details structure or NULL
545 *
546 * Sets up the link and restarts the Auto-Negotiation over the link.
547 **/
548i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
549 struct i40e_asq_cmd_details *cmd_details)
550{
551 struct i40e_aq_desc desc;
552 struct i40e_aqc_set_link_restart_an *cmd =
553 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
554 i40e_status status;
555
556 i40e_fill_default_direct_cmd_desc(&desc,
557 i40e_aqc_opc_set_link_restart_an);
558
559 cmd->command = I40E_AQ_PHY_RESTART_AN;
560
561 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
562
563 return status;
564}
565
566/**
567 * i40e_aq_get_link_info
568 * @hw: pointer to the hw struct
569 * @enable_lse: enable/disable LinkStatusEvent reporting
570 * @link: pointer to link status structure - optional
571 * @cmd_details: pointer to command details structure or NULL
572 *
573 * Returns the link status of the adapter.
574 **/
575i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
576 bool enable_lse, struct i40e_link_status *link,
577 struct i40e_asq_cmd_details *cmd_details)
578{
579 struct i40e_aq_desc desc;
580 struct i40e_aqc_get_link_status *resp =
581 (struct i40e_aqc_get_link_status *)&desc.params.raw;
582 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
583 i40e_status status;
584 u16 command_flags;
585
586 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
587
588 if (enable_lse)
589 command_flags = I40E_AQ_LSE_ENABLE;
590 else
591 command_flags = I40E_AQ_LSE_DISABLE;
592 resp->command_flags = cpu_to_le16(command_flags);
593
594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
595
596 if (status)
597 goto aq_get_link_info_exit;
598
599 /* save off old link status information */
600 memcpy(&hw->phy.link_info_old, hw_link_info,
601 sizeof(struct i40e_link_status));
602
603 /* update link status */
604 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 605 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 606 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
607 hw_link_info->link_info = resp->link_info;
608 hw_link_info->an_info = resp->an_info;
609 hw_link_info->ext_info = resp->ext_info;
639dc377 610 hw_link_info->loopback = resp->loopback;
56a62fc8
JB		 611
612 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
613 hw_link_info->lse_enable = true;
614 else
615 hw_link_info->lse_enable = false;
616
617 /* save link status information */
618 if (link)
d7595a22 619 *link = *hw_link_info;
56a62fc8
JB		 620
621 /* flag cleared so helper functions don't call AQ again */
622 hw->phy.get_link_info = false;
623
624aq_get_link_info_exit:
625 return status;
626}
627
628/**
629 * i40e_aq_add_vsi
630 * @hw: pointer to the hw struct
631 * @vsi: pointer to a vsi context struct
632 * @cmd_details: pointer to command details structure or NULL
633 *
634 * Add a VSI context to the hardware.
635**/
636i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
637 struct i40e_vsi_context *vsi_ctx,
638 struct i40e_asq_cmd_details *cmd_details)
639{
640 struct i40e_aq_desc desc;
641 struct i40e_aqc_add_get_update_vsi *cmd =
642 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
643 struct i40e_aqc_add_get_update_vsi_completion *resp =
644 (struct i40e_aqc_add_get_update_vsi_completion *)
645 &desc.params.raw;
646 i40e_status status;
647
648 i40e_fill_default_direct_cmd_desc(&desc,
649 i40e_aqc_opc_add_vsi);
650
651 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
652 cmd->connection_type = vsi_ctx->connection_type;
653 cmd->vf_id = vsi_ctx->vf_num;
654 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
655
656 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
657 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
658 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
659
660 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
661 sizeof(vsi_ctx->info), cmd_details);
662
663 if (status)
664 goto aq_add_vsi_exit;
665
666 vsi_ctx->seid = le16_to_cpu(resp->seid);
667 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
668 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
669 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
670
671aq_add_vsi_exit:
672 return status;
673}
674
675/**
676 * i40e_aq_set_vsi_unicast_promiscuous
677 * @hw: pointer to the hw struct
678 * @seid: vsi number
679 * @set: set unicast promiscuous enable/disable
680 * @cmd_details: pointer to command details structure or NULL
681 **/
682i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
683 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
684{
685 struct i40e_aq_desc desc;
686 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
687 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
688 i40e_status status;
689 u16 flags = 0;
690
691 i40e_fill_default_direct_cmd_desc(&desc,
692 i40e_aqc_opc_set_vsi_promiscuous_modes);
693
694 if (set)
695 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
696
697 cmd->promiscuous_flags = cpu_to_le16(flags);
698
699 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
700
701 cmd->seid = cpu_to_le16(seid);
702 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
703
704 return status;
705}
706
707/**
708 * i40e_aq_set_vsi_multicast_promiscuous
709 * @hw: pointer to the hw struct
710 * @seid: vsi number
711 * @set: set multicast promiscuous enable/disable
712 * @cmd_details: pointer to command details structure or NULL
713 **/
714i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
715 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
716{
717 struct i40e_aq_desc desc;
718 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
719 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
720 i40e_status status;
721 u16 flags = 0;
722
723 i40e_fill_default_direct_cmd_desc(&desc,
724 i40e_aqc_opc_set_vsi_promiscuous_modes);
725
726 if (set)
727 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
728
729 cmd->promiscuous_flags = cpu_to_le16(flags);
730
731 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
732
733 cmd->seid = cpu_to_le16(seid);
734 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
735
736 return status;
737}
738
739/**
740 * i40e_aq_set_vsi_broadcast
741 * @hw: pointer to the hw struct
742 * @seid: vsi number
743 * @set_filter: true to set filter, false to clear filter
744 * @cmd_details: pointer to command details structure or NULL
745 *
746 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
747 **/
748i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
749 u16 seid, bool set_filter,
750 struct i40e_asq_cmd_details *cmd_details)
751{
752 struct i40e_aq_desc desc;
753 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
754 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
755 i40e_status status;
756
757 i40e_fill_default_direct_cmd_desc(&desc,
758 i40e_aqc_opc_set_vsi_promiscuous_modes);
759
760 if (set_filter)
761 cmd->promiscuous_flags
762 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
763 else
764 cmd->promiscuous_flags
765 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
766
767 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
768 cmd->seid = cpu_to_le16(seid);
769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
770
771 return status;
772}
773
774/**
775 * i40e_get_vsi_params - get VSI configuration info
776 * @hw: pointer to the hw struct
777 * @vsi: pointer to a vsi context struct
778 * @cmd_details: pointer to command details structure or NULL
779 **/
780i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
781 struct i40e_vsi_context *vsi_ctx,
782 struct i40e_asq_cmd_details *cmd_details)
783{
784 struct i40e_aq_desc desc;
f5ac8579
SN		 785 struct i40e_aqc_add_get_update_vsi *cmd =
786 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 787 struct i40e_aqc_add_get_update_vsi_completion *resp =
788 (struct i40e_aqc_add_get_update_vsi_completion *)
789 &desc.params.raw;
790 i40e_status status;
791
792 i40e_fill_default_direct_cmd_desc(&desc,
793 i40e_aqc_opc_get_vsi_parameters);
794
f5ac8579 795 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 796
797 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
798 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
799 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
800
801 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
802 sizeof(vsi_ctx->info), NULL);
803
804 if (status)
805 goto aq_get_vsi_params_exit;
806
807 vsi_ctx->seid = le16_to_cpu(resp->seid);
808 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
809 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
810 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
811
812aq_get_vsi_params_exit:
813 return status;
814}
815
816/**
817 * i40e_aq_update_vsi_params
818 * @hw: pointer to the hw struct
819 * @vsi: pointer to a vsi context struct
820 * @cmd_details: pointer to command details structure or NULL
821 *
822 * Update a VSI context.
823 **/
824i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
825 struct i40e_vsi_context *vsi_ctx,
826 struct i40e_asq_cmd_details *cmd_details)
827{
828 struct i40e_aq_desc desc;
f5ac8579
SN		 829 struct i40e_aqc_add_get_update_vsi *cmd =
830 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 831 i40e_status status;
832
833 i40e_fill_default_direct_cmd_desc(&desc,
834 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 835 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 836
837 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
838 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
839 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
840
841 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
842 sizeof(vsi_ctx->info), cmd_details);
843
844 return status;
845}
846
847/**
848 * i40e_aq_get_switch_config
849 * @hw: pointer to the hardware structure
850 * @buf: pointer to the result buffer
851 * @buf_size: length of input buffer
852 * @start_seid: seid to start for the report, 0 == beginning
853 * @cmd_details: pointer to command details structure or NULL
854 *
855 * Fill the buf with switch configuration returned from AdminQ command
856 **/
857i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
858 struct i40e_aqc_get_switch_config_resp *buf,
859 u16 buf_size, u16 *start_seid,
860 struct i40e_asq_cmd_details *cmd_details)
861{
862 struct i40e_aq_desc desc;
863 struct i40e_aqc_switch_seid *scfg =
864 (struct i40e_aqc_switch_seid *)&desc.params.raw;
865 i40e_status status;
866
867 i40e_fill_default_direct_cmd_desc(&desc,
868 i40e_aqc_opc_get_switch_config);
869 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
870 if (buf_size > I40E_AQ_LARGE_BUF)
871 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
872 scfg->seid = cpu_to_le16(*start_seid);
873
874 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
875 *start_seid = le16_to_cpu(scfg->seid);
876
877 return status;
878}
879
880/**
881 * i40e_aq_get_firmware_version
882 * @hw: pointer to the hw struct
883 * @fw_major_version: firmware major version
884 * @fw_minor_version: firmware minor version
885 * @api_major_version: major queue version
886 * @api_minor_version: minor queue version
887 * @cmd_details: pointer to command details structure or NULL
888 *
889 * Get the firmware version from the admin queue commands
890 **/
891i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
892 u16 *fw_major_version, u16 *fw_minor_version,
893 u16 *api_major_version, u16 *api_minor_version,
894 struct i40e_asq_cmd_details *cmd_details)
895{
896 struct i40e_aq_desc desc;
897 struct i40e_aqc_get_version *resp =
898 (struct i40e_aqc_get_version *)&desc.params.raw;
899 i40e_status status;
900
901 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
902
903 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
904
905 if (!status) {
906 if (fw_major_version != NULL)
907 *fw_major_version = le16_to_cpu(resp->fw_major);
908 if (fw_minor_version != NULL)
909 *fw_minor_version = le16_to_cpu(resp->fw_minor);
910 if (api_major_version != NULL)
911 *api_major_version = le16_to_cpu(resp->api_major);
912 if (api_minor_version != NULL)
913 *api_minor_version = le16_to_cpu(resp->api_minor);
914 }
915
916 return status;
917}
918
919/**
920 * i40e_aq_send_driver_version
921 * @hw: pointer to the hw struct
922 * @event: driver event: driver ok, start or stop
923 * @dv: driver's major, minor version
924 * @cmd_details: pointer to command details structure or NULL
925 *
926 * Send the driver version to the firmware
927 **/
928i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
929 struct i40e_driver_version *dv,
930 struct i40e_asq_cmd_details *cmd_details)
931{
932 struct i40e_aq_desc desc;
933 struct i40e_aqc_driver_version *cmd =
934 (struct i40e_aqc_driver_version *)&desc.params.raw;
935 i40e_status status;
936
937 if (dv == NULL)
938 return I40E_ERR_PARAM;
939
940 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
941
942 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
943 cmd->driver_major_ver = dv->major_version;
944 cmd->driver_minor_ver = dv->minor_version;
945 cmd->driver_build_ver = dv->build_version;
946 cmd->driver_subbuild_ver = dv->subbuild_version;
947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
948
949 return status;
950}
951
952/**
953 * i40e_get_link_status - get status of the HW network link
954 * @hw: pointer to the hw struct
955 *
956 * Returns true if link is up, false if link is down.
957 *
958 * Side effect: LinkStatusEvent reporting becomes enabled
959 **/
960bool i40e_get_link_status(struct i40e_hw *hw)
961{
962 i40e_status status = 0;
963 bool link_status = false;
964
965 if (hw->phy.get_link_info) {
966 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
967
968 if (status)
969 goto i40e_get_link_status_exit;
970 }
971
972 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
973
974i40e_get_link_status_exit:
975 return link_status;
976}
977
978/**
979 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
980 * @hw: pointer to the hw struct
981 * @uplink_seid: the MAC or other gizmo SEID
982 * @downlink_seid: the VSI SEID
983 * @enabled_tc: bitmap of TCs to be enabled
984 * @default_port: true for default port VSI, false for control port
e1c51b95 985 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 986 * @veb_seid: pointer to where to put the resulting VEB SEID
987 * @cmd_details: pointer to command details structure or NULL
988 *
989 * This asks the FW to add a VEB between the uplink and downlink
990 * elements. If the uplink SEID is 0, this will be a floating VEB.
991 **/
992i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
993 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 994 bool default_port, bool enable_l2_filtering,
995 u16 *veb_seid,
56a62fc8
JB		 996 struct i40e_asq_cmd_details *cmd_details)
997{
998 struct i40e_aq_desc desc;
999 struct i40e_aqc_add_veb *cmd =
1000 (struct i40e_aqc_add_veb *)&desc.params.raw;
1001 struct i40e_aqc_add_veb_completion *resp =
1002 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1003 i40e_status status;
1004 u16 veb_flags = 0;
1005
1006 /* SEIDs need to either both be set or both be 0 for floating VEB */
1007 if (!!uplink_seid != !!downlink_seid)
1008 return I40E_ERR_PARAM;
1009
1010 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1011
1012 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1013 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1014 cmd->enable_tcs = enabled_tc;
1015 if (!uplink_seid)
1016 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1017 if (default_port)
1018 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1019 else
1020 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1021
1022 if (enable_l2_filtering)
1023 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1024
56a62fc8
JB		 1025 cmd->veb_flags = cpu_to_le16(veb_flags);
1026
1027 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1028
1029 if (!status && veb_seid)
1030 *veb_seid = le16_to_cpu(resp->veb_seid);
1031
1032 return status;
1033}
1034
1035/**
1036 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1037 * @hw: pointer to the hw struct
1038 * @veb_seid: the SEID of the VEB to query
1039 * @switch_id: the uplink switch id
1040 * @floating_veb: set to true if the VEB is floating
1041 * @statistic_index: index of the stats counter block for this VEB
1042 * @vebs_used: number of VEB's used by function
1043 * @vebs_unallocated: total VEB's not reserved by any function
1044 * @cmd_details: pointer to command details structure or NULL
1045 *
1046 * This retrieves the parameters for a particular VEB, specified by
1047 * uplink_seid, and returns them to the caller.
1048 **/
1049i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1050 u16 veb_seid, u16 *switch_id,
1051 bool *floating, u16 *statistic_index,
1052 u16 *vebs_used, u16 *vebs_free,
1053 struct i40e_asq_cmd_details *cmd_details)
1054{
1055 struct i40e_aq_desc desc;
1056 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1057 (struct i40e_aqc_get_veb_parameters_completion *)
1058 &desc.params.raw;
1059 i40e_status status;
1060
1061 if (veb_seid == 0)
1062 return I40E_ERR_PARAM;
1063
1064 i40e_fill_default_direct_cmd_desc(&desc,
1065 i40e_aqc_opc_get_veb_parameters);
1066 cmd_resp->seid = cpu_to_le16(veb_seid);
1067
1068 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1069 if (status)
1070 goto get_veb_exit;
1071
1072 if (switch_id)
1073 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1074 if (statistic_index)
1075 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1076 if (vebs_used)
1077 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1078 if (vebs_free)
1079 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1080 if (floating) {
1081 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1082 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1083 *floating = true;
1084 else
1085 *floating = false;
1086 }
1087
1088get_veb_exit:
1089 return status;
1090}
1091
1092/**
1093 * i40e_aq_add_macvlan
1094 * @hw: pointer to the hw struct
1095 * @seid: VSI for the mac address
1096 * @mv_list: list of macvlans to be added
1097 * @count: length of the list
1098 * @cmd_details: pointer to command details structure or NULL
1099 *
1100 * Add MAC/VLAN addresses to the HW filtering
1101 **/
1102i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1103 struct i40e_aqc_add_macvlan_element_data *mv_list,
1104 u16 count, struct i40e_asq_cmd_details *cmd_details)
1105{
1106 struct i40e_aq_desc desc;
1107 struct i40e_aqc_macvlan *cmd =
1108 (struct i40e_aqc_macvlan *)&desc.params.raw;
1109 i40e_status status;
1110 u16 buf_size;
1111
1112 if (count == 0 || !mv_list || !hw)
1113 return I40E_ERR_PARAM;
1114
1115 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1116
1117 /* prep the rest of the request */
1118 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1119 cmd->num_addresses = cpu_to_le16(count);
1120 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1121 cmd->seid[1] = 0;
1122 cmd->seid[2] = 0;
1123
1124 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1125 if (buf_size > I40E_AQ_LARGE_BUF)
1126 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1127
1128 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1129 cmd_details);
1130
1131 return status;
1132}
1133
1134/**
1135 * i40e_aq_remove_macvlan
1136 * @hw: pointer to the hw struct
1137 * @seid: VSI for the mac address
1138 * @mv_list: list of macvlans to be removed
1139 * @count: length of the list
1140 * @cmd_details: pointer to command details structure or NULL
1141 *
1142 * Remove MAC/VLAN addresses from the HW filtering
1143 **/
1144i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1145 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1146 u16 count, struct i40e_asq_cmd_details *cmd_details)
1147{
1148 struct i40e_aq_desc desc;
1149 struct i40e_aqc_macvlan *cmd =
1150 (struct i40e_aqc_macvlan *)&desc.params.raw;
1151 i40e_status status;
1152 u16 buf_size;
1153
1154 if (count == 0 || !mv_list || !hw)
1155 return I40E_ERR_PARAM;
1156
1157 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1158
1159 /* prep the rest of the request */
1160 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1161 cmd->num_addresses = cpu_to_le16(count);
1162 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1163 cmd->seid[1] = 0;
1164 cmd->seid[2] = 0;
1165
1166 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1167 if (buf_size > I40E_AQ_LARGE_BUF)
1168 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1169
1170 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1171 cmd_details);
1172
1173 return status;
1174}
1175
56a62fc8
JB		 1176/**
1177 * i40e_aq_send_msg_to_vf
1178 * @hw: pointer to the hardware structure
1179 * @vfid: vf id to send msg
1180 * @msg: pointer to the msg buffer
1181 * @msglen: msg length
1182 * @cmd_details: pointer to command details
1183 *
1184 * send msg to vf
1185 **/
1186i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1187 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1188 struct i40e_asq_cmd_details *cmd_details)
1189{
1190 struct i40e_aq_desc desc;
1191 struct i40e_aqc_pf_vf_message *cmd =
1192 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1193 i40e_status status;
1194
1195 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1196 cmd->id = cpu_to_le32(vfid);
1197 desc.cookie_high = cpu_to_le32(v_opcode);
1198 desc.cookie_low = cpu_to_le32(v_retval);
1199 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1200 if (msglen) {
1201 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1202 I40E_AQ_FLAG_RD));
1203 if (msglen > I40E_AQ_LARGE_BUF)
1204 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1205 desc.datalen = cpu_to_le16(msglen);
1206 }
1207 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1208
1209 return status;
1210}
1211
1212/**
1213 * i40e_aq_set_hmc_resource_profile
1214 * @hw: pointer to the hw struct
1215 * @profile: type of profile the HMC is to be set as
1216 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1217 * @cmd_details: pointer to command details structure or NULL
1218 *
1219 * set the HMC profile of the device.
1220 **/
1221i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1222 enum i40e_aq_hmc_profile profile,
1223 u8 pe_vf_enabled_count,
1224 struct i40e_asq_cmd_details *cmd_details)
1225{
1226 struct i40e_aq_desc desc;
1227 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1228 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1229 i40e_status status;
1230
1231 i40e_fill_default_direct_cmd_desc(&desc,
1232 i40e_aqc_opc_set_hmc_resource_profile);
1233
1234 cmd->pm_profile = (u8)profile;
1235 cmd->pe_vf_enabled = pe_vf_enabled_count;
1236
1237 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1238
1239 return status;
1240}
1241
1242/**
1243 * i40e_aq_request_resource
1244 * @hw: pointer to the hw struct
1245 * @resource: resource id
1246 * @access: access type
1247 * @sdp_number: resource number
1248 * @timeout: the maximum time in ms that the driver may hold the resource
1249 * @cmd_details: pointer to command details structure or NULL
1250 *
1251 * requests common resource using the admin queue commands
1252 **/
1253i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1254 enum i40e_aq_resources_ids resource,
1255 enum i40e_aq_resource_access_type access,
1256 u8 sdp_number, u64 *timeout,
1257 struct i40e_asq_cmd_details *cmd_details)
1258{
1259 struct i40e_aq_desc desc;
1260 struct i40e_aqc_request_resource *cmd_resp =
1261 (struct i40e_aqc_request_resource *)&desc.params.raw;
1262 i40e_status status;
1263
1264 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1265
1266 cmd_resp->resource_id = cpu_to_le16(resource);
1267 cmd_resp->access_type = cpu_to_le16(access);
1268 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1269
1270 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1271 /* The completion specifies the maximum time in ms that the driver
1272 * may hold the resource in the Timeout field.
1273 * If the resource is held by someone else, the command completes with
1274 * busy return value and the timeout field indicates the maximum time
1275 * the current owner of the resource has to free it.
1276 */
1277 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1278 *timeout = le32_to_cpu(cmd_resp->timeout);
1279
1280 return status;
1281}
1282
1283/**
1284 * i40e_aq_release_resource
1285 * @hw: pointer to the hw struct
1286 * @resource: resource id
1287 * @sdp_number: resource number
1288 * @cmd_details: pointer to command details structure or NULL
1289 *
1290 * release common resource using the admin queue commands
1291 **/
1292i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1293 enum i40e_aq_resources_ids resource,
1294 u8 sdp_number,
1295 struct i40e_asq_cmd_details *cmd_details)
1296{
1297 struct i40e_aq_desc desc;
1298 struct i40e_aqc_request_resource *cmd =
1299 (struct i40e_aqc_request_resource *)&desc.params.raw;
1300 i40e_status status;
1301
1302 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1303
1304 cmd->resource_id = cpu_to_le16(resource);
1305 cmd->resource_number = cpu_to_le32(sdp_number);
1306
1307 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1308
1309 return status;
1310}
1311
1312/**
1313 * i40e_aq_read_nvm
1314 * @hw: pointer to the hw struct
1315 * @module_pointer: module pointer location in words from the NVM beginning
1316 * @offset: byte offset from the module beginning
1317 * @length: length of the section to be read (in bytes from the offset)
1318 * @data: command buffer (size [bytes] = length)
1319 * @last_command: tells if this is the last command in a series
1320 * @cmd_details: pointer to command details structure or NULL
1321 *
1322 * Read the NVM using the admin queue commands
1323 **/
1324i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1325 u32 offset, u16 length, void *data,
1326 bool last_command,
1327 struct i40e_asq_cmd_details *cmd_details)
1328{
1329 struct i40e_aq_desc desc;
1330 struct i40e_aqc_nvm_update *cmd =
1331 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1332 i40e_status status;
1333
1334 /* In offset the highest byte must be zeroed. */
1335 if (offset & 0xFF000000) {
1336 status = I40E_ERR_PARAM;
1337 goto i40e_aq_read_nvm_exit;
1338 }
1339
1340 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1341
1342 /* If this is the last command in a series, set the proper flag. */
1343 if (last_command)
1344 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1345 cmd->module_pointer = module_pointer;
1346 cmd->offset = cpu_to_le32(offset);
1347 cmd->length = cpu_to_le16(length);
1348
1349 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1350 if (length > I40E_AQ_LARGE_BUF)
1351 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1352
1353 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1354
1355i40e_aq_read_nvm_exit:
1356 return status;
1357}
1358
1359#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1360#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1361#define I40E_DEV_FUNC_CAP_NPAR 0x03
1362#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1363#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1364#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1365#define I40E_DEV_FUNC_CAP_VF 0x13
1366#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1367#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1368#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1369#define I40E_DEV_FUNC_CAP_VSI 0x17
1370#define I40E_DEV_FUNC_CAP_DCB 0x18
1371#define I40E_DEV_FUNC_CAP_FCOE 0x21
1372#define I40E_DEV_FUNC_CAP_RSS 0x40
1373#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1374#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1375#define I40E_DEV_FUNC_CAP_MSIX 0x43
1376#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1377#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1378#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1379#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1380#define I40E_DEV_FUNC_CAP_CEM 0xF2
1381#define I40E_DEV_FUNC_CAP_IWARP 0x51
1382#define I40E_DEV_FUNC_CAP_LED 0x61
1383#define I40E_DEV_FUNC_CAP_SDP 0x62
1384#define I40E_DEV_FUNC_CAP_MDIO 0x63
1385
1386/**
1387 * i40e_parse_discover_capabilities
1388 * @hw: pointer to the hw struct
1389 * @buff: pointer to a buffer containing device/function capability records
1390 * @cap_count: number of capability records in the list
1391 * @list_type_opc: type of capabilities list to parse
1392 *
1393 * Parse the device/function capabilities list.
1394 **/
1395static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1396 u32 cap_count,
1397 enum i40e_admin_queue_opc list_type_opc)
1398{
1399 struct i40e_aqc_list_capabilities_element_resp *cap;
1400 u32 number, logical_id, phys_id;
1401 struct i40e_hw_capabilities *p;
1402 u32 reg_val;
1403 u32 i = 0;
1404 u16 id;
1405
1406 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1407
1408 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
1409 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
1410 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
1411 p = (struct i40e_hw_capabilities *)&hw->func_caps;
1412 else
1413 return;
1414
1415 for (i = 0; i < cap_count; i++, cap++) {
1416 id = le16_to_cpu(cap->id);
1417 number = le32_to_cpu(cap->number);
1418 logical_id = le32_to_cpu(cap->logical_id);
1419 phys_id = le32_to_cpu(cap->phys_id);
1420
1421 switch (id) {
1422 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1423 p->switch_mode = number;
1424 break;
1425 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1426 p->management_mode = number;
1427 break;
1428 case I40E_DEV_FUNC_CAP_NPAR:
1429 p->npar_enable = number;
1430 break;
1431 case I40E_DEV_FUNC_CAP_OS2BMC:
1432 p->os2bmc = number;
1433 break;
1434 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1435 p->valid_functions = number;
1436 break;
1437 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1438 if (number == 1)
1439 p->sr_iov_1_1 = true;
1440 break;
1441 case I40E_DEV_FUNC_CAP_VF:
1442 p->num_vfs = number;
1443 p->vf_base_id = logical_id;
1444 break;
1445 case I40E_DEV_FUNC_CAP_VMDQ:
1446 if (number == 1)
1447 p->vmdq = true;
1448 break;
1449 case I40E_DEV_FUNC_CAP_802_1_QBG:
1450 if (number == 1)
1451 p->evb_802_1_qbg = true;
1452 break;
1453 case I40E_DEV_FUNC_CAP_802_1_QBH:
1454 if (number == 1)
1455 p->evb_802_1_qbh = true;
1456 break;
1457 case I40E_DEV_FUNC_CAP_VSI:
1458 p->num_vsis = number;
1459 break;
1460 case I40E_DEV_FUNC_CAP_DCB:
1461 if (number == 1) {
1462 p->dcb = true;
1463 p->enabled_tcmap = logical_id;
1464 p->maxtc = phys_id;
1465 }
1466 break;
1467 case I40E_DEV_FUNC_CAP_FCOE:
1468 if (number == 1)
1469 p->fcoe = true;
1470 break;
1471 case I40E_DEV_FUNC_CAP_RSS:
1472 p->rss = true;
1473 reg_val = rd32(hw, I40E_PFQF_CTL_0);
1474 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1475 p->rss_table_size = number;
1476 else
1477 p->rss_table_size = 128;
1478 p->rss_table_entry_width = logical_id;
1479 break;
1480 case I40E_DEV_FUNC_CAP_RX_QUEUES:
1481 p->num_rx_qp = number;
1482 p->base_queue = phys_id;
1483 break;
1484 case I40E_DEV_FUNC_CAP_TX_QUEUES:
1485 p->num_tx_qp = number;
1486 p->base_queue = phys_id;
1487 break;
1488 case I40E_DEV_FUNC_CAP_MSIX:
1489 p->num_msix_vectors = number;
1490 break;
1491 case I40E_DEV_FUNC_CAP_MSIX_VF:
1492 p->num_msix_vectors_vf = number;
1493 break;
1494 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
1495 if (number == 1)
1496 p->mfp_mode_1 = true;
1497 break;
1498 case I40E_DEV_FUNC_CAP_CEM:
1499 if (number == 1)
1500 p->mgmt_cem = true;
1501 break;
1502 case I40E_DEV_FUNC_CAP_IWARP:
1503 if (number == 1)
1504 p->iwarp = true;
1505 break;
1506 case I40E_DEV_FUNC_CAP_LED:
1507 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1508 p->led[phys_id] = true;
1509 break;
1510 case I40E_DEV_FUNC_CAP_SDP:
1511 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1512 p->sdp[phys_id] = true;
1513 break;
1514 case I40E_DEV_FUNC_CAP_MDIO:
1515 if (number == 1) {
1516 p->mdio_port_num = phys_id;
1517 p->mdio_port_mode = logical_id;
1518 }
1519 break;
1520 case I40E_DEV_FUNC_CAP_IEEE_1588:
1521 if (number == 1)
1522 p->ieee_1588 = true;
1523 break;
1524 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
1525 p->fd = true;
1526 p->fd_filters_guaranteed = number;
1527 p->fd_filters_best_effort = logical_id;
1528 break;
1529 default:
1530 break;
1531 }
1532 }
1533
1534 /* additional HW specific goodies that might
1535 * someday be HW version specific
1536 */
1537 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
1538}
1539
1540/**
1541 * i40e_aq_discover_capabilities
1542 * @hw: pointer to the hw struct
1543 * @buff: a virtual buffer to hold the capabilities
1544 * @buff_size: Size of the virtual buffer
1545 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1546 * @list_type_opc: capabilities type to discover - pass in the command opcode
1547 * @cmd_details: pointer to command details structure or NULL
1548 *
1549 * Get the device capabilities descriptions from the firmware
1550 **/
1551i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
1552 void *buff, u16 buff_size, u16 *data_size,
1553 enum i40e_admin_queue_opc list_type_opc,
1554 struct i40e_asq_cmd_details *cmd_details)
1555{
1556 struct i40e_aqc_list_capabilites *cmd;
1557 i40e_status status = 0;
1558 struct i40e_aq_desc desc;
1559
1560 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
1561
1562 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
1563 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
1564 status = I40E_ERR_PARAM;
1565 goto exit;
1566 }
1567
1568 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
1569
1570 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1571 if (buff_size > I40E_AQ_LARGE_BUF)
1572 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1573
1574 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1575 *data_size = le16_to_cpu(desc.datalen);
1576
1577 if (status)
1578 goto exit;
1579
1580 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
1581 list_type_opc);
1582
1583exit:
1584 return status;
1585}
1586
1587/**
1588 * i40e_aq_get_lldp_mib
1589 * @hw: pointer to the hw struct
1590 * @bridge_type: type of bridge requested
1591 * @mib_type: Local, Remote or both Local and Remote MIBs
1592 * @buff: pointer to a user supplied buffer to store the MIB block
1593 * @buff_size: size of the buffer (in bytes)
1594 * @local_len : length of the returned Local LLDP MIB
1595 * @remote_len: length of the returned Remote LLDP MIB
1596 * @cmd_details: pointer to command details structure or NULL
1597 *
1598 * Requests the complete LLDP MIB (entire packet).
1599 **/
1600i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
1601 u8 mib_type, void *buff, u16 buff_size,
1602 u16 *local_len, u16 *remote_len,
1603 struct i40e_asq_cmd_details *cmd_details)
1604{
1605 struct i40e_aq_desc desc;
1606 struct i40e_aqc_lldp_get_mib *cmd =
1607 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1608 struct i40e_aqc_lldp_get_mib *resp =
1609 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1610 i40e_status status;
1611
1612 if (buff_size == 0 || !buff)
1613 return I40E_ERR_PARAM;
1614
1615 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
1616 /* Indirect Command */
1617 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1618
1619 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
1620 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
1621 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
1622
1623 desc.datalen = cpu_to_le16(buff_size);
1624
1625 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1626 if (buff_size > I40E_AQ_LARGE_BUF)
1627 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1628
1629 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1630 if (!status) {
1631 if (local_len != NULL)
1632 *local_len = le16_to_cpu(resp->local_len);
1633 if (remote_len != NULL)
1634 *remote_len = le16_to_cpu(resp->remote_len);
1635 }
1636
1637 return status;
1638}
1639
1640/**
1641 * i40e_aq_cfg_lldp_mib_change_event
1642 * @hw: pointer to the hw struct
1643 * @enable_update: Enable or Disable event posting
1644 * @cmd_details: pointer to command details structure or NULL
1645 *
1646 * Enable or Disable posting of an event on ARQ when LLDP MIB
1647 * associated with the interface changes
1648 **/
1649i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
1650 bool enable_update,
1651 struct i40e_asq_cmd_details *cmd_details)
1652{
1653 struct i40e_aq_desc desc;
1654 struct i40e_aqc_lldp_update_mib *cmd =
1655 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
1656 i40e_status status;
1657
1658 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
1659
1660 if (!enable_update)
1661 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
1662
1663 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1664
1665 return status;
1666}
1667
1668/**
1669 * i40e_aq_stop_lldp
1670 * @hw: pointer to the hw struct
1671 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
1672 * @cmd_details: pointer to command details structure or NULL
1673 *
1674 * Stop or Shutdown the embedded LLDP Agent
1675 **/
1676i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
1677 struct i40e_asq_cmd_details *cmd_details)
1678{
1679 struct i40e_aq_desc desc;
1680 struct i40e_aqc_lldp_stop *cmd =
1681 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
1682 i40e_status status;
1683
1684 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
1685
1686 if (shutdown_agent)
1687 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
1688
1689 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1690
1691 return status;
1692}
1693
1694/**
1695 * i40e_aq_start_lldp
1696 * @hw: pointer to the hw struct
1697 * @cmd_details: pointer to command details structure or NULL
1698 *
1699 * Start the embedded LLDP Agent on all ports.
1700 **/
1701i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
1702 struct i40e_asq_cmd_details *cmd_details)
1703{
1704 struct i40e_aq_desc desc;
1705 struct i40e_aqc_lldp_start *cmd =
1706 (struct i40e_aqc_lldp_start *)&desc.params.raw;
1707 i40e_status status;
1708
1709 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
1710
1711 cmd->command = I40E_AQ_LLDP_AGENT_START;
1712
1713 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1714
1715 return status;
1716}
1717
a1c9a9d9
JK		 1718/**
1719 * i40e_aq_add_udp_tunnel
1720 * @hw: pointer to the hw struct
1721 * @udp_port: the UDP port to add
1722 * @header_len: length of the tunneling header length in DWords
1723 * @protocol_index: protocol index type
1724 * @cmd_details: pointer to command details structure or NULL
1725 **/
1726i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
1727 u16 udp_port, u8 header_len,
1728 u8 protocol_index, u8 *filter_index,
1729 struct i40e_asq_cmd_details *cmd_details)
1730{
1731 struct i40e_aq_desc desc;
1732 struct i40e_aqc_add_udp_tunnel *cmd =
1733 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
1734 struct i40e_aqc_del_udp_tunnel_completion *resp =
1735 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
1736 i40e_status status;
1737
1738 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
1739
1740 cmd->udp_port = cpu_to_le16(udp_port);
1741 cmd->header_len = header_len;
981b7545 1742 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 1743
1744 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1745
1746 if (!status)
1747 *filter_index = resp->index;
1748
1749 return status;
1750}
1751
1752/**
1753 * i40e_aq_del_udp_tunnel
1754 * @hw: pointer to the hw struct
1755 * @index: filter index
1756 * @cmd_details: pointer to command details structure or NULL
1757 **/
1758i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
1759 struct i40e_asq_cmd_details *cmd_details)
1760{
1761 struct i40e_aq_desc desc;
1762 struct i40e_aqc_remove_udp_tunnel *cmd =
1763 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
1764 i40e_status status;
1765
1766 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
1767
1768 cmd->index = index;
1769
1770 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1771
1772 return status;
1773}
1774
56a62fc8
JB		 1775/**
1776 * i40e_aq_delete_element - Delete switch element
1777 * @hw: pointer to the hw struct
1778 * @seid: the SEID to delete from the switch
1779 * @cmd_details: pointer to command details structure or NULL
1780 *
1781 * This deletes a switch element from the switch.
1782 **/
1783i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
1784 struct i40e_asq_cmd_details *cmd_details)
1785{
1786 struct i40e_aq_desc desc;
1787 struct i40e_aqc_switch_seid *cmd =
1788 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1789 i40e_status status;
1790
1791 if (seid == 0)
1792 return I40E_ERR_PARAM;
1793
1794 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
1795
1796 cmd->seid = cpu_to_le16(seid);
1797
1798 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1799
1800 return status;
1801}
1802
1803/**
1804 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
1805 * @hw: pointer to the hw struct
1806 * @seid: seid for the physical port/switching component/vsi
1807 * @buff: Indirect buffer to hold data parameters and response
1808 * @buff_size: Indirect buffer size
1809 * @opcode: Tx scheduler AQ command opcode
1810 * @cmd_details: pointer to command details structure or NULL
1811 *
1812 * Generic command handler for Tx scheduler AQ commands
1813 **/
1814static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
1815 void *buff, u16 buff_size,
1816 enum i40e_admin_queue_opc opcode,
1817 struct i40e_asq_cmd_details *cmd_details)
1818{
1819 struct i40e_aq_desc desc;
1820 struct i40e_aqc_tx_sched_ind *cmd =
1821 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
1822 i40e_status status;
1823 bool cmd_param_flag = false;
1824
1825 switch (opcode) {
1826 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
1827 case i40e_aqc_opc_configure_vsi_tc_bw:
1828 case i40e_aqc_opc_enable_switching_comp_ets:
1829 case i40e_aqc_opc_modify_switching_comp_ets:
1830 case i40e_aqc_opc_disable_switching_comp_ets:
1831 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
1832 case i40e_aqc_opc_configure_switching_comp_bw_config:
1833 cmd_param_flag = true;
1834 break;
1835 case i40e_aqc_opc_query_vsi_bw_config:
1836 case i40e_aqc_opc_query_vsi_ets_sla_config:
1837 case i40e_aqc_opc_query_switching_comp_ets_config:
1838 case i40e_aqc_opc_query_port_ets_config:
1839 case i40e_aqc_opc_query_switching_comp_bw_config:
1840 cmd_param_flag = false;
1841 break;
1842 default:
1843 return I40E_ERR_PARAM;
1844 }
1845
1846 i40e_fill_default_direct_cmd_desc(&desc, opcode);
1847
1848 /* Indirect command */
1849 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1850 if (cmd_param_flag)
1851 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
1852 if (buff_size > I40E_AQ_LARGE_BUF)
1853 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1854
1855 desc.datalen = cpu_to_le16(buff_size);
1856
1857 cmd->vsi_seid = cpu_to_le16(seid);
1858
1859 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1860
1861 return status;
1862}
1863
1864/**
1865 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
1866 * @hw: pointer to the hw struct
1867 * @seid: VSI seid
1868 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
1869 * @cmd_details: pointer to command details structure or NULL
1870 **/
1871i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
1872 u16 seid,
1873 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
1874 struct i40e_asq_cmd_details *cmd_details)
1875{
1876 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1877 i40e_aqc_opc_configure_vsi_tc_bw,
1878 cmd_details);
1879}
1880
1881/**
1882 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
1883 * @hw: pointer to the hw struct
1884 * @seid: seid of the VSI
1885 * @bw_data: Buffer to hold VSI BW configuration
1886 * @cmd_details: pointer to command details structure or NULL
1887 **/
1888i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
1889 u16 seid,
1890 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
1891 struct i40e_asq_cmd_details *cmd_details)
1892{
1893 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1894 i40e_aqc_opc_query_vsi_bw_config,
1895 cmd_details);
1896}
1897
1898/**
1899 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
1900 * @hw: pointer to the hw struct
1901 * @seid: seid of the VSI
1902 * @bw_data: Buffer to hold VSI BW configuration per TC
1903 * @cmd_details: pointer to command details structure or NULL
1904 **/
1905i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
1906 u16 seid,
1907 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
1908 struct i40e_asq_cmd_details *cmd_details)
1909{
1910 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1911 i40e_aqc_opc_query_vsi_ets_sla_config,
1912 cmd_details);
1913}
1914
1915/**
1916 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
1917 * @hw: pointer to the hw struct
1918 * @seid: seid of the switching component
1919 * @bw_data: Buffer to hold switching component's per TC BW config
1920 * @cmd_details: pointer to command details structure or NULL
1921 **/
1922i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
1923 u16 seid,
1924 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
1925 struct i40e_asq_cmd_details *cmd_details)
1926{
1927 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1928 i40e_aqc_opc_query_switching_comp_ets_config,
1929 cmd_details);
1930}
1931
1932/**
1933 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
1934 * @hw: pointer to the hw struct
1935 * @seid: seid of the VSI or switching component connected to Physical Port
1936 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
1937 * @cmd_details: pointer to command details structure or NULL
1938 **/
1939i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
1940 u16 seid,
1941 struct i40e_aqc_query_port_ets_config_resp *bw_data,
1942 struct i40e_asq_cmd_details *cmd_details)
1943{
1944 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1945 i40e_aqc_opc_query_port_ets_config,
1946 cmd_details);
1947}
1948
1949/**
1950 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
1951 * @hw: pointer to the hw struct
1952 * @seid: seid of the switching component
1953 * @bw_data: Buffer to hold switching component's BW configuration
1954 * @cmd_details: pointer to command details structure or NULL
1955 **/
1956i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
1957 u16 seid,
1958 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
1959 struct i40e_asq_cmd_details *cmd_details)
1960{
1961 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1962 i40e_aqc_opc_query_switching_comp_bw_config,
1963 cmd_details);
1964}
1965
1966/**
1967 * i40e_validate_filter_settings
1968 * @hw: pointer to the hardware structure
1969 * @settings: Filter control settings
1970 *
1971 * Check and validate the filter control settings passed.
1972 * The function checks for the valid filter/context sizes being
1973 * passed for FCoE and PE.
1974 *
1975 * Returns 0 if the values passed are valid and within
1976 * range else returns an error.
1977 **/
1978static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
1979 struct i40e_filter_control_settings *settings)
1980{
1981 u32 fcoe_cntx_size, fcoe_filt_size;
1982 u32 pe_cntx_size, pe_filt_size;
1983 u32 fcoe_fmax, pe_fmax;
1984 u32 val;
1985
1986 /* Validate FCoE settings passed */
1987 switch (settings->fcoe_filt_num) {
1988 case I40E_HASH_FILTER_SIZE_1K:
1989 case I40E_HASH_FILTER_SIZE_2K:
1990 case I40E_HASH_FILTER_SIZE_4K:
1991 case I40E_HASH_FILTER_SIZE_8K:
1992 case I40E_HASH_FILTER_SIZE_16K:
1993 case I40E_HASH_FILTER_SIZE_32K:
1994 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
1995 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
1996 break;
1997 default:
1998 return I40E_ERR_PARAM;
1999 }
2000
2001 switch (settings->fcoe_cntx_num) {
2002 case I40E_DMA_CNTX_SIZE_512:
2003 case I40E_DMA_CNTX_SIZE_1K:
2004 case I40E_DMA_CNTX_SIZE_2K:
2005 case I40E_DMA_CNTX_SIZE_4K:
2006 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2007 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2008 break;
2009 default:
2010 return I40E_ERR_PARAM;
2011 }
2012
2013 /* Validate PE settings passed */
2014 switch (settings->pe_filt_num) {
2015 case I40E_HASH_FILTER_SIZE_1K:
2016 case I40E_HASH_FILTER_SIZE_2K:
2017 case I40E_HASH_FILTER_SIZE_4K:
2018 case I40E_HASH_FILTER_SIZE_8K:
2019 case I40E_HASH_FILTER_SIZE_16K:
2020 case I40E_HASH_FILTER_SIZE_32K:
2021 case I40E_HASH_FILTER_SIZE_64K:
2022 case I40E_HASH_FILTER_SIZE_128K:
2023 case I40E_HASH_FILTER_SIZE_256K:
2024 case I40E_HASH_FILTER_SIZE_512K:
2025 case I40E_HASH_FILTER_SIZE_1M:
2026 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2027 pe_filt_size <<= (u32)settings->pe_filt_num;
2028 break;
2029 default:
2030 return I40E_ERR_PARAM;
2031 }
2032
2033 switch (settings->pe_cntx_num) {
2034 case I40E_DMA_CNTX_SIZE_512:
2035 case I40E_DMA_CNTX_SIZE_1K:
2036 case I40E_DMA_CNTX_SIZE_2K:
2037 case I40E_DMA_CNTX_SIZE_4K:
2038 case I40E_DMA_CNTX_SIZE_8K:
2039 case I40E_DMA_CNTX_SIZE_16K:
2040 case I40E_DMA_CNTX_SIZE_32K:
2041 case I40E_DMA_CNTX_SIZE_64K:
2042 case I40E_DMA_CNTX_SIZE_128K:
2043 case I40E_DMA_CNTX_SIZE_256K:
2044 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2045 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2046 break;
2047 default:
2048 return I40E_ERR_PARAM;
2049 }
2050
2051 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2052 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2053 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2054 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2055 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2056 return I40E_ERR_INVALID_SIZE;
2057
2058 /* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
2059 val = rd32(hw, I40E_GLHMC_PEXFMAX);
2060 pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
2061 >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
2062 if (pe_filt_size + pe_cntx_size > pe_fmax)
2063 return I40E_ERR_INVALID_SIZE;
2064
2065 return 0;
2066}
2067
2068/**
2069 * i40e_set_filter_control
2070 * @hw: pointer to the hardware structure
2071 * @settings: Filter control settings
2072 *
2073 * Set the Queue Filters for PE/FCoE and enable filters required
2074 * for a single PF. It is expected that these settings are programmed
2075 * at the driver initialization time.
2076 **/
2077i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2078 struct i40e_filter_control_settings *settings)
2079{
2080 i40e_status ret = 0;
2081 u32 hash_lut_size = 0;
2082 u32 val;
2083
2084 if (!settings)
2085 return I40E_ERR_PARAM;
2086
2087 /* Validate the input settings */
2088 ret = i40e_validate_filter_settings(hw, settings);
2089 if (ret)
2090 return ret;
2091
2092 /* Read the PF Queue Filter control register */
2093 val = rd32(hw, I40E_PFQF_CTL_0);
2094
2095 /* Program required PE hash buckets for the PF */
2096 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2097 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2098 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2099 /* Program required PE contexts for the PF */
2100 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2101 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2102 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2103
2104 /* Program required FCoE hash buckets for the PF */
2105 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2106 val |= ((u32)settings->fcoe_filt_num <<
2107 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2108 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2109 /* Program required FCoE DDP contexts for the PF */
2110 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2111 val |= ((u32)settings->fcoe_cntx_num <<
2112 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2113 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2114
2115 /* Program Hash LUT size for the PF */
2116 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2117 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2118 hash_lut_size = 1;
2119 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2120 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2121
2122 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2123 if (settings->enable_fdir)
2124 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2125 if (settings->enable_ethtype)
2126 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2127 if (settings->enable_macvlan)
2128 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2129
2130 wr32(hw, I40E_PFQF_CTL_0, val);
2131
2132 return 0;
2133}
d4dfb81a
CS		 2134/**
2135 * i40e_set_pci_config_data - store PCI bus info
2136 * @hw: pointer to hardware structure
2137 * @link_status: the link status word from PCI config space
2138 *
2139 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2140 **/
2141void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2142{
2143 hw->bus.type = i40e_bus_type_pci_express;
2144
2145 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2146 case PCI_EXP_LNKSTA_NLW_X1:
2147 hw->bus.width = i40e_bus_width_pcie_x1;
2148 break;
2149 case PCI_EXP_LNKSTA_NLW_X2:
2150 hw->bus.width = i40e_bus_width_pcie_x2;
2151 break;
2152 case PCI_EXP_LNKSTA_NLW_X4:
2153 hw->bus.width = i40e_bus_width_pcie_x4;
2154 break;
2155 case PCI_EXP_LNKSTA_NLW_X8:
2156 hw->bus.width = i40e_bus_width_pcie_x8;
2157 break;
2158 default:
2159 hw->bus.width = i40e_bus_width_unknown;
2160 break;
2161 }
2162
2163 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2164 case PCI_EXP_LNKSTA_CLS_2_5GB:
2165 hw->bus.speed = i40e_bus_speed_2500;
2166 break;
2167 case PCI_EXP_LNKSTA_CLS_5_0GB:
2168 hw->bus.speed = i40e_bus_speed_5000;
2169 break;
2170 case PCI_EXP_LNKSTA_CLS_8_0GB:
2171 hw->bus.speed = i40e_bus_speed_8000;
2172 break;
2173 default:
2174 hw->bus.speed = i40e_bus_speed_unknown;
2175 break;
2176 }
2177}
Linux kernel - Deliverables
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