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i40e/i40evf: Add set_fc and init of FC settings
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e
SN		 46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
ab60085e
SN		 50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
56a62fc8
JB		 53 hw->mac.type = I40E_MAC_XL710;
54 break;
ab60085e
SN		 55 case I40E_DEV_ID_VF:
56 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 57 hw->mac.type = I40E_MAC_VF;
58 break;
59 default:
60 hw->mac.type = I40E_MAC_GENERIC;
61 break;
62 }
63 } else {
64 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
65 }
66
67 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
68 hw->mac.type, status);
69 return status;
70}
71
72/**
73 * i40e_debug_aq
74 * @hw: debug mask related to admin queue
98d44381
JK		 75 * @mask: debug mask
76 * @desc: pointer to admin queue descriptor
56a62fc8
JB		 77 * @buffer: pointer to command buffer
78 *
79 * Dumps debug log about adminq command with descriptor contents.
80 **/
81void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
82 void *buffer)
83{
84 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
85 u8 *aq_buffer = (u8 *)buffer;
86 u32 data[4];
87 u32 i = 0;
88
89 if ((!(mask & hw->debug_mask)) || (desc == NULL))
90 return;
91
92 i40e_debug(hw, mask,
93 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
94 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
95 aq_desc->retval);
96 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
97 aq_desc->cookie_high, aq_desc->cookie_low);
98 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
99 aq_desc->params.internal.param0,
100 aq_desc->params.internal.param1);
101 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
102 aq_desc->params.external.addr_high,
103 aq_desc->params.external.addr_low);
104
105 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
106 memset(data, 0, sizeof(data));
107 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
108 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
109 data[((i % 16) / 4)] |=
110 ((u32)aq_buffer[i]) << (8 * (i % 4));
111 if ((i % 16) == 15) {
112 i40e_debug(hw, mask,
113 "\t0x%04X %08X %08X %08X %08X\n",
114 i - 15, data[0], data[1], data[2],
115 data[3]);
116 memset(data, 0, sizeof(data));
117 }
118 }
119 if ((i % 16) != 0)
120 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
121 i - (i % 16), data[0], data[1], data[2],
122 data[3]);
123 }
124}
125
e1860d8f
ASJ		 126/**
127 * i40e_check_asq_alive
128 * @hw: pointer to the hw struct
129 *
130 * Returns true if Queue is enabled else false.
131 **/
132bool i40e_check_asq_alive(struct i40e_hw *hw)
133{
8b833b4f
KS		 134 if (hw->aq.asq.len)
135 return !!(rd32(hw, hw->aq.asq.len) &
136 I40E_PF_ATQLEN_ATQENABLE_MASK);
137 else
138 return false;
e1860d8f
ASJ		 139}
140
141/**
142 * i40e_aq_queue_shutdown
143 * @hw: pointer to the hw struct
144 * @unloading: is the driver unloading itself
145 *
146 * Tell the Firmware that we're shutting down the AdminQ and whether
147 * or not the driver is unloading as well.
148 **/
149i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
150 bool unloading)
151{
152 struct i40e_aq_desc desc;
153 struct i40e_aqc_queue_shutdown *cmd =
154 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
155 i40e_status status;
156
157 i40e_fill_default_direct_cmd_desc(&desc,
158 i40e_aqc_opc_queue_shutdown);
159
160 if (unloading)
161 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
162 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
163
164 return status;
165}
166
206812b5
JB		 167/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
168 * hardware to a bit-field that can be used by SW to more easily determine the
169 * packet type.
170 *
171 * Macros are used to shorten the table lines and make this table human
172 * readable.
173 *
174 * We store the PTYPE in the top byte of the bit field - this is just so that
175 * we can check that the table doesn't have a row missing, as the index into
176 * the table should be the PTYPE.
177 *
178 * Typical work flow:
179 *
180 * IF NOT i40e_ptype_lookup[ptype].known
181 * THEN
182 * Packet is unknown
183 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
184 * Use the rest of the fields to look at the tunnels, inner protocols, etc
185 * ELSE
186 * Use the enum i40e_rx_l2_ptype to decode the packet type
187 * ENDIF
188 */
189
190/* macro to make the table lines short */
191#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
192 { PTYPE, \
193 1, \
194 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
195 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
196 I40E_RX_PTYPE_##OUTER_FRAG, \
197 I40E_RX_PTYPE_TUNNEL_##T, \
198 I40E_RX_PTYPE_TUNNEL_END_##TE, \
199 I40E_RX_PTYPE_##TEF, \
200 I40E_RX_PTYPE_INNER_PROT_##I, \
201 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
202
203#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
204 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
205
206/* shorter macros makes the table fit but are terse */
207#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
208#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
209#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
210
211/* Lookup table mapping the HW PTYPE to the bit field for decoding */
212struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
213 /* L2 Packet types */
214 I40E_PTT_UNUSED_ENTRY(0),
215 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
216 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
217 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
218 I40E_PTT_UNUSED_ENTRY(4),
219 I40E_PTT_UNUSED_ENTRY(5),
220 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
222 I40E_PTT_UNUSED_ENTRY(8),
223 I40E_PTT_UNUSED_ENTRY(9),
224 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
225 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
226 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
227 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
228 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
229 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
230 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236
237 /* Non Tunneled IPv4 */
238 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
241 I40E_PTT_UNUSED_ENTRY(25),
242 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
243 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
244 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
245
246 /* IPv4 --> IPv4 */
247 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
248 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
249 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
250 I40E_PTT_UNUSED_ENTRY(32),
251 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
252 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
253 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
254
255 /* IPv4 --> IPv6 */
256 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
257 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
258 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
259 I40E_PTT_UNUSED_ENTRY(39),
260 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
261 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
262 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
263
264 /* IPv4 --> GRE/NAT */
265 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
266
267 /* IPv4 --> GRE/NAT --> IPv4 */
268 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
269 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
270 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
271 I40E_PTT_UNUSED_ENTRY(47),
272 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
273 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
274 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
275
276 /* IPv4 --> GRE/NAT --> IPv6 */
277 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
278 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
279 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
280 I40E_PTT_UNUSED_ENTRY(54),
281 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
282 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
283 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
284
285 /* IPv4 --> GRE/NAT --> MAC */
286 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
287
288 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
289 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
290 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
291 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
292 I40E_PTT_UNUSED_ENTRY(62),
293 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
294 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
295 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
296
297 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
298 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
299 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
300 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
301 I40E_PTT_UNUSED_ENTRY(69),
302 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
303 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
304 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
305
306 /* IPv4 --> GRE/NAT --> MAC/VLAN */
307 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
308
309 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
310 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
311 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
312 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
313 I40E_PTT_UNUSED_ENTRY(77),
314 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
315 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
316 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
317
318 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
319 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
320 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
321 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
322 I40E_PTT_UNUSED_ENTRY(84),
323 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
324 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
325 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
326
327 /* Non Tunneled IPv6 */
328 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
329 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
330 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
331 I40E_PTT_UNUSED_ENTRY(91),
332 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
333 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
334 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
335
336 /* IPv6 --> IPv4 */
337 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
338 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
339 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
340 I40E_PTT_UNUSED_ENTRY(98),
341 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
342 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
343 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
344
345 /* IPv6 --> IPv6 */
346 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
347 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
348 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
349 I40E_PTT_UNUSED_ENTRY(105),
350 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
351 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
352 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
353
354 /* IPv6 --> GRE/NAT */
355 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
356
357 /* IPv6 --> GRE/NAT -> IPv4 */
358 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
359 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
360 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
361 I40E_PTT_UNUSED_ENTRY(113),
362 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
363 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
364 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
365
366 /* IPv6 --> GRE/NAT -> IPv6 */
367 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
368 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
369 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
370 I40E_PTT_UNUSED_ENTRY(120),
371 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
372 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
373 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
374
375 /* IPv6 --> GRE/NAT -> MAC */
376 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
377
378 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
379 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
380 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
381 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
382 I40E_PTT_UNUSED_ENTRY(128),
383 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
384 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
385 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
386
387 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
388 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
389 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
390 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
391 I40E_PTT_UNUSED_ENTRY(135),
392 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
393 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
394 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
395
396 /* IPv6 --> GRE/NAT -> MAC/VLAN */
397 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
398
399 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
400 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
401 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
402 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
403 I40E_PTT_UNUSED_ENTRY(143),
404 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
405 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
406 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
407
408 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
409 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
410 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
411 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
412 I40E_PTT_UNUSED_ENTRY(150),
413 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
414 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
415 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
416
417 /* unused entries */
418 I40E_PTT_UNUSED_ENTRY(154),
419 I40E_PTT_UNUSED_ENTRY(155),
420 I40E_PTT_UNUSED_ENTRY(156),
421 I40E_PTT_UNUSED_ENTRY(157),
422 I40E_PTT_UNUSED_ENTRY(158),
423 I40E_PTT_UNUSED_ENTRY(159),
424
425 I40E_PTT_UNUSED_ENTRY(160),
426 I40E_PTT_UNUSED_ENTRY(161),
427 I40E_PTT_UNUSED_ENTRY(162),
428 I40E_PTT_UNUSED_ENTRY(163),
429 I40E_PTT_UNUSED_ENTRY(164),
430 I40E_PTT_UNUSED_ENTRY(165),
431 I40E_PTT_UNUSED_ENTRY(166),
432 I40E_PTT_UNUSED_ENTRY(167),
433 I40E_PTT_UNUSED_ENTRY(168),
434 I40E_PTT_UNUSED_ENTRY(169),
435
436 I40E_PTT_UNUSED_ENTRY(170),
437 I40E_PTT_UNUSED_ENTRY(171),
438 I40E_PTT_UNUSED_ENTRY(172),
439 I40E_PTT_UNUSED_ENTRY(173),
440 I40E_PTT_UNUSED_ENTRY(174),
441 I40E_PTT_UNUSED_ENTRY(175),
442 I40E_PTT_UNUSED_ENTRY(176),
443 I40E_PTT_UNUSED_ENTRY(177),
444 I40E_PTT_UNUSED_ENTRY(178),
445 I40E_PTT_UNUSED_ENTRY(179),
446
447 I40E_PTT_UNUSED_ENTRY(180),
448 I40E_PTT_UNUSED_ENTRY(181),
449 I40E_PTT_UNUSED_ENTRY(182),
450 I40E_PTT_UNUSED_ENTRY(183),
451 I40E_PTT_UNUSED_ENTRY(184),
452 I40E_PTT_UNUSED_ENTRY(185),
453 I40E_PTT_UNUSED_ENTRY(186),
454 I40E_PTT_UNUSED_ENTRY(187),
455 I40E_PTT_UNUSED_ENTRY(188),
456 I40E_PTT_UNUSED_ENTRY(189),
457
458 I40E_PTT_UNUSED_ENTRY(190),
459 I40E_PTT_UNUSED_ENTRY(191),
460 I40E_PTT_UNUSED_ENTRY(192),
461 I40E_PTT_UNUSED_ENTRY(193),
462 I40E_PTT_UNUSED_ENTRY(194),
463 I40E_PTT_UNUSED_ENTRY(195),
464 I40E_PTT_UNUSED_ENTRY(196),
465 I40E_PTT_UNUSED_ENTRY(197),
466 I40E_PTT_UNUSED_ENTRY(198),
467 I40E_PTT_UNUSED_ENTRY(199),
468
469 I40E_PTT_UNUSED_ENTRY(200),
470 I40E_PTT_UNUSED_ENTRY(201),
471 I40E_PTT_UNUSED_ENTRY(202),
472 I40E_PTT_UNUSED_ENTRY(203),
473 I40E_PTT_UNUSED_ENTRY(204),
474 I40E_PTT_UNUSED_ENTRY(205),
475 I40E_PTT_UNUSED_ENTRY(206),
476 I40E_PTT_UNUSED_ENTRY(207),
477 I40E_PTT_UNUSED_ENTRY(208),
478 I40E_PTT_UNUSED_ENTRY(209),
479
480 I40E_PTT_UNUSED_ENTRY(210),
481 I40E_PTT_UNUSED_ENTRY(211),
482 I40E_PTT_UNUSED_ENTRY(212),
483 I40E_PTT_UNUSED_ENTRY(213),
484 I40E_PTT_UNUSED_ENTRY(214),
485 I40E_PTT_UNUSED_ENTRY(215),
486 I40E_PTT_UNUSED_ENTRY(216),
487 I40E_PTT_UNUSED_ENTRY(217),
488 I40E_PTT_UNUSED_ENTRY(218),
489 I40E_PTT_UNUSED_ENTRY(219),
490
491 I40E_PTT_UNUSED_ENTRY(220),
492 I40E_PTT_UNUSED_ENTRY(221),
493 I40E_PTT_UNUSED_ENTRY(222),
494 I40E_PTT_UNUSED_ENTRY(223),
495 I40E_PTT_UNUSED_ENTRY(224),
496 I40E_PTT_UNUSED_ENTRY(225),
497 I40E_PTT_UNUSED_ENTRY(226),
498 I40E_PTT_UNUSED_ENTRY(227),
499 I40E_PTT_UNUSED_ENTRY(228),
500 I40E_PTT_UNUSED_ENTRY(229),
501
502 I40E_PTT_UNUSED_ENTRY(230),
503 I40E_PTT_UNUSED_ENTRY(231),
504 I40E_PTT_UNUSED_ENTRY(232),
505 I40E_PTT_UNUSED_ENTRY(233),
506 I40E_PTT_UNUSED_ENTRY(234),
507 I40E_PTT_UNUSED_ENTRY(235),
508 I40E_PTT_UNUSED_ENTRY(236),
509 I40E_PTT_UNUSED_ENTRY(237),
510 I40E_PTT_UNUSED_ENTRY(238),
511 I40E_PTT_UNUSED_ENTRY(239),
512
513 I40E_PTT_UNUSED_ENTRY(240),
514 I40E_PTT_UNUSED_ENTRY(241),
515 I40E_PTT_UNUSED_ENTRY(242),
516 I40E_PTT_UNUSED_ENTRY(243),
517 I40E_PTT_UNUSED_ENTRY(244),
518 I40E_PTT_UNUSED_ENTRY(245),
519 I40E_PTT_UNUSED_ENTRY(246),
520 I40E_PTT_UNUSED_ENTRY(247),
521 I40E_PTT_UNUSED_ENTRY(248),
522 I40E_PTT_UNUSED_ENTRY(249),
523
524 I40E_PTT_UNUSED_ENTRY(250),
525 I40E_PTT_UNUSED_ENTRY(251),
526 I40E_PTT_UNUSED_ENTRY(252),
527 I40E_PTT_UNUSED_ENTRY(253),
528 I40E_PTT_UNUSED_ENTRY(254),
529 I40E_PTT_UNUSED_ENTRY(255)
530};
531
532
56a62fc8
JB		 533/**
534 * i40e_init_shared_code - Initialize the shared code
535 * @hw: pointer to hardware structure
536 *
537 * This assigns the MAC type and PHY code and inits the NVM.
538 * Does not touch the hardware. This function must be called prior to any
539 * other function in the shared code. The i40e_hw structure should be
540 * memset to 0 prior to calling this function. The following fields in
541 * hw structure should be filled in prior to calling this function:
542 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
543 * subsystem_vendor_id, and revision_id
544 **/
545i40e_status i40e_init_shared_code(struct i40e_hw *hw)
546{
547 i40e_status status = 0;
548 u32 reg;
549
56a62fc8
JB		 550 i40e_set_mac_type(hw);
551
552 switch (hw->mac.type) {
553 case I40E_MAC_XL710:
554 break;
555 default:
556 return I40E_ERR_DEVICE_NOT_SUPPORTED;
557 break;
558 }
559
af89d26c
SN		 560 hw->phy.get_link_info = true;
561
562 /* Determine port number */
563 reg = rd32(hw, I40E_PFGEN_PORTNUM);
564 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
565 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
566 hw->port = (u8)reg;
567
5f9116ac
SN		 568 /* Determine the PF number based on the PCI fn */
569 reg = rd32(hw, I40E_GLPCI_CAPSUP);
570 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
571 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
572 else
573 hw->pf_id = (u8)hw->bus.func;
574
56a62fc8
JB		 575 status = i40e_init_nvm(hw);
576 return status;
577}
578
579/**
580 * i40e_aq_mac_address_read - Retrieve the MAC addresses
581 * @hw: pointer to the hw struct
582 * @flags: a return indicator of what addresses were added to the addr store
583 * @addrs: the requestor's mac addr store
584 * @cmd_details: pointer to command details structure or NULL
585 **/
586static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
587 u16 *flags,
588 struct i40e_aqc_mac_address_read_data *addrs,
589 struct i40e_asq_cmd_details *cmd_details)
590{
591 struct i40e_aq_desc desc;
592 struct i40e_aqc_mac_address_read *cmd_data =
593 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
594 i40e_status status;
595
596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
597 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
598
599 status = i40e_asq_send_command(hw, &desc, addrs,
600 sizeof(*addrs), cmd_details);
601 *flags = le16_to_cpu(cmd_data->command_flags);
602
603 return status;
604}
605
606/**
607 * i40e_aq_mac_address_write - Change the MAC addresses
608 * @hw: pointer to the hw struct
609 * @flags: indicates which MAC to be written
610 * @mac_addr: address to write
611 * @cmd_details: pointer to command details structure or NULL
612 **/
613i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
614 u16 flags, u8 *mac_addr,
615 struct i40e_asq_cmd_details *cmd_details)
616{
617 struct i40e_aq_desc desc;
618 struct i40e_aqc_mac_address_write *cmd_data =
619 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
620 i40e_status status;
621
622 i40e_fill_default_direct_cmd_desc(&desc,
623 i40e_aqc_opc_mac_address_write);
624 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 625 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
626 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
627 ((u32)mac_addr[3] << 16) |
628 ((u32)mac_addr[4] << 8) |
629 mac_addr[5]);
56a62fc8
JB		 630
631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
632
633 return status;
634}
635
636/**
637 * i40e_get_mac_addr - get MAC address
638 * @hw: pointer to the HW structure
639 * @mac_addr: pointer to MAC address
640 *
641 * Reads the adapter's MAC address from register
642 **/
643i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
644{
645 struct i40e_aqc_mac_address_read_data addrs;
646 i40e_status status;
647 u16 flags = 0;
648
649 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
650
651 if (flags & I40E_AQC_LAN_ADDR_VALID)
652 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
653
654 return status;
655}
656
351499ab
MJ		 657/**
658 * i40e_pre_tx_queue_cfg - pre tx queue configure
659 * @hw: pointer to the HW structure
660 * @queue: target pf queue index
661 * @enable: state change request
662 *
663 * Handles hw requirement to indicate intention to enable
664 * or disable target queue.
665 **/
666void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
667{
dfb699f9 668 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 669 u32 reg_block = 0;
dfb699f9 670 u32 reg_val;
351499ab 671
24a768cf 672 if (abs_queue_idx >= 128) {
351499ab 673 reg_block = abs_queue_idx / 128;
24a768cf
CP		 674 abs_queue_idx %= 128;
675 }
351499ab
MJ		 676
677 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
678 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
679 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
680
681 if (enable)
682 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
683 else
684 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
685
686 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
687}
688
be405eb0
JB		 689/**
690 * i40e_get_media_type - Gets media type
691 * @hw: pointer to the hardware structure
692 **/
693static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
694{
695 enum i40e_media_type media;
696
697 switch (hw->phy.link_info.phy_type) {
698 case I40E_PHY_TYPE_10GBASE_SR:
699 case I40E_PHY_TYPE_10GBASE_LR:
700 case I40E_PHY_TYPE_40GBASE_SR4:
701 case I40E_PHY_TYPE_40GBASE_LR4:
702 media = I40E_MEDIA_TYPE_FIBER;
703 break;
704 case I40E_PHY_TYPE_100BASE_TX:
705 case I40E_PHY_TYPE_1000BASE_T:
706 case I40E_PHY_TYPE_10GBASE_T:
707 media = I40E_MEDIA_TYPE_BASET;
708 break;
709 case I40E_PHY_TYPE_10GBASE_CR1_CU:
710 case I40E_PHY_TYPE_40GBASE_CR4_CU:
711 case I40E_PHY_TYPE_10GBASE_CR1:
712 case I40E_PHY_TYPE_40GBASE_CR4:
713 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
714 media = I40E_MEDIA_TYPE_DA;
715 break;
716 case I40E_PHY_TYPE_1000BASE_KX:
717 case I40E_PHY_TYPE_10GBASE_KX4:
718 case I40E_PHY_TYPE_10GBASE_KR:
719 case I40E_PHY_TYPE_40GBASE_KR4:
720 media = I40E_MEDIA_TYPE_BACKPLANE;
721 break;
722 case I40E_PHY_TYPE_SGMII:
723 case I40E_PHY_TYPE_XAUI:
724 case I40E_PHY_TYPE_XFI:
725 case I40E_PHY_TYPE_XLAUI:
726 case I40E_PHY_TYPE_XLPPI:
727 default:
728 media = I40E_MEDIA_TYPE_UNKNOWN;
729 break;
730 }
731
732 return media;
733}
734
7134f9ce 735#define I40E_PF_RESET_WAIT_COUNT_A0 200
d0ff5687 736#define I40E_PF_RESET_WAIT_COUNT 100
56a62fc8
JB		 737/**
738 * i40e_pf_reset - Reset the PF
739 * @hw: pointer to the hardware structure
740 *
741 * Assuming someone else has triggered a global reset,
742 * assure the global reset is complete and then reset the PF
743 **/
744i40e_status i40e_pf_reset(struct i40e_hw *hw)
745{
7134f9ce 746 u32 cnt = 0;
42794bd8 747 u32 cnt1 = 0;
56a62fc8
JB		 748 u32 reg = 0;
749 u32 grst_del;
750
751 /* Poll for Global Reset steady state in case of recent GRST.
752 * The grst delay value is in 100ms units, and we'll wait a
753 * couple counts longer to be sure we don't just miss the end.
754 */
755 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
756 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 757 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 758 reg = rd32(hw, I40E_GLGEN_RSTAT);
759 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
760 break;
761 msleep(100);
762 }
763 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
764 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 765 return I40E_ERR_RESET_FAILED;
766 }
767
768 /* Now Wait for the FW to be ready */
769 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
770 reg = rd32(hw, I40E_GLNVM_ULD);
771 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
772 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
773 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
774 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
775 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
776 break;
777 }
778 usleep_range(10000, 20000);
779 }
780 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
781 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
782 hw_dbg(hw, "wait for FW Reset complete timedout\n");
783 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 784 return I40E_ERR_RESET_FAILED;
785 }
786
56a62fc8
JB		 787 /* If there was a Global Reset in progress when we got here,
788 * we don't need to do the PF Reset
789 */
7134f9ce
JB		 790 if (!cnt) {
791 if (hw->revision_id == 0)
792 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
793 else
794 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 795 reg = rd32(hw, I40E_PFGEN_CTRL);
796 wr32(hw, I40E_PFGEN_CTRL,
797 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 798 for (; cnt; cnt--) {
56a62fc8
JB		 799 reg = rd32(hw, I40E_PFGEN_CTRL);
800 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
801 break;
802 usleep_range(1000, 2000);
803 }
804 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
805 hw_dbg(hw, "PF reset polling failed to complete.\n");
806 return I40E_ERR_RESET_FAILED;
807 }
808 }
809
810 i40e_clear_pxe_mode(hw);
922680b9 811
56a62fc8
JB		 812 return 0;
813}
814
838d41d9
SN		 815/**
816 * i40e_clear_hw - clear out any left over hw state
817 * @hw: pointer to the hw struct
818 *
819 * Clear queues and interrupts, typically called at init time,
820 * but after the capabilities have been found so we know how many
821 * queues and msix vectors have been allocated.
822 **/
823void i40e_clear_hw(struct i40e_hw *hw)
824{
825 u32 num_queues, base_queue;
826 u32 num_pf_int;
827 u32 num_vf_int;
828 u32 num_vfs;
829 u32 i, j;
830 u32 val;
831 u32 eol = 0x7ff;
832
833 /* get number of interrupts, queues, and vfs */
834 val = rd32(hw, I40E_GLPCI_CNF2);
835 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
836 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
837 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
838 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
839
840 val = rd32(hw, I40E_PFLAN_QALLOC);
841 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
842 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
843 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
844 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
845 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
846 num_queues = (j - base_queue) + 1;
847 else
848 num_queues = 0;
849
850 val = rd32(hw, I40E_PF_VT_PFALLOC);
851 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
852 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
853 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
854 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
855 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
856 num_vfs = (j - i) + 1;
857 else
858 num_vfs = 0;
859
860 /* stop all the interrupts */
861 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
862 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
863 for (i = 0; i < num_pf_int - 2; i++)
864 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
865
866 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
867 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
868 wr32(hw, I40E_PFINT_LNKLST0, val);
869 for (i = 0; i < num_pf_int - 2; i++)
870 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
871 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
872 for (i = 0; i < num_vfs; i++)
873 wr32(hw, I40E_VPINT_LNKLST0(i), val);
874 for (i = 0; i < num_vf_int - 2; i++)
875 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
876
877 /* warn the HW of the coming Tx disables */
878 for (i = 0; i < num_queues; i++) {
879 u32 abs_queue_idx = base_queue + i;
880 u32 reg_block = 0;
881
882 if (abs_queue_idx >= 128) {
883 reg_block = abs_queue_idx / 128;
884 abs_queue_idx %= 128;
885 }
886
887 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
888 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
889 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
890 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
891
892 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
893 }
894 udelay(400);
895
896 /* stop all the queues */
897 for (i = 0; i < num_queues; i++) {
898 wr32(hw, I40E_QINT_TQCTL(i), 0);
899 wr32(hw, I40E_QTX_ENA(i), 0);
900 wr32(hw, I40E_QINT_RQCTL(i), 0);
901 wr32(hw, I40E_QRX_ENA(i), 0);
902 }
903
904 /* short wait for all queue disables to settle */
905 udelay(50);
906}
907
56a62fc8
JB		 908/**
909 * i40e_clear_pxe_mode - clear pxe operations mode
910 * @hw: pointer to the hw struct
911 *
912 * Make sure all PXE mode settings are cleared, including things
913 * like descriptor fetch/write-back mode.
914 **/
915void i40e_clear_pxe_mode(struct i40e_hw *hw)
916{
917 u32 reg;
918
c9b9b0ae
SN		 919 if (i40e_check_asq_alive(hw))
920 i40e_aq_clear_pxe_mode(hw, NULL);
921
56a62fc8
JB		 922 /* Clear single descriptor fetch/write-back mode */
923 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 924
925 if (hw->revision_id == 0) {
926 /* As a work around clear PXE_MODE instead of setting it */
927 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
928 } else {
929 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
930 }
56a62fc8
JB		 931}
932
0556a9e3
JB		 933/**
934 * i40e_led_is_mine - helper to find matching led
935 * @hw: pointer to the hw struct
936 * @idx: index into GPIO registers
937 *
938 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
939 */
940static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
941{
942 u32 gpio_val = 0;
943 u32 port;
944
945 if (!hw->func_caps.led[idx])
946 return 0;
947
948 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
949 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
950 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
951
952 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
953 * if it is not our port then ignore
954 */
955 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
956 (port != hw->port))
957 return 0;
958
959 return gpio_val;
960}
961
962#define I40E_LED0 22
963#define I40E_LINK_ACTIVITY 0xC
964
56a62fc8
JB		 965/**
966 * i40e_led_get - return current on/off mode
967 * @hw: pointer to the hw struct
968 *
969 * The value returned is the 'mode' field as defined in the
970 * GPIO register definitions: 0x0 = off, 0xf = on, and other
971 * values are variations of possible behaviors relating to
972 * blink, link, and wire.
973 **/
974u32 i40e_led_get(struct i40e_hw *hw)
975{
56a62fc8 976 u32 mode = 0;
56a62fc8
JB		 977 int i;
978
0556a9e3
JB		 979 /* as per the documentation GPIO 22-29 are the LED
980 * GPIO pins named LED0..LED7
981 */
982 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
983 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 984
0556a9e3 985 if (!gpio_val)
56a62fc8
JB		 986 continue;
987
0556a9e3
JB		 988 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
989 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 990 break;
991 }
992
993 return mode;
994}
995
996/**
997 * i40e_led_set - set new on/off mode
998 * @hw: pointer to the hw struct
0556a9e3
JB		 999 * @mode: 0=off, 0xf=on (else see manual for mode details)
1000 * @blink: true if the LED should blink when on, false if steady
1001 *
1002 * if this function is used to turn on the blink it should
1003 * be used to disable the blink when restoring the original state.
56a62fc8 1004 **/
0556a9e3 1005void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1006{
56a62fc8
JB		 1007 int i;
1008
0556a9e3
JB		 1009 if (mode & 0xfffffff0)
1010 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1011
0556a9e3
JB		 1012 /* as per the documentation GPIO 22-29 are the LED
1013 * GPIO pins named LED0..LED7
1014 */
1015 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1016 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1017
0556a9e3 1018 if (!gpio_val)
56a62fc8
JB		 1019 continue;
1020
56a62fc8 1021 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1022 /* this & is a bit of paranoia, but serves as a range check */
1023 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1024 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1025
1026 if (mode == I40E_LINK_ACTIVITY)
1027 blink = false;
1028
1029 gpio_val |= (blink ? 1 : 0) <<
1030 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1031
56a62fc8 1032 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1033 break;
56a62fc8
JB		 1034 }
1035}
1036
1037/* Admin command wrappers */
56a62fc8 1038
8109e123
CS		 1039/**
1040 * i40e_aq_get_phy_capabilities
1041 * @hw: pointer to the hw struct
1042 * @abilities: structure for PHY capabilities to be filled
1043 * @qualified_modules: report Qualified Modules
1044 * @report_init: report init capabilities (active are default)
1045 * @cmd_details: pointer to command details structure or NULL
1046 *
1047 * Returns the various PHY abilities supported on the Port.
1048 **/
1049i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1050 bool qualified_modules, bool report_init,
1051 struct i40e_aq_get_phy_abilities_resp *abilities,
1052 struct i40e_asq_cmd_details *cmd_details)
1053{
1054 struct i40e_aq_desc desc;
1055 i40e_status status;
1056 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1057
1058 if (!abilities)
1059 return I40E_ERR_PARAM;
1060
1061 i40e_fill_default_direct_cmd_desc(&desc,
1062 i40e_aqc_opc_get_phy_abilities);
1063
1064 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1065 if (abilities_size > I40E_AQ_LARGE_BUF)
1066 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1067
1068 if (qualified_modules)
1069 desc.params.external.param0 |=
1070 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1071
1072 if (report_init)
1073 desc.params.external.param0 |=
1074 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1075
1076 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1077 cmd_details);
1078
1079 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1080 status = I40E_ERR_UNKNOWN_PHY;
1081
1082 return status;
1083}
1084
c56999f9
CS		 1085/**
1086 * i40e_aq_set_phy_config
1087 * @hw: pointer to the hw struct
1088 * @config: structure with PHY configuration to be set
1089 * @cmd_details: pointer to command details structure or NULL
1090 *
1091 * Set the various PHY configuration parameters
1092 * supported on the Port.One or more of the Set PHY config parameters may be
1093 * ignored in an MFP mode as the PF may not have the privilege to set some
1094 * of the PHY Config parameters. This status will be indicated by the
1095 * command response.
1096 **/
1097enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1098 struct i40e_aq_set_phy_config *config,
1099 struct i40e_asq_cmd_details *cmd_details)
1100{
1101 struct i40e_aq_desc desc;
1102 struct i40e_aq_set_phy_config *cmd =
1103 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1104 enum i40e_status_code status;
1105
1106 if (!config)
1107 return I40E_ERR_PARAM;
1108
1109 i40e_fill_default_direct_cmd_desc(&desc,
1110 i40e_aqc_opc_set_phy_config);
1111
1112 *cmd = *config;
1113
1114 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1115
1116 return status;
1117}
1118
1119/**
1120 * i40e_set_fc
1121 * @hw: pointer to the hw struct
1122 *
1123 * Set the requested flow control mode using set_phy_config.
1124 **/
1125enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1126 bool atomic_restart)
1127{
1128 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1129 struct i40e_aq_get_phy_abilities_resp abilities;
1130 struct i40e_aq_set_phy_config config;
1131 enum i40e_status_code status;
1132 u8 pause_mask = 0x0;
1133
1134 *aq_failures = 0x0;
1135
1136 switch (fc_mode) {
1137 case I40E_FC_FULL:
1138 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1139 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1140 break;
1141 case I40E_FC_RX_PAUSE:
1142 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1143 break;
1144 case I40E_FC_TX_PAUSE:
1145 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1146 break;
1147 default:
1148 break;
1149 }
1150
1151 /* Get the current phy config */
1152 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1153 NULL);
1154 if (status) {
1155 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1156 return status;
1157 }
1158
1159 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1160 /* clear the old pause settings */
1161 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1162 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1163 /* set the new abilities */
1164 config.abilities |= pause_mask;
1165 /* If the abilities have changed, then set the new config */
1166 if (config.abilities != abilities.abilities) {
1167 /* Auto restart link so settings take effect */
1168 if (atomic_restart)
1169 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1170 /* Copy over all the old settings */
1171 config.phy_type = abilities.phy_type;
1172 config.link_speed = abilities.link_speed;
1173 config.eee_capability = abilities.eee_capability;
1174 config.eeer = abilities.eeer_val;
1175 config.low_power_ctrl = abilities.d3_lpan;
1176 status = i40e_aq_set_phy_config(hw, &config, NULL);
1177
1178 if (status)
1179 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1180 }
1181 /* Update the link info */
1182 status = i40e_update_link_info(hw, true);
1183 if (status) {
1184 /* Wait a little bit (on 40G cards it sometimes takes a really
1185 * long time for link to come back from the atomic reset)
1186 * and try once more
1187 */
1188 msleep(1000);
1189 status = i40e_update_link_info(hw, true);
1190 }
1191 if (status)
1192 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1193
1194 return status;
1195}
1196
c9b9b0ae
SN		 1197/**
1198 * i40e_aq_clear_pxe_mode
1199 * @hw: pointer to the hw struct
1200 * @cmd_details: pointer to command details structure or NULL
1201 *
1202 * Tell the firmware that the driver is taking over from PXE
1203 **/
1204i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1205 struct i40e_asq_cmd_details *cmd_details)
1206{
1207 i40e_status status;
1208 struct i40e_aq_desc desc;
1209 struct i40e_aqc_clear_pxe *cmd =
1210 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1211
1212 i40e_fill_default_direct_cmd_desc(&desc,
1213 i40e_aqc_opc_clear_pxe_mode);
1214
1215 cmd->rx_cnt = 0x2;
1216
1217 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1218
1219 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1220
1221 return status;
1222}
1223
56a62fc8
JB		 1224/**
1225 * i40e_aq_set_link_restart_an
1226 * @hw: pointer to the hw struct
1ac978af 1227 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1228 * @cmd_details: pointer to command details structure or NULL
1229 *
1230 * Sets up the link and restarts the Auto-Negotiation over the link.
1231 **/
1232i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1233 bool enable_link,
1234 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1235{
1236 struct i40e_aq_desc desc;
1237 struct i40e_aqc_set_link_restart_an *cmd =
1238 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1239 i40e_status status;
1240
1241 i40e_fill_default_direct_cmd_desc(&desc,
1242 i40e_aqc_opc_set_link_restart_an);
1243
1244 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1245 if (enable_link)
1246 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1247 else
1248 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1249
1250 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1251
1252 return status;
1253}
1254
1255/**
1256 * i40e_aq_get_link_info
1257 * @hw: pointer to the hw struct
1258 * @enable_lse: enable/disable LinkStatusEvent reporting
1259 * @link: pointer to link status structure - optional
1260 * @cmd_details: pointer to command details structure or NULL
1261 *
1262 * Returns the link status of the adapter.
1263 **/
1264i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1265 bool enable_lse, struct i40e_link_status *link,
1266 struct i40e_asq_cmd_details *cmd_details)
1267{
1268 struct i40e_aq_desc desc;
1269 struct i40e_aqc_get_link_status *resp =
1270 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1271 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1272 i40e_status status;
c56999f9 1273 bool tx_pause, rx_pause;
56a62fc8
JB		 1274 u16 command_flags;
1275
1276 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1277
1278 if (enable_lse)
1279 command_flags = I40E_AQ_LSE_ENABLE;
1280 else
1281 command_flags = I40E_AQ_LSE_DISABLE;
1282 resp->command_flags = cpu_to_le16(command_flags);
1283
1284 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1285
1286 if (status)
1287 goto aq_get_link_info_exit;
1288
1289 /* save off old link status information */
c36bd4a7 1290 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1291
1292 /* update link status */
1293 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1294 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1295 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1296 hw_link_info->link_info = resp->link_info;
1297 hw_link_info->an_info = resp->an_info;
1298 hw_link_info->ext_info = resp->ext_info;
639dc377 1299 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1300 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1301 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1302
c56999f9
CS		 1303 /* update fc info */
1304 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1305 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1306 if (tx_pause & rx_pause)
1307 hw->fc.current_mode = I40E_FC_FULL;
1308 else if (tx_pause)
1309 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1310 else if (rx_pause)
1311 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1312 else
1313 hw->fc.current_mode = I40E_FC_NONE;
1314
6bb3f23c
NP		 1315 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1316 hw_link_info->crc_enable = true;
1317 else
1318 hw_link_info->crc_enable = false;
56a62fc8
JB		 1319
1320 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1321 hw_link_info->lse_enable = true;
1322 else
1323 hw_link_info->lse_enable = false;
1324
1325 /* save link status information */
1326 if (link)
d7595a22 1327 *link = *hw_link_info;
56a62fc8
JB		 1328
1329 /* flag cleared so helper functions don't call AQ again */
1330 hw->phy.get_link_info = false;
1331
1332aq_get_link_info_exit:
1333 return status;
1334}
1335
8109e123
CS		 1336/**
1337 * i40e_update_link_info
1338 * @hw: pointer to the hw struct
1339 * @enable_lse: enable/disable LinkStatusEvent reporting
1340 *
1341 * Returns the link status of the adapter
1342 **/
1343i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse)
1344{
1345 struct i40e_aq_get_phy_abilities_resp abilities;
1346 i40e_status status;
1347
1348 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1349 if (status)
1350 return status;
1351
1352 status = i40e_aq_get_phy_capabilities(hw, false, false,
1353 &abilities, NULL);
1354 if (status)
1355 return status;
1356
1357 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1358 hw->phy.link_info.an_enabled = true;
1359 else
1360 hw->phy.link_info.an_enabled = false;
1361
1362 return status;
1363}
1364
56a62fc8
JB		 1365/**
1366 * i40e_aq_add_vsi
1367 * @hw: pointer to the hw struct
98d44381 1368 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1369 * @cmd_details: pointer to command details structure or NULL
1370 *
1371 * Add a VSI context to the hardware.
1372**/
1373i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1374 struct i40e_vsi_context *vsi_ctx,
1375 struct i40e_asq_cmd_details *cmd_details)
1376{
1377 struct i40e_aq_desc desc;
1378 struct i40e_aqc_add_get_update_vsi *cmd =
1379 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1380 struct i40e_aqc_add_get_update_vsi_completion *resp =
1381 (struct i40e_aqc_add_get_update_vsi_completion *)
1382 &desc.params.raw;
1383 i40e_status status;
1384
1385 i40e_fill_default_direct_cmd_desc(&desc,
1386 i40e_aqc_opc_add_vsi);
1387
1388 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1389 cmd->connection_type = vsi_ctx->connection_type;
1390 cmd->vf_id = vsi_ctx->vf_num;
1391 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1392
1393 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1394
1395 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1396 sizeof(vsi_ctx->info), cmd_details);
1397
1398 if (status)
1399 goto aq_add_vsi_exit;
1400
1401 vsi_ctx->seid = le16_to_cpu(resp->seid);
1402 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1403 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1404 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1405
1406aq_add_vsi_exit:
1407 return status;
1408}
1409
1410/**
1411 * i40e_aq_set_vsi_unicast_promiscuous
1412 * @hw: pointer to the hw struct
1413 * @seid: vsi number
1414 * @set: set unicast promiscuous enable/disable
1415 * @cmd_details: pointer to command details structure or NULL
1416 **/
1417i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1418 u16 seid, bool set,
1419 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1420{
1421 struct i40e_aq_desc desc;
1422 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1423 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1424 i40e_status status;
1425 u16 flags = 0;
1426
1427 i40e_fill_default_direct_cmd_desc(&desc,
1428 i40e_aqc_opc_set_vsi_promiscuous_modes);
1429
1430 if (set)
1431 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1432
1433 cmd->promiscuous_flags = cpu_to_le16(flags);
1434
1435 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1436
1437 cmd->seid = cpu_to_le16(seid);
1438 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1439
1440 return status;
1441}
1442
1443/**
1444 * i40e_aq_set_vsi_multicast_promiscuous
1445 * @hw: pointer to the hw struct
1446 * @seid: vsi number
1447 * @set: set multicast promiscuous enable/disable
1448 * @cmd_details: pointer to command details structure or NULL
1449 **/
1450i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1451 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1452{
1453 struct i40e_aq_desc desc;
1454 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1455 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1456 i40e_status status;
1457 u16 flags = 0;
1458
1459 i40e_fill_default_direct_cmd_desc(&desc,
1460 i40e_aqc_opc_set_vsi_promiscuous_modes);
1461
1462 if (set)
1463 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1464
1465 cmd->promiscuous_flags = cpu_to_le16(flags);
1466
1467 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1468
1469 cmd->seid = cpu_to_le16(seid);
1470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1471
1472 return status;
1473}
1474
1475/**
1476 * i40e_aq_set_vsi_broadcast
1477 * @hw: pointer to the hw struct
1478 * @seid: vsi number
1479 * @set_filter: true to set filter, false to clear filter
1480 * @cmd_details: pointer to command details structure or NULL
1481 *
1482 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1483 **/
1484i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1485 u16 seid, bool set_filter,
1486 struct i40e_asq_cmd_details *cmd_details)
1487{
1488 struct i40e_aq_desc desc;
1489 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1490 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1491 i40e_status status;
1492
1493 i40e_fill_default_direct_cmd_desc(&desc,
1494 i40e_aqc_opc_set_vsi_promiscuous_modes);
1495
1496 if (set_filter)
1497 cmd->promiscuous_flags
1498 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1499 else
1500 cmd->promiscuous_flags
1501 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1502
1503 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1504 cmd->seid = cpu_to_le16(seid);
1505 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1506
1507 return status;
1508}
1509
1510/**
1511 * i40e_get_vsi_params - get VSI configuration info
1512 * @hw: pointer to the hw struct
98d44381 1513 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1514 * @cmd_details: pointer to command details structure or NULL
1515 **/
1516i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1517 struct i40e_vsi_context *vsi_ctx,
1518 struct i40e_asq_cmd_details *cmd_details)
1519{
1520 struct i40e_aq_desc desc;
f5ac8579
SN		 1521 struct i40e_aqc_add_get_update_vsi *cmd =
1522 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1523 struct i40e_aqc_add_get_update_vsi_completion *resp =
1524 (struct i40e_aqc_add_get_update_vsi_completion *)
1525 &desc.params.raw;
1526 i40e_status status;
1527
1528 i40e_fill_default_direct_cmd_desc(&desc,
1529 i40e_aqc_opc_get_vsi_parameters);
1530
f5ac8579 1531 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1532
1533 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 1534
1535 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1536 sizeof(vsi_ctx->info), NULL);
1537
1538 if (status)
1539 goto aq_get_vsi_params_exit;
1540
1541 vsi_ctx->seid = le16_to_cpu(resp->seid);
1542 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1543 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1544 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1545
1546aq_get_vsi_params_exit:
1547 return status;
1548}
1549
1550/**
1551 * i40e_aq_update_vsi_params
1552 * @hw: pointer to the hw struct
98d44381 1553 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1554 * @cmd_details: pointer to command details structure or NULL
1555 *
1556 * Update a VSI context.
1557 **/
1558i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1559 struct i40e_vsi_context *vsi_ctx,
1560 struct i40e_asq_cmd_details *cmd_details)
1561{
1562 struct i40e_aq_desc desc;
f5ac8579
SN		 1563 struct i40e_aqc_add_get_update_vsi *cmd =
1564 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1565 i40e_status status;
1566
1567 i40e_fill_default_direct_cmd_desc(&desc,
1568 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 1569 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1570
1571 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1572
1573 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1574 sizeof(vsi_ctx->info), cmd_details);
1575
1576 return status;
1577}
1578
1579/**
1580 * i40e_aq_get_switch_config
1581 * @hw: pointer to the hardware structure
1582 * @buf: pointer to the result buffer
1583 * @buf_size: length of input buffer
1584 * @start_seid: seid to start for the report, 0 == beginning
1585 * @cmd_details: pointer to command details structure or NULL
1586 *
1587 * Fill the buf with switch configuration returned from AdminQ command
1588 **/
1589i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1590 struct i40e_aqc_get_switch_config_resp *buf,
1591 u16 buf_size, u16 *start_seid,
1592 struct i40e_asq_cmd_details *cmd_details)
1593{
1594 struct i40e_aq_desc desc;
1595 struct i40e_aqc_switch_seid *scfg =
1596 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1597 i40e_status status;
1598
1599 i40e_fill_default_direct_cmd_desc(&desc,
1600 i40e_aqc_opc_get_switch_config);
1601 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1602 if (buf_size > I40E_AQ_LARGE_BUF)
1603 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1604 scfg->seid = cpu_to_le16(*start_seid);
1605
1606 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1607 *start_seid = le16_to_cpu(scfg->seid);
1608
1609 return status;
1610}
1611
1612/**
1613 * i40e_aq_get_firmware_version
1614 * @hw: pointer to the hw struct
1615 * @fw_major_version: firmware major version
1616 * @fw_minor_version: firmware minor version
1617 * @api_major_version: major queue version
1618 * @api_minor_version: minor queue version
1619 * @cmd_details: pointer to command details structure or NULL
1620 *
1621 * Get the firmware version from the admin queue commands
1622 **/
1623i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1624 u16 *fw_major_version, u16 *fw_minor_version,
1625 u16 *api_major_version, u16 *api_minor_version,
1626 struct i40e_asq_cmd_details *cmd_details)
1627{
1628 struct i40e_aq_desc desc;
1629 struct i40e_aqc_get_version *resp =
1630 (struct i40e_aqc_get_version *)&desc.params.raw;
1631 i40e_status status;
1632
1633 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1634
1635 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1636
1637 if (!status) {
1638 if (fw_major_version != NULL)
1639 *fw_major_version = le16_to_cpu(resp->fw_major);
1640 if (fw_minor_version != NULL)
1641 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1642 if (api_major_version != NULL)
1643 *api_major_version = le16_to_cpu(resp->api_major);
1644 if (api_minor_version != NULL)
1645 *api_minor_version = le16_to_cpu(resp->api_minor);
1646 }
1647
1648 return status;
1649}
1650
1651/**
1652 * i40e_aq_send_driver_version
1653 * @hw: pointer to the hw struct
56a62fc8
JB		 1654 * @dv: driver's major, minor version
1655 * @cmd_details: pointer to command details structure or NULL
1656 *
1657 * Send the driver version to the firmware
1658 **/
1659i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1660 struct i40e_driver_version *dv,
1661 struct i40e_asq_cmd_details *cmd_details)
1662{
1663 struct i40e_aq_desc desc;
1664 struct i40e_aqc_driver_version *cmd =
1665 (struct i40e_aqc_driver_version *)&desc.params.raw;
1666 i40e_status status;
9d2f98e1 1667 u16 len;
56a62fc8
JB		 1668
1669 if (dv == NULL)
1670 return I40E_ERR_PARAM;
1671
1672 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1673
1674 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1675 cmd->driver_major_ver = dv->major_version;
1676 cmd->driver_minor_ver = dv->minor_version;
1677 cmd->driver_build_ver = dv->build_version;
1678 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 1679
1680 len = 0;
1681 while (len < sizeof(dv->driver_string) &&
1682 (dv->driver_string[len] < 0x80) &&
1683 dv->driver_string[len])
1684 len++;
1685 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1686 len, cmd_details);
56a62fc8
JB		 1687
1688 return status;
1689}
1690
1691/**
1692 * i40e_get_link_status - get status of the HW network link
1693 * @hw: pointer to the hw struct
1694 *
1695 * Returns true if link is up, false if link is down.
1696 *
1697 * Side effect: LinkStatusEvent reporting becomes enabled
1698 **/
1699bool i40e_get_link_status(struct i40e_hw *hw)
1700{
1701 i40e_status status = 0;
1702 bool link_status = false;
1703
1704 if (hw->phy.get_link_info) {
1705 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1706
1707 if (status)
1708 goto i40e_get_link_status_exit;
1709 }
1710
1711 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1712
1713i40e_get_link_status_exit:
1714 return link_status;
1715}
1716
1717/**
1718 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1719 * @hw: pointer to the hw struct
1720 * @uplink_seid: the MAC or other gizmo SEID
1721 * @downlink_seid: the VSI SEID
1722 * @enabled_tc: bitmap of TCs to be enabled
1723 * @default_port: true for default port VSI, false for control port
e1c51b95 1724 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 1725 * @veb_seid: pointer to where to put the resulting VEB SEID
1726 * @cmd_details: pointer to command details structure or NULL
1727 *
1728 * This asks the FW to add a VEB between the uplink and downlink
1729 * elements. If the uplink SEID is 0, this will be a floating VEB.
1730 **/
1731i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1732 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 1733 bool default_port, bool enable_l2_filtering,
1734 u16 *veb_seid,
56a62fc8
JB		 1735 struct i40e_asq_cmd_details *cmd_details)
1736{
1737 struct i40e_aq_desc desc;
1738 struct i40e_aqc_add_veb *cmd =
1739 (struct i40e_aqc_add_veb *)&desc.params.raw;
1740 struct i40e_aqc_add_veb_completion *resp =
1741 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1742 i40e_status status;
1743 u16 veb_flags = 0;
1744
1745 /* SEIDs need to either both be set or both be 0 for floating VEB */
1746 if (!!uplink_seid != !!downlink_seid)
1747 return I40E_ERR_PARAM;
1748
1749 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1750
1751 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1752 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1753 cmd->enable_tcs = enabled_tc;
1754 if (!uplink_seid)
1755 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1756 if (default_port)
1757 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1758 else
1759 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1760
1761 if (enable_l2_filtering)
1762 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1763
56a62fc8
JB		 1764 cmd->veb_flags = cpu_to_le16(veb_flags);
1765
1766 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1767
1768 if (!status && veb_seid)
1769 *veb_seid = le16_to_cpu(resp->veb_seid);
1770
1771 return status;
1772}
1773
1774/**
1775 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1776 * @hw: pointer to the hw struct
1777 * @veb_seid: the SEID of the VEB to query
1778 * @switch_id: the uplink switch id
98d44381 1779 * @floating: set to true if the VEB is floating
56a62fc8
JB		 1780 * @statistic_index: index of the stats counter block for this VEB
1781 * @vebs_used: number of VEB's used by function
98d44381 1782 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 1783 * @cmd_details: pointer to command details structure or NULL
1784 *
1785 * This retrieves the parameters for a particular VEB, specified by
1786 * uplink_seid, and returns them to the caller.
1787 **/
1788i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1789 u16 veb_seid, u16 *switch_id,
1790 bool *floating, u16 *statistic_index,
1791 u16 *vebs_used, u16 *vebs_free,
1792 struct i40e_asq_cmd_details *cmd_details)
1793{
1794 struct i40e_aq_desc desc;
1795 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1796 (struct i40e_aqc_get_veb_parameters_completion *)
1797 &desc.params.raw;
1798 i40e_status status;
1799
1800 if (veb_seid == 0)
1801 return I40E_ERR_PARAM;
1802
1803 i40e_fill_default_direct_cmd_desc(&desc,
1804 i40e_aqc_opc_get_veb_parameters);
1805 cmd_resp->seid = cpu_to_le16(veb_seid);
1806
1807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1808 if (status)
1809 goto get_veb_exit;
1810
1811 if (switch_id)
1812 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1813 if (statistic_index)
1814 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1815 if (vebs_used)
1816 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1817 if (vebs_free)
1818 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1819 if (floating) {
1820 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1821 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1822 *floating = true;
1823 else
1824 *floating = false;
1825 }
1826
1827get_veb_exit:
1828 return status;
1829}
1830
1831/**
1832 * i40e_aq_add_macvlan
1833 * @hw: pointer to the hw struct
1834 * @seid: VSI for the mac address
1835 * @mv_list: list of macvlans to be added
1836 * @count: length of the list
1837 * @cmd_details: pointer to command details structure or NULL
1838 *
1839 * Add MAC/VLAN addresses to the HW filtering
1840 **/
1841i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1842 struct i40e_aqc_add_macvlan_element_data *mv_list,
1843 u16 count, struct i40e_asq_cmd_details *cmd_details)
1844{
1845 struct i40e_aq_desc desc;
1846 struct i40e_aqc_macvlan *cmd =
1847 (struct i40e_aqc_macvlan *)&desc.params.raw;
1848 i40e_status status;
1849 u16 buf_size;
1850
1851 if (count == 0 || !mv_list || !hw)
1852 return I40E_ERR_PARAM;
1853
1854 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1855
1856 /* prep the rest of the request */
1857 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1858 cmd->num_addresses = cpu_to_le16(count);
1859 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1860 cmd->seid[1] = 0;
1861 cmd->seid[2] = 0;
1862
1863 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1864 if (buf_size > I40E_AQ_LARGE_BUF)
1865 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1866
1867 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1868 cmd_details);
1869
1870 return status;
1871}
1872
1873/**
1874 * i40e_aq_remove_macvlan
1875 * @hw: pointer to the hw struct
1876 * @seid: VSI for the mac address
1877 * @mv_list: list of macvlans to be removed
1878 * @count: length of the list
1879 * @cmd_details: pointer to command details structure or NULL
1880 *
1881 * Remove MAC/VLAN addresses from the HW filtering
1882 **/
1883i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1884 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1885 u16 count, struct i40e_asq_cmd_details *cmd_details)
1886{
1887 struct i40e_aq_desc desc;
1888 struct i40e_aqc_macvlan *cmd =
1889 (struct i40e_aqc_macvlan *)&desc.params.raw;
1890 i40e_status status;
1891 u16 buf_size;
1892
1893 if (count == 0 || !mv_list || !hw)
1894 return I40E_ERR_PARAM;
1895
1896 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1897
1898 /* prep the rest of the request */
1899 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1900 cmd->num_addresses = cpu_to_le16(count);
1901 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1902 cmd->seid[1] = 0;
1903 cmd->seid[2] = 0;
1904
1905 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1906 if (buf_size > I40E_AQ_LARGE_BUF)
1907 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1908
1909 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1910 cmd_details);
1911
1912 return status;
1913}
1914
56a62fc8
JB		 1915/**
1916 * i40e_aq_send_msg_to_vf
1917 * @hw: pointer to the hardware structure
1918 * @vfid: vf id to send msg
98d44381
JK		 1919 * @v_opcode: opcodes for VF-PF communication
1920 * @v_retval: return error code
56a62fc8
JB		 1921 * @msg: pointer to the msg buffer
1922 * @msglen: msg length
1923 * @cmd_details: pointer to command details
1924 *
1925 * send msg to vf
1926 **/
1927i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1928 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1929 struct i40e_asq_cmd_details *cmd_details)
1930{
1931 struct i40e_aq_desc desc;
1932 struct i40e_aqc_pf_vf_message *cmd =
1933 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1934 i40e_status status;
1935
1936 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1937 cmd->id = cpu_to_le32(vfid);
1938 desc.cookie_high = cpu_to_le32(v_opcode);
1939 desc.cookie_low = cpu_to_le32(v_retval);
1940 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1941 if (msglen) {
1942 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1943 I40E_AQ_FLAG_RD));
1944 if (msglen > I40E_AQ_LARGE_BUF)
1945 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1946 desc.datalen = cpu_to_le16(msglen);
1947 }
1948 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1949
1950 return status;
1951}
1952
1953/**
1954 * i40e_aq_set_hmc_resource_profile
1955 * @hw: pointer to the hw struct
1956 * @profile: type of profile the HMC is to be set as
1957 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1958 * @cmd_details: pointer to command details structure or NULL
1959 *
1960 * set the HMC profile of the device.
1961 **/
1962i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1963 enum i40e_aq_hmc_profile profile,
1964 u8 pe_vf_enabled_count,
1965 struct i40e_asq_cmd_details *cmd_details)
1966{
1967 struct i40e_aq_desc desc;
1968 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1969 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1970 i40e_status status;
1971
1972 i40e_fill_default_direct_cmd_desc(&desc,
1973 i40e_aqc_opc_set_hmc_resource_profile);
1974
1975 cmd->pm_profile = (u8)profile;
1976 cmd->pe_vf_enabled = pe_vf_enabled_count;
1977
1978 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1979
1980 return status;
1981}
1982
1983/**
1984 * i40e_aq_request_resource
1985 * @hw: pointer to the hw struct
1986 * @resource: resource id
1987 * @access: access type
1988 * @sdp_number: resource number
1989 * @timeout: the maximum time in ms that the driver may hold the resource
1990 * @cmd_details: pointer to command details structure or NULL
1991 *
1992 * requests common resource using the admin queue commands
1993 **/
1994i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1995 enum i40e_aq_resources_ids resource,
1996 enum i40e_aq_resource_access_type access,
1997 u8 sdp_number, u64 *timeout,
1998 struct i40e_asq_cmd_details *cmd_details)
1999{
2000 struct i40e_aq_desc desc;
2001 struct i40e_aqc_request_resource *cmd_resp =
2002 (struct i40e_aqc_request_resource *)&desc.params.raw;
2003 i40e_status status;
2004
2005 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2006
2007 cmd_resp->resource_id = cpu_to_le16(resource);
2008 cmd_resp->access_type = cpu_to_le16(access);
2009 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2010
2011 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2012 /* The completion specifies the maximum time in ms that the driver
2013 * may hold the resource in the Timeout field.
2014 * If the resource is held by someone else, the command completes with
2015 * busy return value and the timeout field indicates the maximum time
2016 * the current owner of the resource has to free it.
2017 */
2018 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2019 *timeout = le32_to_cpu(cmd_resp->timeout);
2020
2021 return status;
2022}
2023
2024/**
2025 * i40e_aq_release_resource
2026 * @hw: pointer to the hw struct
2027 * @resource: resource id
2028 * @sdp_number: resource number
2029 * @cmd_details: pointer to command details structure or NULL
2030 *
2031 * release common resource using the admin queue commands
2032 **/
2033i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2034 enum i40e_aq_resources_ids resource,
2035 u8 sdp_number,
2036 struct i40e_asq_cmd_details *cmd_details)
2037{
2038 struct i40e_aq_desc desc;
2039 struct i40e_aqc_request_resource *cmd =
2040 (struct i40e_aqc_request_resource *)&desc.params.raw;
2041 i40e_status status;
2042
2043 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2044
2045 cmd->resource_id = cpu_to_le16(resource);
2046 cmd->resource_number = cpu_to_le32(sdp_number);
2047
2048 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2049
2050 return status;
2051}
2052
2053/**
2054 * i40e_aq_read_nvm
2055 * @hw: pointer to the hw struct
2056 * @module_pointer: module pointer location in words from the NVM beginning
2057 * @offset: byte offset from the module beginning
2058 * @length: length of the section to be read (in bytes from the offset)
2059 * @data: command buffer (size [bytes] = length)
2060 * @last_command: tells if this is the last command in a series
2061 * @cmd_details: pointer to command details structure or NULL
2062 *
2063 * Read the NVM using the admin queue commands
2064 **/
2065i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2066 u32 offset, u16 length, void *data,
2067 bool last_command,
2068 struct i40e_asq_cmd_details *cmd_details)
2069{
2070 struct i40e_aq_desc desc;
2071 struct i40e_aqc_nvm_update *cmd =
2072 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2073 i40e_status status;
2074
2075 /* In offset the highest byte must be zeroed. */
2076 if (offset & 0xFF000000) {
2077 status = I40E_ERR_PARAM;
2078 goto i40e_aq_read_nvm_exit;
2079 }
2080
2081 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2082
2083 /* If this is the last command in a series, set the proper flag. */
2084 if (last_command)
2085 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2086 cmd->module_pointer = module_pointer;
2087 cmd->offset = cpu_to_le32(offset);
2088 cmd->length = cpu_to_le16(length);
2089
2090 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2091 if (length > I40E_AQ_LARGE_BUF)
2092 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2093
2094 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2095
2096i40e_aq_read_nvm_exit:
2097 return status;
2098}
2099
2100#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2101#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2102#define I40E_DEV_FUNC_CAP_NPAR 0x03
2103#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2104#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2105#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2106#define I40E_DEV_FUNC_CAP_VF 0x13
2107#define I40E_DEV_FUNC_CAP_VMDQ 0x14
2108#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2109#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2110#define I40E_DEV_FUNC_CAP_VSI 0x17
2111#define I40E_DEV_FUNC_CAP_DCB 0x18
2112#define I40E_DEV_FUNC_CAP_FCOE 0x21
2113#define I40E_DEV_FUNC_CAP_RSS 0x40
2114#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2115#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2116#define I40E_DEV_FUNC_CAP_MSIX 0x43
2117#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2118#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2119#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2120#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2121#define I40E_DEV_FUNC_CAP_CEM 0xF2
2122#define I40E_DEV_FUNC_CAP_IWARP 0x51
2123#define I40E_DEV_FUNC_CAP_LED 0x61
2124#define I40E_DEV_FUNC_CAP_SDP 0x62
2125#define I40E_DEV_FUNC_CAP_MDIO 0x63
2126
2127/**
2128 * i40e_parse_discover_capabilities
2129 * @hw: pointer to the hw struct
2130 * @buff: pointer to a buffer containing device/function capability records
2131 * @cap_count: number of capability records in the list
2132 * @list_type_opc: type of capabilities list to parse
2133 *
2134 * Parse the device/function capabilities list.
2135 **/
2136static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2137 u32 cap_count,
2138 enum i40e_admin_queue_opc list_type_opc)
2139{
2140 struct i40e_aqc_list_capabilities_element_resp *cap;
2141 u32 number, logical_id, phys_id;
2142 struct i40e_hw_capabilities *p;
56a62fc8
JB		 2143 u32 i = 0;
2144 u16 id;
2145
2146 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2147
2148 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 2149 p = &hw->dev_caps;
56a62fc8 2150 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 2151 p = &hw->func_caps;
56a62fc8
JB		 2152 else
2153 return;
2154
2155 for (i = 0; i < cap_count; i++, cap++) {
2156 id = le16_to_cpu(cap->id);
2157 number = le32_to_cpu(cap->number);
2158 logical_id = le32_to_cpu(cap->logical_id);
2159 phys_id = le32_to_cpu(cap->phys_id);
2160
2161 switch (id) {
2162 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2163 p->switch_mode = number;
2164 break;
2165 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2166 p->management_mode = number;
2167 break;
2168 case I40E_DEV_FUNC_CAP_NPAR:
2169 p->npar_enable = number;
2170 break;
2171 case I40E_DEV_FUNC_CAP_OS2BMC:
2172 p->os2bmc = number;
2173 break;
2174 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2175 p->valid_functions = number;
2176 break;
2177 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2178 if (number == 1)
2179 p->sr_iov_1_1 = true;
2180 break;
2181 case I40E_DEV_FUNC_CAP_VF:
2182 p->num_vfs = number;
2183 p->vf_base_id = logical_id;
2184 break;
2185 case I40E_DEV_FUNC_CAP_VMDQ:
2186 if (number == 1)
2187 p->vmdq = true;
2188 break;
2189 case I40E_DEV_FUNC_CAP_802_1_QBG:
2190 if (number == 1)
2191 p->evb_802_1_qbg = true;
2192 break;
2193 case I40E_DEV_FUNC_CAP_802_1_QBH:
2194 if (number == 1)
2195 p->evb_802_1_qbh = true;
2196 break;
2197 case I40E_DEV_FUNC_CAP_VSI:
2198 p->num_vsis = number;
2199 break;
2200 case I40E_DEV_FUNC_CAP_DCB:
2201 if (number == 1) {
2202 p->dcb = true;
2203 p->enabled_tcmap = logical_id;
2204 p->maxtc = phys_id;
2205 }
2206 break;
2207 case I40E_DEV_FUNC_CAP_FCOE:
2208 if (number == 1)
2209 p->fcoe = true;
2210 break;
2211 case I40E_DEV_FUNC_CAP_RSS:
2212 p->rss = true;
e157ea30 2213 p->rss_table_size = number;
56a62fc8
JB		 2214 p->rss_table_entry_width = logical_id;
2215 break;
2216 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2217 p->num_rx_qp = number;
2218 p->base_queue = phys_id;
2219 break;
2220 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2221 p->num_tx_qp = number;
2222 p->base_queue = phys_id;
2223 break;
2224 case I40E_DEV_FUNC_CAP_MSIX:
2225 p->num_msix_vectors = number;
2226 break;
2227 case I40E_DEV_FUNC_CAP_MSIX_VF:
2228 p->num_msix_vectors_vf = number;
2229 break;
2230 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2231 if (number == 1)
2232 p->mfp_mode_1 = true;
2233 break;
2234 case I40E_DEV_FUNC_CAP_CEM:
2235 if (number == 1)
2236 p->mgmt_cem = true;
2237 break;
2238 case I40E_DEV_FUNC_CAP_IWARP:
2239 if (number == 1)
2240 p->iwarp = true;
2241 break;
2242 case I40E_DEV_FUNC_CAP_LED:
2243 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2244 p->led[phys_id] = true;
2245 break;
2246 case I40E_DEV_FUNC_CAP_SDP:
2247 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2248 p->sdp[phys_id] = true;
2249 break;
2250 case I40E_DEV_FUNC_CAP_MDIO:
2251 if (number == 1) {
2252 p->mdio_port_num = phys_id;
2253 p->mdio_port_mode = logical_id;
2254 }
2255 break;
2256 case I40E_DEV_FUNC_CAP_IEEE_1588:
2257 if (number == 1)
2258 p->ieee_1588 = true;
2259 break;
2260 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2261 p->fd = true;
2262 p->fd_filters_guaranteed = number;
2263 p->fd_filters_best_effort = logical_id;
2264 break;
2265 default:
2266 break;
2267 }
2268 }
2269
566bb85d
VD		 2270 /* Software override ensuring FCoE is disabled if npar or mfp
2271 * mode because it is not supported in these modes.
2272 */
2273 if (p->npar_enable || p->mfp_mode_1)
2274 p->fcoe = false;
2275
56a62fc8
JB		 2276 /* additional HW specific goodies that might
2277 * someday be HW version specific
2278 */
2279 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2280}
2281
2282/**
2283 * i40e_aq_discover_capabilities
2284 * @hw: pointer to the hw struct
2285 * @buff: a virtual buffer to hold the capabilities
2286 * @buff_size: Size of the virtual buffer
2287 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2288 * @list_type_opc: capabilities type to discover - pass in the command opcode
2289 * @cmd_details: pointer to command details structure or NULL
2290 *
2291 * Get the device capabilities descriptions from the firmware
2292 **/
2293i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2294 void *buff, u16 buff_size, u16 *data_size,
2295 enum i40e_admin_queue_opc list_type_opc,
2296 struct i40e_asq_cmd_details *cmd_details)
2297{
2298 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 2299 struct i40e_aq_desc desc;
8fb905b3 2300 i40e_status status = 0;
56a62fc8
JB		 2301
2302 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2303
2304 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2305 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2306 status = I40E_ERR_PARAM;
2307 goto exit;
2308 }
2309
2310 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2311
2312 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2313 if (buff_size > I40E_AQ_LARGE_BUF)
2314 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2315
2316 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2317 *data_size = le16_to_cpu(desc.datalen);
2318
2319 if (status)
2320 goto exit;
2321
2322 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2323 list_type_opc);
2324
2325exit:
2326 return status;
2327}
2328
2329/**
2330 * i40e_aq_get_lldp_mib
2331 * @hw: pointer to the hw struct
2332 * @bridge_type: type of bridge requested
2333 * @mib_type: Local, Remote or both Local and Remote MIBs
2334 * @buff: pointer to a user supplied buffer to store the MIB block
2335 * @buff_size: size of the buffer (in bytes)
2336 * @local_len : length of the returned Local LLDP MIB
2337 * @remote_len: length of the returned Remote LLDP MIB
2338 * @cmd_details: pointer to command details structure or NULL
2339 *
2340 * Requests the complete LLDP MIB (entire packet).
2341 **/
2342i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2343 u8 mib_type, void *buff, u16 buff_size,
2344 u16 *local_len, u16 *remote_len,
2345 struct i40e_asq_cmd_details *cmd_details)
2346{
2347 struct i40e_aq_desc desc;
2348 struct i40e_aqc_lldp_get_mib *cmd =
2349 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2350 struct i40e_aqc_lldp_get_mib *resp =
2351 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2352 i40e_status status;
2353
2354 if (buff_size == 0 || !buff)
2355 return I40E_ERR_PARAM;
2356
2357 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2358 /* Indirect Command */
2359 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2360
2361 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2362 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2363 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2364
2365 desc.datalen = cpu_to_le16(buff_size);
2366
2367 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2368 if (buff_size > I40E_AQ_LARGE_BUF)
2369 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2370
2371 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2372 if (!status) {
2373 if (local_len != NULL)
2374 *local_len = le16_to_cpu(resp->local_len);
2375 if (remote_len != NULL)
2376 *remote_len = le16_to_cpu(resp->remote_len);
2377 }
2378
2379 return status;
2380}
2381
2382/**
2383 * i40e_aq_cfg_lldp_mib_change_event
2384 * @hw: pointer to the hw struct
2385 * @enable_update: Enable or Disable event posting
2386 * @cmd_details: pointer to command details structure or NULL
2387 *
2388 * Enable or Disable posting of an event on ARQ when LLDP MIB
2389 * associated with the interface changes
2390 **/
2391i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2392 bool enable_update,
2393 struct i40e_asq_cmd_details *cmd_details)
2394{
2395 struct i40e_aq_desc desc;
2396 struct i40e_aqc_lldp_update_mib *cmd =
2397 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2398 i40e_status status;
2399
2400 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2401
2402 if (!enable_update)
2403 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2404
2405 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2406
2407 return status;
2408}
2409
2410/**
2411 * i40e_aq_stop_lldp
2412 * @hw: pointer to the hw struct
2413 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2414 * @cmd_details: pointer to command details structure or NULL
2415 *
2416 * Stop or Shutdown the embedded LLDP Agent
2417 **/
2418i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2419 struct i40e_asq_cmd_details *cmd_details)
2420{
2421 struct i40e_aq_desc desc;
2422 struct i40e_aqc_lldp_stop *cmd =
2423 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2424 i40e_status status;
2425
2426 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2427
2428 if (shutdown_agent)
2429 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2430
2431 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2432
2433 return status;
2434}
2435
2436/**
2437 * i40e_aq_start_lldp
2438 * @hw: pointer to the hw struct
2439 * @cmd_details: pointer to command details structure or NULL
2440 *
2441 * Start the embedded LLDP Agent on all ports.
2442 **/
2443i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2444 struct i40e_asq_cmd_details *cmd_details)
2445{
2446 struct i40e_aq_desc desc;
2447 struct i40e_aqc_lldp_start *cmd =
2448 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2449 i40e_status status;
2450
2451 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2452
2453 cmd->command = I40E_AQ_LLDP_AGENT_START;
2454
2455 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2456
2457 return status;
2458}
2459
a1c9a9d9
JK		 2460/**
2461 * i40e_aq_add_udp_tunnel
2462 * @hw: pointer to the hw struct
2463 * @udp_port: the UDP port to add
2464 * @header_len: length of the tunneling header length in DWords
2465 * @protocol_index: protocol index type
98d44381 2466 * @filter_index: pointer to filter index
a1c9a9d9
JK		 2467 * @cmd_details: pointer to command details structure or NULL
2468 **/
2469i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 2470 u16 udp_port, u8 protocol_index,
2471 u8 *filter_index,
a1c9a9d9
JK		 2472 struct i40e_asq_cmd_details *cmd_details)
2473{
2474 struct i40e_aq_desc desc;
2475 struct i40e_aqc_add_udp_tunnel *cmd =
2476 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2477 struct i40e_aqc_del_udp_tunnel_completion *resp =
2478 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2479 i40e_status status;
2480
2481 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2482
2483 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 2484 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 2485
2486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2487
2488 if (!status)
2489 *filter_index = resp->index;
2490
2491 return status;
2492}
2493
2494/**
2495 * i40e_aq_del_udp_tunnel
2496 * @hw: pointer to the hw struct
2497 * @index: filter index
2498 * @cmd_details: pointer to command details structure or NULL
2499 **/
2500i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2501 struct i40e_asq_cmd_details *cmd_details)
2502{
2503 struct i40e_aq_desc desc;
2504 struct i40e_aqc_remove_udp_tunnel *cmd =
2505 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2506 i40e_status status;
2507
2508 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2509
2510 cmd->index = index;
2511
2512 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2513
2514 return status;
2515}
2516
56a62fc8
JB		 2517/**
2518 * i40e_aq_delete_element - Delete switch element
2519 * @hw: pointer to the hw struct
2520 * @seid: the SEID to delete from the switch
2521 * @cmd_details: pointer to command details structure or NULL
2522 *
2523 * This deletes a switch element from the switch.
2524 **/
2525i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2526 struct i40e_asq_cmd_details *cmd_details)
2527{
2528 struct i40e_aq_desc desc;
2529 struct i40e_aqc_switch_seid *cmd =
2530 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2531 i40e_status status;
2532
2533 if (seid == 0)
2534 return I40E_ERR_PARAM;
2535
2536 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2537
2538 cmd->seid = cpu_to_le16(seid);
2539
2540 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2541
2542 return status;
2543}
2544
afb3ff0d
NP		 2545/**
2546 * i40e_aq_dcb_updated - DCB Updated Command
2547 * @hw: pointer to the hw struct
2548 * @cmd_details: pointer to command details structure or NULL
2549 *
2550 * EMP will return when the shared RPB settings have been
2551 * recomputed and modified. The retval field in the descriptor
2552 * will be set to 0 when RPB is modified.
2553 **/
2554i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2555 struct i40e_asq_cmd_details *cmd_details)
2556{
2557 struct i40e_aq_desc desc;
2558 i40e_status status;
2559
2560 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2561
2562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2563
2564 return status;
2565}
2566
56a62fc8
JB		 2567/**
2568 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2569 * @hw: pointer to the hw struct
2570 * @seid: seid for the physical port/switching component/vsi
2571 * @buff: Indirect buffer to hold data parameters and response
2572 * @buff_size: Indirect buffer size
2573 * @opcode: Tx scheduler AQ command opcode
2574 * @cmd_details: pointer to command details structure or NULL
2575 *
2576 * Generic command handler for Tx scheduler AQ commands
2577 **/
2578static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2579 void *buff, u16 buff_size,
2580 enum i40e_admin_queue_opc opcode,
2581 struct i40e_asq_cmd_details *cmd_details)
2582{
2583 struct i40e_aq_desc desc;
2584 struct i40e_aqc_tx_sched_ind *cmd =
2585 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2586 i40e_status status;
2587 bool cmd_param_flag = false;
2588
2589 switch (opcode) {
2590 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2591 case i40e_aqc_opc_configure_vsi_tc_bw:
2592 case i40e_aqc_opc_enable_switching_comp_ets:
2593 case i40e_aqc_opc_modify_switching_comp_ets:
2594 case i40e_aqc_opc_disable_switching_comp_ets:
2595 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2596 case i40e_aqc_opc_configure_switching_comp_bw_config:
2597 cmd_param_flag = true;
2598 break;
2599 case i40e_aqc_opc_query_vsi_bw_config:
2600 case i40e_aqc_opc_query_vsi_ets_sla_config:
2601 case i40e_aqc_opc_query_switching_comp_ets_config:
2602 case i40e_aqc_opc_query_port_ets_config:
2603 case i40e_aqc_opc_query_switching_comp_bw_config:
2604 cmd_param_flag = false;
2605 break;
2606 default:
2607 return I40E_ERR_PARAM;
2608 }
2609
2610 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2611
2612 /* Indirect command */
2613 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2614 if (cmd_param_flag)
2615 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2616 if (buff_size > I40E_AQ_LARGE_BUF)
2617 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2618
2619 desc.datalen = cpu_to_le16(buff_size);
2620
2621 cmd->vsi_seid = cpu_to_le16(seid);
2622
2623 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2624
2625 return status;
2626}
2627
6b192891
MW		 2628/**
2629 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2630 * @hw: pointer to the hw struct
2631 * @seid: VSI seid
2632 * @credit: BW limit credits (0 = disabled)
2633 * @max_credit: Max BW limit credits
2634 * @cmd_details: pointer to command details structure or NULL
2635 **/
2636i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2637 u16 seid, u16 credit, u8 max_credit,
2638 struct i40e_asq_cmd_details *cmd_details)
2639{
2640 struct i40e_aq_desc desc;
2641 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2642 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2643 i40e_status status;
2644
2645 i40e_fill_default_direct_cmd_desc(&desc,
2646 i40e_aqc_opc_configure_vsi_bw_limit);
2647
2648 cmd->vsi_seid = cpu_to_le16(seid);
2649 cmd->credit = cpu_to_le16(credit);
2650 cmd->max_credit = max_credit;
2651
2652 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2653
2654 return status;
2655}
2656
56a62fc8
JB		 2657/**
2658 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2659 * @hw: pointer to the hw struct
2660 * @seid: VSI seid
2661 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2662 * @cmd_details: pointer to command details structure or NULL
2663 **/
2664i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2665 u16 seid,
2666 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2667 struct i40e_asq_cmd_details *cmd_details)
2668{
2669 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2670 i40e_aqc_opc_configure_vsi_tc_bw,
2671 cmd_details);
2672}
2673
afb3ff0d
NP		 2674/**
2675 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2676 * @hw: pointer to the hw struct
2677 * @seid: seid of the switching component connected to Physical Port
2678 * @ets_data: Buffer holding ETS parameters
2679 * @cmd_details: pointer to command details structure or NULL
2680 **/
2681i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2682 u16 seid,
2683 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2684 enum i40e_admin_queue_opc opcode,
2685 struct i40e_asq_cmd_details *cmd_details)
2686{
2687 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2688 sizeof(*ets_data), opcode, cmd_details);
2689}
2690
2691/**
2692 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2693 * @hw: pointer to the hw struct
2694 * @seid: seid of the switching component
2695 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2696 * @cmd_details: pointer to command details structure or NULL
2697 **/
2698i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2699 u16 seid,
2700 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2701 struct i40e_asq_cmd_details *cmd_details)
2702{
2703 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2704 i40e_aqc_opc_configure_switching_comp_bw_config,
2705 cmd_details);
2706}
2707
56a62fc8
JB		 2708/**
2709 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2710 * @hw: pointer to the hw struct
2711 * @seid: seid of the VSI
2712 * @bw_data: Buffer to hold VSI BW configuration
2713 * @cmd_details: pointer to command details structure or NULL
2714 **/
2715i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2716 u16 seid,
2717 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2718 struct i40e_asq_cmd_details *cmd_details)
2719{
2720 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2721 i40e_aqc_opc_query_vsi_bw_config,
2722 cmd_details);
2723}
2724
2725/**
2726 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2727 * @hw: pointer to the hw struct
2728 * @seid: seid of the VSI
2729 * @bw_data: Buffer to hold VSI BW configuration per TC
2730 * @cmd_details: pointer to command details structure or NULL
2731 **/
2732i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2733 u16 seid,
2734 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2735 struct i40e_asq_cmd_details *cmd_details)
2736{
2737 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2738 i40e_aqc_opc_query_vsi_ets_sla_config,
2739 cmd_details);
2740}
2741
2742/**
2743 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2744 * @hw: pointer to the hw struct
2745 * @seid: seid of the switching component
2746 * @bw_data: Buffer to hold switching component's per TC BW config
2747 * @cmd_details: pointer to command details structure or NULL
2748 **/
2749i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2750 u16 seid,
2751 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2752 struct i40e_asq_cmd_details *cmd_details)
2753{
2754 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2755 i40e_aqc_opc_query_switching_comp_ets_config,
2756 cmd_details);
2757}
2758
2759/**
2760 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2761 * @hw: pointer to the hw struct
2762 * @seid: seid of the VSI or switching component connected to Physical Port
2763 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2764 * @cmd_details: pointer to command details structure or NULL
2765 **/
2766i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2767 u16 seid,
2768 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2769 struct i40e_asq_cmd_details *cmd_details)
2770{
2771 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2772 i40e_aqc_opc_query_port_ets_config,
2773 cmd_details);
2774}
2775
2776/**
2777 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2778 * @hw: pointer to the hw struct
2779 * @seid: seid of the switching component
2780 * @bw_data: Buffer to hold switching component's BW configuration
2781 * @cmd_details: pointer to command details structure or NULL
2782 **/
2783i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2784 u16 seid,
2785 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2786 struct i40e_asq_cmd_details *cmd_details)
2787{
2788 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2789 i40e_aqc_opc_query_switching_comp_bw_config,
2790 cmd_details);
2791}
2792
2793/**
2794 * i40e_validate_filter_settings
2795 * @hw: pointer to the hardware structure
2796 * @settings: Filter control settings
2797 *
2798 * Check and validate the filter control settings passed.
2799 * The function checks for the valid filter/context sizes being
2800 * passed for FCoE and PE.
2801 *
2802 * Returns 0 if the values passed are valid and within
2803 * range else returns an error.
2804 **/
2805static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2806 struct i40e_filter_control_settings *settings)
2807{
2808 u32 fcoe_cntx_size, fcoe_filt_size;
2809 u32 pe_cntx_size, pe_filt_size;
467d729a 2810 u32 fcoe_fmax;
56a62fc8
JB		 2811 u32 val;
2812
2813 /* Validate FCoE settings passed */
2814 switch (settings->fcoe_filt_num) {
2815 case I40E_HASH_FILTER_SIZE_1K:
2816 case I40E_HASH_FILTER_SIZE_2K:
2817 case I40E_HASH_FILTER_SIZE_4K:
2818 case I40E_HASH_FILTER_SIZE_8K:
2819 case I40E_HASH_FILTER_SIZE_16K:
2820 case I40E_HASH_FILTER_SIZE_32K:
2821 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2822 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2823 break;
2824 default:
2825 return I40E_ERR_PARAM;
2826 }
2827
2828 switch (settings->fcoe_cntx_num) {
2829 case I40E_DMA_CNTX_SIZE_512:
2830 case I40E_DMA_CNTX_SIZE_1K:
2831 case I40E_DMA_CNTX_SIZE_2K:
2832 case I40E_DMA_CNTX_SIZE_4K:
2833 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2834 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2835 break;
2836 default:
2837 return I40E_ERR_PARAM;
2838 }
2839
2840 /* Validate PE settings passed */
2841 switch (settings->pe_filt_num) {
2842 case I40E_HASH_FILTER_SIZE_1K:
2843 case I40E_HASH_FILTER_SIZE_2K:
2844 case I40E_HASH_FILTER_SIZE_4K:
2845 case I40E_HASH_FILTER_SIZE_8K:
2846 case I40E_HASH_FILTER_SIZE_16K:
2847 case I40E_HASH_FILTER_SIZE_32K:
2848 case I40E_HASH_FILTER_SIZE_64K:
2849 case I40E_HASH_FILTER_SIZE_128K:
2850 case I40E_HASH_FILTER_SIZE_256K:
2851 case I40E_HASH_FILTER_SIZE_512K:
2852 case I40E_HASH_FILTER_SIZE_1M:
2853 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2854 pe_filt_size <<= (u32)settings->pe_filt_num;
2855 break;
2856 default:
2857 return I40E_ERR_PARAM;
2858 }
2859
2860 switch (settings->pe_cntx_num) {
2861 case I40E_DMA_CNTX_SIZE_512:
2862 case I40E_DMA_CNTX_SIZE_1K:
2863 case I40E_DMA_CNTX_SIZE_2K:
2864 case I40E_DMA_CNTX_SIZE_4K:
2865 case I40E_DMA_CNTX_SIZE_8K:
2866 case I40E_DMA_CNTX_SIZE_16K:
2867 case I40E_DMA_CNTX_SIZE_32K:
2868 case I40E_DMA_CNTX_SIZE_64K:
2869 case I40E_DMA_CNTX_SIZE_128K:
2870 case I40E_DMA_CNTX_SIZE_256K:
2871 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2872 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2873 break;
2874 default:
2875 return I40E_ERR_PARAM;
2876 }
2877
2878 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2879 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2880 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2881 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2882 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2883 return I40E_ERR_INVALID_SIZE;
2884
56a62fc8
JB		 2885 return 0;
2886}
2887
2888/**
2889 * i40e_set_filter_control
2890 * @hw: pointer to the hardware structure
2891 * @settings: Filter control settings
2892 *
2893 * Set the Queue Filters for PE/FCoE and enable filters required
2894 * for a single PF. It is expected that these settings are programmed
2895 * at the driver initialization time.
2896 **/
2897i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2898 struct i40e_filter_control_settings *settings)
2899{
2900 i40e_status ret = 0;
2901 u32 hash_lut_size = 0;
2902 u32 val;
2903
2904 if (!settings)
2905 return I40E_ERR_PARAM;
2906
2907 /* Validate the input settings */
2908 ret = i40e_validate_filter_settings(hw, settings);
2909 if (ret)
2910 return ret;
2911
2912 /* Read the PF Queue Filter control register */
2913 val = rd32(hw, I40E_PFQF_CTL_0);
2914
2915 /* Program required PE hash buckets for the PF */
2916 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2917 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2918 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2919 /* Program required PE contexts for the PF */
2920 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2921 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2922 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2923
2924 /* Program required FCoE hash buckets for the PF */
2925 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2926 val |= ((u32)settings->fcoe_filt_num <<
2927 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2928 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2929 /* Program required FCoE DDP contexts for the PF */
2930 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2931 val |= ((u32)settings->fcoe_cntx_num <<
2932 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2933 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2934
2935 /* Program Hash LUT size for the PF */
2936 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2937 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2938 hash_lut_size = 1;
2939 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2940 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2941
2942 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2943 if (settings->enable_fdir)
2944 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2945 if (settings->enable_ethtype)
2946 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2947 if (settings->enable_macvlan)
2948 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2949
2950 wr32(hw, I40E_PFQF_CTL_0, val);
2951
2952 return 0;
2953}
afb3ff0d
NP		 2954
2955/**
2956 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2957 * @hw: pointer to the hw struct
2958 * @mac_addr: MAC address to use in the filter
2959 * @ethtype: Ethertype to use in the filter
2960 * @flags: Flags that needs to be applied to the filter
2961 * @vsi_seid: seid of the control VSI
2962 * @queue: VSI queue number to send the packet to
2963 * @is_add: Add control packet filter if True else remove
2964 * @stats: Structure to hold information on control filter counts
2965 * @cmd_details: pointer to command details structure or NULL
2966 *
2967 * This command will Add or Remove control packet filter for a control VSI.
2968 * In return it will update the total number of perfect filter count in
2969 * the stats member.
2970 **/
2971i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
2972 u8 *mac_addr, u16 ethtype, u16 flags,
2973 u16 vsi_seid, u16 queue, bool is_add,
2974 struct i40e_control_filter_stats *stats,
2975 struct i40e_asq_cmd_details *cmd_details)
2976{
2977 struct i40e_aq_desc desc;
2978 struct i40e_aqc_add_remove_control_packet_filter *cmd =
2979 (struct i40e_aqc_add_remove_control_packet_filter *)
2980 &desc.params.raw;
2981 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
2982 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
2983 &desc.params.raw;
2984 i40e_status status;
2985
2986 if (vsi_seid == 0)
2987 return I40E_ERR_PARAM;
2988
2989 if (is_add) {
2990 i40e_fill_default_direct_cmd_desc(&desc,
2991 i40e_aqc_opc_add_control_packet_filter);
2992 cmd->queue = cpu_to_le16(queue);
2993 } else {
2994 i40e_fill_default_direct_cmd_desc(&desc,
2995 i40e_aqc_opc_remove_control_packet_filter);
2996 }
2997
2998 if (mac_addr)
2999 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3000
3001 cmd->etype = cpu_to_le16(ethtype);
3002 cmd->flags = cpu_to_le16(flags);
3003 cmd->seid = cpu_to_le16(vsi_seid);
3004
3005 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3006
3007 if (!status && stats) {
3008 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3009 stats->etype_used = le16_to_cpu(resp->etype_used);
3010 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3011 stats->etype_free = le16_to_cpu(resp->etype_free);
3012 }
3013
3014 return status;
3015}
3016
d4dfb81a
CS		 3017/**
3018 * i40e_set_pci_config_data - store PCI bus info
3019 * @hw: pointer to hardware structure
3020 * @link_status: the link status word from PCI config space
3021 *
3022 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3023 **/
3024void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3025{
3026 hw->bus.type = i40e_bus_type_pci_express;
3027
3028 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3029 case PCI_EXP_LNKSTA_NLW_X1:
3030 hw->bus.width = i40e_bus_width_pcie_x1;
3031 break;
3032 case PCI_EXP_LNKSTA_NLW_X2:
3033 hw->bus.width = i40e_bus_width_pcie_x2;
3034 break;
3035 case PCI_EXP_LNKSTA_NLW_X4:
3036 hw->bus.width = i40e_bus_width_pcie_x4;
3037 break;
3038 case PCI_EXP_LNKSTA_NLW_X8:
3039 hw->bus.width = i40e_bus_width_pcie_x8;
3040 break;
3041 default:
3042 hw->bus.width = i40e_bus_width_unknown;
3043 break;
3044 }
3045
3046 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3047 case PCI_EXP_LNKSTA_CLS_2_5GB:
3048 hw->bus.speed = i40e_bus_speed_2500;
3049 break;
3050 case PCI_EXP_LNKSTA_CLS_5_0GB:
3051 hw->bus.speed = i40e_bus_speed_5000;
3052 break;
3053 case PCI_EXP_LNKSTA_CLS_8_0GB:
3054 hw->bus.speed = i40e_bus_speed_8000;
3055 break;
3056 default:
3057 hw->bus.speed = i40e_bus_speed_unknown;
3058 break;
3059 }
3060}
Linux kernel - Deliverables
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