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i40evf: fix overlong BIT defines
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
f1abd7db 4 * Copyright(c) 2013 - 2015 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e
SN		 46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
ab60085e
SN		 50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
5960d33f 53 case I40E_DEV_ID_10G_BASE_T:
bc5166b9 54 case I40E_DEV_ID_10G_BASE_T4:
ae24b409 55 case I40E_DEV_ID_20G_KR2:
48a3b512 56 case I40E_DEV_ID_20G_KR2_A:
56a62fc8
JB		 57 hw->mac.type = I40E_MAC_XL710;
58 break;
87e6c1d7
ASJ		 59 case I40E_DEV_ID_SFP_X722:
60 case I40E_DEV_ID_1G_BASE_T_X722:
61 case I40E_DEV_ID_10G_BASE_T_X722:
62 hw->mac.type = I40E_MAC_X722;
63 break;
64 case I40E_DEV_ID_X722_VF:
65 case I40E_DEV_ID_X722_VF_HV:
66 hw->mac.type = I40E_MAC_X722_VF;
67 break;
ab60085e
SN		 68 case I40E_DEV_ID_VF:
69 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 70 hw->mac.type = I40E_MAC_VF;
71 break;
72 default:
73 hw->mac.type = I40E_MAC_GENERIC;
74 break;
75 }
76 } else {
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
78 }
79
80 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
82 return status;
83}
84
f1c7e72e
SN		 85/**
86 * i40e_aq_str - convert AQ err code to a string
87 * @hw: pointer to the HW structure
88 * @aq_err: the AQ error code to convert
89 **/
4e68adfe 90const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
f1c7e72e
SN		 91{
92 switch (aq_err) {
93 case I40E_AQ_RC_OK:
94 return "OK";
95 case I40E_AQ_RC_EPERM:
96 return "I40E_AQ_RC_EPERM";
97 case I40E_AQ_RC_ENOENT:
98 return "I40E_AQ_RC_ENOENT";
99 case I40E_AQ_RC_ESRCH:
100 return "I40E_AQ_RC_ESRCH";
101 case I40E_AQ_RC_EINTR:
102 return "I40E_AQ_RC_EINTR";
103 case I40E_AQ_RC_EIO:
104 return "I40E_AQ_RC_EIO";
105 case I40E_AQ_RC_ENXIO:
106 return "I40E_AQ_RC_ENXIO";
107 case I40E_AQ_RC_E2BIG:
108 return "I40E_AQ_RC_E2BIG";
109 case I40E_AQ_RC_EAGAIN:
110 return "I40E_AQ_RC_EAGAIN";
111 case I40E_AQ_RC_ENOMEM:
112 return "I40E_AQ_RC_ENOMEM";
113 case I40E_AQ_RC_EACCES:
114 return "I40E_AQ_RC_EACCES";
115 case I40E_AQ_RC_EFAULT:
116 return "I40E_AQ_RC_EFAULT";
117 case I40E_AQ_RC_EBUSY:
118 return "I40E_AQ_RC_EBUSY";
119 case I40E_AQ_RC_EEXIST:
120 return "I40E_AQ_RC_EEXIST";
121 case I40E_AQ_RC_EINVAL:
122 return "I40E_AQ_RC_EINVAL";
123 case I40E_AQ_RC_ENOTTY:
124 return "I40E_AQ_RC_ENOTTY";
125 case I40E_AQ_RC_ENOSPC:
126 return "I40E_AQ_RC_ENOSPC";
127 case I40E_AQ_RC_ENOSYS:
128 return "I40E_AQ_RC_ENOSYS";
129 case I40E_AQ_RC_ERANGE:
130 return "I40E_AQ_RC_ERANGE";
131 case I40E_AQ_RC_EFLUSHED:
132 return "I40E_AQ_RC_EFLUSHED";
133 case I40E_AQ_RC_BAD_ADDR:
134 return "I40E_AQ_RC_BAD_ADDR";
135 case I40E_AQ_RC_EMODE:
136 return "I40E_AQ_RC_EMODE";
137 case I40E_AQ_RC_EFBIG:
138 return "I40E_AQ_RC_EFBIG";
139 }
140
141 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
142 return hw->err_str;
143}
144
145/**
146 * i40e_stat_str - convert status err code to a string
147 * @hw: pointer to the HW structure
148 * @stat_err: the status error code to convert
149 **/
4e68adfe 150const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
f1c7e72e
SN		 151{
152 switch (stat_err) {
153 case 0:
154 return "OK";
155 case I40E_ERR_NVM:
156 return "I40E_ERR_NVM";
157 case I40E_ERR_NVM_CHECKSUM:
158 return "I40E_ERR_NVM_CHECKSUM";
159 case I40E_ERR_PHY:
160 return "I40E_ERR_PHY";
161 case I40E_ERR_CONFIG:
162 return "I40E_ERR_CONFIG";
163 case I40E_ERR_PARAM:
164 return "I40E_ERR_PARAM";
165 case I40E_ERR_MAC_TYPE:
166 return "I40E_ERR_MAC_TYPE";
167 case I40E_ERR_UNKNOWN_PHY:
168 return "I40E_ERR_UNKNOWN_PHY";
169 case I40E_ERR_LINK_SETUP:
170 return "I40E_ERR_LINK_SETUP";
171 case I40E_ERR_ADAPTER_STOPPED:
172 return "I40E_ERR_ADAPTER_STOPPED";
173 case I40E_ERR_INVALID_MAC_ADDR:
174 return "I40E_ERR_INVALID_MAC_ADDR";
175 case I40E_ERR_DEVICE_NOT_SUPPORTED:
176 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
177 case I40E_ERR_MASTER_REQUESTS_PENDING:
178 return "I40E_ERR_MASTER_REQUESTS_PENDING";
179 case I40E_ERR_INVALID_LINK_SETTINGS:
180 return "I40E_ERR_INVALID_LINK_SETTINGS";
181 case I40E_ERR_AUTONEG_NOT_COMPLETE:
182 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
183 case I40E_ERR_RESET_FAILED:
184 return "I40E_ERR_RESET_FAILED";
185 case I40E_ERR_SWFW_SYNC:
186 return "I40E_ERR_SWFW_SYNC";
187 case I40E_ERR_NO_AVAILABLE_VSI:
188 return "I40E_ERR_NO_AVAILABLE_VSI";
189 case I40E_ERR_NO_MEMORY:
190 return "I40E_ERR_NO_MEMORY";
191 case I40E_ERR_BAD_PTR:
192 return "I40E_ERR_BAD_PTR";
193 case I40E_ERR_RING_FULL:
194 return "I40E_ERR_RING_FULL";
195 case I40E_ERR_INVALID_PD_ID:
196 return "I40E_ERR_INVALID_PD_ID";
197 case I40E_ERR_INVALID_QP_ID:
198 return "I40E_ERR_INVALID_QP_ID";
199 case I40E_ERR_INVALID_CQ_ID:
200 return "I40E_ERR_INVALID_CQ_ID";
201 case I40E_ERR_INVALID_CEQ_ID:
202 return "I40E_ERR_INVALID_CEQ_ID";
203 case I40E_ERR_INVALID_AEQ_ID:
204 return "I40E_ERR_INVALID_AEQ_ID";
205 case I40E_ERR_INVALID_SIZE:
206 return "I40E_ERR_INVALID_SIZE";
207 case I40E_ERR_INVALID_ARP_INDEX:
208 return "I40E_ERR_INVALID_ARP_INDEX";
209 case I40E_ERR_INVALID_FPM_FUNC_ID:
210 return "I40E_ERR_INVALID_FPM_FUNC_ID";
211 case I40E_ERR_QP_INVALID_MSG_SIZE:
212 return "I40E_ERR_QP_INVALID_MSG_SIZE";
213 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
214 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
215 case I40E_ERR_INVALID_FRAG_COUNT:
216 return "I40E_ERR_INVALID_FRAG_COUNT";
217 case I40E_ERR_QUEUE_EMPTY:
218 return "I40E_ERR_QUEUE_EMPTY";
219 case I40E_ERR_INVALID_ALIGNMENT:
220 return "I40E_ERR_INVALID_ALIGNMENT";
221 case I40E_ERR_FLUSHED_QUEUE:
222 return "I40E_ERR_FLUSHED_QUEUE";
223 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
224 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
225 case I40E_ERR_INVALID_IMM_DATA_SIZE:
226 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
227 case I40E_ERR_TIMEOUT:
228 return "I40E_ERR_TIMEOUT";
229 case I40E_ERR_OPCODE_MISMATCH:
230 return "I40E_ERR_OPCODE_MISMATCH";
231 case I40E_ERR_CQP_COMPL_ERROR:
232 return "I40E_ERR_CQP_COMPL_ERROR";
233 case I40E_ERR_INVALID_VF_ID:
234 return "I40E_ERR_INVALID_VF_ID";
235 case I40E_ERR_INVALID_HMCFN_ID:
236 return "I40E_ERR_INVALID_HMCFN_ID";
237 case I40E_ERR_BACKING_PAGE_ERROR:
238 return "I40E_ERR_BACKING_PAGE_ERROR";
239 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
240 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
241 case I40E_ERR_INVALID_PBLE_INDEX:
242 return "I40E_ERR_INVALID_PBLE_INDEX";
243 case I40E_ERR_INVALID_SD_INDEX:
244 return "I40E_ERR_INVALID_SD_INDEX";
245 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
246 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
247 case I40E_ERR_INVALID_SD_TYPE:
248 return "I40E_ERR_INVALID_SD_TYPE";
249 case I40E_ERR_MEMCPY_FAILED:
250 return "I40E_ERR_MEMCPY_FAILED";
251 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
252 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
253 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
254 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
255 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
256 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
257 case I40E_ERR_SRQ_ENABLED:
258 return "I40E_ERR_SRQ_ENABLED";
259 case I40E_ERR_ADMIN_QUEUE_ERROR:
260 return "I40E_ERR_ADMIN_QUEUE_ERROR";
261 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
262 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
263 case I40E_ERR_BUF_TOO_SHORT:
264 return "I40E_ERR_BUF_TOO_SHORT";
265 case I40E_ERR_ADMIN_QUEUE_FULL:
266 return "I40E_ERR_ADMIN_QUEUE_FULL";
267 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
268 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
269 case I40E_ERR_BAD_IWARP_CQE:
270 return "I40E_ERR_BAD_IWARP_CQE";
271 case I40E_ERR_NVM_BLANK_MODE:
272 return "I40E_ERR_NVM_BLANK_MODE";
273 case I40E_ERR_NOT_IMPLEMENTED:
274 return "I40E_ERR_NOT_IMPLEMENTED";
275 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
276 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
277 case I40E_ERR_DIAG_TEST_FAILED:
278 return "I40E_ERR_DIAG_TEST_FAILED";
279 case I40E_ERR_NOT_READY:
280 return "I40E_ERR_NOT_READY";
281 case I40E_NOT_SUPPORTED:
282 return "I40E_NOT_SUPPORTED";
283 case I40E_ERR_FIRMWARE_API_VERSION:
284 return "I40E_ERR_FIRMWARE_API_VERSION";
285 }
286
287 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
288 return hw->err_str;
289}
290
56a62fc8
JB		 291/**
292 * i40e_debug_aq
293 * @hw: debug mask related to admin queue
98d44381
JK		 294 * @mask: debug mask
295 * @desc: pointer to admin queue descriptor
56a62fc8 296 * @buffer: pointer to command buffer
f905dd62 297 * @buf_len: max length of buffer
56a62fc8
JB		 298 *
299 * Dumps debug log about adminq command with descriptor contents.
300 **/
301void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
f905dd62 302 void *buffer, u16 buf_len)
56a62fc8
JB		 303{
304 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
f905dd62 305 u16 len = le16_to_cpu(aq_desc->datalen);
37a2973a
SN		 306 u8 *buf = (u8 *)buffer;
307 u16 i = 0;
56a62fc8
JB		 308
309 if ((!(mask & hw->debug_mask)) || (desc == NULL))
310 return;
311
312 i40e_debug(hw, mask,
313 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
f1abd7db
PSJ		 314 le16_to_cpu(aq_desc->opcode),
315 le16_to_cpu(aq_desc->flags),
316 le16_to_cpu(aq_desc->datalen),
317 le16_to_cpu(aq_desc->retval));
56a62fc8 318 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 319 le32_to_cpu(aq_desc->cookie_high),
320 le32_to_cpu(aq_desc->cookie_low));
56a62fc8 321 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 322 le32_to_cpu(aq_desc->params.internal.param0),
323 le32_to_cpu(aq_desc->params.internal.param1));
56a62fc8 324 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 325 le32_to_cpu(aq_desc->params.external.addr_high),
326 le32_to_cpu(aq_desc->params.external.addr_low));
56a62fc8
JB		 327
328 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
56a62fc8 329 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
f905dd62
SN		 330 if (buf_len < len)
331 len = buf_len;
37a2973a
SN		 332 /* write the full 16-byte chunks */
333 for (i = 0; i < (len - 16); i += 16)
334 i40e_debug(hw, mask,
335 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
336 i, buf[i], buf[i + 1], buf[i + 2],
337 buf[i + 3], buf[i + 4], buf[i + 5],
338 buf[i + 6], buf[i + 7], buf[i + 8],
339 buf[i + 9], buf[i + 10], buf[i + 11],
340 buf[i + 12], buf[i + 13], buf[i + 14],
341 buf[i + 15]);
342 /* write whatever's left over without overrunning the buffer */
343 if (i < len) {
344 char d_buf[80];
345 int j = 0;
346
347 memset(d_buf, 0, sizeof(d_buf));
348 j += sprintf(d_buf, "\t0x%04X ", i);
349 while (i < len)
350 j += sprintf(&d_buf[j], " %02X", buf[i++]);
351 i40e_debug(hw, mask, "%s\n", d_buf);
56a62fc8 352 }
56a62fc8
JB		 353 }
354}
355
e1860d8f
ASJ		 356/**
357 * i40e_check_asq_alive
358 * @hw: pointer to the hw struct
359 *
360 * Returns true if Queue is enabled else false.
361 **/
362bool i40e_check_asq_alive(struct i40e_hw *hw)
363{
8b833b4f
KS		 364 if (hw->aq.asq.len)
365 return !!(rd32(hw, hw->aq.asq.len) &
366 I40E_PF_ATQLEN_ATQENABLE_MASK);
367 else
368 return false;
e1860d8f
ASJ		 369}
370
371/**
372 * i40e_aq_queue_shutdown
373 * @hw: pointer to the hw struct
374 * @unloading: is the driver unloading itself
375 *
376 * Tell the Firmware that we're shutting down the AdminQ and whether
377 * or not the driver is unloading as well.
378 **/
379i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
380 bool unloading)
381{
382 struct i40e_aq_desc desc;
383 struct i40e_aqc_queue_shutdown *cmd =
384 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
385 i40e_status status;
386
387 i40e_fill_default_direct_cmd_desc(&desc,
388 i40e_aqc_opc_queue_shutdown);
389
390 if (unloading)
391 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
392 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
393
394 return status;
395}
396
e50c8d6d
ASJ		 397/**
398 * i40e_aq_get_set_rss_lut
399 * @hw: pointer to the hardware structure
400 * @vsi_id: vsi fw index
401 * @pf_lut: for PF table set true, for VSI table set false
402 * @lut: pointer to the lut buffer provided by the caller
403 * @lut_size: size of the lut buffer
404 * @set: set true to set the table, false to get the table
405 *
406 * Internal function to get or set RSS look up table
407 **/
408static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
409 u16 vsi_id, bool pf_lut,
410 u8 *lut, u16 lut_size,
411 bool set)
412{
413 i40e_status status;
414 struct i40e_aq_desc desc;
415 struct i40e_aqc_get_set_rss_lut *cmd_resp =
416 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
417
418 if (set)
419 i40e_fill_default_direct_cmd_desc(&desc,
420 i40e_aqc_opc_set_rss_lut);
421 else
422 i40e_fill_default_direct_cmd_desc(&desc,
423 i40e_aqc_opc_get_rss_lut);
424
425 /* Indirect command */
426 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
427 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
428
429 cmd_resp->vsi_id =
430 cpu_to_le16((u16)((vsi_id <<
431 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
432 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
433 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
434
435 if (pf_lut)
436 cmd_resp->flags |= cpu_to_le16((u16)
437 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
438 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
439 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
440 else
441 cmd_resp->flags |= cpu_to_le16((u16)
442 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
443 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
444 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
445
e50c8d6d
ASJ		 446 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
447
448 return status;
449}
450
451/**
452 * i40e_aq_get_rss_lut
453 * @hw: pointer to the hardware structure
454 * @vsi_id: vsi fw index
455 * @pf_lut: for PF table set true, for VSI table set false
456 * @lut: pointer to the lut buffer provided by the caller
457 * @lut_size: size of the lut buffer
458 *
459 * get the RSS lookup table, PF or VSI type
460 **/
461i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
462 bool pf_lut, u8 *lut, u16 lut_size)
463{
464 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
465 false);
466}
467
468/**
469 * i40e_aq_set_rss_lut
470 * @hw: pointer to the hardware structure
471 * @vsi_id: vsi fw index
472 * @pf_lut: for PF table set true, for VSI table set false
473 * @lut: pointer to the lut buffer provided by the caller
474 * @lut_size: size of the lut buffer
475 *
476 * set the RSS lookup table, PF or VSI type
477 **/
478i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
479 bool pf_lut, u8 *lut, u16 lut_size)
480{
481 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
482}
483
484/**
485 * i40e_aq_get_set_rss_key
486 * @hw: pointer to the hw struct
487 * @vsi_id: vsi fw index
488 * @key: pointer to key info struct
489 * @set: set true to set the key, false to get the key
490 *
491 * get the RSS key per VSI
492 **/
493static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
494 u16 vsi_id,
495 struct i40e_aqc_get_set_rss_key_data *key,
496 bool set)
497{
498 i40e_status status;
499 struct i40e_aq_desc desc;
500 struct i40e_aqc_get_set_rss_key *cmd_resp =
501 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
502 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
503
504 if (set)
505 i40e_fill_default_direct_cmd_desc(&desc,
506 i40e_aqc_opc_set_rss_key);
507 else
508 i40e_fill_default_direct_cmd_desc(&desc,
509 i40e_aqc_opc_get_rss_key);
510
511 /* Indirect command */
512 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
513 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
514
515 cmd_resp->vsi_id =
516 cpu_to_le16((u16)((vsi_id <<
517 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
518 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
519 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
e50c8d6d
ASJ		 520
521 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
522
523 return status;
524}
525
526/**
527 * i40e_aq_get_rss_key
528 * @hw: pointer to the hw struct
529 * @vsi_id: vsi fw index
530 * @key: pointer to key info struct
531 *
532 **/
533i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
534 u16 vsi_id,
535 struct i40e_aqc_get_set_rss_key_data *key)
536{
537 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
538}
539
540/**
541 * i40e_aq_set_rss_key
542 * @hw: pointer to the hw struct
543 * @vsi_id: vsi fw index
544 * @key: pointer to key info struct
545 *
546 * set the RSS key per VSI
547 **/
548i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
549 u16 vsi_id,
550 struct i40e_aqc_get_set_rss_key_data *key)
551{
552 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
553}
554
206812b5
JB		 555/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
556 * hardware to a bit-field that can be used by SW to more easily determine the
557 * packet type.
558 *
559 * Macros are used to shorten the table lines and make this table human
560 * readable.
561 *
562 * We store the PTYPE in the top byte of the bit field - this is just so that
563 * we can check that the table doesn't have a row missing, as the index into
564 * the table should be the PTYPE.
565 *
566 * Typical work flow:
567 *
568 * IF NOT i40e_ptype_lookup[ptype].known
569 * THEN
570 * Packet is unknown
571 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
572 * Use the rest of the fields to look at the tunnels, inner protocols, etc
573 * ELSE
574 * Use the enum i40e_rx_l2_ptype to decode the packet type
575 * ENDIF
576 */
577
578/* macro to make the table lines short */
579#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
580 { PTYPE, \
581 1, \
582 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
583 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
584 I40E_RX_PTYPE_##OUTER_FRAG, \
585 I40E_RX_PTYPE_TUNNEL_##T, \
586 I40E_RX_PTYPE_TUNNEL_END_##TE, \
587 I40E_RX_PTYPE_##TEF, \
588 I40E_RX_PTYPE_INNER_PROT_##I, \
589 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
590
591#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
592 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
593
594/* shorter macros makes the table fit but are terse */
595#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
596#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
597#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
598
599/* Lookup table mapping the HW PTYPE to the bit field for decoding */
600struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
601 /* L2 Packet types */
602 I40E_PTT_UNUSED_ENTRY(0),
603 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
604 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
605 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
606 I40E_PTT_UNUSED_ENTRY(4),
607 I40E_PTT_UNUSED_ENTRY(5),
608 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
609 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
610 I40E_PTT_UNUSED_ENTRY(8),
611 I40E_PTT_UNUSED_ENTRY(9),
612 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
613 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
614 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
615 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
616 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
617 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
618 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
619 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
620 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
621 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
622 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
623 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
624
625 /* Non Tunneled IPv4 */
626 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
627 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
628 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
629 I40E_PTT_UNUSED_ENTRY(25),
630 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
631 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
632 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
633
634 /* IPv4 --> IPv4 */
635 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(32),
639 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
642
643 /* IPv4 --> IPv6 */
644 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(39),
648 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
651
652 /* IPv4 --> GRE/NAT */
653 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
654
655 /* IPv4 --> GRE/NAT --> IPv4 */
656 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(47),
660 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
663
664 /* IPv4 --> GRE/NAT --> IPv6 */
665 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(54),
669 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
672
673 /* IPv4 --> GRE/NAT --> MAC */
674 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
675
676 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
677 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
678 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
679 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
680 I40E_PTT_UNUSED_ENTRY(62),
681 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
682 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
683 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
684
685 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
686 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
687 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
688 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
689 I40E_PTT_UNUSED_ENTRY(69),
690 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
691 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
692 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
693
694 /* IPv4 --> GRE/NAT --> MAC/VLAN */
695 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
696
697 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
698 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
699 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
700 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
701 I40E_PTT_UNUSED_ENTRY(77),
702 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
703 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
704 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
705
706 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
707 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
708 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
709 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
710 I40E_PTT_UNUSED_ENTRY(84),
711 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
712 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
713 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
714
715 /* Non Tunneled IPv6 */
716 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
717 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
718 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
719 I40E_PTT_UNUSED_ENTRY(91),
720 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
721 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
722 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
723
724 /* IPv6 --> IPv4 */
725 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(98),
729 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
732
733 /* IPv6 --> IPv6 */
734 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(105),
738 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
741
742 /* IPv6 --> GRE/NAT */
743 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
744
745 /* IPv6 --> GRE/NAT -> IPv4 */
746 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
747 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
748 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
749 I40E_PTT_UNUSED_ENTRY(113),
750 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
751 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
752 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
753
754 /* IPv6 --> GRE/NAT -> IPv6 */
755 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
756 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
757 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(120),
759 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
760 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
761 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
762
763 /* IPv6 --> GRE/NAT -> MAC */
764 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
765
766 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
767 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
768 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
769 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
770 I40E_PTT_UNUSED_ENTRY(128),
771 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
772 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
773 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
774
775 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
776 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
777 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
778 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
779 I40E_PTT_UNUSED_ENTRY(135),
780 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
781 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
782 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
783
784 /* IPv6 --> GRE/NAT -> MAC/VLAN */
785 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
786
787 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
788 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
789 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
790 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
791 I40E_PTT_UNUSED_ENTRY(143),
792 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
793 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
794 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
795
796 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
797 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
798 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
799 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
800 I40E_PTT_UNUSED_ENTRY(150),
801 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
802 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
803 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
804
805 /* unused entries */
806 I40E_PTT_UNUSED_ENTRY(154),
807 I40E_PTT_UNUSED_ENTRY(155),
808 I40E_PTT_UNUSED_ENTRY(156),
809 I40E_PTT_UNUSED_ENTRY(157),
810 I40E_PTT_UNUSED_ENTRY(158),
811 I40E_PTT_UNUSED_ENTRY(159),
812
813 I40E_PTT_UNUSED_ENTRY(160),
814 I40E_PTT_UNUSED_ENTRY(161),
815 I40E_PTT_UNUSED_ENTRY(162),
816 I40E_PTT_UNUSED_ENTRY(163),
817 I40E_PTT_UNUSED_ENTRY(164),
818 I40E_PTT_UNUSED_ENTRY(165),
819 I40E_PTT_UNUSED_ENTRY(166),
820 I40E_PTT_UNUSED_ENTRY(167),
821 I40E_PTT_UNUSED_ENTRY(168),
822 I40E_PTT_UNUSED_ENTRY(169),
823
824 I40E_PTT_UNUSED_ENTRY(170),
825 I40E_PTT_UNUSED_ENTRY(171),
826 I40E_PTT_UNUSED_ENTRY(172),
827 I40E_PTT_UNUSED_ENTRY(173),
828 I40E_PTT_UNUSED_ENTRY(174),
829 I40E_PTT_UNUSED_ENTRY(175),
830 I40E_PTT_UNUSED_ENTRY(176),
831 I40E_PTT_UNUSED_ENTRY(177),
832 I40E_PTT_UNUSED_ENTRY(178),
833 I40E_PTT_UNUSED_ENTRY(179),
834
835 I40E_PTT_UNUSED_ENTRY(180),
836 I40E_PTT_UNUSED_ENTRY(181),
837 I40E_PTT_UNUSED_ENTRY(182),
838 I40E_PTT_UNUSED_ENTRY(183),
839 I40E_PTT_UNUSED_ENTRY(184),
840 I40E_PTT_UNUSED_ENTRY(185),
841 I40E_PTT_UNUSED_ENTRY(186),
842 I40E_PTT_UNUSED_ENTRY(187),
843 I40E_PTT_UNUSED_ENTRY(188),
844 I40E_PTT_UNUSED_ENTRY(189),
845
846 I40E_PTT_UNUSED_ENTRY(190),
847 I40E_PTT_UNUSED_ENTRY(191),
848 I40E_PTT_UNUSED_ENTRY(192),
849 I40E_PTT_UNUSED_ENTRY(193),
850 I40E_PTT_UNUSED_ENTRY(194),
851 I40E_PTT_UNUSED_ENTRY(195),
852 I40E_PTT_UNUSED_ENTRY(196),
853 I40E_PTT_UNUSED_ENTRY(197),
854 I40E_PTT_UNUSED_ENTRY(198),
855 I40E_PTT_UNUSED_ENTRY(199),
856
857 I40E_PTT_UNUSED_ENTRY(200),
858 I40E_PTT_UNUSED_ENTRY(201),
859 I40E_PTT_UNUSED_ENTRY(202),
860 I40E_PTT_UNUSED_ENTRY(203),
861 I40E_PTT_UNUSED_ENTRY(204),
862 I40E_PTT_UNUSED_ENTRY(205),
863 I40E_PTT_UNUSED_ENTRY(206),
864 I40E_PTT_UNUSED_ENTRY(207),
865 I40E_PTT_UNUSED_ENTRY(208),
866 I40E_PTT_UNUSED_ENTRY(209),
867
868 I40E_PTT_UNUSED_ENTRY(210),
869 I40E_PTT_UNUSED_ENTRY(211),
870 I40E_PTT_UNUSED_ENTRY(212),
871 I40E_PTT_UNUSED_ENTRY(213),
872 I40E_PTT_UNUSED_ENTRY(214),
873 I40E_PTT_UNUSED_ENTRY(215),
874 I40E_PTT_UNUSED_ENTRY(216),
875 I40E_PTT_UNUSED_ENTRY(217),
876 I40E_PTT_UNUSED_ENTRY(218),
877 I40E_PTT_UNUSED_ENTRY(219),
878
879 I40E_PTT_UNUSED_ENTRY(220),
880 I40E_PTT_UNUSED_ENTRY(221),
881 I40E_PTT_UNUSED_ENTRY(222),
882 I40E_PTT_UNUSED_ENTRY(223),
883 I40E_PTT_UNUSED_ENTRY(224),
884 I40E_PTT_UNUSED_ENTRY(225),
885 I40E_PTT_UNUSED_ENTRY(226),
886 I40E_PTT_UNUSED_ENTRY(227),
887 I40E_PTT_UNUSED_ENTRY(228),
888 I40E_PTT_UNUSED_ENTRY(229),
889
890 I40E_PTT_UNUSED_ENTRY(230),
891 I40E_PTT_UNUSED_ENTRY(231),
892 I40E_PTT_UNUSED_ENTRY(232),
893 I40E_PTT_UNUSED_ENTRY(233),
894 I40E_PTT_UNUSED_ENTRY(234),
895 I40E_PTT_UNUSED_ENTRY(235),
896 I40E_PTT_UNUSED_ENTRY(236),
897 I40E_PTT_UNUSED_ENTRY(237),
898 I40E_PTT_UNUSED_ENTRY(238),
899 I40E_PTT_UNUSED_ENTRY(239),
900
901 I40E_PTT_UNUSED_ENTRY(240),
902 I40E_PTT_UNUSED_ENTRY(241),
903 I40E_PTT_UNUSED_ENTRY(242),
904 I40E_PTT_UNUSED_ENTRY(243),
905 I40E_PTT_UNUSED_ENTRY(244),
906 I40E_PTT_UNUSED_ENTRY(245),
907 I40E_PTT_UNUSED_ENTRY(246),
908 I40E_PTT_UNUSED_ENTRY(247),
909 I40E_PTT_UNUSED_ENTRY(248),
910 I40E_PTT_UNUSED_ENTRY(249),
911
912 I40E_PTT_UNUSED_ENTRY(250),
913 I40E_PTT_UNUSED_ENTRY(251),
914 I40E_PTT_UNUSED_ENTRY(252),
915 I40E_PTT_UNUSED_ENTRY(253),
916 I40E_PTT_UNUSED_ENTRY(254),
917 I40E_PTT_UNUSED_ENTRY(255)
918};
919
56a62fc8
JB		 920/**
921 * i40e_init_shared_code - Initialize the shared code
922 * @hw: pointer to hardware structure
923 *
924 * This assigns the MAC type and PHY code and inits the NVM.
925 * Does not touch the hardware. This function must be called prior to any
926 * other function in the shared code. The i40e_hw structure should be
927 * memset to 0 prior to calling this function. The following fields in
928 * hw structure should be filled in prior to calling this function:
929 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
930 * subsystem_vendor_id, and revision_id
931 **/
932i40e_status i40e_init_shared_code(struct i40e_hw *hw)
933{
934 i40e_status status = 0;
5fb11d76 935 u32 port, ari, func_rid;
56a62fc8 936
56a62fc8
JB		 937 i40e_set_mac_type(hw);
938
939 switch (hw->mac.type) {
940 case I40E_MAC_XL710:
87e6c1d7 941 case I40E_MAC_X722:
56a62fc8
JB		 942 break;
943 default:
944 return I40E_ERR_DEVICE_NOT_SUPPORTED;
56a62fc8
JB		 945 }
946
af89d26c
SN		 947 hw->phy.get_link_info = true;
948
5fb11d76
SN		 949 /* Determine port number and PF number*/
950 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
951 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
952 hw->port = (u8)port;
953 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
954 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
955 func_rid = rd32(hw, I40E_PF_FUNC_RID);
956 if (ari)
957 hw->pf_id = (u8)(func_rid & 0xff);
5f9116ac 958 else
5fb11d76 959 hw->pf_id = (u8)(func_rid & 0x7);
5f9116ac 960
56a62fc8
JB		 961 status = i40e_init_nvm(hw);
962 return status;
963}
964
965/**
966 * i40e_aq_mac_address_read - Retrieve the MAC addresses
967 * @hw: pointer to the hw struct
968 * @flags: a return indicator of what addresses were added to the addr store
969 * @addrs: the requestor's mac addr store
970 * @cmd_details: pointer to command details structure or NULL
971 **/
972static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
973 u16 *flags,
974 struct i40e_aqc_mac_address_read_data *addrs,
975 struct i40e_asq_cmd_details *cmd_details)
976{
977 struct i40e_aq_desc desc;
978 struct i40e_aqc_mac_address_read *cmd_data =
979 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
980 i40e_status status;
981
982 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
983 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
984
985 status = i40e_asq_send_command(hw, &desc, addrs,
986 sizeof(*addrs), cmd_details);
987 *flags = le16_to_cpu(cmd_data->command_flags);
988
989 return status;
990}
991
992/**
993 * i40e_aq_mac_address_write - Change the MAC addresses
994 * @hw: pointer to the hw struct
995 * @flags: indicates which MAC to be written
996 * @mac_addr: address to write
997 * @cmd_details: pointer to command details structure or NULL
998 **/
999i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
1000 u16 flags, u8 *mac_addr,
1001 struct i40e_asq_cmd_details *cmd_details)
1002{
1003 struct i40e_aq_desc desc;
1004 struct i40e_aqc_mac_address_write *cmd_data =
1005 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1006 i40e_status status;
1007
1008 i40e_fill_default_direct_cmd_desc(&desc,
1009 i40e_aqc_opc_mac_address_write);
1010 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 1011 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
1012 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
1013 ((u32)mac_addr[3] << 16) |
1014 ((u32)mac_addr[4] << 8) |
1015 mac_addr[5]);
56a62fc8
JB		 1016
1017 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1018
1019 return status;
1020}
1021
1022/**
1023 * i40e_get_mac_addr - get MAC address
1024 * @hw: pointer to the HW structure
1025 * @mac_addr: pointer to MAC address
1026 *
1027 * Reads the adapter's MAC address from register
1028 **/
1029i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1030{
1031 struct i40e_aqc_mac_address_read_data addrs;
1032 i40e_status status;
1033 u16 flags = 0;
1034
1035 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1036
1037 if (flags & I40E_AQC_LAN_ADDR_VALID)
6995b36c 1038 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
56a62fc8
JB		 1039
1040 return status;
1041}
1042
1f224ad2
NP		 1043/**
1044 * i40e_get_port_mac_addr - get Port MAC address
1045 * @hw: pointer to the HW structure
1046 * @mac_addr: pointer to Port MAC address
1047 *
1048 * Reads the adapter's Port MAC address
1049 **/
1050i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1051{
1052 struct i40e_aqc_mac_address_read_data addrs;
1053 i40e_status status;
1054 u16 flags = 0;
1055
1056 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1057 if (status)
1058 return status;
1059
1060 if (flags & I40E_AQC_PORT_ADDR_VALID)
6995b36c 1061 ether_addr_copy(mac_addr, addrs.port_mac);
1f224ad2
NP		 1062 else
1063 status = I40E_ERR_INVALID_MAC_ADDR;
1064
1065 return status;
1066}
1067
351499ab
MJ		 1068/**
1069 * i40e_pre_tx_queue_cfg - pre tx queue configure
1070 * @hw: pointer to the HW structure
b40c82e6 1071 * @queue: target PF queue index
351499ab
MJ		 1072 * @enable: state change request
1073 *
1074 * Handles hw requirement to indicate intention to enable
1075 * or disable target queue.
1076 **/
1077void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1078{
dfb699f9 1079 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 1080 u32 reg_block = 0;
dfb699f9 1081 u32 reg_val;
351499ab 1082
24a768cf 1083 if (abs_queue_idx >= 128) {
351499ab 1084 reg_block = abs_queue_idx / 128;
24a768cf
CP		 1085 abs_queue_idx %= 128;
1086 }
351499ab
MJ		 1087
1088 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1089 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1090 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1091
1092 if (enable)
1093 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1094 else
1095 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1096
1097 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1098}
38e00438
VD		 1099#ifdef I40E_FCOE
1100
1101/**
1102 * i40e_get_san_mac_addr - get SAN MAC address
1103 * @hw: pointer to the HW structure
1104 * @mac_addr: pointer to SAN MAC address
1105 *
1106 * Reads the adapter's SAN MAC address from NVM
1107 **/
1108i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1109{
1110 struct i40e_aqc_mac_address_read_data addrs;
1111 i40e_status status;
1112 u16 flags = 0;
1113
1114 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1115 if (status)
1116 return status;
1117
1118 if (flags & I40E_AQC_SAN_ADDR_VALID)
6995b36c 1119 ether_addr_copy(mac_addr, addrs.pf_san_mac);
38e00438
VD		 1120 else
1121 status = I40E_ERR_INVALID_MAC_ADDR;
1122
1123 return status;
1124}
1125#endif
351499ab 1126
18f680c6
KK		 1127/**
1128 * i40e_read_pba_string - Reads part number string from EEPROM
1129 * @hw: pointer to hardware structure
1130 * @pba_num: stores the part number string from the EEPROM
1131 * @pba_num_size: part number string buffer length
1132 *
1133 * Reads the part number string from the EEPROM.
1134 **/
1135i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1136 u32 pba_num_size)
1137{
1138 i40e_status status = 0;
1139 u16 pba_word = 0;
1140 u16 pba_size = 0;
1141 u16 pba_ptr = 0;
1142 u16 i = 0;
1143
1144 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1145 if (status || (pba_word != 0xFAFA)) {
1146 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1147 return status;
1148 }
1149
1150 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1151 if (status) {
1152 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1153 return status;
1154 }
1155
1156 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1157 if (status) {
1158 hw_dbg(hw, "Failed to read PBA Block size.\n");
1159 return status;
1160 }
1161
1162 /* Subtract one to get PBA word count (PBA Size word is included in
1163 * total size)
1164 */
1165 pba_size--;
1166 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1167 hw_dbg(hw, "Buffer to small for PBA data.\n");
1168 return I40E_ERR_PARAM;
1169 }
1170
1171 for (i = 0; i < pba_size; i++) {
1172 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1173 if (status) {
1174 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1175 return status;
1176 }
1177
1178 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1179 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1180 }
1181 pba_num[(pba_size * 2)] = '\0';
1182
1183 return status;
1184}
1185
be405eb0
JB		 1186/**
1187 * i40e_get_media_type - Gets media type
1188 * @hw: pointer to the hardware structure
1189 **/
1190static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1191{
1192 enum i40e_media_type media;
1193
1194 switch (hw->phy.link_info.phy_type) {
1195 case I40E_PHY_TYPE_10GBASE_SR:
1196 case I40E_PHY_TYPE_10GBASE_LR:
124ed15b
CS		 1197 case I40E_PHY_TYPE_1000BASE_SX:
1198 case I40E_PHY_TYPE_1000BASE_LX:
be405eb0
JB		 1199 case I40E_PHY_TYPE_40GBASE_SR4:
1200 case I40E_PHY_TYPE_40GBASE_LR4:
1201 media = I40E_MEDIA_TYPE_FIBER;
1202 break;
1203 case I40E_PHY_TYPE_100BASE_TX:
1204 case I40E_PHY_TYPE_1000BASE_T:
1205 case I40E_PHY_TYPE_10GBASE_T:
1206 media = I40E_MEDIA_TYPE_BASET;
1207 break;
1208 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1209 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1210 case I40E_PHY_TYPE_10GBASE_CR1:
1211 case I40E_PHY_TYPE_40GBASE_CR4:
1212 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
180204c7
CS		 1213 case I40E_PHY_TYPE_40GBASE_AOC:
1214 case I40E_PHY_TYPE_10GBASE_AOC:
be405eb0
JB		 1215 media = I40E_MEDIA_TYPE_DA;
1216 break;
1217 case I40E_PHY_TYPE_1000BASE_KX:
1218 case I40E_PHY_TYPE_10GBASE_KX4:
1219 case I40E_PHY_TYPE_10GBASE_KR:
1220 case I40E_PHY_TYPE_40GBASE_KR4:
ae24b409 1221 case I40E_PHY_TYPE_20GBASE_KR2:
be405eb0
JB		 1222 media = I40E_MEDIA_TYPE_BACKPLANE;
1223 break;
1224 case I40E_PHY_TYPE_SGMII:
1225 case I40E_PHY_TYPE_XAUI:
1226 case I40E_PHY_TYPE_XFI:
1227 case I40E_PHY_TYPE_XLAUI:
1228 case I40E_PHY_TYPE_XLPPI:
1229 default:
1230 media = I40E_MEDIA_TYPE_UNKNOWN;
1231 break;
1232 }
1233
1234 return media;
1235}
1236
7134f9ce 1237#define I40E_PF_RESET_WAIT_COUNT_A0 200
8af580df 1238#define I40E_PF_RESET_WAIT_COUNT 200
56a62fc8
JB		 1239/**
1240 * i40e_pf_reset - Reset the PF
1241 * @hw: pointer to the hardware structure
1242 *
1243 * Assuming someone else has triggered a global reset,
1244 * assure the global reset is complete and then reset the PF
1245 **/
1246i40e_status i40e_pf_reset(struct i40e_hw *hw)
1247{
7134f9ce 1248 u32 cnt = 0;
42794bd8 1249 u32 cnt1 = 0;
56a62fc8
JB		 1250 u32 reg = 0;
1251 u32 grst_del;
1252
1253 /* Poll for Global Reset steady state in case of recent GRST.
1254 * The grst delay value is in 100ms units, and we'll wait a
1255 * couple counts longer to be sure we don't just miss the end.
1256 */
de78fc5a
SN		 1257 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1258 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1259 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
22e05bd6 1260 for (cnt = 0; cnt < grst_del + 10; cnt++) {
56a62fc8
JB		 1261 reg = rd32(hw, I40E_GLGEN_RSTAT);
1262 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1263 break;
1264 msleep(100);
1265 }
1266 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1267 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 1268 return I40E_ERR_RESET_FAILED;
1269 }
1270
1271 /* Now Wait for the FW to be ready */
1272 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1273 reg = rd32(hw, I40E_GLNVM_ULD);
1274 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1275 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1276 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1277 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1278 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1279 break;
1280 }
1281 usleep_range(10000, 20000);
1282 }
1283 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1284 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1285 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1286 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 1287 return I40E_ERR_RESET_FAILED;
1288 }
1289
56a62fc8
JB		 1290 /* If there was a Global Reset in progress when we got here,
1291 * we don't need to do the PF Reset
1292 */
7134f9ce
JB		 1293 if (!cnt) {
1294 if (hw->revision_id == 0)
1295 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1296 else
1297 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 1298 reg = rd32(hw, I40E_PFGEN_CTRL);
1299 wr32(hw, I40E_PFGEN_CTRL,
1300 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 1301 for (; cnt; cnt--) {
56a62fc8
JB		 1302 reg = rd32(hw, I40E_PFGEN_CTRL);
1303 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1304 break;
1305 usleep_range(1000, 2000);
1306 }
1307 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1308 hw_dbg(hw, "PF reset polling failed to complete.\n");
1309 return I40E_ERR_RESET_FAILED;
1310 }
1311 }
1312
1313 i40e_clear_pxe_mode(hw);
922680b9 1314
56a62fc8
JB		 1315 return 0;
1316}
1317
838d41d9
SN		 1318/**
1319 * i40e_clear_hw - clear out any left over hw state
1320 * @hw: pointer to the hw struct
1321 *
1322 * Clear queues and interrupts, typically called at init time,
1323 * but after the capabilities have been found so we know how many
1324 * queues and msix vectors have been allocated.
1325 **/
1326void i40e_clear_hw(struct i40e_hw *hw)
1327{
1328 u32 num_queues, base_queue;
1329 u32 num_pf_int;
1330 u32 num_vf_int;
1331 u32 num_vfs;
1332 u32 i, j;
1333 u32 val;
1334 u32 eol = 0x7ff;
1335
b40c82e6 1336 /* get number of interrupts, queues, and VFs */
838d41d9
SN		 1337 val = rd32(hw, I40E_GLPCI_CNF2);
1338 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1339 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1340 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1341 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1342
1343 val = rd32(hw, I40E_PFLAN_QALLOC);
1344 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1345 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1346 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1347 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1348 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1349 num_queues = (j - base_queue) + 1;
1350 else
1351 num_queues = 0;
1352
1353 val = rd32(hw, I40E_PF_VT_PFALLOC);
1354 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1355 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1356 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1357 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1358 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1359 num_vfs = (j - i) + 1;
1360 else
1361 num_vfs = 0;
1362
1363 /* stop all the interrupts */
1364 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1365 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1366 for (i = 0; i < num_pf_int - 2; i++)
1367 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1368
1369 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1370 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1371 wr32(hw, I40E_PFINT_LNKLST0, val);
1372 for (i = 0; i < num_pf_int - 2; i++)
1373 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1374 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1375 for (i = 0; i < num_vfs; i++)
1376 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1377 for (i = 0; i < num_vf_int - 2; i++)
1378 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1379
1380 /* warn the HW of the coming Tx disables */
1381 for (i = 0; i < num_queues; i++) {
1382 u32 abs_queue_idx = base_queue + i;
1383 u32 reg_block = 0;
1384
1385 if (abs_queue_idx >= 128) {
1386 reg_block = abs_queue_idx / 128;
1387 abs_queue_idx %= 128;
1388 }
1389
1390 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1391 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1392 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1393 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1394
1395 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1396 }
1397 udelay(400);
1398
1399 /* stop all the queues */
1400 for (i = 0; i < num_queues; i++) {
1401 wr32(hw, I40E_QINT_TQCTL(i), 0);
1402 wr32(hw, I40E_QTX_ENA(i), 0);
1403 wr32(hw, I40E_QINT_RQCTL(i), 0);
1404 wr32(hw, I40E_QRX_ENA(i), 0);
1405 }
1406
1407 /* short wait for all queue disables to settle */
1408 udelay(50);
1409}
1410
56a62fc8
JB		 1411/**
1412 * i40e_clear_pxe_mode - clear pxe operations mode
1413 * @hw: pointer to the hw struct
1414 *
1415 * Make sure all PXE mode settings are cleared, including things
1416 * like descriptor fetch/write-back mode.
1417 **/
1418void i40e_clear_pxe_mode(struct i40e_hw *hw)
1419{
1420 u32 reg;
1421
c9b9b0ae
SN		 1422 if (i40e_check_asq_alive(hw))
1423 i40e_aq_clear_pxe_mode(hw, NULL);
1424
56a62fc8
JB		 1425 /* Clear single descriptor fetch/write-back mode */
1426 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 1427
1428 if (hw->revision_id == 0) {
1429 /* As a work around clear PXE_MODE instead of setting it */
1430 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1431 } else {
1432 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1433 }
56a62fc8
JB		 1434}
1435
0556a9e3
JB		 1436/**
1437 * i40e_led_is_mine - helper to find matching led
1438 * @hw: pointer to the hw struct
1439 * @idx: index into GPIO registers
1440 *
1441 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1442 */
1443static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1444{
1445 u32 gpio_val = 0;
1446 u32 port;
1447
1448 if (!hw->func_caps.led[idx])
1449 return 0;
1450
1451 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1452 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1453 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1454
1455 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1456 * if it is not our port then ignore
1457 */
1458 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1459 (port != hw->port))
1460 return 0;
1461
1462 return gpio_val;
1463}
1464
b84d5cd8
MJ		 1465#define I40E_COMBINED_ACTIVITY 0xA
1466#define I40E_FILTER_ACTIVITY 0xE
0556a9e3 1467#define I40E_LINK_ACTIVITY 0xC
b84d5cd8
MJ		 1468#define I40E_MAC_ACTIVITY 0xD
1469#define I40E_LED0 22
0556a9e3 1470
56a62fc8
JB		 1471/**
1472 * i40e_led_get - return current on/off mode
1473 * @hw: pointer to the hw struct
1474 *
1475 * The value returned is the 'mode' field as defined in the
1476 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1477 * values are variations of possible behaviors relating to
1478 * blink, link, and wire.
1479 **/
1480u32 i40e_led_get(struct i40e_hw *hw)
1481{
b84d5cd8 1482 u32 current_mode = 0;
56a62fc8 1483 u32 mode = 0;
56a62fc8
JB		 1484 int i;
1485
0556a9e3
JB		 1486 /* as per the documentation GPIO 22-29 are the LED
1487 * GPIO pins named LED0..LED7
1488 */
1489 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1490 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1491
0556a9e3 1492 if (!gpio_val)
56a62fc8
JB		 1493 continue;
1494
b84d5cd8
MJ		 1495 /* ignore gpio LED src mode entries related to the activity
1496 * LEDs
1497 */
1498 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1499 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1500 switch (current_mode) {
1501 case I40E_COMBINED_ACTIVITY:
1502 case I40E_FILTER_ACTIVITY:
1503 case I40E_MAC_ACTIVITY:
1504 continue;
1505 default:
1506 break;
1507 }
1508
0556a9e3
JB		 1509 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1510 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 1511 break;
1512 }
1513
1514 return mode;
1515}
1516
1517/**
1518 * i40e_led_set - set new on/off mode
1519 * @hw: pointer to the hw struct
0556a9e3
JB		 1520 * @mode: 0=off, 0xf=on (else see manual for mode details)
1521 * @blink: true if the LED should blink when on, false if steady
1522 *
1523 * if this function is used to turn on the blink it should
1524 * be used to disable the blink when restoring the original state.
56a62fc8 1525 **/
0556a9e3 1526void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1527{
b84d5cd8 1528 u32 current_mode = 0;
56a62fc8
JB		 1529 int i;
1530
0556a9e3
JB		 1531 if (mode & 0xfffffff0)
1532 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1533
0556a9e3
JB		 1534 /* as per the documentation GPIO 22-29 are the LED
1535 * GPIO pins named LED0..LED7
1536 */
1537 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1538 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1539
0556a9e3 1540 if (!gpio_val)
56a62fc8
JB		 1541 continue;
1542
b84d5cd8
MJ		 1543 /* ignore gpio LED src mode entries related to the activity
1544 * LEDs
1545 */
1546 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1547 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1548 switch (current_mode) {
1549 case I40E_COMBINED_ACTIVITY:
1550 case I40E_FILTER_ACTIVITY:
1551 case I40E_MAC_ACTIVITY:
1552 continue;
1553 default:
1554 break;
1555 }
1556
56a62fc8 1557 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1558 /* this & is a bit of paranoia, but serves as a range check */
1559 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1560 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1561
1562 if (mode == I40E_LINK_ACTIVITY)
1563 blink = false;
1564
9be00d67 1565 if (blink)
41a1d04b 1566 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
9be00d67 1567 else
41a1d04b 1568 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
0556a9e3 1569
56a62fc8 1570 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1571 break;
56a62fc8
JB		 1572 }
1573}
1574
1575/* Admin command wrappers */
56a62fc8 1576
8109e123
CS		 1577/**
1578 * i40e_aq_get_phy_capabilities
1579 * @hw: pointer to the hw struct
1580 * @abilities: structure for PHY capabilities to be filled
1581 * @qualified_modules: report Qualified Modules
1582 * @report_init: report init capabilities (active are default)
1583 * @cmd_details: pointer to command details structure or NULL
1584 *
1585 * Returns the various PHY abilities supported on the Port.
1586 **/
1587i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1588 bool qualified_modules, bool report_init,
1589 struct i40e_aq_get_phy_abilities_resp *abilities,
1590 struct i40e_asq_cmd_details *cmd_details)
1591{
1592 struct i40e_aq_desc desc;
1593 i40e_status status;
1594 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1595
1596 if (!abilities)
1597 return I40E_ERR_PARAM;
1598
1599 i40e_fill_default_direct_cmd_desc(&desc,
1600 i40e_aqc_opc_get_phy_abilities);
1601
1602 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1603 if (abilities_size > I40E_AQ_LARGE_BUF)
1604 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1605
1606 if (qualified_modules)
1607 desc.params.external.param0 |=
1608 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1609
1610 if (report_init)
1611 desc.params.external.param0 |=
1612 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1613
1614 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1615 cmd_details);
1616
1617 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1618 status = I40E_ERR_UNKNOWN_PHY;
1619
3ac67d7b
KS		 1620 if (report_init)
1621 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1622
8109e123
CS		 1623 return status;
1624}
1625
c56999f9
CS		 1626/**
1627 * i40e_aq_set_phy_config
1628 * @hw: pointer to the hw struct
1629 * @config: structure with PHY configuration to be set
1630 * @cmd_details: pointer to command details structure or NULL
1631 *
1632 * Set the various PHY configuration parameters
1633 * supported on the Port.One or more of the Set PHY config parameters may be
1634 * ignored in an MFP mode as the PF may not have the privilege to set some
1635 * of the PHY Config parameters. This status will be indicated by the
1636 * command response.
1637 **/
1638enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1639 struct i40e_aq_set_phy_config *config,
1640 struct i40e_asq_cmd_details *cmd_details)
1641{
1642 struct i40e_aq_desc desc;
1643 struct i40e_aq_set_phy_config *cmd =
1644 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1645 enum i40e_status_code status;
1646
1647 if (!config)
1648 return I40E_ERR_PARAM;
1649
1650 i40e_fill_default_direct_cmd_desc(&desc,
1651 i40e_aqc_opc_set_phy_config);
1652
1653 *cmd = *config;
1654
1655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1656
1657 return status;
1658}
1659
1660/**
1661 * i40e_set_fc
1662 * @hw: pointer to the hw struct
1663 *
1664 * Set the requested flow control mode using set_phy_config.
1665 **/
1666enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1667 bool atomic_restart)
1668{
1669 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1670 struct i40e_aq_get_phy_abilities_resp abilities;
1671 struct i40e_aq_set_phy_config config;
1672 enum i40e_status_code status;
1673 u8 pause_mask = 0x0;
1674
1675 *aq_failures = 0x0;
1676
1677 switch (fc_mode) {
1678 case I40E_FC_FULL:
1679 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1680 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1681 break;
1682 case I40E_FC_RX_PAUSE:
1683 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1684 break;
1685 case I40E_FC_TX_PAUSE:
1686 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1687 break;
1688 default:
1689 break;
1690 }
1691
1692 /* Get the current phy config */
1693 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1694 NULL);
1695 if (status) {
1696 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1697 return status;
1698 }
1699
1700 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1701 /* clear the old pause settings */
1702 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1703 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1704 /* set the new abilities */
1705 config.abilities |= pause_mask;
1706 /* If the abilities have changed, then set the new config */
1707 if (config.abilities != abilities.abilities) {
1708 /* Auto restart link so settings take effect */
1709 if (atomic_restart)
1710 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1711 /* Copy over all the old settings */
1712 config.phy_type = abilities.phy_type;
1713 config.link_speed = abilities.link_speed;
1714 config.eee_capability = abilities.eee_capability;
1715 config.eeer = abilities.eeer_val;
1716 config.low_power_ctrl = abilities.d3_lpan;
1717 status = i40e_aq_set_phy_config(hw, &config, NULL);
1718
1719 if (status)
1720 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1721 }
1722 /* Update the link info */
0a862b43 1723 status = i40e_update_link_info(hw);
c56999f9
CS		 1724 if (status) {
1725 /* Wait a little bit (on 40G cards it sometimes takes a really
1726 * long time for link to come back from the atomic reset)
1727 * and try once more
1728 */
1729 msleep(1000);
0a862b43 1730 status = i40e_update_link_info(hw);
c56999f9
CS		 1731 }
1732 if (status)
1733 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1734
1735 return status;
1736}
1737
c9b9b0ae
SN		 1738/**
1739 * i40e_aq_clear_pxe_mode
1740 * @hw: pointer to the hw struct
1741 * @cmd_details: pointer to command details structure or NULL
1742 *
1743 * Tell the firmware that the driver is taking over from PXE
1744 **/
1745i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1746 struct i40e_asq_cmd_details *cmd_details)
1747{
1748 i40e_status status;
1749 struct i40e_aq_desc desc;
1750 struct i40e_aqc_clear_pxe *cmd =
1751 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1752
1753 i40e_fill_default_direct_cmd_desc(&desc,
1754 i40e_aqc_opc_clear_pxe_mode);
1755
1756 cmd->rx_cnt = 0x2;
1757
1758 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1759
1760 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1761
1762 return status;
1763}
1764
56a62fc8
JB		 1765/**
1766 * i40e_aq_set_link_restart_an
1767 * @hw: pointer to the hw struct
1ac978af 1768 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1769 * @cmd_details: pointer to command details structure or NULL
1770 *
1771 * Sets up the link and restarts the Auto-Negotiation over the link.
1772 **/
1773i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1774 bool enable_link,
1775 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1776{
1777 struct i40e_aq_desc desc;
1778 struct i40e_aqc_set_link_restart_an *cmd =
1779 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1780 i40e_status status;
1781
1782 i40e_fill_default_direct_cmd_desc(&desc,
1783 i40e_aqc_opc_set_link_restart_an);
1784
1785 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1786 if (enable_link)
1787 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1788 else
1789 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1790
1791 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1792
1793 return status;
1794}
1795
1796/**
1797 * i40e_aq_get_link_info
1798 * @hw: pointer to the hw struct
1799 * @enable_lse: enable/disable LinkStatusEvent reporting
1800 * @link: pointer to link status structure - optional
1801 * @cmd_details: pointer to command details structure or NULL
1802 *
1803 * Returns the link status of the adapter.
1804 **/
1805i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1806 bool enable_lse, struct i40e_link_status *link,
1807 struct i40e_asq_cmd_details *cmd_details)
1808{
1809 struct i40e_aq_desc desc;
1810 struct i40e_aqc_get_link_status *resp =
1811 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1812 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1813 i40e_status status;
c56999f9 1814 bool tx_pause, rx_pause;
56a62fc8
JB		 1815 u16 command_flags;
1816
1817 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1818
1819 if (enable_lse)
1820 command_flags = I40E_AQ_LSE_ENABLE;
1821 else
1822 command_flags = I40E_AQ_LSE_DISABLE;
1823 resp->command_flags = cpu_to_le16(command_flags);
1824
1825 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1826
1827 if (status)
1828 goto aq_get_link_info_exit;
1829
1830 /* save off old link status information */
c36bd4a7 1831 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1832
1833 /* update link status */
1834 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1835 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1836 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1837 hw_link_info->link_info = resp->link_info;
1838 hw_link_info->an_info = resp->an_info;
1839 hw_link_info->ext_info = resp->ext_info;
639dc377 1840 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1841 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1842 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1843
c56999f9
CS		 1844 /* update fc info */
1845 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1846 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1847 if (tx_pause & rx_pause)
1848 hw->fc.current_mode = I40E_FC_FULL;
1849 else if (tx_pause)
1850 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1851 else if (rx_pause)
1852 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1853 else
1854 hw->fc.current_mode = I40E_FC_NONE;
1855
6bb3f23c
NP		 1856 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1857 hw_link_info->crc_enable = true;
1858 else
1859 hw_link_info->crc_enable = false;
56a62fc8
JB		 1860
1861 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1862 hw_link_info->lse_enable = true;
1863 else
1864 hw_link_info->lse_enable = false;
1865
088c4ee3
CS		 1866 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1867 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1868 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1869
56a62fc8
JB		 1870 /* save link status information */
1871 if (link)
d7595a22 1872 *link = *hw_link_info;
56a62fc8
JB		 1873
1874 /* flag cleared so helper functions don't call AQ again */
1875 hw->phy.get_link_info = false;
1876
1877aq_get_link_info_exit:
1878 return status;
1879}
1880
7e2453fe
JB		 1881/**
1882 * i40e_aq_set_phy_int_mask
1883 * @hw: pointer to the hw struct
1884 * @mask: interrupt mask to be set
1885 * @cmd_details: pointer to command details structure or NULL
1886 *
1887 * Set link interrupt mask.
1888 **/
1889i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1890 u16 mask,
1891 struct i40e_asq_cmd_details *cmd_details)
1892{
1893 struct i40e_aq_desc desc;
1894 struct i40e_aqc_set_phy_int_mask *cmd =
1895 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1896 i40e_status status;
1897
1898 i40e_fill_default_direct_cmd_desc(&desc,
1899 i40e_aqc_opc_set_phy_int_mask);
1900
1901 cmd->event_mask = cpu_to_le16(mask);
1902
1903 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1904
1905 return status;
1906}
1907
56a62fc8
JB		 1908/**
1909 * i40e_aq_add_vsi
1910 * @hw: pointer to the hw struct
98d44381 1911 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1912 * @cmd_details: pointer to command details structure or NULL
1913 *
1914 * Add a VSI context to the hardware.
1915**/
1916i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1917 struct i40e_vsi_context *vsi_ctx,
1918 struct i40e_asq_cmd_details *cmd_details)
1919{
1920 struct i40e_aq_desc desc;
1921 struct i40e_aqc_add_get_update_vsi *cmd =
1922 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1923 struct i40e_aqc_add_get_update_vsi_completion *resp =
1924 (struct i40e_aqc_add_get_update_vsi_completion *)
1925 &desc.params.raw;
1926 i40e_status status;
1927
1928 i40e_fill_default_direct_cmd_desc(&desc,
1929 i40e_aqc_opc_add_vsi);
1930
1931 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1932 cmd->connection_type = vsi_ctx->connection_type;
1933 cmd->vf_id = vsi_ctx->vf_num;
1934 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1935
1936 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1937
1938 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1939 sizeof(vsi_ctx->info), cmd_details);
1940
1941 if (status)
1942 goto aq_add_vsi_exit;
1943
1944 vsi_ctx->seid = le16_to_cpu(resp->seid);
1945 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1946 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1947 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1948
1949aq_add_vsi_exit:
1950 return status;
1951}
1952
1953/**
1954 * i40e_aq_set_vsi_unicast_promiscuous
1955 * @hw: pointer to the hw struct
1956 * @seid: vsi number
1957 * @set: set unicast promiscuous enable/disable
1958 * @cmd_details: pointer to command details structure or NULL
1959 **/
1960i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1961 u16 seid, bool set,
1962 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1963{
1964 struct i40e_aq_desc desc;
1965 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1966 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1967 i40e_status status;
1968 u16 flags = 0;
1969
1970 i40e_fill_default_direct_cmd_desc(&desc,
1971 i40e_aqc_opc_set_vsi_promiscuous_modes);
1972
1973 if (set)
1974 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1975
1976 cmd->promiscuous_flags = cpu_to_le16(flags);
1977
1978 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1979
1980 cmd->seid = cpu_to_le16(seid);
1981 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1982
1983 return status;
1984}
1985
1986/**
1987 * i40e_aq_set_vsi_multicast_promiscuous
1988 * @hw: pointer to the hw struct
1989 * @seid: vsi number
1990 * @set: set multicast promiscuous enable/disable
1991 * @cmd_details: pointer to command details structure or NULL
1992 **/
1993i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1994 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1995{
1996 struct i40e_aq_desc desc;
1997 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1998 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1999 i40e_status status;
2000 u16 flags = 0;
2001
2002 i40e_fill_default_direct_cmd_desc(&desc,
2003 i40e_aqc_opc_set_vsi_promiscuous_modes);
2004
2005 if (set)
2006 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2007
2008 cmd->promiscuous_flags = cpu_to_le16(flags);
2009
2010 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2011
2012 cmd->seid = cpu_to_le16(seid);
2013 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2014
2015 return status;
2016}
2017
2018/**
2019 * i40e_aq_set_vsi_broadcast
2020 * @hw: pointer to the hw struct
2021 * @seid: vsi number
2022 * @set_filter: true to set filter, false to clear filter
2023 * @cmd_details: pointer to command details structure or NULL
2024 *
2025 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2026 **/
2027i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2028 u16 seid, bool set_filter,
2029 struct i40e_asq_cmd_details *cmd_details)
2030{
2031 struct i40e_aq_desc desc;
2032 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2033 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2034 i40e_status status;
2035
2036 i40e_fill_default_direct_cmd_desc(&desc,
2037 i40e_aqc_opc_set_vsi_promiscuous_modes);
2038
2039 if (set_filter)
2040 cmd->promiscuous_flags
2041 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2042 else
2043 cmd->promiscuous_flags
2044 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2045
2046 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2047 cmd->seid = cpu_to_le16(seid);
2048 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2049
2050 return status;
2051}
2052
2053/**
2054 * i40e_get_vsi_params - get VSI configuration info
2055 * @hw: pointer to the hw struct
98d44381 2056 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2057 * @cmd_details: pointer to command details structure or NULL
2058 **/
2059i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2060 struct i40e_vsi_context *vsi_ctx,
2061 struct i40e_asq_cmd_details *cmd_details)
2062{
2063 struct i40e_aq_desc desc;
f5ac8579
SN		 2064 struct i40e_aqc_add_get_update_vsi *cmd =
2065 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 2066 struct i40e_aqc_add_get_update_vsi_completion *resp =
2067 (struct i40e_aqc_add_get_update_vsi_completion *)
2068 &desc.params.raw;
2069 i40e_status status;
2070
2071 i40e_fill_default_direct_cmd_desc(&desc,
2072 i40e_aqc_opc_get_vsi_parameters);
2073
f5ac8579 2074 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2075
2076 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 2077
2078 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2079 sizeof(vsi_ctx->info), NULL);
2080
2081 if (status)
2082 goto aq_get_vsi_params_exit;
2083
2084 vsi_ctx->seid = le16_to_cpu(resp->seid);
2085 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2086 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2087 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2088
2089aq_get_vsi_params_exit:
2090 return status;
2091}
2092
2093/**
2094 * i40e_aq_update_vsi_params
2095 * @hw: pointer to the hw struct
98d44381 2096 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2097 * @cmd_details: pointer to command details structure or NULL
2098 *
2099 * Update a VSI context.
2100 **/
2101i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2102 struct i40e_vsi_context *vsi_ctx,
2103 struct i40e_asq_cmd_details *cmd_details)
2104{
2105 struct i40e_aq_desc desc;
f5ac8579
SN		 2106 struct i40e_aqc_add_get_update_vsi *cmd =
2107 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 2108 i40e_status status;
2109
2110 i40e_fill_default_direct_cmd_desc(&desc,
2111 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 2112 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2113
2114 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 2115
2116 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2117 sizeof(vsi_ctx->info), cmd_details);
2118
2119 return status;
2120}
2121
2122/**
2123 * i40e_aq_get_switch_config
2124 * @hw: pointer to the hardware structure
2125 * @buf: pointer to the result buffer
2126 * @buf_size: length of input buffer
2127 * @start_seid: seid to start for the report, 0 == beginning
2128 * @cmd_details: pointer to command details structure or NULL
2129 *
2130 * Fill the buf with switch configuration returned from AdminQ command
2131 **/
2132i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2133 struct i40e_aqc_get_switch_config_resp *buf,
2134 u16 buf_size, u16 *start_seid,
2135 struct i40e_asq_cmd_details *cmd_details)
2136{
2137 struct i40e_aq_desc desc;
2138 struct i40e_aqc_switch_seid *scfg =
2139 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2140 i40e_status status;
2141
2142 i40e_fill_default_direct_cmd_desc(&desc,
2143 i40e_aqc_opc_get_switch_config);
2144 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2145 if (buf_size > I40E_AQ_LARGE_BUF)
2146 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2147 scfg->seid = cpu_to_le16(*start_seid);
2148
2149 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2150 *start_seid = le16_to_cpu(scfg->seid);
2151
2152 return status;
2153}
2154
2155/**
2156 * i40e_aq_get_firmware_version
2157 * @hw: pointer to the hw struct
2158 * @fw_major_version: firmware major version
2159 * @fw_minor_version: firmware minor version
7edf810c 2160 * @fw_build: firmware build number
56a62fc8
JB		 2161 * @api_major_version: major queue version
2162 * @api_minor_version: minor queue version
2163 * @cmd_details: pointer to command details structure or NULL
2164 *
2165 * Get the firmware version from the admin queue commands
2166 **/
2167i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2168 u16 *fw_major_version, u16 *fw_minor_version,
7edf810c 2169 u32 *fw_build,
56a62fc8
JB		 2170 u16 *api_major_version, u16 *api_minor_version,
2171 struct i40e_asq_cmd_details *cmd_details)
2172{
2173 struct i40e_aq_desc desc;
2174 struct i40e_aqc_get_version *resp =
2175 (struct i40e_aqc_get_version *)&desc.params.raw;
2176 i40e_status status;
2177
2178 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2179
2180 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2181
2182 if (!status) {
7edf810c 2183 if (fw_major_version)
56a62fc8 2184 *fw_major_version = le16_to_cpu(resp->fw_major);
7edf810c 2185 if (fw_minor_version)
56a62fc8 2186 *fw_minor_version = le16_to_cpu(resp->fw_minor);
7edf810c
SN		 2187 if (fw_build)
2188 *fw_build = le32_to_cpu(resp->fw_build);
2189 if (api_major_version)
56a62fc8 2190 *api_major_version = le16_to_cpu(resp->api_major);
7edf810c 2191 if (api_minor_version)
56a62fc8
JB		 2192 *api_minor_version = le16_to_cpu(resp->api_minor);
2193 }
2194
2195 return status;
2196}
2197
2198/**
2199 * i40e_aq_send_driver_version
2200 * @hw: pointer to the hw struct
56a62fc8
JB		 2201 * @dv: driver's major, minor version
2202 * @cmd_details: pointer to command details structure or NULL
2203 *
2204 * Send the driver version to the firmware
2205 **/
2206i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2207 struct i40e_driver_version *dv,
2208 struct i40e_asq_cmd_details *cmd_details)
2209{
2210 struct i40e_aq_desc desc;
2211 struct i40e_aqc_driver_version *cmd =
2212 (struct i40e_aqc_driver_version *)&desc.params.raw;
2213 i40e_status status;
9d2f98e1 2214 u16 len;
56a62fc8
JB		 2215
2216 if (dv == NULL)
2217 return I40E_ERR_PARAM;
2218
2219 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2220
3b38cd17 2221 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
56a62fc8
JB		 2222 cmd->driver_major_ver = dv->major_version;
2223 cmd->driver_minor_ver = dv->minor_version;
2224 cmd->driver_build_ver = dv->build_version;
2225 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 2226
2227 len = 0;
2228 while (len < sizeof(dv->driver_string) &&
2229 (dv->driver_string[len] < 0x80) &&
2230 dv->driver_string[len])
2231 len++;
2232 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2233 len, cmd_details);
56a62fc8
JB		 2234
2235 return status;
2236}
2237
2238/**
2239 * i40e_get_link_status - get status of the HW network link
2240 * @hw: pointer to the hw struct
a72a5abc 2241 * @link_up: pointer to bool (true/false = linkup/linkdown)
56a62fc8 2242 *
a72a5abc
JB		 2243 * Variable link_up true if link is up, false if link is down.
2244 * The variable link_up is invalid if returned value of status != 0
56a62fc8
JB		 2245 *
2246 * Side effect: LinkStatusEvent reporting becomes enabled
2247 **/
a72a5abc 2248i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
56a62fc8
JB		 2249{
2250 i40e_status status = 0;
56a62fc8
JB		 2251
2252 if (hw->phy.get_link_info) {
0a862b43 2253 status = i40e_update_link_info(hw);
56a62fc8
JB		 2254
2255 if (status)
a72a5abc
JB		 2256 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2257 status);
56a62fc8
JB		 2258 }
2259
a72a5abc 2260 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
56a62fc8 2261
a72a5abc 2262 return status;
56a62fc8
JB		 2263}
2264
0a862b43
CS		 2265/**
2266 * i40e_updatelink_status - update status of the HW network link
2267 * @hw: pointer to the hw struct
2268 **/
2269i40e_status i40e_update_link_info(struct i40e_hw *hw)
2270{
2271 struct i40e_aq_get_phy_abilities_resp abilities;
2272 i40e_status status = 0;
2273
2274 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2275 if (status)
2276 return status;
2277
2278 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2279 NULL);
2280 if (status)
2281 return status;
2282
2283 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2284 sizeof(hw->phy.link_info.module_type));
2285
2286 return status;
2287}
2288
56a62fc8
JB		 2289/**
2290 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2291 * @hw: pointer to the hw struct
2292 * @uplink_seid: the MAC or other gizmo SEID
2293 * @downlink_seid: the VSI SEID
2294 * @enabled_tc: bitmap of TCs to be enabled
2295 * @default_port: true for default port VSI, false for control port
e1c51b95 2296 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 2297 * @veb_seid: pointer to where to put the resulting VEB SEID
2298 * @cmd_details: pointer to command details structure or NULL
2299 *
2300 * This asks the FW to add a VEB between the uplink and downlink
2301 * elements. If the uplink SEID is 0, this will be a floating VEB.
2302 **/
2303i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2304 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 2305 bool default_port, bool enable_l2_filtering,
2306 u16 *veb_seid,
56a62fc8
JB		 2307 struct i40e_asq_cmd_details *cmd_details)
2308{
2309 struct i40e_aq_desc desc;
2310 struct i40e_aqc_add_veb *cmd =
2311 (struct i40e_aqc_add_veb *)&desc.params.raw;
2312 struct i40e_aqc_add_veb_completion *resp =
2313 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2314 i40e_status status;
2315 u16 veb_flags = 0;
2316
2317 /* SEIDs need to either both be set or both be 0 for floating VEB */
2318 if (!!uplink_seid != !!downlink_seid)
2319 return I40E_ERR_PARAM;
2320
2321 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2322
2323 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2324 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2325 cmd->enable_tcs = enabled_tc;
2326 if (!uplink_seid)
2327 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2328 if (default_port)
2329 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2330 else
2331 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 2332
2333 if (enable_l2_filtering)
2334 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2335
56a62fc8
JB		 2336 cmd->veb_flags = cpu_to_le16(veb_flags);
2337
2338 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2339
2340 if (!status && veb_seid)
2341 *veb_seid = le16_to_cpu(resp->veb_seid);
2342
2343 return status;
2344}
2345
2346/**
2347 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2348 * @hw: pointer to the hw struct
2349 * @veb_seid: the SEID of the VEB to query
2350 * @switch_id: the uplink switch id
98d44381 2351 * @floating: set to true if the VEB is floating
56a62fc8
JB		 2352 * @statistic_index: index of the stats counter block for this VEB
2353 * @vebs_used: number of VEB's used by function
98d44381 2354 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 2355 * @cmd_details: pointer to command details structure or NULL
2356 *
2357 * This retrieves the parameters for a particular VEB, specified by
2358 * uplink_seid, and returns them to the caller.
2359 **/
2360i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2361 u16 veb_seid, u16 *switch_id,
2362 bool *floating, u16 *statistic_index,
2363 u16 *vebs_used, u16 *vebs_free,
2364 struct i40e_asq_cmd_details *cmd_details)
2365{
2366 struct i40e_aq_desc desc;
2367 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2368 (struct i40e_aqc_get_veb_parameters_completion *)
2369 &desc.params.raw;
2370 i40e_status status;
2371
2372 if (veb_seid == 0)
2373 return I40E_ERR_PARAM;
2374
2375 i40e_fill_default_direct_cmd_desc(&desc,
2376 i40e_aqc_opc_get_veb_parameters);
2377 cmd_resp->seid = cpu_to_le16(veb_seid);
2378
2379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2380 if (status)
2381 goto get_veb_exit;
2382
2383 if (switch_id)
2384 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2385 if (statistic_index)
2386 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2387 if (vebs_used)
2388 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2389 if (vebs_free)
2390 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2391 if (floating) {
2392 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
6995b36c 2393
56a62fc8
JB		 2394 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2395 *floating = true;
2396 else
2397 *floating = false;
2398 }
2399
2400get_veb_exit:
2401 return status;
2402}
2403
2404/**
2405 * i40e_aq_add_macvlan
2406 * @hw: pointer to the hw struct
2407 * @seid: VSI for the mac address
2408 * @mv_list: list of macvlans to be added
2409 * @count: length of the list
2410 * @cmd_details: pointer to command details structure or NULL
2411 *
2412 * Add MAC/VLAN addresses to the HW filtering
2413 **/
2414i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2415 struct i40e_aqc_add_macvlan_element_data *mv_list,
2416 u16 count, struct i40e_asq_cmd_details *cmd_details)
2417{
2418 struct i40e_aq_desc desc;
2419 struct i40e_aqc_macvlan *cmd =
2420 (struct i40e_aqc_macvlan *)&desc.params.raw;
2421 i40e_status status;
2422 u16 buf_size;
2423
2424 if (count == 0 || !mv_list || !hw)
2425 return I40E_ERR_PARAM;
2426
1efc80ee 2427 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2428
2429 /* prep the rest of the request */
2430 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2431 cmd->num_addresses = cpu_to_le16(count);
2432 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2433 cmd->seid[1] = 0;
2434 cmd->seid[2] = 0;
2435
2436 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2437 if (buf_size > I40E_AQ_LARGE_BUF)
2438 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2439
2440 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2441 cmd_details);
2442
2443 return status;
2444}
2445
2446/**
2447 * i40e_aq_remove_macvlan
2448 * @hw: pointer to the hw struct
2449 * @seid: VSI for the mac address
2450 * @mv_list: list of macvlans to be removed
2451 * @count: length of the list
2452 * @cmd_details: pointer to command details structure or NULL
2453 *
2454 * Remove MAC/VLAN addresses from the HW filtering
2455 **/
2456i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2457 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2458 u16 count, struct i40e_asq_cmd_details *cmd_details)
2459{
2460 struct i40e_aq_desc desc;
2461 struct i40e_aqc_macvlan *cmd =
2462 (struct i40e_aqc_macvlan *)&desc.params.raw;
2463 i40e_status status;
2464 u16 buf_size;
2465
2466 if (count == 0 || !mv_list || !hw)
2467 return I40E_ERR_PARAM;
2468
1efc80ee 2469 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2470
2471 /* prep the rest of the request */
2472 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2473 cmd->num_addresses = cpu_to_le16(count);
2474 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2475 cmd->seid[1] = 0;
2476 cmd->seid[2] = 0;
2477
2478 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2479 if (buf_size > I40E_AQ_LARGE_BUF)
2480 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2481
2482 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2483 cmd_details);
2484
2485 return status;
2486}
2487
56a62fc8
JB		 2488/**
2489 * i40e_aq_send_msg_to_vf
2490 * @hw: pointer to the hardware structure
b40c82e6 2491 * @vfid: VF id to send msg
98d44381
JK		 2492 * @v_opcode: opcodes for VF-PF communication
2493 * @v_retval: return error code
56a62fc8
JB		 2494 * @msg: pointer to the msg buffer
2495 * @msglen: msg length
2496 * @cmd_details: pointer to command details
2497 *
2498 * send msg to vf
2499 **/
2500i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2501 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2502 struct i40e_asq_cmd_details *cmd_details)
2503{
2504 struct i40e_aq_desc desc;
2505 struct i40e_aqc_pf_vf_message *cmd =
2506 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2507 i40e_status status;
2508
2509 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2510 cmd->id = cpu_to_le32(vfid);
2511 desc.cookie_high = cpu_to_le32(v_opcode);
2512 desc.cookie_low = cpu_to_le32(v_retval);
2513 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2514 if (msglen) {
2515 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2516 I40E_AQ_FLAG_RD));
2517 if (msglen > I40E_AQ_LARGE_BUF)
2518 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2519 desc.datalen = cpu_to_le16(msglen);
2520 }
2521 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2522
2523 return status;
2524}
2525
9fee9db5
SN		 2526/**
2527 * i40e_aq_debug_read_register
2528 * @hw: pointer to the hw struct
2529 * @reg_addr: register address
2530 * @reg_val: register value
2531 * @cmd_details: pointer to command details structure or NULL
2532 *
2533 * Read the register using the admin queue commands
2534 **/
2535i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
7b115dd0 2536 u32 reg_addr, u64 *reg_val,
9fee9db5
SN		 2537 struct i40e_asq_cmd_details *cmd_details)
2538{
2539 struct i40e_aq_desc desc;
2540 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2541 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2542 i40e_status status;
2543
2544 if (reg_val == NULL)
2545 return I40E_ERR_PARAM;
2546
7b115dd0 2547 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
9fee9db5
SN		 2548
2549 cmd_resp->address = cpu_to_le32(reg_addr);
2550
2551 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2552
2553 if (!status) {
7b115dd0
JB		 2554 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2555 (u64)le32_to_cpu(cmd_resp->value_low);
9fee9db5
SN		 2556 }
2557
2558 return status;
2559}
2560
53db45cd
SN		 2561/**
2562 * i40e_aq_debug_write_register
2563 * @hw: pointer to the hw struct
2564 * @reg_addr: register address
2565 * @reg_val: register value
2566 * @cmd_details: pointer to command details structure or NULL
2567 *
2568 * Write to a register using the admin queue commands
2569 **/
2570i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2571 u32 reg_addr, u64 reg_val,
2572 struct i40e_asq_cmd_details *cmd_details)
2573{
2574 struct i40e_aq_desc desc;
2575 struct i40e_aqc_debug_reg_read_write *cmd =
2576 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2577 i40e_status status;
2578
2579 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2580
2581 cmd->address = cpu_to_le32(reg_addr);
2582 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2583 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2584
2585 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2586
2587 return status;
2588}
2589
56a62fc8
JB		 2590/**
2591 * i40e_aq_set_hmc_resource_profile
2592 * @hw: pointer to the hw struct
2593 * @profile: type of profile the HMC is to be set as
2594 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2595 * @cmd_details: pointer to command details structure or NULL
2596 *
2597 * set the HMC profile of the device.
2598 **/
2599i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2600 enum i40e_aq_hmc_profile profile,
2601 u8 pe_vf_enabled_count,
2602 struct i40e_asq_cmd_details *cmd_details)
2603{
2604 struct i40e_aq_desc desc;
2605 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2606 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2607 i40e_status status;
2608
2609 i40e_fill_default_direct_cmd_desc(&desc,
2610 i40e_aqc_opc_set_hmc_resource_profile);
2611
2612 cmd->pm_profile = (u8)profile;
2613 cmd->pe_vf_enabled = pe_vf_enabled_count;
2614
2615 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2616
2617 return status;
2618}
2619
2620/**
2621 * i40e_aq_request_resource
2622 * @hw: pointer to the hw struct
2623 * @resource: resource id
2624 * @access: access type
2625 * @sdp_number: resource number
2626 * @timeout: the maximum time in ms that the driver may hold the resource
2627 * @cmd_details: pointer to command details structure or NULL
2628 *
2629 * requests common resource using the admin queue commands
2630 **/
2631i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2632 enum i40e_aq_resources_ids resource,
2633 enum i40e_aq_resource_access_type access,
2634 u8 sdp_number, u64 *timeout,
2635 struct i40e_asq_cmd_details *cmd_details)
2636{
2637 struct i40e_aq_desc desc;
2638 struct i40e_aqc_request_resource *cmd_resp =
2639 (struct i40e_aqc_request_resource *)&desc.params.raw;
2640 i40e_status status;
2641
2642 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2643
2644 cmd_resp->resource_id = cpu_to_le16(resource);
2645 cmd_resp->access_type = cpu_to_le16(access);
2646 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2647
2648 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2649 /* The completion specifies the maximum time in ms that the driver
2650 * may hold the resource in the Timeout field.
2651 * If the resource is held by someone else, the command completes with
2652 * busy return value and the timeout field indicates the maximum time
2653 * the current owner of the resource has to free it.
2654 */
2655 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2656 *timeout = le32_to_cpu(cmd_resp->timeout);
2657
2658 return status;
2659}
2660
2661/**
2662 * i40e_aq_release_resource
2663 * @hw: pointer to the hw struct
2664 * @resource: resource id
2665 * @sdp_number: resource number
2666 * @cmd_details: pointer to command details structure or NULL
2667 *
2668 * release common resource using the admin queue commands
2669 **/
2670i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2671 enum i40e_aq_resources_ids resource,
2672 u8 sdp_number,
2673 struct i40e_asq_cmd_details *cmd_details)
2674{
2675 struct i40e_aq_desc desc;
2676 struct i40e_aqc_request_resource *cmd =
2677 (struct i40e_aqc_request_resource *)&desc.params.raw;
2678 i40e_status status;
2679
2680 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2681
2682 cmd->resource_id = cpu_to_le16(resource);
2683 cmd->resource_number = cpu_to_le32(sdp_number);
2684
2685 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2686
2687 return status;
2688}
2689
2690/**
2691 * i40e_aq_read_nvm
2692 * @hw: pointer to the hw struct
2693 * @module_pointer: module pointer location in words from the NVM beginning
2694 * @offset: byte offset from the module beginning
2695 * @length: length of the section to be read (in bytes from the offset)
2696 * @data: command buffer (size [bytes] = length)
2697 * @last_command: tells if this is the last command in a series
2698 * @cmd_details: pointer to command details structure or NULL
2699 *
2700 * Read the NVM using the admin queue commands
2701 **/
2702i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2703 u32 offset, u16 length, void *data,
2704 bool last_command,
2705 struct i40e_asq_cmd_details *cmd_details)
2706{
2707 struct i40e_aq_desc desc;
2708 struct i40e_aqc_nvm_update *cmd =
2709 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2710 i40e_status status;
2711
2712 /* In offset the highest byte must be zeroed. */
2713 if (offset & 0xFF000000) {
2714 status = I40E_ERR_PARAM;
2715 goto i40e_aq_read_nvm_exit;
2716 }
2717
2718 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2719
2720 /* If this is the last command in a series, set the proper flag. */
2721 if (last_command)
2722 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2723 cmd->module_pointer = module_pointer;
2724 cmd->offset = cpu_to_le32(offset);
2725 cmd->length = cpu_to_le16(length);
2726
2727 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2728 if (length > I40E_AQ_LARGE_BUF)
2729 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2730
2731 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2732
2733i40e_aq_read_nvm_exit:
2734 return status;
2735}
2736
cd552cb4
SN		 2737/**
2738 * i40e_aq_erase_nvm
2739 * @hw: pointer to the hw struct
2740 * @module_pointer: module pointer location in words from the NVM beginning
2741 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2742 * @length: length of the section to be erased (expressed in 4 KB)
2743 * @last_command: tells if this is the last command in a series
2744 * @cmd_details: pointer to command details structure or NULL
2745 *
2746 * Erase the NVM sector using the admin queue commands
2747 **/
2748i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2749 u32 offset, u16 length, bool last_command,
2750 struct i40e_asq_cmd_details *cmd_details)
2751{
2752 struct i40e_aq_desc desc;
2753 struct i40e_aqc_nvm_update *cmd =
2754 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2755 i40e_status status;
2756
2757 /* In offset the highest byte must be zeroed. */
2758 if (offset & 0xFF000000) {
2759 status = I40E_ERR_PARAM;
2760 goto i40e_aq_erase_nvm_exit;
2761 }
2762
2763 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2764
2765 /* If this is the last command in a series, set the proper flag. */
2766 if (last_command)
2767 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2768 cmd->module_pointer = module_pointer;
2769 cmd->offset = cpu_to_le32(offset);
2770 cmd->length = cpu_to_le16(length);
2771
2772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2773
2774i40e_aq_erase_nvm_exit:
2775 return status;
2776}
2777
56a62fc8
JB		 2778#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2779#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2780#define I40E_DEV_FUNC_CAP_NPAR 0x03
2781#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2782#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2783#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2784#define I40E_DEV_FUNC_CAP_VF 0x13
2785#define I40E_DEV_FUNC_CAP_VMDQ 0x14
2786#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2787#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2788#define I40E_DEV_FUNC_CAP_VSI 0x17
2789#define I40E_DEV_FUNC_CAP_DCB 0x18
2790#define I40E_DEV_FUNC_CAP_FCOE 0x21
63d7e5a4 2791#define I40E_DEV_FUNC_CAP_ISCSI 0x22
56a62fc8
JB		 2792#define I40E_DEV_FUNC_CAP_RSS 0x40
2793#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2794#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2795#define I40E_DEV_FUNC_CAP_MSIX 0x43
2796#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2797#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2798#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
c78b953e 2799#define I40E_DEV_FUNC_CAP_FLEX10 0xF1
56a62fc8
JB		 2800#define I40E_DEV_FUNC_CAP_CEM 0xF2
2801#define I40E_DEV_FUNC_CAP_IWARP 0x51
2802#define I40E_DEV_FUNC_CAP_LED 0x61
2803#define I40E_DEV_FUNC_CAP_SDP 0x62
2804#define I40E_DEV_FUNC_CAP_MDIO 0x63
73b23402 2805#define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
56a62fc8
JB		 2806
2807/**
2808 * i40e_parse_discover_capabilities
2809 * @hw: pointer to the hw struct
2810 * @buff: pointer to a buffer containing device/function capability records
2811 * @cap_count: number of capability records in the list
2812 * @list_type_opc: type of capabilities list to parse
2813 *
2814 * Parse the device/function capabilities list.
2815 **/
2816static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2817 u32 cap_count,
2818 enum i40e_admin_queue_opc list_type_opc)
2819{
2820 struct i40e_aqc_list_capabilities_element_resp *cap;
9fee9db5 2821 u32 valid_functions, num_functions;
56a62fc8
JB		 2822 u32 number, logical_id, phys_id;
2823 struct i40e_hw_capabilities *p;
c78b953e 2824 u8 major_rev;
56a62fc8
JB		 2825 u32 i = 0;
2826 u16 id;
2827
2828 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2829
2830 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 2831 p = &hw->dev_caps;
56a62fc8 2832 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 2833 p = &hw->func_caps;
56a62fc8
JB		 2834 else
2835 return;
2836
2837 for (i = 0; i < cap_count; i++, cap++) {
2838 id = le16_to_cpu(cap->id);
2839 number = le32_to_cpu(cap->number);
2840 logical_id = le32_to_cpu(cap->logical_id);
2841 phys_id = le32_to_cpu(cap->phys_id);
c78b953e 2842 major_rev = cap->major_rev;
56a62fc8
JB		 2843
2844 switch (id) {
2845 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2846 p->switch_mode = number;
2847 break;
2848 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2849 p->management_mode = number;
2850 break;
2851 case I40E_DEV_FUNC_CAP_NPAR:
2852 p->npar_enable = number;
2853 break;
2854 case I40E_DEV_FUNC_CAP_OS2BMC:
2855 p->os2bmc = number;
2856 break;
2857 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2858 p->valid_functions = number;
2859 break;
2860 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2861 if (number == 1)
2862 p->sr_iov_1_1 = true;
2863 break;
2864 case I40E_DEV_FUNC_CAP_VF:
2865 p->num_vfs = number;
2866 p->vf_base_id = logical_id;
2867 break;
2868 case I40E_DEV_FUNC_CAP_VMDQ:
2869 if (number == 1)
2870 p->vmdq = true;
2871 break;
2872 case I40E_DEV_FUNC_CAP_802_1_QBG:
2873 if (number == 1)
2874 p->evb_802_1_qbg = true;
2875 break;
2876 case I40E_DEV_FUNC_CAP_802_1_QBH:
2877 if (number == 1)
2878 p->evb_802_1_qbh = true;
2879 break;
2880 case I40E_DEV_FUNC_CAP_VSI:
2881 p->num_vsis = number;
2882 break;
2883 case I40E_DEV_FUNC_CAP_DCB:
2884 if (number == 1) {
2885 p->dcb = true;
2886 p->enabled_tcmap = logical_id;
2887 p->maxtc = phys_id;
2888 }
2889 break;
2890 case I40E_DEV_FUNC_CAP_FCOE:
2891 if (number == 1)
2892 p->fcoe = true;
2893 break;
63d7e5a4
NP		 2894 case I40E_DEV_FUNC_CAP_ISCSI:
2895 if (number == 1)
2896 p->iscsi = true;
2897 break;
56a62fc8
JB		 2898 case I40E_DEV_FUNC_CAP_RSS:
2899 p->rss = true;
e157ea30 2900 p->rss_table_size = number;
56a62fc8
JB		 2901 p->rss_table_entry_width = logical_id;
2902 break;
2903 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2904 p->num_rx_qp = number;
2905 p->base_queue = phys_id;
2906 break;
2907 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2908 p->num_tx_qp = number;
2909 p->base_queue = phys_id;
2910 break;
2911 case I40E_DEV_FUNC_CAP_MSIX:
2912 p->num_msix_vectors = number;
2913 break;
2914 case I40E_DEV_FUNC_CAP_MSIX_VF:
2915 p->num_msix_vectors_vf = number;
2916 break;
c78b953e
PO		 2917 case I40E_DEV_FUNC_CAP_FLEX10:
2918 if (major_rev == 1) {
2919 if (number == 1) {
2920 p->flex10_enable = true;
2921 p->flex10_capable = true;
2922 }
2923 } else {
2924 /* Capability revision >= 2 */
2925 if (number & 1)
2926 p->flex10_enable = true;
2927 if (number & 2)
2928 p->flex10_capable = true;
2929 }
2930 p->flex10_mode = logical_id;
2931 p->flex10_status = phys_id;
56a62fc8
JB		 2932 break;
2933 case I40E_DEV_FUNC_CAP_CEM:
2934 if (number == 1)
2935 p->mgmt_cem = true;
2936 break;
2937 case I40E_DEV_FUNC_CAP_IWARP:
2938 if (number == 1)
2939 p->iwarp = true;
2940 break;
2941 case I40E_DEV_FUNC_CAP_LED:
2942 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2943 p->led[phys_id] = true;
2944 break;
2945 case I40E_DEV_FUNC_CAP_SDP:
2946 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2947 p->sdp[phys_id] = true;
2948 break;
2949 case I40E_DEV_FUNC_CAP_MDIO:
2950 if (number == 1) {
2951 p->mdio_port_num = phys_id;
2952 p->mdio_port_mode = logical_id;
2953 }
2954 break;
2955 case I40E_DEV_FUNC_CAP_IEEE_1588:
2956 if (number == 1)
2957 p->ieee_1588 = true;
2958 break;
2959 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2960 p->fd = true;
2961 p->fd_filters_guaranteed = number;
2962 p->fd_filters_best_effort = logical_id;
2963 break;
73b23402
KS		 2964 case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
2965 p->wr_csr_prot = (u64)number;
2966 p->wr_csr_prot |= (u64)logical_id << 32;
2967 break;
56a62fc8
JB		 2968 default:
2969 break;
2970 }
2971 }
2972
f18ae100
VD		 2973 if (p->fcoe)
2974 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
2975
566bb85d
VD		 2976 /* Software override ensuring FCoE is disabled if npar or mfp
2977 * mode because it is not supported in these modes.
2978 */
c78b953e 2979 if (p->npar_enable || p->flex10_enable)
566bb85d
VD		 2980 p->fcoe = false;
2981
9fee9db5
SN		 2982 /* count the enabled ports (aka the "not disabled" ports) */
2983 hw->num_ports = 0;
2984 for (i = 0; i < 4; i++) {
2985 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2986 u64 port_cfg = 0;
2987
2988 /* use AQ read to get the physical register offset instead
2989 * of the port relative offset
2990 */
2991 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2992 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2993 hw->num_ports++;
2994 }
2995
2996 valid_functions = p->valid_functions;
2997 num_functions = 0;
2998 while (valid_functions) {
2999 if (valid_functions & 1)
3000 num_functions++;
3001 valid_functions >>= 1;
3002 }
3003
3004 /* partition id is 1-based, and functions are evenly spread
3005 * across the ports as partitions
3006 */
3007 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3008 hw->num_partitions = num_functions / hw->num_ports;
3009
56a62fc8
JB		 3010 /* additional HW specific goodies that might
3011 * someday be HW version specific
3012 */
3013 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3014}
3015
3016/**
3017 * i40e_aq_discover_capabilities
3018 * @hw: pointer to the hw struct
3019 * @buff: a virtual buffer to hold the capabilities
3020 * @buff_size: Size of the virtual buffer
3021 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3022 * @list_type_opc: capabilities type to discover - pass in the command opcode
3023 * @cmd_details: pointer to command details structure or NULL
3024 *
3025 * Get the device capabilities descriptions from the firmware
3026 **/
3027i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3028 void *buff, u16 buff_size, u16 *data_size,
3029 enum i40e_admin_queue_opc list_type_opc,
3030 struct i40e_asq_cmd_details *cmd_details)
3031{
3032 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 3033 struct i40e_aq_desc desc;
8fb905b3 3034 i40e_status status = 0;
56a62fc8
JB		 3035
3036 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3037
3038 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3039 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3040 status = I40E_ERR_PARAM;
3041 goto exit;
3042 }
3043
3044 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3045
3046 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3047 if (buff_size > I40E_AQ_LARGE_BUF)
3048 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3049
3050 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3051 *data_size = le16_to_cpu(desc.datalen);
3052
3053 if (status)
3054 goto exit;
3055
3056 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3057 list_type_opc);
3058
3059exit:
3060 return status;
3061}
3062
cd552cb4
SN		 3063/**
3064 * i40e_aq_update_nvm
3065 * @hw: pointer to the hw struct
3066 * @module_pointer: module pointer location in words from the NVM beginning
3067 * @offset: byte offset from the module beginning
3068 * @length: length of the section to be written (in bytes from the offset)
3069 * @data: command buffer (size [bytes] = length)
3070 * @last_command: tells if this is the last command in a series
3071 * @cmd_details: pointer to command details structure or NULL
3072 *
3073 * Update the NVM using the admin queue commands
3074 **/
3075i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3076 u32 offset, u16 length, void *data,
3077 bool last_command,
3078 struct i40e_asq_cmd_details *cmd_details)
3079{
3080 struct i40e_aq_desc desc;
3081 struct i40e_aqc_nvm_update *cmd =
3082 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3083 i40e_status status;
3084
3085 /* In offset the highest byte must be zeroed. */
3086 if (offset & 0xFF000000) {
3087 status = I40E_ERR_PARAM;
3088 goto i40e_aq_update_nvm_exit;
3089 }
3090
3091 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3092
3093 /* If this is the last command in a series, set the proper flag. */
3094 if (last_command)
3095 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3096 cmd->module_pointer = module_pointer;
3097 cmd->offset = cpu_to_le32(offset);
3098 cmd->length = cpu_to_le16(length);
3099
3100 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3101 if (length > I40E_AQ_LARGE_BUF)
3102 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3103
3104 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3105
3106i40e_aq_update_nvm_exit:
3107 return status;
3108}
3109
56a62fc8
JB		 3110/**
3111 * i40e_aq_get_lldp_mib
3112 * @hw: pointer to the hw struct
3113 * @bridge_type: type of bridge requested
3114 * @mib_type: Local, Remote or both Local and Remote MIBs
3115 * @buff: pointer to a user supplied buffer to store the MIB block
3116 * @buff_size: size of the buffer (in bytes)
3117 * @local_len : length of the returned Local LLDP MIB
3118 * @remote_len: length of the returned Remote LLDP MIB
3119 * @cmd_details: pointer to command details structure or NULL
3120 *
3121 * Requests the complete LLDP MIB (entire packet).
3122 **/
3123i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3124 u8 mib_type, void *buff, u16 buff_size,
3125 u16 *local_len, u16 *remote_len,
3126 struct i40e_asq_cmd_details *cmd_details)
3127{
3128 struct i40e_aq_desc desc;
3129 struct i40e_aqc_lldp_get_mib *cmd =
3130 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3131 struct i40e_aqc_lldp_get_mib *resp =
3132 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3133 i40e_status status;
3134
3135 if (buff_size == 0 || !buff)
3136 return I40E_ERR_PARAM;
3137
3138 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3139 /* Indirect Command */
3140 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3141
3142 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3143 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3144 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3145
3146 desc.datalen = cpu_to_le16(buff_size);
3147
3148 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3149 if (buff_size > I40E_AQ_LARGE_BUF)
3150 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3151
3152 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3153 if (!status) {
3154 if (local_len != NULL)
3155 *local_len = le16_to_cpu(resp->local_len);
3156 if (remote_len != NULL)
3157 *remote_len = le16_to_cpu(resp->remote_len);
3158 }
3159
3160 return status;
3161}
3162
3163/**
3164 * i40e_aq_cfg_lldp_mib_change_event
3165 * @hw: pointer to the hw struct
3166 * @enable_update: Enable or Disable event posting
3167 * @cmd_details: pointer to command details structure or NULL
3168 *
3169 * Enable or Disable posting of an event on ARQ when LLDP MIB
3170 * associated with the interface changes
3171 **/
3172i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3173 bool enable_update,
3174 struct i40e_asq_cmd_details *cmd_details)
3175{
3176 struct i40e_aq_desc desc;
3177 struct i40e_aqc_lldp_update_mib *cmd =
3178 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3179 i40e_status status;
3180
3181 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3182
3183 if (!enable_update)
3184 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3185
3186 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3187
3188 return status;
3189}
3190
3191/**
3192 * i40e_aq_stop_lldp
3193 * @hw: pointer to the hw struct
3194 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3195 * @cmd_details: pointer to command details structure or NULL
3196 *
3197 * Stop or Shutdown the embedded LLDP Agent
3198 **/
3199i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3200 struct i40e_asq_cmd_details *cmd_details)
3201{
3202 struct i40e_aq_desc desc;
3203 struct i40e_aqc_lldp_stop *cmd =
3204 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3205 i40e_status status;
3206
3207 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3208
3209 if (shutdown_agent)
3210 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3211
3212 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3213
3214 return status;
3215}
3216
3217/**
3218 * i40e_aq_start_lldp
3219 * @hw: pointer to the hw struct
3220 * @cmd_details: pointer to command details structure or NULL
3221 *
3222 * Start the embedded LLDP Agent on all ports.
3223 **/
3224i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3225 struct i40e_asq_cmd_details *cmd_details)
3226{
3227 struct i40e_aq_desc desc;
3228 struct i40e_aqc_lldp_start *cmd =
3229 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3230 i40e_status status;
3231
3232 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3233
3234 cmd->command = I40E_AQ_LLDP_AGENT_START;
3235
3236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3237
3238 return status;
3239}
3240
9fa61dd2
NP		 3241/**
3242 * i40e_aq_get_cee_dcb_config
3243 * @hw: pointer to the hw struct
3244 * @buff: response buffer that stores CEE operational configuration
3245 * @buff_size: size of the buffer passed
3246 * @cmd_details: pointer to command details structure or NULL
3247 *
3248 * Get CEE DCBX mode operational configuration from firmware
3249 **/
3250i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3251 void *buff, u16 buff_size,
3252 struct i40e_asq_cmd_details *cmd_details)
3253{
3254 struct i40e_aq_desc desc;
3255 i40e_status status;
3256
3257 if (buff_size == 0 || !buff)
3258 return I40E_ERR_PARAM;
3259
3260 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3261
3262 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3263 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3264 cmd_details);
3265
3266 return status;
3267}
3268
a1c9a9d9
JK		 3269/**
3270 * i40e_aq_add_udp_tunnel
3271 * @hw: pointer to the hw struct
3272 * @udp_port: the UDP port to add
3273 * @header_len: length of the tunneling header length in DWords
3274 * @protocol_index: protocol index type
98d44381 3275 * @filter_index: pointer to filter index
a1c9a9d9
JK		 3276 * @cmd_details: pointer to command details structure or NULL
3277 **/
3278i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 3279 u16 udp_port, u8 protocol_index,
3280 u8 *filter_index,
a1c9a9d9
JK		 3281 struct i40e_asq_cmd_details *cmd_details)
3282{
3283 struct i40e_aq_desc desc;
3284 struct i40e_aqc_add_udp_tunnel *cmd =
3285 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3286 struct i40e_aqc_del_udp_tunnel_completion *resp =
3287 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3288 i40e_status status;
3289
3290 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3291
3292 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 3293 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 3294
3295 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3296
65d13461 3297 if (!status && filter_index)
a1c9a9d9
JK		 3298 *filter_index = resp->index;
3299
3300 return status;
3301}
3302
3303/**
3304 * i40e_aq_del_udp_tunnel
3305 * @hw: pointer to the hw struct
3306 * @index: filter index
3307 * @cmd_details: pointer to command details structure or NULL
3308 **/
3309i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3310 struct i40e_asq_cmd_details *cmd_details)
3311{
3312 struct i40e_aq_desc desc;
3313 struct i40e_aqc_remove_udp_tunnel *cmd =
3314 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3315 i40e_status status;
3316
3317 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3318
3319 cmd->index = index;
3320
3321 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3322
3323 return status;
3324}
3325
56a62fc8
JB		 3326/**
3327 * i40e_aq_delete_element - Delete switch element
3328 * @hw: pointer to the hw struct
3329 * @seid: the SEID to delete from the switch
3330 * @cmd_details: pointer to command details structure or NULL
3331 *
3332 * This deletes a switch element from the switch.
3333 **/
3334i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3335 struct i40e_asq_cmd_details *cmd_details)
3336{
3337 struct i40e_aq_desc desc;
3338 struct i40e_aqc_switch_seid *cmd =
3339 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3340 i40e_status status;
3341
3342 if (seid == 0)
3343 return I40E_ERR_PARAM;
3344
3345 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3346
3347 cmd->seid = cpu_to_le16(seid);
3348
3349 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3350
3351 return status;
3352}
3353
afb3ff0d
NP		 3354/**
3355 * i40e_aq_dcb_updated - DCB Updated Command
3356 * @hw: pointer to the hw struct
3357 * @cmd_details: pointer to command details structure or NULL
3358 *
3359 * EMP will return when the shared RPB settings have been
3360 * recomputed and modified. The retval field in the descriptor
3361 * will be set to 0 when RPB is modified.
3362 **/
3363i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3364 struct i40e_asq_cmd_details *cmd_details)
3365{
3366 struct i40e_aq_desc desc;
3367 i40e_status status;
3368
3369 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3370
3371 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3372
3373 return status;
3374}
3375
56a62fc8
JB		 3376/**
3377 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3378 * @hw: pointer to the hw struct
3379 * @seid: seid for the physical port/switching component/vsi
3380 * @buff: Indirect buffer to hold data parameters and response
3381 * @buff_size: Indirect buffer size
3382 * @opcode: Tx scheduler AQ command opcode
3383 * @cmd_details: pointer to command details structure or NULL
3384 *
3385 * Generic command handler for Tx scheduler AQ commands
3386 **/
3387static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3388 void *buff, u16 buff_size,
3389 enum i40e_admin_queue_opc opcode,
3390 struct i40e_asq_cmd_details *cmd_details)
3391{
3392 struct i40e_aq_desc desc;
3393 struct i40e_aqc_tx_sched_ind *cmd =
3394 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3395 i40e_status status;
3396 bool cmd_param_flag = false;
3397
3398 switch (opcode) {
3399 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3400 case i40e_aqc_opc_configure_vsi_tc_bw:
3401 case i40e_aqc_opc_enable_switching_comp_ets:
3402 case i40e_aqc_opc_modify_switching_comp_ets:
3403 case i40e_aqc_opc_disable_switching_comp_ets:
3404 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3405 case i40e_aqc_opc_configure_switching_comp_bw_config:
3406 cmd_param_flag = true;
3407 break;
3408 case i40e_aqc_opc_query_vsi_bw_config:
3409 case i40e_aqc_opc_query_vsi_ets_sla_config:
3410 case i40e_aqc_opc_query_switching_comp_ets_config:
3411 case i40e_aqc_opc_query_port_ets_config:
3412 case i40e_aqc_opc_query_switching_comp_bw_config:
3413 cmd_param_flag = false;
3414 break;
3415 default:
3416 return I40E_ERR_PARAM;
3417 }
3418
3419 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3420
3421 /* Indirect command */
3422 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3423 if (cmd_param_flag)
3424 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3425 if (buff_size > I40E_AQ_LARGE_BUF)
3426 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3427
3428 desc.datalen = cpu_to_le16(buff_size);
3429
3430 cmd->vsi_seid = cpu_to_le16(seid);
3431
3432 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3433
3434 return status;
3435}
3436
6b192891
MW		 3437/**
3438 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3439 * @hw: pointer to the hw struct
3440 * @seid: VSI seid
3441 * @credit: BW limit credits (0 = disabled)
3442 * @max_credit: Max BW limit credits
3443 * @cmd_details: pointer to command details structure or NULL
3444 **/
3445i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3446 u16 seid, u16 credit, u8 max_credit,
3447 struct i40e_asq_cmd_details *cmd_details)
3448{
3449 struct i40e_aq_desc desc;
3450 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3451 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3452 i40e_status status;
3453
3454 i40e_fill_default_direct_cmd_desc(&desc,
3455 i40e_aqc_opc_configure_vsi_bw_limit);
3456
3457 cmd->vsi_seid = cpu_to_le16(seid);
3458 cmd->credit = cpu_to_le16(credit);
3459 cmd->max_credit = max_credit;
3460
3461 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3462
3463 return status;
3464}
3465
56a62fc8
JB		 3466/**
3467 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3468 * @hw: pointer to the hw struct
3469 * @seid: VSI seid
3470 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3471 * @cmd_details: pointer to command details structure or NULL
3472 **/
3473i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3474 u16 seid,
3475 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3476 struct i40e_asq_cmd_details *cmd_details)
3477{
3478 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3479 i40e_aqc_opc_configure_vsi_tc_bw,
3480 cmd_details);
3481}
3482
afb3ff0d
NP		 3483/**
3484 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3485 * @hw: pointer to the hw struct
3486 * @seid: seid of the switching component connected to Physical Port
3487 * @ets_data: Buffer holding ETS parameters
3488 * @cmd_details: pointer to command details structure or NULL
3489 **/
3490i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3491 u16 seid,
3492 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3493 enum i40e_admin_queue_opc opcode,
3494 struct i40e_asq_cmd_details *cmd_details)
3495{
3496 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3497 sizeof(*ets_data), opcode, cmd_details);
3498}
3499
3500/**
3501 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3502 * @hw: pointer to the hw struct
3503 * @seid: seid of the switching component
3504 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3505 * @cmd_details: pointer to command details structure or NULL
3506 **/
3507i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3508 u16 seid,
3509 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3510 struct i40e_asq_cmd_details *cmd_details)
3511{
3512 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3513 i40e_aqc_opc_configure_switching_comp_bw_config,
3514 cmd_details);
3515}
3516
56a62fc8
JB		 3517/**
3518 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3519 * @hw: pointer to the hw struct
3520 * @seid: seid of the VSI
3521 * @bw_data: Buffer to hold VSI BW configuration
3522 * @cmd_details: pointer to command details structure or NULL
3523 **/
3524i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3525 u16 seid,
3526 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3527 struct i40e_asq_cmd_details *cmd_details)
3528{
3529 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3530 i40e_aqc_opc_query_vsi_bw_config,
3531 cmd_details);
3532}
3533
3534/**
3535 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3536 * @hw: pointer to the hw struct
3537 * @seid: seid of the VSI
3538 * @bw_data: Buffer to hold VSI BW configuration per TC
3539 * @cmd_details: pointer to command details structure or NULL
3540 **/
3541i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3542 u16 seid,
3543 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3544 struct i40e_asq_cmd_details *cmd_details)
3545{
3546 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3547 i40e_aqc_opc_query_vsi_ets_sla_config,
3548 cmd_details);
3549}
3550
3551/**
3552 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3553 * @hw: pointer to the hw struct
3554 * @seid: seid of the switching component
3555 * @bw_data: Buffer to hold switching component's per TC BW config
3556 * @cmd_details: pointer to command details structure or NULL
3557 **/
3558i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3559 u16 seid,
3560 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3561 struct i40e_asq_cmd_details *cmd_details)
3562{
3563 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3564 i40e_aqc_opc_query_switching_comp_ets_config,
3565 cmd_details);
3566}
3567
3568/**
3569 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3570 * @hw: pointer to the hw struct
3571 * @seid: seid of the VSI or switching component connected to Physical Port
3572 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3573 * @cmd_details: pointer to command details structure or NULL
3574 **/
3575i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3576 u16 seid,
3577 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3578 struct i40e_asq_cmd_details *cmd_details)
3579{
3580 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3581 i40e_aqc_opc_query_port_ets_config,
3582 cmd_details);
3583}
3584
3585/**
3586 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3587 * @hw: pointer to the hw struct
3588 * @seid: seid of the switching component
3589 * @bw_data: Buffer to hold switching component's BW configuration
3590 * @cmd_details: pointer to command details structure or NULL
3591 **/
3592i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3593 u16 seid,
3594 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3595 struct i40e_asq_cmd_details *cmd_details)
3596{
3597 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3598 i40e_aqc_opc_query_switching_comp_bw_config,
3599 cmd_details);
3600}
3601
3602/**
3603 * i40e_validate_filter_settings
3604 * @hw: pointer to the hardware structure
3605 * @settings: Filter control settings
3606 *
3607 * Check and validate the filter control settings passed.
3608 * The function checks for the valid filter/context sizes being
3609 * passed for FCoE and PE.
3610 *
3611 * Returns 0 if the values passed are valid and within
3612 * range else returns an error.
3613 **/
3614static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3615 struct i40e_filter_control_settings *settings)
3616{
3617 u32 fcoe_cntx_size, fcoe_filt_size;
3618 u32 pe_cntx_size, pe_filt_size;
467d729a 3619 u32 fcoe_fmax;
56a62fc8
JB		 3620 u32 val;
3621
3622 /* Validate FCoE settings passed */
3623 switch (settings->fcoe_filt_num) {
3624 case I40E_HASH_FILTER_SIZE_1K:
3625 case I40E_HASH_FILTER_SIZE_2K:
3626 case I40E_HASH_FILTER_SIZE_4K:
3627 case I40E_HASH_FILTER_SIZE_8K:
3628 case I40E_HASH_FILTER_SIZE_16K:
3629 case I40E_HASH_FILTER_SIZE_32K:
3630 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3631 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3632 break;
3633 default:
3634 return I40E_ERR_PARAM;
3635 }
3636
3637 switch (settings->fcoe_cntx_num) {
3638 case I40E_DMA_CNTX_SIZE_512:
3639 case I40E_DMA_CNTX_SIZE_1K:
3640 case I40E_DMA_CNTX_SIZE_2K:
3641 case I40E_DMA_CNTX_SIZE_4K:
3642 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3643 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3644 break;
3645 default:
3646 return I40E_ERR_PARAM;
3647 }
3648
3649 /* Validate PE settings passed */
3650 switch (settings->pe_filt_num) {
3651 case I40E_HASH_FILTER_SIZE_1K:
3652 case I40E_HASH_FILTER_SIZE_2K:
3653 case I40E_HASH_FILTER_SIZE_4K:
3654 case I40E_HASH_FILTER_SIZE_8K:
3655 case I40E_HASH_FILTER_SIZE_16K:
3656 case I40E_HASH_FILTER_SIZE_32K:
3657 case I40E_HASH_FILTER_SIZE_64K:
3658 case I40E_HASH_FILTER_SIZE_128K:
3659 case I40E_HASH_FILTER_SIZE_256K:
3660 case I40E_HASH_FILTER_SIZE_512K:
3661 case I40E_HASH_FILTER_SIZE_1M:
3662 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3663 pe_filt_size <<= (u32)settings->pe_filt_num;
3664 break;
3665 default:
3666 return I40E_ERR_PARAM;
3667 }
3668
3669 switch (settings->pe_cntx_num) {
3670 case I40E_DMA_CNTX_SIZE_512:
3671 case I40E_DMA_CNTX_SIZE_1K:
3672 case I40E_DMA_CNTX_SIZE_2K:
3673 case I40E_DMA_CNTX_SIZE_4K:
3674 case I40E_DMA_CNTX_SIZE_8K:
3675 case I40E_DMA_CNTX_SIZE_16K:
3676 case I40E_DMA_CNTX_SIZE_32K:
3677 case I40E_DMA_CNTX_SIZE_64K:
3678 case I40E_DMA_CNTX_SIZE_128K:
3679 case I40E_DMA_CNTX_SIZE_256K:
3680 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3681 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3682 break;
3683 default:
3684 return I40E_ERR_PARAM;
3685 }
3686
3687 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3688 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3689 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3690 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3691 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3692 return I40E_ERR_INVALID_SIZE;
3693
56a62fc8
JB		 3694 return 0;
3695}
3696
3697/**
3698 * i40e_set_filter_control
3699 * @hw: pointer to the hardware structure
3700 * @settings: Filter control settings
3701 *
3702 * Set the Queue Filters for PE/FCoE and enable filters required
3703 * for a single PF. It is expected that these settings are programmed
3704 * at the driver initialization time.
3705 **/
3706i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3707 struct i40e_filter_control_settings *settings)
3708{
3709 i40e_status ret = 0;
3710 u32 hash_lut_size = 0;
3711 u32 val;
3712
3713 if (!settings)
3714 return I40E_ERR_PARAM;
3715
3716 /* Validate the input settings */
3717 ret = i40e_validate_filter_settings(hw, settings);
3718 if (ret)
3719 return ret;
3720
3721 /* Read the PF Queue Filter control register */
3722 val = rd32(hw, I40E_PFQF_CTL_0);
3723
3724 /* Program required PE hash buckets for the PF */
3725 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3726 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3727 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3728 /* Program required PE contexts for the PF */
3729 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3730 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3731 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3732
3733 /* Program required FCoE hash buckets for the PF */
3734 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3735 val |= ((u32)settings->fcoe_filt_num <<
3736 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3737 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3738 /* Program required FCoE DDP contexts for the PF */
3739 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3740 val |= ((u32)settings->fcoe_cntx_num <<
3741 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3742 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3743
3744 /* Program Hash LUT size for the PF */
3745 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3746 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3747 hash_lut_size = 1;
3748 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3749 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3750
3751 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3752 if (settings->enable_fdir)
3753 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3754 if (settings->enable_ethtype)
3755 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3756 if (settings->enable_macvlan)
3757 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3758
3759 wr32(hw, I40E_PFQF_CTL_0, val);
3760
3761 return 0;
3762}
afb3ff0d
NP		 3763
3764/**
3765 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3766 * @hw: pointer to the hw struct
3767 * @mac_addr: MAC address to use in the filter
3768 * @ethtype: Ethertype to use in the filter
3769 * @flags: Flags that needs to be applied to the filter
3770 * @vsi_seid: seid of the control VSI
3771 * @queue: VSI queue number to send the packet to
3772 * @is_add: Add control packet filter if True else remove
3773 * @stats: Structure to hold information on control filter counts
3774 * @cmd_details: pointer to command details structure or NULL
3775 *
3776 * This command will Add or Remove control packet filter for a control VSI.
3777 * In return it will update the total number of perfect filter count in
3778 * the stats member.
3779 **/
3780i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3781 u8 *mac_addr, u16 ethtype, u16 flags,
3782 u16 vsi_seid, u16 queue, bool is_add,
3783 struct i40e_control_filter_stats *stats,
3784 struct i40e_asq_cmd_details *cmd_details)
3785{
3786 struct i40e_aq_desc desc;
3787 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3788 (struct i40e_aqc_add_remove_control_packet_filter *)
3789 &desc.params.raw;
3790 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3791 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3792 &desc.params.raw;
3793 i40e_status status;
3794
3795 if (vsi_seid == 0)
3796 return I40E_ERR_PARAM;
3797
3798 if (is_add) {
3799 i40e_fill_default_direct_cmd_desc(&desc,
3800 i40e_aqc_opc_add_control_packet_filter);
3801 cmd->queue = cpu_to_le16(queue);
3802 } else {
3803 i40e_fill_default_direct_cmd_desc(&desc,
3804 i40e_aqc_opc_remove_control_packet_filter);
3805 }
3806
3807 if (mac_addr)
6995b36c 3808 ether_addr_copy(cmd->mac, mac_addr);
afb3ff0d
NP		 3809
3810 cmd->etype = cpu_to_le16(ethtype);
3811 cmd->flags = cpu_to_le16(flags);
3812 cmd->seid = cpu_to_le16(vsi_seid);
3813
3814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3815
3816 if (!status && stats) {
3817 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3818 stats->etype_used = le16_to_cpu(resp->etype_used);
3819 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3820 stats->etype_free = le16_to_cpu(resp->etype_free);
3821 }
3822
3823 return status;
3824}
3825
f4492db1
GR		 3826/**
3827 * i40e_aq_alternate_read
3828 * @hw: pointer to the hardware structure
3829 * @reg_addr0: address of first dword to be read
3830 * @reg_val0: pointer for data read from 'reg_addr0'
3831 * @reg_addr1: address of second dword to be read
3832 * @reg_val1: pointer for data read from 'reg_addr1'
3833 *
3834 * Read one or two dwords from alternate structure. Fields are indicated
3835 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3836 * is not passed then only register at 'reg_addr0' is read.
3837 *
3838 **/
37a2973a
SN		 3839static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
3840 u32 reg_addr0, u32 *reg_val0,
3841 u32 reg_addr1, u32 *reg_val1)
f4492db1
GR		 3842{
3843 struct i40e_aq_desc desc;
3844 struct i40e_aqc_alternate_write *cmd_resp =
3845 (struct i40e_aqc_alternate_write *)&desc.params.raw;
3846 i40e_status status;
3847
3848 if (!reg_val0)
3849 return I40E_ERR_PARAM;
3850
3851 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
3852 cmd_resp->address0 = cpu_to_le32(reg_addr0);
3853 cmd_resp->address1 = cpu_to_le32(reg_addr1);
3854
3855 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3856
3857 if (!status) {
3858 *reg_val0 = le32_to_cpu(cmd_resp->data0);
3859
3860 if (reg_val1)
3861 *reg_val1 = le32_to_cpu(cmd_resp->data1);
3862 }
3863
3864 return status;
3865}
3866
2fd75f31
NP		 3867/**
3868 * i40e_aq_resume_port_tx
3869 * @hw: pointer to the hardware structure
3870 * @cmd_details: pointer to command details structure or NULL
3871 *
3872 * Resume port's Tx traffic
3873 **/
3874i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3875 struct i40e_asq_cmd_details *cmd_details)
3876{
3877 struct i40e_aq_desc desc;
3878 i40e_status status;
3879
3880 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3881
3882 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3883
3884 return status;
3885}
3886
d4dfb81a
CS		 3887/**
3888 * i40e_set_pci_config_data - store PCI bus info
3889 * @hw: pointer to hardware structure
3890 * @link_status: the link status word from PCI config space
3891 *
3892 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3893 **/
3894void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3895{
3896 hw->bus.type = i40e_bus_type_pci_express;
3897
3898 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3899 case PCI_EXP_LNKSTA_NLW_X1:
3900 hw->bus.width = i40e_bus_width_pcie_x1;
3901 break;
3902 case PCI_EXP_LNKSTA_NLW_X2:
3903 hw->bus.width = i40e_bus_width_pcie_x2;
3904 break;
3905 case PCI_EXP_LNKSTA_NLW_X4:
3906 hw->bus.width = i40e_bus_width_pcie_x4;
3907 break;
3908 case PCI_EXP_LNKSTA_NLW_X8:
3909 hw->bus.width = i40e_bus_width_pcie_x8;
3910 break;
3911 default:
3912 hw->bus.width = i40e_bus_width_unknown;
3913 break;
3914 }
3915
3916 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3917 case PCI_EXP_LNKSTA_CLS_2_5GB:
3918 hw->bus.speed = i40e_bus_speed_2500;
3919 break;
3920 case PCI_EXP_LNKSTA_CLS_5_0GB:
3921 hw->bus.speed = i40e_bus_speed_5000;
3922 break;
3923 case PCI_EXP_LNKSTA_CLS_8_0GB:
3924 hw->bus.speed = i40e_bus_speed_8000;
3925 break;
3926 default:
3927 hw->bus.speed = i40e_bus_speed_unknown;
3928 break;
3929 }
3930}
f4492db1 3931
3169c323
JB		 3932/**
3933 * i40e_aq_debug_dump
3934 * @hw: pointer to the hardware structure
3935 * @cluster_id: specific cluster to dump
3936 * @table_id: table id within cluster
3937 * @start_index: index of line in the block to read
3938 * @buff_size: dump buffer size
3939 * @buff: dump buffer
3940 * @ret_buff_size: actual buffer size returned
3941 * @ret_next_table: next block to read
3942 * @ret_next_index: next index to read
3943 *
3944 * Dump internal FW/HW data for debug purposes.
3945 *
3946 **/
3947i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
3948 u8 table_id, u32 start_index, u16 buff_size,
3949 void *buff, u16 *ret_buff_size,
3950 u8 *ret_next_table, u32 *ret_next_index,
3951 struct i40e_asq_cmd_details *cmd_details)
3952{
3953 struct i40e_aq_desc desc;
3954 struct i40e_aqc_debug_dump_internals *cmd =
3955 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3956 struct i40e_aqc_debug_dump_internals *resp =
3957 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3958 i40e_status status;
3959
3960 if (buff_size == 0 || !buff)
3961 return I40E_ERR_PARAM;
3962
3963 i40e_fill_default_direct_cmd_desc(&desc,
3964 i40e_aqc_opc_debug_dump_internals);
3965 /* Indirect Command */
3966 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3967 if (buff_size > I40E_AQ_LARGE_BUF)
3968 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3969
3970 cmd->cluster_id = cluster_id;
3971 cmd->table_id = table_id;
3972 cmd->idx = cpu_to_le32(start_index);
3973
3974 desc.datalen = cpu_to_le16(buff_size);
3975
3976 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3977 if (!status) {
3978 if (ret_buff_size)
3979 *ret_buff_size = le16_to_cpu(desc.datalen);
3980 if (ret_next_table)
3981 *ret_next_table = resp->table_id;
3982 if (ret_next_index)
3983 *ret_next_index = le32_to_cpu(resp->idx);
3984 }
3985
3986 return status;
3987}
3988
f4492db1
GR		 3989/**
3990 * i40e_read_bw_from_alt_ram
3991 * @hw: pointer to the hardware structure
3992 * @max_bw: pointer for max_bw read
3993 * @min_bw: pointer for min_bw read
3994 * @min_valid: pointer for bool that is true if min_bw is a valid value
3995 * @max_valid: pointer for bool that is true if max_bw is a valid value
3996 *
3997 * Read bw from the alternate ram for the given pf
3998 **/
3999i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4000 u32 *max_bw, u32 *min_bw,
4001 bool *min_valid, bool *max_valid)
4002{
4003 i40e_status status;
4004 u32 max_bw_addr, min_bw_addr;
4005
4006 /* Calculate the address of the min/max bw registers */
4007 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4008 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4009 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4010 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4011 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4012 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4013
4014 /* Read the bandwidths from alt ram */
4015 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4016 min_bw_addr, min_bw);
4017
4018 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4019 *min_valid = true;
4020 else
4021 *min_valid = false;
4022
4023 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4024 *max_valid = true;
4025 else
4026 *max_valid = false;
4027
4028 return status;
4029}
4030
4031/**
4032 * i40e_aq_configure_partition_bw
4033 * @hw: pointer to the hardware structure
4034 * @bw_data: Buffer holding valid pfs and bw limits
4035 * @cmd_details: pointer to command details
4036 *
4037 * Configure partitions guaranteed/max bw
4038 **/
4039i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4040 struct i40e_aqc_configure_partition_bw_data *bw_data,
4041 struct i40e_asq_cmd_details *cmd_details)
4042{
4043 i40e_status status;
4044 struct i40e_aq_desc desc;
4045 u16 bwd_size = sizeof(*bw_data);
4046
4047 i40e_fill_default_direct_cmd_desc(&desc,
4048 i40e_aqc_opc_configure_partition_bw);
4049
4050 /* Indirect command */
4051 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4052 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4053
4054 if (bwd_size > I40E_AQ_LARGE_BUF)
4055 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4056
4057 desc.datalen = cpu_to_le16(bwd_size);
4058
4059 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4060 cmd_details);
4061
4062 return status;
4063}
Linux kernel - Deliverables
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