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Merge branch 'sfp-infra'
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
67be6eb2 4 * Copyright(c) 2013 - 2016 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e 46 case I40E_DEV_ID_QEMU:
ab60085e
SN		 47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
ab60085e
SN		 49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
5960d33f 52 case I40E_DEV_ID_10G_BASE_T:
bc5166b9 53 case I40E_DEV_ID_10G_BASE_T4:
ae24b409 54 case I40E_DEV_ID_20G_KR2:
48a3b512 55 case I40E_DEV_ID_20G_KR2_A:
56a62fc8
JB		 56 hw->mac.type = I40E_MAC_XL710;
57 break;
35dae51d
ASJ		 58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
87e6c1d7
ASJ		 60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
d6bf58c2 63 case I40E_DEV_ID_SFP_I_X722:
bccf4744 64 case I40E_DEV_ID_QSFP_I_X722:
87e6c1d7
ASJ		 65 hw->mac.type = I40E_MAC_X722;
66 break;
56a62fc8
JB		 67 default:
68 hw->mac.type = I40E_MAC_GENERIC;
69 break;
70 }
71 } else {
72 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
73 }
74
75 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
76 hw->mac.type, status);
77 return status;
78}
79
f1c7e72e
SN		 80/**
81 * i40e_aq_str - convert AQ err code to a string
82 * @hw: pointer to the HW structure
83 * @aq_err: the AQ error code to convert
84 **/
4e68adfe 85const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
f1c7e72e
SN		 86{
87 switch (aq_err) {
88 case I40E_AQ_RC_OK:
89 return "OK";
90 case I40E_AQ_RC_EPERM:
91 return "I40E_AQ_RC_EPERM";
92 case I40E_AQ_RC_ENOENT:
93 return "I40E_AQ_RC_ENOENT";
94 case I40E_AQ_RC_ESRCH:
95 return "I40E_AQ_RC_ESRCH";
96 case I40E_AQ_RC_EINTR:
97 return "I40E_AQ_RC_EINTR";
98 case I40E_AQ_RC_EIO:
99 return "I40E_AQ_RC_EIO";
100 case I40E_AQ_RC_ENXIO:
101 return "I40E_AQ_RC_ENXIO";
102 case I40E_AQ_RC_E2BIG:
103 return "I40E_AQ_RC_E2BIG";
104 case I40E_AQ_RC_EAGAIN:
105 return "I40E_AQ_RC_EAGAIN";
106 case I40E_AQ_RC_ENOMEM:
107 return "I40E_AQ_RC_ENOMEM";
108 case I40E_AQ_RC_EACCES:
109 return "I40E_AQ_RC_EACCES";
110 case I40E_AQ_RC_EFAULT:
111 return "I40E_AQ_RC_EFAULT";
112 case I40E_AQ_RC_EBUSY:
113 return "I40E_AQ_RC_EBUSY";
114 case I40E_AQ_RC_EEXIST:
115 return "I40E_AQ_RC_EEXIST";
116 case I40E_AQ_RC_EINVAL:
117 return "I40E_AQ_RC_EINVAL";
118 case I40E_AQ_RC_ENOTTY:
119 return "I40E_AQ_RC_ENOTTY";
120 case I40E_AQ_RC_ENOSPC:
121 return "I40E_AQ_RC_ENOSPC";
122 case I40E_AQ_RC_ENOSYS:
123 return "I40E_AQ_RC_ENOSYS";
124 case I40E_AQ_RC_ERANGE:
125 return "I40E_AQ_RC_ERANGE";
126 case I40E_AQ_RC_EFLUSHED:
127 return "I40E_AQ_RC_EFLUSHED";
128 case I40E_AQ_RC_BAD_ADDR:
129 return "I40E_AQ_RC_BAD_ADDR";
130 case I40E_AQ_RC_EMODE:
131 return "I40E_AQ_RC_EMODE";
132 case I40E_AQ_RC_EFBIG:
133 return "I40E_AQ_RC_EFBIG";
134 }
135
136 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
137 return hw->err_str;
138}
139
140/**
141 * i40e_stat_str - convert status err code to a string
142 * @hw: pointer to the HW structure
143 * @stat_err: the status error code to convert
144 **/
4e68adfe 145const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
f1c7e72e
SN		 146{
147 switch (stat_err) {
148 case 0:
149 return "OK";
150 case I40E_ERR_NVM:
151 return "I40E_ERR_NVM";
152 case I40E_ERR_NVM_CHECKSUM:
153 return "I40E_ERR_NVM_CHECKSUM";
154 case I40E_ERR_PHY:
155 return "I40E_ERR_PHY";
156 case I40E_ERR_CONFIG:
157 return "I40E_ERR_CONFIG";
158 case I40E_ERR_PARAM:
159 return "I40E_ERR_PARAM";
160 case I40E_ERR_MAC_TYPE:
161 return "I40E_ERR_MAC_TYPE";
162 case I40E_ERR_UNKNOWN_PHY:
163 return "I40E_ERR_UNKNOWN_PHY";
164 case I40E_ERR_LINK_SETUP:
165 return "I40E_ERR_LINK_SETUP";
166 case I40E_ERR_ADAPTER_STOPPED:
167 return "I40E_ERR_ADAPTER_STOPPED";
168 case I40E_ERR_INVALID_MAC_ADDR:
169 return "I40E_ERR_INVALID_MAC_ADDR";
170 case I40E_ERR_DEVICE_NOT_SUPPORTED:
171 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
172 case I40E_ERR_MASTER_REQUESTS_PENDING:
173 return "I40E_ERR_MASTER_REQUESTS_PENDING";
174 case I40E_ERR_INVALID_LINK_SETTINGS:
175 return "I40E_ERR_INVALID_LINK_SETTINGS";
176 case I40E_ERR_AUTONEG_NOT_COMPLETE:
177 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
178 case I40E_ERR_RESET_FAILED:
179 return "I40E_ERR_RESET_FAILED";
180 case I40E_ERR_SWFW_SYNC:
181 return "I40E_ERR_SWFW_SYNC";
182 case I40E_ERR_NO_AVAILABLE_VSI:
183 return "I40E_ERR_NO_AVAILABLE_VSI";
184 case I40E_ERR_NO_MEMORY:
185 return "I40E_ERR_NO_MEMORY";
186 case I40E_ERR_BAD_PTR:
187 return "I40E_ERR_BAD_PTR";
188 case I40E_ERR_RING_FULL:
189 return "I40E_ERR_RING_FULL";
190 case I40E_ERR_INVALID_PD_ID:
191 return "I40E_ERR_INVALID_PD_ID";
192 case I40E_ERR_INVALID_QP_ID:
193 return "I40E_ERR_INVALID_QP_ID";
194 case I40E_ERR_INVALID_CQ_ID:
195 return "I40E_ERR_INVALID_CQ_ID";
196 case I40E_ERR_INVALID_CEQ_ID:
197 return "I40E_ERR_INVALID_CEQ_ID";
198 case I40E_ERR_INVALID_AEQ_ID:
199 return "I40E_ERR_INVALID_AEQ_ID";
200 case I40E_ERR_INVALID_SIZE:
201 return "I40E_ERR_INVALID_SIZE";
202 case I40E_ERR_INVALID_ARP_INDEX:
203 return "I40E_ERR_INVALID_ARP_INDEX";
204 case I40E_ERR_INVALID_FPM_FUNC_ID:
205 return "I40E_ERR_INVALID_FPM_FUNC_ID";
206 case I40E_ERR_QP_INVALID_MSG_SIZE:
207 return "I40E_ERR_QP_INVALID_MSG_SIZE";
208 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
209 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
210 case I40E_ERR_INVALID_FRAG_COUNT:
211 return "I40E_ERR_INVALID_FRAG_COUNT";
212 case I40E_ERR_QUEUE_EMPTY:
213 return "I40E_ERR_QUEUE_EMPTY";
214 case I40E_ERR_INVALID_ALIGNMENT:
215 return "I40E_ERR_INVALID_ALIGNMENT";
216 case I40E_ERR_FLUSHED_QUEUE:
217 return "I40E_ERR_FLUSHED_QUEUE";
218 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
219 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
220 case I40E_ERR_INVALID_IMM_DATA_SIZE:
221 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
222 case I40E_ERR_TIMEOUT:
223 return "I40E_ERR_TIMEOUT";
224 case I40E_ERR_OPCODE_MISMATCH:
225 return "I40E_ERR_OPCODE_MISMATCH";
226 case I40E_ERR_CQP_COMPL_ERROR:
227 return "I40E_ERR_CQP_COMPL_ERROR";
228 case I40E_ERR_INVALID_VF_ID:
229 return "I40E_ERR_INVALID_VF_ID";
230 case I40E_ERR_INVALID_HMCFN_ID:
231 return "I40E_ERR_INVALID_HMCFN_ID";
232 case I40E_ERR_BACKING_PAGE_ERROR:
233 return "I40E_ERR_BACKING_PAGE_ERROR";
234 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
235 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
236 case I40E_ERR_INVALID_PBLE_INDEX:
237 return "I40E_ERR_INVALID_PBLE_INDEX";
238 case I40E_ERR_INVALID_SD_INDEX:
239 return "I40E_ERR_INVALID_SD_INDEX";
240 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
241 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
242 case I40E_ERR_INVALID_SD_TYPE:
243 return "I40E_ERR_INVALID_SD_TYPE";
244 case I40E_ERR_MEMCPY_FAILED:
245 return "I40E_ERR_MEMCPY_FAILED";
246 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
247 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
248 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
249 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
250 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
251 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
252 case I40E_ERR_SRQ_ENABLED:
253 return "I40E_ERR_SRQ_ENABLED";
254 case I40E_ERR_ADMIN_QUEUE_ERROR:
255 return "I40E_ERR_ADMIN_QUEUE_ERROR";
256 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
257 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
258 case I40E_ERR_BUF_TOO_SHORT:
259 return "I40E_ERR_BUF_TOO_SHORT";
260 case I40E_ERR_ADMIN_QUEUE_FULL:
261 return "I40E_ERR_ADMIN_QUEUE_FULL";
262 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
263 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
264 case I40E_ERR_BAD_IWARP_CQE:
265 return "I40E_ERR_BAD_IWARP_CQE";
266 case I40E_ERR_NVM_BLANK_MODE:
267 return "I40E_ERR_NVM_BLANK_MODE";
268 case I40E_ERR_NOT_IMPLEMENTED:
269 return "I40E_ERR_NOT_IMPLEMENTED";
270 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
271 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
272 case I40E_ERR_DIAG_TEST_FAILED:
273 return "I40E_ERR_DIAG_TEST_FAILED";
274 case I40E_ERR_NOT_READY:
275 return "I40E_ERR_NOT_READY";
276 case I40E_NOT_SUPPORTED:
277 return "I40E_NOT_SUPPORTED";
278 case I40E_ERR_FIRMWARE_API_VERSION:
279 return "I40E_ERR_FIRMWARE_API_VERSION";
280 }
281
282 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
283 return hw->err_str;
284}
285
56a62fc8
JB		 286/**
287 * i40e_debug_aq
288 * @hw: debug mask related to admin queue
98d44381
JK		 289 * @mask: debug mask
290 * @desc: pointer to admin queue descriptor
56a62fc8 291 * @buffer: pointer to command buffer
f905dd62 292 * @buf_len: max length of buffer
56a62fc8
JB		 293 *
294 * Dumps debug log about adminq command with descriptor contents.
295 **/
296void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
f905dd62 297 void *buffer, u16 buf_len)
56a62fc8
JB		 298{
299 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
f905dd62 300 u16 len = le16_to_cpu(aq_desc->datalen);
37a2973a
SN		 301 u8 *buf = (u8 *)buffer;
302 u16 i = 0;
56a62fc8
JB		 303
304 if ((!(mask & hw->debug_mask)) || (desc == NULL))
305 return;
306
307 i40e_debug(hw, mask,
308 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
f1abd7db
PSJ		 309 le16_to_cpu(aq_desc->opcode),
310 le16_to_cpu(aq_desc->flags),
311 le16_to_cpu(aq_desc->datalen),
312 le16_to_cpu(aq_desc->retval));
56a62fc8 313 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 314 le32_to_cpu(aq_desc->cookie_high),
315 le32_to_cpu(aq_desc->cookie_low));
56a62fc8 316 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 317 le32_to_cpu(aq_desc->params.internal.param0),
318 le32_to_cpu(aq_desc->params.internal.param1));
56a62fc8 319 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 320 le32_to_cpu(aq_desc->params.external.addr_high),
321 le32_to_cpu(aq_desc->params.external.addr_low));
56a62fc8
JB		 322
323 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
56a62fc8 324 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
f905dd62
SN		 325 if (buf_len < len)
326 len = buf_len;
37a2973a
SN		 327 /* write the full 16-byte chunks */
328 for (i = 0; i < (len - 16); i += 16)
a3524e95 329 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
37a2973a 330 /* write whatever's left over without overrunning the buffer */
a3524e95
AS		 331 if (i < len)
332 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
333 i, len - i, buf + i);
56a62fc8
JB		 334 }
335}
336
e1860d8f
ASJ		 337/**
338 * i40e_check_asq_alive
339 * @hw: pointer to the hw struct
340 *
341 * Returns true if Queue is enabled else false.
342 **/
343bool i40e_check_asq_alive(struct i40e_hw *hw)
344{
8b833b4f
KS		 345 if (hw->aq.asq.len)
346 return !!(rd32(hw, hw->aq.asq.len) &
347 I40E_PF_ATQLEN_ATQENABLE_MASK);
348 else
349 return false;
e1860d8f
ASJ		 350}
351
352/**
353 * i40e_aq_queue_shutdown
354 * @hw: pointer to the hw struct
355 * @unloading: is the driver unloading itself
356 *
357 * Tell the Firmware that we're shutting down the AdminQ and whether
358 * or not the driver is unloading as well.
359 **/
360i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
361 bool unloading)
362{
363 struct i40e_aq_desc desc;
364 struct i40e_aqc_queue_shutdown *cmd =
365 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
366 i40e_status status;
367
368 i40e_fill_default_direct_cmd_desc(&desc,
369 i40e_aqc_opc_queue_shutdown);
370
371 if (unloading)
372 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
373 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
374
375 return status;
376}
377
e50c8d6d
ASJ		 378/**
379 * i40e_aq_get_set_rss_lut
380 * @hw: pointer to the hardware structure
381 * @vsi_id: vsi fw index
382 * @pf_lut: for PF table set true, for VSI table set false
383 * @lut: pointer to the lut buffer provided by the caller
384 * @lut_size: size of the lut buffer
385 * @set: set true to set the table, false to get the table
386 *
387 * Internal function to get or set RSS look up table
388 **/
389static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
390 u16 vsi_id, bool pf_lut,
391 u8 *lut, u16 lut_size,
392 bool set)
393{
394 i40e_status status;
395 struct i40e_aq_desc desc;
396 struct i40e_aqc_get_set_rss_lut *cmd_resp =
397 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
398
399 if (set)
400 i40e_fill_default_direct_cmd_desc(&desc,
401 i40e_aqc_opc_set_rss_lut);
402 else
403 i40e_fill_default_direct_cmd_desc(&desc,
404 i40e_aqc_opc_get_rss_lut);
405
406 /* Indirect command */
407 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
408 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
409
410 cmd_resp->vsi_id =
411 cpu_to_le16((u16)((vsi_id <<
412 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
413 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
414 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
415
416 if (pf_lut)
417 cmd_resp->flags |= cpu_to_le16((u16)
418 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
419 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
421 else
422 cmd_resp->flags |= cpu_to_le16((u16)
423 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
424 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
425 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
426
e50c8d6d
ASJ		 427 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
428
429 return status;
430}
431
432/**
433 * i40e_aq_get_rss_lut
434 * @hw: pointer to the hardware structure
435 * @vsi_id: vsi fw index
436 * @pf_lut: for PF table set true, for VSI table set false
437 * @lut: pointer to the lut buffer provided by the caller
438 * @lut_size: size of the lut buffer
439 *
440 * get the RSS lookup table, PF or VSI type
441 **/
442i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
443 bool pf_lut, u8 *lut, u16 lut_size)
444{
445 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
446 false);
447}
448
449/**
450 * i40e_aq_set_rss_lut
451 * @hw: pointer to the hardware structure
452 * @vsi_id: vsi fw index
453 * @pf_lut: for PF table set true, for VSI table set false
454 * @lut: pointer to the lut buffer provided by the caller
455 * @lut_size: size of the lut buffer
456 *
457 * set the RSS lookup table, PF or VSI type
458 **/
459i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
460 bool pf_lut, u8 *lut, u16 lut_size)
461{
462 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
463}
464
465/**
466 * i40e_aq_get_set_rss_key
467 * @hw: pointer to the hw struct
468 * @vsi_id: vsi fw index
469 * @key: pointer to key info struct
470 * @set: set true to set the key, false to get the key
471 *
472 * get the RSS key per VSI
473 **/
474static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
475 u16 vsi_id,
476 struct i40e_aqc_get_set_rss_key_data *key,
477 bool set)
478{
479 i40e_status status;
480 struct i40e_aq_desc desc;
481 struct i40e_aqc_get_set_rss_key *cmd_resp =
482 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
483 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
484
485 if (set)
486 i40e_fill_default_direct_cmd_desc(&desc,
487 i40e_aqc_opc_set_rss_key);
488 else
489 i40e_fill_default_direct_cmd_desc(&desc,
490 i40e_aqc_opc_get_rss_key);
491
492 /* Indirect command */
493 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
494 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
495
496 cmd_resp->vsi_id =
497 cpu_to_le16((u16)((vsi_id <<
498 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
499 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
500 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
e50c8d6d
ASJ		 501
502 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
503
504 return status;
505}
506
507/**
508 * i40e_aq_get_rss_key
509 * @hw: pointer to the hw struct
510 * @vsi_id: vsi fw index
511 * @key: pointer to key info struct
512 *
513 **/
514i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
515 u16 vsi_id,
516 struct i40e_aqc_get_set_rss_key_data *key)
517{
518 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
519}
520
521/**
522 * i40e_aq_set_rss_key
523 * @hw: pointer to the hw struct
524 * @vsi_id: vsi fw index
525 * @key: pointer to key info struct
526 *
527 * set the RSS key per VSI
528 **/
529i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
530 u16 vsi_id,
531 struct i40e_aqc_get_set_rss_key_data *key)
532{
533 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
534}
535
206812b5
JB		 536/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
537 * hardware to a bit-field that can be used by SW to more easily determine the
538 * packet type.
539 *
540 * Macros are used to shorten the table lines and make this table human
541 * readable.
542 *
543 * We store the PTYPE in the top byte of the bit field - this is just so that
544 * we can check that the table doesn't have a row missing, as the index into
545 * the table should be the PTYPE.
546 *
547 * Typical work flow:
548 *
549 * IF NOT i40e_ptype_lookup[ptype].known
550 * THEN
551 * Packet is unknown
552 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
553 * Use the rest of the fields to look at the tunnels, inner protocols, etc
554 * ELSE
555 * Use the enum i40e_rx_l2_ptype to decode the packet type
556 * ENDIF
557 */
558
559/* macro to make the table lines short */
560#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
561 { PTYPE, \
562 1, \
563 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
564 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
565 I40E_RX_PTYPE_##OUTER_FRAG, \
566 I40E_RX_PTYPE_TUNNEL_##T, \
567 I40E_RX_PTYPE_TUNNEL_END_##TE, \
568 I40E_RX_PTYPE_##TEF, \
569 I40E_RX_PTYPE_INNER_PROT_##I, \
570 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
571
572#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
573 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
574
575/* shorter macros makes the table fit but are terse */
576#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
577#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
578#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
579
580/* Lookup table mapping the HW PTYPE to the bit field for decoding */
581struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
582 /* L2 Packet types */
583 I40E_PTT_UNUSED_ENTRY(0),
584 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
586 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
587 I40E_PTT_UNUSED_ENTRY(4),
588 I40E_PTT_UNUSED_ENTRY(5),
589 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
590 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
591 I40E_PTT_UNUSED_ENTRY(8),
592 I40E_PTT_UNUSED_ENTRY(9),
593 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
594 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
595 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
605
606 /* Non Tunneled IPv4 */
607 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
608 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
609 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
610 I40E_PTT_UNUSED_ENTRY(25),
611 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
612 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
613 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
614
615 /* IPv4 --> IPv4 */
616 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
617 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
618 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
619 I40E_PTT_UNUSED_ENTRY(32),
620 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
621 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
622 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
623
624 /* IPv4 --> IPv6 */
625 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
626 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
627 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
628 I40E_PTT_UNUSED_ENTRY(39),
629 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
630 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
631 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
632
633 /* IPv4 --> GRE/NAT */
634 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
635
636 /* IPv4 --> GRE/NAT --> IPv4 */
637 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
638 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
639 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
640 I40E_PTT_UNUSED_ENTRY(47),
641 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
642 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
643 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
644
645 /* IPv4 --> GRE/NAT --> IPv6 */
646 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
647 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
648 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
649 I40E_PTT_UNUSED_ENTRY(54),
650 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
651 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
652 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
653
654 /* IPv4 --> GRE/NAT --> MAC */
655 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
656
657 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
658 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
659 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
660 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
661 I40E_PTT_UNUSED_ENTRY(62),
662 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
663 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
664 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
665
666 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
667 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
668 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
669 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
670 I40E_PTT_UNUSED_ENTRY(69),
671 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
672 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
673 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
674
675 /* IPv4 --> GRE/NAT --> MAC/VLAN */
676 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
677
678 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
679 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
680 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
681 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
682 I40E_PTT_UNUSED_ENTRY(77),
683 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
684 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
685 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
686
687 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
688 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
689 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
690 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
691 I40E_PTT_UNUSED_ENTRY(84),
692 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
693 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
694 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
695
696 /* Non Tunneled IPv6 */
697 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
698 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
73df8c9e 699 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
206812b5
JB		 700 I40E_PTT_UNUSED_ENTRY(91),
701 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
702 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
703 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
704
705 /* IPv6 --> IPv4 */
706 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
707 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
708 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
709 I40E_PTT_UNUSED_ENTRY(98),
710 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
711 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
712 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
713
714 /* IPv6 --> IPv6 */
715 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
716 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
717 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
718 I40E_PTT_UNUSED_ENTRY(105),
719 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
720 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
721 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
722
723 /* IPv6 --> GRE/NAT */
724 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
725
726 /* IPv6 --> GRE/NAT -> IPv4 */
727 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
728 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
729 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
730 I40E_PTT_UNUSED_ENTRY(113),
731 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
732 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
733 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
734
735 /* IPv6 --> GRE/NAT -> IPv6 */
736 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
737 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
738 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
739 I40E_PTT_UNUSED_ENTRY(120),
740 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
741 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
742 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
743
744 /* IPv6 --> GRE/NAT -> MAC */
745 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
746
747 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
748 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
749 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
750 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
751 I40E_PTT_UNUSED_ENTRY(128),
752 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
753 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
754 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
755
756 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
757 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
758 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
759 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
760 I40E_PTT_UNUSED_ENTRY(135),
761 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
762 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
763 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
764
765 /* IPv6 --> GRE/NAT -> MAC/VLAN */
766 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
767
768 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
769 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
770 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
771 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
772 I40E_PTT_UNUSED_ENTRY(143),
773 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
774 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
775 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
776
777 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
778 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
779 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
780 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
781 I40E_PTT_UNUSED_ENTRY(150),
782 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
783 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
784 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
785
786 /* unused entries */
787 I40E_PTT_UNUSED_ENTRY(154),
788 I40E_PTT_UNUSED_ENTRY(155),
789 I40E_PTT_UNUSED_ENTRY(156),
790 I40E_PTT_UNUSED_ENTRY(157),
791 I40E_PTT_UNUSED_ENTRY(158),
792 I40E_PTT_UNUSED_ENTRY(159),
793
794 I40E_PTT_UNUSED_ENTRY(160),
795 I40E_PTT_UNUSED_ENTRY(161),
796 I40E_PTT_UNUSED_ENTRY(162),
797 I40E_PTT_UNUSED_ENTRY(163),
798 I40E_PTT_UNUSED_ENTRY(164),
799 I40E_PTT_UNUSED_ENTRY(165),
800 I40E_PTT_UNUSED_ENTRY(166),
801 I40E_PTT_UNUSED_ENTRY(167),
802 I40E_PTT_UNUSED_ENTRY(168),
803 I40E_PTT_UNUSED_ENTRY(169),
804
805 I40E_PTT_UNUSED_ENTRY(170),
806 I40E_PTT_UNUSED_ENTRY(171),
807 I40E_PTT_UNUSED_ENTRY(172),
808 I40E_PTT_UNUSED_ENTRY(173),
809 I40E_PTT_UNUSED_ENTRY(174),
810 I40E_PTT_UNUSED_ENTRY(175),
811 I40E_PTT_UNUSED_ENTRY(176),
812 I40E_PTT_UNUSED_ENTRY(177),
813 I40E_PTT_UNUSED_ENTRY(178),
814 I40E_PTT_UNUSED_ENTRY(179),
815
816 I40E_PTT_UNUSED_ENTRY(180),
817 I40E_PTT_UNUSED_ENTRY(181),
818 I40E_PTT_UNUSED_ENTRY(182),
819 I40E_PTT_UNUSED_ENTRY(183),
820 I40E_PTT_UNUSED_ENTRY(184),
821 I40E_PTT_UNUSED_ENTRY(185),
822 I40E_PTT_UNUSED_ENTRY(186),
823 I40E_PTT_UNUSED_ENTRY(187),
824 I40E_PTT_UNUSED_ENTRY(188),
825 I40E_PTT_UNUSED_ENTRY(189),
826
827 I40E_PTT_UNUSED_ENTRY(190),
828 I40E_PTT_UNUSED_ENTRY(191),
829 I40E_PTT_UNUSED_ENTRY(192),
830 I40E_PTT_UNUSED_ENTRY(193),
831 I40E_PTT_UNUSED_ENTRY(194),
832 I40E_PTT_UNUSED_ENTRY(195),
833 I40E_PTT_UNUSED_ENTRY(196),
834 I40E_PTT_UNUSED_ENTRY(197),
835 I40E_PTT_UNUSED_ENTRY(198),
836 I40E_PTT_UNUSED_ENTRY(199),
837
838 I40E_PTT_UNUSED_ENTRY(200),
839 I40E_PTT_UNUSED_ENTRY(201),
840 I40E_PTT_UNUSED_ENTRY(202),
841 I40E_PTT_UNUSED_ENTRY(203),
842 I40E_PTT_UNUSED_ENTRY(204),
843 I40E_PTT_UNUSED_ENTRY(205),
844 I40E_PTT_UNUSED_ENTRY(206),
845 I40E_PTT_UNUSED_ENTRY(207),
846 I40E_PTT_UNUSED_ENTRY(208),
847 I40E_PTT_UNUSED_ENTRY(209),
848
849 I40E_PTT_UNUSED_ENTRY(210),
850 I40E_PTT_UNUSED_ENTRY(211),
851 I40E_PTT_UNUSED_ENTRY(212),
852 I40E_PTT_UNUSED_ENTRY(213),
853 I40E_PTT_UNUSED_ENTRY(214),
854 I40E_PTT_UNUSED_ENTRY(215),
855 I40E_PTT_UNUSED_ENTRY(216),
856 I40E_PTT_UNUSED_ENTRY(217),
857 I40E_PTT_UNUSED_ENTRY(218),
858 I40E_PTT_UNUSED_ENTRY(219),
859
860 I40E_PTT_UNUSED_ENTRY(220),
861 I40E_PTT_UNUSED_ENTRY(221),
862 I40E_PTT_UNUSED_ENTRY(222),
863 I40E_PTT_UNUSED_ENTRY(223),
864 I40E_PTT_UNUSED_ENTRY(224),
865 I40E_PTT_UNUSED_ENTRY(225),
866 I40E_PTT_UNUSED_ENTRY(226),
867 I40E_PTT_UNUSED_ENTRY(227),
868 I40E_PTT_UNUSED_ENTRY(228),
869 I40E_PTT_UNUSED_ENTRY(229),
870
871 I40E_PTT_UNUSED_ENTRY(230),
872 I40E_PTT_UNUSED_ENTRY(231),
873 I40E_PTT_UNUSED_ENTRY(232),
874 I40E_PTT_UNUSED_ENTRY(233),
875 I40E_PTT_UNUSED_ENTRY(234),
876 I40E_PTT_UNUSED_ENTRY(235),
877 I40E_PTT_UNUSED_ENTRY(236),
878 I40E_PTT_UNUSED_ENTRY(237),
879 I40E_PTT_UNUSED_ENTRY(238),
880 I40E_PTT_UNUSED_ENTRY(239),
881
882 I40E_PTT_UNUSED_ENTRY(240),
883 I40E_PTT_UNUSED_ENTRY(241),
884 I40E_PTT_UNUSED_ENTRY(242),
885 I40E_PTT_UNUSED_ENTRY(243),
886 I40E_PTT_UNUSED_ENTRY(244),
887 I40E_PTT_UNUSED_ENTRY(245),
888 I40E_PTT_UNUSED_ENTRY(246),
889 I40E_PTT_UNUSED_ENTRY(247),
890 I40E_PTT_UNUSED_ENTRY(248),
891 I40E_PTT_UNUSED_ENTRY(249),
892
893 I40E_PTT_UNUSED_ENTRY(250),
894 I40E_PTT_UNUSED_ENTRY(251),
895 I40E_PTT_UNUSED_ENTRY(252),
896 I40E_PTT_UNUSED_ENTRY(253),
897 I40E_PTT_UNUSED_ENTRY(254),
898 I40E_PTT_UNUSED_ENTRY(255)
899};
900
56a62fc8
JB		 901/**
902 * i40e_init_shared_code - Initialize the shared code
903 * @hw: pointer to hardware structure
904 *
905 * This assigns the MAC type and PHY code and inits the NVM.
906 * Does not touch the hardware. This function must be called prior to any
907 * other function in the shared code. The i40e_hw structure should be
908 * memset to 0 prior to calling this function. The following fields in
909 * hw structure should be filled in prior to calling this function:
910 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
911 * subsystem_vendor_id, and revision_id
912 **/
913i40e_status i40e_init_shared_code(struct i40e_hw *hw)
914{
915 i40e_status status = 0;
5fb11d76 916 u32 port, ari, func_rid;
56a62fc8 917
56a62fc8
JB		 918 i40e_set_mac_type(hw);
919
920 switch (hw->mac.type) {
921 case I40E_MAC_XL710:
87e6c1d7 922 case I40E_MAC_X722:
56a62fc8
JB		 923 break;
924 default:
925 return I40E_ERR_DEVICE_NOT_SUPPORTED;
56a62fc8
JB		 926 }
927
af89d26c
SN		 928 hw->phy.get_link_info = true;
929
5fb11d76
SN		 930 /* Determine port number and PF number*/
931 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
932 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
933 hw->port = (u8)port;
934 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
935 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
936 func_rid = rd32(hw, I40E_PF_FUNC_RID);
937 if (ari)
938 hw->pf_id = (u8)(func_rid & 0xff);
5f9116ac 939 else
5fb11d76 940 hw->pf_id = (u8)(func_rid & 0x7);
5f9116ac 941
07f89be8
AS		 942 if (hw->mac.type == I40E_MAC_X722)
943 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
944
56a62fc8
JB		 945 status = i40e_init_nvm(hw);
946 return status;
947}
948
949/**
950 * i40e_aq_mac_address_read - Retrieve the MAC addresses
951 * @hw: pointer to the hw struct
952 * @flags: a return indicator of what addresses were added to the addr store
953 * @addrs: the requestor's mac addr store
954 * @cmd_details: pointer to command details structure or NULL
955 **/
956static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
957 u16 *flags,
958 struct i40e_aqc_mac_address_read_data *addrs,
959 struct i40e_asq_cmd_details *cmd_details)
960{
961 struct i40e_aq_desc desc;
962 struct i40e_aqc_mac_address_read *cmd_data =
963 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
964 i40e_status status;
965
966 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
967 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
968
969 status = i40e_asq_send_command(hw, &desc, addrs,
970 sizeof(*addrs), cmd_details);
971 *flags = le16_to_cpu(cmd_data->command_flags);
972
973 return status;
974}
975
976/**
977 * i40e_aq_mac_address_write - Change the MAC addresses
978 * @hw: pointer to the hw struct
979 * @flags: indicates which MAC to be written
980 * @mac_addr: address to write
981 * @cmd_details: pointer to command details structure or NULL
982 **/
983i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
984 u16 flags, u8 *mac_addr,
985 struct i40e_asq_cmd_details *cmd_details)
986{
987 struct i40e_aq_desc desc;
988 struct i40e_aqc_mac_address_write *cmd_data =
989 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
990 i40e_status status;
991
992 i40e_fill_default_direct_cmd_desc(&desc,
993 i40e_aqc_opc_mac_address_write);
994 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 995 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
996 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
997 ((u32)mac_addr[3] << 16) |
998 ((u32)mac_addr[4] << 8) |
999 mac_addr[5]);
56a62fc8
JB		 1000
1001 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1002
1003 return status;
1004}
1005
1006/**
1007 * i40e_get_mac_addr - get MAC address
1008 * @hw: pointer to the HW structure
1009 * @mac_addr: pointer to MAC address
1010 *
1011 * Reads the adapter's MAC address from register
1012 **/
1013i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1014{
1015 struct i40e_aqc_mac_address_read_data addrs;
1016 i40e_status status;
1017 u16 flags = 0;
1018
1019 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1020
1021 if (flags & I40E_AQC_LAN_ADDR_VALID)
6995b36c 1022 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
56a62fc8
JB		 1023
1024 return status;
1025}
1026
1f224ad2
NP		 1027/**
1028 * i40e_get_port_mac_addr - get Port MAC address
1029 * @hw: pointer to the HW structure
1030 * @mac_addr: pointer to Port MAC address
1031 *
1032 * Reads the adapter's Port MAC address
1033 **/
1034i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1035{
1036 struct i40e_aqc_mac_address_read_data addrs;
1037 i40e_status status;
1038 u16 flags = 0;
1039
1040 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1041 if (status)
1042 return status;
1043
1044 if (flags & I40E_AQC_PORT_ADDR_VALID)
6995b36c 1045 ether_addr_copy(mac_addr, addrs.port_mac);
1f224ad2
NP		 1046 else
1047 status = I40E_ERR_INVALID_MAC_ADDR;
1048
1049 return status;
1050}
1051
351499ab
MJ		 1052/**
1053 * i40e_pre_tx_queue_cfg - pre tx queue configure
1054 * @hw: pointer to the HW structure
b40c82e6 1055 * @queue: target PF queue index
351499ab
MJ		 1056 * @enable: state change request
1057 *
1058 * Handles hw requirement to indicate intention to enable
1059 * or disable target queue.
1060 **/
1061void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1062{
dfb699f9 1063 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 1064 u32 reg_block = 0;
dfb699f9 1065 u32 reg_val;
351499ab 1066
24a768cf 1067 if (abs_queue_idx >= 128) {
351499ab 1068 reg_block = abs_queue_idx / 128;
24a768cf
CP		 1069 abs_queue_idx %= 128;
1070 }
351499ab
MJ		 1071
1072 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1073 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1074 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1075
1076 if (enable)
1077 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1078 else
1079 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1080
1081 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1082}
38e00438
VD		 1083#ifdef I40E_FCOE
1084
1085/**
1086 * i40e_get_san_mac_addr - get SAN MAC address
1087 * @hw: pointer to the HW structure
1088 * @mac_addr: pointer to SAN MAC address
1089 *
1090 * Reads the adapter's SAN MAC address from NVM
1091 **/
1092i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1093{
1094 struct i40e_aqc_mac_address_read_data addrs;
1095 i40e_status status;
1096 u16 flags = 0;
1097
1098 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1099 if (status)
1100 return status;
1101
1102 if (flags & I40E_AQC_SAN_ADDR_VALID)
6995b36c 1103 ether_addr_copy(mac_addr, addrs.pf_san_mac);
38e00438
VD		 1104 else
1105 status = I40E_ERR_INVALID_MAC_ADDR;
1106
1107 return status;
1108}
1109#endif
351499ab 1110
18f680c6
KK		 1111/**
1112 * i40e_read_pba_string - Reads part number string from EEPROM
1113 * @hw: pointer to hardware structure
1114 * @pba_num: stores the part number string from the EEPROM
1115 * @pba_num_size: part number string buffer length
1116 *
1117 * Reads the part number string from the EEPROM.
1118 **/
1119i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1120 u32 pba_num_size)
1121{
1122 i40e_status status = 0;
1123 u16 pba_word = 0;
1124 u16 pba_size = 0;
1125 u16 pba_ptr = 0;
1126 u16 i = 0;
1127
1128 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1129 if (status || (pba_word != 0xFAFA)) {
1130 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1131 return status;
1132 }
1133
1134 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1135 if (status) {
1136 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1137 return status;
1138 }
1139
1140 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1141 if (status) {
1142 hw_dbg(hw, "Failed to read PBA Block size.\n");
1143 return status;
1144 }
1145
1146 /* Subtract one to get PBA word count (PBA Size word is included in
1147 * total size)
1148 */
1149 pba_size--;
1150 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1151 hw_dbg(hw, "Buffer to small for PBA data.\n");
1152 return I40E_ERR_PARAM;
1153 }
1154
1155 for (i = 0; i < pba_size; i++) {
1156 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1157 if (status) {
1158 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1159 return status;
1160 }
1161
1162 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1163 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1164 }
1165 pba_num[(pba_size * 2)] = '\0';
1166
1167 return status;
1168}
1169
be405eb0
JB		 1170/**
1171 * i40e_get_media_type - Gets media type
1172 * @hw: pointer to the hardware structure
1173 **/
1174static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1175{
1176 enum i40e_media_type media;
1177
1178 switch (hw->phy.link_info.phy_type) {
1179 case I40E_PHY_TYPE_10GBASE_SR:
1180 case I40E_PHY_TYPE_10GBASE_LR:
124ed15b
CS		 1181 case I40E_PHY_TYPE_1000BASE_SX:
1182 case I40E_PHY_TYPE_1000BASE_LX:
be405eb0
JB		 1183 case I40E_PHY_TYPE_40GBASE_SR4:
1184 case I40E_PHY_TYPE_40GBASE_LR4:
1185 media = I40E_MEDIA_TYPE_FIBER;
1186 break;
1187 case I40E_PHY_TYPE_100BASE_TX:
1188 case I40E_PHY_TYPE_1000BASE_T:
1189 case I40E_PHY_TYPE_10GBASE_T:
1190 media = I40E_MEDIA_TYPE_BASET;
1191 break;
1192 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1193 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1194 case I40E_PHY_TYPE_10GBASE_CR1:
1195 case I40E_PHY_TYPE_40GBASE_CR4:
1196 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
180204c7
CS		 1197 case I40E_PHY_TYPE_40GBASE_AOC:
1198 case I40E_PHY_TYPE_10GBASE_AOC:
be405eb0
JB		 1199 media = I40E_MEDIA_TYPE_DA;
1200 break;
1201 case I40E_PHY_TYPE_1000BASE_KX:
1202 case I40E_PHY_TYPE_10GBASE_KX4:
1203 case I40E_PHY_TYPE_10GBASE_KR:
1204 case I40E_PHY_TYPE_40GBASE_KR4:
ae24b409 1205 case I40E_PHY_TYPE_20GBASE_KR2:
be405eb0
JB		 1206 media = I40E_MEDIA_TYPE_BACKPLANE;
1207 break;
1208 case I40E_PHY_TYPE_SGMII:
1209 case I40E_PHY_TYPE_XAUI:
1210 case I40E_PHY_TYPE_XFI:
1211 case I40E_PHY_TYPE_XLAUI:
1212 case I40E_PHY_TYPE_XLPPI:
1213 default:
1214 media = I40E_MEDIA_TYPE_UNKNOWN;
1215 break;
1216 }
1217
1218 return media;
1219}
1220
7134f9ce 1221#define I40E_PF_RESET_WAIT_COUNT_A0 200
8af580df 1222#define I40E_PF_RESET_WAIT_COUNT 200
56a62fc8
JB		 1223/**
1224 * i40e_pf_reset - Reset the PF
1225 * @hw: pointer to the hardware structure
1226 *
1227 * Assuming someone else has triggered a global reset,
1228 * assure the global reset is complete and then reset the PF
1229 **/
1230i40e_status i40e_pf_reset(struct i40e_hw *hw)
1231{
7134f9ce 1232 u32 cnt = 0;
42794bd8 1233 u32 cnt1 = 0;
56a62fc8
JB		 1234 u32 reg = 0;
1235 u32 grst_del;
1236
1237 /* Poll for Global Reset steady state in case of recent GRST.
1238 * The grst delay value is in 100ms units, and we'll wait a
1239 * couple counts longer to be sure we don't just miss the end.
1240 */
de78fc5a
SN		 1241 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1242 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1243 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
4d7cec07
KS		 1244
1245 /* It can take upto 15 secs for GRST steady state.
1246 * Bump it to 16 secs max to be safe.
1247 */
1248 grst_del = grst_del * 20;
1249
1250 for (cnt = 0; cnt < grst_del; cnt++) {
56a62fc8
JB		 1251 reg = rd32(hw, I40E_GLGEN_RSTAT);
1252 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1253 break;
1254 msleep(100);
1255 }
1256 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1257 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 1258 return I40E_ERR_RESET_FAILED;
1259 }
1260
1261 /* Now Wait for the FW to be ready */
1262 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1263 reg = rd32(hw, I40E_GLNVM_ULD);
1264 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1265 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1266 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1267 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1268 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1269 break;
1270 }
1271 usleep_range(10000, 20000);
1272 }
1273 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1274 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1275 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1276 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 1277 return I40E_ERR_RESET_FAILED;
1278 }
1279
56a62fc8
JB		 1280 /* If there was a Global Reset in progress when we got here,
1281 * we don't need to do the PF Reset
1282 */
7134f9ce
JB		 1283 if (!cnt) {
1284 if (hw->revision_id == 0)
1285 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1286 else
1287 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 1288 reg = rd32(hw, I40E_PFGEN_CTRL);
1289 wr32(hw, I40E_PFGEN_CTRL,
1290 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 1291 for (; cnt; cnt--) {
56a62fc8
JB		 1292 reg = rd32(hw, I40E_PFGEN_CTRL);
1293 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1294 break;
1295 usleep_range(1000, 2000);
1296 }
1297 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1298 hw_dbg(hw, "PF reset polling failed to complete.\n");
1299 return I40E_ERR_RESET_FAILED;
1300 }
1301 }
1302
1303 i40e_clear_pxe_mode(hw);
922680b9 1304
56a62fc8
JB		 1305 return 0;
1306}
1307
838d41d9
SN		 1308/**
1309 * i40e_clear_hw - clear out any left over hw state
1310 * @hw: pointer to the hw struct
1311 *
1312 * Clear queues and interrupts, typically called at init time,
1313 * but after the capabilities have been found so we know how many
1314 * queues and msix vectors have been allocated.
1315 **/
1316void i40e_clear_hw(struct i40e_hw *hw)
1317{
1318 u32 num_queues, base_queue;
1319 u32 num_pf_int;
1320 u32 num_vf_int;
1321 u32 num_vfs;
1322 u32 i, j;
1323 u32 val;
1324 u32 eol = 0x7ff;
1325
b40c82e6 1326 /* get number of interrupts, queues, and VFs */
838d41d9
SN		 1327 val = rd32(hw, I40E_GLPCI_CNF2);
1328 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1329 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1330 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1331 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1332
272cdaf2 1333 val = rd32(hw, I40E_PFLAN_QALLOC);
838d41d9
SN		 1334 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1335 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1336 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1337 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1338 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1339 num_queues = (j - base_queue) + 1;
1340 else
1341 num_queues = 0;
1342
1343 val = rd32(hw, I40E_PF_VT_PFALLOC);
1344 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1345 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1346 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1347 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1348 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1349 num_vfs = (j - i) + 1;
1350 else
1351 num_vfs = 0;
1352
1353 /* stop all the interrupts */
1354 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1355 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1356 for (i = 0; i < num_pf_int - 2; i++)
1357 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1358
1359 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1360 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1361 wr32(hw, I40E_PFINT_LNKLST0, val);
1362 for (i = 0; i < num_pf_int - 2; i++)
1363 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1364 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1365 for (i = 0; i < num_vfs; i++)
1366 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1367 for (i = 0; i < num_vf_int - 2; i++)
1368 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1369
1370 /* warn the HW of the coming Tx disables */
1371 for (i = 0; i < num_queues; i++) {
1372 u32 abs_queue_idx = base_queue + i;
1373 u32 reg_block = 0;
1374
1375 if (abs_queue_idx >= 128) {
1376 reg_block = abs_queue_idx / 128;
1377 abs_queue_idx %= 128;
1378 }
1379
1380 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1381 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1382 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1383 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1384
1385 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1386 }
1387 udelay(400);
1388
1389 /* stop all the queues */
1390 for (i = 0; i < num_queues; i++) {
1391 wr32(hw, I40E_QINT_TQCTL(i), 0);
1392 wr32(hw, I40E_QTX_ENA(i), 0);
1393 wr32(hw, I40E_QINT_RQCTL(i), 0);
1394 wr32(hw, I40E_QRX_ENA(i), 0);
1395 }
1396
1397 /* short wait for all queue disables to settle */
1398 udelay(50);
1399}
1400
56a62fc8
JB		 1401/**
1402 * i40e_clear_pxe_mode - clear pxe operations mode
1403 * @hw: pointer to the hw struct
1404 *
1405 * Make sure all PXE mode settings are cleared, including things
1406 * like descriptor fetch/write-back mode.
1407 **/
1408void i40e_clear_pxe_mode(struct i40e_hw *hw)
1409{
1410 u32 reg;
1411
c9b9b0ae
SN		 1412 if (i40e_check_asq_alive(hw))
1413 i40e_aq_clear_pxe_mode(hw, NULL);
1414
56a62fc8
JB		 1415 /* Clear single descriptor fetch/write-back mode */
1416 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 1417
1418 if (hw->revision_id == 0) {
1419 /* As a work around clear PXE_MODE instead of setting it */
1420 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1421 } else {
1422 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1423 }
56a62fc8
JB		 1424}
1425
0556a9e3
JB		 1426/**
1427 * i40e_led_is_mine - helper to find matching led
1428 * @hw: pointer to the hw struct
1429 * @idx: index into GPIO registers
1430 *
1431 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1432 */
1433static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1434{
1435 u32 gpio_val = 0;
1436 u32 port;
1437
1438 if (!hw->func_caps.led[idx])
1439 return 0;
1440
1441 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1442 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1443 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1444
1445 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1446 * if it is not our port then ignore
1447 */
1448 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1449 (port != hw->port))
1450 return 0;
1451
1452 return gpio_val;
1453}
1454
b84d5cd8
MJ		 1455#define I40E_COMBINED_ACTIVITY 0xA
1456#define I40E_FILTER_ACTIVITY 0xE
0556a9e3 1457#define I40E_LINK_ACTIVITY 0xC
b84d5cd8
MJ		 1458#define I40E_MAC_ACTIVITY 0xD
1459#define I40E_LED0 22
0556a9e3 1460
56a62fc8
JB		 1461/**
1462 * i40e_led_get - return current on/off mode
1463 * @hw: pointer to the hw struct
1464 *
1465 * The value returned is the 'mode' field as defined in the
1466 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1467 * values are variations of possible behaviors relating to
1468 * blink, link, and wire.
1469 **/
1470u32 i40e_led_get(struct i40e_hw *hw)
1471{
b84d5cd8 1472 u32 current_mode = 0;
56a62fc8 1473 u32 mode = 0;
56a62fc8
JB		 1474 int i;
1475
0556a9e3
JB		 1476 /* as per the documentation GPIO 22-29 are the LED
1477 * GPIO pins named LED0..LED7
1478 */
1479 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1480 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1481
0556a9e3 1482 if (!gpio_val)
56a62fc8
JB		 1483 continue;
1484
b84d5cd8
MJ		 1485 /* ignore gpio LED src mode entries related to the activity
1486 * LEDs
1487 */
1488 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1489 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1490 switch (current_mode) {
1491 case I40E_COMBINED_ACTIVITY:
1492 case I40E_FILTER_ACTIVITY:
1493 case I40E_MAC_ACTIVITY:
1494 continue;
1495 default:
1496 break;
1497 }
1498
0556a9e3
JB		 1499 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1500 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 1501 break;
1502 }
1503
1504 return mode;
1505}
1506
1507/**
1508 * i40e_led_set - set new on/off mode
1509 * @hw: pointer to the hw struct
0556a9e3
JB		 1510 * @mode: 0=off, 0xf=on (else see manual for mode details)
1511 * @blink: true if the LED should blink when on, false if steady
1512 *
1513 * if this function is used to turn on the blink it should
1514 * be used to disable the blink when restoring the original state.
56a62fc8 1515 **/
0556a9e3 1516void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1517{
b84d5cd8 1518 u32 current_mode = 0;
56a62fc8
JB		 1519 int i;
1520
0556a9e3
JB		 1521 if (mode & 0xfffffff0)
1522 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1523
0556a9e3
JB		 1524 /* as per the documentation GPIO 22-29 are the LED
1525 * GPIO pins named LED0..LED7
1526 */
1527 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1528 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1529
0556a9e3 1530 if (!gpio_val)
56a62fc8
JB		 1531 continue;
1532
b84d5cd8
MJ		 1533 /* ignore gpio LED src mode entries related to the activity
1534 * LEDs
1535 */
1536 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1537 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1538 switch (current_mode) {
1539 case I40E_COMBINED_ACTIVITY:
1540 case I40E_FILTER_ACTIVITY:
1541 case I40E_MAC_ACTIVITY:
1542 continue;
1543 default:
1544 break;
1545 }
1546
56a62fc8 1547 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1548 /* this & is a bit of paranoia, but serves as a range check */
1549 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1550 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1551
1552 if (mode == I40E_LINK_ACTIVITY)
1553 blink = false;
1554
9be00d67 1555 if (blink)
41a1d04b 1556 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
9be00d67 1557 else
41a1d04b 1558 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
0556a9e3 1559
56a62fc8 1560 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1561 break;
56a62fc8
JB		 1562 }
1563}
1564
1565/* Admin command wrappers */
56a62fc8 1566
8109e123
CS		 1567/**
1568 * i40e_aq_get_phy_capabilities
1569 * @hw: pointer to the hw struct
1570 * @abilities: structure for PHY capabilities to be filled
1571 * @qualified_modules: report Qualified Modules
1572 * @report_init: report init capabilities (active are default)
1573 * @cmd_details: pointer to command details structure or NULL
1574 *
1575 * Returns the various PHY abilities supported on the Port.
1576 **/
1577i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1578 bool qualified_modules, bool report_init,
1579 struct i40e_aq_get_phy_abilities_resp *abilities,
1580 struct i40e_asq_cmd_details *cmd_details)
1581{
1582 struct i40e_aq_desc desc;
1583 i40e_status status;
1584 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1585
1586 if (!abilities)
1587 return I40E_ERR_PARAM;
1588
1589 i40e_fill_default_direct_cmd_desc(&desc,
1590 i40e_aqc_opc_get_phy_abilities);
1591
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1593 if (abilities_size > I40E_AQ_LARGE_BUF)
1594 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1595
1596 if (qualified_modules)
1597 desc.params.external.param0 |=
1598 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1599
1600 if (report_init)
1601 desc.params.external.param0 |=
1602 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1603
1604 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1605 cmd_details);
1606
1607 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1608 status = I40E_ERR_UNKNOWN_PHY;
1609
3ac67d7b
KS		 1610 if (report_init)
1611 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1612
8109e123
CS		 1613 return status;
1614}
1615
c56999f9
CS		 1616/**
1617 * i40e_aq_set_phy_config
1618 * @hw: pointer to the hw struct
1619 * @config: structure with PHY configuration to be set
1620 * @cmd_details: pointer to command details structure or NULL
1621 *
1622 * Set the various PHY configuration parameters
1623 * supported on the Port.One or more of the Set PHY config parameters may be
1624 * ignored in an MFP mode as the PF may not have the privilege to set some
1625 * of the PHY Config parameters. This status will be indicated by the
1626 * command response.
1627 **/
1628enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1629 struct i40e_aq_set_phy_config *config,
1630 struct i40e_asq_cmd_details *cmd_details)
1631{
1632 struct i40e_aq_desc desc;
1633 struct i40e_aq_set_phy_config *cmd =
1634 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1635 enum i40e_status_code status;
1636
1637 if (!config)
1638 return I40E_ERR_PARAM;
1639
1640 i40e_fill_default_direct_cmd_desc(&desc,
1641 i40e_aqc_opc_set_phy_config);
1642
1643 *cmd = *config;
1644
1645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1646
1647 return status;
1648}
1649
1650/**
1651 * i40e_set_fc
1652 * @hw: pointer to the hw struct
1653 *
1654 * Set the requested flow control mode using set_phy_config.
1655 **/
1656enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1657 bool atomic_restart)
1658{
1659 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1660 struct i40e_aq_get_phy_abilities_resp abilities;
1661 struct i40e_aq_set_phy_config config;
1662 enum i40e_status_code status;
1663 u8 pause_mask = 0x0;
1664
1665 *aq_failures = 0x0;
1666
1667 switch (fc_mode) {
1668 case I40E_FC_FULL:
1669 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1670 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1671 break;
1672 case I40E_FC_RX_PAUSE:
1673 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1674 break;
1675 case I40E_FC_TX_PAUSE:
1676 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1677 break;
1678 default:
1679 break;
1680 }
1681
1682 /* Get the current phy config */
1683 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1684 NULL);
1685 if (status) {
1686 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1687 return status;
1688 }
1689
1690 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1691 /* clear the old pause settings */
1692 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1693 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1694 /* set the new abilities */
1695 config.abilities |= pause_mask;
1696 /* If the abilities have changed, then set the new config */
1697 if (config.abilities != abilities.abilities) {
1698 /* Auto restart link so settings take effect */
1699 if (atomic_restart)
1700 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1701 /* Copy over all the old settings */
1702 config.phy_type = abilities.phy_type;
1703 config.link_speed = abilities.link_speed;
1704 config.eee_capability = abilities.eee_capability;
1705 config.eeer = abilities.eeer_val;
1706 config.low_power_ctrl = abilities.d3_lpan;
1707 status = i40e_aq_set_phy_config(hw, &config, NULL);
1708
1709 if (status)
1710 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1711 }
1712 /* Update the link info */
0a862b43 1713 status = i40e_update_link_info(hw);
c56999f9
CS		 1714 if (status) {
1715 /* Wait a little bit (on 40G cards it sometimes takes a really
1716 * long time for link to come back from the atomic reset)
1717 * and try once more
1718 */
1719 msleep(1000);
0a862b43 1720 status = i40e_update_link_info(hw);
c56999f9
CS		 1721 }
1722 if (status)
1723 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1724
1725 return status;
1726}
1727
c9b9b0ae
SN		 1728/**
1729 * i40e_aq_clear_pxe_mode
1730 * @hw: pointer to the hw struct
1731 * @cmd_details: pointer to command details structure or NULL
1732 *
1733 * Tell the firmware that the driver is taking over from PXE
1734 **/
1735i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1736 struct i40e_asq_cmd_details *cmd_details)
1737{
1738 i40e_status status;
1739 struct i40e_aq_desc desc;
1740 struct i40e_aqc_clear_pxe *cmd =
1741 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1742
1743 i40e_fill_default_direct_cmd_desc(&desc,
1744 i40e_aqc_opc_clear_pxe_mode);
1745
1746 cmd->rx_cnt = 0x2;
1747
1748 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1749
1750 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1751
1752 return status;
1753}
1754
56a62fc8
JB		 1755/**
1756 * i40e_aq_set_link_restart_an
1757 * @hw: pointer to the hw struct
1ac978af 1758 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1759 * @cmd_details: pointer to command details structure or NULL
1760 *
1761 * Sets up the link and restarts the Auto-Negotiation over the link.
1762 **/
1763i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1764 bool enable_link,
1765 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1766{
1767 struct i40e_aq_desc desc;
1768 struct i40e_aqc_set_link_restart_an *cmd =
1769 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1770 i40e_status status;
1771
1772 i40e_fill_default_direct_cmd_desc(&desc,
1773 i40e_aqc_opc_set_link_restart_an);
1774
1775 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1776 if (enable_link)
1777 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1778 else
1779 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1780
1781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1782
1783 return status;
1784}
1785
1786/**
1787 * i40e_aq_get_link_info
1788 * @hw: pointer to the hw struct
1789 * @enable_lse: enable/disable LinkStatusEvent reporting
1790 * @link: pointer to link status structure - optional
1791 * @cmd_details: pointer to command details structure or NULL
1792 *
1793 * Returns the link status of the adapter.
1794 **/
1795i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1796 bool enable_lse, struct i40e_link_status *link,
1797 struct i40e_asq_cmd_details *cmd_details)
1798{
1799 struct i40e_aq_desc desc;
1800 struct i40e_aqc_get_link_status *resp =
1801 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1802 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1803 i40e_status status;
c56999f9 1804 bool tx_pause, rx_pause;
56a62fc8
JB		 1805 u16 command_flags;
1806
1807 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1808
1809 if (enable_lse)
1810 command_flags = I40E_AQ_LSE_ENABLE;
1811 else
1812 command_flags = I40E_AQ_LSE_DISABLE;
1813 resp->command_flags = cpu_to_le16(command_flags);
1814
1815 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1816
1817 if (status)
1818 goto aq_get_link_info_exit;
1819
1820 /* save off old link status information */
c36bd4a7 1821 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1822
1823 /* update link status */
1824 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1825 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1826 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1827 hw_link_info->link_info = resp->link_info;
1828 hw_link_info->an_info = resp->an_info;
1829 hw_link_info->ext_info = resp->ext_info;
639dc377 1830 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1831 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1832 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1833
c56999f9
CS		 1834 /* update fc info */
1835 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1836 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1837 if (tx_pause & rx_pause)
1838 hw->fc.current_mode = I40E_FC_FULL;
1839 else if (tx_pause)
1840 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1841 else if (rx_pause)
1842 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1843 else
1844 hw->fc.current_mode = I40E_FC_NONE;
1845
6bb3f23c
NP		 1846 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1847 hw_link_info->crc_enable = true;
1848 else
1849 hw_link_info->crc_enable = false;
56a62fc8
JB		 1850
1851 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1852 hw_link_info->lse_enable = true;
1853 else
1854 hw_link_info->lse_enable = false;
1855
088c4ee3
CS		 1856 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1857 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1858 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1859
56a62fc8
JB		 1860 /* save link status information */
1861 if (link)
d7595a22 1862 *link = *hw_link_info;
56a62fc8
JB		 1863
1864 /* flag cleared so helper functions don't call AQ again */
1865 hw->phy.get_link_info = false;
1866
1867aq_get_link_info_exit:
1868 return status;
1869}
1870
7e2453fe
JB		 1871/**
1872 * i40e_aq_set_phy_int_mask
1873 * @hw: pointer to the hw struct
1874 * @mask: interrupt mask to be set
1875 * @cmd_details: pointer to command details structure or NULL
1876 *
1877 * Set link interrupt mask.
1878 **/
1879i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1880 u16 mask,
1881 struct i40e_asq_cmd_details *cmd_details)
1882{
1883 struct i40e_aq_desc desc;
1884 struct i40e_aqc_set_phy_int_mask *cmd =
1885 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1886 i40e_status status;
1887
1888 i40e_fill_default_direct_cmd_desc(&desc,
1889 i40e_aqc_opc_set_phy_int_mask);
1890
1891 cmd->event_mask = cpu_to_le16(mask);
1892
1893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1894
1895 return status;
1896}
1897
31b606d0
CW		 1898/**
1899 * i40e_aq_set_phy_debug
1900 * @hw: pointer to the hw struct
1901 * @cmd_flags: debug command flags
1902 * @cmd_details: pointer to command details structure or NULL
1903 *
1904 * Reset the external PHY.
1905 **/
61829026
JB		 1906i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1907 struct i40e_asq_cmd_details *cmd_details)
31b606d0
CW		 1908{
1909 struct i40e_aq_desc desc;
1910 struct i40e_aqc_set_phy_debug *cmd =
1911 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
61829026 1912 i40e_status status;
31b606d0
CW		 1913
1914 i40e_fill_default_direct_cmd_desc(&desc,
1915 i40e_aqc_opc_set_phy_debug);
1916
1917 cmd->command_flags = cmd_flags;
1918
1919 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1920
1921 return status;
1922}
1923
56a62fc8
JB		 1924/**
1925 * i40e_aq_add_vsi
1926 * @hw: pointer to the hw struct
98d44381 1927 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1928 * @cmd_details: pointer to command details structure or NULL
1929 *
1930 * Add a VSI context to the hardware.
1931**/
1932i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1933 struct i40e_vsi_context *vsi_ctx,
1934 struct i40e_asq_cmd_details *cmd_details)
1935{
1936 struct i40e_aq_desc desc;
1937 struct i40e_aqc_add_get_update_vsi *cmd =
1938 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1939 struct i40e_aqc_add_get_update_vsi_completion *resp =
1940 (struct i40e_aqc_add_get_update_vsi_completion *)
1941 &desc.params.raw;
1942 i40e_status status;
1943
1944 i40e_fill_default_direct_cmd_desc(&desc,
1945 i40e_aqc_opc_add_vsi);
1946
1947 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1948 cmd->connection_type = vsi_ctx->connection_type;
1949 cmd->vf_id = vsi_ctx->vf_num;
1950 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1951
1952 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1953
1954 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1955 sizeof(vsi_ctx->info), cmd_details);
1956
1957 if (status)
1958 goto aq_add_vsi_exit;
1959
1960 vsi_ctx->seid = le16_to_cpu(resp->seid);
1961 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1962 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1963 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1964
1965aq_add_vsi_exit:
1966 return status;
1967}
1968
1969/**
1970 * i40e_aq_set_vsi_unicast_promiscuous
1971 * @hw: pointer to the hw struct
1972 * @seid: vsi number
1973 * @set: set unicast promiscuous enable/disable
1974 * @cmd_details: pointer to command details structure or NULL
b5569892 1975 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
56a62fc8
JB		 1976 **/
1977i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2 1978 u16 seid, bool set,
b5569892
ASJ		 1979 struct i40e_asq_cmd_details *cmd_details,
1980 bool rx_only_promisc)
56a62fc8
JB		 1981{
1982 struct i40e_aq_desc desc;
1983 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1984 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1985 i40e_status status;
1986 u16 flags = 0;
1987
1988 i40e_fill_default_direct_cmd_desc(&desc,
1989 i40e_aqc_opc_set_vsi_promiscuous_modes);
1990
3b120089 1991 if (set) {
56a62fc8 1992 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
b5569892
ASJ		 1993 if (rx_only_promisc &&
1994 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
1995 (hw->aq.api_maj_ver > 1)))
3b120089
ASJ		 1996 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
1997 }
56a62fc8
JB		 1998
1999 cmd->promiscuous_flags = cpu_to_le16(flags);
2000
2001 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
3b120089
ASJ		 2002 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2003 (hw->aq.api_maj_ver > 1))
2004 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
56a62fc8
JB		 2005
2006 cmd->seid = cpu_to_le16(seid);
2007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2008
2009 return status;
2010}
2011
2012/**
2013 * i40e_aq_set_vsi_multicast_promiscuous
2014 * @hw: pointer to the hw struct
2015 * @seid: vsi number
2016 * @set: set multicast promiscuous enable/disable
2017 * @cmd_details: pointer to command details structure or NULL
2018 **/
2019i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2020 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2021{
2022 struct i40e_aq_desc desc;
2023 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2024 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2025 i40e_status status;
2026 u16 flags = 0;
2027
2028 i40e_fill_default_direct_cmd_desc(&desc,
2029 i40e_aqc_opc_set_vsi_promiscuous_modes);
2030
2031 if (set)
2032 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2033
2034 cmd->promiscuous_flags = cpu_to_le16(flags);
2035
2036 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2037
2038 cmd->seid = cpu_to_le16(seid);
2039 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2040
2041 return status;
2042}
2043
6c41a760
GR		 2044/**
2045 * i40e_aq_set_vsi_mc_promisc_on_vlan
2046 * @hw: pointer to the hw struct
2047 * @seid: vsi number
2048 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2049 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2050 * @cmd_details: pointer to command details structure or NULL
2051 **/
2052enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2053 u16 seid, bool enable,
2054 u16 vid,
2055 struct i40e_asq_cmd_details *cmd_details)
2056{
2057 struct i40e_aq_desc desc;
2058 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2059 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2060 enum i40e_status_code status;
2061 u16 flags = 0;
2062
2063 i40e_fill_default_direct_cmd_desc(&desc,
2064 i40e_aqc_opc_set_vsi_promiscuous_modes);
2065
2066 if (enable)
2067 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2068
2069 cmd->promiscuous_flags = cpu_to_le16(flags);
2070 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2071 cmd->seid = cpu_to_le16(seid);
2072 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2073
2074 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2075
2076 return status;
2077}
2078
2079/**
2080 * i40e_aq_set_vsi_uc_promisc_on_vlan
2081 * @hw: pointer to the hw struct
2082 * @seid: vsi number
2083 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2084 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2085 * @cmd_details: pointer to command details structure or NULL
2086 **/
2087enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2088 u16 seid, bool enable,
2089 u16 vid,
2090 struct i40e_asq_cmd_details *cmd_details)
2091{
2092 struct i40e_aq_desc desc;
2093 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2094 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2095 enum i40e_status_code status;
2096 u16 flags = 0;
2097
2098 i40e_fill_default_direct_cmd_desc(&desc,
2099 i40e_aqc_opc_set_vsi_promiscuous_modes);
2100
2101 if (enable)
2102 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2103
2104 cmd->promiscuous_flags = cpu_to_le16(flags);
2105 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2106 cmd->seid = cpu_to_le16(seid);
2107 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2108
2109 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2110
2111 return status;
2112}
2113
56a62fc8
JB		 2114/**
2115 * i40e_aq_set_vsi_broadcast
2116 * @hw: pointer to the hw struct
2117 * @seid: vsi number
2118 * @set_filter: true to set filter, false to clear filter
2119 * @cmd_details: pointer to command details structure or NULL
2120 *
2121 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2122 **/
2123i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2124 u16 seid, bool set_filter,
2125 struct i40e_asq_cmd_details *cmd_details)
2126{
2127 struct i40e_aq_desc desc;
2128 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2129 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2130 i40e_status status;
2131
2132 i40e_fill_default_direct_cmd_desc(&desc,
2133 i40e_aqc_opc_set_vsi_promiscuous_modes);
2134
2135 if (set_filter)
2136 cmd->promiscuous_flags
2137 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2138 else
2139 cmd->promiscuous_flags
2140 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2141
2142 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2143 cmd->seid = cpu_to_le16(seid);
2144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2145
2146 return status;
2147}
2148
7bd6875b
KP		 2149/**
2150 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2151 * @hw: pointer to the hw struct
2152 * @seid: vsi number
2153 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2154 * @cmd_details: pointer to command details structure or NULL
2155 **/
2156i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2157 u16 seid, bool enable,
2158 struct i40e_asq_cmd_details *cmd_details)
2159{
2160 struct i40e_aq_desc desc;
2161 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2162 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2163 i40e_status status;
2164 u16 flags = 0;
2165
2166 i40e_fill_default_direct_cmd_desc(&desc,
2167 i40e_aqc_opc_set_vsi_promiscuous_modes);
2168 if (enable)
2169 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2170
2171 cmd->promiscuous_flags = cpu_to_le16(flags);
2172 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2173 cmd->seid = cpu_to_le16(seid);
2174
2175 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2176
2177 return status;
2178}
2179
56a62fc8
JB		 2180/**
2181 * i40e_get_vsi_params - get VSI configuration info
2182 * @hw: pointer to the hw struct
98d44381 2183 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2184 * @cmd_details: pointer to command details structure or NULL
2185 **/
2186i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2187 struct i40e_vsi_context *vsi_ctx,
2188 struct i40e_asq_cmd_details *cmd_details)
2189{
2190 struct i40e_aq_desc desc;
f5ac8579
SN		 2191 struct i40e_aqc_add_get_update_vsi *cmd =
2192 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 2193 struct i40e_aqc_add_get_update_vsi_completion *resp =
2194 (struct i40e_aqc_add_get_update_vsi_completion *)
2195 &desc.params.raw;
2196 i40e_status status;
2197
2198 i40e_fill_default_direct_cmd_desc(&desc,
2199 i40e_aqc_opc_get_vsi_parameters);
2200
f5ac8579 2201 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2202
2203 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 2204
2205 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2206 sizeof(vsi_ctx->info), NULL);
2207
2208 if (status)
2209 goto aq_get_vsi_params_exit;
2210
2211 vsi_ctx->seid = le16_to_cpu(resp->seid);
2212 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2213 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2214 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2215
2216aq_get_vsi_params_exit:
2217 return status;
2218}
2219
2220/**
2221 * i40e_aq_update_vsi_params
2222 * @hw: pointer to the hw struct
98d44381 2223 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2224 * @cmd_details: pointer to command details structure or NULL
2225 *
2226 * Update a VSI context.
2227 **/
2228i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2229 struct i40e_vsi_context *vsi_ctx,
2230 struct i40e_asq_cmd_details *cmd_details)
2231{
2232 struct i40e_aq_desc desc;
f5ac8579
SN		 2233 struct i40e_aqc_add_get_update_vsi *cmd =
2234 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
b6caccac
KS		 2235 struct i40e_aqc_add_get_update_vsi_completion *resp =
2236 (struct i40e_aqc_add_get_update_vsi_completion *)
2237 &desc.params.raw;
56a62fc8
JB		 2238 i40e_status status;
2239
2240 i40e_fill_default_direct_cmd_desc(&desc,
2241 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 2242 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2243
2244 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 2245
2246 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2247 sizeof(vsi_ctx->info), cmd_details);
2248
b6caccac
KS		 2249 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2250 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2251
56a62fc8
JB		 2252 return status;
2253}
2254
2255/**
2256 * i40e_aq_get_switch_config
2257 * @hw: pointer to the hardware structure
2258 * @buf: pointer to the result buffer
2259 * @buf_size: length of input buffer
2260 * @start_seid: seid to start for the report, 0 == beginning
2261 * @cmd_details: pointer to command details structure or NULL
2262 *
2263 * Fill the buf with switch configuration returned from AdminQ command
2264 **/
2265i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2266 struct i40e_aqc_get_switch_config_resp *buf,
2267 u16 buf_size, u16 *start_seid,
2268 struct i40e_asq_cmd_details *cmd_details)
2269{
2270 struct i40e_aq_desc desc;
2271 struct i40e_aqc_switch_seid *scfg =
2272 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2273 i40e_status status;
2274
2275 i40e_fill_default_direct_cmd_desc(&desc,
2276 i40e_aqc_opc_get_switch_config);
2277 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2278 if (buf_size > I40E_AQ_LARGE_BUF)
2279 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2280 scfg->seid = cpu_to_le16(*start_seid);
2281
2282 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2283 *start_seid = le16_to_cpu(scfg->seid);
2284
2285 return status;
2286}
2287
f3d58497
SN		 2288/**
2289 * i40e_aq_set_switch_config
2290 * @hw: pointer to the hardware structure
2291 * @flags: bit flag values to set
2292 * @valid_flags: which bit flags to set
2293 * @cmd_details: pointer to command details structure or NULL
2294 *
2295 * Set switch configuration bits
2296 **/
2297enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2298 u16 flags,
2299 u16 valid_flags,
2300 struct i40e_asq_cmd_details *cmd_details)
2301{
2302 struct i40e_aq_desc desc;
2303 struct i40e_aqc_set_switch_config *scfg =
2304 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2305 enum i40e_status_code status;
2306
2307 i40e_fill_default_direct_cmd_desc(&desc,
2308 i40e_aqc_opc_set_switch_config);
2309 scfg->flags = cpu_to_le16(flags);
2310 scfg->valid_flags = cpu_to_le16(valid_flags);
2311
2312 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2313
2314 return status;
2315}
2316
56a62fc8
JB		 2317/**
2318 * i40e_aq_get_firmware_version
2319 * @hw: pointer to the hw struct
2320 * @fw_major_version: firmware major version
2321 * @fw_minor_version: firmware minor version
7edf810c 2322 * @fw_build: firmware build number
56a62fc8
JB		 2323 * @api_major_version: major queue version
2324 * @api_minor_version: minor queue version
2325 * @cmd_details: pointer to command details structure or NULL
2326 *
2327 * Get the firmware version from the admin queue commands
2328 **/
2329i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2330 u16 *fw_major_version, u16 *fw_minor_version,
7edf810c 2331 u32 *fw_build,
56a62fc8
JB		 2332 u16 *api_major_version, u16 *api_minor_version,
2333 struct i40e_asq_cmd_details *cmd_details)
2334{
2335 struct i40e_aq_desc desc;
2336 struct i40e_aqc_get_version *resp =
2337 (struct i40e_aqc_get_version *)&desc.params.raw;
2338 i40e_status status;
2339
2340 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2341
2342 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2343
2344 if (!status) {
7edf810c 2345 if (fw_major_version)
56a62fc8 2346 *fw_major_version = le16_to_cpu(resp->fw_major);
7edf810c 2347 if (fw_minor_version)
56a62fc8 2348 *fw_minor_version = le16_to_cpu(resp->fw_minor);
7edf810c
SN		 2349 if (fw_build)
2350 *fw_build = le32_to_cpu(resp->fw_build);
2351 if (api_major_version)
56a62fc8 2352 *api_major_version = le16_to_cpu(resp->api_major);
7edf810c 2353 if (api_minor_version)
56a62fc8
JB		 2354 *api_minor_version = le16_to_cpu(resp->api_minor);
2355 }
2356
2357 return status;
2358}
2359
2360/**
2361 * i40e_aq_send_driver_version
2362 * @hw: pointer to the hw struct
56a62fc8
JB		 2363 * @dv: driver's major, minor version
2364 * @cmd_details: pointer to command details structure or NULL
2365 *
2366 * Send the driver version to the firmware
2367 **/
2368i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2369 struct i40e_driver_version *dv,
2370 struct i40e_asq_cmd_details *cmd_details)
2371{
2372 struct i40e_aq_desc desc;
2373 struct i40e_aqc_driver_version *cmd =
2374 (struct i40e_aqc_driver_version *)&desc.params.raw;
2375 i40e_status status;
9d2f98e1 2376 u16 len;
56a62fc8
JB		 2377
2378 if (dv == NULL)
2379 return I40E_ERR_PARAM;
2380
2381 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2382
3b38cd17 2383 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
56a62fc8
JB		 2384 cmd->driver_major_ver = dv->major_version;
2385 cmd->driver_minor_ver = dv->minor_version;
2386 cmd->driver_build_ver = dv->build_version;
2387 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 2388
2389 len = 0;
2390 while (len < sizeof(dv->driver_string) &&
2391 (dv->driver_string[len] < 0x80) &&
2392 dv->driver_string[len])
2393 len++;
2394 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2395 len, cmd_details);
56a62fc8
JB		 2396
2397 return status;
2398}
2399
2400/**
2401 * i40e_get_link_status - get status of the HW network link
2402 * @hw: pointer to the hw struct
a72a5abc 2403 * @link_up: pointer to bool (true/false = linkup/linkdown)
56a62fc8 2404 *
a72a5abc
JB		 2405 * Variable link_up true if link is up, false if link is down.
2406 * The variable link_up is invalid if returned value of status != 0
56a62fc8
JB		 2407 *
2408 * Side effect: LinkStatusEvent reporting becomes enabled
2409 **/
a72a5abc 2410i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
56a62fc8
JB		 2411{
2412 i40e_status status = 0;
56a62fc8
JB		 2413
2414 if (hw->phy.get_link_info) {
0a862b43 2415 status = i40e_update_link_info(hw);
56a62fc8
JB		 2416
2417 if (status)
a72a5abc
JB		 2418 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2419 status);
56a62fc8
JB		 2420 }
2421
a72a5abc 2422 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
56a62fc8 2423
a72a5abc 2424 return status;
56a62fc8
JB		 2425}
2426
0a862b43
CS		 2427/**
2428 * i40e_updatelink_status - update status of the HW network link
2429 * @hw: pointer to the hw struct
2430 **/
2431i40e_status i40e_update_link_info(struct i40e_hw *hw)
2432{
2433 struct i40e_aq_get_phy_abilities_resp abilities;
2434 i40e_status status = 0;
2435
2436 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2437 if (status)
2438 return status;
2439
8589af70
CW		 2440 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2441 status = i40e_aq_get_phy_capabilities(hw, false, false,
2442 &abilities, NULL);
2443 if (status)
2444 return status;
0a862b43 2445
8589af70
CW		 2446 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2447 sizeof(hw->phy.link_info.module_type));
2448 }
0a862b43
CS		 2449
2450 return status;
2451}
2452
56a62fc8
JB		 2453/**
2454 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2455 * @hw: pointer to the hw struct
2456 * @uplink_seid: the MAC or other gizmo SEID
2457 * @downlink_seid: the VSI SEID
2458 * @enabled_tc: bitmap of TCs to be enabled
2459 * @default_port: true for default port VSI, false for control port
2460 * @veb_seid: pointer to where to put the resulting VEB SEID
8a187f44 2461 * @enable_stats: true to turn on VEB stats
56a62fc8
JB		 2462 * @cmd_details: pointer to command details structure or NULL
2463 *
2464 * This asks the FW to add a VEB between the uplink and downlink
2465 * elements. If the uplink SEID is 0, this will be a floating VEB.
2466 **/
2467i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2468 u16 downlink_seid, u8 enabled_tc,
8a187f44
SN		 2469 bool default_port, u16 *veb_seid,
2470 bool enable_stats,
56a62fc8
JB		 2471 struct i40e_asq_cmd_details *cmd_details)
2472{
2473 struct i40e_aq_desc desc;
2474 struct i40e_aqc_add_veb *cmd =
2475 (struct i40e_aqc_add_veb *)&desc.params.raw;
2476 struct i40e_aqc_add_veb_completion *resp =
2477 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2478 i40e_status status;
2479 u16 veb_flags = 0;
2480
2481 /* SEIDs need to either both be set or both be 0 for floating VEB */
2482 if (!!uplink_seid != !!downlink_seid)
2483 return I40E_ERR_PARAM;
2484
2485 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2486
2487 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2488 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2489 cmd->enable_tcs = enabled_tc;
2490 if (!uplink_seid)
2491 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2492 if (default_port)
2493 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2494 else
2495 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95 2496
8a187f44
SN		 2497 /* reverse logic here: set the bitflag to disable the stats */
2498 if (!enable_stats)
2499 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
e1c51b95 2500
56a62fc8
JB		 2501 cmd->veb_flags = cpu_to_le16(veb_flags);
2502
2503 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2504
2505 if (!status && veb_seid)
2506 *veb_seid = le16_to_cpu(resp->veb_seid);
2507
2508 return status;
2509}
2510
2511/**
2512 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2513 * @hw: pointer to the hw struct
2514 * @veb_seid: the SEID of the VEB to query
2515 * @switch_id: the uplink switch id
98d44381 2516 * @floating: set to true if the VEB is floating
56a62fc8
JB		 2517 * @statistic_index: index of the stats counter block for this VEB
2518 * @vebs_used: number of VEB's used by function
98d44381 2519 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 2520 * @cmd_details: pointer to command details structure or NULL
2521 *
2522 * This retrieves the parameters for a particular VEB, specified by
2523 * uplink_seid, and returns them to the caller.
2524 **/
2525i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2526 u16 veb_seid, u16 *switch_id,
2527 bool *floating, u16 *statistic_index,
2528 u16 *vebs_used, u16 *vebs_free,
2529 struct i40e_asq_cmd_details *cmd_details)
2530{
2531 struct i40e_aq_desc desc;
2532 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2533 (struct i40e_aqc_get_veb_parameters_completion *)
2534 &desc.params.raw;
2535 i40e_status status;
2536
2537 if (veb_seid == 0)
2538 return I40E_ERR_PARAM;
2539
2540 i40e_fill_default_direct_cmd_desc(&desc,
2541 i40e_aqc_opc_get_veb_parameters);
2542 cmd_resp->seid = cpu_to_le16(veb_seid);
2543
2544 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2545 if (status)
2546 goto get_veb_exit;
2547
2548 if (switch_id)
2549 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2550 if (statistic_index)
2551 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2552 if (vebs_used)
2553 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2554 if (vebs_free)
2555 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2556 if (floating) {
2557 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
6995b36c 2558
56a62fc8
JB		 2559 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2560 *floating = true;
2561 else
2562 *floating = false;
2563 }
2564
2565get_veb_exit:
2566 return status;
2567}
2568
2569/**
2570 * i40e_aq_add_macvlan
2571 * @hw: pointer to the hw struct
2572 * @seid: VSI for the mac address
2573 * @mv_list: list of macvlans to be added
2574 * @count: length of the list
2575 * @cmd_details: pointer to command details structure or NULL
2576 *
2577 * Add MAC/VLAN addresses to the HW filtering
2578 **/
2579i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2580 struct i40e_aqc_add_macvlan_element_data *mv_list,
2581 u16 count, struct i40e_asq_cmd_details *cmd_details)
2582{
2583 struct i40e_aq_desc desc;
2584 struct i40e_aqc_macvlan *cmd =
2585 (struct i40e_aqc_macvlan *)&desc.params.raw;
2586 i40e_status status;
2587 u16 buf_size;
67be6eb2 2588 int i;
56a62fc8
JB		 2589
2590 if (count == 0 || !mv_list || !hw)
2591 return I40E_ERR_PARAM;
2592
1efc80ee 2593 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2594
2595 /* prep the rest of the request */
2596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2597 cmd->num_addresses = cpu_to_le16(count);
2598 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2599 cmd->seid[1] = 0;
2600 cmd->seid[2] = 0;
2601
67be6eb2
SN		 2602 for (i = 0; i < count; i++)
2603 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2604 mv_list[i].flags |=
2605 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2606
56a62fc8
JB		 2607 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2608 if (buf_size > I40E_AQ_LARGE_BUF)
2609 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2610
2611 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
67be6eb2 2612 cmd_details);
56a62fc8
JB		 2613
2614 return status;
2615}
2616
2617/**
2618 * i40e_aq_remove_macvlan
2619 * @hw: pointer to the hw struct
2620 * @seid: VSI for the mac address
2621 * @mv_list: list of macvlans to be removed
2622 * @count: length of the list
2623 * @cmd_details: pointer to command details structure or NULL
2624 *
2625 * Remove MAC/VLAN addresses from the HW filtering
2626 **/
2627i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2628 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2629 u16 count, struct i40e_asq_cmd_details *cmd_details)
2630{
2631 struct i40e_aq_desc desc;
2632 struct i40e_aqc_macvlan *cmd =
2633 (struct i40e_aqc_macvlan *)&desc.params.raw;
2634 i40e_status status;
2635 u16 buf_size;
2636
2637 if (count == 0 || !mv_list || !hw)
2638 return I40E_ERR_PARAM;
2639
1efc80ee 2640 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2641
2642 /* prep the rest of the request */
2643 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2644 cmd->num_addresses = cpu_to_le16(count);
2645 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2646 cmd->seid[1] = 0;
2647 cmd->seid[2] = 0;
2648
2649 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2650 if (buf_size > I40E_AQ_LARGE_BUF)
2651 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2652
2653 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2654 cmd_details);
2655
2656 return status;
2657}
2658
7bd6875b
KP		 2659/**
2660 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2661 * @hw: pointer to the hw struct
2662 * @opcode: AQ opcode for add or delete mirror rule
2663 * @sw_seid: Switch SEID (to which rule refers)
2664 * @rule_type: Rule Type (ingress/egress/VLAN)
2665 * @id: Destination VSI SEID or Rule ID
2666 * @count: length of the list
2667 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2668 * @cmd_details: pointer to command details structure or NULL
2669 * @rule_id: Rule ID returned from FW
2670 * @rule_used: Number of rules used in internal switch
2671 * @rule_free: Number of rules free in internal switch
2672 *
2673 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2674 * VEBs/VEPA elements only
2675 **/
2676static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2677 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2678 u16 count, __le16 *mr_list,
2679 struct i40e_asq_cmd_details *cmd_details,
2680 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2681{
2682 struct i40e_aq_desc desc;
2683 struct i40e_aqc_add_delete_mirror_rule *cmd =
2684 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2685 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2686 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2687 i40e_status status;
2688 u16 buf_size;
2689
2690 buf_size = count * sizeof(*mr_list);
2691
2692 /* prep the rest of the request */
2693 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2694 cmd->seid = cpu_to_le16(sw_seid);
2695 cmd->rule_type = cpu_to_le16(rule_type &
2696 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2697 cmd->num_entries = cpu_to_le16(count);
2698 /* Dest VSI for add, rule_id for delete */
2699 cmd->destination = cpu_to_le16(id);
2700 if (mr_list) {
2701 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2702 I40E_AQ_FLAG_RD));
2703 if (buf_size > I40E_AQ_LARGE_BUF)
2704 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2705 }
2706
2707 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2708 cmd_details);
2709 if (!status ||
2710 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2711 if (rule_id)
2712 *rule_id = le16_to_cpu(resp->rule_id);
2713 if (rules_used)
2714 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2715 if (rules_free)
2716 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2717 }
2718 return status;
2719}
2720
2721/**
2722 * i40e_aq_add_mirrorrule - add a mirror rule
2723 * @hw: pointer to the hw struct
2724 * @sw_seid: Switch SEID (to which rule refers)
2725 * @rule_type: Rule Type (ingress/egress/VLAN)
2726 * @dest_vsi: SEID of VSI to which packets will be mirrored
2727 * @count: length of the list
2728 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2729 * @cmd_details: pointer to command details structure or NULL
2730 * @rule_id: Rule ID returned from FW
2731 * @rule_used: Number of rules used in internal switch
2732 * @rule_free: Number of rules free in internal switch
2733 *
2734 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2735 **/
2736i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2737 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2738 struct i40e_asq_cmd_details *cmd_details,
2739 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2740{
2741 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2742 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2743 if (count == 0 || !mr_list)
2744 return I40E_ERR_PARAM;
2745 }
2746
2747 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2748 rule_type, dest_vsi, count, mr_list,
2749 cmd_details, rule_id, rules_used, rules_free);
2750}
2751
2752/**
2753 * i40e_aq_delete_mirrorrule - delete a mirror rule
2754 * @hw: pointer to the hw struct
2755 * @sw_seid: Switch SEID (to which rule refers)
2756 * @rule_type: Rule Type (ingress/egress/VLAN)
2757 * @count: length of the list
2758 * @rule_id: Rule ID that is returned in the receive desc as part of
2759 * add_mirrorrule.
2760 * @mr_list: list of mirrored VLAN IDs to be removed
2761 * @cmd_details: pointer to command details structure or NULL
2762 * @rule_used: Number of rules used in internal switch
2763 * @rule_free: Number of rules free in internal switch
2764 *
2765 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2766 **/
2767i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2768 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2769 struct i40e_asq_cmd_details *cmd_details,
2770 u16 *rules_used, u16 *rules_free)
2771{
2772 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
db077278 2773 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7bd6875b
KP		 2774 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2775 * mirroring. For other rule_type, count and rule_type should
2776 * not matter.
2777 */
2778 if (count == 0 || !mr_list)
2779 return I40E_ERR_PARAM;
2780 }
2781
2782 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2783 rule_type, rule_id, count, mr_list,
2784 cmd_details, NULL, rules_used, rules_free);
2785}
2786
56a62fc8
JB		 2787/**
2788 * i40e_aq_send_msg_to_vf
2789 * @hw: pointer to the hardware structure
b40c82e6 2790 * @vfid: VF id to send msg
98d44381
JK		 2791 * @v_opcode: opcodes for VF-PF communication
2792 * @v_retval: return error code
56a62fc8
JB		 2793 * @msg: pointer to the msg buffer
2794 * @msglen: msg length
2795 * @cmd_details: pointer to command details
2796 *
2797 * send msg to vf
2798 **/
2799i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2800 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2801 struct i40e_asq_cmd_details *cmd_details)
2802{
2803 struct i40e_aq_desc desc;
2804 struct i40e_aqc_pf_vf_message *cmd =
2805 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2806 i40e_status status;
2807
2808 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2809 cmd->id = cpu_to_le32(vfid);
2810 desc.cookie_high = cpu_to_le32(v_opcode);
2811 desc.cookie_low = cpu_to_le32(v_retval);
2812 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2813 if (msglen) {
2814 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2815 I40E_AQ_FLAG_RD));
2816 if (msglen > I40E_AQ_LARGE_BUF)
2817 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2818 desc.datalen = cpu_to_le16(msglen);
2819 }
2820 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2821
2822 return status;
2823}
2824
9fee9db5
SN		 2825/**
2826 * i40e_aq_debug_read_register
2827 * @hw: pointer to the hw struct
2828 * @reg_addr: register address
2829 * @reg_val: register value
2830 * @cmd_details: pointer to command details structure or NULL
2831 *
2832 * Read the register using the admin queue commands
2833 **/
2834i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
7b115dd0 2835 u32 reg_addr, u64 *reg_val,
9fee9db5
SN		 2836 struct i40e_asq_cmd_details *cmd_details)
2837{
2838 struct i40e_aq_desc desc;
2839 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2840 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2841 i40e_status status;
2842
2843 if (reg_val == NULL)
2844 return I40E_ERR_PARAM;
2845
7b115dd0 2846 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
9fee9db5
SN		 2847
2848 cmd_resp->address = cpu_to_le32(reg_addr);
2849
2850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2851
2852 if (!status) {
7b115dd0
JB		 2853 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2854 (u64)le32_to_cpu(cmd_resp->value_low);
9fee9db5
SN		 2855 }
2856
2857 return status;
2858}
2859
53db45cd
SN		 2860/**
2861 * i40e_aq_debug_write_register
2862 * @hw: pointer to the hw struct
2863 * @reg_addr: register address
2864 * @reg_val: register value
2865 * @cmd_details: pointer to command details structure or NULL
2866 *
2867 * Write to a register using the admin queue commands
2868 **/
2869i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2870 u32 reg_addr, u64 reg_val,
2871 struct i40e_asq_cmd_details *cmd_details)
2872{
2873 struct i40e_aq_desc desc;
2874 struct i40e_aqc_debug_reg_read_write *cmd =
2875 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2876 i40e_status status;
2877
2878 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2879
2880 cmd->address = cpu_to_le32(reg_addr);
2881 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2882 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2883
2884 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2885
2886 return status;
2887}
2888
56a62fc8
JB		 2889/**
2890 * i40e_aq_request_resource
2891 * @hw: pointer to the hw struct
2892 * @resource: resource id
2893 * @access: access type
2894 * @sdp_number: resource number
2895 * @timeout: the maximum time in ms that the driver may hold the resource
2896 * @cmd_details: pointer to command details structure or NULL
2897 *
2898 * requests common resource using the admin queue commands
2899 **/
2900i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2901 enum i40e_aq_resources_ids resource,
2902 enum i40e_aq_resource_access_type access,
2903 u8 sdp_number, u64 *timeout,
2904 struct i40e_asq_cmd_details *cmd_details)
2905{
2906 struct i40e_aq_desc desc;
2907 struct i40e_aqc_request_resource *cmd_resp =
2908 (struct i40e_aqc_request_resource *)&desc.params.raw;
2909 i40e_status status;
2910
2911 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2912
2913 cmd_resp->resource_id = cpu_to_le16(resource);
2914 cmd_resp->access_type = cpu_to_le16(access);
2915 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2916
2917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2918 /* The completion specifies the maximum time in ms that the driver
2919 * may hold the resource in the Timeout field.
2920 * If the resource is held by someone else, the command completes with
2921 * busy return value and the timeout field indicates the maximum time
2922 * the current owner of the resource has to free it.
2923 */
2924 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2925 *timeout = le32_to_cpu(cmd_resp->timeout);
2926
2927 return status;
2928}
2929
2930/**
2931 * i40e_aq_release_resource
2932 * @hw: pointer to the hw struct
2933 * @resource: resource id
2934 * @sdp_number: resource number
2935 * @cmd_details: pointer to command details structure or NULL
2936 *
2937 * release common resource using the admin queue commands
2938 **/
2939i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2940 enum i40e_aq_resources_ids resource,
2941 u8 sdp_number,
2942 struct i40e_asq_cmd_details *cmd_details)
2943{
2944 struct i40e_aq_desc desc;
2945 struct i40e_aqc_request_resource *cmd =
2946 (struct i40e_aqc_request_resource *)&desc.params.raw;
2947 i40e_status status;
2948
2949 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2950
2951 cmd->resource_id = cpu_to_le16(resource);
2952 cmd->resource_number = cpu_to_le32(sdp_number);
2953
2954 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2955
2956 return status;
2957}
2958
2959/**
2960 * i40e_aq_read_nvm
2961 * @hw: pointer to the hw struct
2962 * @module_pointer: module pointer location in words from the NVM beginning
2963 * @offset: byte offset from the module beginning
2964 * @length: length of the section to be read (in bytes from the offset)
2965 * @data: command buffer (size [bytes] = length)
2966 * @last_command: tells if this is the last command in a series
2967 * @cmd_details: pointer to command details structure or NULL
2968 *
2969 * Read the NVM using the admin queue commands
2970 **/
2971i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2972 u32 offset, u16 length, void *data,
2973 bool last_command,
2974 struct i40e_asq_cmd_details *cmd_details)
2975{
2976 struct i40e_aq_desc desc;
2977 struct i40e_aqc_nvm_update *cmd =
2978 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2979 i40e_status status;
2980
2981 /* In offset the highest byte must be zeroed. */
2982 if (offset & 0xFF000000) {
2983 status = I40E_ERR_PARAM;
2984 goto i40e_aq_read_nvm_exit;
2985 }
2986
2987 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2988
2989 /* If this is the last command in a series, set the proper flag. */
2990 if (last_command)
2991 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2992 cmd->module_pointer = module_pointer;
2993 cmd->offset = cpu_to_le32(offset);
2994 cmd->length = cpu_to_le16(length);
2995
2996 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2997 if (length > I40E_AQ_LARGE_BUF)
2998 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2999
3000 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3001
3002i40e_aq_read_nvm_exit:
3003 return status;
3004}
3005
cd552cb4
SN		 3006/**
3007 * i40e_aq_erase_nvm
3008 * @hw: pointer to the hw struct
3009 * @module_pointer: module pointer location in words from the NVM beginning
3010 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3011 * @length: length of the section to be erased (expressed in 4 KB)
3012 * @last_command: tells if this is the last command in a series
3013 * @cmd_details: pointer to command details structure or NULL
3014 *
3015 * Erase the NVM sector using the admin queue commands
3016 **/
3017i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3018 u32 offset, u16 length, bool last_command,
3019 struct i40e_asq_cmd_details *cmd_details)
3020{
3021 struct i40e_aq_desc desc;
3022 struct i40e_aqc_nvm_update *cmd =
3023 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3024 i40e_status status;
3025
3026 /* In offset the highest byte must be zeroed. */
3027 if (offset & 0xFF000000) {
3028 status = I40E_ERR_PARAM;
3029 goto i40e_aq_erase_nvm_exit;
3030 }
3031
3032 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3033
3034 /* If this is the last command in a series, set the proper flag. */
3035 if (last_command)
3036 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3037 cmd->module_pointer = module_pointer;
3038 cmd->offset = cpu_to_le32(offset);
3039 cmd->length = cpu_to_le16(length);
3040
3041 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3042
3043i40e_aq_erase_nvm_exit:
3044 return status;
3045}
3046
56a62fc8
JB		 3047/**
3048 * i40e_parse_discover_capabilities
3049 * @hw: pointer to the hw struct
3050 * @buff: pointer to a buffer containing device/function capability records
3051 * @cap_count: number of capability records in the list
3052 * @list_type_opc: type of capabilities list to parse
3053 *
3054 * Parse the device/function capabilities list.
3055 **/
3056static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3057 u32 cap_count,
3058 enum i40e_admin_queue_opc list_type_opc)
3059{
3060 struct i40e_aqc_list_capabilities_element_resp *cap;
9fee9db5 3061 u32 valid_functions, num_functions;
56a62fc8
JB		 3062 u32 number, logical_id, phys_id;
3063 struct i40e_hw_capabilities *p;
c78b953e 3064 u8 major_rev;
56a62fc8
JB		 3065 u32 i = 0;
3066 u16 id;
3067
3068 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3069
3070 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 3071 p = &hw->dev_caps;
56a62fc8 3072 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 3073 p = &hw->func_caps;
56a62fc8
JB		 3074 else
3075 return;
3076
3077 for (i = 0; i < cap_count; i++, cap++) {
3078 id = le16_to_cpu(cap->id);
3079 number = le32_to_cpu(cap->number);
3080 logical_id = le32_to_cpu(cap->logical_id);
3081 phys_id = le32_to_cpu(cap->phys_id);
c78b953e 3082 major_rev = cap->major_rev;
56a62fc8
JB		 3083
3084 switch (id) {
406e734a 3085 case I40E_AQ_CAP_ID_SWITCH_MODE:
56a62fc8
JB		 3086 p->switch_mode = number;
3087 break;
406e734a 3088 case I40E_AQ_CAP_ID_MNG_MODE:
56a62fc8
JB		 3089 p->management_mode = number;
3090 break;
406e734a 3091 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
56a62fc8
JB		 3092 p->npar_enable = number;
3093 break;
406e734a 3094 case I40E_AQ_CAP_ID_OS2BMC_CAP:
56a62fc8
JB		 3095 p->os2bmc = number;
3096 break;
406e734a 3097 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
56a62fc8
JB		 3098 p->valid_functions = number;
3099 break;
406e734a 3100 case I40E_AQ_CAP_ID_SRIOV:
56a62fc8
JB		 3101 if (number == 1)
3102 p->sr_iov_1_1 = true;
3103 break;
406e734a 3104 case I40E_AQ_CAP_ID_VF:
56a62fc8
JB		 3105 p->num_vfs = number;
3106 p->vf_base_id = logical_id;
3107 break;
406e734a 3108 case I40E_AQ_CAP_ID_VMDQ:
56a62fc8
JB		 3109 if (number == 1)
3110 p->vmdq = true;
3111 break;
406e734a 3112 case I40E_AQ_CAP_ID_8021QBG:
56a62fc8
JB		 3113 if (number == 1)
3114 p->evb_802_1_qbg = true;
3115 break;
406e734a 3116 case I40E_AQ_CAP_ID_8021QBR:
56a62fc8
JB		 3117 if (number == 1)
3118 p->evb_802_1_qbh = true;
3119 break;
406e734a 3120 case I40E_AQ_CAP_ID_VSI:
56a62fc8
JB		 3121 p->num_vsis = number;
3122 break;
406e734a 3123 case I40E_AQ_CAP_ID_DCB:
56a62fc8
JB		 3124 if (number == 1) {
3125 p->dcb = true;
3126 p->enabled_tcmap = logical_id;
3127 p->maxtc = phys_id;
3128 }
3129 break;
406e734a 3130 case I40E_AQ_CAP_ID_FCOE:
56a62fc8
JB		 3131 if (number == 1)
3132 p->fcoe = true;
3133 break;
406e734a 3134 case I40E_AQ_CAP_ID_ISCSI:
63d7e5a4
NP		 3135 if (number == 1)
3136 p->iscsi = true;
3137 break;
406e734a 3138 case I40E_AQ_CAP_ID_RSS:
56a62fc8 3139 p->rss = true;
e157ea30 3140 p->rss_table_size = number;
56a62fc8
JB		 3141 p->rss_table_entry_width = logical_id;
3142 break;
406e734a 3143 case I40E_AQ_CAP_ID_RXQ:
56a62fc8
JB		 3144 p->num_rx_qp = number;
3145 p->base_queue = phys_id;
3146 break;
406e734a 3147 case I40E_AQ_CAP_ID_TXQ:
56a62fc8
JB		 3148 p->num_tx_qp = number;
3149 p->base_queue = phys_id;
3150 break;
406e734a 3151 case I40E_AQ_CAP_ID_MSIX:
56a62fc8 3152 p->num_msix_vectors = number;
453e16e8
DK		 3153 i40e_debug(hw, I40E_DEBUG_INIT,
3154 "HW Capability: MSIX vector count = %d\n",
3155 p->num_msix_vectors);
56a62fc8 3156 break;
406e734a 3157 case I40E_AQ_CAP_ID_VF_MSIX:
56a62fc8
JB		 3158 p->num_msix_vectors_vf = number;
3159 break;
406e734a 3160 case I40E_AQ_CAP_ID_FLEX10:
c78b953e
PO		 3161 if (major_rev == 1) {
3162 if (number == 1) {
3163 p->flex10_enable = true;
3164 p->flex10_capable = true;
3165 }
3166 } else {
3167 /* Capability revision >= 2 */
3168 if (number & 1)
3169 p->flex10_enable = true;
3170 if (number & 2)
3171 p->flex10_capable = true;
3172 }
3173 p->flex10_mode = logical_id;
3174 p->flex10_status = phys_id;
56a62fc8 3175 break;
406e734a 3176 case I40E_AQ_CAP_ID_CEM:
56a62fc8
JB		 3177 if (number == 1)
3178 p->mgmt_cem = true;
3179 break;
406e734a 3180 case I40E_AQ_CAP_ID_IWARP:
56a62fc8
JB		 3181 if (number == 1)
3182 p->iwarp = true;
3183 break;
406e734a 3184 case I40E_AQ_CAP_ID_LED:
56a62fc8
JB		 3185 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3186 p->led[phys_id] = true;
3187 break;
406e734a 3188 case I40E_AQ_CAP_ID_SDP:
56a62fc8
JB		 3189 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3190 p->sdp[phys_id] = true;
3191 break;
406e734a 3192 case I40E_AQ_CAP_ID_MDIO:
56a62fc8
JB		 3193 if (number == 1) {
3194 p->mdio_port_num = phys_id;
3195 p->mdio_port_mode = logical_id;
3196 }
3197 break;
406e734a 3198 case I40E_AQ_CAP_ID_1588:
56a62fc8
JB		 3199 if (number == 1)
3200 p->ieee_1588 = true;
3201 break;
406e734a 3202 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
56a62fc8
JB		 3203 p->fd = true;
3204 p->fd_filters_guaranteed = number;
3205 p->fd_filters_best_effort = logical_id;
3206 break;
406e734a 3207 case I40E_AQ_CAP_ID_WSR_PROT:
73b23402
KS		 3208 p->wr_csr_prot = (u64)number;
3209 p->wr_csr_prot |= (u64)logical_id << 32;
3210 break;
68a1c5a7
MK		 3211 case I40E_AQ_CAP_ID_NVM_MGMT:
3212 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3213 p->sec_rev_disabled = true;
3214 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3215 p->update_disabled = true;
3216 break;
56a62fc8
JB		 3217 default:
3218 break;
3219 }
3220 }
3221
f18ae100
VD		 3222 if (p->fcoe)
3223 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3224
566bb85d
VD		 3225 /* Software override ensuring FCoE is disabled if npar or mfp
3226 * mode because it is not supported in these modes.
3227 */
c78b953e 3228 if (p->npar_enable || p->flex10_enable)
566bb85d
VD		 3229 p->fcoe = false;
3230
9fee9db5
SN		 3231 /* count the enabled ports (aka the "not disabled" ports) */
3232 hw->num_ports = 0;
3233 for (i = 0; i < 4; i++) {
3234 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3235 u64 port_cfg = 0;
3236
3237 /* use AQ read to get the physical register offset instead
3238 * of the port relative offset
3239 */
3240 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3241 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3242 hw->num_ports++;
3243 }
3244
3245 valid_functions = p->valid_functions;
3246 num_functions = 0;
3247 while (valid_functions) {
3248 if (valid_functions & 1)
3249 num_functions++;
3250 valid_functions >>= 1;
3251 }
3252
3253 /* partition id is 1-based, and functions are evenly spread
3254 * across the ports as partitions
3255 */
3256 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3257 hw->num_partitions = num_functions / hw->num_ports;
3258
56a62fc8
JB		 3259 /* additional HW specific goodies that might
3260 * someday be HW version specific
3261 */
3262 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3263}
3264
3265/**
3266 * i40e_aq_discover_capabilities
3267 * @hw: pointer to the hw struct
3268 * @buff: a virtual buffer to hold the capabilities
3269 * @buff_size: Size of the virtual buffer
3270 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3271 * @list_type_opc: capabilities type to discover - pass in the command opcode
3272 * @cmd_details: pointer to command details structure or NULL
3273 *
3274 * Get the device capabilities descriptions from the firmware
3275 **/
3276i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3277 void *buff, u16 buff_size, u16 *data_size,
3278 enum i40e_admin_queue_opc list_type_opc,
3279 struct i40e_asq_cmd_details *cmd_details)
3280{
3281 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 3282 struct i40e_aq_desc desc;
8fb905b3 3283 i40e_status status = 0;
56a62fc8
JB		 3284
3285 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3286
3287 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3288 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3289 status = I40E_ERR_PARAM;
3290 goto exit;
3291 }
3292
3293 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3294
3295 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3296 if (buff_size > I40E_AQ_LARGE_BUF)
3297 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3298
3299 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3300 *data_size = le16_to_cpu(desc.datalen);
3301
3302 if (status)
3303 goto exit;
3304
3305 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3306 list_type_opc);
3307
3308exit:
3309 return status;
3310}
3311
cd552cb4
SN		 3312/**
3313 * i40e_aq_update_nvm
3314 * @hw: pointer to the hw struct
3315 * @module_pointer: module pointer location in words from the NVM beginning
3316 * @offset: byte offset from the module beginning
3317 * @length: length of the section to be written (in bytes from the offset)
3318 * @data: command buffer (size [bytes] = length)
3319 * @last_command: tells if this is the last command in a series
3320 * @cmd_details: pointer to command details structure or NULL
3321 *
3322 * Update the NVM using the admin queue commands
3323 **/
3324i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3325 u32 offset, u16 length, void *data,
3326 bool last_command,
3327 struct i40e_asq_cmd_details *cmd_details)
3328{
3329 struct i40e_aq_desc desc;
3330 struct i40e_aqc_nvm_update *cmd =
3331 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3332 i40e_status status;
3333
3334 /* In offset the highest byte must be zeroed. */
3335 if (offset & 0xFF000000) {
3336 status = I40E_ERR_PARAM;
3337 goto i40e_aq_update_nvm_exit;
3338 }
3339
3340 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3341
3342 /* If this is the last command in a series, set the proper flag. */
3343 if (last_command)
3344 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3345 cmd->module_pointer = module_pointer;
3346 cmd->offset = cpu_to_le32(offset);
3347 cmd->length = cpu_to_le16(length);
3348
3349 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3350 if (length > I40E_AQ_LARGE_BUF)
3351 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3352
3353 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3354
3355i40e_aq_update_nvm_exit:
3356 return status;
3357}
3358
56a62fc8
JB		 3359/**
3360 * i40e_aq_get_lldp_mib
3361 * @hw: pointer to the hw struct
3362 * @bridge_type: type of bridge requested
3363 * @mib_type: Local, Remote or both Local and Remote MIBs
3364 * @buff: pointer to a user supplied buffer to store the MIB block
3365 * @buff_size: size of the buffer (in bytes)
3366 * @local_len : length of the returned Local LLDP MIB
3367 * @remote_len: length of the returned Remote LLDP MIB
3368 * @cmd_details: pointer to command details structure or NULL
3369 *
3370 * Requests the complete LLDP MIB (entire packet).
3371 **/
3372i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3373 u8 mib_type, void *buff, u16 buff_size,
3374 u16 *local_len, u16 *remote_len,
3375 struct i40e_asq_cmd_details *cmd_details)
3376{
3377 struct i40e_aq_desc desc;
3378 struct i40e_aqc_lldp_get_mib *cmd =
3379 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3380 struct i40e_aqc_lldp_get_mib *resp =
3381 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3382 i40e_status status;
3383
3384 if (buff_size == 0 || !buff)
3385 return I40E_ERR_PARAM;
3386
3387 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3388 /* Indirect Command */
3389 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3390
3391 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3392 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3393 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3394
3395 desc.datalen = cpu_to_le16(buff_size);
3396
3397 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3398 if (buff_size > I40E_AQ_LARGE_BUF)
3399 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3400
3401 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3402 if (!status) {
3403 if (local_len != NULL)
3404 *local_len = le16_to_cpu(resp->local_len);
3405 if (remote_len != NULL)
3406 *remote_len = le16_to_cpu(resp->remote_len);
3407 }
3408
3409 return status;
3410}
3411
3412/**
3413 * i40e_aq_cfg_lldp_mib_change_event
3414 * @hw: pointer to the hw struct
3415 * @enable_update: Enable or Disable event posting
3416 * @cmd_details: pointer to command details structure or NULL
3417 *
3418 * Enable or Disable posting of an event on ARQ when LLDP MIB
3419 * associated with the interface changes
3420 **/
3421i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3422 bool enable_update,
3423 struct i40e_asq_cmd_details *cmd_details)
3424{
3425 struct i40e_aq_desc desc;
3426 struct i40e_aqc_lldp_update_mib *cmd =
3427 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3428 i40e_status status;
3429
3430 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3431
3432 if (!enable_update)
3433 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3434
3435 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3436
3437 return status;
3438}
3439
3440/**
3441 * i40e_aq_stop_lldp
3442 * @hw: pointer to the hw struct
3443 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3444 * @cmd_details: pointer to command details structure or NULL
3445 *
3446 * Stop or Shutdown the embedded LLDP Agent
3447 **/
3448i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3449 struct i40e_asq_cmd_details *cmd_details)
3450{
3451 struct i40e_aq_desc desc;
3452 struct i40e_aqc_lldp_stop *cmd =
3453 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3454 i40e_status status;
3455
3456 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3457
3458 if (shutdown_agent)
3459 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3460
3461 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3462
3463 return status;
3464}
3465
3466/**
3467 * i40e_aq_start_lldp
3468 * @hw: pointer to the hw struct
3469 * @cmd_details: pointer to command details structure or NULL
3470 *
3471 * Start the embedded LLDP Agent on all ports.
3472 **/
3473i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3474 struct i40e_asq_cmd_details *cmd_details)
3475{
3476 struct i40e_aq_desc desc;
3477 struct i40e_aqc_lldp_start *cmd =
3478 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3479 i40e_status status;
3480
3481 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3482
3483 cmd->command = I40E_AQ_LLDP_AGENT_START;
3484
3485 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3486
3487 return status;
3488}
3489
9fa61dd2
NP		 3490/**
3491 * i40e_aq_get_cee_dcb_config
3492 * @hw: pointer to the hw struct
3493 * @buff: response buffer that stores CEE operational configuration
3494 * @buff_size: size of the buffer passed
3495 * @cmd_details: pointer to command details structure or NULL
3496 *
3497 * Get CEE DCBX mode operational configuration from firmware
3498 **/
3499i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3500 void *buff, u16 buff_size,
3501 struct i40e_asq_cmd_details *cmd_details)
3502{
3503 struct i40e_aq_desc desc;
3504 i40e_status status;
3505
3506 if (buff_size == 0 || !buff)
3507 return I40E_ERR_PARAM;
3508
3509 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3510
3511 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3512 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3513 cmd_details);
3514
3515 return status;
3516}
3517
a1c9a9d9
JK		 3518/**
3519 * i40e_aq_add_udp_tunnel
3520 * @hw: pointer to the hw struct
3521 * @udp_port: the UDP port to add
3522 * @header_len: length of the tunneling header length in DWords
3523 * @protocol_index: protocol index type
98d44381 3524 * @filter_index: pointer to filter index
a1c9a9d9
JK		 3525 * @cmd_details: pointer to command details structure or NULL
3526 **/
3527i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 3528 u16 udp_port, u8 protocol_index,
3529 u8 *filter_index,
a1c9a9d9
JK		 3530 struct i40e_asq_cmd_details *cmd_details)
3531{
3532 struct i40e_aq_desc desc;
3533 struct i40e_aqc_add_udp_tunnel *cmd =
3534 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3535 struct i40e_aqc_del_udp_tunnel_completion *resp =
3536 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3537 i40e_status status;
3538
3539 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3540
3541 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 3542 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 3543
3544 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3545
65d13461 3546 if (!status && filter_index)
a1c9a9d9
JK		 3547 *filter_index = resp->index;
3548
3549 return status;
3550}
3551
3552/**
3553 * i40e_aq_del_udp_tunnel
3554 * @hw: pointer to the hw struct
3555 * @index: filter index
3556 * @cmd_details: pointer to command details structure or NULL
3557 **/
3558i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3559 struct i40e_asq_cmd_details *cmd_details)
3560{
3561 struct i40e_aq_desc desc;
3562 struct i40e_aqc_remove_udp_tunnel *cmd =
3563 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3564 i40e_status status;
3565
3566 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3567
3568 cmd->index = index;
3569
3570 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3571
3572 return status;
3573}
3574
56a62fc8
JB		 3575/**
3576 * i40e_aq_delete_element - Delete switch element
3577 * @hw: pointer to the hw struct
3578 * @seid: the SEID to delete from the switch
3579 * @cmd_details: pointer to command details structure or NULL
3580 *
3581 * This deletes a switch element from the switch.
3582 **/
3583i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3584 struct i40e_asq_cmd_details *cmd_details)
3585{
3586 struct i40e_aq_desc desc;
3587 struct i40e_aqc_switch_seid *cmd =
3588 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3589 i40e_status status;
3590
3591 if (seid == 0)
3592 return I40E_ERR_PARAM;
3593
3594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3595
3596 cmd->seid = cpu_to_le16(seid);
3597
3598 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3599
3600 return status;
3601}
3602
afb3ff0d
NP		 3603/**
3604 * i40e_aq_dcb_updated - DCB Updated Command
3605 * @hw: pointer to the hw struct
3606 * @cmd_details: pointer to command details structure or NULL
3607 *
3608 * EMP will return when the shared RPB settings have been
3609 * recomputed and modified. The retval field in the descriptor
3610 * will be set to 0 when RPB is modified.
3611 **/
3612i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3613 struct i40e_asq_cmd_details *cmd_details)
3614{
3615 struct i40e_aq_desc desc;
3616 i40e_status status;
3617
3618 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3619
3620 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3621
3622 return status;
3623}
3624
56a62fc8
JB		 3625/**
3626 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3627 * @hw: pointer to the hw struct
3628 * @seid: seid for the physical port/switching component/vsi
3629 * @buff: Indirect buffer to hold data parameters and response
3630 * @buff_size: Indirect buffer size
3631 * @opcode: Tx scheduler AQ command opcode
3632 * @cmd_details: pointer to command details structure or NULL
3633 *
3634 * Generic command handler for Tx scheduler AQ commands
3635 **/
3636static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3637 void *buff, u16 buff_size,
3638 enum i40e_admin_queue_opc opcode,
3639 struct i40e_asq_cmd_details *cmd_details)
3640{
3641 struct i40e_aq_desc desc;
3642 struct i40e_aqc_tx_sched_ind *cmd =
3643 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3644 i40e_status status;
3645 bool cmd_param_flag = false;
3646
3647 switch (opcode) {
3648 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3649 case i40e_aqc_opc_configure_vsi_tc_bw:
3650 case i40e_aqc_opc_enable_switching_comp_ets:
3651 case i40e_aqc_opc_modify_switching_comp_ets:
3652 case i40e_aqc_opc_disable_switching_comp_ets:
3653 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3654 case i40e_aqc_opc_configure_switching_comp_bw_config:
3655 cmd_param_flag = true;
3656 break;
3657 case i40e_aqc_opc_query_vsi_bw_config:
3658 case i40e_aqc_opc_query_vsi_ets_sla_config:
3659 case i40e_aqc_opc_query_switching_comp_ets_config:
3660 case i40e_aqc_opc_query_port_ets_config:
3661 case i40e_aqc_opc_query_switching_comp_bw_config:
3662 cmd_param_flag = false;
3663 break;
3664 default:
3665 return I40E_ERR_PARAM;
3666 }
3667
3668 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3669
3670 /* Indirect command */
3671 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3672 if (cmd_param_flag)
3673 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3674 if (buff_size > I40E_AQ_LARGE_BUF)
3675 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3676
3677 desc.datalen = cpu_to_le16(buff_size);
3678
3679 cmd->vsi_seid = cpu_to_le16(seid);
3680
3681 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3682
3683 return status;
3684}
3685
6b192891
MW		 3686/**
3687 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3688 * @hw: pointer to the hw struct
3689 * @seid: VSI seid
3690 * @credit: BW limit credits (0 = disabled)
3691 * @max_credit: Max BW limit credits
3692 * @cmd_details: pointer to command details structure or NULL
3693 **/
3694i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3695 u16 seid, u16 credit, u8 max_credit,
3696 struct i40e_asq_cmd_details *cmd_details)
3697{
3698 struct i40e_aq_desc desc;
3699 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3700 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3701 i40e_status status;
3702
3703 i40e_fill_default_direct_cmd_desc(&desc,
3704 i40e_aqc_opc_configure_vsi_bw_limit);
3705
3706 cmd->vsi_seid = cpu_to_le16(seid);
3707 cmd->credit = cpu_to_le16(credit);
3708 cmd->max_credit = max_credit;
3709
3710 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3711
3712 return status;
3713}
3714
56a62fc8
JB		 3715/**
3716 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3717 * @hw: pointer to the hw struct
3718 * @seid: VSI seid
3719 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3720 * @cmd_details: pointer to command details structure or NULL
3721 **/
3722i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3723 u16 seid,
3724 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3725 struct i40e_asq_cmd_details *cmd_details)
3726{
3727 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3728 i40e_aqc_opc_configure_vsi_tc_bw,
3729 cmd_details);
3730}
3731
afb3ff0d
NP		 3732/**
3733 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3734 * @hw: pointer to the hw struct
3735 * @seid: seid of the switching component connected to Physical Port
3736 * @ets_data: Buffer holding ETS parameters
3737 * @cmd_details: pointer to command details structure or NULL
3738 **/
3739i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3740 u16 seid,
3741 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3742 enum i40e_admin_queue_opc opcode,
3743 struct i40e_asq_cmd_details *cmd_details)
3744{
3745 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3746 sizeof(*ets_data), opcode, cmd_details);
3747}
3748
3749/**
3750 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3751 * @hw: pointer to the hw struct
3752 * @seid: seid of the switching component
3753 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3754 * @cmd_details: pointer to command details structure or NULL
3755 **/
3756i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3757 u16 seid,
3758 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3759 struct i40e_asq_cmd_details *cmd_details)
3760{
3761 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3762 i40e_aqc_opc_configure_switching_comp_bw_config,
3763 cmd_details);
3764}
3765
56a62fc8
JB		 3766/**
3767 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3768 * @hw: pointer to the hw struct
3769 * @seid: seid of the VSI
3770 * @bw_data: Buffer to hold VSI BW configuration
3771 * @cmd_details: pointer to command details structure or NULL
3772 **/
3773i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3774 u16 seid,
3775 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3776 struct i40e_asq_cmd_details *cmd_details)
3777{
3778 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3779 i40e_aqc_opc_query_vsi_bw_config,
3780 cmd_details);
3781}
3782
3783/**
3784 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3785 * @hw: pointer to the hw struct
3786 * @seid: seid of the VSI
3787 * @bw_data: Buffer to hold VSI BW configuration per TC
3788 * @cmd_details: pointer to command details structure or NULL
3789 **/
3790i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3791 u16 seid,
3792 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3793 struct i40e_asq_cmd_details *cmd_details)
3794{
3795 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3796 i40e_aqc_opc_query_vsi_ets_sla_config,
3797 cmd_details);
3798}
3799
3800/**
3801 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3802 * @hw: pointer to the hw struct
3803 * @seid: seid of the switching component
3804 * @bw_data: Buffer to hold switching component's per TC BW config
3805 * @cmd_details: pointer to command details structure or NULL
3806 **/
3807i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3808 u16 seid,
3809 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3810 struct i40e_asq_cmd_details *cmd_details)
3811{
3812 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3813 i40e_aqc_opc_query_switching_comp_ets_config,
3814 cmd_details);
3815}
3816
3817/**
3818 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3819 * @hw: pointer to the hw struct
3820 * @seid: seid of the VSI or switching component connected to Physical Port
3821 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3822 * @cmd_details: pointer to command details structure or NULL
3823 **/
3824i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3825 u16 seid,
3826 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3827 struct i40e_asq_cmd_details *cmd_details)
3828{
3829 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3830 i40e_aqc_opc_query_port_ets_config,
3831 cmd_details);
3832}
3833
3834/**
3835 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3836 * @hw: pointer to the hw struct
3837 * @seid: seid of the switching component
3838 * @bw_data: Buffer to hold switching component's BW configuration
3839 * @cmd_details: pointer to command details structure or NULL
3840 **/
3841i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3842 u16 seid,
3843 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3844 struct i40e_asq_cmd_details *cmd_details)
3845{
3846 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3847 i40e_aqc_opc_query_switching_comp_bw_config,
3848 cmd_details);
3849}
3850
3851/**
3852 * i40e_validate_filter_settings
3853 * @hw: pointer to the hardware structure
3854 * @settings: Filter control settings
3855 *
3856 * Check and validate the filter control settings passed.
3857 * The function checks for the valid filter/context sizes being
3858 * passed for FCoE and PE.
3859 *
3860 * Returns 0 if the values passed are valid and within
3861 * range else returns an error.
3862 **/
3863static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3864 struct i40e_filter_control_settings *settings)
3865{
3866 u32 fcoe_cntx_size, fcoe_filt_size;
3867 u32 pe_cntx_size, pe_filt_size;
467d729a 3868 u32 fcoe_fmax;
56a62fc8
JB		 3869 u32 val;
3870
3871 /* Validate FCoE settings passed */
3872 switch (settings->fcoe_filt_num) {
3873 case I40E_HASH_FILTER_SIZE_1K:
3874 case I40E_HASH_FILTER_SIZE_2K:
3875 case I40E_HASH_FILTER_SIZE_4K:
3876 case I40E_HASH_FILTER_SIZE_8K:
3877 case I40E_HASH_FILTER_SIZE_16K:
3878 case I40E_HASH_FILTER_SIZE_32K:
3879 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3880 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3881 break;
3882 default:
3883 return I40E_ERR_PARAM;
3884 }
3885
3886 switch (settings->fcoe_cntx_num) {
3887 case I40E_DMA_CNTX_SIZE_512:
3888 case I40E_DMA_CNTX_SIZE_1K:
3889 case I40E_DMA_CNTX_SIZE_2K:
3890 case I40E_DMA_CNTX_SIZE_4K:
3891 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3892 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3893 break;
3894 default:
3895 return I40E_ERR_PARAM;
3896 }
3897
3898 /* Validate PE settings passed */
3899 switch (settings->pe_filt_num) {
3900 case I40E_HASH_FILTER_SIZE_1K:
3901 case I40E_HASH_FILTER_SIZE_2K:
3902 case I40E_HASH_FILTER_SIZE_4K:
3903 case I40E_HASH_FILTER_SIZE_8K:
3904 case I40E_HASH_FILTER_SIZE_16K:
3905 case I40E_HASH_FILTER_SIZE_32K:
3906 case I40E_HASH_FILTER_SIZE_64K:
3907 case I40E_HASH_FILTER_SIZE_128K:
3908 case I40E_HASH_FILTER_SIZE_256K:
3909 case I40E_HASH_FILTER_SIZE_512K:
3910 case I40E_HASH_FILTER_SIZE_1M:
3911 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3912 pe_filt_size <<= (u32)settings->pe_filt_num;
3913 break;
3914 default:
3915 return I40E_ERR_PARAM;
3916 }
3917
3918 switch (settings->pe_cntx_num) {
3919 case I40E_DMA_CNTX_SIZE_512:
3920 case I40E_DMA_CNTX_SIZE_1K:
3921 case I40E_DMA_CNTX_SIZE_2K:
3922 case I40E_DMA_CNTX_SIZE_4K:
3923 case I40E_DMA_CNTX_SIZE_8K:
3924 case I40E_DMA_CNTX_SIZE_16K:
3925 case I40E_DMA_CNTX_SIZE_32K:
3926 case I40E_DMA_CNTX_SIZE_64K:
3927 case I40E_DMA_CNTX_SIZE_128K:
3928 case I40E_DMA_CNTX_SIZE_256K:
3929 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3930 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3931 break;
3932 default:
3933 return I40E_ERR_PARAM;
3934 }
3935
3936 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3937 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3938 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3939 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3940 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3941 return I40E_ERR_INVALID_SIZE;
3942
56a62fc8
JB		 3943 return 0;
3944}
3945
3946/**
3947 * i40e_set_filter_control
3948 * @hw: pointer to the hardware structure
3949 * @settings: Filter control settings
3950 *
3951 * Set the Queue Filters for PE/FCoE and enable filters required
3952 * for a single PF. It is expected that these settings are programmed
3953 * at the driver initialization time.
3954 **/
3955i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3956 struct i40e_filter_control_settings *settings)
3957{
3958 i40e_status ret = 0;
3959 u32 hash_lut_size = 0;
3960 u32 val;
3961
3962 if (!settings)
3963 return I40E_ERR_PARAM;
3964
3965 /* Validate the input settings */
3966 ret = i40e_validate_filter_settings(hw, settings);
3967 if (ret)
3968 return ret;
3969
3970 /* Read the PF Queue Filter control register */
f658137c 3971 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
56a62fc8
JB		 3972
3973 /* Program required PE hash buckets for the PF */
3974 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3975 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3976 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3977 /* Program required PE contexts for the PF */
3978 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3979 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3980 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3981
3982 /* Program required FCoE hash buckets for the PF */
3983 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3984 val |= ((u32)settings->fcoe_filt_num <<
3985 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3986 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3987 /* Program required FCoE DDP contexts for the PF */
3988 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3989 val |= ((u32)settings->fcoe_cntx_num <<
3990 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3991 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3992
3993 /* Program Hash LUT size for the PF */
3994 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3995 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3996 hash_lut_size = 1;
3997 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3998 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3999
4000 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4001 if (settings->enable_fdir)
4002 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4003 if (settings->enable_ethtype)
4004 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4005 if (settings->enable_macvlan)
4006 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4007
f658137c 4008 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
56a62fc8
JB		 4009
4010 return 0;
4011}
afb3ff0d
NP		 4012
4013/**
4014 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4015 * @hw: pointer to the hw struct
4016 * @mac_addr: MAC address to use in the filter
4017 * @ethtype: Ethertype to use in the filter
4018 * @flags: Flags that needs to be applied to the filter
4019 * @vsi_seid: seid of the control VSI
4020 * @queue: VSI queue number to send the packet to
4021 * @is_add: Add control packet filter if True else remove
4022 * @stats: Structure to hold information on control filter counts
4023 * @cmd_details: pointer to command details structure or NULL
4024 *
4025 * This command will Add or Remove control packet filter for a control VSI.
4026 * In return it will update the total number of perfect filter count in
4027 * the stats member.
4028 **/
4029i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4030 u8 *mac_addr, u16 ethtype, u16 flags,
4031 u16 vsi_seid, u16 queue, bool is_add,
4032 struct i40e_control_filter_stats *stats,
4033 struct i40e_asq_cmd_details *cmd_details)
4034{
4035 struct i40e_aq_desc desc;
4036 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4037 (struct i40e_aqc_add_remove_control_packet_filter *)
4038 &desc.params.raw;
4039 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4040 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4041 &desc.params.raw;
4042 i40e_status status;
4043
4044 if (vsi_seid == 0)
4045 return I40E_ERR_PARAM;
4046
4047 if (is_add) {
4048 i40e_fill_default_direct_cmd_desc(&desc,
4049 i40e_aqc_opc_add_control_packet_filter);
4050 cmd->queue = cpu_to_le16(queue);
4051 } else {
4052 i40e_fill_default_direct_cmd_desc(&desc,
4053 i40e_aqc_opc_remove_control_packet_filter);
4054 }
4055
4056 if (mac_addr)
6995b36c 4057 ether_addr_copy(cmd->mac, mac_addr);
afb3ff0d
NP		 4058
4059 cmd->etype = cpu_to_le16(ethtype);
4060 cmd->flags = cpu_to_le16(flags);
4061 cmd->seid = cpu_to_le16(vsi_seid);
4062
4063 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4064
4065 if (!status && stats) {
4066 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4067 stats->etype_used = le16_to_cpu(resp->etype_used);
4068 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4069 stats->etype_free = le16_to_cpu(resp->etype_free);
4070 }
4071
4072 return status;
4073}
4074
e7358f54
ASJ		 4075/**
4076 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4077 * @hw: pointer to the hw struct
4078 * @seid: VSI seid to add ethertype filter from
4079 **/
4080#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4081void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4082 u16 seid)
4083{
4084 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4085 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4086 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4087 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4088 i40e_status status;
4089
4090 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4091 seid, 0, true, NULL,
4092 NULL);
4093 if (status)
4094 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4095}
4096
f4492db1
GR		 4097/**
4098 * i40e_aq_alternate_read
4099 * @hw: pointer to the hardware structure
4100 * @reg_addr0: address of first dword to be read
4101 * @reg_val0: pointer for data read from 'reg_addr0'
4102 * @reg_addr1: address of second dword to be read
4103 * @reg_val1: pointer for data read from 'reg_addr1'
4104 *
4105 * Read one or two dwords from alternate structure. Fields are indicated
4106 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4107 * is not passed then only register at 'reg_addr0' is read.
4108 *
4109 **/
37a2973a
SN		 4110static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4111 u32 reg_addr0, u32 *reg_val0,
4112 u32 reg_addr1, u32 *reg_val1)
f4492db1
GR		 4113{
4114 struct i40e_aq_desc desc;
4115 struct i40e_aqc_alternate_write *cmd_resp =
4116 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4117 i40e_status status;
4118
4119 if (!reg_val0)
4120 return I40E_ERR_PARAM;
4121
4122 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4123 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4124 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4125
4126 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4127
4128 if (!status) {
4129 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4130
4131 if (reg_val1)
4132 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4133 }
4134
4135 return status;
4136}
4137
2fd75f31
NP		 4138/**
4139 * i40e_aq_resume_port_tx
4140 * @hw: pointer to the hardware structure
4141 * @cmd_details: pointer to command details structure or NULL
4142 *
4143 * Resume port's Tx traffic
4144 **/
4145i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4146 struct i40e_asq_cmd_details *cmd_details)
4147{
4148 struct i40e_aq_desc desc;
4149 i40e_status status;
4150
4151 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4152
4153 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4154
4155 return status;
4156}
4157
d4dfb81a
CS		 4158/**
4159 * i40e_set_pci_config_data - store PCI bus info
4160 * @hw: pointer to hardware structure
4161 * @link_status: the link status word from PCI config space
4162 *
4163 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4164 **/
4165void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4166{
4167 hw->bus.type = i40e_bus_type_pci_express;
4168
4169 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4170 case PCI_EXP_LNKSTA_NLW_X1:
4171 hw->bus.width = i40e_bus_width_pcie_x1;
4172 break;
4173 case PCI_EXP_LNKSTA_NLW_X2:
4174 hw->bus.width = i40e_bus_width_pcie_x2;
4175 break;
4176 case PCI_EXP_LNKSTA_NLW_X4:
4177 hw->bus.width = i40e_bus_width_pcie_x4;
4178 break;
4179 case PCI_EXP_LNKSTA_NLW_X8:
4180 hw->bus.width = i40e_bus_width_pcie_x8;
4181 break;
4182 default:
4183 hw->bus.width = i40e_bus_width_unknown;
4184 break;
4185 }
4186
4187 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4188 case PCI_EXP_LNKSTA_CLS_2_5GB:
4189 hw->bus.speed = i40e_bus_speed_2500;
4190 break;
4191 case PCI_EXP_LNKSTA_CLS_5_0GB:
4192 hw->bus.speed = i40e_bus_speed_5000;
4193 break;
4194 case PCI_EXP_LNKSTA_CLS_8_0GB:
4195 hw->bus.speed = i40e_bus_speed_8000;
4196 break;
4197 default:
4198 hw->bus.speed = i40e_bus_speed_unknown;
4199 break;
4200 }
4201}
f4492db1 4202
3169c323
JB		 4203/**
4204 * i40e_aq_debug_dump
4205 * @hw: pointer to the hardware structure
4206 * @cluster_id: specific cluster to dump
4207 * @table_id: table id within cluster
4208 * @start_index: index of line in the block to read
4209 * @buff_size: dump buffer size
4210 * @buff: dump buffer
4211 * @ret_buff_size: actual buffer size returned
4212 * @ret_next_table: next block to read
4213 * @ret_next_index: next index to read
4214 *
4215 * Dump internal FW/HW data for debug purposes.
4216 *
4217 **/
4218i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4219 u8 table_id, u32 start_index, u16 buff_size,
4220 void *buff, u16 *ret_buff_size,
4221 u8 *ret_next_table, u32 *ret_next_index,
4222 struct i40e_asq_cmd_details *cmd_details)
4223{
4224 struct i40e_aq_desc desc;
4225 struct i40e_aqc_debug_dump_internals *cmd =
4226 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4227 struct i40e_aqc_debug_dump_internals *resp =
4228 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4229 i40e_status status;
4230
4231 if (buff_size == 0 || !buff)
4232 return I40E_ERR_PARAM;
4233
4234 i40e_fill_default_direct_cmd_desc(&desc,
4235 i40e_aqc_opc_debug_dump_internals);
4236 /* Indirect Command */
4237 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4238 if (buff_size > I40E_AQ_LARGE_BUF)
4239 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4240
4241 cmd->cluster_id = cluster_id;
4242 cmd->table_id = table_id;
4243 cmd->idx = cpu_to_le32(start_index);
4244
4245 desc.datalen = cpu_to_le16(buff_size);
4246
4247 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4248 if (!status) {
4249 if (ret_buff_size)
4250 *ret_buff_size = le16_to_cpu(desc.datalen);
4251 if (ret_next_table)
4252 *ret_next_table = resp->table_id;
4253 if (ret_next_index)
4254 *ret_next_index = le32_to_cpu(resp->idx);
4255 }
4256
4257 return status;
4258}
4259
f4492db1
GR		 4260/**
4261 * i40e_read_bw_from_alt_ram
4262 * @hw: pointer to the hardware structure
4263 * @max_bw: pointer for max_bw read
4264 * @min_bw: pointer for min_bw read
4265 * @min_valid: pointer for bool that is true if min_bw is a valid value
4266 * @max_valid: pointer for bool that is true if max_bw is a valid value
4267 *
4268 * Read bw from the alternate ram for the given pf
4269 **/
4270i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4271 u32 *max_bw, u32 *min_bw,
4272 bool *min_valid, bool *max_valid)
4273{
4274 i40e_status status;
4275 u32 max_bw_addr, min_bw_addr;
4276
4277 /* Calculate the address of the min/max bw registers */
4278 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4279 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4280 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4281 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4282 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4283 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4284
4285 /* Read the bandwidths from alt ram */
4286 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4287 min_bw_addr, min_bw);
4288
4289 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4290 *min_valid = true;
4291 else
4292 *min_valid = false;
4293
4294 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4295 *max_valid = true;
4296 else
4297 *max_valid = false;
4298
4299 return status;
4300}
4301
4302/**
4303 * i40e_aq_configure_partition_bw
4304 * @hw: pointer to the hardware structure
4305 * @bw_data: Buffer holding valid pfs and bw limits
4306 * @cmd_details: pointer to command details
4307 *
4308 * Configure partitions guaranteed/max bw
4309 **/
4310i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4311 struct i40e_aqc_configure_partition_bw_data *bw_data,
4312 struct i40e_asq_cmd_details *cmd_details)
4313{
4314 i40e_status status;
4315 struct i40e_aq_desc desc;
4316 u16 bwd_size = sizeof(*bw_data);
4317
4318 i40e_fill_default_direct_cmd_desc(&desc,
4319 i40e_aqc_opc_configure_partition_bw);
4320
4321 /* Indirect command */
4322 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4323 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4324
4325 if (bwd_size > I40E_AQ_LARGE_BUF)
4326 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4327
4328 desc.datalen = cpu_to_le16(bwd_size);
4329
4330 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4331 cmd_details);
4332
4333 return status;
4334}
fd077cd3
CW		 4335
4336/**
4337 * i40e_read_phy_register
4338 * @hw: pointer to the HW structure
4339 * @page: registers page number
4340 * @reg: register address in the page
4341 * @phy_adr: PHY address on MDIO interface
4342 * @value: PHY register value
4343 *
4344 * Reads specified PHY register value
4345 **/
4346i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4347 u8 page, u16 reg, u8 phy_addr,
4348 u16 *value)
4349{
4350 i40e_status status = I40E_ERR_TIMEOUT;
4351 u32 command = 0;
4352 u16 retry = 1000;
4353 u8 port_num = hw->func_caps.mdio_port_num;
4354
4355 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4356 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4357 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4358 (I40E_MDIO_OPCODE_ADDRESS) |
4359 (I40E_MDIO_STCODE) |
4360 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4361 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4362 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4363 do {
4364 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4365 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4366 status = 0;
4367 break;
4368 }
4369 usleep_range(10, 20);
4370 retry--;
4371 } while (retry);
4372
4373 if (status) {
4374 i40e_debug(hw, I40E_DEBUG_PHY,
4375 "PHY: Can't write command to external PHY.\n");
4376 goto phy_read_end;
4377 }
4378
4379 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4380 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4381 (I40E_MDIO_OPCODE_READ) |
4382 (I40E_MDIO_STCODE) |
4383 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4384 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4385 status = I40E_ERR_TIMEOUT;
4386 retry = 1000;
4387 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4388 do {
4389 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4390 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4391 status = 0;
4392 break;
4393 }
4394 usleep_range(10, 20);
4395 retry--;
4396 } while (retry);
4397
4398 if (!status) {
4399 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4400 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4401 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4402 } else {
4403 i40e_debug(hw, I40E_DEBUG_PHY,
4404 "PHY: Can't read register value from external PHY.\n");
4405 }
4406
4407phy_read_end:
4408 return status;
4409}
4410
4411/**
4412 * i40e_write_phy_register
4413 * @hw: pointer to the HW structure
4414 * @page: registers page number
4415 * @reg: register address in the page
4416 * @phy_adr: PHY address on MDIO interface
4417 * @value: PHY register value
4418 *
4419 * Writes value to specified PHY register
4420 **/
4421i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4422 u8 page, u16 reg, u8 phy_addr,
4423 u16 value)
4424{
4425 i40e_status status = I40E_ERR_TIMEOUT;
4426 u32 command = 0;
4427 u16 retry = 1000;
4428 u8 port_num = hw->func_caps.mdio_port_num;
4429
4430 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4431 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4432 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4433 (I40E_MDIO_OPCODE_ADDRESS) |
4434 (I40E_MDIO_STCODE) |
4435 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4436 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4437 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4438 do {
4439 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4440 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4441 status = 0;
4442 break;
4443 }
4444 usleep_range(10, 20);
4445 retry--;
4446 } while (retry);
4447 if (status) {
4448 i40e_debug(hw, I40E_DEBUG_PHY,
4449 "PHY: Can't write command to external PHY.\n");
4450 goto phy_write_end;
4451 }
4452
4453 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4454 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4455
4456 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4457 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4458 (I40E_MDIO_OPCODE_WRITE) |
4459 (I40E_MDIO_STCODE) |
4460 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4461 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4462 status = I40E_ERR_TIMEOUT;
4463 retry = 1000;
4464 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4465 do {
4466 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4467 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4468 status = 0;
4469 break;
4470 }
4471 usleep_range(10, 20);
4472 retry--;
4473 } while (retry);
4474
4475phy_write_end:
4476 return status;
4477}
4478
4479/**
4480 * i40e_get_phy_address
4481 * @hw: pointer to the HW structure
4482 * @dev_num: PHY port num that address we want
4483 * @phy_addr: Returned PHY address
4484 *
4485 * Gets PHY address for current port
4486 **/
4487u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4488{
4489 u8 port_num = hw->func_caps.mdio_port_num;
4490 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4491
4492 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4493}
4494
4495/**
4496 * i40e_blink_phy_led
4497 * @hw: pointer to the HW structure
4498 * @time: time how long led will blinks in secs
4499 * @interval: gap between LED on and off in msecs
4500 *
4501 * Blinks PHY link LED
4502 **/
4503i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4504 u32 time, u32 interval)
4505{
4506 i40e_status status = 0;
4507 u32 i;
4508 u16 led_ctl;
4509 u16 gpio_led_port;
4510 u16 led_reg;
4511 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4512 u8 phy_addr = 0;
4513 u8 port_num;
4514
4515 i = rd32(hw, I40E_PFGEN_PORTNUM);
4516 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4517 phy_addr = i40e_get_phy_address(hw, port_num);
4518
4519 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4520 led_addr++) {
4521 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4522 led_addr, phy_addr, &led_reg);
4523 if (status)
4524 goto phy_blinking_end;
4525 led_ctl = led_reg;
4526 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4527 led_reg = 0;
4528 status = i40e_write_phy_register(hw,
4529 I40E_PHY_COM_REG_PAGE,
4530 led_addr, phy_addr,
4531 led_reg);
4532 if (status)
4533 goto phy_blinking_end;
4534 break;
4535 }
4536 }
4537
4538 if (time > 0 && interval > 0) {
4539 for (i = 0; i < time * 1000; i += interval) {
4540 status = i40e_read_phy_register(hw,
4541 I40E_PHY_COM_REG_PAGE,
4542 led_addr, phy_addr,
4543 &led_reg);
4544 if (status)
4545 goto restore_config;
4546 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4547 led_reg = 0;
4548 else
4549 led_reg = I40E_PHY_LED_MANUAL_ON;
4550 status = i40e_write_phy_register(hw,
4551 I40E_PHY_COM_REG_PAGE,
4552 led_addr, phy_addr,
4553 led_reg);
4554 if (status)
4555 goto restore_config;
4556 msleep(interval);
4557 }
4558 }
4559
4560restore_config:
4561 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4562 phy_addr, led_ctl);
4563
4564phy_blinking_end:
4565 return status;
4566}
4567
4568/**
4569 * i40e_led_get_phy - return current on/off mode
4570 * @hw: pointer to the hw struct
4571 * @led_addr: address of led register to use
4572 * @val: original value of register to use
4573 *
4574 **/
4575i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4576 u16 *val)
4577{
4578 i40e_status status = 0;
4579 u16 gpio_led_port;
4580 u8 phy_addr = 0;
4581 u16 reg_val;
4582 u16 temp_addr;
4583 u8 port_num;
4584 u32 i;
4585
4586 temp_addr = I40E_PHY_LED_PROV_REG_1;
4587 i = rd32(hw, I40E_PFGEN_PORTNUM);
4588 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4589 phy_addr = i40e_get_phy_address(hw, port_num);
4590
4591 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4592 temp_addr++) {
4593 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4594 temp_addr, phy_addr, &reg_val);
4595 if (status)
4596 return status;
4597 *val = reg_val;
4598 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4599 *led_addr = temp_addr;
4600 break;
4601 }
4602 }
4603 return status;
4604}
4605
4606/**
4607 * i40e_led_set_phy
4608 * @hw: pointer to the HW structure
4609 * @on: true or false
4610 * @mode: original val plus bit for set or ignore
4611 * Set led's on or off when controlled by the PHY
4612 *
4613 **/
4614i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4615 u16 led_addr, u32 mode)
4616{
4617 i40e_status status = 0;
4618 u16 led_ctl = 0;
4619 u16 led_reg = 0;
4620 u8 phy_addr = 0;
4621 u8 port_num;
4622 u32 i;
4623
4624 i = rd32(hw, I40E_PFGEN_PORTNUM);
4625 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4626 phy_addr = i40e_get_phy_address(hw, port_num);
4627
4628 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4629 phy_addr, &led_reg);
4630 if (status)
4631 return status;
4632 led_ctl = led_reg;
4633 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4634 led_reg = 0;
4635 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4636 led_addr, phy_addr, led_reg);
4637 if (status)
4638 return status;
4639 }
4640 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4641 led_addr, phy_addr, &led_reg);
4642 if (status)
4643 goto restore_config;
4644 if (on)
4645 led_reg = I40E_PHY_LED_MANUAL_ON;
4646 else
4647 led_reg = 0;
4648 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4649 led_addr, phy_addr, led_reg);
4650 if (status)
4651 goto restore_config;
4652 if (mode & I40E_PHY_LED_MODE_ORIG) {
4653 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4654 status = i40e_write_phy_register(hw,
4655 I40E_PHY_COM_REG_PAGE,
4656 led_addr, phy_addr, led_ctl);
4657 }
4658 return status;
4659restore_config:
4660 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4661 phy_addr, led_ctl);
4662 return status;
4663}
f658137c
SN		 4664
4665/**
4666 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4667 * @hw: pointer to the hw struct
4668 * @reg_addr: register address
4669 * @reg_val: ptr to register value
4670 * @cmd_details: pointer to command details structure or NULL
4671 *
4672 * Use the firmware to read the Rx control register,
4673 * especially useful if the Rx unit is under heavy pressure
4674 **/
4675i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4676 u32 reg_addr, u32 *reg_val,
4677 struct i40e_asq_cmd_details *cmd_details)
4678{
4679 struct i40e_aq_desc desc;
4680 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4681 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4682 i40e_status status;
4683
4684 if (!reg_val)
4685 return I40E_ERR_PARAM;
4686
4687 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4688
4689 cmd_resp->address = cpu_to_le32(reg_addr);
4690
4691 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4692
4693 if (status == 0)
4694 *reg_val = le32_to_cpu(cmd_resp->value);
4695
4696 return status;
4697}
4698
4699/**
4700 * i40e_read_rx_ctl - read from an Rx control register
4701 * @hw: pointer to the hw struct
4702 * @reg_addr: register address
4703 **/
4704u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4705{
4706 i40e_status status = 0;
4707 bool use_register;
4708 int retry = 5;
4709 u32 val = 0;
4710
4711 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4712 if (!use_register) {
4713do_retry:
4714 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4715 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4716 usleep_range(1000, 2000);
4717 retry--;
4718 goto do_retry;
4719 }
4720 }
4721
4722 /* if the AQ access failed, try the old-fashioned way */
4723 if (status || use_register)
4724 val = rd32(hw, reg_addr);
4725
4726 return val;
4727}
4728
4729/**
4730 * i40e_aq_rx_ctl_write_register
4731 * @hw: pointer to the hw struct
4732 * @reg_addr: register address
4733 * @reg_val: register value
4734 * @cmd_details: pointer to command details structure or NULL
4735 *
4736 * Use the firmware to write to an Rx control register,
4737 * especially useful if the Rx unit is under heavy pressure
4738 **/
4739i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4740 u32 reg_addr, u32 reg_val,
4741 struct i40e_asq_cmd_details *cmd_details)
4742{
4743 struct i40e_aq_desc desc;
4744 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4745 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4746 i40e_status status;
4747
4748 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4749
4750 cmd->address = cpu_to_le32(reg_addr);
4751 cmd->value = cpu_to_le32(reg_val);
4752
4753 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4754
4755 return status;
4756}
4757
4758/**
4759 * i40e_write_rx_ctl - write to an Rx control register
4760 * @hw: pointer to the hw struct
4761 * @reg_addr: register address
4762 * @reg_val: register value
4763 **/
4764void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
4765{
4766 i40e_status status = 0;
4767 bool use_register;
4768 int retry = 5;
4769
4770 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4771 if (!use_register) {
4772do_retry:
4773 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
4774 reg_val, NULL);
4775 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4776 usleep_range(1000, 2000);
4777 retry--;
4778 goto do_retry;
4779 }
4780 }
4781
4782 /* if the AQ access failed, try the old-fashioned way */
4783 if (status || use_register)
4784 wr32(hw, reg_addr, reg_val);
4785}
Linux kernel - Deliverables
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