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56a62fc8 JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
f1abd7db | 4 | * Copyright(c) 2013 - 2015 Intel Corporation. |
56a62fc8 JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
56a62fc8 JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
27 | #include "i40e_type.h" | |
28 | #include "i40e_adminq.h" | |
29 | #include "i40e_prototype.h" | |
30 | #include "i40e_virtchnl.h" | |
31 | ||
32 | /** | |
33 | * i40e_set_mac_type - Sets MAC type | |
34 | * @hw: pointer to the HW structure | |
35 | * | |
36 | * This function sets the mac type of the adapter based on the | |
37 | * vendor ID and device ID stored in the hw structure. | |
38 | **/ | |
39 | static i40e_status i40e_set_mac_type(struct i40e_hw *hw) | |
40 | { | |
41 | i40e_status status = 0; | |
42 | ||
43 | if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { | |
44 | switch (hw->device_id) { | |
ab60085e | 45 | case I40E_DEV_ID_SFP_XL710: |
ab60085e SN |
46 | case I40E_DEV_ID_QEMU: |
47 | case I40E_DEV_ID_KX_A: | |
48 | case I40E_DEV_ID_KX_B: | |
49 | case I40E_DEV_ID_KX_C: | |
ab60085e SN |
50 | case I40E_DEV_ID_QSFP_A: |
51 | case I40E_DEV_ID_QSFP_B: | |
52 | case I40E_DEV_ID_QSFP_C: | |
5960d33f | 53 | case I40E_DEV_ID_10G_BASE_T: |
ae24b409 | 54 | case I40E_DEV_ID_20G_KR2: |
56a62fc8 JB |
55 | hw->mac.type = I40E_MAC_XL710; |
56 | break; | |
ab60085e SN |
57 | case I40E_DEV_ID_VF: |
58 | case I40E_DEV_ID_VF_HV: | |
56a62fc8 JB |
59 | hw->mac.type = I40E_MAC_VF; |
60 | break; | |
61 | default: | |
62 | hw->mac.type = I40E_MAC_GENERIC; | |
63 | break; | |
64 | } | |
65 | } else { | |
66 | status = I40E_ERR_DEVICE_NOT_SUPPORTED; | |
67 | } | |
68 | ||
69 | hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", | |
70 | hw->mac.type, status); | |
71 | return status; | |
72 | } | |
73 | ||
74 | /** | |
75 | * i40e_debug_aq | |
76 | * @hw: debug mask related to admin queue | |
98d44381 JK |
77 | * @mask: debug mask |
78 | * @desc: pointer to admin queue descriptor | |
56a62fc8 | 79 | * @buffer: pointer to command buffer |
f905dd62 | 80 | * @buf_len: max length of buffer |
56a62fc8 JB |
81 | * |
82 | * Dumps debug log about adminq command with descriptor contents. | |
83 | **/ | |
84 | void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, | |
f905dd62 | 85 | void *buffer, u16 buf_len) |
56a62fc8 JB |
86 | { |
87 | struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; | |
f905dd62 | 88 | u16 len = le16_to_cpu(aq_desc->datalen); |
37a2973a SN |
89 | u8 *buf = (u8 *)buffer; |
90 | u16 i = 0; | |
56a62fc8 JB |
91 | |
92 | if ((!(mask & hw->debug_mask)) || (desc == NULL)) | |
93 | return; | |
94 | ||
95 | i40e_debug(hw, mask, | |
96 | "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", | |
f1abd7db PSJ |
97 | le16_to_cpu(aq_desc->opcode), |
98 | le16_to_cpu(aq_desc->flags), | |
99 | le16_to_cpu(aq_desc->datalen), | |
100 | le16_to_cpu(aq_desc->retval)); | |
56a62fc8 | 101 | i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", |
f1abd7db PSJ |
102 | le32_to_cpu(aq_desc->cookie_high), |
103 | le32_to_cpu(aq_desc->cookie_low)); | |
56a62fc8 | 104 | i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", |
f1abd7db PSJ |
105 | le32_to_cpu(aq_desc->params.internal.param0), |
106 | le32_to_cpu(aq_desc->params.internal.param1)); | |
56a62fc8 | 107 | i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", |
f1abd7db PSJ |
108 | le32_to_cpu(aq_desc->params.external.addr_high), |
109 | le32_to_cpu(aq_desc->params.external.addr_low)); | |
56a62fc8 JB |
110 | |
111 | if ((buffer != NULL) && (aq_desc->datalen != 0)) { | |
56a62fc8 | 112 | i40e_debug(hw, mask, "AQ CMD Buffer:\n"); |
f905dd62 SN |
113 | if (buf_len < len) |
114 | len = buf_len; | |
37a2973a SN |
115 | /* write the full 16-byte chunks */ |
116 | for (i = 0; i < (len - 16); i += 16) | |
117 | i40e_debug(hw, mask, | |
118 | "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", | |
119 | i, buf[i], buf[i + 1], buf[i + 2], | |
120 | buf[i + 3], buf[i + 4], buf[i + 5], | |
121 | buf[i + 6], buf[i + 7], buf[i + 8], | |
122 | buf[i + 9], buf[i + 10], buf[i + 11], | |
123 | buf[i + 12], buf[i + 13], buf[i + 14], | |
124 | buf[i + 15]); | |
125 | /* write whatever's left over without overrunning the buffer */ | |
126 | if (i < len) { | |
127 | char d_buf[80]; | |
128 | int j = 0; | |
129 | ||
130 | memset(d_buf, 0, sizeof(d_buf)); | |
131 | j += sprintf(d_buf, "\t0x%04X ", i); | |
132 | while (i < len) | |
133 | j += sprintf(&d_buf[j], " %02X", buf[i++]); | |
134 | i40e_debug(hw, mask, "%s\n", d_buf); | |
56a62fc8 | 135 | } |
56a62fc8 JB |
136 | } |
137 | } | |
138 | ||
e1860d8f ASJ |
139 | /** |
140 | * i40e_check_asq_alive | |
141 | * @hw: pointer to the hw struct | |
142 | * | |
143 | * Returns true if Queue is enabled else false. | |
144 | **/ | |
145 | bool i40e_check_asq_alive(struct i40e_hw *hw) | |
146 | { | |
8b833b4f KS |
147 | if (hw->aq.asq.len) |
148 | return !!(rd32(hw, hw->aq.asq.len) & | |
149 | I40E_PF_ATQLEN_ATQENABLE_MASK); | |
150 | else | |
151 | return false; | |
e1860d8f ASJ |
152 | } |
153 | ||
154 | /** | |
155 | * i40e_aq_queue_shutdown | |
156 | * @hw: pointer to the hw struct | |
157 | * @unloading: is the driver unloading itself | |
158 | * | |
159 | * Tell the Firmware that we're shutting down the AdminQ and whether | |
160 | * or not the driver is unloading as well. | |
161 | **/ | |
162 | i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, | |
163 | bool unloading) | |
164 | { | |
165 | struct i40e_aq_desc desc; | |
166 | struct i40e_aqc_queue_shutdown *cmd = | |
167 | (struct i40e_aqc_queue_shutdown *)&desc.params.raw; | |
168 | i40e_status status; | |
169 | ||
170 | i40e_fill_default_direct_cmd_desc(&desc, | |
171 | i40e_aqc_opc_queue_shutdown); | |
172 | ||
173 | if (unloading) | |
174 | cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); | |
175 | status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); | |
176 | ||
177 | return status; | |
178 | } | |
179 | ||
206812b5 JB |
180 | /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the |
181 | * hardware to a bit-field that can be used by SW to more easily determine the | |
182 | * packet type. | |
183 | * | |
184 | * Macros are used to shorten the table lines and make this table human | |
185 | * readable. | |
186 | * | |
187 | * We store the PTYPE in the top byte of the bit field - this is just so that | |
188 | * we can check that the table doesn't have a row missing, as the index into | |
189 | * the table should be the PTYPE. | |
190 | * | |
191 | * Typical work flow: | |
192 | * | |
193 | * IF NOT i40e_ptype_lookup[ptype].known | |
194 | * THEN | |
195 | * Packet is unknown | |
196 | * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP | |
197 | * Use the rest of the fields to look at the tunnels, inner protocols, etc | |
198 | * ELSE | |
199 | * Use the enum i40e_rx_l2_ptype to decode the packet type | |
200 | * ENDIF | |
201 | */ | |
202 | ||
203 | /* macro to make the table lines short */ | |
204 | #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ | |
205 | { PTYPE, \ | |
206 | 1, \ | |
207 | I40E_RX_PTYPE_OUTER_##OUTER_IP, \ | |
208 | I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ | |
209 | I40E_RX_PTYPE_##OUTER_FRAG, \ | |
210 | I40E_RX_PTYPE_TUNNEL_##T, \ | |
211 | I40E_RX_PTYPE_TUNNEL_END_##TE, \ | |
212 | I40E_RX_PTYPE_##TEF, \ | |
213 | I40E_RX_PTYPE_INNER_PROT_##I, \ | |
214 | I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } | |
215 | ||
216 | #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ | |
217 | { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | |
218 | ||
219 | /* shorter macros makes the table fit but are terse */ | |
220 | #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG | |
221 | #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG | |
222 | #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC | |
223 | ||
224 | /* Lookup table mapping the HW PTYPE to the bit field for decoding */ | |
225 | struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { | |
226 | /* L2 Packet types */ | |
227 | I40E_PTT_UNUSED_ENTRY(0), | |
228 | I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), | |
229 | I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), | |
230 | I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), | |
231 | I40E_PTT_UNUSED_ENTRY(4), | |
232 | I40E_PTT_UNUSED_ENTRY(5), | |
233 | I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), | |
234 | I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), | |
235 | I40E_PTT_UNUSED_ENTRY(8), | |
236 | I40E_PTT_UNUSED_ENTRY(9), | |
237 | I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), | |
238 | I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), | |
239 | I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
240 | I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
241 | I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
242 | I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
243 | I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
244 | I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
245 | I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
246 | I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
247 | I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
248 | I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), | |
249 | ||
250 | /* Non Tunneled IPv4 */ | |
251 | I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), | |
252 | I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), | |
253 | I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), | |
254 | I40E_PTT_UNUSED_ENTRY(25), | |
255 | I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), | |
256 | I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), | |
257 | I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), | |
258 | ||
259 | /* IPv4 --> IPv4 */ | |
260 | I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), | |
261 | I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), | |
262 | I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), | |
263 | I40E_PTT_UNUSED_ENTRY(32), | |
264 | I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), | |
265 | I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), | |
266 | I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), | |
267 | ||
268 | /* IPv4 --> IPv6 */ | |
269 | I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), | |
270 | I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), | |
271 | I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), | |
272 | I40E_PTT_UNUSED_ENTRY(39), | |
273 | I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), | |
274 | I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), | |
275 | I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), | |
276 | ||
277 | /* IPv4 --> GRE/NAT */ | |
278 | I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), | |
279 | ||
280 | /* IPv4 --> GRE/NAT --> IPv4 */ | |
281 | I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), | |
282 | I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), | |
283 | I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), | |
284 | I40E_PTT_UNUSED_ENTRY(47), | |
285 | I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), | |
286 | I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), | |
287 | I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), | |
288 | ||
289 | /* IPv4 --> GRE/NAT --> IPv6 */ | |
290 | I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), | |
291 | I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), | |
292 | I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), | |
293 | I40E_PTT_UNUSED_ENTRY(54), | |
294 | I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), | |
295 | I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), | |
296 | I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), | |
297 | ||
298 | /* IPv4 --> GRE/NAT --> MAC */ | |
299 | I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), | |
300 | ||
301 | /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ | |
302 | I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), | |
303 | I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), | |
304 | I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), | |
305 | I40E_PTT_UNUSED_ENTRY(62), | |
306 | I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), | |
307 | I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), | |
308 | I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), | |
309 | ||
310 | /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ | |
311 | I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), | |
312 | I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), | |
313 | I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), | |
314 | I40E_PTT_UNUSED_ENTRY(69), | |
315 | I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), | |
316 | I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), | |
317 | I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), | |
318 | ||
319 | /* IPv4 --> GRE/NAT --> MAC/VLAN */ | |
320 | I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), | |
321 | ||
322 | /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ | |
323 | I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), | |
324 | I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), | |
325 | I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), | |
326 | I40E_PTT_UNUSED_ENTRY(77), | |
327 | I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), | |
328 | I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), | |
329 | I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), | |
330 | ||
331 | /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ | |
332 | I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), | |
333 | I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), | |
334 | I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), | |
335 | I40E_PTT_UNUSED_ENTRY(84), | |
336 | I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), | |
337 | I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), | |
338 | I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), | |
339 | ||
340 | /* Non Tunneled IPv6 */ | |
341 | I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), | |
342 | I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), | |
343 | I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), | |
344 | I40E_PTT_UNUSED_ENTRY(91), | |
345 | I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), | |
346 | I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), | |
347 | I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), | |
348 | ||
349 | /* IPv6 --> IPv4 */ | |
350 | I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), | |
351 | I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), | |
352 | I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), | |
353 | I40E_PTT_UNUSED_ENTRY(98), | |
354 | I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), | |
355 | I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), | |
356 | I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), | |
357 | ||
358 | /* IPv6 --> IPv6 */ | |
359 | I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), | |
360 | I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), | |
361 | I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), | |
362 | I40E_PTT_UNUSED_ENTRY(105), | |
363 | I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), | |
364 | I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), | |
365 | I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), | |
366 | ||
367 | /* IPv6 --> GRE/NAT */ | |
368 | I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), | |
369 | ||
370 | /* IPv6 --> GRE/NAT -> IPv4 */ | |
371 | I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), | |
372 | I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), | |
373 | I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), | |
374 | I40E_PTT_UNUSED_ENTRY(113), | |
375 | I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), | |
376 | I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), | |
377 | I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), | |
378 | ||
379 | /* IPv6 --> GRE/NAT -> IPv6 */ | |
380 | I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), | |
381 | I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), | |
382 | I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), | |
383 | I40E_PTT_UNUSED_ENTRY(120), | |
384 | I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), | |
385 | I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), | |
386 | I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), | |
387 | ||
388 | /* IPv6 --> GRE/NAT -> MAC */ | |
389 | I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), | |
390 | ||
391 | /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ | |
392 | I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), | |
393 | I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), | |
394 | I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), | |
395 | I40E_PTT_UNUSED_ENTRY(128), | |
396 | I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), | |
397 | I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), | |
398 | I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), | |
399 | ||
400 | /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ | |
401 | I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), | |
402 | I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), | |
403 | I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), | |
404 | I40E_PTT_UNUSED_ENTRY(135), | |
405 | I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), | |
406 | I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), | |
407 | I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), | |
408 | ||
409 | /* IPv6 --> GRE/NAT -> MAC/VLAN */ | |
410 | I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), | |
411 | ||
412 | /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ | |
413 | I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), | |
414 | I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), | |
415 | I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), | |
416 | I40E_PTT_UNUSED_ENTRY(143), | |
417 | I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), | |
418 | I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), | |
419 | I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), | |
420 | ||
421 | /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ | |
422 | I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), | |
423 | I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), | |
424 | I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), | |
425 | I40E_PTT_UNUSED_ENTRY(150), | |
426 | I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), | |
427 | I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), | |
428 | I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), | |
429 | ||
430 | /* unused entries */ | |
431 | I40E_PTT_UNUSED_ENTRY(154), | |
432 | I40E_PTT_UNUSED_ENTRY(155), | |
433 | I40E_PTT_UNUSED_ENTRY(156), | |
434 | I40E_PTT_UNUSED_ENTRY(157), | |
435 | I40E_PTT_UNUSED_ENTRY(158), | |
436 | I40E_PTT_UNUSED_ENTRY(159), | |
437 | ||
438 | I40E_PTT_UNUSED_ENTRY(160), | |
439 | I40E_PTT_UNUSED_ENTRY(161), | |
440 | I40E_PTT_UNUSED_ENTRY(162), | |
441 | I40E_PTT_UNUSED_ENTRY(163), | |
442 | I40E_PTT_UNUSED_ENTRY(164), | |
443 | I40E_PTT_UNUSED_ENTRY(165), | |
444 | I40E_PTT_UNUSED_ENTRY(166), | |
445 | I40E_PTT_UNUSED_ENTRY(167), | |
446 | I40E_PTT_UNUSED_ENTRY(168), | |
447 | I40E_PTT_UNUSED_ENTRY(169), | |
448 | ||
449 | I40E_PTT_UNUSED_ENTRY(170), | |
450 | I40E_PTT_UNUSED_ENTRY(171), | |
451 | I40E_PTT_UNUSED_ENTRY(172), | |
452 | I40E_PTT_UNUSED_ENTRY(173), | |
453 | I40E_PTT_UNUSED_ENTRY(174), | |
454 | I40E_PTT_UNUSED_ENTRY(175), | |
455 | I40E_PTT_UNUSED_ENTRY(176), | |
456 | I40E_PTT_UNUSED_ENTRY(177), | |
457 | I40E_PTT_UNUSED_ENTRY(178), | |
458 | I40E_PTT_UNUSED_ENTRY(179), | |
459 | ||
460 | I40E_PTT_UNUSED_ENTRY(180), | |
461 | I40E_PTT_UNUSED_ENTRY(181), | |
462 | I40E_PTT_UNUSED_ENTRY(182), | |
463 | I40E_PTT_UNUSED_ENTRY(183), | |
464 | I40E_PTT_UNUSED_ENTRY(184), | |
465 | I40E_PTT_UNUSED_ENTRY(185), | |
466 | I40E_PTT_UNUSED_ENTRY(186), | |
467 | I40E_PTT_UNUSED_ENTRY(187), | |
468 | I40E_PTT_UNUSED_ENTRY(188), | |
469 | I40E_PTT_UNUSED_ENTRY(189), | |
470 | ||
471 | I40E_PTT_UNUSED_ENTRY(190), | |
472 | I40E_PTT_UNUSED_ENTRY(191), | |
473 | I40E_PTT_UNUSED_ENTRY(192), | |
474 | I40E_PTT_UNUSED_ENTRY(193), | |
475 | I40E_PTT_UNUSED_ENTRY(194), | |
476 | I40E_PTT_UNUSED_ENTRY(195), | |
477 | I40E_PTT_UNUSED_ENTRY(196), | |
478 | I40E_PTT_UNUSED_ENTRY(197), | |
479 | I40E_PTT_UNUSED_ENTRY(198), | |
480 | I40E_PTT_UNUSED_ENTRY(199), | |
481 | ||
482 | I40E_PTT_UNUSED_ENTRY(200), | |
483 | I40E_PTT_UNUSED_ENTRY(201), | |
484 | I40E_PTT_UNUSED_ENTRY(202), | |
485 | I40E_PTT_UNUSED_ENTRY(203), | |
486 | I40E_PTT_UNUSED_ENTRY(204), | |
487 | I40E_PTT_UNUSED_ENTRY(205), | |
488 | I40E_PTT_UNUSED_ENTRY(206), | |
489 | I40E_PTT_UNUSED_ENTRY(207), | |
490 | I40E_PTT_UNUSED_ENTRY(208), | |
491 | I40E_PTT_UNUSED_ENTRY(209), | |
492 | ||
493 | I40E_PTT_UNUSED_ENTRY(210), | |
494 | I40E_PTT_UNUSED_ENTRY(211), | |
495 | I40E_PTT_UNUSED_ENTRY(212), | |
496 | I40E_PTT_UNUSED_ENTRY(213), | |
497 | I40E_PTT_UNUSED_ENTRY(214), | |
498 | I40E_PTT_UNUSED_ENTRY(215), | |
499 | I40E_PTT_UNUSED_ENTRY(216), | |
500 | I40E_PTT_UNUSED_ENTRY(217), | |
501 | I40E_PTT_UNUSED_ENTRY(218), | |
502 | I40E_PTT_UNUSED_ENTRY(219), | |
503 | ||
504 | I40E_PTT_UNUSED_ENTRY(220), | |
505 | I40E_PTT_UNUSED_ENTRY(221), | |
506 | I40E_PTT_UNUSED_ENTRY(222), | |
507 | I40E_PTT_UNUSED_ENTRY(223), | |
508 | I40E_PTT_UNUSED_ENTRY(224), | |
509 | I40E_PTT_UNUSED_ENTRY(225), | |
510 | I40E_PTT_UNUSED_ENTRY(226), | |
511 | I40E_PTT_UNUSED_ENTRY(227), | |
512 | I40E_PTT_UNUSED_ENTRY(228), | |
513 | I40E_PTT_UNUSED_ENTRY(229), | |
514 | ||
515 | I40E_PTT_UNUSED_ENTRY(230), | |
516 | I40E_PTT_UNUSED_ENTRY(231), | |
517 | I40E_PTT_UNUSED_ENTRY(232), | |
518 | I40E_PTT_UNUSED_ENTRY(233), | |
519 | I40E_PTT_UNUSED_ENTRY(234), | |
520 | I40E_PTT_UNUSED_ENTRY(235), | |
521 | I40E_PTT_UNUSED_ENTRY(236), | |
522 | I40E_PTT_UNUSED_ENTRY(237), | |
523 | I40E_PTT_UNUSED_ENTRY(238), | |
524 | I40E_PTT_UNUSED_ENTRY(239), | |
525 | ||
526 | I40E_PTT_UNUSED_ENTRY(240), | |
527 | I40E_PTT_UNUSED_ENTRY(241), | |
528 | I40E_PTT_UNUSED_ENTRY(242), | |
529 | I40E_PTT_UNUSED_ENTRY(243), | |
530 | I40E_PTT_UNUSED_ENTRY(244), | |
531 | I40E_PTT_UNUSED_ENTRY(245), | |
532 | I40E_PTT_UNUSED_ENTRY(246), | |
533 | I40E_PTT_UNUSED_ENTRY(247), | |
534 | I40E_PTT_UNUSED_ENTRY(248), | |
535 | I40E_PTT_UNUSED_ENTRY(249), | |
536 | ||
537 | I40E_PTT_UNUSED_ENTRY(250), | |
538 | I40E_PTT_UNUSED_ENTRY(251), | |
539 | I40E_PTT_UNUSED_ENTRY(252), | |
540 | I40E_PTT_UNUSED_ENTRY(253), | |
541 | I40E_PTT_UNUSED_ENTRY(254), | |
542 | I40E_PTT_UNUSED_ENTRY(255) | |
543 | }; | |
544 | ||
56a62fc8 JB |
545 | /** |
546 | * i40e_init_shared_code - Initialize the shared code | |
547 | * @hw: pointer to hardware structure | |
548 | * | |
549 | * This assigns the MAC type and PHY code and inits the NVM. | |
550 | * Does not touch the hardware. This function must be called prior to any | |
551 | * other function in the shared code. The i40e_hw structure should be | |
552 | * memset to 0 prior to calling this function. The following fields in | |
553 | * hw structure should be filled in prior to calling this function: | |
554 | * hw_addr, back, device_id, vendor_id, subsystem_device_id, | |
555 | * subsystem_vendor_id, and revision_id | |
556 | **/ | |
557 | i40e_status i40e_init_shared_code(struct i40e_hw *hw) | |
558 | { | |
559 | i40e_status status = 0; | |
5fb11d76 | 560 | u32 port, ari, func_rid; |
56a62fc8 | 561 | |
56a62fc8 JB |
562 | i40e_set_mac_type(hw); |
563 | ||
564 | switch (hw->mac.type) { | |
565 | case I40E_MAC_XL710: | |
566 | break; | |
567 | default: | |
568 | return I40E_ERR_DEVICE_NOT_SUPPORTED; | |
56a62fc8 JB |
569 | } |
570 | ||
af89d26c SN |
571 | hw->phy.get_link_info = true; |
572 | ||
5fb11d76 SN |
573 | /* Determine port number and PF number*/ |
574 | port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) | |
575 | >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; | |
576 | hw->port = (u8)port; | |
577 | ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> | |
578 | I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; | |
579 | func_rid = rd32(hw, I40E_PF_FUNC_RID); | |
580 | if (ari) | |
581 | hw->pf_id = (u8)(func_rid & 0xff); | |
5f9116ac | 582 | else |
5fb11d76 | 583 | hw->pf_id = (u8)(func_rid & 0x7); |
5f9116ac | 584 | |
56a62fc8 JB |
585 | status = i40e_init_nvm(hw); |
586 | return status; | |
587 | } | |
588 | ||
589 | /** | |
590 | * i40e_aq_mac_address_read - Retrieve the MAC addresses | |
591 | * @hw: pointer to the hw struct | |
592 | * @flags: a return indicator of what addresses were added to the addr store | |
593 | * @addrs: the requestor's mac addr store | |
594 | * @cmd_details: pointer to command details structure or NULL | |
595 | **/ | |
596 | static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, | |
597 | u16 *flags, | |
598 | struct i40e_aqc_mac_address_read_data *addrs, | |
599 | struct i40e_asq_cmd_details *cmd_details) | |
600 | { | |
601 | struct i40e_aq_desc desc; | |
602 | struct i40e_aqc_mac_address_read *cmd_data = | |
603 | (struct i40e_aqc_mac_address_read *)&desc.params.raw; | |
604 | i40e_status status; | |
605 | ||
606 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); | |
607 | desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); | |
608 | ||
609 | status = i40e_asq_send_command(hw, &desc, addrs, | |
610 | sizeof(*addrs), cmd_details); | |
611 | *flags = le16_to_cpu(cmd_data->command_flags); | |
612 | ||
613 | return status; | |
614 | } | |
615 | ||
616 | /** | |
617 | * i40e_aq_mac_address_write - Change the MAC addresses | |
618 | * @hw: pointer to the hw struct | |
619 | * @flags: indicates which MAC to be written | |
620 | * @mac_addr: address to write | |
621 | * @cmd_details: pointer to command details structure or NULL | |
622 | **/ | |
623 | i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, | |
624 | u16 flags, u8 *mac_addr, | |
625 | struct i40e_asq_cmd_details *cmd_details) | |
626 | { | |
627 | struct i40e_aq_desc desc; | |
628 | struct i40e_aqc_mac_address_write *cmd_data = | |
629 | (struct i40e_aqc_mac_address_write *)&desc.params.raw; | |
630 | i40e_status status; | |
631 | ||
632 | i40e_fill_default_direct_cmd_desc(&desc, | |
633 | i40e_aqc_opc_mac_address_write); | |
634 | cmd_data->command_flags = cpu_to_le16(flags); | |
55c29c31 KK |
635 | cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); |
636 | cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | | |
637 | ((u32)mac_addr[3] << 16) | | |
638 | ((u32)mac_addr[4] << 8) | | |
639 | mac_addr[5]); | |
56a62fc8 JB |
640 | |
641 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
642 | ||
643 | return status; | |
644 | } | |
645 | ||
646 | /** | |
647 | * i40e_get_mac_addr - get MAC address | |
648 | * @hw: pointer to the HW structure | |
649 | * @mac_addr: pointer to MAC address | |
650 | * | |
651 | * Reads the adapter's MAC address from register | |
652 | **/ | |
653 | i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) | |
654 | { | |
655 | struct i40e_aqc_mac_address_read_data addrs; | |
656 | i40e_status status; | |
657 | u16 flags = 0; | |
658 | ||
659 | status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); | |
660 | ||
661 | if (flags & I40E_AQC_LAN_ADDR_VALID) | |
662 | memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); | |
663 | ||
664 | return status; | |
665 | } | |
666 | ||
1f224ad2 NP |
667 | /** |
668 | * i40e_get_port_mac_addr - get Port MAC address | |
669 | * @hw: pointer to the HW structure | |
670 | * @mac_addr: pointer to Port MAC address | |
671 | * | |
672 | * Reads the adapter's Port MAC address | |
673 | **/ | |
674 | i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) | |
675 | { | |
676 | struct i40e_aqc_mac_address_read_data addrs; | |
677 | i40e_status status; | |
678 | u16 flags = 0; | |
679 | ||
680 | status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); | |
681 | if (status) | |
682 | return status; | |
683 | ||
684 | if (flags & I40E_AQC_PORT_ADDR_VALID) | |
685 | memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); | |
686 | else | |
687 | status = I40E_ERR_INVALID_MAC_ADDR; | |
688 | ||
689 | return status; | |
690 | } | |
691 | ||
351499ab MJ |
692 | /** |
693 | * i40e_pre_tx_queue_cfg - pre tx queue configure | |
694 | * @hw: pointer to the HW structure | |
b40c82e6 | 695 | * @queue: target PF queue index |
351499ab MJ |
696 | * @enable: state change request |
697 | * | |
698 | * Handles hw requirement to indicate intention to enable | |
699 | * or disable target queue. | |
700 | **/ | |
701 | void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) | |
702 | { | |
dfb699f9 | 703 | u32 abs_queue_idx = hw->func_caps.base_queue + queue; |
351499ab | 704 | u32 reg_block = 0; |
dfb699f9 | 705 | u32 reg_val; |
351499ab | 706 | |
24a768cf | 707 | if (abs_queue_idx >= 128) { |
351499ab | 708 | reg_block = abs_queue_idx / 128; |
24a768cf CP |
709 | abs_queue_idx %= 128; |
710 | } | |
351499ab MJ |
711 | |
712 | reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); | |
713 | reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; | |
714 | reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); | |
715 | ||
716 | if (enable) | |
717 | reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; | |
718 | else | |
719 | reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; | |
720 | ||
721 | wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); | |
722 | } | |
38e00438 VD |
723 | #ifdef I40E_FCOE |
724 | ||
725 | /** | |
726 | * i40e_get_san_mac_addr - get SAN MAC address | |
727 | * @hw: pointer to the HW structure | |
728 | * @mac_addr: pointer to SAN MAC address | |
729 | * | |
730 | * Reads the adapter's SAN MAC address from NVM | |
731 | **/ | |
732 | i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr) | |
733 | { | |
734 | struct i40e_aqc_mac_address_read_data addrs; | |
735 | i40e_status status; | |
736 | u16 flags = 0; | |
737 | ||
738 | status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); | |
739 | if (status) | |
740 | return status; | |
741 | ||
742 | if (flags & I40E_AQC_SAN_ADDR_VALID) | |
743 | memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac)); | |
744 | else | |
745 | status = I40E_ERR_INVALID_MAC_ADDR; | |
746 | ||
747 | return status; | |
748 | } | |
749 | #endif | |
351499ab | 750 | |
18f680c6 KK |
751 | /** |
752 | * i40e_read_pba_string - Reads part number string from EEPROM | |
753 | * @hw: pointer to hardware structure | |
754 | * @pba_num: stores the part number string from the EEPROM | |
755 | * @pba_num_size: part number string buffer length | |
756 | * | |
757 | * Reads the part number string from the EEPROM. | |
758 | **/ | |
759 | i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, | |
760 | u32 pba_num_size) | |
761 | { | |
762 | i40e_status status = 0; | |
763 | u16 pba_word = 0; | |
764 | u16 pba_size = 0; | |
765 | u16 pba_ptr = 0; | |
766 | u16 i = 0; | |
767 | ||
768 | status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); | |
769 | if (status || (pba_word != 0xFAFA)) { | |
770 | hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); | |
771 | return status; | |
772 | } | |
773 | ||
774 | status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); | |
775 | if (status) { | |
776 | hw_dbg(hw, "Failed to read PBA Block pointer.\n"); | |
777 | return status; | |
778 | } | |
779 | ||
780 | status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); | |
781 | if (status) { | |
782 | hw_dbg(hw, "Failed to read PBA Block size.\n"); | |
783 | return status; | |
784 | } | |
785 | ||
786 | /* Subtract one to get PBA word count (PBA Size word is included in | |
787 | * total size) | |
788 | */ | |
789 | pba_size--; | |
790 | if (pba_num_size < (((u32)pba_size * 2) + 1)) { | |
791 | hw_dbg(hw, "Buffer to small for PBA data.\n"); | |
792 | return I40E_ERR_PARAM; | |
793 | } | |
794 | ||
795 | for (i = 0; i < pba_size; i++) { | |
796 | status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); | |
797 | if (status) { | |
798 | hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); | |
799 | return status; | |
800 | } | |
801 | ||
802 | pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; | |
803 | pba_num[(i * 2) + 1] = pba_word & 0xFF; | |
804 | } | |
805 | pba_num[(pba_size * 2)] = '\0'; | |
806 | ||
807 | return status; | |
808 | } | |
809 | ||
be405eb0 JB |
810 | /** |
811 | * i40e_get_media_type - Gets media type | |
812 | * @hw: pointer to the hardware structure | |
813 | **/ | |
814 | static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) | |
815 | { | |
816 | enum i40e_media_type media; | |
817 | ||
818 | switch (hw->phy.link_info.phy_type) { | |
819 | case I40E_PHY_TYPE_10GBASE_SR: | |
820 | case I40E_PHY_TYPE_10GBASE_LR: | |
124ed15b CS |
821 | case I40E_PHY_TYPE_1000BASE_SX: |
822 | case I40E_PHY_TYPE_1000BASE_LX: | |
be405eb0 JB |
823 | case I40E_PHY_TYPE_40GBASE_SR4: |
824 | case I40E_PHY_TYPE_40GBASE_LR4: | |
825 | media = I40E_MEDIA_TYPE_FIBER; | |
826 | break; | |
827 | case I40E_PHY_TYPE_100BASE_TX: | |
828 | case I40E_PHY_TYPE_1000BASE_T: | |
829 | case I40E_PHY_TYPE_10GBASE_T: | |
830 | media = I40E_MEDIA_TYPE_BASET; | |
831 | break; | |
832 | case I40E_PHY_TYPE_10GBASE_CR1_CU: | |
833 | case I40E_PHY_TYPE_40GBASE_CR4_CU: | |
834 | case I40E_PHY_TYPE_10GBASE_CR1: | |
835 | case I40E_PHY_TYPE_40GBASE_CR4: | |
836 | case I40E_PHY_TYPE_10GBASE_SFPP_CU: | |
180204c7 CS |
837 | case I40E_PHY_TYPE_40GBASE_AOC: |
838 | case I40E_PHY_TYPE_10GBASE_AOC: | |
be405eb0 JB |
839 | media = I40E_MEDIA_TYPE_DA; |
840 | break; | |
841 | case I40E_PHY_TYPE_1000BASE_KX: | |
842 | case I40E_PHY_TYPE_10GBASE_KX4: | |
843 | case I40E_PHY_TYPE_10GBASE_KR: | |
844 | case I40E_PHY_TYPE_40GBASE_KR4: | |
ae24b409 | 845 | case I40E_PHY_TYPE_20GBASE_KR2: |
be405eb0 JB |
846 | media = I40E_MEDIA_TYPE_BACKPLANE; |
847 | break; | |
848 | case I40E_PHY_TYPE_SGMII: | |
849 | case I40E_PHY_TYPE_XAUI: | |
850 | case I40E_PHY_TYPE_XFI: | |
851 | case I40E_PHY_TYPE_XLAUI: | |
852 | case I40E_PHY_TYPE_XLPPI: | |
853 | default: | |
854 | media = I40E_MEDIA_TYPE_UNKNOWN; | |
855 | break; | |
856 | } | |
857 | ||
858 | return media; | |
859 | } | |
860 | ||
7134f9ce | 861 | #define I40E_PF_RESET_WAIT_COUNT_A0 200 |
8af580df | 862 | #define I40E_PF_RESET_WAIT_COUNT 200 |
56a62fc8 JB |
863 | /** |
864 | * i40e_pf_reset - Reset the PF | |
865 | * @hw: pointer to the hardware structure | |
866 | * | |
867 | * Assuming someone else has triggered a global reset, | |
868 | * assure the global reset is complete and then reset the PF | |
869 | **/ | |
870 | i40e_status i40e_pf_reset(struct i40e_hw *hw) | |
871 | { | |
7134f9ce | 872 | u32 cnt = 0; |
42794bd8 | 873 | u32 cnt1 = 0; |
56a62fc8 JB |
874 | u32 reg = 0; |
875 | u32 grst_del; | |
876 | ||
877 | /* Poll for Global Reset steady state in case of recent GRST. | |
878 | * The grst delay value is in 100ms units, and we'll wait a | |
879 | * couple counts longer to be sure we don't just miss the end. | |
880 | */ | |
de78fc5a SN |
881 | grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & |
882 | I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> | |
883 | I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; | |
7134f9ce | 884 | for (cnt = 0; cnt < grst_del + 2; cnt++) { |
56a62fc8 JB |
885 | reg = rd32(hw, I40E_GLGEN_RSTAT); |
886 | if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) | |
887 | break; | |
888 | msleep(100); | |
889 | } | |
890 | if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { | |
891 | hw_dbg(hw, "Global reset polling failed to complete.\n"); | |
42794bd8 SN |
892 | return I40E_ERR_RESET_FAILED; |
893 | } | |
894 | ||
895 | /* Now Wait for the FW to be ready */ | |
896 | for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { | |
897 | reg = rd32(hw, I40E_GLNVM_ULD); | |
898 | reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | | |
899 | I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); | |
900 | if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | | |
901 | I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { | |
902 | hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); | |
903 | break; | |
904 | } | |
905 | usleep_range(10000, 20000); | |
906 | } | |
907 | if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | | |
908 | I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { | |
909 | hw_dbg(hw, "wait for FW Reset complete timedout\n"); | |
910 | hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); | |
56a62fc8 JB |
911 | return I40E_ERR_RESET_FAILED; |
912 | } | |
913 | ||
56a62fc8 JB |
914 | /* If there was a Global Reset in progress when we got here, |
915 | * we don't need to do the PF Reset | |
916 | */ | |
7134f9ce JB |
917 | if (!cnt) { |
918 | if (hw->revision_id == 0) | |
919 | cnt = I40E_PF_RESET_WAIT_COUNT_A0; | |
920 | else | |
921 | cnt = I40E_PF_RESET_WAIT_COUNT; | |
56a62fc8 JB |
922 | reg = rd32(hw, I40E_PFGEN_CTRL); |
923 | wr32(hw, I40E_PFGEN_CTRL, | |
924 | (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); | |
7134f9ce | 925 | for (; cnt; cnt--) { |
56a62fc8 JB |
926 | reg = rd32(hw, I40E_PFGEN_CTRL); |
927 | if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) | |
928 | break; | |
929 | usleep_range(1000, 2000); | |
930 | } | |
931 | if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { | |
932 | hw_dbg(hw, "PF reset polling failed to complete.\n"); | |
933 | return I40E_ERR_RESET_FAILED; | |
934 | } | |
935 | } | |
936 | ||
937 | i40e_clear_pxe_mode(hw); | |
922680b9 | 938 | |
56a62fc8 JB |
939 | return 0; |
940 | } | |
941 | ||
838d41d9 SN |
942 | /** |
943 | * i40e_clear_hw - clear out any left over hw state | |
944 | * @hw: pointer to the hw struct | |
945 | * | |
946 | * Clear queues and interrupts, typically called at init time, | |
947 | * but after the capabilities have been found so we know how many | |
948 | * queues and msix vectors have been allocated. | |
949 | **/ | |
950 | void i40e_clear_hw(struct i40e_hw *hw) | |
951 | { | |
952 | u32 num_queues, base_queue; | |
953 | u32 num_pf_int; | |
954 | u32 num_vf_int; | |
955 | u32 num_vfs; | |
956 | u32 i, j; | |
957 | u32 val; | |
958 | u32 eol = 0x7ff; | |
959 | ||
b40c82e6 | 960 | /* get number of interrupts, queues, and VFs */ |
838d41d9 SN |
961 | val = rd32(hw, I40E_GLPCI_CNF2); |
962 | num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> | |
963 | I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; | |
964 | num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> | |
965 | I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; | |
966 | ||
967 | val = rd32(hw, I40E_PFLAN_QALLOC); | |
968 | base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> | |
969 | I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; | |
970 | j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> | |
971 | I40E_PFLAN_QALLOC_LASTQ_SHIFT; | |
972 | if (val & I40E_PFLAN_QALLOC_VALID_MASK) | |
973 | num_queues = (j - base_queue) + 1; | |
974 | else | |
975 | num_queues = 0; | |
976 | ||
977 | val = rd32(hw, I40E_PF_VT_PFALLOC); | |
978 | i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> | |
979 | I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; | |
980 | j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> | |
981 | I40E_PF_VT_PFALLOC_LASTVF_SHIFT; | |
982 | if (val & I40E_PF_VT_PFALLOC_VALID_MASK) | |
983 | num_vfs = (j - i) + 1; | |
984 | else | |
985 | num_vfs = 0; | |
986 | ||
987 | /* stop all the interrupts */ | |
988 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); | |
989 | val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; | |
990 | for (i = 0; i < num_pf_int - 2; i++) | |
991 | wr32(hw, I40E_PFINT_DYN_CTLN(i), val); | |
992 | ||
993 | /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ | |
994 | val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; | |
995 | wr32(hw, I40E_PFINT_LNKLST0, val); | |
996 | for (i = 0; i < num_pf_int - 2; i++) | |
997 | wr32(hw, I40E_PFINT_LNKLSTN(i), val); | |
998 | val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; | |
999 | for (i = 0; i < num_vfs; i++) | |
1000 | wr32(hw, I40E_VPINT_LNKLST0(i), val); | |
1001 | for (i = 0; i < num_vf_int - 2; i++) | |
1002 | wr32(hw, I40E_VPINT_LNKLSTN(i), val); | |
1003 | ||
1004 | /* warn the HW of the coming Tx disables */ | |
1005 | for (i = 0; i < num_queues; i++) { | |
1006 | u32 abs_queue_idx = base_queue + i; | |
1007 | u32 reg_block = 0; | |
1008 | ||
1009 | if (abs_queue_idx >= 128) { | |
1010 | reg_block = abs_queue_idx / 128; | |
1011 | abs_queue_idx %= 128; | |
1012 | } | |
1013 | ||
1014 | val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); | |
1015 | val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; | |
1016 | val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); | |
1017 | val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; | |
1018 | ||
1019 | wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); | |
1020 | } | |
1021 | udelay(400); | |
1022 | ||
1023 | /* stop all the queues */ | |
1024 | for (i = 0; i < num_queues; i++) { | |
1025 | wr32(hw, I40E_QINT_TQCTL(i), 0); | |
1026 | wr32(hw, I40E_QTX_ENA(i), 0); | |
1027 | wr32(hw, I40E_QINT_RQCTL(i), 0); | |
1028 | wr32(hw, I40E_QRX_ENA(i), 0); | |
1029 | } | |
1030 | ||
1031 | /* short wait for all queue disables to settle */ | |
1032 | udelay(50); | |
1033 | } | |
1034 | ||
56a62fc8 JB |
1035 | /** |
1036 | * i40e_clear_pxe_mode - clear pxe operations mode | |
1037 | * @hw: pointer to the hw struct | |
1038 | * | |
1039 | * Make sure all PXE mode settings are cleared, including things | |
1040 | * like descriptor fetch/write-back mode. | |
1041 | **/ | |
1042 | void i40e_clear_pxe_mode(struct i40e_hw *hw) | |
1043 | { | |
1044 | u32 reg; | |
1045 | ||
c9b9b0ae SN |
1046 | if (i40e_check_asq_alive(hw)) |
1047 | i40e_aq_clear_pxe_mode(hw, NULL); | |
1048 | ||
56a62fc8 JB |
1049 | /* Clear single descriptor fetch/write-back mode */ |
1050 | reg = rd32(hw, I40E_GLLAN_RCTL_0); | |
7134f9ce JB |
1051 | |
1052 | if (hw->revision_id == 0) { | |
1053 | /* As a work around clear PXE_MODE instead of setting it */ | |
1054 | wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); | |
1055 | } else { | |
1056 | wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); | |
1057 | } | |
56a62fc8 JB |
1058 | } |
1059 | ||
0556a9e3 JB |
1060 | /** |
1061 | * i40e_led_is_mine - helper to find matching led | |
1062 | * @hw: pointer to the hw struct | |
1063 | * @idx: index into GPIO registers | |
1064 | * | |
1065 | * returns: 0 if no match, otherwise the value of the GPIO_CTL register | |
1066 | */ | |
1067 | static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) | |
1068 | { | |
1069 | u32 gpio_val = 0; | |
1070 | u32 port; | |
1071 | ||
1072 | if (!hw->func_caps.led[idx]) | |
1073 | return 0; | |
1074 | ||
1075 | gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); | |
1076 | port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> | |
1077 | I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; | |
1078 | ||
1079 | /* if PRT_NUM_NA is 1 then this LED is not port specific, OR | |
1080 | * if it is not our port then ignore | |
1081 | */ | |
1082 | if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || | |
1083 | (port != hw->port)) | |
1084 | return 0; | |
1085 | ||
1086 | return gpio_val; | |
1087 | } | |
1088 | ||
b84d5cd8 MJ |
1089 | #define I40E_COMBINED_ACTIVITY 0xA |
1090 | #define I40E_FILTER_ACTIVITY 0xE | |
0556a9e3 | 1091 | #define I40E_LINK_ACTIVITY 0xC |
b84d5cd8 MJ |
1092 | #define I40E_MAC_ACTIVITY 0xD |
1093 | #define I40E_LED0 22 | |
0556a9e3 | 1094 | |
56a62fc8 JB |
1095 | /** |
1096 | * i40e_led_get - return current on/off mode | |
1097 | * @hw: pointer to the hw struct | |
1098 | * | |
1099 | * The value returned is the 'mode' field as defined in the | |
1100 | * GPIO register definitions: 0x0 = off, 0xf = on, and other | |
1101 | * values are variations of possible behaviors relating to | |
1102 | * blink, link, and wire. | |
1103 | **/ | |
1104 | u32 i40e_led_get(struct i40e_hw *hw) | |
1105 | { | |
b84d5cd8 | 1106 | u32 current_mode = 0; |
56a62fc8 | 1107 | u32 mode = 0; |
56a62fc8 JB |
1108 | int i; |
1109 | ||
0556a9e3 JB |
1110 | /* as per the documentation GPIO 22-29 are the LED |
1111 | * GPIO pins named LED0..LED7 | |
1112 | */ | |
1113 | for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { | |
1114 | u32 gpio_val = i40e_led_is_mine(hw, i); | |
56a62fc8 | 1115 | |
0556a9e3 | 1116 | if (!gpio_val) |
56a62fc8 JB |
1117 | continue; |
1118 | ||
b84d5cd8 MJ |
1119 | /* ignore gpio LED src mode entries related to the activity |
1120 | * LEDs | |
1121 | */ | |
1122 | current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) | |
1123 | >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); | |
1124 | switch (current_mode) { | |
1125 | case I40E_COMBINED_ACTIVITY: | |
1126 | case I40E_FILTER_ACTIVITY: | |
1127 | case I40E_MAC_ACTIVITY: | |
1128 | continue; | |
1129 | default: | |
1130 | break; | |
1131 | } | |
1132 | ||
0556a9e3 JB |
1133 | mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> |
1134 | I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; | |
56a62fc8 JB |
1135 | break; |
1136 | } | |
1137 | ||
1138 | return mode; | |
1139 | } | |
1140 | ||
1141 | /** | |
1142 | * i40e_led_set - set new on/off mode | |
1143 | * @hw: pointer to the hw struct | |
0556a9e3 JB |
1144 | * @mode: 0=off, 0xf=on (else see manual for mode details) |
1145 | * @blink: true if the LED should blink when on, false if steady | |
1146 | * | |
1147 | * if this function is used to turn on the blink it should | |
1148 | * be used to disable the blink when restoring the original state. | |
56a62fc8 | 1149 | **/ |
0556a9e3 | 1150 | void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) |
56a62fc8 | 1151 | { |
b84d5cd8 | 1152 | u32 current_mode = 0; |
56a62fc8 JB |
1153 | int i; |
1154 | ||
0556a9e3 JB |
1155 | if (mode & 0xfffffff0) |
1156 | hw_dbg(hw, "invalid mode passed in %X\n", mode); | |
56a62fc8 | 1157 | |
0556a9e3 JB |
1158 | /* as per the documentation GPIO 22-29 are the LED |
1159 | * GPIO pins named LED0..LED7 | |
1160 | */ | |
1161 | for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { | |
1162 | u32 gpio_val = i40e_led_is_mine(hw, i); | |
56a62fc8 | 1163 | |
0556a9e3 | 1164 | if (!gpio_val) |
56a62fc8 JB |
1165 | continue; |
1166 | ||
b84d5cd8 MJ |
1167 | /* ignore gpio LED src mode entries related to the activity |
1168 | * LEDs | |
1169 | */ | |
1170 | current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) | |
1171 | >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); | |
1172 | switch (current_mode) { | |
1173 | case I40E_COMBINED_ACTIVITY: | |
1174 | case I40E_FILTER_ACTIVITY: | |
1175 | case I40E_MAC_ACTIVITY: | |
1176 | continue; | |
1177 | default: | |
1178 | break; | |
1179 | } | |
1180 | ||
56a62fc8 | 1181 | gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; |
0556a9e3 JB |
1182 | /* this & is a bit of paranoia, but serves as a range check */ |
1183 | gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & | |
1184 | I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); | |
1185 | ||
1186 | if (mode == I40E_LINK_ACTIVITY) | |
1187 | blink = false; | |
1188 | ||
9be00d67 MJ |
1189 | if (blink) |
1190 | gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); | |
1191 | else | |
1192 | gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); | |
0556a9e3 | 1193 | |
56a62fc8 | 1194 | wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); |
0556a9e3 | 1195 | break; |
56a62fc8 JB |
1196 | } |
1197 | } | |
1198 | ||
1199 | /* Admin command wrappers */ | |
56a62fc8 | 1200 | |
8109e123 CS |
1201 | /** |
1202 | * i40e_aq_get_phy_capabilities | |
1203 | * @hw: pointer to the hw struct | |
1204 | * @abilities: structure for PHY capabilities to be filled | |
1205 | * @qualified_modules: report Qualified Modules | |
1206 | * @report_init: report init capabilities (active are default) | |
1207 | * @cmd_details: pointer to command details structure or NULL | |
1208 | * | |
1209 | * Returns the various PHY abilities supported on the Port. | |
1210 | **/ | |
1211 | i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, | |
1212 | bool qualified_modules, bool report_init, | |
1213 | struct i40e_aq_get_phy_abilities_resp *abilities, | |
1214 | struct i40e_asq_cmd_details *cmd_details) | |
1215 | { | |
1216 | struct i40e_aq_desc desc; | |
1217 | i40e_status status; | |
1218 | u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); | |
1219 | ||
1220 | if (!abilities) | |
1221 | return I40E_ERR_PARAM; | |
1222 | ||
1223 | i40e_fill_default_direct_cmd_desc(&desc, | |
1224 | i40e_aqc_opc_get_phy_abilities); | |
1225 | ||
1226 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
1227 | if (abilities_size > I40E_AQ_LARGE_BUF) | |
1228 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
1229 | ||
1230 | if (qualified_modules) | |
1231 | desc.params.external.param0 |= | |
1232 | cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); | |
1233 | ||
1234 | if (report_init) | |
1235 | desc.params.external.param0 |= | |
1236 | cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); | |
1237 | ||
1238 | status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, | |
1239 | cmd_details); | |
1240 | ||
1241 | if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) | |
1242 | status = I40E_ERR_UNKNOWN_PHY; | |
1243 | ||
1244 | return status; | |
1245 | } | |
1246 | ||
c56999f9 CS |
1247 | /** |
1248 | * i40e_aq_set_phy_config | |
1249 | * @hw: pointer to the hw struct | |
1250 | * @config: structure with PHY configuration to be set | |
1251 | * @cmd_details: pointer to command details structure or NULL | |
1252 | * | |
1253 | * Set the various PHY configuration parameters | |
1254 | * supported on the Port.One or more of the Set PHY config parameters may be | |
1255 | * ignored in an MFP mode as the PF may not have the privilege to set some | |
1256 | * of the PHY Config parameters. This status will be indicated by the | |
1257 | * command response. | |
1258 | **/ | |
1259 | enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, | |
1260 | struct i40e_aq_set_phy_config *config, | |
1261 | struct i40e_asq_cmd_details *cmd_details) | |
1262 | { | |
1263 | struct i40e_aq_desc desc; | |
1264 | struct i40e_aq_set_phy_config *cmd = | |
1265 | (struct i40e_aq_set_phy_config *)&desc.params.raw; | |
1266 | enum i40e_status_code status; | |
1267 | ||
1268 | if (!config) | |
1269 | return I40E_ERR_PARAM; | |
1270 | ||
1271 | i40e_fill_default_direct_cmd_desc(&desc, | |
1272 | i40e_aqc_opc_set_phy_config); | |
1273 | ||
1274 | *cmd = *config; | |
1275 | ||
1276 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1277 | ||
1278 | return status; | |
1279 | } | |
1280 | ||
1281 | /** | |
1282 | * i40e_set_fc | |
1283 | * @hw: pointer to the hw struct | |
1284 | * | |
1285 | * Set the requested flow control mode using set_phy_config. | |
1286 | **/ | |
1287 | enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, | |
1288 | bool atomic_restart) | |
1289 | { | |
1290 | enum i40e_fc_mode fc_mode = hw->fc.requested_mode; | |
1291 | struct i40e_aq_get_phy_abilities_resp abilities; | |
1292 | struct i40e_aq_set_phy_config config; | |
1293 | enum i40e_status_code status; | |
1294 | u8 pause_mask = 0x0; | |
1295 | ||
1296 | *aq_failures = 0x0; | |
1297 | ||
1298 | switch (fc_mode) { | |
1299 | case I40E_FC_FULL: | |
1300 | pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; | |
1301 | pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; | |
1302 | break; | |
1303 | case I40E_FC_RX_PAUSE: | |
1304 | pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; | |
1305 | break; | |
1306 | case I40E_FC_TX_PAUSE: | |
1307 | pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; | |
1308 | break; | |
1309 | default: | |
1310 | break; | |
1311 | } | |
1312 | ||
1313 | /* Get the current phy config */ | |
1314 | status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, | |
1315 | NULL); | |
1316 | if (status) { | |
1317 | *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; | |
1318 | return status; | |
1319 | } | |
1320 | ||
1321 | memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); | |
1322 | /* clear the old pause settings */ | |
1323 | config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & | |
1324 | ~(I40E_AQ_PHY_FLAG_PAUSE_RX); | |
1325 | /* set the new abilities */ | |
1326 | config.abilities |= pause_mask; | |
1327 | /* If the abilities have changed, then set the new config */ | |
1328 | if (config.abilities != abilities.abilities) { | |
1329 | /* Auto restart link so settings take effect */ | |
1330 | if (atomic_restart) | |
1331 | config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; | |
1332 | /* Copy over all the old settings */ | |
1333 | config.phy_type = abilities.phy_type; | |
1334 | config.link_speed = abilities.link_speed; | |
1335 | config.eee_capability = abilities.eee_capability; | |
1336 | config.eeer = abilities.eeer_val; | |
1337 | config.low_power_ctrl = abilities.d3_lpan; | |
1338 | status = i40e_aq_set_phy_config(hw, &config, NULL); | |
1339 | ||
1340 | if (status) | |
1341 | *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; | |
1342 | } | |
1343 | /* Update the link info */ | |
21af70fb | 1344 | status = i40e_aq_get_link_info(hw, true, NULL, NULL); |
c56999f9 CS |
1345 | if (status) { |
1346 | /* Wait a little bit (on 40G cards it sometimes takes a really | |
1347 | * long time for link to come back from the atomic reset) | |
1348 | * and try once more | |
1349 | */ | |
1350 | msleep(1000); | |
21af70fb | 1351 | status = i40e_aq_get_link_info(hw, true, NULL, NULL); |
c56999f9 CS |
1352 | } |
1353 | if (status) | |
1354 | *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; | |
1355 | ||
1356 | return status; | |
1357 | } | |
1358 | ||
c9b9b0ae SN |
1359 | /** |
1360 | * i40e_aq_clear_pxe_mode | |
1361 | * @hw: pointer to the hw struct | |
1362 | * @cmd_details: pointer to command details structure or NULL | |
1363 | * | |
1364 | * Tell the firmware that the driver is taking over from PXE | |
1365 | **/ | |
1366 | i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, | |
1367 | struct i40e_asq_cmd_details *cmd_details) | |
1368 | { | |
1369 | i40e_status status; | |
1370 | struct i40e_aq_desc desc; | |
1371 | struct i40e_aqc_clear_pxe *cmd = | |
1372 | (struct i40e_aqc_clear_pxe *)&desc.params.raw; | |
1373 | ||
1374 | i40e_fill_default_direct_cmd_desc(&desc, | |
1375 | i40e_aqc_opc_clear_pxe_mode); | |
1376 | ||
1377 | cmd->rx_cnt = 0x2; | |
1378 | ||
1379 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1380 | ||
1381 | wr32(hw, I40E_GLLAN_RCTL_0, 0x1); | |
1382 | ||
1383 | return status; | |
1384 | } | |
1385 | ||
56a62fc8 JB |
1386 | /** |
1387 | * i40e_aq_set_link_restart_an | |
1388 | * @hw: pointer to the hw struct | |
1ac978af | 1389 | * @enable_link: if true: enable link, if false: disable link |
56a62fc8 JB |
1390 | * @cmd_details: pointer to command details structure or NULL |
1391 | * | |
1392 | * Sets up the link and restarts the Auto-Negotiation over the link. | |
1393 | **/ | |
1394 | i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, | |
1ac978af CS |
1395 | bool enable_link, |
1396 | struct i40e_asq_cmd_details *cmd_details) | |
56a62fc8 JB |
1397 | { |
1398 | struct i40e_aq_desc desc; | |
1399 | struct i40e_aqc_set_link_restart_an *cmd = | |
1400 | (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; | |
1401 | i40e_status status; | |
1402 | ||
1403 | i40e_fill_default_direct_cmd_desc(&desc, | |
1404 | i40e_aqc_opc_set_link_restart_an); | |
1405 | ||
1406 | cmd->command = I40E_AQ_PHY_RESTART_AN; | |
1ac978af CS |
1407 | if (enable_link) |
1408 | cmd->command |= I40E_AQ_PHY_LINK_ENABLE; | |
1409 | else | |
1410 | cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; | |
56a62fc8 JB |
1411 | |
1412 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1413 | ||
1414 | return status; | |
1415 | } | |
1416 | ||
1417 | /** | |
1418 | * i40e_aq_get_link_info | |
1419 | * @hw: pointer to the hw struct | |
1420 | * @enable_lse: enable/disable LinkStatusEvent reporting | |
1421 | * @link: pointer to link status structure - optional | |
1422 | * @cmd_details: pointer to command details structure or NULL | |
1423 | * | |
1424 | * Returns the link status of the adapter. | |
1425 | **/ | |
1426 | i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, | |
1427 | bool enable_lse, struct i40e_link_status *link, | |
1428 | struct i40e_asq_cmd_details *cmd_details) | |
1429 | { | |
1430 | struct i40e_aq_desc desc; | |
1431 | struct i40e_aqc_get_link_status *resp = | |
1432 | (struct i40e_aqc_get_link_status *)&desc.params.raw; | |
1433 | struct i40e_link_status *hw_link_info = &hw->phy.link_info; | |
1434 | i40e_status status; | |
c56999f9 | 1435 | bool tx_pause, rx_pause; |
56a62fc8 JB |
1436 | u16 command_flags; |
1437 | ||
1438 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); | |
1439 | ||
1440 | if (enable_lse) | |
1441 | command_flags = I40E_AQ_LSE_ENABLE; | |
1442 | else | |
1443 | command_flags = I40E_AQ_LSE_DISABLE; | |
1444 | resp->command_flags = cpu_to_le16(command_flags); | |
1445 | ||
1446 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1447 | ||
1448 | if (status) | |
1449 | goto aq_get_link_info_exit; | |
1450 | ||
1451 | /* save off old link status information */ | |
c36bd4a7 | 1452 | hw->phy.link_info_old = *hw_link_info; |
56a62fc8 JB |
1453 | |
1454 | /* update link status */ | |
1455 | hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; | |
be405eb0 | 1456 | hw->phy.media_type = i40e_get_media_type(hw); |
56a62fc8 JB |
1457 | hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; |
1458 | hw_link_info->link_info = resp->link_info; | |
1459 | hw_link_info->an_info = resp->an_info; | |
1460 | hw_link_info->ext_info = resp->ext_info; | |
639dc377 | 1461 | hw_link_info->loopback = resp->loopback; |
6bb3f23c NP |
1462 | hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); |
1463 | hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; | |
1464 | ||
c56999f9 CS |
1465 | /* update fc info */ |
1466 | tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); | |
1467 | rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); | |
1468 | if (tx_pause & rx_pause) | |
1469 | hw->fc.current_mode = I40E_FC_FULL; | |
1470 | else if (tx_pause) | |
1471 | hw->fc.current_mode = I40E_FC_TX_PAUSE; | |
1472 | else if (rx_pause) | |
1473 | hw->fc.current_mode = I40E_FC_RX_PAUSE; | |
1474 | else | |
1475 | hw->fc.current_mode = I40E_FC_NONE; | |
1476 | ||
6bb3f23c NP |
1477 | if (resp->config & I40E_AQ_CONFIG_CRC_ENA) |
1478 | hw_link_info->crc_enable = true; | |
1479 | else | |
1480 | hw_link_info->crc_enable = false; | |
56a62fc8 JB |
1481 | |
1482 | if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE)) | |
1483 | hw_link_info->lse_enable = true; | |
1484 | else | |
1485 | hw_link_info->lse_enable = false; | |
1486 | ||
088c4ee3 CS |
1487 | if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && |
1488 | hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) | |
1489 | hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; | |
1490 | ||
56a62fc8 JB |
1491 | /* save link status information */ |
1492 | if (link) | |
d7595a22 | 1493 | *link = *hw_link_info; |
56a62fc8 JB |
1494 | |
1495 | /* flag cleared so helper functions don't call AQ again */ | |
1496 | hw->phy.get_link_info = false; | |
1497 | ||
1498 | aq_get_link_info_exit: | |
1499 | return status; | |
1500 | } | |
1501 | ||
7e2453fe JB |
1502 | /** |
1503 | * i40e_aq_set_phy_int_mask | |
1504 | * @hw: pointer to the hw struct | |
1505 | * @mask: interrupt mask to be set | |
1506 | * @cmd_details: pointer to command details structure or NULL | |
1507 | * | |
1508 | * Set link interrupt mask. | |
1509 | **/ | |
1510 | i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, | |
1511 | u16 mask, | |
1512 | struct i40e_asq_cmd_details *cmd_details) | |
1513 | { | |
1514 | struct i40e_aq_desc desc; | |
1515 | struct i40e_aqc_set_phy_int_mask *cmd = | |
1516 | (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; | |
1517 | i40e_status status; | |
1518 | ||
1519 | i40e_fill_default_direct_cmd_desc(&desc, | |
1520 | i40e_aqc_opc_set_phy_int_mask); | |
1521 | ||
1522 | cmd->event_mask = cpu_to_le16(mask); | |
1523 | ||
1524 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1525 | ||
1526 | return status; | |
1527 | } | |
1528 | ||
56a62fc8 JB |
1529 | /** |
1530 | * i40e_aq_add_vsi | |
1531 | * @hw: pointer to the hw struct | |
98d44381 | 1532 | * @vsi_ctx: pointer to a vsi context struct |
56a62fc8 JB |
1533 | * @cmd_details: pointer to command details structure or NULL |
1534 | * | |
1535 | * Add a VSI context to the hardware. | |
1536 | **/ | |
1537 | i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, | |
1538 | struct i40e_vsi_context *vsi_ctx, | |
1539 | struct i40e_asq_cmd_details *cmd_details) | |
1540 | { | |
1541 | struct i40e_aq_desc desc; | |
1542 | struct i40e_aqc_add_get_update_vsi *cmd = | |
1543 | (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; | |
1544 | struct i40e_aqc_add_get_update_vsi_completion *resp = | |
1545 | (struct i40e_aqc_add_get_update_vsi_completion *) | |
1546 | &desc.params.raw; | |
1547 | i40e_status status; | |
1548 | ||
1549 | i40e_fill_default_direct_cmd_desc(&desc, | |
1550 | i40e_aqc_opc_add_vsi); | |
1551 | ||
1552 | cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); | |
1553 | cmd->connection_type = vsi_ctx->connection_type; | |
1554 | cmd->vf_id = vsi_ctx->vf_num; | |
1555 | cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); | |
1556 | ||
1557 | desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); | |
56a62fc8 JB |
1558 | |
1559 | status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, | |
1560 | sizeof(vsi_ctx->info), cmd_details); | |
1561 | ||
1562 | if (status) | |
1563 | goto aq_add_vsi_exit; | |
1564 | ||
1565 | vsi_ctx->seid = le16_to_cpu(resp->seid); | |
1566 | vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); | |
1567 | vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); | |
1568 | vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); | |
1569 | ||
1570 | aq_add_vsi_exit: | |
1571 | return status; | |
1572 | } | |
1573 | ||
1574 | /** | |
1575 | * i40e_aq_set_vsi_unicast_promiscuous | |
1576 | * @hw: pointer to the hw struct | |
1577 | * @seid: vsi number | |
1578 | * @set: set unicast promiscuous enable/disable | |
1579 | * @cmd_details: pointer to command details structure or NULL | |
1580 | **/ | |
1581 | i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, | |
885552a2 MW |
1582 | u16 seid, bool set, |
1583 | struct i40e_asq_cmd_details *cmd_details) | |
56a62fc8 JB |
1584 | { |
1585 | struct i40e_aq_desc desc; | |
1586 | struct i40e_aqc_set_vsi_promiscuous_modes *cmd = | |
1587 | (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; | |
1588 | i40e_status status; | |
1589 | u16 flags = 0; | |
1590 | ||
1591 | i40e_fill_default_direct_cmd_desc(&desc, | |
1592 | i40e_aqc_opc_set_vsi_promiscuous_modes); | |
1593 | ||
1594 | if (set) | |
1595 | flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; | |
1596 | ||
1597 | cmd->promiscuous_flags = cpu_to_le16(flags); | |
1598 | ||
1599 | cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); | |
1600 | ||
1601 | cmd->seid = cpu_to_le16(seid); | |
1602 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1603 | ||
1604 | return status; | |
1605 | } | |
1606 | ||
1607 | /** | |
1608 | * i40e_aq_set_vsi_multicast_promiscuous | |
1609 | * @hw: pointer to the hw struct | |
1610 | * @seid: vsi number | |
1611 | * @set: set multicast promiscuous enable/disable | |
1612 | * @cmd_details: pointer to command details structure or NULL | |
1613 | **/ | |
1614 | i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, | |
1615 | u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) | |
1616 | { | |
1617 | struct i40e_aq_desc desc; | |
1618 | struct i40e_aqc_set_vsi_promiscuous_modes *cmd = | |
1619 | (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; | |
1620 | i40e_status status; | |
1621 | u16 flags = 0; | |
1622 | ||
1623 | i40e_fill_default_direct_cmd_desc(&desc, | |
1624 | i40e_aqc_opc_set_vsi_promiscuous_modes); | |
1625 | ||
1626 | if (set) | |
1627 | flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; | |
1628 | ||
1629 | cmd->promiscuous_flags = cpu_to_le16(flags); | |
1630 | ||
1631 | cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); | |
1632 | ||
1633 | cmd->seid = cpu_to_le16(seid); | |
1634 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1635 | ||
1636 | return status; | |
1637 | } | |
1638 | ||
1639 | /** | |
1640 | * i40e_aq_set_vsi_broadcast | |
1641 | * @hw: pointer to the hw struct | |
1642 | * @seid: vsi number | |
1643 | * @set_filter: true to set filter, false to clear filter | |
1644 | * @cmd_details: pointer to command details structure or NULL | |
1645 | * | |
1646 | * Set or clear the broadcast promiscuous flag (filter) for a given VSI. | |
1647 | **/ | |
1648 | i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, | |
1649 | u16 seid, bool set_filter, | |
1650 | struct i40e_asq_cmd_details *cmd_details) | |
1651 | { | |
1652 | struct i40e_aq_desc desc; | |
1653 | struct i40e_aqc_set_vsi_promiscuous_modes *cmd = | |
1654 | (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; | |
1655 | i40e_status status; | |
1656 | ||
1657 | i40e_fill_default_direct_cmd_desc(&desc, | |
1658 | i40e_aqc_opc_set_vsi_promiscuous_modes); | |
1659 | ||
1660 | if (set_filter) | |
1661 | cmd->promiscuous_flags | |
1662 | |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); | |
1663 | else | |
1664 | cmd->promiscuous_flags | |
1665 | &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); | |
1666 | ||
1667 | cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); | |
1668 | cmd->seid = cpu_to_le16(seid); | |
1669 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1670 | ||
1671 | return status; | |
1672 | } | |
1673 | ||
1674 | /** | |
1675 | * i40e_get_vsi_params - get VSI configuration info | |
1676 | * @hw: pointer to the hw struct | |
98d44381 | 1677 | * @vsi_ctx: pointer to a vsi context struct |
56a62fc8 JB |
1678 | * @cmd_details: pointer to command details structure or NULL |
1679 | **/ | |
1680 | i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, | |
1681 | struct i40e_vsi_context *vsi_ctx, | |
1682 | struct i40e_asq_cmd_details *cmd_details) | |
1683 | { | |
1684 | struct i40e_aq_desc desc; | |
f5ac8579 SN |
1685 | struct i40e_aqc_add_get_update_vsi *cmd = |
1686 | (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; | |
56a62fc8 JB |
1687 | struct i40e_aqc_add_get_update_vsi_completion *resp = |
1688 | (struct i40e_aqc_add_get_update_vsi_completion *) | |
1689 | &desc.params.raw; | |
1690 | i40e_status status; | |
1691 | ||
1692 | i40e_fill_default_direct_cmd_desc(&desc, | |
1693 | i40e_aqc_opc_get_vsi_parameters); | |
1694 | ||
f5ac8579 | 1695 | cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); |
56a62fc8 JB |
1696 | |
1697 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
56a62fc8 JB |
1698 | |
1699 | status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, | |
1700 | sizeof(vsi_ctx->info), NULL); | |
1701 | ||
1702 | if (status) | |
1703 | goto aq_get_vsi_params_exit; | |
1704 | ||
1705 | vsi_ctx->seid = le16_to_cpu(resp->seid); | |
1706 | vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); | |
1707 | vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); | |
1708 | vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); | |
1709 | ||
1710 | aq_get_vsi_params_exit: | |
1711 | return status; | |
1712 | } | |
1713 | ||
1714 | /** | |
1715 | * i40e_aq_update_vsi_params | |
1716 | * @hw: pointer to the hw struct | |
98d44381 | 1717 | * @vsi_ctx: pointer to a vsi context struct |
56a62fc8 JB |
1718 | * @cmd_details: pointer to command details structure or NULL |
1719 | * | |
1720 | * Update a VSI context. | |
1721 | **/ | |
1722 | i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, | |
1723 | struct i40e_vsi_context *vsi_ctx, | |
1724 | struct i40e_asq_cmd_details *cmd_details) | |
1725 | { | |
1726 | struct i40e_aq_desc desc; | |
f5ac8579 SN |
1727 | struct i40e_aqc_add_get_update_vsi *cmd = |
1728 | (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; | |
56a62fc8 JB |
1729 | i40e_status status; |
1730 | ||
1731 | i40e_fill_default_direct_cmd_desc(&desc, | |
1732 | i40e_aqc_opc_update_vsi_parameters); | |
f5ac8579 | 1733 | cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); |
56a62fc8 JB |
1734 | |
1735 | desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); | |
56a62fc8 JB |
1736 | |
1737 | status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, | |
1738 | sizeof(vsi_ctx->info), cmd_details); | |
1739 | ||
1740 | return status; | |
1741 | } | |
1742 | ||
1743 | /** | |
1744 | * i40e_aq_get_switch_config | |
1745 | * @hw: pointer to the hardware structure | |
1746 | * @buf: pointer to the result buffer | |
1747 | * @buf_size: length of input buffer | |
1748 | * @start_seid: seid to start for the report, 0 == beginning | |
1749 | * @cmd_details: pointer to command details structure or NULL | |
1750 | * | |
1751 | * Fill the buf with switch configuration returned from AdminQ command | |
1752 | **/ | |
1753 | i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, | |
1754 | struct i40e_aqc_get_switch_config_resp *buf, | |
1755 | u16 buf_size, u16 *start_seid, | |
1756 | struct i40e_asq_cmd_details *cmd_details) | |
1757 | { | |
1758 | struct i40e_aq_desc desc; | |
1759 | struct i40e_aqc_switch_seid *scfg = | |
1760 | (struct i40e_aqc_switch_seid *)&desc.params.raw; | |
1761 | i40e_status status; | |
1762 | ||
1763 | i40e_fill_default_direct_cmd_desc(&desc, | |
1764 | i40e_aqc_opc_get_switch_config); | |
1765 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
1766 | if (buf_size > I40E_AQ_LARGE_BUF) | |
1767 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
1768 | scfg->seid = cpu_to_le16(*start_seid); | |
1769 | ||
1770 | status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); | |
1771 | *start_seid = le16_to_cpu(scfg->seid); | |
1772 | ||
1773 | return status; | |
1774 | } | |
1775 | ||
1776 | /** | |
1777 | * i40e_aq_get_firmware_version | |
1778 | * @hw: pointer to the hw struct | |
1779 | * @fw_major_version: firmware major version | |
1780 | * @fw_minor_version: firmware minor version | |
7edf810c | 1781 | * @fw_build: firmware build number |
56a62fc8 JB |
1782 | * @api_major_version: major queue version |
1783 | * @api_minor_version: minor queue version | |
1784 | * @cmd_details: pointer to command details structure or NULL | |
1785 | * | |
1786 | * Get the firmware version from the admin queue commands | |
1787 | **/ | |
1788 | i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, | |
1789 | u16 *fw_major_version, u16 *fw_minor_version, | |
7edf810c | 1790 | u32 *fw_build, |
56a62fc8 JB |
1791 | u16 *api_major_version, u16 *api_minor_version, |
1792 | struct i40e_asq_cmd_details *cmd_details) | |
1793 | { | |
1794 | struct i40e_aq_desc desc; | |
1795 | struct i40e_aqc_get_version *resp = | |
1796 | (struct i40e_aqc_get_version *)&desc.params.raw; | |
1797 | i40e_status status; | |
1798 | ||
1799 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); | |
1800 | ||
1801 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1802 | ||
1803 | if (!status) { | |
7edf810c | 1804 | if (fw_major_version) |
56a62fc8 | 1805 | *fw_major_version = le16_to_cpu(resp->fw_major); |
7edf810c | 1806 | if (fw_minor_version) |
56a62fc8 | 1807 | *fw_minor_version = le16_to_cpu(resp->fw_minor); |
7edf810c SN |
1808 | if (fw_build) |
1809 | *fw_build = le32_to_cpu(resp->fw_build); | |
1810 | if (api_major_version) | |
56a62fc8 | 1811 | *api_major_version = le16_to_cpu(resp->api_major); |
7edf810c | 1812 | if (api_minor_version) |
56a62fc8 JB |
1813 | *api_minor_version = le16_to_cpu(resp->api_minor); |
1814 | } | |
1815 | ||
1816 | return status; | |
1817 | } | |
1818 | ||
1819 | /** | |
1820 | * i40e_aq_send_driver_version | |
1821 | * @hw: pointer to the hw struct | |
56a62fc8 JB |
1822 | * @dv: driver's major, minor version |
1823 | * @cmd_details: pointer to command details structure or NULL | |
1824 | * | |
1825 | * Send the driver version to the firmware | |
1826 | **/ | |
1827 | i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, | |
1828 | struct i40e_driver_version *dv, | |
1829 | struct i40e_asq_cmd_details *cmd_details) | |
1830 | { | |
1831 | struct i40e_aq_desc desc; | |
1832 | struct i40e_aqc_driver_version *cmd = | |
1833 | (struct i40e_aqc_driver_version *)&desc.params.raw; | |
1834 | i40e_status status; | |
9d2f98e1 | 1835 | u16 len; |
56a62fc8 JB |
1836 | |
1837 | if (dv == NULL) | |
1838 | return I40E_ERR_PARAM; | |
1839 | ||
1840 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); | |
1841 | ||
3b38cd17 | 1842 | desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); |
56a62fc8 JB |
1843 | cmd->driver_major_ver = dv->major_version; |
1844 | cmd->driver_minor_ver = dv->minor_version; | |
1845 | cmd->driver_build_ver = dv->build_version; | |
1846 | cmd->driver_subbuild_ver = dv->subbuild_version; | |
d2466013 SN |
1847 | |
1848 | len = 0; | |
1849 | while (len < sizeof(dv->driver_string) && | |
1850 | (dv->driver_string[len] < 0x80) && | |
1851 | dv->driver_string[len]) | |
1852 | len++; | |
1853 | status = i40e_asq_send_command(hw, &desc, dv->driver_string, | |
1854 | len, cmd_details); | |
56a62fc8 JB |
1855 | |
1856 | return status; | |
1857 | } | |
1858 | ||
1859 | /** | |
1860 | * i40e_get_link_status - get status of the HW network link | |
1861 | * @hw: pointer to the hw struct | |
1862 | * | |
1863 | * Returns true if link is up, false if link is down. | |
1864 | * | |
1865 | * Side effect: LinkStatusEvent reporting becomes enabled | |
1866 | **/ | |
1867 | bool i40e_get_link_status(struct i40e_hw *hw) | |
1868 | { | |
1869 | i40e_status status = 0; | |
1870 | bool link_status = false; | |
1871 | ||
1872 | if (hw->phy.get_link_info) { | |
1873 | status = i40e_aq_get_link_info(hw, true, NULL, NULL); | |
1874 | ||
1875 | if (status) | |
1876 | goto i40e_get_link_status_exit; | |
1877 | } | |
1878 | ||
1879 | link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; | |
1880 | ||
1881 | i40e_get_link_status_exit: | |
1882 | return link_status; | |
1883 | } | |
1884 | ||
1885 | /** | |
1886 | * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC | |
1887 | * @hw: pointer to the hw struct | |
1888 | * @uplink_seid: the MAC or other gizmo SEID | |
1889 | * @downlink_seid: the VSI SEID | |
1890 | * @enabled_tc: bitmap of TCs to be enabled | |
1891 | * @default_port: true for default port VSI, false for control port | |
e1c51b95 | 1892 | * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support |
56a62fc8 JB |
1893 | * @veb_seid: pointer to where to put the resulting VEB SEID |
1894 | * @cmd_details: pointer to command details structure or NULL | |
1895 | * | |
1896 | * This asks the FW to add a VEB between the uplink and downlink | |
1897 | * elements. If the uplink SEID is 0, this will be a floating VEB. | |
1898 | **/ | |
1899 | i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, | |
1900 | u16 downlink_seid, u8 enabled_tc, | |
e1c51b95 KS |
1901 | bool default_port, bool enable_l2_filtering, |
1902 | u16 *veb_seid, | |
56a62fc8 JB |
1903 | struct i40e_asq_cmd_details *cmd_details) |
1904 | { | |
1905 | struct i40e_aq_desc desc; | |
1906 | struct i40e_aqc_add_veb *cmd = | |
1907 | (struct i40e_aqc_add_veb *)&desc.params.raw; | |
1908 | struct i40e_aqc_add_veb_completion *resp = | |
1909 | (struct i40e_aqc_add_veb_completion *)&desc.params.raw; | |
1910 | i40e_status status; | |
1911 | u16 veb_flags = 0; | |
1912 | ||
1913 | /* SEIDs need to either both be set or both be 0 for floating VEB */ | |
1914 | if (!!uplink_seid != !!downlink_seid) | |
1915 | return I40E_ERR_PARAM; | |
1916 | ||
1917 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); | |
1918 | ||
1919 | cmd->uplink_seid = cpu_to_le16(uplink_seid); | |
1920 | cmd->downlink_seid = cpu_to_le16(downlink_seid); | |
1921 | cmd->enable_tcs = enabled_tc; | |
1922 | if (!uplink_seid) | |
1923 | veb_flags |= I40E_AQC_ADD_VEB_FLOATING; | |
1924 | if (default_port) | |
1925 | veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; | |
1926 | else | |
1927 | veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; | |
e1c51b95 KS |
1928 | |
1929 | if (enable_l2_filtering) | |
1930 | veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; | |
1931 | ||
56a62fc8 JB |
1932 | cmd->veb_flags = cpu_to_le16(veb_flags); |
1933 | ||
1934 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1935 | ||
1936 | if (!status && veb_seid) | |
1937 | *veb_seid = le16_to_cpu(resp->veb_seid); | |
1938 | ||
1939 | return status; | |
1940 | } | |
1941 | ||
1942 | /** | |
1943 | * i40e_aq_get_veb_parameters - Retrieve VEB parameters | |
1944 | * @hw: pointer to the hw struct | |
1945 | * @veb_seid: the SEID of the VEB to query | |
1946 | * @switch_id: the uplink switch id | |
98d44381 | 1947 | * @floating: set to true if the VEB is floating |
56a62fc8 JB |
1948 | * @statistic_index: index of the stats counter block for this VEB |
1949 | * @vebs_used: number of VEB's used by function | |
98d44381 | 1950 | * @vebs_free: total VEB's not reserved by any function |
56a62fc8 JB |
1951 | * @cmd_details: pointer to command details structure or NULL |
1952 | * | |
1953 | * This retrieves the parameters for a particular VEB, specified by | |
1954 | * uplink_seid, and returns them to the caller. | |
1955 | **/ | |
1956 | i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, | |
1957 | u16 veb_seid, u16 *switch_id, | |
1958 | bool *floating, u16 *statistic_index, | |
1959 | u16 *vebs_used, u16 *vebs_free, | |
1960 | struct i40e_asq_cmd_details *cmd_details) | |
1961 | { | |
1962 | struct i40e_aq_desc desc; | |
1963 | struct i40e_aqc_get_veb_parameters_completion *cmd_resp = | |
1964 | (struct i40e_aqc_get_veb_parameters_completion *) | |
1965 | &desc.params.raw; | |
1966 | i40e_status status; | |
1967 | ||
1968 | if (veb_seid == 0) | |
1969 | return I40E_ERR_PARAM; | |
1970 | ||
1971 | i40e_fill_default_direct_cmd_desc(&desc, | |
1972 | i40e_aqc_opc_get_veb_parameters); | |
1973 | cmd_resp->seid = cpu_to_le16(veb_seid); | |
1974 | ||
1975 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
1976 | if (status) | |
1977 | goto get_veb_exit; | |
1978 | ||
1979 | if (switch_id) | |
1980 | *switch_id = le16_to_cpu(cmd_resp->switch_id); | |
1981 | if (statistic_index) | |
1982 | *statistic_index = le16_to_cpu(cmd_resp->statistic_index); | |
1983 | if (vebs_used) | |
1984 | *vebs_used = le16_to_cpu(cmd_resp->vebs_used); | |
1985 | if (vebs_free) | |
1986 | *vebs_free = le16_to_cpu(cmd_resp->vebs_free); | |
1987 | if (floating) { | |
1988 | u16 flags = le16_to_cpu(cmd_resp->veb_flags); | |
1989 | if (flags & I40E_AQC_ADD_VEB_FLOATING) | |
1990 | *floating = true; | |
1991 | else | |
1992 | *floating = false; | |
1993 | } | |
1994 | ||
1995 | get_veb_exit: | |
1996 | return status; | |
1997 | } | |
1998 | ||
1999 | /** | |
2000 | * i40e_aq_add_macvlan | |
2001 | * @hw: pointer to the hw struct | |
2002 | * @seid: VSI for the mac address | |
2003 | * @mv_list: list of macvlans to be added | |
2004 | * @count: length of the list | |
2005 | * @cmd_details: pointer to command details structure or NULL | |
2006 | * | |
2007 | * Add MAC/VLAN addresses to the HW filtering | |
2008 | **/ | |
2009 | i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, | |
2010 | struct i40e_aqc_add_macvlan_element_data *mv_list, | |
2011 | u16 count, struct i40e_asq_cmd_details *cmd_details) | |
2012 | { | |
2013 | struct i40e_aq_desc desc; | |
2014 | struct i40e_aqc_macvlan *cmd = | |
2015 | (struct i40e_aqc_macvlan *)&desc.params.raw; | |
2016 | i40e_status status; | |
2017 | u16 buf_size; | |
2018 | ||
2019 | if (count == 0 || !mv_list || !hw) | |
2020 | return I40E_ERR_PARAM; | |
2021 | ||
1efc80ee | 2022 | buf_size = count * sizeof(*mv_list); |
56a62fc8 JB |
2023 | |
2024 | /* prep the rest of the request */ | |
2025 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); | |
2026 | cmd->num_addresses = cpu_to_le16(count); | |
2027 | cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); | |
2028 | cmd->seid[1] = 0; | |
2029 | cmd->seid[2] = 0; | |
2030 | ||
2031 | desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); | |
2032 | if (buf_size > I40E_AQ_LARGE_BUF) | |
2033 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
2034 | ||
2035 | status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, | |
2036 | cmd_details); | |
2037 | ||
2038 | return status; | |
2039 | } | |
2040 | ||
2041 | /** | |
2042 | * i40e_aq_remove_macvlan | |
2043 | * @hw: pointer to the hw struct | |
2044 | * @seid: VSI for the mac address | |
2045 | * @mv_list: list of macvlans to be removed | |
2046 | * @count: length of the list | |
2047 | * @cmd_details: pointer to command details structure or NULL | |
2048 | * | |
2049 | * Remove MAC/VLAN addresses from the HW filtering | |
2050 | **/ | |
2051 | i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, | |
2052 | struct i40e_aqc_remove_macvlan_element_data *mv_list, | |
2053 | u16 count, struct i40e_asq_cmd_details *cmd_details) | |
2054 | { | |
2055 | struct i40e_aq_desc desc; | |
2056 | struct i40e_aqc_macvlan *cmd = | |
2057 | (struct i40e_aqc_macvlan *)&desc.params.raw; | |
2058 | i40e_status status; | |
2059 | u16 buf_size; | |
2060 | ||
2061 | if (count == 0 || !mv_list || !hw) | |
2062 | return I40E_ERR_PARAM; | |
2063 | ||
1efc80ee | 2064 | buf_size = count * sizeof(*mv_list); |
56a62fc8 JB |
2065 | |
2066 | /* prep the rest of the request */ | |
2067 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); | |
2068 | cmd->num_addresses = cpu_to_le16(count); | |
2069 | cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); | |
2070 | cmd->seid[1] = 0; | |
2071 | cmd->seid[2] = 0; | |
2072 | ||
2073 | desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); | |
2074 | if (buf_size > I40E_AQ_LARGE_BUF) | |
2075 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
2076 | ||
2077 | status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, | |
2078 | cmd_details); | |
2079 | ||
2080 | return status; | |
2081 | } | |
2082 | ||
56a62fc8 JB |
2083 | /** |
2084 | * i40e_aq_send_msg_to_vf | |
2085 | * @hw: pointer to the hardware structure | |
b40c82e6 | 2086 | * @vfid: VF id to send msg |
98d44381 JK |
2087 | * @v_opcode: opcodes for VF-PF communication |
2088 | * @v_retval: return error code | |
56a62fc8 JB |
2089 | * @msg: pointer to the msg buffer |
2090 | * @msglen: msg length | |
2091 | * @cmd_details: pointer to command details | |
2092 | * | |
2093 | * send msg to vf | |
2094 | **/ | |
2095 | i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, | |
2096 | u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, | |
2097 | struct i40e_asq_cmd_details *cmd_details) | |
2098 | { | |
2099 | struct i40e_aq_desc desc; | |
2100 | struct i40e_aqc_pf_vf_message *cmd = | |
2101 | (struct i40e_aqc_pf_vf_message *)&desc.params.raw; | |
2102 | i40e_status status; | |
2103 | ||
2104 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); | |
2105 | cmd->id = cpu_to_le32(vfid); | |
2106 | desc.cookie_high = cpu_to_le32(v_opcode); | |
2107 | desc.cookie_low = cpu_to_le32(v_retval); | |
2108 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); | |
2109 | if (msglen) { | |
2110 | desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | | |
2111 | I40E_AQ_FLAG_RD)); | |
2112 | if (msglen > I40E_AQ_LARGE_BUF) | |
2113 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
2114 | desc.datalen = cpu_to_le16(msglen); | |
2115 | } | |
2116 | status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); | |
2117 | ||
2118 | return status; | |
2119 | } | |
2120 | ||
9fee9db5 SN |
2121 | /** |
2122 | * i40e_aq_debug_read_register | |
2123 | * @hw: pointer to the hw struct | |
2124 | * @reg_addr: register address | |
2125 | * @reg_val: register value | |
2126 | * @cmd_details: pointer to command details structure or NULL | |
2127 | * | |
2128 | * Read the register using the admin queue commands | |
2129 | **/ | |
2130 | i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, | |
7b115dd0 | 2131 | u32 reg_addr, u64 *reg_val, |
9fee9db5 SN |
2132 | struct i40e_asq_cmd_details *cmd_details) |
2133 | { | |
2134 | struct i40e_aq_desc desc; | |
2135 | struct i40e_aqc_debug_reg_read_write *cmd_resp = | |
2136 | (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; | |
2137 | i40e_status status; | |
2138 | ||
2139 | if (reg_val == NULL) | |
2140 | return I40E_ERR_PARAM; | |
2141 | ||
7b115dd0 | 2142 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); |
9fee9db5 SN |
2143 | |
2144 | cmd_resp->address = cpu_to_le32(reg_addr); | |
2145 | ||
2146 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2147 | ||
2148 | if (!status) { | |
7b115dd0 JB |
2149 | *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | |
2150 | (u64)le32_to_cpu(cmd_resp->value_low); | |
9fee9db5 SN |
2151 | } |
2152 | ||
2153 | return status; | |
2154 | } | |
2155 | ||
53db45cd SN |
2156 | /** |
2157 | * i40e_aq_debug_write_register | |
2158 | * @hw: pointer to the hw struct | |
2159 | * @reg_addr: register address | |
2160 | * @reg_val: register value | |
2161 | * @cmd_details: pointer to command details structure or NULL | |
2162 | * | |
2163 | * Write to a register using the admin queue commands | |
2164 | **/ | |
2165 | i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, | |
2166 | u32 reg_addr, u64 reg_val, | |
2167 | struct i40e_asq_cmd_details *cmd_details) | |
2168 | { | |
2169 | struct i40e_aq_desc desc; | |
2170 | struct i40e_aqc_debug_reg_read_write *cmd = | |
2171 | (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; | |
2172 | i40e_status status; | |
2173 | ||
2174 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); | |
2175 | ||
2176 | cmd->address = cpu_to_le32(reg_addr); | |
2177 | cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); | |
2178 | cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); | |
2179 | ||
2180 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2181 | ||
2182 | return status; | |
2183 | } | |
2184 | ||
56a62fc8 JB |
2185 | /** |
2186 | * i40e_aq_set_hmc_resource_profile | |
2187 | * @hw: pointer to the hw struct | |
2188 | * @profile: type of profile the HMC is to be set as | |
2189 | * @pe_vf_enabled_count: the number of PE enabled VFs the system has | |
2190 | * @cmd_details: pointer to command details structure or NULL | |
2191 | * | |
2192 | * set the HMC profile of the device. | |
2193 | **/ | |
2194 | i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, | |
2195 | enum i40e_aq_hmc_profile profile, | |
2196 | u8 pe_vf_enabled_count, | |
2197 | struct i40e_asq_cmd_details *cmd_details) | |
2198 | { | |
2199 | struct i40e_aq_desc desc; | |
2200 | struct i40e_aq_get_set_hmc_resource_profile *cmd = | |
2201 | (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; | |
2202 | i40e_status status; | |
2203 | ||
2204 | i40e_fill_default_direct_cmd_desc(&desc, | |
2205 | i40e_aqc_opc_set_hmc_resource_profile); | |
2206 | ||
2207 | cmd->pm_profile = (u8)profile; | |
2208 | cmd->pe_vf_enabled = pe_vf_enabled_count; | |
2209 | ||
2210 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2211 | ||
2212 | return status; | |
2213 | } | |
2214 | ||
2215 | /** | |
2216 | * i40e_aq_request_resource | |
2217 | * @hw: pointer to the hw struct | |
2218 | * @resource: resource id | |
2219 | * @access: access type | |
2220 | * @sdp_number: resource number | |
2221 | * @timeout: the maximum time in ms that the driver may hold the resource | |
2222 | * @cmd_details: pointer to command details structure or NULL | |
2223 | * | |
2224 | * requests common resource using the admin queue commands | |
2225 | **/ | |
2226 | i40e_status i40e_aq_request_resource(struct i40e_hw *hw, | |
2227 | enum i40e_aq_resources_ids resource, | |
2228 | enum i40e_aq_resource_access_type access, | |
2229 | u8 sdp_number, u64 *timeout, | |
2230 | struct i40e_asq_cmd_details *cmd_details) | |
2231 | { | |
2232 | struct i40e_aq_desc desc; | |
2233 | struct i40e_aqc_request_resource *cmd_resp = | |
2234 | (struct i40e_aqc_request_resource *)&desc.params.raw; | |
2235 | i40e_status status; | |
2236 | ||
2237 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); | |
2238 | ||
2239 | cmd_resp->resource_id = cpu_to_le16(resource); | |
2240 | cmd_resp->access_type = cpu_to_le16(access); | |
2241 | cmd_resp->resource_number = cpu_to_le32(sdp_number); | |
2242 | ||
2243 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2244 | /* The completion specifies the maximum time in ms that the driver | |
2245 | * may hold the resource in the Timeout field. | |
2246 | * If the resource is held by someone else, the command completes with | |
2247 | * busy return value and the timeout field indicates the maximum time | |
2248 | * the current owner of the resource has to free it. | |
2249 | */ | |
2250 | if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) | |
2251 | *timeout = le32_to_cpu(cmd_resp->timeout); | |
2252 | ||
2253 | return status; | |
2254 | } | |
2255 | ||
2256 | /** | |
2257 | * i40e_aq_release_resource | |
2258 | * @hw: pointer to the hw struct | |
2259 | * @resource: resource id | |
2260 | * @sdp_number: resource number | |
2261 | * @cmd_details: pointer to command details structure or NULL | |
2262 | * | |
2263 | * release common resource using the admin queue commands | |
2264 | **/ | |
2265 | i40e_status i40e_aq_release_resource(struct i40e_hw *hw, | |
2266 | enum i40e_aq_resources_ids resource, | |
2267 | u8 sdp_number, | |
2268 | struct i40e_asq_cmd_details *cmd_details) | |
2269 | { | |
2270 | struct i40e_aq_desc desc; | |
2271 | struct i40e_aqc_request_resource *cmd = | |
2272 | (struct i40e_aqc_request_resource *)&desc.params.raw; | |
2273 | i40e_status status; | |
2274 | ||
2275 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); | |
2276 | ||
2277 | cmd->resource_id = cpu_to_le16(resource); | |
2278 | cmd->resource_number = cpu_to_le32(sdp_number); | |
2279 | ||
2280 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2281 | ||
2282 | return status; | |
2283 | } | |
2284 | ||
2285 | /** | |
2286 | * i40e_aq_read_nvm | |
2287 | * @hw: pointer to the hw struct | |
2288 | * @module_pointer: module pointer location in words from the NVM beginning | |
2289 | * @offset: byte offset from the module beginning | |
2290 | * @length: length of the section to be read (in bytes from the offset) | |
2291 | * @data: command buffer (size [bytes] = length) | |
2292 | * @last_command: tells if this is the last command in a series | |
2293 | * @cmd_details: pointer to command details structure or NULL | |
2294 | * | |
2295 | * Read the NVM using the admin queue commands | |
2296 | **/ | |
2297 | i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, | |
2298 | u32 offset, u16 length, void *data, | |
2299 | bool last_command, | |
2300 | struct i40e_asq_cmd_details *cmd_details) | |
2301 | { | |
2302 | struct i40e_aq_desc desc; | |
2303 | struct i40e_aqc_nvm_update *cmd = | |
2304 | (struct i40e_aqc_nvm_update *)&desc.params.raw; | |
2305 | i40e_status status; | |
2306 | ||
2307 | /* In offset the highest byte must be zeroed. */ | |
2308 | if (offset & 0xFF000000) { | |
2309 | status = I40E_ERR_PARAM; | |
2310 | goto i40e_aq_read_nvm_exit; | |
2311 | } | |
2312 | ||
2313 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); | |
2314 | ||
2315 | /* If this is the last command in a series, set the proper flag. */ | |
2316 | if (last_command) | |
2317 | cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; | |
2318 | cmd->module_pointer = module_pointer; | |
2319 | cmd->offset = cpu_to_le32(offset); | |
2320 | cmd->length = cpu_to_le16(length); | |
2321 | ||
2322 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
2323 | if (length > I40E_AQ_LARGE_BUF) | |
2324 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
2325 | ||
2326 | status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); | |
2327 | ||
2328 | i40e_aq_read_nvm_exit: | |
2329 | return status; | |
2330 | } | |
2331 | ||
cd552cb4 SN |
2332 | /** |
2333 | * i40e_aq_erase_nvm | |
2334 | * @hw: pointer to the hw struct | |
2335 | * @module_pointer: module pointer location in words from the NVM beginning | |
2336 | * @offset: offset in the module (expressed in 4 KB from module's beginning) | |
2337 | * @length: length of the section to be erased (expressed in 4 KB) | |
2338 | * @last_command: tells if this is the last command in a series | |
2339 | * @cmd_details: pointer to command details structure or NULL | |
2340 | * | |
2341 | * Erase the NVM sector using the admin queue commands | |
2342 | **/ | |
2343 | i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, | |
2344 | u32 offset, u16 length, bool last_command, | |
2345 | struct i40e_asq_cmd_details *cmd_details) | |
2346 | { | |
2347 | struct i40e_aq_desc desc; | |
2348 | struct i40e_aqc_nvm_update *cmd = | |
2349 | (struct i40e_aqc_nvm_update *)&desc.params.raw; | |
2350 | i40e_status status; | |
2351 | ||
2352 | /* In offset the highest byte must be zeroed. */ | |
2353 | if (offset & 0xFF000000) { | |
2354 | status = I40E_ERR_PARAM; | |
2355 | goto i40e_aq_erase_nvm_exit; | |
2356 | } | |
2357 | ||
2358 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); | |
2359 | ||
2360 | /* If this is the last command in a series, set the proper flag. */ | |
2361 | if (last_command) | |
2362 | cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; | |
2363 | cmd->module_pointer = module_pointer; | |
2364 | cmd->offset = cpu_to_le32(offset); | |
2365 | cmd->length = cpu_to_le16(length); | |
2366 | ||
2367 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2368 | ||
2369 | i40e_aq_erase_nvm_exit: | |
2370 | return status; | |
2371 | } | |
2372 | ||
56a62fc8 JB |
2373 | #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 |
2374 | #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 | |
2375 | #define I40E_DEV_FUNC_CAP_NPAR 0x03 | |
2376 | #define I40E_DEV_FUNC_CAP_OS2BMC 0x04 | |
2377 | #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 | |
2378 | #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 | |
2379 | #define I40E_DEV_FUNC_CAP_VF 0x13 | |
2380 | #define I40E_DEV_FUNC_CAP_VMDQ 0x14 | |
2381 | #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 | |
2382 | #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 | |
2383 | #define I40E_DEV_FUNC_CAP_VSI 0x17 | |
2384 | #define I40E_DEV_FUNC_CAP_DCB 0x18 | |
2385 | #define I40E_DEV_FUNC_CAP_FCOE 0x21 | |
63d7e5a4 | 2386 | #define I40E_DEV_FUNC_CAP_ISCSI 0x22 |
56a62fc8 JB |
2387 | #define I40E_DEV_FUNC_CAP_RSS 0x40 |
2388 | #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 | |
2389 | #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 | |
2390 | #define I40E_DEV_FUNC_CAP_MSIX 0x43 | |
2391 | #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 | |
2392 | #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 | |
2393 | #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 | |
2394 | #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1 | |
2395 | #define I40E_DEV_FUNC_CAP_CEM 0xF2 | |
2396 | #define I40E_DEV_FUNC_CAP_IWARP 0x51 | |
2397 | #define I40E_DEV_FUNC_CAP_LED 0x61 | |
2398 | #define I40E_DEV_FUNC_CAP_SDP 0x62 | |
2399 | #define I40E_DEV_FUNC_CAP_MDIO 0x63 | |
2400 | ||
2401 | /** | |
2402 | * i40e_parse_discover_capabilities | |
2403 | * @hw: pointer to the hw struct | |
2404 | * @buff: pointer to a buffer containing device/function capability records | |
2405 | * @cap_count: number of capability records in the list | |
2406 | * @list_type_opc: type of capabilities list to parse | |
2407 | * | |
2408 | * Parse the device/function capabilities list. | |
2409 | **/ | |
2410 | static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, | |
2411 | u32 cap_count, | |
2412 | enum i40e_admin_queue_opc list_type_opc) | |
2413 | { | |
2414 | struct i40e_aqc_list_capabilities_element_resp *cap; | |
9fee9db5 | 2415 | u32 valid_functions, num_functions; |
56a62fc8 JB |
2416 | u32 number, logical_id, phys_id; |
2417 | struct i40e_hw_capabilities *p; | |
56a62fc8 JB |
2418 | u32 i = 0; |
2419 | u16 id; | |
2420 | ||
2421 | cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; | |
2422 | ||
2423 | if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) | |
b58f2f72 | 2424 | p = &hw->dev_caps; |
56a62fc8 | 2425 | else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) |
b58f2f72 | 2426 | p = &hw->func_caps; |
56a62fc8 JB |
2427 | else |
2428 | return; | |
2429 | ||
2430 | for (i = 0; i < cap_count; i++, cap++) { | |
2431 | id = le16_to_cpu(cap->id); | |
2432 | number = le32_to_cpu(cap->number); | |
2433 | logical_id = le32_to_cpu(cap->logical_id); | |
2434 | phys_id = le32_to_cpu(cap->phys_id); | |
2435 | ||
2436 | switch (id) { | |
2437 | case I40E_DEV_FUNC_CAP_SWITCH_MODE: | |
2438 | p->switch_mode = number; | |
2439 | break; | |
2440 | case I40E_DEV_FUNC_CAP_MGMT_MODE: | |
2441 | p->management_mode = number; | |
2442 | break; | |
2443 | case I40E_DEV_FUNC_CAP_NPAR: | |
2444 | p->npar_enable = number; | |
2445 | break; | |
2446 | case I40E_DEV_FUNC_CAP_OS2BMC: | |
2447 | p->os2bmc = number; | |
2448 | break; | |
2449 | case I40E_DEV_FUNC_CAP_VALID_FUNC: | |
2450 | p->valid_functions = number; | |
2451 | break; | |
2452 | case I40E_DEV_FUNC_CAP_SRIOV_1_1: | |
2453 | if (number == 1) | |
2454 | p->sr_iov_1_1 = true; | |
2455 | break; | |
2456 | case I40E_DEV_FUNC_CAP_VF: | |
2457 | p->num_vfs = number; | |
2458 | p->vf_base_id = logical_id; | |
2459 | break; | |
2460 | case I40E_DEV_FUNC_CAP_VMDQ: | |
2461 | if (number == 1) | |
2462 | p->vmdq = true; | |
2463 | break; | |
2464 | case I40E_DEV_FUNC_CAP_802_1_QBG: | |
2465 | if (number == 1) | |
2466 | p->evb_802_1_qbg = true; | |
2467 | break; | |
2468 | case I40E_DEV_FUNC_CAP_802_1_QBH: | |
2469 | if (number == 1) | |
2470 | p->evb_802_1_qbh = true; | |
2471 | break; | |
2472 | case I40E_DEV_FUNC_CAP_VSI: | |
2473 | p->num_vsis = number; | |
2474 | break; | |
2475 | case I40E_DEV_FUNC_CAP_DCB: | |
2476 | if (number == 1) { | |
2477 | p->dcb = true; | |
2478 | p->enabled_tcmap = logical_id; | |
2479 | p->maxtc = phys_id; | |
2480 | } | |
2481 | break; | |
2482 | case I40E_DEV_FUNC_CAP_FCOE: | |
2483 | if (number == 1) | |
2484 | p->fcoe = true; | |
2485 | break; | |
63d7e5a4 NP |
2486 | case I40E_DEV_FUNC_CAP_ISCSI: |
2487 | if (number == 1) | |
2488 | p->iscsi = true; | |
2489 | break; | |
56a62fc8 JB |
2490 | case I40E_DEV_FUNC_CAP_RSS: |
2491 | p->rss = true; | |
e157ea30 | 2492 | p->rss_table_size = number; |
56a62fc8 JB |
2493 | p->rss_table_entry_width = logical_id; |
2494 | break; | |
2495 | case I40E_DEV_FUNC_CAP_RX_QUEUES: | |
2496 | p->num_rx_qp = number; | |
2497 | p->base_queue = phys_id; | |
2498 | break; | |
2499 | case I40E_DEV_FUNC_CAP_TX_QUEUES: | |
2500 | p->num_tx_qp = number; | |
2501 | p->base_queue = phys_id; | |
2502 | break; | |
2503 | case I40E_DEV_FUNC_CAP_MSIX: | |
2504 | p->num_msix_vectors = number; | |
2505 | break; | |
2506 | case I40E_DEV_FUNC_CAP_MSIX_VF: | |
2507 | p->num_msix_vectors_vf = number; | |
2508 | break; | |
2509 | case I40E_DEV_FUNC_CAP_MFP_MODE_1: | |
2510 | if (number == 1) | |
2511 | p->mfp_mode_1 = true; | |
2512 | break; | |
2513 | case I40E_DEV_FUNC_CAP_CEM: | |
2514 | if (number == 1) | |
2515 | p->mgmt_cem = true; | |
2516 | break; | |
2517 | case I40E_DEV_FUNC_CAP_IWARP: | |
2518 | if (number == 1) | |
2519 | p->iwarp = true; | |
2520 | break; | |
2521 | case I40E_DEV_FUNC_CAP_LED: | |
2522 | if (phys_id < I40E_HW_CAP_MAX_GPIO) | |
2523 | p->led[phys_id] = true; | |
2524 | break; | |
2525 | case I40E_DEV_FUNC_CAP_SDP: | |
2526 | if (phys_id < I40E_HW_CAP_MAX_GPIO) | |
2527 | p->sdp[phys_id] = true; | |
2528 | break; | |
2529 | case I40E_DEV_FUNC_CAP_MDIO: | |
2530 | if (number == 1) { | |
2531 | p->mdio_port_num = phys_id; | |
2532 | p->mdio_port_mode = logical_id; | |
2533 | } | |
2534 | break; | |
2535 | case I40E_DEV_FUNC_CAP_IEEE_1588: | |
2536 | if (number == 1) | |
2537 | p->ieee_1588 = true; | |
2538 | break; | |
2539 | case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: | |
2540 | p->fd = true; | |
2541 | p->fd_filters_guaranteed = number; | |
2542 | p->fd_filters_best_effort = logical_id; | |
2543 | break; | |
2544 | default: | |
2545 | break; | |
2546 | } | |
2547 | } | |
2548 | ||
f18ae100 VD |
2549 | if (p->fcoe) |
2550 | i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); | |
2551 | ||
566bb85d VD |
2552 | /* Software override ensuring FCoE is disabled if npar or mfp |
2553 | * mode because it is not supported in these modes. | |
2554 | */ | |
2555 | if (p->npar_enable || p->mfp_mode_1) | |
2556 | p->fcoe = false; | |
2557 | ||
9fee9db5 SN |
2558 | /* count the enabled ports (aka the "not disabled" ports) */ |
2559 | hw->num_ports = 0; | |
2560 | for (i = 0; i < 4; i++) { | |
2561 | u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); | |
2562 | u64 port_cfg = 0; | |
2563 | ||
2564 | /* use AQ read to get the physical register offset instead | |
2565 | * of the port relative offset | |
2566 | */ | |
2567 | i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); | |
2568 | if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) | |
2569 | hw->num_ports++; | |
2570 | } | |
2571 | ||
2572 | valid_functions = p->valid_functions; | |
2573 | num_functions = 0; | |
2574 | while (valid_functions) { | |
2575 | if (valid_functions & 1) | |
2576 | num_functions++; | |
2577 | valid_functions >>= 1; | |
2578 | } | |
2579 | ||
2580 | /* partition id is 1-based, and functions are evenly spread | |
2581 | * across the ports as partitions | |
2582 | */ | |
2583 | hw->partition_id = (hw->pf_id / hw->num_ports) + 1; | |
2584 | hw->num_partitions = num_functions / hw->num_ports; | |
2585 | ||
56a62fc8 JB |
2586 | /* additional HW specific goodies that might |
2587 | * someday be HW version specific | |
2588 | */ | |
2589 | p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; | |
2590 | } | |
2591 | ||
2592 | /** | |
2593 | * i40e_aq_discover_capabilities | |
2594 | * @hw: pointer to the hw struct | |
2595 | * @buff: a virtual buffer to hold the capabilities | |
2596 | * @buff_size: Size of the virtual buffer | |
2597 | * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM | |
2598 | * @list_type_opc: capabilities type to discover - pass in the command opcode | |
2599 | * @cmd_details: pointer to command details structure or NULL | |
2600 | * | |
2601 | * Get the device capabilities descriptions from the firmware | |
2602 | **/ | |
2603 | i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, | |
2604 | void *buff, u16 buff_size, u16 *data_size, | |
2605 | enum i40e_admin_queue_opc list_type_opc, | |
2606 | struct i40e_asq_cmd_details *cmd_details) | |
2607 | { | |
2608 | struct i40e_aqc_list_capabilites *cmd; | |
56a62fc8 | 2609 | struct i40e_aq_desc desc; |
8fb905b3 | 2610 | i40e_status status = 0; |
56a62fc8 JB |
2611 | |
2612 | cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; | |
2613 | ||
2614 | if (list_type_opc != i40e_aqc_opc_list_func_capabilities && | |
2615 | list_type_opc != i40e_aqc_opc_list_dev_capabilities) { | |
2616 | status = I40E_ERR_PARAM; | |
2617 | goto exit; | |
2618 | } | |
2619 | ||
2620 | i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); | |
2621 | ||
2622 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
2623 | if (buff_size > I40E_AQ_LARGE_BUF) | |
2624 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
2625 | ||
2626 | status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); | |
2627 | *data_size = le16_to_cpu(desc.datalen); | |
2628 | ||
2629 | if (status) | |
2630 | goto exit; | |
2631 | ||
2632 | i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), | |
2633 | list_type_opc); | |
2634 | ||
2635 | exit: | |
2636 | return status; | |
2637 | } | |
2638 | ||
cd552cb4 SN |
2639 | /** |
2640 | * i40e_aq_update_nvm | |
2641 | * @hw: pointer to the hw struct | |
2642 | * @module_pointer: module pointer location in words from the NVM beginning | |
2643 | * @offset: byte offset from the module beginning | |
2644 | * @length: length of the section to be written (in bytes from the offset) | |
2645 | * @data: command buffer (size [bytes] = length) | |
2646 | * @last_command: tells if this is the last command in a series | |
2647 | * @cmd_details: pointer to command details structure or NULL | |
2648 | * | |
2649 | * Update the NVM using the admin queue commands | |
2650 | **/ | |
2651 | i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, | |
2652 | u32 offset, u16 length, void *data, | |
2653 | bool last_command, | |
2654 | struct i40e_asq_cmd_details *cmd_details) | |
2655 | { | |
2656 | struct i40e_aq_desc desc; | |
2657 | struct i40e_aqc_nvm_update *cmd = | |
2658 | (struct i40e_aqc_nvm_update *)&desc.params.raw; | |
2659 | i40e_status status; | |
2660 | ||
2661 | /* In offset the highest byte must be zeroed. */ | |
2662 | if (offset & 0xFF000000) { | |
2663 | status = I40E_ERR_PARAM; | |
2664 | goto i40e_aq_update_nvm_exit; | |
2665 | } | |
2666 | ||
2667 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); | |
2668 | ||
2669 | /* If this is the last command in a series, set the proper flag. */ | |
2670 | if (last_command) | |
2671 | cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; | |
2672 | cmd->module_pointer = module_pointer; | |
2673 | cmd->offset = cpu_to_le32(offset); | |
2674 | cmd->length = cpu_to_le16(length); | |
2675 | ||
2676 | desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); | |
2677 | if (length > I40E_AQ_LARGE_BUF) | |
2678 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
2679 | ||
2680 | status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); | |
2681 | ||
2682 | i40e_aq_update_nvm_exit: | |
2683 | return status; | |
2684 | } | |
2685 | ||
56a62fc8 JB |
2686 | /** |
2687 | * i40e_aq_get_lldp_mib | |
2688 | * @hw: pointer to the hw struct | |
2689 | * @bridge_type: type of bridge requested | |
2690 | * @mib_type: Local, Remote or both Local and Remote MIBs | |
2691 | * @buff: pointer to a user supplied buffer to store the MIB block | |
2692 | * @buff_size: size of the buffer (in bytes) | |
2693 | * @local_len : length of the returned Local LLDP MIB | |
2694 | * @remote_len: length of the returned Remote LLDP MIB | |
2695 | * @cmd_details: pointer to command details structure or NULL | |
2696 | * | |
2697 | * Requests the complete LLDP MIB (entire packet). | |
2698 | **/ | |
2699 | i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, | |
2700 | u8 mib_type, void *buff, u16 buff_size, | |
2701 | u16 *local_len, u16 *remote_len, | |
2702 | struct i40e_asq_cmd_details *cmd_details) | |
2703 | { | |
2704 | struct i40e_aq_desc desc; | |
2705 | struct i40e_aqc_lldp_get_mib *cmd = | |
2706 | (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; | |
2707 | struct i40e_aqc_lldp_get_mib *resp = | |
2708 | (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; | |
2709 | i40e_status status; | |
2710 | ||
2711 | if (buff_size == 0 || !buff) | |
2712 | return I40E_ERR_PARAM; | |
2713 | ||
2714 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); | |
2715 | /* Indirect Command */ | |
2716 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
2717 | ||
2718 | cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; | |
2719 | cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & | |
2720 | I40E_AQ_LLDP_BRIDGE_TYPE_MASK); | |
2721 | ||
2722 | desc.datalen = cpu_to_le16(buff_size); | |
2723 | ||
2724 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
2725 | if (buff_size > I40E_AQ_LARGE_BUF) | |
2726 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
2727 | ||
2728 | status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); | |
2729 | if (!status) { | |
2730 | if (local_len != NULL) | |
2731 | *local_len = le16_to_cpu(resp->local_len); | |
2732 | if (remote_len != NULL) | |
2733 | *remote_len = le16_to_cpu(resp->remote_len); | |
2734 | } | |
2735 | ||
2736 | return status; | |
2737 | } | |
2738 | ||
2739 | /** | |
2740 | * i40e_aq_cfg_lldp_mib_change_event | |
2741 | * @hw: pointer to the hw struct | |
2742 | * @enable_update: Enable or Disable event posting | |
2743 | * @cmd_details: pointer to command details structure or NULL | |
2744 | * | |
2745 | * Enable or Disable posting of an event on ARQ when LLDP MIB | |
2746 | * associated with the interface changes | |
2747 | **/ | |
2748 | i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, | |
2749 | bool enable_update, | |
2750 | struct i40e_asq_cmd_details *cmd_details) | |
2751 | { | |
2752 | struct i40e_aq_desc desc; | |
2753 | struct i40e_aqc_lldp_update_mib *cmd = | |
2754 | (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; | |
2755 | i40e_status status; | |
2756 | ||
2757 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); | |
2758 | ||
2759 | if (!enable_update) | |
2760 | cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; | |
2761 | ||
2762 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2763 | ||
2764 | return status; | |
2765 | } | |
2766 | ||
2767 | /** | |
2768 | * i40e_aq_stop_lldp | |
2769 | * @hw: pointer to the hw struct | |
2770 | * @shutdown_agent: True if LLDP Agent needs to be Shutdown | |
2771 | * @cmd_details: pointer to command details structure or NULL | |
2772 | * | |
2773 | * Stop or Shutdown the embedded LLDP Agent | |
2774 | **/ | |
2775 | i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, | |
2776 | struct i40e_asq_cmd_details *cmd_details) | |
2777 | { | |
2778 | struct i40e_aq_desc desc; | |
2779 | struct i40e_aqc_lldp_stop *cmd = | |
2780 | (struct i40e_aqc_lldp_stop *)&desc.params.raw; | |
2781 | i40e_status status; | |
2782 | ||
2783 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); | |
2784 | ||
2785 | if (shutdown_agent) | |
2786 | cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; | |
2787 | ||
2788 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2789 | ||
2790 | return status; | |
2791 | } | |
2792 | ||
2793 | /** | |
2794 | * i40e_aq_start_lldp | |
2795 | * @hw: pointer to the hw struct | |
2796 | * @cmd_details: pointer to command details structure or NULL | |
2797 | * | |
2798 | * Start the embedded LLDP Agent on all ports. | |
2799 | **/ | |
2800 | i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, | |
2801 | struct i40e_asq_cmd_details *cmd_details) | |
2802 | { | |
2803 | struct i40e_aq_desc desc; | |
2804 | struct i40e_aqc_lldp_start *cmd = | |
2805 | (struct i40e_aqc_lldp_start *)&desc.params.raw; | |
2806 | i40e_status status; | |
2807 | ||
2808 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); | |
2809 | ||
2810 | cmd->command = I40E_AQ_LLDP_AGENT_START; | |
2811 | ||
2812 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2813 | ||
2814 | return status; | |
2815 | } | |
2816 | ||
9fa61dd2 NP |
2817 | /** |
2818 | * i40e_aq_get_cee_dcb_config | |
2819 | * @hw: pointer to the hw struct | |
2820 | * @buff: response buffer that stores CEE operational configuration | |
2821 | * @buff_size: size of the buffer passed | |
2822 | * @cmd_details: pointer to command details structure or NULL | |
2823 | * | |
2824 | * Get CEE DCBX mode operational configuration from firmware | |
2825 | **/ | |
2826 | i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, | |
2827 | void *buff, u16 buff_size, | |
2828 | struct i40e_asq_cmd_details *cmd_details) | |
2829 | { | |
2830 | struct i40e_aq_desc desc; | |
2831 | i40e_status status; | |
2832 | ||
2833 | if (buff_size == 0 || !buff) | |
2834 | return I40E_ERR_PARAM; | |
2835 | ||
2836 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); | |
2837 | ||
2838 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
2839 | status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, | |
2840 | cmd_details); | |
2841 | ||
2842 | return status; | |
2843 | } | |
2844 | ||
a1c9a9d9 JK |
2845 | /** |
2846 | * i40e_aq_add_udp_tunnel | |
2847 | * @hw: pointer to the hw struct | |
2848 | * @udp_port: the UDP port to add | |
2849 | * @header_len: length of the tunneling header length in DWords | |
2850 | * @protocol_index: protocol index type | |
98d44381 | 2851 | * @filter_index: pointer to filter index |
a1c9a9d9 JK |
2852 | * @cmd_details: pointer to command details structure or NULL |
2853 | **/ | |
2854 | i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, | |
f4f94b94 KS |
2855 | u16 udp_port, u8 protocol_index, |
2856 | u8 *filter_index, | |
a1c9a9d9 JK |
2857 | struct i40e_asq_cmd_details *cmd_details) |
2858 | { | |
2859 | struct i40e_aq_desc desc; | |
2860 | struct i40e_aqc_add_udp_tunnel *cmd = | |
2861 | (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; | |
2862 | struct i40e_aqc_del_udp_tunnel_completion *resp = | |
2863 | (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; | |
2864 | i40e_status status; | |
2865 | ||
2866 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); | |
2867 | ||
2868 | cmd->udp_port = cpu_to_le16(udp_port); | |
981b7545 | 2869 | cmd->protocol_type = protocol_index; |
a1c9a9d9 JK |
2870 | |
2871 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2872 | ||
65d13461 | 2873 | if (!status && filter_index) |
a1c9a9d9 JK |
2874 | *filter_index = resp->index; |
2875 | ||
2876 | return status; | |
2877 | } | |
2878 | ||
2879 | /** | |
2880 | * i40e_aq_del_udp_tunnel | |
2881 | * @hw: pointer to the hw struct | |
2882 | * @index: filter index | |
2883 | * @cmd_details: pointer to command details structure or NULL | |
2884 | **/ | |
2885 | i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, | |
2886 | struct i40e_asq_cmd_details *cmd_details) | |
2887 | { | |
2888 | struct i40e_aq_desc desc; | |
2889 | struct i40e_aqc_remove_udp_tunnel *cmd = | |
2890 | (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; | |
2891 | i40e_status status; | |
2892 | ||
2893 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); | |
2894 | ||
2895 | cmd->index = index; | |
2896 | ||
2897 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2898 | ||
2899 | return status; | |
2900 | } | |
2901 | ||
56a62fc8 JB |
2902 | /** |
2903 | * i40e_aq_delete_element - Delete switch element | |
2904 | * @hw: pointer to the hw struct | |
2905 | * @seid: the SEID to delete from the switch | |
2906 | * @cmd_details: pointer to command details structure or NULL | |
2907 | * | |
2908 | * This deletes a switch element from the switch. | |
2909 | **/ | |
2910 | i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, | |
2911 | struct i40e_asq_cmd_details *cmd_details) | |
2912 | { | |
2913 | struct i40e_aq_desc desc; | |
2914 | struct i40e_aqc_switch_seid *cmd = | |
2915 | (struct i40e_aqc_switch_seid *)&desc.params.raw; | |
2916 | i40e_status status; | |
2917 | ||
2918 | if (seid == 0) | |
2919 | return I40E_ERR_PARAM; | |
2920 | ||
2921 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); | |
2922 | ||
2923 | cmd->seid = cpu_to_le16(seid); | |
2924 | ||
2925 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2926 | ||
2927 | return status; | |
2928 | } | |
2929 | ||
afb3ff0d NP |
2930 | /** |
2931 | * i40e_aq_dcb_updated - DCB Updated Command | |
2932 | * @hw: pointer to the hw struct | |
2933 | * @cmd_details: pointer to command details structure or NULL | |
2934 | * | |
2935 | * EMP will return when the shared RPB settings have been | |
2936 | * recomputed and modified. The retval field in the descriptor | |
2937 | * will be set to 0 when RPB is modified. | |
2938 | **/ | |
2939 | i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, | |
2940 | struct i40e_asq_cmd_details *cmd_details) | |
2941 | { | |
2942 | struct i40e_aq_desc desc; | |
2943 | i40e_status status; | |
2944 | ||
2945 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); | |
2946 | ||
2947 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
2948 | ||
2949 | return status; | |
2950 | } | |
2951 | ||
56a62fc8 JB |
2952 | /** |
2953 | * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler | |
2954 | * @hw: pointer to the hw struct | |
2955 | * @seid: seid for the physical port/switching component/vsi | |
2956 | * @buff: Indirect buffer to hold data parameters and response | |
2957 | * @buff_size: Indirect buffer size | |
2958 | * @opcode: Tx scheduler AQ command opcode | |
2959 | * @cmd_details: pointer to command details structure or NULL | |
2960 | * | |
2961 | * Generic command handler for Tx scheduler AQ commands | |
2962 | **/ | |
2963 | static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, | |
2964 | void *buff, u16 buff_size, | |
2965 | enum i40e_admin_queue_opc opcode, | |
2966 | struct i40e_asq_cmd_details *cmd_details) | |
2967 | { | |
2968 | struct i40e_aq_desc desc; | |
2969 | struct i40e_aqc_tx_sched_ind *cmd = | |
2970 | (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; | |
2971 | i40e_status status; | |
2972 | bool cmd_param_flag = false; | |
2973 | ||
2974 | switch (opcode) { | |
2975 | case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: | |
2976 | case i40e_aqc_opc_configure_vsi_tc_bw: | |
2977 | case i40e_aqc_opc_enable_switching_comp_ets: | |
2978 | case i40e_aqc_opc_modify_switching_comp_ets: | |
2979 | case i40e_aqc_opc_disable_switching_comp_ets: | |
2980 | case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: | |
2981 | case i40e_aqc_opc_configure_switching_comp_bw_config: | |
2982 | cmd_param_flag = true; | |
2983 | break; | |
2984 | case i40e_aqc_opc_query_vsi_bw_config: | |
2985 | case i40e_aqc_opc_query_vsi_ets_sla_config: | |
2986 | case i40e_aqc_opc_query_switching_comp_ets_config: | |
2987 | case i40e_aqc_opc_query_port_ets_config: | |
2988 | case i40e_aqc_opc_query_switching_comp_bw_config: | |
2989 | cmd_param_flag = false; | |
2990 | break; | |
2991 | default: | |
2992 | return I40E_ERR_PARAM; | |
2993 | } | |
2994 | ||
2995 | i40e_fill_default_direct_cmd_desc(&desc, opcode); | |
2996 | ||
2997 | /* Indirect command */ | |
2998 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
2999 | if (cmd_param_flag) | |
3000 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); | |
3001 | if (buff_size > I40E_AQ_LARGE_BUF) | |
3002 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
3003 | ||
3004 | desc.datalen = cpu_to_le16(buff_size); | |
3005 | ||
3006 | cmd->vsi_seid = cpu_to_le16(seid); | |
3007 | ||
3008 | status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); | |
3009 | ||
3010 | return status; | |
3011 | } | |
3012 | ||
6b192891 MW |
3013 | /** |
3014 | * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit | |
3015 | * @hw: pointer to the hw struct | |
3016 | * @seid: VSI seid | |
3017 | * @credit: BW limit credits (0 = disabled) | |
3018 | * @max_credit: Max BW limit credits | |
3019 | * @cmd_details: pointer to command details structure or NULL | |
3020 | **/ | |
3021 | i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, | |
3022 | u16 seid, u16 credit, u8 max_credit, | |
3023 | struct i40e_asq_cmd_details *cmd_details) | |
3024 | { | |
3025 | struct i40e_aq_desc desc; | |
3026 | struct i40e_aqc_configure_vsi_bw_limit *cmd = | |
3027 | (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; | |
3028 | i40e_status status; | |
3029 | ||
3030 | i40e_fill_default_direct_cmd_desc(&desc, | |
3031 | i40e_aqc_opc_configure_vsi_bw_limit); | |
3032 | ||
3033 | cmd->vsi_seid = cpu_to_le16(seid); | |
3034 | cmd->credit = cpu_to_le16(credit); | |
3035 | cmd->max_credit = max_credit; | |
3036 | ||
3037 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
3038 | ||
3039 | return status; | |
3040 | } | |
3041 | ||
56a62fc8 JB |
3042 | /** |
3043 | * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC | |
3044 | * @hw: pointer to the hw struct | |
3045 | * @seid: VSI seid | |
3046 | * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits | |
3047 | * @cmd_details: pointer to command details structure or NULL | |
3048 | **/ | |
3049 | i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, | |
3050 | u16 seid, | |
3051 | struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, | |
3052 | struct i40e_asq_cmd_details *cmd_details) | |
3053 | { | |
3054 | return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), | |
3055 | i40e_aqc_opc_configure_vsi_tc_bw, | |
3056 | cmd_details); | |
3057 | } | |
3058 | ||
afb3ff0d NP |
3059 | /** |
3060 | * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port | |
3061 | * @hw: pointer to the hw struct | |
3062 | * @seid: seid of the switching component connected to Physical Port | |
3063 | * @ets_data: Buffer holding ETS parameters | |
3064 | * @cmd_details: pointer to command details structure or NULL | |
3065 | **/ | |
3066 | i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, | |
3067 | u16 seid, | |
3068 | struct i40e_aqc_configure_switching_comp_ets_data *ets_data, | |
3069 | enum i40e_admin_queue_opc opcode, | |
3070 | struct i40e_asq_cmd_details *cmd_details) | |
3071 | { | |
3072 | return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, | |
3073 | sizeof(*ets_data), opcode, cmd_details); | |
3074 | } | |
3075 | ||
3076 | /** | |
3077 | * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC | |
3078 | * @hw: pointer to the hw struct | |
3079 | * @seid: seid of the switching component | |
3080 | * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits | |
3081 | * @cmd_details: pointer to command details structure or NULL | |
3082 | **/ | |
3083 | i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, | |
3084 | u16 seid, | |
3085 | struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, | |
3086 | struct i40e_asq_cmd_details *cmd_details) | |
3087 | { | |
3088 | return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), | |
3089 | i40e_aqc_opc_configure_switching_comp_bw_config, | |
3090 | cmd_details); | |
3091 | } | |
3092 | ||
56a62fc8 JB |
3093 | /** |
3094 | * i40e_aq_query_vsi_bw_config - Query VSI BW configuration | |
3095 | * @hw: pointer to the hw struct | |
3096 | * @seid: seid of the VSI | |
3097 | * @bw_data: Buffer to hold VSI BW configuration | |
3098 | * @cmd_details: pointer to command details structure or NULL | |
3099 | **/ | |
3100 | i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, | |
3101 | u16 seid, | |
3102 | struct i40e_aqc_query_vsi_bw_config_resp *bw_data, | |
3103 | struct i40e_asq_cmd_details *cmd_details) | |
3104 | { | |
3105 | return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), | |
3106 | i40e_aqc_opc_query_vsi_bw_config, | |
3107 | cmd_details); | |
3108 | } | |
3109 | ||
3110 | /** | |
3111 | * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC | |
3112 | * @hw: pointer to the hw struct | |
3113 | * @seid: seid of the VSI | |
3114 | * @bw_data: Buffer to hold VSI BW configuration per TC | |
3115 | * @cmd_details: pointer to command details structure or NULL | |
3116 | **/ | |
3117 | i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, | |
3118 | u16 seid, | |
3119 | struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, | |
3120 | struct i40e_asq_cmd_details *cmd_details) | |
3121 | { | |
3122 | return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), | |
3123 | i40e_aqc_opc_query_vsi_ets_sla_config, | |
3124 | cmd_details); | |
3125 | } | |
3126 | ||
3127 | /** | |
3128 | * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC | |
3129 | * @hw: pointer to the hw struct | |
3130 | * @seid: seid of the switching component | |
3131 | * @bw_data: Buffer to hold switching component's per TC BW config | |
3132 | * @cmd_details: pointer to command details structure or NULL | |
3133 | **/ | |
3134 | i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, | |
3135 | u16 seid, | |
3136 | struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, | |
3137 | struct i40e_asq_cmd_details *cmd_details) | |
3138 | { | |
3139 | return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), | |
3140 | i40e_aqc_opc_query_switching_comp_ets_config, | |
3141 | cmd_details); | |
3142 | } | |
3143 | ||
3144 | /** | |
3145 | * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration | |
3146 | * @hw: pointer to the hw struct | |
3147 | * @seid: seid of the VSI or switching component connected to Physical Port | |
3148 | * @bw_data: Buffer to hold current ETS configuration for the Physical Port | |
3149 | * @cmd_details: pointer to command details structure or NULL | |
3150 | **/ | |
3151 | i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, | |
3152 | u16 seid, | |
3153 | struct i40e_aqc_query_port_ets_config_resp *bw_data, | |
3154 | struct i40e_asq_cmd_details *cmd_details) | |
3155 | { | |
3156 | return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), | |
3157 | i40e_aqc_opc_query_port_ets_config, | |
3158 | cmd_details); | |
3159 | } | |
3160 | ||
3161 | /** | |
3162 | * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration | |
3163 | * @hw: pointer to the hw struct | |
3164 | * @seid: seid of the switching component | |
3165 | * @bw_data: Buffer to hold switching component's BW configuration | |
3166 | * @cmd_details: pointer to command details structure or NULL | |
3167 | **/ | |
3168 | i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, | |
3169 | u16 seid, | |
3170 | struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, | |
3171 | struct i40e_asq_cmd_details *cmd_details) | |
3172 | { | |
3173 | return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), | |
3174 | i40e_aqc_opc_query_switching_comp_bw_config, | |
3175 | cmd_details); | |
3176 | } | |
3177 | ||
3178 | /** | |
3179 | * i40e_validate_filter_settings | |
3180 | * @hw: pointer to the hardware structure | |
3181 | * @settings: Filter control settings | |
3182 | * | |
3183 | * Check and validate the filter control settings passed. | |
3184 | * The function checks for the valid filter/context sizes being | |
3185 | * passed for FCoE and PE. | |
3186 | * | |
3187 | * Returns 0 if the values passed are valid and within | |
3188 | * range else returns an error. | |
3189 | **/ | |
3190 | static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, | |
3191 | struct i40e_filter_control_settings *settings) | |
3192 | { | |
3193 | u32 fcoe_cntx_size, fcoe_filt_size; | |
3194 | u32 pe_cntx_size, pe_filt_size; | |
467d729a | 3195 | u32 fcoe_fmax; |
56a62fc8 JB |
3196 | u32 val; |
3197 | ||
3198 | /* Validate FCoE settings passed */ | |
3199 | switch (settings->fcoe_filt_num) { | |
3200 | case I40E_HASH_FILTER_SIZE_1K: | |
3201 | case I40E_HASH_FILTER_SIZE_2K: | |
3202 | case I40E_HASH_FILTER_SIZE_4K: | |
3203 | case I40E_HASH_FILTER_SIZE_8K: | |
3204 | case I40E_HASH_FILTER_SIZE_16K: | |
3205 | case I40E_HASH_FILTER_SIZE_32K: | |
3206 | fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; | |
3207 | fcoe_filt_size <<= (u32)settings->fcoe_filt_num; | |
3208 | break; | |
3209 | default: | |
3210 | return I40E_ERR_PARAM; | |
3211 | } | |
3212 | ||
3213 | switch (settings->fcoe_cntx_num) { | |
3214 | case I40E_DMA_CNTX_SIZE_512: | |
3215 | case I40E_DMA_CNTX_SIZE_1K: | |
3216 | case I40E_DMA_CNTX_SIZE_2K: | |
3217 | case I40E_DMA_CNTX_SIZE_4K: | |
3218 | fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; | |
3219 | fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; | |
3220 | break; | |
3221 | default: | |
3222 | return I40E_ERR_PARAM; | |
3223 | } | |
3224 | ||
3225 | /* Validate PE settings passed */ | |
3226 | switch (settings->pe_filt_num) { | |
3227 | case I40E_HASH_FILTER_SIZE_1K: | |
3228 | case I40E_HASH_FILTER_SIZE_2K: | |
3229 | case I40E_HASH_FILTER_SIZE_4K: | |
3230 | case I40E_HASH_FILTER_SIZE_8K: | |
3231 | case I40E_HASH_FILTER_SIZE_16K: | |
3232 | case I40E_HASH_FILTER_SIZE_32K: | |
3233 | case I40E_HASH_FILTER_SIZE_64K: | |
3234 | case I40E_HASH_FILTER_SIZE_128K: | |
3235 | case I40E_HASH_FILTER_SIZE_256K: | |
3236 | case I40E_HASH_FILTER_SIZE_512K: | |
3237 | case I40E_HASH_FILTER_SIZE_1M: | |
3238 | pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; | |
3239 | pe_filt_size <<= (u32)settings->pe_filt_num; | |
3240 | break; | |
3241 | default: | |
3242 | return I40E_ERR_PARAM; | |
3243 | } | |
3244 | ||
3245 | switch (settings->pe_cntx_num) { | |
3246 | case I40E_DMA_CNTX_SIZE_512: | |
3247 | case I40E_DMA_CNTX_SIZE_1K: | |
3248 | case I40E_DMA_CNTX_SIZE_2K: | |
3249 | case I40E_DMA_CNTX_SIZE_4K: | |
3250 | case I40E_DMA_CNTX_SIZE_8K: | |
3251 | case I40E_DMA_CNTX_SIZE_16K: | |
3252 | case I40E_DMA_CNTX_SIZE_32K: | |
3253 | case I40E_DMA_CNTX_SIZE_64K: | |
3254 | case I40E_DMA_CNTX_SIZE_128K: | |
3255 | case I40E_DMA_CNTX_SIZE_256K: | |
3256 | pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; | |
3257 | pe_cntx_size <<= (u32)settings->pe_cntx_num; | |
3258 | break; | |
3259 | default: | |
3260 | return I40E_ERR_PARAM; | |
3261 | } | |
3262 | ||
3263 | /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ | |
3264 | val = rd32(hw, I40E_GLHMC_FCOEFMAX); | |
3265 | fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) | |
3266 | >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; | |
3267 | if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) | |
3268 | return I40E_ERR_INVALID_SIZE; | |
3269 | ||
56a62fc8 JB |
3270 | return 0; |
3271 | } | |
3272 | ||
3273 | /** | |
3274 | * i40e_set_filter_control | |
3275 | * @hw: pointer to the hardware structure | |
3276 | * @settings: Filter control settings | |
3277 | * | |
3278 | * Set the Queue Filters for PE/FCoE and enable filters required | |
3279 | * for a single PF. It is expected that these settings are programmed | |
3280 | * at the driver initialization time. | |
3281 | **/ | |
3282 | i40e_status i40e_set_filter_control(struct i40e_hw *hw, | |
3283 | struct i40e_filter_control_settings *settings) | |
3284 | { | |
3285 | i40e_status ret = 0; | |
3286 | u32 hash_lut_size = 0; | |
3287 | u32 val; | |
3288 | ||
3289 | if (!settings) | |
3290 | return I40E_ERR_PARAM; | |
3291 | ||
3292 | /* Validate the input settings */ | |
3293 | ret = i40e_validate_filter_settings(hw, settings); | |
3294 | if (ret) | |
3295 | return ret; | |
3296 | ||
3297 | /* Read the PF Queue Filter control register */ | |
3298 | val = rd32(hw, I40E_PFQF_CTL_0); | |
3299 | ||
3300 | /* Program required PE hash buckets for the PF */ | |
3301 | val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; | |
3302 | val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & | |
3303 | I40E_PFQF_CTL_0_PEHSIZE_MASK; | |
3304 | /* Program required PE contexts for the PF */ | |
3305 | val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; | |
3306 | val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & | |
3307 | I40E_PFQF_CTL_0_PEDSIZE_MASK; | |
3308 | ||
3309 | /* Program required FCoE hash buckets for the PF */ | |
3310 | val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; | |
3311 | val |= ((u32)settings->fcoe_filt_num << | |
3312 | I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & | |
3313 | I40E_PFQF_CTL_0_PFFCHSIZE_MASK; | |
3314 | /* Program required FCoE DDP contexts for the PF */ | |
3315 | val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; | |
3316 | val |= ((u32)settings->fcoe_cntx_num << | |
3317 | I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & | |
3318 | I40E_PFQF_CTL_0_PFFCDSIZE_MASK; | |
3319 | ||
3320 | /* Program Hash LUT size for the PF */ | |
3321 | val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; | |
3322 | if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) | |
3323 | hash_lut_size = 1; | |
3324 | val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & | |
3325 | I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; | |
3326 | ||
3327 | /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ | |
3328 | if (settings->enable_fdir) | |
3329 | val |= I40E_PFQF_CTL_0_FD_ENA_MASK; | |
3330 | if (settings->enable_ethtype) | |
3331 | val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; | |
3332 | if (settings->enable_macvlan) | |
3333 | val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; | |
3334 | ||
3335 | wr32(hw, I40E_PFQF_CTL_0, val); | |
3336 | ||
3337 | return 0; | |
3338 | } | |
afb3ff0d NP |
3339 | |
3340 | /** | |
3341 | * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter | |
3342 | * @hw: pointer to the hw struct | |
3343 | * @mac_addr: MAC address to use in the filter | |
3344 | * @ethtype: Ethertype to use in the filter | |
3345 | * @flags: Flags that needs to be applied to the filter | |
3346 | * @vsi_seid: seid of the control VSI | |
3347 | * @queue: VSI queue number to send the packet to | |
3348 | * @is_add: Add control packet filter if True else remove | |
3349 | * @stats: Structure to hold information on control filter counts | |
3350 | * @cmd_details: pointer to command details structure or NULL | |
3351 | * | |
3352 | * This command will Add or Remove control packet filter for a control VSI. | |
3353 | * In return it will update the total number of perfect filter count in | |
3354 | * the stats member. | |
3355 | **/ | |
3356 | i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, | |
3357 | u8 *mac_addr, u16 ethtype, u16 flags, | |
3358 | u16 vsi_seid, u16 queue, bool is_add, | |
3359 | struct i40e_control_filter_stats *stats, | |
3360 | struct i40e_asq_cmd_details *cmd_details) | |
3361 | { | |
3362 | struct i40e_aq_desc desc; | |
3363 | struct i40e_aqc_add_remove_control_packet_filter *cmd = | |
3364 | (struct i40e_aqc_add_remove_control_packet_filter *) | |
3365 | &desc.params.raw; | |
3366 | struct i40e_aqc_add_remove_control_packet_filter_completion *resp = | |
3367 | (struct i40e_aqc_add_remove_control_packet_filter_completion *) | |
3368 | &desc.params.raw; | |
3369 | i40e_status status; | |
3370 | ||
3371 | if (vsi_seid == 0) | |
3372 | return I40E_ERR_PARAM; | |
3373 | ||
3374 | if (is_add) { | |
3375 | i40e_fill_default_direct_cmd_desc(&desc, | |
3376 | i40e_aqc_opc_add_control_packet_filter); | |
3377 | cmd->queue = cpu_to_le16(queue); | |
3378 | } else { | |
3379 | i40e_fill_default_direct_cmd_desc(&desc, | |
3380 | i40e_aqc_opc_remove_control_packet_filter); | |
3381 | } | |
3382 | ||
3383 | if (mac_addr) | |
3384 | memcpy(cmd->mac, mac_addr, ETH_ALEN); | |
3385 | ||
3386 | cmd->etype = cpu_to_le16(ethtype); | |
3387 | cmd->flags = cpu_to_le16(flags); | |
3388 | cmd->seid = cpu_to_le16(vsi_seid); | |
3389 | ||
3390 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
3391 | ||
3392 | if (!status && stats) { | |
3393 | stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); | |
3394 | stats->etype_used = le16_to_cpu(resp->etype_used); | |
3395 | stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); | |
3396 | stats->etype_free = le16_to_cpu(resp->etype_free); | |
3397 | } | |
3398 | ||
3399 | return status; | |
3400 | } | |
3401 | ||
f4492db1 GR |
3402 | /** |
3403 | * i40e_aq_alternate_read | |
3404 | * @hw: pointer to the hardware structure | |
3405 | * @reg_addr0: address of first dword to be read | |
3406 | * @reg_val0: pointer for data read from 'reg_addr0' | |
3407 | * @reg_addr1: address of second dword to be read | |
3408 | * @reg_val1: pointer for data read from 'reg_addr1' | |
3409 | * | |
3410 | * Read one or two dwords from alternate structure. Fields are indicated | |
3411 | * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer | |
3412 | * is not passed then only register at 'reg_addr0' is read. | |
3413 | * | |
3414 | **/ | |
37a2973a SN |
3415 | static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, |
3416 | u32 reg_addr0, u32 *reg_val0, | |
3417 | u32 reg_addr1, u32 *reg_val1) | |
f4492db1 GR |
3418 | { |
3419 | struct i40e_aq_desc desc; | |
3420 | struct i40e_aqc_alternate_write *cmd_resp = | |
3421 | (struct i40e_aqc_alternate_write *)&desc.params.raw; | |
3422 | i40e_status status; | |
3423 | ||
3424 | if (!reg_val0) | |
3425 | return I40E_ERR_PARAM; | |
3426 | ||
3427 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); | |
3428 | cmd_resp->address0 = cpu_to_le32(reg_addr0); | |
3429 | cmd_resp->address1 = cpu_to_le32(reg_addr1); | |
3430 | ||
3431 | status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); | |
3432 | ||
3433 | if (!status) { | |
3434 | *reg_val0 = le32_to_cpu(cmd_resp->data0); | |
3435 | ||
3436 | if (reg_val1) | |
3437 | *reg_val1 = le32_to_cpu(cmd_resp->data1); | |
3438 | } | |
3439 | ||
3440 | return status; | |
3441 | } | |
3442 | ||
2fd75f31 NP |
3443 | /** |
3444 | * i40e_aq_resume_port_tx | |
3445 | * @hw: pointer to the hardware structure | |
3446 | * @cmd_details: pointer to command details structure or NULL | |
3447 | * | |
3448 | * Resume port's Tx traffic | |
3449 | **/ | |
3450 | i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, | |
3451 | struct i40e_asq_cmd_details *cmd_details) | |
3452 | { | |
3453 | struct i40e_aq_desc desc; | |
3454 | i40e_status status; | |
3455 | ||
3456 | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); | |
3457 | ||
3458 | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |
3459 | ||
3460 | return status; | |
3461 | } | |
3462 | ||
d4dfb81a CS |
3463 | /** |
3464 | * i40e_set_pci_config_data - store PCI bus info | |
3465 | * @hw: pointer to hardware structure | |
3466 | * @link_status: the link status word from PCI config space | |
3467 | * | |
3468 | * Stores the PCI bus info (speed, width, type) within the i40e_hw structure | |
3469 | **/ | |
3470 | void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) | |
3471 | { | |
3472 | hw->bus.type = i40e_bus_type_pci_express; | |
3473 | ||
3474 | switch (link_status & PCI_EXP_LNKSTA_NLW) { | |
3475 | case PCI_EXP_LNKSTA_NLW_X1: | |
3476 | hw->bus.width = i40e_bus_width_pcie_x1; | |
3477 | break; | |
3478 | case PCI_EXP_LNKSTA_NLW_X2: | |
3479 | hw->bus.width = i40e_bus_width_pcie_x2; | |
3480 | break; | |
3481 | case PCI_EXP_LNKSTA_NLW_X4: | |
3482 | hw->bus.width = i40e_bus_width_pcie_x4; | |
3483 | break; | |
3484 | case PCI_EXP_LNKSTA_NLW_X8: | |
3485 | hw->bus.width = i40e_bus_width_pcie_x8; | |
3486 | break; | |
3487 | default: | |
3488 | hw->bus.width = i40e_bus_width_unknown; | |
3489 | break; | |
3490 | } | |
3491 | ||
3492 | switch (link_status & PCI_EXP_LNKSTA_CLS) { | |
3493 | case PCI_EXP_LNKSTA_CLS_2_5GB: | |
3494 | hw->bus.speed = i40e_bus_speed_2500; | |
3495 | break; | |
3496 | case PCI_EXP_LNKSTA_CLS_5_0GB: | |
3497 | hw->bus.speed = i40e_bus_speed_5000; | |
3498 | break; | |
3499 | case PCI_EXP_LNKSTA_CLS_8_0GB: | |
3500 | hw->bus.speed = i40e_bus_speed_8000; | |
3501 | break; | |
3502 | default: | |
3503 | hw->bus.speed = i40e_bus_speed_unknown; | |
3504 | break; | |
3505 | } | |
3506 | } | |
f4492db1 GR |
3507 | |
3508 | /** | |
3509 | * i40e_read_bw_from_alt_ram | |
3510 | * @hw: pointer to the hardware structure | |
3511 | * @max_bw: pointer for max_bw read | |
3512 | * @min_bw: pointer for min_bw read | |
3513 | * @min_valid: pointer for bool that is true if min_bw is a valid value | |
3514 | * @max_valid: pointer for bool that is true if max_bw is a valid value | |
3515 | * | |
3516 | * Read bw from the alternate ram for the given pf | |
3517 | **/ | |
3518 | i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, | |
3519 | u32 *max_bw, u32 *min_bw, | |
3520 | bool *min_valid, bool *max_valid) | |
3521 | { | |
3522 | i40e_status status; | |
3523 | u32 max_bw_addr, min_bw_addr; | |
3524 | ||
3525 | /* Calculate the address of the min/max bw registers */ | |
3526 | max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + | |
3527 | I40E_ALT_STRUCT_MAX_BW_OFFSET + | |
3528 | (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); | |
3529 | min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + | |
3530 | I40E_ALT_STRUCT_MIN_BW_OFFSET + | |
3531 | (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); | |
3532 | ||
3533 | /* Read the bandwidths from alt ram */ | |
3534 | status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, | |
3535 | min_bw_addr, min_bw); | |
3536 | ||
3537 | if (*min_bw & I40E_ALT_BW_VALID_MASK) | |
3538 | *min_valid = true; | |
3539 | else | |
3540 | *min_valid = false; | |
3541 | ||
3542 | if (*max_bw & I40E_ALT_BW_VALID_MASK) | |
3543 | *max_valid = true; | |
3544 | else | |
3545 | *max_valid = false; | |
3546 | ||
3547 | return status; | |
3548 | } | |
3549 | ||
3550 | /** | |
3551 | * i40e_aq_configure_partition_bw | |
3552 | * @hw: pointer to the hardware structure | |
3553 | * @bw_data: Buffer holding valid pfs and bw limits | |
3554 | * @cmd_details: pointer to command details | |
3555 | * | |
3556 | * Configure partitions guaranteed/max bw | |
3557 | **/ | |
3558 | i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, | |
3559 | struct i40e_aqc_configure_partition_bw_data *bw_data, | |
3560 | struct i40e_asq_cmd_details *cmd_details) | |
3561 | { | |
3562 | i40e_status status; | |
3563 | struct i40e_aq_desc desc; | |
3564 | u16 bwd_size = sizeof(*bw_data); | |
3565 | ||
3566 | i40e_fill_default_direct_cmd_desc(&desc, | |
3567 | i40e_aqc_opc_configure_partition_bw); | |
3568 | ||
3569 | /* Indirect command */ | |
3570 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); | |
3571 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); | |
3572 | ||
3573 | if (bwd_size > I40E_AQ_LARGE_BUF) | |
3574 | desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); | |
3575 | ||
3576 | desc.datalen = cpu_to_le16(bwd_size); | |
3577 | ||
3578 | status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, | |
3579 | cmd_details); | |
3580 | ||
3581 | return status; | |
3582 | } |