projects / deliverable / linux.git / blame
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|---|---|---|
| a1a69369 VD |
1 | /******************************************************************************* |
| 2 | * | |
| 3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
| 4 | * Copyright(c) 2013 - 2014 Intel Corporation. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms and conditions of the GNU General Public License, | |
| 8 | * version 2, as published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 13 | * more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License along | |
| 16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 17 | * | |
| 18 | * The full GNU General Public License is included in this distribution in | |
| 19 | * the file called "COPYING". | |
| 20 | * | |
| 21 | * Contact Information: | |
| 22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
| 23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 24 | * | |
| 25 | ******************************************************************************/ | |
| 26 | ||
| 27 | #ifndef _I40E_FCOE_H_ | |
| 28 | #define _I40E_FCOE_H_ | |
| 29 | ||
| 30 | /* FCoE HW context helper macros */ | |
| 31 | #define I40E_DDP_CONTEXT_DESC(R, i) \ | |
| 32 | (&(((struct i40e_fcoe_ddp_context_desc *)((R)->desc))[i])) | |
| 33 | ||
| 34 | #define I40E_QUEUE_CONTEXT_DESC(R, i) \ | |
| 35 | (&(((struct i40e_fcoe_queue_context_desc *)((R)->desc))[i])) | |
| 36 | ||
| 37 | #define I40E_FILTER_CONTEXT_DESC(R, i) \ | |
| 38 | (&(((struct i40e_fcoe_filter_context_desc *)((R)->desc))[i])) | |
| 39 | ||
| a1a69369 VD |
40 | /* receive queue descriptor filter status for FCoE */ |
| 41 | #define I40E_RX_DESC_FLTSTAT_FCMASK 0x3 | |
| 42 | #define I40E_RX_DESC_FLTSTAT_NOMTCH 0x0 /* no ddp context match */ | |
| 43 | #define I40E_RX_DESC_FLTSTAT_NODDP 0x1 /* no ddp due to error */ | |
| 44 | #define I40E_RX_DESC_FLTSTAT_DDP 0x2 /* DDPed payload, post header */ | |
| 45 | #define I40E_RX_DESC_FLTSTAT_FCPRSP 0x3 /* FCP_RSP */ | |
| 46 | ||
| 47 | /* receive queue descriptor error codes for FCoE */ | |
| 48 | #define I40E_RX_DESC_FCOE_ERROR_MASK \ | |
| 49 | (I40E_RX_DESC_ERROR_L3L4E_PROT | \ | |
| 50 | I40E_RX_DESC_ERROR_L3L4E_FC | \ | |
| 51 | I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR | \ | |
| 52 | I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN) | |
| 53 | ||
| 54 | /* receive queue descriptor programming error */ | |
| 55 | #define I40E_RX_PROG_FCOE_ERROR_TBL_FULL(e) \ | |
| 56 | (((e) >> I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT) & 0x1) | |
| 57 | ||
| 58 | #define I40E_RX_PROG_FCOE_ERROR_CONFLICT(e) \ | |
| 59 | (((e) >> I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT) & 0x1) | |
| 60 | ||
| 61 | #define I40E_RX_PROG_FCOE_ERROR_TBL_FULL_BIT \ | |
| 62 | (1 << I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT) | |
| 63 | #define I40E_RX_PROG_FCOE_ERROR_CONFLICT_BIT \ | |
| 64 | (1 << I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT) | |
| 65 | ||
| 66 | #define I40E_RX_PROG_FCOE_ERROR_INVLFAIL(e) \ | |
| 67 | I40E_RX_PROG_FCOE_ERROR_CONFLICT(e) | |
| 68 | #define I40E_RX_PROG_FCOE_ERROR_INVLFAIL_BIT \ | |
| 69 | I40E_RX_PROG_FCOE_ERROR_CONFLICT_BIT | |
| 70 | ||
| 71 | /* FCoE DDP related definitions */ | |
| 72 | #define I40E_FCOE_MIN_XID 0x0000 /* the min xid supported by fcoe_sw */ | |
| 73 | #define I40E_FCOE_MAX_XID 0x0FFF /* the max xid supported by fcoe_sw */ | |
| 74 | #define I40E_FCOE_DDP_BUFFCNT_MAX 512 /* 9 bits bufcnt */ | |
| 75 | #define I40E_FCOE_DDP_PTR_ALIGN 16 | |
| 76 | #define I40E_FCOE_DDP_PTR_MAX (I40E_FCOE_DDP_BUFFCNT_MAX * sizeof(dma_addr_t)) | |
| 77 | #define I40E_FCOE_DDP_BUF_MIN 4096 | |
| 78 | #define I40E_FCOE_DDP_MAX 2048 | |
| 79 | #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8 | |
| 80 | ||
| 81 | /* supported netdev features for FCoE */ | |
| 82 | #define I40E_FCOE_NETIF_FEATURES (NETIF_F_ALL_FCOE | \ | |
| 83 | NETIF_F_HW_VLAN_CTAG_TX | \ | |
| 84 | NETIF_F_HW_VLAN_CTAG_RX | \ | |
| 85 | NETIF_F_HW_VLAN_CTAG_FILTER) | |
| 86 | ||
| 87 | /* DDP context flags */ | |
| 88 | enum i40e_fcoe_ddp_flags { | |
| 89 | __I40E_FCOE_DDP_NONE = 1, | |
| 90 | __I40E_FCOE_DDP_TARGET, | |
| 91 | __I40E_FCOE_DDP_INITALIZED, | |
| 92 | __I40E_FCOE_DDP_PROGRAMMED, | |
| 93 | __I40E_FCOE_DDP_DONE, | |
| 94 | __I40E_FCOE_DDP_ABORTED, | |
| 95 | __I40E_FCOE_DDP_UNMAPPED, | |
| 96 | }; | |
| 97 | ||
| 98 | /* DDP SW context struct */ | |
| 99 | struct i40e_fcoe_ddp { | |
| 100 | int len; | |
| 101 | u16 xid; | |
| 102 | u16 firstoff; | |
| 103 | u16 lastsize; | |
| 104 | u16 list_len; | |
| 105 | u8 fcerr; | |
| 106 | u8 prerr; | |
| 107 | unsigned long flags; | |
| 108 | unsigned int sgc; | |
| 109 | struct scatterlist *sgl; | |
| 110 | dma_addr_t udp; | |
| 111 | u64 *udl; | |
| 112 | struct dma_pool *pool; | |
| 113 | ||
| 114 | }; | |
| 115 | ||
| 116 | struct i40e_fcoe_ddp_pool { | |
| 117 | struct dma_pool *pool; | |
| 118 | }; | |
| 119 | ||
| 120 | struct i40e_fcoe { | |
| 121 | unsigned long mode; | |
| 122 | atomic_t refcnt; | |
| 123 | struct i40e_fcoe_ddp_pool __percpu *ddp_pool; | |
| 124 | struct i40e_fcoe_ddp ddp[I40E_FCOE_DDP_MAX]; | |
| 125 | }; | |
| 126 | ||
| 127 | #endif /* _I40E_FCOE_H_ */ |