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i40e: Add FW check to disable DCB and wrap autoneg workaround with FW check
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
a36fdd8e 41#define DRV_VERSION_MINOR 2
5b8eb176 42#define DRV_VERSION_BUILD 9
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
38e00438
VD		 273#ifdef I40E_FCOE
274void i40e_tx_timeout(struct net_device *netdev)
275#else
41c445ff 276static void i40e_tx_timeout(struct net_device *netdev)
38e00438 277#endif
41c445ff
JB		 278{
279 struct i40e_netdev_priv *np = netdev_priv(netdev);
280 struct i40e_vsi *vsi = np->vsi;
281 struct i40e_pf *pf = vsi->back;
282
283 pf->tx_timeout_count++;
284
285 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 286 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 287 pf->tx_timeout_last_recovery = jiffies;
288 netdev_info(netdev, "tx_timeout recovery level %d\n",
289 pf->tx_timeout_recovery_level);
290
291 switch (pf->tx_timeout_recovery_level) {
292 case 0:
293 /* disable and re-enable queues for the VSI */
294 if (in_interrupt()) {
295 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
296 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
297 } else {
298 i40e_vsi_reinit_locked(vsi);
299 }
300 break;
301 case 1:
302 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
303 break;
304 case 2:
305 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
306 break;
307 case 3:
308 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
309 break;
310 default:
311 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 312 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
313 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 314 break;
315 }
316 i40e_service_event_schedule(pf);
317 pf->tx_timeout_recovery_level++;
318}
319
320/**
321 * i40e_release_rx_desc - Store the new tail and head values
322 * @rx_ring: ring to bump
323 * @val: new head index
324 **/
325static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
326{
327 rx_ring->next_to_use = val;
328
329 /* Force memory writes to complete before letting h/w
330 * know there are new descriptors to fetch. (Only
331 * applicable for weak-ordered memory model archs,
332 * such as IA-64).
333 */
334 wmb();
335 writel(val, rx_ring->tail);
336}
337
338/**
339 * i40e_get_vsi_stats_struct - Get System Network Statistics
340 * @vsi: the VSI we care about
341 *
342 * Returns the address of the device statistics structure.
343 * The statistics are actually updated from the service task.
344 **/
345struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
346{
347 return &vsi->net_stats;
348}
349
350/**
351 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
352 * @netdev: network interface device structure
353 *
354 * Returns the address of the device statistics structure.
355 * The statistics are actually updated from the service task.
356 **/
38e00438
VD		 357#ifdef I40E_FCOE
358struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
359 struct net_device *netdev,
360 struct rtnl_link_stats64 *stats)
361#else
41c445ff
JB		 362static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
363 struct net_device *netdev,
980e9b11 364 struct rtnl_link_stats64 *stats)
38e00438 365#endif
41c445ff
JB		 366{
367 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 368 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 369 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 370 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
371 int i;
372
bc7d338f
ASJ		 373 if (test_bit(__I40E_DOWN, &vsi->state))
374 return stats;
375
3c325ced
JB		 376 if (!vsi->tx_rings)
377 return stats;
378
980e9b11
AD		 379 rcu_read_lock();
380 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 381 u64 bytes, packets;
382 unsigned int start;
383
384 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
385 if (!tx_ring)
386 continue;
387
388 do {
57a7744e 389 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 390 packets = tx_ring->stats.packets;
391 bytes = tx_ring->stats.bytes;
57a7744e 392 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 393
394 stats->tx_packets += packets;
395 stats->tx_bytes += bytes;
396 rx_ring = &tx_ring[1];
397
398 do {
57a7744e 399 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 400 packets = rx_ring->stats.packets;
401 bytes = rx_ring->stats.bytes;
57a7744e 402 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 403
980e9b11
AD		 404 stats->rx_packets += packets;
405 stats->rx_bytes += bytes;
406 }
407 rcu_read_unlock();
408
a5282f44 409 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 410 stats->multicast = vsi_stats->multicast;
411 stats->tx_errors = vsi_stats->tx_errors;
412 stats->tx_dropped = vsi_stats->tx_dropped;
413 stats->rx_errors = vsi_stats->rx_errors;
414 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
415 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 416
980e9b11 417 return stats;
41c445ff
JB		 418}
419
420/**
421 * i40e_vsi_reset_stats - Resets all stats of the given vsi
422 * @vsi: the VSI to have its stats reset
423 **/
424void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
425{
426 struct rtnl_link_stats64 *ns;
427 int i;
428
429 if (!vsi)
430 return;
431
432 ns = i40e_get_vsi_stats_struct(vsi);
433 memset(ns, 0, sizeof(*ns));
434 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
435 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
436 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 437 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 438 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 439 memset(&vsi->rx_rings[i]->stats, 0 ,
440 sizeof(vsi->rx_rings[i]->stats));
441 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
442 sizeof(vsi->rx_rings[i]->rx_stats));
443 memset(&vsi->tx_rings[i]->stats, 0 ,
444 sizeof(vsi->tx_rings[i]->stats));
445 memset(&vsi->tx_rings[i]->tx_stats, 0,
446 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 447 }
8e9dca53 448 }
41c445ff
JB		 449 vsi->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_pf_reset_stats - Reset all of the stats for the given pf
454 * @pf: the PF to be reset
455 **/
456void i40e_pf_reset_stats(struct i40e_pf *pf)
457{
e91fdf76
SN		 458 int i;
459
41c445ff
JB		 460 memset(&pf->stats, 0, sizeof(pf->stats));
461 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
462 pf->stat_offsets_loaded = false;
e91fdf76
SN		 463
464 for (i = 0; i < I40E_MAX_VEB; i++) {
465 if (pf->veb[i]) {
466 memset(&pf->veb[i]->stats, 0,
467 sizeof(pf->veb[i]->stats));
468 memset(&pf->veb[i]->stats_offsets, 0,
469 sizeof(pf->veb[i]->stats_offsets));
470 pf->veb[i]->stat_offsets_loaded = false;
471 }
472 }
41c445ff
JB		 473}
474
475/**
476 * i40e_stat_update48 - read and update a 48 bit stat from the chip
477 * @hw: ptr to the hardware info
478 * @hireg: the high 32 bit reg to read
479 * @loreg: the low 32 bit reg to read
480 * @offset_loaded: has the initial offset been loaded yet
481 * @offset: ptr to current offset value
482 * @stat: ptr to the stat
483 *
484 * Since the device stats are not reset at PFReset, they likely will not
485 * be zeroed when the driver starts. We'll save the first values read
486 * and use them as offsets to be subtracted from the raw values in order
487 * to report stats that count from zero. In the process, we also manage
488 * the potential roll-over.
489 **/
490static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
491 bool offset_loaded, u64 *offset, u64 *stat)
492{
493 u64 new_data;
494
ab60085e 495 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 496 new_data = rd32(hw, loreg);
497 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
498 } else {
499 new_data = rd64(hw, loreg);
500 }
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = new_data - *offset;
505 else
506 *stat = (new_data + ((u64)1 << 48)) - *offset;
507 *stat &= 0xFFFFFFFFFFFFULL;
508}
509
510/**
511 * i40e_stat_update32 - read and update a 32 bit stat from the chip
512 * @hw: ptr to the hardware info
513 * @reg: the hw reg to read
514 * @offset_loaded: has the initial offset been loaded yet
515 * @offset: ptr to current offset value
516 * @stat: ptr to the stat
517 **/
518static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
519 bool offset_loaded, u64 *offset, u64 *stat)
520{
521 u32 new_data;
522
523 new_data = rd32(hw, reg);
524 if (!offset_loaded)
525 *offset = new_data;
526 if (likely(new_data >= *offset))
527 *stat = (u32)(new_data - *offset);
528 else
529 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
530}
531
532/**
533 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
534 * @vsi: the VSI to be updated
535 **/
536void i40e_update_eth_stats(struct i40e_vsi *vsi)
537{
538 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
539 struct i40e_pf *pf = vsi->back;
540 struct i40e_hw *hw = &pf->hw;
541 struct i40e_eth_stats *oes;
542 struct i40e_eth_stats *es; /* device's eth stats */
543
544 es = &vsi->eth_stats;
545 oes = &vsi->eth_stats_offsets;
546
547 /* Gather up the stats that the hw collects */
548 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_errors, &es->tx_errors);
551 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 554 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
555 vsi->stat_offsets_loaded,
556 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
557 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 560
561 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
562 I40E_GLV_GORCL(stat_idx),
563 vsi->stat_offsets_loaded,
564 &oes->rx_bytes, &es->rx_bytes);
565 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
566 I40E_GLV_UPRCL(stat_idx),
567 vsi->stat_offsets_loaded,
568 &oes->rx_unicast, &es->rx_unicast);
569 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
570 I40E_GLV_MPRCL(stat_idx),
571 vsi->stat_offsets_loaded,
572 &oes->rx_multicast, &es->rx_multicast);
573 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
574 I40E_GLV_BPRCL(stat_idx),
575 vsi->stat_offsets_loaded,
576 &oes->rx_broadcast, &es->rx_broadcast);
577
578 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
579 I40E_GLV_GOTCL(stat_idx),
580 vsi->stat_offsets_loaded,
581 &oes->tx_bytes, &es->tx_bytes);
582 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
583 I40E_GLV_UPTCL(stat_idx),
584 vsi->stat_offsets_loaded,
585 &oes->tx_unicast, &es->tx_unicast);
586 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
587 I40E_GLV_MPTCL(stat_idx),
588 vsi->stat_offsets_loaded,
589 &oes->tx_multicast, &es->tx_multicast);
590 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
591 I40E_GLV_BPTCL(stat_idx),
592 vsi->stat_offsets_loaded,
593 &oes->tx_broadcast, &es->tx_broadcast);
594 vsi->stat_offsets_loaded = true;
595}
596
597/**
598 * i40e_update_veb_stats - Update Switch component statistics
599 * @veb: the VEB being updated
600 **/
601static void i40e_update_veb_stats(struct i40e_veb *veb)
602{
603 struct i40e_pf *pf = veb->pf;
604 struct i40e_hw *hw = &pf->hw;
605 struct i40e_eth_stats *oes;
606 struct i40e_eth_stats *es; /* device's eth stats */
607 int idx = 0;
608
609 idx = veb->stats_idx;
610 es = &veb->stats;
611 oes = &veb->stats_offsets;
612
613 /* Gather up the stats that the hw collects */
614 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 617 if (hw->revision_id > 0)
618 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
619 veb->stat_offsets_loaded,
620 &oes->rx_unknown_protocol,
621 &es->rx_unknown_protocol);
41c445ff
JB		 622 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
623 veb->stat_offsets_loaded,
624 &oes->rx_bytes, &es->rx_bytes);
625 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
626 veb->stat_offsets_loaded,
627 &oes->rx_unicast, &es->rx_unicast);
628 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
629 veb->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
632 veb->stat_offsets_loaded,
633 &oes->rx_broadcast, &es->rx_broadcast);
634
635 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
636 veb->stat_offsets_loaded,
637 &oes->tx_bytes, &es->tx_bytes);
638 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
639 veb->stat_offsets_loaded,
640 &oes->tx_unicast, &es->tx_unicast);
641 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
642 veb->stat_offsets_loaded,
643 &oes->tx_multicast, &es->tx_multicast);
644 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
645 veb->stat_offsets_loaded,
646 &oes->tx_broadcast, &es->tx_broadcast);
647 veb->stat_offsets_loaded = true;
648}
649
38e00438
VD		 650#ifdef I40E_FCOE
651/**
652 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
653 * @vsi: the VSI that is capable of doing FCoE
654 **/
655static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
656{
657 struct i40e_pf *pf = vsi->back;
658 struct i40e_hw *hw = &pf->hw;
659 struct i40e_fcoe_stats *ofs;
660 struct i40e_fcoe_stats *fs; /* device's eth stats */
661 int idx;
662
663 if (vsi->type != I40E_VSI_FCOE)
664 return;
665
666 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
667 fs = &vsi->fcoe_stats;
668 ofs = &vsi->fcoe_stats_offsets;
669
670 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
671 vsi->fcoe_stat_offsets_loaded,
672 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
673 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
674 vsi->fcoe_stat_offsets_loaded,
675 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
676 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
677 vsi->fcoe_stat_offsets_loaded,
678 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
679 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
680 vsi->fcoe_stat_offsets_loaded,
681 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
682 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
683 vsi->fcoe_stat_offsets_loaded,
684 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
685 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
686 vsi->fcoe_stat_offsets_loaded,
687 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
688 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
689 vsi->fcoe_stat_offsets_loaded,
690 &ofs->fcoe_last_error, &fs->fcoe_last_error);
691 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
692 vsi->fcoe_stat_offsets_loaded,
693 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
694
695 vsi->fcoe_stat_offsets_loaded = true;
696}
697
698#endif
41c445ff
JB		 699/**
700 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
701 * @pf: the corresponding PF
702 *
703 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
704 **/
705static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
706{
707 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
708 struct i40e_hw_port_stats *nsd = &pf->stats;
709 struct i40e_hw *hw = &pf->hw;
710 u64 xoff = 0;
711 u16 i, v;
712
713 if ((hw->fc.current_mode != I40E_FC_FULL) &&
714 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
715 return;
716
717 xoff = nsd->link_xoff_rx;
718 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
719 pf->stat_offsets_loaded,
720 &osd->link_xoff_rx, &nsd->link_xoff_rx);
721
722 /* No new LFC xoff rx */
723 if (!(nsd->link_xoff_rx - xoff))
724 return;
725
726 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 727 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 728 struct i40e_vsi *vsi = pf->vsi[v];
729
ddfda80f 730 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 731 continue;
732
733 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 734 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 735 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
736 }
737 }
738}
739
740/**
741 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
742 * @pf: the corresponding PF
743 *
744 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
745 **/
746static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
747{
748 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
749 struct i40e_hw_port_stats *nsd = &pf->stats;
750 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
751 struct i40e_dcbx_config *dcb_cfg;
752 struct i40e_hw *hw = &pf->hw;
753 u16 i, v;
754 u8 tc;
755
756 dcb_cfg = &hw->local_dcbx_config;
757
758 /* See if DCB enabled with PFC TC */
759 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
760 !(dcb_cfg->pfc.pfcenable)) {
761 i40e_update_link_xoff_rx(pf);
762 return;
763 }
764
765 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
766 u64 prio_xoff = nsd->priority_xoff_rx[i];
767 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
768 pf->stat_offsets_loaded,
769 &osd->priority_xoff_rx[i],
770 &nsd->priority_xoff_rx[i]);
771
772 /* No new PFC xoff rx */
773 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
774 continue;
775 /* Get the TC for given priority */
776 tc = dcb_cfg->etscfg.prioritytable[i];
777 xoff[tc] = true;
778 }
779
780 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 781 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 782 struct i40e_vsi *vsi = pf->vsi[v];
783
ddfda80f 784 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 785 continue;
786
787 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 788 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 789
790 tc = ring->dcb_tc;
791 if (xoff[tc])
792 clear_bit(__I40E_HANG_CHECK_ARMED,
793 &ring->state);
794 }
795 }
796}
797
798/**
7812fddc 799 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 800 * @vsi: the VSI to be updated
801 *
802 * There are a few instances where we store the same stat in a
803 * couple of different structs. This is partly because we have
804 * the netdev stats that need to be filled out, which is slightly
805 * different from the "eth_stats" defined by the chip and used in
7812fddc 806 * VF communications. We sort it out here.
41c445ff 807 **/
7812fddc 808static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 809{
810 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 811 struct rtnl_link_stats64 *ons;
812 struct rtnl_link_stats64 *ns; /* netdev stats */
813 struct i40e_eth_stats *oes;
814 struct i40e_eth_stats *es; /* device's eth stats */
815 u32 tx_restart, tx_busy;
bf00b376 816 struct i40e_ring *p;
41c445ff 817 u32 rx_page, rx_buf;
bf00b376
AA		 818 u64 bytes, packets;
819 unsigned int start;
41c445ff
JB		 820 u64 rx_p, rx_b;
821 u64 tx_p, tx_b;
41c445ff
JB		 822 u16 q;
823
824 if (test_bit(__I40E_DOWN, &vsi->state) ||
825 test_bit(__I40E_CONFIG_BUSY, &pf->state))
826 return;
827
828 ns = i40e_get_vsi_stats_struct(vsi);
829 ons = &vsi->net_stats_offsets;
830 es = &vsi->eth_stats;
831 oes = &vsi->eth_stats_offsets;
832
833 /* Gather up the netdev and vsi stats that the driver collects
834 * on the fly during packet processing
835 */
836 rx_b = rx_p = 0;
837 tx_b = tx_p = 0;
838 tx_restart = tx_busy = 0;
839 rx_page = 0;
840 rx_buf = 0;
980e9b11 841 rcu_read_lock();
41c445ff 842 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc
SN		 898/**
899 * i40e_update_pf_stats - Update the pf statistics counters.
900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
532d283d
SN		 922 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
923 I40E_GLPRT_UPRCL(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_unicast,
926 &nsd->eth.rx_unicast);
7812fddc
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
928 I40E_GLPRT_MPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_multicast,
931 &nsd->eth.rx_multicast);
532d283d
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
933 I40E_GLPRT_BPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_broadcast,
936 &nsd->eth.rx_broadcast);
937 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
938 I40E_GLPRT_UPTCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.tx_unicast,
941 &nsd->eth.tx_unicast);
942 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
943 I40E_GLPRT_MPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_multicast,
946 &nsd->eth.tx_multicast);
947 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
948 I40E_GLPRT_BPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_broadcast,
951 &nsd->eth.tx_broadcast);
41c445ff 952
7812fddc
SN		 953 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_dropped_link_down,
956 &nsd->tx_dropped_link_down);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->crc_errors, &nsd->crc_errors);
41c445ff 961
7812fddc
SN		 962 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 965
7812fddc
SN		 966 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->mac_local_faults,
969 &nsd->mac_local_faults);
970 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->mac_remote_faults,
973 &nsd->mac_remote_faults);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->rx_length_errors,
978 &nsd->rx_length_errors);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->link_xon_rx, &nsd->link_xon_rx);
983 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->link_xon_tx, &nsd->link_xon_tx);
986 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
987 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 990
7812fddc
SN		 991 for (i = 0; i < 8; i++) {
992 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 993 pf->stat_offsets_loaded,
7812fddc
SN		 994 &osd->priority_xon_rx[i],
995 &nsd->priority_xon_rx[i]);
996 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 997 pf->stat_offsets_loaded,
7812fddc
SN		 998 &osd->priority_xon_tx[i],
999 &nsd->priority_xon_tx[i]);
1000 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1001 pf->stat_offsets_loaded,
7812fddc
SN		 1002 &osd->priority_xoff_tx[i],
1003 &nsd->priority_xoff_tx[i]);
1004 i40e_stat_update32(hw,
1005 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xon_2_xoff[i],
1008 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1009 }
1010
7812fddc
SN		 1011 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1012 I40E_GLPRT_PRC64L(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->rx_size_64, &nsd->rx_size_64);
1015 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1016 I40E_GLPRT_PRC127L(hw->port),
1017 pf->stat_offsets_loaded,
1018 &osd->rx_size_127, &nsd->rx_size_127);
1019 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1020 I40E_GLPRT_PRC255L(hw->port),
1021 pf->stat_offsets_loaded,
1022 &osd->rx_size_255, &nsd->rx_size_255);
1023 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1024 I40E_GLPRT_PRC511L(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->rx_size_511, &nsd->rx_size_511);
1027 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1028 I40E_GLPRT_PRC1023L(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->rx_size_1023, &nsd->rx_size_1023);
1031 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1032 I40E_GLPRT_PRC1522L(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->rx_size_1522, &nsd->rx_size_1522);
1035 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1036 I40E_GLPRT_PRC9522L(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->rx_size_big, &nsd->rx_size_big);
1039
1040 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1041 I40E_GLPRT_PTC64L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->tx_size_64, &nsd->tx_size_64);
1044 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1045 I40E_GLPRT_PTC127L(hw->port),
1046 pf->stat_offsets_loaded,
1047 &osd->tx_size_127, &nsd->tx_size_127);
1048 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1049 I40E_GLPRT_PTC255L(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->tx_size_255, &nsd->tx_size_255);
1052 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1053 I40E_GLPRT_PTC511L(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->tx_size_511, &nsd->tx_size_511);
1056 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1057 I40E_GLPRT_PTC1023L(hw->port),
1058 pf->stat_offsets_loaded,
1059 &osd->tx_size_1023, &nsd->tx_size_1023);
1060 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1061 I40E_GLPRT_PTC1522L(hw->port),
1062 pf->stat_offsets_loaded,
1063 &osd->tx_size_1522, &nsd->tx_size_1522);
1064 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1065 I40E_GLPRT_PTC9522L(hw->port),
1066 pf->stat_offsets_loaded,
1067 &osd->tx_size_big, &nsd->tx_size_big);
1068
1069 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1070 pf->stat_offsets_loaded,
1071 &osd->rx_undersize, &nsd->rx_undersize);
1072 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->rx_fragments, &nsd->rx_fragments);
1075 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1076 pf->stat_offsets_loaded,
1077 &osd->rx_oversize, &nsd->rx_oversize);
1078 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_jabber, &nsd->rx_jabber);
1081
433c47de
ASJ		 1082 /* FDIR stats */
1083 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1084 pf->stat_offsets_loaded,
1085 &osd->fd_atr_match, &nsd->fd_atr_match);
1086 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1087 pf->stat_offsets_loaded,
1088 &osd->fd_sb_match, &nsd->fd_sb_match);
1089
7812fddc
SN		 1090 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1091 nsd->tx_lpi_status =
1092 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1093 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1094 nsd->rx_lpi_status =
1095 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1096 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1097 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1098 pf->stat_offsets_loaded,
1099 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1100 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1101 pf->stat_offsets_loaded,
1102 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1103
41c445ff
JB		 1104 pf->stat_offsets_loaded = true;
1105}
1106
7812fddc
SN		 1107/**
1108 * i40e_update_stats - Update the various statistics counters.
1109 * @vsi: the VSI to be updated
1110 *
1111 * Update the various stats for this VSI and its related entities.
1112 **/
1113void i40e_update_stats(struct i40e_vsi *vsi)
1114{
1115 struct i40e_pf *pf = vsi->back;
1116
1117 if (vsi == pf->vsi[pf->lan_vsi])
1118 i40e_update_pf_stats(pf);
1119
1120 i40e_update_vsi_stats(vsi);
38e00438
VD		 1121#ifdef I40E_FCOE
1122 i40e_update_fcoe_stats(vsi);
1123#endif
7812fddc
SN		 1124}
1125
41c445ff
JB		 1126/**
1127 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1128 * @vsi: the VSI to be searched
1129 * @macaddr: the MAC address
1130 * @vlan: the vlan
1131 * @is_vf: make sure its a vf filter, else doesn't matter
1132 * @is_netdev: make sure its a netdev filter, else doesn't matter
1133 *
1134 * Returns ptr to the filter object or NULL
1135 **/
1136static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1137 u8 *macaddr, s16 vlan,
1138 bool is_vf, bool is_netdev)
1139{
1140 struct i40e_mac_filter *f;
1141
1142 if (!vsi || !macaddr)
1143 return NULL;
1144
1145 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1146 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1147 (vlan == f->vlan) &&
1148 (!is_vf || f->is_vf) &&
1149 (!is_netdev || f->is_netdev))
1150 return f;
1151 }
1152 return NULL;
1153}
1154
1155/**
1156 * i40e_find_mac - Find a mac addr in the macvlan filters list
1157 * @vsi: the VSI to be searched
1158 * @macaddr: the MAC address we are searching for
1159 * @is_vf: make sure its a vf filter, else doesn't matter
1160 * @is_netdev: make sure its a netdev filter, else doesn't matter
1161 *
1162 * Returns the first filter with the provided MAC address or NULL if
1163 * MAC address was not found
1164 **/
1165struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1166 bool is_vf, bool is_netdev)
1167{
1168 struct i40e_mac_filter *f;
1169
1170 if (!vsi || !macaddr)
1171 return NULL;
1172
1173 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1174 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1175 (!is_vf || f->is_vf) &&
1176 (!is_netdev || f->is_netdev))
1177 return f;
1178 }
1179 return NULL;
1180}
1181
1182/**
1183 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1184 * @vsi: the VSI to be searched
1185 *
1186 * Returns true if VSI is in vlan mode or false otherwise
1187 **/
1188bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1189{
1190 struct i40e_mac_filter *f;
1191
1192 /* Only -1 for all the filters denotes not in vlan mode
1193 * so we have to go through all the list in order to make sure
1194 */
1195 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1196 if (f->vlan >= 0)
1197 return true;
1198 }
1199
1200 return false;
1201}
1202
1203/**
1204 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1205 * @vsi: the VSI to be searched
1206 * @macaddr: the mac address to be filtered
1207 * @is_vf: true if it is a vf
1208 * @is_netdev: true if it is a netdev
1209 *
1210 * Goes through all the macvlan filters and adds a
1211 * macvlan filter for each unique vlan that already exists
1212 *
1213 * Returns first filter found on success, else NULL
1214 **/
1215struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1216 bool is_vf, bool is_netdev)
1217{
1218 struct i40e_mac_filter *f;
1219
1220 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1221 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1222 is_vf, is_netdev)) {
1223 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1224 is_vf, is_netdev))
41c445ff
JB		 1225 return NULL;
1226 }
1227 }
1228
1229 return list_first_entry_or_null(&vsi->mac_filter_list,
1230 struct i40e_mac_filter, list);
1231}
1232
8c27d42e
GR		 1233/**
1234 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1235 * @vsi: the PF Main VSI - inappropriate for any other VSI
1236 * @macaddr: the MAC address
30650cc5
SN		 1237 *
1238 * Some older firmware configurations set up a default promiscuous VLAN
1239 * filter that needs to be removed.
8c27d42e 1240 **/
30650cc5 1241static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1242{
1243 struct i40e_aqc_remove_macvlan_element_data element;
1244 struct i40e_pf *pf = vsi->back;
1245 i40e_status aq_ret;
1246
1247 /* Only appropriate for the PF main VSI */
1248 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1249 return -EINVAL;
8c27d42e 1250
30650cc5 1251 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1252 ether_addr_copy(element.mac_addr, macaddr);
1253 element.vlan_tag = 0;
1254 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1255 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1256 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1257 if (aq_ret)
30650cc5
SN		 1258 return -ENOENT;
1259
1260 return 0;
8c27d42e
GR		 1261}
1262
41c445ff
JB		 1263/**
1264 * i40e_add_filter - Add a mac/vlan filter to the VSI
1265 * @vsi: the VSI to be searched
1266 * @macaddr: the MAC address
1267 * @vlan: the vlan
1268 * @is_vf: make sure its a vf filter, else doesn't matter
1269 * @is_netdev: make sure its a netdev filter, else doesn't matter
1270 *
1271 * Returns ptr to the filter object or NULL when no memory available.
1272 **/
1273struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1274 u8 *macaddr, s16 vlan,
1275 bool is_vf, bool is_netdev)
1276{
1277 struct i40e_mac_filter *f;
1278
1279 if (!vsi || !macaddr)
1280 return NULL;
1281
1282 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1283 if (!f) {
1284 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1285 if (!f)
1286 goto add_filter_out;
1287
9a173901 1288 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1289 f->vlan = vlan;
1290 f->changed = true;
1291
1292 INIT_LIST_HEAD(&f->list);
1293 list_add(&f->list, &vsi->mac_filter_list);
1294 }
1295
1296 /* increment counter and add a new flag if needed */
1297 if (is_vf) {
1298 if (!f->is_vf) {
1299 f->is_vf = true;
1300 f->counter++;
1301 }
1302 } else if (is_netdev) {
1303 if (!f->is_netdev) {
1304 f->is_netdev = true;
1305 f->counter++;
1306 }
1307 } else {
1308 f->counter++;
1309 }
1310
1311 /* changed tells sync_filters_subtask to
1312 * push the filter down to the firmware
1313 */
1314 if (f->changed) {
1315 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1316 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1317 }
1318
1319add_filter_out:
1320 return f;
1321}
1322
1323/**
1324 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1325 * @vsi: the VSI to be searched
1326 * @macaddr: the MAC address
1327 * @vlan: the vlan
1328 * @is_vf: make sure it's a vf filter, else doesn't matter
1329 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1330 **/
1331void i40e_del_filter(struct i40e_vsi *vsi,
1332 u8 *macaddr, s16 vlan,
1333 bool is_vf, bool is_netdev)
1334{
1335 struct i40e_mac_filter *f;
1336
1337 if (!vsi || !macaddr)
1338 return;
1339
1340 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1341 if (!f || f->counter == 0)
1342 return;
1343
1344 if (is_vf) {
1345 if (f->is_vf) {
1346 f->is_vf = false;
1347 f->counter--;
1348 }
1349 } else if (is_netdev) {
1350 if (f->is_netdev) {
1351 f->is_netdev = false;
1352 f->counter--;
1353 }
1354 } else {
1355 /* make sure we don't remove a filter in use by vf or netdev */
1356 int min_f = 0;
1357 min_f += (f->is_vf ? 1 : 0);
1358 min_f += (f->is_netdev ? 1 : 0);
1359
1360 if (f->counter > min_f)
1361 f->counter--;
1362 }
1363
1364 /* counter == 0 tells sync_filters_subtask to
1365 * remove the filter from the firmware's list
1366 */
1367 if (f->counter == 0) {
1368 f->changed = true;
1369 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1370 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1371 }
1372}
1373
1374/**
1375 * i40e_set_mac - NDO callback to set mac address
1376 * @netdev: network interface device structure
1377 * @p: pointer to an address structure
1378 *
1379 * Returns 0 on success, negative on failure
1380 **/
38e00438
VD		 1381#ifdef I40E_FCOE
1382int i40e_set_mac(struct net_device *netdev, void *p)
1383#else
41c445ff 1384static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1385#endif
41c445ff
JB		 1386{
1387 struct i40e_netdev_priv *np = netdev_priv(netdev);
1388 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1389 struct i40e_pf *pf = vsi->back;
1390 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1391 struct sockaddr *addr = p;
1392 struct i40e_mac_filter *f;
1393
1394 if (!is_valid_ether_addr(addr->sa_data))
1395 return -EADDRNOTAVAIL;
1396
30650cc5
SN		 1397 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1398 netdev_info(netdev, "already using mac address %pM\n",
1399 addr->sa_data);
1400 return 0;
1401 }
41c445ff 1402
80f6428f
ASJ		 1403 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1404 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1405 return -EADDRNOTAVAIL;
1406
30650cc5
SN		 1407 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1408 netdev_info(netdev, "returning to hw mac address %pM\n",
1409 hw->mac.addr);
1410 else
1411 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1412
41c445ff
JB		 1413 if (vsi->type == I40E_VSI_MAIN) {
1414 i40e_status ret;
1415 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1416 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1417 addr->sa_data, NULL);
1418 if (ret) {
1419 netdev_info(netdev,
1420 "Addr change for Main VSI failed: %d\n",
1421 ret);
1422 return -EADDRNOTAVAIL;
1423 }
41c445ff
JB		 1424 }
1425
30650cc5
SN		 1426 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1427 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1428
30650cc5
SN		 1429 memset(&element, 0, sizeof(element));
1430 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1431 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1432 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1433 } else {
6c8ad1ba
SN		 1434 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1435 false, false);
6c8ad1ba 1436 }
41c445ff 1437
30650cc5
SN		 1438 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1439 struct i40e_aqc_add_macvlan_element_data element;
1440
1441 memset(&element, 0, sizeof(element));
1442 ether_addr_copy(element.mac_addr, hw->mac.addr);
1443 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1444 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1445 } else {
1446 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1447 false, false);
1448 if (f)
1449 f->is_laa = true;
1450 }
1451
1452 i40e_sync_vsi_filters(vsi);
1453 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1454
1455 return 0;
1456}
1457
1458/**
1459 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1460 * @vsi: the VSI being setup
1461 * @ctxt: VSI context structure
1462 * @enabled_tc: Enabled TCs bitmap
1463 * @is_add: True if called before Add VSI
1464 *
1465 * Setup VSI queue mapping for enabled traffic classes.
1466 **/
38e00438
VD		 1467#ifdef I40E_FCOE
1468void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1469 struct i40e_vsi_context *ctxt,
1470 u8 enabled_tc,
1471 bool is_add)
1472#else
41c445ff
JB		 1473static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1474 struct i40e_vsi_context *ctxt,
1475 u8 enabled_tc,
1476 bool is_add)
38e00438 1477#endif
41c445ff
JB		 1478{
1479 struct i40e_pf *pf = vsi->back;
1480 u16 sections = 0;
1481 u8 netdev_tc = 0;
1482 u16 numtc = 0;
1483 u16 qcount;
1484 u8 offset;
1485 u16 qmap;
1486 int i;
4e3b35b0 1487 u16 num_tc_qps = 0;
41c445ff
JB		 1488
1489 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1490 offset = 0;
1491
1492 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1493 /* Find numtc from enabled TC bitmap */
1494 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1495 if (enabled_tc & (1 << i)) /* TC is enabled */
1496 numtc++;
1497 }
1498 if (!numtc) {
1499 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1500 numtc = 1;
1501 }
1502 } else {
1503 /* At least TC0 is enabled in case of non-DCB case */
1504 numtc = 1;
1505 }
1506
1507 vsi->tc_config.numtc = numtc;
1508 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1509 /* Number of queues per enabled TC */
eb051afe 1510 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1511 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1512
1513 /* Setup queue offset/count for all TCs for given VSI */
1514 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1515 /* See if the given TC is enabled for the given VSI */
1516 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1517 int pow, num_qps;
1518
41c445ff
JB		 1519 switch (vsi->type) {
1520 case I40E_VSI_MAIN:
4e3b35b0 1521 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1522 break;
38e00438
VD		 1523#ifdef I40E_FCOE
1524 case I40E_VSI_FCOE:
1525 qcount = num_tc_qps;
1526 break;
1527#endif
41c445ff
JB		 1528 case I40E_VSI_FDIR:
1529 case I40E_VSI_SRIOV:
1530 case I40E_VSI_VMDQ2:
1531 default:
4e3b35b0 1532 qcount = num_tc_qps;
41c445ff
JB		 1533 WARN_ON(i != 0);
1534 break;
1535 }
4e3b35b0
NP		 1536 vsi->tc_config.tc_info[i].qoffset = offset;
1537 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1538
1539 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1540 num_qps = qcount;
41c445ff 1541 pow = 0;
4e3b35b0 1542 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1543 pow++;
1544 num_qps >>= 1;
1545 }
1546
1547 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1548 qmap =
1549 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1550 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1551
4e3b35b0 1552 offset += qcount;
41c445ff
JB		 1553 } else {
1554 /* TC is not enabled so set the offset to
1555 * default queue and allocate one queue
1556 * for the given TC.
1557 */
1558 vsi->tc_config.tc_info[i].qoffset = 0;
1559 vsi->tc_config.tc_info[i].qcount = 1;
1560 vsi->tc_config.tc_info[i].netdev_tc = 0;
1561
1562 qmap = 0;
1563 }
1564 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1565 }
1566
1567 /* Set actual Tx/Rx queue pairs */
1568 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1569 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1570 if (vsi->req_queue_pairs > 0)
1571 vsi->num_queue_pairs = vsi->req_queue_pairs;
1572 else
1573 vsi->num_queue_pairs = pf->num_lan_msix;
1574 }
41c445ff
JB		 1575
1576 /* Scheduler section valid can only be set for ADD VSI */
1577 if (is_add) {
1578 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1579
1580 ctxt->info.up_enable_bits = enabled_tc;
1581 }
1582 if (vsi->type == I40E_VSI_SRIOV) {
1583 ctxt->info.mapping_flags |=
1584 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1585 for (i = 0; i < vsi->num_queue_pairs; i++)
1586 ctxt->info.queue_mapping[i] =
1587 cpu_to_le16(vsi->base_queue + i);
1588 } else {
1589 ctxt->info.mapping_flags |=
1590 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1591 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1592 }
1593 ctxt->info.valid_sections |= cpu_to_le16(sections);
1594}
1595
1596/**
1597 * i40e_set_rx_mode - NDO callback to set the netdev filters
1598 * @netdev: network interface device structure
1599 **/
38e00438
VD		 1600#ifdef I40E_FCOE
1601void i40e_set_rx_mode(struct net_device *netdev)
1602#else
41c445ff 1603static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1604#endif
41c445ff
JB		 1605{
1606 struct i40e_netdev_priv *np = netdev_priv(netdev);
1607 struct i40e_mac_filter *f, *ftmp;
1608 struct i40e_vsi *vsi = np->vsi;
1609 struct netdev_hw_addr *uca;
1610 struct netdev_hw_addr *mca;
1611 struct netdev_hw_addr *ha;
1612
1613 /* add addr if not already in the filter list */
1614 netdev_for_each_uc_addr(uca, netdev) {
1615 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1616 if (i40e_is_vsi_in_vlan(vsi))
1617 i40e_put_mac_in_vlan(vsi, uca->addr,
1618 false, true);
1619 else
1620 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1621 false, true);
1622 }
1623 }
1624
1625 netdev_for_each_mc_addr(mca, netdev) {
1626 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1627 if (i40e_is_vsi_in_vlan(vsi))
1628 i40e_put_mac_in_vlan(vsi, mca->addr,
1629 false, true);
1630 else
1631 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1632 false, true);
1633 }
1634 }
1635
1636 /* remove filter if not in netdev list */
1637 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1638 bool found = false;
1639
1640 if (!f->is_netdev)
1641 continue;
1642
1643 if (is_multicast_ether_addr(f->macaddr)) {
1644 netdev_for_each_mc_addr(mca, netdev) {
1645 if (ether_addr_equal(mca->addr, f->macaddr)) {
1646 found = true;
1647 break;
1648 }
1649 }
1650 } else {
1651 netdev_for_each_uc_addr(uca, netdev) {
1652 if (ether_addr_equal(uca->addr, f->macaddr)) {
1653 found = true;
1654 break;
1655 }
1656 }
1657
1658 for_each_dev_addr(netdev, ha) {
1659 if (ether_addr_equal(ha->addr, f->macaddr)) {
1660 found = true;
1661 break;
1662 }
1663 }
1664 }
1665 if (!found)
1666 i40e_del_filter(
1667 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1668 }
1669
1670 /* check for other flag changes */
1671 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1672 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1673 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1674 }
1675}
1676
1677/**
1678 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1679 * @vsi: ptr to the VSI
1680 *
1681 * Push any outstanding VSI filter changes through the AdminQ.
1682 *
1683 * Returns 0 or error value
1684 **/
1685int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1686{
1687 struct i40e_mac_filter *f, *ftmp;
1688 bool promisc_forced_on = false;
1689 bool add_happened = false;
1690 int filter_list_len = 0;
1691 u32 changed_flags = 0;
dcae29be 1692 i40e_status aq_ret = 0;
41c445ff
JB		 1693 struct i40e_pf *pf;
1694 int num_add = 0;
1695 int num_del = 0;
1696 u16 cmd_flags;
1697
1698 /* empty array typed pointers, kcalloc later */
1699 struct i40e_aqc_add_macvlan_element_data *add_list;
1700 struct i40e_aqc_remove_macvlan_element_data *del_list;
1701
1702 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1703 usleep_range(1000, 2000);
1704 pf = vsi->back;
1705
1706 if (vsi->netdev) {
1707 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1708 vsi->current_netdev_flags = vsi->netdev->flags;
1709 }
1710
1711 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1712 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1713
1714 filter_list_len = pf->hw.aq.asq_buf_size /
1715 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1716 del_list = kcalloc(filter_list_len,
1717 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1718 GFP_KERNEL);
1719 if (!del_list)
1720 return -ENOMEM;
1721
1722 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1723 if (!f->changed)
1724 continue;
1725
1726 if (f->counter != 0)
1727 continue;
1728 f->changed = false;
1729 cmd_flags = 0;
1730
1731 /* add to delete list */
9a173901 1732 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1733 del_list[num_del].vlan_tag =
1734 cpu_to_le16((u16)(f->vlan ==
1735 I40E_VLAN_ANY ? 0 : f->vlan));
1736
41c445ff
JB		 1737 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1738 del_list[num_del].flags = cmd_flags;
1739 num_del++;
1740
1741 /* unlink from filter list */
1742 list_del(&f->list);
1743 kfree(f);
1744
1745 /* flush a full buffer */
1746 if (num_del == filter_list_len) {
dcae29be 1747 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1748 vsi->seid, del_list, num_del,
1749 NULL);
1750 num_del = 0;
1751 memset(del_list, 0, sizeof(*del_list));
1752
fdfe9cbe
SN		 1753 if (aq_ret &&
1754 pf->hw.aq.asq_last_status !=
1755 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1756 dev_info(&pf->pdev->dev,
1757 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1758 aq_ret,
41c445ff
JB		 1759 pf->hw.aq.asq_last_status);
1760 }
1761 }
1762 if (num_del) {
dcae29be 1763 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1764 del_list, num_del, NULL);
1765 num_del = 0;
1766
fdfe9cbe
SN		 1767 if (aq_ret &&
1768 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1769 dev_info(&pf->pdev->dev,
1770 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1771 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1772 }
1773
1774 kfree(del_list);
1775 del_list = NULL;
1776
1777 /* do all the adds now */
1778 filter_list_len = pf->hw.aq.asq_buf_size /
1779 sizeof(struct i40e_aqc_add_macvlan_element_data),
1780 add_list = kcalloc(filter_list_len,
1781 sizeof(struct i40e_aqc_add_macvlan_element_data),
1782 GFP_KERNEL);
1783 if (!add_list)
1784 return -ENOMEM;
1785
1786 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1787 if (!f->changed)
1788 continue;
1789
1790 if (f->counter == 0)
1791 continue;
1792 f->changed = false;
1793 add_happened = true;
1794 cmd_flags = 0;
1795
1796 /* add to add array */
9a173901 1797 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1798 add_list[num_add].vlan_tag =
1799 cpu_to_le16(
1800 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1801 add_list[num_add].queue_number = 0;
1802
1803 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1804 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1805 num_add++;
1806
1807 /* flush a full buffer */
1808 if (num_add == filter_list_len) {
dcae29be
JB		 1809 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1810 add_list, num_add,
1811 NULL);
41c445ff
JB		 1812 num_add = 0;
1813
dcae29be 1814 if (aq_ret)
41c445ff
JB		 1815 break;
1816 memset(add_list, 0, sizeof(*add_list));
1817 }
1818 }
1819 if (num_add) {
dcae29be
JB		 1820 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1821 add_list, num_add, NULL);
41c445ff
JB		 1822 num_add = 0;
1823 }
1824 kfree(add_list);
1825 add_list = NULL;
1826
30650cc5
SN		 1827 if (add_happened && aq_ret &&
1828 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1829 dev_info(&pf->pdev->dev,
1830 "add filter failed, err %d, aq_err %d\n",
dcae29be 1831 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1832 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1833 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1834 &vsi->state)) {
1835 promisc_forced_on = true;
1836 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1837 &vsi->state);
1838 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1839 }
1840 }
1841 }
1842
1843 /* check for changes in promiscuous modes */
1844 if (changed_flags & IFF_ALLMULTI) {
1845 bool cur_multipromisc;
1846 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1847 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1848 vsi->seid,
1849 cur_multipromisc,
1850 NULL);
1851 if (aq_ret)
41c445ff
JB		 1852 dev_info(&pf->pdev->dev,
1853 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1854 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1855 }
1856 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1857 bool cur_promisc;
1858 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1859 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1860 &vsi->state));
dcae29be
JB		 1861 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1862 vsi->seid,
1863 cur_promisc, NULL);
1864 if (aq_ret)
41c445ff
JB		 1865 dev_info(&pf->pdev->dev,
1866 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1867 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1868 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1869 vsi->seid,
1870 cur_promisc, NULL);
1871 if (aq_ret)
1872 dev_info(&pf->pdev->dev,
1873 "set brdcast promisc failed, err %d, aq_err %d\n",
1874 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1875 }
1876
1877 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1878 return 0;
1879}
1880
1881/**
1882 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1883 * @pf: board private structure
1884 **/
1885static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1886{
1887 int v;
1888
1889 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1890 return;
1891 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1892
505682cd 1893 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1894 if (pf->vsi[v] &&
1895 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1896 i40e_sync_vsi_filters(pf->vsi[v]);
1897 }
1898}
1899
1900/**
1901 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1902 * @netdev: network interface device structure
1903 * @new_mtu: new value for maximum frame size
1904 *
1905 * Returns 0 on success, negative on failure
1906 **/
1907static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1908{
1909 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1910 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1911 struct i40e_vsi *vsi = np->vsi;
1912
1913 /* MTU < 68 is an error and causes problems on some kernels */
1914 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1915 return -EINVAL;
1916
1917 netdev_info(netdev, "changing MTU from %d to %d\n",
1918 netdev->mtu, new_mtu);
1919 netdev->mtu = new_mtu;
1920 if (netif_running(netdev))
1921 i40e_vsi_reinit_locked(vsi);
1922
1923 return 0;
1924}
1925
beb0dff1
JK		 1926/**
1927 * i40e_ioctl - Access the hwtstamp interface
1928 * @netdev: network interface device structure
1929 * @ifr: interface request data
1930 * @cmd: ioctl command
1931 **/
1932int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1933{
1934 struct i40e_netdev_priv *np = netdev_priv(netdev);
1935 struct i40e_pf *pf = np->vsi->back;
1936
1937 switch (cmd) {
1938 case SIOCGHWTSTAMP:
1939 return i40e_ptp_get_ts_config(pf, ifr);
1940 case SIOCSHWTSTAMP:
1941 return i40e_ptp_set_ts_config(pf, ifr);
1942 default:
1943 return -EOPNOTSUPP;
1944 }
1945}
1946
41c445ff
JB		 1947/**
1948 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1949 * @vsi: the vsi being adjusted
1950 **/
1951void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1952{
1953 struct i40e_vsi_context ctxt;
1954 i40e_status ret;
1955
1956 if ((vsi->info.valid_sections &
1957 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1958 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1959 return; /* already enabled */
1960
1961 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1962 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1963 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1964
1965 ctxt.seid = vsi->seid;
1966 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1967 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1968 if (ret) {
1969 dev_info(&vsi->back->pdev->dev,
1970 "%s: update vsi failed, aq_err=%d\n",
1971 __func__, vsi->back->hw.aq.asq_last_status);
1972 }
1973}
1974
1975/**
1976 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1977 * @vsi: the vsi being adjusted
1978 **/
1979void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1980{
1981 struct i40e_vsi_context ctxt;
1982 i40e_status ret;
1983
1984 if ((vsi->info.valid_sections &
1985 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1986 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1987 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1988 return; /* already disabled */
1989
1990 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1991 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1992 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1993
1994 ctxt.seid = vsi->seid;
1995 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1996 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1997 if (ret) {
1998 dev_info(&vsi->back->pdev->dev,
1999 "%s: update vsi failed, aq_err=%d\n",
2000 __func__, vsi->back->hw.aq.asq_last_status);
2001 }
2002}
2003
2004/**
2005 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2006 * @netdev: network interface to be adjusted
2007 * @features: netdev features to test if VLAN offload is enabled or not
2008 **/
2009static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2010{
2011 struct i40e_netdev_priv *np = netdev_priv(netdev);
2012 struct i40e_vsi *vsi = np->vsi;
2013
2014 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2015 i40e_vlan_stripping_enable(vsi);
2016 else
2017 i40e_vlan_stripping_disable(vsi);
2018}
2019
2020/**
2021 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2022 * @vsi: the vsi being configured
2023 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2024 **/
2025int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2026{
2027 struct i40e_mac_filter *f, *add_f;
2028 bool is_netdev, is_vf;
41c445ff
JB		 2029
2030 is_vf = (vsi->type == I40E_VSI_SRIOV);
2031 is_netdev = !!(vsi->netdev);
2032
2033 if (is_netdev) {
2034 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2035 is_vf, is_netdev);
2036 if (!add_f) {
2037 dev_info(&vsi->back->pdev->dev,
2038 "Could not add vlan filter %d for %pM\n",
2039 vid, vsi->netdev->dev_addr);
2040 return -ENOMEM;
2041 }
2042 }
2043
2044 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2045 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2046 if (!add_f) {
2047 dev_info(&vsi->back->pdev->dev,
2048 "Could not add vlan filter %d for %pM\n",
2049 vid, f->macaddr);
2050 return -ENOMEM;
2051 }
2052 }
2053
41c445ff
JB		 2054 /* Now if we add a vlan tag, make sure to check if it is the first
2055 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2056 * with 0, so we now accept untagged and specified tagged traffic
2057 * (and not any taged and untagged)
2058 */
2059 if (vid > 0) {
2060 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2061 I40E_VLAN_ANY,
2062 is_vf, is_netdev)) {
2063 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2064 I40E_VLAN_ANY, is_vf, is_netdev);
2065 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2066 is_vf, is_netdev);
2067 if (!add_f) {
2068 dev_info(&vsi->back->pdev->dev,
2069 "Could not add filter 0 for %pM\n",
2070 vsi->netdev->dev_addr);
2071 return -ENOMEM;
2072 }
2073 }
8d82a7c5 2074 }
41c445ff 2075
8d82a7c5
GR		 2076 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2077 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2078 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2079 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2080 is_vf, is_netdev)) {
2081 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2082 is_vf, is_netdev);
2083 add_f = i40e_add_filter(vsi, f->macaddr,
2084 0, is_vf, is_netdev);
2085 if (!add_f) {
2086 dev_info(&vsi->back->pdev->dev,
2087 "Could not add filter 0 for %pM\n",
2088 f->macaddr);
2089 return -ENOMEM;
2090 }
2091 }
2092 }
41c445ff
JB		 2093 }
2094
80f6428f
ASJ		 2095 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2096 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2097 return 0;
2098
2099 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2100}
2101
2102/**
2103 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2104 * @vsi: the vsi being configured
2105 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2106 *
2107 * Return: 0 on success or negative otherwise
41c445ff
JB		 2108 **/
2109int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2110{
2111 struct net_device *netdev = vsi->netdev;
2112 struct i40e_mac_filter *f, *add_f;
2113 bool is_vf, is_netdev;
2114 int filter_count = 0;
41c445ff
JB		 2115
2116 is_vf = (vsi->type == I40E_VSI_SRIOV);
2117 is_netdev = !!(netdev);
2118
2119 if (is_netdev)
2120 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2121
2122 list_for_each_entry(f, &vsi->mac_filter_list, list)
2123 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2124
41c445ff
JB		 2125 /* go through all the filters for this VSI and if there is only
2126 * vid == 0 it means there are no other filters, so vid 0 must
2127 * be replaced with -1. This signifies that we should from now
2128 * on accept any traffic (with any tag present, or untagged)
2129 */
2130 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2131 if (is_netdev) {
2132 if (f->vlan &&
2133 ether_addr_equal(netdev->dev_addr, f->macaddr))
2134 filter_count++;
2135 }
2136
2137 if (f->vlan)
2138 filter_count++;
2139 }
2140
2141 if (!filter_count && is_netdev) {
2142 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2143 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2144 is_vf, is_netdev);
2145 if (!f) {
2146 dev_info(&vsi->back->pdev->dev,
2147 "Could not add filter %d for %pM\n",
2148 I40E_VLAN_ANY, netdev->dev_addr);
2149 return -ENOMEM;
2150 }
2151 }
2152
2153 if (!filter_count) {
2154 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2155 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2156 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2157 is_vf, is_netdev);
2158 if (!add_f) {
2159 dev_info(&vsi->back->pdev->dev,
2160 "Could not add filter %d for %pM\n",
2161 I40E_VLAN_ANY, f->macaddr);
2162 return -ENOMEM;
2163 }
2164 }
2165 }
2166
80f6428f
ASJ		 2167 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2168 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2169 return 0;
2170
41c445ff
JB		 2171 return i40e_sync_vsi_filters(vsi);
2172}
2173
2174/**
2175 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2176 * @netdev: network interface to be adjusted
2177 * @vid: vlan id to be added
078b5876
JB		 2178 *
2179 * net_device_ops implementation for adding vlan ids
41c445ff 2180 **/
38e00438
VD		 2181#ifdef I40E_FCOE
2182int i40e_vlan_rx_add_vid(struct net_device *netdev,
2183 __always_unused __be16 proto, u16 vid)
2184#else
41c445ff
JB		 2185static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2186 __always_unused __be16 proto, u16 vid)
38e00438 2187#endif
41c445ff
JB		 2188{
2189 struct i40e_netdev_priv *np = netdev_priv(netdev);
2190 struct i40e_vsi *vsi = np->vsi;
078b5876 2191 int ret = 0;
41c445ff
JB		 2192
2193 if (vid > 4095)
078b5876
JB		 2194 return -EINVAL;
2195
2196 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2197
6982d429
ASJ		 2198 /* If the network stack called us with vid = 0 then
2199 * it is asking to receive priority tagged packets with
2200 * vlan id 0. Our HW receives them by default when configured
2201 * to receive untagged packets so there is no need to add an
2202 * extra filter for vlan 0 tagged packets.
41c445ff 2203 */
6982d429
ASJ		 2204 if (vid)
2205 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2206
078b5876
JB		 2207 if (!ret && (vid < VLAN_N_VID))
2208 set_bit(vid, vsi->active_vlans);
41c445ff 2209
078b5876 2210 return ret;
41c445ff
JB		 2211}
2212
2213/**
2214 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2215 * @netdev: network interface to be adjusted
2216 * @vid: vlan id to be removed
078b5876 2217 *
fdfd943e 2218 * net_device_ops implementation for removing vlan ids
41c445ff 2219 **/
38e00438
VD		 2220#ifdef I40E_FCOE
2221int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2222 __always_unused __be16 proto, u16 vid)
2223#else
41c445ff
JB		 2224static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2225 __always_unused __be16 proto, u16 vid)
38e00438 2226#endif
41c445ff
JB		 2227{
2228 struct i40e_netdev_priv *np = netdev_priv(netdev);
2229 struct i40e_vsi *vsi = np->vsi;
2230
078b5876
JB		 2231 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2232
41c445ff
JB		 2233 /* return code is ignored as there is nothing a user
2234 * can do about failure to remove and a log message was
078b5876 2235 * already printed from the other function
41c445ff
JB		 2236 */
2237 i40e_vsi_kill_vlan(vsi, vid);
2238
2239 clear_bit(vid, vsi->active_vlans);
078b5876 2240
41c445ff
JB		 2241 return 0;
2242}
2243
2244/**
2245 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2246 * @vsi: the vsi being brought back up
2247 **/
2248static void i40e_restore_vlan(struct i40e_vsi *vsi)
2249{
2250 u16 vid;
2251
2252 if (!vsi->netdev)
2253 return;
2254
2255 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2256
2257 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2258 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2259 vid);
2260}
2261
2262/**
2263 * i40e_vsi_add_pvid - Add pvid for the VSI
2264 * @vsi: the vsi being adjusted
2265 * @vid: the vlan id to set as a PVID
2266 **/
dcae29be 2267int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2268{
2269 struct i40e_vsi_context ctxt;
dcae29be 2270 i40e_status aq_ret;
41c445ff
JB		 2271
2272 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2273 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2274 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2275 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2276 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2277
2278 ctxt.seid = vsi->seid;
2279 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2280 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2281 if (aq_ret) {
41c445ff
JB		 2282 dev_info(&vsi->back->pdev->dev,
2283 "%s: update vsi failed, aq_err=%d\n",
2284 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2285 return -ENOENT;
41c445ff
JB		 2286 }
2287
dcae29be 2288 return 0;
41c445ff
JB		 2289}
2290
2291/**
2292 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2293 * @vsi: the vsi being adjusted
2294 *
2295 * Just use the vlan_rx_register() service to put it back to normal
2296 **/
2297void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2298{
6c12fcbf
GR		 2299 i40e_vlan_stripping_disable(vsi);
2300
41c445ff 2301 vsi->info.pvid = 0;
41c445ff
JB		 2302}
2303
2304/**
2305 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2306 * @vsi: ptr to the VSI
2307 *
2308 * If this function returns with an error, then it's possible one or
2309 * more of the rings is populated (while the rest are not). It is the
2310 * callers duty to clean those orphaned rings.
2311 *
2312 * Return 0 on success, negative on failure
2313 **/
2314static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2315{
2316 int i, err = 0;
2317
2318 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2319 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2320
2321 return err;
2322}
2323
2324/**
2325 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2326 * @vsi: ptr to the VSI
2327 *
2328 * Free VSI's transmit software resources
2329 **/
2330static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2331{
2332 int i;
2333
8e9dca53
GR		 2334 if (!vsi->tx_rings)
2335 return;
2336
41c445ff 2337 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2338 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2339 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2340}
2341
2342/**
2343 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2344 * @vsi: ptr to the VSI
2345 *
2346 * If this function returns with an error, then it's possible one or
2347 * more of the rings is populated (while the rest are not). It is the
2348 * callers duty to clean those orphaned rings.
2349 *
2350 * Return 0 on success, negative on failure
2351 **/
2352static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2353{
2354 int i, err = 0;
2355
2356 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2357 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2358#ifdef I40E_FCOE
2359 i40e_fcoe_setup_ddp_resources(vsi);
2360#endif
41c445ff
JB		 2361 return err;
2362}
2363
2364/**
2365 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2366 * @vsi: ptr to the VSI
2367 *
2368 * Free all receive software resources
2369 **/
2370static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2371{
2372 int i;
2373
8e9dca53
GR		 2374 if (!vsi->rx_rings)
2375 return;
2376
41c445ff 2377 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2378 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2379 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2380#ifdef I40E_FCOE
2381 i40e_fcoe_free_ddp_resources(vsi);
2382#endif
41c445ff
JB		 2383}
2384
3ffa037d
NP		 2385/**
2386 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2387 * @ring: The Tx ring to configure
2388 *
2389 * This enables/disables XPS for a given Tx descriptor ring
2390 * based on the TCs enabled for the VSI that ring belongs to.
2391 **/
2392static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2393{
2394 struct i40e_vsi *vsi = ring->vsi;
2395 cpumask_var_t mask;
2396
2397 if (ring->q_vector && ring->netdev) {
2398 /* Single TC mode enable XPS */
2399 if (vsi->tc_config.numtc <= 1 &&
2400 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state)) {
2401 netif_set_xps_queue(ring->netdev,
2402 &ring->q_vector->affinity_mask,
2403 ring->queue_index);
2404 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2405 /* Disable XPS to allow selection based on TC */
2406 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2407 netif_set_xps_queue(ring->netdev, mask,
2408 ring->queue_index);
2409 free_cpumask_var(mask);
2410 }
2411 }
2412}
2413
41c445ff
JB		 2414/**
2415 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2416 * @ring: The Tx ring to configure
2417 *
2418 * Configure the Tx descriptor ring in the HMC context.
2419 **/
2420static int i40e_configure_tx_ring(struct i40e_ring *ring)
2421{
2422 struct i40e_vsi *vsi = ring->vsi;
2423 u16 pf_q = vsi->base_queue + ring->queue_index;
2424 struct i40e_hw *hw = &vsi->back->hw;
2425 struct i40e_hmc_obj_txq tx_ctx;
2426 i40e_status err = 0;
2427 u32 qtx_ctl = 0;
2428
2429 /* some ATR related tx ring init */
60ea5f83 2430 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2431 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2432 ring->atr_count = 0;
2433 } else {
2434 ring->atr_sample_rate = 0;
2435 }
2436
3ffa037d
NP		 2437 /* configure XPS */
2438 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2439
2440 /* clear the context structure first */
2441 memset(&tx_ctx, 0, sizeof(tx_ctx));
2442
2443 tx_ctx.new_context = 1;
2444 tx_ctx.base = (ring->dma / 128);
2445 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2446 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2447 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2448#ifdef I40E_FCOE
2449 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2450#endif
beb0dff1 2451 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2452 /* FDIR VSI tx ring can still use RS bit and writebacks */
2453 if (vsi->type != I40E_VSI_FDIR)
2454 tx_ctx.head_wb_ena = 1;
2455 tx_ctx.head_wb_addr = ring->dma +
2456 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2457
2458 /* As part of VSI creation/update, FW allocates certain
2459 * Tx arbitration queue sets for each TC enabled for
2460 * the VSI. The FW returns the handles to these queue
2461 * sets as part of the response buffer to Add VSI,
2462 * Update VSI, etc. AQ commands. It is expected that
2463 * these queue set handles be associated with the Tx
2464 * queues by the driver as part of the TX queue context
2465 * initialization. This has to be done regardless of
2466 * DCB as by default everything is mapped to TC0.
2467 */
2468 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2469 tx_ctx.rdylist_act = 0;
2470
2471 /* clear the context in the HMC */
2472 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2473 if (err) {
2474 dev_info(&vsi->back->pdev->dev,
2475 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2476 ring->queue_index, pf_q, err);
2477 return -ENOMEM;
2478 }
2479
2480 /* set the context in the HMC */
2481 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2482 if (err) {
2483 dev_info(&vsi->back->pdev->dev,
2484 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2485 ring->queue_index, pf_q, err);
2486 return -ENOMEM;
2487 }
2488
2489 /* Now associate this queue with this PCI function */
7a28d885 2490 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2491 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2492 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2493 I40E_QTX_CTL_VFVM_INDX_MASK;
2494 } else {
9d8bf547 2495 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2496 }
2497
13fd9774
SN		 2498 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2499 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2500 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2501 i40e_flush(hw);
2502
2503 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2504
2505 /* cache tail off for easier writes later */
2506 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2507
2508 return 0;
2509}
2510
2511/**
2512 * i40e_configure_rx_ring - Configure a receive ring context
2513 * @ring: The Rx ring to configure
2514 *
2515 * Configure the Rx descriptor ring in the HMC context.
2516 **/
2517static int i40e_configure_rx_ring(struct i40e_ring *ring)
2518{
2519 struct i40e_vsi *vsi = ring->vsi;
2520 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2521 u16 pf_q = vsi->base_queue + ring->queue_index;
2522 struct i40e_hw *hw = &vsi->back->hw;
2523 struct i40e_hmc_obj_rxq rx_ctx;
2524 i40e_status err = 0;
2525
2526 ring->state = 0;
2527
2528 /* clear the context structure first */
2529 memset(&rx_ctx, 0, sizeof(rx_ctx));
2530
2531 ring->rx_buf_len = vsi->rx_buf_len;
2532 ring->rx_hdr_len = vsi->rx_hdr_len;
2533
2534 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2535 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2536
2537 rx_ctx.base = (ring->dma / 128);
2538 rx_ctx.qlen = ring->count;
2539
2540 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2541 set_ring_16byte_desc_enabled(ring);
2542 rx_ctx.dsize = 0;
2543 } else {
2544 rx_ctx.dsize = 1;
2545 }
2546
2547 rx_ctx.dtype = vsi->dtype;
2548 if (vsi->dtype) {
2549 set_ring_ps_enabled(ring);
2550 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2551 I40E_RX_SPLIT_IP |
2552 I40E_RX_SPLIT_TCP_UDP |
2553 I40E_RX_SPLIT_SCTP;
2554 } else {
2555 rx_ctx.hsplit_0 = 0;
2556 }
2557
2558 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2559 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2560 if (hw->revision_id == 0)
2561 rx_ctx.lrxqthresh = 0;
2562 else
2563 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2564 rx_ctx.crcstrip = 1;
2565 rx_ctx.l2tsel = 1;
2566 rx_ctx.showiv = 1;
38e00438
VD		 2567#ifdef I40E_FCOE
2568 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2569#endif
acb3676b
CS		 2570 /* set the prefena field to 1 because the manual says to */
2571 rx_ctx.prefena = 1;
41c445ff
JB		 2572
2573 /* clear the context in the HMC */
2574 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2575 if (err) {
2576 dev_info(&vsi->back->pdev->dev,
2577 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2578 ring->queue_index, pf_q, err);
2579 return -ENOMEM;
2580 }
2581
2582 /* set the context in the HMC */
2583 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2584 if (err) {
2585 dev_info(&vsi->back->pdev->dev,
2586 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2587 ring->queue_index, pf_q, err);
2588 return -ENOMEM;
2589 }
2590
2591 /* cache tail for quicker writes, and clear the reg before use */
2592 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2593 writel(0, ring->tail);
2594
a132af24
MW		 2595 if (ring_is_ps_enabled(ring)) {
2596 i40e_alloc_rx_headers(ring);
2597 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2598 } else {
2599 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2600 }
41c445ff
JB		 2601
2602 return 0;
2603}
2604
2605/**
2606 * i40e_vsi_configure_tx - Configure the VSI for Tx
2607 * @vsi: VSI structure describing this set of rings and resources
2608 *
2609 * Configure the Tx VSI for operation.
2610 **/
2611static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2612{
2613 int err = 0;
2614 u16 i;
2615
9f65e15b
AD		 2616 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2617 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2618
2619 return err;
2620}
2621
2622/**
2623 * i40e_vsi_configure_rx - Configure the VSI for Rx
2624 * @vsi: the VSI being configured
2625 *
2626 * Configure the Rx VSI for operation.
2627 **/
2628static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2629{
2630 int err = 0;
2631 u16 i;
2632
2633 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2634 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2635 + ETH_FCS_LEN + VLAN_HLEN;
2636 else
2637 vsi->max_frame = I40E_RXBUFFER_2048;
2638
2639 /* figure out correct receive buffer length */
2640 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2641 I40E_FLAG_RX_PS_ENABLED)) {
2642 case I40E_FLAG_RX_1BUF_ENABLED:
2643 vsi->rx_hdr_len = 0;
2644 vsi->rx_buf_len = vsi->max_frame;
2645 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2646 break;
2647 case I40E_FLAG_RX_PS_ENABLED:
2648 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2649 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2650 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2651 break;
2652 default:
2653 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2654 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2655 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2656 break;
2657 }
2658
38e00438
VD		 2659#ifdef I40E_FCOE
2660 /* setup rx buffer for FCoE */
2661 if ((vsi->type == I40E_VSI_FCOE) &&
2662 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2663 vsi->rx_hdr_len = 0;
2664 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2665 vsi->max_frame = I40E_RXBUFFER_3072;
2666 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2667 }
2668
2669#endif /* I40E_FCOE */
41c445ff
JB		 2670 /* round up for the chip's needs */
2671 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2672 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2673 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2674 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2675
2676 /* set up individual rings */
2677 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2678 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2679
2680 return err;
2681}
2682
2683/**
2684 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2685 * @vsi: ptr to the VSI
2686 **/
2687static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2688{
e7046ee1 2689 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2690 u16 qoffset, qcount;
2691 int i, n;
2692
2693 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2694 return;
2695
2696 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2697 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2698 continue;
2699
2700 qoffset = vsi->tc_config.tc_info[n].qoffset;
2701 qcount = vsi->tc_config.tc_info[n].qcount;
2702 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2703 rx_ring = vsi->rx_rings[i];
2704 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2705 rx_ring->dcb_tc = n;
2706 tx_ring->dcb_tc = n;
2707 }
2708 }
2709}
2710
2711/**
2712 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2713 * @vsi: ptr to the VSI
2714 **/
2715static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2716{
2717 if (vsi->netdev)
2718 i40e_set_rx_mode(vsi->netdev);
2719}
2720
17a73f6b
JG		 2721/**
2722 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2723 * @vsi: Pointer to the targeted VSI
2724 *
2725 * This function replays the hlist on the hw where all the SB Flow Director
2726 * filters were saved.
2727 **/
2728static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2729{
2730 struct i40e_fdir_filter *filter;
2731 struct i40e_pf *pf = vsi->back;
2732 struct hlist_node *node;
2733
55a5e60b
ASJ		 2734 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2735 return;
2736
17a73f6b
JG		 2737 hlist_for_each_entry_safe(filter, node,
2738 &pf->fdir_filter_list, fdir_node) {
2739 i40e_add_del_fdir(vsi, filter, true);
2740 }
2741}
2742
41c445ff
JB		 2743/**
2744 * i40e_vsi_configure - Set up the VSI for action
2745 * @vsi: the VSI being configured
2746 **/
2747static int i40e_vsi_configure(struct i40e_vsi *vsi)
2748{
2749 int err;
2750
2751 i40e_set_vsi_rx_mode(vsi);
2752 i40e_restore_vlan(vsi);
2753 i40e_vsi_config_dcb_rings(vsi);
2754 err = i40e_vsi_configure_tx(vsi);
2755 if (!err)
2756 err = i40e_vsi_configure_rx(vsi);
2757
2758 return err;
2759}
2760
2761/**
2762 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2763 * @vsi: the VSI being configured
2764 **/
2765static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2766{
2767 struct i40e_pf *pf = vsi->back;
2768 struct i40e_q_vector *q_vector;
2769 struct i40e_hw *hw = &pf->hw;
2770 u16 vector;
2771 int i, q;
2772 u32 val;
2773 u32 qp;
2774
2775 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2776 * and PFINT_LNKLSTn registers, e.g.:
2777 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2778 */
2779 qp = vsi->base_queue;
2780 vector = vsi->base_vector;
493fb300
AD		 2781 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2782 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2783 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2784 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2785 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2786 q_vector->rx.itr);
2787 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2788 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2789 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2790 q_vector->tx.itr);
2791
2792 /* Linked list for the queuepairs assigned to this vector */
2793 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2794 for (q = 0; q < q_vector->num_ringpairs; q++) {
2795 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2796 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2797 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2798 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2799 (I40E_QUEUE_TYPE_TX
2800 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2801
2802 wr32(hw, I40E_QINT_RQCTL(qp), val);
2803
2804 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2805 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2806 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2807 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2808 (I40E_QUEUE_TYPE_RX
2809 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2810
2811 /* Terminate the linked list */
2812 if (q == (q_vector->num_ringpairs - 1))
2813 val |= (I40E_QUEUE_END_OF_LIST
2814 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2815
2816 wr32(hw, I40E_QINT_TQCTL(qp), val);
2817 qp++;
2818 }
2819 }
2820
2821 i40e_flush(hw);
2822}
2823
2824/**
2825 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2826 * @hw: ptr to the hardware info
2827 **/
ab437b5a 2828static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2829{
ab437b5a 2830 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2831 u32 val;
2832
2833 /* clear things first */
2834 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2835 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2836
2837 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2838 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2839 I40E_PFINT_ICR0_ENA_GRST_MASK |
2840 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2841 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2842 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2843 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2844 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2845
ab437b5a
JK		 2846 if (pf->flags & I40E_FLAG_PTP)
2847 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2848
41c445ff
JB		 2849 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2850
2851 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2852 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2853 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2854
2855 /* OTHER_ITR_IDX = 0 */
2856 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2857}
2858
2859/**
2860 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2861 * @vsi: the VSI being configured
2862 **/
2863static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2864{
493fb300 2865 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2866 struct i40e_pf *pf = vsi->back;
2867 struct i40e_hw *hw = &pf->hw;
2868 u32 val;
2869
2870 /* set the ITR configuration */
2871 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2872 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2873 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2874 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2875 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2876 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2877
ab437b5a 2878 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 2879
2880 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2881 wr32(hw, I40E_PFINT_LNKLST0, 0);
2882
f29eaa3d 2883 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2884 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2885 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2886 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2887
2888 wr32(hw, I40E_QINT_RQCTL(0), val);
2889
2890 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2891 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2892 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2893
2894 wr32(hw, I40E_QINT_TQCTL(0), val);
2895 i40e_flush(hw);
2896}
2897
2ef28cfb
MW		 2898/**
2899 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2900 * @pf: board private structure
2901 **/
2902void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2903{
2904 struct i40e_hw *hw = &pf->hw;
2905
2906 wr32(hw, I40E_PFINT_DYN_CTL0,
2907 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2908 i40e_flush(hw);
2909}
2910
41c445ff
JB		 2911/**
2912 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2913 * @pf: board private structure
2914 **/
116a57d4 2915void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2916{
2917 struct i40e_hw *hw = &pf->hw;
2918 u32 val;
2919
2920 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2921 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2922 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2923
2924 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2925 i40e_flush(hw);
2926}
2927
2928/**
2929 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2930 * @vsi: pointer to a vsi
2931 * @vector: enable a particular Hw Interrupt vector
2932 **/
2933void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2934{
2935 struct i40e_pf *pf = vsi->back;
2936 struct i40e_hw *hw = &pf->hw;
2937 u32 val;
2938
2939 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2940 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2941 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2942 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2943 /* skip the flush */
41c445ff
JB		 2944}
2945
5c2cebda
CW		 2946/**
2947 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2948 * @vsi: pointer to a vsi
03147773 2949 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 2950 **/
2951void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2952{
2953 struct i40e_pf *pf = vsi->back;
2954 struct i40e_hw *hw = &pf->hw;
2955 u32 val;
2956
2957 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2958 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2959 i40e_flush(hw);
2960}
2961
41c445ff
JB		 2962/**
2963 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2964 * @irq: interrupt number
2965 * @data: pointer to a q_vector
2966 **/
2967static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2968{
2969 struct i40e_q_vector *q_vector = data;
2970
cd0b6fa6 2971 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2972 return IRQ_HANDLED;
2973
2974 napi_schedule(&q_vector->napi);
2975
2976 return IRQ_HANDLED;
2977}
2978
41c445ff
JB		 2979/**
2980 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2981 * @vsi: the VSI being configured
2982 * @basename: name for the vector
2983 *
2984 * Allocates MSI-X vectors and requests interrupts from the kernel.
2985 **/
2986static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2987{
2988 int q_vectors = vsi->num_q_vectors;
2989 struct i40e_pf *pf = vsi->back;
2990 int base = vsi->base_vector;
2991 int rx_int_idx = 0;
2992 int tx_int_idx = 0;
2993 int vector, err;
2994
2995 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2996 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2997
cd0b6fa6 2998 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2999 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3000 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3001 tx_int_idx++;
cd0b6fa6 3002 } else if (q_vector->rx.ring) {
41c445ff
JB		 3003 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3004 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3005 } else if (q_vector->tx.ring) {
41c445ff
JB		 3006 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3007 "%s-%s-%d", basename, "tx", tx_int_idx++);
3008 } else {
3009 /* skip this unused q_vector */
3010 continue;
3011 }
3012 err = request_irq(pf->msix_entries[base + vector].vector,
3013 vsi->irq_handler,
3014 0,
3015 q_vector->name,
3016 q_vector);
3017 if (err) {
3018 dev_info(&pf->pdev->dev,
3019 "%s: request_irq failed, error: %d\n",
3020 __func__, err);
3021 goto free_queue_irqs;
3022 }
3023 /* assign the mask for this irq */
3024 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3025 &q_vector->affinity_mask);
3026 }
3027
63741846 3028 vsi->irqs_ready = true;
41c445ff
JB		 3029 return 0;
3030
3031free_queue_irqs:
3032 while (vector) {
3033 vector--;
3034 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3035 NULL);
3036 free_irq(pf->msix_entries[base + vector].vector,
3037 &(vsi->q_vectors[vector]));
3038 }
3039 return err;
3040}
3041
3042/**
3043 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3044 * @vsi: the VSI being un-configured
3045 **/
3046static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3047{
3048 struct i40e_pf *pf = vsi->back;
3049 struct i40e_hw *hw = &pf->hw;
3050 int base = vsi->base_vector;
3051 int i;
3052
3053 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3054 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3055 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3056 }
3057
3058 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3059 for (i = vsi->base_vector;
3060 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3061 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3062
3063 i40e_flush(hw);
3064 for (i = 0; i < vsi->num_q_vectors; i++)
3065 synchronize_irq(pf->msix_entries[i + base].vector);
3066 } else {
3067 /* Legacy and MSI mode - this stops all interrupt handling */
3068 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3069 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3070 i40e_flush(hw);
3071 synchronize_irq(pf->pdev->irq);
3072 }
3073}
3074
3075/**
3076 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3077 * @vsi: the VSI being configured
3078 **/
3079static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3080{
3081 struct i40e_pf *pf = vsi->back;
3082 int i;
3083
3084 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3085 for (i = vsi->base_vector;
3086 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3087 i40e_irq_dynamic_enable(vsi, i);
3088 } else {
3089 i40e_irq_dynamic_enable_icr0(pf);
3090 }
3091
1022cb6c 3092 i40e_flush(&pf->hw);
41c445ff
JB		 3093 return 0;
3094}
3095
3096/**
3097 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3098 * @pf: board private structure
3099 **/
3100static void i40e_stop_misc_vector(struct i40e_pf *pf)
3101{
3102 /* Disable ICR 0 */
3103 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3104 i40e_flush(&pf->hw);
3105}
3106
3107/**
3108 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3109 * @irq: interrupt number
3110 * @data: pointer to a q_vector
3111 *
3112 * This is the handler used for all MSI/Legacy interrupts, and deals
3113 * with both queue and non-queue interrupts. This is also used in
3114 * MSIX mode to handle the non-queue interrupts.
3115 **/
3116static irqreturn_t i40e_intr(int irq, void *data)
3117{
3118 struct i40e_pf *pf = (struct i40e_pf *)data;
3119 struct i40e_hw *hw = &pf->hw;
5e823066 3120 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3121 u32 icr0, icr0_remaining;
3122 u32 val, ena_mask;
3123
3124 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3125 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3126
116a57d4
SN		 3127 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3128 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3129 goto enable_intr;
41c445ff 3130
cd92e72f
SN		 3131 /* if interrupt but no bits showing, must be SWINT */
3132 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3133 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3134 pf->sw_int_count++;
3135
41c445ff
JB		 3136 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3137 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3138
3139 /* temporarily disable queue cause for NAPI processing */
3140 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3141 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3142 wr32(hw, I40E_QINT_RQCTL(0), qval);
3143
3144 qval = rd32(hw, I40E_QINT_TQCTL(0));
3145 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3146 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3147
3148 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3149 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3150 }
3151
3152 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3153 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3154 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3155 }
3156
3157 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3158 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3159 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3160 }
3161
3162 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3163 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3164 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3165 }
3166
3167 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3168 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3169 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3170 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3171 val = rd32(hw, I40E_GLGEN_RSTAT);
3172 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3173 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3174 if (val == I40E_RESET_CORER) {
41c445ff 3175 pf->corer_count++;
4eb3f768 3176 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3177 pf->globr_count++;
4eb3f768 3178 } else if (val == I40E_RESET_EMPR) {
41c445ff 3179 pf->empr_count++;
9df42d1a 3180 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3181 }
41c445ff
JB		 3182 }
3183
9c010ee0
ASJ		 3184 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3185 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3186 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3187 }
3188
beb0dff1
JK		 3189 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3190 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3191
3192 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3193 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3194 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3195 }
beb0dff1
JK		 3196 }
3197
41c445ff
JB		 3198 /* If a critical error is pending we have no choice but to reset the
3199 * device.
3200 * Report and mask out any remaining unexpected interrupts.
3201 */
3202 icr0_remaining = icr0 & ena_mask;
3203 if (icr0_remaining) {
3204 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3205 icr0_remaining);
9c010ee0 3206 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3207 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3208 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3209 dev_info(&pf->pdev->dev, "device will be reset\n");
3210 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3211 i40e_service_event_schedule(pf);
41c445ff
JB		 3212 }
3213 ena_mask &= ~icr0_remaining;
3214 }
5e823066 3215 ret = IRQ_HANDLED;
41c445ff 3216
5e823066 3217enable_intr:
41c445ff
JB		 3218 /* re-enable interrupt causes */
3219 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3220 if (!test_bit(__I40E_DOWN, &pf->state)) {
3221 i40e_service_event_schedule(pf);
3222 i40e_irq_dynamic_enable_icr0(pf);
3223 }
3224
5e823066 3225 return ret;
41c445ff
JB		 3226}
3227
cbf61325
ASJ		 3228/**
3229 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3230 * @tx_ring: tx ring to clean
3231 * @budget: how many cleans we're allowed
3232 *
3233 * Returns true if there's any budget left (e.g. the clean is finished)
3234 **/
3235static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3236{
3237 struct i40e_vsi *vsi = tx_ring->vsi;
3238 u16 i = tx_ring->next_to_clean;
3239 struct i40e_tx_buffer *tx_buf;
3240 struct i40e_tx_desc *tx_desc;
3241
3242 tx_buf = &tx_ring->tx_bi[i];
3243 tx_desc = I40E_TX_DESC(tx_ring, i);
3244 i -= tx_ring->count;
3245
3246 do {
3247 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3248
3249 /* if next_to_watch is not set then there is no work pending */
3250 if (!eop_desc)
3251 break;
3252
3253 /* prevent any other reads prior to eop_desc */
3254 read_barrier_depends();
3255
3256 /* if the descriptor isn't done, no work yet to do */
3257 if (!(eop_desc->cmd_type_offset_bsz &
3258 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3259 break;
3260
3261 /* clear next_to_watch to prevent false hangs */
3262 tx_buf->next_to_watch = NULL;
3263
49d7d933
ASJ		 3264 tx_desc->buffer_addr = 0;
3265 tx_desc->cmd_type_offset_bsz = 0;
3266 /* move past filter desc */
3267 tx_buf++;
3268 tx_desc++;
3269 i++;
3270 if (unlikely(!i)) {
3271 i -= tx_ring->count;
3272 tx_buf = tx_ring->tx_bi;
3273 tx_desc = I40E_TX_DESC(tx_ring, 0);
3274 }
cbf61325
ASJ		 3275 /* unmap skb header data */
3276 dma_unmap_single(tx_ring->dev,
3277 dma_unmap_addr(tx_buf, dma),
3278 dma_unmap_len(tx_buf, len),
3279 DMA_TO_DEVICE);
49d7d933
ASJ		 3280 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3281 kfree(tx_buf->raw_buf);
cbf61325 3282
49d7d933
ASJ		 3283 tx_buf->raw_buf = NULL;
3284 tx_buf->tx_flags = 0;
3285 tx_buf->next_to_watch = NULL;
cbf61325 3286 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3287 tx_desc->buffer_addr = 0;
3288 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3289
49d7d933 3290 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3291 tx_buf++;
3292 tx_desc++;
3293 i++;
3294 if (unlikely(!i)) {
3295 i -= tx_ring->count;
3296 tx_buf = tx_ring->tx_bi;
3297 tx_desc = I40E_TX_DESC(tx_ring, 0);
3298 }
3299
3300 /* update budget accounting */
3301 budget--;
3302 } while (likely(budget));
3303
3304 i += tx_ring->count;
3305 tx_ring->next_to_clean = i;
3306
3307 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3308 i40e_irq_dynamic_enable(vsi,
3309 tx_ring->q_vector->v_idx + vsi->base_vector);
3310 }
3311 return budget > 0;
3312}
3313
3314/**
3315 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3316 * @irq: interrupt number
3317 * @data: pointer to a q_vector
3318 **/
3319static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3320{
3321 struct i40e_q_vector *q_vector = data;
3322 struct i40e_vsi *vsi;
3323
3324 if (!q_vector->tx.ring)
3325 return IRQ_HANDLED;
3326
3327 vsi = q_vector->tx.ring->vsi;
3328 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3329
3330 return IRQ_HANDLED;
3331}
3332
41c445ff 3333/**
cd0b6fa6 3334 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3335 * @vsi: the VSI being configured
3336 * @v_idx: vector index
cd0b6fa6 3337 * @qp_idx: queue pair index
41c445ff 3338 **/
cd0b6fa6 3339static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3340{
493fb300 3341 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3342 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3343 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3344
3345 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3346 tx_ring->next = q_vector->tx.ring;
3347 q_vector->tx.ring = tx_ring;
41c445ff 3348 q_vector->tx.count++;
cd0b6fa6
AD		 3349
3350 rx_ring->q_vector = q_vector;
3351 rx_ring->next = q_vector->rx.ring;
3352 q_vector->rx.ring = rx_ring;
3353 q_vector->rx.count++;
41c445ff
JB		 3354}
3355
3356/**
3357 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3358 * @vsi: the VSI being configured
3359 *
3360 * This function maps descriptor rings to the queue-specific vectors
3361 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3362 * one vector per queue pair, but on a constrained vector budget, we
3363 * group the queue pairs as "efficiently" as possible.
3364 **/
3365static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3366{
3367 int qp_remaining = vsi->num_queue_pairs;
3368 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3369 int num_ringpairs;
41c445ff
JB		 3370 int v_start = 0;
3371 int qp_idx = 0;
3372
3373 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3374 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3375 * It is also important to go through all the vectors available to be
3376 * sure that if we don't use all the vectors, that the remaining vectors
3377 * are cleared. This is especially important when decreasing the
3378 * number of queues in use.
41c445ff 3379 */
70114ec4 3380 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3381 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3382
3383 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3384
3385 q_vector->num_ringpairs = num_ringpairs;
3386
3387 q_vector->rx.count = 0;
3388 q_vector->tx.count = 0;
3389 q_vector->rx.ring = NULL;
3390 q_vector->tx.ring = NULL;
3391
3392 while (num_ringpairs--) {
3393 map_vector_to_qp(vsi, v_start, qp_idx);
3394 qp_idx++;
3395 qp_remaining--;
41c445ff
JB		 3396 }
3397 }
3398}
3399
3400/**
3401 * i40e_vsi_request_irq - Request IRQ from the OS
3402 * @vsi: the VSI being configured
3403 * @basename: name for the vector
3404 **/
3405static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3406{
3407 struct i40e_pf *pf = vsi->back;
3408 int err;
3409
3410 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3411 err = i40e_vsi_request_irq_msix(vsi, basename);
3412 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3413 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3414 pf->int_name, pf);
41c445ff
JB		 3415 else
3416 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3417 pf->int_name, pf);
41c445ff
JB		 3418
3419 if (err)
3420 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3421
3422 return err;
3423}
3424
3425#ifdef CONFIG_NET_POLL_CONTROLLER
3426/**
3427 * i40e_netpoll - A Polling 'interrupt'handler
3428 * @netdev: network interface device structure
3429 *
3430 * This is used by netconsole to send skbs without having to re-enable
3431 * interrupts. It's not called while the normal interrupt routine is executing.
3432 **/
38e00438
VD		 3433#ifdef I40E_FCOE
3434void i40e_netpoll(struct net_device *netdev)
3435#else
41c445ff 3436static void i40e_netpoll(struct net_device *netdev)
38e00438 3437#endif
41c445ff
JB		 3438{
3439 struct i40e_netdev_priv *np = netdev_priv(netdev);
3440 struct i40e_vsi *vsi = np->vsi;
3441 struct i40e_pf *pf = vsi->back;
3442 int i;
3443
3444 /* if interface is down do nothing */
3445 if (test_bit(__I40E_DOWN, &vsi->state))
3446 return;
3447
3448 pf->flags |= I40E_FLAG_IN_NETPOLL;
3449 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3450 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3451 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3452 } else {
3453 i40e_intr(pf->pdev->irq, netdev);
3454 }
3455 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3456}
3457#endif
3458
23527308
NP		 3459/**
3460 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3461 * @pf: the PF being configured
3462 * @pf_q: the PF queue
3463 * @enable: enable or disable state of the queue
3464 *
3465 * This routine will wait for the given Tx queue of the PF to reach the
3466 * enabled or disabled state.
3467 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3468 * multiple retries; else will return 0 in case of success.
3469 **/
3470static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3471{
3472 int i;
3473 u32 tx_reg;
3474
3475 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3476 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3477 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3478 break;
3479
f98a2006 3480 usleep_range(10, 20);
23527308
NP		 3481 }
3482 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3483 return -ETIMEDOUT;
3484
3485 return 0;
3486}
3487
41c445ff
JB		 3488/**
3489 * i40e_vsi_control_tx - Start or stop a VSI's rings
3490 * @vsi: the VSI being configured
3491 * @enable: start or stop the rings
3492 **/
3493static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3494{
3495 struct i40e_pf *pf = vsi->back;
3496 struct i40e_hw *hw = &pf->hw;
23527308 3497 int i, j, pf_q, ret = 0;
41c445ff
JB		 3498 u32 tx_reg;
3499
3500 pf_q = vsi->base_queue;
3501 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3502
3503 /* warn the TX unit of coming changes */
3504 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3505 if (!enable)
f98a2006 3506 usleep_range(10, 20);
351499ab 3507
6c5ef620 3508 for (j = 0; j < 50; j++) {
41c445ff 3509 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3510 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3511 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3512 break;
3513 usleep_range(1000, 2000);
3514 }
fda972f6 3515 /* Skip if the queue is already in the requested state */
7c122007 3516 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3517 continue;
41c445ff
JB		 3518
3519 /* turn on/off the queue */
c5c9eb9e
SN		 3520 if (enable) {
3521 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3522 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3523 } else {
41c445ff 3524 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3525 }
41c445ff
JB		 3526
3527 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3528 /* No waiting for the Tx queue to disable */
3529 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3530 continue;
41c445ff
JB		 3531
3532 /* wait for the change to finish */
23527308
NP		 3533 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3534 if (ret) {
3535 dev_info(&pf->pdev->dev,
3536 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3537 __func__, vsi->seid, pf_q,
3538 (enable ? "en" : "dis"));
3539 break;
41c445ff
JB		 3540 }
3541 }
3542
7134f9ce
JB		 3543 if (hw->revision_id == 0)
3544 mdelay(50);
23527308
NP		 3545 return ret;
3546}
3547
3548/**
3549 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3550 * @pf: the PF being configured
3551 * @pf_q: the PF queue
3552 * @enable: enable or disable state of the queue
3553 *
3554 * This routine will wait for the given Rx queue of the PF to reach the
3555 * enabled or disabled state.
3556 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3557 * multiple retries; else will return 0 in case of success.
3558 **/
3559static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3560{
3561 int i;
3562 u32 rx_reg;
3563
3564 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3565 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3566 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3567 break;
3568
f98a2006 3569 usleep_range(10, 20);
23527308
NP		 3570 }
3571 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3572 return -ETIMEDOUT;
7134f9ce 3573
41c445ff
JB		 3574 return 0;
3575}
3576
3577/**
3578 * i40e_vsi_control_rx - Start or stop a VSI's rings
3579 * @vsi: the VSI being configured
3580 * @enable: start or stop the rings
3581 **/
3582static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3583{
3584 struct i40e_pf *pf = vsi->back;
3585 struct i40e_hw *hw = &pf->hw;
23527308 3586 int i, j, pf_q, ret = 0;
41c445ff
JB		 3587 u32 rx_reg;
3588
3589 pf_q = vsi->base_queue;
3590 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3591 for (j = 0; j < 50; j++) {
41c445ff 3592 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3593 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3594 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3595 break;
3596 usleep_range(1000, 2000);
3597 }
41c445ff 3598
7c122007
CS		 3599 /* Skip if the queue is already in the requested state */
3600 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3601 continue;
41c445ff
JB		 3602
3603 /* turn on/off the queue */
3604 if (enable)
6c5ef620 3605 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3606 else
6c5ef620 3607 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3608 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3609
3610 /* wait for the change to finish */
23527308
NP		 3611 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3612 if (ret) {
3613 dev_info(&pf->pdev->dev,
3614 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3615 __func__, vsi->seid, pf_q,
3616 (enable ? "en" : "dis"));
3617 break;
41c445ff
JB		 3618 }
3619 }
3620
23527308 3621 return ret;
41c445ff
JB		 3622}
3623
3624/**
3625 * i40e_vsi_control_rings - Start or stop a VSI's rings
3626 * @vsi: the VSI being configured
3627 * @enable: start or stop the rings
3628 **/
fc18eaa0 3629int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3630{
3b867b28 3631 int ret = 0;
41c445ff
JB		 3632
3633 /* do rx first for enable and last for disable */
3634 if (request) {
3635 ret = i40e_vsi_control_rx(vsi, request);
3636 if (ret)
3637 return ret;
3638 ret = i40e_vsi_control_tx(vsi, request);
3639 } else {
3b867b28
ASJ		 3640 /* Ignore return value, we need to shutdown whatever we can */
3641 i40e_vsi_control_tx(vsi, request);
3642 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3643 }
3644
3645 return ret;
3646}
3647
3648/**
3649 * i40e_vsi_free_irq - Free the irq association with the OS
3650 * @vsi: the VSI being configured
3651 **/
3652static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3653{
3654 struct i40e_pf *pf = vsi->back;
3655 struct i40e_hw *hw = &pf->hw;
3656 int base = vsi->base_vector;
3657 u32 val, qp;
3658 int i;
3659
3660 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3661 if (!vsi->q_vectors)
3662 return;
3663
63741846
SN		 3664 if (!vsi->irqs_ready)
3665 return;
3666
3667 vsi->irqs_ready = false;
41c445ff
JB		 3668 for (i = 0; i < vsi->num_q_vectors; i++) {
3669 u16 vector = i + base;
3670
3671 /* free only the irqs that were actually requested */
78681b1f
SN		 3672 if (!vsi->q_vectors[i] ||
3673 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3674 continue;
3675
3676 /* clear the affinity_mask in the IRQ descriptor */
3677 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3678 NULL);
3679 free_irq(pf->msix_entries[vector].vector,
493fb300 3680 vsi->q_vectors[i]);
41c445ff
JB		 3681
3682 /* Tear down the interrupt queue link list
3683 *
3684 * We know that they come in pairs and always
3685 * the Rx first, then the Tx. To clear the
3686 * link list, stick the EOL value into the
3687 * next_q field of the registers.
3688 */
3689 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3690 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3691 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3692 val |= I40E_QUEUE_END_OF_LIST
3693 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3694 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3695
3696 while (qp != I40E_QUEUE_END_OF_LIST) {
3697 u32 next;
3698
3699 val = rd32(hw, I40E_QINT_RQCTL(qp));
3700
3701 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3702 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3703 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3704 I40E_QINT_RQCTL_INTEVENT_MASK);
3705
3706 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3707 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3708
3709 wr32(hw, I40E_QINT_RQCTL(qp), val);
3710
3711 val = rd32(hw, I40E_QINT_TQCTL(qp));
3712
3713 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3714 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3715
3716 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3717 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3718 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3719 I40E_QINT_TQCTL_INTEVENT_MASK);
3720
3721 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3722 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3723
3724 wr32(hw, I40E_QINT_TQCTL(qp), val);
3725 qp = next;
3726 }
3727 }
3728 } else {
3729 free_irq(pf->pdev->irq, pf);
3730
3731 val = rd32(hw, I40E_PFINT_LNKLST0);
3732 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3733 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3734 val |= I40E_QUEUE_END_OF_LIST
3735 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3736 wr32(hw, I40E_PFINT_LNKLST0, val);
3737
3738 val = rd32(hw, I40E_QINT_RQCTL(qp));
3739 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3740 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3741 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3742 I40E_QINT_RQCTL_INTEVENT_MASK);
3743
3744 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3745 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3746
3747 wr32(hw, I40E_QINT_RQCTL(qp), val);
3748
3749 val = rd32(hw, I40E_QINT_TQCTL(qp));
3750
3751 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3752 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3753 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3754 I40E_QINT_TQCTL_INTEVENT_MASK);
3755
3756 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3757 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3758
3759 wr32(hw, I40E_QINT_TQCTL(qp), val);
3760 }
3761}
3762
493fb300
AD		 3763/**
3764 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3765 * @vsi: the VSI being configured
3766 * @v_idx: Index of vector to be freed
3767 *
3768 * This function frees the memory allocated to the q_vector. In addition if
3769 * NAPI is enabled it will delete any references to the NAPI struct prior
3770 * to freeing the q_vector.
3771 **/
3772static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3773{
3774 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3775 struct i40e_ring *ring;
493fb300
AD		 3776
3777 if (!q_vector)
3778 return;
3779
3780 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3781 i40e_for_each_ring(ring, q_vector->tx)
3782 ring->q_vector = NULL;
3783
3784 i40e_for_each_ring(ring, q_vector->rx)
3785 ring->q_vector = NULL;
493fb300
AD		 3786
3787 /* only VSI w/ an associated netdev is set up w/ NAPI */
3788 if (vsi->netdev)
3789 netif_napi_del(&q_vector->napi);
3790
3791 vsi->q_vectors[v_idx] = NULL;
3792
3793 kfree_rcu(q_vector, rcu);
3794}
3795
41c445ff
JB		 3796/**
3797 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3798 * @vsi: the VSI being un-configured
3799 *
3800 * This frees the memory allocated to the q_vectors and
3801 * deletes references to the NAPI struct.
3802 **/
3803static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3804{
3805 int v_idx;
3806
493fb300
AD		 3807 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3808 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3809}
3810
3811/**
3812 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3813 * @pf: board private structure
3814 **/
3815static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3816{
3817 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3818 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3819 pci_disable_msix(pf->pdev);
3820 kfree(pf->msix_entries);
3821 pf->msix_entries = NULL;
3822 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3823 pci_disable_msi(pf->pdev);
3824 }
3825 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3826}
3827
3828/**
3829 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3830 * @pf: board private structure
3831 *
3832 * We go through and clear interrupt specific resources and reset the structure
3833 * to pre-load conditions
3834 **/
3835static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3836{
3837 int i;
3838
3839 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3840 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3841 if (pf->vsi[i])
3842 i40e_vsi_free_q_vectors(pf->vsi[i]);
3843 i40e_reset_interrupt_capability(pf);
3844}
3845
3846/**
3847 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3848 * @vsi: the VSI being configured
3849 **/
3850static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3851{
3852 int q_idx;
3853
3854 if (!vsi->netdev)
3855 return;
3856
3857 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3858 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3859}
3860
3861/**
3862 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3863 * @vsi: the VSI being configured
3864 **/
3865static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3866{
3867 int q_idx;
3868
3869 if (!vsi->netdev)
3870 return;
3871
3872 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3873 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3874}
3875
90ef8d47
SN		 3876/**
3877 * i40e_vsi_close - Shut down a VSI
3878 * @vsi: the vsi to be quelled
3879 **/
3880static void i40e_vsi_close(struct i40e_vsi *vsi)
3881{
3882 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3883 i40e_down(vsi);
3884 i40e_vsi_free_irq(vsi);
3885 i40e_vsi_free_tx_resources(vsi);
3886 i40e_vsi_free_rx_resources(vsi);
3887}
3888
41c445ff
JB		 3889/**
3890 * i40e_quiesce_vsi - Pause a given VSI
3891 * @vsi: the VSI being paused
3892 **/
3893static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3894{
3895 if (test_bit(__I40E_DOWN, &vsi->state))
3896 return;
3897
d341b7a5
NP		 3898 /* No need to disable FCoE VSI when Tx suspended */
3899 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
3900 vsi->type == I40E_VSI_FCOE) {
3901 dev_dbg(&vsi->back->pdev->dev,
3902 "%s: VSI seid %d skipping FCoE VSI disable\n",
3903 __func__, vsi->seid);
3904 return;
3905 }
3906
41c445ff
JB		 3907 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3908 if (vsi->netdev && netif_running(vsi->netdev)) {
3909 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3910 } else {
90ef8d47 3911 i40e_vsi_close(vsi);
41c445ff
JB		 3912 }
3913}
3914
3915/**
3916 * i40e_unquiesce_vsi - Resume a given VSI
3917 * @vsi: the VSI being resumed
3918 **/
3919static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3920{
3921 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3922 return;
3923
3924 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3925 if (vsi->netdev && netif_running(vsi->netdev))
3926 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3927 else
8276f757 3928 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3929}
3930
3931/**
3932 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3933 * @pf: the PF
3934 **/
3935static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3936{
3937 int v;
3938
505682cd 3939 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3940 if (pf->vsi[v])
3941 i40e_quiesce_vsi(pf->vsi[v]);
3942 }
3943}
3944
3945/**
3946 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3947 * @pf: the PF
3948 **/
3949static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3950{
3951 int v;
3952
505682cd 3953 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3954 if (pf->vsi[v])
3955 i40e_unquiesce_vsi(pf->vsi[v]);
3956 }
3957}
3958
69129dc3
NP		 3959#ifdef CONFIG_I40E_DCB
3960/**
3961 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
3962 * @vsi: the VSI being configured
3963 *
3964 * This function waits for the given VSI's Tx queues to be disabled.
3965 **/
3966static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
3967{
3968 struct i40e_pf *pf = vsi->back;
3969 int i, pf_q, ret;
3970
3971 pf_q = vsi->base_queue;
3972 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3973 /* Check and wait for the disable status of the queue */
3974 ret = i40e_pf_txq_wait(pf, pf_q, false);
3975 if (ret) {
3976 dev_info(&pf->pdev->dev,
3977 "%s: VSI seid %d Tx ring %d disable timeout\n",
3978 __func__, vsi->seid, pf_q);
3979 return ret;
3980 }
3981 }
3982
3983 return 0;
3984}
3985
3986/**
3987 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
3988 * @pf: the PF
3989 *
3990 * This function waits for the Tx queues to be in disabled state for all the
3991 * VSIs that are managed by this PF.
3992 **/
3993static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
3994{
3995 int v, ret = 0;
3996
3997 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 3998 /* No need to wait for FCoE VSI queues */
3999 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4000 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4001 if (ret)
4002 break;
4003 }
4004 }
4005
4006 return ret;
4007}
4008
4009#endif
63d7e5a4
NP		 4010/**
4011 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
4012 * @pf: pointer to pf
4013 *
4014 * Get TC map for ISCSI PF type that will include iSCSI TC
4015 * and LAN TC.
4016 **/
4017static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4018{
4019 struct i40e_dcb_app_priority_table app;
4020 struct i40e_hw *hw = &pf->hw;
4021 u8 enabled_tc = 1; /* TC0 is always enabled */
4022 u8 tc, i;
4023 /* Get the iSCSI APP TLV */
4024 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4025
4026 for (i = 0; i < dcbcfg->numapps; i++) {
4027 app = dcbcfg->app[i];
4028 if (app.selector == I40E_APP_SEL_TCPIP &&
4029 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4030 tc = dcbcfg->etscfg.prioritytable[app.priority];
4031 enabled_tc |= (1 << tc);
4032 break;
4033 }
4034 }
4035
4036 return enabled_tc;
4037}
4038
41c445ff
JB		 4039/**
4040 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4041 * @dcbcfg: the corresponding DCBx configuration structure
4042 *
4043 * Return the number of TCs from given DCBx configuration
4044 **/
4045static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4046{
078b5876
JB		 4047 u8 num_tc = 0;
4048 int i;
41c445ff
JB		 4049
4050 /* Scan the ETS Config Priority Table to find
4051 * traffic class enabled for a given priority
4052 * and use the traffic class index to get the
4053 * number of traffic classes enabled
4054 */
4055 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4056 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4057 num_tc = dcbcfg->etscfg.prioritytable[i];
4058 }
4059
4060 /* Traffic class index starts from zero so
4061 * increment to return the actual count
4062 */
078b5876 4063 return num_tc + 1;
41c445ff
JB		 4064}
4065
4066/**
4067 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4068 * @dcbcfg: the corresponding DCBx configuration structure
4069 *
4070 * Query the current DCB configuration and return the number of
4071 * traffic classes enabled from the given DCBX config
4072 **/
4073static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4074{
4075 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4076 u8 enabled_tc = 1;
4077 u8 i;
4078
4079 for (i = 0; i < num_tc; i++)
4080 enabled_tc |= 1 << i;
4081
4082 return enabled_tc;
4083}
4084
4085/**
4086 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4087 * @pf: PF being queried
4088 *
4089 * Return number of traffic classes enabled for the given PF
4090 **/
4091static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4092{
4093 struct i40e_hw *hw = &pf->hw;
4094 u8 i, enabled_tc;
4095 u8 num_tc = 0;
4096 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4097
4098 /* If DCB is not enabled then always in single TC */
4099 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4100 return 1;
4101
63d7e5a4
NP		 4102 /* SFP mode will be enabled for all TCs on port */
4103 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4104 return i40e_dcb_get_num_tc(dcbcfg);
4105
41c445ff 4106 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4107 if (pf->hw.func_caps.iscsi)
4108 enabled_tc = i40e_get_iscsi_tc_map(pf);
4109 else
41c445ff 4110 enabled_tc = pf->hw.func_caps.enabled_tcmap;
41c445ff 4111
63d7e5a4
NP		 4112 /* At least have TC0 */
4113 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4114 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4115 if (enabled_tc & (1 << i))
4116 num_tc++;
4117 }
4118 return num_tc;
41c445ff
JB		 4119}
4120
4121/**
4122 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4123 * @pf: PF being queried
4124 *
4125 * Return a bitmap for first enabled traffic class for this PF.
4126 **/
4127static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4128{
4129 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4130 u8 i = 0;
4131
4132 if (!enabled_tc)
4133 return 0x1; /* TC0 */
4134
4135 /* Find the first enabled TC */
4136 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4137 if (enabled_tc & (1 << i))
4138 break;
4139 }
4140
4141 return 1 << i;
4142}
4143
4144/**
4145 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4146 * @pf: PF being queried
4147 *
4148 * Return a bitmap for enabled traffic classes for this PF.
4149 **/
4150static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4151{
4152 /* If DCB is not enabled for this PF then just return default TC */
4153 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4154 return i40e_pf_get_default_tc(pf);
4155
41c445ff 4156 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4157 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4158 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4159
4160 /* MPF enabled and iSCSI PF type */
4161 if (pf->hw.func_caps.iscsi)
4162 return i40e_get_iscsi_tc_map(pf);
4163 else
4164 return pf->hw.func_caps.enabled_tcmap;
41c445ff
JB		 4165}
4166
4167/**
4168 * i40e_vsi_get_bw_info - Query VSI BW Information
4169 * @vsi: the VSI being queried
4170 *
4171 * Returns 0 on success, negative value on failure
4172 **/
4173static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4174{
4175 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4176 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4177 struct i40e_pf *pf = vsi->back;
4178 struct i40e_hw *hw = &pf->hw;
dcae29be 4179 i40e_status aq_ret;
41c445ff 4180 u32 tc_bw_max;
41c445ff
JB		 4181 int i;
4182
4183 /* Get the VSI level BW configuration */
dcae29be
JB		 4184 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4185 if (aq_ret) {
41c445ff
JB		 4186 dev_info(&pf->pdev->dev,
4187 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4188 aq_ret, pf->hw.aq.asq_last_status);
4189 return -EINVAL;
41c445ff
JB		 4190 }
4191
4192 /* Get the VSI level BW configuration per TC */
dcae29be 4193 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4194 NULL);
dcae29be 4195 if (aq_ret) {
41c445ff
JB		 4196 dev_info(&pf->pdev->dev,
4197 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4198 aq_ret, pf->hw.aq.asq_last_status);
4199 return -EINVAL;
41c445ff
JB		 4200 }
4201
4202 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4203 dev_info(&pf->pdev->dev,
4204 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4205 bw_config.tc_valid_bits,
4206 bw_ets_config.tc_valid_bits);
4207 /* Still continuing */
4208 }
4209
4210 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4211 vsi->bw_max_quanta = bw_config.max_bw;
4212 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4213 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4214 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4215 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4216 vsi->bw_ets_limit_credits[i] =
4217 le16_to_cpu(bw_ets_config.credits[i]);
4218 /* 3 bits out of 4 for each TC */
4219 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4220 }
078b5876 4221
dcae29be 4222 return 0;
41c445ff
JB		 4223}
4224
4225/**
4226 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4227 * @vsi: the VSI being configured
4228 * @enabled_tc: TC bitmap
4229 * @bw_credits: BW shared credits per TC
4230 *
4231 * Returns 0 on success, negative value on failure
4232 **/
dcae29be 4233static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4234 u8 *bw_share)
4235{
4236 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4237 i40e_status aq_ret;
4238 int i;
41c445ff
JB		 4239
4240 bw_data.tc_valid_bits = enabled_tc;
4241 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4242 bw_data.tc_bw_credits[i] = bw_share[i];
4243
dcae29be
JB		 4244 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4245 NULL);
4246 if (aq_ret) {
41c445ff 4247 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4248 "AQ command Config VSI BW allocation per TC failed = %d\n",
4249 vsi->back->hw.aq.asq_last_status);
dcae29be 4250 return -EINVAL;
41c445ff
JB		 4251 }
4252
4253 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4254 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4255
dcae29be 4256 return 0;
41c445ff
JB		 4257}
4258
4259/**
4260 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4261 * @vsi: the VSI being configured
4262 * @enabled_tc: TC map to be enabled
4263 *
4264 **/
4265static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4266{
4267 struct net_device *netdev = vsi->netdev;
4268 struct i40e_pf *pf = vsi->back;
4269 struct i40e_hw *hw = &pf->hw;
4270 u8 netdev_tc = 0;
4271 int i;
4272 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4273
4274 if (!netdev)
4275 return;
4276
4277 if (!enabled_tc) {
4278 netdev_reset_tc(netdev);
4279 return;
4280 }
4281
4282 /* Set up actual enabled TCs on the VSI */
4283 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4284 return;
4285
4286 /* set per TC queues for the VSI */
4287 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4288 /* Only set TC queues for enabled tcs
4289 *
4290 * e.g. For a VSI that has TC0 and TC3 enabled the
4291 * enabled_tc bitmap would be 0x00001001; the driver
4292 * will set the numtc for netdev as 2 that will be
4293 * referenced by the netdev layer as TC 0 and 1.
4294 */
4295 if (vsi->tc_config.enabled_tc & (1 << i))
4296 netdev_set_tc_queue(netdev,
4297 vsi->tc_config.tc_info[i].netdev_tc,
4298 vsi->tc_config.tc_info[i].qcount,
4299 vsi->tc_config.tc_info[i].qoffset);
4300 }
4301
4302 /* Assign UP2TC map for the VSI */
4303 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4304 /* Get the actual TC# for the UP */
4305 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4306 /* Get the mapped netdev TC# for the UP */
4307 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4308 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4309 }
4310}
4311
4312/**
4313 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4314 * @vsi: the VSI being configured
4315 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4316 **/
4317static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4318 struct i40e_vsi_context *ctxt)
4319{
4320 /* copy just the sections touched not the entire info
4321 * since not all sections are valid as returned by
4322 * update vsi params
4323 */
4324 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4325 memcpy(&vsi->info.queue_mapping,
4326 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4327 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4328 sizeof(vsi->info.tc_mapping));
4329}
4330
4331/**
4332 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4333 * @vsi: VSI to be configured
4334 * @enabled_tc: TC bitmap
4335 *
4336 * This configures a particular VSI for TCs that are mapped to the
4337 * given TC bitmap. It uses default bandwidth share for TCs across
4338 * VSIs to configure TC for a particular VSI.
4339 *
4340 * NOTE:
4341 * It is expected that the VSI queues have been quisced before calling
4342 * this function.
4343 **/
4344static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4345{
4346 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4347 struct i40e_vsi_context ctxt;
4348 int ret = 0;
4349 int i;
4350
4351 /* Check if enabled_tc is same as existing or new TCs */
4352 if (vsi->tc_config.enabled_tc == enabled_tc)
4353 return ret;
4354
4355 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4356 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4357 if (enabled_tc & (1 << i))
4358 bw_share[i] = 1;
4359 }
4360
4361 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4362 if (ret) {
4363 dev_info(&vsi->back->pdev->dev,
4364 "Failed configuring TC map %d for VSI %d\n",
4365 enabled_tc, vsi->seid);
4366 goto out;
4367 }
4368
4369 /* Update Queue Pairs Mapping for currently enabled UPs */
4370 ctxt.seid = vsi->seid;
4371 ctxt.pf_num = vsi->back->hw.pf_id;
4372 ctxt.vf_num = 0;
4373 ctxt.uplink_seid = vsi->uplink_seid;
4374 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4375 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4376
4377 /* Update the VSI after updating the VSI queue-mapping information */
4378 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4379 if (ret) {
4380 dev_info(&vsi->back->pdev->dev,
4381 "update vsi failed, aq_err=%d\n",
4382 vsi->back->hw.aq.asq_last_status);
4383 goto out;
4384 }
4385 /* update the local VSI info with updated queue map */
4386 i40e_vsi_update_queue_map(vsi, &ctxt);
4387 vsi->info.valid_sections = 0;
4388
4389 /* Update current VSI BW information */
4390 ret = i40e_vsi_get_bw_info(vsi);
4391 if (ret) {
4392 dev_info(&vsi->back->pdev->dev,
4393 "Failed updating vsi bw info, aq_err=%d\n",
4394 vsi->back->hw.aq.asq_last_status);
4395 goto out;
4396 }
4397
4398 /* Update the netdev TC setup */
4399 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4400out:
4401 return ret;
4402}
4403
4e3b35b0
NP		 4404/**
4405 * i40e_veb_config_tc - Configure TCs for given VEB
4406 * @veb: given VEB
4407 * @enabled_tc: TC bitmap
4408 *
4409 * Configures given TC bitmap for VEB (switching) element
4410 **/
4411int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4412{
4413 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4414 struct i40e_pf *pf = veb->pf;
4415 int ret = 0;
4416 int i;
4417
4418 /* No TCs or already enabled TCs just return */
4419 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4420 return ret;
4421
4422 bw_data.tc_valid_bits = enabled_tc;
4423 /* bw_data.absolute_credits is not set (relative) */
4424
4425 /* Enable ETS TCs with equal BW Share for now */
4426 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4427 if (enabled_tc & (1 << i))
4428 bw_data.tc_bw_share_credits[i] = 1;
4429 }
4430
4431 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4432 &bw_data, NULL);
4433 if (ret) {
4434 dev_info(&pf->pdev->dev,
4435 "veb bw config failed, aq_err=%d\n",
4436 pf->hw.aq.asq_last_status);
4437 goto out;
4438 }
4439
4440 /* Update the BW information */
4441 ret = i40e_veb_get_bw_info(veb);
4442 if (ret) {
4443 dev_info(&pf->pdev->dev,
4444 "Failed getting veb bw config, aq_err=%d\n",
4445 pf->hw.aq.asq_last_status);
4446 }
4447
4448out:
4449 return ret;
4450}
4451
4452#ifdef CONFIG_I40E_DCB
4453/**
4454 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4455 * @pf: PF struct
4456 *
4457 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4458 * the caller would've quiesce all the VSIs before calling
4459 * this function
4460 **/
4461static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4462{
4463 u8 tc_map = 0;
4464 int ret;
4465 u8 v;
4466
4467 /* Enable the TCs available on PF to all VEBs */
4468 tc_map = i40e_pf_get_tc_map(pf);
4469 for (v = 0; v < I40E_MAX_VEB; v++) {
4470 if (!pf->veb[v])
4471 continue;
4472 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4473 if (ret) {
4474 dev_info(&pf->pdev->dev,
4475 "Failed configuring TC for VEB seid=%d\n",
4476 pf->veb[v]->seid);
4477 /* Will try to configure as many components */
4478 }
4479 }
4480
4481 /* Update each VSI */
505682cd 4482 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4483 if (!pf->vsi[v])
4484 continue;
4485
4486 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4487#ifdef I40E_FCOE
4488 * - For FCoE VSI only enable the TC configured
4489 * as per the APP TLV
4490#endif
4e3b35b0
NP		 4491 * - For all others keep them at TC0 for now
4492 */
4493 if (v == pf->lan_vsi)
4494 tc_map = i40e_pf_get_tc_map(pf);
4495 else
4496 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4497#ifdef I40E_FCOE
4498 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4499 tc_map = i40e_get_fcoe_tc_map(pf);
4500#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4501
4502 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4503 if (ret) {
4504 dev_info(&pf->pdev->dev,
4505 "Failed configuring TC for VSI seid=%d\n",
4506 pf->vsi[v]->seid);
4507 /* Will try to configure as many components */
4508 } else {
0672a091
NP		 4509 /* Re-configure VSI vectors based on updated TC map */
4510 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4511 if (pf->vsi[v]->netdev)
4512 i40e_dcbnl_set_all(pf->vsi[v]);
4513 }
4514 }
4515}
4516
2fd75f31
NP		 4517/**
4518 * i40e_resume_port_tx - Resume port Tx
4519 * @pf: PF struct
4520 *
4521 * Resume a port's Tx and issue a PF reset in case of failure to
4522 * resume.
4523 **/
4524static int i40e_resume_port_tx(struct i40e_pf *pf)
4525{
4526 struct i40e_hw *hw = &pf->hw;
4527 int ret;
4528
4529 ret = i40e_aq_resume_port_tx(hw, NULL);
4530 if (ret) {
4531 dev_info(&pf->pdev->dev,
4532 "AQ command Resume Port Tx failed = %d\n",
4533 pf->hw.aq.asq_last_status);
4534 /* Schedule PF reset to recover */
4535 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4536 i40e_service_event_schedule(pf);
4537 }
4538
4539 return ret;
4540}
4541
4e3b35b0
NP		 4542/**
4543 * i40e_init_pf_dcb - Initialize DCB configuration
4544 * @pf: PF being configured
4545 *
4546 * Query the current DCB configuration and cache it
4547 * in the hardware structure
4548 **/
4549static int i40e_init_pf_dcb(struct i40e_pf *pf)
4550{
4551 struct i40e_hw *hw = &pf->hw;
4552 int err = 0;
4553
025b4a54
ASJ		 4554 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4555 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4556 (pf->hw.aq.fw_maj_ver < 4))
4557 goto out;
4558
4e3b35b0
NP		 4559 /* Get the initial DCB configuration */
4560 err = i40e_init_dcb(hw);
4561 if (!err) {
4562 /* Device/Function is not DCBX capable */
4563 if ((!hw->func_caps.dcb) ||
4564 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4565 dev_info(&pf->pdev->dev,
4566 "DCBX offload is not supported or is disabled for this PF.\n");
4567
4568 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4569 goto out;
4570
4571 } else {
4572 /* When status is not DISABLED then DCBX in FW */
4573 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4574 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4575
4576 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4577 /* Enable DCB tagging only when more than one TC */
4578 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4579 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4580 dev_dbg(&pf->pdev->dev,
4581 "DCBX offload is supported for this PF.\n");
4e3b35b0 4582 }
014269ff 4583 } else {
aebfc816
SN		 4584 dev_info(&pf->pdev->dev,
4585 "AQ Querying DCB configuration failed: aq_err %d\n",
014269ff 4586 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4587 }
4588
4589out:
4590 return err;
4591}
4592#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4593#define SPEED_SIZE 14
4594#define FC_SIZE 8
4595/**
4596 * i40e_print_link_message - print link up or down
4597 * @vsi: the VSI for which link needs a message
4598 */
4599static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4600{
4601 char speed[SPEED_SIZE] = "Unknown";
4602 char fc[FC_SIZE] = "RX/TX";
4603
4604 if (!isup) {
4605 netdev_info(vsi->netdev, "NIC Link is Down\n");
4606 return;
4607 }
4608
148c2d80
GR		 4609 /* Warn user if link speed on NPAR enabled partition is not at
4610 * least 10GB
4611 */
4612 if (vsi->back->hw.func_caps.npar_enable &&
4613 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4614 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4615 netdev_warn(vsi->netdev,
4616 "The partition detected link speed that is less than 10Gbps\n");
4617
cf05ed08
JB		 4618 switch (vsi->back->hw.phy.link_info.link_speed) {
4619 case I40E_LINK_SPEED_40GB:
35a7d804 4620 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4621 break;
4622 case I40E_LINK_SPEED_10GB:
35a7d804 4623 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4624 break;
4625 case I40E_LINK_SPEED_1GB:
35a7d804 4626 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4627 break;
5960d33f
MW		 4628 case I40E_LINK_SPEED_100MB:
4629 strncpy(speed, "100 Mbps", SPEED_SIZE);
4630 break;
cf05ed08
JB		 4631 default:
4632 break;
4633 }
4634
4635 switch (vsi->back->hw.fc.current_mode) {
4636 case I40E_FC_FULL:
35a7d804 4637 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4638 break;
4639 case I40E_FC_TX_PAUSE:
35a7d804 4640 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4641 break;
4642 case I40E_FC_RX_PAUSE:
35a7d804 4643 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4644 break;
4645 default:
35a7d804 4646 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4647 break;
4648 }
4649
4650 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4651 speed, fc);
4652}
4e3b35b0 4653
41c445ff
JB		 4654/**
4655 * i40e_up_complete - Finish the last steps of bringing up a connection
4656 * @vsi: the VSI being configured
4657 **/
4658static int i40e_up_complete(struct i40e_vsi *vsi)
4659{
4660 struct i40e_pf *pf = vsi->back;
4661 int err;
4662
4663 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4664 i40e_vsi_configure_msix(vsi);
4665 else
4666 i40e_configure_msi_and_legacy(vsi);
4667
4668 /* start rings */
4669 err = i40e_vsi_control_rings(vsi, true);
4670 if (err)
4671 return err;
4672
4673 clear_bit(__I40E_DOWN, &vsi->state);
4674 i40e_napi_enable_all(vsi);
4675 i40e_vsi_enable_irq(vsi);
4676
4677 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4678 (vsi->netdev)) {
cf05ed08 4679 i40e_print_link_message(vsi, true);
41c445ff
JB		 4680 netif_tx_start_all_queues(vsi->netdev);
4681 netif_carrier_on(vsi->netdev);
6d779b41 4682 } else if (vsi->netdev) {
cf05ed08 4683 i40e_print_link_message(vsi, false);
7b592f61
CW		 4684 /* need to check for qualified module here*/
4685 if ((pf->hw.phy.link_info.link_info &
4686 I40E_AQ_MEDIA_AVAILABLE) &&
4687 (!(pf->hw.phy.link_info.an_info &
4688 I40E_AQ_QUALIFIED_MODULE)))
4689 netdev_err(vsi->netdev,
4690 "the driver failed to link because an unqualified module was detected.");
41c445ff 4691 }
ca64fa4e
ASJ		 4692
4693 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4694 if (vsi->type == I40E_VSI_FDIR) {
4695 /* reset fd counters */
4696 pf->fd_add_err = pf->fd_atr_cnt = 0;
4697 if (pf->fd_tcp_rule > 0) {
4698 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4699 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4700 pf->fd_tcp_rule = 0;
4701 }
ca64fa4e 4702 i40e_fdir_filter_restore(vsi);
1e1be8f6 4703 }
41c445ff
JB		 4704 i40e_service_event_schedule(pf);
4705
4706 return 0;
4707}
4708
4709/**
4710 * i40e_vsi_reinit_locked - Reset the VSI
4711 * @vsi: the VSI being configured
4712 *
4713 * Rebuild the ring structs after some configuration
4714 * has changed, e.g. MTU size.
4715 **/
4716static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4717{
4718 struct i40e_pf *pf = vsi->back;
4719
4720 WARN_ON(in_interrupt());
4721 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4722 usleep_range(1000, 2000);
4723 i40e_down(vsi);
4724
4725 /* Give a VF some time to respond to the reset. The
4726 * two second wait is based upon the watchdog cycle in
4727 * the VF driver.
4728 */
4729 if (vsi->type == I40E_VSI_SRIOV)
4730 msleep(2000);
4731 i40e_up(vsi);
4732 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4733}
4734
4735/**
4736 * i40e_up - Bring the connection back up after being down
4737 * @vsi: the VSI being configured
4738 **/
4739int i40e_up(struct i40e_vsi *vsi)
4740{
4741 int err;
4742
4743 err = i40e_vsi_configure(vsi);
4744 if (!err)
4745 err = i40e_up_complete(vsi);
4746
4747 return err;
4748}
4749
4750/**
4751 * i40e_down - Shutdown the connection processing
4752 * @vsi: the VSI being stopped
4753 **/
4754void i40e_down(struct i40e_vsi *vsi)
4755{
4756 int i;
4757
4758 /* It is assumed that the caller of this function
4759 * sets the vsi->state __I40E_DOWN bit.
4760 */
4761 if (vsi->netdev) {
4762 netif_carrier_off(vsi->netdev);
4763 netif_tx_disable(vsi->netdev);
4764 }
4765 i40e_vsi_disable_irq(vsi);
4766 i40e_vsi_control_rings(vsi, false);
4767 i40e_napi_disable_all(vsi);
4768
4769 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4770 i40e_clean_tx_ring(vsi->tx_rings[i]);
4771 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4772 }
4773}
4774
4775/**
4776 * i40e_setup_tc - configure multiple traffic classes
4777 * @netdev: net device to configure
4778 * @tc: number of traffic classes to enable
4779 **/
38e00438
VD		 4780#ifdef I40E_FCOE
4781int i40e_setup_tc(struct net_device *netdev, u8 tc)
4782#else
41c445ff 4783static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4784#endif
41c445ff
JB		 4785{
4786 struct i40e_netdev_priv *np = netdev_priv(netdev);
4787 struct i40e_vsi *vsi = np->vsi;
4788 struct i40e_pf *pf = vsi->back;
4789 u8 enabled_tc = 0;
4790 int ret = -EINVAL;
4791 int i;
4792
4793 /* Check if DCB enabled to continue */
4794 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4795 netdev_info(netdev, "DCB is not enabled for adapter\n");
4796 goto exit;
4797 }
4798
4799 /* Check if MFP enabled */
4800 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4801 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4802 goto exit;
4803 }
4804
4805 /* Check whether tc count is within enabled limit */
4806 if (tc > i40e_pf_get_num_tc(pf)) {
4807 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4808 goto exit;
4809 }
4810
4811 /* Generate TC map for number of tc requested */
4812 for (i = 0; i < tc; i++)
4813 enabled_tc |= (1 << i);
4814
4815 /* Requesting same TC configuration as already enabled */
4816 if (enabled_tc == vsi->tc_config.enabled_tc)
4817 return 0;
4818
4819 /* Quiesce VSI queues */
4820 i40e_quiesce_vsi(vsi);
4821
4822 /* Configure VSI for enabled TCs */
4823 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4824 if (ret) {
4825 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4826 vsi->seid);
4827 goto exit;
4828 }
4829
4830 /* Unquiesce VSI */
4831 i40e_unquiesce_vsi(vsi);
4832
4833exit:
4834 return ret;
4835}
4836
4837/**
4838 * i40e_open - Called when a network interface is made active
4839 * @netdev: network interface device structure
4840 *
4841 * The open entry point is called when a network interface is made
4842 * active by the system (IFF_UP). At this point all resources needed
4843 * for transmit and receive operations are allocated, the interrupt
4844 * handler is registered with the OS, the netdev watchdog subtask is
4845 * enabled, and the stack is notified that the interface is ready.
4846 *
4847 * Returns 0 on success, negative value on failure
4848 **/
38e00438 4849int i40e_open(struct net_device *netdev)
41c445ff
JB		 4850{
4851 struct i40e_netdev_priv *np = netdev_priv(netdev);
4852 struct i40e_vsi *vsi = np->vsi;
4853 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4854 int err;
4855
4eb3f768
SN		 4856 /* disallow open during test or if eeprom is broken */
4857 if (test_bit(__I40E_TESTING, &pf->state) ||
4858 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4859 return -EBUSY;
4860
4861 netif_carrier_off(netdev);
4862
6c167f58
EK		 4863 err = i40e_vsi_open(vsi);
4864 if (err)
4865 return err;
4866
059dab69
JB		 4867 /* configure global TSO hardware offload settings */
4868 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4869 TCP_FLAG_FIN) >> 16);
4870 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4871 TCP_FLAG_FIN |
4872 TCP_FLAG_CWR) >> 16);
4873 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4874
6c167f58
EK		 4875#ifdef CONFIG_I40E_VXLAN
4876 vxlan_get_rx_port(netdev);
4877#endif
4878
4879 return 0;
4880}
4881
4882/**
4883 * i40e_vsi_open -
4884 * @vsi: the VSI to open
4885 *
4886 * Finish initialization of the VSI.
4887 *
4888 * Returns 0 on success, negative value on failure
4889 **/
4890int i40e_vsi_open(struct i40e_vsi *vsi)
4891{
4892 struct i40e_pf *pf = vsi->back;
b294ac70 4893 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 4894 int err;
4895
41c445ff
JB		 4896 /* allocate descriptors */
4897 err = i40e_vsi_setup_tx_resources(vsi);
4898 if (err)
4899 goto err_setup_tx;
4900 err = i40e_vsi_setup_rx_resources(vsi);
4901 if (err)
4902 goto err_setup_rx;
4903
4904 err = i40e_vsi_configure(vsi);
4905 if (err)
4906 goto err_setup_rx;
4907
c22e3c6c
SN		 4908 if (vsi->netdev) {
4909 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4910 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4911 err = i40e_vsi_request_irq(vsi, int_name);
4912 if (err)
4913 goto err_setup_rx;
41c445ff 4914
c22e3c6c
SN		 4915 /* Notify the stack of the actual queue counts. */
4916 err = netif_set_real_num_tx_queues(vsi->netdev,
4917 vsi->num_queue_pairs);
4918 if (err)
4919 goto err_set_queues;
25946ddb 4920
c22e3c6c
SN		 4921 err = netif_set_real_num_rx_queues(vsi->netdev,
4922 vsi->num_queue_pairs);
4923 if (err)
4924 goto err_set_queues;
8a9eb7d3
SN		 4925
4926 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 4927 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 4928 dev_driver_string(&pf->pdev->dev),
4929 dev_name(&pf->pdev->dev));
8a9eb7d3 4930 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 4931
c22e3c6c 4932 } else {
ce9ccb17 4933 err = -EINVAL;
6c167f58
EK		 4934 goto err_setup_rx;
4935 }
25946ddb 4936
41c445ff
JB		 4937 err = i40e_up_complete(vsi);
4938 if (err)
4939 goto err_up_complete;
4940
41c445ff
JB		 4941 return 0;
4942
4943err_up_complete:
4944 i40e_down(vsi);
25946ddb 4945err_set_queues:
41c445ff
JB		 4946 i40e_vsi_free_irq(vsi);
4947err_setup_rx:
4948 i40e_vsi_free_rx_resources(vsi);
4949err_setup_tx:
4950 i40e_vsi_free_tx_resources(vsi);
4951 if (vsi == pf->vsi[pf->lan_vsi])
4952 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4953
4954 return err;
4955}
4956
17a73f6b
JG		 4957/**
4958 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4959 * @pf: Pointer to pf
4960 *
4961 * This function destroys the hlist where all the Flow Director
4962 * filters were saved.
4963 **/
4964static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4965{
4966 struct i40e_fdir_filter *filter;
4967 struct hlist_node *node2;
4968
4969 hlist_for_each_entry_safe(filter, node2,
4970 &pf->fdir_filter_list, fdir_node) {
4971 hlist_del(&filter->fdir_node);
4972 kfree(filter);
4973 }
4974 pf->fdir_pf_active_filters = 0;
4975}
4976
41c445ff
JB		 4977/**
4978 * i40e_close - Disables a network interface
4979 * @netdev: network interface device structure
4980 *
4981 * The close entry point is called when an interface is de-activated
4982 * by the OS. The hardware is still under the driver's control, but
4983 * this netdev interface is disabled.
4984 *
4985 * Returns 0, this is not allowed to fail
4986 **/
38e00438
VD		 4987#ifdef I40E_FCOE
4988int i40e_close(struct net_device *netdev)
4989#else
41c445ff 4990static int i40e_close(struct net_device *netdev)
38e00438 4991#endif
41c445ff
JB		 4992{
4993 struct i40e_netdev_priv *np = netdev_priv(netdev);
4994 struct i40e_vsi *vsi = np->vsi;
4995
90ef8d47 4996 i40e_vsi_close(vsi);
41c445ff
JB		 4997
4998 return 0;
4999}
5000
5001/**
5002 * i40e_do_reset - Start a PF or Core Reset sequence
5003 * @pf: board private structure
5004 * @reset_flags: which reset is requested
5005 *
5006 * The essential difference in resets is that the PF Reset
5007 * doesn't clear the packet buffers, doesn't reset the PE
5008 * firmware, and doesn't bother the other PFs on the chip.
5009 **/
5010void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5011{
5012 u32 val;
5013
5014 WARN_ON(in_interrupt());
5015
263fc48f
MW		 5016 if (i40e_check_asq_alive(&pf->hw))
5017 i40e_vc_notify_reset(pf);
5018
41c445ff
JB		 5019 /* do the biggest reset indicated */
5020 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
5021
5022 /* Request a Global Reset
5023 *
5024 * This will start the chip's countdown to the actual full
5025 * chip reset event, and a warning interrupt to be sent
5026 * to all PFs, including the requestor. Our handler
5027 * for the warning interrupt will deal with the shutdown
5028 * and recovery of the switch setup.
5029 */
69bfb110 5030 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5031 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5032 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5033 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5034
5035 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
5036
5037 /* Request a Core Reset
5038 *
5039 * Same as Global Reset, except does *not* include the MAC/PHY
5040 */
69bfb110 5041 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5042 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5043 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5044 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5045 i40e_flush(&pf->hw);
5046
5047 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
5048
5049 /* Request a PF Reset
5050 *
5051 * Resets only the PF-specific registers
5052 *
5053 * This goes directly to the tear-down and rebuild of
5054 * the switch, since we need to do all the recovery as
5055 * for the Core Reset.
5056 */
69bfb110 5057 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5058 i40e_handle_reset_warning(pf);
5059
5060 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
5061 int v;
5062
5063 /* Find the VSI(s) that requested a re-init */
5064 dev_info(&pf->pdev->dev,
5065 "VSI reinit requested\n");
505682cd 5066 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5067 struct i40e_vsi *vsi = pf->vsi[v];
5068 if (vsi != NULL &&
5069 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5070 i40e_vsi_reinit_locked(pf->vsi[v]);
5071 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5072 }
5073 }
5074
b5d06f05
NP		 5075 /* no further action needed, so return now */
5076 return;
5077 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
5078 int v;
5079
5080 /* Find the VSI(s) that needs to be brought down */
5081 dev_info(&pf->pdev->dev, "VSI down requested\n");
5082 for (v = 0; v < pf->num_alloc_vsi; v++) {
5083 struct i40e_vsi *vsi = pf->vsi[v];
5084 if (vsi != NULL &&
5085 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5086 set_bit(__I40E_DOWN, &vsi->state);
5087 i40e_down(vsi);
5088 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5089 }
5090 }
5091
41c445ff
JB		 5092 /* no further action needed, so return now */
5093 return;
5094 } else {
5095 dev_info(&pf->pdev->dev,
5096 "bad reset request 0x%08x\n", reset_flags);
5097 return;
5098 }
5099}
5100
4e3b35b0
NP		 5101#ifdef CONFIG_I40E_DCB
5102/**
5103 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5104 * @pf: board private structure
5105 * @old_cfg: current DCB config
5106 * @new_cfg: new DCB config
5107 **/
5108bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5109 struct i40e_dcbx_config *old_cfg,
5110 struct i40e_dcbx_config *new_cfg)
5111{
5112 bool need_reconfig = false;
5113
5114 /* Check if ETS configuration has changed */
5115 if (memcmp(&new_cfg->etscfg,
5116 &old_cfg->etscfg,
5117 sizeof(new_cfg->etscfg))) {
5118 /* If Priority Table has changed reconfig is needed */
5119 if (memcmp(&new_cfg->etscfg.prioritytable,
5120 &old_cfg->etscfg.prioritytable,
5121 sizeof(new_cfg->etscfg.prioritytable))) {
5122 need_reconfig = true;
69bfb110 5123 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5124 }
5125
5126 if (memcmp(&new_cfg->etscfg.tcbwtable,
5127 &old_cfg->etscfg.tcbwtable,
5128 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5129 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5130
5131 if (memcmp(&new_cfg->etscfg.tsatable,
5132 &old_cfg->etscfg.tsatable,
5133 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5134 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5135 }
5136
5137 /* Check if PFC configuration has changed */
5138 if (memcmp(&new_cfg->pfc,
5139 &old_cfg->pfc,
5140 sizeof(new_cfg->pfc))) {
5141 need_reconfig = true;
69bfb110 5142 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5143 }
5144
5145 /* Check if APP Table has changed */
5146 if (memcmp(&new_cfg->app,
5147 &old_cfg->app,
3d9667a9 5148 sizeof(new_cfg->app))) {
4e3b35b0 5149 need_reconfig = true;
69bfb110 5150 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5151 }
4e3b35b0 5152
9fa61dd2
NP		 5153 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5154 need_reconfig);
4e3b35b0
NP		 5155 return need_reconfig;
5156}
5157
5158/**
5159 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5160 * @pf: board private structure
5161 * @e: event info posted on ARQ
5162 **/
5163static int i40e_handle_lldp_event(struct i40e_pf *pf,
5164 struct i40e_arq_event_info *e)
5165{
5166 struct i40e_aqc_lldp_get_mib *mib =
5167 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5168 struct i40e_hw *hw = &pf->hw;
5169 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
5170 struct i40e_dcbx_config tmp_dcbx_cfg;
5171 bool need_reconfig = false;
5172 int ret = 0;
5173 u8 type;
5174
4d9b6043
NP		 5175 /* Not DCB capable or capability disabled */
5176 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5177 return ret;
5178
4e3b35b0
NP		 5179 /* Ignore if event is not for Nearest Bridge */
5180 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5181 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5182 dev_dbg(&pf->pdev->dev,
5183 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5184 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5185 return ret;
5186
5187 /* Check MIB Type and return if event for Remote MIB update */
5188 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5189 dev_dbg(&pf->pdev->dev,
5190 "%s: LLDP event mib type %s\n", __func__,
5191 type ? "remote" : "local");
4e3b35b0
NP		 5192 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5193 /* Update the remote cached instance and return */
5194 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5195 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5196 &hw->remote_dcbx_config);
5197 goto exit;
5198 }
5199
4e3b35b0 5200 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
9fa61dd2
NP		 5201 /* Store the old configuration */
5202 tmp_dcbx_cfg = *dcbx_cfg;
5203
5204 /* Get updated DCBX data from firmware */
5205 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5206 if (ret) {
9fa61dd2 5207 dev_info(&pf->pdev->dev, "Failed querying DCB configuration data from firmware.\n");
4e3b35b0
NP		 5208 goto exit;
5209 }
5210
5211 /* No change detected in DCBX configs */
5212 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 5213 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5214 goto exit;
5215 }
5216
9fa61dd2 5217 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, dcbx_cfg);
4e3b35b0 5218
9fa61dd2 5219 i40e_dcbnl_flush_apps(pf, dcbx_cfg);
4e3b35b0
NP		 5220
5221 if (!need_reconfig)
5222 goto exit;
5223
4d9b6043
NP		 5224 /* Enable DCB tagging only when more than one TC */
5225 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
5226 pf->flags |= I40E_FLAG_DCB_ENABLED;
5227 else
5228 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5229
69129dc3 5230 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5231 /* Reconfiguration needed quiesce all VSIs */
5232 i40e_pf_quiesce_all_vsi(pf);
5233
5234 /* Changes in configuration update VEB/VSI */
5235 i40e_dcb_reconfigure(pf);
5236
2fd75f31
NP		 5237 ret = i40e_resume_port_tx(pf);
5238
69129dc3 5239 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5240 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5241 if (ret)
5242 goto exit;
5243
5244 /* Wait for the PF's Tx queues to be disabled */
5245 ret = i40e_pf_wait_txq_disabled(pf);
2fd75f31
NP		 5246 if (!ret)
5247 i40e_pf_unquiesce_all_vsi(pf);
4e3b35b0
NP		 5248exit:
5249 return ret;
5250}
5251#endif /* CONFIG_I40E_DCB */
5252
23326186
ASJ		 5253/**
5254 * i40e_do_reset_safe - Protected reset path for userland calls.
5255 * @pf: board private structure
5256 * @reset_flags: which reset is requested
5257 *
5258 **/
5259void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5260{
5261 rtnl_lock();
5262 i40e_do_reset(pf, reset_flags);
5263 rtnl_unlock();
5264}
5265
41c445ff
JB		 5266/**
5267 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5268 * @pf: board private structure
5269 * @e: event info posted on ARQ
5270 *
5271 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5272 * and VF queues
5273 **/
5274static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5275 struct i40e_arq_event_info *e)
5276{
5277 struct i40e_aqc_lan_overflow *data =
5278 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5279 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5280 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5281 struct i40e_hw *hw = &pf->hw;
5282 struct i40e_vf *vf;
5283 u16 vf_id;
5284
69bfb110
JB		 5285 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5286 queue, qtx_ctl);
41c445ff
JB		 5287
5288 /* Queue belongs to VF, find the VF and issue VF reset */
5289 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5290 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5291 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5292 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5293 vf_id -= hw->func_caps.vf_base_id;
5294 vf = &pf->vf[vf_id];
5295 i40e_vc_notify_vf_reset(vf);
5296 /* Allow VF to process pending reset notification */
5297 msleep(20);
5298 i40e_reset_vf(vf, false);
5299 }
5300}
5301
5302/**
5303 * i40e_service_event_complete - Finish up the service event
5304 * @pf: board private structure
5305 **/
5306static void i40e_service_event_complete(struct i40e_pf *pf)
5307{
5308 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5309
5310 /* flush memory to make sure state is correct before next watchog */
4e857c58 5311 smp_mb__before_atomic();
41c445ff
JB		 5312 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5313}
5314
55a5e60b 5315/**
12957388
ASJ		 5316 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5317 * @pf: board private structure
5318 **/
5319int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
5320{
5321 int val, fcnt_prog;
5322
5323 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5324 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5325 return fcnt_prog;
5326}
5327
5328/**
5329 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 5330 * @pf: board private structure
5331 **/
5332int i40e_get_current_fd_count(struct i40e_pf *pf)
5333{
5334 int val, fcnt_prog;
5335 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5336 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5337 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5338 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5339 return fcnt_prog;
5340}
1e1be8f6 5341
55a5e60b
ASJ		 5342/**
5343 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5344 * @pf: board private structure
5345 **/
5346void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5347{
5348 u32 fcnt_prog, fcnt_avail;
5349
1e1be8f6
ASJ		 5350 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5351 return;
5352
55a5e60b
ASJ		 5353 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5354 * to re-enable
5355 */
12957388
ASJ		 5356 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5357 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5358 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5359 (pf->fd_add_err == 0) ||
5360 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5361 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5362 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5363 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5364 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5365 }
5366 }
5367 /* Wait for some more space to be available to turn on ATR */
5368 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5369 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5370 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5371 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5372 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5373 }
5374 }
5375}
5376
1e1be8f6
ASJ		 5377#define I40E_MIN_FD_FLUSH_INTERVAL 10
5378/**
5379 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5380 * @pf: board private structure
5381 **/
5382static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5383{
5384 int flush_wait_retry = 50;
5385 int reg;
5386
1790ed0c
AA		 5387 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5388 return;
5389
1e1be8f6
ASJ		 5390 if (time_after(jiffies, pf->fd_flush_timestamp +
5391 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
5392 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5393 pf->fd_flush_timestamp = jiffies;
5394 pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
5395 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5396 /* flush all filters */
5397 wr32(&pf->hw, I40E_PFQF_CTL_1,
5398 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5399 i40e_flush(&pf->hw);
60793f4a 5400 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5401 pf->fd_add_err = 0;
5402 do {
5403 /* Check FD flush status every 5-6msec */
5404 usleep_range(5000, 6000);
5405 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5406 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5407 break;
5408 } while (flush_wait_retry--);
5409 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5410 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5411 } else {
5412 /* replay sideband filters */
5413 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5414
5415 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5416 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5417 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5418 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5419 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5420 }
5421 }
5422}
5423
5424/**
5425 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5426 * @pf: board private structure
5427 **/
5428int i40e_get_current_atr_cnt(struct i40e_pf *pf)
5429{
5430 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5431}
5432
5433/* We can see up to 256 filter programming desc in transit if the filters are
5434 * being applied really fast; before we see the first
5435 * filter miss error on Rx queue 0. Accumulating enough error messages before
5436 * reacting will make sure we don't cause flush too often.
5437 */
5438#define I40E_MAX_FD_PROGRAM_ERROR 256
5439
41c445ff
JB		 5440/**
5441 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5442 * @pf: board private structure
5443 **/
5444static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5445{
41c445ff 5446
41c445ff
JB		 5447 /* if interface is down do nothing */
5448 if (test_bit(__I40E_DOWN, &pf->state))
5449 return;
1e1be8f6 5450
1790ed0c
AA		 5451 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5452 return;
5453
1e1be8f6
ASJ		 5454 if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
5455 (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
5456 (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
5457 i40e_fdir_flush_and_replay(pf);
5458
55a5e60b
ASJ		 5459 i40e_fdir_check_and_reenable(pf);
5460
41c445ff
JB		 5461}
5462
5463/**
5464 * i40e_vsi_link_event - notify VSI of a link event
5465 * @vsi: vsi to be notified
5466 * @link_up: link up or down
5467 **/
5468static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5469{
32b5b811 5470 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5471 return;
5472
5473 switch (vsi->type) {
5474 case I40E_VSI_MAIN:
38e00438
VD		 5475#ifdef I40E_FCOE
5476 case I40E_VSI_FCOE:
5477#endif
41c445ff
JB		 5478 if (!vsi->netdev || !vsi->netdev_registered)
5479 break;
5480
5481 if (link_up) {
5482 netif_carrier_on(vsi->netdev);
5483 netif_tx_wake_all_queues(vsi->netdev);
5484 } else {
5485 netif_carrier_off(vsi->netdev);
5486 netif_tx_stop_all_queues(vsi->netdev);
5487 }
5488 break;
5489
5490 case I40E_VSI_SRIOV:
41c445ff
JB		 5491 case I40E_VSI_VMDQ2:
5492 case I40E_VSI_CTRL:
5493 case I40E_VSI_MIRROR:
5494 default:
5495 /* there is no notification for other VSIs */
5496 break;
5497 }
5498}
5499
5500/**
5501 * i40e_veb_link_event - notify elements on the veb of a link event
5502 * @veb: veb to be notified
5503 * @link_up: link up or down
5504 **/
5505static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5506{
5507 struct i40e_pf *pf;
5508 int i;
5509
5510 if (!veb || !veb->pf)
5511 return;
5512 pf = veb->pf;
5513
5514 /* depth first... */
5515 for (i = 0; i < I40E_MAX_VEB; i++)
5516 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5517 i40e_veb_link_event(pf->veb[i], link_up);
5518
5519 /* ... now the local VSIs */
505682cd 5520 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5521 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5522 i40e_vsi_link_event(pf->vsi[i], link_up);
5523}
5524
5525/**
5526 * i40e_link_event - Update netif_carrier status
5527 * @pf: board private structure
5528 **/
5529static void i40e_link_event(struct i40e_pf *pf)
5530{
5531 bool new_link, old_link;
320684cd 5532 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5533 u8 new_link_speed, old_link_speed;
41c445ff 5534
1e701e09
JB		 5535 /* set this to force the get_link_status call to refresh state */
5536 pf->hw.phy.get_link_info = true;
5537
41c445ff 5538 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5539 new_link = i40e_get_link_status(&pf->hw);
fef59ddf
CS		 5540 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5541 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5542
1e701e09 5543 if (new_link == old_link &&
fef59ddf 5544 new_link_speed == old_link_speed &&
320684cd
MW		 5545 (test_bit(__I40E_DOWN, &vsi->state) ||
5546 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5547 return;
320684cd
MW		 5548
5549 if (!test_bit(__I40E_DOWN, &vsi->state))
5550 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5551
5552 /* Notify the base of the switch tree connected to
5553 * the link. Floating VEBs are not notified.
5554 */
5555 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5556 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5557 else
320684cd 5558 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5559
5560 if (pf->vf)
5561 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5562
5563 if (pf->flags & I40E_FLAG_PTP)
5564 i40e_ptp_set_increment(pf);
41c445ff
JB		 5565}
5566
5567/**
5568 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5569 * @pf: board private structure
5570 *
5571 * Set the per-queue flags to request a check for stuck queues in the irq
5572 * clean functions, then force interrupts to be sure the irq clean is called.
5573 **/
5574static void i40e_check_hang_subtask(struct i40e_pf *pf)
5575{
5576 int i, v;
5577
5578 /* If we're down or resetting, just bail */
5579 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5580 return;
5581
5582 /* for each VSI/netdev
5583 * for each Tx queue
5584 * set the check flag
5585 * for each q_vector
5586 * force an interrupt
5587 */
505682cd 5588 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5589 struct i40e_vsi *vsi = pf->vsi[v];
5590 int armed = 0;
5591
5592 if (!pf->vsi[v] ||
5593 test_bit(__I40E_DOWN, &vsi->state) ||
5594 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5595 continue;
5596
5597 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5598 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5599 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5600 &vsi->tx_rings[i]->state))
41c445ff
JB		 5601 armed++;
5602 }
5603
5604 if (armed) {
5605 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5606 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5607 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5d1ff106
SN		 5608 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
5609 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
5610 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
5611 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
41c445ff
JB		 5612 } else {
5613 u16 vec = vsi->base_vector - 1;
5614 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5d1ff106
SN		 5615 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
5616 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK |
5617 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK |
5618 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK);
41c445ff
JB		 5619 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5620 wr32(&vsi->back->hw,
5621 I40E_PFINT_DYN_CTLN(vec), val);
5622 }
5623 i40e_flush(&vsi->back->hw);
5624 }
5625 }
5626}
5627
5628/**
21536717 5629 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5630 * @pf: board private structure
5631 **/
5632static void i40e_watchdog_subtask(struct i40e_pf *pf)
5633{
5634 int i;
5635
5636 /* if interface is down do nothing */
5637 if (test_bit(__I40E_DOWN, &pf->state) ||
5638 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5639 return;
5640
21536717
SN		 5641 /* make sure we don't do these things too often */
5642 if (time_before(jiffies, (pf->service_timer_previous +
5643 pf->service_timer_period)))
5644 return;
5645 pf->service_timer_previous = jiffies;
5646
5647 i40e_check_hang_subtask(pf);
5648 i40e_link_event(pf);
5649
41c445ff
JB		 5650 /* Update the stats for active netdevs so the network stack
5651 * can look at updated numbers whenever it cares to
5652 */
505682cd 5653 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5654 if (pf->vsi[i] && pf->vsi[i]->netdev)
5655 i40e_update_stats(pf->vsi[i]);
5656
5657 /* Update the stats for the active switching components */
5658 for (i = 0; i < I40E_MAX_VEB; i++)
5659 if (pf->veb[i])
5660 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5661
5662 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5663}
5664
5665/**
5666 * i40e_reset_subtask - Set up for resetting the device and driver
5667 * @pf: board private structure
5668 **/
5669static void i40e_reset_subtask(struct i40e_pf *pf)
5670{
5671 u32 reset_flags = 0;
5672
23326186 5673 rtnl_lock();
41c445ff
JB		 5674 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5675 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5676 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5677 }
5678 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5679 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5680 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5681 }
5682 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5683 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5684 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5685 }
5686 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5687 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5688 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5689 }
b5d06f05
NP		 5690 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5691 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5692 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5693 }
41c445ff
JB		 5694
5695 /* If there's a recovery already waiting, it takes
5696 * precedence before starting a new reset sequence.
5697 */
5698 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5699 i40e_handle_reset_warning(pf);
23326186 5700 goto unlock;
41c445ff
JB		 5701 }
5702
5703 /* If we're already down or resetting, just bail */
5704 if (reset_flags &&
5705 !test_bit(__I40E_DOWN, &pf->state) &&
5706 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5707 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5708
5709unlock:
5710 rtnl_unlock();
41c445ff
JB		 5711}
5712
5713/**
5714 * i40e_handle_link_event - Handle link event
5715 * @pf: board private structure
5716 * @e: event info posted on ARQ
5717 **/
5718static void i40e_handle_link_event(struct i40e_pf *pf,
5719 struct i40e_arq_event_info *e)
5720{
5721 struct i40e_hw *hw = &pf->hw;
5722 struct i40e_aqc_get_link_status *status =
5723 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5724 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5725
5726 /* save off old link status information */
5727 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5728 sizeof(pf->hw.phy.link_info_old));
5729
1e701e09
JB		 5730 /* Do a new status request to re-enable LSE reporting
5731 * and load new status information into the hw struct
5732 * This completely ignores any state information
5733 * in the ARQ event info, instead choosing to always
5734 * issue the AQ update link status command.
5735 */
5736 i40e_link_event(pf);
5737
7b592f61
CW		 5738 /* check for unqualified module, if link is down */
5739 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5740 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5741 (!(status->link_info & I40E_AQ_LINK_UP)))
5742 dev_err(&pf->pdev->dev,
5743 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5744}
5745
5746/**
5747 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5748 * @pf: board private structure
5749 **/
5750static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5751{
5752 struct i40e_arq_event_info event;
5753 struct i40e_hw *hw = &pf->hw;
5754 u16 pending, i = 0;
5755 i40e_status ret;
5756 u16 opcode;
86df242b 5757 u32 oldval;
41c445ff
JB		 5758 u32 val;
5759
a316f651
ASJ		 5760 /* Do not run clean AQ when PF reset fails */
5761 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5762 return;
5763
86df242b
SN		 5764 /* check for error indications */
5765 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5766 oldval = val;
5767 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5768 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5769 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5770 }
5771 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5772 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5773 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5774 }
5775 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5776 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5777 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5778 }
5779 if (oldval != val)
5780 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5781
5782 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5783 oldval = val;
5784 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5785 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5786 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5787 }
5788 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5789 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5790 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5791 }
5792 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5793 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5794 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5795 }
5796 if (oldval != val)
5797 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5798
1001dc37
MW		 5799 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
5800 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 5801 if (!event.msg_buf)
5802 return;
5803
5804 do {
5805 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5806 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5807 break;
56497978 5808 else if (ret) {
41c445ff
JB		 5809 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5810 break;
5811 }
5812
5813 opcode = le16_to_cpu(event.desc.opcode);
5814 switch (opcode) {
5815
5816 case i40e_aqc_opc_get_link_status:
5817 i40e_handle_link_event(pf, &event);
5818 break;
5819 case i40e_aqc_opc_send_msg_to_pf:
5820 ret = i40e_vc_process_vf_msg(pf,
5821 le16_to_cpu(event.desc.retval),
5822 le32_to_cpu(event.desc.cookie_high),
5823 le32_to_cpu(event.desc.cookie_low),
5824 event.msg_buf,
1001dc37 5825 event.msg_len);
41c445ff
JB		 5826 break;
5827 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5828 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5829#ifdef CONFIG_I40E_DCB
5830 rtnl_lock();
5831 ret = i40e_handle_lldp_event(pf, &event);
5832 rtnl_unlock();
5833#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5834 break;
5835 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5836 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5837 i40e_handle_lan_overflow_event(pf, &event);
5838 break;
0467bc91
SN		 5839 case i40e_aqc_opc_send_msg_to_peer:
5840 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5841 break;
41c445ff
JB		 5842 default:
5843 dev_info(&pf->pdev->dev,
0467bc91
SN		 5844 "ARQ Error: Unknown event 0x%04x received\n",
5845 opcode);
41c445ff
JB		 5846 break;
5847 }
5848 } while (pending && (i++ < pf->adminq_work_limit));
5849
5850 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5851 /* re-enable Admin queue interrupt cause */
5852 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5853 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5854 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5855 i40e_flush(hw);
5856
5857 kfree(event.msg_buf);
5858}
5859
4eb3f768
SN		 5860/**
5861 * i40e_verify_eeprom - make sure eeprom is good to use
5862 * @pf: board private structure
5863 **/
5864static void i40e_verify_eeprom(struct i40e_pf *pf)
5865{
5866 int err;
5867
5868 err = i40e_diag_eeprom_test(&pf->hw);
5869 if (err) {
5870 /* retry in case of garbage read */
5871 err = i40e_diag_eeprom_test(&pf->hw);
5872 if (err) {
5873 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5874 err);
5875 set_bit(__I40E_BAD_EEPROM, &pf->state);
5876 }
5877 }
5878
5879 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5880 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5881 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5882 }
5883}
5884
51616018
NP		 5885/**
5886 * i40e_config_bridge_mode - Configure the HW bridge mode
5887 * @veb: pointer to the bridge instance
5888 *
5889 * Configure the loop back mode for the LAN VSI that is downlink to the
5890 * specified HW bridge instance. It is expected this function is called
5891 * when a new HW bridge is instantiated.
5892 **/
5893static void i40e_config_bridge_mode(struct i40e_veb *veb)
5894{
5895 struct i40e_pf *pf = veb->pf;
5896
5897 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
5898 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
5899 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
5900 i40e_disable_pf_switch_lb(pf);
5901 else
5902 i40e_enable_pf_switch_lb(pf);
5903}
5904
41c445ff
JB		 5905/**
5906 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5907 * @veb: pointer to the VEB instance
5908 *
5909 * This is a recursive function that first builds the attached VSIs then
5910 * recurses in to build the next layer of VEB. We track the connections
5911 * through our own index numbers because the seid's from the HW could
5912 * change across the reset.
5913 **/
5914static int i40e_reconstitute_veb(struct i40e_veb *veb)
5915{
5916 struct i40e_vsi *ctl_vsi = NULL;
5917 struct i40e_pf *pf = veb->pf;
5918 int v, veb_idx;
5919 int ret;
5920
5921 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5922 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5923 if (pf->vsi[v] &&
5924 pf->vsi[v]->veb_idx == veb->idx &&
5925 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5926 ctl_vsi = pf->vsi[v];
5927 break;
5928 }
5929 }
5930 if (!ctl_vsi) {
5931 dev_info(&pf->pdev->dev,
5932 "missing owner VSI for veb_idx %d\n", veb->idx);
5933 ret = -ENOENT;
5934 goto end_reconstitute;
5935 }
5936 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5937 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5938 ret = i40e_add_vsi(ctl_vsi);
5939 if (ret) {
5940 dev_info(&pf->pdev->dev,
5941 "rebuild of owner VSI failed: %d\n", ret);
5942 goto end_reconstitute;
5943 }
5944 i40e_vsi_reset_stats(ctl_vsi);
5945
5946 /* create the VEB in the switch and move the VSI onto the VEB */
5947 ret = i40e_add_veb(veb, ctl_vsi);
5948 if (ret)
5949 goto end_reconstitute;
5950
51616018 5951 i40e_config_bridge_mode(veb);
b64ba084 5952
41c445ff 5953 /* create the remaining VSIs attached to this VEB */
505682cd 5954 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5955 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5956 continue;
5957
5958 if (pf->vsi[v]->veb_idx == veb->idx) {
5959 struct i40e_vsi *vsi = pf->vsi[v];
5960 vsi->uplink_seid = veb->seid;
5961 ret = i40e_add_vsi(vsi);
5962 if (ret) {
5963 dev_info(&pf->pdev->dev,
5964 "rebuild of vsi_idx %d failed: %d\n",
5965 v, ret);
5966 goto end_reconstitute;
5967 }
5968 i40e_vsi_reset_stats(vsi);
5969 }
5970 }
5971
5972 /* create any VEBs attached to this VEB - RECURSION */
5973 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5974 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5975 pf->veb[veb_idx]->uplink_seid = veb->seid;
5976 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5977 if (ret)
5978 break;
5979 }
5980 }
5981
5982end_reconstitute:
5983 return ret;
5984}
5985
5986/**
5987 * i40e_get_capabilities - get info about the HW
5988 * @pf: the PF struct
5989 **/
5990static int i40e_get_capabilities(struct i40e_pf *pf)
5991{
5992 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5993 u16 data_size;
5994 int buf_len;
5995 int err;
5996
5997 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5998 do {
5999 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6000 if (!cap_buf)
6001 return -ENOMEM;
6002
6003 /* this loads the data into the hw struct for us */
6004 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6005 &data_size,
6006 i40e_aqc_opc_list_func_capabilities,
6007 NULL);
6008 /* data loaded, buffer no longer needed */
6009 kfree(cap_buf);
6010
6011 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6012 /* retry with a larger buffer */
6013 buf_len = data_size;
6014 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6015 dev_info(&pf->pdev->dev,
6016 "capability discovery failed: aq=%d\n",
6017 pf->hw.aq.asq_last_status);
6018 return -ENODEV;
6019 }
6020 } while (err);
6021
ac71b7ba
ASJ		 6022 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6023 (pf->hw.aq.fw_maj_ver < 2)) {
6024 pf->hw.func_caps.num_msix_vectors++;
6025 pf->hw.func_caps.num_msix_vectors_vf++;
6026 }
6027
41c445ff
JB		 6028 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6029 dev_info(&pf->pdev->dev,
6030 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6031 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6032 pf->hw.func_caps.num_msix_vectors,
6033 pf->hw.func_caps.num_msix_vectors_vf,
6034 pf->hw.func_caps.fd_filters_guaranteed,
6035 pf->hw.func_caps.fd_filters_best_effort,
6036 pf->hw.func_caps.num_tx_qp,
6037 pf->hw.func_caps.num_vsis);
6038
7134f9ce
JB		 6039#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6040 + pf->hw.func_caps.num_vfs)
6041 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6042 dev_info(&pf->pdev->dev,
6043 "got num_vsis %d, setting num_vsis to %d\n",
6044 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6045 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6046 }
6047
41c445ff
JB		 6048 return 0;
6049}
6050
cbf61325
ASJ		 6051static int i40e_vsi_clear(struct i40e_vsi *vsi);
6052
41c445ff 6053/**
cbf61325 6054 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6055 * @pf: board private structure
6056 **/
cbf61325 6057static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6058{
6059 struct i40e_vsi *vsi;
8a9eb7d3 6060 int i;
41c445ff 6061
407e063c
JB		 6062 /* quick workaround for an NVM issue that leaves a critical register
6063 * uninitialized
6064 */
6065 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6066 static const u32 hkey[] = {
6067 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6068 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6069 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6070 0x95b3a76d};
6071
6072 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6073 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6074 }
6075
cbf61325 6076 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6077 return;
6078
cbf61325 6079 /* find existing VSI and see if it needs configuring */
41c445ff 6080 vsi = NULL;
505682cd 6081 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6082 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6083 vsi = pf->vsi[i];
cbf61325
ASJ		 6084 break;
6085 }
6086 }
6087
6088 /* create a new VSI if none exists */
41c445ff 6089 if (!vsi) {
cbf61325
ASJ		 6090 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6091 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6092 if (!vsi) {
6093 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6094 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6095 return;
41c445ff 6096 }
cbf61325 6097 }
41c445ff 6098
8a9eb7d3 6099 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6100}
6101
6102/**
6103 * i40e_fdir_teardown - release the Flow Director resources
6104 * @pf: board private structure
6105 **/
6106static void i40e_fdir_teardown(struct i40e_pf *pf)
6107{
6108 int i;
6109
17a73f6b 6110 i40e_fdir_filter_exit(pf);
505682cd 6111 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6112 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6113 i40e_vsi_release(pf->vsi[i]);
6114 break;
6115 }
6116 }
6117}
6118
6119/**
f650a38b 6120 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6121 * @pf: board private structure
6122 *
f650a38b
ASJ		 6123 * Close up the VFs and other things in prep for pf Reset.
6124 **/
23cfbe07 6125static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6126{
41c445ff 6127 struct i40e_hw *hw = &pf->hw;
60442dea 6128 i40e_status ret = 0;
41c445ff
JB		 6129 u32 v;
6130
6131 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6132 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6133 return;
41c445ff 6134
69bfb110 6135 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6136
41c445ff
JB		 6137 /* quiesce the VSIs and their queues that are not already DOWN */
6138 i40e_pf_quiesce_all_vsi(pf);
6139
505682cd 6140 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6141 if (pf->vsi[v])
6142 pf->vsi[v]->seid = 0;
6143 }
6144
6145 i40e_shutdown_adminq(&pf->hw);
6146
f650a38b 6147 /* call shutdown HMC */
60442dea
SN		 6148 if (hw->hmc.hmc_obj) {
6149 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6150 if (ret)
60442dea
SN		 6151 dev_warn(&pf->pdev->dev,
6152 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6153 }
f650a38b
ASJ		 6154}
6155
44033fac
JB		 6156/**
6157 * i40e_send_version - update firmware with driver version
6158 * @pf: PF struct
6159 */
6160static void i40e_send_version(struct i40e_pf *pf)
6161{
6162 struct i40e_driver_version dv;
6163
6164 dv.major_version = DRV_VERSION_MAJOR;
6165 dv.minor_version = DRV_VERSION_MINOR;
6166 dv.build_version = DRV_VERSION_BUILD;
6167 dv.subbuild_version = 0;
35a7d804 6168 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6169 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6170}
6171
f650a38b 6172/**
4dda12e6 6173 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6174 * @pf: board private structure
bc7d338f 6175 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6176 **/
bc7d338f 6177static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6178{
f650a38b 6179 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6180 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6181 i40e_status ret;
6182 u32 v;
6183
41c445ff
JB		 6184 /* Now we wait for GRST to settle out.
6185 * We don't have to delete the VEBs or VSIs from the hw switch
6186 * because the reset will make them disappear.
6187 */
6188 ret = i40e_pf_reset(hw);
b5565400 6189 if (ret) {
41c445ff 6190 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6191 set_bit(__I40E_RESET_FAILED, &pf->state);
6192 goto clear_recovery;
b5565400 6193 }
41c445ff
JB		 6194 pf->pfr_count++;
6195
6196 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6197 goto clear_recovery;
69bfb110 6198 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6199
6200 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6201 ret = i40e_init_adminq(&pf->hw);
6202 if (ret) {
6203 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 6204 goto clear_recovery;
41c445ff
JB		 6205 }
6206
4eb3f768 6207 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6208 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6209 i40e_verify_eeprom(pf);
4eb3f768 6210
e78ac4bf 6211 i40e_clear_pxe_mode(hw);
41c445ff
JB		 6212 ret = i40e_get_capabilities(pf);
6213 if (ret) {
6214 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
6215 ret);
6216 goto end_core_reset;
6217 }
6218
41c445ff
JB		 6219 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6220 hw->func_caps.num_rx_qp,
6221 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6222 if (ret) {
6223 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6224 goto end_core_reset;
6225 }
6226 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6227 if (ret) {
6228 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6229 goto end_core_reset;
6230 }
6231
4e3b35b0
NP		 6232#ifdef CONFIG_I40E_DCB
6233 ret = i40e_init_pf_dcb(pf);
6234 if (ret) {
aebfc816
SN		 6235 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6236 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6237 /* Continue without DCB enabled */
4e3b35b0
NP		 6238 }
6239#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6240#ifdef I40E_FCOE
6241 ret = i40e_init_pf_fcoe(pf);
6242 if (ret)
6243 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6244
38e00438 6245#endif
41c445ff 6246 /* do basic switch setup */
bc7d338f 6247 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6248 if (ret)
6249 goto end_core_reset;
6250
7e2453fe
JB		 6251 /* driver is only interested in link up/down and module qualification
6252 * reports from firmware
6253 */
6254 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6255 I40E_AQ_EVENT_LINK_UPDOWN |
6256 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6257 if (ret)
6258 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6259
cafa2ee6
ASJ		 6260 /* make sure our flow control settings are restored */
6261 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6262 if (ret)
6263 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6264
41c445ff
JB		 6265 /* Rebuild the VSIs and VEBs that existed before reset.
6266 * They are still in our local switch element arrays, so only
6267 * need to rebuild the switch model in the HW.
6268 *
6269 * If there were VEBs but the reconstitution failed, we'll try
6270 * try to recover minimal use by getting the basic PF VSI working.
6271 */
6272 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6273 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6274 /* find the one VEB connected to the MAC, and find orphans */
6275 for (v = 0; v < I40E_MAX_VEB; v++) {
6276 if (!pf->veb[v])
6277 continue;
6278
6279 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6280 pf->veb[v]->uplink_seid == 0) {
6281 ret = i40e_reconstitute_veb(pf->veb[v]);
6282
6283 if (!ret)
6284 continue;
6285
6286 /* If Main VEB failed, we're in deep doodoo,
6287 * so give up rebuilding the switch and set up
6288 * for minimal rebuild of PF VSI.
6289 * If orphan failed, we'll report the error
6290 * but try to keep going.
6291 */
6292 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6293 dev_info(&pf->pdev->dev,
6294 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6295 ret);
6296 pf->vsi[pf->lan_vsi]->uplink_seid
6297 = pf->mac_seid;
6298 break;
6299 } else if (pf->veb[v]->uplink_seid == 0) {
6300 dev_info(&pf->pdev->dev,
6301 "rebuild of orphan VEB failed: %d\n",
6302 ret);
6303 }
6304 }
6305 }
6306 }
6307
6308 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6309 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6310 /* no VEB, so rebuild only the Main VSI */
6311 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6312 if (ret) {
6313 dev_info(&pf->pdev->dev,
6314 "rebuild of Main VSI failed: %d\n", ret);
6315 goto end_core_reset;
6316 }
6317 }
6318
025b4a54
ASJ		 6319 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6320 (pf->hw.aq.fw_maj_ver < 4)) {
6321 msleep(75);
6322 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6323 if (ret)
6324 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6325 pf->hw.aq.asq_last_status);
cafa2ee6 6326 }
41c445ff
JB		 6327 /* reinit the misc interrupt */
6328 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6329 ret = i40e_setup_misc_vector(pf);
6330
6331 /* restart the VSIs that were rebuilt and running before the reset */
6332 i40e_pf_unquiesce_all_vsi(pf);
6333
69f64b2b
MW		 6334 if (pf->num_alloc_vfs) {
6335 for (v = 0; v < pf->num_alloc_vfs; v++)
6336 i40e_reset_vf(&pf->vf[v], true);
6337 }
6338
41c445ff 6339 /* tell the firmware that we're starting */
44033fac 6340 i40e_send_version(pf);
41c445ff
JB		 6341
6342end_core_reset:
a316f651
ASJ		 6343 clear_bit(__I40E_RESET_FAILED, &pf->state);
6344clear_recovery:
41c445ff
JB		 6345 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6346}
6347
f650a38b
ASJ		 6348/**
6349 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
6350 * @pf: board private structure
6351 *
6352 * Close up the VFs and other things in prep for a Core Reset,
6353 * then get ready to rebuild the world.
6354 **/
6355static void i40e_handle_reset_warning(struct i40e_pf *pf)
6356{
23cfbe07
SN		 6357 i40e_prep_for_reset(pf);
6358 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6359}
6360
41c445ff
JB		 6361/**
6362 * i40e_handle_mdd_event
6363 * @pf: pointer to the pf structure
6364 *
6365 * Called from the MDD irq handler to identify possibly malicious vfs
6366 **/
6367static void i40e_handle_mdd_event(struct i40e_pf *pf)
6368{
6369 struct i40e_hw *hw = &pf->hw;
6370 bool mdd_detected = false;
df430b12 6371 bool pf_mdd_detected = false;
41c445ff
JB		 6372 struct i40e_vf *vf;
6373 u32 reg;
6374 int i;
6375
6376 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6377 return;
6378
6379 /* find what triggered the MDD event */
6380 reg = rd32(hw, I40E_GL_MDET_TX);
6381 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6382 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6383 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6384 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6385 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6386 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6387 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6388 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6389 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6390 pf->hw.func_caps.base_queue;
faf32978
JB		 6391 if (netif_msg_tx_err(pf))
6392 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
6393 event, queue, pf_num, vf_num);
41c445ff
JB		 6394 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6395 mdd_detected = true;
6396 }
6397 reg = rd32(hw, I40E_GL_MDET_RX);
6398 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6399 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6400 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6401 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6402 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6403 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6404 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6405 pf->hw.func_caps.base_queue;
faf32978
JB		 6406 if (netif_msg_rx_err(pf))
6407 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6408 event, queue, func);
41c445ff
JB		 6409 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6410 mdd_detected = true;
6411 }
6412
df430b12
NP		 6413 if (mdd_detected) {
6414 reg = rd32(hw, I40E_PF_MDET_TX);
6415 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6416 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6417 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6418 pf_mdd_detected = true;
6419 }
6420 reg = rd32(hw, I40E_PF_MDET_RX);
6421 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6422 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6423 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6424 pf_mdd_detected = true;
6425 }
6426 /* Queue belongs to the PF, initiate a reset */
6427 if (pf_mdd_detected) {
6428 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6429 i40e_service_event_schedule(pf);
6430 }
6431 }
6432
41c445ff
JB		 6433 /* see if one of the VFs needs its hand slapped */
6434 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6435 vf = &(pf->vf[i]);
6436 reg = rd32(hw, I40E_VP_MDET_TX(i));
6437 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6438 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6439 vf->num_mdd_events++;
faf32978
JB		 6440 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6441 i);
41c445ff
JB		 6442 }
6443
6444 reg = rd32(hw, I40E_VP_MDET_RX(i));
6445 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6446 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6447 vf->num_mdd_events++;
faf32978
JB		 6448 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6449 i);
41c445ff
JB		 6450 }
6451
6452 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6453 dev_info(&pf->pdev->dev,
6454 "Too many MDD events on VF %d, disabled\n", i);
6455 dev_info(&pf->pdev->dev,
6456 "Use PF Control I/F to re-enable the VF\n");
6457 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6458 }
6459 }
6460
6461 /* re-enable mdd interrupt cause */
6462 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6463 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6464 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6465 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6466 i40e_flush(hw);
6467}
6468
a1c9a9d9
JK		 6469#ifdef CONFIG_I40E_VXLAN
6470/**
6471 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6472 * @pf: board private structure
6473 **/
6474static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6475{
a1c9a9d9
JK		 6476 struct i40e_hw *hw = &pf->hw;
6477 i40e_status ret;
6478 u8 filter_index;
6479 __be16 port;
6480 int i;
6481
6482 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6483 return;
6484
6485 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6486
6487 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6488 if (pf->pending_vxlan_bitmap & (1 << i)) {
6489 pf->pending_vxlan_bitmap &= ~(1 << i);
6490 port = pf->vxlan_ports[i];
6491 ret = port ?
6492 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6493 I40E_AQC_TUNNEL_TYPE_VXLAN,
6494 &filter_index, NULL)
6495 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6496
6497 if (ret) {
6498 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6499 port ? "adding" : "deleting",
6500 ntohs(port), port ? i : i);
6501
6502 pf->vxlan_ports[i] = 0;
6503 } else {
6504 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6505 port ? "Added" : "Deleted",
6506 ntohs(port), port ? i : filter_index);
6507 }
6508 }
6509 }
6510}
6511
6512#endif
41c445ff
JB		 6513/**
6514 * i40e_service_task - Run the driver's async subtasks
6515 * @work: pointer to work_struct containing our data
6516 **/
6517static void i40e_service_task(struct work_struct *work)
6518{
6519 struct i40e_pf *pf = container_of(work,
6520 struct i40e_pf,
6521 service_task);
6522 unsigned long start_time = jiffies;
6523
e57a2fea
SN		 6524 /* don't bother with service tasks if a reset is in progress */
6525 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6526 i40e_service_event_complete(pf);
6527 return;
6528 }
6529
41c445ff
JB		 6530 i40e_reset_subtask(pf);
6531 i40e_handle_mdd_event(pf);
6532 i40e_vc_process_vflr_event(pf);
6533 i40e_watchdog_subtask(pf);
6534 i40e_fdir_reinit_subtask(pf);
41c445ff 6535 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6536#ifdef CONFIG_I40E_VXLAN
6537 i40e_sync_vxlan_filters_subtask(pf);
6538#endif
41c445ff
JB		 6539 i40e_clean_adminq_subtask(pf);
6540
6541 i40e_service_event_complete(pf);
6542
6543 /* If the tasks have taken longer than one timer cycle or there
6544 * is more work to be done, reschedule the service task now
6545 * rather than wait for the timer to tick again.
6546 */
6547 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6548 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6549 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6550 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6551 i40e_service_event_schedule(pf);
6552}
6553
6554/**
6555 * i40e_service_timer - timer callback
6556 * @data: pointer to PF struct
6557 **/
6558static void i40e_service_timer(unsigned long data)
6559{
6560 struct i40e_pf *pf = (struct i40e_pf *)data;
6561
6562 mod_timer(&pf->service_timer,
6563 round_jiffies(jiffies + pf->service_timer_period));
6564 i40e_service_event_schedule(pf);
6565}
6566
6567/**
6568 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6569 * @vsi: the VSI being configured
6570 **/
6571static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6572{
6573 struct i40e_pf *pf = vsi->back;
6574
6575 switch (vsi->type) {
6576 case I40E_VSI_MAIN:
6577 vsi->alloc_queue_pairs = pf->num_lan_qps;
6578 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6579 I40E_REQ_DESCRIPTOR_MULTIPLE);
6580 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6581 vsi->num_q_vectors = pf->num_lan_msix;
6582 else
6583 vsi->num_q_vectors = 1;
6584
6585 break;
6586
6587 case I40E_VSI_FDIR:
6588 vsi->alloc_queue_pairs = 1;
6589 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6590 I40E_REQ_DESCRIPTOR_MULTIPLE);
6591 vsi->num_q_vectors = 1;
6592 break;
6593
6594 case I40E_VSI_VMDQ2:
6595 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6596 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6597 I40E_REQ_DESCRIPTOR_MULTIPLE);
6598 vsi->num_q_vectors = pf->num_vmdq_msix;
6599 break;
6600
6601 case I40E_VSI_SRIOV:
6602 vsi->alloc_queue_pairs = pf->num_vf_qps;
6603 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6604 I40E_REQ_DESCRIPTOR_MULTIPLE);
6605 break;
6606
38e00438
VD		 6607#ifdef I40E_FCOE
6608 case I40E_VSI_FCOE:
6609 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6610 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6611 I40E_REQ_DESCRIPTOR_MULTIPLE);
6612 vsi->num_q_vectors = pf->num_fcoe_msix;
6613 break;
6614
6615#endif /* I40E_FCOE */
41c445ff
JB		 6616 default:
6617 WARN_ON(1);
6618 return -ENODATA;
6619 }
6620
6621 return 0;
6622}
6623
f650a38b
ASJ		 6624/**
6625 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6626 * @type: VSI pointer
bc7d338f 6627 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6628 *
6629 * On error: returns error code (negative)
6630 * On success: returns 0
6631 **/
bc7d338f 6632static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6633{
6634 int size;
6635 int ret = 0;
6636
ac6c5e3d 6637 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6638 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6639 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6640 if (!vsi->tx_rings)
6641 return -ENOMEM;
f650a38b
ASJ		 6642 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6643
bc7d338f
ASJ		 6644 if (alloc_qvectors) {
6645 /* allocate memory for q_vector pointers */
f57e4fbd 6646 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6647 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6648 if (!vsi->q_vectors) {
6649 ret = -ENOMEM;
6650 goto err_vectors;
6651 }
f650a38b
ASJ		 6652 }
6653 return ret;
6654
6655err_vectors:
6656 kfree(vsi->tx_rings);
6657 return ret;
6658}
6659
41c445ff
JB		 6660/**
6661 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6662 * @pf: board private structure
6663 * @type: type of VSI
6664 *
6665 * On error: returns error code (negative)
6666 * On success: returns vsi index in PF (positive)
6667 **/
6668static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6669{
6670 int ret = -ENODEV;
6671 struct i40e_vsi *vsi;
6672 int vsi_idx;
6673 int i;
6674
6675 /* Need to protect the allocation of the VSIs at the PF level */
6676 mutex_lock(&pf->switch_mutex);
6677
6678 /* VSI list may be fragmented if VSI creation/destruction has
6679 * been happening. We can afford to do a quick scan to look
6680 * for any free VSIs in the list.
6681 *
6682 * find next empty vsi slot, looping back around if necessary
6683 */
6684 i = pf->next_vsi;
505682cd 6685 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6686 i++;
505682cd 6687 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6688 i = 0;
6689 while (i < pf->next_vsi && pf->vsi[i])
6690 i++;
6691 }
6692
505682cd 6693 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6694 vsi_idx = i; /* Found one! */
6695 } else {
6696 ret = -ENODEV;
493fb300 6697 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6698 }
6699 pf->next_vsi = ++i;
6700
6701 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6702 if (!vsi) {
6703 ret = -ENOMEM;
493fb300 6704 goto unlock_pf;
41c445ff
JB		 6705 }
6706 vsi->type = type;
6707 vsi->back = pf;
6708 set_bit(__I40E_DOWN, &vsi->state);
6709 vsi->flags = 0;
6710 vsi->idx = vsi_idx;
6711 vsi->rx_itr_setting = pf->rx_itr_default;
6712 vsi->tx_itr_setting = pf->tx_itr_default;
6713 vsi->netdev_registered = false;
6714 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6715 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6716 vsi->irqs_ready = false;
41c445ff 6717
9f65e15b
AD		 6718 ret = i40e_set_num_rings_in_vsi(vsi);
6719 if (ret)
6720 goto err_rings;
6721
bc7d338f 6722 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6723 if (ret)
9f65e15b 6724 goto err_rings;
493fb300 6725
41c445ff
JB		 6726 /* Setup default MSIX irq handler for VSI */
6727 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6728
6729 pf->vsi[vsi_idx] = vsi;
6730 ret = vsi_idx;
493fb300
AD		 6731 goto unlock_pf;
6732
9f65e15b 6733err_rings:
493fb300
AD		 6734 pf->next_vsi = i - 1;
6735 kfree(vsi);
6736unlock_pf:
41c445ff
JB		 6737 mutex_unlock(&pf->switch_mutex);
6738 return ret;
6739}
6740
f650a38b
ASJ		 6741/**
6742 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6743 * @type: VSI pointer
bc7d338f 6744 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6745 *
6746 * On error: returns error code (negative)
6747 * On success: returns 0
6748 **/
bc7d338f 6749static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6750{
6751 /* free the ring and vector containers */
bc7d338f
ASJ		 6752 if (free_qvectors) {
6753 kfree(vsi->q_vectors);
6754 vsi->q_vectors = NULL;
6755 }
f650a38b
ASJ		 6756 kfree(vsi->tx_rings);
6757 vsi->tx_rings = NULL;
6758 vsi->rx_rings = NULL;
6759}
6760
41c445ff
JB		 6761/**
6762 * i40e_vsi_clear - Deallocate the VSI provided
6763 * @vsi: the VSI being un-configured
6764 **/
6765static int i40e_vsi_clear(struct i40e_vsi *vsi)
6766{
6767 struct i40e_pf *pf;
6768
6769 if (!vsi)
6770 return 0;
6771
6772 if (!vsi->back)
6773 goto free_vsi;
6774 pf = vsi->back;
6775
6776 mutex_lock(&pf->switch_mutex);
6777 if (!pf->vsi[vsi->idx]) {
6778 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6779 vsi->idx, vsi->idx, vsi, vsi->type);
6780 goto unlock_vsi;
6781 }
6782
6783 if (pf->vsi[vsi->idx] != vsi) {
6784 dev_err(&pf->pdev->dev,
6785 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6786 pf->vsi[vsi->idx]->idx,
6787 pf->vsi[vsi->idx],
6788 pf->vsi[vsi->idx]->type,
6789 vsi->idx, vsi, vsi->type);
6790 goto unlock_vsi;
6791 }
6792
6793 /* updates the pf for this cleared vsi */
6794 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6795 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6796
bc7d338f 6797 i40e_vsi_free_arrays(vsi, true);
493fb300 6798
41c445ff
JB		 6799 pf->vsi[vsi->idx] = NULL;
6800 if (vsi->idx < pf->next_vsi)
6801 pf->next_vsi = vsi->idx;
6802
6803unlock_vsi:
6804 mutex_unlock(&pf->switch_mutex);
6805free_vsi:
6806 kfree(vsi);
6807
6808 return 0;
6809}
6810
9f65e15b
AD		 6811/**
6812 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6813 * @vsi: the VSI being cleaned
6814 **/
be1d5eea 6815static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6816{
6817 int i;
6818
8e9dca53 6819 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6820 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6821 kfree_rcu(vsi->tx_rings[i], rcu);
6822 vsi->tx_rings[i] = NULL;
6823 vsi->rx_rings[i] = NULL;
6824 }
be1d5eea 6825 }
9f65e15b
AD		 6826}
6827
41c445ff
JB		 6828/**
6829 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6830 * @vsi: the VSI being configured
6831 **/
6832static int i40e_alloc_rings(struct i40e_vsi *vsi)
6833{
e7046ee1 6834 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6835 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6836 int i;
6837
41c445ff 6838 /* Set basic values in the rings to be used later during open() */
d7397644 6839 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6840 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6841 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6842 if (!tx_ring)
6843 goto err_out;
41c445ff
JB		 6844
6845 tx_ring->queue_index = i;
6846 tx_ring->reg_idx = vsi->base_queue + i;
6847 tx_ring->ring_active = false;
6848 tx_ring->vsi = vsi;
6849 tx_ring->netdev = vsi->netdev;
6850 tx_ring->dev = &pf->pdev->dev;
6851 tx_ring->count = vsi->num_desc;
6852 tx_ring->size = 0;
6853 tx_ring->dcb_tc = 0;
9f65e15b 6854 vsi->tx_rings[i] = tx_ring;
41c445ff 6855
9f65e15b 6856 rx_ring = &tx_ring[1];
41c445ff
JB		 6857 rx_ring->queue_index = i;
6858 rx_ring->reg_idx = vsi->base_queue + i;
6859 rx_ring->ring_active = false;
6860 rx_ring->vsi = vsi;
6861 rx_ring->netdev = vsi->netdev;
6862 rx_ring->dev = &pf->pdev->dev;
6863 rx_ring->count = vsi->num_desc;
6864 rx_ring->size = 0;
6865 rx_ring->dcb_tc = 0;
6866 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6867 set_ring_16byte_desc_enabled(rx_ring);
6868 else
6869 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6870 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6871 }
6872
6873 return 0;
9f65e15b
AD		 6874
6875err_out:
6876 i40e_vsi_clear_rings(vsi);
6877 return -ENOMEM;
41c445ff
JB		 6878}
6879
6880/**
6881 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6882 * @pf: board private structure
6883 * @vectors: the number of MSI-X vectors to request
6884 *
6885 * Returns the number of vectors reserved, or error
6886 **/
6887static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6888{
7b37f376
AG		 6889 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6890 I40E_MIN_MSIX, vectors);
6891 if (vectors < 0) {
41c445ff 6892 dev_info(&pf->pdev->dev,
7b37f376 6893 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6894 vectors = 0;
6895 }
6896
6897 return vectors;
6898}
6899
6900/**
6901 * i40e_init_msix - Setup the MSIX capability
6902 * @pf: board private structure
6903 *
6904 * Work with the OS to set up the MSIX vectors needed.
6905 *
6906 * Returns 0 on success, negative on failure
6907 **/
6908static int i40e_init_msix(struct i40e_pf *pf)
6909{
6910 i40e_status err = 0;
6911 struct i40e_hw *hw = &pf->hw;
c135b0de 6912 int other_vecs = 0;
41c445ff
JB		 6913 int v_budget, i;
6914 int vec;
6915
6916 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6917 return -ENODEV;
6918
6919 /* The number of vectors we'll request will be comprised of:
6920 * - Add 1 for "other" cause for Admin Queue events, etc.
6921 * - The number of LAN queue pairs
f8ff1464
ASJ		 6922 * - Queues being used for RSS.
6923 * We don't need as many as max_rss_size vectors.
6924 * use rss_size instead in the calculation since that
6925 * is governed by number of cpus in the system.
6926 * - assumes symmetric Tx/Rx pairing
41c445ff 6927 * - The number of VMDq pairs
38e00438
VD		 6928#ifdef I40E_FCOE
6929 * - The number of FCOE qps.
6930#endif
41c445ff
JB		 6931 * Once we count this up, try the request.
6932 *
6933 * If we can't get what we want, we'll simplify to nearly nothing
6934 * and try again. If that still fails, we punt.
6935 */
9a3bd2f1
ASJ		 6936 pf->num_lan_msix = min_t(int, num_online_cpus(),
6937 hw->func_caps.num_msix_vectors);
41c445ff 6938 pf->num_vmdq_msix = pf->num_vmdq_qps;
c135b0de
SN		 6939 other_vecs = 1;
6940 other_vecs += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6941 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
c135b0de 6942 other_vecs++;
41c445ff 6943
83840e4b
JL		 6944 /* Scale down if necessary, and the rings will share vectors */
6945 pf->num_lan_msix = min_t(int, pf->num_lan_msix,
6946 (hw->func_caps.num_msix_vectors - other_vecs));
6947 v_budget = pf->num_lan_msix + other_vecs;
6948
38e00438
VD		 6949#ifdef I40E_FCOE
6950 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6951 pf->num_fcoe_msix = pf->num_fcoe_qps;
6952 v_budget += pf->num_fcoe_msix;
6953 }
38e00438 6954#endif
41c445ff
JB		 6955
6956 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6957 GFP_KERNEL);
6958 if (!pf->msix_entries)
6959 return -ENOMEM;
6960
6961 for (i = 0; i < v_budget; i++)
6962 pf->msix_entries[i].entry = i;
6963 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6964
6965 if (vec != v_budget) {
6966 /* If we have limited resources, we will start with no vectors
6967 * for the special features and then allocate vectors to some
6968 * of these features based on the policy and at the end disable
6969 * the features that did not get any vectors.
6970 */
38e00438
VD		 6971#ifdef I40E_FCOE
6972 pf->num_fcoe_qps = 0;
6973 pf->num_fcoe_msix = 0;
6974#endif
a34977ba
ASJ		 6975 pf->num_vmdq_msix = 0;
6976 }
6977
41c445ff
JB		 6978 if (vec < I40E_MIN_MSIX) {
6979 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6980 kfree(pf->msix_entries);
6981 pf->msix_entries = NULL;
6982 return -ENODEV;
6983
6984 } else if (vec == I40E_MIN_MSIX) {
6985 /* Adjust for minimal MSIX use */
41c445ff
JB		 6986 pf->num_vmdq_vsis = 0;
6987 pf->num_vmdq_qps = 0;
41c445ff
JB		 6988 pf->num_lan_qps = 1;
6989 pf->num_lan_msix = 1;
6990
6991 } else if (vec != v_budget) {
a34977ba
ASJ		 6992 /* reserve the misc vector */
6993 vec--;
6994
41c445ff
JB		 6995 /* Scale vector usage down */
6996 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6997 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6998
6999 /* partition out the remaining vectors */
7000 switch (vec) {
7001 case 2:
41c445ff
JB		 7002 pf->num_lan_msix = 1;
7003 break;
7004 case 3:
38e00438
VD		 7005#ifdef I40E_FCOE
7006 /* give one vector to FCoE */
7007 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7008 pf->num_lan_msix = 1;
7009 pf->num_fcoe_msix = 1;
7010 }
7011#else
41c445ff 7012 pf->num_lan_msix = 2;
38e00438 7013#endif
41c445ff
JB		 7014 break;
7015 default:
38e00438
VD		 7016#ifdef I40E_FCOE
7017 /* give one vector to FCoE */
7018 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7019 pf->num_fcoe_msix = 1;
7020 vec--;
7021 }
7022#endif
41c445ff
JB		 7023 pf->num_lan_msix = min_t(int, (vec / 2),
7024 pf->num_lan_qps);
7025 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
7026 I40E_DEFAULT_NUM_VMDQ_VSI);
7027 break;
7028 }
7029 }
7030
a34977ba
ASJ		 7031 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7032 (pf->num_vmdq_msix == 0)) {
7033 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7034 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7035 }
38e00438
VD		 7036#ifdef I40E_FCOE
7037
7038 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7039 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7040 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7041 }
7042#endif
41c445ff
JB		 7043 return err;
7044}
7045
493fb300 7046/**
90e04070 7047 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7048 * @vsi: the VSI being configured
7049 * @v_idx: index of the vector in the vsi struct
7050 *
7051 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7052 **/
90e04070 7053static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7054{
7055 struct i40e_q_vector *q_vector;
7056
7057 /* allocate q_vector */
7058 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7059 if (!q_vector)
7060 return -ENOMEM;
7061
7062 q_vector->vsi = vsi;
7063 q_vector->v_idx = v_idx;
7064 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7065 if (vsi->netdev)
7066 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7067 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7068
cd0b6fa6
AD		 7069 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7070 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7071
493fb300
AD		 7072 /* tie q_vector and vsi together */
7073 vsi->q_vectors[v_idx] = q_vector;
7074
7075 return 0;
7076}
7077
41c445ff 7078/**
90e04070 7079 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7080 * @vsi: the VSI being configured
7081 *
7082 * We allocate one q_vector per queue interrupt. If allocation fails we
7083 * return -ENOMEM.
7084 **/
90e04070 7085static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7086{
7087 struct i40e_pf *pf = vsi->back;
7088 int v_idx, num_q_vectors;
493fb300 7089 int err;
41c445ff
JB		 7090
7091 /* if not MSIX, give the one vector only to the LAN VSI */
7092 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7093 num_q_vectors = vsi->num_q_vectors;
7094 else if (vsi == pf->vsi[pf->lan_vsi])
7095 num_q_vectors = 1;
7096 else
7097 return -EINVAL;
7098
41c445ff 7099 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7100 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7101 if (err)
7102 goto err_out;
41c445ff
JB		 7103 }
7104
7105 return 0;
493fb300
AD		 7106
7107err_out:
7108 while (v_idx--)
7109 i40e_free_q_vector(vsi, v_idx);
7110
7111 return err;
41c445ff
JB		 7112}
7113
7114/**
7115 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7116 * @pf: board private structure to initialize
7117 **/
7118static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
7119{
7120 int err = 0;
7121
7122 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7123 err = i40e_init_msix(pf);
7124 if (err) {
60ea5f83 7125 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7126#ifdef I40E_FCOE
7127 I40E_FLAG_FCOE_ENABLED |
7128#endif
60ea5f83 7129 I40E_FLAG_RSS_ENABLED |
4d9b6043 7130 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7131 I40E_FLAG_SRIOV_ENABLED |
7132 I40E_FLAG_FD_SB_ENABLED |
7133 I40E_FLAG_FD_ATR_ENABLED |
7134 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7135
7136 /* rework the queue expectations without MSIX */
7137 i40e_determine_queue_usage(pf);
7138 }
7139 }
7140
7141 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7142 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7143 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 7144 err = pci_enable_msi(pf->pdev);
7145 if (err) {
958a3e3b 7146 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 7147 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7148 }
7149 }
7150
958a3e3b 7151 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7152 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7153
41c445ff
JB		 7154 /* track first vector for misc interrupts */
7155 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
7156}
7157
7158/**
7159 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7160 * @pf: board private structure
7161 *
7162 * This sets up the handler for MSIX 0, which is used to manage the
7163 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7164 * when in MSI or Legacy interrupt mode.
7165 **/
7166static int i40e_setup_misc_vector(struct i40e_pf *pf)
7167{
7168 struct i40e_hw *hw = &pf->hw;
7169 int err = 0;
7170
7171 /* Only request the irq if this is the first time through, and
7172 * not when we're rebuilding after a Reset
7173 */
7174 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7175 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7176 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7177 if (err) {
7178 dev_info(&pf->pdev->dev,
77fa28be 7179 "request_irq for %s failed: %d\n",
b294ac70 7180 pf->int_name, err);
41c445ff
JB		 7181 return -EFAULT;
7182 }
7183 }
7184
ab437b5a 7185 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7186
7187 /* associate no queues to the misc vector */
7188 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7189 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7190
7191 i40e_flush(hw);
7192
7193 i40e_irq_dynamic_enable_icr0(pf);
7194
7195 return err;
7196}
7197
7198/**
7199 * i40e_config_rss - Prepare for RSS if used
7200 * @pf: board private structure
7201 **/
7202static int i40e_config_rss(struct i40e_pf *pf)
7203{
22f258a1 7204 u32 rss_key[I40E_PFQF_HKEY_MAX_INDEX + 1];
4617e8c0
ASJ		 7205 struct i40e_hw *hw = &pf->hw;
7206 u32 lut = 0;
7207 int i, j;
7208 u64 hena;
e157ea30 7209 u32 reg_val;
41c445ff 7210
22f258a1 7211 netdev_rss_key_fill(rss_key, sizeof(rss_key));
41c445ff 7212 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
22f258a1 7213 wr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);
41c445ff
JB		 7214
7215 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7216 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7217 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7218 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7219 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7220 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7221
e157ea30
CW		 7222 /* Check capability and Set table size and register per hw expectation*/
7223 reg_val = rd32(hw, I40E_PFQF_CTL_0);
7224 if (hw->func_caps.rss_table_size == 512) {
7225 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7226 pf->rss_table_size = 512;
7227 } else {
7228 pf->rss_table_size = 128;
7229 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7230 }
7231 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7232
41c445ff 7233 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7234 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7235
7236 /* The assumption is that lan qp count will be the highest
7237 * qp count for any PF VSI that needs RSS.
7238 * If multiple VSIs need RSS support, all the qp counts
7239 * for those VSIs should be a power of 2 for RSS to work.
7240 * If LAN VSI is the only consumer for RSS then this requirement
7241 * is not necessary.
7242 */
7243 if (j == pf->rss_size)
7244 j = 0;
7245 /* lut = 4-byte sliding window of 4 lut entries */
7246 lut = (lut << 8) | (j &
7247 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7248 /* On i = 3, we have 4 entries in lut; write to the register */
7249 if ((i & 3) == 3)
7250 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7251 }
7252 i40e_flush(hw);
7253
7254 return 0;
7255}
7256
f8ff1464
ASJ		 7257/**
7258 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7259 * @pf: board private structure
7260 * @queue_count: the requested queue count for rss.
7261 *
7262 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7263 * count which may be different from the requested queue count.
7264 **/
7265int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7266{
9a3bd2f1
ASJ		 7267 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7268 int new_rss_size;
7269
f8ff1464
ASJ		 7270 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7271 return 0;
7272
9a3bd2f1 7273 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7274
9a3bd2f1
ASJ		 7275 if (queue_count != vsi->num_queue_pairs) {
7276 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7277 i40e_prep_for_reset(pf);
7278
9a3bd2f1 7279 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7280
7281 i40e_reset_and_rebuild(pf, true);
7282 i40e_config_rss(pf);
7283 }
7284 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7285 return pf->rss_size;
7286}
7287
f4492db1
GR		 7288/**
7289 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7290 * @pf: board private structure
7291 **/
7292i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7293{
7294 i40e_status status;
7295 bool min_valid, max_valid;
7296 u32 max_bw, min_bw;
7297
7298 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7299 &min_valid, &max_valid);
7300
7301 if (!status) {
7302 if (min_valid)
7303 pf->npar_min_bw = min_bw;
7304 if (max_valid)
7305 pf->npar_max_bw = max_bw;
7306 }
7307
7308 return status;
7309}
7310
7311/**
7312 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7313 * @pf: board private structure
7314 **/
7315i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7316{
7317 struct i40e_aqc_configure_partition_bw_data bw_data;
7318 i40e_status status;
7319
7320 /* Set the valid bit for this pf */
7321 bw_data.pf_valid_bits = cpu_to_le16(1 << pf->hw.pf_id);
7322 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7323 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7324
7325 /* Set the new bandwidths */
7326 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7327
7328 return status;
7329}
7330
7331/**
7332 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7333 * @pf: board private structure
7334 **/
7335i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7336{
7337 /* Commit temporary BW setting to permanent NVM image */
7338 enum i40e_admin_queue_err last_aq_status;
7339 i40e_status ret;
7340 u16 nvm_word;
7341
7342 if (pf->hw.partition_id != 1) {
7343 dev_info(&pf->pdev->dev,
7344 "Commit BW only works on partition 1! This is partition %d",
7345 pf->hw.partition_id);
7346 ret = I40E_NOT_SUPPORTED;
7347 goto bw_commit_out;
7348 }
7349
7350 /* Acquire NVM for read access */
7351 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7352 last_aq_status = pf->hw.aq.asq_last_status;
7353 if (ret) {
7354 dev_info(&pf->pdev->dev,
7355 "Cannot acquire NVM for read access, err %d: aq_err %d\n",
7356 ret, last_aq_status);
7357 goto bw_commit_out;
7358 }
7359
7360 /* Read word 0x10 of NVM - SW compatibility word 1 */
7361 ret = i40e_aq_read_nvm(&pf->hw,
7362 I40E_SR_NVM_CONTROL_WORD,
7363 0x10, sizeof(nvm_word), &nvm_word,
7364 false, NULL);
7365 /* Save off last admin queue command status before releasing
7366 * the NVM
7367 */
7368 last_aq_status = pf->hw.aq.asq_last_status;
7369 i40e_release_nvm(&pf->hw);
7370 if (ret) {
7371 dev_info(&pf->pdev->dev, "NVM read error, err %d aq_err %d\n",
7372 ret, last_aq_status);
7373 goto bw_commit_out;
7374 }
7375
7376 /* Wait a bit for NVM release to complete */
7377 msleep(50);
7378
7379 /* Acquire NVM for write access */
7380 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7381 last_aq_status = pf->hw.aq.asq_last_status;
7382 if (ret) {
7383 dev_info(&pf->pdev->dev,
7384 "Cannot acquire NVM for write access, err %d: aq_err %d\n",
7385 ret, last_aq_status);
7386 goto bw_commit_out;
7387 }
7388 /* Write it back out unchanged to initiate update NVM,
7389 * which will force a write of the shadow (alt) RAM to
7390 * the NVM - thus storing the bandwidth values permanently.
7391 */
7392 ret = i40e_aq_update_nvm(&pf->hw,
7393 I40E_SR_NVM_CONTROL_WORD,
7394 0x10, sizeof(nvm_word),
7395 &nvm_word, true, NULL);
7396 /* Save off last admin queue command status before releasing
7397 * the NVM
7398 */
7399 last_aq_status = pf->hw.aq.asq_last_status;
7400 i40e_release_nvm(&pf->hw);
7401 if (ret)
7402 dev_info(&pf->pdev->dev,
7403 "BW settings NOT SAVED, err %d aq_err %d\n",
7404 ret, last_aq_status);
7405bw_commit_out:
7406
7407 return ret;
7408}
7409
41c445ff
JB		 7410/**
7411 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7412 * @pf: board private structure to initialize
7413 *
7414 * i40e_sw_init initializes the Adapter private data structure.
7415 * Fields are initialized based on PCI device information and
7416 * OS network device settings (MTU size).
7417 **/
7418static int i40e_sw_init(struct i40e_pf *pf)
7419{
7420 int err = 0;
7421 int size;
7422
7423 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7424 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7425 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7426 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7427 if (I40E_DEBUG_USER & debug)
7428 pf->hw.debug_mask = debug;
7429 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7430 I40E_DEFAULT_MSG_ENABLE);
7431 }
7432
7433 /* Set default capability flags */
7434 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7435 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 7436 I40E_FLAG_MSIX_ENABLED;
7437
7438 if (iommu_present(&pci_bus_type))
7439 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7440 else
7441 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7442
ca99eb99
MW		 7443 /* Set default ITR */
7444 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7445 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7446
7134f9ce
JB		 7447 /* Depending on PF configurations, it is possible that the RSS
7448 * maximum might end up larger than the available queues
7449 */
41c445ff 7450 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7451 pf->rss_size = 1;
7134f9ce
JB		 7452 pf->rss_size_max = min_t(int, pf->rss_size_max,
7453 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7454 if (pf->hw.func_caps.rss) {
7455 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7456 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7457 }
7458
2050bc65
CS		 7459 /* MFP mode enabled */
7460 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7461 pf->flags |= I40E_FLAG_MFP_ENABLED;
7462 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7463 if (i40e_get_npar_bw_setting(pf))
7464 dev_warn(&pf->pdev->dev,
7465 "Could not get NPAR bw settings\n");
7466 else
7467 dev_info(&pf->pdev->dev,
7468 "Min BW = %8.8x, Max BW = %8.8x\n",
7469 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7470 }
7471
cbf61325
ASJ		 7472 /* FW/NVM is not yet fixed in this regard */
7473 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7474 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7475 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7476 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 7477 /* Setup a counter for fd_atr per pf */
7478 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7479 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7480 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 7481 /* Setup a counter for fd_sb per pf */
7482 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7483 } else {
7484 dev_info(&pf->pdev->dev,
0b67584f 7485 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7486 }
cbf61325
ASJ		 7487 pf->fdir_pf_filter_count =
7488 pf->hw.func_caps.fd_filters_guaranteed;
7489 pf->hw.fdir_shared_filter_count =
7490 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7491 }
7492
7493 if (pf->hw.func_caps.vmdq) {
7494 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7495 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7496 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7497 }
7498
38e00438
VD		 7499#ifdef I40E_FCOE
7500 err = i40e_init_pf_fcoe(pf);
7501 if (err)
7502 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7503
7504#endif /* I40E_FCOE */
41c445ff 7505#ifdef CONFIG_PCI_IOV
ba252f13 7506 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7507 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7508 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7509 pf->num_req_vfs = min_t(int,
7510 pf->hw.func_caps.num_vfs,
7511 I40E_MAX_VF_COUNT);
7512 }
7513#endif /* CONFIG_PCI_IOV */
7514 pf->eeprom_version = 0xDEAD;
7515 pf->lan_veb = I40E_NO_VEB;
7516 pf->lan_vsi = I40E_NO_VSI;
7517
7518 /* set up queue assignment tracking */
7519 size = sizeof(struct i40e_lump_tracking)
7520 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7521 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7522 if (!pf->qp_pile) {
7523 err = -ENOMEM;
7524 goto sw_init_done;
7525 }
7526 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7527 pf->qp_pile->search_hint = 0;
7528
7529 /* set up vector assignment tracking */
7530 size = sizeof(struct i40e_lump_tracking)
7531 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
7532 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7533 if (!pf->irq_pile) {
7534 kfree(pf->qp_pile);
7535 err = -ENOMEM;
7536 goto sw_init_done;
7537 }
7538 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
7539 pf->irq_pile->search_hint = 0;
7540
327fe04b
ASJ		 7541 pf->tx_timeout_recovery_level = 1;
7542
41c445ff
JB		 7543 mutex_init(&pf->switch_mutex);
7544
7545sw_init_done:
7546 return err;
7547}
7548
7c3c288b
ASJ		 7549/**
7550 * i40e_set_ntuple - set the ntuple feature flag and take action
7551 * @pf: board private structure to initialize
7552 * @features: the feature set that the stack is suggesting
7553 *
7554 * returns a bool to indicate if reset needs to happen
7555 **/
7556bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7557{
7558 bool need_reset = false;
7559
7560 /* Check if Flow Director n-tuple support was enabled or disabled. If
7561 * the state changed, we need to reset.
7562 */
7563 if (features & NETIF_F_NTUPLE) {
7564 /* Enable filters and mark for reset */
7565 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7566 need_reset = true;
7567 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7568 } else {
7569 /* turn off filters, mark for reset and clear SW filter list */
7570 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7571 need_reset = true;
7572 i40e_fdir_filter_exit(pf);
7573 }
7574 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7575 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7576 /* reset fd counters */
7577 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7578 pf->fdir_pf_active_filters = 0;
7579 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7580 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7581 /* if ATR was auto disabled it can be re-enabled. */
7582 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7583 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7584 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7585 }
7586 return need_reset;
7587}
7588
41c445ff
JB		 7589/**
7590 * i40e_set_features - set the netdev feature flags
7591 * @netdev: ptr to the netdev being adjusted
7592 * @features: the feature set that the stack is suggesting
7593 **/
7594static int i40e_set_features(struct net_device *netdev,
7595 netdev_features_t features)
7596{
7597 struct i40e_netdev_priv *np = netdev_priv(netdev);
7598 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7599 struct i40e_pf *pf = vsi->back;
7600 bool need_reset;
41c445ff
JB		 7601
7602 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7603 i40e_vlan_stripping_enable(vsi);
7604 else
7605 i40e_vlan_stripping_disable(vsi);
7606
7c3c288b
ASJ		 7607 need_reset = i40e_set_ntuple(pf, features);
7608
7609 if (need_reset)
7610 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7611
41c445ff
JB		 7612 return 0;
7613}
7614
a1c9a9d9
JK		 7615#ifdef CONFIG_I40E_VXLAN
7616/**
7617 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7618 * @pf: board private structure
7619 * @port: The UDP port to look up
7620 *
7621 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7622 **/
7623static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7624{
7625 u8 i;
7626
7627 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7628 if (pf->vxlan_ports[i] == port)
7629 return i;
7630 }
7631
7632 return i;
7633}
7634
7635/**
7636 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7637 * @netdev: This physical port's netdev
7638 * @sa_family: Socket Family that VXLAN is notifying us about
7639 * @port: New UDP port number that VXLAN started listening to
7640 **/
7641static void i40e_add_vxlan_port(struct net_device *netdev,
7642 sa_family_t sa_family, __be16 port)
7643{
7644 struct i40e_netdev_priv *np = netdev_priv(netdev);
7645 struct i40e_vsi *vsi = np->vsi;
7646 struct i40e_pf *pf = vsi->back;
7647 u8 next_idx;
7648 u8 idx;
7649
7650 if (sa_family == AF_INET6)
7651 return;
7652
7653 idx = i40e_get_vxlan_port_idx(pf, port);
7654
7655 /* Check if port already exists */
7656 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7657 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7658 return;
7659 }
7660
7661 /* Now check if there is space to add the new port */
7662 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7663
7664 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7665 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7666 ntohs(port));
7667 return;
7668 }
7669
7670 /* New port: add it and mark its index in the bitmap */
7671 pf->vxlan_ports[next_idx] = port;
7672 pf->pending_vxlan_bitmap |= (1 << next_idx);
7673
7674 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7675}
7676
7677/**
7678 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7679 * @netdev: This physical port's netdev
7680 * @sa_family: Socket Family that VXLAN is notifying us about
7681 * @port: UDP port number that VXLAN stopped listening to
7682 **/
7683static void i40e_del_vxlan_port(struct net_device *netdev,
7684 sa_family_t sa_family, __be16 port)
7685{
7686 struct i40e_netdev_priv *np = netdev_priv(netdev);
7687 struct i40e_vsi *vsi = np->vsi;
7688 struct i40e_pf *pf = vsi->back;
7689 u8 idx;
7690
7691 if (sa_family == AF_INET6)
7692 return;
7693
7694 idx = i40e_get_vxlan_port_idx(pf, port);
7695
7696 /* Check if port already exists */
7697 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7698 /* if port exists, set it to 0 (mark for deletion)
7699 * and make it pending
7700 */
7701 pf->vxlan_ports[idx] = 0;
7702
7703 pf->pending_vxlan_bitmap |= (1 << idx);
7704
7705 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7706 } else {
7707 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7708 ntohs(port));
7709 }
7710}
7711
7712#endif
1f224ad2 7713static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 7714 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 7715{
7716 struct i40e_netdev_priv *np = netdev_priv(netdev);
7717 struct i40e_pf *pf = np->vsi->back;
7718 struct i40e_hw *hw = &pf->hw;
7719
7720 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7721 return -EOPNOTSUPP;
7722
7723 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7724 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7725
7726 return 0;
7727}
7728
2f90ade6
JB		 7729/**
7730 * i40e_ndo_fdb_add - add an entry to the hardware database
7731 * @ndm: the input from the stack
7732 * @tb: pointer to array of nladdr (unused)
7733 * @dev: the net device pointer
7734 * @addr: the MAC address entry being added
7735 * @flags: instructions from stack about fdb operation
7736 */
4ba0dea5
GR		 7737static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7738 struct net_device *dev,
f6f6424b 7739 const unsigned char *addr, u16 vid,
4ba0dea5 7740 u16 flags)
4ba0dea5
GR		 7741{
7742 struct i40e_netdev_priv *np = netdev_priv(dev);
7743 struct i40e_pf *pf = np->vsi->back;
7744 int err = 0;
7745
7746 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7747 return -EOPNOTSUPP;
7748
65891fea
OG		 7749 if (vid) {
7750 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
7751 return -EINVAL;
7752 }
7753
4ba0dea5
GR		 7754 /* Hardware does not support aging addresses so if a
7755 * ndm_state is given only allow permanent addresses
7756 */
7757 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7758 netdev_info(dev, "FDB only supports static addresses\n");
7759 return -EINVAL;
7760 }
7761
7762 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7763 err = dev_uc_add_excl(dev, addr);
7764 else if (is_multicast_ether_addr(addr))
7765 err = dev_mc_add_excl(dev, addr);
7766 else
7767 err = -EINVAL;
7768
7769 /* Only return duplicate errors if NLM_F_EXCL is set */
7770 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7771 err = 0;
7772
7773 return err;
7774}
7775
51616018
NP		 7776#ifdef HAVE_BRIDGE_ATTRIBS
7777/**
7778 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
7779 * @dev: the netdev being configured
7780 * @nlh: RTNL message
7781 *
7782 * Inserts a new hardware bridge if not already created and
7783 * enables the bridging mode requested (VEB or VEPA). If the
7784 * hardware bridge has already been inserted and the request
7785 * is to change the mode then that requires a PF reset to
7786 * allow rebuild of the components with required hardware
7787 * bridge mode enabled.
7788 **/
7789static int i40e_ndo_bridge_setlink(struct net_device *dev,
7790 struct nlmsghdr *nlh)
7791{
7792 struct i40e_netdev_priv *np = netdev_priv(dev);
7793 struct i40e_vsi *vsi = np->vsi;
7794 struct i40e_pf *pf = vsi->back;
7795 struct i40e_veb *veb = NULL;
7796 struct nlattr *attr, *br_spec;
7797 int i, rem;
7798
7799 /* Only for PF VSI for now */
7800 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
7801 return -EOPNOTSUPP;
7802
7803 /* Find the HW bridge for PF VSI */
7804 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7805 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7806 veb = pf->veb[i];
7807 }
7808
7809 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7810
7811 nla_for_each_nested(attr, br_spec, rem) {
7812 __u16 mode;
7813
7814 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7815 continue;
7816
7817 mode = nla_get_u16(attr);
7818 if ((mode != BRIDGE_MODE_VEPA) &&
7819 (mode != BRIDGE_MODE_VEB))
7820 return -EINVAL;
7821
7822 /* Insert a new HW bridge */
7823 if (!veb) {
7824 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7825 vsi->tc_config.enabled_tc);
7826 if (veb) {
7827 veb->bridge_mode = mode;
7828 i40e_config_bridge_mode(veb);
7829 } else {
7830 /* No Bridge HW offload available */
7831 return -ENOENT;
7832 }
7833 break;
7834 } else if (mode != veb->bridge_mode) {
7835 /* Existing HW bridge but different mode needs reset */
7836 veb->bridge_mode = mode;
7837 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7838 break;
7839 }
7840 }
7841
7842 return 0;
7843}
7844
7845/**
7846 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
7847 * @skb: skb buff
7848 * @pid: process id
7849 * @seq: RTNL message seq #
7850 * @dev: the netdev being configured
7851 * @filter_mask: unused
7852 *
7853 * Return the mode in which the hardware bridge is operating in
7854 * i.e VEB or VEPA.
7855 **/
7856#ifdef HAVE_BRIDGE_FILTER
7857static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7858 struct net_device *dev,
7859 u32 __always_unused filter_mask)
7860#else
7861static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7862 struct net_device *dev)
7863#endif /* HAVE_BRIDGE_FILTER */
7864{
7865 struct i40e_netdev_priv *np = netdev_priv(dev);
7866 struct i40e_vsi *vsi = np->vsi;
7867 struct i40e_pf *pf = vsi->back;
7868 struct i40e_veb *veb = NULL;
7869 int i;
7870
7871 /* Only for PF VSI for now */
7872 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
7873 return -EOPNOTSUPP;
7874
7875 /* Find the HW bridge for the PF VSI */
7876 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7877 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7878 veb = pf->veb[i];
7879 }
7880
7881 if (!veb)
7882 return 0;
7883
7884 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode);
7885}
7886#endif /* HAVE_BRIDGE_ATTRIBS */
7887
96664483 7888const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 7889 .ndo_open = i40e_open,
7890 .ndo_stop = i40e_close,
7891 .ndo_start_xmit = i40e_lan_xmit_frame,
7892 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7893 .ndo_set_rx_mode = i40e_set_rx_mode,
7894 .ndo_validate_addr = eth_validate_addr,
7895 .ndo_set_mac_address = i40e_set_mac,
7896 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7897 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7898 .ndo_tx_timeout = i40e_tx_timeout,
7899 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7900 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7901#ifdef CONFIG_NET_POLL_CONTROLLER
7902 .ndo_poll_controller = i40e_netpoll,
7903#endif
7904 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 7905#ifdef I40E_FCOE
7906 .ndo_fcoe_enable = i40e_fcoe_enable,
7907 .ndo_fcoe_disable = i40e_fcoe_disable,
7908#endif
41c445ff
JB		 7909 .ndo_set_features = i40e_set_features,
7910 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7911 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7912 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7913 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7914 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 7915 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 7916#ifdef CONFIG_I40E_VXLAN
7917 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7918 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7919#endif
1f224ad2 7920 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 7921 .ndo_fdb_add = i40e_ndo_fdb_add,
51616018
NP		 7922#ifdef HAVE_BRIDGE_ATTRIBS
7923 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
7924 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
7925#endif /* HAVE_BRIDGE_ATTRIBS */
41c445ff
JB		 7926};
7927
7928/**
7929 * i40e_config_netdev - Setup the netdev flags
7930 * @vsi: the VSI being configured
7931 *
7932 * Returns 0 on success, negative value on failure
7933 **/
7934static int i40e_config_netdev(struct i40e_vsi *vsi)
7935{
1a10370a 7936 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7937 struct i40e_pf *pf = vsi->back;
7938 struct i40e_hw *hw = &pf->hw;
7939 struct i40e_netdev_priv *np;
7940 struct net_device *netdev;
7941 u8 mac_addr[ETH_ALEN];
7942 int etherdev_size;
7943
7944 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7945 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7946 if (!netdev)
7947 return -ENOMEM;
7948
7949 vsi->netdev = netdev;
7950 np = netdev_priv(netdev);
7951 np->vsi = vsi;
7952
d70e941b 7953 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7954 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7955 NETIF_F_TSO;
41c445ff
JB		 7956
7957 netdev->features = NETIF_F_SG |
7958 NETIF_F_IP_CSUM |
7959 NETIF_F_SCTP_CSUM |
7960 NETIF_F_HIGHDMA |
7961 NETIF_F_GSO_UDP_TUNNEL |
7962 NETIF_F_HW_VLAN_CTAG_TX |
7963 NETIF_F_HW_VLAN_CTAG_RX |
7964 NETIF_F_HW_VLAN_CTAG_FILTER |
7965 NETIF_F_IPV6_CSUM |
7966 NETIF_F_TSO |
059dab69 7967 NETIF_F_TSO_ECN |
41c445ff
JB		 7968 NETIF_F_TSO6 |
7969 NETIF_F_RXCSUM |
7970 NETIF_F_RXHASH |
7971 0;
7972
2e86a0b6
ASJ		 7973 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7974 netdev->features |= NETIF_F_NTUPLE;
7975
41c445ff
JB		 7976 /* copy netdev features into list of user selectable features */
7977 netdev->hw_features |= netdev->features;
7978
7979 if (vsi->type == I40E_VSI_MAIN) {
7980 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7981 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 7982 /* The following steps are necessary to prevent reception
7983 * of tagged packets - some older NVM configurations load a
7984 * default a MAC-VLAN filter that accepts any tagged packet
7985 * which must be replaced by a normal filter.
8c27d42e 7986 */
30650cc5
SN		 7987 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
7988 i40e_add_filter(vsi, mac_addr,
7989 I40E_VLAN_ANY, false, true);
41c445ff
JB		 7990 } else {
7991 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7992 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7993 pf->vsi[pf->lan_vsi]->netdev->name);
7994 random_ether_addr(mac_addr);
7995 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7996 }
1a10370a 7997 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7998
9a173901
GR		 7999 ether_addr_copy(netdev->dev_addr, mac_addr);
8000 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8001 /* vlan gets same features (except vlan offload)
8002 * after any tweaks for specific VSI types
8003 */
8004 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8005 NETIF_F_HW_VLAN_CTAG_RX |
8006 NETIF_F_HW_VLAN_CTAG_FILTER);
8007 netdev->priv_flags |= IFF_UNICAST_FLT;
8008 netdev->priv_flags |= IFF_SUPP_NOFCS;
8009 /* Setup netdev TC information */
8010 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8011
8012 netdev->netdev_ops = &i40e_netdev_ops;
8013 netdev->watchdog_timeo = 5 * HZ;
8014 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8015#ifdef I40E_FCOE
8016 i40e_fcoe_config_netdev(netdev, vsi);
8017#endif
41c445ff
JB		 8018
8019 return 0;
8020}
8021
8022/**
8023 * i40e_vsi_delete - Delete a VSI from the switch
8024 * @vsi: the VSI being removed
8025 *
8026 * Returns 0 on success, negative value on failure
8027 **/
8028static void i40e_vsi_delete(struct i40e_vsi *vsi)
8029{
8030 /* remove default VSI is not allowed */
8031 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8032 return;
8033
41c445ff 8034 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8035}
8036
51616018
NP		 8037/**
8038 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8039 * @vsi: the VSI being queried
8040 *
8041 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8042 **/
8043int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8044{
8045 struct i40e_veb *veb;
8046 struct i40e_pf *pf = vsi->back;
8047
8048 /* Uplink is not a bridge so default to VEB */
8049 if (vsi->veb_idx == I40E_NO_VEB)
8050 return 1;
8051
8052 veb = pf->veb[vsi->veb_idx];
8053 /* Uplink is a bridge in VEPA mode */
8054 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8055 return 0;
8056
8057 /* Uplink is a bridge in VEB mode */
8058 return 1;
8059}
8060
41c445ff
JB		 8061/**
8062 * i40e_add_vsi - Add a VSI to the switch
8063 * @vsi: the VSI being configured
8064 *
8065 * This initializes a VSI context depending on the VSI type to be added and
8066 * passes it down to the add_vsi aq command.
8067 **/
8068static int i40e_add_vsi(struct i40e_vsi *vsi)
8069{
8070 int ret = -ENODEV;
8071 struct i40e_mac_filter *f, *ftmp;
8072 struct i40e_pf *pf = vsi->back;
8073 struct i40e_hw *hw = &pf->hw;
8074 struct i40e_vsi_context ctxt;
8075 u8 enabled_tc = 0x1; /* TC0 enabled */
8076 int f_count = 0;
8077
8078 memset(&ctxt, 0, sizeof(ctxt));
8079 switch (vsi->type) {
8080 case I40E_VSI_MAIN:
8081 /* The PF's main VSI is already setup as part of the
8082 * device initialization, so we'll not bother with
8083 * the add_vsi call, but we will retrieve the current
8084 * VSI context.
8085 */
8086 ctxt.seid = pf->main_vsi_seid;
8087 ctxt.pf_num = pf->hw.pf_id;
8088 ctxt.vf_num = 0;
8089 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8090 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8091 if (ret) {
8092 dev_info(&pf->pdev->dev,
8093 "couldn't get pf vsi config, err %d, aq_err %d\n",
8094 ret, pf->hw.aq.asq_last_status);
8095 return -ENOENT;
8096 }
8097 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
8098 vsi->info.valid_sections = 0;
8099
8100 vsi->seid = ctxt.seid;
8101 vsi->id = ctxt.vsi_number;
8102
8103 enabled_tc = i40e_pf_get_tc_map(pf);
8104
8105 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8106 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8107 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8108 memset(&ctxt, 0, sizeof(ctxt));
8109 ctxt.seid = pf->main_vsi_seid;
8110 ctxt.pf_num = pf->hw.pf_id;
8111 ctxt.vf_num = 0;
8112 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8113 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8114 if (ret) {
8115 dev_info(&pf->pdev->dev,
8116 "update vsi failed, aq_err=%d\n",
8117 pf->hw.aq.asq_last_status);
8118 ret = -ENOENT;
8119 goto err;
8120 }
8121 /* update the local VSI info queue map */
8122 i40e_vsi_update_queue_map(vsi, &ctxt);
8123 vsi->info.valid_sections = 0;
8124 } else {
8125 /* Default/Main VSI is only enabled for TC0
8126 * reconfigure it to enable all TCs that are
8127 * available on the port in SFP mode.
63d7e5a4
NP		 8128 * For MFP case the iSCSI PF would use this
8129 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8130 */
8131 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8132 if (ret) {
8133 dev_info(&pf->pdev->dev,
8134 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
8135 enabled_tc, ret,
8136 pf->hw.aq.asq_last_status);
8137 ret = -ENOENT;
8138 }
8139 }
8140 break;
8141
8142 case I40E_VSI_FDIR:
cbf61325
ASJ		 8143 ctxt.pf_num = hw->pf_id;
8144 ctxt.vf_num = 0;
8145 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8146 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8147 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
51616018
NP		 8148 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8149 ctxt.info.valid_sections |=
79c21a82 8150 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8151 ctxt.info.switch_id =
79c21a82 8152 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8153 }
41c445ff 8154 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8155 break;
8156
8157 case I40E_VSI_VMDQ2:
8158 ctxt.pf_num = hw->pf_id;
8159 ctxt.vf_num = 0;
8160 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8161 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8162 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8163
41c445ff
JB		 8164 /* This VSI is connected to VEB so the switch_id
8165 * should be set to zero by default.
8166 */
51616018
NP		 8167 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8168 ctxt.info.valid_sections |=
8169 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8170 ctxt.info.switch_id =
8171 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8172 }
41c445ff
JB		 8173
8174 /* Setup the VSI tx/rx queue map for TC0 only for now */
8175 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8176 break;
8177
8178 case I40E_VSI_SRIOV:
8179 ctxt.pf_num = hw->pf_id;
8180 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8181 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8182 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8183 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8184
41c445ff
JB		 8185 /* This VSI is connected to VEB so the switch_id
8186 * should be set to zero by default.
8187 */
51616018
NP		 8188 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8189 ctxt.info.valid_sections |=
8190 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8191 ctxt.info.switch_id =
8192 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8193 }
41c445ff
JB		 8194
8195 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8196 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8197 if (pf->vf[vsi->vf_id].spoofchk) {
8198 ctxt.info.valid_sections |=
8199 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8200 ctxt.info.sec_flags |=
8201 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8202 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8203 }
41c445ff
JB		 8204 /* Setup the VSI tx/rx queue map for TC0 only for now */
8205 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8206 break;
8207
38e00438
VD		 8208#ifdef I40E_FCOE
8209 case I40E_VSI_FCOE:
8210 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8211 if (ret) {
8212 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8213 return ret;
8214 }
8215 break;
8216
8217#endif /* I40E_FCOE */
41c445ff
JB		 8218 default:
8219 return -ENODEV;
8220 }
8221
8222 if (vsi->type != I40E_VSI_MAIN) {
8223 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8224 if (ret) {
8225 dev_info(&vsi->back->pdev->dev,
8226 "add vsi failed, aq_err=%d\n",
8227 vsi->back->hw.aq.asq_last_status);
8228 ret = -ENOENT;
8229 goto err;
8230 }
8231 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
8232 vsi->info.valid_sections = 0;
8233 vsi->seid = ctxt.seid;
8234 vsi->id = ctxt.vsi_number;
8235 }
8236
8237 /* If macvlan filters already exist, force them to get loaded */
8238 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8239 f->changed = true;
8240 f_count++;
6252c7e4
SN		 8241
8242 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8243 struct i40e_aqc_remove_macvlan_element_data element;
8244
8245 memset(&element, 0, sizeof(element));
8246 ether_addr_copy(element.mac_addr, f->macaddr);
8247 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8248 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8249 &element, 1, NULL);
8250 if (ret) {
8251 /* some older FW has a different default */
8252 element.flags |=
8253 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8254 i40e_aq_remove_macvlan(hw, vsi->seid,
8255 &element, 1, NULL);
8256 }
8257
8258 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8259 I40E_AQC_WRITE_TYPE_LAA_WOL,
8260 f->macaddr, NULL);
8261 }
41c445ff
JB		 8262 }
8263 if (f_count) {
8264 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8265 pf->flags |= I40E_FLAG_FILTER_SYNC;
8266 }
8267
8268 /* Update VSI BW information */
8269 ret = i40e_vsi_get_bw_info(vsi);
8270 if (ret) {
8271 dev_info(&pf->pdev->dev,
8272 "couldn't get vsi bw info, err %d, aq_err %d\n",
8273 ret, pf->hw.aq.asq_last_status);
8274 /* VSI is already added so not tearing that up */
8275 ret = 0;
8276 }
8277
8278err:
8279 return ret;
8280}
8281
8282/**
8283 * i40e_vsi_release - Delete a VSI and free its resources
8284 * @vsi: the VSI being removed
8285 *
8286 * Returns 0 on success or < 0 on error
8287 **/
8288int i40e_vsi_release(struct i40e_vsi *vsi)
8289{
8290 struct i40e_mac_filter *f, *ftmp;
8291 struct i40e_veb *veb = NULL;
8292 struct i40e_pf *pf;
8293 u16 uplink_seid;
8294 int i, n;
8295
8296 pf = vsi->back;
8297
8298 /* release of a VEB-owner or last VSI is not allowed */
8299 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8300 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8301 vsi->seid, vsi->uplink_seid);
8302 return -ENODEV;
8303 }
8304 if (vsi == pf->vsi[pf->lan_vsi] &&
8305 !test_bit(__I40E_DOWN, &pf->state)) {
8306 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8307 return -ENODEV;
8308 }
8309
8310 uplink_seid = vsi->uplink_seid;
8311 if (vsi->type != I40E_VSI_SRIOV) {
8312 if (vsi->netdev_registered) {
8313 vsi->netdev_registered = false;
8314 if (vsi->netdev) {
8315 /* results in a call to i40e_close() */
8316 unregister_netdev(vsi->netdev);
41c445ff
JB		 8317 }
8318 } else {
90ef8d47 8319 i40e_vsi_close(vsi);
41c445ff
JB		 8320 }
8321 i40e_vsi_disable_irq(vsi);
8322 }
8323
8324 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8325 i40e_del_filter(vsi, f->macaddr, f->vlan,
8326 f->is_vf, f->is_netdev);
8327 i40e_sync_vsi_filters(vsi);
8328
8329 i40e_vsi_delete(vsi);
8330 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8331 if (vsi->netdev) {
8332 free_netdev(vsi->netdev);
8333 vsi->netdev = NULL;
8334 }
41c445ff
JB		 8335 i40e_vsi_clear_rings(vsi);
8336 i40e_vsi_clear(vsi);
8337
8338 /* If this was the last thing on the VEB, except for the
8339 * controlling VSI, remove the VEB, which puts the controlling
8340 * VSI onto the next level down in the switch.
8341 *
8342 * Well, okay, there's one more exception here: don't remove
8343 * the orphan VEBs yet. We'll wait for an explicit remove request
8344 * from up the network stack.
8345 */
505682cd 8346 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8347 if (pf->vsi[i] &&
8348 pf->vsi[i]->uplink_seid == uplink_seid &&
8349 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8350 n++; /* count the VSIs */
8351 }
8352 }
8353 for (i = 0; i < I40E_MAX_VEB; i++) {
8354 if (!pf->veb[i])
8355 continue;
8356 if (pf->veb[i]->uplink_seid == uplink_seid)
8357 n++; /* count the VEBs */
8358 if (pf->veb[i]->seid == uplink_seid)
8359 veb = pf->veb[i];
8360 }
8361 if (n == 0 && veb && veb->uplink_seid != 0)
8362 i40e_veb_release(veb);
8363
8364 return 0;
8365}
8366
8367/**
8368 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8369 * @vsi: ptr to the VSI
8370 *
8371 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8372 * corresponding SW VSI structure and initializes num_queue_pairs for the
8373 * newly allocated VSI.
8374 *
8375 * Returns 0 on success or negative on failure
8376 **/
8377static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8378{
8379 int ret = -ENOENT;
8380 struct i40e_pf *pf = vsi->back;
8381
493fb300 8382 if (vsi->q_vectors[0]) {
41c445ff
JB		 8383 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8384 vsi->seid);
8385 return -EEXIST;
8386 }
8387
8388 if (vsi->base_vector) {
f29eaa3d 8389 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8390 vsi->seid, vsi->base_vector);
8391 return -EEXIST;
8392 }
8393
90e04070 8394 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8395 if (ret) {
8396 dev_info(&pf->pdev->dev,
8397 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8398 vsi->num_q_vectors, vsi->seid, ret);
8399 vsi->num_q_vectors = 0;
8400 goto vector_setup_out;
8401 }
8402
958a3e3b
SN		 8403 if (vsi->num_q_vectors)
8404 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8405 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8406 if (vsi->base_vector < 0) {
8407 dev_info(&pf->pdev->dev,
049a2be8
SN		 8408 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8409 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8410 i40e_vsi_free_q_vectors(vsi);
8411 ret = -ENOENT;
8412 goto vector_setup_out;
8413 }
8414
8415vector_setup_out:
8416 return ret;
8417}
8418
bc7d338f
ASJ		 8419/**
8420 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8421 * @vsi: pointer to the vsi.
8422 *
8423 * This re-allocates a vsi's queue resources.
8424 *
8425 * Returns pointer to the successfully allocated and configured VSI sw struct
8426 * on success, otherwise returns NULL on failure.
8427 **/
8428static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8429{
8430 struct i40e_pf *pf = vsi->back;
8431 u8 enabled_tc;
8432 int ret;
8433
8434 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8435 i40e_vsi_clear_rings(vsi);
8436
8437 i40e_vsi_free_arrays(vsi, false);
8438 i40e_set_num_rings_in_vsi(vsi);
8439 ret = i40e_vsi_alloc_arrays(vsi, false);
8440 if (ret)
8441 goto err_vsi;
8442
8443 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8444 if (ret < 0) {
049a2be8
SN		 8445 dev_info(&pf->pdev->dev,
8446 "failed to get tracking for %d queues for VSI %d err=%d\n",
8447 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8448 goto err_vsi;
8449 }
8450 vsi->base_queue = ret;
8451
8452 /* Update the FW view of the VSI. Force a reset of TC and queue
8453 * layout configurations.
8454 */
8455 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8456 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8457 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8458 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8459
8460 /* assign it some queues */
8461 ret = i40e_alloc_rings(vsi);
8462 if (ret)
8463 goto err_rings;
8464
8465 /* map all of the rings to the q_vectors */
8466 i40e_vsi_map_rings_to_vectors(vsi);
8467 return vsi;
8468
8469err_rings:
8470 i40e_vsi_free_q_vectors(vsi);
8471 if (vsi->netdev_registered) {
8472 vsi->netdev_registered = false;
8473 unregister_netdev(vsi->netdev);
8474 free_netdev(vsi->netdev);
8475 vsi->netdev = NULL;
8476 }
8477 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8478err_vsi:
8479 i40e_vsi_clear(vsi);
8480 return NULL;
8481}
8482
41c445ff
JB		 8483/**
8484 * i40e_vsi_setup - Set up a VSI by a given type
8485 * @pf: board private structure
8486 * @type: VSI type
8487 * @uplink_seid: the switch element to link to
8488 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8489 *
8490 * This allocates the sw VSI structure and its queue resources, then add a VSI
8491 * to the identified VEB.
8492 *
8493 * Returns pointer to the successfully allocated and configure VSI sw struct on
8494 * success, otherwise returns NULL on failure.
8495 **/
8496struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8497 u16 uplink_seid, u32 param1)
8498{
8499 struct i40e_vsi *vsi = NULL;
8500 struct i40e_veb *veb = NULL;
8501 int ret, i;
8502 int v_idx;
8503
8504 /* The requested uplink_seid must be either
8505 * - the PF's port seid
8506 * no VEB is needed because this is the PF
8507 * or this is a Flow Director special case VSI
8508 * - seid of an existing VEB
8509 * - seid of a VSI that owns an existing VEB
8510 * - seid of a VSI that doesn't own a VEB
8511 * a new VEB is created and the VSI becomes the owner
8512 * - seid of the PF VSI, which is what creates the first VEB
8513 * this is a special case of the previous
8514 *
8515 * Find which uplink_seid we were given and create a new VEB if needed
8516 */
8517 for (i = 0; i < I40E_MAX_VEB; i++) {
8518 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8519 veb = pf->veb[i];
8520 break;
8521 }
8522 }
8523
8524 if (!veb && uplink_seid != pf->mac_seid) {
8525
505682cd 8526 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8527 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8528 vsi = pf->vsi[i];
8529 break;
8530 }
8531 }
8532 if (!vsi) {
8533 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8534 uplink_seid);
8535 return NULL;
8536 }
8537
8538 if (vsi->uplink_seid == pf->mac_seid)
8539 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8540 vsi->tc_config.enabled_tc);
8541 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8542 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8543 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 8544 if (veb) {
8545 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
8546 dev_info(&vsi->back->pdev->dev,
8547 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
8548 __func__);
8549 return NULL;
8550 }
51616018 8551 i40e_config_bridge_mode(veb);
79c21a82 8552 }
41c445ff
JB		 8553 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8554 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8555 veb = pf->veb[i];
8556 }
8557 if (!veb) {
8558 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8559 return NULL;
8560 }
8561
8562 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8563 uplink_seid = veb->seid;
8564 }
8565
8566 /* get vsi sw struct */
8567 v_idx = i40e_vsi_mem_alloc(pf, type);
8568 if (v_idx < 0)
8569 goto err_alloc;
8570 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8571 if (!vsi)
8572 goto err_alloc;
41c445ff
JB		 8573 vsi->type = type;
8574 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8575
8576 if (type == I40E_VSI_MAIN)
8577 pf->lan_vsi = v_idx;
8578 else if (type == I40E_VSI_SRIOV)
8579 vsi->vf_id = param1;
8580 /* assign it some queues */
cbf61325
ASJ		 8581 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8582 vsi->idx);
41c445ff 8583 if (ret < 0) {
049a2be8
SN		 8584 dev_info(&pf->pdev->dev,
8585 "failed to get tracking for %d queues for VSI %d err=%d\n",
8586 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 8587 goto err_vsi;
8588 }
8589 vsi->base_queue = ret;
8590
8591 /* get a VSI from the hardware */
8592 vsi->uplink_seid = uplink_seid;
8593 ret = i40e_add_vsi(vsi);
8594 if (ret)
8595 goto err_vsi;
8596
8597 switch (vsi->type) {
8598 /* setup the netdev if needed */
8599 case I40E_VSI_MAIN:
8600 case I40E_VSI_VMDQ2:
38e00438 8601 case I40E_VSI_FCOE:
41c445ff
JB		 8602 ret = i40e_config_netdev(vsi);
8603 if (ret)
8604 goto err_netdev;
8605 ret = register_netdev(vsi->netdev);
8606 if (ret)
8607 goto err_netdev;
8608 vsi->netdev_registered = true;
8609 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8610#ifdef CONFIG_I40E_DCB
8611 /* Setup DCB netlink interface */
8612 i40e_dcbnl_setup(vsi);
8613#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8614 /* fall through */
8615
8616 case I40E_VSI_FDIR:
8617 /* set up vectors and rings if needed */
8618 ret = i40e_vsi_setup_vectors(vsi);
8619 if (ret)
8620 goto err_msix;
8621
8622 ret = i40e_alloc_rings(vsi);
8623 if (ret)
8624 goto err_rings;
8625
8626 /* map all of the rings to the q_vectors */
8627 i40e_vsi_map_rings_to_vectors(vsi);
8628
8629 i40e_vsi_reset_stats(vsi);
8630 break;
8631
8632 default:
8633 /* no netdev or rings for the other VSI types */
8634 break;
8635 }
8636
8637 return vsi;
8638
8639err_rings:
8640 i40e_vsi_free_q_vectors(vsi);
8641err_msix:
8642 if (vsi->netdev_registered) {
8643 vsi->netdev_registered = false;
8644 unregister_netdev(vsi->netdev);
8645 free_netdev(vsi->netdev);
8646 vsi->netdev = NULL;
8647 }
8648err_netdev:
8649 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8650err_vsi:
8651 i40e_vsi_clear(vsi);
8652err_alloc:
8653 return NULL;
8654}
8655
8656/**
8657 * i40e_veb_get_bw_info - Query VEB BW information
8658 * @veb: the veb to query
8659 *
8660 * Query the Tx scheduler BW configuration data for given VEB
8661 **/
8662static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8663{
8664 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8665 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8666 struct i40e_pf *pf = veb->pf;
8667 struct i40e_hw *hw = &pf->hw;
8668 u32 tc_bw_max;
8669 int ret = 0;
8670 int i;
8671
8672 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8673 &bw_data, NULL);
8674 if (ret) {
8675 dev_info(&pf->pdev->dev,
8676 "query veb bw config failed, aq_err=%d\n",
8677 hw->aq.asq_last_status);
8678 goto out;
8679 }
8680
8681 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8682 &ets_data, NULL);
8683 if (ret) {
8684 dev_info(&pf->pdev->dev,
8685 "query veb bw ets config failed, aq_err=%d\n",
8686 hw->aq.asq_last_status);
8687 goto out;
8688 }
8689
8690 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8691 veb->bw_max_quanta = ets_data.tc_bw_max;
8692 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 8693 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 8694 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8695 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8696 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8697 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8698 veb->bw_tc_limit_credits[i] =
8699 le16_to_cpu(bw_data.tc_bw_limits[i]);
8700 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8701 }
8702
8703out:
8704 return ret;
8705}
8706
8707/**
8708 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8709 * @pf: board private structure
8710 *
8711 * On error: returns error code (negative)
8712 * On success: returns vsi index in PF (positive)
8713 **/
8714static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8715{
8716 int ret = -ENOENT;
8717 struct i40e_veb *veb;
8718 int i;
8719
8720 /* Need to protect the allocation of switch elements at the PF level */
8721 mutex_lock(&pf->switch_mutex);
8722
8723 /* VEB list may be fragmented if VEB creation/destruction has
8724 * been happening. We can afford to do a quick scan to look
8725 * for any free slots in the list.
8726 *
8727 * find next empty veb slot, looping back around if necessary
8728 */
8729 i = 0;
8730 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8731 i++;
8732 if (i >= I40E_MAX_VEB) {
8733 ret = -ENOMEM;
8734 goto err_alloc_veb; /* out of VEB slots! */
8735 }
8736
8737 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8738 if (!veb) {
8739 ret = -ENOMEM;
8740 goto err_alloc_veb;
8741 }
8742 veb->pf = pf;
8743 veb->idx = i;
8744 veb->enabled_tc = 1;
8745
8746 pf->veb[i] = veb;
8747 ret = i;
8748err_alloc_veb:
8749 mutex_unlock(&pf->switch_mutex);
8750 return ret;
8751}
8752
8753/**
8754 * i40e_switch_branch_release - Delete a branch of the switch tree
8755 * @branch: where to start deleting
8756 *
8757 * This uses recursion to find the tips of the branch to be
8758 * removed, deleting until we get back to and can delete this VEB.
8759 **/
8760static void i40e_switch_branch_release(struct i40e_veb *branch)
8761{
8762 struct i40e_pf *pf = branch->pf;
8763 u16 branch_seid = branch->seid;
8764 u16 veb_idx = branch->idx;
8765 int i;
8766
8767 /* release any VEBs on this VEB - RECURSION */
8768 for (i = 0; i < I40E_MAX_VEB; i++) {
8769 if (!pf->veb[i])
8770 continue;
8771 if (pf->veb[i]->uplink_seid == branch->seid)
8772 i40e_switch_branch_release(pf->veb[i]);
8773 }
8774
8775 /* Release the VSIs on this VEB, but not the owner VSI.
8776 *
8777 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8778 * the VEB itself, so don't use (*branch) after this loop.
8779 */
505682cd 8780 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8781 if (!pf->vsi[i])
8782 continue;
8783 if (pf->vsi[i]->uplink_seid == branch_seid &&
8784 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8785 i40e_vsi_release(pf->vsi[i]);
8786 }
8787 }
8788
8789 /* There's one corner case where the VEB might not have been
8790 * removed, so double check it here and remove it if needed.
8791 * This case happens if the veb was created from the debugfs
8792 * commands and no VSIs were added to it.
8793 */
8794 if (pf->veb[veb_idx])
8795 i40e_veb_release(pf->veb[veb_idx]);
8796}
8797
8798/**
8799 * i40e_veb_clear - remove veb struct
8800 * @veb: the veb to remove
8801 **/
8802static void i40e_veb_clear(struct i40e_veb *veb)
8803{
8804 if (!veb)
8805 return;
8806
8807 if (veb->pf) {
8808 struct i40e_pf *pf = veb->pf;
8809
8810 mutex_lock(&pf->switch_mutex);
8811 if (pf->veb[veb->idx] == veb)
8812 pf->veb[veb->idx] = NULL;
8813 mutex_unlock(&pf->switch_mutex);
8814 }
8815
8816 kfree(veb);
8817}
8818
8819/**
8820 * i40e_veb_release - Delete a VEB and free its resources
8821 * @veb: the VEB being removed
8822 **/
8823void i40e_veb_release(struct i40e_veb *veb)
8824{
8825 struct i40e_vsi *vsi = NULL;
8826 struct i40e_pf *pf;
8827 int i, n = 0;
8828
8829 pf = veb->pf;
8830
8831 /* find the remaining VSI and check for extras */
505682cd 8832 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8833 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
8834 n++;
8835 vsi = pf->vsi[i];
8836 }
8837 }
8838 if (n != 1) {
8839 dev_info(&pf->pdev->dev,
8840 "can't remove VEB %d with %d VSIs left\n",
8841 veb->seid, n);
8842 return;
8843 }
8844
8845 /* move the remaining VSI to uplink veb */
8846 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8847 if (veb->uplink_seid) {
8848 vsi->uplink_seid = veb->uplink_seid;
8849 if (veb->uplink_seid == pf->mac_seid)
8850 vsi->veb_idx = I40E_NO_VEB;
8851 else
8852 vsi->veb_idx = veb->veb_idx;
8853 } else {
8854 /* floating VEB */
8855 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8856 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8857 }
8858
8859 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8860 i40e_veb_clear(veb);
41c445ff
JB		 8861}
8862
8863/**
8864 * i40e_add_veb - create the VEB in the switch
8865 * @veb: the VEB to be instantiated
8866 * @vsi: the controlling VSI
8867 **/
8868static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8869{
56747264 8870 bool is_default = false;
e1c51b95 8871 bool is_cloud = false;
41c445ff
JB		 8872 int ret;
8873
8874 /* get a VEB from the hardware */
8875 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8876 veb->enabled_tc, is_default,
8877 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8878 if (ret) {
8879 dev_info(&veb->pf->pdev->dev,
8880 "couldn't add VEB, err %d, aq_err %d\n",
8881 ret, veb->pf->hw.aq.asq_last_status);
8882 return -EPERM;
8883 }
8884
8885 /* get statistics counter */
8886 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8887 &veb->stats_idx, NULL, NULL, NULL);
8888 if (ret) {
8889 dev_info(&veb->pf->pdev->dev,
8890 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8891 ret, veb->pf->hw.aq.asq_last_status);
8892 return -EPERM;
8893 }
8894 ret = i40e_veb_get_bw_info(veb);
8895 if (ret) {
8896 dev_info(&veb->pf->pdev->dev,
8897 "couldn't get VEB bw info, err %d, aq_err %d\n",
8898 ret, veb->pf->hw.aq.asq_last_status);
8899 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8900 return -ENOENT;
8901 }
8902
8903 vsi->uplink_seid = veb->seid;
8904 vsi->veb_idx = veb->idx;
8905 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8906
8907 return 0;
8908}
8909
8910/**
8911 * i40e_veb_setup - Set up a VEB
8912 * @pf: board private structure
8913 * @flags: VEB setup flags
8914 * @uplink_seid: the switch element to link to
8915 * @vsi_seid: the initial VSI seid
8916 * @enabled_tc: Enabled TC bit-map
8917 *
8918 * This allocates the sw VEB structure and links it into the switch
8919 * It is possible and legal for this to be a duplicate of an already
8920 * existing VEB. It is also possible for both uplink and vsi seids
8921 * to be zero, in order to create a floating VEB.
8922 *
8923 * Returns pointer to the successfully allocated VEB sw struct on
8924 * success, otherwise returns NULL on failure.
8925 **/
8926struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8927 u16 uplink_seid, u16 vsi_seid,
8928 u8 enabled_tc)
8929{
8930 struct i40e_veb *veb, *uplink_veb = NULL;
8931 int vsi_idx, veb_idx;
8932 int ret;
8933
8934 /* if one seid is 0, the other must be 0 to create a floating relay */
8935 if ((uplink_seid == 0 || vsi_seid == 0) &&
8936 (uplink_seid + vsi_seid != 0)) {
8937 dev_info(&pf->pdev->dev,
8938 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8939 uplink_seid, vsi_seid);
8940 return NULL;
8941 }
8942
8943 /* make sure there is such a vsi and uplink */
505682cd 8944 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8945 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8946 break;
505682cd 8947 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8948 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8949 vsi_seid);
8950 return NULL;
8951 }
8952
8953 if (uplink_seid && uplink_seid != pf->mac_seid) {
8954 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8955 if (pf->veb[veb_idx] &&
8956 pf->veb[veb_idx]->seid == uplink_seid) {
8957 uplink_veb = pf->veb[veb_idx];
8958 break;
8959 }
8960 }
8961 if (!uplink_veb) {
8962 dev_info(&pf->pdev->dev,
8963 "uplink seid %d not found\n", uplink_seid);
8964 return NULL;
8965 }
8966 }
8967
8968 /* get veb sw struct */
8969 veb_idx = i40e_veb_mem_alloc(pf);
8970 if (veb_idx < 0)
8971 goto err_alloc;
8972 veb = pf->veb[veb_idx];
8973 veb->flags = flags;
8974 veb->uplink_seid = uplink_seid;
8975 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8976 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8977
8978 /* create the VEB in the switch */
8979 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8980 if (ret)
8981 goto err_veb;
1bb8b935
SN		 8982 if (vsi_idx == pf->lan_vsi)
8983 pf->lan_veb = veb->idx;
41c445ff
JB		 8984
8985 return veb;
8986
8987err_veb:
8988 i40e_veb_clear(veb);
8989err_alloc:
8990 return NULL;
8991}
8992
8993/**
8994 * i40e_setup_pf_switch_element - set pf vars based on switch type
8995 * @pf: board private structure
8996 * @ele: element we are building info from
8997 * @num_reported: total number of elements
8998 * @printconfig: should we print the contents
8999 *
9000 * helper function to assist in extracting a few useful SEID values.
9001 **/
9002static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9003 struct i40e_aqc_switch_config_element_resp *ele,
9004 u16 num_reported, bool printconfig)
9005{
9006 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9007 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9008 u8 element_type = ele->element_type;
9009 u16 seid = le16_to_cpu(ele->seid);
9010
9011 if (printconfig)
9012 dev_info(&pf->pdev->dev,
9013 "type=%d seid=%d uplink=%d downlink=%d\n",
9014 element_type, seid, uplink_seid, downlink_seid);
9015
9016 switch (element_type) {
9017 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9018 pf->mac_seid = seid;
9019 break;
9020 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9021 /* Main VEB? */
9022 if (uplink_seid != pf->mac_seid)
9023 break;
9024 if (pf->lan_veb == I40E_NO_VEB) {
9025 int v;
9026
9027 /* find existing or else empty VEB */
9028 for (v = 0; v < I40E_MAX_VEB; v++) {
9029 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9030 pf->lan_veb = v;
9031 break;
9032 }
9033 }
9034 if (pf->lan_veb == I40E_NO_VEB) {
9035 v = i40e_veb_mem_alloc(pf);
9036 if (v < 0)
9037 break;
9038 pf->lan_veb = v;
9039 }
9040 }
9041
9042 pf->veb[pf->lan_veb]->seid = seid;
9043 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9044 pf->veb[pf->lan_veb]->pf = pf;
9045 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9046 break;
9047 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9048 if (num_reported != 1)
9049 break;
9050 /* This is immediately after a reset so we can assume this is
9051 * the PF's VSI
9052 */
9053 pf->mac_seid = uplink_seid;
9054 pf->pf_seid = downlink_seid;
9055 pf->main_vsi_seid = seid;
9056 if (printconfig)
9057 dev_info(&pf->pdev->dev,
9058 "pf_seid=%d main_vsi_seid=%d\n",
9059 pf->pf_seid, pf->main_vsi_seid);
9060 break;
9061 case I40E_SWITCH_ELEMENT_TYPE_PF:
9062 case I40E_SWITCH_ELEMENT_TYPE_VF:
9063 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9064 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9065 case I40E_SWITCH_ELEMENT_TYPE_PE:
9066 case I40E_SWITCH_ELEMENT_TYPE_PA:
9067 /* ignore these for now */
9068 break;
9069 default:
9070 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9071 element_type, seid);
9072 break;
9073 }
9074}
9075
9076/**
9077 * i40e_fetch_switch_configuration - Get switch config from firmware
9078 * @pf: board private structure
9079 * @printconfig: should we print the contents
9080 *
9081 * Get the current switch configuration from the device and
9082 * extract a few useful SEID values.
9083 **/
9084int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9085{
9086 struct i40e_aqc_get_switch_config_resp *sw_config;
9087 u16 next_seid = 0;
9088 int ret = 0;
9089 u8 *aq_buf;
9090 int i;
9091
9092 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9093 if (!aq_buf)
9094 return -ENOMEM;
9095
9096 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9097 do {
9098 u16 num_reported, num_total;
9099
9100 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9101 I40E_AQ_LARGE_BUF,
9102 &next_seid, NULL);
9103 if (ret) {
9104 dev_info(&pf->pdev->dev,
9105 "get switch config failed %d aq_err=%x\n",
9106 ret, pf->hw.aq.asq_last_status);
9107 kfree(aq_buf);
9108 return -ENOENT;
9109 }
9110
9111 num_reported = le16_to_cpu(sw_config->header.num_reported);
9112 num_total = le16_to_cpu(sw_config->header.num_total);
9113
9114 if (printconfig)
9115 dev_info(&pf->pdev->dev,
9116 "header: %d reported %d total\n",
9117 num_reported, num_total);
9118
41c445ff
JB		 9119 for (i = 0; i < num_reported; i++) {
9120 struct i40e_aqc_switch_config_element_resp *ele =
9121 &sw_config->element[i];
9122
9123 i40e_setup_pf_switch_element(pf, ele, num_reported,
9124 printconfig);
9125 }
9126 } while (next_seid != 0);
9127
9128 kfree(aq_buf);
9129 return ret;
9130}
9131
9132/**
9133 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9134 * @pf: board private structure
bc7d338f 9135 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9136 *
9137 * Returns 0 on success, negative value on failure
9138 **/
bc7d338f 9139static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9140{
9141 int ret;
9142
9143 /* find out what's out there already */
9144 ret = i40e_fetch_switch_configuration(pf, false);
9145 if (ret) {
9146 dev_info(&pf->pdev->dev,
9147 "couldn't fetch switch config, err %d, aq_err %d\n",
9148 ret, pf->hw.aq.asq_last_status);
9149 return ret;
9150 }
9151 i40e_pf_reset_stats(pf);
9152
41c445ff 9153 /* first time setup */
bc7d338f 9154 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9155 struct i40e_vsi *vsi = NULL;
9156 u16 uplink_seid;
9157
9158 /* Set up the PF VSI associated with the PF's main VSI
9159 * that is already in the HW switch
9160 */
9161 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9162 uplink_seid = pf->veb[pf->lan_veb]->seid;
9163 else
9164 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9165 if (pf->lan_vsi == I40E_NO_VSI)
9166 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9167 else if (reinit)
9168 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9169 if (!vsi) {
9170 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9171 i40e_fdir_teardown(pf);
9172 return -EAGAIN;
9173 }
41c445ff
JB		 9174 } else {
9175 /* force a reset of TC and queue layout configurations */
9176 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9177 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9178 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9179 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9180 }
9181 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9182
cbf61325
ASJ		 9183 i40e_fdir_sb_setup(pf);
9184
41c445ff
JB		 9185 /* Setup static PF queue filter control settings */
9186 ret = i40e_setup_pf_filter_control(pf);
9187 if (ret) {
9188 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9189 ret);
9190 /* Failure here should not stop continuing other steps */
9191 }
9192
9193 /* enable RSS in the HW, even for only one queue, as the stack can use
9194 * the hash
9195 */
9196 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9197 i40e_config_rss(pf);
9198
9199 /* fill in link information and enable LSE reporting */
21af70fb 9200 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9201 i40e_link_event(pf);
9202
9203 /* Initialize user-specific link properties */
9204 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9205 I40E_AQ_AN_COMPLETED) ? true : false);
9206
9207 /* fill in link information and enable LSE reporting */
21af70fb 9208 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
41c445ff
JB		 9209 i40e_link_event(pf);
9210
d52c20b7 9211 /* Initialize user-specific link properties */
41c445ff
JB		 9212 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9213 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9214
beb0dff1
JK		 9215 i40e_ptp_init(pf);
9216
41c445ff
JB		 9217 return ret;
9218}
9219
41c445ff
JB		 9220/**
9221 * i40e_determine_queue_usage - Work out queue distribution
9222 * @pf: board private structure
9223 **/
9224static void i40e_determine_queue_usage(struct i40e_pf *pf)
9225{
41c445ff
JB		 9226 int queues_left;
9227
9228 pf->num_lan_qps = 0;
38e00438
VD		 9229#ifdef I40E_FCOE
9230 pf->num_fcoe_qps = 0;
9231#endif
41c445ff
JB		 9232
9233 /* Find the max queues to be put into basic use. We'll always be
9234 * using TC0, whether or not DCB is running, and TC0 will get the
9235 * big RSS set.
9236 */
9237 queues_left = pf->hw.func_caps.num_tx_qp;
9238
cbf61325 9239 if ((queues_left == 1) ||
9aa7e935 9240 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9241 /* one qp for PF, no queues for anything else */
9242 queues_left = 0;
9243 pf->rss_size = pf->num_lan_qps = 1;
9244
9245 /* make sure all the fancies are disabled */
60ea5f83 9246 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9247#ifdef I40E_FCOE
9248 I40E_FLAG_FCOE_ENABLED |
9249#endif
60ea5f83
JB		 9250 I40E_FLAG_FD_SB_ENABLED |
9251 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9252 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9253 I40E_FLAG_SRIOV_ENABLED |
9254 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9255 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9256 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9257 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9258 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9259 /* one qp for PF */
9260 pf->rss_size = pf->num_lan_qps = 1;
9261 queues_left -= pf->num_lan_qps;
9262
9263 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9264#ifdef I40E_FCOE
9265 I40E_FLAG_FCOE_ENABLED |
9266#endif
9aa7e935
FZ		 9267 I40E_FLAG_FD_SB_ENABLED |
9268 I40E_FLAG_FD_ATR_ENABLED |
9269 I40E_FLAG_DCB_ENABLED |
9270 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9271 } else {
cbf61325 9272 /* Not enough queues for all TCs */
4d9b6043 9273 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9274 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9275 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9276 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9277 }
9a3bd2f1
ASJ		 9278 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9279 num_online_cpus());
9280 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9281 pf->hw.func_caps.num_tx_qp);
9282
cbf61325
ASJ		 9283 queues_left -= pf->num_lan_qps;
9284 }
9285
38e00438
VD		 9286#ifdef I40E_FCOE
9287 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9288 if (I40E_DEFAULT_FCOE <= queues_left) {
9289 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9290 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9291 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9292 } else {
9293 pf->num_fcoe_qps = 0;
9294 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9295 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9296 }
9297
9298 queues_left -= pf->num_fcoe_qps;
9299 }
9300
9301#endif
cbf61325
ASJ		 9302 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9303 if (queues_left > 1) {
9304 queues_left -= 1; /* save 1 queue for FD */
9305 } else {
9306 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9307 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9308 }
41c445ff
JB		 9309 }
9310
9311 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9312 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9313 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9314 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9315 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9316 }
9317
9318 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9319 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9320 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9321 (queues_left / pf->num_vmdq_qps));
9322 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9323 }
9324
f8ff1464 9325 pf->queues_left = queues_left;
38e00438
VD		 9326#ifdef I40E_FCOE
9327 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9328#endif
41c445ff
JB		 9329}
9330
9331/**
9332 * i40e_setup_pf_filter_control - Setup PF static filter control
9333 * @pf: PF to be setup
9334 *
9335 * i40e_setup_pf_filter_control sets up a pf's initial filter control
9336 * settings. If PE/FCoE are enabled then it will also set the per PF
9337 * based filter sizes required for them. It also enables Flow director,
9338 * ethertype and macvlan type filter settings for the pf.
9339 *
9340 * Returns 0 on success, negative on failure
9341 **/
9342static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9343{
9344 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9345
9346 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9347
9348 /* Flow Director is enabled */
60ea5f83 9349 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9350 settings->enable_fdir = true;
9351
9352 /* Ethtype and MACVLAN filters enabled for PF */
9353 settings->enable_ethtype = true;
9354 settings->enable_macvlan = true;
9355
9356 if (i40e_set_filter_control(&pf->hw, settings))
9357 return -ENOENT;
9358
9359 return 0;
9360}
9361
0c22b3dd
JB		 9362#define INFO_STRING_LEN 255
9363static void i40e_print_features(struct i40e_pf *pf)
9364{
9365 struct i40e_hw *hw = &pf->hw;
9366 char *buf, *string;
9367
9368 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9369 if (!string) {
9370 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9371 return;
9372 }
9373
9374 buf = string;
9375
9376 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9377#ifdef CONFIG_PCI_IOV
9378 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9379#endif
aba237d1
MW		 9380 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9381 pf->hw.func_caps.num_vsis,
9382 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9383 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9384
9385 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9386 buf += sprintf(buf, "RSS ");
0c22b3dd 9387 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9388 buf += sprintf(buf, "FD_ATR ");
9389 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9390 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9391 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9392 }
4d9b6043 9393 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9394 buf += sprintf(buf, "DCB ");
9395 if (pf->flags & I40E_FLAG_PTP)
9396 buf += sprintf(buf, "PTP ");
38e00438
VD		 9397#ifdef I40E_FCOE
9398 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9399 buf += sprintf(buf, "FCOE ");
9400#endif
0c22b3dd
JB		 9401
9402 BUG_ON(buf > (string + INFO_STRING_LEN));
9403 dev_info(&pf->pdev->dev, "%s\n", string);
9404 kfree(string);
9405}
9406
41c445ff
JB		 9407/**
9408 * i40e_probe - Device initialization routine
9409 * @pdev: PCI device information struct
9410 * @ent: entry in i40e_pci_tbl
9411 *
9412 * i40e_probe initializes a pf identified by a pci_dev structure.
9413 * The OS initialization, configuring of the pf private structure,
9414 * and a hardware reset occur.
9415 *
9416 * Returns 0 on success, negative on failure
9417 **/
9418static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9419{
e827845c 9420 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 9421 struct i40e_pf *pf;
9422 struct i40e_hw *hw;
93cd765b 9423 static u16 pfs_found;
d4dfb81a 9424 u16 link_status;
41c445ff
JB		 9425 int err = 0;
9426 u32 len;
8a9eb7d3 9427 u32 i;
41c445ff
JB		 9428
9429 err = pci_enable_device_mem(pdev);
9430 if (err)
9431 return err;
9432
9433 /* set up for high or low dma */
6494294f 9434 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9435 if (err) {
e3e3bfdd
JS		 9436 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9437 if (err) {
9438 dev_err(&pdev->dev,
9439 "DMA configuration failed: 0x%x\n", err);
9440 goto err_dma;
9441 }
41c445ff
JB		 9442 }
9443
9444 /* set up pci connections */
9445 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9446 IORESOURCE_MEM), i40e_driver_name);
9447 if (err) {
9448 dev_info(&pdev->dev,
9449 "pci_request_selected_regions failed %d\n", err);
9450 goto err_pci_reg;
9451 }
9452
9453 pci_enable_pcie_error_reporting(pdev);
9454 pci_set_master(pdev);
9455
9456 /* Now that we have a PCI connection, we need to do the
9457 * low level device setup. This is primarily setting up
9458 * the Admin Queue structures and then querying for the
9459 * device's current profile information.
9460 */
9461 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9462 if (!pf) {
9463 err = -ENOMEM;
9464 goto err_pf_alloc;
9465 }
9466 pf->next_vsi = 0;
9467 pf->pdev = pdev;
9468 set_bit(__I40E_DOWN, &pf->state);
9469
9470 hw = &pf->hw;
9471 hw->back = pf;
9472 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9473 pci_resource_len(pdev, 0));
9474 if (!hw->hw_addr) {
9475 err = -EIO;
9476 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9477 (unsigned int)pci_resource_start(pdev, 0),
9478 (unsigned int)pci_resource_len(pdev, 0), err);
9479 goto err_ioremap;
9480 }
9481 hw->vendor_id = pdev->vendor;
9482 hw->device_id = pdev->device;
9483 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9484 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9485 hw->subsystem_device_id = pdev->subsystem_device;
9486 hw->bus.device = PCI_SLOT(pdev->devfn);
9487 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9488 pf->instance = pfs_found;
41c445ff 9489
5b5faa43
SN		 9490 if (debug != -1) {
9491 pf->msg_enable = pf->hw.debug_mask;
9492 pf->msg_enable = debug;
9493 }
9494
7134f9ce
JB		 9495 /* do a special CORER for clearing PXE mode once at init */
9496 if (hw->revision_id == 0 &&
9497 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9498 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9499 i40e_flush(hw);
9500 msleep(200);
9501 pf->corer_count++;
9502
9503 i40e_clear_pxe_mode(hw);
9504 }
9505
41c445ff 9506 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9507 i40e_clear_hw(hw);
41c445ff
JB		 9508 err = i40e_pf_reset(hw);
9509 if (err) {
9510 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9511 goto err_pf_reset;
9512 }
9513 pf->pfr_count++;
9514
9515 hw->aq.num_arq_entries = I40E_AQ_LEN;
9516 hw->aq.num_asq_entries = I40E_AQ_LEN;
9517 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9518 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9519 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 9520
b294ac70 9521 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 9522 "%s-%s:misc",
9523 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 9524
9525 err = i40e_init_shared_code(hw);
9526 if (err) {
9527 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9528 goto err_pf_reset;
9529 }
9530
d52c20b7
JB		 9531 /* set up a default setting for link flow control */
9532 pf->hw.fc.requested_mode = I40E_FC_NONE;
9533
41c445ff
JB		 9534 err = i40e_init_adminq(hw);
9535 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9536 if (err) {
9537 dev_info(&pdev->dev,
7aa67613 9538 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9539 goto err_pf_reset;
9540 }
9541
7aa67613
CS		 9542 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9543 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9544 dev_info(&pdev->dev,
7aa67613
CS		 9545 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9546 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9547 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9548 dev_info(&pdev->dev,
7aa67613 9549 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62
SN		 9550
9551
4eb3f768
SN		 9552 i40e_verify_eeprom(pf);
9553
2c5fe33b
JB		 9554 /* Rev 0 hardware was never productized */
9555 if (hw->revision_id < 1)
9556 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9557
6ff4ef86 9558 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9559 err = i40e_get_capabilities(pf);
9560 if (err)
9561 goto err_adminq_setup;
9562
9563 err = i40e_sw_init(pf);
9564 if (err) {
9565 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9566 goto err_sw_init;
9567 }
9568
9569 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9570 hw->func_caps.num_rx_qp,
9571 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9572 if (err) {
9573 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9574 goto err_init_lan_hmc;
9575 }
9576
9577 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9578 if (err) {
9579 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9580 err = -ENOENT;
9581 goto err_configure_lan_hmc;
9582 }
9583
b686ece5
NP		 9584 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
9585 * Ignore error return codes because if it was already disabled via
9586 * hardware settings this will fail
9587 */
9588 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
9589 (pf->hw.aq.fw_maj_ver < 4)) {
9590 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
9591 i40e_aq_stop_lldp(hw, true, NULL);
9592 }
9593
41c445ff 9594 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9595 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9596 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9597 err = -EIO;
9598 goto err_mac_addr;
9599 }
9600 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9601 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9602 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9603 if (is_valid_ether_addr(hw->mac.port_addr))
9604 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9605#ifdef I40E_FCOE
9606 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9607 if (err)
9608 dev_info(&pdev->dev,
9609 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9610 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9611 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9612 hw->mac.san_addr);
9613 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9614 }
9615 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9616#endif /* I40E_FCOE */
41c445ff
JB		 9617
9618 pci_set_drvdata(pdev, pf);
9619 pci_save_state(pdev);
4e3b35b0
NP		 9620#ifdef CONFIG_I40E_DCB
9621 err = i40e_init_pf_dcb(pf);
9622 if (err) {
aebfc816 9623 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 9624 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9625 /* Continue without DCB enabled */
4e3b35b0
NP		 9626 }
9627#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9628
9629 /* set up periodic task facility */
9630 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9631 pf->service_timer_period = HZ;
9632
9633 INIT_WORK(&pf->service_task, i40e_service_task);
9634 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9635 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9636 pf->link_check_timeout = jiffies;
9637
8e2773ae
SN		 9638 /* WoL defaults to disabled */
9639 pf->wol_en = false;
9640 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9641
41c445ff
JB		 9642 /* set up the main switch operations */
9643 i40e_determine_queue_usage(pf);
9644 i40e_init_interrupt_scheme(pf);
9645
505682cd
MW		 9646 /* The number of VSIs reported by the FW is the minimum guaranteed
9647 * to us; HW supports far more and we share the remaining pool with
9648 * the other PFs. We allocate space for more than the guarantee with
9649 * the understanding that we might not get them all later.
41c445ff 9650 */
505682cd
MW		 9651 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9652 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9653 else
9654 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9655
9656 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9657 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9658 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9659 if (!pf->vsi) {
9660 err = -ENOMEM;
41c445ff 9661 goto err_switch_setup;
ed87ac09 9662 }
41c445ff 9663
bc7d338f 9664 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9665 if (err) {
9666 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9667 goto err_vsis;
9668 }
8a9eb7d3 9669 /* if FDIR VSI was set up, start it now */
505682cd 9670 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9671 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9672 i40e_vsi_open(pf->vsi[i]);
9673 break;
9674 }
9675 }
41c445ff 9676
7e2453fe
JB		 9677 /* driver is only interested in link up/down and module qualification
9678 * reports from firmware
9679 */
9680 err = i40e_aq_set_phy_int_mask(&pf->hw,
9681 I40E_AQ_EVENT_LINK_UPDOWN |
9682 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9683 if (err)
9684 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9685
025b4a54
ASJ		 9686 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
9687 (pf->hw.aq.fw_maj_ver < 4)) {
9688 msleep(75);
9689 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9690 if (err)
9691 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9692 pf->hw.aq.asq_last_status);
cafa2ee6 9693 }
41c445ff
JB		 9694 /* The main driver is (mostly) up and happy. We need to set this state
9695 * before setting up the misc vector or we get a race and the vector
9696 * ends up disabled forever.
9697 */
9698 clear_bit(__I40E_DOWN, &pf->state);
9699
9700 /* In case of MSIX we are going to setup the misc vector right here
9701 * to handle admin queue events etc. In case of legacy and MSI
9702 * the misc functionality and queue processing is combined in
9703 * the same vector and that gets setup at open.
9704 */
9705 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9706 err = i40e_setup_misc_vector(pf);
9707 if (err) {
9708 dev_info(&pdev->dev,
9709 "setup of misc vector failed: %d\n", err);
9710 goto err_vsis;
9711 }
9712 }
9713
df805f62 9714#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9715 /* prep for VF support */
9716 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9717 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9718 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9719 u32 val;
9720
9721 /* disable link interrupts for VFs */
9722 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9723 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9724 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9725 i40e_flush(hw);
4aeec010
MW		 9726
9727 if (pci_num_vf(pdev)) {
9728 dev_info(&pdev->dev,
9729 "Active VFs found, allocating resources.\n");
9730 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9731 if (err)
9732 dev_info(&pdev->dev,
9733 "Error %d allocating resources for existing VFs\n",
9734 err);
9735 }
41c445ff 9736 }
df805f62 9737#endif /* CONFIG_PCI_IOV */
41c445ff 9738
93cd765b
ASJ		 9739 pfs_found++;
9740
41c445ff
JB		 9741 i40e_dbg_pf_init(pf);
9742
9743 /* tell the firmware that we're starting */
44033fac 9744 i40e_send_version(pf);
41c445ff
JB		 9745
9746 /* since everything's happy, start the service_task timer */
9747 mod_timer(&pf->service_timer,
9748 round_jiffies(jiffies + pf->service_timer_period));
9749
38e00438
VD		 9750#ifdef I40E_FCOE
9751 /* create FCoE interface */
9752 i40e_fcoe_vsi_setup(pf);
9753
9754#endif
d4dfb81a
CS		 9755 /* Get the negotiated link width and speed from PCI config space */
9756 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9757
9758 i40e_set_pci_config_data(hw, link_status);
9759
69bfb110 9760 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9761 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9762 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9763 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9764 "Unknown"),
9765 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9766 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9767 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9768 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9769 "Unknown"));
9770
9771 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9772 hw->bus.speed < i40e_bus_speed_8000) {
9773 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9774 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9775 }
9776
e827845c
CS		 9777 /* get the requested speeds from the fw */
9778 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
9779 if (err)
9780 dev_info(&pf->pdev->dev, "get phy abilities failed, aq_err %d, advertised speed settings may not be correct\n",
9781 err);
9782 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
9783
0c22b3dd
JB		 9784 /* print a string summarizing features */
9785 i40e_print_features(pf);
9786
41c445ff
JB		 9787 return 0;
9788
9789 /* Unwind what we've done if something failed in the setup */
9790err_vsis:
9791 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9792 i40e_clear_interrupt_scheme(pf);
9793 kfree(pf->vsi);
04b03013
SN		 9794err_switch_setup:
9795 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9796 del_timer_sync(&pf->service_timer);
9797err_mac_addr:
9798err_configure_lan_hmc:
9799 (void)i40e_shutdown_lan_hmc(hw);
9800err_init_lan_hmc:
9801 kfree(pf->qp_pile);
9802 kfree(pf->irq_pile);
9803err_sw_init:
9804err_adminq_setup:
9805 (void)i40e_shutdown_adminq(hw);
9806err_pf_reset:
9807 iounmap(hw->hw_addr);
9808err_ioremap:
9809 kfree(pf);
9810err_pf_alloc:
9811 pci_disable_pcie_error_reporting(pdev);
9812 pci_release_selected_regions(pdev,
9813 pci_select_bars(pdev, IORESOURCE_MEM));
9814err_pci_reg:
9815err_dma:
9816 pci_disable_device(pdev);
9817 return err;
9818}
9819
9820/**
9821 * i40e_remove - Device removal routine
9822 * @pdev: PCI device information struct
9823 *
9824 * i40e_remove is called by the PCI subsystem to alert the driver
9825 * that is should release a PCI device. This could be caused by a
9826 * Hot-Plug event, or because the driver is going to be removed from
9827 * memory.
9828 **/
9829static void i40e_remove(struct pci_dev *pdev)
9830{
9831 struct i40e_pf *pf = pci_get_drvdata(pdev);
9832 i40e_status ret_code;
41c445ff
JB		 9833 int i;
9834
9835 i40e_dbg_pf_exit(pf);
9836
beb0dff1
JK		 9837 i40e_ptp_stop(pf);
9838
41c445ff
JB		 9839 /* no more scheduling of any task */
9840 set_bit(__I40E_DOWN, &pf->state);
9841 del_timer_sync(&pf->service_timer);
9842 cancel_work_sync(&pf->service_task);
9843
eb2d80bc
MW		 9844 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
9845 i40e_free_vfs(pf);
9846 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
9847 }
9848
41c445ff
JB		 9849 i40e_fdir_teardown(pf);
9850
9851 /* If there is a switch structure or any orphans, remove them.
9852 * This will leave only the PF's VSI remaining.
9853 */
9854 for (i = 0; i < I40E_MAX_VEB; i++) {
9855 if (!pf->veb[i])
9856 continue;
9857
9858 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
9859 pf->veb[i]->uplink_seid == 0)
9860 i40e_switch_branch_release(pf->veb[i]);
9861 }
9862
9863 /* Now we can shutdown the PF's VSI, just before we kill
9864 * adminq and hmc.
9865 */
9866 if (pf->vsi[pf->lan_vsi])
9867 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
9868
9869 i40e_stop_misc_vector(pf);
9870 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9871 synchronize_irq(pf->msix_entries[0].vector);
9872 free_irq(pf->msix_entries[0].vector, pf);
9873 }
9874
9875 /* shutdown and destroy the HMC */
60442dea
SN		 9876 if (pf->hw.hmc.hmc_obj) {
9877 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
9878 if (ret_code)
9879 dev_warn(&pdev->dev,
9880 "Failed to destroy the HMC resources: %d\n",
9881 ret_code);
9882 }
41c445ff
JB		 9883
9884 /* shutdown the adminq */
41c445ff
JB		 9885 ret_code = i40e_shutdown_adminq(&pf->hw);
9886 if (ret_code)
9887 dev_warn(&pdev->dev,
9888 "Failed to destroy the Admin Queue resources: %d\n",
9889 ret_code);
9890
9891 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
9892 i40e_clear_interrupt_scheme(pf);
505682cd 9893 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9894 if (pf->vsi[i]) {
9895 i40e_vsi_clear_rings(pf->vsi[i]);
9896 i40e_vsi_clear(pf->vsi[i]);
9897 pf->vsi[i] = NULL;
9898 }
9899 }
9900
9901 for (i = 0; i < I40E_MAX_VEB; i++) {
9902 kfree(pf->veb[i]);
9903 pf->veb[i] = NULL;
9904 }
9905
9906 kfree(pf->qp_pile);
9907 kfree(pf->irq_pile);
41c445ff
JB		 9908 kfree(pf->vsi);
9909
41c445ff
JB		 9910 iounmap(pf->hw.hw_addr);
9911 kfree(pf);
9912 pci_release_selected_regions(pdev,
9913 pci_select_bars(pdev, IORESOURCE_MEM));
9914
9915 pci_disable_pcie_error_reporting(pdev);
9916 pci_disable_device(pdev);
9917}
9918
9919/**
9920 * i40e_pci_error_detected - warning that something funky happened in PCI land
9921 * @pdev: PCI device information struct
9922 *
9923 * Called to warn that something happened and the error handling steps
9924 * are in progress. Allows the driver to quiesce things, be ready for
9925 * remediation.
9926 **/
9927static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
9928 enum pci_channel_state error)
9929{
9930 struct i40e_pf *pf = pci_get_drvdata(pdev);
9931
9932 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9933
9934 /* shutdown all operations */
9007bccd
SN		 9935 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9936 rtnl_lock();
9937 i40e_prep_for_reset(pf);
9938 rtnl_unlock();
9939 }
41c445ff
JB		 9940
9941 /* Request a slot reset */
9942 return PCI_ERS_RESULT_NEED_RESET;
9943}
9944
9945/**
9946 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9947 * @pdev: PCI device information struct
9948 *
9949 * Called to find if the driver can work with the device now that
9950 * the pci slot has been reset. If a basic connection seems good
9951 * (registers are readable and have sane content) then return a
9952 * happy little PCI_ERS_RESULT_xxx.
9953 **/
9954static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9955{
9956 struct i40e_pf *pf = pci_get_drvdata(pdev);
9957 pci_ers_result_t result;
9958 int err;
9959 u32 reg;
9960
9961 dev_info(&pdev->dev, "%s\n", __func__);
9962 if (pci_enable_device_mem(pdev)) {
9963 dev_info(&pdev->dev,
9964 "Cannot re-enable PCI device after reset.\n");
9965 result = PCI_ERS_RESULT_DISCONNECT;
9966 } else {
9967 pci_set_master(pdev);
9968 pci_restore_state(pdev);
9969 pci_save_state(pdev);
9970 pci_wake_from_d3(pdev, false);
9971
9972 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9973 if (reg == 0)
9974 result = PCI_ERS_RESULT_RECOVERED;
9975 else
9976 result = PCI_ERS_RESULT_DISCONNECT;
9977 }
9978
9979 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9980 if (err) {
9981 dev_info(&pdev->dev,
9982 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9983 err);
9984 /* non-fatal, continue */
9985 }
9986
9987 return result;
9988}
9989
9990/**
9991 * i40e_pci_error_resume - restart operations after PCI error recovery
9992 * @pdev: PCI device information struct
9993 *
9994 * Called to allow the driver to bring things back up after PCI error
9995 * and/or reset recovery has finished.
9996 **/
9997static void i40e_pci_error_resume(struct pci_dev *pdev)
9998{
9999 struct i40e_pf *pf = pci_get_drvdata(pdev);
10000
10001 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10002 if (test_bit(__I40E_SUSPENDED, &pf->state))
10003 return;
10004
10005 rtnl_lock();
41c445ff 10006 i40e_handle_reset_warning(pf);
9007bccd
SN		 10007 rtnl_lock();
10008}
10009
10010/**
10011 * i40e_shutdown - PCI callback for shutting down
10012 * @pdev: PCI device information struct
10013 **/
10014static void i40e_shutdown(struct pci_dev *pdev)
10015{
10016 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10017 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10018
10019 set_bit(__I40E_SUSPENDED, &pf->state);
10020 set_bit(__I40E_DOWN, &pf->state);
10021 rtnl_lock();
10022 i40e_prep_for_reset(pf);
10023 rtnl_unlock();
10024
8e2773ae
SN		 10025 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10026 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10027
9007bccd 10028 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10029 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10030 pci_set_power_state(pdev, PCI_D3hot);
10031 }
10032}
10033
10034#ifdef CONFIG_PM
10035/**
10036 * i40e_suspend - PCI callback for moving to D3
10037 * @pdev: PCI device information struct
10038 **/
10039static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10040{
10041 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10042 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10043
10044 set_bit(__I40E_SUSPENDED, &pf->state);
10045 set_bit(__I40E_DOWN, &pf->state);
88086e5d
MW		 10046 del_timer_sync(&pf->service_timer);
10047 cancel_work_sync(&pf->service_task);
9007bccd
SN		 10048 rtnl_lock();
10049 i40e_prep_for_reset(pf);
10050 rtnl_unlock();
10051
8e2773ae
SN		 10052 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10053 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10054
10055 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10056 pci_set_power_state(pdev, PCI_D3hot);
10057
10058 return 0;
41c445ff
JB		 10059}
10060
9007bccd
SN		 10061/**
10062 * i40e_resume - PCI callback for waking up from D3
10063 * @pdev: PCI device information struct
10064 **/
10065static int i40e_resume(struct pci_dev *pdev)
10066{
10067 struct i40e_pf *pf = pci_get_drvdata(pdev);
10068 u32 err;
10069
10070 pci_set_power_state(pdev, PCI_D0);
10071 pci_restore_state(pdev);
10072 /* pci_restore_state() clears dev->state_saves, so
10073 * call pci_save_state() again to restore it.
10074 */
10075 pci_save_state(pdev);
10076
10077 err = pci_enable_device_mem(pdev);
10078 if (err) {
10079 dev_err(&pdev->dev,
10080 "%s: Cannot enable PCI device from suspend\n",
10081 __func__);
10082 return err;
10083 }
10084 pci_set_master(pdev);
10085
10086 /* no wakeup events while running */
10087 pci_wake_from_d3(pdev, false);
10088
10089 /* handling the reset will rebuild the device state */
10090 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10091 clear_bit(__I40E_DOWN, &pf->state);
10092 rtnl_lock();
10093 i40e_reset_and_rebuild(pf, false);
10094 rtnl_unlock();
10095 }
10096
10097 return 0;
10098}
10099
10100#endif
41c445ff
JB		 10101static const struct pci_error_handlers i40e_err_handler = {
10102 .error_detected = i40e_pci_error_detected,
10103 .slot_reset = i40e_pci_error_slot_reset,
10104 .resume = i40e_pci_error_resume,
10105};
10106
10107static struct pci_driver i40e_driver = {
10108 .name = i40e_driver_name,
10109 .id_table = i40e_pci_tbl,
10110 .probe = i40e_probe,
10111 .remove = i40e_remove,
9007bccd
SN		 10112#ifdef CONFIG_PM
10113 .suspend = i40e_suspend,
10114 .resume = i40e_resume,
10115#endif
10116 .shutdown = i40e_shutdown,
41c445ff
JB		 10117 .err_handler = &i40e_err_handler,
10118 .sriov_configure = i40e_pci_sriov_configure,
10119};
10120
10121/**
10122 * i40e_init_module - Driver registration routine
10123 *
10124 * i40e_init_module is the first routine called when the driver is
10125 * loaded. All it does is register with the PCI subsystem.
10126 **/
10127static int __init i40e_init_module(void)
10128{
10129 pr_info("%s: %s - version %s\n", i40e_driver_name,
10130 i40e_driver_string, i40e_driver_version_str);
10131 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483
GR		 10132
10133#if IS_ENABLED(CONFIG_CONFIGFS_FS)
10134 i40e_configfs_init();
10135#endif /* CONFIG_CONFIGFS_FS */
41c445ff
JB		 10136 i40e_dbg_init();
10137 return pci_register_driver(&i40e_driver);
10138}
10139module_init(i40e_init_module);
10140
10141/**
10142 * i40e_exit_module - Driver exit cleanup routine
10143 *
10144 * i40e_exit_module is called just before the driver is removed
10145 * from memory.
10146 **/
10147static void __exit i40e_exit_module(void)
10148{
10149 pci_unregister_driver(&i40e_driver);
10150 i40e_dbg_exit();
96664483
GR		 10151#if IS_ENABLED(CONFIG_CONFIGFS_FS)
10152 i40e_configfs_exit();
10153#endif /* CONFIG_CONFIGFS_FS */
41c445ff
JB		 10154}
10155module_exit(i40e_exit_module);
Linux kernel - Deliverables
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