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geneve: Add geneve_get_rx_port support
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
6a899024 30#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 31#include <net/vxlan.h>
32#endif
6a899024
SA		 33#if IS_ENABLED(CONFIG_GENEVE)
34#include <net/geneve.h>
35#endif
41c445ff
JB		 36
37const char i40e_driver_name[] = "i40e";
38static const char i40e_driver_string[] =
39 "Intel(R) Ethernet Connection XL710 Network Driver";
40
41#define DRV_KERN "-k"
42
e8e724db 43#define DRV_VERSION_MAJOR 1
1c2df9e5 44#define DRV_VERSION_MINOR 4
c9c9f1ba 45#define DRV_VERSION_BUILD 8
41c445ff
JB		 46#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
47 __stringify(DRV_VERSION_MINOR) "." \
48 __stringify(DRV_VERSION_BUILD) DRV_KERN
49const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 50static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 51
52/* a bit of forward declarations */
53static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
54static void i40e_handle_reset_warning(struct i40e_pf *pf);
55static int i40e_add_vsi(struct i40e_vsi *vsi);
56static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 57static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 58static int i40e_setup_misc_vector(struct i40e_pf *pf);
59static void i40e_determine_queue_usage(struct i40e_pf *pf);
60static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 61static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
62 u16 rss_table_size, u16 rss_size);
cbf61325 63static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 64static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 65
66/* i40e_pci_tbl - PCI Device ID Table
67 *
68 * Last entry must be all 0s
69 *
70 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
71 * Class, Class Mask, private data (not used) }
72 */
9baa3c34 73static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 90 /* required last entry */
91 {0, }
92};
93MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
94
95#define I40E_MAX_VF_COUNT 128
96static int debug = -1;
97module_param(debug, int, 0);
98MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
99
100MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
101MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
102MODULE_LICENSE("GPL");
103MODULE_VERSION(DRV_VERSION);
104
105/**
106 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
107 * @hw: pointer to the HW structure
108 * @mem: ptr to mem struct to fill out
109 * @size: size of memory requested
110 * @alignment: what to align the allocation to
111 **/
112int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
113 u64 size, u32 alignment)
114{
115 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
116
117 mem->size = ALIGN(size, alignment);
118 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
119 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 120 if (!mem->va)
121 return -ENOMEM;
41c445ff 122
93bc73b8 123 return 0;
41c445ff
JB		 124}
125
126/**
127 * i40e_free_dma_mem_d - OS specific memory free for shared code
128 * @hw: pointer to the HW structure
129 * @mem: ptr to mem struct to free
130 **/
131int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
132{
133 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
134
135 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
136 mem->va = NULL;
137 mem->pa = 0;
138 mem->size = 0;
139
140 return 0;
141}
142
143/**
144 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
145 * @hw: pointer to the HW structure
146 * @mem: ptr to mem struct to fill out
147 * @size: size of memory requested
148 **/
149int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
150 u32 size)
151{
152 mem->size = size;
153 mem->va = kzalloc(size, GFP_KERNEL);
154
93bc73b8
JB		 155 if (!mem->va)
156 return -ENOMEM;
41c445ff 157
93bc73b8 158 return 0;
41c445ff
JB		 159}
160
161/**
162 * i40e_free_virt_mem_d - OS specific memory free for shared code
163 * @hw: pointer to the HW structure
164 * @mem: ptr to mem struct to free
165 **/
166int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
167{
168 /* it's ok to kfree a NULL pointer */
169 kfree(mem->va);
170 mem->va = NULL;
171 mem->size = 0;
172
173 return 0;
174}
175
176/**
177 * i40e_get_lump - find a lump of free generic resource
178 * @pf: board private structure
179 * @pile: the pile of resource to search
180 * @needed: the number of items needed
181 * @id: an owner id to stick on the items assigned
182 *
183 * Returns the base item index of the lump, or negative for error
184 *
185 * The search_hint trick and lack of advanced fit-finding only work
186 * because we're highly likely to have all the same size lump requests.
187 * Linear search time and any fragmentation should be minimal.
188 **/
189static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
190 u16 needed, u16 id)
191{
192 int ret = -ENOMEM;
ddf434ac 193 int i, j;
41c445ff
JB		 194
195 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
196 dev_info(&pf->pdev->dev,
197 "param err: pile=%p needed=%d id=0x%04x\n",
198 pile, needed, id);
199 return -EINVAL;
200 }
201
202 /* start the linear search with an imperfect hint */
203 i = pile->search_hint;
ddf434ac 204 while (i < pile->num_entries) {
41c445ff
JB		 205 /* skip already allocated entries */
206 if (pile->list[i] & I40E_PILE_VALID_BIT) {
207 i++;
208 continue;
209 }
210
211 /* do we have enough in this lump? */
212 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
213 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
214 break;
215 }
216
217 if (j == needed) {
218 /* there was enough, so assign it to the requestor */
219 for (j = 0; j < needed; j++)
220 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
221 ret = i;
222 pile->search_hint = i + j;
ddf434ac 223 break;
41c445ff 224 }
6995b36c
JB		 225
226 /* not enough, so skip over it and continue looking */
227 i += j;
41c445ff
JB		 228 }
229
230 return ret;
231}
232
233/**
234 * i40e_put_lump - return a lump of generic resource
235 * @pile: the pile of resource to search
236 * @index: the base item index
237 * @id: the owner id of the items assigned
238 *
239 * Returns the count of items in the lump
240 **/
241static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
242{
243 int valid_id = (id | I40E_PILE_VALID_BIT);
244 int count = 0;
245 int i;
246
247 if (!pile || index >= pile->num_entries)
248 return -EINVAL;
249
250 for (i = index;
251 i < pile->num_entries && pile->list[i] == valid_id;
252 i++) {
253 pile->list[i] = 0;
254 count++;
255 }
256
257 if (count && index < pile->search_hint)
258 pile->search_hint = index;
259
260 return count;
261}
262
fdf0e0bf
ASJ		 263/**
264 * i40e_find_vsi_from_id - searches for the vsi with the given id
265 * @pf - the pf structure to search for the vsi
266 * @id - id of the vsi it is searching for
267 **/
268struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
269{
270 int i;
271
272 for (i = 0; i < pf->num_alloc_vsi; i++)
273 if (pf->vsi[i] && (pf->vsi[i]->id == id))
274 return pf->vsi[i];
275
276 return NULL;
277}
278
41c445ff
JB		 279/**
280 * i40e_service_event_schedule - Schedule the service task to wake up
281 * @pf: board private structure
282 *
283 * If not already scheduled, this puts the task into the work queue
284 **/
285static void i40e_service_event_schedule(struct i40e_pf *pf)
286{
287 if (!test_bit(__I40E_DOWN, &pf->state) &&
288 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
289 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
290 schedule_work(&pf->service_task);
291}
292
293/**
294 * i40e_tx_timeout - Respond to a Tx Hang
295 * @netdev: network interface device structure
296 *
297 * If any port has noticed a Tx timeout, it is likely that the whole
298 * device is munged, not just the one netdev port, so go for the full
299 * reset.
300 **/
38e00438
VD		 301#ifdef I40E_FCOE
302void i40e_tx_timeout(struct net_device *netdev)
303#else
41c445ff 304static void i40e_tx_timeout(struct net_device *netdev)
38e00438 305#endif
41c445ff
JB		 306{
307 struct i40e_netdev_priv *np = netdev_priv(netdev);
308 struct i40e_vsi *vsi = np->vsi;
309 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 310 struct i40e_ring *tx_ring = NULL;
311 unsigned int i, hung_queue = 0;
312 u32 head, val;
41c445ff
JB		 313
314 pf->tx_timeout_count++;
315
b03a8c1f
KP		 316 /* find the stopped queue the same way the stack does */
317 for (i = 0; i < netdev->num_tx_queues; i++) {
318 struct netdev_queue *q;
319 unsigned long trans_start;
320
321 q = netdev_get_tx_queue(netdev, i);
322 trans_start = q->trans_start ? : netdev->trans_start;
323 if (netif_xmit_stopped(q) &&
324 time_after(jiffies,
325 (trans_start + netdev->watchdog_timeo))) {
326 hung_queue = i;
327 break;
328 }
329 }
330
331 if (i == netdev->num_tx_queues) {
332 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
333 } else {
334 /* now that we have an index, find the tx_ring struct */
335 for (i = 0; i < vsi->num_queue_pairs; i++) {
336 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
337 if (hung_queue ==
338 vsi->tx_rings[i]->queue_index) {
339 tx_ring = vsi->tx_rings[i];
340 break;
341 }
342 }
343 }
344 }
345
41c445ff 346 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 347 pf->tx_timeout_recovery_level = 1; /* reset after some time */
348 else if (time_before(jiffies,
349 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
350 return; /* don't do any new action before the next timeout */
351
352 if (tx_ring) {
353 head = i40e_get_head(tx_ring);
354 /* Read interrupt register */
355 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
356 val = rd32(&pf->hw,
357 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
358 tx_ring->vsi->base_vector - 1));
359 else
360 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
361
362 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
363 vsi->seid, hung_queue, tx_ring->next_to_clean,
364 head, tx_ring->next_to_use,
365 readl(tx_ring->tail), val);
366 }
367
41c445ff 368 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 369 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
370 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 371
372 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 373 case 1:
374 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
375 break;
376 case 2:
377 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
378 break;
379 case 3:
380 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
381 break;
382 default:
383 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 384 break;
385 }
b03a8c1f 386
41c445ff
JB		 387 i40e_service_event_schedule(pf);
388 pf->tx_timeout_recovery_level++;
389}
390
391/**
392 * i40e_release_rx_desc - Store the new tail and head values
393 * @rx_ring: ring to bump
394 * @val: new head index
395 **/
396static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
397{
398 rx_ring->next_to_use = val;
399
400 /* Force memory writes to complete before letting h/w
401 * know there are new descriptors to fetch. (Only
402 * applicable for weak-ordered memory model archs,
403 * such as IA-64).
404 */
405 wmb();
406 writel(val, rx_ring->tail);
407}
408
409/**
410 * i40e_get_vsi_stats_struct - Get System Network Statistics
411 * @vsi: the VSI we care about
412 *
413 * Returns the address of the device statistics structure.
414 * The statistics are actually updated from the service task.
415 **/
416struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
417{
418 return &vsi->net_stats;
419}
420
421/**
422 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
423 * @netdev: network interface device structure
424 *
425 * Returns the address of the device statistics structure.
426 * The statistics are actually updated from the service task.
427 **/
38e00438
VD		 428#ifdef I40E_FCOE
429struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
430 struct net_device *netdev,
431 struct rtnl_link_stats64 *stats)
432#else
41c445ff
JB		 433static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
434 struct net_device *netdev,
980e9b11 435 struct rtnl_link_stats64 *stats)
38e00438 436#endif
41c445ff
JB		 437{
438 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 439 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 440 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 441 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
442 int i;
443
bc7d338f
ASJ		 444 if (test_bit(__I40E_DOWN, &vsi->state))
445 return stats;
446
3c325ced
JB		 447 if (!vsi->tx_rings)
448 return stats;
449
980e9b11
AD		 450 rcu_read_lock();
451 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 452 u64 bytes, packets;
453 unsigned int start;
454
455 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
456 if (!tx_ring)
457 continue;
458
459 do {
57a7744e 460 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 461 packets = tx_ring->stats.packets;
462 bytes = tx_ring->stats.bytes;
57a7744e 463 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 464
465 stats->tx_packets += packets;
466 stats->tx_bytes += bytes;
467 rx_ring = &tx_ring[1];
468
469 do {
57a7744e 470 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 471 packets = rx_ring->stats.packets;
472 bytes = rx_ring->stats.bytes;
57a7744e 473 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 474
980e9b11
AD		 475 stats->rx_packets += packets;
476 stats->rx_bytes += bytes;
477 }
478 rcu_read_unlock();
479
a5282f44 480 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 481 stats->multicast = vsi_stats->multicast;
482 stats->tx_errors = vsi_stats->tx_errors;
483 stats->tx_dropped = vsi_stats->tx_dropped;
484 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 485 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 486 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
487 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 488
980e9b11 489 return stats;
41c445ff
JB		 490}
491
492/**
493 * i40e_vsi_reset_stats - Resets all stats of the given vsi
494 * @vsi: the VSI to have its stats reset
495 **/
496void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
497{
498 struct rtnl_link_stats64 *ns;
499 int i;
500
501 if (!vsi)
502 return;
503
504 ns = i40e_get_vsi_stats_struct(vsi);
505 memset(ns, 0, sizeof(*ns));
506 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
507 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
508 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 509 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 510 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 511 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 512 sizeof(vsi->rx_rings[i]->stats));
6995b36c 513 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 514 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 515 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 516 sizeof(vsi->tx_rings[i]->stats));
517 memset(&vsi->tx_rings[i]->tx_stats, 0,
518 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 519 }
8e9dca53 520 }
41c445ff
JB		 521 vsi->stat_offsets_loaded = false;
522}
523
524/**
b40c82e6 525 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 526 * @pf: the PF to be reset
527 **/
528void i40e_pf_reset_stats(struct i40e_pf *pf)
529{
e91fdf76
SN		 530 int i;
531
41c445ff
JB		 532 memset(&pf->stats, 0, sizeof(pf->stats));
533 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
534 pf->stat_offsets_loaded = false;
e91fdf76
SN		 535
536 for (i = 0; i < I40E_MAX_VEB; i++) {
537 if (pf->veb[i]) {
538 memset(&pf->veb[i]->stats, 0,
539 sizeof(pf->veb[i]->stats));
540 memset(&pf->veb[i]->stats_offsets, 0,
541 sizeof(pf->veb[i]->stats_offsets));
542 pf->veb[i]->stat_offsets_loaded = false;
543 }
544 }
41c445ff
JB		 545}
546
547/**
548 * i40e_stat_update48 - read and update a 48 bit stat from the chip
549 * @hw: ptr to the hardware info
550 * @hireg: the high 32 bit reg to read
551 * @loreg: the low 32 bit reg to read
552 * @offset_loaded: has the initial offset been loaded yet
553 * @offset: ptr to current offset value
554 * @stat: ptr to the stat
555 *
556 * Since the device stats are not reset at PFReset, they likely will not
557 * be zeroed when the driver starts. We'll save the first values read
558 * and use them as offsets to be subtracted from the raw values in order
559 * to report stats that count from zero. In the process, we also manage
560 * the potential roll-over.
561 **/
562static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
563 bool offset_loaded, u64 *offset, u64 *stat)
564{
565 u64 new_data;
566
ab60085e 567 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 568 new_data = rd32(hw, loreg);
569 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
570 } else {
571 new_data = rd64(hw, loreg);
572 }
573 if (!offset_loaded)
574 *offset = new_data;
575 if (likely(new_data >= *offset))
576 *stat = new_data - *offset;
577 else
41a1d04b 578 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 579 *stat &= 0xFFFFFFFFFFFFULL;
580}
581
582/**
583 * i40e_stat_update32 - read and update a 32 bit stat from the chip
584 * @hw: ptr to the hardware info
585 * @reg: the hw reg to read
586 * @offset_loaded: has the initial offset been loaded yet
587 * @offset: ptr to current offset value
588 * @stat: ptr to the stat
589 **/
590static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
591 bool offset_loaded, u64 *offset, u64 *stat)
592{
593 u32 new_data;
594
595 new_data = rd32(hw, reg);
596 if (!offset_loaded)
597 *offset = new_data;
598 if (likely(new_data >= *offset))
599 *stat = (u32)(new_data - *offset);
600 else
41a1d04b 601 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 602}
603
604/**
605 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
606 * @vsi: the VSI to be updated
607 **/
608void i40e_update_eth_stats(struct i40e_vsi *vsi)
609{
610 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
611 struct i40e_pf *pf = vsi->back;
612 struct i40e_hw *hw = &pf->hw;
613 struct i40e_eth_stats *oes;
614 struct i40e_eth_stats *es; /* device's eth stats */
615
616 es = &vsi->eth_stats;
617 oes = &vsi->eth_stats_offsets;
618
619 /* Gather up the stats that the hw collects */
620 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->tx_errors, &es->tx_errors);
623 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
624 vsi->stat_offsets_loaded,
625 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 626 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
627 vsi->stat_offsets_loaded,
628 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
629 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
630 vsi->stat_offsets_loaded,
631 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 632
633 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
634 I40E_GLV_GORCL(stat_idx),
635 vsi->stat_offsets_loaded,
636 &oes->rx_bytes, &es->rx_bytes);
637 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
638 I40E_GLV_UPRCL(stat_idx),
639 vsi->stat_offsets_loaded,
640 &oes->rx_unicast, &es->rx_unicast);
641 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
642 I40E_GLV_MPRCL(stat_idx),
643 vsi->stat_offsets_loaded,
644 &oes->rx_multicast, &es->rx_multicast);
645 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
646 I40E_GLV_BPRCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->rx_broadcast, &es->rx_broadcast);
649
650 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
651 I40E_GLV_GOTCL(stat_idx),
652 vsi->stat_offsets_loaded,
653 &oes->tx_bytes, &es->tx_bytes);
654 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
655 I40E_GLV_UPTCL(stat_idx),
656 vsi->stat_offsets_loaded,
657 &oes->tx_unicast, &es->tx_unicast);
658 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
659 I40E_GLV_MPTCL(stat_idx),
660 vsi->stat_offsets_loaded,
661 &oes->tx_multicast, &es->tx_multicast);
662 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
663 I40E_GLV_BPTCL(stat_idx),
664 vsi->stat_offsets_loaded,
665 &oes->tx_broadcast, &es->tx_broadcast);
666 vsi->stat_offsets_loaded = true;
667}
668
669/**
670 * i40e_update_veb_stats - Update Switch component statistics
671 * @veb: the VEB being updated
672 **/
673static void i40e_update_veb_stats(struct i40e_veb *veb)
674{
675 struct i40e_pf *pf = veb->pf;
676 struct i40e_hw *hw = &pf->hw;
677 struct i40e_eth_stats *oes;
678 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 679 struct i40e_veb_tc_stats *veb_oes;
680 struct i40e_veb_tc_stats *veb_es;
681 int i, idx = 0;
41c445ff
JB		 682
683 idx = veb->stats_idx;
684 es = &veb->stats;
685 oes = &veb->stats_offsets;
fe860afb
NP		 686 veb_es = &veb->tc_stats;
687 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 688
689 /* Gather up the stats that the hw collects */
690 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
691 veb->stat_offsets_loaded,
692 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 693 if (hw->revision_id > 0)
694 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
695 veb->stat_offsets_loaded,
696 &oes->rx_unknown_protocol,
697 &es->rx_unknown_protocol);
41c445ff
JB		 698 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
699 veb->stat_offsets_loaded,
700 &oes->rx_bytes, &es->rx_bytes);
701 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
702 veb->stat_offsets_loaded,
703 &oes->rx_unicast, &es->rx_unicast);
704 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
705 veb->stat_offsets_loaded,
706 &oes->rx_multicast, &es->rx_multicast);
707 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
708 veb->stat_offsets_loaded,
709 &oes->rx_broadcast, &es->rx_broadcast);
710
711 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
712 veb->stat_offsets_loaded,
713 &oes->tx_bytes, &es->tx_bytes);
714 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
715 veb->stat_offsets_loaded,
716 &oes->tx_unicast, &es->tx_unicast);
717 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
718 veb->stat_offsets_loaded,
719 &oes->tx_multicast, &es->tx_multicast);
720 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
721 veb->stat_offsets_loaded,
722 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 723 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
724 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
725 I40E_GLVEBTC_RPCL(i, idx),
726 veb->stat_offsets_loaded,
727 &veb_oes->tc_rx_packets[i],
728 &veb_es->tc_rx_packets[i]);
729 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
730 I40E_GLVEBTC_RBCL(i, idx),
731 veb->stat_offsets_loaded,
732 &veb_oes->tc_rx_bytes[i],
733 &veb_es->tc_rx_bytes[i]);
734 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
735 I40E_GLVEBTC_TPCL(i, idx),
736 veb->stat_offsets_loaded,
737 &veb_oes->tc_tx_packets[i],
738 &veb_es->tc_tx_packets[i]);
739 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
740 I40E_GLVEBTC_TBCL(i, idx),
741 veb->stat_offsets_loaded,
742 &veb_oes->tc_tx_bytes[i],
743 &veb_es->tc_tx_bytes[i]);
744 }
41c445ff
JB		 745 veb->stat_offsets_loaded = true;
746}
747
38e00438
VD		 748#ifdef I40E_FCOE
749/**
750 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
751 * @vsi: the VSI that is capable of doing FCoE
752 **/
753static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
754{
755 struct i40e_pf *pf = vsi->back;
756 struct i40e_hw *hw = &pf->hw;
757 struct i40e_fcoe_stats *ofs;
758 struct i40e_fcoe_stats *fs; /* device's eth stats */
759 int idx;
760
761 if (vsi->type != I40E_VSI_FCOE)
762 return;
763
764 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
765 fs = &vsi->fcoe_stats;
766 ofs = &vsi->fcoe_stats_offsets;
767
768 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
769 vsi->fcoe_stat_offsets_loaded,
770 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
771 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
772 vsi->fcoe_stat_offsets_loaded,
773 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
774 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
775 vsi->fcoe_stat_offsets_loaded,
776 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
777 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
778 vsi->fcoe_stat_offsets_loaded,
779 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
780 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
781 vsi->fcoe_stat_offsets_loaded,
782 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
783 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
784 vsi->fcoe_stat_offsets_loaded,
785 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
786 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
787 vsi->fcoe_stat_offsets_loaded,
788 &ofs->fcoe_last_error, &fs->fcoe_last_error);
789 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
790 vsi->fcoe_stat_offsets_loaded,
791 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
792
793 vsi->fcoe_stat_offsets_loaded = true;
794}
795
796#endif
41c445ff 797/**
7812fddc 798 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 799 * @vsi: the VSI to be updated
800 *
801 * There are a few instances where we store the same stat in a
802 * couple of different structs. This is partly because we have
803 * the netdev stats that need to be filled out, which is slightly
804 * different from the "eth_stats" defined by the chip and used in
7812fddc 805 * VF communications. We sort it out here.
41c445ff 806 **/
7812fddc 807static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 808{
809 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 810 struct rtnl_link_stats64 *ons;
811 struct rtnl_link_stats64 *ns; /* netdev stats */
812 struct i40e_eth_stats *oes;
813 struct i40e_eth_stats *es; /* device's eth stats */
814 u32 tx_restart, tx_busy;
bf00b376 815 struct i40e_ring *p;
41c445ff 816 u32 rx_page, rx_buf;
bf00b376
AA		 817 u64 bytes, packets;
818 unsigned int start;
2fc3d715 819 u64 tx_linearize;
164c9f54 820 u64 tx_force_wb;
41c445ff
JB		 821 u64 rx_p, rx_b;
822 u64 tx_p, tx_b;
41c445ff
JB		 823 u16 q;
824
825 if (test_bit(__I40E_DOWN, &vsi->state) ||
826 test_bit(__I40E_CONFIG_BUSY, &pf->state))
827 return;
828
829 ns = i40e_get_vsi_stats_struct(vsi);
830 ons = &vsi->net_stats_offsets;
831 es = &vsi->eth_stats;
832 oes = &vsi->eth_stats_offsets;
833
834 /* Gather up the netdev and vsi stats that the driver collects
835 * on the fly during packet processing
836 */
837 rx_b = rx_p = 0;
838 tx_b = tx_p = 0;
164c9f54 839 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
41c445ff
JB		 840 rx_page = 0;
841 rx_buf = 0;
980e9b11 842 rcu_read_lock();
41c445ff 843 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 844 /* locate Tx ring */
845 p = ACCESS_ONCE(vsi->tx_rings[q]);
846
847 do {
57a7744e 848 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 849 packets = p->stats.packets;
850 bytes = p->stats.bytes;
57a7744e 851 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 852 tx_b += bytes;
853 tx_p += packets;
854 tx_restart += p->tx_stats.restart_queue;
855 tx_busy += p->tx_stats.tx_busy;
2fc3d715 856 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 857 tx_force_wb += p->tx_stats.tx_force_wb;
41c445ff 858
980e9b11
AD		 859 /* Rx queue is part of the same block as Tx queue */
860 p = &p[1];
861 do {
57a7744e 862 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 863 packets = p->stats.packets;
864 bytes = p->stats.bytes;
57a7744e 865 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 866 rx_b += bytes;
867 rx_p += packets;
420136cc
MW		 868 rx_buf += p->rx_stats.alloc_buff_failed;
869 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 870 }
980e9b11 871 rcu_read_unlock();
41c445ff
JB		 872 vsi->tx_restart = tx_restart;
873 vsi->tx_busy = tx_busy;
2fc3d715 874 vsi->tx_linearize = tx_linearize;
164c9f54 875 vsi->tx_force_wb = tx_force_wb;
41c445ff
JB		 876 vsi->rx_page_failed = rx_page;
877 vsi->rx_buf_failed = rx_buf;
878
879 ns->rx_packets = rx_p;
880 ns->rx_bytes = rx_b;
881 ns->tx_packets = tx_p;
882 ns->tx_bytes = tx_b;
883
41c445ff 884 /* update netdev stats from eth stats */
7812fddc 885 i40e_update_eth_stats(vsi);
41c445ff
JB		 886 ons->tx_errors = oes->tx_errors;
887 ns->tx_errors = es->tx_errors;
888 ons->multicast = oes->rx_multicast;
889 ns->multicast = es->rx_multicast;
41a9e55c
SN		 890 ons->rx_dropped = oes->rx_discards;
891 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 892 ons->tx_dropped = oes->tx_discards;
893 ns->tx_dropped = es->tx_discards;
894
7812fddc 895 /* pull in a couple PF stats if this is the main vsi */
41c445ff 896 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 897 ns->rx_crc_errors = pf->stats.crc_errors;
898 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
899 ns->rx_length_errors = pf->stats.rx_length_errors;
900 }
901}
41c445ff 902
7812fddc 903/**
b40c82e6 904 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 905 * @pf: the PF to be updated
906 **/
907static void i40e_update_pf_stats(struct i40e_pf *pf)
908{
909 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
910 struct i40e_hw_port_stats *nsd = &pf->stats;
911 struct i40e_hw *hw = &pf->hw;
912 u32 val;
913 int i;
41c445ff 914
7812fddc
SN		 915 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
916 I40E_GLPRT_GORCL(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
919 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
920 I40E_GLPRT_GOTCL(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
923 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_discards,
926 &nsd->eth.rx_discards);
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
928 I40E_GLPRT_UPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_unicast,
931 &nsd->eth.rx_unicast);
7812fddc
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
933 I40E_GLPRT_MPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_multicast,
936 &nsd->eth.rx_multicast);
532d283d
SN		 937 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
938 I40E_GLPRT_BPRCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.rx_broadcast,
941 &nsd->eth.rx_broadcast);
942 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
943 I40E_GLPRT_UPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_unicast,
946 &nsd->eth.tx_unicast);
947 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
948 I40E_GLPRT_MPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_multicast,
951 &nsd->eth.tx_multicast);
952 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
953 I40E_GLPRT_BPTCL(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->eth.tx_broadcast,
956 &nsd->eth.tx_broadcast);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->tx_dropped_link_down,
961 &nsd->tx_dropped_link_down);
41c445ff 962
7812fddc
SN		 963 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->crc_errors, &nsd->crc_errors);
41c445ff 966
7812fddc
SN		 967 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 970
7812fddc
SN		 971 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->mac_local_faults,
974 &nsd->mac_local_faults);
975 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->mac_remote_faults,
978 &nsd->mac_remote_faults);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->rx_length_errors,
983 &nsd->rx_length_errors);
41c445ff 984
7812fddc
SN		 985 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->link_xon_rx, &nsd->link_xon_rx);
988 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 991 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
992 pf->stat_offsets_loaded,
993 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 994 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
995 pf->stat_offsets_loaded,
996 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 997
7812fddc 998 for (i = 0; i < 8; i++) {
95db239f
NP		 999 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1000 pf->stat_offsets_loaded,
1001 &osd->priority_xoff_rx[i],
1002 &nsd->priority_xoff_rx[i]);
7812fddc 1003 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1004 pf->stat_offsets_loaded,
7812fddc
SN		 1005 &osd->priority_xon_rx[i],
1006 &nsd->priority_xon_rx[i]);
1007 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1008 pf->stat_offsets_loaded,
7812fddc
SN		 1009 &osd->priority_xon_tx[i],
1010 &nsd->priority_xon_tx[i]);
1011 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1012 pf->stat_offsets_loaded,
7812fddc
SN		 1013 &osd->priority_xoff_tx[i],
1014 &nsd->priority_xoff_tx[i]);
1015 i40e_stat_update32(hw,
1016 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1017 pf->stat_offsets_loaded,
7812fddc
SN		 1018 &osd->priority_xon_2_xoff[i],
1019 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1020 }
1021
7812fddc
SN		 1022 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1023 I40E_GLPRT_PRC64L(hw->port),
1024 pf->stat_offsets_loaded,
1025 &osd->rx_size_64, &nsd->rx_size_64);
1026 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1027 I40E_GLPRT_PRC127L(hw->port),
1028 pf->stat_offsets_loaded,
1029 &osd->rx_size_127, &nsd->rx_size_127);
1030 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1031 I40E_GLPRT_PRC255L(hw->port),
1032 pf->stat_offsets_loaded,
1033 &osd->rx_size_255, &nsd->rx_size_255);
1034 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1035 I40E_GLPRT_PRC511L(hw->port),
1036 pf->stat_offsets_loaded,
1037 &osd->rx_size_511, &nsd->rx_size_511);
1038 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1039 I40E_GLPRT_PRC1023L(hw->port),
1040 pf->stat_offsets_loaded,
1041 &osd->rx_size_1023, &nsd->rx_size_1023);
1042 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1043 I40E_GLPRT_PRC1522L(hw->port),
1044 pf->stat_offsets_loaded,
1045 &osd->rx_size_1522, &nsd->rx_size_1522);
1046 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1047 I40E_GLPRT_PRC9522L(hw->port),
1048 pf->stat_offsets_loaded,
1049 &osd->rx_size_big, &nsd->rx_size_big);
1050
1051 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1052 I40E_GLPRT_PTC64L(hw->port),
1053 pf->stat_offsets_loaded,
1054 &osd->tx_size_64, &nsd->tx_size_64);
1055 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1056 I40E_GLPRT_PTC127L(hw->port),
1057 pf->stat_offsets_loaded,
1058 &osd->tx_size_127, &nsd->tx_size_127);
1059 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1060 I40E_GLPRT_PTC255L(hw->port),
1061 pf->stat_offsets_loaded,
1062 &osd->tx_size_255, &nsd->tx_size_255);
1063 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1064 I40E_GLPRT_PTC511L(hw->port),
1065 pf->stat_offsets_loaded,
1066 &osd->tx_size_511, &nsd->tx_size_511);
1067 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1068 I40E_GLPRT_PTC1023L(hw->port),
1069 pf->stat_offsets_loaded,
1070 &osd->tx_size_1023, &nsd->tx_size_1023);
1071 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1072 I40E_GLPRT_PTC1522L(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->tx_size_1522, &nsd->tx_size_1522);
1075 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1076 I40E_GLPRT_PTC9522L(hw->port),
1077 pf->stat_offsets_loaded,
1078 &osd->tx_size_big, &nsd->tx_size_big);
1079
1080 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_undersize, &nsd->rx_undersize);
1083 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_fragments, &nsd->rx_fragments);
1086 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1087 pf->stat_offsets_loaded,
1088 &osd->rx_oversize, &nsd->rx_oversize);
1089 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1090 pf->stat_offsets_loaded,
1091 &osd->rx_jabber, &nsd->rx_jabber);
1092
433c47de 1093 /* FDIR stats */
0bf4b1b0
ASJ		 1094 i40e_stat_update32(hw,
1095 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1096 pf->stat_offsets_loaded,
1097 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1098 i40e_stat_update32(hw,
1099 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1100 pf->stat_offsets_loaded,
1101 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1102 i40e_stat_update32(hw,
1103 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1104 pf->stat_offsets_loaded,
1105 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1106
7812fddc
SN		 1107 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1108 nsd->tx_lpi_status =
1109 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1110 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1111 nsd->rx_lpi_status =
1112 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1113 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1114 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1115 pf->stat_offsets_loaded,
1116 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1117 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1118 pf->stat_offsets_loaded,
1119 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1120
d0389e51
ASJ		 1121 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1122 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1123 nsd->fd_sb_status = true;
1124 else
1125 nsd->fd_sb_status = false;
1126
1127 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1128 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1129 nsd->fd_atr_status = true;
1130 else
1131 nsd->fd_atr_status = false;
1132
41c445ff
JB		 1133 pf->stat_offsets_loaded = true;
1134}
1135
7812fddc
SN		 1136/**
1137 * i40e_update_stats - Update the various statistics counters.
1138 * @vsi: the VSI to be updated
1139 *
1140 * Update the various stats for this VSI and its related entities.
1141 **/
1142void i40e_update_stats(struct i40e_vsi *vsi)
1143{
1144 struct i40e_pf *pf = vsi->back;
1145
1146 if (vsi == pf->vsi[pf->lan_vsi])
1147 i40e_update_pf_stats(pf);
1148
1149 i40e_update_vsi_stats(vsi);
38e00438
VD		 1150#ifdef I40E_FCOE
1151 i40e_update_fcoe_stats(vsi);
1152#endif
7812fddc
SN		 1153}
1154
41c445ff
JB		 1155/**
1156 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1157 * @vsi: the VSI to be searched
1158 * @macaddr: the MAC address
1159 * @vlan: the vlan
b40c82e6 1160 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1161 * @is_netdev: make sure its a netdev filter, else doesn't matter
1162 *
1163 * Returns ptr to the filter object or NULL
1164 **/
1165static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1166 u8 *macaddr, s16 vlan,
1167 bool is_vf, bool is_netdev)
1168{
1169 struct i40e_mac_filter *f;
1170
1171 if (!vsi || !macaddr)
1172 return NULL;
1173
1174 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1175 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1176 (vlan == f->vlan) &&
1177 (!is_vf || f->is_vf) &&
1178 (!is_netdev || f->is_netdev))
1179 return f;
1180 }
1181 return NULL;
1182}
1183
1184/**
1185 * i40e_find_mac - Find a mac addr in the macvlan filters list
1186 * @vsi: the VSI to be searched
1187 * @macaddr: the MAC address we are searching for
b40c82e6 1188 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1189 * @is_netdev: make sure its a netdev filter, else doesn't matter
1190 *
1191 * Returns the first filter with the provided MAC address or NULL if
1192 * MAC address was not found
1193 **/
1194struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1195 bool is_vf, bool is_netdev)
1196{
1197 struct i40e_mac_filter *f;
1198
1199 if (!vsi || !macaddr)
1200 return NULL;
1201
1202 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1203 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1204 (!is_vf || f->is_vf) &&
1205 (!is_netdev || f->is_netdev))
1206 return f;
1207 }
1208 return NULL;
1209}
1210
1211/**
1212 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1213 * @vsi: the VSI to be searched
1214 *
1215 * Returns true if VSI is in vlan mode or false otherwise
1216 **/
1217bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1218{
1219 struct i40e_mac_filter *f;
1220
1221 /* Only -1 for all the filters denotes not in vlan mode
1222 * so we have to go through all the list in order to make sure
1223 */
1224 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1225 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1226 return true;
1227 }
1228
1229 return false;
1230}
1231
1232/**
1233 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1234 * @vsi: the VSI to be searched
1235 * @macaddr: the mac address to be filtered
b40c82e6 1236 * @is_vf: true if it is a VF
41c445ff
JB		 1237 * @is_netdev: true if it is a netdev
1238 *
1239 * Goes through all the macvlan filters and adds a
1240 * macvlan filter for each unique vlan that already exists
1241 *
1242 * Returns first filter found on success, else NULL
1243 **/
1244struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1245 bool is_vf, bool is_netdev)
1246{
1247 struct i40e_mac_filter *f;
1248
1249 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1250 if (vsi->info.pvid)
1251 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1252 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1253 is_vf, is_netdev)) {
1254 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1255 is_vf, is_netdev))
41c445ff
JB		 1256 return NULL;
1257 }
1258 }
1259
1260 return list_first_entry_or_null(&vsi->mac_filter_list,
1261 struct i40e_mac_filter, list);
1262}
1263
b36e9ab5
MW		 1264/**
1265 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1266 * @vsi: the VSI to be searched
1267 * @macaddr: the mac address to be removed
1268 * @is_vf: true if it is a VF
1269 * @is_netdev: true if it is a netdev
1270 *
1271 * Removes a given MAC address from a VSI, regardless of VLAN
1272 *
1273 * Returns 0 for success, or error
1274 **/
1275int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1276 bool is_vf, bool is_netdev)
1277{
1278 struct i40e_mac_filter *f = NULL;
1279 int changed = 0;
1280
1281 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1282 "Missing mac_filter_list_lock\n");
1283 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1284 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1285 (is_vf == f->is_vf) &&
1286 (is_netdev == f->is_netdev)) {
1287 f->counter--;
1288 f->changed = true;
1289 changed = 1;
1290 }
1291 }
1292 if (changed) {
1293 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1294 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1295 return 0;
1296 }
1297 return -ENOENT;
1298}
1299
8c27d42e
GR		 1300/**
1301 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1302 * @vsi: the PF Main VSI - inappropriate for any other VSI
1303 * @macaddr: the MAC address
30650cc5
SN		 1304 *
1305 * Some older firmware configurations set up a default promiscuous VLAN
1306 * filter that needs to be removed.
8c27d42e 1307 **/
30650cc5 1308static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1309{
1310 struct i40e_aqc_remove_macvlan_element_data element;
1311 struct i40e_pf *pf = vsi->back;
f1c7e72e 1312 i40e_status ret;
8c27d42e
GR		 1313
1314 /* Only appropriate for the PF main VSI */
1315 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1316 return -EINVAL;
8c27d42e 1317
30650cc5 1318 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1319 ether_addr_copy(element.mac_addr, macaddr);
1320 element.vlan_tag = 0;
1321 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1322 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1323 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1324 if (ret)
30650cc5
SN		 1325 return -ENOENT;
1326
1327 return 0;
8c27d42e
GR		 1328}
1329
41c445ff
JB		 1330/**
1331 * i40e_add_filter - Add a mac/vlan filter to the VSI
1332 * @vsi: the VSI to be searched
1333 * @macaddr: the MAC address
1334 * @vlan: the vlan
b40c82e6 1335 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1336 * @is_netdev: make sure its a netdev filter, else doesn't matter
1337 *
1338 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1339 *
1340 * NOTE: This function is expected to be called with mac_filter_list_lock
1341 * being held.
41c445ff
JB		 1342 **/
1343struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1344 u8 *macaddr, s16 vlan,
1345 bool is_vf, bool is_netdev)
1346{
1347 struct i40e_mac_filter *f;
1348
1349 if (!vsi || !macaddr)
1350 return NULL;
1351
1352 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1353 if (!f) {
1354 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1355 if (!f)
1356 goto add_filter_out;
1357
9a173901 1358 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1359 f->vlan = vlan;
1360 f->changed = true;
1361
1362 INIT_LIST_HEAD(&f->list);
1363 list_add(&f->list, &vsi->mac_filter_list);
1364 }
1365
1366 /* increment counter and add a new flag if needed */
1367 if (is_vf) {
1368 if (!f->is_vf) {
1369 f->is_vf = true;
1370 f->counter++;
1371 }
1372 } else if (is_netdev) {
1373 if (!f->is_netdev) {
1374 f->is_netdev = true;
1375 f->counter++;
1376 }
1377 } else {
1378 f->counter++;
1379 }
1380
1381 /* changed tells sync_filters_subtask to
1382 * push the filter down to the firmware
1383 */
1384 if (f->changed) {
1385 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1386 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1387 }
1388
1389add_filter_out:
1390 return f;
1391}
1392
1393/**
1394 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1395 * @vsi: the VSI to be searched
1396 * @macaddr: the MAC address
1397 * @vlan: the vlan
b40c82e6 1398 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1399 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1400 *
1401 * NOTE: This function is expected to be called with mac_filter_list_lock
1402 * being held.
41c445ff
JB		 1403 **/
1404void i40e_del_filter(struct i40e_vsi *vsi,
1405 u8 *macaddr, s16 vlan,
1406 bool is_vf, bool is_netdev)
1407{
1408 struct i40e_mac_filter *f;
1409
1410 if (!vsi || !macaddr)
1411 return;
1412
1413 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1414 if (!f || f->counter == 0)
1415 return;
1416
1417 if (is_vf) {
1418 if (f->is_vf) {
1419 f->is_vf = false;
1420 f->counter--;
1421 }
1422 } else if (is_netdev) {
1423 if (f->is_netdev) {
1424 f->is_netdev = false;
1425 f->counter--;
1426 }
1427 } else {
b40c82e6 1428 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1429 int min_f = 0;
6995b36c 1430
41c445ff
JB		 1431 min_f += (f->is_vf ? 1 : 0);
1432 min_f += (f->is_netdev ? 1 : 0);
1433
1434 if (f->counter > min_f)
1435 f->counter--;
1436 }
1437
1438 /* counter == 0 tells sync_filters_subtask to
1439 * remove the filter from the firmware's list
1440 */
1441 if (f->counter == 0) {
1442 f->changed = true;
1443 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1444 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1445 }
1446}
1447
1448/**
1449 * i40e_set_mac - NDO callback to set mac address
1450 * @netdev: network interface device structure
1451 * @p: pointer to an address structure
1452 *
1453 * Returns 0 on success, negative on failure
1454 **/
38e00438
VD		 1455#ifdef I40E_FCOE
1456int i40e_set_mac(struct net_device *netdev, void *p)
1457#else
41c445ff 1458static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1459#endif
41c445ff
JB		 1460{
1461 struct i40e_netdev_priv *np = netdev_priv(netdev);
1462 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1463 struct i40e_pf *pf = vsi->back;
1464 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1465 struct sockaddr *addr = p;
1466 struct i40e_mac_filter *f;
1467
1468 if (!is_valid_ether_addr(addr->sa_data))
1469 return -EADDRNOTAVAIL;
1470
30650cc5
SN		 1471 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1472 netdev_info(netdev, "already using mac address %pM\n",
1473 addr->sa_data);
1474 return 0;
1475 }
41c445ff 1476
80f6428f
ASJ		 1477 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1478 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1479 return -EADDRNOTAVAIL;
1480
30650cc5
SN		 1481 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1482 netdev_info(netdev, "returning to hw mac address %pM\n",
1483 hw->mac.addr);
1484 else
1485 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1486
41c445ff
JB		 1487 if (vsi->type == I40E_VSI_MAIN) {
1488 i40e_status ret;
6995b36c 1489
41c445ff 1490 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1491 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1492 addr->sa_data, NULL);
1493 if (ret) {
1494 netdev_info(netdev,
1495 "Addr change for Main VSI failed: %d\n",
1496 ret);
1497 return -EADDRNOTAVAIL;
1498 }
41c445ff
JB		 1499 }
1500
30650cc5
SN		 1501 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1502 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1503
30650cc5
SN		 1504 memset(&element, 0, sizeof(element));
1505 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1506 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1507 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1508 } else {
21659035 1509 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1510 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1511 false, false);
21659035 1512 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1513 }
41c445ff 1514
30650cc5
SN		 1515 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1516 struct i40e_aqc_add_macvlan_element_data element;
1517
1518 memset(&element, 0, sizeof(element));
1519 ether_addr_copy(element.mac_addr, hw->mac.addr);
1520 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1521 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1522 } else {
21659035 1523 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1524 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1525 false, false);
1526 if (f)
1527 f->is_laa = true;
21659035 1528 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1529 }
1530
30650cc5 1531 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b
MW		 1532
1533 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1534}
1535
1536/**
1537 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1538 * @vsi: the VSI being setup
1539 * @ctxt: VSI context structure
1540 * @enabled_tc: Enabled TCs bitmap
1541 * @is_add: True if called before Add VSI
1542 *
1543 * Setup VSI queue mapping for enabled traffic classes.
1544 **/
38e00438
VD		 1545#ifdef I40E_FCOE
1546void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1547 struct i40e_vsi_context *ctxt,
1548 u8 enabled_tc,
1549 bool is_add)
1550#else
41c445ff
JB		 1551static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1552 struct i40e_vsi_context *ctxt,
1553 u8 enabled_tc,
1554 bool is_add)
38e00438 1555#endif
41c445ff
JB		 1556{
1557 struct i40e_pf *pf = vsi->back;
1558 u16 sections = 0;
1559 u8 netdev_tc = 0;
1560 u16 numtc = 0;
1561 u16 qcount;
1562 u8 offset;
1563 u16 qmap;
1564 int i;
4e3b35b0 1565 u16 num_tc_qps = 0;
41c445ff
JB		 1566
1567 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1568 offset = 0;
1569
1570 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1571 /* Find numtc from enabled TC bitmap */
1572 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1573 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1574 numtc++;
1575 }
1576 if (!numtc) {
1577 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1578 numtc = 1;
1579 }
1580 } else {
1581 /* At least TC0 is enabled in case of non-DCB case */
1582 numtc = 1;
1583 }
1584
1585 vsi->tc_config.numtc = numtc;
1586 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1587 /* Number of queues per enabled TC */
7f9ff476
AS		 1588 /* In MFP case we can have a much lower count of MSIx
1589 * vectors available and so we need to lower the used
1590 * q count.
1591 */
26cdc443
ASJ		 1592 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1593 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1594 else
1595 qcount = vsi->alloc_queue_pairs;
7f9ff476 1596 num_tc_qps = qcount / numtc;
e25d00b8 1597 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1598
1599 /* Setup queue offset/count for all TCs for given VSI */
1600 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1601 /* See if the given TC is enabled for the given VSI */
75f5cea9 1602 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1603 /* TC is enabled */
41c445ff
JB		 1604 int pow, num_qps;
1605
41c445ff
JB		 1606 switch (vsi->type) {
1607 case I40E_VSI_MAIN:
acd65448
HZ		 1608 qcount = min_t(int, pf->alloc_rss_size,
1609 num_tc_qps);
41c445ff 1610 break;
38e00438
VD		 1611#ifdef I40E_FCOE
1612 case I40E_VSI_FCOE:
1613 qcount = num_tc_qps;
1614 break;
1615#endif
41c445ff
JB		 1616 case I40E_VSI_FDIR:
1617 case I40E_VSI_SRIOV:
1618 case I40E_VSI_VMDQ2:
1619 default:
4e3b35b0 1620 qcount = num_tc_qps;
41c445ff
JB		 1621 WARN_ON(i != 0);
1622 break;
1623 }
4e3b35b0
NP		 1624 vsi->tc_config.tc_info[i].qoffset = offset;
1625 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1626
1e200e4a 1627 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1628 num_qps = qcount;
41c445ff 1629 pow = 0;
41a1d04b 1630 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1631 pow++;
1632 num_qps >>= 1;
1633 }
1634
1635 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1636 qmap =
1637 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1638 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1639
4e3b35b0 1640 offset += qcount;
41c445ff
JB		 1641 } else {
1642 /* TC is not enabled so set the offset to
1643 * default queue and allocate one queue
1644 * for the given TC.
1645 */
1646 vsi->tc_config.tc_info[i].qoffset = 0;
1647 vsi->tc_config.tc_info[i].qcount = 1;
1648 vsi->tc_config.tc_info[i].netdev_tc = 0;
1649
1650 qmap = 0;
1651 }
1652 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1653 }
1654
1655 /* Set actual Tx/Rx queue pairs */
1656 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1657 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1658 if (vsi->req_queue_pairs > 0)
1659 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1660 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1661 vsi->num_queue_pairs = pf->num_lan_msix;
1662 }
41c445ff
JB		 1663
1664 /* Scheduler section valid can only be set for ADD VSI */
1665 if (is_add) {
1666 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1667
1668 ctxt->info.up_enable_bits = enabled_tc;
1669 }
1670 if (vsi->type == I40E_VSI_SRIOV) {
1671 ctxt->info.mapping_flags |=
1672 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1673 for (i = 0; i < vsi->num_queue_pairs; i++)
1674 ctxt->info.queue_mapping[i] =
1675 cpu_to_le16(vsi->base_queue + i);
1676 } else {
1677 ctxt->info.mapping_flags |=
1678 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1679 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1680 }
1681 ctxt->info.valid_sections |= cpu_to_le16(sections);
1682}
1683
1684/**
1685 * i40e_set_rx_mode - NDO callback to set the netdev filters
1686 * @netdev: network interface device structure
1687 **/
38e00438
VD		 1688#ifdef I40E_FCOE
1689void i40e_set_rx_mode(struct net_device *netdev)
1690#else
41c445ff 1691static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1692#endif
41c445ff
JB		 1693{
1694 struct i40e_netdev_priv *np = netdev_priv(netdev);
1695 struct i40e_mac_filter *f, *ftmp;
1696 struct i40e_vsi *vsi = np->vsi;
1697 struct netdev_hw_addr *uca;
1698 struct netdev_hw_addr *mca;
1699 struct netdev_hw_addr *ha;
1700
21659035
KP		 1701 spin_lock_bh(&vsi->mac_filter_list_lock);
1702
41c445ff
JB		 1703 /* add addr if not already in the filter list */
1704 netdev_for_each_uc_addr(uca, netdev) {
1705 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1706 if (i40e_is_vsi_in_vlan(vsi))
1707 i40e_put_mac_in_vlan(vsi, uca->addr,
1708 false, true);
1709 else
1710 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1711 false, true);
1712 }
1713 }
1714
1715 netdev_for_each_mc_addr(mca, netdev) {
1716 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1717 if (i40e_is_vsi_in_vlan(vsi))
1718 i40e_put_mac_in_vlan(vsi, mca->addr,
1719 false, true);
1720 else
1721 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1722 false, true);
1723 }
1724 }
1725
1726 /* remove filter if not in netdev list */
1727 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1728
1729 if (!f->is_netdev)
1730 continue;
1731
2f41f335
SN		 1732 netdev_for_each_mc_addr(mca, netdev)
1733 if (ether_addr_equal(mca->addr, f->macaddr))
1734 goto bottom_of_search_loop;
41c445ff 1735
2f41f335
SN		 1736 netdev_for_each_uc_addr(uca, netdev)
1737 if (ether_addr_equal(uca->addr, f->macaddr))
1738 goto bottom_of_search_loop;
1739
1740 for_each_dev_addr(netdev, ha)
1741 if (ether_addr_equal(ha->addr, f->macaddr))
1742 goto bottom_of_search_loop;
1743
1744 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1745 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1746
1747bottom_of_search_loop:
1748 continue;
41c445ff 1749 }
21659035 1750 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1751
1752 /* check for other flag changes */
1753 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1754 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1755 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1756 }
1757}
1758
21659035
KP		 1759/**
1760 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1761 * @src: source MAC filter entry to be clones
1762 *
1763 * Returns the pointer to newly cloned MAC filter entry or NULL
1764 * in case of error
1765 **/
1766static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1767 struct i40e_mac_filter *src)
1768{
1769 struct i40e_mac_filter *f;
1770
1771 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1772 if (!f)
1773 return NULL;
1774 *f = *src;
1775
1776 INIT_LIST_HEAD(&f->list);
1777
1778 return f;
1779}
1780
1781/**
1782 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1783 * @vsi: pointer to vsi struct
1784 * @from: Pointer to list which contains MAC filter entries - changes to
1785 * those entries needs to be undone.
1786 *
1787 * MAC filter entries from list were slated to be removed from device.
1788 **/
1789static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1790 struct list_head *from)
1791{
1792 struct i40e_mac_filter *f, *ftmp;
1793
1794 list_for_each_entry_safe(f, ftmp, from, list) {
1795 f->changed = true;
1796 /* Move the element back into MAC filter list*/
1797 list_move_tail(&f->list, &vsi->mac_filter_list);
1798 }
1799}
1800
1801/**
1802 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1803 * @vsi: pointer to vsi struct
1804 *
1805 * MAC filter entries from list were slated to be added from device.
1806 **/
1807static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1808{
1809 struct i40e_mac_filter *f, *ftmp;
1810
1811 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1812 if (!f->changed && f->counter)
1813 f->changed = true;
1814 }
1815}
1816
1817/**
1818 * i40e_cleanup_add_list - Deletes the element from add list and release
1819 * memory
1820 * @add_list: Pointer to list which contains MAC filter entries
1821 **/
1822static void i40e_cleanup_add_list(struct list_head *add_list)
1823{
1824 struct i40e_mac_filter *f, *ftmp;
1825
1826 list_for_each_entry_safe(f, ftmp, add_list, list) {
1827 list_del(&f->list);
1828 kfree(f);
1829 }
1830}
1831
41c445ff
JB		 1832/**
1833 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1834 * @vsi: ptr to the VSI
1835 *
1836 * Push any outstanding VSI filter changes through the AdminQ.
1837 *
1838 * Returns 0 or error value
1839 **/
17652c63 1840int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1841{
21659035
KP		 1842 struct list_head tmp_del_list, tmp_add_list;
1843 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1844 bool promisc_forced_on = false;
1845 bool add_happened = false;
1846 int filter_list_len = 0;
1847 u32 changed_flags = 0;
ea02e90b 1848 i40e_status aq_ret = 0;
21659035 1849 bool err_cond = false;
ea02e90b 1850 int retval = 0;
41c445ff
JB		 1851 struct i40e_pf *pf;
1852 int num_add = 0;
1853 int num_del = 0;
f1c7e72e 1854 int aq_err = 0;
41c445ff
JB		 1855 u16 cmd_flags;
1856
1857 /* empty array typed pointers, kcalloc later */
1858 struct i40e_aqc_add_macvlan_element_data *add_list;
1859 struct i40e_aqc_remove_macvlan_element_data *del_list;
1860
1861 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1862 usleep_range(1000, 2000);
1863 pf = vsi->back;
1864
1865 if (vsi->netdev) {
1866 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1867 vsi->current_netdev_flags = vsi->netdev->flags;
1868 }
1869
21659035
KP		 1870 INIT_LIST_HEAD(&tmp_del_list);
1871 INIT_LIST_HEAD(&tmp_add_list);
1872
41c445ff
JB		 1873 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1874 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1875
21659035 1876 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1877 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1878 if (!f->changed)
1879 continue;
1880
1881 if (f->counter != 0)
1882 continue;
1883 f->changed = false;
21659035
KP		 1884
1885 /* Move the element into temporary del_list */
1886 list_move_tail(&f->list, &tmp_del_list);
1887 }
1888
1889 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1890 if (!f->changed)
1891 continue;
1892
1893 if (f->counter == 0)
1894 continue;
1895 f->changed = false;
1896
1897 /* Clone MAC filter entry and add into temporary list */
1898 fclone = i40e_mac_filter_entry_clone(f);
1899 if (!fclone) {
1900 err_cond = true;
1901 break;
1902 }
1903 list_add_tail(&fclone->list, &tmp_add_list);
1904 }
1905
1906 /* if failed to clone MAC filter entry - undo */
1907 if (err_cond) {
1908 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1909 i40e_undo_add_filter_entries(vsi);
1910 }
1911 spin_unlock_bh(&vsi->mac_filter_list_lock);
1912
ea02e90b 1913 if (err_cond) {
21659035 1914 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1915 retval = -ENOMEM;
1916 goto out;
1917 }
21659035
KP		 1918 }
1919
1920 /* Now process 'del_list' outside the lock */
1921 if (!list_empty(&tmp_del_list)) {
f1199998
SN		 1922 int del_list_size;
1923
21659035
KP		 1924 filter_list_len = pf->hw.aq.asq_buf_size /
1925 sizeof(struct i40e_aqc_remove_macvlan_element_data);
f1199998
SN		 1926 del_list_size = filter_list_len *
1927 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1928 del_list = kzalloc(del_list_size, GFP_KERNEL);
21659035
KP		 1929 if (!del_list) {
1930 i40e_cleanup_add_list(&tmp_add_list);
1931
1932 /* Undo VSI's MAC filter entry element updates */
1933 spin_lock_bh(&vsi->mac_filter_list_lock);
1934 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1935 i40e_undo_add_filter_entries(vsi);
1936 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1937 retval = -ENOMEM;
1938 goto out;
21659035
KP		 1939 }
1940
1941 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1942 cmd_flags = 0;
1943
1944 /* add to delete list */
9a173901 1945 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1946 del_list[num_del].vlan_tag =
1947 cpu_to_le16((u16)(f->vlan ==
1948 I40E_VLAN_ANY ? 0 : f->vlan));
1949
41c445ff
JB		 1950 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1951 del_list[num_del].flags = cmd_flags;
1952 num_del++;
1953
41c445ff
JB		 1954 /* flush a full buffer */
1955 if (num_del == filter_list_len) {
ea02e90b
MW		 1956 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1957 vsi->seid,
1958 del_list,
1959 num_del,
1960 NULL);
f1c7e72e 1961 aq_err = pf->hw.aq.asq_last_status;
41c445ff 1962 num_del = 0;
f1199998 1963 memset(del_list, 0, del_list_size);
41c445ff 1964
ea02e90b
MW		 1965 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1966 retval = -EIO;
21659035
KP		 1967 dev_err(&pf->pdev->dev,
1968 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
ea02e90b 1969 i40e_stat_str(&pf->hw, aq_ret),
21659035 1970 i40e_aq_str(&pf->hw, aq_err));
ea02e90b 1971 }
41c445ff 1972 }
21659035
KP		 1973 /* Release memory for MAC filter entries which were
1974 * synced up with HW.
1975 */
1976 list_del(&f->list);
1977 kfree(f);
41c445ff 1978 }
21659035 1979
41c445ff 1980 if (num_del) {
ea02e90b
MW		 1981 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
1982 del_list, num_del,
1983 NULL);
f1c7e72e 1984 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1985 num_del = 0;
1986
ea02e90b 1987 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1988 dev_info(&pf->pdev->dev,
f1c7e72e 1989 "ignoring delete macvlan error, err %s aq_err %s\n",
ea02e90b 1990 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 1991 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1992 }
1993
1994 kfree(del_list);
1995 del_list = NULL;
21659035
KP		 1996 }
1997
1998 if (!list_empty(&tmp_add_list)) {
f1199998 1999 int add_list_size;
41c445ff
JB		 2000
2001 /* do all the adds now */
2002 filter_list_len = pf->hw.aq.asq_buf_size /
2003 sizeof(struct i40e_aqc_add_macvlan_element_data),
f1199998
SN		 2004 add_list_size = filter_list_len *
2005 sizeof(struct i40e_aqc_add_macvlan_element_data);
2006 add_list = kzalloc(add_list_size, GFP_KERNEL);
21659035
KP		 2007 if (!add_list) {
2008 /* Purge element from temporary lists */
2009 i40e_cleanup_add_list(&tmp_add_list);
2010
2011 /* Undo add filter entries from VSI MAC filter list */
2012 spin_lock_bh(&vsi->mac_filter_list_lock);
2013 i40e_undo_add_filter_entries(vsi);
2014 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2015 retval = -ENOMEM;
2016 goto out;
21659035 2017 }
41c445ff 2018
21659035 2019 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2020
41c445ff
JB		 2021 add_happened = true;
2022 cmd_flags = 0;
2023
2024 /* add to add array */
9a173901 2025 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2026 add_list[num_add].vlan_tag =
2027 cpu_to_le16(
2028 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2029 add_list[num_add].queue_number = 0;
2030
2031 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2032 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2033 num_add++;
2034
2035 /* flush a full buffer */
2036 if (num_add == filter_list_len) {
ea02e90b
MW		 2037 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2038 add_list, num_add,
2039 NULL);
f1c7e72e 2040 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2041 num_add = 0;
2042
ea02e90b 2043 if (aq_ret)
41c445ff 2044 break;
f1199998 2045 memset(add_list, 0, add_list_size);
41c445ff 2046 }
21659035
KP		 2047 /* Entries from tmp_add_list were cloned from MAC
2048 * filter list, hence clean those cloned entries
2049 */
2050 list_del(&f->list);
2051 kfree(f);
41c445ff 2052 }
21659035 2053
41c445ff 2054 if (num_add) {
ea02e90b
MW		 2055 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2056 add_list, num_add, NULL);
f1c7e72e 2057 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2058 num_add = 0;
2059 }
2060 kfree(add_list);
2061 add_list = NULL;
2062
ea02e90b
MW		 2063 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2064 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2065 dev_info(&pf->pdev->dev,
f1c7e72e 2066 "add filter failed, err %s aq_err %s\n",
ea02e90b 2067 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2068 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2069 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2070 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2071 &vsi->state)) {
2072 promisc_forced_on = true;
2073 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2074 &vsi->state);
2075 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2076 }
2077 }
2078 }
2079
2080 /* check for changes in promiscuous modes */
2081 if (changed_flags & IFF_ALLMULTI) {
2082 bool cur_multipromisc;
6995b36c 2083
41c445ff 2084 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2085 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2086 vsi->seid,
2087 cur_multipromisc,
2088 NULL);
2089 if (aq_ret) {
2090 retval = i40e_aq_rc_to_posix(aq_ret,
2091 pf->hw.aq.asq_last_status);
41c445ff 2092 dev_info(&pf->pdev->dev,
f1c7e72e 2093 "set multi promisc failed, err %s aq_err %s\n",
ea02e90b 2094 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2095 i40e_aq_str(&pf->hw,
2096 pf->hw.aq.asq_last_status));
ea02e90b 2097 }
41c445ff
JB		 2098 }
2099 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2100 bool cur_promisc;
6995b36c 2101
41c445ff
JB		 2102 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2103 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2104 &vsi->state));
92faef85
ASJ		 2105 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
2106 /* set defport ON for Main VSI instead of true promisc
2107 * this way we will get all unicast/multicast and VLAN
2108 * promisc behavior but will not get VF or VMDq traffic
2109 * replicated on the Main VSI.
2110 */
2111 if (pf->cur_promisc != cur_promisc) {
2112 pf->cur_promisc = cur_promisc;
0e4425ed 2113 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2114 }
2115 } else {
ea02e90b 2116 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
92faef85 2117 &vsi->back->hw,
f1c7e72e
SN		 2118 vsi->seid,
2119 cur_promisc, NULL);
ea02e90b
MW		 2120 if (aq_ret) {
2121 retval =
2122 i40e_aq_rc_to_posix(aq_ret,
2123 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2124 dev_info(&pf->pdev->dev,
2125 "set unicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2126 aq_ret, pf->hw.aq.asq_last_status);
2127 }
2128 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
92faef85
ASJ		 2129 &vsi->back->hw,
2130 vsi->seid,
2131 cur_promisc, NULL);
ea02e90b
MW		 2132 if (aq_ret) {
2133 retval =
2134 i40e_aq_rc_to_posix(aq_ret,
2135 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2136 dev_info(&pf->pdev->dev,
2137 "set multicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2138 aq_ret, pf->hw.aq.asq_last_status);
2139 }
92faef85 2140 }
ea02e90b
MW		 2141 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2142 vsi->seid,
2143 cur_promisc, NULL);
2144 if (aq_ret) {
2145 retval = i40e_aq_rc_to_posix(aq_ret,
2146 pf->hw.aq.asq_last_status);
1a10370a 2147 dev_info(&pf->pdev->dev,
f1c7e72e 2148 "set brdcast promisc failed, err %s, aq_err %s\n",
ea02e90b 2149 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2150 i40e_aq_str(&pf->hw,
2151 pf->hw.aq.asq_last_status));
ea02e90b 2152 }
41c445ff 2153 }
ea02e90b 2154out:
41c445ff 2155 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2156 return retval;
41c445ff
JB		 2157}
2158
2159/**
2160 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2161 * @pf: board private structure
2162 **/
2163static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2164{
2165 int v;
2166
2167 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2168 return;
2169 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2170
505682cd 2171 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2172 if (pf->vsi[v] &&
17652c63
JB		 2173 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2174 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2175
2176 if (ret) {
2177 /* come back and try again later */
2178 pf->flags |= I40E_FLAG_FILTER_SYNC;
2179 break;
2180 }
2181 }
41c445ff
JB		 2182 }
2183}
2184
2185/**
2186 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2187 * @netdev: network interface device structure
2188 * @new_mtu: new value for maximum frame size
2189 *
2190 * Returns 0 on success, negative on failure
2191 **/
2192static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2193{
2194 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2195 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2196 struct i40e_vsi *vsi = np->vsi;
2197
2198 /* MTU < 68 is an error and causes problems on some kernels */
2199 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2200 return -EINVAL;
2201
2202 netdev_info(netdev, "changing MTU from %d to %d\n",
2203 netdev->mtu, new_mtu);
2204 netdev->mtu = new_mtu;
2205 if (netif_running(netdev))
2206 i40e_vsi_reinit_locked(vsi);
2207
2208 return 0;
2209}
2210
beb0dff1
JK		 2211/**
2212 * i40e_ioctl - Access the hwtstamp interface
2213 * @netdev: network interface device structure
2214 * @ifr: interface request data
2215 * @cmd: ioctl command
2216 **/
2217int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2218{
2219 struct i40e_netdev_priv *np = netdev_priv(netdev);
2220 struct i40e_pf *pf = np->vsi->back;
2221
2222 switch (cmd) {
2223 case SIOCGHWTSTAMP:
2224 return i40e_ptp_get_ts_config(pf, ifr);
2225 case SIOCSHWTSTAMP:
2226 return i40e_ptp_set_ts_config(pf, ifr);
2227 default:
2228 return -EOPNOTSUPP;
2229 }
2230}
2231
41c445ff
JB		 2232/**
2233 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2234 * @vsi: the vsi being adjusted
2235 **/
2236void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2237{
2238 struct i40e_vsi_context ctxt;
2239 i40e_status ret;
2240
2241 if ((vsi->info.valid_sections &
2242 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2243 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2244 return; /* already enabled */
2245
2246 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2247 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2248 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2249
2250 ctxt.seid = vsi->seid;
1a2f6248 2251 ctxt.info = vsi->info;
41c445ff
JB		 2252 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2253 if (ret) {
2254 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2255 "update vlan stripping failed, err %s aq_err %s\n",
2256 i40e_stat_str(&vsi->back->hw, ret),
2257 i40e_aq_str(&vsi->back->hw,
2258 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2259 }
2260}
2261
2262/**
2263 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2264 * @vsi: the vsi being adjusted
2265 **/
2266void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2267{
2268 struct i40e_vsi_context ctxt;
2269 i40e_status ret;
2270
2271 if ((vsi->info.valid_sections &
2272 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2273 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2274 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2275 return; /* already disabled */
2276
2277 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2278 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2279 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2280
2281 ctxt.seid = vsi->seid;
1a2f6248 2282 ctxt.info = vsi->info;
41c445ff
JB		 2283 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2284 if (ret) {
2285 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2286 "update vlan stripping failed, err %s aq_err %s\n",
2287 i40e_stat_str(&vsi->back->hw, ret),
2288 i40e_aq_str(&vsi->back->hw,
2289 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2290 }
2291}
2292
2293/**
2294 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2295 * @netdev: network interface to be adjusted
2296 * @features: netdev features to test if VLAN offload is enabled or not
2297 **/
2298static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2299{
2300 struct i40e_netdev_priv *np = netdev_priv(netdev);
2301 struct i40e_vsi *vsi = np->vsi;
2302
2303 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2304 i40e_vlan_stripping_enable(vsi);
2305 else
2306 i40e_vlan_stripping_disable(vsi);
2307}
2308
2309/**
2310 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2311 * @vsi: the vsi being configured
2312 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2313 **/
2314int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2315{
2316 struct i40e_mac_filter *f, *add_f;
2317 bool is_netdev, is_vf;
41c445ff
JB		 2318
2319 is_vf = (vsi->type == I40E_VSI_SRIOV);
2320 is_netdev = !!(vsi->netdev);
2321
21659035
KP		 2322 /* Locked once because all functions invoked below iterates list*/
2323 spin_lock_bh(&vsi->mac_filter_list_lock);
2324
41c445ff
JB		 2325 if (is_netdev) {
2326 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2327 is_vf, is_netdev);
2328 if (!add_f) {
2329 dev_info(&vsi->back->pdev->dev,
2330 "Could not add vlan filter %d for %pM\n",
2331 vid, vsi->netdev->dev_addr);
21659035 2332 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2333 return -ENOMEM;
2334 }
2335 }
2336
2337 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2338 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2339 if (!add_f) {
2340 dev_info(&vsi->back->pdev->dev,
2341 "Could not add vlan filter %d for %pM\n",
2342 vid, f->macaddr);
21659035 2343 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2344 return -ENOMEM;
2345 }
2346 }
2347
41c445ff
JB		 2348 /* Now if we add a vlan tag, make sure to check if it is the first
2349 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2350 * with 0, so we now accept untagged and specified tagged traffic
2351 * (and not any taged and untagged)
2352 */
2353 if (vid > 0) {
2354 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2355 I40E_VLAN_ANY,
2356 is_vf, is_netdev)) {
2357 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2358 I40E_VLAN_ANY, is_vf, is_netdev);
2359 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2360 is_vf, is_netdev);
2361 if (!add_f) {
2362 dev_info(&vsi->back->pdev->dev,
2363 "Could not add filter 0 for %pM\n",
2364 vsi->netdev->dev_addr);
21659035 2365 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2366 return -ENOMEM;
2367 }
2368 }
8d82a7c5 2369 }
41c445ff 2370
8d82a7c5
GR		 2371 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2372 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2373 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2374 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2375 is_vf, is_netdev))
2376 continue;
2377 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2378 is_vf, is_netdev);
2379 add_f = i40e_add_filter(vsi, f->macaddr,
2380 0, is_vf, is_netdev);
2381 if (!add_f) {
2382 dev_info(&vsi->back->pdev->dev,
2383 "Could not add filter 0 for %pM\n",
2384 f->macaddr);
2385 spin_unlock_bh(&vsi->mac_filter_list_lock);
2386 return -ENOMEM;
41c445ff
JB		 2387 }
2388 }
41c445ff
JB		 2389 }
2390
21659035
KP		 2391 spin_unlock_bh(&vsi->mac_filter_list_lock);
2392
0e4425ed
JB		 2393 /* schedule our worker thread which will take care of
2394 * applying the new filter changes
2395 */
2396 i40e_service_event_schedule(vsi->back);
2397 return 0;
41c445ff
JB		 2398}
2399
2400/**
2401 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2402 * @vsi: the vsi being configured
2403 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2404 *
2405 * Return: 0 on success or negative otherwise
41c445ff
JB		 2406 **/
2407int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2408{
2409 struct net_device *netdev = vsi->netdev;
2410 struct i40e_mac_filter *f, *add_f;
2411 bool is_vf, is_netdev;
2412 int filter_count = 0;
41c445ff
JB		 2413
2414 is_vf = (vsi->type == I40E_VSI_SRIOV);
2415 is_netdev = !!(netdev);
2416
21659035
KP		 2417 /* Locked once because all functions invoked below iterates list */
2418 spin_lock_bh(&vsi->mac_filter_list_lock);
2419
41c445ff
JB		 2420 if (is_netdev)
2421 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2422
2423 list_for_each_entry(f, &vsi->mac_filter_list, list)
2424 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2425
41c445ff
JB		 2426 /* go through all the filters for this VSI and if there is only
2427 * vid == 0 it means there are no other filters, so vid 0 must
2428 * be replaced with -1. This signifies that we should from now
2429 * on accept any traffic (with any tag present, or untagged)
2430 */
2431 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2432 if (is_netdev) {
2433 if (f->vlan &&
2434 ether_addr_equal(netdev->dev_addr, f->macaddr))
2435 filter_count++;
2436 }
2437
2438 if (f->vlan)
2439 filter_count++;
2440 }
2441
2442 if (!filter_count && is_netdev) {
2443 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2444 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2445 is_vf, is_netdev);
2446 if (!f) {
2447 dev_info(&vsi->back->pdev->dev,
2448 "Could not add filter %d for %pM\n",
2449 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2450 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2451 return -ENOMEM;
2452 }
2453 }
2454
2455 if (!filter_count) {
2456 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2457 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2458 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2459 is_vf, is_netdev);
41c445ff
JB		 2460 if (!add_f) {
2461 dev_info(&vsi->back->pdev->dev,
2462 "Could not add filter %d for %pM\n",
2463 I40E_VLAN_ANY, f->macaddr);
21659035 2464 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2465 return -ENOMEM;
2466 }
2467 }
2468 }
2469
21659035
KP		 2470 spin_unlock_bh(&vsi->mac_filter_list_lock);
2471
0e4425ed
JB		 2472 /* schedule our worker thread which will take care of
2473 * applying the new filter changes
2474 */
2475 i40e_service_event_schedule(vsi->back);
2476 return 0;
41c445ff
JB		 2477}
2478
2479/**
2480 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2481 * @netdev: network interface to be adjusted
2482 * @vid: vlan id to be added
078b5876
JB		 2483 *
2484 * net_device_ops implementation for adding vlan ids
41c445ff 2485 **/
38e00438
VD		 2486#ifdef I40E_FCOE
2487int i40e_vlan_rx_add_vid(struct net_device *netdev,
2488 __always_unused __be16 proto, u16 vid)
2489#else
41c445ff
JB		 2490static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2491 __always_unused __be16 proto, u16 vid)
38e00438 2492#endif
41c445ff
JB		 2493{
2494 struct i40e_netdev_priv *np = netdev_priv(netdev);
2495 struct i40e_vsi *vsi = np->vsi;
078b5876 2496 int ret = 0;
41c445ff
JB		 2497
2498 if (vid > 4095)
078b5876
JB		 2499 return -EINVAL;
2500
2501 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2502
6982d429
ASJ		 2503 /* If the network stack called us with vid = 0 then
2504 * it is asking to receive priority tagged packets with
2505 * vlan id 0. Our HW receives them by default when configured
2506 * to receive untagged packets so there is no need to add an
2507 * extra filter for vlan 0 tagged packets.
41c445ff 2508 */
6982d429
ASJ		 2509 if (vid)
2510 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2511
078b5876
JB		 2512 if (!ret && (vid < VLAN_N_VID))
2513 set_bit(vid, vsi->active_vlans);
41c445ff 2514
078b5876 2515 return ret;
41c445ff
JB		 2516}
2517
2518/**
2519 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2520 * @netdev: network interface to be adjusted
2521 * @vid: vlan id to be removed
078b5876 2522 *
fdfd943e 2523 * net_device_ops implementation for removing vlan ids
41c445ff 2524 **/
38e00438
VD		 2525#ifdef I40E_FCOE
2526int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2527 __always_unused __be16 proto, u16 vid)
2528#else
41c445ff
JB		 2529static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2530 __always_unused __be16 proto, u16 vid)
38e00438 2531#endif
41c445ff
JB		 2532{
2533 struct i40e_netdev_priv *np = netdev_priv(netdev);
2534 struct i40e_vsi *vsi = np->vsi;
2535
078b5876
JB		 2536 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2537
41c445ff
JB		 2538 /* return code is ignored as there is nothing a user
2539 * can do about failure to remove and a log message was
078b5876 2540 * already printed from the other function
41c445ff
JB		 2541 */
2542 i40e_vsi_kill_vlan(vsi, vid);
2543
2544 clear_bit(vid, vsi->active_vlans);
078b5876 2545
41c445ff
JB		 2546 return 0;
2547}
2548
2549/**
2550 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2551 * @vsi: the vsi being brought back up
2552 **/
2553static void i40e_restore_vlan(struct i40e_vsi *vsi)
2554{
2555 u16 vid;
2556
2557 if (!vsi->netdev)
2558 return;
2559
2560 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2561
2562 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2563 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2564 vid);
2565}
2566
2567/**
2568 * i40e_vsi_add_pvid - Add pvid for the VSI
2569 * @vsi: the vsi being adjusted
2570 * @vid: the vlan id to set as a PVID
2571 **/
dcae29be 2572int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2573{
2574 struct i40e_vsi_context ctxt;
f1c7e72e 2575 i40e_status ret;
41c445ff
JB		 2576
2577 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2578 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2579 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2580 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2581 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2582
2583 ctxt.seid = vsi->seid;
1a2f6248 2584 ctxt.info = vsi->info;
f1c7e72e
SN		 2585 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2586 if (ret) {
41c445ff 2587 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2588 "add pvid failed, err %s aq_err %s\n",
2589 i40e_stat_str(&vsi->back->hw, ret),
2590 i40e_aq_str(&vsi->back->hw,
2591 vsi->back->hw.aq.asq_last_status));
dcae29be 2592 return -ENOENT;
41c445ff
JB		 2593 }
2594
dcae29be 2595 return 0;
41c445ff
JB		 2596}
2597
2598/**
2599 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2600 * @vsi: the vsi being adjusted
2601 *
2602 * Just use the vlan_rx_register() service to put it back to normal
2603 **/
2604void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2605{
6c12fcbf
GR		 2606 i40e_vlan_stripping_disable(vsi);
2607
41c445ff 2608 vsi->info.pvid = 0;
41c445ff
JB		 2609}
2610
2611/**
2612 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2613 * @vsi: ptr to the VSI
2614 *
2615 * If this function returns with an error, then it's possible one or
2616 * more of the rings is populated (while the rest are not). It is the
2617 * callers duty to clean those orphaned rings.
2618 *
2619 * Return 0 on success, negative on failure
2620 **/
2621static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2622{
2623 int i, err = 0;
2624
2625 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2626 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2627
2628 return err;
2629}
2630
2631/**
2632 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2633 * @vsi: ptr to the VSI
2634 *
2635 * Free VSI's transmit software resources
2636 **/
2637static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2638{
2639 int i;
2640
8e9dca53
GR		 2641 if (!vsi->tx_rings)
2642 return;
2643
41c445ff 2644 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2645 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2646 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2647}
2648
2649/**
2650 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2651 * @vsi: ptr to the VSI
2652 *
2653 * If this function returns with an error, then it's possible one or
2654 * more of the rings is populated (while the rest are not). It is the
2655 * callers duty to clean those orphaned rings.
2656 *
2657 * Return 0 on success, negative on failure
2658 **/
2659static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2660{
2661 int i, err = 0;
2662
2663 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2664 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2665#ifdef I40E_FCOE
2666 i40e_fcoe_setup_ddp_resources(vsi);
2667#endif
41c445ff
JB		 2668 return err;
2669}
2670
2671/**
2672 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2673 * @vsi: ptr to the VSI
2674 *
2675 * Free all receive software resources
2676 **/
2677static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2678{
2679 int i;
2680
8e9dca53
GR		 2681 if (!vsi->rx_rings)
2682 return;
2683
41c445ff 2684 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2685 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2686 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2687#ifdef I40E_FCOE
2688 i40e_fcoe_free_ddp_resources(vsi);
2689#endif
41c445ff
JB		 2690}
2691
3ffa037d
NP		 2692/**
2693 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2694 * @ring: The Tx ring to configure
2695 *
2696 * This enables/disables XPS for a given Tx descriptor ring
2697 * based on the TCs enabled for the VSI that ring belongs to.
2698 **/
2699static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2700{
2701 struct i40e_vsi *vsi = ring->vsi;
2702 cpumask_var_t mask;
2703
9a660eea
JB		 2704 if (!ring->q_vector || !ring->netdev)
2705 return;
2706
2707 /* Single TC mode enable XPS */
2708 if (vsi->tc_config.numtc <= 1) {
2709 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2710 netif_set_xps_queue(ring->netdev,
2711 &ring->q_vector->affinity_mask,
2712 ring->queue_index);
9a660eea
JB		 2713 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2714 /* Disable XPS to allow selection based on TC */
2715 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2716 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2717 free_cpumask_var(mask);
3ffa037d 2718 }
0e4425ed
JB		 2719
2720 /* schedule our worker thread which will take care of
2721 * applying the new filter changes
2722 */
2723 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2724}
2725
41c445ff
JB		 2726/**
2727 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2728 * @ring: The Tx ring to configure
2729 *
2730 * Configure the Tx descriptor ring in the HMC context.
2731 **/
2732static int i40e_configure_tx_ring(struct i40e_ring *ring)
2733{
2734 struct i40e_vsi *vsi = ring->vsi;
2735 u16 pf_q = vsi->base_queue + ring->queue_index;
2736 struct i40e_hw *hw = &vsi->back->hw;
2737 struct i40e_hmc_obj_txq tx_ctx;
2738 i40e_status err = 0;
2739 u32 qtx_ctl = 0;
2740
2741 /* some ATR related tx ring init */
60ea5f83 2742 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2743 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2744 ring->atr_count = 0;
2745 } else {
2746 ring->atr_sample_rate = 0;
2747 }
2748
3ffa037d
NP		 2749 /* configure XPS */
2750 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2751
2752 /* clear the context structure first */
2753 memset(&tx_ctx, 0, sizeof(tx_ctx));
2754
2755 tx_ctx.new_context = 1;
2756 tx_ctx.base = (ring->dma / 128);
2757 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2758 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2759 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2760#ifdef I40E_FCOE
2761 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2762#endif
beb0dff1 2763 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2764 /* FDIR VSI tx ring can still use RS bit and writebacks */
2765 if (vsi->type != I40E_VSI_FDIR)
2766 tx_ctx.head_wb_ena = 1;
2767 tx_ctx.head_wb_addr = ring->dma +
2768 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2769
2770 /* As part of VSI creation/update, FW allocates certain
2771 * Tx arbitration queue sets for each TC enabled for
2772 * the VSI. The FW returns the handles to these queue
2773 * sets as part of the response buffer to Add VSI,
2774 * Update VSI, etc. AQ commands. It is expected that
2775 * these queue set handles be associated with the Tx
2776 * queues by the driver as part of the TX queue context
2777 * initialization. This has to be done regardless of
2778 * DCB as by default everything is mapped to TC0.
2779 */
2780 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2781 tx_ctx.rdylist_act = 0;
2782
2783 /* clear the context in the HMC */
2784 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2785 if (err) {
2786 dev_info(&vsi->back->pdev->dev,
2787 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2788 ring->queue_index, pf_q, err);
2789 return -ENOMEM;
2790 }
2791
2792 /* set the context in the HMC */
2793 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2794 if (err) {
2795 dev_info(&vsi->back->pdev->dev,
2796 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2797 ring->queue_index, pf_q, err);
2798 return -ENOMEM;
2799 }
2800
2801 /* Now associate this queue with this PCI function */
7a28d885 2802 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2803 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2804 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2805 I40E_QTX_CTL_VFVM_INDX_MASK;
2806 } else {
9d8bf547 2807 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2808 }
2809
13fd9774
SN		 2810 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2811 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2812 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2813 i40e_flush(hw);
2814
41c445ff
JB		 2815 /* cache tail off for easier writes later */
2816 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2817
2818 return 0;
2819}
2820
2821/**
2822 * i40e_configure_rx_ring - Configure a receive ring context
2823 * @ring: The Rx ring to configure
2824 *
2825 * Configure the Rx descriptor ring in the HMC context.
2826 **/
2827static int i40e_configure_rx_ring(struct i40e_ring *ring)
2828{
2829 struct i40e_vsi *vsi = ring->vsi;
2830 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2831 u16 pf_q = vsi->base_queue + ring->queue_index;
2832 struct i40e_hw *hw = &vsi->back->hw;
2833 struct i40e_hmc_obj_rxq rx_ctx;
2834 i40e_status err = 0;
2835
2836 ring->state = 0;
2837
2838 /* clear the context structure first */
2839 memset(&rx_ctx, 0, sizeof(rx_ctx));
2840
2841 ring->rx_buf_len = vsi->rx_buf_len;
2842 ring->rx_hdr_len = vsi->rx_hdr_len;
2843
2844 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2845 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2846
2847 rx_ctx.base = (ring->dma / 128);
2848 rx_ctx.qlen = ring->count;
2849
2850 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2851 set_ring_16byte_desc_enabled(ring);
2852 rx_ctx.dsize = 0;
2853 } else {
2854 rx_ctx.dsize = 1;
2855 }
2856
2857 rx_ctx.dtype = vsi->dtype;
2858 if (vsi->dtype) {
2859 set_ring_ps_enabled(ring);
2860 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2861 I40E_RX_SPLIT_IP |
2862 I40E_RX_SPLIT_TCP_UDP |
2863 I40E_RX_SPLIT_SCTP;
2864 } else {
2865 rx_ctx.hsplit_0 = 0;
2866 }
2867
2868 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2869 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2870 if (hw->revision_id == 0)
2871 rx_ctx.lrxqthresh = 0;
2872 else
2873 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2874 rx_ctx.crcstrip = 1;
2875 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2876 /* this controls whether VLAN is stripped from inner headers */
2877 rx_ctx.showiv = 0;
38e00438
VD		 2878#ifdef I40E_FCOE
2879 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2880#endif
acb3676b
CS		 2881 /* set the prefena field to 1 because the manual says to */
2882 rx_ctx.prefena = 1;
41c445ff
JB		 2883
2884 /* clear the context in the HMC */
2885 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2886 if (err) {
2887 dev_info(&vsi->back->pdev->dev,
2888 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2889 ring->queue_index, pf_q, err);
2890 return -ENOMEM;
2891 }
2892
2893 /* set the context in the HMC */
2894 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2895 if (err) {
2896 dev_info(&vsi->back->pdev->dev,
2897 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2898 ring->queue_index, pf_q, err);
2899 return -ENOMEM;
2900 }
2901
2902 /* cache tail for quicker writes, and clear the reg before use */
2903 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2904 writel(0, ring->tail);
2905
a132af24
MW		 2906 if (ring_is_ps_enabled(ring)) {
2907 i40e_alloc_rx_headers(ring);
2908 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2909 } else {
2910 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2911 }
41c445ff
JB		 2912
2913 return 0;
2914}
2915
2916/**
2917 * i40e_vsi_configure_tx - Configure the VSI for Tx
2918 * @vsi: VSI structure describing this set of rings and resources
2919 *
2920 * Configure the Tx VSI for operation.
2921 **/
2922static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2923{
2924 int err = 0;
2925 u16 i;
2926
9f65e15b
AD		 2927 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2928 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2929
2930 return err;
2931}
2932
2933/**
2934 * i40e_vsi_configure_rx - Configure the VSI for Rx
2935 * @vsi: the VSI being configured
2936 *
2937 * Configure the Rx VSI for operation.
2938 **/
2939static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2940{
2941 int err = 0;
2942 u16 i;
2943
2944 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2945 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2946 + ETH_FCS_LEN + VLAN_HLEN;
2947 else
2948 vsi->max_frame = I40E_RXBUFFER_2048;
2949
2950 /* figure out correct receive buffer length */
2951 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2952 I40E_FLAG_RX_PS_ENABLED)) {
2953 case I40E_FLAG_RX_1BUF_ENABLED:
2954 vsi->rx_hdr_len = 0;
2955 vsi->rx_buf_len = vsi->max_frame;
2956 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2957 break;
2958 case I40E_FLAG_RX_PS_ENABLED:
2959 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2960 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2961 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2962 break;
2963 default:
2964 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2965 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2966 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2967 break;
2968 }
2969
38e00438
VD		 2970#ifdef I40E_FCOE
2971 /* setup rx buffer for FCoE */
2972 if ((vsi->type == I40E_VSI_FCOE) &&
2973 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2974 vsi->rx_hdr_len = 0;
2975 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2976 vsi->max_frame = I40E_RXBUFFER_3072;
2977 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2978 }
2979
2980#endif /* I40E_FCOE */
41c445ff
JB		 2981 /* round up for the chip's needs */
2982 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2983 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2984 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2985 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2986
2987 /* set up individual rings */
2988 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2989 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2990
2991 return err;
2992}
2993
2994/**
2995 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2996 * @vsi: ptr to the VSI
2997 **/
2998static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2999{
e7046ee1 3000 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 3001 u16 qoffset, qcount;
3002 int i, n;
3003
cd238a3e
PN		 3004 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3005 /* Reset the TC information */
3006 for (i = 0; i < vsi->num_queue_pairs; i++) {
3007 rx_ring = vsi->rx_rings[i];
3008 tx_ring = vsi->tx_rings[i];
3009 rx_ring->dcb_tc = 0;
3010 tx_ring->dcb_tc = 0;
3011 }
3012 }
41c445ff
JB		 3013
3014 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3015 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3016 continue;
3017
3018 qoffset = vsi->tc_config.tc_info[n].qoffset;
3019 qcount = vsi->tc_config.tc_info[n].qcount;
3020 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3021 rx_ring = vsi->rx_rings[i];
3022 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3023 rx_ring->dcb_tc = n;
3024 tx_ring->dcb_tc = n;
3025 }
3026 }
3027}
3028
3029/**
3030 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3031 * @vsi: ptr to the VSI
3032 **/
3033static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3034{
3035 if (vsi->netdev)
3036 i40e_set_rx_mode(vsi->netdev);
3037}
3038
17a73f6b
JG		 3039/**
3040 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3041 * @vsi: Pointer to the targeted VSI
3042 *
3043 * This function replays the hlist on the hw where all the SB Flow Director
3044 * filters were saved.
3045 **/
3046static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3047{
3048 struct i40e_fdir_filter *filter;
3049 struct i40e_pf *pf = vsi->back;
3050 struct hlist_node *node;
3051
55a5e60b
ASJ		 3052 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3053 return;
3054
17a73f6b
JG		 3055 hlist_for_each_entry_safe(filter, node,
3056 &pf->fdir_filter_list, fdir_node) {
3057 i40e_add_del_fdir(vsi, filter, true);
3058 }
3059}
3060
41c445ff
JB		 3061/**
3062 * i40e_vsi_configure - Set up the VSI for action
3063 * @vsi: the VSI being configured
3064 **/
3065static int i40e_vsi_configure(struct i40e_vsi *vsi)
3066{
3067 int err;
3068
3069 i40e_set_vsi_rx_mode(vsi);
3070 i40e_restore_vlan(vsi);
3071 i40e_vsi_config_dcb_rings(vsi);
3072 err = i40e_vsi_configure_tx(vsi);
3073 if (!err)
3074 err = i40e_vsi_configure_rx(vsi);
3075
3076 return err;
3077}
3078
3079/**
3080 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3081 * @vsi: the VSI being configured
3082 **/
3083static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3084{
3085 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3086 struct i40e_hw *hw = &pf->hw;
3087 u16 vector;
3088 int i, q;
41c445ff
JB		 3089 u32 qp;
3090
3091 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3092 * and PFINT_LNKLSTn registers, e.g.:
3093 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3094 */
3095 qp = vsi->base_queue;
3096 vector = vsi->base_vector;
493fb300 3097 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3098 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3099
ee2319cf 3100 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3101 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3102 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3103 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3104 q_vector->rx.itr);
3105 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3106 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3107 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3108 q_vector->tx.itr);
ac26fc13
JB		 3109 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3110 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3111
3112 /* Linked list for the queuepairs assigned to this vector */
3113 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3114 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3115 u32 val;
3116
41c445ff
JB		 3117 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3118 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3119 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3120 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3121 (I40E_QUEUE_TYPE_TX
3122 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3123
3124 wr32(hw, I40E_QINT_RQCTL(qp), val);
3125
3126 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3127 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3128 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3129 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3130 (I40E_QUEUE_TYPE_RX
3131 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3132
3133 /* Terminate the linked list */
3134 if (q == (q_vector->num_ringpairs - 1))
3135 val |= (I40E_QUEUE_END_OF_LIST
3136 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3137
3138 wr32(hw, I40E_QINT_TQCTL(qp), val);
3139 qp++;
3140 }
3141 }
3142
3143 i40e_flush(hw);
3144}
3145
3146/**
3147 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3148 * @hw: ptr to the hardware info
3149 **/
ab437b5a 3150static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3151{
ab437b5a 3152 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3153 u32 val;
3154
3155 /* clear things first */
3156 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3157 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3158
3159 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3160 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3161 I40E_PFINT_ICR0_ENA_GRST_MASK |
3162 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3163 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3164 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3165 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3166 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3167
0d8e1439
ASJ		 3168 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3169 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3170
ab437b5a
JK		 3171 if (pf->flags & I40E_FLAG_PTP)
3172 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3173
41c445ff
JB		 3174 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3175
3176 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3177 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3178 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3179
3180 /* OTHER_ITR_IDX = 0 */
3181 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3182}
3183
3184/**
3185 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3186 * @vsi: the VSI being configured
3187 **/
3188static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3189{
493fb300 3190 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3191 struct i40e_pf *pf = vsi->back;
3192 struct i40e_hw *hw = &pf->hw;
3193 u32 val;
3194
3195 /* set the ITR configuration */
ee2319cf 3196 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3197 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3198 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3199 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3200 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3201 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3202 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3203
ab437b5a 3204 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3205
3206 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3207 wr32(hw, I40E_PFINT_LNKLST0, 0);
3208
f29eaa3d 3209 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3210 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3211 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3212 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3213
3214 wr32(hw, I40E_QINT_RQCTL(0), val);
3215
3216 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3217 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3218 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3219
3220 wr32(hw, I40E_QINT_TQCTL(0), val);
3221 i40e_flush(hw);
3222}
3223
2ef28cfb
MW		 3224/**
3225 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3226 * @pf: board private structure
3227 **/
3228void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3229{
3230 struct i40e_hw *hw = &pf->hw;
3231
3232 wr32(hw, I40E_PFINT_DYN_CTL0,
3233 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3234 i40e_flush(hw);
3235}
3236
41c445ff
JB		 3237/**
3238 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3239 * @pf: board private structure
3240 **/
116a57d4 3241void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3242{
3243 struct i40e_hw *hw = &pf->hw;
3244 u32 val;
3245
3246 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3247 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3248 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3249
3250 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3251 i40e_flush(hw);
3252}
3253
5c2cebda
CW		 3254/**
3255 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3256 * @vsi: pointer to a vsi
03147773 3257 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3258 **/
3259void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3260{
3261 struct i40e_pf *pf = vsi->back;
3262 struct i40e_hw *hw = &pf->hw;
3263 u32 val;
3264
3265 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3266 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3267 i40e_flush(hw);
3268}
3269
41c445ff
JB		 3270/**
3271 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3272 * @irq: interrupt number
3273 * @data: pointer to a q_vector
3274 **/
3275static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3276{
3277 struct i40e_q_vector *q_vector = data;
3278
cd0b6fa6 3279 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3280 return IRQ_HANDLED;
3281
5d3465a1 3282 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3283
3284 return IRQ_HANDLED;
3285}
3286
41c445ff
JB		 3287/**
3288 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3289 * @vsi: the VSI being configured
3290 * @basename: name for the vector
3291 *
3292 * Allocates MSI-X vectors and requests interrupts from the kernel.
3293 **/
3294static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3295{
3296 int q_vectors = vsi->num_q_vectors;
3297 struct i40e_pf *pf = vsi->back;
3298 int base = vsi->base_vector;
3299 int rx_int_idx = 0;
3300 int tx_int_idx = 0;
3301 int vector, err;
3302
3303 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3304 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3305
cd0b6fa6 3306 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3307 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3308 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3309 tx_int_idx++;
cd0b6fa6 3310 } else if (q_vector->rx.ring) {
41c445ff
JB		 3311 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3312 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3313 } else if (q_vector->tx.ring) {
41c445ff
JB		 3314 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3315 "%s-%s-%d", basename, "tx", tx_int_idx++);
3316 } else {
3317 /* skip this unused q_vector */
3318 continue;
3319 }
3320 err = request_irq(pf->msix_entries[base + vector].vector,
3321 vsi->irq_handler,
3322 0,
3323 q_vector->name,
3324 q_vector);
3325 if (err) {
3326 dev_info(&pf->pdev->dev,
fb43201f 3327 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3328 goto free_queue_irqs;
3329 }
3330 /* assign the mask for this irq */
3331 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3332 &q_vector->affinity_mask);
3333 }
3334
63741846 3335 vsi->irqs_ready = true;
41c445ff
JB		 3336 return 0;
3337
3338free_queue_irqs:
3339 while (vector) {
3340 vector--;
3341 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3342 NULL);
3343 free_irq(pf->msix_entries[base + vector].vector,
3344 &(vsi->q_vectors[vector]));
3345 }
3346 return err;
3347}
3348
3349/**
3350 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3351 * @vsi: the VSI being un-configured
3352 **/
3353static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3354{
3355 struct i40e_pf *pf = vsi->back;
3356 struct i40e_hw *hw = &pf->hw;
3357 int base = vsi->base_vector;
3358 int i;
3359
3360 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3361 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3362 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3363 }
3364
3365 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3366 for (i = vsi->base_vector;
3367 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3368 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3369
3370 i40e_flush(hw);
3371 for (i = 0; i < vsi->num_q_vectors; i++)
3372 synchronize_irq(pf->msix_entries[i + base].vector);
3373 } else {
3374 /* Legacy and MSI mode - this stops all interrupt handling */
3375 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3376 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3377 i40e_flush(hw);
3378 synchronize_irq(pf->pdev->irq);
3379 }
3380}
3381
3382/**
3383 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3384 * @vsi: the VSI being configured
3385 **/
3386static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3387{
3388 struct i40e_pf *pf = vsi->back;
3389 int i;
3390
3391 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3392 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3393 i40e_irq_dynamic_enable(vsi, i);
3394 } else {
3395 i40e_irq_dynamic_enable_icr0(pf);
3396 }
3397
1022cb6c 3398 i40e_flush(&pf->hw);
41c445ff
JB		 3399 return 0;
3400}
3401
3402/**
3403 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3404 * @pf: board private structure
3405 **/
3406static void i40e_stop_misc_vector(struct i40e_pf *pf)
3407{
3408 /* Disable ICR 0 */
3409 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3410 i40e_flush(&pf->hw);
3411}
3412
3413/**
3414 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3415 * @irq: interrupt number
3416 * @data: pointer to a q_vector
3417 *
3418 * This is the handler used for all MSI/Legacy interrupts, and deals
3419 * with both queue and non-queue interrupts. This is also used in
3420 * MSIX mode to handle the non-queue interrupts.
3421 **/
3422static irqreturn_t i40e_intr(int irq, void *data)
3423{
3424 struct i40e_pf *pf = (struct i40e_pf *)data;
3425 struct i40e_hw *hw = &pf->hw;
5e823066 3426 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3427 u32 icr0, icr0_remaining;
3428 u32 val, ena_mask;
3429
3430 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3431 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3432
116a57d4
SN		 3433 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3434 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3435 goto enable_intr;
41c445ff 3436
cd92e72f
SN		 3437 /* if interrupt but no bits showing, must be SWINT */
3438 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3439 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3440 pf->sw_int_count++;
3441
0d8e1439
ASJ		 3442 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3443 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3444 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3445 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3446 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3447 }
3448
41c445ff
JB		 3449 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3450 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3451 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3452 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3453
3454 /* temporarily disable queue cause for NAPI processing */
3455 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3456
41c445ff
JB		 3457 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3458 wr32(hw, I40E_QINT_RQCTL(0), qval);
3459
3460 qval = rd32(hw, I40E_QINT_TQCTL(0));
3461 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3462 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3463
3464 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3465 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3466 }
3467
3468 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3469 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3470 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3471 }
3472
3473 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3474 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3475 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3476 }
3477
3478 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3479 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3480 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3481 }
3482
3483 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3484 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3485 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3486 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3487 val = rd32(hw, I40E_GLGEN_RSTAT);
3488 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3489 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3490 if (val == I40E_RESET_CORER) {
41c445ff 3491 pf->corer_count++;
4eb3f768 3492 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3493 pf->globr_count++;
4eb3f768 3494 } else if (val == I40E_RESET_EMPR) {
41c445ff 3495 pf->empr_count++;
9df42d1a 3496 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3497 }
41c445ff
JB		 3498 }
3499
9c010ee0
ASJ		 3500 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3501 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3502 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3503 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3504 rd32(hw, I40E_PFHMC_ERRORINFO),
3505 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3506 }
3507
beb0dff1
JK		 3508 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3509 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3510
3511 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3512 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3513 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3514 }
beb0dff1
JK		 3515 }
3516
41c445ff
JB		 3517 /* If a critical error is pending we have no choice but to reset the
3518 * device.
3519 * Report and mask out any remaining unexpected interrupts.
3520 */
3521 icr0_remaining = icr0 & ena_mask;
3522 if (icr0_remaining) {
3523 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3524 icr0_remaining);
9c010ee0 3525 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3526 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3527 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3528 dev_info(&pf->pdev->dev, "device will be reset\n");
3529 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3530 i40e_service_event_schedule(pf);
41c445ff
JB		 3531 }
3532 ena_mask &= ~icr0_remaining;
3533 }
5e823066 3534 ret = IRQ_HANDLED;
41c445ff 3535
5e823066 3536enable_intr:
41c445ff
JB		 3537 /* re-enable interrupt causes */
3538 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3539 if (!test_bit(__I40E_DOWN, &pf->state)) {
3540 i40e_service_event_schedule(pf);
3541 i40e_irq_dynamic_enable_icr0(pf);
3542 }
3543
5e823066 3544 return ret;
41c445ff
JB		 3545}
3546
cbf61325
ASJ		 3547/**
3548 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3549 * @tx_ring: tx ring to clean
3550 * @budget: how many cleans we're allowed
3551 *
3552 * Returns true if there's any budget left (e.g. the clean is finished)
3553 **/
3554static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3555{
3556 struct i40e_vsi *vsi = tx_ring->vsi;
3557 u16 i = tx_ring->next_to_clean;
3558 struct i40e_tx_buffer *tx_buf;
3559 struct i40e_tx_desc *tx_desc;
3560
3561 tx_buf = &tx_ring->tx_bi[i];
3562 tx_desc = I40E_TX_DESC(tx_ring, i);
3563 i -= tx_ring->count;
3564
3565 do {
3566 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3567
3568 /* if next_to_watch is not set then there is no work pending */
3569 if (!eop_desc)
3570 break;
3571
3572 /* prevent any other reads prior to eop_desc */
3573 read_barrier_depends();
3574
3575 /* if the descriptor isn't done, no work yet to do */
3576 if (!(eop_desc->cmd_type_offset_bsz &
3577 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3578 break;
3579
3580 /* clear next_to_watch to prevent false hangs */
3581 tx_buf->next_to_watch = NULL;
3582
49d7d933
ASJ		 3583 tx_desc->buffer_addr = 0;
3584 tx_desc->cmd_type_offset_bsz = 0;
3585 /* move past filter desc */
3586 tx_buf++;
3587 tx_desc++;
3588 i++;
3589 if (unlikely(!i)) {
3590 i -= tx_ring->count;
3591 tx_buf = tx_ring->tx_bi;
3592 tx_desc = I40E_TX_DESC(tx_ring, 0);
3593 }
cbf61325
ASJ		 3594 /* unmap skb header data */
3595 dma_unmap_single(tx_ring->dev,
3596 dma_unmap_addr(tx_buf, dma),
3597 dma_unmap_len(tx_buf, len),
3598 DMA_TO_DEVICE);
49d7d933
ASJ		 3599 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3600 kfree(tx_buf->raw_buf);
cbf61325 3601
49d7d933
ASJ		 3602 tx_buf->raw_buf = NULL;
3603 tx_buf->tx_flags = 0;
3604 tx_buf->next_to_watch = NULL;
cbf61325 3605 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3606 tx_desc->buffer_addr = 0;
3607 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3608
49d7d933 3609 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3610 tx_buf++;
3611 tx_desc++;
3612 i++;
3613 if (unlikely(!i)) {
3614 i -= tx_ring->count;
3615 tx_buf = tx_ring->tx_bi;
3616 tx_desc = I40E_TX_DESC(tx_ring, 0);
3617 }
3618
3619 /* update budget accounting */
3620 budget--;
3621 } while (likely(budget));
3622
3623 i += tx_ring->count;
3624 tx_ring->next_to_clean = i;
3625
6995b36c 3626 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3627 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3628
cbf61325
ASJ		 3629 return budget > 0;
3630}
3631
3632/**
3633 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3634 * @irq: interrupt number
3635 * @data: pointer to a q_vector
3636 **/
3637static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3638{
3639 struct i40e_q_vector *q_vector = data;
3640 struct i40e_vsi *vsi;
3641
3642 if (!q_vector->tx.ring)
3643 return IRQ_HANDLED;
3644
3645 vsi = q_vector->tx.ring->vsi;
3646 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3647
3648 return IRQ_HANDLED;
3649}
3650
41c445ff 3651/**
cd0b6fa6 3652 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3653 * @vsi: the VSI being configured
3654 * @v_idx: vector index
cd0b6fa6 3655 * @qp_idx: queue pair index
41c445ff 3656 **/
26cdc443 3657static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3658{
493fb300 3659 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3660 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3661 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3662
3663 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3664 tx_ring->next = q_vector->tx.ring;
3665 q_vector->tx.ring = tx_ring;
41c445ff 3666 q_vector->tx.count++;
cd0b6fa6
AD		 3667
3668 rx_ring->q_vector = q_vector;
3669 rx_ring->next = q_vector->rx.ring;
3670 q_vector->rx.ring = rx_ring;
3671 q_vector->rx.count++;
41c445ff
JB		 3672}
3673
3674/**
3675 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3676 * @vsi: the VSI being configured
3677 *
3678 * This function maps descriptor rings to the queue-specific vectors
3679 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3680 * one vector per queue pair, but on a constrained vector budget, we
3681 * group the queue pairs as "efficiently" as possible.
3682 **/
3683static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3684{
3685 int qp_remaining = vsi->num_queue_pairs;
3686 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3687 int num_ringpairs;
41c445ff
JB		 3688 int v_start = 0;
3689 int qp_idx = 0;
3690
3691 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3692 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3693 * It is also important to go through all the vectors available to be
3694 * sure that if we don't use all the vectors, that the remaining vectors
3695 * are cleared. This is especially important when decreasing the
3696 * number of queues in use.
41c445ff 3697 */
70114ec4 3698 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3699 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3700
3701 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3702
3703 q_vector->num_ringpairs = num_ringpairs;
3704
3705 q_vector->rx.count = 0;
3706 q_vector->tx.count = 0;
3707 q_vector->rx.ring = NULL;
3708 q_vector->tx.ring = NULL;
3709
3710 while (num_ringpairs--) {
26cdc443 3711 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3712 qp_idx++;
3713 qp_remaining--;
41c445ff
JB		 3714 }
3715 }
3716}
3717
3718/**
3719 * i40e_vsi_request_irq - Request IRQ from the OS
3720 * @vsi: the VSI being configured
3721 * @basename: name for the vector
3722 **/
3723static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3724{
3725 struct i40e_pf *pf = vsi->back;
3726 int err;
3727
3728 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3729 err = i40e_vsi_request_irq_msix(vsi, basename);
3730 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3731 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3732 pf->int_name, pf);
41c445ff
JB		 3733 else
3734 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3735 pf->int_name, pf);
41c445ff
JB		 3736
3737 if (err)
3738 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3739
3740 return err;
3741}
3742
3743#ifdef CONFIG_NET_POLL_CONTROLLER
3744/**
3745 * i40e_netpoll - A Polling 'interrupt'handler
3746 * @netdev: network interface device structure
3747 *
3748 * This is used by netconsole to send skbs without having to re-enable
3749 * interrupts. It's not called while the normal interrupt routine is executing.
3750 **/
38e00438
VD		 3751#ifdef I40E_FCOE
3752void i40e_netpoll(struct net_device *netdev)
3753#else
41c445ff 3754static void i40e_netpoll(struct net_device *netdev)
38e00438 3755#endif
41c445ff
JB		 3756{
3757 struct i40e_netdev_priv *np = netdev_priv(netdev);
3758 struct i40e_vsi *vsi = np->vsi;
3759 struct i40e_pf *pf = vsi->back;
3760 int i;
3761
3762 /* if interface is down do nothing */
3763 if (test_bit(__I40E_DOWN, &vsi->state))
3764 return;
3765
41c445ff
JB		 3766 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3767 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3768 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3769 } else {
3770 i40e_intr(pf->pdev->irq, netdev);
3771 }
41c445ff
JB		 3772}
3773#endif
3774
23527308
NP		 3775/**
3776 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3777 * @pf: the PF being configured
3778 * @pf_q: the PF queue
3779 * @enable: enable or disable state of the queue
3780 *
3781 * This routine will wait for the given Tx queue of the PF to reach the
3782 * enabled or disabled state.
3783 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3784 * multiple retries; else will return 0 in case of success.
3785 **/
3786static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3787{
3788 int i;
3789 u32 tx_reg;
3790
3791 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3792 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3793 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3794 break;
3795
f98a2006 3796 usleep_range(10, 20);
23527308
NP		 3797 }
3798 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3799 return -ETIMEDOUT;
3800
3801 return 0;
3802}
3803
41c445ff
JB		 3804/**
3805 * i40e_vsi_control_tx - Start or stop a VSI's rings
3806 * @vsi: the VSI being configured
3807 * @enable: start or stop the rings
3808 **/
3809static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3810{
3811 struct i40e_pf *pf = vsi->back;
3812 struct i40e_hw *hw = &pf->hw;
23527308 3813 int i, j, pf_q, ret = 0;
41c445ff
JB		 3814 u32 tx_reg;
3815
3816 pf_q = vsi->base_queue;
3817 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3818
3819 /* warn the TX unit of coming changes */
3820 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3821 if (!enable)
f98a2006 3822 usleep_range(10, 20);
351499ab 3823
6c5ef620 3824 for (j = 0; j < 50; j++) {
41c445ff 3825 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3826 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3827 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3828 break;
3829 usleep_range(1000, 2000);
3830 }
fda972f6 3831 /* Skip if the queue is already in the requested state */
7c122007 3832 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3833 continue;
41c445ff
JB		 3834
3835 /* turn on/off the queue */
c5c9eb9e
SN		 3836 if (enable) {
3837 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3838 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3839 } else {
41c445ff 3840 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3841 }
41c445ff
JB		 3842
3843 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3844 /* No waiting for the Tx queue to disable */
3845 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3846 continue;
41c445ff
JB		 3847
3848 /* wait for the change to finish */
23527308
NP		 3849 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3850 if (ret) {
3851 dev_info(&pf->pdev->dev,
fb43201f
SN		 3852 "VSI seid %d Tx ring %d %sable timeout\n",
3853 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3854 break;
41c445ff
JB		 3855 }
3856 }
3857
7134f9ce
JB		 3858 if (hw->revision_id == 0)
3859 mdelay(50);
23527308
NP		 3860 return ret;
3861}
3862
3863/**
3864 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3865 * @pf: the PF being configured
3866 * @pf_q: the PF queue
3867 * @enable: enable or disable state of the queue
3868 *
3869 * This routine will wait for the given Rx queue of the PF to reach the
3870 * enabled or disabled state.
3871 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3872 * multiple retries; else will return 0 in case of success.
3873 **/
3874static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3875{
3876 int i;
3877 u32 rx_reg;
3878
3879 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3880 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3881 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3882 break;
3883
f98a2006 3884 usleep_range(10, 20);
23527308
NP		 3885 }
3886 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3887 return -ETIMEDOUT;
7134f9ce 3888
41c445ff
JB		 3889 return 0;
3890}
3891
3892/**
3893 * i40e_vsi_control_rx - Start or stop a VSI's rings
3894 * @vsi: the VSI being configured
3895 * @enable: start or stop the rings
3896 **/
3897static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3898{
3899 struct i40e_pf *pf = vsi->back;
3900 struct i40e_hw *hw = &pf->hw;
23527308 3901 int i, j, pf_q, ret = 0;
41c445ff
JB		 3902 u32 rx_reg;
3903
3904 pf_q = vsi->base_queue;
3905 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3906 for (j = 0; j < 50; j++) {
41c445ff 3907 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3908 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3909 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3910 break;
3911 usleep_range(1000, 2000);
3912 }
41c445ff 3913
7c122007
CS		 3914 /* Skip if the queue is already in the requested state */
3915 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3916 continue;
41c445ff
JB		 3917
3918 /* turn on/off the queue */
3919 if (enable)
6c5ef620 3920 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3921 else
6c5ef620 3922 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3923 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3924
3925 /* wait for the change to finish */
23527308
NP		 3926 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3927 if (ret) {
3928 dev_info(&pf->pdev->dev,
fb43201f
SN		 3929 "VSI seid %d Rx ring %d %sable timeout\n",
3930 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3931 break;
41c445ff
JB		 3932 }
3933 }
3934
23527308 3935 return ret;
41c445ff
JB		 3936}
3937
3938/**
3939 * i40e_vsi_control_rings - Start or stop a VSI's rings
3940 * @vsi: the VSI being configured
3941 * @enable: start or stop the rings
3942 **/
fc18eaa0 3943int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3944{
3b867b28 3945 int ret = 0;
41c445ff
JB		 3946
3947 /* do rx first for enable and last for disable */
3948 if (request) {
3949 ret = i40e_vsi_control_rx(vsi, request);
3950 if (ret)
3951 return ret;
3952 ret = i40e_vsi_control_tx(vsi, request);
3953 } else {
3b867b28
ASJ		 3954 /* Ignore return value, we need to shutdown whatever we can */
3955 i40e_vsi_control_tx(vsi, request);
3956 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3957 }
3958
3959 return ret;
3960}
3961
3962/**
3963 * i40e_vsi_free_irq - Free the irq association with the OS
3964 * @vsi: the VSI being configured
3965 **/
3966static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3967{
3968 struct i40e_pf *pf = vsi->back;
3969 struct i40e_hw *hw = &pf->hw;
3970 int base = vsi->base_vector;
3971 u32 val, qp;
3972 int i;
3973
3974 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3975 if (!vsi->q_vectors)
3976 return;
3977
63741846
SN		 3978 if (!vsi->irqs_ready)
3979 return;
3980
3981 vsi->irqs_ready = false;
41c445ff
JB		 3982 for (i = 0; i < vsi->num_q_vectors; i++) {
3983 u16 vector = i + base;
3984
3985 /* free only the irqs that were actually requested */
78681b1f
SN		 3986 if (!vsi->q_vectors[i] ||
3987 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3988 continue;
3989
3990 /* clear the affinity_mask in the IRQ descriptor */
3991 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3992 NULL);
3993 free_irq(pf->msix_entries[vector].vector,
493fb300 3994 vsi->q_vectors[i]);
41c445ff
JB		 3995
3996 /* Tear down the interrupt queue link list
3997 *
3998 * We know that they come in pairs and always
3999 * the Rx first, then the Tx. To clear the
4000 * link list, stick the EOL value into the
4001 * next_q field of the registers.
4002 */
4003 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
4004 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4005 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4006 val |= I40E_QUEUE_END_OF_LIST
4007 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4008 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4009
4010 while (qp != I40E_QUEUE_END_OF_LIST) {
4011 u32 next;
4012
4013 val = rd32(hw, I40E_QINT_RQCTL(qp));
4014
4015 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4016 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4017 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4018 I40E_QINT_RQCTL_INTEVENT_MASK);
4019
4020 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4021 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4022
4023 wr32(hw, I40E_QINT_RQCTL(qp), val);
4024
4025 val = rd32(hw, I40E_QINT_TQCTL(qp));
4026
4027 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4028 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4029
4030 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4031 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4032 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4033 I40E_QINT_TQCTL_INTEVENT_MASK);
4034
4035 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4036 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4037
4038 wr32(hw, I40E_QINT_TQCTL(qp), val);
4039 qp = next;
4040 }
4041 }
4042 } else {
4043 free_irq(pf->pdev->irq, pf);
4044
4045 val = rd32(hw, I40E_PFINT_LNKLST0);
4046 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4047 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4048 val |= I40E_QUEUE_END_OF_LIST
4049 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4050 wr32(hw, I40E_PFINT_LNKLST0, val);
4051
4052 val = rd32(hw, I40E_QINT_RQCTL(qp));
4053 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4054 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4055 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4056 I40E_QINT_RQCTL_INTEVENT_MASK);
4057
4058 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4059 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4060
4061 wr32(hw, I40E_QINT_RQCTL(qp), val);
4062
4063 val = rd32(hw, I40E_QINT_TQCTL(qp));
4064
4065 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4066 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4067 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4068 I40E_QINT_TQCTL_INTEVENT_MASK);
4069
4070 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4071 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4072
4073 wr32(hw, I40E_QINT_TQCTL(qp), val);
4074 }
4075}
4076
493fb300
AD		 4077/**
4078 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4079 * @vsi: the VSI being configured
4080 * @v_idx: Index of vector to be freed
4081 *
4082 * This function frees the memory allocated to the q_vector. In addition if
4083 * NAPI is enabled it will delete any references to the NAPI struct prior
4084 * to freeing the q_vector.
4085 **/
4086static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4087{
4088 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4089 struct i40e_ring *ring;
493fb300
AD		 4090
4091 if (!q_vector)
4092 return;
4093
4094 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4095 i40e_for_each_ring(ring, q_vector->tx)
4096 ring->q_vector = NULL;
4097
4098 i40e_for_each_ring(ring, q_vector->rx)
4099 ring->q_vector = NULL;
493fb300
AD		 4100
4101 /* only VSI w/ an associated netdev is set up w/ NAPI */
4102 if (vsi->netdev)
4103 netif_napi_del(&q_vector->napi);
4104
4105 vsi->q_vectors[v_idx] = NULL;
4106
4107 kfree_rcu(q_vector, rcu);
4108}
4109
41c445ff
JB		 4110/**
4111 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4112 * @vsi: the VSI being un-configured
4113 *
4114 * This frees the memory allocated to the q_vectors and
4115 * deletes references to the NAPI struct.
4116 **/
4117static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4118{
4119 int v_idx;
4120
493fb300
AD		 4121 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4122 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4123}
4124
4125/**
4126 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4127 * @pf: board private structure
4128 **/
4129static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4130{
4131 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4132 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4133 pci_disable_msix(pf->pdev);
4134 kfree(pf->msix_entries);
4135 pf->msix_entries = NULL;
3b444399
SN		 4136 kfree(pf->irq_pile);
4137 pf->irq_pile = NULL;
41c445ff
JB		 4138 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4139 pci_disable_msi(pf->pdev);
4140 }
4141 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4142}
4143
4144/**
4145 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4146 * @pf: board private structure
4147 *
4148 * We go through and clear interrupt specific resources and reset the structure
4149 * to pre-load conditions
4150 **/
4151static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4152{
4153 int i;
4154
e147758d
SN		 4155 i40e_stop_misc_vector(pf);
4156 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4157 synchronize_irq(pf->msix_entries[0].vector);
4158 free_irq(pf->msix_entries[0].vector, pf);
4159 }
4160
41c445ff 4161 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4162 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4163 if (pf->vsi[i])
4164 i40e_vsi_free_q_vectors(pf->vsi[i]);
4165 i40e_reset_interrupt_capability(pf);
4166}
4167
4168/**
4169 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4170 * @vsi: the VSI being configured
4171 **/
4172static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4173{
4174 int q_idx;
4175
4176 if (!vsi->netdev)
4177 return;
4178
4179 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4180 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4181}
4182
4183/**
4184 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4185 * @vsi: the VSI being configured
4186 **/
4187static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4188{
4189 int q_idx;
4190
4191 if (!vsi->netdev)
4192 return;
4193
4194 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4195 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4196}
4197
90ef8d47
SN		 4198/**
4199 * i40e_vsi_close - Shut down a VSI
4200 * @vsi: the vsi to be quelled
4201 **/
4202static void i40e_vsi_close(struct i40e_vsi *vsi)
4203{
4204 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4205 i40e_down(vsi);
4206 i40e_vsi_free_irq(vsi);
4207 i40e_vsi_free_tx_resources(vsi);
4208 i40e_vsi_free_rx_resources(vsi);
92faef85 4209 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4210}
4211
41c445ff
JB		 4212/**
4213 * i40e_quiesce_vsi - Pause a given VSI
4214 * @vsi: the VSI being paused
4215 **/
4216static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4217{
4218 if (test_bit(__I40E_DOWN, &vsi->state))
4219 return;
4220
d341b7a5
NP		 4221 /* No need to disable FCoE VSI when Tx suspended */
4222 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4223 vsi->type == I40E_VSI_FCOE) {
4224 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4225 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4226 return;
4227 }
4228
41c445ff 4229 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4230 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4231 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4232 else
90ef8d47 4233 i40e_vsi_close(vsi);
41c445ff
JB		 4234}
4235
4236/**
4237 * i40e_unquiesce_vsi - Resume a given VSI
4238 * @vsi: the VSI being resumed
4239 **/
4240static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4241{
4242 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4243 return;
4244
4245 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4246 if (vsi->netdev && netif_running(vsi->netdev))
4247 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4248 else
8276f757 4249 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4250}
4251
4252/**
4253 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4254 * @pf: the PF
4255 **/
4256static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4257{
4258 int v;
4259
505682cd 4260 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4261 if (pf->vsi[v])
4262 i40e_quiesce_vsi(pf->vsi[v]);
4263 }
4264}
4265
4266/**
4267 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4268 * @pf: the PF
4269 **/
4270static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4271{
4272 int v;
4273
505682cd 4274 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4275 if (pf->vsi[v])
4276 i40e_unquiesce_vsi(pf->vsi[v]);
4277 }
4278}
4279
69129dc3
NP		 4280#ifdef CONFIG_I40E_DCB
4281/**
4282 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4283 * @vsi: the VSI being configured
4284 *
4285 * This function waits for the given VSI's Tx queues to be disabled.
4286 **/
4287static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4288{
4289 struct i40e_pf *pf = vsi->back;
4290 int i, pf_q, ret;
4291
4292 pf_q = vsi->base_queue;
4293 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4294 /* Check and wait for the disable status of the queue */
4295 ret = i40e_pf_txq_wait(pf, pf_q, false);
4296 if (ret) {
4297 dev_info(&pf->pdev->dev,
fb43201f
SN		 4298 "VSI seid %d Tx ring %d disable timeout\n",
4299 vsi->seid, pf_q);
69129dc3
NP		 4300 return ret;
4301 }
4302 }
4303
4304 return 0;
4305}
4306
4307/**
4308 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4309 * @pf: the PF
4310 *
4311 * This function waits for the Tx queues to be in disabled state for all the
4312 * VSIs that are managed by this PF.
4313 **/
4314static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4315{
4316 int v, ret = 0;
4317
4318 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4319 /* No need to wait for FCoE VSI queues */
4320 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4321 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4322 if (ret)
4323 break;
4324 }
4325 }
4326
4327 return ret;
4328}
4329
4330#endif
b03a8c1f
KP		 4331
4332/**
4333 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4334 * @q_idx: TX queue number
4335 * @vsi: Pointer to VSI struct
4336 *
4337 * This function checks specified queue for given VSI. Detects hung condition.
4338 * Sets hung bit since it is two step process. Before next run of service task
4339 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4340 * hung condition remain unchanged and during subsequent run, this function
4341 * issues SW interrupt to recover from hung condition.
4342 **/
4343static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4344{
4345 struct i40e_ring *tx_ring = NULL;
4346 struct i40e_pf *pf;
4347 u32 head, val, tx_pending;
4348 int i;
4349
4350 pf = vsi->back;
4351
4352 /* now that we have an index, find the tx_ring struct */
4353 for (i = 0; i < vsi->num_queue_pairs; i++) {
4354 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4355 if (q_idx == vsi->tx_rings[i]->queue_index) {
4356 tx_ring = vsi->tx_rings[i];
4357 break;
4358 }
4359 }
4360 }
4361
4362 if (!tx_ring)
4363 return;
4364
4365 /* Read interrupt register */
4366 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4367 val = rd32(&pf->hw,
4368 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4369 tx_ring->vsi->base_vector - 1));
4370 else
4371 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4372
9c6c1259
KP		 4373 /* Bail out if interrupts are disabled because napi_poll
4374 * execution in-progress or will get scheduled soon.
4375 * napi_poll cleans TX and RX queues and updates 'next_to_clean'.
4376 */
4377 if (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))
4378 return;
4379
b03a8c1f
KP		 4380 head = i40e_get_head(tx_ring);
4381
4382 tx_pending = i40e_get_tx_pending(tx_ring);
4383
9c6c1259
KP		 4384 /* HW is done executing descriptors, updated HEAD write back,
4385 * but SW hasn't processed those descriptors. If interrupt is
4386 * not generated from this point ON, it could result into
4387 * dev_watchdog detecting timeout on those netdev_queue,
4388 * hence proactively trigger SW interrupt.
b03a8c1f 4389 */
9c6c1259
KP		 4390 if (tx_pending) {
4391 /* NAPI Poll didn't run and clear since it was set */
4392 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4393 &tx_ring->q_vector->hung_detected)) {
4394 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4395 vsi->seid, q_idx, tx_pending,
4396 tx_ring->next_to_clean, head,
4397 tx_ring->next_to_use,
4398 readl(tx_ring->tail));
4399 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4400 vsi->seid, q_idx, val);
4401 i40e_force_wb(vsi, tx_ring->q_vector);
4402 } else {
4403 /* First Chance - detected possible hung */
4404 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4405 &tx_ring->q_vector->hung_detected);
4406 }
4407 }
b03a8c1f
KP		 4408}
4409
4410/**
4411 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4412 * @pf: pointer to PF struct
4413 *
4414 * LAN VSI has netdev and netdev has TX queues. This function is to check
4415 * each of those TX queues if they are hung, trigger recovery by issuing
4416 * SW interrupt.
4417 **/
4418static void i40e_detect_recover_hung(struct i40e_pf *pf)
4419{
4420 struct net_device *netdev;
4421 struct i40e_vsi *vsi;
4422 int i;
4423
4424 /* Only for LAN VSI */
4425 vsi = pf->vsi[pf->lan_vsi];
4426
4427 if (!vsi)
4428 return;
4429
4430 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4431 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4432 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4433 return;
4434
4435 /* Make sure type is MAIN VSI */
4436 if (vsi->type != I40E_VSI_MAIN)
4437 return;
4438
4439 netdev = vsi->netdev;
4440 if (!netdev)
4441 return;
4442
4443 /* Bail out if netif_carrier is not OK */
4444 if (!netif_carrier_ok(netdev))
4445 return;
4446
4447 /* Go thru' TX queues for netdev */
4448 for (i = 0; i < netdev->num_tx_queues; i++) {
4449 struct netdev_queue *q;
4450
4451 q = netdev_get_tx_queue(netdev, i);
4452 if (q)
4453 i40e_detect_recover_hung_queue(i, vsi);
4454 }
4455}
4456
63d7e5a4
NP		 4457/**
4458 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4459 * @pf: pointer to PF
63d7e5a4
NP		 4460 *
4461 * Get TC map for ISCSI PF type that will include iSCSI TC
4462 * and LAN TC.
4463 **/
4464static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4465{
4466 struct i40e_dcb_app_priority_table app;
4467 struct i40e_hw *hw = &pf->hw;
4468 u8 enabled_tc = 1; /* TC0 is always enabled */
4469 u8 tc, i;
4470 /* Get the iSCSI APP TLV */
4471 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4472
4473 for (i = 0; i < dcbcfg->numapps; i++) {
4474 app = dcbcfg->app[i];
4475 if (app.selector == I40E_APP_SEL_TCPIP &&
4476 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4477 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4478 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4479 break;
4480 }
4481 }
4482
4483 return enabled_tc;
4484}
4485
41c445ff
JB		 4486/**
4487 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4488 * @dcbcfg: the corresponding DCBx configuration structure
4489 *
4490 * Return the number of TCs from given DCBx configuration
4491 **/
4492static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4493{
078b5876
JB		 4494 u8 num_tc = 0;
4495 int i;
41c445ff
JB		 4496
4497 /* Scan the ETS Config Priority Table to find
4498 * traffic class enabled for a given priority
4499 * and use the traffic class index to get the
4500 * number of traffic classes enabled
4501 */
4502 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4503 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4504 num_tc = dcbcfg->etscfg.prioritytable[i];
4505 }
4506
4507 /* Traffic class index starts from zero so
4508 * increment to return the actual count
4509 */
078b5876 4510 return num_tc + 1;
41c445ff
JB		 4511}
4512
4513/**
4514 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4515 * @dcbcfg: the corresponding DCBx configuration structure
4516 *
4517 * Query the current DCB configuration and return the number of
4518 * traffic classes enabled from the given DCBX config
4519 **/
4520static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4521{
4522 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4523 u8 enabled_tc = 1;
4524 u8 i;
4525
4526 for (i = 0; i < num_tc; i++)
41a1d04b 4527 enabled_tc |= BIT(i);
41c445ff
JB		 4528
4529 return enabled_tc;
4530}
4531
4532/**
4533 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4534 * @pf: PF being queried
4535 *
4536 * Return number of traffic classes enabled for the given PF
4537 **/
4538static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4539{
4540 struct i40e_hw *hw = &pf->hw;
4541 u8 i, enabled_tc;
4542 u8 num_tc = 0;
4543 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4544
4545 /* If DCB is not enabled then always in single TC */
4546 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4547 return 1;
4548
63d7e5a4
NP		 4549 /* SFP mode will be enabled for all TCs on port */
4550 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4551 return i40e_dcb_get_num_tc(dcbcfg);
4552
41c445ff 4553 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4554 if (pf->hw.func_caps.iscsi)
4555 enabled_tc = i40e_get_iscsi_tc_map(pf);
4556 else
fc51de96 4557 return 1; /* Only TC0 */
41c445ff 4558
63d7e5a4
NP		 4559 /* At least have TC0 */
4560 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4561 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4562 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4563 num_tc++;
4564 }
4565 return num_tc;
41c445ff
JB		 4566}
4567
4568/**
4569 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4570 * @pf: PF being queried
4571 *
4572 * Return a bitmap for first enabled traffic class for this PF.
4573 **/
4574static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4575{
4576 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4577 u8 i = 0;
4578
4579 if (!enabled_tc)
4580 return 0x1; /* TC0 */
4581
4582 /* Find the first enabled TC */
4583 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4584 if (enabled_tc & BIT(i))
41c445ff
JB		 4585 break;
4586 }
4587
41a1d04b 4588 return BIT(i);
41c445ff
JB		 4589}
4590
4591/**
4592 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4593 * @pf: PF being queried
4594 *
4595 * Return a bitmap for enabled traffic classes for this PF.
4596 **/
4597static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4598{
4599 /* If DCB is not enabled for this PF then just return default TC */
4600 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4601 return i40e_pf_get_default_tc(pf);
4602
41c445ff 4603 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4604 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4605 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4606
fc51de96 4607 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4608 if (pf->hw.func_caps.iscsi)
4609 return i40e_get_iscsi_tc_map(pf);
4610 else
fc51de96 4611 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4612}
4613
4614/**
4615 * i40e_vsi_get_bw_info - Query VSI BW Information
4616 * @vsi: the VSI being queried
4617 *
4618 * Returns 0 on success, negative value on failure
4619 **/
4620static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4621{
4622 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4623 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4624 struct i40e_pf *pf = vsi->back;
4625 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4626 i40e_status ret;
41c445ff 4627 u32 tc_bw_max;
41c445ff
JB		 4628 int i;
4629
4630 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4631 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4632 if (ret) {
41c445ff 4633 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4634 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4635 i40e_stat_str(&pf->hw, ret),
4636 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4637 return -EINVAL;
41c445ff
JB		 4638 }
4639
4640 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4641 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4642 NULL);
4643 if (ret) {
41c445ff 4644 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4645 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4646 i40e_stat_str(&pf->hw, ret),
4647 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4648 return -EINVAL;
41c445ff
JB		 4649 }
4650
4651 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4652 dev_info(&pf->pdev->dev,
4653 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4654 bw_config.tc_valid_bits,
4655 bw_ets_config.tc_valid_bits);
4656 /* Still continuing */
4657 }
4658
4659 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4660 vsi->bw_max_quanta = bw_config.max_bw;
4661 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4662 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4663 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4664 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4665 vsi->bw_ets_limit_credits[i] =
4666 le16_to_cpu(bw_ets_config.credits[i]);
4667 /* 3 bits out of 4 for each TC */
4668 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4669 }
078b5876 4670
dcae29be 4671 return 0;
41c445ff
JB		 4672}
4673
4674/**
4675 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4676 * @vsi: the VSI being configured
4677 * @enabled_tc: TC bitmap
4678 * @bw_credits: BW shared credits per TC
4679 *
4680 * Returns 0 on success, negative value on failure
4681 **/
dcae29be 4682static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4683 u8 *bw_share)
4684{
4685 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4686 i40e_status ret;
dcae29be 4687 int i;
41c445ff
JB		 4688
4689 bw_data.tc_valid_bits = enabled_tc;
4690 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4691 bw_data.tc_bw_credits[i] = bw_share[i];
4692
f1c7e72e
SN		 4693 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4694 NULL);
4695 if (ret) {
41c445ff 4696 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4697 "AQ command Config VSI BW allocation per TC failed = %d\n",
4698 vsi->back->hw.aq.asq_last_status);
dcae29be 4699 return -EINVAL;
41c445ff
JB		 4700 }
4701
4702 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4703 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4704
dcae29be 4705 return 0;
41c445ff
JB		 4706}
4707
4708/**
4709 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4710 * @vsi: the VSI being configured
4711 * @enabled_tc: TC map to be enabled
4712 *
4713 **/
4714static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4715{
4716 struct net_device *netdev = vsi->netdev;
4717 struct i40e_pf *pf = vsi->back;
4718 struct i40e_hw *hw = &pf->hw;
4719 u8 netdev_tc = 0;
4720 int i;
4721 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4722
4723 if (!netdev)
4724 return;
4725
4726 if (!enabled_tc) {
4727 netdev_reset_tc(netdev);
4728 return;
4729 }
4730
4731 /* Set up actual enabled TCs on the VSI */
4732 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4733 return;
4734
4735 /* set per TC queues for the VSI */
4736 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4737 /* Only set TC queues for enabled tcs
4738 *
4739 * e.g. For a VSI that has TC0 and TC3 enabled the
4740 * enabled_tc bitmap would be 0x00001001; the driver
4741 * will set the numtc for netdev as 2 that will be
4742 * referenced by the netdev layer as TC 0 and 1.
4743 */
75f5cea9 4744 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4745 netdev_set_tc_queue(netdev,
4746 vsi->tc_config.tc_info[i].netdev_tc,
4747 vsi->tc_config.tc_info[i].qcount,
4748 vsi->tc_config.tc_info[i].qoffset);
4749 }
4750
4751 /* Assign UP2TC map for the VSI */
4752 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4753 /* Get the actual TC# for the UP */
4754 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4755 /* Get the mapped netdev TC# for the UP */
4756 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4757 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4758 }
4759}
4760
4761/**
4762 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4763 * @vsi: the VSI being configured
4764 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4765 **/
4766static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4767 struct i40e_vsi_context *ctxt)
4768{
4769 /* copy just the sections touched not the entire info
4770 * since not all sections are valid as returned by
4771 * update vsi params
4772 */
4773 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4774 memcpy(&vsi->info.queue_mapping,
4775 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4776 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4777 sizeof(vsi->info.tc_mapping));
4778}
4779
4780/**
4781 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4782 * @vsi: VSI to be configured
4783 * @enabled_tc: TC bitmap
4784 *
4785 * This configures a particular VSI for TCs that are mapped to the
4786 * given TC bitmap. It uses default bandwidth share for TCs across
4787 * VSIs to configure TC for a particular VSI.
4788 *
4789 * NOTE:
4790 * It is expected that the VSI queues have been quisced before calling
4791 * this function.
4792 **/
4793static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4794{
4795 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4796 struct i40e_vsi_context ctxt;
4797 int ret = 0;
4798 int i;
4799
4800 /* Check if enabled_tc is same as existing or new TCs */
4801 if (vsi->tc_config.enabled_tc == enabled_tc)
4802 return ret;
4803
4804 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4805 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4806 if (enabled_tc & BIT(i))
41c445ff
JB		 4807 bw_share[i] = 1;
4808 }
4809
4810 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4811 if (ret) {
4812 dev_info(&vsi->back->pdev->dev,
4813 "Failed configuring TC map %d for VSI %d\n",
4814 enabled_tc, vsi->seid);
4815 goto out;
4816 }
4817
4818 /* Update Queue Pairs Mapping for currently enabled UPs */
4819 ctxt.seid = vsi->seid;
4820 ctxt.pf_num = vsi->back->hw.pf_id;
4821 ctxt.vf_num = 0;
4822 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4823 ctxt.info = vsi->info;
41c445ff
JB		 4824 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4825
4826 /* Update the VSI after updating the VSI queue-mapping information */
4827 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4828 if (ret) {
4829 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4830 "Update vsi tc config failed, err %s aq_err %s\n",
4831 i40e_stat_str(&vsi->back->hw, ret),
4832 i40e_aq_str(&vsi->back->hw,
4833 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4834 goto out;
4835 }
4836 /* update the local VSI info with updated queue map */
4837 i40e_vsi_update_queue_map(vsi, &ctxt);
4838 vsi->info.valid_sections = 0;
4839
4840 /* Update current VSI BW information */
4841 ret = i40e_vsi_get_bw_info(vsi);
4842 if (ret) {
4843 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4844 "Failed updating vsi bw info, err %s aq_err %s\n",
4845 i40e_stat_str(&vsi->back->hw, ret),
4846 i40e_aq_str(&vsi->back->hw,
4847 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4848 goto out;
4849 }
4850
4851 /* Update the netdev TC setup */
4852 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4853out:
4854 return ret;
4855}
4856
4e3b35b0
NP		 4857/**
4858 * i40e_veb_config_tc - Configure TCs for given VEB
4859 * @veb: given VEB
4860 * @enabled_tc: TC bitmap
4861 *
4862 * Configures given TC bitmap for VEB (switching) element
4863 **/
4864int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4865{
4866 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4867 struct i40e_pf *pf = veb->pf;
4868 int ret = 0;
4869 int i;
4870
4871 /* No TCs or already enabled TCs just return */
4872 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4873 return ret;
4874
4875 bw_data.tc_valid_bits = enabled_tc;
4876 /* bw_data.absolute_credits is not set (relative) */
4877
4878 /* Enable ETS TCs with equal BW Share for now */
4879 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4880 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4881 bw_data.tc_bw_share_credits[i] = 1;
4882 }
4883
4884 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4885 &bw_data, NULL);
4886 if (ret) {
4887 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4888 "VEB bw config failed, err %s aq_err %s\n",
4889 i40e_stat_str(&pf->hw, ret),
4890 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4891 goto out;
4892 }
4893
4894 /* Update the BW information */
4895 ret = i40e_veb_get_bw_info(veb);
4896 if (ret) {
4897 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4898 "Failed getting veb bw config, err %s aq_err %s\n",
4899 i40e_stat_str(&pf->hw, ret),
4900 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4901 }
4902
4903out:
4904 return ret;
4905}
4906
4907#ifdef CONFIG_I40E_DCB
4908/**
4909 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4910 * @pf: PF struct
4911 *
4912 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4913 * the caller would've quiesce all the VSIs before calling
4914 * this function
4915 **/
4916static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4917{
4918 u8 tc_map = 0;
4919 int ret;
4920 u8 v;
4921
4922 /* Enable the TCs available on PF to all VEBs */
4923 tc_map = i40e_pf_get_tc_map(pf);
4924 for (v = 0; v < I40E_MAX_VEB; v++) {
4925 if (!pf->veb[v])
4926 continue;
4927 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4928 if (ret) {
4929 dev_info(&pf->pdev->dev,
4930 "Failed configuring TC for VEB seid=%d\n",
4931 pf->veb[v]->seid);
4932 /* Will try to configure as many components */
4933 }
4934 }
4935
4936 /* Update each VSI */
505682cd 4937 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4938 if (!pf->vsi[v])
4939 continue;
4940
4941 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4942#ifdef I40E_FCOE
4943 * - For FCoE VSI only enable the TC configured
4944 * as per the APP TLV
4945#endif
4e3b35b0
NP		 4946 * - For all others keep them at TC0 for now
4947 */
4948 if (v == pf->lan_vsi)
4949 tc_map = i40e_pf_get_tc_map(pf);
4950 else
4951 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4952#ifdef I40E_FCOE
4953 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4954 tc_map = i40e_get_fcoe_tc_map(pf);
4955#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4956
4957 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4958 if (ret) {
4959 dev_info(&pf->pdev->dev,
4960 "Failed configuring TC for VSI seid=%d\n",
4961 pf->vsi[v]->seid);
4962 /* Will try to configure as many components */
4963 } else {
0672a091
NP		 4964 /* Re-configure VSI vectors based on updated TC map */
4965 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4966 if (pf->vsi[v]->netdev)
4967 i40e_dcbnl_set_all(pf->vsi[v]);
4968 }
4969 }
4970}
4971
2fd75f31
NP		 4972/**
4973 * i40e_resume_port_tx - Resume port Tx
4974 * @pf: PF struct
4975 *
4976 * Resume a port's Tx and issue a PF reset in case of failure to
4977 * resume.
4978 **/
4979static int i40e_resume_port_tx(struct i40e_pf *pf)
4980{
4981 struct i40e_hw *hw = &pf->hw;
4982 int ret;
4983
4984 ret = i40e_aq_resume_port_tx(hw, NULL);
4985 if (ret) {
4986 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4987 "Resume Port Tx failed, err %s aq_err %s\n",
4988 i40e_stat_str(&pf->hw, ret),
4989 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4990 /* Schedule PF reset to recover */
4991 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4992 i40e_service_event_schedule(pf);
4993 }
4994
4995 return ret;
4996}
4997
4e3b35b0
NP		 4998/**
4999 * i40e_init_pf_dcb - Initialize DCB configuration
5000 * @pf: PF being configured
5001 *
5002 * Query the current DCB configuration and cache it
5003 * in the hardware structure
5004 **/
5005static int i40e_init_pf_dcb(struct i40e_pf *pf)
5006{
5007 struct i40e_hw *hw = &pf->hw;
5008 int err = 0;
5009
025b4a54
ASJ		 5010 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
5011 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
5012 (pf->hw.aq.fw_maj_ver < 4))
5013 goto out;
5014
4e3b35b0
NP		 5015 /* Get the initial DCB configuration */
5016 err = i40e_init_dcb(hw);
5017 if (!err) {
5018 /* Device/Function is not DCBX capable */
5019 if ((!hw->func_caps.dcb) ||
5020 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5021 dev_info(&pf->pdev->dev,
5022 "DCBX offload is not supported or is disabled for this PF.\n");
5023
5024 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5025 goto out;
5026
5027 } else {
5028 /* When status is not DISABLED then DCBX in FW */
5029 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5030 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5031
5032 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5033 /* Enable DCB tagging only when more than one TC */
5034 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5035 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5036 dev_dbg(&pf->pdev->dev,
5037 "DCBX offload is supported for this PF.\n");
4e3b35b0 5038 }
014269ff 5039 } else {
aebfc816 5040 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5041 "Query for DCB configuration failed, err %s aq_err %s\n",
5042 i40e_stat_str(&pf->hw, err),
5043 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5044 }
5045
5046out:
5047 return err;
5048}
5049#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5050#define SPEED_SIZE 14
5051#define FC_SIZE 8
5052/**
5053 * i40e_print_link_message - print link up or down
5054 * @vsi: the VSI for which link needs a message
5055 */
c156f856 5056void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5057{
a9165490
SN		 5058 char *speed = "Unknown";
5059 char *fc = "Unknown";
cf05ed08 5060
c156f856
MJ		 5061 if (vsi->current_isup == isup)
5062 return;
5063 vsi->current_isup = isup;
cf05ed08
JB		 5064 if (!isup) {
5065 netdev_info(vsi->netdev, "NIC Link is Down\n");
5066 return;
5067 }
5068
148c2d80
GR		 5069 /* Warn user if link speed on NPAR enabled partition is not at
5070 * least 10GB
5071 */
5072 if (vsi->back->hw.func_caps.npar_enable &&
5073 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5074 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5075 netdev_warn(vsi->netdev,
5076 "The partition detected link speed that is less than 10Gbps\n");
5077
cf05ed08
JB		 5078 switch (vsi->back->hw.phy.link_info.link_speed) {
5079 case I40E_LINK_SPEED_40GB:
a9165490 5080 speed = "40 G";
cf05ed08 5081 break;
ae24b409 5082 case I40E_LINK_SPEED_20GB:
a9165490 5083 speed = "20 G";
ae24b409 5084 break;
cf05ed08 5085 case I40E_LINK_SPEED_10GB:
a9165490 5086 speed = "10 G";
cf05ed08
JB		 5087 break;
5088 case I40E_LINK_SPEED_1GB:
a9165490 5089 speed = "1000 M";
cf05ed08 5090 break;
5960d33f 5091 case I40E_LINK_SPEED_100MB:
a9165490 5092 speed = "100 M";
5960d33f 5093 break;
cf05ed08
JB		 5094 default:
5095 break;
5096 }
5097
5098 switch (vsi->back->hw.fc.current_mode) {
5099 case I40E_FC_FULL:
a9165490 5100 fc = "RX/TX";
cf05ed08
JB		 5101 break;
5102 case I40E_FC_TX_PAUSE:
a9165490 5103 fc = "TX";
cf05ed08
JB		 5104 break;
5105 case I40E_FC_RX_PAUSE:
a9165490 5106 fc = "RX";
cf05ed08
JB		 5107 break;
5108 default:
a9165490 5109 fc = "None";
cf05ed08
JB		 5110 break;
5111 }
5112
a9165490 5113 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5114 speed, fc);
5115}
4e3b35b0 5116
41c445ff
JB		 5117/**
5118 * i40e_up_complete - Finish the last steps of bringing up a connection
5119 * @vsi: the VSI being configured
5120 **/
5121static int i40e_up_complete(struct i40e_vsi *vsi)
5122{
5123 struct i40e_pf *pf = vsi->back;
5124 int err;
5125
5126 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5127 i40e_vsi_configure_msix(vsi);
5128 else
5129 i40e_configure_msi_and_legacy(vsi);
5130
5131 /* start rings */
5132 err = i40e_vsi_control_rings(vsi, true);
5133 if (err)
5134 return err;
5135
5136 clear_bit(__I40E_DOWN, &vsi->state);
5137 i40e_napi_enable_all(vsi);
5138 i40e_vsi_enable_irq(vsi);
5139
5140 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5141 (vsi->netdev)) {
cf05ed08 5142 i40e_print_link_message(vsi, true);
41c445ff
JB		 5143 netif_tx_start_all_queues(vsi->netdev);
5144 netif_carrier_on(vsi->netdev);
6d779b41 5145 } else if (vsi->netdev) {
cf05ed08 5146 i40e_print_link_message(vsi, false);
7b592f61
CW		 5147 /* need to check for qualified module here*/
5148 if ((pf->hw.phy.link_info.link_info &
5149 I40E_AQ_MEDIA_AVAILABLE) &&
5150 (!(pf->hw.phy.link_info.an_info &
5151 I40E_AQ_QUALIFIED_MODULE)))
5152 netdev_err(vsi->netdev,
5153 "the driver failed to link because an unqualified module was detected.");
41c445ff 5154 }
ca64fa4e
ASJ		 5155
5156 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5157 if (vsi->type == I40E_VSI_FDIR) {
5158 /* reset fd counters */
5159 pf->fd_add_err = pf->fd_atr_cnt = 0;
5160 if (pf->fd_tcp_rule > 0) {
5161 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5162 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5163 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5164 pf->fd_tcp_rule = 0;
5165 }
ca64fa4e 5166 i40e_fdir_filter_restore(vsi);
1e1be8f6 5167 }
41c445ff
JB		 5168 i40e_service_event_schedule(pf);
5169
5170 return 0;
5171}
5172
5173/**
5174 * i40e_vsi_reinit_locked - Reset the VSI
5175 * @vsi: the VSI being configured
5176 *
5177 * Rebuild the ring structs after some configuration
5178 * has changed, e.g. MTU size.
5179 **/
5180static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5181{
5182 struct i40e_pf *pf = vsi->back;
5183
5184 WARN_ON(in_interrupt());
5185 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5186 usleep_range(1000, 2000);
5187 i40e_down(vsi);
5188
5189 /* Give a VF some time to respond to the reset. The
5190 * two second wait is based upon the watchdog cycle in
5191 * the VF driver.
5192 */
5193 if (vsi->type == I40E_VSI_SRIOV)
5194 msleep(2000);
5195 i40e_up(vsi);
5196 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5197}
5198
5199/**
5200 * i40e_up - Bring the connection back up after being down
5201 * @vsi: the VSI being configured
5202 **/
5203int i40e_up(struct i40e_vsi *vsi)
5204{
5205 int err;
5206
5207 err = i40e_vsi_configure(vsi);
5208 if (!err)
5209 err = i40e_up_complete(vsi);
5210
5211 return err;
5212}
5213
5214/**
5215 * i40e_down - Shutdown the connection processing
5216 * @vsi: the VSI being stopped
5217 **/
5218void i40e_down(struct i40e_vsi *vsi)
5219{
5220 int i;
5221
5222 /* It is assumed that the caller of this function
5223 * sets the vsi->state __I40E_DOWN bit.
5224 */
5225 if (vsi->netdev) {
5226 netif_carrier_off(vsi->netdev);
5227 netif_tx_disable(vsi->netdev);
5228 }
5229 i40e_vsi_disable_irq(vsi);
5230 i40e_vsi_control_rings(vsi, false);
5231 i40e_napi_disable_all(vsi);
5232
5233 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5234 i40e_clean_tx_ring(vsi->tx_rings[i]);
5235 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5236 }
5237}
5238
5239/**
5240 * i40e_setup_tc - configure multiple traffic classes
5241 * @netdev: net device to configure
5242 * @tc: number of traffic classes to enable
5243 **/
38e00438
VD		 5244#ifdef I40E_FCOE
5245int i40e_setup_tc(struct net_device *netdev, u8 tc)
5246#else
41c445ff 5247static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5248#endif
41c445ff
JB		 5249{
5250 struct i40e_netdev_priv *np = netdev_priv(netdev);
5251 struct i40e_vsi *vsi = np->vsi;
5252 struct i40e_pf *pf = vsi->back;
5253 u8 enabled_tc = 0;
5254 int ret = -EINVAL;
5255 int i;
5256
5257 /* Check if DCB enabled to continue */
5258 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5259 netdev_info(netdev, "DCB is not enabled for adapter\n");
5260 goto exit;
5261 }
5262
5263 /* Check if MFP enabled */
5264 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5265 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5266 goto exit;
5267 }
5268
5269 /* Check whether tc count is within enabled limit */
5270 if (tc > i40e_pf_get_num_tc(pf)) {
5271 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5272 goto exit;
5273 }
5274
5275 /* Generate TC map for number of tc requested */
5276 for (i = 0; i < tc; i++)
75f5cea9 5277 enabled_tc |= BIT(i);
41c445ff
JB		 5278
5279 /* Requesting same TC configuration as already enabled */
5280 if (enabled_tc == vsi->tc_config.enabled_tc)
5281 return 0;
5282
5283 /* Quiesce VSI queues */
5284 i40e_quiesce_vsi(vsi);
5285
5286 /* Configure VSI for enabled TCs */
5287 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5288 if (ret) {
5289 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5290 vsi->seid);
5291 goto exit;
5292 }
5293
5294 /* Unquiesce VSI */
5295 i40e_unquiesce_vsi(vsi);
5296
5297exit:
5298 return ret;
5299}
5300
5301/**
5302 * i40e_open - Called when a network interface is made active
5303 * @netdev: network interface device structure
5304 *
5305 * The open entry point is called when a network interface is made
5306 * active by the system (IFF_UP). At this point all resources needed
5307 * for transmit and receive operations are allocated, the interrupt
5308 * handler is registered with the OS, the netdev watchdog subtask is
5309 * enabled, and the stack is notified that the interface is ready.
5310 *
5311 * Returns 0 on success, negative value on failure
5312 **/
38e00438 5313int i40e_open(struct net_device *netdev)
41c445ff
JB		 5314{
5315 struct i40e_netdev_priv *np = netdev_priv(netdev);
5316 struct i40e_vsi *vsi = np->vsi;
5317 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5318 int err;
5319
4eb3f768
SN		 5320 /* disallow open during test or if eeprom is broken */
5321 if (test_bit(__I40E_TESTING, &pf->state) ||
5322 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5323 return -EBUSY;
5324
5325 netif_carrier_off(netdev);
5326
6c167f58
EK		 5327 err = i40e_vsi_open(vsi);
5328 if (err)
5329 return err;
5330
059dab69
JB		 5331 /* configure global TSO hardware offload settings */
5332 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5333 TCP_FLAG_FIN) >> 16);
5334 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5335 TCP_FLAG_FIN |
5336 TCP_FLAG_CWR) >> 16);
5337 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5338
6633d381 5339#ifdef CONFIG_I40E_VXLAN
6c167f58
EK		 5340 vxlan_get_rx_port(netdev);
5341#endif
5342
5343 return 0;
5344}
5345
5346/**
5347 * i40e_vsi_open -
5348 * @vsi: the VSI to open
5349 *
5350 * Finish initialization of the VSI.
5351 *
5352 * Returns 0 on success, negative value on failure
5353 **/
5354int i40e_vsi_open(struct i40e_vsi *vsi)
5355{
5356 struct i40e_pf *pf = vsi->back;
b294ac70 5357 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5358 int err;
5359
41c445ff
JB		 5360 /* allocate descriptors */
5361 err = i40e_vsi_setup_tx_resources(vsi);
5362 if (err)
5363 goto err_setup_tx;
5364 err = i40e_vsi_setup_rx_resources(vsi);
5365 if (err)
5366 goto err_setup_rx;
5367
5368 err = i40e_vsi_configure(vsi);
5369 if (err)
5370 goto err_setup_rx;
5371
c22e3c6c
SN		 5372 if (vsi->netdev) {
5373 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5374 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5375 err = i40e_vsi_request_irq(vsi, int_name);
5376 if (err)
5377 goto err_setup_rx;
41c445ff 5378
c22e3c6c
SN		 5379 /* Notify the stack of the actual queue counts. */
5380 err = netif_set_real_num_tx_queues(vsi->netdev,
5381 vsi->num_queue_pairs);
5382 if (err)
5383 goto err_set_queues;
25946ddb 5384
c22e3c6c
SN		 5385 err = netif_set_real_num_rx_queues(vsi->netdev,
5386 vsi->num_queue_pairs);
5387 if (err)
5388 goto err_set_queues;
8a9eb7d3
SN		 5389
5390 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5391 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5392 dev_driver_string(&pf->pdev->dev),
5393 dev_name(&pf->pdev->dev));
8a9eb7d3 5394 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5395
c22e3c6c 5396 } else {
ce9ccb17 5397 err = -EINVAL;
6c167f58
EK		 5398 goto err_setup_rx;
5399 }
25946ddb 5400
41c445ff
JB		 5401 err = i40e_up_complete(vsi);
5402 if (err)
5403 goto err_up_complete;
5404
41c445ff
JB		 5405 return 0;
5406
5407err_up_complete:
5408 i40e_down(vsi);
25946ddb 5409err_set_queues:
41c445ff
JB		 5410 i40e_vsi_free_irq(vsi);
5411err_setup_rx:
5412 i40e_vsi_free_rx_resources(vsi);
5413err_setup_tx:
5414 i40e_vsi_free_tx_resources(vsi);
5415 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5416 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5417
5418 return err;
5419}
5420
17a73f6b
JG		 5421/**
5422 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5423 * @pf: Pointer to PF
17a73f6b
JG		 5424 *
5425 * This function destroys the hlist where all the Flow Director
5426 * filters were saved.
5427 **/
5428static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5429{
5430 struct i40e_fdir_filter *filter;
5431 struct hlist_node *node2;
5432
5433 hlist_for_each_entry_safe(filter, node2,
5434 &pf->fdir_filter_list, fdir_node) {
5435 hlist_del(&filter->fdir_node);
5436 kfree(filter);
5437 }
5438 pf->fdir_pf_active_filters = 0;
5439}
5440
41c445ff
JB		 5441/**
5442 * i40e_close - Disables a network interface
5443 * @netdev: network interface device structure
5444 *
5445 * The close entry point is called when an interface is de-activated
5446 * by the OS. The hardware is still under the driver's control, but
5447 * this netdev interface is disabled.
5448 *
5449 * Returns 0, this is not allowed to fail
5450 **/
38e00438
VD		 5451#ifdef I40E_FCOE
5452int i40e_close(struct net_device *netdev)
5453#else
41c445ff 5454static int i40e_close(struct net_device *netdev)
38e00438 5455#endif
41c445ff
JB		 5456{
5457 struct i40e_netdev_priv *np = netdev_priv(netdev);
5458 struct i40e_vsi *vsi = np->vsi;
5459
90ef8d47 5460 i40e_vsi_close(vsi);
41c445ff
JB		 5461
5462 return 0;
5463}
5464
5465/**
5466 * i40e_do_reset - Start a PF or Core Reset sequence
5467 * @pf: board private structure
5468 * @reset_flags: which reset is requested
5469 *
5470 * The essential difference in resets is that the PF Reset
5471 * doesn't clear the packet buffers, doesn't reset the PE
5472 * firmware, and doesn't bother the other PFs on the chip.
5473 **/
5474void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5475{
5476 u32 val;
5477
5478 WARN_ON(in_interrupt());
5479
263fc48f
MW		 5480 if (i40e_check_asq_alive(&pf->hw))
5481 i40e_vc_notify_reset(pf);
5482
41c445ff 5483 /* do the biggest reset indicated */
41a1d04b 5484 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5485
5486 /* Request a Global Reset
5487 *
5488 * This will start the chip's countdown to the actual full
5489 * chip reset event, and a warning interrupt to be sent
5490 * to all PFs, including the requestor. Our handler
5491 * for the warning interrupt will deal with the shutdown
5492 * and recovery of the switch setup.
5493 */
69bfb110 5494 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5495 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5496 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5497 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5498
41a1d04b 5499 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5500
5501 /* Request a Core Reset
5502 *
5503 * Same as Global Reset, except does *not* include the MAC/PHY
5504 */
69bfb110 5505 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5506 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5507 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5508 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5509 i40e_flush(&pf->hw);
5510
41a1d04b 5511 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5512
5513 /* Request a PF Reset
5514 *
5515 * Resets only the PF-specific registers
5516 *
5517 * This goes directly to the tear-down and rebuild of
5518 * the switch, since we need to do all the recovery as
5519 * for the Core Reset.
5520 */
69bfb110 5521 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5522 i40e_handle_reset_warning(pf);
5523
41a1d04b 5524 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5525 int v;
5526
5527 /* Find the VSI(s) that requested a re-init */
5528 dev_info(&pf->pdev->dev,
5529 "VSI reinit requested\n");
505682cd 5530 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5531 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5532
41c445ff
JB		 5533 if (vsi != NULL &&
5534 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5535 i40e_vsi_reinit_locked(pf->vsi[v]);
5536 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5537 }
5538 }
41a1d04b 5539 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5540 int v;
5541
5542 /* Find the VSI(s) that needs to be brought down */
5543 dev_info(&pf->pdev->dev, "VSI down requested\n");
5544 for (v = 0; v < pf->num_alloc_vsi; v++) {
5545 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5546
b5d06f05
NP		 5547 if (vsi != NULL &&
5548 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5549 set_bit(__I40E_DOWN, &vsi->state);
5550 i40e_down(vsi);
5551 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5552 }
5553 }
41c445ff
JB		 5554 } else {
5555 dev_info(&pf->pdev->dev,
5556 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5557 }
5558}
5559
4e3b35b0
NP		 5560#ifdef CONFIG_I40E_DCB
5561/**
5562 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5563 * @pf: board private structure
5564 * @old_cfg: current DCB config
5565 * @new_cfg: new DCB config
5566 **/
5567bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5568 struct i40e_dcbx_config *old_cfg,
5569 struct i40e_dcbx_config *new_cfg)
5570{
5571 bool need_reconfig = false;
5572
5573 /* Check if ETS configuration has changed */
5574 if (memcmp(&new_cfg->etscfg,
5575 &old_cfg->etscfg,
5576 sizeof(new_cfg->etscfg))) {
5577 /* If Priority Table has changed reconfig is needed */
5578 if (memcmp(&new_cfg->etscfg.prioritytable,
5579 &old_cfg->etscfg.prioritytable,
5580 sizeof(new_cfg->etscfg.prioritytable))) {
5581 need_reconfig = true;
69bfb110 5582 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5583 }
5584
5585 if (memcmp(&new_cfg->etscfg.tcbwtable,
5586 &old_cfg->etscfg.tcbwtable,
5587 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5588 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5589
5590 if (memcmp(&new_cfg->etscfg.tsatable,
5591 &old_cfg->etscfg.tsatable,
5592 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5593 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5594 }
5595
5596 /* Check if PFC configuration has changed */
5597 if (memcmp(&new_cfg->pfc,
5598 &old_cfg->pfc,
5599 sizeof(new_cfg->pfc))) {
5600 need_reconfig = true;
69bfb110 5601 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5602 }
5603
5604 /* Check if APP Table has changed */
5605 if (memcmp(&new_cfg->app,
5606 &old_cfg->app,
3d9667a9 5607 sizeof(new_cfg->app))) {
4e3b35b0 5608 need_reconfig = true;
69bfb110 5609 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5610 }
4e3b35b0 5611
fb43201f 5612 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5613 return need_reconfig;
5614}
5615
5616/**
5617 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5618 * @pf: board private structure
5619 * @e: event info posted on ARQ
5620 **/
5621static int i40e_handle_lldp_event(struct i40e_pf *pf,
5622 struct i40e_arq_event_info *e)
5623{
5624 struct i40e_aqc_lldp_get_mib *mib =
5625 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5626 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5627 struct i40e_dcbx_config tmp_dcbx_cfg;
5628 bool need_reconfig = false;
5629 int ret = 0;
5630 u8 type;
5631
4d9b6043
NP		 5632 /* Not DCB capable or capability disabled */
5633 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5634 return ret;
5635
4e3b35b0
NP		 5636 /* Ignore if event is not for Nearest Bridge */
5637 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5638 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5639 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5640 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5641 return ret;
5642
5643 /* Check MIB Type and return if event for Remote MIB update */
5644 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5645 dev_dbg(&pf->pdev->dev,
fb43201f 5646 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5647 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5648 /* Update the remote cached instance and return */
5649 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5650 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5651 &hw->remote_dcbx_config);
5652 goto exit;
5653 }
5654
9fa61dd2 5655 /* Store the old configuration */
1a2f6248 5656 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5657
750fcbcf
NP		 5658 /* Reset the old DCBx configuration data */
5659 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5660 /* Get updated DCBX data from firmware */
5661 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5662 if (ret) {
f1c7e72e
SN		 5663 dev_info(&pf->pdev->dev,
5664 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5665 i40e_stat_str(&pf->hw, ret),
5666 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5667 goto exit;
5668 }
5669
5670 /* No change detected in DCBX configs */
750fcbcf
NP		 5671 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5672 sizeof(tmp_dcbx_cfg))) {
69bfb110 5673 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5674 goto exit;
5675 }
5676
750fcbcf
NP		 5677 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5678 &hw->local_dcbx_config);
4e3b35b0 5679
750fcbcf 5680 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5681
5682 if (!need_reconfig)
5683 goto exit;
5684
4d9b6043 5685 /* Enable DCB tagging only when more than one TC */
750fcbcf 5686 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5687 pf->flags |= I40E_FLAG_DCB_ENABLED;
5688 else
5689 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5690
69129dc3 5691 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5692 /* Reconfiguration needed quiesce all VSIs */
5693 i40e_pf_quiesce_all_vsi(pf);
5694
5695 /* Changes in configuration update VEB/VSI */
5696 i40e_dcb_reconfigure(pf);
5697
2fd75f31
NP		 5698 ret = i40e_resume_port_tx(pf);
5699
69129dc3 5700 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5701 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5702 if (ret)
5703 goto exit;
5704
5705 /* Wait for the PF's Tx queues to be disabled */
5706 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5707 if (ret) {
5708 /* Schedule PF reset to recover */
5709 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5710 i40e_service_event_schedule(pf);
5711 } else {
2fd75f31 5712 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5713 }
5714
4e3b35b0
NP		 5715exit:
5716 return ret;
5717}
5718#endif /* CONFIG_I40E_DCB */
5719
23326186
ASJ		 5720/**
5721 * i40e_do_reset_safe - Protected reset path for userland calls.
5722 * @pf: board private structure
5723 * @reset_flags: which reset is requested
5724 *
5725 **/
5726void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5727{
5728 rtnl_lock();
5729 i40e_do_reset(pf, reset_flags);
5730 rtnl_unlock();
5731}
5732
41c445ff
JB		 5733/**
5734 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5735 * @pf: board private structure
5736 * @e: event info posted on ARQ
5737 *
5738 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5739 * and VF queues
5740 **/
5741static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5742 struct i40e_arq_event_info *e)
5743{
5744 struct i40e_aqc_lan_overflow *data =
5745 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5746 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5747 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5748 struct i40e_hw *hw = &pf->hw;
5749 struct i40e_vf *vf;
5750 u16 vf_id;
5751
69bfb110
JB		 5752 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5753 queue, qtx_ctl);
41c445ff
JB		 5754
5755 /* Queue belongs to VF, find the VF and issue VF reset */
5756 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5757 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5758 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5759 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5760 vf_id -= hw->func_caps.vf_base_id;
5761 vf = &pf->vf[vf_id];
5762 i40e_vc_notify_vf_reset(vf);
5763 /* Allow VF to process pending reset notification */
5764 msleep(20);
5765 i40e_reset_vf(vf, false);
5766 }
5767}
5768
5769/**
5770 * i40e_service_event_complete - Finish up the service event
5771 * @pf: board private structure
5772 **/
5773static void i40e_service_event_complete(struct i40e_pf *pf)
5774{
b875f99b 5775 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5776
5777 /* flush memory to make sure state is correct before next watchog */
4e857c58 5778 smp_mb__before_atomic();
41c445ff
JB		 5779 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5780}
5781
55a5e60b 5782/**
12957388
ASJ		 5783 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5784 * @pf: board private structure
5785 **/
04294e38 5786u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5787{
04294e38 5788 u32 val, fcnt_prog;
12957388
ASJ		 5789
5790 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5791 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5792 return fcnt_prog;
5793}
5794
5795/**
04294e38 5796 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5797 * @pf: board private structure
5798 **/
04294e38 5799u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5800{
04294e38
ASJ		 5801 u32 val, fcnt_prog;
5802
55a5e60b
ASJ		 5803 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5804 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5805 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5806 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5807 return fcnt_prog;
5808}
1e1be8f6 5809
04294e38
ASJ		 5810/**
5811 * i40e_get_global_fd_count - Get total FD filters programmed on device
5812 * @pf: board private structure
5813 **/
5814u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5815{
5816 u32 val, fcnt_prog;
5817
5818 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5819 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5820 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5821 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5822 return fcnt_prog;
5823}
5824
55a5e60b
ASJ		 5825/**
5826 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5827 * @pf: board private structure
5828 **/
5829void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5830{
3487b6c3 5831 struct i40e_fdir_filter *filter;
55a5e60b 5832 u32 fcnt_prog, fcnt_avail;
3487b6c3 5833 struct hlist_node *node;
55a5e60b 5834
1e1be8f6
ASJ		 5835 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5836 return;
5837
55a5e60b
ASJ		 5838 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5839 * to re-enable
5840 */
04294e38 5841 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5842 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5843 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5844 (pf->fd_add_err == 0) ||
5845 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5846 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5847 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5848 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5849 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5850 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5851 }
5852 }
5853 /* Wait for some more space to be available to turn on ATR */
5854 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5855 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5856 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5857 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5858 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5859 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5860 }
5861 }
3487b6c3
CW		 5862
5863 /* if hw had a problem adding a filter, delete it */
5864 if (pf->fd_inv > 0) {
5865 hlist_for_each_entry_safe(filter, node,
5866 &pf->fdir_filter_list, fdir_node) {
5867 if (filter->fd_id == pf->fd_inv) {
5868 hlist_del(&filter->fdir_node);
5869 kfree(filter);
5870 pf->fdir_pf_active_filters--;
5871 }
5872 }
5873 }
55a5e60b
ASJ		 5874}
5875
1e1be8f6 5876#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5877#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5878/**
5879 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5880 * @pf: board private structure
5881 **/
5882static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5883{
04294e38 5884 unsigned long min_flush_time;
1e1be8f6 5885 int flush_wait_retry = 50;
04294e38
ASJ		 5886 bool disable_atr = false;
5887 int fd_room;
1e1be8f6
ASJ		 5888 int reg;
5889
1790ed0c
AA		 5890 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5891 return;
5892
a5fdaf34
JB		 5893 if (!time_after(jiffies, pf->fd_flush_timestamp +
5894 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5895 return;
04294e38 5896
a5fdaf34
JB		 5897 /* If the flush is happening too quick and we have mostly SB rules we
5898 * should not re-enable ATR for some time.
5899 */
5900 min_flush_time = pf->fd_flush_timestamp +
5901 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5902 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5903
5904 if (!(time_after(jiffies, min_flush_time)) &&
5905 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5906 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5907 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5908 disable_atr = true;
5909 }
5910
5911 pf->fd_flush_timestamp = jiffies;
5912 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5913 /* flush all filters */
5914 wr32(&pf->hw, I40E_PFQF_CTL_1,
5915 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5916 i40e_flush(&pf->hw);
5917 pf->fd_flush_cnt++;
5918 pf->fd_add_err = 0;
5919 do {
5920 /* Check FD flush status every 5-6msec */
5921 usleep_range(5000, 6000);
5922 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5923 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5924 break;
5925 } while (flush_wait_retry--);
5926 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5927 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5928 } else {
5929 /* replay sideband filters */
5930 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5931 if (!disable_atr)
5932 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5933 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5934 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5935 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5936 }
a5fdaf34 5937
1e1be8f6
ASJ		 5938}
5939
5940/**
5941 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5942 * @pf: board private structure
5943 **/
04294e38 5944u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5945{
5946 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5947}
5948
5949/* We can see up to 256 filter programming desc in transit if the filters are
5950 * being applied really fast; before we see the first
5951 * filter miss error on Rx queue 0. Accumulating enough error messages before
5952 * reacting will make sure we don't cause flush too often.
5953 */
5954#define I40E_MAX_FD_PROGRAM_ERROR 256
5955
41c445ff
JB		 5956/**
5957 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5958 * @pf: board private structure
5959 **/
5960static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5961{
41c445ff 5962
41c445ff
JB		 5963 /* if interface is down do nothing */
5964 if (test_bit(__I40E_DOWN, &pf->state))
5965 return;
1e1be8f6 5966
1790ed0c
AA		 5967 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5968 return;
5969
04294e38 5970 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5971 i40e_fdir_flush_and_replay(pf);
5972
55a5e60b
ASJ		 5973 i40e_fdir_check_and_reenable(pf);
5974
41c445ff
JB		 5975}
5976
5977/**
5978 * i40e_vsi_link_event - notify VSI of a link event
5979 * @vsi: vsi to be notified
5980 * @link_up: link up or down
5981 **/
5982static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5983{
32b5b811 5984 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5985 return;
5986
5987 switch (vsi->type) {
5988 case I40E_VSI_MAIN:
38e00438
VD		 5989#ifdef I40E_FCOE
5990 case I40E_VSI_FCOE:
5991#endif
41c445ff
JB		 5992 if (!vsi->netdev || !vsi->netdev_registered)
5993 break;
5994
5995 if (link_up) {
5996 netif_carrier_on(vsi->netdev);
5997 netif_tx_wake_all_queues(vsi->netdev);
5998 } else {
5999 netif_carrier_off(vsi->netdev);
6000 netif_tx_stop_all_queues(vsi->netdev);
6001 }
6002 break;
6003
6004 case I40E_VSI_SRIOV:
41c445ff
JB		 6005 case I40E_VSI_VMDQ2:
6006 case I40E_VSI_CTRL:
6007 case I40E_VSI_MIRROR:
6008 default:
6009 /* there is no notification for other VSIs */
6010 break;
6011 }
6012}
6013
6014/**
6015 * i40e_veb_link_event - notify elements on the veb of a link event
6016 * @veb: veb to be notified
6017 * @link_up: link up or down
6018 **/
6019static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6020{
6021 struct i40e_pf *pf;
6022 int i;
6023
6024 if (!veb || !veb->pf)
6025 return;
6026 pf = veb->pf;
6027
6028 /* depth first... */
6029 for (i = 0; i < I40E_MAX_VEB; i++)
6030 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6031 i40e_veb_link_event(pf->veb[i], link_up);
6032
6033 /* ... now the local VSIs */
505682cd 6034 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6035 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6036 i40e_vsi_link_event(pf->vsi[i], link_up);
6037}
6038
6039/**
6040 * i40e_link_event - Update netif_carrier status
6041 * @pf: board private structure
6042 **/
6043static void i40e_link_event(struct i40e_pf *pf)
6044{
320684cd 6045 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6046 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6047 i40e_status status;
6048 bool new_link, old_link;
41c445ff 6049
1f9610e4
CS		 6050 /* save off old link status information */
6051 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6052
1e701e09
JB		 6053 /* set this to force the get_link_status call to refresh state */
6054 pf->hw.phy.get_link_info = true;
6055
41c445ff 6056 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6057
6058 status = i40e_get_link_status(&pf->hw, &new_link);
6059 if (status) {
6060 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6061 status);
6062 return;
6063 }
6064
fef59ddf
CS		 6065 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6066 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6067
1e701e09 6068 if (new_link == old_link &&
fef59ddf 6069 new_link_speed == old_link_speed &&
320684cd
MW		 6070 (test_bit(__I40E_DOWN, &vsi->state) ||
6071 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6072 return;
320684cd
MW		 6073
6074 if (!test_bit(__I40E_DOWN, &vsi->state))
6075 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6076
6077 /* Notify the base of the switch tree connected to
6078 * the link. Floating VEBs are not notified.
6079 */
6080 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6081 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6082 else
320684cd 6083 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6084
6085 if (pf->vf)
6086 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6087
6088 if (pf->flags & I40E_FLAG_PTP)
6089 i40e_ptp_set_increment(pf);
41c445ff
JB		 6090}
6091
41c445ff 6092/**
21536717 6093 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6094 * @pf: board private structure
6095 **/
6096static void i40e_watchdog_subtask(struct i40e_pf *pf)
6097{
6098 int i;
6099
6100 /* if interface is down do nothing */
6101 if (test_bit(__I40E_DOWN, &pf->state) ||
6102 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6103 return;
6104
21536717
SN		 6105 /* make sure we don't do these things too often */
6106 if (time_before(jiffies, (pf->service_timer_previous +
6107 pf->service_timer_period)))
6108 return;
6109 pf->service_timer_previous = jiffies;
6110
9ac77266
SN		 6111 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6112 i40e_link_event(pf);
21536717 6113
41c445ff
JB		 6114 /* Update the stats for active netdevs so the network stack
6115 * can look at updated numbers whenever it cares to
6116 */
505682cd 6117 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6118 if (pf->vsi[i] && pf->vsi[i]->netdev)
6119 i40e_update_stats(pf->vsi[i]);
6120
d1a8d275
ASJ		 6121 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6122 /* Update the stats for the active switching components */
6123 for (i = 0; i < I40E_MAX_VEB; i++)
6124 if (pf->veb[i])
6125 i40e_update_veb_stats(pf->veb[i]);
6126 }
beb0dff1
JK		 6127
6128 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6129}
6130
6131/**
6132 * i40e_reset_subtask - Set up for resetting the device and driver
6133 * @pf: board private structure
6134 **/
6135static void i40e_reset_subtask(struct i40e_pf *pf)
6136{
6137 u32 reset_flags = 0;
6138
23326186 6139 rtnl_lock();
41c445ff 6140 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6141 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6142 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6143 }
6144 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6145 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6146 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6147 }
6148 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6149 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6150 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6151 }
6152 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6153 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6154 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6155 }
b5d06f05 6156 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6157 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6158 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6159 }
41c445ff
JB		 6160
6161 /* If there's a recovery already waiting, it takes
6162 * precedence before starting a new reset sequence.
6163 */
6164 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6165 i40e_handle_reset_warning(pf);
23326186 6166 goto unlock;
41c445ff
JB		 6167 }
6168
6169 /* If we're already down or resetting, just bail */
6170 if (reset_flags &&
6171 !test_bit(__I40E_DOWN, &pf->state) &&
6172 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6173 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6174
6175unlock:
6176 rtnl_unlock();
41c445ff
JB		 6177}
6178
6179/**
6180 * i40e_handle_link_event - Handle link event
6181 * @pf: board private structure
6182 * @e: event info posted on ARQ
6183 **/
6184static void i40e_handle_link_event(struct i40e_pf *pf,
6185 struct i40e_arq_event_info *e)
6186{
41c445ff
JB		 6187 struct i40e_aqc_get_link_status *status =
6188 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6189
1e701e09
JB		 6190 /* Do a new status request to re-enable LSE reporting
6191 * and load new status information into the hw struct
6192 * This completely ignores any state information
6193 * in the ARQ event info, instead choosing to always
6194 * issue the AQ update link status command.
6195 */
6196 i40e_link_event(pf);
6197
7b592f61
CW		 6198 /* check for unqualified module, if link is down */
6199 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6200 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6201 (!(status->link_info & I40E_AQ_LINK_UP)))
6202 dev_err(&pf->pdev->dev,
6203 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6204}
6205
6206/**
6207 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6208 * @pf: board private structure
6209 **/
6210static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6211{
6212 struct i40e_arq_event_info event;
6213 struct i40e_hw *hw = &pf->hw;
6214 u16 pending, i = 0;
6215 i40e_status ret;
6216 u16 opcode;
86df242b 6217 u32 oldval;
41c445ff
JB		 6218 u32 val;
6219
a316f651
ASJ		 6220 /* Do not run clean AQ when PF reset fails */
6221 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6222 return;
6223
86df242b
SN		 6224 /* check for error indications */
6225 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6226 oldval = val;
6227 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6228 if (hw->debug_mask & I40E_DEBUG_AQ)
6229 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6230 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6231 }
6232 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6233 if (hw->debug_mask & I40E_DEBUG_AQ)
6234 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b
SN		 6235 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6236 }
6237 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6238 if (hw->debug_mask & I40E_DEBUG_AQ)
6239 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6240 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6241 }
6242 if (oldval != val)
6243 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6244
6245 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6246 oldval = val;
6247 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6248 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6249 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6250 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6251 }
6252 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6253 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6254 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6255 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6256 }
6257 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6258 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6259 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6260 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6261 }
6262 if (oldval != val)
6263 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6264
1001dc37
MW		 6265 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6266 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6267 if (!event.msg_buf)
6268 return;
6269
6270 do {
6271 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6272 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6273 break;
56497978 6274 else if (ret) {
41c445ff
JB		 6275 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6276 break;
6277 }
6278
6279 opcode = le16_to_cpu(event.desc.opcode);
6280 switch (opcode) {
6281
6282 case i40e_aqc_opc_get_link_status:
6283 i40e_handle_link_event(pf, &event);
6284 break;
6285 case i40e_aqc_opc_send_msg_to_pf:
6286 ret = i40e_vc_process_vf_msg(pf,
6287 le16_to_cpu(event.desc.retval),
6288 le32_to_cpu(event.desc.cookie_high),
6289 le32_to_cpu(event.desc.cookie_low),
6290 event.msg_buf,
1001dc37 6291 event.msg_len);
41c445ff
JB		 6292 break;
6293 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6294 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6295#ifdef CONFIG_I40E_DCB
6296 rtnl_lock();
6297 ret = i40e_handle_lldp_event(pf, &event);
6298 rtnl_unlock();
6299#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6300 break;
6301 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6302 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6303 i40e_handle_lan_overflow_event(pf, &event);
6304 break;
0467bc91
SN		 6305 case i40e_aqc_opc_send_msg_to_peer:
6306 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6307 break;
91a0f930
SN		 6308 case i40e_aqc_opc_nvm_erase:
6309 case i40e_aqc_opc_nvm_update:
00ada50d 6310 case i40e_aqc_opc_oem_post_update:
91a0f930
SN		 6311 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6312 break;
41c445ff
JB		 6313 default:
6314 dev_info(&pf->pdev->dev,
0467bc91
SN		 6315 "ARQ Error: Unknown event 0x%04x received\n",
6316 opcode);
41c445ff
JB		 6317 break;
6318 }
6319 } while (pending && (i++ < pf->adminq_work_limit));
6320
6321 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6322 /* re-enable Admin queue interrupt cause */
6323 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6324 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6325 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6326 i40e_flush(hw);
6327
6328 kfree(event.msg_buf);
6329}
6330
4eb3f768
SN		 6331/**
6332 * i40e_verify_eeprom - make sure eeprom is good to use
6333 * @pf: board private structure
6334 **/
6335static void i40e_verify_eeprom(struct i40e_pf *pf)
6336{
6337 int err;
6338
6339 err = i40e_diag_eeprom_test(&pf->hw);
6340 if (err) {
6341 /* retry in case of garbage read */
6342 err = i40e_diag_eeprom_test(&pf->hw);
6343 if (err) {
6344 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6345 err);
6346 set_bit(__I40E_BAD_EEPROM, &pf->state);
6347 }
6348 }
6349
6350 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6351 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6352 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6353 }
6354}
6355
386a0afa
AA		 6356/**
6357 * i40e_enable_pf_switch_lb
b40c82e6 6358 * @pf: pointer to the PF structure
386a0afa
AA		 6359 *
6360 * enable switch loop back or die - no point in a return value
6361 **/
6362static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6363{
6364 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6365 struct i40e_vsi_context ctxt;
f1c7e72e 6366 int ret;
386a0afa
AA		 6367
6368 ctxt.seid = pf->main_vsi_seid;
6369 ctxt.pf_num = pf->hw.pf_id;
6370 ctxt.vf_num = 0;
f1c7e72e
SN		 6371 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6372 if (ret) {
386a0afa 6373 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6374 "couldn't get PF vsi config, err %s aq_err %s\n",
6375 i40e_stat_str(&pf->hw, ret),
6376 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6377 return;
6378 }
6379 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6380 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6381 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6382
f1c7e72e
SN		 6383 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6384 if (ret) {
386a0afa 6385 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6386 "update vsi switch failed, err %s aq_err %s\n",
6387 i40e_stat_str(&pf->hw, ret),
6388 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6389 }
6390}
6391
6392/**
6393 * i40e_disable_pf_switch_lb
b40c82e6 6394 * @pf: pointer to the PF structure
386a0afa
AA		 6395 *
6396 * disable switch loop back or die - no point in a return value
6397 **/
6398static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6399{
6400 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6401 struct i40e_vsi_context ctxt;
f1c7e72e 6402 int ret;
386a0afa
AA		 6403
6404 ctxt.seid = pf->main_vsi_seid;
6405 ctxt.pf_num = pf->hw.pf_id;
6406 ctxt.vf_num = 0;
f1c7e72e
SN		 6407 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6408 if (ret) {
386a0afa 6409 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6410 "couldn't get PF vsi config, err %s aq_err %s\n",
6411 i40e_stat_str(&pf->hw, ret),
6412 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6413 return;
6414 }
6415 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6416 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6417 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6418
f1c7e72e
SN		 6419 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6420 if (ret) {
386a0afa 6421 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6422 "update vsi switch failed, err %s aq_err %s\n",
6423 i40e_stat_str(&pf->hw, ret),
6424 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6425 }
6426}
6427
51616018
NP		 6428/**
6429 * i40e_config_bridge_mode - Configure the HW bridge mode
6430 * @veb: pointer to the bridge instance
6431 *
6432 * Configure the loop back mode for the LAN VSI that is downlink to the
6433 * specified HW bridge instance. It is expected this function is called
6434 * when a new HW bridge is instantiated.
6435 **/
6436static void i40e_config_bridge_mode(struct i40e_veb *veb)
6437{
6438 struct i40e_pf *pf = veb->pf;
6439
6dec1017
SN		 6440 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6441 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6442 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6443 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6444 i40e_disable_pf_switch_lb(pf);
6445 else
6446 i40e_enable_pf_switch_lb(pf);
6447}
6448
41c445ff
JB		 6449/**
6450 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6451 * @veb: pointer to the VEB instance
6452 *
6453 * This is a recursive function that first builds the attached VSIs then
6454 * recurses in to build the next layer of VEB. We track the connections
6455 * through our own index numbers because the seid's from the HW could
6456 * change across the reset.
6457 **/
6458static int i40e_reconstitute_veb(struct i40e_veb *veb)
6459{
6460 struct i40e_vsi *ctl_vsi = NULL;
6461 struct i40e_pf *pf = veb->pf;
6462 int v, veb_idx;
6463 int ret;
6464
6465 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6466 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6467 if (pf->vsi[v] &&
6468 pf->vsi[v]->veb_idx == veb->idx &&
6469 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6470 ctl_vsi = pf->vsi[v];
6471 break;
6472 }
6473 }
6474 if (!ctl_vsi) {
6475 dev_info(&pf->pdev->dev,
6476 "missing owner VSI for veb_idx %d\n", veb->idx);
6477 ret = -ENOENT;
6478 goto end_reconstitute;
6479 }
6480 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6481 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6482 ret = i40e_add_vsi(ctl_vsi);
6483 if (ret) {
6484 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6485 "rebuild of veb_idx %d owner VSI failed: %d\n",
6486 veb->idx, ret);
41c445ff
JB		 6487 goto end_reconstitute;
6488 }
6489 i40e_vsi_reset_stats(ctl_vsi);
6490
6491 /* create the VEB in the switch and move the VSI onto the VEB */
6492 ret = i40e_add_veb(veb, ctl_vsi);
6493 if (ret)
6494 goto end_reconstitute;
6495
fc60861e
ASJ		 6496 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6497 veb->bridge_mode = BRIDGE_MODE_VEB;
6498 else
6499 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6500 i40e_config_bridge_mode(veb);
b64ba084 6501
41c445ff 6502 /* create the remaining VSIs attached to this VEB */
505682cd 6503 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6504 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6505 continue;
6506
6507 if (pf->vsi[v]->veb_idx == veb->idx) {
6508 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6509
41c445ff
JB		 6510 vsi->uplink_seid = veb->seid;
6511 ret = i40e_add_vsi(vsi);
6512 if (ret) {
6513 dev_info(&pf->pdev->dev,
6514 "rebuild of vsi_idx %d failed: %d\n",
6515 v, ret);
6516 goto end_reconstitute;
6517 }
6518 i40e_vsi_reset_stats(vsi);
6519 }
6520 }
6521
6522 /* create any VEBs attached to this VEB - RECURSION */
6523 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6524 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6525 pf->veb[veb_idx]->uplink_seid = veb->seid;
6526 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6527 if (ret)
6528 break;
6529 }
6530 }
6531
6532end_reconstitute:
6533 return ret;
6534}
6535
6536/**
6537 * i40e_get_capabilities - get info about the HW
6538 * @pf: the PF struct
6539 **/
6540static int i40e_get_capabilities(struct i40e_pf *pf)
6541{
6542 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6543 u16 data_size;
6544 int buf_len;
6545 int err;
6546
6547 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6548 do {
6549 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6550 if (!cap_buf)
6551 return -ENOMEM;
6552
6553 /* this loads the data into the hw struct for us */
6554 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6555 &data_size,
6556 i40e_aqc_opc_list_func_capabilities,
6557 NULL);
6558 /* data loaded, buffer no longer needed */
6559 kfree(cap_buf);
6560
6561 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6562 /* retry with a larger buffer */
6563 buf_len = data_size;
6564 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6565 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6566 "capability discovery failed, err %s aq_err %s\n",
6567 i40e_stat_str(&pf->hw, err),
6568 i40e_aq_str(&pf->hw,
6569 pf->hw.aq.asq_last_status));
41c445ff
JB		 6570 return -ENODEV;
6571 }
6572 } while (err);
6573
6574 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6575 dev_info(&pf->pdev->dev,
6576 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6577 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6578 pf->hw.func_caps.num_msix_vectors,
6579 pf->hw.func_caps.num_msix_vectors_vf,
6580 pf->hw.func_caps.fd_filters_guaranteed,
6581 pf->hw.func_caps.fd_filters_best_effort,
6582 pf->hw.func_caps.num_tx_qp,
6583 pf->hw.func_caps.num_vsis);
6584
7134f9ce
JB		 6585#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6586 + pf->hw.func_caps.num_vfs)
6587 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6588 dev_info(&pf->pdev->dev,
6589 "got num_vsis %d, setting num_vsis to %d\n",
6590 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6591 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6592 }
6593
41c445ff
JB		 6594 return 0;
6595}
6596
cbf61325
ASJ		 6597static int i40e_vsi_clear(struct i40e_vsi *vsi);
6598
41c445ff 6599/**
cbf61325 6600 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6601 * @pf: board private structure
6602 **/
cbf61325 6603static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6604{
6605 struct i40e_vsi *vsi;
8a9eb7d3 6606 int i;
41c445ff 6607
407e063c
JB		 6608 /* quick workaround for an NVM issue that leaves a critical register
6609 * uninitialized
6610 */
6611 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6612 static const u32 hkey[] = {
6613 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6614 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6615 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6616 0x95b3a76d};
6617
6618 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6619 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6620 }
6621
cbf61325 6622 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6623 return;
6624
cbf61325 6625 /* find existing VSI and see if it needs configuring */
41c445ff 6626 vsi = NULL;
505682cd 6627 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6628 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6629 vsi = pf->vsi[i];
cbf61325
ASJ		 6630 break;
6631 }
6632 }
6633
6634 /* create a new VSI if none exists */
41c445ff 6635 if (!vsi) {
cbf61325
ASJ		 6636 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6637 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6638 if (!vsi) {
6639 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6640 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6641 return;
41c445ff 6642 }
cbf61325 6643 }
41c445ff 6644
8a9eb7d3 6645 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6646}
6647
6648/**
6649 * i40e_fdir_teardown - release the Flow Director resources
6650 * @pf: board private structure
6651 **/
6652static void i40e_fdir_teardown(struct i40e_pf *pf)
6653{
6654 int i;
6655
17a73f6b 6656 i40e_fdir_filter_exit(pf);
505682cd 6657 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6658 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6659 i40e_vsi_release(pf->vsi[i]);
6660 break;
6661 }
6662 }
6663}
6664
6665/**
f650a38b 6666 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6667 * @pf: board private structure
6668 *
b40c82e6 6669 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6670 **/
23cfbe07 6671static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6672{
41c445ff 6673 struct i40e_hw *hw = &pf->hw;
60442dea 6674 i40e_status ret = 0;
41c445ff
JB		 6675 u32 v;
6676
6677 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6678 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6679 return;
41c445ff 6680
69bfb110 6681 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6682
41c445ff
JB		 6683 /* quiesce the VSIs and their queues that are not already DOWN */
6684 i40e_pf_quiesce_all_vsi(pf);
6685
505682cd 6686 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6687 if (pf->vsi[v])
6688 pf->vsi[v]->seid = 0;
6689 }
6690
6691 i40e_shutdown_adminq(&pf->hw);
6692
f650a38b 6693 /* call shutdown HMC */
60442dea
SN		 6694 if (hw->hmc.hmc_obj) {
6695 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6696 if (ret)
60442dea
SN		 6697 dev_warn(&pf->pdev->dev,
6698 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6699 }
f650a38b
ASJ		 6700}
6701
44033fac
JB		 6702/**
6703 * i40e_send_version - update firmware with driver version
6704 * @pf: PF struct
6705 */
6706static void i40e_send_version(struct i40e_pf *pf)
6707{
6708 struct i40e_driver_version dv;
6709
6710 dv.major_version = DRV_VERSION_MAJOR;
6711 dv.minor_version = DRV_VERSION_MINOR;
6712 dv.build_version = DRV_VERSION_BUILD;
6713 dv.subbuild_version = 0;
35a7d804 6714 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6715 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6716}
6717
f650a38b 6718/**
4dda12e6 6719 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6720 * @pf: board private structure
bc7d338f 6721 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6722 **/
bc7d338f 6723static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6724{
f650a38b 6725 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6726 u8 set_fc_aq_fail = 0;
f650a38b 6727 i40e_status ret;
4f2f017c 6728 u32 val;
f650a38b
ASJ		 6729 u32 v;
6730
41c445ff
JB		 6731 /* Now we wait for GRST to settle out.
6732 * We don't have to delete the VEBs or VSIs from the hw switch
6733 * because the reset will make them disappear.
6734 */
6735 ret = i40e_pf_reset(hw);
b5565400 6736 if (ret) {
41c445ff 6737 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6738 set_bit(__I40E_RESET_FAILED, &pf->state);
6739 goto clear_recovery;
b5565400 6740 }
41c445ff
JB		 6741 pf->pfr_count++;
6742
6743 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6744 goto clear_recovery;
69bfb110 6745 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6746
6747 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6748 ret = i40e_init_adminq(&pf->hw);
6749 if (ret) {
f1c7e72e
SN		 6750 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6751 i40e_stat_str(&pf->hw, ret),
6752 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6753 goto clear_recovery;
41c445ff
JB		 6754 }
6755
4eb3f768 6756 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6757 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6758 i40e_verify_eeprom(pf);
4eb3f768 6759
e78ac4bf 6760 i40e_clear_pxe_mode(hw);
41c445ff 6761 ret = i40e_get_capabilities(pf);
f1c7e72e 6762 if (ret)
41c445ff 6763 goto end_core_reset;
41c445ff 6764
41c445ff
JB		 6765 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6766 hw->func_caps.num_rx_qp,
6767 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6768 if (ret) {
6769 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6770 goto end_core_reset;
6771 }
6772 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6773 if (ret) {
6774 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6775 goto end_core_reset;
6776 }
6777
4e3b35b0
NP		 6778#ifdef CONFIG_I40E_DCB
6779 ret = i40e_init_pf_dcb(pf);
6780 if (ret) {
aebfc816
SN		 6781 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6782 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6783 /* Continue without DCB enabled */
4e3b35b0
NP		 6784 }
6785#endif /* CONFIG_I40E_DCB */
38e00438 6786#ifdef I40E_FCOE
21364bcf 6787 i40e_init_pf_fcoe(pf);
4e3b35b0 6788
38e00438 6789#endif
41c445ff 6790 /* do basic switch setup */
bc7d338f 6791 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6792 if (ret)
6793 goto end_core_reset;
6794
7e2453fe
JB		 6795 /* driver is only interested in link up/down and module qualification
6796 * reports from firmware
6797 */
6798 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6799 I40E_AQ_EVENT_LINK_UPDOWN |
6800 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6801 if (ret)
f1c7e72e
SN		 6802 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6803 i40e_stat_str(&pf->hw, ret),
6804 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6805
cafa2ee6
ASJ		 6806 /* make sure our flow control settings are restored */
6807 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6808 if (ret)
8279e495
NP		 6809 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6810 i40e_stat_str(&pf->hw, ret),
6811 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6812
41c445ff
JB		 6813 /* Rebuild the VSIs and VEBs that existed before reset.
6814 * They are still in our local switch element arrays, so only
6815 * need to rebuild the switch model in the HW.
6816 *
6817 * If there were VEBs but the reconstitution failed, we'll try
6818 * try to recover minimal use by getting the basic PF VSI working.
6819 */
6820 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6821 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6822 /* find the one VEB connected to the MAC, and find orphans */
6823 for (v = 0; v < I40E_MAX_VEB; v++) {
6824 if (!pf->veb[v])
6825 continue;
6826
6827 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6828 pf->veb[v]->uplink_seid == 0) {
6829 ret = i40e_reconstitute_veb(pf->veb[v]);
6830
6831 if (!ret)
6832 continue;
6833
6834 /* If Main VEB failed, we're in deep doodoo,
6835 * so give up rebuilding the switch and set up
6836 * for minimal rebuild of PF VSI.
6837 * If orphan failed, we'll report the error
6838 * but try to keep going.
6839 */
6840 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6841 dev_info(&pf->pdev->dev,
6842 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6843 ret);
6844 pf->vsi[pf->lan_vsi]->uplink_seid
6845 = pf->mac_seid;
6846 break;
6847 } else if (pf->veb[v]->uplink_seid == 0) {
6848 dev_info(&pf->pdev->dev,
6849 "rebuild of orphan VEB failed: %d\n",
6850 ret);
6851 }
6852 }
6853 }
6854 }
6855
6856 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6857 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6858 /* no VEB, so rebuild only the Main VSI */
6859 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6860 if (ret) {
6861 dev_info(&pf->pdev->dev,
6862 "rebuild of Main VSI failed: %d\n", ret);
6863 goto end_core_reset;
6864 }
6865 }
6866
4f2f017c
ASJ		 6867 /* Reconfigure hardware for allowing smaller MSS in the case
6868 * of TSO, so that we avoid the MDD being fired and causing
6869 * a reset in the case of small MSS+TSO.
6870 */
6871#define I40E_REG_MSS 0x000E64DC
6872#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6873#define I40E_64BYTE_MSS 0x400000
6874 val = rd32(hw, I40E_REG_MSS);
6875 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6876 val &= ~I40E_REG_MSS_MIN_MASK;
6877 val |= I40E_64BYTE_MSS;
6878 wr32(hw, I40E_REG_MSS, val);
6879 }
6880
025b4a54
ASJ		 6881 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6882 (pf->hw.aq.fw_maj_ver < 4)) {
6883 msleep(75);
6884 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6885 if (ret)
f1c7e72e
SN		 6886 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6887 i40e_stat_str(&pf->hw, ret),
6888 i40e_aq_str(&pf->hw,
6889 pf->hw.aq.asq_last_status));
cafa2ee6 6890 }
41c445ff
JB		 6891 /* reinit the misc interrupt */
6892 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6893 ret = i40e_setup_misc_vector(pf);
6894
e7358f54
ASJ		 6895 /* Add a filter to drop all Flow control frames from any VSI from being
6896 * transmitted. By doing so we stop a malicious VF from sending out
6897 * PAUSE or PFC frames and potentially controlling traffic for other
6898 * PF/VF VSIs.
6899 * The FW can still send Flow control frames if enabled.
6900 */
6901 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6902 pf->main_vsi_seid);
6903
41c445ff
JB		 6904 /* restart the VSIs that were rebuilt and running before the reset */
6905 i40e_pf_unquiesce_all_vsi(pf);
6906
69f64b2b
MW		 6907 if (pf->num_alloc_vfs) {
6908 for (v = 0; v < pf->num_alloc_vfs; v++)
6909 i40e_reset_vf(&pf->vf[v], true);
6910 }
6911
41c445ff 6912 /* tell the firmware that we're starting */
44033fac 6913 i40e_send_version(pf);
41c445ff
JB		 6914
6915end_core_reset:
a316f651
ASJ		 6916 clear_bit(__I40E_RESET_FAILED, &pf->state);
6917clear_recovery:
41c445ff
JB		 6918 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6919}
6920
f650a38b 6921/**
b40c82e6 6922 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6923 * @pf: board private structure
6924 *
6925 * Close up the VFs and other things in prep for a Core Reset,
6926 * then get ready to rebuild the world.
6927 **/
6928static void i40e_handle_reset_warning(struct i40e_pf *pf)
6929{
23cfbe07
SN		 6930 i40e_prep_for_reset(pf);
6931 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6932}
6933
41c445ff
JB		 6934/**
6935 * i40e_handle_mdd_event
b40c82e6 6936 * @pf: pointer to the PF structure
41c445ff
JB		 6937 *
6938 * Called from the MDD irq handler to identify possibly malicious vfs
6939 **/
6940static void i40e_handle_mdd_event(struct i40e_pf *pf)
6941{
6942 struct i40e_hw *hw = &pf->hw;
6943 bool mdd_detected = false;
df430b12 6944 bool pf_mdd_detected = false;
41c445ff
JB		 6945 struct i40e_vf *vf;
6946 u32 reg;
6947 int i;
6948
6949 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6950 return;
6951
6952 /* find what triggered the MDD event */
6953 reg = rd32(hw, I40E_GL_MDET_TX);
6954 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6955 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6956 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6957 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6958 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6959 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6960 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6961 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6962 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6963 pf->hw.func_caps.base_queue;
faf32978 6964 if (netif_msg_tx_err(pf))
b40c82e6 6965 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6966 event, queue, pf_num, vf_num);
41c445ff
JB		 6967 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6968 mdd_detected = true;
6969 }
6970 reg = rd32(hw, I40E_GL_MDET_RX);
6971 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6972 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6973 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6974 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6975 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6976 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6977 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6978 pf->hw.func_caps.base_queue;
faf32978
JB		 6979 if (netif_msg_rx_err(pf))
6980 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6981 event, queue, func);
41c445ff
JB		 6982 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6983 mdd_detected = true;
6984 }
6985
df430b12
NP		 6986 if (mdd_detected) {
6987 reg = rd32(hw, I40E_PF_MDET_TX);
6988 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6989 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6990 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6991 pf_mdd_detected = true;
6992 }
6993 reg = rd32(hw, I40E_PF_MDET_RX);
6994 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6995 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6996 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6997 pf_mdd_detected = true;
6998 }
6999 /* Queue belongs to the PF, initiate a reset */
7000 if (pf_mdd_detected) {
7001 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7002 i40e_service_event_schedule(pf);
7003 }
7004 }
7005
41c445ff
JB		 7006 /* see if one of the VFs needs its hand slapped */
7007 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7008 vf = &(pf->vf[i]);
7009 reg = rd32(hw, I40E_VP_MDET_TX(i));
7010 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7011 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7012 vf->num_mdd_events++;
faf32978
JB		 7013 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7014 i);
41c445ff
JB		 7015 }
7016
7017 reg = rd32(hw, I40E_VP_MDET_RX(i));
7018 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7019 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7020 vf->num_mdd_events++;
faf32978
JB		 7021 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7022 i);
41c445ff
JB		 7023 }
7024
7025 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7026 dev_info(&pf->pdev->dev,
7027 "Too many MDD events on VF %d, disabled\n", i);
7028 dev_info(&pf->pdev->dev,
7029 "Use PF Control I/F to re-enable the VF\n");
7030 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7031 }
7032 }
7033
7034 /* re-enable mdd interrupt cause */
7035 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7036 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7037 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7038 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7039 i40e_flush(hw);
7040}
7041
a1c9a9d9 7042/**
6a899024 7043 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7044 * @pf: board private structure
7045 **/
6a899024 7046static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7047{
6a899024 7048#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9
JK		 7049 struct i40e_hw *hw = &pf->hw;
7050 i40e_status ret;
a1c9a9d9
JK		 7051 __be16 port;
7052 int i;
7053
6a899024 7054 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7055 return;
7056
6a899024 7057 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7058
7059 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7060 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7061 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7062 port = pf->udp_ports[i].index;
c22c06c8
SN		 7063 if (port)
7064 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7065 pf->udp_ports[i].type,
c22c06c8
SN		 7066 NULL, NULL);
7067 else
7068 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7069
7070 if (ret) {
c22c06c8 7071 dev_info(&pf->pdev->dev,
f1c7e72e 7072 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 7073 port ? "add" : "delete",
f1c7e72e
SN		 7074 ntohs(port), i,
7075 i40e_stat_str(&pf->hw, ret),
7076 i40e_aq_str(&pf->hw,
7077 pf->hw.aq.asq_last_status));
6a899024 7078 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7079 }
7080 }
7081 }
6a899024 7082#endif
a1c9a9d9
JK		 7083}
7084
41c445ff
JB		 7085/**
7086 * i40e_service_task - Run the driver's async subtasks
7087 * @work: pointer to work_struct containing our data
7088 **/
7089static void i40e_service_task(struct work_struct *work)
7090{
7091 struct i40e_pf *pf = container_of(work,
7092 struct i40e_pf,
7093 service_task);
7094 unsigned long start_time = jiffies;
7095
e57a2fea
SN		 7096 /* don't bother with service tasks if a reset is in progress */
7097 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7098 i40e_service_event_complete(pf);
7099 return;
7100 }
7101
b03a8c1f 7102 i40e_detect_recover_hung(pf);
41c445ff
JB		 7103 i40e_reset_subtask(pf);
7104 i40e_handle_mdd_event(pf);
7105 i40e_vc_process_vflr_event(pf);
7106 i40e_watchdog_subtask(pf);
7107 i40e_fdir_reinit_subtask(pf);
41c445ff 7108 i40e_sync_filters_subtask(pf);
6a899024
SA		 7109#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
7110 i40e_sync_udp_filters_subtask(pf);
a1c9a9d9 7111#endif
41c445ff
JB		 7112 i40e_clean_adminq_subtask(pf);
7113
7114 i40e_service_event_complete(pf);
7115
7116 /* If the tasks have taken longer than one timer cycle or there
7117 * is more work to be done, reschedule the service task now
7118 * rather than wait for the timer to tick again.
7119 */
7120 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7121 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7122 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7123 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7124 i40e_service_event_schedule(pf);
7125}
7126
7127/**
7128 * i40e_service_timer - timer callback
7129 * @data: pointer to PF struct
7130 **/
7131static void i40e_service_timer(unsigned long data)
7132{
7133 struct i40e_pf *pf = (struct i40e_pf *)data;
7134
7135 mod_timer(&pf->service_timer,
7136 round_jiffies(jiffies + pf->service_timer_period));
7137 i40e_service_event_schedule(pf);
7138}
7139
7140/**
7141 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7142 * @vsi: the VSI being configured
7143 **/
7144static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7145{
7146 struct i40e_pf *pf = vsi->back;
7147
7148 switch (vsi->type) {
7149 case I40E_VSI_MAIN:
7150 vsi->alloc_queue_pairs = pf->num_lan_qps;
7151 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7152 I40E_REQ_DESCRIPTOR_MULTIPLE);
7153 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7154 vsi->num_q_vectors = pf->num_lan_msix;
7155 else
7156 vsi->num_q_vectors = 1;
7157
7158 break;
7159
7160 case I40E_VSI_FDIR:
7161 vsi->alloc_queue_pairs = 1;
7162 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7163 I40E_REQ_DESCRIPTOR_MULTIPLE);
7164 vsi->num_q_vectors = 1;
7165 break;
7166
7167 case I40E_VSI_VMDQ2:
7168 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7169 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7170 I40E_REQ_DESCRIPTOR_MULTIPLE);
7171 vsi->num_q_vectors = pf->num_vmdq_msix;
7172 break;
7173
7174 case I40E_VSI_SRIOV:
7175 vsi->alloc_queue_pairs = pf->num_vf_qps;
7176 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7177 I40E_REQ_DESCRIPTOR_MULTIPLE);
7178 break;
7179
38e00438
VD		 7180#ifdef I40E_FCOE
7181 case I40E_VSI_FCOE:
7182 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7183 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7184 I40E_REQ_DESCRIPTOR_MULTIPLE);
7185 vsi->num_q_vectors = pf->num_fcoe_msix;
7186 break;
7187
7188#endif /* I40E_FCOE */
41c445ff
JB		 7189 default:
7190 WARN_ON(1);
7191 return -ENODATA;
7192 }
7193
7194 return 0;
7195}
7196
f650a38b
ASJ		 7197/**
7198 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7199 * @type: VSI pointer
bc7d338f 7200 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7201 *
7202 * On error: returns error code (negative)
7203 * On success: returns 0
7204 **/
bc7d338f 7205static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7206{
7207 int size;
7208 int ret = 0;
7209
ac6c5e3d 7210 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7211 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7212 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7213 if (!vsi->tx_rings)
7214 return -ENOMEM;
f650a38b
ASJ		 7215 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7216
bc7d338f
ASJ		 7217 if (alloc_qvectors) {
7218 /* allocate memory for q_vector pointers */
f57e4fbd 7219 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7220 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7221 if (!vsi->q_vectors) {
7222 ret = -ENOMEM;
7223 goto err_vectors;
7224 }
f650a38b
ASJ		 7225 }
7226 return ret;
7227
7228err_vectors:
7229 kfree(vsi->tx_rings);
7230 return ret;
7231}
7232
41c445ff
JB		 7233/**
7234 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7235 * @pf: board private structure
7236 * @type: type of VSI
7237 *
7238 * On error: returns error code (negative)
7239 * On success: returns vsi index in PF (positive)
7240 **/
7241static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7242{
7243 int ret = -ENODEV;
7244 struct i40e_vsi *vsi;
7245 int vsi_idx;
7246 int i;
7247
7248 /* Need to protect the allocation of the VSIs at the PF level */
7249 mutex_lock(&pf->switch_mutex);
7250
7251 /* VSI list may be fragmented if VSI creation/destruction has
7252 * been happening. We can afford to do a quick scan to look
7253 * for any free VSIs in the list.
7254 *
7255 * find next empty vsi slot, looping back around if necessary
7256 */
7257 i = pf->next_vsi;
505682cd 7258 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7259 i++;
505682cd 7260 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7261 i = 0;
7262 while (i < pf->next_vsi && pf->vsi[i])
7263 i++;
7264 }
7265
505682cd 7266 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7267 vsi_idx = i; /* Found one! */
7268 } else {
7269 ret = -ENODEV;
493fb300 7270 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7271 }
7272 pf->next_vsi = ++i;
7273
7274 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7275 if (!vsi) {
7276 ret = -ENOMEM;
493fb300 7277 goto unlock_pf;
41c445ff
JB		 7278 }
7279 vsi->type = type;
7280 vsi->back = pf;
7281 set_bit(__I40E_DOWN, &vsi->state);
7282 vsi->flags = 0;
7283 vsi->idx = vsi_idx;
7284 vsi->rx_itr_setting = pf->rx_itr_default;
7285 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7286 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7287 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7288 pf->rss_table_size : 64;
41c445ff
JB		 7289 vsi->netdev_registered = false;
7290 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7291 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7292 vsi->irqs_ready = false;
41c445ff 7293
9f65e15b
AD		 7294 ret = i40e_set_num_rings_in_vsi(vsi);
7295 if (ret)
7296 goto err_rings;
7297
bc7d338f 7298 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7299 if (ret)
9f65e15b 7300 goto err_rings;
493fb300 7301
41c445ff
JB		 7302 /* Setup default MSIX irq handler for VSI */
7303 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7304
21659035
KP		 7305 /* Initialize VSI lock */
7306 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7307 pf->vsi[vsi_idx] = vsi;
7308 ret = vsi_idx;
493fb300
AD		 7309 goto unlock_pf;
7310
9f65e15b 7311err_rings:
493fb300
AD		 7312 pf->next_vsi = i - 1;
7313 kfree(vsi);
7314unlock_pf:
41c445ff
JB		 7315 mutex_unlock(&pf->switch_mutex);
7316 return ret;
7317}
7318
f650a38b
ASJ		 7319/**
7320 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7321 * @type: VSI pointer
bc7d338f 7322 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7323 *
7324 * On error: returns error code (negative)
7325 * On success: returns 0
7326 **/
bc7d338f 7327static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7328{
7329 /* free the ring and vector containers */
bc7d338f
ASJ		 7330 if (free_qvectors) {
7331 kfree(vsi->q_vectors);
7332 vsi->q_vectors = NULL;
7333 }
f650a38b
ASJ		 7334 kfree(vsi->tx_rings);
7335 vsi->tx_rings = NULL;
7336 vsi->rx_rings = NULL;
7337}
7338
28c5869f
HZ		 7339/**
7340 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7341 * and lookup table
7342 * @vsi: Pointer to VSI structure
7343 */
7344static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7345{
7346 if (!vsi)
7347 return;
7348
7349 kfree(vsi->rss_hkey_user);
7350 vsi->rss_hkey_user = NULL;
7351
7352 kfree(vsi->rss_lut_user);
7353 vsi->rss_lut_user = NULL;
7354}
7355
41c445ff
JB		 7356/**
7357 * i40e_vsi_clear - Deallocate the VSI provided
7358 * @vsi: the VSI being un-configured
7359 **/
7360static int i40e_vsi_clear(struct i40e_vsi *vsi)
7361{
7362 struct i40e_pf *pf;
7363
7364 if (!vsi)
7365 return 0;
7366
7367 if (!vsi->back)
7368 goto free_vsi;
7369 pf = vsi->back;
7370
7371 mutex_lock(&pf->switch_mutex);
7372 if (!pf->vsi[vsi->idx]) {
7373 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7374 vsi->idx, vsi->idx, vsi, vsi->type);
7375 goto unlock_vsi;
7376 }
7377
7378 if (pf->vsi[vsi->idx] != vsi) {
7379 dev_err(&pf->pdev->dev,
7380 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7381 pf->vsi[vsi->idx]->idx,
7382 pf->vsi[vsi->idx],
7383 pf->vsi[vsi->idx]->type,
7384 vsi->idx, vsi, vsi->type);
7385 goto unlock_vsi;
7386 }
7387
b40c82e6 7388 /* updates the PF for this cleared vsi */
41c445ff
JB		 7389 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7390 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7391
bc7d338f 7392 i40e_vsi_free_arrays(vsi, true);
28c5869f 7393 i40e_clear_rss_config_user(vsi);
493fb300 7394
41c445ff
JB		 7395 pf->vsi[vsi->idx] = NULL;
7396 if (vsi->idx < pf->next_vsi)
7397 pf->next_vsi = vsi->idx;
7398
7399unlock_vsi:
7400 mutex_unlock(&pf->switch_mutex);
7401free_vsi:
7402 kfree(vsi);
7403
7404 return 0;
7405}
7406
9f65e15b
AD		 7407/**
7408 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7409 * @vsi: the VSI being cleaned
7410 **/
be1d5eea 7411static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7412{
7413 int i;
7414
8e9dca53 7415 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7416 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7417 kfree_rcu(vsi->tx_rings[i], rcu);
7418 vsi->tx_rings[i] = NULL;
7419 vsi->rx_rings[i] = NULL;
7420 }
be1d5eea 7421 }
9f65e15b
AD		 7422}
7423
41c445ff
JB		 7424/**
7425 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7426 * @vsi: the VSI being configured
7427 **/
7428static int i40e_alloc_rings(struct i40e_vsi *vsi)
7429{
e7046ee1 7430 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7431 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7432 int i;
7433
41c445ff 7434 /* Set basic values in the rings to be used later during open() */
d7397644 7435 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7436 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7437 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7438 if (!tx_ring)
7439 goto err_out;
41c445ff
JB		 7440
7441 tx_ring->queue_index = i;
7442 tx_ring->reg_idx = vsi->base_queue + i;
7443 tx_ring->ring_active = false;
7444 tx_ring->vsi = vsi;
7445 tx_ring->netdev = vsi->netdev;
7446 tx_ring->dev = &pf->pdev->dev;
7447 tx_ring->count = vsi->num_desc;
7448 tx_ring->size = 0;
7449 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7450 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7451 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7452 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7453 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7454 vsi->tx_rings[i] = tx_ring;
41c445ff 7455
9f65e15b 7456 rx_ring = &tx_ring[1];
41c445ff
JB		 7457 rx_ring->queue_index = i;
7458 rx_ring->reg_idx = vsi->base_queue + i;
7459 rx_ring->ring_active = false;
7460 rx_ring->vsi = vsi;
7461 rx_ring->netdev = vsi->netdev;
7462 rx_ring->dev = &pf->pdev->dev;
7463 rx_ring->count = vsi->num_desc;
7464 rx_ring->size = 0;
7465 rx_ring->dcb_tc = 0;
7466 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7467 set_ring_16byte_desc_enabled(rx_ring);
7468 else
7469 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7470 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7471 }
7472
7473 return 0;
9f65e15b
AD		 7474
7475err_out:
7476 i40e_vsi_clear_rings(vsi);
7477 return -ENOMEM;
41c445ff
JB		 7478}
7479
7480/**
7481 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7482 * @pf: board private structure
7483 * @vectors: the number of MSI-X vectors to request
7484 *
7485 * Returns the number of vectors reserved, or error
7486 **/
7487static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7488{
7b37f376
AG		 7489 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7490 I40E_MIN_MSIX, vectors);
7491 if (vectors < 0) {
41c445ff 7492 dev_info(&pf->pdev->dev,
7b37f376 7493 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7494 vectors = 0;
7495 }
7496
7497 return vectors;
7498}
7499
7500/**
7501 * i40e_init_msix - Setup the MSIX capability
7502 * @pf: board private structure
7503 *
7504 * Work with the OS to set up the MSIX vectors needed.
7505 *
3b444399 7506 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7507 **/
7508static int i40e_init_msix(struct i40e_pf *pf)
7509{
41c445ff 7510 struct i40e_hw *hw = &pf->hw;
1e200e4a 7511 int vectors_left;
41c445ff 7512 int v_budget, i;
3b444399 7513 int v_actual;
41c445ff
JB		 7514
7515 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7516 return -ENODEV;
7517
7518 /* The number of vectors we'll request will be comprised of:
7519 * - Add 1 for "other" cause for Admin Queue events, etc.
7520 * - The number of LAN queue pairs
f8ff1464
ASJ		 7521 * - Queues being used for RSS.
7522 * We don't need as many as max_rss_size vectors.
7523 * use rss_size instead in the calculation since that
7524 * is governed by number of cpus in the system.
7525 * - assumes symmetric Tx/Rx pairing
41c445ff 7526 * - The number of VMDq pairs
38e00438
VD		 7527#ifdef I40E_FCOE
7528 * - The number of FCOE qps.
7529#endif
41c445ff
JB		 7530 * Once we count this up, try the request.
7531 *
7532 * If we can't get what we want, we'll simplify to nearly nothing
7533 * and try again. If that still fails, we punt.
7534 */
1e200e4a
SN		 7535 vectors_left = hw->func_caps.num_msix_vectors;
7536 v_budget = 0;
7537
7538 /* reserve one vector for miscellaneous handler */
7539 if (vectors_left) {
7540 v_budget++;
7541 vectors_left--;
7542 }
7543
7544 /* reserve vectors for the main PF traffic queues */
7545 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7546 vectors_left -= pf->num_lan_msix;
7547 v_budget += pf->num_lan_msix;
7548
7549 /* reserve one vector for sideband flow director */
7550 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7551 if (vectors_left) {
7552 v_budget++;
7553 vectors_left--;
7554 } else {
7555 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7556 }
7557 }
83840e4b 7558
38e00438 7559#ifdef I40E_FCOE
1e200e4a 7560 /* can we reserve enough for FCoE? */
38e00438 7561 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7562 if (!vectors_left)
7563 pf->num_fcoe_msix = 0;
7564 else if (vectors_left >= pf->num_fcoe_qps)
7565 pf->num_fcoe_msix = pf->num_fcoe_qps;
7566 else
7567 pf->num_fcoe_msix = 1;
38e00438 7568 v_budget += pf->num_fcoe_msix;
1e200e4a 7569 vectors_left -= pf->num_fcoe_msix;
38e00438 7570 }
1e200e4a 7571
38e00438 7572#endif
1e200e4a
SN		 7573 /* any vectors left over go for VMDq support */
7574 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7575 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7576 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7577
7578 /* if we're short on vectors for what's desired, we limit
7579 * the queues per vmdq. If this is still more than are
7580 * available, the user will need to change the number of
7581 * queues/vectors used by the PF later with the ethtool
7582 * channels command
7583 */
7584 if (vmdq_vecs < vmdq_vecs_wanted)
7585 pf->num_vmdq_qps = 1;
7586 pf->num_vmdq_msix = pf->num_vmdq_qps;
7587
7588 v_budget += vmdq_vecs;
7589 vectors_left -= vmdq_vecs;
7590 }
41c445ff
JB		 7591
7592 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7593 GFP_KERNEL);
7594 if (!pf->msix_entries)
7595 return -ENOMEM;
7596
7597 for (i = 0; i < v_budget; i++)
7598 pf->msix_entries[i].entry = i;
3b444399 7599 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7600
3b444399 7601 if (v_actual != v_budget) {
a34977ba
ASJ		 7602 /* If we have limited resources, we will start with no vectors
7603 * for the special features and then allocate vectors to some
7604 * of these features based on the policy and at the end disable
7605 * the features that did not get any vectors.
7606 */
38e00438
VD		 7607#ifdef I40E_FCOE
7608 pf->num_fcoe_qps = 0;
7609 pf->num_fcoe_msix = 0;
7610#endif
a34977ba
ASJ		 7611 pf->num_vmdq_msix = 0;
7612 }
7613
3b444399 7614 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7615 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7616 kfree(pf->msix_entries);
7617 pf->msix_entries = NULL;
7618 return -ENODEV;
7619
3b444399 7620 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7621 /* Adjust for minimal MSIX use */
41c445ff
JB		 7622 pf->num_vmdq_vsis = 0;
7623 pf->num_vmdq_qps = 0;
41c445ff
JB		 7624 pf->num_lan_qps = 1;
7625 pf->num_lan_msix = 1;
7626
3b444399
SN		 7627 } else if (v_actual != v_budget) {
7628 int vec;
7629
a34977ba 7630 /* reserve the misc vector */
3b444399 7631 vec = v_actual - 1;
a34977ba 7632
41c445ff
JB		 7633 /* Scale vector usage down */
7634 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7635 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7636 pf->num_vmdq_qps = 1;
7637 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7638
7639 /* partition out the remaining vectors */
7640 switch (vec) {
7641 case 2:
41c445ff
JB		 7642 pf->num_lan_msix = 1;
7643 break;
7644 case 3:
38e00438
VD		 7645#ifdef I40E_FCOE
7646 /* give one vector to FCoE */
7647 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7648 pf->num_lan_msix = 1;
7649 pf->num_fcoe_msix = 1;
7650 }
7651#else
41c445ff 7652 pf->num_lan_msix = 2;
38e00438 7653#endif
41c445ff
JB		 7654 break;
7655 default:
38e00438
VD		 7656#ifdef I40E_FCOE
7657 /* give one vector to FCoE */
7658 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7659 pf->num_fcoe_msix = 1;
7660 vec--;
7661 }
7662#endif
1e200e4a
SN		 7663 /* give the rest to the PF */
7664 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7665 break;
7666 }
7667 }
7668
a34977ba
ASJ		 7669 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7670 (pf->num_vmdq_msix == 0)) {
7671 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7672 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7673 }
38e00438
VD		 7674#ifdef I40E_FCOE
7675
7676 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7677 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7678 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7679 }
7680#endif
3b444399 7681 return v_actual;
41c445ff
JB		 7682}
7683
493fb300 7684/**
90e04070 7685 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7686 * @vsi: the VSI being configured
7687 * @v_idx: index of the vector in the vsi struct
7688 *
7689 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7690 **/
90e04070 7691static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7692{
7693 struct i40e_q_vector *q_vector;
7694
7695 /* allocate q_vector */
7696 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7697 if (!q_vector)
7698 return -ENOMEM;
7699
7700 q_vector->vsi = vsi;
7701 q_vector->v_idx = v_idx;
7702 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7703 if (vsi->netdev)
7704 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7705 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7706
cd0b6fa6
AD		 7707 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7708 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7709
493fb300
AD		 7710 /* tie q_vector and vsi together */
7711 vsi->q_vectors[v_idx] = q_vector;
7712
7713 return 0;
7714}
7715
41c445ff 7716/**
90e04070 7717 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7718 * @vsi: the VSI being configured
7719 *
7720 * We allocate one q_vector per queue interrupt. If allocation fails we
7721 * return -ENOMEM.
7722 **/
90e04070 7723static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7724{
7725 struct i40e_pf *pf = vsi->back;
7726 int v_idx, num_q_vectors;
493fb300 7727 int err;
41c445ff
JB		 7728
7729 /* if not MSIX, give the one vector only to the LAN VSI */
7730 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7731 num_q_vectors = vsi->num_q_vectors;
7732 else if (vsi == pf->vsi[pf->lan_vsi])
7733 num_q_vectors = 1;
7734 else
7735 return -EINVAL;
7736
41c445ff 7737 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7738 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7739 if (err)
7740 goto err_out;
41c445ff
JB		 7741 }
7742
7743 return 0;
493fb300
AD		 7744
7745err_out:
7746 while (v_idx--)
7747 i40e_free_q_vector(vsi, v_idx);
7748
7749 return err;
41c445ff
JB		 7750}
7751
7752/**
7753 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7754 * @pf: board private structure to initialize
7755 **/
c1147280 7756static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7757{
3b444399
SN		 7758 int vectors = 0;
7759 ssize_t size;
41c445ff
JB		 7760
7761 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7762 vectors = i40e_init_msix(pf);
7763 if (vectors < 0) {
60ea5f83 7764 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7765#ifdef I40E_FCOE
7766 I40E_FLAG_FCOE_ENABLED |
7767#endif
60ea5f83 7768 I40E_FLAG_RSS_ENABLED |
4d9b6043 7769 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7770 I40E_FLAG_SRIOV_ENABLED |
7771 I40E_FLAG_FD_SB_ENABLED |
7772 I40E_FLAG_FD_ATR_ENABLED |
7773 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7774
7775 /* rework the queue expectations without MSIX */
7776 i40e_determine_queue_usage(pf);
7777 }
7778 }
7779
7780 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7781 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7782 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7783 vectors = pci_enable_msi(pf->pdev);
7784 if (vectors < 0) {
7785 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7786 vectors);
41c445ff
JB		 7787 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7788 }
3b444399 7789 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7790 }
7791
958a3e3b 7792 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7793 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7794
3b444399
SN		 7795 /* set up vector assignment tracking */
7796 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7797 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7798 if (!pf->irq_pile) {
7799 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7800 return -ENOMEM;
7801 }
3b444399
SN		 7802 pf->irq_pile->num_entries = vectors;
7803 pf->irq_pile->search_hint = 0;
7804
c1147280 7805 /* track first vector for misc interrupts, ignore return */
3b444399 7806 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7807
7808 return 0;
41c445ff
JB		 7809}
7810
7811/**
7812 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7813 * @pf: board private structure
7814 *
7815 * This sets up the handler for MSIX 0, which is used to manage the
7816 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7817 * when in MSI or Legacy interrupt mode.
7818 **/
7819static int i40e_setup_misc_vector(struct i40e_pf *pf)
7820{
7821 struct i40e_hw *hw = &pf->hw;
7822 int err = 0;
7823
7824 /* Only request the irq if this is the first time through, and
7825 * not when we're rebuilding after a Reset
7826 */
7827 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7828 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7829 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7830 if (err) {
7831 dev_info(&pf->pdev->dev,
77fa28be 7832 "request_irq for %s failed: %d\n",
b294ac70 7833 pf->int_name, err);
41c445ff
JB		 7834 return -EFAULT;
7835 }
7836 }
7837
ab437b5a 7838 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7839
7840 /* associate no queues to the misc vector */
7841 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7842 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7843
7844 i40e_flush(hw);
7845
7846 i40e_irq_dynamic_enable_icr0(pf);
7847
7848 return err;
7849}
7850
7851/**
e25d00b8
ASJ		 7852 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7853 * @vsi: vsi structure
7854 * @seed: RSS hash seed
7855 **/
e69ff813
HZ		 7856static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7857 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7858{
7859 struct i40e_aqc_get_set_rss_key_data rss_key;
7860 struct i40e_pf *pf = vsi->back;
7861 struct i40e_hw *hw = &pf->hw;
7862 bool pf_lut = false;
7863 u8 *rss_lut;
7864 int ret, i;
7865
7866 memset(&rss_key, 0, sizeof(rss_key));
7867 memcpy(&rss_key, seed, sizeof(rss_key));
7868
7869 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7870 if (!rss_lut)
7871 return -ENOMEM;
7872
7873 /* Populate the LUT with max no. of queues in round robin fashion */
7874 for (i = 0; i < vsi->rss_table_size; i++)
7875 rss_lut[i] = i % vsi->rss_size;
7876
7877 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7878 if (ret) {
7879 dev_info(&pf->pdev->dev,
7880 "Cannot set RSS key, err %s aq_err %s\n",
7881 i40e_stat_str(&pf->hw, ret),
7882 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7883 goto config_rss_aq_out;
e25d00b8
ASJ		 7884 }
7885
7886 if (vsi->type == I40E_VSI_MAIN)
7887 pf_lut = true;
7888
7889 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7890 vsi->rss_table_size);
7891 if (ret)
7892 dev_info(&pf->pdev->dev,
7893 "Cannot set RSS lut, err %s aq_err %s\n",
7894 i40e_stat_str(&pf->hw, ret),
7895 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7896
126b63d9
AS		 7897config_rss_aq_out:
7898 kfree(rss_lut);
e25d00b8
ASJ		 7899 return ret;
7900}
7901
7902/**
7903 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7904 * @vsi: VSI structure
7905 **/
7906static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7907{
7908 u8 seed[I40E_HKEY_ARRAY_SIZE];
7909 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7910 u8 *lut;
7911 int ret;
7912
7913 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7914 return 0;
7915
7916 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7917 if (!lut)
7918 return -ENOMEM;
e25d00b8 7919
e69ff813 7920 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7921 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7922 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7923 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7924 kfree(lut);
e25d00b8 7925
e69ff813 7926 return ret;
e25d00b8
ASJ		 7927}
7928
7929/**
043dd650 7930 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 7931 * @vsi: Pointer to vsi structure
e25d00b8 7932 * @seed: RSS hash seed
e69ff813
HZ		 7933 * @lut: Lookup table
7934 * @lut_size: Lookup table size
7935 *
7936 * Returns 0 on success, negative on failure
41c445ff 7937 **/
e69ff813
HZ		 7938static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
7939 const u8 *lut, u16 lut_size)
41c445ff 7940{
e69ff813 7941 struct i40e_pf *pf = vsi->back;
4617e8c0 7942 struct i40e_hw *hw = &pf->hw;
e69ff813 7943 u8 i;
41c445ff 7944
e25d00b8 7945 /* Fill out hash function seed */
e69ff813
HZ		 7946 if (seed) {
7947 u32 *seed_dw = (u32 *)seed;
7948
7949 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7950 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7951 }
7952
7953 if (lut) {
7954 u32 *lut_dw = (u32 *)lut;
7955
7956 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7957 return -EINVAL;
7958
7959 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7960 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
e25d00b8
ASJ		 7961 }
7962 i40e_flush(hw);
7963
7964 return 0;
7965}
7966
043dd650
HZ		 7967/**
7968 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
7969 * @vsi: Pointer to VSI structure
7970 * @seed: Buffer to store the keys
7971 * @lut: Buffer to store the lookup table entries
7972 * @lut_size: Size of buffer to store the lookup table entries
7973 *
7974 * Returns 0 on success, negative on failure
7975 */
7976static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
7977 u8 *lut, u16 lut_size)
7978{
7979 struct i40e_pf *pf = vsi->back;
7980 struct i40e_hw *hw = &pf->hw;
7981 u16 i;
7982
7983 if (seed) {
7984 u32 *seed_dw = (u32 *)seed;
7985
7986 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7987 seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
7988 }
7989 if (lut) {
7990 u32 *lut_dw = (u32 *)lut;
7991
7992 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7993 return -EINVAL;
7994 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7995 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
7996 }
7997
7998 return 0;
7999}
8000
8001/**
8002 * i40e_config_rss - Configure RSS keys and lut
8003 * @vsi: Pointer to VSI structure
8004 * @seed: RSS hash seed
8005 * @lut: Lookup table
8006 * @lut_size: Lookup table size
8007 *
8008 * Returns 0 on success, negative on failure
8009 */
8010int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8011{
8012 struct i40e_pf *pf = vsi->back;
8013
8014 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8015 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8016 else
8017 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8018}
8019
8020/**
8021 * i40e_get_rss - Get RSS keys and lut
8022 * @vsi: Pointer to VSI structure
8023 * @seed: Buffer to store the keys
8024 * @lut: Buffer to store the lookup table entries
8025 * lut_size: Size of buffer to store the lookup table entries
8026 *
8027 * Returns 0 on success, negative on failure
8028 */
8029int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8030{
8031 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
8032}
8033
e69ff813
HZ		 8034/**
8035 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8036 * @pf: Pointer to board private structure
8037 * @lut: Lookup table
8038 * @rss_table_size: Lookup table size
8039 * @rss_size: Range of queue number for hashing
8040 */
8041static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8042 u16 rss_table_size, u16 rss_size)
8043{
8044 u16 i;
8045
8046 for (i = 0; i < rss_table_size; i++)
8047 lut[i] = i % rss_size;
8048}
8049
e25d00b8 8050/**
043dd650 8051 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8052 * @pf: board private structure
8053 **/
043dd650 8054static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8055{
8056 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8057 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8058 u8 *lut;
e25d00b8
ASJ		 8059 struct i40e_hw *hw = &pf->hw;
8060 u32 reg_val;
8061 u64 hena;
e69ff813 8062 int ret;
e25d00b8 8063
41c445ff
JB		 8064 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
8065 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
8066 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8067 hena |= i40e_pf_get_default_rss_hena(pf);
8068
41c445ff
JB		 8069 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
8070 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
8071
e25d00b8 8072 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 8073 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8074 reg_val = (pf->rss_table_size == 512) ?
8075 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8076 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 8077 wr32(hw, I40E_PFQF_CTL_0, reg_val);
8078
28c5869f
HZ		 8079 /* Determine the RSS size of the VSI */
8080 if (!vsi->rss_size)
acd65448
HZ		 8081 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8082 vsi->num_queue_pairs);
28c5869f 8083
e69ff813
HZ		 8084 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8085 if (!lut)
8086 return -ENOMEM;
8087
28c5869f
HZ		 8088 /* Use user configured lut if there is one, otherwise use default */
8089 if (vsi->rss_lut_user)
8090 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8091 else
8092 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8093
28c5869f
HZ		 8094 /* Use user configured hash key if there is one, otherwise
8095 * use default.
8096 */
8097 if (vsi->rss_hkey_user)
8098 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8099 else
8100 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8101 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8102 kfree(lut);
8103
8104 return ret;
41c445ff
JB		 8105}
8106
f8ff1464
ASJ		 8107/**
8108 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8109 * @pf: board private structure
8110 * @queue_count: the requested queue count for rss.
8111 *
8112 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8113 * count which may be different from the requested queue count.
8114 **/
8115int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8116{
9a3bd2f1
ASJ		 8117 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8118 int new_rss_size;
8119
f8ff1464
ASJ		 8120 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8121 return 0;
8122
9a3bd2f1 8123 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8124
9a3bd2f1
ASJ		 8125 if (queue_count != vsi->num_queue_pairs) {
8126 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8127 i40e_prep_for_reset(pf);
8128
acd65448 8129 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8130
8131 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8132
8133 /* Discard the user configured hash keys and lut, if less
8134 * queues are enabled.
8135 */
8136 if (queue_count < vsi->rss_size) {
8137 i40e_clear_rss_config_user(vsi);
8138 dev_dbg(&pf->pdev->dev,
8139 "discard user configured hash keys and lut\n");
8140 }
8141
8142 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8143 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8144 vsi->num_queue_pairs);
28c5869f 8145
043dd650 8146 i40e_pf_config_rss(pf);
f8ff1464 8147 }
e36b0b11
HZ		 8148 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8149 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8150 return pf->alloc_rss_size;
f8ff1464
ASJ		 8151}
8152
f4492db1
GR		 8153/**
8154 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8155 * @pf: board private structure
8156 **/
8157i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8158{
8159 i40e_status status;
8160 bool min_valid, max_valid;
8161 u32 max_bw, min_bw;
8162
8163 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8164 &min_valid, &max_valid);
8165
8166 if (!status) {
8167 if (min_valid)
8168 pf->npar_min_bw = min_bw;
8169 if (max_valid)
8170 pf->npar_max_bw = max_bw;
8171 }
8172
8173 return status;
8174}
8175
8176/**
8177 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8178 * @pf: board private structure
8179 **/
8180i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8181{
8182 struct i40e_aqc_configure_partition_bw_data bw_data;
8183 i40e_status status;
8184
b40c82e6 8185 /* Set the valid bit for this PF */
41a1d04b 8186 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8187 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8188 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8189
8190 /* Set the new bandwidths */
8191 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8192
8193 return status;
8194}
8195
8196/**
8197 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8198 * @pf: board private structure
8199 **/
8200i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8201{
8202 /* Commit temporary BW setting to permanent NVM image */
8203 enum i40e_admin_queue_err last_aq_status;
8204 i40e_status ret;
8205 u16 nvm_word;
8206
8207 if (pf->hw.partition_id != 1) {
8208 dev_info(&pf->pdev->dev,
8209 "Commit BW only works on partition 1! This is partition %d",
8210 pf->hw.partition_id);
8211 ret = I40E_NOT_SUPPORTED;
8212 goto bw_commit_out;
8213 }
8214
8215 /* Acquire NVM for read access */
8216 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8217 last_aq_status = pf->hw.aq.asq_last_status;
8218 if (ret) {
8219 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8220 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8221 i40e_stat_str(&pf->hw, ret),
8222 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8223 goto bw_commit_out;
8224 }
8225
8226 /* Read word 0x10 of NVM - SW compatibility word 1 */
8227 ret = i40e_aq_read_nvm(&pf->hw,
8228 I40E_SR_NVM_CONTROL_WORD,
8229 0x10, sizeof(nvm_word), &nvm_word,
8230 false, NULL);
8231 /* Save off last admin queue command status before releasing
8232 * the NVM
8233 */
8234 last_aq_status = pf->hw.aq.asq_last_status;
8235 i40e_release_nvm(&pf->hw);
8236 if (ret) {
f1c7e72e
SN		 8237 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8238 i40e_stat_str(&pf->hw, ret),
8239 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8240 goto bw_commit_out;
8241 }
8242
8243 /* Wait a bit for NVM release to complete */
8244 msleep(50);
8245
8246 /* Acquire NVM for write access */
8247 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8248 last_aq_status = pf->hw.aq.asq_last_status;
8249 if (ret) {
8250 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8251 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8252 i40e_stat_str(&pf->hw, ret),
8253 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8254 goto bw_commit_out;
8255 }
8256 /* Write it back out unchanged to initiate update NVM,
8257 * which will force a write of the shadow (alt) RAM to
8258 * the NVM - thus storing the bandwidth values permanently.
8259 */
8260 ret = i40e_aq_update_nvm(&pf->hw,
8261 I40E_SR_NVM_CONTROL_WORD,
8262 0x10, sizeof(nvm_word),
8263 &nvm_word, true, NULL);
8264 /* Save off last admin queue command status before releasing
8265 * the NVM
8266 */
8267 last_aq_status = pf->hw.aq.asq_last_status;
8268 i40e_release_nvm(&pf->hw);
8269 if (ret)
8270 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8271 "BW settings NOT SAVED, err %s aq_err %s\n",
8272 i40e_stat_str(&pf->hw, ret),
8273 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8274bw_commit_out:
8275
8276 return ret;
8277}
8278
41c445ff
JB		 8279/**
8280 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8281 * @pf: board private structure to initialize
8282 *
8283 * i40e_sw_init initializes the Adapter private data structure.
8284 * Fields are initialized based on PCI device information and
8285 * OS network device settings (MTU size).
8286 **/
8287static int i40e_sw_init(struct i40e_pf *pf)
8288{
8289 int err = 0;
8290 int size;
8291
8292 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8293 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 8294 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 8295 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8296 if (I40E_DEBUG_USER & debug)
8297 pf->hw.debug_mask = debug;
8298 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8299 I40E_DEFAULT_MSG_ENABLE);
8300 }
8301
8302 /* Set default capability flags */
8303 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8304 I40E_FLAG_MSI_ENABLED |
9ac77266 8305 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 8306 I40E_FLAG_MSIX_ENABLED;
8307
8308 if (iommu_present(&pci_bus_type))
8309 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8310 else
8311 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8312
ca99eb99
MW		 8313 /* Set default ITR */
8314 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8315 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8316
7134f9ce
JB		 8317 /* Depending on PF configurations, it is possible that the RSS
8318 * maximum might end up larger than the available queues
8319 */
41a1d04b 8320 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8321 pf->alloc_rss_size = 1;
5db4cb59 8322 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8323 pf->rss_size_max = min_t(int, pf->rss_size_max,
8324 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8325 if (pf->hw.func_caps.rss) {
8326 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8327 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8328 num_online_cpus());
41c445ff
JB		 8329 }
8330
2050bc65 8331 /* MFP mode enabled */
c78b953e 8332 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8333 pf->flags |= I40E_FLAG_MFP_ENABLED;
8334 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8335 if (i40e_get_npar_bw_setting(pf))
8336 dev_warn(&pf->pdev->dev,
8337 "Could not get NPAR bw settings\n");
8338 else
8339 dev_info(&pf->pdev->dev,
8340 "Min BW = %8.8x, Max BW = %8.8x\n",
8341 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8342 }
8343
cbf61325
ASJ		 8344 /* FW/NVM is not yet fixed in this regard */
8345 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8346 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8347 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8348 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8349 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8350 pf->hw.num_partitions > 1)
cbf61325 8351 dev_info(&pf->pdev->dev,
0b67584f 8352 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8353 else
8354 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8355 pf->fdir_pf_filter_count =
8356 pf->hw.func_caps.fd_filters_guaranteed;
8357 pf->hw.fdir_shared_filter_count =
8358 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8359 }
8360
8361 if (pf->hw.func_caps.vmdq) {
41c445ff 8362 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8363 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8364 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8365 }
8366
38e00438 8367#ifdef I40E_FCOE
21364bcf 8368 i40e_init_pf_fcoe(pf);
38e00438
VD		 8369
8370#endif /* I40E_FCOE */
41c445ff 8371#ifdef CONFIG_PCI_IOV
ba252f13 8372 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8373 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8374 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8375 pf->num_req_vfs = min_t(int,
8376 pf->hw.func_caps.num_vfs,
8377 I40E_MAX_VF_COUNT);
8378 }
8379#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8380 if (pf->hw.mac.type == I40E_MAC_X722) {
8381 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8382 I40E_FLAG_128_QP_RSS_CAPABLE |
8383 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8384 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8385 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024
SA		 8386 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
8387 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
d502ce01 8388 }
41c445ff
JB		 8389 pf->eeprom_version = 0xDEAD;
8390 pf->lan_veb = I40E_NO_VEB;
8391 pf->lan_vsi = I40E_NO_VSI;
8392
d1a8d275
ASJ		 8393 /* By default FW has this off for performance reasons */
8394 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8395
41c445ff
JB		 8396 /* set up queue assignment tracking */
8397 size = sizeof(struct i40e_lump_tracking)
8398 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8399 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8400 if (!pf->qp_pile) {
8401 err = -ENOMEM;
8402 goto sw_init_done;
8403 }
8404 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8405 pf->qp_pile->search_hint = 0;
8406
327fe04b
ASJ		 8407 pf->tx_timeout_recovery_level = 1;
8408
41c445ff
JB		 8409 mutex_init(&pf->switch_mutex);
8410
c668a12c
GR		 8411 /* If NPAR is enabled nudge the Tx scheduler */
8412 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8413 i40e_set_npar_bw_setting(pf);
8414
41c445ff
JB		 8415sw_init_done:
8416 return err;
8417}
8418
7c3c288b
ASJ		 8419/**
8420 * i40e_set_ntuple - set the ntuple feature flag and take action
8421 * @pf: board private structure to initialize
8422 * @features: the feature set that the stack is suggesting
8423 *
8424 * returns a bool to indicate if reset needs to happen
8425 **/
8426bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8427{
8428 bool need_reset = false;
8429
8430 /* Check if Flow Director n-tuple support was enabled or disabled. If
8431 * the state changed, we need to reset.
8432 */
8433 if (features & NETIF_F_NTUPLE) {
8434 /* Enable filters and mark for reset */
8435 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8436 need_reset = true;
8437 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8438 } else {
8439 /* turn off filters, mark for reset and clear SW filter list */
8440 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8441 need_reset = true;
8442 i40e_fdir_filter_exit(pf);
8443 }
8444 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8445 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8446 /* reset fd counters */
8447 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8448 pf->fdir_pf_active_filters = 0;
8449 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8450 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8451 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8452 /* if ATR was auto disabled it can be re-enabled. */
8453 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8454 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8455 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8456 }
8457 return need_reset;
8458}
8459
41c445ff
JB		 8460/**
8461 * i40e_set_features - set the netdev feature flags
8462 * @netdev: ptr to the netdev being adjusted
8463 * @features: the feature set that the stack is suggesting
8464 **/
8465static int i40e_set_features(struct net_device *netdev,
8466 netdev_features_t features)
8467{
8468 struct i40e_netdev_priv *np = netdev_priv(netdev);
8469 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8470 struct i40e_pf *pf = vsi->back;
8471 bool need_reset;
41c445ff
JB		 8472
8473 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8474 i40e_vlan_stripping_enable(vsi);
8475 else
8476 i40e_vlan_stripping_disable(vsi);
8477
7c3c288b
ASJ		 8478 need_reset = i40e_set_ntuple(pf, features);
8479
8480 if (need_reset)
41a1d04b 8481 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8482
41c445ff
JB		 8483 return 0;
8484}
8485
6a899024 8486#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9 8487/**
6a899024 8488 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8489 * @pf: board private structure
8490 * @port: The UDP port to look up
8491 *
8492 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8493 **/
6a899024 8494static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8495{
8496 u8 i;
8497
8498 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8499 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8500 return i;
8501 }
8502
8503 return i;
8504}
8505
6a899024 8506#endif
a1c9a9d9
JK		 8507/**
8508 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8509 * @netdev: This physical port's netdev
8510 * @sa_family: Socket Family that VXLAN is notifying us about
8511 * @port: New UDP port number that VXLAN started listening to
8512 **/
8513static void i40e_add_vxlan_port(struct net_device *netdev,
8514 sa_family_t sa_family, __be16 port)
8515{
6a899024 8516#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8517 struct i40e_netdev_priv *np = netdev_priv(netdev);
8518 struct i40e_vsi *vsi = np->vsi;
8519 struct i40e_pf *pf = vsi->back;
8520 u8 next_idx;
8521 u8 idx;
8522
8523 if (sa_family == AF_INET6)
8524 return;
8525
6a899024 8526 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8527
8528 /* Check if port already exists */
8529 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8530 netdev_info(netdev, "vxlan port %d already offloaded\n",
8531 ntohs(port));
a1c9a9d9
JK		 8532 return;
8533 }
8534
8535 /* Now check if there is space to add the new port */
6a899024 8536 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8537
8538 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8539 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8540 ntohs(port));
8541 return;
8542 }
8543
8544 /* New port: add it and mark its index in the bitmap */
6a899024
SA		 8545 pf->udp_ports[next_idx].index = port;
8546 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8547 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8548 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8549#endif
a1c9a9d9
JK		 8550}
8551
8552/**
8553 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8554 * @netdev: This physical port's netdev
8555 * @sa_family: Socket Family that VXLAN is notifying us about
8556 * @port: UDP port number that VXLAN stopped listening to
8557 **/
8558static void i40e_del_vxlan_port(struct net_device *netdev,
8559 sa_family_t sa_family, __be16 port)
8560{
6a899024 8561#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8562 struct i40e_netdev_priv *np = netdev_priv(netdev);
8563 struct i40e_vsi *vsi = np->vsi;
8564 struct i40e_pf *pf = vsi->back;
8565 u8 idx;
8566
8567 if (sa_family == AF_INET6)
8568 return;
8569
6a899024 8570 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8571
8572 /* Check if port already exists */
8573 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8574 /* if port exists, set it to 0 (mark for deletion)
8575 * and make it pending
8576 */
6a899024
SA		 8577 pf->udp_ports[idx].index = 0;
8578 pf->pending_udp_bitmap |= BIT_ULL(idx);
8579 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9 8580 } else {
c22c06c8 8581 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8582 ntohs(port));
8583 }
6a899024
SA		 8584#endif
8585}
8586
8587/**
8588 * i40e_add_geneve_port - Get notifications about GENEVE ports that come up
8589 * @netdev: This physical port's netdev
8590 * @sa_family: Socket Family that GENEVE is notifying us about
8591 * @port: New UDP port number that GENEVE started listening to
8592 **/
8593static void i40e_add_geneve_port(struct net_device *netdev,
8594 sa_family_t sa_family, __be16 port)
8595{
8596#if IS_ENABLED(CONFIG_GENEVE)
8597 struct i40e_netdev_priv *np = netdev_priv(netdev);
8598 struct i40e_vsi *vsi = np->vsi;
8599 struct i40e_pf *pf = vsi->back;
8600 u8 next_idx;
8601 u8 idx;
8602
8603 if (sa_family == AF_INET6)
8604 return;
8605
8606 idx = i40e_get_udp_port_idx(pf, port);
8607
8608 /* Check if port already exists */
8609 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8610 netdev_info(netdev, "udp port %d already offloaded\n",
8611 ntohs(port));
8612 return;
8613 }
8614
8615 /* Now check if there is space to add the new port */
8616 next_idx = i40e_get_udp_port_idx(pf, 0);
8617
8618 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8619 netdev_info(netdev, "maximum number of UDP ports reached, not adding port %d\n",
8620 ntohs(port));
8621 return;
8622 }
8623
8624 /* New port: add it and mark its index in the bitmap */
8625 pf->udp_ports[next_idx].index = port;
8626 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8627 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8628 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8629
8630 dev_info(&pf->pdev->dev, "adding geneve port %d\n", ntohs(port));
8631#endif
a1c9a9d9
JK		 8632}
8633
6a899024
SA		 8634/**
8635 * i40e_del_geneve_port - Get notifications about GENEVE ports that go away
8636 * @netdev: This physical port's netdev
8637 * @sa_family: Socket Family that GENEVE is notifying us about
8638 * @port: UDP port number that GENEVE stopped listening to
8639 **/
8640static void i40e_del_geneve_port(struct net_device *netdev,
8641 sa_family_t sa_family, __be16 port)
8642{
8643#if IS_ENABLED(CONFIG_GENEVE)
8644 struct i40e_netdev_priv *np = netdev_priv(netdev);
8645 struct i40e_vsi *vsi = np->vsi;
8646 struct i40e_pf *pf = vsi->back;
8647 u8 idx;
8648
8649 if (sa_family == AF_INET6)
8650 return;
8651
8652 idx = i40e_get_udp_port_idx(pf, port);
8653
8654 /* Check if port already exists */
8655 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8656 /* if port exists, set it to 0 (mark for deletion)
8657 * and make it pending
8658 */
8659 pf->udp_ports[idx].index = 0;
8660 pf->pending_udp_bitmap |= BIT_ULL(idx);
8661 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8662
8663 dev_info(&pf->pdev->dev, "deleting geneve port %d\n",
8664 ntohs(port));
8665 } else {
8666 netdev_warn(netdev, "geneve port %d was not found, not deleting\n",
8667 ntohs(port));
8668 }
a1c9a9d9 8669#endif
6a899024
SA		 8670}
8671
1f224ad2 8672static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8673 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8674{
8675 struct i40e_netdev_priv *np = netdev_priv(netdev);
8676 struct i40e_pf *pf = np->vsi->back;
8677 struct i40e_hw *hw = &pf->hw;
8678
8679 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8680 return -EOPNOTSUPP;
8681
8682 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8683 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8684
8685 return 0;
8686}
8687
2f90ade6
JB		 8688/**
8689 * i40e_ndo_fdb_add - add an entry to the hardware database
8690 * @ndm: the input from the stack
8691 * @tb: pointer to array of nladdr (unused)
8692 * @dev: the net device pointer
8693 * @addr: the MAC address entry being added
8694 * @flags: instructions from stack about fdb operation
8695 */
4ba0dea5
GR		 8696static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8697 struct net_device *dev,
f6f6424b 8698 const unsigned char *addr, u16 vid,
4ba0dea5 8699 u16 flags)
4ba0dea5
GR		 8700{
8701 struct i40e_netdev_priv *np = netdev_priv(dev);
8702 struct i40e_pf *pf = np->vsi->back;
8703 int err = 0;
8704
8705 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8706 return -EOPNOTSUPP;
8707
65891fea
OG		 8708 if (vid) {
8709 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8710 return -EINVAL;
8711 }
8712
4ba0dea5
GR		 8713 /* Hardware does not support aging addresses so if a
8714 * ndm_state is given only allow permanent addresses
8715 */
8716 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8717 netdev_info(dev, "FDB only supports static addresses\n");
8718 return -EINVAL;
8719 }
8720
8721 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8722 err = dev_uc_add_excl(dev, addr);
8723 else if (is_multicast_ether_addr(addr))
8724 err = dev_mc_add_excl(dev, addr);
8725 else
8726 err = -EINVAL;
8727
8728 /* Only return duplicate errors if NLM_F_EXCL is set */
8729 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8730 err = 0;
8731
8732 return err;
8733}
8734
51616018
NP		 8735/**
8736 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8737 * @dev: the netdev being configured
8738 * @nlh: RTNL message
8739 *
8740 * Inserts a new hardware bridge if not already created and
8741 * enables the bridging mode requested (VEB or VEPA). If the
8742 * hardware bridge has already been inserted and the request
8743 * is to change the mode then that requires a PF reset to
8744 * allow rebuild of the components with required hardware
8745 * bridge mode enabled.
8746 **/
8747static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8748 struct nlmsghdr *nlh,
8749 u16 flags)
51616018
NP		 8750{
8751 struct i40e_netdev_priv *np = netdev_priv(dev);
8752 struct i40e_vsi *vsi = np->vsi;
8753 struct i40e_pf *pf = vsi->back;
8754 struct i40e_veb *veb = NULL;
8755 struct nlattr *attr, *br_spec;
8756 int i, rem;
8757
8758 /* Only for PF VSI for now */
8759 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8760 return -EOPNOTSUPP;
8761
8762 /* Find the HW bridge for PF VSI */
8763 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8764 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8765 veb = pf->veb[i];
8766 }
8767
8768 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8769
8770 nla_for_each_nested(attr, br_spec, rem) {
8771 __u16 mode;
8772
8773 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8774 continue;
8775
8776 mode = nla_get_u16(attr);
8777 if ((mode != BRIDGE_MODE_VEPA) &&
8778 (mode != BRIDGE_MODE_VEB))
8779 return -EINVAL;
8780
8781 /* Insert a new HW bridge */
8782 if (!veb) {
8783 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8784 vsi->tc_config.enabled_tc);
8785 if (veb) {
8786 veb->bridge_mode = mode;
8787 i40e_config_bridge_mode(veb);
8788 } else {
8789 /* No Bridge HW offload available */
8790 return -ENOENT;
8791 }
8792 break;
8793 } else if (mode != veb->bridge_mode) {
8794 /* Existing HW bridge but different mode needs reset */
8795 veb->bridge_mode = mode;
fc60861e
ASJ		 8796 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8797 if (mode == BRIDGE_MODE_VEB)
8798 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8799 else
8800 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8801 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8802 break;
8803 }
8804 }
8805
8806 return 0;
8807}
8808
8809/**
8810 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8811 * @skb: skb buff
8812 * @pid: process id
8813 * @seq: RTNL message seq #
8814 * @dev: the netdev being configured
8815 * @filter_mask: unused
d4b2f9fe 8816 * @nlflags: netlink flags passed in
51616018
NP		 8817 *
8818 * Return the mode in which the hardware bridge is operating in
8819 * i.e VEB or VEPA.
8820 **/
51616018
NP		 8821static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8822 struct net_device *dev,
9f4ffc44
CW		 8823 u32 __always_unused filter_mask,
8824 int nlflags)
51616018
NP		 8825{
8826 struct i40e_netdev_priv *np = netdev_priv(dev);
8827 struct i40e_vsi *vsi = np->vsi;
8828 struct i40e_pf *pf = vsi->back;
8829 struct i40e_veb *veb = NULL;
8830 int i;
8831
8832 /* Only for PF VSI for now */
8833 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8834 return -EOPNOTSUPP;
8835
8836 /* Find the HW bridge for the PF VSI */
8837 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8838 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8839 veb = pf->veb[i];
8840 }
8841
8842 if (!veb)
8843 return 0;
8844
46c264da 8845 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8846 nlflags, 0, 0, filter_mask, NULL);
51616018 8847}
51616018 8848
6a899024
SA		 8849/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
8850 * inner mac plus all inner ethertypes.
8851 */
8852#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 8853/**
8854 * i40e_features_check - Validate encapsulated packet conforms to limits
8855 * @skb: skb buff
2bc11c63 8856 * @dev: This physical port's netdev
f44a75e2
JS		 8857 * @features: Offload features that the stack believes apply
8858 **/
8859static netdev_features_t i40e_features_check(struct sk_buff *skb,
8860 struct net_device *dev,
8861 netdev_features_t features)
8862{
8863 if (skb->encapsulation &&
6a899024 8864 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 8865 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 8866 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 8867
8868 return features;
8869}
8870
37a2973a 8871static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8872 .ndo_open = i40e_open,
8873 .ndo_stop = i40e_close,
8874 .ndo_start_xmit = i40e_lan_xmit_frame,
8875 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8876 .ndo_set_rx_mode = i40e_set_rx_mode,
8877 .ndo_validate_addr = eth_validate_addr,
8878 .ndo_set_mac_address = i40e_set_mac,
8879 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8880 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8881 .ndo_tx_timeout = i40e_tx_timeout,
8882 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8883 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8884#ifdef CONFIG_NET_POLL_CONTROLLER
8885 .ndo_poll_controller = i40e_netpoll,
8886#endif
8887 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8888#ifdef I40E_FCOE
8889 .ndo_fcoe_enable = i40e_fcoe_enable,
8890 .ndo_fcoe_disable = i40e_fcoe_disable,
8891#endif
41c445ff
JB		 8892 .ndo_set_features = i40e_set_features,
8893 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8894 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8895 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8896 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8897 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8898 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
6a899024 8899#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8900 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8901 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6a899024
SA		 8902#endif
8903#if IS_ENABLED(CONFIG_GENEVE)
8904 .ndo_add_geneve_port = i40e_add_geneve_port,
8905 .ndo_del_geneve_port = i40e_del_geneve_port,
a1c9a9d9 8906#endif
1f224ad2 8907 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8908 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8909 .ndo_features_check = i40e_features_check,
51616018
NP		 8910 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8911 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8912};
8913
8914/**
8915 * i40e_config_netdev - Setup the netdev flags
8916 * @vsi: the VSI being configured
8917 *
8918 * Returns 0 on success, negative value on failure
8919 **/
8920static int i40e_config_netdev(struct i40e_vsi *vsi)
8921{
1a10370a 8922 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8923 struct i40e_pf *pf = vsi->back;
8924 struct i40e_hw *hw = &pf->hw;
8925 struct i40e_netdev_priv *np;
8926 struct net_device *netdev;
8927 u8 mac_addr[ETH_ALEN];
8928 int etherdev_size;
8929
8930 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8931 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8932 if (!netdev)
8933 return -ENOMEM;
8934
8935 vsi->netdev = netdev;
8936 np = netdev_priv(netdev);
8937 np->vsi = vsi;
8938
d70e941b 8939 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
6a899024 8940 NETIF_F_RXCSUM |
41c445ff 8941 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8942 NETIF_F_GSO_GRE |
d70e941b 8943 NETIF_F_TSO;
41c445ff
JB		 8944
8945 netdev->features = NETIF_F_SG |
8946 NETIF_F_IP_CSUM |
53692b1d 8947 NETIF_F_SCTP_CRC |
41c445ff
JB		 8948 NETIF_F_HIGHDMA |
8949 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8950 NETIF_F_GSO_GRE |
41c445ff
JB		 8951 NETIF_F_HW_VLAN_CTAG_TX |
8952 NETIF_F_HW_VLAN_CTAG_RX |
8953 NETIF_F_HW_VLAN_CTAG_FILTER |
8954 NETIF_F_IPV6_CSUM |
8955 NETIF_F_TSO |
059dab69 8956 NETIF_F_TSO_ECN |
41c445ff
JB		 8957 NETIF_F_TSO6 |
8958 NETIF_F_RXCSUM |
8959 NETIF_F_RXHASH |
8960 0;
8961
2e86a0b6
ASJ		 8962 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8963 netdev->features |= NETIF_F_NTUPLE;
8964
41c445ff
JB		 8965 /* copy netdev features into list of user selectable features */
8966 netdev->hw_features |= netdev->features;
8967
8968 if (vsi->type == I40E_VSI_MAIN) {
8969 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8970 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8971 /* The following steps are necessary to prevent reception
8972 * of tagged packets - some older NVM configurations load a
8973 * default a MAC-VLAN filter that accepts any tagged packet
8974 * which must be replaced by a normal filter.
8c27d42e 8975 */
21659035
KP		 8976 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
8977 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 8978 i40e_add_filter(vsi, mac_addr,
8979 I40E_VLAN_ANY, false, true);
21659035
KP		 8980 spin_unlock_bh(&vsi->mac_filter_list_lock);
8981 }
41c445ff
JB		 8982 } else {
8983 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8984 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8985 pf->vsi[pf->lan_vsi]->netdev->name);
8986 random_ether_addr(mac_addr);
21659035
KP		 8987
8988 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 8989 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 8990 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8991 }
21659035
KP		 8992
8993 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 8994 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 8995 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8996
9a173901
GR		 8997 ether_addr_copy(netdev->dev_addr, mac_addr);
8998 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8999 /* vlan gets same features (except vlan offload)
9000 * after any tweaks for specific VSI types
9001 */
9002 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
9003 NETIF_F_HW_VLAN_CTAG_RX |
9004 NETIF_F_HW_VLAN_CTAG_FILTER);
9005 netdev->priv_flags |= IFF_UNICAST_FLT;
9006 netdev->priv_flags |= IFF_SUPP_NOFCS;
9007 /* Setup netdev TC information */
9008 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9009
9010 netdev->netdev_ops = &i40e_netdev_ops;
9011 netdev->watchdog_timeo = 5 * HZ;
9012 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9013#ifdef I40E_FCOE
9014 i40e_fcoe_config_netdev(netdev, vsi);
9015#endif
41c445ff
JB		 9016
9017 return 0;
9018}
9019
9020/**
9021 * i40e_vsi_delete - Delete a VSI from the switch
9022 * @vsi: the VSI being removed
9023 *
9024 * Returns 0 on success, negative value on failure
9025 **/
9026static void i40e_vsi_delete(struct i40e_vsi *vsi)
9027{
9028 /* remove default VSI is not allowed */
9029 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9030 return;
9031
41c445ff 9032 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9033}
9034
51616018
NP		 9035/**
9036 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9037 * @vsi: the VSI being queried
9038 *
9039 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9040 **/
9041int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9042{
9043 struct i40e_veb *veb;
9044 struct i40e_pf *pf = vsi->back;
9045
9046 /* Uplink is not a bridge so default to VEB */
9047 if (vsi->veb_idx == I40E_NO_VEB)
9048 return 1;
9049
9050 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9051 if (!veb) {
9052 dev_info(&pf->pdev->dev,
9053 "There is no veb associated with the bridge\n");
9054 return -ENOENT;
9055 }
9056
51616018 9057 /* Uplink is a bridge in VEPA mode */
09603eaa 9058 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9059 return 0;
09603eaa
AA		 9060 } else {
9061 /* Uplink is a bridge in VEB mode */
9062 return 1;
9063 }
51616018 9064
09603eaa
AA		 9065 /* VEPA is now default bridge, so return 0 */
9066 return 0;
51616018
NP		 9067}
9068
41c445ff
JB		 9069/**
9070 * i40e_add_vsi - Add a VSI to the switch
9071 * @vsi: the VSI being configured
9072 *
9073 * This initializes a VSI context depending on the VSI type to be added and
9074 * passes it down to the add_vsi aq command.
9075 **/
9076static int i40e_add_vsi(struct i40e_vsi *vsi)
9077{
9078 int ret = -ENODEV;
21659035
KP		 9079 u8 laa_macaddr[ETH_ALEN];
9080 bool found_laa_mac_filter = false;
41c445ff
JB		 9081 struct i40e_pf *pf = vsi->back;
9082 struct i40e_hw *hw = &pf->hw;
9083 struct i40e_vsi_context ctxt;
21659035
KP		 9084 struct i40e_mac_filter *f, *ftmp;
9085
41c445ff
JB		 9086 u8 enabled_tc = 0x1; /* TC0 enabled */
9087 int f_count = 0;
9088
9089 memset(&ctxt, 0, sizeof(ctxt));
9090 switch (vsi->type) {
9091 case I40E_VSI_MAIN:
9092 /* The PF's main VSI is already setup as part of the
9093 * device initialization, so we'll not bother with
9094 * the add_vsi call, but we will retrieve the current
9095 * VSI context.
9096 */
9097 ctxt.seid = pf->main_vsi_seid;
9098 ctxt.pf_num = pf->hw.pf_id;
9099 ctxt.vf_num = 0;
9100 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9101 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9102 if (ret) {
9103 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9104 "couldn't get PF vsi config, err %s aq_err %s\n",
9105 i40e_stat_str(&pf->hw, ret),
9106 i40e_aq_str(&pf->hw,
9107 pf->hw.aq.asq_last_status));
41c445ff
JB		 9108 return -ENOENT;
9109 }
1a2f6248 9110 vsi->info = ctxt.info;
41c445ff
JB		 9111 vsi->info.valid_sections = 0;
9112
9113 vsi->seid = ctxt.seid;
9114 vsi->id = ctxt.vsi_number;
9115
9116 enabled_tc = i40e_pf_get_tc_map(pf);
9117
9118 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9119 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9120 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9121 memset(&ctxt, 0, sizeof(ctxt));
9122 ctxt.seid = pf->main_vsi_seid;
9123 ctxt.pf_num = pf->hw.pf_id;
9124 ctxt.vf_num = 0;
9125 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9126 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9127 if (ret) {
9128 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9129 "update vsi failed, err %s aq_err %s\n",
9130 i40e_stat_str(&pf->hw, ret),
9131 i40e_aq_str(&pf->hw,
9132 pf->hw.aq.asq_last_status));
41c445ff
JB		 9133 ret = -ENOENT;
9134 goto err;
9135 }
9136 /* update the local VSI info queue map */
9137 i40e_vsi_update_queue_map(vsi, &ctxt);
9138 vsi->info.valid_sections = 0;
9139 } else {
9140 /* Default/Main VSI is only enabled for TC0
9141 * reconfigure it to enable all TCs that are
9142 * available on the port in SFP mode.
63d7e5a4
NP		 9143 * For MFP case the iSCSI PF would use this
9144 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9145 */
9146 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9147 if (ret) {
9148 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9149 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9150 enabled_tc,
9151 i40e_stat_str(&pf->hw, ret),
9152 i40e_aq_str(&pf->hw,
9153 pf->hw.aq.asq_last_status));
41c445ff
JB		 9154 ret = -ENOENT;
9155 }
9156 }
9157 break;
9158
9159 case I40E_VSI_FDIR:
cbf61325
ASJ		 9160 ctxt.pf_num = hw->pf_id;
9161 ctxt.vf_num = 0;
9162 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9163 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9164 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9165 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9166 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9167 ctxt.info.valid_sections |=
fc60861e 9168 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9169 ctxt.info.switch_id =
fc60861e 9170 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9171 }
41c445ff 9172 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9173 break;
9174
9175 case I40E_VSI_VMDQ2:
9176 ctxt.pf_num = hw->pf_id;
9177 ctxt.vf_num = 0;
9178 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9179 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9180 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9181
41c445ff
JB		 9182 /* This VSI is connected to VEB so the switch_id
9183 * should be set to zero by default.
9184 */
51616018
NP		 9185 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9186 ctxt.info.valid_sections |=
9187 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9188 ctxt.info.switch_id =
9189 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9190 }
41c445ff
JB		 9191
9192 /* Setup the VSI tx/rx queue map for TC0 only for now */
9193 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9194 break;
9195
9196 case I40E_VSI_SRIOV:
9197 ctxt.pf_num = hw->pf_id;
9198 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9199 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9200 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9201 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9202
41c445ff
JB		 9203 /* This VSI is connected to VEB so the switch_id
9204 * should be set to zero by default.
9205 */
51616018
NP		 9206 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9207 ctxt.info.valid_sections |=
9208 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9209 ctxt.info.switch_id =
9210 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9211 }
41c445ff
JB		 9212
9213 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9214 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9215 if (pf->vf[vsi->vf_id].spoofchk) {
9216 ctxt.info.valid_sections |=
9217 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9218 ctxt.info.sec_flags |=
9219 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9220 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9221 }
41c445ff
JB		 9222 /* Setup the VSI tx/rx queue map for TC0 only for now */
9223 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9224 break;
9225
38e00438
VD		 9226#ifdef I40E_FCOE
9227 case I40E_VSI_FCOE:
9228 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9229 if (ret) {
9230 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9231 return ret;
9232 }
9233 break;
9234
9235#endif /* I40E_FCOE */
41c445ff
JB		 9236 default:
9237 return -ENODEV;
9238 }
9239
9240 if (vsi->type != I40E_VSI_MAIN) {
9241 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9242 if (ret) {
9243 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9244 "add vsi failed, err %s aq_err %s\n",
9245 i40e_stat_str(&pf->hw, ret),
9246 i40e_aq_str(&pf->hw,
9247 pf->hw.aq.asq_last_status));
41c445ff
JB		 9248 ret = -ENOENT;
9249 goto err;
9250 }
1a2f6248 9251 vsi->info = ctxt.info;
41c445ff
JB		 9252 vsi->info.valid_sections = 0;
9253 vsi->seid = ctxt.seid;
9254 vsi->id = ctxt.vsi_number;
9255 }
9256
21659035 9257 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9258 /* If macvlan filters already exist, force them to get loaded */
9259 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9260 f->changed = true;
9261 f_count++;
6252c7e4 9262
21659035 9263 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9264 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9265 ether_addr_copy(laa_macaddr, f->macaddr);
9266 found_laa_mac_filter = true;
9267 }
9268 }
9269 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9270
21659035
KP		 9271 if (found_laa_mac_filter) {
9272 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9273
21659035
KP		 9274 memset(&element, 0, sizeof(element));
9275 ether_addr_copy(element.mac_addr, laa_macaddr);
9276 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9277 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9278 &element, 1, NULL);
9279 if (ret) {
9280 /* some older FW has a different default */
9281 element.flags |=
9282 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9283 i40e_aq_remove_macvlan(hw, vsi->seid,
9284 &element, 1, NULL);
6252c7e4 9285 }
21659035
KP		 9286
9287 i40e_aq_mac_address_write(hw,
9288 I40E_AQC_WRITE_TYPE_LAA_WOL,
9289 laa_macaddr, NULL);
41c445ff 9290 }
21659035 9291
41c445ff
JB		 9292 if (f_count) {
9293 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9294 pf->flags |= I40E_FLAG_FILTER_SYNC;
9295 }
9296
9297 /* Update VSI BW information */
9298 ret = i40e_vsi_get_bw_info(vsi);
9299 if (ret) {
9300 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9301 "couldn't get vsi bw info, err %s aq_err %s\n",
9302 i40e_stat_str(&pf->hw, ret),
9303 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9304 /* VSI is already added so not tearing that up */
9305 ret = 0;
9306 }
9307
9308err:
9309 return ret;
9310}
9311
9312/**
9313 * i40e_vsi_release - Delete a VSI and free its resources
9314 * @vsi: the VSI being removed
9315 *
9316 * Returns 0 on success or < 0 on error
9317 **/
9318int i40e_vsi_release(struct i40e_vsi *vsi)
9319{
9320 struct i40e_mac_filter *f, *ftmp;
9321 struct i40e_veb *veb = NULL;
9322 struct i40e_pf *pf;
9323 u16 uplink_seid;
9324 int i, n;
9325
9326 pf = vsi->back;
9327
9328 /* release of a VEB-owner or last VSI is not allowed */
9329 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9330 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9331 vsi->seid, vsi->uplink_seid);
9332 return -ENODEV;
9333 }
9334 if (vsi == pf->vsi[pf->lan_vsi] &&
9335 !test_bit(__I40E_DOWN, &pf->state)) {
9336 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9337 return -ENODEV;
9338 }
9339
9340 uplink_seid = vsi->uplink_seid;
9341 if (vsi->type != I40E_VSI_SRIOV) {
9342 if (vsi->netdev_registered) {
9343 vsi->netdev_registered = false;
9344 if (vsi->netdev) {
9345 /* results in a call to i40e_close() */
9346 unregister_netdev(vsi->netdev);
41c445ff
JB		 9347 }
9348 } else {
90ef8d47 9349 i40e_vsi_close(vsi);
41c445ff
JB		 9350 }
9351 i40e_vsi_disable_irq(vsi);
9352 }
9353
21659035 9354 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9355 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9356 i40e_del_filter(vsi, f->macaddr, f->vlan,
9357 f->is_vf, f->is_netdev);
21659035
KP		 9358 spin_unlock_bh(&vsi->mac_filter_list_lock);
9359
17652c63 9360 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9361
9362 i40e_vsi_delete(vsi);
9363 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9364 if (vsi->netdev) {
9365 free_netdev(vsi->netdev);
9366 vsi->netdev = NULL;
9367 }
41c445ff
JB		 9368 i40e_vsi_clear_rings(vsi);
9369 i40e_vsi_clear(vsi);
9370
9371 /* If this was the last thing on the VEB, except for the
9372 * controlling VSI, remove the VEB, which puts the controlling
9373 * VSI onto the next level down in the switch.
9374 *
9375 * Well, okay, there's one more exception here: don't remove
9376 * the orphan VEBs yet. We'll wait for an explicit remove request
9377 * from up the network stack.
9378 */
505682cd 9379 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9380 if (pf->vsi[i] &&
9381 pf->vsi[i]->uplink_seid == uplink_seid &&
9382 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9383 n++; /* count the VSIs */
9384 }
9385 }
9386 for (i = 0; i < I40E_MAX_VEB; i++) {
9387 if (!pf->veb[i])
9388 continue;
9389 if (pf->veb[i]->uplink_seid == uplink_seid)
9390 n++; /* count the VEBs */
9391 if (pf->veb[i]->seid == uplink_seid)
9392 veb = pf->veb[i];
9393 }
9394 if (n == 0 && veb && veb->uplink_seid != 0)
9395 i40e_veb_release(veb);
9396
9397 return 0;
9398}
9399
9400/**
9401 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9402 * @vsi: ptr to the VSI
9403 *
9404 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9405 * corresponding SW VSI structure and initializes num_queue_pairs for the
9406 * newly allocated VSI.
9407 *
9408 * Returns 0 on success or negative on failure
9409 **/
9410static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9411{
9412 int ret = -ENOENT;
9413 struct i40e_pf *pf = vsi->back;
9414
493fb300 9415 if (vsi->q_vectors[0]) {
41c445ff
JB		 9416 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9417 vsi->seid);
9418 return -EEXIST;
9419 }
9420
9421 if (vsi->base_vector) {
f29eaa3d 9422 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9423 vsi->seid, vsi->base_vector);
9424 return -EEXIST;
9425 }
9426
90e04070 9427 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9428 if (ret) {
9429 dev_info(&pf->pdev->dev,
9430 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9431 vsi->num_q_vectors, vsi->seid, ret);
9432 vsi->num_q_vectors = 0;
9433 goto vector_setup_out;
9434 }
9435
26cdc443
ASJ		 9436 /* In Legacy mode, we do not have to get any other vector since we
9437 * piggyback on the misc/ICR0 for queue interrupts.
9438 */
9439 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9440 return ret;
958a3e3b
SN		 9441 if (vsi->num_q_vectors)
9442 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9443 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9444 if (vsi->base_vector < 0) {
9445 dev_info(&pf->pdev->dev,
049a2be8
SN		 9446 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9447 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9448 i40e_vsi_free_q_vectors(vsi);
9449 ret = -ENOENT;
9450 goto vector_setup_out;
9451 }
9452
9453vector_setup_out:
9454 return ret;
9455}
9456
bc7d338f
ASJ		 9457/**
9458 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9459 * @vsi: pointer to the vsi.
9460 *
9461 * This re-allocates a vsi's queue resources.
9462 *
9463 * Returns pointer to the successfully allocated and configured VSI sw struct
9464 * on success, otherwise returns NULL on failure.
9465 **/
9466static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9467{
9468 struct i40e_pf *pf = vsi->back;
9469 u8 enabled_tc;
9470 int ret;
9471
9472 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9473 i40e_vsi_clear_rings(vsi);
9474
9475 i40e_vsi_free_arrays(vsi, false);
9476 i40e_set_num_rings_in_vsi(vsi);
9477 ret = i40e_vsi_alloc_arrays(vsi, false);
9478 if (ret)
9479 goto err_vsi;
9480
9481 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9482 if (ret < 0) {
049a2be8 9483 dev_info(&pf->pdev->dev,
f1c7e72e 9484 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9485 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9486 goto err_vsi;
9487 }
9488 vsi->base_queue = ret;
9489
9490 /* Update the FW view of the VSI. Force a reset of TC and queue
9491 * layout configurations.
9492 */
9493 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9494 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9495 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9496 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9497
9498 /* assign it some queues */
9499 ret = i40e_alloc_rings(vsi);
9500 if (ret)
9501 goto err_rings;
9502
9503 /* map all of the rings to the q_vectors */
9504 i40e_vsi_map_rings_to_vectors(vsi);
9505 return vsi;
9506
9507err_rings:
9508 i40e_vsi_free_q_vectors(vsi);
9509 if (vsi->netdev_registered) {
9510 vsi->netdev_registered = false;
9511 unregister_netdev(vsi->netdev);
9512 free_netdev(vsi->netdev);
9513 vsi->netdev = NULL;
9514 }
9515 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9516err_vsi:
9517 i40e_vsi_clear(vsi);
9518 return NULL;
9519}
9520
41c445ff
JB		 9521/**
9522 * i40e_vsi_setup - Set up a VSI by a given type
9523 * @pf: board private structure
9524 * @type: VSI type
9525 * @uplink_seid: the switch element to link to
9526 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9527 *
9528 * This allocates the sw VSI structure and its queue resources, then add a VSI
9529 * to the identified VEB.
9530 *
9531 * Returns pointer to the successfully allocated and configure VSI sw struct on
9532 * success, otherwise returns NULL on failure.
9533 **/
9534struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9535 u16 uplink_seid, u32 param1)
9536{
9537 struct i40e_vsi *vsi = NULL;
9538 struct i40e_veb *veb = NULL;
9539 int ret, i;
9540 int v_idx;
9541
9542 /* The requested uplink_seid must be either
9543 * - the PF's port seid
9544 * no VEB is needed because this is the PF
9545 * or this is a Flow Director special case VSI
9546 * - seid of an existing VEB
9547 * - seid of a VSI that owns an existing VEB
9548 * - seid of a VSI that doesn't own a VEB
9549 * a new VEB is created and the VSI becomes the owner
9550 * - seid of the PF VSI, which is what creates the first VEB
9551 * this is a special case of the previous
9552 *
9553 * Find which uplink_seid we were given and create a new VEB if needed
9554 */
9555 for (i = 0; i < I40E_MAX_VEB; i++) {
9556 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9557 veb = pf->veb[i];
9558 break;
9559 }
9560 }
9561
9562 if (!veb && uplink_seid != pf->mac_seid) {
9563
505682cd 9564 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9565 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9566 vsi = pf->vsi[i];
9567 break;
9568 }
9569 }
9570 if (!vsi) {
9571 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9572 uplink_seid);
9573 return NULL;
9574 }
9575
9576 if (vsi->uplink_seid == pf->mac_seid)
9577 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9578 vsi->tc_config.enabled_tc);
9579 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9580 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9581 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9582 if (veb) {
9583 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9584 dev_info(&vsi->back->pdev->dev,
fb43201f 9585 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9586 return NULL;
9587 }
fa11cb3d
ASJ		 9588 /* We come up by default in VEPA mode if SRIOV is not
9589 * already enabled, in which case we can't force VEPA
9590 * mode.
9591 */
9592 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9593 veb->bridge_mode = BRIDGE_MODE_VEPA;
9594 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9595 }
51616018 9596 i40e_config_bridge_mode(veb);
79c21a82 9597 }
41c445ff
JB		 9598 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9599 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9600 veb = pf->veb[i];
9601 }
9602 if (!veb) {
9603 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9604 return NULL;
9605 }
9606
9607 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9608 uplink_seid = veb->seid;
9609 }
9610
9611 /* get vsi sw struct */
9612 v_idx = i40e_vsi_mem_alloc(pf, type);
9613 if (v_idx < 0)
9614 goto err_alloc;
9615 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9616 if (!vsi)
9617 goto err_alloc;
41c445ff
JB		 9618 vsi->type = type;
9619 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9620
9621 if (type == I40E_VSI_MAIN)
9622 pf->lan_vsi = v_idx;
9623 else if (type == I40E_VSI_SRIOV)
9624 vsi->vf_id = param1;
9625 /* assign it some queues */
cbf61325
ASJ		 9626 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9627 vsi->idx);
41c445ff 9628 if (ret < 0) {
049a2be8
SN		 9629 dev_info(&pf->pdev->dev,
9630 "failed to get tracking for %d queues for VSI %d err=%d\n",
9631 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9632 goto err_vsi;
9633 }
9634 vsi->base_queue = ret;
9635
9636 /* get a VSI from the hardware */
9637 vsi->uplink_seid = uplink_seid;
9638 ret = i40e_add_vsi(vsi);
9639 if (ret)
9640 goto err_vsi;
9641
9642 switch (vsi->type) {
9643 /* setup the netdev if needed */
9644 case I40E_VSI_MAIN:
9645 case I40E_VSI_VMDQ2:
38e00438 9646 case I40E_VSI_FCOE:
41c445ff
JB		 9647 ret = i40e_config_netdev(vsi);
9648 if (ret)
9649 goto err_netdev;
9650 ret = register_netdev(vsi->netdev);
9651 if (ret)
9652 goto err_netdev;
9653 vsi->netdev_registered = true;
9654 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9655#ifdef CONFIG_I40E_DCB
9656 /* Setup DCB netlink interface */
9657 i40e_dcbnl_setup(vsi);
9658#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9659 /* fall through */
9660
9661 case I40E_VSI_FDIR:
9662 /* set up vectors and rings if needed */
9663 ret = i40e_vsi_setup_vectors(vsi);
9664 if (ret)
9665 goto err_msix;
9666
9667 ret = i40e_alloc_rings(vsi);
9668 if (ret)
9669 goto err_rings;
9670
9671 /* map all of the rings to the q_vectors */
9672 i40e_vsi_map_rings_to_vectors(vsi);
9673
9674 i40e_vsi_reset_stats(vsi);
9675 break;
9676
9677 default:
9678 /* no netdev or rings for the other VSI types */
9679 break;
9680 }
9681
e25d00b8
ASJ		 9682 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9683 (vsi->type == I40E_VSI_VMDQ2)) {
9684 ret = i40e_vsi_config_rss(vsi);
9685 }
41c445ff
JB		 9686 return vsi;
9687
9688err_rings:
9689 i40e_vsi_free_q_vectors(vsi);
9690err_msix:
9691 if (vsi->netdev_registered) {
9692 vsi->netdev_registered = false;
9693 unregister_netdev(vsi->netdev);
9694 free_netdev(vsi->netdev);
9695 vsi->netdev = NULL;
9696 }
9697err_netdev:
9698 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9699err_vsi:
9700 i40e_vsi_clear(vsi);
9701err_alloc:
9702 return NULL;
9703}
9704
9705/**
9706 * i40e_veb_get_bw_info - Query VEB BW information
9707 * @veb: the veb to query
9708 *
9709 * Query the Tx scheduler BW configuration data for given VEB
9710 **/
9711static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9712{
9713 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9714 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9715 struct i40e_pf *pf = veb->pf;
9716 struct i40e_hw *hw = &pf->hw;
9717 u32 tc_bw_max;
9718 int ret = 0;
9719 int i;
9720
9721 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9722 &bw_data, NULL);
9723 if (ret) {
9724 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9725 "query veb bw config failed, err %s aq_err %s\n",
9726 i40e_stat_str(&pf->hw, ret),
9727 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9728 goto out;
9729 }
9730
9731 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9732 &ets_data, NULL);
9733 if (ret) {
9734 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9735 "query veb bw ets config failed, err %s aq_err %s\n",
9736 i40e_stat_str(&pf->hw, ret),
9737 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9738 goto out;
9739 }
9740
9741 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9742 veb->bw_max_quanta = ets_data.tc_bw_max;
9743 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9744 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9745 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9746 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9747 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9748 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9749 veb->bw_tc_limit_credits[i] =
9750 le16_to_cpu(bw_data.tc_bw_limits[i]);
9751 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9752 }
9753
9754out:
9755 return ret;
9756}
9757
9758/**
9759 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9760 * @pf: board private structure
9761 *
9762 * On error: returns error code (negative)
9763 * On success: returns vsi index in PF (positive)
9764 **/
9765static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9766{
9767 int ret = -ENOENT;
9768 struct i40e_veb *veb;
9769 int i;
9770
9771 /* Need to protect the allocation of switch elements at the PF level */
9772 mutex_lock(&pf->switch_mutex);
9773
9774 /* VEB list may be fragmented if VEB creation/destruction has
9775 * been happening. We can afford to do a quick scan to look
9776 * for any free slots in the list.
9777 *
9778 * find next empty veb slot, looping back around if necessary
9779 */
9780 i = 0;
9781 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9782 i++;
9783 if (i >= I40E_MAX_VEB) {
9784 ret = -ENOMEM;
9785 goto err_alloc_veb; /* out of VEB slots! */
9786 }
9787
9788 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9789 if (!veb) {
9790 ret = -ENOMEM;
9791 goto err_alloc_veb;
9792 }
9793 veb->pf = pf;
9794 veb->idx = i;
9795 veb->enabled_tc = 1;
9796
9797 pf->veb[i] = veb;
9798 ret = i;
9799err_alloc_veb:
9800 mutex_unlock(&pf->switch_mutex);
9801 return ret;
9802}
9803
9804/**
9805 * i40e_switch_branch_release - Delete a branch of the switch tree
9806 * @branch: where to start deleting
9807 *
9808 * This uses recursion to find the tips of the branch to be
9809 * removed, deleting until we get back to and can delete this VEB.
9810 **/
9811static void i40e_switch_branch_release(struct i40e_veb *branch)
9812{
9813 struct i40e_pf *pf = branch->pf;
9814 u16 branch_seid = branch->seid;
9815 u16 veb_idx = branch->idx;
9816 int i;
9817
9818 /* release any VEBs on this VEB - RECURSION */
9819 for (i = 0; i < I40E_MAX_VEB; i++) {
9820 if (!pf->veb[i])
9821 continue;
9822 if (pf->veb[i]->uplink_seid == branch->seid)
9823 i40e_switch_branch_release(pf->veb[i]);
9824 }
9825
9826 /* Release the VSIs on this VEB, but not the owner VSI.
9827 *
9828 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9829 * the VEB itself, so don't use (*branch) after this loop.
9830 */
505682cd 9831 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9832 if (!pf->vsi[i])
9833 continue;
9834 if (pf->vsi[i]->uplink_seid == branch_seid &&
9835 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9836 i40e_vsi_release(pf->vsi[i]);
9837 }
9838 }
9839
9840 /* There's one corner case where the VEB might not have been
9841 * removed, so double check it here and remove it if needed.
9842 * This case happens if the veb was created from the debugfs
9843 * commands and no VSIs were added to it.
9844 */
9845 if (pf->veb[veb_idx])
9846 i40e_veb_release(pf->veb[veb_idx]);
9847}
9848
9849/**
9850 * i40e_veb_clear - remove veb struct
9851 * @veb: the veb to remove
9852 **/
9853static void i40e_veb_clear(struct i40e_veb *veb)
9854{
9855 if (!veb)
9856 return;
9857
9858 if (veb->pf) {
9859 struct i40e_pf *pf = veb->pf;
9860
9861 mutex_lock(&pf->switch_mutex);
9862 if (pf->veb[veb->idx] == veb)
9863 pf->veb[veb->idx] = NULL;
9864 mutex_unlock(&pf->switch_mutex);
9865 }
9866
9867 kfree(veb);
9868}
9869
9870/**
9871 * i40e_veb_release - Delete a VEB and free its resources
9872 * @veb: the VEB being removed
9873 **/
9874void i40e_veb_release(struct i40e_veb *veb)
9875{
9876 struct i40e_vsi *vsi = NULL;
9877 struct i40e_pf *pf;
9878 int i, n = 0;
9879
9880 pf = veb->pf;
9881
9882 /* find the remaining VSI and check for extras */
505682cd 9883 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9884 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9885 n++;
9886 vsi = pf->vsi[i];
9887 }
9888 }
9889 if (n != 1) {
9890 dev_info(&pf->pdev->dev,
9891 "can't remove VEB %d with %d VSIs left\n",
9892 veb->seid, n);
9893 return;
9894 }
9895
9896 /* move the remaining VSI to uplink veb */
9897 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9898 if (veb->uplink_seid) {
9899 vsi->uplink_seid = veb->uplink_seid;
9900 if (veb->uplink_seid == pf->mac_seid)
9901 vsi->veb_idx = I40E_NO_VEB;
9902 else
9903 vsi->veb_idx = veb->veb_idx;
9904 } else {
9905 /* floating VEB */
9906 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9907 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9908 }
9909
9910 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9911 i40e_veb_clear(veb);
41c445ff
JB		 9912}
9913
9914/**
9915 * i40e_add_veb - create the VEB in the switch
9916 * @veb: the VEB to be instantiated
9917 * @vsi: the controlling VSI
9918 **/
9919static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9920{
f1c7e72e 9921 struct i40e_pf *pf = veb->pf;
92faef85 9922 bool is_default = veb->pf->cur_promisc;
e1c51b95 9923 bool is_cloud = false;
41c445ff
JB		 9924 int ret;
9925
9926 /* get a VEB from the hardware */
f1c7e72e 9927 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9928 veb->enabled_tc, is_default,
9929 is_cloud, &veb->seid, NULL);
41c445ff 9930 if (ret) {
f1c7e72e
SN		 9931 dev_info(&pf->pdev->dev,
9932 "couldn't add VEB, err %s aq_err %s\n",
9933 i40e_stat_str(&pf->hw, ret),
9934 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9935 return -EPERM;
9936 }
9937
9938 /* get statistics counter */
f1c7e72e 9939 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9940 &veb->stats_idx, NULL, NULL, NULL);
9941 if (ret) {
f1c7e72e
SN		 9942 dev_info(&pf->pdev->dev,
9943 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9944 i40e_stat_str(&pf->hw, ret),
9945 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9946 return -EPERM;
9947 }
9948 ret = i40e_veb_get_bw_info(veb);
9949 if (ret) {
f1c7e72e
SN		 9950 dev_info(&pf->pdev->dev,
9951 "couldn't get VEB bw info, err %s aq_err %s\n",
9952 i40e_stat_str(&pf->hw, ret),
9953 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9954 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9955 return -ENOENT;
9956 }
9957
9958 vsi->uplink_seid = veb->seid;
9959 vsi->veb_idx = veb->idx;
9960 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9961
9962 return 0;
9963}
9964
9965/**
9966 * i40e_veb_setup - Set up a VEB
9967 * @pf: board private structure
9968 * @flags: VEB setup flags
9969 * @uplink_seid: the switch element to link to
9970 * @vsi_seid: the initial VSI seid
9971 * @enabled_tc: Enabled TC bit-map
9972 *
9973 * This allocates the sw VEB structure and links it into the switch
9974 * It is possible and legal for this to be a duplicate of an already
9975 * existing VEB. It is also possible for both uplink and vsi seids
9976 * to be zero, in order to create a floating VEB.
9977 *
9978 * Returns pointer to the successfully allocated VEB sw struct on
9979 * success, otherwise returns NULL on failure.
9980 **/
9981struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9982 u16 uplink_seid, u16 vsi_seid,
9983 u8 enabled_tc)
9984{
9985 struct i40e_veb *veb, *uplink_veb = NULL;
9986 int vsi_idx, veb_idx;
9987 int ret;
9988
9989 /* if one seid is 0, the other must be 0 to create a floating relay */
9990 if ((uplink_seid == 0 || vsi_seid == 0) &&
9991 (uplink_seid + vsi_seid != 0)) {
9992 dev_info(&pf->pdev->dev,
9993 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9994 uplink_seid, vsi_seid);
9995 return NULL;
9996 }
9997
9998 /* make sure there is such a vsi and uplink */
505682cd 9999 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10000 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10001 break;
505682cd 10002 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10003 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10004 vsi_seid);
10005 return NULL;
10006 }
10007
10008 if (uplink_seid && uplink_seid != pf->mac_seid) {
10009 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10010 if (pf->veb[veb_idx] &&
10011 pf->veb[veb_idx]->seid == uplink_seid) {
10012 uplink_veb = pf->veb[veb_idx];
10013 break;
10014 }
10015 }
10016 if (!uplink_veb) {
10017 dev_info(&pf->pdev->dev,
10018 "uplink seid %d not found\n", uplink_seid);
10019 return NULL;
10020 }
10021 }
10022
10023 /* get veb sw struct */
10024 veb_idx = i40e_veb_mem_alloc(pf);
10025 if (veb_idx < 0)
10026 goto err_alloc;
10027 veb = pf->veb[veb_idx];
10028 veb->flags = flags;
10029 veb->uplink_seid = uplink_seid;
10030 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10031 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10032
10033 /* create the VEB in the switch */
10034 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10035 if (ret)
10036 goto err_veb;
1bb8b935
SN		 10037 if (vsi_idx == pf->lan_vsi)
10038 pf->lan_veb = veb->idx;
41c445ff
JB		 10039
10040 return veb;
10041
10042err_veb:
10043 i40e_veb_clear(veb);
10044err_alloc:
10045 return NULL;
10046}
10047
10048/**
b40c82e6 10049 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10050 * @pf: board private structure
10051 * @ele: element we are building info from
10052 * @num_reported: total number of elements
10053 * @printconfig: should we print the contents
10054 *
10055 * helper function to assist in extracting a few useful SEID values.
10056 **/
10057static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10058 struct i40e_aqc_switch_config_element_resp *ele,
10059 u16 num_reported, bool printconfig)
10060{
10061 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10062 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10063 u8 element_type = ele->element_type;
10064 u16 seid = le16_to_cpu(ele->seid);
10065
10066 if (printconfig)
10067 dev_info(&pf->pdev->dev,
10068 "type=%d seid=%d uplink=%d downlink=%d\n",
10069 element_type, seid, uplink_seid, downlink_seid);
10070
10071 switch (element_type) {
10072 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10073 pf->mac_seid = seid;
10074 break;
10075 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10076 /* Main VEB? */
10077 if (uplink_seid != pf->mac_seid)
10078 break;
10079 if (pf->lan_veb == I40E_NO_VEB) {
10080 int v;
10081
10082 /* find existing or else empty VEB */
10083 for (v = 0; v < I40E_MAX_VEB; v++) {
10084 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10085 pf->lan_veb = v;
10086 break;
10087 }
10088 }
10089 if (pf->lan_veb == I40E_NO_VEB) {
10090 v = i40e_veb_mem_alloc(pf);
10091 if (v < 0)
10092 break;
10093 pf->lan_veb = v;
10094 }
10095 }
10096
10097 pf->veb[pf->lan_veb]->seid = seid;
10098 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10099 pf->veb[pf->lan_veb]->pf = pf;
10100 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10101 break;
10102 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10103 if (num_reported != 1)
10104 break;
10105 /* This is immediately after a reset so we can assume this is
10106 * the PF's VSI
10107 */
10108 pf->mac_seid = uplink_seid;
10109 pf->pf_seid = downlink_seid;
10110 pf->main_vsi_seid = seid;
10111 if (printconfig)
10112 dev_info(&pf->pdev->dev,
10113 "pf_seid=%d main_vsi_seid=%d\n",
10114 pf->pf_seid, pf->main_vsi_seid);
10115 break;
10116 case I40E_SWITCH_ELEMENT_TYPE_PF:
10117 case I40E_SWITCH_ELEMENT_TYPE_VF:
10118 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10119 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10120 case I40E_SWITCH_ELEMENT_TYPE_PE:
10121 case I40E_SWITCH_ELEMENT_TYPE_PA:
10122 /* ignore these for now */
10123 break;
10124 default:
10125 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10126 element_type, seid);
10127 break;
10128 }
10129}
10130
10131/**
10132 * i40e_fetch_switch_configuration - Get switch config from firmware
10133 * @pf: board private structure
10134 * @printconfig: should we print the contents
10135 *
10136 * Get the current switch configuration from the device and
10137 * extract a few useful SEID values.
10138 **/
10139int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10140{
10141 struct i40e_aqc_get_switch_config_resp *sw_config;
10142 u16 next_seid = 0;
10143 int ret = 0;
10144 u8 *aq_buf;
10145 int i;
10146
10147 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10148 if (!aq_buf)
10149 return -ENOMEM;
10150
10151 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10152 do {
10153 u16 num_reported, num_total;
10154
10155 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10156 I40E_AQ_LARGE_BUF,
10157 &next_seid, NULL);
10158 if (ret) {
10159 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10160 "get switch config failed err %s aq_err %s\n",
10161 i40e_stat_str(&pf->hw, ret),
10162 i40e_aq_str(&pf->hw,
10163 pf->hw.aq.asq_last_status));
41c445ff
JB		 10164 kfree(aq_buf);
10165 return -ENOENT;
10166 }
10167
10168 num_reported = le16_to_cpu(sw_config->header.num_reported);
10169 num_total = le16_to_cpu(sw_config->header.num_total);
10170
10171 if (printconfig)
10172 dev_info(&pf->pdev->dev,
10173 "header: %d reported %d total\n",
10174 num_reported, num_total);
10175
41c445ff
JB		 10176 for (i = 0; i < num_reported; i++) {
10177 struct i40e_aqc_switch_config_element_resp *ele =
10178 &sw_config->element[i];
10179
10180 i40e_setup_pf_switch_element(pf, ele, num_reported,
10181 printconfig);
10182 }
10183 } while (next_seid != 0);
10184
10185 kfree(aq_buf);
10186 return ret;
10187}
10188
10189/**
10190 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10191 * @pf: board private structure
bc7d338f 10192 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10193 *
10194 * Returns 0 on success, negative value on failure
10195 **/
bc7d338f 10196static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10197{
10198 int ret;
10199
10200 /* find out what's out there already */
10201 ret = i40e_fetch_switch_configuration(pf, false);
10202 if (ret) {
10203 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10204 "couldn't fetch switch config, err %s aq_err %s\n",
10205 i40e_stat_str(&pf->hw, ret),
10206 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10207 return ret;
10208 }
10209 i40e_pf_reset_stats(pf);
10210
41c445ff 10211 /* first time setup */
bc7d338f 10212 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10213 struct i40e_vsi *vsi = NULL;
10214 u16 uplink_seid;
10215
10216 /* Set up the PF VSI associated with the PF's main VSI
10217 * that is already in the HW switch
10218 */
10219 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10220 uplink_seid = pf->veb[pf->lan_veb]->seid;
10221 else
10222 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10223 if (pf->lan_vsi == I40E_NO_VSI)
10224 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10225 else if (reinit)
10226 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10227 if (!vsi) {
10228 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10229 i40e_fdir_teardown(pf);
10230 return -EAGAIN;
10231 }
41c445ff
JB		 10232 } else {
10233 /* force a reset of TC and queue layout configurations */
10234 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10235
41c445ff
JB		 10236 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10237 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10238 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10239 }
10240 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10241
cbf61325
ASJ		 10242 i40e_fdir_sb_setup(pf);
10243
41c445ff
JB		 10244 /* Setup static PF queue filter control settings */
10245 ret = i40e_setup_pf_filter_control(pf);
10246 if (ret) {
10247 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10248 ret);
10249 /* Failure here should not stop continuing other steps */
10250 }
10251
10252 /* enable RSS in the HW, even for only one queue, as the stack can use
10253 * the hash
10254 */
10255 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10256 i40e_pf_config_rss(pf);
41c445ff
JB		 10257
10258 /* fill in link information and enable LSE reporting */
0a862b43 10259 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10260 i40e_link_event(pf);
10261
d52c20b7 10262 /* Initialize user-specific link properties */
41c445ff
JB		 10263 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10264 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10265
beb0dff1
JK		 10266 i40e_ptp_init(pf);
10267
41c445ff
JB		 10268 return ret;
10269}
10270
41c445ff
JB		 10271/**
10272 * i40e_determine_queue_usage - Work out queue distribution
10273 * @pf: board private structure
10274 **/
10275static void i40e_determine_queue_usage(struct i40e_pf *pf)
10276{
41c445ff
JB		 10277 int queues_left;
10278
10279 pf->num_lan_qps = 0;
38e00438
VD		 10280#ifdef I40E_FCOE
10281 pf->num_fcoe_qps = 0;
10282#endif
41c445ff
JB		 10283
10284 /* Find the max queues to be put into basic use. We'll always be
10285 * using TC0, whether or not DCB is running, and TC0 will get the
10286 * big RSS set.
10287 */
10288 queues_left = pf->hw.func_caps.num_tx_qp;
10289
cbf61325 10290 if ((queues_left == 1) ||
9aa7e935 10291 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10292 /* one qp for PF, no queues for anything else */
10293 queues_left = 0;
acd65448 10294 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10295
10296 /* make sure all the fancies are disabled */
60ea5f83 10297 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10298#ifdef I40E_FCOE
10299 I40E_FLAG_FCOE_ENABLED |
10300#endif
60ea5f83
JB		 10301 I40E_FLAG_FD_SB_ENABLED |
10302 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10303 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10304 I40E_FLAG_SRIOV_ENABLED |
10305 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10306 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10307 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10308 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10309 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10310 /* one qp for PF */
acd65448 10311 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10312 queues_left -= pf->num_lan_qps;
10313
10314 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10315#ifdef I40E_FCOE
10316 I40E_FLAG_FCOE_ENABLED |
10317#endif
9aa7e935
FZ		 10318 I40E_FLAG_FD_SB_ENABLED |
10319 I40E_FLAG_FD_ATR_ENABLED |
10320 I40E_FLAG_DCB_ENABLED |
10321 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10322 } else {
cbf61325 10323 /* Not enough queues for all TCs */
4d9b6043 10324 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10325 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10326 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10327 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10328 }
9a3bd2f1
ASJ		 10329 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10330 num_online_cpus());
10331 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10332 pf->hw.func_caps.num_tx_qp);
10333
cbf61325
ASJ		 10334 queues_left -= pf->num_lan_qps;
10335 }
10336
38e00438
VD		 10337#ifdef I40E_FCOE
10338 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10339 if (I40E_DEFAULT_FCOE <= queues_left) {
10340 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10341 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10342 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10343 } else {
10344 pf->num_fcoe_qps = 0;
10345 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10346 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10347 }
10348
10349 queues_left -= pf->num_fcoe_qps;
10350 }
10351
10352#endif
cbf61325
ASJ		 10353 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10354 if (queues_left > 1) {
10355 queues_left -= 1; /* save 1 queue for FD */
10356 } else {
10357 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10358 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10359 }
41c445ff
JB		 10360 }
10361
10362 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10363 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10364 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10365 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10366 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10367 }
10368
10369 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10370 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10371 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10372 (queues_left / pf->num_vmdq_qps));
10373 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10374 }
10375
f8ff1464 10376 pf->queues_left = queues_left;
8279e495
NP		 10377 dev_dbg(&pf->pdev->dev,
10378 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10379 pf->hw.func_caps.num_tx_qp,
10380 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10381 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10382 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10383 queues_left);
38e00438 10384#ifdef I40E_FCOE
8279e495 10385 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10386#endif
41c445ff
JB		 10387}
10388
10389/**
10390 * i40e_setup_pf_filter_control - Setup PF static filter control
10391 * @pf: PF to be setup
10392 *
b40c82e6 10393 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10394 * settings. If PE/FCoE are enabled then it will also set the per PF
10395 * based filter sizes required for them. It also enables Flow director,
10396 * ethertype and macvlan type filter settings for the pf.
10397 *
10398 * Returns 0 on success, negative on failure
10399 **/
10400static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10401{
10402 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10403
10404 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10405
10406 /* Flow Director is enabled */
60ea5f83 10407 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10408 settings->enable_fdir = true;
10409
10410 /* Ethtype and MACVLAN filters enabled for PF */
10411 settings->enable_ethtype = true;
10412 settings->enable_macvlan = true;
10413
10414 if (i40e_set_filter_control(&pf->hw, settings))
10415 return -ENOENT;
10416
10417 return 0;
10418}
10419
0c22b3dd 10420#define INFO_STRING_LEN 255
7fd89545 10421#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10422static void i40e_print_features(struct i40e_pf *pf)
10423{
10424 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10425 char *buf;
10426 int i;
0c22b3dd 10427
3b195843
JP		 10428 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10429 if (!buf)
0c22b3dd 10430 return;
0c22b3dd 10431
3b195843 10432 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10433#ifdef CONFIG_PCI_IOV
3b195843 10434 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10435#endif
3b195843 10436 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d RX: %s",
7fd89545
SN		 10437 pf->hw.func_caps.num_vsis,
10438 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10439 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10440
10441 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10442 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10443 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10444 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10445 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10446 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10447 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10448 }
4d9b6043 10449 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10450 i += snprintf(&buf[i], REMAIN(i), " DCB");
ce6fcb3f 10451#if IS_ENABLED(CONFIG_VXLAN)
3b195843 10452 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024
SA		 10453#endif
10454#if IS_ENABLED(CONFIG_GENEVE)
10455 i += snprintf(&buf[i], REMAIN(i), " Geneve");
ce6fcb3f 10456#endif
0c22b3dd 10457 if (pf->flags & I40E_FLAG_PTP)
3b195843 10458 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10459#ifdef I40E_FCOE
10460 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10461 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10462#endif
6dec1017 10463 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10464 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10465 else
3b195843 10466 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10467
3b195843
JP		 10468 dev_info(&pf->pdev->dev, "%s\n", buf);
10469 kfree(buf);
7fd89545 10470 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10471}
10472
41c445ff
JB		 10473/**
10474 * i40e_probe - Device initialization routine
10475 * @pdev: PCI device information struct
10476 * @ent: entry in i40e_pci_tbl
10477 *
b40c82e6
JK		 10478 * i40e_probe initializes a PF identified by a pci_dev structure.
10479 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10480 * and a hardware reset occur.
10481 *
10482 * Returns 0 on success, negative on failure
10483 **/
10484static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10485{
e827845c 10486 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10487 struct i40e_pf *pf;
10488 struct i40e_hw *hw;
93cd765b 10489 static u16 pfs_found;
1d5109d1 10490 u16 wol_nvm_bits;
d4dfb81a 10491 u16 link_status;
6f66a484 10492 int err;
41c445ff 10493 u32 len;
4f2f017c 10494 u32 val;
8a9eb7d3 10495 u32 i;
58fc3267 10496 u8 set_fc_aq_fail;
41c445ff
JB		 10497
10498 err = pci_enable_device_mem(pdev);
10499 if (err)
10500 return err;
10501
10502 /* set up for high or low dma */
6494294f 10503 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10504 if (err) {
e3e3bfdd
JS		 10505 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10506 if (err) {
10507 dev_err(&pdev->dev,
10508 "DMA configuration failed: 0x%x\n", err);
10509 goto err_dma;
10510 }
41c445ff
JB		 10511 }
10512
10513 /* set up pci connections */
10514 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10515 IORESOURCE_MEM), i40e_driver_name);
10516 if (err) {
10517 dev_info(&pdev->dev,
10518 "pci_request_selected_regions failed %d\n", err);
10519 goto err_pci_reg;
10520 }
10521
10522 pci_enable_pcie_error_reporting(pdev);
10523 pci_set_master(pdev);
10524
10525 /* Now that we have a PCI connection, we need to do the
10526 * low level device setup. This is primarily setting up
10527 * the Admin Queue structures and then querying for the
10528 * device's current profile information.
10529 */
10530 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10531 if (!pf) {
10532 err = -ENOMEM;
10533 goto err_pf_alloc;
10534 }
10535 pf->next_vsi = 0;
10536 pf->pdev = pdev;
10537 set_bit(__I40E_DOWN, &pf->state);
10538
10539 hw = &pf->hw;
10540 hw->back = pf;
232f4706 10541
2ac8b675
SN		 10542 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10543 I40E_MAX_CSR_SPACE);
232f4706 10544
2ac8b675 10545 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10546 if (!hw->hw_addr) {
10547 err = -EIO;
10548 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10549 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10550 pf->ioremap_len, err);
41c445ff
JB		 10551 goto err_ioremap;
10552 }
10553 hw->vendor_id = pdev->vendor;
10554 hw->device_id = pdev->device;
10555 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10556 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10557 hw->subsystem_device_id = pdev->subsystem_device;
10558 hw->bus.device = PCI_SLOT(pdev->devfn);
10559 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10560 pf->instance = pfs_found;
41c445ff 10561
5b5faa43
SN		 10562 if (debug != -1) {
10563 pf->msg_enable = pf->hw.debug_mask;
10564 pf->msg_enable = debug;
10565 }
10566
7134f9ce
JB		 10567 /* do a special CORER for clearing PXE mode once at init */
10568 if (hw->revision_id == 0 &&
10569 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10570 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10571 i40e_flush(hw);
10572 msleep(200);
10573 pf->corer_count++;
10574
10575 i40e_clear_pxe_mode(hw);
10576 }
10577
41c445ff 10578 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10579 i40e_clear_hw(hw);
41c445ff
JB		 10580 err = i40e_pf_reset(hw);
10581 if (err) {
10582 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10583 goto err_pf_reset;
10584 }
10585 pf->pfr_count++;
10586
10587 hw->aq.num_arq_entries = I40E_AQ_LEN;
10588 hw->aq.num_asq_entries = I40E_AQ_LEN;
10589 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10590 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10591 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10592
b294ac70 10593 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10594 "%s-%s:misc",
10595 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10596
10597 err = i40e_init_shared_code(hw);
10598 if (err) {
b2a75c58
ASJ		 10599 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10600 err);
41c445ff
JB		 10601 goto err_pf_reset;
10602 }
10603
d52c20b7
JB		 10604 /* set up a default setting for link flow control */
10605 pf->hw.fc.requested_mode = I40E_FC_NONE;
10606
41c445ff 10607 err = i40e_init_adminq(hw);
2b2426a7
CW		 10608 if (err) {
10609 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10610 dev_info(&pdev->dev,
10611 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10612 else
10613 dev_info(&pdev->dev,
10614 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10615
10616 goto err_pf_reset;
10617 }
f0b44440 10618
6dec1017
SN		 10619 /* provide nvm, fw, api versions */
10620 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10621 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10622 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10623 i40e_nvm_version_str(hw));
f0b44440 10624
7aa67613
CS		 10625 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10626 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10627 dev_info(&pdev->dev,
7aa67613
CS		 10628 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10629 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10630 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10631 dev_info(&pdev->dev,
7aa67613 10632 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10633
4eb3f768
SN		 10634 i40e_verify_eeprom(pf);
10635
2c5fe33b
JB		 10636 /* Rev 0 hardware was never productized */
10637 if (hw->revision_id < 1)
10638 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10639
6ff4ef86 10640 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10641 err = i40e_get_capabilities(pf);
10642 if (err)
10643 goto err_adminq_setup;
10644
10645 err = i40e_sw_init(pf);
10646 if (err) {
10647 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10648 goto err_sw_init;
10649 }
10650
10651 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10652 hw->func_caps.num_rx_qp,
10653 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10654 if (err) {
10655 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10656 goto err_init_lan_hmc;
10657 }
10658
10659 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10660 if (err) {
10661 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10662 err = -ENOENT;
10663 goto err_configure_lan_hmc;
10664 }
10665
b686ece5
NP		 10666 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10667 * Ignore error return codes because if it was already disabled via
10668 * hardware settings this will fail
10669 */
10670 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10671 (pf->hw.aq.fw_maj_ver < 4)) {
10672 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10673 i40e_aq_stop_lldp(hw, true, NULL);
10674 }
10675
41c445ff 10676 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10677 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10678 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10679 err = -EIO;
10680 goto err_mac_addr;
10681 }
10682 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10683 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10684 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10685 if (is_valid_ether_addr(hw->mac.port_addr))
10686 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10687#ifdef I40E_FCOE
10688 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10689 if (err)
10690 dev_info(&pdev->dev,
10691 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10692 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10693 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10694 hw->mac.san_addr);
10695 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10696 }
10697 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10698#endif /* I40E_FCOE */
41c445ff
JB		 10699
10700 pci_set_drvdata(pdev, pf);
10701 pci_save_state(pdev);
4e3b35b0
NP		 10702#ifdef CONFIG_I40E_DCB
10703 err = i40e_init_pf_dcb(pf);
10704 if (err) {
aebfc816 10705 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10706 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10707 /* Continue without DCB enabled */
4e3b35b0
NP		 10708 }
10709#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10710
10711 /* set up periodic task facility */
10712 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10713 pf->service_timer_period = HZ;
10714
10715 INIT_WORK(&pf->service_task, i40e_service_task);
10716 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10717 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10718
1d5109d1
SN		 10719 /* NVM bit on means WoL disabled for the port */
10720 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10721 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10722 pf->wol_en = false;
10723 else
10724 pf->wol_en = true;
8e2773ae
SN		 10725 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10726
41c445ff
JB		 10727 /* set up the main switch operations */
10728 i40e_determine_queue_usage(pf);
c1147280
JB		 10729 err = i40e_init_interrupt_scheme(pf);
10730 if (err)
10731 goto err_switch_setup;
41c445ff 10732
505682cd
MW		 10733 /* The number of VSIs reported by the FW is the minimum guaranteed
10734 * to us; HW supports far more and we share the remaining pool with
10735 * the other PFs. We allocate space for more than the guarantee with
10736 * the understanding that we might not get them all later.
41c445ff 10737 */
505682cd
MW		 10738 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10739 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10740 else
10741 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10742
10743 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10744 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10745 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10746 if (!pf->vsi) {
10747 err = -ENOMEM;
41c445ff 10748 goto err_switch_setup;
ed87ac09 10749 }
41c445ff 10750
fa11cb3d
ASJ		 10751#ifdef CONFIG_PCI_IOV
10752 /* prep for VF support */
10753 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10754 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10755 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10756 if (pci_num_vf(pdev))
10757 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10758 }
10759#endif
bc7d338f 10760 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10761 if (err) {
10762 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10763 goto err_vsis;
10764 }
58fc3267
HZ		 10765
10766 /* Make sure flow control is set according to current settings */
10767 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10768 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10769 dev_dbg(&pf->pdev->dev,
10770 "Set fc with err %s aq_err %s on get_phy_cap\n",
10771 i40e_stat_str(hw, err),
10772 i40e_aq_str(hw, hw->aq.asq_last_status));
10773 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10774 dev_dbg(&pf->pdev->dev,
10775 "Set fc with err %s aq_err %s on set_phy_config\n",
10776 i40e_stat_str(hw, err),
10777 i40e_aq_str(hw, hw->aq.asq_last_status));
10778 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10779 dev_dbg(&pf->pdev->dev,
10780 "Set fc with err %s aq_err %s on get_link_info\n",
10781 i40e_stat_str(hw, err),
10782 i40e_aq_str(hw, hw->aq.asq_last_status));
10783
8a9eb7d3 10784 /* if FDIR VSI was set up, start it now */
505682cd 10785 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10786 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10787 i40e_vsi_open(pf->vsi[i]);
10788 break;
10789 }
10790 }
41c445ff 10791
7e2453fe
JB		 10792 /* driver is only interested in link up/down and module qualification
10793 * reports from firmware
10794 */
10795 err = i40e_aq_set_phy_int_mask(&pf->hw,
10796 I40E_AQ_EVENT_LINK_UPDOWN |
10797 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10798 if (err)
f1c7e72e
SN		 10799 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10800 i40e_stat_str(&pf->hw, err),
10801 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10802
4f2f017c
ASJ		 10803 /* Reconfigure hardware for allowing smaller MSS in the case
10804 * of TSO, so that we avoid the MDD being fired and causing
10805 * a reset in the case of small MSS+TSO.
10806 */
10807 val = rd32(hw, I40E_REG_MSS);
10808 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10809 val &= ~I40E_REG_MSS_MIN_MASK;
10810 val |= I40E_64BYTE_MSS;
10811 wr32(hw, I40E_REG_MSS, val);
10812 }
10813
025b4a54
ASJ		 10814 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10815 (pf->hw.aq.fw_maj_ver < 4)) {
10816 msleep(75);
10817 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10818 if (err)
f1c7e72e
SN		 10819 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10820 i40e_stat_str(&pf->hw, err),
10821 i40e_aq_str(&pf->hw,
10822 pf->hw.aq.asq_last_status));
cafa2ee6 10823 }
41c445ff
JB		 10824 /* The main driver is (mostly) up and happy. We need to set this state
10825 * before setting up the misc vector or we get a race and the vector
10826 * ends up disabled forever.
10827 */
10828 clear_bit(__I40E_DOWN, &pf->state);
10829
10830 /* In case of MSIX we are going to setup the misc vector right here
10831 * to handle admin queue events etc. In case of legacy and MSI
10832 * the misc functionality and queue processing is combined in
10833 * the same vector and that gets setup at open.
10834 */
10835 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10836 err = i40e_setup_misc_vector(pf);
10837 if (err) {
10838 dev_info(&pdev->dev,
10839 "setup of misc vector failed: %d\n", err);
10840 goto err_vsis;
10841 }
10842 }
10843
df805f62 10844#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10845 /* prep for VF support */
10846 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10847 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10848 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10849 u32 val;
10850
10851 /* disable link interrupts for VFs */
10852 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10853 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10854 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10855 i40e_flush(hw);
4aeec010
MW		 10856
10857 if (pci_num_vf(pdev)) {
10858 dev_info(&pdev->dev,
10859 "Active VFs found, allocating resources.\n");
10860 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10861 if (err)
10862 dev_info(&pdev->dev,
10863 "Error %d allocating resources for existing VFs\n",
10864 err);
10865 }
41c445ff 10866 }
df805f62 10867#endif /* CONFIG_PCI_IOV */
41c445ff 10868
93cd765b
ASJ		 10869 pfs_found++;
10870
41c445ff
JB		 10871 i40e_dbg_pf_init(pf);
10872
10873 /* tell the firmware that we're starting */
44033fac 10874 i40e_send_version(pf);
41c445ff
JB		 10875
10876 /* since everything's happy, start the service_task timer */
10877 mod_timer(&pf->service_timer,
10878 round_jiffies(jiffies + pf->service_timer_period));
10879
38e00438
VD		 10880#ifdef I40E_FCOE
10881 /* create FCoE interface */
10882 i40e_fcoe_vsi_setup(pf);
10883
10884#endif
3fced535
ASJ		 10885#define PCI_SPEED_SIZE 8
10886#define PCI_WIDTH_SIZE 8
10887 /* Devices on the IOSF bus do not have this information
10888 * and will report PCI Gen 1 x 1 by default so don't bother
10889 * checking them.
10890 */
10891 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
10892 char speed[PCI_SPEED_SIZE] = "Unknown";
10893 char width[PCI_WIDTH_SIZE] = "Unknown";
10894
10895 /* Get the negotiated link width and speed from PCI config
10896 * space
10897 */
10898 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
10899 &link_status);
10900
10901 i40e_set_pci_config_data(hw, link_status);
10902
10903 switch (hw->bus.speed) {
10904 case i40e_bus_speed_8000:
10905 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
10906 case i40e_bus_speed_5000:
10907 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
10908 case i40e_bus_speed_2500:
10909 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
10910 default:
10911 break;
10912 }
10913 switch (hw->bus.width) {
10914 case i40e_bus_width_pcie_x8:
10915 strncpy(width, "8", PCI_WIDTH_SIZE); break;
10916 case i40e_bus_width_pcie_x4:
10917 strncpy(width, "4", PCI_WIDTH_SIZE); break;
10918 case i40e_bus_width_pcie_x2:
10919 strncpy(width, "2", PCI_WIDTH_SIZE); break;
10920 case i40e_bus_width_pcie_x1:
10921 strncpy(width, "1", PCI_WIDTH_SIZE); break;
10922 default:
10923 break;
10924 }
10925
10926 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
10927 speed, width);
10928
10929 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10930 hw->bus.speed < i40e_bus_speed_8000) {
10931 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10932 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10933 }
d4dfb81a
CS		 10934 }
10935
e827845c
CS		 10936 /* get the requested speeds from the fw */
10937 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10938 if (err)
8279e495
NP		 10939 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
10940 i40e_stat_str(&pf->hw, err),
10941 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10942 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10943
fc72dbce
CS		 10944 /* get the supported phy types from the fw */
10945 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
10946 if (err)
10947 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
10948 i40e_stat_str(&pf->hw, err),
10949 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10950 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
10951
e7358f54
ASJ		 10952 /* Add a filter to drop all Flow control frames from any VSI from being
10953 * transmitted. By doing so we stop a malicious VF from sending out
10954 * PAUSE or PFC frames and potentially controlling traffic for other
10955 * PF/VF VSIs.
10956 * The FW can still send Flow control frames if enabled.
10957 */
10958 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
10959 pf->main_vsi_seid);
10960
0c22b3dd
JB		 10961 /* print a string summarizing features */
10962 i40e_print_features(pf);
10963
41c445ff
JB		 10964 return 0;
10965
10966 /* Unwind what we've done if something failed in the setup */
10967err_vsis:
10968 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10969 i40e_clear_interrupt_scheme(pf);
10970 kfree(pf->vsi);
04b03013
SN		 10971err_switch_setup:
10972 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10973 del_timer_sync(&pf->service_timer);
10974err_mac_addr:
10975err_configure_lan_hmc:
10976 (void)i40e_shutdown_lan_hmc(hw);
10977err_init_lan_hmc:
10978 kfree(pf->qp_pile);
41c445ff
JB		 10979err_sw_init:
10980err_adminq_setup:
10981 (void)i40e_shutdown_adminq(hw);
10982err_pf_reset:
10983 iounmap(hw->hw_addr);
10984err_ioremap:
10985 kfree(pf);
10986err_pf_alloc:
10987 pci_disable_pcie_error_reporting(pdev);
10988 pci_release_selected_regions(pdev,
10989 pci_select_bars(pdev, IORESOURCE_MEM));
10990err_pci_reg:
10991err_dma:
10992 pci_disable_device(pdev);
10993 return err;
10994}
10995
10996/**
10997 * i40e_remove - Device removal routine
10998 * @pdev: PCI device information struct
10999 *
11000 * i40e_remove is called by the PCI subsystem to alert the driver
11001 * that is should release a PCI device. This could be caused by a
11002 * Hot-Plug event, or because the driver is going to be removed from
11003 * memory.
11004 **/
11005static void i40e_remove(struct pci_dev *pdev)
11006{
11007 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11008 struct i40e_hw *hw = &pf->hw;
41c445ff 11009 i40e_status ret_code;
41c445ff
JB		 11010 int i;
11011
11012 i40e_dbg_pf_exit(pf);
11013
beb0dff1
JK		 11014 i40e_ptp_stop(pf);
11015
bcab2db9
CW		 11016 /* Disable RSS in hw */
11017 wr32(hw, I40E_PFQF_HENA(0), 0);
11018 wr32(hw, I40E_PFQF_HENA(1), 0);
11019
41c445ff
JB		 11020 /* no more scheduling of any task */
11021 set_bit(__I40E_DOWN, &pf->state);
11022 del_timer_sync(&pf->service_timer);
11023 cancel_work_sync(&pf->service_task);
33c62b34 11024 i40e_fdir_teardown(pf);
41c445ff 11025
eb2d80bc
MW		 11026 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11027 i40e_free_vfs(pf);
11028 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11029 }
11030
41c445ff
JB		 11031 i40e_fdir_teardown(pf);
11032
11033 /* If there is a switch structure or any orphans, remove them.
11034 * This will leave only the PF's VSI remaining.
11035 */
11036 for (i = 0; i < I40E_MAX_VEB; i++) {
11037 if (!pf->veb[i])
11038 continue;
11039
11040 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11041 pf->veb[i]->uplink_seid == 0)
11042 i40e_switch_branch_release(pf->veb[i]);
11043 }
11044
11045 /* Now we can shutdown the PF's VSI, just before we kill
11046 * adminq and hmc.
11047 */
11048 if (pf->vsi[pf->lan_vsi])
11049 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11050
41c445ff 11051 /* shutdown and destroy the HMC */
60442dea
SN		 11052 if (pf->hw.hmc.hmc_obj) {
11053 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
11054 if (ret_code)
11055 dev_warn(&pdev->dev,
11056 "Failed to destroy the HMC resources: %d\n",
11057 ret_code);
11058 }
41c445ff
JB		 11059
11060 /* shutdown the adminq */
41c445ff
JB		 11061 ret_code = i40e_shutdown_adminq(&pf->hw);
11062 if (ret_code)
11063 dev_warn(&pdev->dev,
11064 "Failed to destroy the Admin Queue resources: %d\n",
11065 ret_code);
11066
11067 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11068 i40e_clear_interrupt_scheme(pf);
505682cd 11069 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11070 if (pf->vsi[i]) {
11071 i40e_vsi_clear_rings(pf->vsi[i]);
11072 i40e_vsi_clear(pf->vsi[i]);
11073 pf->vsi[i] = NULL;
11074 }
11075 }
11076
11077 for (i = 0; i < I40E_MAX_VEB; i++) {
11078 kfree(pf->veb[i]);
11079 pf->veb[i] = NULL;
11080 }
11081
11082 kfree(pf->qp_pile);
41c445ff
JB		 11083 kfree(pf->vsi);
11084
41c445ff
JB		 11085 iounmap(pf->hw.hw_addr);
11086 kfree(pf);
11087 pci_release_selected_regions(pdev,
11088 pci_select_bars(pdev, IORESOURCE_MEM));
11089
11090 pci_disable_pcie_error_reporting(pdev);
11091 pci_disable_device(pdev);
11092}
11093
11094/**
11095 * i40e_pci_error_detected - warning that something funky happened in PCI land
11096 * @pdev: PCI device information struct
11097 *
11098 * Called to warn that something happened and the error handling steps
11099 * are in progress. Allows the driver to quiesce things, be ready for
11100 * remediation.
11101 **/
11102static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11103 enum pci_channel_state error)
11104{
11105 struct i40e_pf *pf = pci_get_drvdata(pdev);
11106
11107 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11108
11109 /* shutdown all operations */
9007bccd
SN		 11110 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11111 rtnl_lock();
11112 i40e_prep_for_reset(pf);
11113 rtnl_unlock();
11114 }
41c445ff
JB		 11115
11116 /* Request a slot reset */
11117 return PCI_ERS_RESULT_NEED_RESET;
11118}
11119
11120/**
11121 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11122 * @pdev: PCI device information struct
11123 *
11124 * Called to find if the driver can work with the device now that
11125 * the pci slot has been reset. If a basic connection seems good
11126 * (registers are readable and have sane content) then return a
11127 * happy little PCI_ERS_RESULT_xxx.
11128 **/
11129static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11130{
11131 struct i40e_pf *pf = pci_get_drvdata(pdev);
11132 pci_ers_result_t result;
11133 int err;
11134 u32 reg;
11135
fb43201f 11136 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11137 if (pci_enable_device_mem(pdev)) {
11138 dev_info(&pdev->dev,
11139 "Cannot re-enable PCI device after reset.\n");
11140 result = PCI_ERS_RESULT_DISCONNECT;
11141 } else {
11142 pci_set_master(pdev);
11143 pci_restore_state(pdev);
11144 pci_save_state(pdev);
11145 pci_wake_from_d3(pdev, false);
11146
11147 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11148 if (reg == 0)
11149 result = PCI_ERS_RESULT_RECOVERED;
11150 else
11151 result = PCI_ERS_RESULT_DISCONNECT;
11152 }
11153
11154 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11155 if (err) {
11156 dev_info(&pdev->dev,
11157 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11158 err);
11159 /* non-fatal, continue */
11160 }
11161
11162 return result;
11163}
11164
11165/**
11166 * i40e_pci_error_resume - restart operations after PCI error recovery
11167 * @pdev: PCI device information struct
11168 *
11169 * Called to allow the driver to bring things back up after PCI error
11170 * and/or reset recovery has finished.
11171 **/
11172static void i40e_pci_error_resume(struct pci_dev *pdev)
11173{
11174 struct i40e_pf *pf = pci_get_drvdata(pdev);
11175
fb43201f 11176 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11177 if (test_bit(__I40E_SUSPENDED, &pf->state))
11178 return;
11179
11180 rtnl_lock();
41c445ff 11181 i40e_handle_reset_warning(pf);
4c4935a9 11182 rtnl_unlock();
9007bccd
SN		 11183}
11184
11185/**
11186 * i40e_shutdown - PCI callback for shutting down
11187 * @pdev: PCI device information struct
11188 **/
11189static void i40e_shutdown(struct pci_dev *pdev)
11190{
11191 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11192 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11193
11194 set_bit(__I40E_SUSPENDED, &pf->state);
11195 set_bit(__I40E_DOWN, &pf->state);
11196 rtnl_lock();
11197 i40e_prep_for_reset(pf);
11198 rtnl_unlock();
11199
8e2773ae
SN		 11200 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11201 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11202
02b42498
CS		 11203 del_timer_sync(&pf->service_timer);
11204 cancel_work_sync(&pf->service_task);
11205 i40e_fdir_teardown(pf);
11206
11207 rtnl_lock();
11208 i40e_prep_for_reset(pf);
11209 rtnl_unlock();
11210
11211 wr32(hw, I40E_PFPM_APM,
11212 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11213 wr32(hw, I40E_PFPM_WUFC,
11214 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11215
e147758d
SN		 11216 i40e_clear_interrupt_scheme(pf);
11217
9007bccd 11218 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11219 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11220 pci_set_power_state(pdev, PCI_D3hot);
11221 }
11222}
11223
11224#ifdef CONFIG_PM
11225/**
11226 * i40e_suspend - PCI callback for moving to D3
11227 * @pdev: PCI device information struct
11228 **/
11229static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11230{
11231 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11232 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11233
11234 set_bit(__I40E_SUSPENDED, &pf->state);
11235 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11236
9007bccd
SN		 11237 rtnl_lock();
11238 i40e_prep_for_reset(pf);
11239 rtnl_unlock();
11240
8e2773ae
SN		 11241 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11242 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11243
11244 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11245 pci_set_power_state(pdev, PCI_D3hot);
11246
11247 return 0;
41c445ff
JB		 11248}
11249
9007bccd
SN		 11250/**
11251 * i40e_resume - PCI callback for waking up from D3
11252 * @pdev: PCI device information struct
11253 **/
11254static int i40e_resume(struct pci_dev *pdev)
11255{
11256 struct i40e_pf *pf = pci_get_drvdata(pdev);
11257 u32 err;
11258
11259 pci_set_power_state(pdev, PCI_D0);
11260 pci_restore_state(pdev);
11261 /* pci_restore_state() clears dev->state_saves, so
11262 * call pci_save_state() again to restore it.
11263 */
11264 pci_save_state(pdev);
11265
11266 err = pci_enable_device_mem(pdev);
11267 if (err) {
fb43201f 11268 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11269 return err;
11270 }
11271 pci_set_master(pdev);
11272
11273 /* no wakeup events while running */
11274 pci_wake_from_d3(pdev, false);
11275
11276 /* handling the reset will rebuild the device state */
11277 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11278 clear_bit(__I40E_DOWN, &pf->state);
11279 rtnl_lock();
11280 i40e_reset_and_rebuild(pf, false);
11281 rtnl_unlock();
11282 }
11283
11284 return 0;
11285}
11286
11287#endif
41c445ff
JB		 11288static const struct pci_error_handlers i40e_err_handler = {
11289 .error_detected = i40e_pci_error_detected,
11290 .slot_reset = i40e_pci_error_slot_reset,
11291 .resume = i40e_pci_error_resume,
11292};
11293
11294static struct pci_driver i40e_driver = {
11295 .name = i40e_driver_name,
11296 .id_table = i40e_pci_tbl,
11297 .probe = i40e_probe,
11298 .remove = i40e_remove,
9007bccd
SN		 11299#ifdef CONFIG_PM
11300 .suspend = i40e_suspend,
11301 .resume = i40e_resume,
11302#endif
11303 .shutdown = i40e_shutdown,
41c445ff
JB		 11304 .err_handler = &i40e_err_handler,
11305 .sriov_configure = i40e_pci_sriov_configure,
11306};
11307
11308/**
11309 * i40e_init_module - Driver registration routine
11310 *
11311 * i40e_init_module is the first routine called when the driver is
11312 * loaded. All it does is register with the PCI subsystem.
11313 **/
11314static int __init i40e_init_module(void)
11315{
11316 pr_info("%s: %s - version %s\n", i40e_driver_name,
11317 i40e_driver_string, i40e_driver_version_str);
11318 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11319
41c445ff
JB		 11320 i40e_dbg_init();
11321 return pci_register_driver(&i40e_driver);
11322}
11323module_init(i40e_init_module);
11324
11325/**
11326 * i40e_exit_module - Driver exit cleanup routine
11327 *
11328 * i40e_exit_module is called just before the driver is removed
11329 * from memory.
11330 **/
11331static void __exit i40e_exit_module(void)
11332{
11333 pci_unregister_driver(&i40e_driver);
11334 i40e_dbg_exit();
11335}
11336module_exit(i40e_exit_module);
Linux kernel - Deliverables
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