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i40e: poll firmware slower
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db
CS		 40#define DRV_VERSION_MAJOR 1
41#define DRV_VERSION_MINOR 0
e8720db1 42#define DRV_VERSION_BUILD 21
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
38e00438
VD		 273#ifdef I40E_FCOE
274void i40e_tx_timeout(struct net_device *netdev)
275#else
41c445ff 276static void i40e_tx_timeout(struct net_device *netdev)
38e00438 277#endif
41c445ff
JB		 278{
279 struct i40e_netdev_priv *np = netdev_priv(netdev);
280 struct i40e_vsi *vsi = np->vsi;
281 struct i40e_pf *pf = vsi->back;
282
283 pf->tx_timeout_count++;
284
285 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 286 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 287 pf->tx_timeout_last_recovery = jiffies;
288 netdev_info(netdev, "tx_timeout recovery level %d\n",
289 pf->tx_timeout_recovery_level);
290
291 switch (pf->tx_timeout_recovery_level) {
292 case 0:
293 /* disable and re-enable queues for the VSI */
294 if (in_interrupt()) {
295 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
296 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
297 } else {
298 i40e_vsi_reinit_locked(vsi);
299 }
300 break;
301 case 1:
302 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
303 break;
304 case 2:
305 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
306 break;
307 case 3:
308 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
309 break;
310 default:
311 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 312 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
313 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 314 break;
315 }
316 i40e_service_event_schedule(pf);
317 pf->tx_timeout_recovery_level++;
318}
319
320/**
321 * i40e_release_rx_desc - Store the new tail and head values
322 * @rx_ring: ring to bump
323 * @val: new head index
324 **/
325static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
326{
327 rx_ring->next_to_use = val;
328
329 /* Force memory writes to complete before letting h/w
330 * know there are new descriptors to fetch. (Only
331 * applicable for weak-ordered memory model archs,
332 * such as IA-64).
333 */
334 wmb();
335 writel(val, rx_ring->tail);
336}
337
338/**
339 * i40e_get_vsi_stats_struct - Get System Network Statistics
340 * @vsi: the VSI we care about
341 *
342 * Returns the address of the device statistics structure.
343 * The statistics are actually updated from the service task.
344 **/
345struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
346{
347 return &vsi->net_stats;
348}
349
350/**
351 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
352 * @netdev: network interface device structure
353 *
354 * Returns the address of the device statistics structure.
355 * The statistics are actually updated from the service task.
356 **/
38e00438
VD		 357#ifdef I40E_FCOE
358struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
359 struct net_device *netdev,
360 struct rtnl_link_stats64 *stats)
361#else
41c445ff
JB		 362static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
363 struct net_device *netdev,
980e9b11 364 struct rtnl_link_stats64 *stats)
38e00438 365#endif
41c445ff
JB		 366{
367 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 368 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 369 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 370 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
371 int i;
372
bc7d338f
ASJ		 373 if (test_bit(__I40E_DOWN, &vsi->state))
374 return stats;
375
3c325ced
JB		 376 if (!vsi->tx_rings)
377 return stats;
378
980e9b11
AD		 379 rcu_read_lock();
380 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 381 u64 bytes, packets;
382 unsigned int start;
383
384 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
385 if (!tx_ring)
386 continue;
387
388 do {
57a7744e 389 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 390 packets = tx_ring->stats.packets;
391 bytes = tx_ring->stats.bytes;
57a7744e 392 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 393
394 stats->tx_packets += packets;
395 stats->tx_bytes += bytes;
396 rx_ring = &tx_ring[1];
397
398 do {
57a7744e 399 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 400 packets = rx_ring->stats.packets;
401 bytes = rx_ring->stats.bytes;
57a7744e 402 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 403
980e9b11
AD		 404 stats->rx_packets += packets;
405 stats->rx_bytes += bytes;
406 }
407 rcu_read_unlock();
408
a5282f44 409 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 410 stats->multicast = vsi_stats->multicast;
411 stats->tx_errors = vsi_stats->tx_errors;
412 stats->tx_dropped = vsi_stats->tx_dropped;
413 stats->rx_errors = vsi_stats->rx_errors;
414 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
415 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 416
980e9b11 417 return stats;
41c445ff
JB		 418}
419
420/**
421 * i40e_vsi_reset_stats - Resets all stats of the given vsi
422 * @vsi: the VSI to have its stats reset
423 **/
424void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
425{
426 struct rtnl_link_stats64 *ns;
427 int i;
428
429 if (!vsi)
430 return;
431
432 ns = i40e_get_vsi_stats_struct(vsi);
433 memset(ns, 0, sizeof(*ns));
434 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
435 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
436 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 437 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 438 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 439 memset(&vsi->rx_rings[i]->stats, 0 ,
440 sizeof(vsi->rx_rings[i]->stats));
441 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
442 sizeof(vsi->rx_rings[i]->rx_stats));
443 memset(&vsi->tx_rings[i]->stats, 0 ,
444 sizeof(vsi->tx_rings[i]->stats));
445 memset(&vsi->tx_rings[i]->tx_stats, 0,
446 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 447 }
8e9dca53 448 }
41c445ff
JB		 449 vsi->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_pf_reset_stats - Reset all of the stats for the given pf
454 * @pf: the PF to be reset
455 **/
456void i40e_pf_reset_stats(struct i40e_pf *pf)
457{
e91fdf76
SN		 458 int i;
459
41c445ff
JB		 460 memset(&pf->stats, 0, sizeof(pf->stats));
461 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
462 pf->stat_offsets_loaded = false;
e91fdf76
SN		 463
464 for (i = 0; i < I40E_MAX_VEB; i++) {
465 if (pf->veb[i]) {
466 memset(&pf->veb[i]->stats, 0,
467 sizeof(pf->veb[i]->stats));
468 memset(&pf->veb[i]->stats_offsets, 0,
469 sizeof(pf->veb[i]->stats_offsets));
470 pf->veb[i]->stat_offsets_loaded = false;
471 }
472 }
41c445ff
JB		 473}
474
475/**
476 * i40e_stat_update48 - read and update a 48 bit stat from the chip
477 * @hw: ptr to the hardware info
478 * @hireg: the high 32 bit reg to read
479 * @loreg: the low 32 bit reg to read
480 * @offset_loaded: has the initial offset been loaded yet
481 * @offset: ptr to current offset value
482 * @stat: ptr to the stat
483 *
484 * Since the device stats are not reset at PFReset, they likely will not
485 * be zeroed when the driver starts. We'll save the first values read
486 * and use them as offsets to be subtracted from the raw values in order
487 * to report stats that count from zero. In the process, we also manage
488 * the potential roll-over.
489 **/
490static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
491 bool offset_loaded, u64 *offset, u64 *stat)
492{
493 u64 new_data;
494
ab60085e 495 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 496 new_data = rd32(hw, loreg);
497 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
498 } else {
499 new_data = rd64(hw, loreg);
500 }
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = new_data - *offset;
505 else
506 *stat = (new_data + ((u64)1 << 48)) - *offset;
507 *stat &= 0xFFFFFFFFFFFFULL;
508}
509
510/**
511 * i40e_stat_update32 - read and update a 32 bit stat from the chip
512 * @hw: ptr to the hardware info
513 * @reg: the hw reg to read
514 * @offset_loaded: has the initial offset been loaded yet
515 * @offset: ptr to current offset value
516 * @stat: ptr to the stat
517 **/
518static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
519 bool offset_loaded, u64 *offset, u64 *stat)
520{
521 u32 new_data;
522
523 new_data = rd32(hw, reg);
524 if (!offset_loaded)
525 *offset = new_data;
526 if (likely(new_data >= *offset))
527 *stat = (u32)(new_data - *offset);
528 else
529 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
530}
531
532/**
533 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
534 * @vsi: the VSI to be updated
535 **/
536void i40e_update_eth_stats(struct i40e_vsi *vsi)
537{
538 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
539 struct i40e_pf *pf = vsi->back;
540 struct i40e_hw *hw = &pf->hw;
541 struct i40e_eth_stats *oes;
542 struct i40e_eth_stats *es; /* device's eth stats */
543
544 es = &vsi->eth_stats;
545 oes = &vsi->eth_stats_offsets;
546
547 /* Gather up the stats that the hw collects */
548 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_errors, &es->tx_errors);
551 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 554 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
555 vsi->stat_offsets_loaded,
556 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
557 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 560
561 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
562 I40E_GLV_GORCL(stat_idx),
563 vsi->stat_offsets_loaded,
564 &oes->rx_bytes, &es->rx_bytes);
565 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
566 I40E_GLV_UPRCL(stat_idx),
567 vsi->stat_offsets_loaded,
568 &oes->rx_unicast, &es->rx_unicast);
569 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
570 I40E_GLV_MPRCL(stat_idx),
571 vsi->stat_offsets_loaded,
572 &oes->rx_multicast, &es->rx_multicast);
573 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
574 I40E_GLV_BPRCL(stat_idx),
575 vsi->stat_offsets_loaded,
576 &oes->rx_broadcast, &es->rx_broadcast);
577
578 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
579 I40E_GLV_GOTCL(stat_idx),
580 vsi->stat_offsets_loaded,
581 &oes->tx_bytes, &es->tx_bytes);
582 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
583 I40E_GLV_UPTCL(stat_idx),
584 vsi->stat_offsets_loaded,
585 &oes->tx_unicast, &es->tx_unicast);
586 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
587 I40E_GLV_MPTCL(stat_idx),
588 vsi->stat_offsets_loaded,
589 &oes->tx_multicast, &es->tx_multicast);
590 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
591 I40E_GLV_BPTCL(stat_idx),
592 vsi->stat_offsets_loaded,
593 &oes->tx_broadcast, &es->tx_broadcast);
594 vsi->stat_offsets_loaded = true;
595}
596
597/**
598 * i40e_update_veb_stats - Update Switch component statistics
599 * @veb: the VEB being updated
600 **/
601static void i40e_update_veb_stats(struct i40e_veb *veb)
602{
603 struct i40e_pf *pf = veb->pf;
604 struct i40e_hw *hw = &pf->hw;
605 struct i40e_eth_stats *oes;
606 struct i40e_eth_stats *es; /* device's eth stats */
607 int idx = 0;
608
609 idx = veb->stats_idx;
610 es = &veb->stats;
611 oes = &veb->stats_offsets;
612
613 /* Gather up the stats that the hw collects */
614 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 617 if (hw->revision_id > 0)
618 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
619 veb->stat_offsets_loaded,
620 &oes->rx_unknown_protocol,
621 &es->rx_unknown_protocol);
41c445ff
JB		 622 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
623 veb->stat_offsets_loaded,
624 &oes->rx_bytes, &es->rx_bytes);
625 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
626 veb->stat_offsets_loaded,
627 &oes->rx_unicast, &es->rx_unicast);
628 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
629 veb->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
632 veb->stat_offsets_loaded,
633 &oes->rx_broadcast, &es->rx_broadcast);
634
635 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
636 veb->stat_offsets_loaded,
637 &oes->tx_bytes, &es->tx_bytes);
638 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
639 veb->stat_offsets_loaded,
640 &oes->tx_unicast, &es->tx_unicast);
641 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
642 veb->stat_offsets_loaded,
643 &oes->tx_multicast, &es->tx_multicast);
644 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
645 veb->stat_offsets_loaded,
646 &oes->tx_broadcast, &es->tx_broadcast);
647 veb->stat_offsets_loaded = true;
648}
649
38e00438
VD		 650#ifdef I40E_FCOE
651/**
652 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
653 * @vsi: the VSI that is capable of doing FCoE
654 **/
655static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
656{
657 struct i40e_pf *pf = vsi->back;
658 struct i40e_hw *hw = &pf->hw;
659 struct i40e_fcoe_stats *ofs;
660 struct i40e_fcoe_stats *fs; /* device's eth stats */
661 int idx;
662
663 if (vsi->type != I40E_VSI_FCOE)
664 return;
665
666 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
667 fs = &vsi->fcoe_stats;
668 ofs = &vsi->fcoe_stats_offsets;
669
670 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
671 vsi->fcoe_stat_offsets_loaded,
672 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
673 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
674 vsi->fcoe_stat_offsets_loaded,
675 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
676 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
677 vsi->fcoe_stat_offsets_loaded,
678 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
679 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
680 vsi->fcoe_stat_offsets_loaded,
681 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
682 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
683 vsi->fcoe_stat_offsets_loaded,
684 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
685 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
686 vsi->fcoe_stat_offsets_loaded,
687 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
688 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
689 vsi->fcoe_stat_offsets_loaded,
690 &ofs->fcoe_last_error, &fs->fcoe_last_error);
691 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
692 vsi->fcoe_stat_offsets_loaded,
693 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
694
695 vsi->fcoe_stat_offsets_loaded = true;
696}
697
698#endif
41c445ff
JB		 699/**
700 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
701 * @pf: the corresponding PF
702 *
703 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
704 **/
705static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
706{
707 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
708 struct i40e_hw_port_stats *nsd = &pf->stats;
709 struct i40e_hw *hw = &pf->hw;
710 u64 xoff = 0;
711 u16 i, v;
712
713 if ((hw->fc.current_mode != I40E_FC_FULL) &&
714 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
715 return;
716
717 xoff = nsd->link_xoff_rx;
718 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
719 pf->stat_offsets_loaded,
720 &osd->link_xoff_rx, &nsd->link_xoff_rx);
721
722 /* No new LFC xoff rx */
723 if (!(nsd->link_xoff_rx - xoff))
724 return;
725
726 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 727 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 728 struct i40e_vsi *vsi = pf->vsi[v];
729
ddfda80f 730 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 731 continue;
732
733 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 734 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 735 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
736 }
737 }
738}
739
740/**
741 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
742 * @pf: the corresponding PF
743 *
744 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
745 **/
746static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
747{
748 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
749 struct i40e_hw_port_stats *nsd = &pf->stats;
750 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
751 struct i40e_dcbx_config *dcb_cfg;
752 struct i40e_hw *hw = &pf->hw;
753 u16 i, v;
754 u8 tc;
755
756 dcb_cfg = &hw->local_dcbx_config;
757
758 /* See if DCB enabled with PFC TC */
759 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
760 !(dcb_cfg->pfc.pfcenable)) {
761 i40e_update_link_xoff_rx(pf);
762 return;
763 }
764
765 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
766 u64 prio_xoff = nsd->priority_xoff_rx[i];
767 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
768 pf->stat_offsets_loaded,
769 &osd->priority_xoff_rx[i],
770 &nsd->priority_xoff_rx[i]);
771
772 /* No new PFC xoff rx */
773 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
774 continue;
775 /* Get the TC for given priority */
776 tc = dcb_cfg->etscfg.prioritytable[i];
777 xoff[tc] = true;
778 }
779
780 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 781 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 782 struct i40e_vsi *vsi = pf->vsi[v];
783
ddfda80f 784 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 785 continue;
786
787 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 788 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 789
790 tc = ring->dcb_tc;
791 if (xoff[tc])
792 clear_bit(__I40E_HANG_CHECK_ARMED,
793 &ring->state);
794 }
795 }
796}
797
798/**
7812fddc 799 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 800 * @vsi: the VSI to be updated
801 *
802 * There are a few instances where we store the same stat in a
803 * couple of different structs. This is partly because we have
804 * the netdev stats that need to be filled out, which is slightly
805 * different from the "eth_stats" defined by the chip and used in
7812fddc 806 * VF communications. We sort it out here.
41c445ff 807 **/
7812fddc 808static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 809{
810 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 811 struct rtnl_link_stats64 *ons;
812 struct rtnl_link_stats64 *ns; /* netdev stats */
813 struct i40e_eth_stats *oes;
814 struct i40e_eth_stats *es; /* device's eth stats */
815 u32 tx_restart, tx_busy;
bf00b376 816 struct i40e_ring *p;
41c445ff 817 u32 rx_page, rx_buf;
bf00b376
AA		 818 u64 bytes, packets;
819 unsigned int start;
41c445ff
JB		 820 u64 rx_p, rx_b;
821 u64 tx_p, tx_b;
41c445ff
JB		 822 u16 q;
823
824 if (test_bit(__I40E_DOWN, &vsi->state) ||
825 test_bit(__I40E_CONFIG_BUSY, &pf->state))
826 return;
827
828 ns = i40e_get_vsi_stats_struct(vsi);
829 ons = &vsi->net_stats_offsets;
830 es = &vsi->eth_stats;
831 oes = &vsi->eth_stats_offsets;
832
833 /* Gather up the netdev and vsi stats that the driver collects
834 * on the fly during packet processing
835 */
836 rx_b = rx_p = 0;
837 tx_b = tx_p = 0;
838 tx_restart = tx_busy = 0;
839 rx_page = 0;
840 rx_buf = 0;
980e9b11 841 rcu_read_lock();
41c445ff 842 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc
SN		 898/**
899 * i40e_update_pf_stats - Update the pf statistics counters.
900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
922 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->eth.tx_discards,
925 &nsd->eth.tx_discards);
41c445ff 926
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
928 I40E_GLPRT_UPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_unicast,
931 &nsd->eth.rx_unicast);
7812fddc
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
933 I40E_GLPRT_MPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_multicast,
936 &nsd->eth.rx_multicast);
532d283d
SN		 937 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
938 I40E_GLPRT_BPRCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.rx_broadcast,
941 &nsd->eth.rx_broadcast);
942 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
943 I40E_GLPRT_UPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_unicast,
946 &nsd->eth.tx_unicast);
947 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
948 I40E_GLPRT_MPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_multicast,
951 &nsd->eth.tx_multicast);
952 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
953 I40E_GLPRT_BPTCL(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->eth.tx_broadcast,
956 &nsd->eth.tx_broadcast);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->tx_dropped_link_down,
961 &nsd->tx_dropped_link_down);
41c445ff 962
7812fddc
SN		 963 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->crc_errors, &nsd->crc_errors);
41c445ff 966
7812fddc
SN		 967 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 970
7812fddc
SN		 971 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->mac_local_faults,
974 &nsd->mac_local_faults);
975 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->mac_remote_faults,
978 &nsd->mac_remote_faults);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->rx_length_errors,
983 &nsd->rx_length_errors);
41c445ff 984
7812fddc
SN		 985 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->link_xon_rx, &nsd->link_xon_rx);
988 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xon_tx, &nsd->link_xon_tx);
991 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
992 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 995
7812fddc
SN		 996 for (i = 0; i < 8; i++) {
997 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_rx[i],
1000 &nsd->priority_xon_rx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xon_tx[i],
1004 &nsd->priority_xon_tx[i]);
1005 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xoff_tx[i],
1008 &nsd->priority_xoff_tx[i]);
1009 i40e_stat_update32(hw,
1010 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1011 pf->stat_offsets_loaded,
7812fddc
SN		 1012 &osd->priority_xon_2_xoff[i],
1013 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1014 }
1015
7812fddc
SN		 1016 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1017 I40E_GLPRT_PRC64L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_64, &nsd->rx_size_64);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1021 I40E_GLPRT_PRC127L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_127, &nsd->rx_size_127);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1025 I40E_GLPRT_PRC255L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_255, &nsd->rx_size_255);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1029 I40E_GLPRT_PRC511L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_511, &nsd->rx_size_511);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1033 I40E_GLPRT_PRC1023L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1023, &nsd->rx_size_1023);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1037 I40E_GLPRT_PRC1522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_1522, &nsd->rx_size_1522);
1040 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1041 I40E_GLPRT_PRC9522L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->rx_size_big, &nsd->rx_size_big);
1044
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1046 I40E_GLPRT_PTC64L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_64, &nsd->tx_size_64);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1050 I40E_GLPRT_PTC127L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_127, &nsd->tx_size_127);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1054 I40E_GLPRT_PTC255L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_255, &nsd->tx_size_255);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1058 I40E_GLPRT_PTC511L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_511, &nsd->tx_size_511);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1062 I40E_GLPRT_PTC1023L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1023, &nsd->tx_size_1023);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1066 I40E_GLPRT_PTC1522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_1522, &nsd->tx_size_1522);
1069 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1070 I40E_GLPRT_PTC9522L(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->tx_size_big, &nsd->tx_size_big);
1073
1074 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1075 pf->stat_offsets_loaded,
1076 &osd->rx_undersize, &nsd->rx_undersize);
1077 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1078 pf->stat_offsets_loaded,
1079 &osd->rx_fragments, &nsd->rx_fragments);
1080 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_oversize, &nsd->rx_oversize);
1083 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_jabber, &nsd->rx_jabber);
1086
433c47de
ASJ		 1087 /* FDIR stats */
1088 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1089 pf->stat_offsets_loaded,
1090 &osd->fd_atr_match, &nsd->fd_atr_match);
1091 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1092 pf->stat_offsets_loaded,
1093 &osd->fd_sb_match, &nsd->fd_sb_match);
1094
7812fddc
SN		 1095 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1096 nsd->tx_lpi_status =
1097 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1098 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1099 nsd->rx_lpi_status =
1100 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1101 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1102 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1103 pf->stat_offsets_loaded,
1104 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1105 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1106 pf->stat_offsets_loaded,
1107 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1108
41c445ff
JB		 1109 pf->stat_offsets_loaded = true;
1110}
1111
7812fddc
SN		 1112/**
1113 * i40e_update_stats - Update the various statistics counters.
1114 * @vsi: the VSI to be updated
1115 *
1116 * Update the various stats for this VSI and its related entities.
1117 **/
1118void i40e_update_stats(struct i40e_vsi *vsi)
1119{
1120 struct i40e_pf *pf = vsi->back;
1121
1122 if (vsi == pf->vsi[pf->lan_vsi])
1123 i40e_update_pf_stats(pf);
1124
1125 i40e_update_vsi_stats(vsi);
38e00438
VD		 1126#ifdef I40E_FCOE
1127 i40e_update_fcoe_stats(vsi);
1128#endif
7812fddc
SN		 1129}
1130
41c445ff
JB		 1131/**
1132 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1133 * @vsi: the VSI to be searched
1134 * @macaddr: the MAC address
1135 * @vlan: the vlan
1136 * @is_vf: make sure its a vf filter, else doesn't matter
1137 * @is_netdev: make sure its a netdev filter, else doesn't matter
1138 *
1139 * Returns ptr to the filter object or NULL
1140 **/
1141static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1142 u8 *macaddr, s16 vlan,
1143 bool is_vf, bool is_netdev)
1144{
1145 struct i40e_mac_filter *f;
1146
1147 if (!vsi || !macaddr)
1148 return NULL;
1149
1150 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1151 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1152 (vlan == f->vlan) &&
1153 (!is_vf || f->is_vf) &&
1154 (!is_netdev || f->is_netdev))
1155 return f;
1156 }
1157 return NULL;
1158}
1159
1160/**
1161 * i40e_find_mac - Find a mac addr in the macvlan filters list
1162 * @vsi: the VSI to be searched
1163 * @macaddr: the MAC address we are searching for
1164 * @is_vf: make sure its a vf filter, else doesn't matter
1165 * @is_netdev: make sure its a netdev filter, else doesn't matter
1166 *
1167 * Returns the first filter with the provided MAC address or NULL if
1168 * MAC address was not found
1169 **/
1170struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1171 bool is_vf, bool is_netdev)
1172{
1173 struct i40e_mac_filter *f;
1174
1175 if (!vsi || !macaddr)
1176 return NULL;
1177
1178 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1179 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1180 (!is_vf || f->is_vf) &&
1181 (!is_netdev || f->is_netdev))
1182 return f;
1183 }
1184 return NULL;
1185}
1186
1187/**
1188 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1189 * @vsi: the VSI to be searched
1190 *
1191 * Returns true if VSI is in vlan mode or false otherwise
1192 **/
1193bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1194{
1195 struct i40e_mac_filter *f;
1196
1197 /* Only -1 for all the filters denotes not in vlan mode
1198 * so we have to go through all the list in order to make sure
1199 */
1200 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1201 if (f->vlan >= 0)
1202 return true;
1203 }
1204
1205 return false;
1206}
1207
1208/**
1209 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1210 * @vsi: the VSI to be searched
1211 * @macaddr: the mac address to be filtered
1212 * @is_vf: true if it is a vf
1213 * @is_netdev: true if it is a netdev
1214 *
1215 * Goes through all the macvlan filters and adds a
1216 * macvlan filter for each unique vlan that already exists
1217 *
1218 * Returns first filter found on success, else NULL
1219 **/
1220struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1221 bool is_vf, bool is_netdev)
1222{
1223 struct i40e_mac_filter *f;
1224
1225 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1226 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1227 is_vf, is_netdev)) {
1228 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1229 is_vf, is_netdev))
41c445ff
JB		 1230 return NULL;
1231 }
1232 }
1233
1234 return list_first_entry_or_null(&vsi->mac_filter_list,
1235 struct i40e_mac_filter, list);
1236}
1237
8c27d42e
GR		 1238/**
1239 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1240 * @vsi: the PF Main VSI - inappropriate for any other VSI
1241 * @macaddr: the MAC address
30650cc5
SN		 1242 *
1243 * Some older firmware configurations set up a default promiscuous VLAN
1244 * filter that needs to be removed.
8c27d42e 1245 **/
30650cc5 1246static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1247{
1248 struct i40e_aqc_remove_macvlan_element_data element;
1249 struct i40e_pf *pf = vsi->back;
1250 i40e_status aq_ret;
1251
1252 /* Only appropriate for the PF main VSI */
1253 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1254 return -EINVAL;
8c27d42e 1255
30650cc5 1256 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1257 ether_addr_copy(element.mac_addr, macaddr);
1258 element.vlan_tag = 0;
1259 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1260 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1261 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1262 if (aq_ret)
30650cc5
SN		 1263 return -ENOENT;
1264
1265 return 0;
8c27d42e
GR		 1266}
1267
41c445ff
JB		 1268/**
1269 * i40e_add_filter - Add a mac/vlan filter to the VSI
1270 * @vsi: the VSI to be searched
1271 * @macaddr: the MAC address
1272 * @vlan: the vlan
1273 * @is_vf: make sure its a vf filter, else doesn't matter
1274 * @is_netdev: make sure its a netdev filter, else doesn't matter
1275 *
1276 * Returns ptr to the filter object or NULL when no memory available.
1277 **/
1278struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1279 u8 *macaddr, s16 vlan,
1280 bool is_vf, bool is_netdev)
1281{
1282 struct i40e_mac_filter *f;
1283
1284 if (!vsi || !macaddr)
1285 return NULL;
1286
1287 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1288 if (!f) {
1289 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1290 if (!f)
1291 goto add_filter_out;
1292
9a173901 1293 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1294 f->vlan = vlan;
1295 f->changed = true;
1296
1297 INIT_LIST_HEAD(&f->list);
1298 list_add(&f->list, &vsi->mac_filter_list);
1299 }
1300
1301 /* increment counter and add a new flag if needed */
1302 if (is_vf) {
1303 if (!f->is_vf) {
1304 f->is_vf = true;
1305 f->counter++;
1306 }
1307 } else if (is_netdev) {
1308 if (!f->is_netdev) {
1309 f->is_netdev = true;
1310 f->counter++;
1311 }
1312 } else {
1313 f->counter++;
1314 }
1315
1316 /* changed tells sync_filters_subtask to
1317 * push the filter down to the firmware
1318 */
1319 if (f->changed) {
1320 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1321 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1322 }
1323
1324add_filter_out:
1325 return f;
1326}
1327
1328/**
1329 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1330 * @vsi: the VSI to be searched
1331 * @macaddr: the MAC address
1332 * @vlan: the vlan
1333 * @is_vf: make sure it's a vf filter, else doesn't matter
1334 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1335 **/
1336void i40e_del_filter(struct i40e_vsi *vsi,
1337 u8 *macaddr, s16 vlan,
1338 bool is_vf, bool is_netdev)
1339{
1340 struct i40e_mac_filter *f;
1341
1342 if (!vsi || !macaddr)
1343 return;
1344
1345 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1346 if (!f || f->counter == 0)
1347 return;
1348
1349 if (is_vf) {
1350 if (f->is_vf) {
1351 f->is_vf = false;
1352 f->counter--;
1353 }
1354 } else if (is_netdev) {
1355 if (f->is_netdev) {
1356 f->is_netdev = false;
1357 f->counter--;
1358 }
1359 } else {
1360 /* make sure we don't remove a filter in use by vf or netdev */
1361 int min_f = 0;
1362 min_f += (f->is_vf ? 1 : 0);
1363 min_f += (f->is_netdev ? 1 : 0);
1364
1365 if (f->counter > min_f)
1366 f->counter--;
1367 }
1368
1369 /* counter == 0 tells sync_filters_subtask to
1370 * remove the filter from the firmware's list
1371 */
1372 if (f->counter == 0) {
1373 f->changed = true;
1374 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1375 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1376 }
1377}
1378
1379/**
1380 * i40e_set_mac - NDO callback to set mac address
1381 * @netdev: network interface device structure
1382 * @p: pointer to an address structure
1383 *
1384 * Returns 0 on success, negative on failure
1385 **/
38e00438
VD		 1386#ifdef I40E_FCOE
1387int i40e_set_mac(struct net_device *netdev, void *p)
1388#else
41c445ff 1389static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1390#endif
41c445ff
JB		 1391{
1392 struct i40e_netdev_priv *np = netdev_priv(netdev);
1393 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1394 struct i40e_pf *pf = vsi->back;
1395 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1396 struct sockaddr *addr = p;
1397 struct i40e_mac_filter *f;
1398
1399 if (!is_valid_ether_addr(addr->sa_data))
1400 return -EADDRNOTAVAIL;
1401
30650cc5
SN		 1402 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1403 netdev_info(netdev, "already using mac address %pM\n",
1404 addr->sa_data);
1405 return 0;
1406 }
41c445ff 1407
80f6428f
ASJ		 1408 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1409 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1410 return -EADDRNOTAVAIL;
1411
30650cc5
SN		 1412 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1413 netdev_info(netdev, "returning to hw mac address %pM\n",
1414 hw->mac.addr);
1415 else
1416 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1417
41c445ff
JB		 1418 if (vsi->type == I40E_VSI_MAIN) {
1419 i40e_status ret;
1420 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1421 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1422 addr->sa_data, NULL);
1423 if (ret) {
1424 netdev_info(netdev,
1425 "Addr change for Main VSI failed: %d\n",
1426 ret);
1427 return -EADDRNOTAVAIL;
1428 }
41c445ff
JB		 1429 }
1430
30650cc5
SN		 1431 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1432 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1433
30650cc5
SN		 1434 memset(&element, 0, sizeof(element));
1435 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1436 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1437 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1438 } else {
6c8ad1ba
SN		 1439 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1440 false, false);
6c8ad1ba 1441 }
41c445ff 1442
30650cc5
SN		 1443 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1444 struct i40e_aqc_add_macvlan_element_data element;
1445
1446 memset(&element, 0, sizeof(element));
1447 ether_addr_copy(element.mac_addr, hw->mac.addr);
1448 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1449 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1450 } else {
1451 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1452 false, false);
1453 if (f)
1454 f->is_laa = true;
1455 }
1456
1457 i40e_sync_vsi_filters(vsi);
1458 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1459
1460 return 0;
1461}
1462
1463/**
1464 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1465 * @vsi: the VSI being setup
1466 * @ctxt: VSI context structure
1467 * @enabled_tc: Enabled TCs bitmap
1468 * @is_add: True if called before Add VSI
1469 *
1470 * Setup VSI queue mapping for enabled traffic classes.
1471 **/
38e00438
VD		 1472#ifdef I40E_FCOE
1473void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1474 struct i40e_vsi_context *ctxt,
1475 u8 enabled_tc,
1476 bool is_add)
1477#else
41c445ff
JB		 1478static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1479 struct i40e_vsi_context *ctxt,
1480 u8 enabled_tc,
1481 bool is_add)
38e00438 1482#endif
41c445ff
JB		 1483{
1484 struct i40e_pf *pf = vsi->back;
1485 u16 sections = 0;
1486 u8 netdev_tc = 0;
1487 u16 numtc = 0;
1488 u16 qcount;
1489 u8 offset;
1490 u16 qmap;
1491 int i;
4e3b35b0 1492 u16 num_tc_qps = 0;
41c445ff
JB		 1493
1494 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1495 offset = 0;
1496
1497 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1498 /* Find numtc from enabled TC bitmap */
1499 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1500 if (enabled_tc & (1 << i)) /* TC is enabled */
1501 numtc++;
1502 }
1503 if (!numtc) {
1504 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1505 numtc = 1;
1506 }
1507 } else {
1508 /* At least TC0 is enabled in case of non-DCB case */
1509 numtc = 1;
1510 }
1511
1512 vsi->tc_config.numtc = numtc;
1513 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1514 /* Number of queues per enabled TC */
eb051afe 1515 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1516 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1517
1518 /* Setup queue offset/count for all TCs for given VSI */
1519 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1520 /* See if the given TC is enabled for the given VSI */
1521 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1522 int pow, num_qps;
1523
41c445ff
JB		 1524 switch (vsi->type) {
1525 case I40E_VSI_MAIN:
4e3b35b0 1526 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1527 break;
38e00438
VD		 1528#ifdef I40E_FCOE
1529 case I40E_VSI_FCOE:
1530 qcount = num_tc_qps;
1531 break;
1532#endif
41c445ff
JB		 1533 case I40E_VSI_FDIR:
1534 case I40E_VSI_SRIOV:
1535 case I40E_VSI_VMDQ2:
1536 default:
4e3b35b0 1537 qcount = num_tc_qps;
41c445ff
JB		 1538 WARN_ON(i != 0);
1539 break;
1540 }
4e3b35b0
NP		 1541 vsi->tc_config.tc_info[i].qoffset = offset;
1542 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1543
1544 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1545 num_qps = qcount;
41c445ff 1546 pow = 0;
4e3b35b0 1547 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1548 pow++;
1549 num_qps >>= 1;
1550 }
1551
1552 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1553 qmap =
1554 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1555 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1556
4e3b35b0 1557 offset += qcount;
41c445ff
JB		 1558 } else {
1559 /* TC is not enabled so set the offset to
1560 * default queue and allocate one queue
1561 * for the given TC.
1562 */
1563 vsi->tc_config.tc_info[i].qoffset = 0;
1564 vsi->tc_config.tc_info[i].qcount = 1;
1565 vsi->tc_config.tc_info[i].netdev_tc = 0;
1566
1567 qmap = 0;
1568 }
1569 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1570 }
1571
1572 /* Set actual Tx/Rx queue pairs */
1573 vsi->num_queue_pairs = offset;
1574
1575 /* Scheduler section valid can only be set for ADD VSI */
1576 if (is_add) {
1577 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1578
1579 ctxt->info.up_enable_bits = enabled_tc;
1580 }
1581 if (vsi->type == I40E_VSI_SRIOV) {
1582 ctxt->info.mapping_flags |=
1583 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1584 for (i = 0; i < vsi->num_queue_pairs; i++)
1585 ctxt->info.queue_mapping[i] =
1586 cpu_to_le16(vsi->base_queue + i);
1587 } else {
1588 ctxt->info.mapping_flags |=
1589 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1590 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1591 }
1592 ctxt->info.valid_sections |= cpu_to_le16(sections);
1593}
1594
1595/**
1596 * i40e_set_rx_mode - NDO callback to set the netdev filters
1597 * @netdev: network interface device structure
1598 **/
38e00438
VD		 1599#ifdef I40E_FCOE
1600void i40e_set_rx_mode(struct net_device *netdev)
1601#else
41c445ff 1602static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1603#endif
41c445ff
JB		 1604{
1605 struct i40e_netdev_priv *np = netdev_priv(netdev);
1606 struct i40e_mac_filter *f, *ftmp;
1607 struct i40e_vsi *vsi = np->vsi;
1608 struct netdev_hw_addr *uca;
1609 struct netdev_hw_addr *mca;
1610 struct netdev_hw_addr *ha;
1611
1612 /* add addr if not already in the filter list */
1613 netdev_for_each_uc_addr(uca, netdev) {
1614 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1615 if (i40e_is_vsi_in_vlan(vsi))
1616 i40e_put_mac_in_vlan(vsi, uca->addr,
1617 false, true);
1618 else
1619 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1620 false, true);
1621 }
1622 }
1623
1624 netdev_for_each_mc_addr(mca, netdev) {
1625 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1626 if (i40e_is_vsi_in_vlan(vsi))
1627 i40e_put_mac_in_vlan(vsi, mca->addr,
1628 false, true);
1629 else
1630 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1631 false, true);
1632 }
1633 }
1634
1635 /* remove filter if not in netdev list */
1636 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1637 bool found = false;
1638
1639 if (!f->is_netdev)
1640 continue;
1641
1642 if (is_multicast_ether_addr(f->macaddr)) {
1643 netdev_for_each_mc_addr(mca, netdev) {
1644 if (ether_addr_equal(mca->addr, f->macaddr)) {
1645 found = true;
1646 break;
1647 }
1648 }
1649 } else {
1650 netdev_for_each_uc_addr(uca, netdev) {
1651 if (ether_addr_equal(uca->addr, f->macaddr)) {
1652 found = true;
1653 break;
1654 }
1655 }
1656
1657 for_each_dev_addr(netdev, ha) {
1658 if (ether_addr_equal(ha->addr, f->macaddr)) {
1659 found = true;
1660 break;
1661 }
1662 }
1663 }
1664 if (!found)
1665 i40e_del_filter(
1666 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1667 }
1668
1669 /* check for other flag changes */
1670 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1671 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1672 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1673 }
1674}
1675
1676/**
1677 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1678 * @vsi: ptr to the VSI
1679 *
1680 * Push any outstanding VSI filter changes through the AdminQ.
1681 *
1682 * Returns 0 or error value
1683 **/
1684int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1685{
1686 struct i40e_mac_filter *f, *ftmp;
1687 bool promisc_forced_on = false;
1688 bool add_happened = false;
1689 int filter_list_len = 0;
1690 u32 changed_flags = 0;
dcae29be 1691 i40e_status aq_ret = 0;
41c445ff
JB		 1692 struct i40e_pf *pf;
1693 int num_add = 0;
1694 int num_del = 0;
1695 u16 cmd_flags;
1696
1697 /* empty array typed pointers, kcalloc later */
1698 struct i40e_aqc_add_macvlan_element_data *add_list;
1699 struct i40e_aqc_remove_macvlan_element_data *del_list;
1700
1701 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1702 usleep_range(1000, 2000);
1703 pf = vsi->back;
1704
1705 if (vsi->netdev) {
1706 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1707 vsi->current_netdev_flags = vsi->netdev->flags;
1708 }
1709
1710 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1711 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1712
1713 filter_list_len = pf->hw.aq.asq_buf_size /
1714 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1715 del_list = kcalloc(filter_list_len,
1716 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1717 GFP_KERNEL);
1718 if (!del_list)
1719 return -ENOMEM;
1720
1721 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1722 if (!f->changed)
1723 continue;
1724
1725 if (f->counter != 0)
1726 continue;
1727 f->changed = false;
1728 cmd_flags = 0;
1729
1730 /* add to delete list */
9a173901 1731 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1732 del_list[num_del].vlan_tag =
1733 cpu_to_le16((u16)(f->vlan ==
1734 I40E_VLAN_ANY ? 0 : f->vlan));
1735
41c445ff
JB		 1736 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1737 del_list[num_del].flags = cmd_flags;
1738 num_del++;
1739
1740 /* unlink from filter list */
1741 list_del(&f->list);
1742 kfree(f);
1743
1744 /* flush a full buffer */
1745 if (num_del == filter_list_len) {
dcae29be 1746 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1747 vsi->seid, del_list, num_del,
1748 NULL);
1749 num_del = 0;
1750 memset(del_list, 0, sizeof(*del_list));
1751
fdfe9cbe
SN		 1752 if (aq_ret &&
1753 pf->hw.aq.asq_last_status !=
1754 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1755 dev_info(&pf->pdev->dev,
1756 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1757 aq_ret,
41c445ff
JB		 1758 pf->hw.aq.asq_last_status);
1759 }
1760 }
1761 if (num_del) {
dcae29be 1762 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1763 del_list, num_del, NULL);
1764 num_del = 0;
1765
fdfe9cbe
SN		 1766 if (aq_ret &&
1767 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1768 dev_info(&pf->pdev->dev,
1769 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1770 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1771 }
1772
1773 kfree(del_list);
1774 del_list = NULL;
1775
1776 /* do all the adds now */
1777 filter_list_len = pf->hw.aq.asq_buf_size /
1778 sizeof(struct i40e_aqc_add_macvlan_element_data),
1779 add_list = kcalloc(filter_list_len,
1780 sizeof(struct i40e_aqc_add_macvlan_element_data),
1781 GFP_KERNEL);
1782 if (!add_list)
1783 return -ENOMEM;
1784
1785 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1786 if (!f->changed)
1787 continue;
1788
1789 if (f->counter == 0)
1790 continue;
1791 f->changed = false;
1792 add_happened = true;
1793 cmd_flags = 0;
1794
1795 /* add to add array */
9a173901 1796 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1797 add_list[num_add].vlan_tag =
1798 cpu_to_le16(
1799 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1800 add_list[num_add].queue_number = 0;
1801
1802 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1803 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1804 num_add++;
1805
1806 /* flush a full buffer */
1807 if (num_add == filter_list_len) {
dcae29be
JB		 1808 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1809 add_list, num_add,
1810 NULL);
41c445ff
JB		 1811 num_add = 0;
1812
dcae29be 1813 if (aq_ret)
41c445ff
JB		 1814 break;
1815 memset(add_list, 0, sizeof(*add_list));
1816 }
1817 }
1818 if (num_add) {
dcae29be
JB		 1819 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1820 add_list, num_add, NULL);
41c445ff
JB		 1821 num_add = 0;
1822 }
1823 kfree(add_list);
1824 add_list = NULL;
1825
30650cc5
SN		 1826 if (add_happened && aq_ret &&
1827 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1828 dev_info(&pf->pdev->dev,
1829 "add filter failed, err %d, aq_err %d\n",
dcae29be 1830 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1831 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1832 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1833 &vsi->state)) {
1834 promisc_forced_on = true;
1835 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1836 &vsi->state);
1837 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1838 }
1839 }
1840 }
1841
1842 /* check for changes in promiscuous modes */
1843 if (changed_flags & IFF_ALLMULTI) {
1844 bool cur_multipromisc;
1845 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1846 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1847 vsi->seid,
1848 cur_multipromisc,
1849 NULL);
1850 if (aq_ret)
41c445ff
JB		 1851 dev_info(&pf->pdev->dev,
1852 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1853 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1854 }
1855 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1856 bool cur_promisc;
1857 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1858 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1859 &vsi->state));
dcae29be
JB		 1860 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1861 vsi->seid,
1862 cur_promisc, NULL);
1863 if (aq_ret)
41c445ff
JB		 1864 dev_info(&pf->pdev->dev,
1865 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1866 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1867 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1868 vsi->seid,
1869 cur_promisc, NULL);
1870 if (aq_ret)
1871 dev_info(&pf->pdev->dev,
1872 "set brdcast promisc failed, err %d, aq_err %d\n",
1873 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1874 }
1875
1876 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1877 return 0;
1878}
1879
1880/**
1881 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1882 * @pf: board private structure
1883 **/
1884static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1885{
1886 int v;
1887
1888 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1889 return;
1890 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1891
505682cd 1892 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1893 if (pf->vsi[v] &&
1894 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1895 i40e_sync_vsi_filters(pf->vsi[v]);
1896 }
1897}
1898
1899/**
1900 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1901 * @netdev: network interface device structure
1902 * @new_mtu: new value for maximum frame size
1903 *
1904 * Returns 0 on success, negative on failure
1905 **/
1906static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1907{
1908 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1909 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1910 struct i40e_vsi *vsi = np->vsi;
1911
1912 /* MTU < 68 is an error and causes problems on some kernels */
1913 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1914 return -EINVAL;
1915
1916 netdev_info(netdev, "changing MTU from %d to %d\n",
1917 netdev->mtu, new_mtu);
1918 netdev->mtu = new_mtu;
1919 if (netif_running(netdev))
1920 i40e_vsi_reinit_locked(vsi);
1921
1922 return 0;
1923}
1924
beb0dff1
JK		 1925/**
1926 * i40e_ioctl - Access the hwtstamp interface
1927 * @netdev: network interface device structure
1928 * @ifr: interface request data
1929 * @cmd: ioctl command
1930 **/
1931int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1932{
1933 struct i40e_netdev_priv *np = netdev_priv(netdev);
1934 struct i40e_pf *pf = np->vsi->back;
1935
1936 switch (cmd) {
1937 case SIOCGHWTSTAMP:
1938 return i40e_ptp_get_ts_config(pf, ifr);
1939 case SIOCSHWTSTAMP:
1940 return i40e_ptp_set_ts_config(pf, ifr);
1941 default:
1942 return -EOPNOTSUPP;
1943 }
1944}
1945
41c445ff
JB		 1946/**
1947 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1948 * @vsi: the vsi being adjusted
1949 **/
1950void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1951{
1952 struct i40e_vsi_context ctxt;
1953 i40e_status ret;
1954
1955 if ((vsi->info.valid_sections &
1956 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1957 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1958 return; /* already enabled */
1959
1960 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1961 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1962 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1963
1964 ctxt.seid = vsi->seid;
1965 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1966 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1967 if (ret) {
1968 dev_info(&vsi->back->pdev->dev,
1969 "%s: update vsi failed, aq_err=%d\n",
1970 __func__, vsi->back->hw.aq.asq_last_status);
1971 }
1972}
1973
1974/**
1975 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1976 * @vsi: the vsi being adjusted
1977 **/
1978void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1979{
1980 struct i40e_vsi_context ctxt;
1981 i40e_status ret;
1982
1983 if ((vsi->info.valid_sections &
1984 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1985 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1986 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1987 return; /* already disabled */
1988
1989 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1990 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1991 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1992
1993 ctxt.seid = vsi->seid;
1994 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1995 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1996 if (ret) {
1997 dev_info(&vsi->back->pdev->dev,
1998 "%s: update vsi failed, aq_err=%d\n",
1999 __func__, vsi->back->hw.aq.asq_last_status);
2000 }
2001}
2002
2003/**
2004 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2005 * @netdev: network interface to be adjusted
2006 * @features: netdev features to test if VLAN offload is enabled or not
2007 **/
2008static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2009{
2010 struct i40e_netdev_priv *np = netdev_priv(netdev);
2011 struct i40e_vsi *vsi = np->vsi;
2012
2013 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2014 i40e_vlan_stripping_enable(vsi);
2015 else
2016 i40e_vlan_stripping_disable(vsi);
2017}
2018
2019/**
2020 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2021 * @vsi: the vsi being configured
2022 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2023 **/
2024int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2025{
2026 struct i40e_mac_filter *f, *add_f;
2027 bool is_netdev, is_vf;
41c445ff
JB		 2028
2029 is_vf = (vsi->type == I40E_VSI_SRIOV);
2030 is_netdev = !!(vsi->netdev);
2031
2032 if (is_netdev) {
2033 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2034 is_vf, is_netdev);
2035 if (!add_f) {
2036 dev_info(&vsi->back->pdev->dev,
2037 "Could not add vlan filter %d for %pM\n",
2038 vid, vsi->netdev->dev_addr);
2039 return -ENOMEM;
2040 }
2041 }
2042
2043 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2044 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2045 if (!add_f) {
2046 dev_info(&vsi->back->pdev->dev,
2047 "Could not add vlan filter %d for %pM\n",
2048 vid, f->macaddr);
2049 return -ENOMEM;
2050 }
2051 }
2052
41c445ff
JB		 2053 /* Now if we add a vlan tag, make sure to check if it is the first
2054 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2055 * with 0, so we now accept untagged and specified tagged traffic
2056 * (and not any taged and untagged)
2057 */
2058 if (vid > 0) {
2059 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2060 I40E_VLAN_ANY,
2061 is_vf, is_netdev)) {
2062 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2063 I40E_VLAN_ANY, is_vf, is_netdev);
2064 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2065 is_vf, is_netdev);
2066 if (!add_f) {
2067 dev_info(&vsi->back->pdev->dev,
2068 "Could not add filter 0 for %pM\n",
2069 vsi->netdev->dev_addr);
2070 return -ENOMEM;
2071 }
2072 }
8d82a7c5 2073 }
41c445ff 2074
8d82a7c5
GR		 2075 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2076 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2077 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2078 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2079 is_vf, is_netdev)) {
2080 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2081 is_vf, is_netdev);
2082 add_f = i40e_add_filter(vsi, f->macaddr,
2083 0, is_vf, is_netdev);
2084 if (!add_f) {
2085 dev_info(&vsi->back->pdev->dev,
2086 "Could not add filter 0 for %pM\n",
2087 f->macaddr);
2088 return -ENOMEM;
2089 }
2090 }
2091 }
41c445ff
JB		 2092 }
2093
80f6428f
ASJ		 2094 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2095 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2096 return 0;
2097
2098 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2099}
2100
2101/**
2102 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2103 * @vsi: the vsi being configured
2104 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2105 *
2106 * Return: 0 on success or negative otherwise
41c445ff
JB		 2107 **/
2108int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2109{
2110 struct net_device *netdev = vsi->netdev;
2111 struct i40e_mac_filter *f, *add_f;
2112 bool is_vf, is_netdev;
2113 int filter_count = 0;
41c445ff
JB		 2114
2115 is_vf = (vsi->type == I40E_VSI_SRIOV);
2116 is_netdev = !!(netdev);
2117
2118 if (is_netdev)
2119 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2120
2121 list_for_each_entry(f, &vsi->mac_filter_list, list)
2122 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2123
41c445ff
JB		 2124 /* go through all the filters for this VSI and if there is only
2125 * vid == 0 it means there are no other filters, so vid 0 must
2126 * be replaced with -1. This signifies that we should from now
2127 * on accept any traffic (with any tag present, or untagged)
2128 */
2129 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2130 if (is_netdev) {
2131 if (f->vlan &&
2132 ether_addr_equal(netdev->dev_addr, f->macaddr))
2133 filter_count++;
2134 }
2135
2136 if (f->vlan)
2137 filter_count++;
2138 }
2139
2140 if (!filter_count && is_netdev) {
2141 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2142 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2143 is_vf, is_netdev);
2144 if (!f) {
2145 dev_info(&vsi->back->pdev->dev,
2146 "Could not add filter %d for %pM\n",
2147 I40E_VLAN_ANY, netdev->dev_addr);
2148 return -ENOMEM;
2149 }
2150 }
2151
2152 if (!filter_count) {
2153 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2154 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2155 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2156 is_vf, is_netdev);
2157 if (!add_f) {
2158 dev_info(&vsi->back->pdev->dev,
2159 "Could not add filter %d for %pM\n",
2160 I40E_VLAN_ANY, f->macaddr);
2161 return -ENOMEM;
2162 }
2163 }
2164 }
2165
80f6428f
ASJ		 2166 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2167 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2168 return 0;
2169
41c445ff
JB		 2170 return i40e_sync_vsi_filters(vsi);
2171}
2172
2173/**
2174 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2175 * @netdev: network interface to be adjusted
2176 * @vid: vlan id to be added
078b5876
JB		 2177 *
2178 * net_device_ops implementation for adding vlan ids
41c445ff 2179 **/
38e00438
VD		 2180#ifdef I40E_FCOE
2181int i40e_vlan_rx_add_vid(struct net_device *netdev,
2182 __always_unused __be16 proto, u16 vid)
2183#else
41c445ff
JB		 2184static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2185 __always_unused __be16 proto, u16 vid)
38e00438 2186#endif
41c445ff
JB		 2187{
2188 struct i40e_netdev_priv *np = netdev_priv(netdev);
2189 struct i40e_vsi *vsi = np->vsi;
078b5876 2190 int ret = 0;
41c445ff
JB		 2191
2192 if (vid > 4095)
078b5876
JB		 2193 return -EINVAL;
2194
2195 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2196
6982d429
ASJ		 2197 /* If the network stack called us with vid = 0 then
2198 * it is asking to receive priority tagged packets with
2199 * vlan id 0. Our HW receives them by default when configured
2200 * to receive untagged packets so there is no need to add an
2201 * extra filter for vlan 0 tagged packets.
41c445ff 2202 */
6982d429
ASJ		 2203 if (vid)
2204 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2205
078b5876
JB		 2206 if (!ret && (vid < VLAN_N_VID))
2207 set_bit(vid, vsi->active_vlans);
41c445ff 2208
078b5876 2209 return ret;
41c445ff
JB		 2210}
2211
2212/**
2213 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2214 * @netdev: network interface to be adjusted
2215 * @vid: vlan id to be removed
078b5876 2216 *
fdfd943e 2217 * net_device_ops implementation for removing vlan ids
41c445ff 2218 **/
38e00438
VD		 2219#ifdef I40E_FCOE
2220int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2221 __always_unused __be16 proto, u16 vid)
2222#else
41c445ff
JB		 2223static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2224 __always_unused __be16 proto, u16 vid)
38e00438 2225#endif
41c445ff
JB		 2226{
2227 struct i40e_netdev_priv *np = netdev_priv(netdev);
2228 struct i40e_vsi *vsi = np->vsi;
2229
078b5876
JB		 2230 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2231
41c445ff
JB		 2232 /* return code is ignored as there is nothing a user
2233 * can do about failure to remove and a log message was
078b5876 2234 * already printed from the other function
41c445ff
JB		 2235 */
2236 i40e_vsi_kill_vlan(vsi, vid);
2237
2238 clear_bit(vid, vsi->active_vlans);
078b5876 2239
41c445ff
JB		 2240 return 0;
2241}
2242
2243/**
2244 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2245 * @vsi: the vsi being brought back up
2246 **/
2247static void i40e_restore_vlan(struct i40e_vsi *vsi)
2248{
2249 u16 vid;
2250
2251 if (!vsi->netdev)
2252 return;
2253
2254 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2255
2256 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2257 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2258 vid);
2259}
2260
2261/**
2262 * i40e_vsi_add_pvid - Add pvid for the VSI
2263 * @vsi: the vsi being adjusted
2264 * @vid: the vlan id to set as a PVID
2265 **/
dcae29be 2266int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2267{
2268 struct i40e_vsi_context ctxt;
dcae29be 2269 i40e_status aq_ret;
41c445ff
JB		 2270
2271 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2272 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2273 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2274 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2275 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2276
2277 ctxt.seid = vsi->seid;
2278 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2279 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2280 if (aq_ret) {
41c445ff
JB		 2281 dev_info(&vsi->back->pdev->dev,
2282 "%s: update vsi failed, aq_err=%d\n",
2283 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2284 return -ENOENT;
41c445ff
JB		 2285 }
2286
dcae29be 2287 return 0;
41c445ff
JB		 2288}
2289
2290/**
2291 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2292 * @vsi: the vsi being adjusted
2293 *
2294 * Just use the vlan_rx_register() service to put it back to normal
2295 **/
2296void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2297{
6c12fcbf
GR		 2298 i40e_vlan_stripping_disable(vsi);
2299
41c445ff 2300 vsi->info.pvid = 0;
41c445ff
JB		 2301}
2302
2303/**
2304 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2305 * @vsi: ptr to the VSI
2306 *
2307 * If this function returns with an error, then it's possible one or
2308 * more of the rings is populated (while the rest are not). It is the
2309 * callers duty to clean those orphaned rings.
2310 *
2311 * Return 0 on success, negative on failure
2312 **/
2313static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2314{
2315 int i, err = 0;
2316
2317 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2318 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2319
2320 return err;
2321}
2322
2323/**
2324 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2325 * @vsi: ptr to the VSI
2326 *
2327 * Free VSI's transmit software resources
2328 **/
2329static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2330{
2331 int i;
2332
8e9dca53
GR		 2333 if (!vsi->tx_rings)
2334 return;
2335
41c445ff 2336 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2337 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2338 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2339}
2340
2341/**
2342 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2343 * @vsi: ptr to the VSI
2344 *
2345 * If this function returns with an error, then it's possible one or
2346 * more of the rings is populated (while the rest are not). It is the
2347 * callers duty to clean those orphaned rings.
2348 *
2349 * Return 0 on success, negative on failure
2350 **/
2351static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2352{
2353 int i, err = 0;
2354
2355 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2356 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2357#ifdef I40E_FCOE
2358 i40e_fcoe_setup_ddp_resources(vsi);
2359#endif
41c445ff
JB		 2360 return err;
2361}
2362
2363/**
2364 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2365 * @vsi: ptr to the VSI
2366 *
2367 * Free all receive software resources
2368 **/
2369static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2370{
2371 int i;
2372
8e9dca53
GR		 2373 if (!vsi->rx_rings)
2374 return;
2375
41c445ff 2376 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2377 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2378 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2379#ifdef I40E_FCOE
2380 i40e_fcoe_free_ddp_resources(vsi);
2381#endif
41c445ff
JB		 2382}
2383
2384/**
2385 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2386 * @ring: The Tx ring to configure
2387 *
2388 * Configure the Tx descriptor ring in the HMC context.
2389 **/
2390static int i40e_configure_tx_ring(struct i40e_ring *ring)
2391{
2392 struct i40e_vsi *vsi = ring->vsi;
2393 u16 pf_q = vsi->base_queue + ring->queue_index;
2394 struct i40e_hw *hw = &vsi->back->hw;
2395 struct i40e_hmc_obj_txq tx_ctx;
2396 i40e_status err = 0;
2397 u32 qtx_ctl = 0;
2398
2399 /* some ATR related tx ring init */
60ea5f83 2400 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2401 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2402 ring->atr_count = 0;
2403 } else {
2404 ring->atr_sample_rate = 0;
2405 }
2406
2407 /* initialize XPS */
2408 if (ring->q_vector && ring->netdev &&
4e3b35b0 2409 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2410 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2411 netif_set_xps_queue(ring->netdev,
2412 &ring->q_vector->affinity_mask,
2413 ring->queue_index);
2414
2415 /* clear the context structure first */
2416 memset(&tx_ctx, 0, sizeof(tx_ctx));
2417
2418 tx_ctx.new_context = 1;
2419 tx_ctx.base = (ring->dma / 128);
2420 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2421 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2422 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2423#ifdef I40E_FCOE
2424 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2425#endif
beb0dff1 2426 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2427 /* FDIR VSI tx ring can still use RS bit and writebacks */
2428 if (vsi->type != I40E_VSI_FDIR)
2429 tx_ctx.head_wb_ena = 1;
2430 tx_ctx.head_wb_addr = ring->dma +
2431 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2432
2433 /* As part of VSI creation/update, FW allocates certain
2434 * Tx arbitration queue sets for each TC enabled for
2435 * the VSI. The FW returns the handles to these queue
2436 * sets as part of the response buffer to Add VSI,
2437 * Update VSI, etc. AQ commands. It is expected that
2438 * these queue set handles be associated with the Tx
2439 * queues by the driver as part of the TX queue context
2440 * initialization. This has to be done regardless of
2441 * DCB as by default everything is mapped to TC0.
2442 */
2443 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2444 tx_ctx.rdylist_act = 0;
2445
2446 /* clear the context in the HMC */
2447 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2448 if (err) {
2449 dev_info(&vsi->back->pdev->dev,
2450 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2451 ring->queue_index, pf_q, err);
2452 return -ENOMEM;
2453 }
2454
2455 /* set the context in the HMC */
2456 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2457 if (err) {
2458 dev_info(&vsi->back->pdev->dev,
2459 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2460 ring->queue_index, pf_q, err);
2461 return -ENOMEM;
2462 }
2463
2464 /* Now associate this queue with this PCI function */
7a28d885 2465 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2466 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2467 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2468 I40E_QTX_CTL_VFVM_INDX_MASK;
2469 } else {
9d8bf547 2470 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2471 }
2472
13fd9774
SN		 2473 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2474 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2475 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2476 i40e_flush(hw);
2477
2478 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2479
2480 /* cache tail off for easier writes later */
2481 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2482
2483 return 0;
2484}
2485
2486/**
2487 * i40e_configure_rx_ring - Configure a receive ring context
2488 * @ring: The Rx ring to configure
2489 *
2490 * Configure the Rx descriptor ring in the HMC context.
2491 **/
2492static int i40e_configure_rx_ring(struct i40e_ring *ring)
2493{
2494 struct i40e_vsi *vsi = ring->vsi;
2495 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2496 u16 pf_q = vsi->base_queue + ring->queue_index;
2497 struct i40e_hw *hw = &vsi->back->hw;
2498 struct i40e_hmc_obj_rxq rx_ctx;
2499 i40e_status err = 0;
2500
2501 ring->state = 0;
2502
2503 /* clear the context structure first */
2504 memset(&rx_ctx, 0, sizeof(rx_ctx));
2505
2506 ring->rx_buf_len = vsi->rx_buf_len;
2507 ring->rx_hdr_len = vsi->rx_hdr_len;
2508
2509 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2510 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2511
2512 rx_ctx.base = (ring->dma / 128);
2513 rx_ctx.qlen = ring->count;
2514
2515 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2516 set_ring_16byte_desc_enabled(ring);
2517 rx_ctx.dsize = 0;
2518 } else {
2519 rx_ctx.dsize = 1;
2520 }
2521
2522 rx_ctx.dtype = vsi->dtype;
2523 if (vsi->dtype) {
2524 set_ring_ps_enabled(ring);
2525 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2526 I40E_RX_SPLIT_IP |
2527 I40E_RX_SPLIT_TCP_UDP |
2528 I40E_RX_SPLIT_SCTP;
2529 } else {
2530 rx_ctx.hsplit_0 = 0;
2531 }
2532
2533 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2534 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2535 if (hw->revision_id == 0)
2536 rx_ctx.lrxqthresh = 0;
2537 else
2538 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2539 rx_ctx.crcstrip = 1;
2540 rx_ctx.l2tsel = 1;
2541 rx_ctx.showiv = 1;
38e00438
VD		 2542#ifdef I40E_FCOE
2543 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2544#endif
acb3676b
CS		 2545 /* set the prefena field to 1 because the manual says to */
2546 rx_ctx.prefena = 1;
41c445ff
JB		 2547
2548 /* clear the context in the HMC */
2549 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2550 if (err) {
2551 dev_info(&vsi->back->pdev->dev,
2552 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2553 ring->queue_index, pf_q, err);
2554 return -ENOMEM;
2555 }
2556
2557 /* set the context in the HMC */
2558 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2559 if (err) {
2560 dev_info(&vsi->back->pdev->dev,
2561 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2562 ring->queue_index, pf_q, err);
2563 return -ENOMEM;
2564 }
2565
2566 /* cache tail for quicker writes, and clear the reg before use */
2567 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2568 writel(0, ring->tail);
2569
2570 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2571
2572 return 0;
2573}
2574
2575/**
2576 * i40e_vsi_configure_tx - Configure the VSI for Tx
2577 * @vsi: VSI structure describing this set of rings and resources
2578 *
2579 * Configure the Tx VSI for operation.
2580 **/
2581static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2582{
2583 int err = 0;
2584 u16 i;
2585
9f65e15b
AD		 2586 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2587 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2588
2589 return err;
2590}
2591
2592/**
2593 * i40e_vsi_configure_rx - Configure the VSI for Rx
2594 * @vsi: the VSI being configured
2595 *
2596 * Configure the Rx VSI for operation.
2597 **/
2598static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2599{
2600 int err = 0;
2601 u16 i;
2602
2603 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2604 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2605 + ETH_FCS_LEN + VLAN_HLEN;
2606 else
2607 vsi->max_frame = I40E_RXBUFFER_2048;
2608
2609 /* figure out correct receive buffer length */
2610 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2611 I40E_FLAG_RX_PS_ENABLED)) {
2612 case I40E_FLAG_RX_1BUF_ENABLED:
2613 vsi->rx_hdr_len = 0;
2614 vsi->rx_buf_len = vsi->max_frame;
2615 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2616 break;
2617 case I40E_FLAG_RX_PS_ENABLED:
2618 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2619 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2620 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2621 break;
2622 default:
2623 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2624 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2625 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2626 break;
2627 }
2628
38e00438
VD		 2629#ifdef I40E_FCOE
2630 /* setup rx buffer for FCoE */
2631 if ((vsi->type == I40E_VSI_FCOE) &&
2632 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2633 vsi->rx_hdr_len = 0;
2634 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2635 vsi->max_frame = I40E_RXBUFFER_3072;
2636 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2637 }
2638
2639#endif /* I40E_FCOE */
41c445ff
JB		 2640 /* round up for the chip's needs */
2641 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2642 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2643 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2644 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2645
2646 /* set up individual rings */
2647 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2648 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2649
2650 return err;
2651}
2652
2653/**
2654 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2655 * @vsi: ptr to the VSI
2656 **/
2657static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2658{
e7046ee1 2659 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2660 u16 qoffset, qcount;
2661 int i, n;
2662
2663 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2664 return;
2665
2666 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2667 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2668 continue;
2669
2670 qoffset = vsi->tc_config.tc_info[n].qoffset;
2671 qcount = vsi->tc_config.tc_info[n].qcount;
2672 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2673 rx_ring = vsi->rx_rings[i];
2674 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2675 rx_ring->dcb_tc = n;
2676 tx_ring->dcb_tc = n;
2677 }
2678 }
2679}
2680
2681/**
2682 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2683 * @vsi: ptr to the VSI
2684 **/
2685static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2686{
2687 if (vsi->netdev)
2688 i40e_set_rx_mode(vsi->netdev);
2689}
2690
17a73f6b
JG		 2691/**
2692 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2693 * @vsi: Pointer to the targeted VSI
2694 *
2695 * This function replays the hlist on the hw where all the SB Flow Director
2696 * filters were saved.
2697 **/
2698static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2699{
2700 struct i40e_fdir_filter *filter;
2701 struct i40e_pf *pf = vsi->back;
2702 struct hlist_node *node;
2703
55a5e60b
ASJ		 2704 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2705 return;
2706
17a73f6b
JG		 2707 hlist_for_each_entry_safe(filter, node,
2708 &pf->fdir_filter_list, fdir_node) {
2709 i40e_add_del_fdir(vsi, filter, true);
2710 }
2711}
2712
41c445ff
JB		 2713/**
2714 * i40e_vsi_configure - Set up the VSI for action
2715 * @vsi: the VSI being configured
2716 **/
2717static int i40e_vsi_configure(struct i40e_vsi *vsi)
2718{
2719 int err;
2720
2721 i40e_set_vsi_rx_mode(vsi);
2722 i40e_restore_vlan(vsi);
2723 i40e_vsi_config_dcb_rings(vsi);
2724 err = i40e_vsi_configure_tx(vsi);
2725 if (!err)
2726 err = i40e_vsi_configure_rx(vsi);
2727
2728 return err;
2729}
2730
2731/**
2732 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2733 * @vsi: the VSI being configured
2734 **/
2735static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2736{
2737 struct i40e_pf *pf = vsi->back;
2738 struct i40e_q_vector *q_vector;
2739 struct i40e_hw *hw = &pf->hw;
2740 u16 vector;
2741 int i, q;
2742 u32 val;
2743 u32 qp;
2744
2745 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2746 * and PFINT_LNKLSTn registers, e.g.:
2747 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2748 */
2749 qp = vsi->base_queue;
2750 vector = vsi->base_vector;
493fb300
AD		 2751 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2752 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2753 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2754 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2755 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2756 q_vector->rx.itr);
2757 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2758 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2759 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2760 q_vector->tx.itr);
2761
2762 /* Linked list for the queuepairs assigned to this vector */
2763 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2764 for (q = 0; q < q_vector->num_ringpairs; q++) {
2765 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2766 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2767 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2768 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2769 (I40E_QUEUE_TYPE_TX
2770 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2771
2772 wr32(hw, I40E_QINT_RQCTL(qp), val);
2773
2774 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2775 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2776 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2777 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2778 (I40E_QUEUE_TYPE_RX
2779 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2780
2781 /* Terminate the linked list */
2782 if (q == (q_vector->num_ringpairs - 1))
2783 val |= (I40E_QUEUE_END_OF_LIST
2784 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2785
2786 wr32(hw, I40E_QINT_TQCTL(qp), val);
2787 qp++;
2788 }
2789 }
2790
2791 i40e_flush(hw);
2792}
2793
2794/**
2795 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2796 * @hw: ptr to the hardware info
2797 **/
2798static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2799{
2800 u32 val;
2801
2802 /* clear things first */
2803 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2804 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2805
2806 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2807 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2808 I40E_PFINT_ICR0_ENA_GRST_MASK |
2809 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2810 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2811 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2812 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2813 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2814 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2815
2816 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2817
2818 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2819 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2820 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2821
2822 /* OTHER_ITR_IDX = 0 */
2823 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2824}
2825
2826/**
2827 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2828 * @vsi: the VSI being configured
2829 **/
2830static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2831{
493fb300 2832 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2833 struct i40e_pf *pf = vsi->back;
2834 struct i40e_hw *hw = &pf->hw;
2835 u32 val;
2836
2837 /* set the ITR configuration */
2838 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2839 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2840 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2841 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2842 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2843 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2844
2845 i40e_enable_misc_int_causes(hw);
2846
2847 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2848 wr32(hw, I40E_PFINT_LNKLST0, 0);
2849
f29eaa3d 2850 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2851 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2852 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2853 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2854
2855 wr32(hw, I40E_QINT_RQCTL(0), val);
2856
2857 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2858 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2859 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2860
2861 wr32(hw, I40E_QINT_TQCTL(0), val);
2862 i40e_flush(hw);
2863}
2864
2ef28cfb
MW		 2865/**
2866 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2867 * @pf: board private structure
2868 **/
2869void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2870{
2871 struct i40e_hw *hw = &pf->hw;
2872
2873 wr32(hw, I40E_PFINT_DYN_CTL0,
2874 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2875 i40e_flush(hw);
2876}
2877
41c445ff
JB		 2878/**
2879 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2880 * @pf: board private structure
2881 **/
116a57d4 2882void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2883{
2884 struct i40e_hw *hw = &pf->hw;
2885 u32 val;
2886
2887 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2888 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2889 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2890
2891 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2892 i40e_flush(hw);
2893}
2894
2895/**
2896 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2897 * @vsi: pointer to a vsi
2898 * @vector: enable a particular Hw Interrupt vector
2899 **/
2900void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2901{
2902 struct i40e_pf *pf = vsi->back;
2903 struct i40e_hw *hw = &pf->hw;
2904 u32 val;
2905
2906 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2907 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2908 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2909 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2910 /* skip the flush */
41c445ff
JB		 2911}
2912
5c2cebda
CW		 2913/**
2914 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2915 * @vsi: pointer to a vsi
2916 * @vector: enable a particular Hw Interrupt vector
2917 **/
2918void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2919{
2920 struct i40e_pf *pf = vsi->back;
2921 struct i40e_hw *hw = &pf->hw;
2922 u32 val;
2923
2924 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2925 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2926 i40e_flush(hw);
2927}
2928
41c445ff
JB		 2929/**
2930 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2931 * @irq: interrupt number
2932 * @data: pointer to a q_vector
2933 **/
2934static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2935{
2936 struct i40e_q_vector *q_vector = data;
2937
cd0b6fa6 2938 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2939 return IRQ_HANDLED;
2940
2941 napi_schedule(&q_vector->napi);
2942
2943 return IRQ_HANDLED;
2944}
2945
41c445ff
JB		 2946/**
2947 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2948 * @vsi: the VSI being configured
2949 * @basename: name for the vector
2950 *
2951 * Allocates MSI-X vectors and requests interrupts from the kernel.
2952 **/
2953static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2954{
2955 int q_vectors = vsi->num_q_vectors;
2956 struct i40e_pf *pf = vsi->back;
2957 int base = vsi->base_vector;
2958 int rx_int_idx = 0;
2959 int tx_int_idx = 0;
2960 int vector, err;
2961
2962 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2963 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2964
cd0b6fa6 2965 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2966 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2967 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2968 tx_int_idx++;
cd0b6fa6 2969 } else if (q_vector->rx.ring) {
41c445ff
JB		 2970 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2971 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2972 } else if (q_vector->tx.ring) {
41c445ff
JB		 2973 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2974 "%s-%s-%d", basename, "tx", tx_int_idx++);
2975 } else {
2976 /* skip this unused q_vector */
2977 continue;
2978 }
2979 err = request_irq(pf->msix_entries[base + vector].vector,
2980 vsi->irq_handler,
2981 0,
2982 q_vector->name,
2983 q_vector);
2984 if (err) {
2985 dev_info(&pf->pdev->dev,
2986 "%s: request_irq failed, error: %d\n",
2987 __func__, err);
2988 goto free_queue_irqs;
2989 }
2990 /* assign the mask for this irq */
2991 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2992 &q_vector->affinity_mask);
2993 }
2994
63741846 2995 vsi->irqs_ready = true;
41c445ff
JB		 2996 return 0;
2997
2998free_queue_irqs:
2999 while (vector) {
3000 vector--;
3001 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3002 NULL);
3003 free_irq(pf->msix_entries[base + vector].vector,
3004 &(vsi->q_vectors[vector]));
3005 }
3006 return err;
3007}
3008
3009/**
3010 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3011 * @vsi: the VSI being un-configured
3012 **/
3013static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3014{
3015 struct i40e_pf *pf = vsi->back;
3016 struct i40e_hw *hw = &pf->hw;
3017 int base = vsi->base_vector;
3018 int i;
3019
3020 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3021 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3022 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3023 }
3024
3025 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3026 for (i = vsi->base_vector;
3027 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3028 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3029
3030 i40e_flush(hw);
3031 for (i = 0; i < vsi->num_q_vectors; i++)
3032 synchronize_irq(pf->msix_entries[i + base].vector);
3033 } else {
3034 /* Legacy and MSI mode - this stops all interrupt handling */
3035 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3036 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3037 i40e_flush(hw);
3038 synchronize_irq(pf->pdev->irq);
3039 }
3040}
3041
3042/**
3043 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3044 * @vsi: the VSI being configured
3045 **/
3046static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3047{
3048 struct i40e_pf *pf = vsi->back;
3049 int i;
3050
3051 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3052 for (i = vsi->base_vector;
3053 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3054 i40e_irq_dynamic_enable(vsi, i);
3055 } else {
3056 i40e_irq_dynamic_enable_icr0(pf);
3057 }
3058
1022cb6c 3059 i40e_flush(&pf->hw);
41c445ff
JB		 3060 return 0;
3061}
3062
3063/**
3064 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3065 * @pf: board private structure
3066 **/
3067static void i40e_stop_misc_vector(struct i40e_pf *pf)
3068{
3069 /* Disable ICR 0 */
3070 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3071 i40e_flush(&pf->hw);
3072}
3073
3074/**
3075 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3076 * @irq: interrupt number
3077 * @data: pointer to a q_vector
3078 *
3079 * This is the handler used for all MSI/Legacy interrupts, and deals
3080 * with both queue and non-queue interrupts. This is also used in
3081 * MSIX mode to handle the non-queue interrupts.
3082 **/
3083static irqreturn_t i40e_intr(int irq, void *data)
3084{
3085 struct i40e_pf *pf = (struct i40e_pf *)data;
3086 struct i40e_hw *hw = &pf->hw;
5e823066 3087 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3088 u32 icr0, icr0_remaining;
3089 u32 val, ena_mask;
3090
3091 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3092 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3093
116a57d4
SN		 3094 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3095 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3096 goto enable_intr;
41c445ff 3097
cd92e72f
SN		 3098 /* if interrupt but no bits showing, must be SWINT */
3099 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3100 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3101 pf->sw_int_count++;
3102
41c445ff
JB		 3103 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3104 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3105
3106 /* temporarily disable queue cause for NAPI processing */
3107 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3108 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3109 wr32(hw, I40E_QINT_RQCTL(0), qval);
3110
3111 qval = rd32(hw, I40E_QINT_TQCTL(0));
3112 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3113 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3114
3115 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3116 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3117 }
3118
3119 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3120 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3121 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3122 }
3123
3124 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3125 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3126 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3127 }
3128
3129 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3130 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3131 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3132 }
3133
3134 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3135 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3136 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3137 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3138 val = rd32(hw, I40E_GLGEN_RSTAT);
3139 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3140 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3141 if (val == I40E_RESET_CORER) {
41c445ff 3142 pf->corer_count++;
4eb3f768 3143 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3144 pf->globr_count++;
4eb3f768 3145 } else if (val == I40E_RESET_EMPR) {
41c445ff 3146 pf->empr_count++;
4eb3f768
SN		 3147 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
3148 }
41c445ff
JB		 3149 }
3150
9c010ee0
ASJ		 3151 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3152 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3153 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3154 }
3155
beb0dff1
JK		 3156 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3157 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3158
3159 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3160 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3161 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3162 }
beb0dff1
JK		 3163 }
3164
41c445ff
JB		 3165 /* If a critical error is pending we have no choice but to reset the
3166 * device.
3167 * Report and mask out any remaining unexpected interrupts.
3168 */
3169 icr0_remaining = icr0 & ena_mask;
3170 if (icr0_remaining) {
3171 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3172 icr0_remaining);
9c010ee0 3173 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3174 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3175 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3176 dev_info(&pf->pdev->dev, "device will be reset\n");
3177 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3178 i40e_service_event_schedule(pf);
41c445ff
JB		 3179 }
3180 ena_mask &= ~icr0_remaining;
3181 }
5e823066 3182 ret = IRQ_HANDLED;
41c445ff 3183
5e823066 3184enable_intr:
41c445ff
JB		 3185 /* re-enable interrupt causes */
3186 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3187 if (!test_bit(__I40E_DOWN, &pf->state)) {
3188 i40e_service_event_schedule(pf);
3189 i40e_irq_dynamic_enable_icr0(pf);
3190 }
3191
5e823066 3192 return ret;
41c445ff
JB		 3193}
3194
cbf61325
ASJ		 3195/**
3196 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3197 * @tx_ring: tx ring to clean
3198 * @budget: how many cleans we're allowed
3199 *
3200 * Returns true if there's any budget left (e.g. the clean is finished)
3201 **/
3202static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3203{
3204 struct i40e_vsi *vsi = tx_ring->vsi;
3205 u16 i = tx_ring->next_to_clean;
3206 struct i40e_tx_buffer *tx_buf;
3207 struct i40e_tx_desc *tx_desc;
3208
3209 tx_buf = &tx_ring->tx_bi[i];
3210 tx_desc = I40E_TX_DESC(tx_ring, i);
3211 i -= tx_ring->count;
3212
3213 do {
3214 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3215
3216 /* if next_to_watch is not set then there is no work pending */
3217 if (!eop_desc)
3218 break;
3219
3220 /* prevent any other reads prior to eop_desc */
3221 read_barrier_depends();
3222
3223 /* if the descriptor isn't done, no work yet to do */
3224 if (!(eop_desc->cmd_type_offset_bsz &
3225 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3226 break;
3227
3228 /* clear next_to_watch to prevent false hangs */
3229 tx_buf->next_to_watch = NULL;
3230
49d7d933
ASJ		 3231 tx_desc->buffer_addr = 0;
3232 tx_desc->cmd_type_offset_bsz = 0;
3233 /* move past filter desc */
3234 tx_buf++;
3235 tx_desc++;
3236 i++;
3237 if (unlikely(!i)) {
3238 i -= tx_ring->count;
3239 tx_buf = tx_ring->tx_bi;
3240 tx_desc = I40E_TX_DESC(tx_ring, 0);
3241 }
cbf61325
ASJ		 3242 /* unmap skb header data */
3243 dma_unmap_single(tx_ring->dev,
3244 dma_unmap_addr(tx_buf, dma),
3245 dma_unmap_len(tx_buf, len),
3246 DMA_TO_DEVICE);
49d7d933
ASJ		 3247 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3248 kfree(tx_buf->raw_buf);
cbf61325 3249
49d7d933
ASJ		 3250 tx_buf->raw_buf = NULL;
3251 tx_buf->tx_flags = 0;
3252 tx_buf->next_to_watch = NULL;
cbf61325 3253 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3254 tx_desc->buffer_addr = 0;
3255 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3256
49d7d933 3257 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3258 tx_buf++;
3259 tx_desc++;
3260 i++;
3261 if (unlikely(!i)) {
3262 i -= tx_ring->count;
3263 tx_buf = tx_ring->tx_bi;
3264 tx_desc = I40E_TX_DESC(tx_ring, 0);
3265 }
3266
3267 /* update budget accounting */
3268 budget--;
3269 } while (likely(budget));
3270
3271 i += tx_ring->count;
3272 tx_ring->next_to_clean = i;
3273
3274 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3275 i40e_irq_dynamic_enable(vsi,
3276 tx_ring->q_vector->v_idx + vsi->base_vector);
3277 }
3278 return budget > 0;
3279}
3280
3281/**
3282 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3283 * @irq: interrupt number
3284 * @data: pointer to a q_vector
3285 **/
3286static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3287{
3288 struct i40e_q_vector *q_vector = data;
3289 struct i40e_vsi *vsi;
3290
3291 if (!q_vector->tx.ring)
3292 return IRQ_HANDLED;
3293
3294 vsi = q_vector->tx.ring->vsi;
3295 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3296
3297 return IRQ_HANDLED;
3298}
3299
41c445ff 3300/**
cd0b6fa6 3301 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3302 * @vsi: the VSI being configured
3303 * @v_idx: vector index
cd0b6fa6 3304 * @qp_idx: queue pair index
41c445ff 3305 **/
cd0b6fa6 3306static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3307{
493fb300 3308 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3309 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3310 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3311
3312 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3313 tx_ring->next = q_vector->tx.ring;
3314 q_vector->tx.ring = tx_ring;
41c445ff 3315 q_vector->tx.count++;
cd0b6fa6
AD		 3316
3317 rx_ring->q_vector = q_vector;
3318 rx_ring->next = q_vector->rx.ring;
3319 q_vector->rx.ring = rx_ring;
3320 q_vector->rx.count++;
41c445ff
JB		 3321}
3322
3323/**
3324 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3325 * @vsi: the VSI being configured
3326 *
3327 * This function maps descriptor rings to the queue-specific vectors
3328 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3329 * one vector per queue pair, but on a constrained vector budget, we
3330 * group the queue pairs as "efficiently" as possible.
3331 **/
3332static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3333{
3334 int qp_remaining = vsi->num_queue_pairs;
3335 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3336 int num_ringpairs;
41c445ff
JB		 3337 int v_start = 0;
3338 int qp_idx = 0;
3339
3340 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3341 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3342 * It is also important to go through all the vectors available to be
3343 * sure that if we don't use all the vectors, that the remaining vectors
3344 * are cleared. This is especially important when decreasing the
3345 * number of queues in use.
41c445ff 3346 */
70114ec4 3347 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3348 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3349
3350 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3351
3352 q_vector->num_ringpairs = num_ringpairs;
3353
3354 q_vector->rx.count = 0;
3355 q_vector->tx.count = 0;
3356 q_vector->rx.ring = NULL;
3357 q_vector->tx.ring = NULL;
3358
3359 while (num_ringpairs--) {
3360 map_vector_to_qp(vsi, v_start, qp_idx);
3361 qp_idx++;
3362 qp_remaining--;
41c445ff
JB		 3363 }
3364 }
3365}
3366
3367/**
3368 * i40e_vsi_request_irq - Request IRQ from the OS
3369 * @vsi: the VSI being configured
3370 * @basename: name for the vector
3371 **/
3372static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3373{
3374 struct i40e_pf *pf = vsi->back;
3375 int err;
3376
3377 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3378 err = i40e_vsi_request_irq_msix(vsi, basename);
3379 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3380 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3381 pf->misc_int_name, pf);
3382 else
3383 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3384 pf->misc_int_name, pf);
3385
3386 if (err)
3387 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3388
3389 return err;
3390}
3391
3392#ifdef CONFIG_NET_POLL_CONTROLLER
3393/**
3394 * i40e_netpoll - A Polling 'interrupt'handler
3395 * @netdev: network interface device structure
3396 *
3397 * This is used by netconsole to send skbs without having to re-enable
3398 * interrupts. It's not called while the normal interrupt routine is executing.
3399 **/
38e00438
VD		 3400#ifdef I40E_FCOE
3401void i40e_netpoll(struct net_device *netdev)
3402#else
41c445ff 3403static void i40e_netpoll(struct net_device *netdev)
38e00438 3404#endif
41c445ff
JB		 3405{
3406 struct i40e_netdev_priv *np = netdev_priv(netdev);
3407 struct i40e_vsi *vsi = np->vsi;
3408 struct i40e_pf *pf = vsi->back;
3409 int i;
3410
3411 /* if interface is down do nothing */
3412 if (test_bit(__I40E_DOWN, &vsi->state))
3413 return;
3414
3415 pf->flags |= I40E_FLAG_IN_NETPOLL;
3416 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3417 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3418 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3419 } else {
3420 i40e_intr(pf->pdev->irq, netdev);
3421 }
3422 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3423}
3424#endif
3425
23527308
NP		 3426/**
3427 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3428 * @pf: the PF being configured
3429 * @pf_q: the PF queue
3430 * @enable: enable or disable state of the queue
3431 *
3432 * This routine will wait for the given Tx queue of the PF to reach the
3433 * enabled or disabled state.
3434 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3435 * multiple retries; else will return 0 in case of success.
3436 **/
3437static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3438{
3439 int i;
3440 u32 tx_reg;
3441
3442 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3443 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3444 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3445 break;
3446
f98a2006 3447 usleep_range(10, 20);
23527308
NP		 3448 }
3449 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3450 return -ETIMEDOUT;
3451
3452 return 0;
3453}
3454
41c445ff
JB		 3455/**
3456 * i40e_vsi_control_tx - Start or stop a VSI's rings
3457 * @vsi: the VSI being configured
3458 * @enable: start or stop the rings
3459 **/
3460static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3461{
3462 struct i40e_pf *pf = vsi->back;
3463 struct i40e_hw *hw = &pf->hw;
23527308 3464 int i, j, pf_q, ret = 0;
41c445ff
JB		 3465 u32 tx_reg;
3466
3467 pf_q = vsi->base_queue;
3468 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3469
3470 /* warn the TX unit of coming changes */
3471 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3472 if (!enable)
f98a2006 3473 usleep_range(10, 20);
351499ab 3474
6c5ef620 3475 for (j = 0; j < 50; j++) {
41c445ff 3476 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3477 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3478 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3479 break;
3480 usleep_range(1000, 2000);
3481 }
fda972f6 3482 /* Skip if the queue is already in the requested state */
7c122007 3483 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3484 continue;
41c445ff
JB		 3485
3486 /* turn on/off the queue */
c5c9eb9e
SN		 3487 if (enable) {
3488 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3489 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3490 } else {
41c445ff 3491 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3492 }
41c445ff
JB		 3493
3494 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3495
3496 /* wait for the change to finish */
23527308
NP		 3497 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3498 if (ret) {
3499 dev_info(&pf->pdev->dev,
3500 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3501 __func__, vsi->seid, pf_q,
3502 (enable ? "en" : "dis"));
3503 break;
41c445ff
JB		 3504 }
3505 }
3506
7134f9ce
JB		 3507 if (hw->revision_id == 0)
3508 mdelay(50);
23527308
NP		 3509 return ret;
3510}
3511
3512/**
3513 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3514 * @pf: the PF being configured
3515 * @pf_q: the PF queue
3516 * @enable: enable or disable state of the queue
3517 *
3518 * This routine will wait for the given Rx queue of the PF to reach the
3519 * enabled or disabled state.
3520 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3521 * multiple retries; else will return 0 in case of success.
3522 **/
3523static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3524{
3525 int i;
3526 u32 rx_reg;
3527
3528 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3529 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3530 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3531 break;
3532
f98a2006 3533 usleep_range(10, 20);
23527308
NP		 3534 }
3535 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3536 return -ETIMEDOUT;
7134f9ce 3537
41c445ff
JB		 3538 return 0;
3539}
3540
3541/**
3542 * i40e_vsi_control_rx - Start or stop a VSI's rings
3543 * @vsi: the VSI being configured
3544 * @enable: start or stop the rings
3545 **/
3546static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3547{
3548 struct i40e_pf *pf = vsi->back;
3549 struct i40e_hw *hw = &pf->hw;
23527308 3550 int i, j, pf_q, ret = 0;
41c445ff
JB		 3551 u32 rx_reg;
3552
3553 pf_q = vsi->base_queue;
3554 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3555 for (j = 0; j < 50; j++) {
41c445ff 3556 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3557 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3558 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3559 break;
3560 usleep_range(1000, 2000);
3561 }
41c445ff 3562
7c122007
CS		 3563 /* Skip if the queue is already in the requested state */
3564 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3565 continue;
41c445ff
JB		 3566
3567 /* turn on/off the queue */
3568 if (enable)
6c5ef620 3569 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3570 else
6c5ef620 3571 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3572 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3573
3574 /* wait for the change to finish */
23527308
NP		 3575 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3576 if (ret) {
3577 dev_info(&pf->pdev->dev,
3578 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3579 __func__, vsi->seid, pf_q,
3580 (enable ? "en" : "dis"));
3581 break;
41c445ff
JB		 3582 }
3583 }
3584
23527308 3585 return ret;
41c445ff
JB		 3586}
3587
3588/**
3589 * i40e_vsi_control_rings - Start or stop a VSI's rings
3590 * @vsi: the VSI being configured
3591 * @enable: start or stop the rings
3592 **/
fc18eaa0 3593int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3594{
3b867b28 3595 int ret = 0;
41c445ff
JB		 3596
3597 /* do rx first for enable and last for disable */
3598 if (request) {
3599 ret = i40e_vsi_control_rx(vsi, request);
3600 if (ret)
3601 return ret;
3602 ret = i40e_vsi_control_tx(vsi, request);
3603 } else {
3b867b28
ASJ		 3604 /* Ignore return value, we need to shutdown whatever we can */
3605 i40e_vsi_control_tx(vsi, request);
3606 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3607 }
3608
3609 return ret;
3610}
3611
3612/**
3613 * i40e_vsi_free_irq - Free the irq association with the OS
3614 * @vsi: the VSI being configured
3615 **/
3616static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3617{
3618 struct i40e_pf *pf = vsi->back;
3619 struct i40e_hw *hw = &pf->hw;
3620 int base = vsi->base_vector;
3621 u32 val, qp;
3622 int i;
3623
3624 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3625 if (!vsi->q_vectors)
3626 return;
3627
63741846
SN		 3628 if (!vsi->irqs_ready)
3629 return;
3630
3631 vsi->irqs_ready = false;
41c445ff
JB		 3632 for (i = 0; i < vsi->num_q_vectors; i++) {
3633 u16 vector = i + base;
3634
3635 /* free only the irqs that were actually requested */
78681b1f
SN		 3636 if (!vsi->q_vectors[i] ||
3637 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3638 continue;
3639
3640 /* clear the affinity_mask in the IRQ descriptor */
3641 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3642 NULL);
3643 free_irq(pf->msix_entries[vector].vector,
493fb300 3644 vsi->q_vectors[i]);
41c445ff
JB		 3645
3646 /* Tear down the interrupt queue link list
3647 *
3648 * We know that they come in pairs and always
3649 * the Rx first, then the Tx. To clear the
3650 * link list, stick the EOL value into the
3651 * next_q field of the registers.
3652 */
3653 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3654 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3655 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3656 val |= I40E_QUEUE_END_OF_LIST
3657 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3658 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3659
3660 while (qp != I40E_QUEUE_END_OF_LIST) {
3661 u32 next;
3662
3663 val = rd32(hw, I40E_QINT_RQCTL(qp));
3664
3665 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3666 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3667 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3668 I40E_QINT_RQCTL_INTEVENT_MASK);
3669
3670 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3671 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3672
3673 wr32(hw, I40E_QINT_RQCTL(qp), val);
3674
3675 val = rd32(hw, I40E_QINT_TQCTL(qp));
3676
3677 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3678 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3679
3680 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3681 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3682 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3683 I40E_QINT_TQCTL_INTEVENT_MASK);
3684
3685 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3686 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3687
3688 wr32(hw, I40E_QINT_TQCTL(qp), val);
3689 qp = next;
3690 }
3691 }
3692 } else {
3693 free_irq(pf->pdev->irq, pf);
3694
3695 val = rd32(hw, I40E_PFINT_LNKLST0);
3696 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3697 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3698 val |= I40E_QUEUE_END_OF_LIST
3699 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3700 wr32(hw, I40E_PFINT_LNKLST0, val);
3701
3702 val = rd32(hw, I40E_QINT_RQCTL(qp));
3703 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3704 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3705 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3706 I40E_QINT_RQCTL_INTEVENT_MASK);
3707
3708 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3709 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3710
3711 wr32(hw, I40E_QINT_RQCTL(qp), val);
3712
3713 val = rd32(hw, I40E_QINT_TQCTL(qp));
3714
3715 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3716 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3717 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3718 I40E_QINT_TQCTL_INTEVENT_MASK);
3719
3720 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3721 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3722
3723 wr32(hw, I40E_QINT_TQCTL(qp), val);
3724 }
3725}
3726
493fb300
AD		 3727/**
3728 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3729 * @vsi: the VSI being configured
3730 * @v_idx: Index of vector to be freed
3731 *
3732 * This function frees the memory allocated to the q_vector. In addition if
3733 * NAPI is enabled it will delete any references to the NAPI struct prior
3734 * to freeing the q_vector.
3735 **/
3736static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3737{
3738 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3739 struct i40e_ring *ring;
493fb300
AD		 3740
3741 if (!q_vector)
3742 return;
3743
3744 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3745 i40e_for_each_ring(ring, q_vector->tx)
3746 ring->q_vector = NULL;
3747
3748 i40e_for_each_ring(ring, q_vector->rx)
3749 ring->q_vector = NULL;
493fb300
AD		 3750
3751 /* only VSI w/ an associated netdev is set up w/ NAPI */
3752 if (vsi->netdev)
3753 netif_napi_del(&q_vector->napi);
3754
3755 vsi->q_vectors[v_idx] = NULL;
3756
3757 kfree_rcu(q_vector, rcu);
3758}
3759
41c445ff
JB		 3760/**
3761 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3762 * @vsi: the VSI being un-configured
3763 *
3764 * This frees the memory allocated to the q_vectors and
3765 * deletes references to the NAPI struct.
3766 **/
3767static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3768{
3769 int v_idx;
3770
493fb300
AD		 3771 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3772 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3773}
3774
3775/**
3776 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3777 * @pf: board private structure
3778 **/
3779static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3780{
3781 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3782 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3783 pci_disable_msix(pf->pdev);
3784 kfree(pf->msix_entries);
3785 pf->msix_entries = NULL;
3786 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3787 pci_disable_msi(pf->pdev);
3788 }
3789 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3790}
3791
3792/**
3793 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3794 * @pf: board private structure
3795 *
3796 * We go through and clear interrupt specific resources and reset the structure
3797 * to pre-load conditions
3798 **/
3799static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3800{
3801 int i;
3802
3803 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3804 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3805 if (pf->vsi[i])
3806 i40e_vsi_free_q_vectors(pf->vsi[i]);
3807 i40e_reset_interrupt_capability(pf);
3808}
3809
3810/**
3811 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3812 * @vsi: the VSI being configured
3813 **/
3814static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3815{
3816 int q_idx;
3817
3818 if (!vsi->netdev)
3819 return;
3820
3821 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3822 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3823}
3824
3825/**
3826 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3827 * @vsi: the VSI being configured
3828 **/
3829static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3830{
3831 int q_idx;
3832
3833 if (!vsi->netdev)
3834 return;
3835
3836 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3837 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3838}
3839
90ef8d47
SN		 3840/**
3841 * i40e_vsi_close - Shut down a VSI
3842 * @vsi: the vsi to be quelled
3843 **/
3844static void i40e_vsi_close(struct i40e_vsi *vsi)
3845{
3846 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3847 i40e_down(vsi);
3848 i40e_vsi_free_irq(vsi);
3849 i40e_vsi_free_tx_resources(vsi);
3850 i40e_vsi_free_rx_resources(vsi);
3851}
3852
41c445ff
JB		 3853/**
3854 * i40e_quiesce_vsi - Pause a given VSI
3855 * @vsi: the VSI being paused
3856 **/
3857static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3858{
3859 if (test_bit(__I40E_DOWN, &vsi->state))
3860 return;
3861
3862 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3863 if (vsi->netdev && netif_running(vsi->netdev)) {
3864 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3865 } else {
90ef8d47 3866 i40e_vsi_close(vsi);
41c445ff
JB		 3867 }
3868}
3869
3870/**
3871 * i40e_unquiesce_vsi - Resume a given VSI
3872 * @vsi: the VSI being resumed
3873 **/
3874static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3875{
3876 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3877 return;
3878
3879 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3880 if (vsi->netdev && netif_running(vsi->netdev))
3881 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3882 else
8276f757 3883 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3884}
3885
3886/**
3887 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3888 * @pf: the PF
3889 **/
3890static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3891{
3892 int v;
3893
505682cd 3894 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3895 if (pf->vsi[v])
3896 i40e_quiesce_vsi(pf->vsi[v]);
3897 }
3898}
3899
3900/**
3901 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3902 * @pf: the PF
3903 **/
3904static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3905{
3906 int v;
3907
505682cd 3908 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3909 if (pf->vsi[v])
3910 i40e_unquiesce_vsi(pf->vsi[v]);
3911 }
3912}
3913
3914/**
3915 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3916 * @dcbcfg: the corresponding DCBx configuration structure
3917 *
3918 * Return the number of TCs from given DCBx configuration
3919 **/
3920static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3921{
078b5876
JB		 3922 u8 num_tc = 0;
3923 int i;
41c445ff
JB		 3924
3925 /* Scan the ETS Config Priority Table to find
3926 * traffic class enabled for a given priority
3927 * and use the traffic class index to get the
3928 * number of traffic classes enabled
3929 */
3930 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3931 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3932 num_tc = dcbcfg->etscfg.prioritytable[i];
3933 }
3934
3935 /* Traffic class index starts from zero so
3936 * increment to return the actual count
3937 */
078b5876 3938 return num_tc + 1;
41c445ff
JB		 3939}
3940
3941/**
3942 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3943 * @dcbcfg: the corresponding DCBx configuration structure
3944 *
3945 * Query the current DCB configuration and return the number of
3946 * traffic classes enabled from the given DCBX config
3947 **/
3948static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3949{
3950 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3951 u8 enabled_tc = 1;
3952 u8 i;
3953
3954 for (i = 0; i < num_tc; i++)
3955 enabled_tc |= 1 << i;
3956
3957 return enabled_tc;
3958}
3959
3960/**
3961 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3962 * @pf: PF being queried
3963 *
3964 * Return number of traffic classes enabled for the given PF
3965 **/
3966static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3967{
3968 struct i40e_hw *hw = &pf->hw;
3969 u8 i, enabled_tc;
3970 u8 num_tc = 0;
3971 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3972
3973 /* If DCB is not enabled then always in single TC */
3974 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3975 return 1;
3976
3977 /* MFP mode return count of enabled TCs for this PF */
3978 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3979 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3980 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3981 if (enabled_tc & (1 << i))
3982 num_tc++;
3983 }
3984 return num_tc;
3985 }
3986
3987 /* SFP mode will be enabled for all TCs on port */
3988 return i40e_dcb_get_num_tc(dcbcfg);
3989}
3990
3991/**
3992 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3993 * @pf: PF being queried
3994 *
3995 * Return a bitmap for first enabled traffic class for this PF.
3996 **/
3997static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3998{
3999 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4000 u8 i = 0;
4001
4002 if (!enabled_tc)
4003 return 0x1; /* TC0 */
4004
4005 /* Find the first enabled TC */
4006 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4007 if (enabled_tc & (1 << i))
4008 break;
4009 }
4010
4011 return 1 << i;
4012}
4013
4014/**
4015 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4016 * @pf: PF being queried
4017 *
4018 * Return a bitmap for enabled traffic classes for this PF.
4019 **/
4020static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4021{
4022 /* If DCB is not enabled for this PF then just return default TC */
4023 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4024 return i40e_pf_get_default_tc(pf);
4025
4026 /* MFP mode will have enabled TCs set by FW */
4027 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4028 return pf->hw.func_caps.enabled_tcmap;
4029
4030 /* SFP mode we want PF to be enabled for all TCs */
4031 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4032}
4033
4034/**
4035 * i40e_vsi_get_bw_info - Query VSI BW Information
4036 * @vsi: the VSI being queried
4037 *
4038 * Returns 0 on success, negative value on failure
4039 **/
4040static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4041{
4042 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4043 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4044 struct i40e_pf *pf = vsi->back;
4045 struct i40e_hw *hw = &pf->hw;
dcae29be 4046 i40e_status aq_ret;
41c445ff 4047 u32 tc_bw_max;
41c445ff
JB		 4048 int i;
4049
4050 /* Get the VSI level BW configuration */
dcae29be
JB		 4051 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4052 if (aq_ret) {
41c445ff
JB		 4053 dev_info(&pf->pdev->dev,
4054 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4055 aq_ret, pf->hw.aq.asq_last_status);
4056 return -EINVAL;
41c445ff
JB		 4057 }
4058
4059 /* Get the VSI level BW configuration per TC */
dcae29be 4060 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4061 NULL);
dcae29be 4062 if (aq_ret) {
41c445ff
JB		 4063 dev_info(&pf->pdev->dev,
4064 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4065 aq_ret, pf->hw.aq.asq_last_status);
4066 return -EINVAL;
41c445ff
JB		 4067 }
4068
4069 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4070 dev_info(&pf->pdev->dev,
4071 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4072 bw_config.tc_valid_bits,
4073 bw_ets_config.tc_valid_bits);
4074 /* Still continuing */
4075 }
4076
4077 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4078 vsi->bw_max_quanta = bw_config.max_bw;
4079 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4080 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4081 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4082 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4083 vsi->bw_ets_limit_credits[i] =
4084 le16_to_cpu(bw_ets_config.credits[i]);
4085 /* 3 bits out of 4 for each TC */
4086 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4087 }
078b5876 4088
dcae29be 4089 return 0;
41c445ff
JB		 4090}
4091
4092/**
4093 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4094 * @vsi: the VSI being configured
4095 * @enabled_tc: TC bitmap
4096 * @bw_credits: BW shared credits per TC
4097 *
4098 * Returns 0 on success, negative value on failure
4099 **/
dcae29be 4100static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4101 u8 *bw_share)
4102{
4103 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4104 i40e_status aq_ret;
4105 int i;
41c445ff
JB		 4106
4107 bw_data.tc_valid_bits = enabled_tc;
4108 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4109 bw_data.tc_bw_credits[i] = bw_share[i];
4110
dcae29be
JB		 4111 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4112 NULL);
4113 if (aq_ret) {
41c445ff 4114 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4115 "AQ command Config VSI BW allocation per TC failed = %d\n",
4116 vsi->back->hw.aq.asq_last_status);
dcae29be 4117 return -EINVAL;
41c445ff
JB		 4118 }
4119
4120 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4121 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4122
dcae29be 4123 return 0;
41c445ff
JB		 4124}
4125
4126/**
4127 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4128 * @vsi: the VSI being configured
4129 * @enabled_tc: TC map to be enabled
4130 *
4131 **/
4132static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4133{
4134 struct net_device *netdev = vsi->netdev;
4135 struct i40e_pf *pf = vsi->back;
4136 struct i40e_hw *hw = &pf->hw;
4137 u8 netdev_tc = 0;
4138 int i;
4139 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4140
4141 if (!netdev)
4142 return;
4143
4144 if (!enabled_tc) {
4145 netdev_reset_tc(netdev);
4146 return;
4147 }
4148
4149 /* Set up actual enabled TCs on the VSI */
4150 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4151 return;
4152
4153 /* set per TC queues for the VSI */
4154 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4155 /* Only set TC queues for enabled tcs
4156 *
4157 * e.g. For a VSI that has TC0 and TC3 enabled the
4158 * enabled_tc bitmap would be 0x00001001; the driver
4159 * will set the numtc for netdev as 2 that will be
4160 * referenced by the netdev layer as TC 0 and 1.
4161 */
4162 if (vsi->tc_config.enabled_tc & (1 << i))
4163 netdev_set_tc_queue(netdev,
4164 vsi->tc_config.tc_info[i].netdev_tc,
4165 vsi->tc_config.tc_info[i].qcount,
4166 vsi->tc_config.tc_info[i].qoffset);
4167 }
4168
4169 /* Assign UP2TC map for the VSI */
4170 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4171 /* Get the actual TC# for the UP */
4172 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4173 /* Get the mapped netdev TC# for the UP */
4174 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4175 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4176 }
4177}
4178
4179/**
4180 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4181 * @vsi: the VSI being configured
4182 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4183 **/
4184static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4185 struct i40e_vsi_context *ctxt)
4186{
4187 /* copy just the sections touched not the entire info
4188 * since not all sections are valid as returned by
4189 * update vsi params
4190 */
4191 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4192 memcpy(&vsi->info.queue_mapping,
4193 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4194 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4195 sizeof(vsi->info.tc_mapping));
4196}
4197
4198/**
4199 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4200 * @vsi: VSI to be configured
4201 * @enabled_tc: TC bitmap
4202 *
4203 * This configures a particular VSI for TCs that are mapped to the
4204 * given TC bitmap. It uses default bandwidth share for TCs across
4205 * VSIs to configure TC for a particular VSI.
4206 *
4207 * NOTE:
4208 * It is expected that the VSI queues have been quisced before calling
4209 * this function.
4210 **/
4211static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4212{
4213 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4214 struct i40e_vsi_context ctxt;
4215 int ret = 0;
4216 int i;
4217
4218 /* Check if enabled_tc is same as existing or new TCs */
4219 if (vsi->tc_config.enabled_tc == enabled_tc)
4220 return ret;
4221
4222 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4223 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4224 if (enabled_tc & (1 << i))
4225 bw_share[i] = 1;
4226 }
4227
4228 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4229 if (ret) {
4230 dev_info(&vsi->back->pdev->dev,
4231 "Failed configuring TC map %d for VSI %d\n",
4232 enabled_tc, vsi->seid);
4233 goto out;
4234 }
4235
4236 /* Update Queue Pairs Mapping for currently enabled UPs */
4237 ctxt.seid = vsi->seid;
4238 ctxt.pf_num = vsi->back->hw.pf_id;
4239 ctxt.vf_num = 0;
4240 ctxt.uplink_seid = vsi->uplink_seid;
4241 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4242 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4243
4244 /* Update the VSI after updating the VSI queue-mapping information */
4245 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4246 if (ret) {
4247 dev_info(&vsi->back->pdev->dev,
4248 "update vsi failed, aq_err=%d\n",
4249 vsi->back->hw.aq.asq_last_status);
4250 goto out;
4251 }
4252 /* update the local VSI info with updated queue map */
4253 i40e_vsi_update_queue_map(vsi, &ctxt);
4254 vsi->info.valid_sections = 0;
4255
4256 /* Update current VSI BW information */
4257 ret = i40e_vsi_get_bw_info(vsi);
4258 if (ret) {
4259 dev_info(&vsi->back->pdev->dev,
4260 "Failed updating vsi bw info, aq_err=%d\n",
4261 vsi->back->hw.aq.asq_last_status);
4262 goto out;
4263 }
4264
4265 /* Update the netdev TC setup */
4266 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4267out:
4268 return ret;
4269}
4270
4e3b35b0
NP		 4271/**
4272 * i40e_veb_config_tc - Configure TCs for given VEB
4273 * @veb: given VEB
4274 * @enabled_tc: TC bitmap
4275 *
4276 * Configures given TC bitmap for VEB (switching) element
4277 **/
4278int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4279{
4280 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4281 struct i40e_pf *pf = veb->pf;
4282 int ret = 0;
4283 int i;
4284
4285 /* No TCs or already enabled TCs just return */
4286 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4287 return ret;
4288
4289 bw_data.tc_valid_bits = enabled_tc;
4290 /* bw_data.absolute_credits is not set (relative) */
4291
4292 /* Enable ETS TCs with equal BW Share for now */
4293 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4294 if (enabled_tc & (1 << i))
4295 bw_data.tc_bw_share_credits[i] = 1;
4296 }
4297
4298 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4299 &bw_data, NULL);
4300 if (ret) {
4301 dev_info(&pf->pdev->dev,
4302 "veb bw config failed, aq_err=%d\n",
4303 pf->hw.aq.asq_last_status);
4304 goto out;
4305 }
4306
4307 /* Update the BW information */
4308 ret = i40e_veb_get_bw_info(veb);
4309 if (ret) {
4310 dev_info(&pf->pdev->dev,
4311 "Failed getting veb bw config, aq_err=%d\n",
4312 pf->hw.aq.asq_last_status);
4313 }
4314
4315out:
4316 return ret;
4317}
4318
4319#ifdef CONFIG_I40E_DCB
4320/**
4321 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4322 * @pf: PF struct
4323 *
4324 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4325 * the caller would've quiesce all the VSIs before calling
4326 * this function
4327 **/
4328static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4329{
4330 u8 tc_map = 0;
4331 int ret;
4332 u8 v;
4333
4334 /* Enable the TCs available on PF to all VEBs */
4335 tc_map = i40e_pf_get_tc_map(pf);
4336 for (v = 0; v < I40E_MAX_VEB; v++) {
4337 if (!pf->veb[v])
4338 continue;
4339 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4340 if (ret) {
4341 dev_info(&pf->pdev->dev,
4342 "Failed configuring TC for VEB seid=%d\n",
4343 pf->veb[v]->seid);
4344 /* Will try to configure as many components */
4345 }
4346 }
4347
4348 /* Update each VSI */
505682cd 4349 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4350 if (!pf->vsi[v])
4351 continue;
4352
4353 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4354#ifdef I40E_FCOE
4355 * - For FCoE VSI only enable the TC configured
4356 * as per the APP TLV
4357#endif
4e3b35b0
NP		 4358 * - For all others keep them at TC0 for now
4359 */
4360 if (v == pf->lan_vsi)
4361 tc_map = i40e_pf_get_tc_map(pf);
4362 else
4363 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4364#ifdef I40E_FCOE
4365 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4366 tc_map = i40e_get_fcoe_tc_map(pf);
4367#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4368
4369 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4370 if (ret) {
4371 dev_info(&pf->pdev->dev,
4372 "Failed configuring TC for VSI seid=%d\n",
4373 pf->vsi[v]->seid);
4374 /* Will try to configure as many components */
4375 } else {
0672a091
NP		 4376 /* Re-configure VSI vectors based on updated TC map */
4377 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4378 if (pf->vsi[v]->netdev)
4379 i40e_dcbnl_set_all(pf->vsi[v]);
4380 }
4381 }
4382}
4383
4384/**
4385 * i40e_init_pf_dcb - Initialize DCB configuration
4386 * @pf: PF being configured
4387 *
4388 * Query the current DCB configuration and cache it
4389 * in the hardware structure
4390 **/
4391static int i40e_init_pf_dcb(struct i40e_pf *pf)
4392{
4393 struct i40e_hw *hw = &pf->hw;
4394 int err = 0;
4395
4396 if (pf->hw.func_caps.npar_enable)
4397 goto out;
4398
4399 /* Get the initial DCB configuration */
4400 err = i40e_init_dcb(hw);
4401 if (!err) {
4402 /* Device/Function is not DCBX capable */
4403 if ((!hw->func_caps.dcb) ||
4404 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4405 dev_info(&pf->pdev->dev,
4406 "DCBX offload is not supported or is disabled for this PF.\n");
4407
4408 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4409 goto out;
4410
4411 } else {
4412 /* When status is not DISABLED then DCBX in FW */
4413 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4414 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4415
4416 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4417 /* Enable DCB tagging only when more than one TC */
4418 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4419 pf->flags |= I40E_FLAG_DCB_ENABLED;
4e3b35b0 4420 }
014269ff
NP		 4421 } else {
4422 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4423 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4424 }
4425
4426out:
4427 return err;
4428}
4429#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4430#define SPEED_SIZE 14
4431#define FC_SIZE 8
4432/**
4433 * i40e_print_link_message - print link up or down
4434 * @vsi: the VSI for which link needs a message
4435 */
4436static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4437{
4438 char speed[SPEED_SIZE] = "Unknown";
4439 char fc[FC_SIZE] = "RX/TX";
4440
4441 if (!isup) {
4442 netdev_info(vsi->netdev, "NIC Link is Down\n");
4443 return;
4444 }
4445
4446 switch (vsi->back->hw.phy.link_info.link_speed) {
4447 case I40E_LINK_SPEED_40GB:
35a7d804 4448 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4449 break;
4450 case I40E_LINK_SPEED_10GB:
35a7d804 4451 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4452 break;
4453 case I40E_LINK_SPEED_1GB:
35a7d804 4454 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4455 break;
5960d33f
MW		 4456 case I40E_LINK_SPEED_100MB:
4457 strncpy(speed, "100 Mbps", SPEED_SIZE);
4458 break;
cf05ed08
JB		 4459 default:
4460 break;
4461 }
4462
4463 switch (vsi->back->hw.fc.current_mode) {
4464 case I40E_FC_FULL:
35a7d804 4465 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4466 break;
4467 case I40E_FC_TX_PAUSE:
35a7d804 4468 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4469 break;
4470 case I40E_FC_RX_PAUSE:
35a7d804 4471 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4472 break;
4473 default:
35a7d804 4474 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4475 break;
4476 }
4477
4478 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4479 speed, fc);
4480}
4e3b35b0 4481
41c445ff
JB		 4482/**
4483 * i40e_up_complete - Finish the last steps of bringing up a connection
4484 * @vsi: the VSI being configured
4485 **/
4486static int i40e_up_complete(struct i40e_vsi *vsi)
4487{
4488 struct i40e_pf *pf = vsi->back;
4489 int err;
4490
4491 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4492 i40e_vsi_configure_msix(vsi);
4493 else
4494 i40e_configure_msi_and_legacy(vsi);
4495
4496 /* start rings */
4497 err = i40e_vsi_control_rings(vsi, true);
4498 if (err)
4499 return err;
4500
4501 clear_bit(__I40E_DOWN, &vsi->state);
4502 i40e_napi_enable_all(vsi);
4503 i40e_vsi_enable_irq(vsi);
4504
4505 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4506 (vsi->netdev)) {
cf05ed08 4507 i40e_print_link_message(vsi, true);
41c445ff
JB		 4508 netif_tx_start_all_queues(vsi->netdev);
4509 netif_carrier_on(vsi->netdev);
6d779b41 4510 } else if (vsi->netdev) {
cf05ed08 4511 i40e_print_link_message(vsi, false);
7b592f61
CW		 4512 /* need to check for qualified module here*/
4513 if ((pf->hw.phy.link_info.link_info &
4514 I40E_AQ_MEDIA_AVAILABLE) &&
4515 (!(pf->hw.phy.link_info.an_info &
4516 I40E_AQ_QUALIFIED_MODULE)))
4517 netdev_err(vsi->netdev,
4518 "the driver failed to link because an unqualified module was detected.");
41c445ff 4519 }
ca64fa4e
ASJ		 4520
4521 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4522 if (vsi->type == I40E_VSI_FDIR) {
4523 /* reset fd counters */
4524 pf->fd_add_err = pf->fd_atr_cnt = 0;
4525 if (pf->fd_tcp_rule > 0) {
4526 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4527 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4528 pf->fd_tcp_rule = 0;
4529 }
ca64fa4e 4530 i40e_fdir_filter_restore(vsi);
1e1be8f6 4531 }
41c445ff
JB		 4532 i40e_service_event_schedule(pf);
4533
4534 return 0;
4535}
4536
4537/**
4538 * i40e_vsi_reinit_locked - Reset the VSI
4539 * @vsi: the VSI being configured
4540 *
4541 * Rebuild the ring structs after some configuration
4542 * has changed, e.g. MTU size.
4543 **/
4544static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4545{
4546 struct i40e_pf *pf = vsi->back;
4547
4548 WARN_ON(in_interrupt());
4549 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4550 usleep_range(1000, 2000);
4551 i40e_down(vsi);
4552
4553 /* Give a VF some time to respond to the reset. The
4554 * two second wait is based upon the watchdog cycle in
4555 * the VF driver.
4556 */
4557 if (vsi->type == I40E_VSI_SRIOV)
4558 msleep(2000);
4559 i40e_up(vsi);
4560 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4561}
4562
4563/**
4564 * i40e_up - Bring the connection back up after being down
4565 * @vsi: the VSI being configured
4566 **/
4567int i40e_up(struct i40e_vsi *vsi)
4568{
4569 int err;
4570
4571 err = i40e_vsi_configure(vsi);
4572 if (!err)
4573 err = i40e_up_complete(vsi);
4574
4575 return err;
4576}
4577
4578/**
4579 * i40e_down - Shutdown the connection processing
4580 * @vsi: the VSI being stopped
4581 **/
4582void i40e_down(struct i40e_vsi *vsi)
4583{
4584 int i;
4585
4586 /* It is assumed that the caller of this function
4587 * sets the vsi->state __I40E_DOWN bit.
4588 */
4589 if (vsi->netdev) {
4590 netif_carrier_off(vsi->netdev);
4591 netif_tx_disable(vsi->netdev);
4592 }
4593 i40e_vsi_disable_irq(vsi);
4594 i40e_vsi_control_rings(vsi, false);
4595 i40e_napi_disable_all(vsi);
4596
4597 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4598 i40e_clean_tx_ring(vsi->tx_rings[i]);
4599 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4600 }
4601}
4602
4603/**
4604 * i40e_setup_tc - configure multiple traffic classes
4605 * @netdev: net device to configure
4606 * @tc: number of traffic classes to enable
4607 **/
38e00438
VD		 4608#ifdef I40E_FCOE
4609int i40e_setup_tc(struct net_device *netdev, u8 tc)
4610#else
41c445ff 4611static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4612#endif
41c445ff
JB		 4613{
4614 struct i40e_netdev_priv *np = netdev_priv(netdev);
4615 struct i40e_vsi *vsi = np->vsi;
4616 struct i40e_pf *pf = vsi->back;
4617 u8 enabled_tc = 0;
4618 int ret = -EINVAL;
4619 int i;
4620
4621 /* Check if DCB enabled to continue */
4622 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4623 netdev_info(netdev, "DCB is not enabled for adapter\n");
4624 goto exit;
4625 }
4626
4627 /* Check if MFP enabled */
4628 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4629 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4630 goto exit;
4631 }
4632
4633 /* Check whether tc count is within enabled limit */
4634 if (tc > i40e_pf_get_num_tc(pf)) {
4635 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4636 goto exit;
4637 }
4638
4639 /* Generate TC map for number of tc requested */
4640 for (i = 0; i < tc; i++)
4641 enabled_tc |= (1 << i);
4642
4643 /* Requesting same TC configuration as already enabled */
4644 if (enabled_tc == vsi->tc_config.enabled_tc)
4645 return 0;
4646
4647 /* Quiesce VSI queues */
4648 i40e_quiesce_vsi(vsi);
4649
4650 /* Configure VSI for enabled TCs */
4651 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4652 if (ret) {
4653 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4654 vsi->seid);
4655 goto exit;
4656 }
4657
4658 /* Unquiesce VSI */
4659 i40e_unquiesce_vsi(vsi);
4660
4661exit:
4662 return ret;
4663}
4664
4665/**
4666 * i40e_open - Called when a network interface is made active
4667 * @netdev: network interface device structure
4668 *
4669 * The open entry point is called when a network interface is made
4670 * active by the system (IFF_UP). At this point all resources needed
4671 * for transmit and receive operations are allocated, the interrupt
4672 * handler is registered with the OS, the netdev watchdog subtask is
4673 * enabled, and the stack is notified that the interface is ready.
4674 *
4675 * Returns 0 on success, negative value on failure
4676 **/
38e00438
VD		 4677#ifdef I40E_FCOE
4678int i40e_open(struct net_device *netdev)
4679#else
41c445ff 4680static int i40e_open(struct net_device *netdev)
38e00438 4681#endif
41c445ff
JB		 4682{
4683 struct i40e_netdev_priv *np = netdev_priv(netdev);
4684 struct i40e_vsi *vsi = np->vsi;
4685 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4686 int err;
4687
4eb3f768
SN		 4688 /* disallow open during test or if eeprom is broken */
4689 if (test_bit(__I40E_TESTING, &pf->state) ||
4690 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4691 return -EBUSY;
4692
4693 netif_carrier_off(netdev);
4694
6c167f58
EK		 4695 err = i40e_vsi_open(vsi);
4696 if (err)
4697 return err;
4698
059dab69
JB		 4699 /* configure global TSO hardware offload settings */
4700 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4701 TCP_FLAG_FIN) >> 16);
4702 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4703 TCP_FLAG_FIN |
4704 TCP_FLAG_CWR) >> 16);
4705 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4706
6c167f58
EK		 4707#ifdef CONFIG_I40E_VXLAN
4708 vxlan_get_rx_port(netdev);
4709#endif
4710
4711 return 0;
4712}
4713
4714/**
4715 * i40e_vsi_open -
4716 * @vsi: the VSI to open
4717 *
4718 * Finish initialization of the VSI.
4719 *
4720 * Returns 0 on success, negative value on failure
4721 **/
4722int i40e_vsi_open(struct i40e_vsi *vsi)
4723{
4724 struct i40e_pf *pf = vsi->back;
4725 char int_name[IFNAMSIZ];
4726 int err;
4727
41c445ff
JB		 4728 /* allocate descriptors */
4729 err = i40e_vsi_setup_tx_resources(vsi);
4730 if (err)
4731 goto err_setup_tx;
4732 err = i40e_vsi_setup_rx_resources(vsi);
4733 if (err)
4734 goto err_setup_rx;
4735
4736 err = i40e_vsi_configure(vsi);
4737 if (err)
4738 goto err_setup_rx;
4739
c22e3c6c
SN		 4740 if (vsi->netdev) {
4741 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4742 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4743 err = i40e_vsi_request_irq(vsi, int_name);
4744 if (err)
4745 goto err_setup_rx;
41c445ff 4746
c22e3c6c
SN		 4747 /* Notify the stack of the actual queue counts. */
4748 err = netif_set_real_num_tx_queues(vsi->netdev,
4749 vsi->num_queue_pairs);
4750 if (err)
4751 goto err_set_queues;
25946ddb 4752
c22e3c6c
SN		 4753 err = netif_set_real_num_rx_queues(vsi->netdev,
4754 vsi->num_queue_pairs);
4755 if (err)
4756 goto err_set_queues;
8a9eb7d3
SN		 4757
4758 } else if (vsi->type == I40E_VSI_FDIR) {
4759 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4760 dev_driver_string(&pf->pdev->dev));
4761 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4762 } else {
ce9ccb17 4763 err = -EINVAL;
6c167f58
EK		 4764 goto err_setup_rx;
4765 }
25946ddb 4766
41c445ff
JB		 4767 err = i40e_up_complete(vsi);
4768 if (err)
4769 goto err_up_complete;
4770
41c445ff
JB		 4771 return 0;
4772
4773err_up_complete:
4774 i40e_down(vsi);
25946ddb 4775err_set_queues:
41c445ff
JB		 4776 i40e_vsi_free_irq(vsi);
4777err_setup_rx:
4778 i40e_vsi_free_rx_resources(vsi);
4779err_setup_tx:
4780 i40e_vsi_free_tx_resources(vsi);
4781 if (vsi == pf->vsi[pf->lan_vsi])
4782 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4783
4784 return err;
4785}
4786
17a73f6b
JG		 4787/**
4788 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4789 * @pf: Pointer to pf
4790 *
4791 * This function destroys the hlist where all the Flow Director
4792 * filters were saved.
4793 **/
4794static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4795{
4796 struct i40e_fdir_filter *filter;
4797 struct hlist_node *node2;
4798
4799 hlist_for_each_entry_safe(filter, node2,
4800 &pf->fdir_filter_list, fdir_node) {
4801 hlist_del(&filter->fdir_node);
4802 kfree(filter);
4803 }
4804 pf->fdir_pf_active_filters = 0;
4805}
4806
41c445ff
JB		 4807/**
4808 * i40e_close - Disables a network interface
4809 * @netdev: network interface device structure
4810 *
4811 * The close entry point is called when an interface is de-activated
4812 * by the OS. The hardware is still under the driver's control, but
4813 * this netdev interface is disabled.
4814 *
4815 * Returns 0, this is not allowed to fail
4816 **/
38e00438
VD		 4817#ifdef I40E_FCOE
4818int i40e_close(struct net_device *netdev)
4819#else
41c445ff 4820static int i40e_close(struct net_device *netdev)
38e00438 4821#endif
41c445ff
JB		 4822{
4823 struct i40e_netdev_priv *np = netdev_priv(netdev);
4824 struct i40e_vsi *vsi = np->vsi;
4825
90ef8d47 4826 i40e_vsi_close(vsi);
41c445ff
JB		 4827
4828 return 0;
4829}
4830
4831/**
4832 * i40e_do_reset - Start a PF or Core Reset sequence
4833 * @pf: board private structure
4834 * @reset_flags: which reset is requested
4835 *
4836 * The essential difference in resets is that the PF Reset
4837 * doesn't clear the packet buffers, doesn't reset the PE
4838 * firmware, and doesn't bother the other PFs on the chip.
4839 **/
4840void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4841{
4842 u32 val;
4843
4844 WARN_ON(in_interrupt());
4845
263fc48f
MW		 4846 if (i40e_check_asq_alive(&pf->hw))
4847 i40e_vc_notify_reset(pf);
4848
41c445ff
JB		 4849 /* do the biggest reset indicated */
4850 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4851
4852 /* Request a Global Reset
4853 *
4854 * This will start the chip's countdown to the actual full
4855 * chip reset event, and a warning interrupt to be sent
4856 * to all PFs, including the requestor. Our handler
4857 * for the warning interrupt will deal with the shutdown
4858 * and recovery of the switch setup.
4859 */
69bfb110 4860 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4861 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4862 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4863 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4864
4865 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4866
4867 /* Request a Core Reset
4868 *
4869 * Same as Global Reset, except does *not* include the MAC/PHY
4870 */
69bfb110 4871 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4872 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4873 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4874 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4875 i40e_flush(&pf->hw);
4876
7823fe34
SN		 4877 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4878
4879 /* Request a Firmware Reset
4880 *
4881 * Same as Global reset, plus restarting the
4882 * embedded firmware engine.
4883 */
4884 /* enable EMP Reset */
4885 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4886 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4887 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4888
4889 /* force the reset */
4890 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4891 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4892 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4893 i40e_flush(&pf->hw);
4894
41c445ff
JB		 4895 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4896
4897 /* Request a PF Reset
4898 *
4899 * Resets only the PF-specific registers
4900 *
4901 * This goes directly to the tear-down and rebuild of
4902 * the switch, since we need to do all the recovery as
4903 * for the Core Reset.
4904 */
69bfb110 4905 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4906 i40e_handle_reset_warning(pf);
4907
4908 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4909 int v;
4910
4911 /* Find the VSI(s) that requested a re-init */
4912 dev_info(&pf->pdev->dev,
4913 "VSI reinit requested\n");
505682cd 4914 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4915 struct i40e_vsi *vsi = pf->vsi[v];
4916 if (vsi != NULL &&
4917 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4918 i40e_vsi_reinit_locked(pf->vsi[v]);
4919 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4920 }
4921 }
4922
b5d06f05
NP		 4923 /* no further action needed, so return now */
4924 return;
4925 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
4926 int v;
4927
4928 /* Find the VSI(s) that needs to be brought down */
4929 dev_info(&pf->pdev->dev, "VSI down requested\n");
4930 for (v = 0; v < pf->num_alloc_vsi; v++) {
4931 struct i40e_vsi *vsi = pf->vsi[v];
4932 if (vsi != NULL &&
4933 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
4934 set_bit(__I40E_DOWN, &vsi->state);
4935 i40e_down(vsi);
4936 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
4937 }
4938 }
4939
41c445ff
JB		 4940 /* no further action needed, so return now */
4941 return;
4942 } else {
4943 dev_info(&pf->pdev->dev,
4944 "bad reset request 0x%08x\n", reset_flags);
4945 return;
4946 }
4947}
4948
4e3b35b0
NP		 4949#ifdef CONFIG_I40E_DCB
4950/**
4951 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4952 * @pf: board private structure
4953 * @old_cfg: current DCB config
4954 * @new_cfg: new DCB config
4955 **/
4956bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4957 struct i40e_dcbx_config *old_cfg,
4958 struct i40e_dcbx_config *new_cfg)
4959{
4960 bool need_reconfig = false;
4961
4962 /* Check if ETS configuration has changed */
4963 if (memcmp(&new_cfg->etscfg,
4964 &old_cfg->etscfg,
4965 sizeof(new_cfg->etscfg))) {
4966 /* If Priority Table has changed reconfig is needed */
4967 if (memcmp(&new_cfg->etscfg.prioritytable,
4968 &old_cfg->etscfg.prioritytable,
4969 sizeof(new_cfg->etscfg.prioritytable))) {
4970 need_reconfig = true;
69bfb110 4971 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4972 }
4973
4974 if (memcmp(&new_cfg->etscfg.tcbwtable,
4975 &old_cfg->etscfg.tcbwtable,
4976 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4977 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4978
4979 if (memcmp(&new_cfg->etscfg.tsatable,
4980 &old_cfg->etscfg.tsatable,
4981 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4982 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4983 }
4984
4985 /* Check if PFC configuration has changed */
4986 if (memcmp(&new_cfg->pfc,
4987 &old_cfg->pfc,
4988 sizeof(new_cfg->pfc))) {
4989 need_reconfig = true;
69bfb110 4990 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4991 }
4992
4993 /* Check if APP Table has changed */
4994 if (memcmp(&new_cfg->app,
4995 &old_cfg->app,
3d9667a9 4996 sizeof(new_cfg->app))) {
4e3b35b0 4997 need_reconfig = true;
69bfb110 4998 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4999 }
4e3b35b0
NP		 5000
5001 return need_reconfig;
5002}
5003
5004/**
5005 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5006 * @pf: board private structure
5007 * @e: event info posted on ARQ
5008 **/
5009static int i40e_handle_lldp_event(struct i40e_pf *pf,
5010 struct i40e_arq_event_info *e)
5011{
5012 struct i40e_aqc_lldp_get_mib *mib =
5013 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5014 struct i40e_hw *hw = &pf->hw;
5015 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
5016 struct i40e_dcbx_config tmp_dcbx_cfg;
5017 bool need_reconfig = false;
5018 int ret = 0;
5019 u8 type;
5020
4d9b6043
NP		 5021 /* Not DCB capable or capability disabled */
5022 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5023 return ret;
5024
4e3b35b0
NP		 5025 /* Ignore if event is not for Nearest Bridge */
5026 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5027 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
5028 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5029 return ret;
5030
5031 /* Check MIB Type and return if event for Remote MIB update */
5032 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
5033 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5034 /* Update the remote cached instance and return */
5035 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5036 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5037 &hw->remote_dcbx_config);
5038 goto exit;
5039 }
5040
5041 /* Convert/store the DCBX data from LLDPDU temporarily */
5042 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
5043 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
5044 if (ret) {
5045 /* Error in LLDPDU parsing return */
5046 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
5047 goto exit;
5048 }
5049
5050 /* No change detected in DCBX configs */
5051 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 5052 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5053 goto exit;
5054 }
5055
5056 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
5057
5058 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
5059
5060 /* Overwrite the new configuration */
5061 *dcbx_cfg = tmp_dcbx_cfg;
5062
5063 if (!need_reconfig)
5064 goto exit;
5065
4d9b6043
NP		 5066 /* Enable DCB tagging only when more than one TC */
5067 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
5068 pf->flags |= I40E_FLAG_DCB_ENABLED;
5069 else
5070 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5071
4e3b35b0
NP		 5072 /* Reconfiguration needed quiesce all VSIs */
5073 i40e_pf_quiesce_all_vsi(pf);
5074
5075 /* Changes in configuration update VEB/VSI */
5076 i40e_dcb_reconfigure(pf);
5077
5078 i40e_pf_unquiesce_all_vsi(pf);
5079exit:
5080 return ret;
5081}
5082#endif /* CONFIG_I40E_DCB */
5083
23326186
ASJ		 5084/**
5085 * i40e_do_reset_safe - Protected reset path for userland calls.
5086 * @pf: board private structure
5087 * @reset_flags: which reset is requested
5088 *
5089 **/
5090void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5091{
5092 rtnl_lock();
5093 i40e_do_reset(pf, reset_flags);
5094 rtnl_unlock();
5095}
5096
41c445ff
JB		 5097/**
5098 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5099 * @pf: board private structure
5100 * @e: event info posted on ARQ
5101 *
5102 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5103 * and VF queues
5104 **/
5105static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5106 struct i40e_arq_event_info *e)
5107{
5108 struct i40e_aqc_lan_overflow *data =
5109 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5110 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5111 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5112 struct i40e_hw *hw = &pf->hw;
5113 struct i40e_vf *vf;
5114 u16 vf_id;
5115
69bfb110
JB		 5116 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5117 queue, qtx_ctl);
41c445ff
JB		 5118
5119 /* Queue belongs to VF, find the VF and issue VF reset */
5120 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5121 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5122 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5123 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5124 vf_id -= hw->func_caps.vf_base_id;
5125 vf = &pf->vf[vf_id];
5126 i40e_vc_notify_vf_reset(vf);
5127 /* Allow VF to process pending reset notification */
5128 msleep(20);
5129 i40e_reset_vf(vf, false);
5130 }
5131}
5132
5133/**
5134 * i40e_service_event_complete - Finish up the service event
5135 * @pf: board private structure
5136 **/
5137static void i40e_service_event_complete(struct i40e_pf *pf)
5138{
5139 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5140
5141 /* flush memory to make sure state is correct before next watchog */
4e857c58 5142 smp_mb__before_atomic();
41c445ff
JB		 5143 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5144}
5145
55a5e60b 5146/**
12957388
ASJ		 5147 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5148 * @pf: board private structure
5149 **/
5150int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
5151{
5152 int val, fcnt_prog;
5153
5154 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5155 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5156 return fcnt_prog;
5157}
5158
5159/**
5160 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 5161 * @pf: board private structure
5162 **/
5163int i40e_get_current_fd_count(struct i40e_pf *pf)
5164{
5165 int val, fcnt_prog;
5166 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5167 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5168 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5169 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5170 return fcnt_prog;
5171}
1e1be8f6 5172
55a5e60b
ASJ		 5173/**
5174 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5175 * @pf: board private structure
5176 **/
5177void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5178{
5179 u32 fcnt_prog, fcnt_avail;
5180
1e1be8f6
ASJ		 5181 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5182 return;
5183
55a5e60b
ASJ		 5184 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5185 * to re-enable
5186 */
12957388
ASJ		 5187 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5188 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5189 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5190 (pf->fd_add_err == 0) ||
5191 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5192 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5193 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5194 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5195 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5196 }
5197 }
5198 /* Wait for some more space to be available to turn on ATR */
5199 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5200 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5201 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5202 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5203 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5204 }
5205 }
5206}
5207
1e1be8f6
ASJ		 5208#define I40E_MIN_FD_FLUSH_INTERVAL 10
5209/**
5210 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5211 * @pf: board private structure
5212 **/
5213static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5214{
5215 int flush_wait_retry = 50;
5216 int reg;
5217
1790ed0c
AA		 5218 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5219 return;
5220
1e1be8f6
ASJ		 5221 if (time_after(jiffies, pf->fd_flush_timestamp +
5222 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
5223 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5224 pf->fd_flush_timestamp = jiffies;
5225 pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
5226 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5227 /* flush all filters */
5228 wr32(&pf->hw, I40E_PFQF_CTL_1,
5229 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5230 i40e_flush(&pf->hw);
60793f4a 5231 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5232 pf->fd_add_err = 0;
5233 do {
5234 /* Check FD flush status every 5-6msec */
5235 usleep_range(5000, 6000);
5236 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5237 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5238 break;
5239 } while (flush_wait_retry--);
5240 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5241 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5242 } else {
5243 /* replay sideband filters */
5244 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5245
5246 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5247 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5248 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5249 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5250 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5251 }
5252 }
5253}
5254
5255/**
5256 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5257 * @pf: board private structure
5258 **/
5259int i40e_get_current_atr_cnt(struct i40e_pf *pf)
5260{
5261 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5262}
5263
5264/* We can see up to 256 filter programming desc in transit if the filters are
5265 * being applied really fast; before we see the first
5266 * filter miss error on Rx queue 0. Accumulating enough error messages before
5267 * reacting will make sure we don't cause flush too often.
5268 */
5269#define I40E_MAX_FD_PROGRAM_ERROR 256
5270
41c445ff
JB		 5271/**
5272 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5273 * @pf: board private structure
5274 **/
5275static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5276{
41c445ff 5277
41c445ff
JB		 5278 /* if interface is down do nothing */
5279 if (test_bit(__I40E_DOWN, &pf->state))
5280 return;
1e1be8f6 5281
1790ed0c
AA		 5282 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5283 return;
5284
1e1be8f6
ASJ		 5285 if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
5286 (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
5287 (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
5288 i40e_fdir_flush_and_replay(pf);
5289
55a5e60b
ASJ		 5290 i40e_fdir_check_and_reenable(pf);
5291
41c445ff
JB		 5292}
5293
5294/**
5295 * i40e_vsi_link_event - notify VSI of a link event
5296 * @vsi: vsi to be notified
5297 * @link_up: link up or down
5298 **/
5299static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5300{
32b5b811 5301 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5302 return;
5303
5304 switch (vsi->type) {
5305 case I40E_VSI_MAIN:
38e00438
VD		 5306#ifdef I40E_FCOE
5307 case I40E_VSI_FCOE:
5308#endif
41c445ff
JB		 5309 if (!vsi->netdev || !vsi->netdev_registered)
5310 break;
5311
5312 if (link_up) {
5313 netif_carrier_on(vsi->netdev);
5314 netif_tx_wake_all_queues(vsi->netdev);
5315 } else {
5316 netif_carrier_off(vsi->netdev);
5317 netif_tx_stop_all_queues(vsi->netdev);
5318 }
5319 break;
5320
5321 case I40E_VSI_SRIOV:
5322 break;
5323
5324 case I40E_VSI_VMDQ2:
5325 case I40E_VSI_CTRL:
5326 case I40E_VSI_MIRROR:
5327 default:
5328 /* there is no notification for other VSIs */
5329 break;
5330 }
5331}
5332
5333/**
5334 * i40e_veb_link_event - notify elements on the veb of a link event
5335 * @veb: veb to be notified
5336 * @link_up: link up or down
5337 **/
5338static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5339{
5340 struct i40e_pf *pf;
5341 int i;
5342
5343 if (!veb || !veb->pf)
5344 return;
5345 pf = veb->pf;
5346
5347 /* depth first... */
5348 for (i = 0; i < I40E_MAX_VEB; i++)
5349 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5350 i40e_veb_link_event(pf->veb[i], link_up);
5351
5352 /* ... now the local VSIs */
505682cd 5353 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5354 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5355 i40e_vsi_link_event(pf->vsi[i], link_up);
5356}
5357
5358/**
5359 * i40e_link_event - Update netif_carrier status
5360 * @pf: board private structure
5361 **/
5362static void i40e_link_event(struct i40e_pf *pf)
5363{
5364 bool new_link, old_link;
320684cd 5365 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
41c445ff 5366
1e701e09
JB		 5367 /* set this to force the get_link_status call to refresh state */
5368 pf->hw.phy.get_link_info = true;
5369
41c445ff 5370 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5371 new_link = i40e_get_link_status(&pf->hw);
41c445ff 5372
1e701e09 5373 if (new_link == old_link &&
320684cd
MW		 5374 (test_bit(__I40E_DOWN, &vsi->state) ||
5375 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5376 return;
320684cd
MW		 5377
5378 if (!test_bit(__I40E_DOWN, &vsi->state))
5379 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5380
5381 /* Notify the base of the switch tree connected to
5382 * the link. Floating VEBs are not notified.
5383 */
5384 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5385 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5386 else
320684cd 5387 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5388
5389 if (pf->vf)
5390 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5391
5392 if (pf->flags & I40E_FLAG_PTP)
5393 i40e_ptp_set_increment(pf);
41c445ff
JB		 5394}
5395
5396/**
5397 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5398 * @pf: board private structure
5399 *
5400 * Set the per-queue flags to request a check for stuck queues in the irq
5401 * clean functions, then force interrupts to be sure the irq clean is called.
5402 **/
5403static void i40e_check_hang_subtask(struct i40e_pf *pf)
5404{
5405 int i, v;
5406
5407 /* If we're down or resetting, just bail */
5408 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5409 return;
5410
5411 /* for each VSI/netdev
5412 * for each Tx queue
5413 * set the check flag
5414 * for each q_vector
5415 * force an interrupt
5416 */
505682cd 5417 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5418 struct i40e_vsi *vsi = pf->vsi[v];
5419 int armed = 0;
5420
5421 if (!pf->vsi[v] ||
5422 test_bit(__I40E_DOWN, &vsi->state) ||
5423 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5424 continue;
5425
5426 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5427 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5428 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5429 &vsi->tx_rings[i]->state))
41c445ff
JB		 5430 armed++;
5431 }
5432
5433 if (armed) {
5434 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5435 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5436 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5437 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5438 } else {
5439 u16 vec = vsi->base_vector - 1;
5440 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5441 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5442 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5443 wr32(&vsi->back->hw,
5444 I40E_PFINT_DYN_CTLN(vec), val);
5445 }
5446 i40e_flush(&vsi->back->hw);
5447 }
5448 }
5449}
5450
5451/**
5452 * i40e_watchdog_subtask - Check and bring link up
5453 * @pf: board private structure
5454 **/
5455static void i40e_watchdog_subtask(struct i40e_pf *pf)
5456{
5457 int i;
5458
5459 /* if interface is down do nothing */
5460 if (test_bit(__I40E_DOWN, &pf->state) ||
5461 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5462 return;
5463
5464 /* Update the stats for active netdevs so the network stack
5465 * can look at updated numbers whenever it cares to
5466 */
505682cd 5467 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5468 if (pf->vsi[i] && pf->vsi[i]->netdev)
5469 i40e_update_stats(pf->vsi[i]);
5470
5471 /* Update the stats for the active switching components */
5472 for (i = 0; i < I40E_MAX_VEB; i++)
5473 if (pf->veb[i])
5474 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5475
5476 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5477}
5478
5479/**
5480 * i40e_reset_subtask - Set up for resetting the device and driver
5481 * @pf: board private structure
5482 **/
5483static void i40e_reset_subtask(struct i40e_pf *pf)
5484{
5485 u32 reset_flags = 0;
5486
23326186 5487 rtnl_lock();
41c445ff
JB		 5488 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5489 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5490 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5491 }
5492 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5493 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5494 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5495 }
5496 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5497 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5498 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5499 }
5500 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5501 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5502 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5503 }
b5d06f05
NP		 5504 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5505 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5506 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5507 }
41c445ff
JB		 5508
5509 /* If there's a recovery already waiting, it takes
5510 * precedence before starting a new reset sequence.
5511 */
5512 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5513 i40e_handle_reset_warning(pf);
23326186 5514 goto unlock;
41c445ff
JB		 5515 }
5516
5517 /* If we're already down or resetting, just bail */
5518 if (reset_flags &&
5519 !test_bit(__I40E_DOWN, &pf->state) &&
5520 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5521 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5522
5523unlock:
5524 rtnl_unlock();
41c445ff
JB		 5525}
5526
5527/**
5528 * i40e_handle_link_event - Handle link event
5529 * @pf: board private structure
5530 * @e: event info posted on ARQ
5531 **/
5532static void i40e_handle_link_event(struct i40e_pf *pf,
5533 struct i40e_arq_event_info *e)
5534{
5535 struct i40e_hw *hw = &pf->hw;
5536 struct i40e_aqc_get_link_status *status =
5537 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5538 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5539
5540 /* save off old link status information */
5541 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5542 sizeof(pf->hw.phy.link_info_old));
5543
1e701e09
JB		 5544 /* Do a new status request to re-enable LSE reporting
5545 * and load new status information into the hw struct
5546 * This completely ignores any state information
5547 * in the ARQ event info, instead choosing to always
5548 * issue the AQ update link status command.
5549 */
5550 i40e_link_event(pf);
5551
7b592f61
CW		 5552 /* check for unqualified module, if link is down */
5553 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5554 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5555 (!(status->link_info & I40E_AQ_LINK_UP)))
5556 dev_err(&pf->pdev->dev,
5557 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5558}
5559
5560/**
5561 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5562 * @pf: board private structure
5563 **/
5564static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5565{
5566 struct i40e_arq_event_info event;
5567 struct i40e_hw *hw = &pf->hw;
5568 u16 pending, i = 0;
5569 i40e_status ret;
5570 u16 opcode;
86df242b 5571 u32 oldval;
41c445ff
JB		 5572 u32 val;
5573
a316f651
ASJ		 5574 /* Do not run clean AQ when PF reset fails */
5575 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5576 return;
5577
86df242b
SN		 5578 /* check for error indications */
5579 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5580 oldval = val;
5581 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5582 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5583 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5584 }
5585 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5586 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5587 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5588 }
5589 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5590 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5591 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5592 }
5593 if (oldval != val)
5594 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5595
5596 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5597 oldval = val;
5598 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5599 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5600 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5601 }
5602 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5603 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5604 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5605 }
5606 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5607 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5608 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5609 }
5610 if (oldval != val)
5611 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5612
3197ce22 5613 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5614 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5615 if (!event.msg_buf)
5616 return;
5617
5618 do {
2f019123 5619 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff 5620 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5621 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5622 break;
56497978 5623 else if (ret) {
41c445ff
JB		 5624 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5625 break;
5626 }
5627
5628 opcode = le16_to_cpu(event.desc.opcode);
5629 switch (opcode) {
5630
5631 case i40e_aqc_opc_get_link_status:
5632 i40e_handle_link_event(pf, &event);
5633 break;
5634 case i40e_aqc_opc_send_msg_to_pf:
5635 ret = i40e_vc_process_vf_msg(pf,
5636 le16_to_cpu(event.desc.retval),
5637 le32_to_cpu(event.desc.cookie_high),
5638 le32_to_cpu(event.desc.cookie_low),
5639 event.msg_buf,
5640 event.msg_size);
5641 break;
5642 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5643 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5644#ifdef CONFIG_I40E_DCB
5645 rtnl_lock();
5646 ret = i40e_handle_lldp_event(pf, &event);
5647 rtnl_unlock();
5648#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5649 break;
5650 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5651 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5652 i40e_handle_lan_overflow_event(pf, &event);
5653 break;
0467bc91
SN		 5654 case i40e_aqc_opc_send_msg_to_peer:
5655 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5656 break;
41c445ff
JB		 5657 default:
5658 dev_info(&pf->pdev->dev,
0467bc91
SN		 5659 "ARQ Error: Unknown event 0x%04x received\n",
5660 opcode);
41c445ff
JB		 5661 break;
5662 }
5663 } while (pending && (i++ < pf->adminq_work_limit));
5664
5665 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5666 /* re-enable Admin queue interrupt cause */
5667 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5668 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5669 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5670 i40e_flush(hw);
5671
5672 kfree(event.msg_buf);
5673}
5674
4eb3f768
SN		 5675/**
5676 * i40e_verify_eeprom - make sure eeprom is good to use
5677 * @pf: board private structure
5678 **/
5679static void i40e_verify_eeprom(struct i40e_pf *pf)
5680{
5681 int err;
5682
5683 err = i40e_diag_eeprom_test(&pf->hw);
5684 if (err) {
5685 /* retry in case of garbage read */
5686 err = i40e_diag_eeprom_test(&pf->hw);
5687 if (err) {
5688 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5689 err);
5690 set_bit(__I40E_BAD_EEPROM, &pf->state);
5691 }
5692 }
5693
5694 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5695 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5696 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5697 }
5698}
5699
41c445ff
JB		 5700/**
5701 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5702 * @veb: pointer to the VEB instance
5703 *
5704 * This is a recursive function that first builds the attached VSIs then
5705 * recurses in to build the next layer of VEB. We track the connections
5706 * through our own index numbers because the seid's from the HW could
5707 * change across the reset.
5708 **/
5709static int i40e_reconstitute_veb(struct i40e_veb *veb)
5710{
5711 struct i40e_vsi *ctl_vsi = NULL;
5712 struct i40e_pf *pf = veb->pf;
5713 int v, veb_idx;
5714 int ret;
5715
5716 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5717 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5718 if (pf->vsi[v] &&
5719 pf->vsi[v]->veb_idx == veb->idx &&
5720 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5721 ctl_vsi = pf->vsi[v];
5722 break;
5723 }
5724 }
5725 if (!ctl_vsi) {
5726 dev_info(&pf->pdev->dev,
5727 "missing owner VSI for veb_idx %d\n", veb->idx);
5728 ret = -ENOENT;
5729 goto end_reconstitute;
5730 }
5731 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5732 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5733 ret = i40e_add_vsi(ctl_vsi);
5734 if (ret) {
5735 dev_info(&pf->pdev->dev,
5736 "rebuild of owner VSI failed: %d\n", ret);
5737 goto end_reconstitute;
5738 }
5739 i40e_vsi_reset_stats(ctl_vsi);
5740
5741 /* create the VEB in the switch and move the VSI onto the VEB */
5742 ret = i40e_add_veb(veb, ctl_vsi);
5743 if (ret)
5744 goto end_reconstitute;
5745
5746 /* create the remaining VSIs attached to this VEB */
505682cd 5747 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5748 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5749 continue;
5750
5751 if (pf->vsi[v]->veb_idx == veb->idx) {
5752 struct i40e_vsi *vsi = pf->vsi[v];
5753 vsi->uplink_seid = veb->seid;
5754 ret = i40e_add_vsi(vsi);
5755 if (ret) {
5756 dev_info(&pf->pdev->dev,
5757 "rebuild of vsi_idx %d failed: %d\n",
5758 v, ret);
5759 goto end_reconstitute;
5760 }
5761 i40e_vsi_reset_stats(vsi);
5762 }
5763 }
5764
5765 /* create any VEBs attached to this VEB - RECURSION */
5766 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5767 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5768 pf->veb[veb_idx]->uplink_seid = veb->seid;
5769 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5770 if (ret)
5771 break;
5772 }
5773 }
5774
5775end_reconstitute:
5776 return ret;
5777}
5778
5779/**
5780 * i40e_get_capabilities - get info about the HW
5781 * @pf: the PF struct
5782 **/
5783static int i40e_get_capabilities(struct i40e_pf *pf)
5784{
5785 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5786 u16 data_size;
5787 int buf_len;
5788 int err;
5789
5790 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5791 do {
5792 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5793 if (!cap_buf)
5794 return -ENOMEM;
5795
5796 /* this loads the data into the hw struct for us */
5797 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5798 &data_size,
5799 i40e_aqc_opc_list_func_capabilities,
5800 NULL);
5801 /* data loaded, buffer no longer needed */
5802 kfree(cap_buf);
5803
5804 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5805 /* retry with a larger buffer */
5806 buf_len = data_size;
5807 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5808 dev_info(&pf->pdev->dev,
5809 "capability discovery failed: aq=%d\n",
5810 pf->hw.aq.asq_last_status);
5811 return -ENODEV;
5812 }
5813 } while (err);
5814
ac71b7ba
ASJ		 5815 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5816 (pf->hw.aq.fw_maj_ver < 2)) {
5817 pf->hw.func_caps.num_msix_vectors++;
5818 pf->hw.func_caps.num_msix_vectors_vf++;
5819 }
5820
41c445ff
JB		 5821 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5822 dev_info(&pf->pdev->dev,
5823 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5824 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5825 pf->hw.func_caps.num_msix_vectors,
5826 pf->hw.func_caps.num_msix_vectors_vf,
5827 pf->hw.func_caps.fd_filters_guaranteed,
5828 pf->hw.func_caps.fd_filters_best_effort,
5829 pf->hw.func_caps.num_tx_qp,
5830 pf->hw.func_caps.num_vsis);
5831
7134f9ce
JB		 5832#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5833 + pf->hw.func_caps.num_vfs)
5834 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5835 dev_info(&pf->pdev->dev,
5836 "got num_vsis %d, setting num_vsis to %d\n",
5837 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5838 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5839 }
5840
41c445ff
JB		 5841 return 0;
5842}
5843
cbf61325
ASJ		 5844static int i40e_vsi_clear(struct i40e_vsi *vsi);
5845
41c445ff 5846/**
cbf61325 5847 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5848 * @pf: board private structure
5849 **/
cbf61325 5850static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5851{
5852 struct i40e_vsi *vsi;
8a9eb7d3 5853 int i;
41c445ff 5854
407e063c
JB		 5855 /* quick workaround for an NVM issue that leaves a critical register
5856 * uninitialized
5857 */
5858 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
5859 static const u32 hkey[] = {
5860 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
5861 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
5862 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
5863 0x95b3a76d};
5864
5865 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
5866 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
5867 }
5868
cbf61325 5869 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5870 return;
5871
cbf61325 5872 /* find existing VSI and see if it needs configuring */
41c445ff 5873 vsi = NULL;
505682cd 5874 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 5875 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5876 vsi = pf->vsi[i];
cbf61325
ASJ		 5877 break;
5878 }
5879 }
5880
5881 /* create a new VSI if none exists */
41c445ff 5882 if (!vsi) {
cbf61325
ASJ		 5883 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5884 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5885 if (!vsi) {
5886 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5887 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5888 return;
41c445ff 5889 }
cbf61325 5890 }
41c445ff 5891
8a9eb7d3 5892 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5893}
5894
5895/**
5896 * i40e_fdir_teardown - release the Flow Director resources
5897 * @pf: board private structure
5898 **/
5899static void i40e_fdir_teardown(struct i40e_pf *pf)
5900{
5901 int i;
5902
17a73f6b 5903 i40e_fdir_filter_exit(pf);
505682cd 5904 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 5905 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5906 i40e_vsi_release(pf->vsi[i]);
5907 break;
5908 }
5909 }
5910}
5911
5912/**
f650a38b 5913 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5914 * @pf: board private structure
5915 *
f650a38b
ASJ		 5916 * Close up the VFs and other things in prep for pf Reset.
5917 **/
23cfbe07 5918static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5919{
41c445ff 5920 struct i40e_hw *hw = &pf->hw;
60442dea 5921 i40e_status ret = 0;
41c445ff
JB		 5922 u32 v;
5923
5924 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5925 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 5926 return;
41c445ff 5927
69bfb110 5928 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5929
41c445ff
JB		 5930 /* quiesce the VSIs and their queues that are not already DOWN */
5931 i40e_pf_quiesce_all_vsi(pf);
5932
505682cd 5933 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5934 if (pf->vsi[v])
5935 pf->vsi[v]->seid = 0;
5936 }
5937
5938 i40e_shutdown_adminq(&pf->hw);
5939
f650a38b 5940 /* call shutdown HMC */
60442dea
SN		 5941 if (hw->hmc.hmc_obj) {
5942 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 5943 if (ret)
60442dea
SN		 5944 dev_warn(&pf->pdev->dev,
5945 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 5946 }
f650a38b
ASJ		 5947}
5948
44033fac
JB		 5949/**
5950 * i40e_send_version - update firmware with driver version
5951 * @pf: PF struct
5952 */
5953static void i40e_send_version(struct i40e_pf *pf)
5954{
5955 struct i40e_driver_version dv;
5956
5957 dv.major_version = DRV_VERSION_MAJOR;
5958 dv.minor_version = DRV_VERSION_MINOR;
5959 dv.build_version = DRV_VERSION_BUILD;
5960 dv.subbuild_version = 0;
35a7d804 5961 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 5962 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5963}
5964
f650a38b 5965/**
4dda12e6 5966 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5967 * @pf: board private structure
bc7d338f 5968 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5969 **/
bc7d338f 5970static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5971{
f650a38b 5972 struct i40e_hw *hw = &pf->hw;
cafa2ee6 5973 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 5974 i40e_status ret;
5975 u32 v;
5976
41c445ff
JB		 5977 /* Now we wait for GRST to settle out.
5978 * We don't have to delete the VEBs or VSIs from the hw switch
5979 * because the reset will make them disappear.
5980 */
5981 ret = i40e_pf_reset(hw);
b5565400 5982 if (ret) {
41c445ff 5983 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 5984 set_bit(__I40E_RESET_FAILED, &pf->state);
5985 goto clear_recovery;
b5565400 5986 }
41c445ff
JB		 5987 pf->pfr_count++;
5988
5989 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 5990 goto clear_recovery;
69bfb110 5991 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5992
5993 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5994 ret = i40e_init_adminq(&pf->hw);
5995 if (ret) {
5996 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 5997 goto clear_recovery;
41c445ff
JB		 5998 }
5999
4eb3f768
SN		 6000 /* re-verify the eeprom if we just had an EMP reset */
6001 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
6002 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
6003 i40e_verify_eeprom(pf);
6004 }
6005
e78ac4bf 6006 i40e_clear_pxe_mode(hw);
41c445ff
JB		 6007 ret = i40e_get_capabilities(pf);
6008 if (ret) {
6009 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
6010 ret);
6011 goto end_core_reset;
6012 }
6013
41c445ff
JB		 6014 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6015 hw->func_caps.num_rx_qp,
6016 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6017 if (ret) {
6018 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6019 goto end_core_reset;
6020 }
6021 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6022 if (ret) {
6023 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6024 goto end_core_reset;
6025 }
6026
4e3b35b0
NP		 6027#ifdef CONFIG_I40E_DCB
6028 ret = i40e_init_pf_dcb(pf);
6029 if (ret) {
6030 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
6031 goto end_core_reset;
6032 }
6033#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6034#ifdef I40E_FCOE
6035 ret = i40e_init_pf_fcoe(pf);
6036 if (ret)
6037 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6038
38e00438 6039#endif
41c445ff 6040 /* do basic switch setup */
bc7d338f 6041 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6042 if (ret)
6043 goto end_core_reset;
6044
7e2453fe
JB		 6045 /* driver is only interested in link up/down and module qualification
6046 * reports from firmware
6047 */
6048 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6049 I40E_AQ_EVENT_LINK_UPDOWN |
6050 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6051 if (ret)
6052 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6053
cafa2ee6
ASJ		 6054 /* make sure our flow control settings are restored */
6055 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6056 if (ret)
6057 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6058
41c445ff
JB		 6059 /* Rebuild the VSIs and VEBs that existed before reset.
6060 * They are still in our local switch element arrays, so only
6061 * need to rebuild the switch model in the HW.
6062 *
6063 * If there were VEBs but the reconstitution failed, we'll try
6064 * try to recover minimal use by getting the basic PF VSI working.
6065 */
6066 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6067 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6068 /* find the one VEB connected to the MAC, and find orphans */
6069 for (v = 0; v < I40E_MAX_VEB; v++) {
6070 if (!pf->veb[v])
6071 continue;
6072
6073 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6074 pf->veb[v]->uplink_seid == 0) {
6075 ret = i40e_reconstitute_veb(pf->veb[v]);
6076
6077 if (!ret)
6078 continue;
6079
6080 /* If Main VEB failed, we're in deep doodoo,
6081 * so give up rebuilding the switch and set up
6082 * for minimal rebuild of PF VSI.
6083 * If orphan failed, we'll report the error
6084 * but try to keep going.
6085 */
6086 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6087 dev_info(&pf->pdev->dev,
6088 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6089 ret);
6090 pf->vsi[pf->lan_vsi]->uplink_seid
6091 = pf->mac_seid;
6092 break;
6093 } else if (pf->veb[v]->uplink_seid == 0) {
6094 dev_info(&pf->pdev->dev,
6095 "rebuild of orphan VEB failed: %d\n",
6096 ret);
6097 }
6098 }
6099 }
6100 }
6101
6102 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6103 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6104 /* no VEB, so rebuild only the Main VSI */
6105 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6106 if (ret) {
6107 dev_info(&pf->pdev->dev,
6108 "rebuild of Main VSI failed: %d\n", ret);
6109 goto end_core_reset;
6110 }
6111 }
6112
cafa2ee6
ASJ		 6113 msleep(75);
6114 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6115 if (ret) {
6116 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6117 pf->hw.aq.asq_last_status);
6118 }
6119
41c445ff
JB		 6120 /* reinit the misc interrupt */
6121 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6122 ret = i40e_setup_misc_vector(pf);
6123
6124 /* restart the VSIs that were rebuilt and running before the reset */
6125 i40e_pf_unquiesce_all_vsi(pf);
6126
69f64b2b
MW		 6127 if (pf->num_alloc_vfs) {
6128 for (v = 0; v < pf->num_alloc_vfs; v++)
6129 i40e_reset_vf(&pf->vf[v], true);
6130 }
6131
41c445ff 6132 /* tell the firmware that we're starting */
44033fac 6133 i40e_send_version(pf);
41c445ff
JB		 6134
6135end_core_reset:
a316f651
ASJ		 6136 clear_bit(__I40E_RESET_FAILED, &pf->state);
6137clear_recovery:
41c445ff
JB		 6138 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6139}
6140
f650a38b
ASJ		 6141/**
6142 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
6143 * @pf: board private structure
6144 *
6145 * Close up the VFs and other things in prep for a Core Reset,
6146 * then get ready to rebuild the world.
6147 **/
6148static void i40e_handle_reset_warning(struct i40e_pf *pf)
6149{
23cfbe07
SN		 6150 i40e_prep_for_reset(pf);
6151 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6152}
6153
41c445ff
JB		 6154/**
6155 * i40e_handle_mdd_event
6156 * @pf: pointer to the pf structure
6157 *
6158 * Called from the MDD irq handler to identify possibly malicious vfs
6159 **/
6160static void i40e_handle_mdd_event(struct i40e_pf *pf)
6161{
6162 struct i40e_hw *hw = &pf->hw;
6163 bool mdd_detected = false;
df430b12 6164 bool pf_mdd_detected = false;
41c445ff
JB		 6165 struct i40e_vf *vf;
6166 u32 reg;
6167 int i;
6168
6169 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6170 return;
6171
6172 /* find what triggered the MDD event */
6173 reg = rd32(hw, I40E_GL_MDET_TX);
6174 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6175 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6176 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6177 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6178 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6179 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6180 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6181 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6182 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6183 pf->hw.func_caps.base_queue;
faf32978
JB		 6184 if (netif_msg_tx_err(pf))
6185 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
6186 event, queue, pf_num, vf_num);
41c445ff
JB		 6187 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6188 mdd_detected = true;
6189 }
6190 reg = rd32(hw, I40E_GL_MDET_RX);
6191 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6192 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6193 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6194 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6195 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6196 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6197 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6198 pf->hw.func_caps.base_queue;
faf32978
JB		 6199 if (netif_msg_rx_err(pf))
6200 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6201 event, queue, func);
41c445ff
JB		 6202 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6203 mdd_detected = true;
6204 }
6205
df430b12
NP		 6206 if (mdd_detected) {
6207 reg = rd32(hw, I40E_PF_MDET_TX);
6208 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6209 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6210 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6211 pf_mdd_detected = true;
6212 }
6213 reg = rd32(hw, I40E_PF_MDET_RX);
6214 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6215 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6216 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6217 pf_mdd_detected = true;
6218 }
6219 /* Queue belongs to the PF, initiate a reset */
6220 if (pf_mdd_detected) {
6221 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6222 i40e_service_event_schedule(pf);
6223 }
6224 }
6225
41c445ff
JB		 6226 /* see if one of the VFs needs its hand slapped */
6227 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6228 vf = &(pf->vf[i]);
6229 reg = rd32(hw, I40E_VP_MDET_TX(i));
6230 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6231 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6232 vf->num_mdd_events++;
faf32978
JB		 6233 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6234 i);
41c445ff
JB		 6235 }
6236
6237 reg = rd32(hw, I40E_VP_MDET_RX(i));
6238 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6239 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6240 vf->num_mdd_events++;
faf32978
JB		 6241 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6242 i);
41c445ff
JB		 6243 }
6244
6245 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6246 dev_info(&pf->pdev->dev,
6247 "Too many MDD events on VF %d, disabled\n", i);
6248 dev_info(&pf->pdev->dev,
6249 "Use PF Control I/F to re-enable the VF\n");
6250 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6251 }
6252 }
6253
6254 /* re-enable mdd interrupt cause */
6255 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6256 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6257 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6258 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6259 i40e_flush(hw);
6260}
6261
a1c9a9d9
JK		 6262#ifdef CONFIG_I40E_VXLAN
6263/**
6264 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6265 * @pf: board private structure
6266 **/
6267static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6268{
a1c9a9d9
JK		 6269 struct i40e_hw *hw = &pf->hw;
6270 i40e_status ret;
6271 u8 filter_index;
6272 __be16 port;
6273 int i;
6274
6275 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6276 return;
6277
6278 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6279
6280 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6281 if (pf->pending_vxlan_bitmap & (1 << i)) {
6282 pf->pending_vxlan_bitmap &= ~(1 << i);
6283 port = pf->vxlan_ports[i];
6284 ret = port ?
6285 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6286 I40E_AQC_TUNNEL_TYPE_VXLAN,
6287 &filter_index, NULL)
6288 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6289
6290 if (ret) {
6291 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6292 port ? "adding" : "deleting",
6293 ntohs(port), port ? i : i);
6294
6295 pf->vxlan_ports[i] = 0;
6296 } else {
6297 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6298 port ? "Added" : "Deleted",
6299 ntohs(port), port ? i : filter_index);
6300 }
6301 }
6302 }
6303}
6304
6305#endif
41c445ff
JB		 6306/**
6307 * i40e_service_task - Run the driver's async subtasks
6308 * @work: pointer to work_struct containing our data
6309 **/
6310static void i40e_service_task(struct work_struct *work)
6311{
6312 struct i40e_pf *pf = container_of(work,
6313 struct i40e_pf,
6314 service_task);
6315 unsigned long start_time = jiffies;
6316
e57a2fea
SN		 6317 /* don't bother with service tasks if a reset is in progress */
6318 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6319 i40e_service_event_complete(pf);
6320 return;
6321 }
6322
41c445ff
JB		 6323 i40e_reset_subtask(pf);
6324 i40e_handle_mdd_event(pf);
6325 i40e_vc_process_vflr_event(pf);
6326 i40e_watchdog_subtask(pf);
6327 i40e_fdir_reinit_subtask(pf);
6328 i40e_check_hang_subtask(pf);
6329 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6330#ifdef CONFIG_I40E_VXLAN
6331 i40e_sync_vxlan_filters_subtask(pf);
6332#endif
41c445ff
JB		 6333 i40e_clean_adminq_subtask(pf);
6334
1e701e09
JB		 6335 i40e_link_event(pf);
6336
41c445ff
JB		 6337 i40e_service_event_complete(pf);
6338
6339 /* If the tasks have taken longer than one timer cycle or there
6340 * is more work to be done, reschedule the service task now
6341 * rather than wait for the timer to tick again.
6342 */
6343 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6344 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6345 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6346 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6347 i40e_service_event_schedule(pf);
6348}
6349
6350/**
6351 * i40e_service_timer - timer callback
6352 * @data: pointer to PF struct
6353 **/
6354static void i40e_service_timer(unsigned long data)
6355{
6356 struct i40e_pf *pf = (struct i40e_pf *)data;
6357
6358 mod_timer(&pf->service_timer,
6359 round_jiffies(jiffies + pf->service_timer_period));
6360 i40e_service_event_schedule(pf);
6361}
6362
6363/**
6364 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6365 * @vsi: the VSI being configured
6366 **/
6367static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6368{
6369 struct i40e_pf *pf = vsi->back;
6370
6371 switch (vsi->type) {
6372 case I40E_VSI_MAIN:
6373 vsi->alloc_queue_pairs = pf->num_lan_qps;
6374 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6375 I40E_REQ_DESCRIPTOR_MULTIPLE);
6376 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6377 vsi->num_q_vectors = pf->num_lan_msix;
6378 else
6379 vsi->num_q_vectors = 1;
6380
6381 break;
6382
6383 case I40E_VSI_FDIR:
6384 vsi->alloc_queue_pairs = 1;
6385 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6386 I40E_REQ_DESCRIPTOR_MULTIPLE);
6387 vsi->num_q_vectors = 1;
6388 break;
6389
6390 case I40E_VSI_VMDQ2:
6391 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6392 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6393 I40E_REQ_DESCRIPTOR_MULTIPLE);
6394 vsi->num_q_vectors = pf->num_vmdq_msix;
6395 break;
6396
6397 case I40E_VSI_SRIOV:
6398 vsi->alloc_queue_pairs = pf->num_vf_qps;
6399 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6400 I40E_REQ_DESCRIPTOR_MULTIPLE);
6401 break;
6402
38e00438
VD		 6403#ifdef I40E_FCOE
6404 case I40E_VSI_FCOE:
6405 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6406 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6407 I40E_REQ_DESCRIPTOR_MULTIPLE);
6408 vsi->num_q_vectors = pf->num_fcoe_msix;
6409 break;
6410
6411#endif /* I40E_FCOE */
41c445ff
JB		 6412 default:
6413 WARN_ON(1);
6414 return -ENODATA;
6415 }
6416
6417 return 0;
6418}
6419
f650a38b
ASJ		 6420/**
6421 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6422 * @type: VSI pointer
bc7d338f 6423 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6424 *
6425 * On error: returns error code (negative)
6426 * On success: returns 0
6427 **/
bc7d338f 6428static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6429{
6430 int size;
6431 int ret = 0;
6432
ac6c5e3d 6433 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6434 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6435 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6436 if (!vsi->tx_rings)
6437 return -ENOMEM;
f650a38b
ASJ		 6438 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6439
bc7d338f
ASJ		 6440 if (alloc_qvectors) {
6441 /* allocate memory for q_vector pointers */
f57e4fbd 6442 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6443 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6444 if (!vsi->q_vectors) {
6445 ret = -ENOMEM;
6446 goto err_vectors;
6447 }
f650a38b
ASJ		 6448 }
6449 return ret;
6450
6451err_vectors:
6452 kfree(vsi->tx_rings);
6453 return ret;
6454}
6455
41c445ff
JB		 6456/**
6457 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6458 * @pf: board private structure
6459 * @type: type of VSI
6460 *
6461 * On error: returns error code (negative)
6462 * On success: returns vsi index in PF (positive)
6463 **/
6464static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6465{
6466 int ret = -ENODEV;
6467 struct i40e_vsi *vsi;
6468 int vsi_idx;
6469 int i;
6470
6471 /* Need to protect the allocation of the VSIs at the PF level */
6472 mutex_lock(&pf->switch_mutex);
6473
6474 /* VSI list may be fragmented if VSI creation/destruction has
6475 * been happening. We can afford to do a quick scan to look
6476 * for any free VSIs in the list.
6477 *
6478 * find next empty vsi slot, looping back around if necessary
6479 */
6480 i = pf->next_vsi;
505682cd 6481 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6482 i++;
505682cd 6483 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6484 i = 0;
6485 while (i < pf->next_vsi && pf->vsi[i])
6486 i++;
6487 }
6488
505682cd 6489 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6490 vsi_idx = i; /* Found one! */
6491 } else {
6492 ret = -ENODEV;
493fb300 6493 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6494 }
6495 pf->next_vsi = ++i;
6496
6497 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6498 if (!vsi) {
6499 ret = -ENOMEM;
493fb300 6500 goto unlock_pf;
41c445ff
JB		 6501 }
6502 vsi->type = type;
6503 vsi->back = pf;
6504 set_bit(__I40E_DOWN, &vsi->state);
6505 vsi->flags = 0;
6506 vsi->idx = vsi_idx;
6507 vsi->rx_itr_setting = pf->rx_itr_default;
6508 vsi->tx_itr_setting = pf->tx_itr_default;
6509 vsi->netdev_registered = false;
6510 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6511 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6512 vsi->irqs_ready = false;
41c445ff 6513
9f65e15b
AD		 6514 ret = i40e_set_num_rings_in_vsi(vsi);
6515 if (ret)
6516 goto err_rings;
6517
bc7d338f 6518 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6519 if (ret)
9f65e15b 6520 goto err_rings;
493fb300 6521
41c445ff
JB		 6522 /* Setup default MSIX irq handler for VSI */
6523 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6524
6525 pf->vsi[vsi_idx] = vsi;
6526 ret = vsi_idx;
493fb300
AD		 6527 goto unlock_pf;
6528
9f65e15b 6529err_rings:
493fb300
AD		 6530 pf->next_vsi = i - 1;
6531 kfree(vsi);
6532unlock_pf:
41c445ff
JB		 6533 mutex_unlock(&pf->switch_mutex);
6534 return ret;
6535}
6536
f650a38b
ASJ		 6537/**
6538 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6539 * @type: VSI pointer
bc7d338f 6540 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6541 *
6542 * On error: returns error code (negative)
6543 * On success: returns 0
6544 **/
bc7d338f 6545static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6546{
6547 /* free the ring and vector containers */
bc7d338f
ASJ		 6548 if (free_qvectors) {
6549 kfree(vsi->q_vectors);
6550 vsi->q_vectors = NULL;
6551 }
f650a38b
ASJ		 6552 kfree(vsi->tx_rings);
6553 vsi->tx_rings = NULL;
6554 vsi->rx_rings = NULL;
6555}
6556
41c445ff
JB		 6557/**
6558 * i40e_vsi_clear - Deallocate the VSI provided
6559 * @vsi: the VSI being un-configured
6560 **/
6561static int i40e_vsi_clear(struct i40e_vsi *vsi)
6562{
6563 struct i40e_pf *pf;
6564
6565 if (!vsi)
6566 return 0;
6567
6568 if (!vsi->back)
6569 goto free_vsi;
6570 pf = vsi->back;
6571
6572 mutex_lock(&pf->switch_mutex);
6573 if (!pf->vsi[vsi->idx]) {
6574 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6575 vsi->idx, vsi->idx, vsi, vsi->type);
6576 goto unlock_vsi;
6577 }
6578
6579 if (pf->vsi[vsi->idx] != vsi) {
6580 dev_err(&pf->pdev->dev,
6581 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6582 pf->vsi[vsi->idx]->idx,
6583 pf->vsi[vsi->idx],
6584 pf->vsi[vsi->idx]->type,
6585 vsi->idx, vsi, vsi->type);
6586 goto unlock_vsi;
6587 }
6588
6589 /* updates the pf for this cleared vsi */
6590 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6591 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6592
bc7d338f 6593 i40e_vsi_free_arrays(vsi, true);
493fb300 6594
41c445ff
JB		 6595 pf->vsi[vsi->idx] = NULL;
6596 if (vsi->idx < pf->next_vsi)
6597 pf->next_vsi = vsi->idx;
6598
6599unlock_vsi:
6600 mutex_unlock(&pf->switch_mutex);
6601free_vsi:
6602 kfree(vsi);
6603
6604 return 0;
6605}
6606
9f65e15b
AD		 6607/**
6608 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6609 * @vsi: the VSI being cleaned
6610 **/
be1d5eea 6611static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6612{
6613 int i;
6614
8e9dca53 6615 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6616 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6617 kfree_rcu(vsi->tx_rings[i], rcu);
6618 vsi->tx_rings[i] = NULL;
6619 vsi->rx_rings[i] = NULL;
6620 }
be1d5eea 6621 }
9f65e15b
AD		 6622}
6623
41c445ff
JB		 6624/**
6625 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6626 * @vsi: the VSI being configured
6627 **/
6628static int i40e_alloc_rings(struct i40e_vsi *vsi)
6629{
e7046ee1 6630 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6631 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6632 int i;
6633
41c445ff 6634 /* Set basic values in the rings to be used later during open() */
d7397644 6635 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6636 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6637 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6638 if (!tx_ring)
6639 goto err_out;
41c445ff
JB		 6640
6641 tx_ring->queue_index = i;
6642 tx_ring->reg_idx = vsi->base_queue + i;
6643 tx_ring->ring_active = false;
6644 tx_ring->vsi = vsi;
6645 tx_ring->netdev = vsi->netdev;
6646 tx_ring->dev = &pf->pdev->dev;
6647 tx_ring->count = vsi->num_desc;
6648 tx_ring->size = 0;
6649 tx_ring->dcb_tc = 0;
9f65e15b 6650 vsi->tx_rings[i] = tx_ring;
41c445ff 6651
9f65e15b 6652 rx_ring = &tx_ring[1];
41c445ff
JB		 6653 rx_ring->queue_index = i;
6654 rx_ring->reg_idx = vsi->base_queue + i;
6655 rx_ring->ring_active = false;
6656 rx_ring->vsi = vsi;
6657 rx_ring->netdev = vsi->netdev;
6658 rx_ring->dev = &pf->pdev->dev;
6659 rx_ring->count = vsi->num_desc;
6660 rx_ring->size = 0;
6661 rx_ring->dcb_tc = 0;
6662 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6663 set_ring_16byte_desc_enabled(rx_ring);
6664 else
6665 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6666 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6667 }
6668
6669 return 0;
9f65e15b
AD		 6670
6671err_out:
6672 i40e_vsi_clear_rings(vsi);
6673 return -ENOMEM;
41c445ff
JB		 6674}
6675
6676/**
6677 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6678 * @pf: board private structure
6679 * @vectors: the number of MSI-X vectors to request
6680 *
6681 * Returns the number of vectors reserved, or error
6682 **/
6683static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6684{
7b37f376
AG		 6685 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6686 I40E_MIN_MSIX, vectors);
6687 if (vectors < 0) {
41c445ff 6688 dev_info(&pf->pdev->dev,
7b37f376 6689 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6690 vectors = 0;
6691 }
6692
6693 return vectors;
6694}
6695
6696/**
6697 * i40e_init_msix - Setup the MSIX capability
6698 * @pf: board private structure
6699 *
6700 * Work with the OS to set up the MSIX vectors needed.
6701 *
6702 * Returns 0 on success, negative on failure
6703 **/
6704static int i40e_init_msix(struct i40e_pf *pf)
6705{
6706 i40e_status err = 0;
6707 struct i40e_hw *hw = &pf->hw;
c135b0de 6708 int other_vecs = 0;
41c445ff
JB		 6709 int v_budget, i;
6710 int vec;
6711
6712 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6713 return -ENODEV;
6714
6715 /* The number of vectors we'll request will be comprised of:
6716 * - Add 1 for "other" cause for Admin Queue events, etc.
6717 * - The number of LAN queue pairs
f8ff1464
ASJ		 6718 * - Queues being used for RSS.
6719 * We don't need as many as max_rss_size vectors.
6720 * use rss_size instead in the calculation since that
6721 * is governed by number of cpus in the system.
6722 * - assumes symmetric Tx/Rx pairing
41c445ff 6723 * - The number of VMDq pairs
38e00438
VD		 6724#ifdef I40E_FCOE
6725 * - The number of FCOE qps.
6726#endif
41c445ff
JB		 6727 * Once we count this up, try the request.
6728 *
6729 * If we can't get what we want, we'll simplify to nearly nothing
6730 * and try again. If that still fails, we punt.
6731 */
f8ff1464 6732 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff 6733 pf->num_vmdq_msix = pf->num_vmdq_qps;
c135b0de
SN		 6734 other_vecs = 1;
6735 other_vecs += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6736 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
c135b0de 6737 other_vecs++;
41c445ff 6738
38e00438
VD		 6739#ifdef I40E_FCOE
6740 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6741 pf->num_fcoe_msix = pf->num_fcoe_qps;
6742 v_budget += pf->num_fcoe_msix;
6743 }
6744
6745#endif
41c445ff 6746 /* Scale down if necessary, and the rings will share vectors */
c135b0de
SN		 6747 pf->num_lan_msix = min_t(int, pf->num_lan_msix,
6748 (hw->func_caps.num_msix_vectors - other_vecs));
6749 v_budget = pf->num_lan_msix + other_vecs;
41c445ff
JB		 6750
6751 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6752 GFP_KERNEL);
6753 if (!pf->msix_entries)
6754 return -ENOMEM;
6755
6756 for (i = 0; i < v_budget; i++)
6757 pf->msix_entries[i].entry = i;
6758 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6759
6760 if (vec != v_budget) {
6761 /* If we have limited resources, we will start with no vectors
6762 * for the special features and then allocate vectors to some
6763 * of these features based on the policy and at the end disable
6764 * the features that did not get any vectors.
6765 */
38e00438
VD		 6766#ifdef I40E_FCOE
6767 pf->num_fcoe_qps = 0;
6768 pf->num_fcoe_msix = 0;
6769#endif
a34977ba
ASJ		 6770 pf->num_vmdq_msix = 0;
6771 }
6772
41c445ff
JB		 6773 if (vec < I40E_MIN_MSIX) {
6774 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6775 kfree(pf->msix_entries);
6776 pf->msix_entries = NULL;
6777 return -ENODEV;
6778
6779 } else if (vec == I40E_MIN_MSIX) {
6780 /* Adjust for minimal MSIX use */
41c445ff
JB		 6781 pf->num_vmdq_vsis = 0;
6782 pf->num_vmdq_qps = 0;
41c445ff
JB		 6783 pf->num_lan_qps = 1;
6784 pf->num_lan_msix = 1;
6785
6786 } else if (vec != v_budget) {
a34977ba
ASJ		 6787 /* reserve the misc vector */
6788 vec--;
6789
41c445ff
JB		 6790 /* Scale vector usage down */
6791 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6792 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6793
6794 /* partition out the remaining vectors */
6795 switch (vec) {
6796 case 2:
41c445ff
JB		 6797 pf->num_lan_msix = 1;
6798 break;
6799 case 3:
38e00438
VD		 6800#ifdef I40E_FCOE
6801 /* give one vector to FCoE */
6802 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6803 pf->num_lan_msix = 1;
6804 pf->num_fcoe_msix = 1;
6805 }
6806#else
41c445ff 6807 pf->num_lan_msix = 2;
38e00438 6808#endif
41c445ff
JB		 6809 break;
6810 default:
38e00438
VD		 6811#ifdef I40E_FCOE
6812 /* give one vector to FCoE */
6813 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6814 pf->num_fcoe_msix = 1;
6815 vec--;
6816 }
6817#endif
41c445ff
JB		 6818 pf->num_lan_msix = min_t(int, (vec / 2),
6819 pf->num_lan_qps);
6820 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6821 I40E_DEFAULT_NUM_VMDQ_VSI);
6822 break;
6823 }
6824 }
6825
a34977ba
ASJ		 6826 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
6827 (pf->num_vmdq_msix == 0)) {
6828 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
6829 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6830 }
38e00438
VD		 6831#ifdef I40E_FCOE
6832
6833 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
6834 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
6835 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
6836 }
6837#endif
41c445ff
JB		 6838 return err;
6839}
6840
493fb300 6841/**
90e04070 6842 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6843 * @vsi: the VSI being configured
6844 * @v_idx: index of the vector in the vsi struct
6845 *
6846 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6847 **/
90e04070 6848static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6849{
6850 struct i40e_q_vector *q_vector;
6851
6852 /* allocate q_vector */
6853 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6854 if (!q_vector)
6855 return -ENOMEM;
6856
6857 q_vector->vsi = vsi;
6858 q_vector->v_idx = v_idx;
6859 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6860 if (vsi->netdev)
6861 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6862 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6863
cd0b6fa6
AD		 6864 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6865 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6866
493fb300
AD		 6867 /* tie q_vector and vsi together */
6868 vsi->q_vectors[v_idx] = q_vector;
6869
6870 return 0;
6871}
6872
41c445ff 6873/**
90e04070 6874 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6875 * @vsi: the VSI being configured
6876 *
6877 * We allocate one q_vector per queue interrupt. If allocation fails we
6878 * return -ENOMEM.
6879 **/
90e04070 6880static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6881{
6882 struct i40e_pf *pf = vsi->back;
6883 int v_idx, num_q_vectors;
493fb300 6884 int err;
41c445ff
JB		 6885
6886 /* if not MSIX, give the one vector only to the LAN VSI */
6887 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6888 num_q_vectors = vsi->num_q_vectors;
6889 else if (vsi == pf->vsi[pf->lan_vsi])
6890 num_q_vectors = 1;
6891 else
6892 return -EINVAL;
6893
41c445ff 6894 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6895 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6896 if (err)
6897 goto err_out;
41c445ff
JB		 6898 }
6899
6900 return 0;
493fb300
AD		 6901
6902err_out:
6903 while (v_idx--)
6904 i40e_free_q_vector(vsi, v_idx);
6905
6906 return err;
41c445ff
JB		 6907}
6908
6909/**
6910 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6911 * @pf: board private structure to initialize
6912 **/
6913static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6914{
6915 int err = 0;
6916
6917 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6918 err = i40e_init_msix(pf);
6919 if (err) {
60ea5f83 6920 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 6921#ifdef I40E_FCOE
6922 I40E_FLAG_FCOE_ENABLED |
6923#endif
60ea5f83 6924 I40E_FLAG_RSS_ENABLED |
4d9b6043 6925 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 6926 I40E_FLAG_SRIOV_ENABLED |
6927 I40E_FLAG_FD_SB_ENABLED |
6928 I40E_FLAG_FD_ATR_ENABLED |
6929 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6930
6931 /* rework the queue expectations without MSIX */
6932 i40e_determine_queue_usage(pf);
6933 }
6934 }
6935
6936 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6937 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6938 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6939 err = pci_enable_msi(pf->pdev);
6940 if (err) {
958a3e3b 6941 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6942 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6943 }
6944 }
6945
958a3e3b 6946 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6947 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6948
41c445ff
JB		 6949 /* track first vector for misc interrupts */
6950 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6951}
6952
6953/**
6954 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6955 * @pf: board private structure
6956 *
6957 * This sets up the handler for MSIX 0, which is used to manage the
6958 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6959 * when in MSI or Legacy interrupt mode.
6960 **/
6961static int i40e_setup_misc_vector(struct i40e_pf *pf)
6962{
6963 struct i40e_hw *hw = &pf->hw;
6964 int err = 0;
6965
6966 /* Only request the irq if this is the first time through, and
6967 * not when we're rebuilding after a Reset
6968 */
6969 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6970 err = request_irq(pf->msix_entries[0].vector,
6971 i40e_intr, 0, pf->misc_int_name, pf);
6972 if (err) {
6973 dev_info(&pf->pdev->dev,
77fa28be
CS		 6974 "request_irq for %s failed: %d\n",
6975 pf->misc_int_name, err);
41c445ff
JB		 6976 return -EFAULT;
6977 }
6978 }
6979
6980 i40e_enable_misc_int_causes(hw);
6981
6982 /* associate no queues to the misc vector */
6983 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6984 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6985
6986 i40e_flush(hw);
6987
6988 i40e_irq_dynamic_enable_icr0(pf);
6989
6990 return err;
6991}
6992
6993/**
6994 * i40e_config_rss - Prepare for RSS if used
6995 * @pf: board private structure
6996 **/
6997static int i40e_config_rss(struct i40e_pf *pf)
6998{
41c445ff
JB		 6999 /* Set of random keys generated using kernel random number generator */
7000 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
7001 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
7002 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
7003 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 7004 struct i40e_hw *hw = &pf->hw;
7005 u32 lut = 0;
7006 int i, j;
7007 u64 hena;
e157ea30 7008 u32 reg_val;
41c445ff
JB		 7009
7010 /* Fill out hash function seed */
7011 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7012 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
7013
7014 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7015 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7016 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7017 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7018 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7019 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7020
e157ea30
CW		 7021 /* Check capability and Set table size and register per hw expectation*/
7022 reg_val = rd32(hw, I40E_PFQF_CTL_0);
7023 if (hw->func_caps.rss_table_size == 512) {
7024 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7025 pf->rss_table_size = 512;
7026 } else {
7027 pf->rss_table_size = 128;
7028 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7029 }
7030 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7031
41c445ff 7032 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7033 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7034
7035 /* The assumption is that lan qp count will be the highest
7036 * qp count for any PF VSI that needs RSS.
7037 * If multiple VSIs need RSS support, all the qp counts
7038 * for those VSIs should be a power of 2 for RSS to work.
7039 * If LAN VSI is the only consumer for RSS then this requirement
7040 * is not necessary.
7041 */
7042 if (j == pf->rss_size)
7043 j = 0;
7044 /* lut = 4-byte sliding window of 4 lut entries */
7045 lut = (lut << 8) | (j &
7046 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7047 /* On i = 3, we have 4 entries in lut; write to the register */
7048 if ((i & 3) == 3)
7049 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7050 }
7051 i40e_flush(hw);
7052
7053 return 0;
7054}
7055
f8ff1464
ASJ		 7056/**
7057 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7058 * @pf: board private structure
7059 * @queue_count: the requested queue count for rss.
7060 *
7061 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7062 * count which may be different from the requested queue count.
7063 **/
7064int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7065{
7066 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7067 return 0;
7068
7069 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 7070
7071 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 7072 i40e_prep_for_reset(pf);
7073
f8ff1464
ASJ		 7074 pf->rss_size = queue_count;
7075
7076 i40e_reset_and_rebuild(pf, true);
7077 i40e_config_rss(pf);
7078 }
7079 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7080 return pf->rss_size;
7081}
7082
41c445ff
JB		 7083/**
7084 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7085 * @pf: board private structure to initialize
7086 *
7087 * i40e_sw_init initializes the Adapter private data structure.
7088 * Fields are initialized based on PCI device information and
7089 * OS network device settings (MTU size).
7090 **/
7091static int i40e_sw_init(struct i40e_pf *pf)
7092{
7093 int err = 0;
7094 int size;
7095
7096 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7097 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7098 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7099 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7100 if (I40E_DEBUG_USER & debug)
7101 pf->hw.debug_mask = debug;
7102 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7103 I40E_DEFAULT_MSG_ENABLE);
7104 }
7105
7106 /* Set default capability flags */
7107 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7108 I40E_FLAG_MSI_ENABLED |
7109 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 7110 I40E_FLAG_RX_1BUF_ENABLED;
7111
ca99eb99
MW		 7112 /* Set default ITR */
7113 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7114 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7115
7134f9ce
JB		 7116 /* Depending on PF configurations, it is possible that the RSS
7117 * maximum might end up larger than the available queues
7118 */
41c445ff 7119 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7120 pf->rss_size = 1;
7134f9ce
JB		 7121 pf->rss_size_max = min_t(int, pf->rss_size_max,
7122 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7123 if (pf->hw.func_caps.rss) {
7124 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7125 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7126 }
7127
2050bc65
CS		 7128 /* MFP mode enabled */
7129 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7130 pf->flags |= I40E_FLAG_MFP_ENABLED;
7131 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
7132 }
7133
cbf61325
ASJ		 7134 /* FW/NVM is not yet fixed in this regard */
7135 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7136 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7137 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7138 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 7139 /* Setup a counter for fd_atr per pf */
7140 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7141 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7142 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 7143 /* Setup a counter for fd_sb per pf */
7144 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7145 } else {
7146 dev_info(&pf->pdev->dev,
0b67584f 7147 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7148 }
cbf61325
ASJ		 7149 pf->fdir_pf_filter_count =
7150 pf->hw.func_caps.fd_filters_guaranteed;
7151 pf->hw.fdir_shared_filter_count =
7152 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7153 }
7154
7155 if (pf->hw.func_caps.vmdq) {
7156 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7157 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7158 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7159 }
7160
38e00438
VD		 7161#ifdef I40E_FCOE
7162 err = i40e_init_pf_fcoe(pf);
7163 if (err)
7164 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7165
7166#endif /* I40E_FCOE */
41c445ff
JB		 7167#ifdef CONFIG_PCI_IOV
7168 if (pf->hw.func_caps.num_vfs) {
7169 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7170 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7171 pf->num_req_vfs = min_t(int,
7172 pf->hw.func_caps.num_vfs,
7173 I40E_MAX_VF_COUNT);
7174 }
7175#endif /* CONFIG_PCI_IOV */
7176 pf->eeprom_version = 0xDEAD;
7177 pf->lan_veb = I40E_NO_VEB;
7178 pf->lan_vsi = I40E_NO_VSI;
7179
7180 /* set up queue assignment tracking */
7181 size = sizeof(struct i40e_lump_tracking)
7182 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7183 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7184 if (!pf->qp_pile) {
7185 err = -ENOMEM;
7186 goto sw_init_done;
7187 }
7188 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7189 pf->qp_pile->search_hint = 0;
7190
7191 /* set up vector assignment tracking */
7192 size = sizeof(struct i40e_lump_tracking)
7193 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
7194 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7195 if (!pf->irq_pile) {
7196 kfree(pf->qp_pile);
7197 err = -ENOMEM;
7198 goto sw_init_done;
7199 }
7200 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
7201 pf->irq_pile->search_hint = 0;
7202
327fe04b
ASJ		 7203 pf->tx_timeout_recovery_level = 1;
7204
41c445ff
JB		 7205 mutex_init(&pf->switch_mutex);
7206
7207sw_init_done:
7208 return err;
7209}
7210
7c3c288b
ASJ		 7211/**
7212 * i40e_set_ntuple - set the ntuple feature flag and take action
7213 * @pf: board private structure to initialize
7214 * @features: the feature set that the stack is suggesting
7215 *
7216 * returns a bool to indicate if reset needs to happen
7217 **/
7218bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7219{
7220 bool need_reset = false;
7221
7222 /* Check if Flow Director n-tuple support was enabled or disabled. If
7223 * the state changed, we need to reset.
7224 */
7225 if (features & NETIF_F_NTUPLE) {
7226 /* Enable filters and mark for reset */
7227 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7228 need_reset = true;
7229 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7230 } else {
7231 /* turn off filters, mark for reset and clear SW filter list */
7232 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7233 need_reset = true;
7234 i40e_fdir_filter_exit(pf);
7235 }
7236 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7237 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7238 /* reset fd counters */
7239 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7240 pf->fdir_pf_active_filters = 0;
7241 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7242 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7243 /* if ATR was auto disabled it can be re-enabled. */
7244 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7245 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7246 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7247 }
7248 return need_reset;
7249}
7250
41c445ff
JB		 7251/**
7252 * i40e_set_features - set the netdev feature flags
7253 * @netdev: ptr to the netdev being adjusted
7254 * @features: the feature set that the stack is suggesting
7255 **/
7256static int i40e_set_features(struct net_device *netdev,
7257 netdev_features_t features)
7258{
7259 struct i40e_netdev_priv *np = netdev_priv(netdev);
7260 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7261 struct i40e_pf *pf = vsi->back;
7262 bool need_reset;
41c445ff
JB		 7263
7264 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7265 i40e_vlan_stripping_enable(vsi);
7266 else
7267 i40e_vlan_stripping_disable(vsi);
7268
7c3c288b
ASJ		 7269 need_reset = i40e_set_ntuple(pf, features);
7270
7271 if (need_reset)
7272 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7273
41c445ff
JB		 7274 return 0;
7275}
7276
a1c9a9d9
JK		 7277#ifdef CONFIG_I40E_VXLAN
7278/**
7279 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7280 * @pf: board private structure
7281 * @port: The UDP port to look up
7282 *
7283 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7284 **/
7285static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7286{
7287 u8 i;
7288
7289 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7290 if (pf->vxlan_ports[i] == port)
7291 return i;
7292 }
7293
7294 return i;
7295}
7296
7297/**
7298 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7299 * @netdev: This physical port's netdev
7300 * @sa_family: Socket Family that VXLAN is notifying us about
7301 * @port: New UDP port number that VXLAN started listening to
7302 **/
7303static void i40e_add_vxlan_port(struct net_device *netdev,
7304 sa_family_t sa_family, __be16 port)
7305{
7306 struct i40e_netdev_priv *np = netdev_priv(netdev);
7307 struct i40e_vsi *vsi = np->vsi;
7308 struct i40e_pf *pf = vsi->back;
7309 u8 next_idx;
7310 u8 idx;
7311
7312 if (sa_family == AF_INET6)
7313 return;
7314
7315 idx = i40e_get_vxlan_port_idx(pf, port);
7316
7317 /* Check if port already exists */
7318 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7319 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7320 return;
7321 }
7322
7323 /* Now check if there is space to add the new port */
7324 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7325
7326 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7327 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7328 ntohs(port));
7329 return;
7330 }
7331
7332 /* New port: add it and mark its index in the bitmap */
7333 pf->vxlan_ports[next_idx] = port;
7334 pf->pending_vxlan_bitmap |= (1 << next_idx);
7335
7336 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7337}
7338
7339/**
7340 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7341 * @netdev: This physical port's netdev
7342 * @sa_family: Socket Family that VXLAN is notifying us about
7343 * @port: UDP port number that VXLAN stopped listening to
7344 **/
7345static void i40e_del_vxlan_port(struct net_device *netdev,
7346 sa_family_t sa_family, __be16 port)
7347{
7348 struct i40e_netdev_priv *np = netdev_priv(netdev);
7349 struct i40e_vsi *vsi = np->vsi;
7350 struct i40e_pf *pf = vsi->back;
7351 u8 idx;
7352
7353 if (sa_family == AF_INET6)
7354 return;
7355
7356 idx = i40e_get_vxlan_port_idx(pf, port);
7357
7358 /* Check if port already exists */
7359 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7360 /* if port exists, set it to 0 (mark for deletion)
7361 * and make it pending
7362 */
7363 pf->vxlan_ports[idx] = 0;
7364
7365 pf->pending_vxlan_bitmap |= (1 << idx);
7366
7367 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7368 } else {
7369 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7370 ntohs(port));
7371 }
7372}
7373
7374#endif
1f224ad2
NP		 7375static int i40e_get_phys_port_id(struct net_device *netdev,
7376 struct netdev_phys_port_id *ppid)
7377{
7378 struct i40e_netdev_priv *np = netdev_priv(netdev);
7379 struct i40e_pf *pf = np->vsi->back;
7380 struct i40e_hw *hw = &pf->hw;
7381
7382 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7383 return -EOPNOTSUPP;
7384
7385 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7386 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7387
7388 return 0;
7389}
7390
4ba0dea5
GR		 7391#ifdef HAVE_FDB_OPS
7392#ifdef USE_CONST_DEV_UC_CHAR
7393static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7394 struct net_device *dev,
7395 const unsigned char *addr,
7396 u16 flags)
7397#else
7398static int i40e_ndo_fdb_add(struct ndmsg *ndm,
7399 struct net_device *dev,
7400 unsigned char *addr,
7401 u16 flags)
7402#endif
7403{
7404 struct i40e_netdev_priv *np = netdev_priv(dev);
7405 struct i40e_pf *pf = np->vsi->back;
7406 int err = 0;
7407
7408 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7409 return -EOPNOTSUPP;
7410
7411 /* Hardware does not support aging addresses so if a
7412 * ndm_state is given only allow permanent addresses
7413 */
7414 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7415 netdev_info(dev, "FDB only supports static addresses\n");
7416 return -EINVAL;
7417 }
7418
7419 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7420 err = dev_uc_add_excl(dev, addr);
7421 else if (is_multicast_ether_addr(addr))
7422 err = dev_mc_add_excl(dev, addr);
7423 else
7424 err = -EINVAL;
7425
7426 /* Only return duplicate errors if NLM_F_EXCL is set */
7427 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7428 err = 0;
7429
7430 return err;
7431}
7432
7433#ifndef USE_DEFAULT_FDB_DEL_DUMP
7434#ifdef USE_CONST_DEV_UC_CHAR
7435static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7436 struct net_device *dev,
7437 const unsigned char *addr)
7438#else
7439static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7440 struct net_device *dev,
7441 unsigned char *addr)
7442#endif
7443{
7444 struct i40e_netdev_priv *np = netdev_priv(dev);
7445 struct i40e_pf *pf = np->vsi->back;
7446 int err = -EOPNOTSUPP;
7447
7448 if (ndm->ndm_state & NUD_PERMANENT) {
7449 netdev_info(dev, "FDB only supports static addresses\n");
7450 return -EINVAL;
7451 }
7452
7453 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7454 if (is_unicast_ether_addr(addr))
7455 err = dev_uc_del(dev, addr);
7456 else if (is_multicast_ether_addr(addr))
7457 err = dev_mc_del(dev, addr);
7458 else
7459 err = -EINVAL;
7460 }
7461
7462 return err;
7463}
7464
7465static int i40e_ndo_fdb_dump(struct sk_buff *skb,
7466 struct netlink_callback *cb,
7467 struct net_device *dev,
5d5eacb3 7468 struct net_device *filter_dev,
4ba0dea5
GR		 7469 int idx)
7470{
7471 struct i40e_netdev_priv *np = netdev_priv(dev);
7472 struct i40e_pf *pf = np->vsi->back;
7473
7474 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
5d5eacb3 7475 idx = ndo_dflt_fdb_dump(skb, cb, dev, filter_dev, idx);
4ba0dea5
GR		 7476
7477 return idx;
7478}
7479
7480#endif /* USE_DEFAULT_FDB_DEL_DUMP */
7481#endif /* HAVE_FDB_OPS */
41c445ff
JB		 7482static const struct net_device_ops i40e_netdev_ops = {
7483 .ndo_open = i40e_open,
7484 .ndo_stop = i40e_close,
7485 .ndo_start_xmit = i40e_lan_xmit_frame,
7486 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7487 .ndo_set_rx_mode = i40e_set_rx_mode,
7488 .ndo_validate_addr = eth_validate_addr,
7489 .ndo_set_mac_address = i40e_set_mac,
7490 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7491 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7492 .ndo_tx_timeout = i40e_tx_timeout,
7493 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7494 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7495#ifdef CONFIG_NET_POLL_CONTROLLER
7496 .ndo_poll_controller = i40e_netpoll,
7497#endif
7498 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 7499#ifdef I40E_FCOE
7500 .ndo_fcoe_enable = i40e_fcoe_enable,
7501 .ndo_fcoe_disable = i40e_fcoe_disable,
7502#endif
41c445ff
JB		 7503 .ndo_set_features = i40e_set_features,
7504 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7505 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7506 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7507 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7508 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 7509 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 7510#ifdef CONFIG_I40E_VXLAN
7511 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7512 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7513#endif
1f224ad2 7514 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5
GR		 7515#ifdef HAVE_FDB_OPS
7516 .ndo_fdb_add = i40e_ndo_fdb_add,
7517#ifndef USE_DEFAULT_FDB_DEL_DUMP
7518 .ndo_fdb_del = i40e_ndo_fdb_del,
7519 .ndo_fdb_dump = i40e_ndo_fdb_dump,
7520#endif
7521#endif
41c445ff
JB		 7522};
7523
7524/**
7525 * i40e_config_netdev - Setup the netdev flags
7526 * @vsi: the VSI being configured
7527 *
7528 * Returns 0 on success, negative value on failure
7529 **/
7530static int i40e_config_netdev(struct i40e_vsi *vsi)
7531{
1a10370a 7532 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7533 struct i40e_pf *pf = vsi->back;
7534 struct i40e_hw *hw = &pf->hw;
7535 struct i40e_netdev_priv *np;
7536 struct net_device *netdev;
7537 u8 mac_addr[ETH_ALEN];
7538 int etherdev_size;
7539
7540 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7541 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7542 if (!netdev)
7543 return -ENOMEM;
7544
7545 vsi->netdev = netdev;
7546 np = netdev_priv(netdev);
7547 np->vsi = vsi;
7548
d70e941b 7549 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7550 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7551 NETIF_F_TSO;
41c445ff
JB		 7552
7553 netdev->features = NETIF_F_SG |
7554 NETIF_F_IP_CSUM |
7555 NETIF_F_SCTP_CSUM |
7556 NETIF_F_HIGHDMA |
7557 NETIF_F_GSO_UDP_TUNNEL |
7558 NETIF_F_HW_VLAN_CTAG_TX |
7559 NETIF_F_HW_VLAN_CTAG_RX |
7560 NETIF_F_HW_VLAN_CTAG_FILTER |
7561 NETIF_F_IPV6_CSUM |
7562 NETIF_F_TSO |
059dab69 7563 NETIF_F_TSO_ECN |
41c445ff
JB		 7564 NETIF_F_TSO6 |
7565 NETIF_F_RXCSUM |
7566 NETIF_F_RXHASH |
7567 0;
7568
2e86a0b6
ASJ		 7569 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7570 netdev->features |= NETIF_F_NTUPLE;
7571
41c445ff
JB		 7572 /* copy netdev features into list of user selectable features */
7573 netdev->hw_features |= netdev->features;
7574
7575 if (vsi->type == I40E_VSI_MAIN) {
7576 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7577 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 7578 /* The following steps are necessary to prevent reception
7579 * of tagged packets - some older NVM configurations load a
7580 * default a MAC-VLAN filter that accepts any tagged packet
7581 * which must be replaced by a normal filter.
8c27d42e 7582 */
30650cc5
SN		 7583 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
7584 i40e_add_filter(vsi, mac_addr,
7585 I40E_VLAN_ANY, false, true);
41c445ff
JB		 7586 } else {
7587 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7588 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7589 pf->vsi[pf->lan_vsi]->netdev->name);
7590 random_ether_addr(mac_addr);
7591 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7592 }
1a10370a 7593 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7594
9a173901
GR		 7595 ether_addr_copy(netdev->dev_addr, mac_addr);
7596 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7597 /* vlan gets same features (except vlan offload)
7598 * after any tweaks for specific VSI types
7599 */
7600 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7601 NETIF_F_HW_VLAN_CTAG_RX |
7602 NETIF_F_HW_VLAN_CTAG_FILTER);
7603 netdev->priv_flags |= IFF_UNICAST_FLT;
7604 netdev->priv_flags |= IFF_SUPP_NOFCS;
7605 /* Setup netdev TC information */
7606 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7607
7608 netdev->netdev_ops = &i40e_netdev_ops;
7609 netdev->watchdog_timeo = 5 * HZ;
7610 i40e_set_ethtool_ops(netdev);
38e00438
VD		 7611#ifdef I40E_FCOE
7612 i40e_fcoe_config_netdev(netdev, vsi);
7613#endif
41c445ff
JB		 7614
7615 return 0;
7616}
7617
7618/**
7619 * i40e_vsi_delete - Delete a VSI from the switch
7620 * @vsi: the VSI being removed
7621 *
7622 * Returns 0 on success, negative value on failure
7623 **/
7624static void i40e_vsi_delete(struct i40e_vsi *vsi)
7625{
7626 /* remove default VSI is not allowed */
7627 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
7628 return;
7629
41c445ff 7630 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 7631}
7632
7633/**
7634 * i40e_add_vsi - Add a VSI to the switch
7635 * @vsi: the VSI being configured
7636 *
7637 * This initializes a VSI context depending on the VSI type to be added and
7638 * passes it down to the add_vsi aq command.
7639 **/
7640static int i40e_add_vsi(struct i40e_vsi *vsi)
7641{
7642 int ret = -ENODEV;
7643 struct i40e_mac_filter *f, *ftmp;
7644 struct i40e_pf *pf = vsi->back;
7645 struct i40e_hw *hw = &pf->hw;
7646 struct i40e_vsi_context ctxt;
7647 u8 enabled_tc = 0x1; /* TC0 enabled */
7648 int f_count = 0;
7649
7650 memset(&ctxt, 0, sizeof(ctxt));
7651 switch (vsi->type) {
7652 case I40E_VSI_MAIN:
7653 /* The PF's main VSI is already setup as part of the
7654 * device initialization, so we'll not bother with
7655 * the add_vsi call, but we will retrieve the current
7656 * VSI context.
7657 */
7658 ctxt.seid = pf->main_vsi_seid;
7659 ctxt.pf_num = pf->hw.pf_id;
7660 ctxt.vf_num = 0;
7661 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7662 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7663 if (ret) {
7664 dev_info(&pf->pdev->dev,
7665 "couldn't get pf vsi config, err %d, aq_err %d\n",
7666 ret, pf->hw.aq.asq_last_status);
7667 return -ENOENT;
7668 }
7669 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7670 vsi->info.valid_sections = 0;
7671
7672 vsi->seid = ctxt.seid;
7673 vsi->id = ctxt.vsi_number;
7674
7675 enabled_tc = i40e_pf_get_tc_map(pf);
7676
7677 /* MFP mode setup queue map and update VSI */
7678 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7679 memset(&ctxt, 0, sizeof(ctxt));
7680 ctxt.seid = pf->main_vsi_seid;
7681 ctxt.pf_num = pf->hw.pf_id;
7682 ctxt.vf_num = 0;
7683 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7684 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7685 if (ret) {
7686 dev_info(&pf->pdev->dev,
7687 "update vsi failed, aq_err=%d\n",
7688 pf->hw.aq.asq_last_status);
7689 ret = -ENOENT;
7690 goto err;
7691 }
7692 /* update the local VSI info queue map */
7693 i40e_vsi_update_queue_map(vsi, &ctxt);
7694 vsi->info.valid_sections = 0;
7695 } else {
7696 /* Default/Main VSI is only enabled for TC0
7697 * reconfigure it to enable all TCs that are
7698 * available on the port in SFP mode.
7699 */
7700 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7701 if (ret) {
7702 dev_info(&pf->pdev->dev,
7703 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7704 enabled_tc, ret,
7705 pf->hw.aq.asq_last_status);
7706 ret = -ENOENT;
7707 }
7708 }
7709 break;
7710
7711 case I40E_VSI_FDIR:
cbf61325
ASJ		 7712 ctxt.pf_num = hw->pf_id;
7713 ctxt.vf_num = 0;
7714 ctxt.uplink_seid = vsi->uplink_seid;
7715 ctxt.connection_type = 0x1; /* regular data port */
7716 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7717 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7718 break;
7719
7720 case I40E_VSI_VMDQ2:
7721 ctxt.pf_num = hw->pf_id;
7722 ctxt.vf_num = 0;
7723 ctxt.uplink_seid = vsi->uplink_seid;
7724 ctxt.connection_type = 0x1; /* regular data port */
7725 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7726
7727 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7728
7729 /* This VSI is connected to VEB so the switch_id
7730 * should be set to zero by default.
7731 */
7732 ctxt.info.switch_id = 0;
41c445ff
JB		 7733 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7734
7735 /* Setup the VSI tx/rx queue map for TC0 only for now */
7736 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7737 break;
7738
7739 case I40E_VSI_SRIOV:
7740 ctxt.pf_num = hw->pf_id;
7741 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7742 ctxt.uplink_seid = vsi->uplink_seid;
7743 ctxt.connection_type = 0x1; /* regular data port */
7744 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7745
7746 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7747
7748 /* This VSI is connected to VEB so the switch_id
7749 * should be set to zero by default.
7750 */
7751 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7752
7753 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7754 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 7755 if (pf->vf[vsi->vf_id].spoofchk) {
7756 ctxt.info.valid_sections |=
7757 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
7758 ctxt.info.sec_flags |=
7759 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
7760 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
7761 }
41c445ff
JB		 7762 /* Setup the VSI tx/rx queue map for TC0 only for now */
7763 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7764 break;
7765
38e00438
VD		 7766#ifdef I40E_FCOE
7767 case I40E_VSI_FCOE:
7768 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
7769 if (ret) {
7770 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
7771 return ret;
7772 }
7773 break;
7774
7775#endif /* I40E_FCOE */
41c445ff
JB		 7776 default:
7777 return -ENODEV;
7778 }
7779
7780 if (vsi->type != I40E_VSI_MAIN) {
7781 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7782 if (ret) {
7783 dev_info(&vsi->back->pdev->dev,
7784 "add vsi failed, aq_err=%d\n",
7785 vsi->back->hw.aq.asq_last_status);
7786 ret = -ENOENT;
7787 goto err;
7788 }
7789 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7790 vsi->info.valid_sections = 0;
7791 vsi->seid = ctxt.seid;
7792 vsi->id = ctxt.vsi_number;
7793 }
7794
7795 /* If macvlan filters already exist, force them to get loaded */
7796 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7797 f->changed = true;
7798 f_count++;
6252c7e4
SN		 7799
7800 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 7801 struct i40e_aqc_remove_macvlan_element_data element;
7802
7803 memset(&element, 0, sizeof(element));
7804 ether_addr_copy(element.mac_addr, f->macaddr);
7805 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7806 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
7807 &element, 1, NULL);
7808 if (ret) {
7809 /* some older FW has a different default */
7810 element.flags |=
7811 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7812 i40e_aq_remove_macvlan(hw, vsi->seid,
7813 &element, 1, NULL);
7814 }
7815
7816 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 7817 I40E_AQC_WRITE_TYPE_LAA_WOL,
7818 f->macaddr, NULL);
7819 }
41c445ff
JB		 7820 }
7821 if (f_count) {
7822 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7823 pf->flags |= I40E_FLAG_FILTER_SYNC;
7824 }
7825
7826 /* Update VSI BW information */
7827 ret = i40e_vsi_get_bw_info(vsi);
7828 if (ret) {
7829 dev_info(&pf->pdev->dev,
7830 "couldn't get vsi bw info, err %d, aq_err %d\n",
7831 ret, pf->hw.aq.asq_last_status);
7832 /* VSI is already added so not tearing that up */
7833 ret = 0;
7834 }
7835
7836err:
7837 return ret;
7838}
7839
7840/**
7841 * i40e_vsi_release - Delete a VSI and free its resources
7842 * @vsi: the VSI being removed
7843 *
7844 * Returns 0 on success or < 0 on error
7845 **/
7846int i40e_vsi_release(struct i40e_vsi *vsi)
7847{
7848 struct i40e_mac_filter *f, *ftmp;
7849 struct i40e_veb *veb = NULL;
7850 struct i40e_pf *pf;
7851 u16 uplink_seid;
7852 int i, n;
7853
7854 pf = vsi->back;
7855
7856 /* release of a VEB-owner or last VSI is not allowed */
7857 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7858 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7859 vsi->seid, vsi->uplink_seid);
7860 return -ENODEV;
7861 }
7862 if (vsi == pf->vsi[pf->lan_vsi] &&
7863 !test_bit(__I40E_DOWN, &pf->state)) {
7864 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7865 return -ENODEV;
7866 }
7867
7868 uplink_seid = vsi->uplink_seid;
7869 if (vsi->type != I40E_VSI_SRIOV) {
7870 if (vsi->netdev_registered) {
7871 vsi->netdev_registered = false;
7872 if (vsi->netdev) {
7873 /* results in a call to i40e_close() */
7874 unregister_netdev(vsi->netdev);
41c445ff
JB		 7875 }
7876 } else {
90ef8d47 7877 i40e_vsi_close(vsi);
41c445ff
JB		 7878 }
7879 i40e_vsi_disable_irq(vsi);
7880 }
7881
7882 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7883 i40e_del_filter(vsi, f->macaddr, f->vlan,
7884 f->is_vf, f->is_netdev);
7885 i40e_sync_vsi_filters(vsi);
7886
7887 i40e_vsi_delete(vsi);
7888 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7889 if (vsi->netdev) {
7890 free_netdev(vsi->netdev);
7891 vsi->netdev = NULL;
7892 }
41c445ff
JB		 7893 i40e_vsi_clear_rings(vsi);
7894 i40e_vsi_clear(vsi);
7895
7896 /* If this was the last thing on the VEB, except for the
7897 * controlling VSI, remove the VEB, which puts the controlling
7898 * VSI onto the next level down in the switch.
7899 *
7900 * Well, okay, there's one more exception here: don't remove
7901 * the orphan VEBs yet. We'll wait for an explicit remove request
7902 * from up the network stack.
7903 */
505682cd 7904 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7905 if (pf->vsi[i] &&
7906 pf->vsi[i]->uplink_seid == uplink_seid &&
7907 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7908 n++; /* count the VSIs */
7909 }
7910 }
7911 for (i = 0; i < I40E_MAX_VEB; i++) {
7912 if (!pf->veb[i])
7913 continue;
7914 if (pf->veb[i]->uplink_seid == uplink_seid)
7915 n++; /* count the VEBs */
7916 if (pf->veb[i]->seid == uplink_seid)
7917 veb = pf->veb[i];
7918 }
7919 if (n == 0 && veb && veb->uplink_seid != 0)
7920 i40e_veb_release(veb);
7921
7922 return 0;
7923}
7924
7925/**
7926 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7927 * @vsi: ptr to the VSI
7928 *
7929 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7930 * corresponding SW VSI structure and initializes num_queue_pairs for the
7931 * newly allocated VSI.
7932 *
7933 * Returns 0 on success or negative on failure
7934 **/
7935static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7936{
7937 int ret = -ENOENT;
7938 struct i40e_pf *pf = vsi->back;
7939
493fb300 7940 if (vsi->q_vectors[0]) {
41c445ff
JB		 7941 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7942 vsi->seid);
7943 return -EEXIST;
7944 }
7945
7946 if (vsi->base_vector) {
f29eaa3d 7947 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7948 vsi->seid, vsi->base_vector);
7949 return -EEXIST;
7950 }
7951
90e04070 7952 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7953 if (ret) {
7954 dev_info(&pf->pdev->dev,
7955 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7956 vsi->num_q_vectors, vsi->seid, ret);
7957 vsi->num_q_vectors = 0;
7958 goto vector_setup_out;
7959 }
7960
958a3e3b
SN		 7961 if (vsi->num_q_vectors)
7962 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7963 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7964 if (vsi->base_vector < 0) {
7965 dev_info(&pf->pdev->dev,
049a2be8
SN		 7966 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
7967 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 7968 i40e_vsi_free_q_vectors(vsi);
7969 ret = -ENOENT;
7970 goto vector_setup_out;
7971 }
7972
7973vector_setup_out:
7974 return ret;
7975}
7976
bc7d338f
ASJ		 7977/**
7978 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7979 * @vsi: pointer to the vsi.
7980 *
7981 * This re-allocates a vsi's queue resources.
7982 *
7983 * Returns pointer to the successfully allocated and configured VSI sw struct
7984 * on success, otherwise returns NULL on failure.
7985 **/
7986static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7987{
7988 struct i40e_pf *pf = vsi->back;
7989 u8 enabled_tc;
7990 int ret;
7991
7992 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7993 i40e_vsi_clear_rings(vsi);
7994
7995 i40e_vsi_free_arrays(vsi, false);
7996 i40e_set_num_rings_in_vsi(vsi);
7997 ret = i40e_vsi_alloc_arrays(vsi, false);
7998 if (ret)
7999 goto err_vsi;
8000
8001 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8002 if (ret < 0) {
049a2be8
SN		 8003 dev_info(&pf->pdev->dev,
8004 "failed to get tracking for %d queues for VSI %d err=%d\n",
8005 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8006 goto err_vsi;
8007 }
8008 vsi->base_queue = ret;
8009
8010 /* Update the FW view of the VSI. Force a reset of TC and queue
8011 * layout configurations.
8012 */
8013 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8014 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8015 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8016 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8017
8018 /* assign it some queues */
8019 ret = i40e_alloc_rings(vsi);
8020 if (ret)
8021 goto err_rings;
8022
8023 /* map all of the rings to the q_vectors */
8024 i40e_vsi_map_rings_to_vectors(vsi);
8025 return vsi;
8026
8027err_rings:
8028 i40e_vsi_free_q_vectors(vsi);
8029 if (vsi->netdev_registered) {
8030 vsi->netdev_registered = false;
8031 unregister_netdev(vsi->netdev);
8032 free_netdev(vsi->netdev);
8033 vsi->netdev = NULL;
8034 }
8035 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8036err_vsi:
8037 i40e_vsi_clear(vsi);
8038 return NULL;
8039}
8040
41c445ff
JB		 8041/**
8042 * i40e_vsi_setup - Set up a VSI by a given type
8043 * @pf: board private structure
8044 * @type: VSI type
8045 * @uplink_seid: the switch element to link to
8046 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8047 *
8048 * This allocates the sw VSI structure and its queue resources, then add a VSI
8049 * to the identified VEB.
8050 *
8051 * Returns pointer to the successfully allocated and configure VSI sw struct on
8052 * success, otherwise returns NULL on failure.
8053 **/
8054struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8055 u16 uplink_seid, u32 param1)
8056{
8057 struct i40e_vsi *vsi = NULL;
8058 struct i40e_veb *veb = NULL;
8059 int ret, i;
8060 int v_idx;
8061
8062 /* The requested uplink_seid must be either
8063 * - the PF's port seid
8064 * no VEB is needed because this is the PF
8065 * or this is a Flow Director special case VSI
8066 * - seid of an existing VEB
8067 * - seid of a VSI that owns an existing VEB
8068 * - seid of a VSI that doesn't own a VEB
8069 * a new VEB is created and the VSI becomes the owner
8070 * - seid of the PF VSI, which is what creates the first VEB
8071 * this is a special case of the previous
8072 *
8073 * Find which uplink_seid we were given and create a new VEB if needed
8074 */
8075 for (i = 0; i < I40E_MAX_VEB; i++) {
8076 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8077 veb = pf->veb[i];
8078 break;
8079 }
8080 }
8081
8082 if (!veb && uplink_seid != pf->mac_seid) {
8083
505682cd 8084 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8085 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8086 vsi = pf->vsi[i];
8087 break;
8088 }
8089 }
8090 if (!vsi) {
8091 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8092 uplink_seid);
8093 return NULL;
8094 }
8095
8096 if (vsi->uplink_seid == pf->mac_seid)
8097 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8098 vsi->tc_config.enabled_tc);
8099 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8100 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8101 vsi->tc_config.enabled_tc);
8102
8103 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8104 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8105 veb = pf->veb[i];
8106 }
8107 if (!veb) {
8108 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8109 return NULL;
8110 }
8111
8112 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8113 uplink_seid = veb->seid;
8114 }
8115
8116 /* get vsi sw struct */
8117 v_idx = i40e_vsi_mem_alloc(pf, type);
8118 if (v_idx < 0)
8119 goto err_alloc;
8120 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8121 if (!vsi)
8122 goto err_alloc;
41c445ff
JB		 8123 vsi->type = type;
8124 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8125
8126 if (type == I40E_VSI_MAIN)
8127 pf->lan_vsi = v_idx;
8128 else if (type == I40E_VSI_SRIOV)
8129 vsi->vf_id = param1;
8130 /* assign it some queues */
cbf61325
ASJ		 8131 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8132 vsi->idx);
41c445ff 8133 if (ret < 0) {
049a2be8
SN		 8134 dev_info(&pf->pdev->dev,
8135 "failed to get tracking for %d queues for VSI %d err=%d\n",
8136 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 8137 goto err_vsi;
8138 }
8139 vsi->base_queue = ret;
8140
8141 /* get a VSI from the hardware */
8142 vsi->uplink_seid = uplink_seid;
8143 ret = i40e_add_vsi(vsi);
8144 if (ret)
8145 goto err_vsi;
8146
8147 switch (vsi->type) {
8148 /* setup the netdev if needed */
8149 case I40E_VSI_MAIN:
8150 case I40E_VSI_VMDQ2:
38e00438 8151 case I40E_VSI_FCOE:
41c445ff
JB		 8152 ret = i40e_config_netdev(vsi);
8153 if (ret)
8154 goto err_netdev;
8155 ret = register_netdev(vsi->netdev);
8156 if (ret)
8157 goto err_netdev;
8158 vsi->netdev_registered = true;
8159 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8160#ifdef CONFIG_I40E_DCB
8161 /* Setup DCB netlink interface */
8162 i40e_dcbnl_setup(vsi);
8163#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8164 /* fall through */
8165
8166 case I40E_VSI_FDIR:
8167 /* set up vectors and rings if needed */
8168 ret = i40e_vsi_setup_vectors(vsi);
8169 if (ret)
8170 goto err_msix;
8171
8172 ret = i40e_alloc_rings(vsi);
8173 if (ret)
8174 goto err_rings;
8175
8176 /* map all of the rings to the q_vectors */
8177 i40e_vsi_map_rings_to_vectors(vsi);
8178
8179 i40e_vsi_reset_stats(vsi);
8180 break;
8181
8182 default:
8183 /* no netdev or rings for the other VSI types */
8184 break;
8185 }
8186
8187 return vsi;
8188
8189err_rings:
8190 i40e_vsi_free_q_vectors(vsi);
8191err_msix:
8192 if (vsi->netdev_registered) {
8193 vsi->netdev_registered = false;
8194 unregister_netdev(vsi->netdev);
8195 free_netdev(vsi->netdev);
8196 vsi->netdev = NULL;
8197 }
8198err_netdev:
8199 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8200err_vsi:
8201 i40e_vsi_clear(vsi);
8202err_alloc:
8203 return NULL;
8204}
8205
8206/**
8207 * i40e_veb_get_bw_info - Query VEB BW information
8208 * @veb: the veb to query
8209 *
8210 * Query the Tx scheduler BW configuration data for given VEB
8211 **/
8212static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8213{
8214 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8215 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8216 struct i40e_pf *pf = veb->pf;
8217 struct i40e_hw *hw = &pf->hw;
8218 u32 tc_bw_max;
8219 int ret = 0;
8220 int i;
8221
8222 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8223 &bw_data, NULL);
8224 if (ret) {
8225 dev_info(&pf->pdev->dev,
8226 "query veb bw config failed, aq_err=%d\n",
8227 hw->aq.asq_last_status);
8228 goto out;
8229 }
8230
8231 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8232 &ets_data, NULL);
8233 if (ret) {
8234 dev_info(&pf->pdev->dev,
8235 "query veb bw ets config failed, aq_err=%d\n",
8236 hw->aq.asq_last_status);
8237 goto out;
8238 }
8239
8240 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8241 veb->bw_max_quanta = ets_data.tc_bw_max;
8242 veb->is_abs_credits = bw_data.absolute_credits_enable;
8243 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8244 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8245 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8246 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8247 veb->bw_tc_limit_credits[i] =
8248 le16_to_cpu(bw_data.tc_bw_limits[i]);
8249 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8250 }
8251
8252out:
8253 return ret;
8254}
8255
8256/**
8257 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8258 * @pf: board private structure
8259 *
8260 * On error: returns error code (negative)
8261 * On success: returns vsi index in PF (positive)
8262 **/
8263static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8264{
8265 int ret = -ENOENT;
8266 struct i40e_veb *veb;
8267 int i;
8268
8269 /* Need to protect the allocation of switch elements at the PF level */
8270 mutex_lock(&pf->switch_mutex);
8271
8272 /* VEB list may be fragmented if VEB creation/destruction has
8273 * been happening. We can afford to do a quick scan to look
8274 * for any free slots in the list.
8275 *
8276 * find next empty veb slot, looping back around if necessary
8277 */
8278 i = 0;
8279 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8280 i++;
8281 if (i >= I40E_MAX_VEB) {
8282 ret = -ENOMEM;
8283 goto err_alloc_veb; /* out of VEB slots! */
8284 }
8285
8286 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8287 if (!veb) {
8288 ret = -ENOMEM;
8289 goto err_alloc_veb;
8290 }
8291 veb->pf = pf;
8292 veb->idx = i;
8293 veb->enabled_tc = 1;
8294
8295 pf->veb[i] = veb;
8296 ret = i;
8297err_alloc_veb:
8298 mutex_unlock(&pf->switch_mutex);
8299 return ret;
8300}
8301
8302/**
8303 * i40e_switch_branch_release - Delete a branch of the switch tree
8304 * @branch: where to start deleting
8305 *
8306 * This uses recursion to find the tips of the branch to be
8307 * removed, deleting until we get back to and can delete this VEB.
8308 **/
8309static void i40e_switch_branch_release(struct i40e_veb *branch)
8310{
8311 struct i40e_pf *pf = branch->pf;
8312 u16 branch_seid = branch->seid;
8313 u16 veb_idx = branch->idx;
8314 int i;
8315
8316 /* release any VEBs on this VEB - RECURSION */
8317 for (i = 0; i < I40E_MAX_VEB; i++) {
8318 if (!pf->veb[i])
8319 continue;
8320 if (pf->veb[i]->uplink_seid == branch->seid)
8321 i40e_switch_branch_release(pf->veb[i]);
8322 }
8323
8324 /* Release the VSIs on this VEB, but not the owner VSI.
8325 *
8326 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8327 * the VEB itself, so don't use (*branch) after this loop.
8328 */
505682cd 8329 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8330 if (!pf->vsi[i])
8331 continue;
8332 if (pf->vsi[i]->uplink_seid == branch_seid &&
8333 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8334 i40e_vsi_release(pf->vsi[i]);
8335 }
8336 }
8337
8338 /* There's one corner case where the VEB might not have been
8339 * removed, so double check it here and remove it if needed.
8340 * This case happens if the veb was created from the debugfs
8341 * commands and no VSIs were added to it.
8342 */
8343 if (pf->veb[veb_idx])
8344 i40e_veb_release(pf->veb[veb_idx]);
8345}
8346
8347/**
8348 * i40e_veb_clear - remove veb struct
8349 * @veb: the veb to remove
8350 **/
8351static void i40e_veb_clear(struct i40e_veb *veb)
8352{
8353 if (!veb)
8354 return;
8355
8356 if (veb->pf) {
8357 struct i40e_pf *pf = veb->pf;
8358
8359 mutex_lock(&pf->switch_mutex);
8360 if (pf->veb[veb->idx] == veb)
8361 pf->veb[veb->idx] = NULL;
8362 mutex_unlock(&pf->switch_mutex);
8363 }
8364
8365 kfree(veb);
8366}
8367
8368/**
8369 * i40e_veb_release - Delete a VEB and free its resources
8370 * @veb: the VEB being removed
8371 **/
8372void i40e_veb_release(struct i40e_veb *veb)
8373{
8374 struct i40e_vsi *vsi = NULL;
8375 struct i40e_pf *pf;
8376 int i, n = 0;
8377
8378 pf = veb->pf;
8379
8380 /* find the remaining VSI and check for extras */
505682cd 8381 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8382 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
8383 n++;
8384 vsi = pf->vsi[i];
8385 }
8386 }
8387 if (n != 1) {
8388 dev_info(&pf->pdev->dev,
8389 "can't remove VEB %d with %d VSIs left\n",
8390 veb->seid, n);
8391 return;
8392 }
8393
8394 /* move the remaining VSI to uplink veb */
8395 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8396 if (veb->uplink_seid) {
8397 vsi->uplink_seid = veb->uplink_seid;
8398 if (veb->uplink_seid == pf->mac_seid)
8399 vsi->veb_idx = I40E_NO_VEB;
8400 else
8401 vsi->veb_idx = veb->veb_idx;
8402 } else {
8403 /* floating VEB */
8404 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8405 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8406 }
8407
8408 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8409 i40e_veb_clear(veb);
41c445ff
JB		 8410}
8411
8412/**
8413 * i40e_add_veb - create the VEB in the switch
8414 * @veb: the VEB to be instantiated
8415 * @vsi: the controlling VSI
8416 **/
8417static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8418{
56747264 8419 bool is_default = false;
e1c51b95 8420 bool is_cloud = false;
41c445ff
JB		 8421 int ret;
8422
8423 /* get a VEB from the hardware */
8424 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8425 veb->enabled_tc, is_default,
8426 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8427 if (ret) {
8428 dev_info(&veb->pf->pdev->dev,
8429 "couldn't add VEB, err %d, aq_err %d\n",
8430 ret, veb->pf->hw.aq.asq_last_status);
8431 return -EPERM;
8432 }
8433
8434 /* get statistics counter */
8435 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8436 &veb->stats_idx, NULL, NULL, NULL);
8437 if (ret) {
8438 dev_info(&veb->pf->pdev->dev,
8439 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8440 ret, veb->pf->hw.aq.asq_last_status);
8441 return -EPERM;
8442 }
8443 ret = i40e_veb_get_bw_info(veb);
8444 if (ret) {
8445 dev_info(&veb->pf->pdev->dev,
8446 "couldn't get VEB bw info, err %d, aq_err %d\n",
8447 ret, veb->pf->hw.aq.asq_last_status);
8448 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8449 return -ENOENT;
8450 }
8451
8452 vsi->uplink_seid = veb->seid;
8453 vsi->veb_idx = veb->idx;
8454 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8455
8456 return 0;
8457}
8458
8459/**
8460 * i40e_veb_setup - Set up a VEB
8461 * @pf: board private structure
8462 * @flags: VEB setup flags
8463 * @uplink_seid: the switch element to link to
8464 * @vsi_seid: the initial VSI seid
8465 * @enabled_tc: Enabled TC bit-map
8466 *
8467 * This allocates the sw VEB structure and links it into the switch
8468 * It is possible and legal for this to be a duplicate of an already
8469 * existing VEB. It is also possible for both uplink and vsi seids
8470 * to be zero, in order to create a floating VEB.
8471 *
8472 * Returns pointer to the successfully allocated VEB sw struct on
8473 * success, otherwise returns NULL on failure.
8474 **/
8475struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8476 u16 uplink_seid, u16 vsi_seid,
8477 u8 enabled_tc)
8478{
8479 struct i40e_veb *veb, *uplink_veb = NULL;
8480 int vsi_idx, veb_idx;
8481 int ret;
8482
8483 /* if one seid is 0, the other must be 0 to create a floating relay */
8484 if ((uplink_seid == 0 || vsi_seid == 0) &&
8485 (uplink_seid + vsi_seid != 0)) {
8486 dev_info(&pf->pdev->dev,
8487 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8488 uplink_seid, vsi_seid);
8489 return NULL;
8490 }
8491
8492 /* make sure there is such a vsi and uplink */
505682cd 8493 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8494 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8495 break;
505682cd 8496 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8497 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8498 vsi_seid);
8499 return NULL;
8500 }
8501
8502 if (uplink_seid && uplink_seid != pf->mac_seid) {
8503 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8504 if (pf->veb[veb_idx] &&
8505 pf->veb[veb_idx]->seid == uplink_seid) {
8506 uplink_veb = pf->veb[veb_idx];
8507 break;
8508 }
8509 }
8510 if (!uplink_veb) {
8511 dev_info(&pf->pdev->dev,
8512 "uplink seid %d not found\n", uplink_seid);
8513 return NULL;
8514 }
8515 }
8516
8517 /* get veb sw struct */
8518 veb_idx = i40e_veb_mem_alloc(pf);
8519 if (veb_idx < 0)
8520 goto err_alloc;
8521 veb = pf->veb[veb_idx];
8522 veb->flags = flags;
8523 veb->uplink_seid = uplink_seid;
8524 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8525 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8526
8527 /* create the VEB in the switch */
8528 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8529 if (ret)
8530 goto err_veb;
1bb8b935
SN		 8531 if (vsi_idx == pf->lan_vsi)
8532 pf->lan_veb = veb->idx;
41c445ff
JB		 8533
8534 return veb;
8535
8536err_veb:
8537 i40e_veb_clear(veb);
8538err_alloc:
8539 return NULL;
8540}
8541
8542/**
8543 * i40e_setup_pf_switch_element - set pf vars based on switch type
8544 * @pf: board private structure
8545 * @ele: element we are building info from
8546 * @num_reported: total number of elements
8547 * @printconfig: should we print the contents
8548 *
8549 * helper function to assist in extracting a few useful SEID values.
8550 **/
8551static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8552 struct i40e_aqc_switch_config_element_resp *ele,
8553 u16 num_reported, bool printconfig)
8554{
8555 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8556 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8557 u8 element_type = ele->element_type;
8558 u16 seid = le16_to_cpu(ele->seid);
8559
8560 if (printconfig)
8561 dev_info(&pf->pdev->dev,
8562 "type=%d seid=%d uplink=%d downlink=%d\n",
8563 element_type, seid, uplink_seid, downlink_seid);
8564
8565 switch (element_type) {
8566 case I40E_SWITCH_ELEMENT_TYPE_MAC:
8567 pf->mac_seid = seid;
8568 break;
8569 case I40E_SWITCH_ELEMENT_TYPE_VEB:
8570 /* Main VEB? */
8571 if (uplink_seid != pf->mac_seid)
8572 break;
8573 if (pf->lan_veb == I40E_NO_VEB) {
8574 int v;
8575
8576 /* find existing or else empty VEB */
8577 for (v = 0; v < I40E_MAX_VEB; v++) {
8578 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
8579 pf->lan_veb = v;
8580 break;
8581 }
8582 }
8583 if (pf->lan_veb == I40E_NO_VEB) {
8584 v = i40e_veb_mem_alloc(pf);
8585 if (v < 0)
8586 break;
8587 pf->lan_veb = v;
8588 }
8589 }
8590
8591 pf->veb[pf->lan_veb]->seid = seid;
8592 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
8593 pf->veb[pf->lan_veb]->pf = pf;
8594 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
8595 break;
8596 case I40E_SWITCH_ELEMENT_TYPE_VSI:
8597 if (num_reported != 1)
8598 break;
8599 /* This is immediately after a reset so we can assume this is
8600 * the PF's VSI
8601 */
8602 pf->mac_seid = uplink_seid;
8603 pf->pf_seid = downlink_seid;
8604 pf->main_vsi_seid = seid;
8605 if (printconfig)
8606 dev_info(&pf->pdev->dev,
8607 "pf_seid=%d main_vsi_seid=%d\n",
8608 pf->pf_seid, pf->main_vsi_seid);
8609 break;
8610 case I40E_SWITCH_ELEMENT_TYPE_PF:
8611 case I40E_SWITCH_ELEMENT_TYPE_VF:
8612 case I40E_SWITCH_ELEMENT_TYPE_EMP:
8613 case I40E_SWITCH_ELEMENT_TYPE_BMC:
8614 case I40E_SWITCH_ELEMENT_TYPE_PE:
8615 case I40E_SWITCH_ELEMENT_TYPE_PA:
8616 /* ignore these for now */
8617 break;
8618 default:
8619 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
8620 element_type, seid);
8621 break;
8622 }
8623}
8624
8625/**
8626 * i40e_fetch_switch_configuration - Get switch config from firmware
8627 * @pf: board private structure
8628 * @printconfig: should we print the contents
8629 *
8630 * Get the current switch configuration from the device and
8631 * extract a few useful SEID values.
8632 **/
8633int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
8634{
8635 struct i40e_aqc_get_switch_config_resp *sw_config;
8636 u16 next_seid = 0;
8637 int ret = 0;
8638 u8 *aq_buf;
8639 int i;
8640
8641 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
8642 if (!aq_buf)
8643 return -ENOMEM;
8644
8645 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
8646 do {
8647 u16 num_reported, num_total;
8648
8649 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
8650 I40E_AQ_LARGE_BUF,
8651 &next_seid, NULL);
8652 if (ret) {
8653 dev_info(&pf->pdev->dev,
8654 "get switch config failed %d aq_err=%x\n",
8655 ret, pf->hw.aq.asq_last_status);
8656 kfree(aq_buf);
8657 return -ENOENT;
8658 }
8659
8660 num_reported = le16_to_cpu(sw_config->header.num_reported);
8661 num_total = le16_to_cpu(sw_config->header.num_total);
8662
8663 if (printconfig)
8664 dev_info(&pf->pdev->dev,
8665 "header: %d reported %d total\n",
8666 num_reported, num_total);
8667
41c445ff
JB		 8668 for (i = 0; i < num_reported; i++) {
8669 struct i40e_aqc_switch_config_element_resp *ele =
8670 &sw_config->element[i];
8671
8672 i40e_setup_pf_switch_element(pf, ele, num_reported,
8673 printconfig);
8674 }
8675 } while (next_seid != 0);
8676
8677 kfree(aq_buf);
8678 return ret;
8679}
8680
8681/**
8682 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8683 * @pf: board private structure
bc7d338f 8684 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8685 *
8686 * Returns 0 on success, negative value on failure
8687 **/
bc7d338f 8688static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 8689{
8690 int ret;
8691
8692 /* find out what's out there already */
8693 ret = i40e_fetch_switch_configuration(pf, false);
8694 if (ret) {
8695 dev_info(&pf->pdev->dev,
8696 "couldn't fetch switch config, err %d, aq_err %d\n",
8697 ret, pf->hw.aq.asq_last_status);
8698 return ret;
8699 }
8700 i40e_pf_reset_stats(pf);
8701
41c445ff 8702 /* first time setup */
bc7d338f 8703 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8704 struct i40e_vsi *vsi = NULL;
8705 u16 uplink_seid;
8706
8707 /* Set up the PF VSI associated with the PF's main VSI
8708 * that is already in the HW switch
8709 */
8710 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8711 uplink_seid = pf->veb[pf->lan_veb]->seid;
8712 else
8713 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8714 if (pf->lan_vsi == I40E_NO_VSI)
8715 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8716 else if (reinit)
8717 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8718 if (!vsi) {
8719 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8720 i40e_fdir_teardown(pf);
8721 return -EAGAIN;
8722 }
41c445ff
JB		 8723 } else {
8724 /* force a reset of TC and queue layout configurations */
8725 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8726 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8727 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8728 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8729 }
8730 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8731
cbf61325
ASJ		 8732 i40e_fdir_sb_setup(pf);
8733
41c445ff
JB		 8734 /* Setup static PF queue filter control settings */
8735 ret = i40e_setup_pf_filter_control(pf);
8736 if (ret) {
8737 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8738 ret);
8739 /* Failure here should not stop continuing other steps */
8740 }
8741
8742 /* enable RSS in the HW, even for only one queue, as the stack can use
8743 * the hash
8744 */
8745 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8746 i40e_config_rss(pf);
8747
8748 /* fill in link information and enable LSE reporting */
a34a6711
MW		 8749 i40e_update_link_info(&pf->hw, true);
8750 i40e_link_event(pf);
8751
8752 /* Initialize user-specific link properties */
8753 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8754 I40E_AQ_AN_COMPLETED) ? true : false);
8755
8756 /* fill in link information and enable LSE reporting */
8109e123 8757 i40e_update_link_info(&pf->hw, true);
41c445ff
JB		 8758 i40e_link_event(pf);
8759
d52c20b7 8760 /* Initialize user-specific link properties */
41c445ff
JB		 8761 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8762 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 8763
beb0dff1
JK		 8764 i40e_ptp_init(pf);
8765
41c445ff
JB		 8766 return ret;
8767}
8768
41c445ff
JB		 8769/**
8770 * i40e_determine_queue_usage - Work out queue distribution
8771 * @pf: board private structure
8772 **/
8773static void i40e_determine_queue_usage(struct i40e_pf *pf)
8774{
41c445ff
JB		 8775 int queues_left;
8776
8777 pf->num_lan_qps = 0;
38e00438
VD		 8778#ifdef I40E_FCOE
8779 pf->num_fcoe_qps = 0;
8780#endif
41c445ff
JB		 8781
8782 /* Find the max queues to be put into basic use. We'll always be
8783 * using TC0, whether or not DCB is running, and TC0 will get the
8784 * big RSS set.
8785 */
8786 queues_left = pf->hw.func_caps.num_tx_qp;
8787
cbf61325 8788 if ((queues_left == 1) ||
9aa7e935 8789 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 8790 /* one qp for PF, no queues for anything else */
8791 queues_left = 0;
8792 pf->rss_size = pf->num_lan_qps = 1;
8793
8794 /* make sure all the fancies are disabled */
60ea5f83 8795 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8796#ifdef I40E_FCOE
8797 I40E_FLAG_FCOE_ENABLED |
8798#endif
60ea5f83
JB		 8799 I40E_FLAG_FD_SB_ENABLED |
8800 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8801 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 8802 I40E_FLAG_SRIOV_ENABLED |
8803 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 8804 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
8805 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 8806 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8807 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 8808 /* one qp for PF */
8809 pf->rss_size = pf->num_lan_qps = 1;
8810 queues_left -= pf->num_lan_qps;
8811
8812 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8813#ifdef I40E_FCOE
8814 I40E_FLAG_FCOE_ENABLED |
8815#endif
9aa7e935
FZ		 8816 I40E_FLAG_FD_SB_ENABLED |
8817 I40E_FLAG_FD_ATR_ENABLED |
8818 I40E_FLAG_DCB_ENABLED |
8819 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8820 } else {
cbf61325 8821 /* Not enough queues for all TCs */
4d9b6043 8822 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 8823 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 8824 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 8825 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8826 }
8827 pf->num_lan_qps = pf->rss_size_max;
8828 queues_left -= pf->num_lan_qps;
8829 }
8830
38e00438
VD		 8831#ifdef I40E_FCOE
8832 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
8833 if (I40E_DEFAULT_FCOE <= queues_left) {
8834 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
8835 } else if (I40E_MINIMUM_FCOE <= queues_left) {
8836 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
8837 } else {
8838 pf->num_fcoe_qps = 0;
8839 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
8840 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
8841 }
8842
8843 queues_left -= pf->num_fcoe_qps;
8844 }
8845
8846#endif
cbf61325
ASJ		 8847 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8848 if (queues_left > 1) {
8849 queues_left -= 1; /* save 1 queue for FD */
8850 } else {
8851 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8852 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8853 }
41c445ff
JB		 8854 }
8855
8856 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8857 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8858 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8859 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8860 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8861 }
8862
8863 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8864 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8865 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8866 (queues_left / pf->num_vmdq_qps));
8867 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8868 }
8869
f8ff1464 8870 pf->queues_left = queues_left;
38e00438
VD		 8871#ifdef I40E_FCOE
8872 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
8873#endif
41c445ff
JB		 8874}
8875
8876/**
8877 * i40e_setup_pf_filter_control - Setup PF static filter control
8878 * @pf: PF to be setup
8879 *
8880 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8881 * settings. If PE/FCoE are enabled then it will also set the per PF
8882 * based filter sizes required for them. It also enables Flow director,
8883 * ethertype and macvlan type filter settings for the pf.
8884 *
8885 * Returns 0 on success, negative on failure
8886 **/
8887static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8888{
8889 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8890
8891 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8892
8893 /* Flow Director is enabled */
60ea5f83 8894 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8895 settings->enable_fdir = true;
8896
8897 /* Ethtype and MACVLAN filters enabled for PF */
8898 settings->enable_ethtype = true;
8899 settings->enable_macvlan = true;
8900
8901 if (i40e_set_filter_control(&pf->hw, settings))
8902 return -ENOENT;
8903
8904 return 0;
8905}
8906
0c22b3dd
JB		 8907#define INFO_STRING_LEN 255
8908static void i40e_print_features(struct i40e_pf *pf)
8909{
8910 struct i40e_hw *hw = &pf->hw;
8911 char *buf, *string;
8912
8913 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8914 if (!string) {
8915 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8916 return;
8917 }
8918
8919 buf = string;
8920
8921 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8922#ifdef CONFIG_PCI_IOV
8923 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8924#endif
8925 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8926 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8927
8928 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8929 buf += sprintf(buf, "RSS ");
0c22b3dd 8930 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8931 buf += sprintf(buf, "FD_ATR ");
8932 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8933 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8934 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8935 }
4d9b6043 8936 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 8937 buf += sprintf(buf, "DCB ");
8938 if (pf->flags & I40E_FLAG_PTP)
8939 buf += sprintf(buf, "PTP ");
38e00438
VD		 8940#ifdef I40E_FCOE
8941 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
8942 buf += sprintf(buf, "FCOE ");
8943#endif
0c22b3dd
JB		 8944
8945 BUG_ON(buf > (string + INFO_STRING_LEN));
8946 dev_info(&pf->pdev->dev, "%s\n", string);
8947 kfree(string);
8948}
8949
41c445ff
JB		 8950/**
8951 * i40e_probe - Device initialization routine
8952 * @pdev: PCI device information struct
8953 * @ent: entry in i40e_pci_tbl
8954 *
8955 * i40e_probe initializes a pf identified by a pci_dev structure.
8956 * The OS initialization, configuring of the pf private structure,
8957 * and a hardware reset occur.
8958 *
8959 * Returns 0 on success, negative on failure
8960 **/
8961static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8962{
41c445ff
JB		 8963 struct i40e_pf *pf;
8964 struct i40e_hw *hw;
93cd765b 8965 static u16 pfs_found;
d4dfb81a 8966 u16 link_status;
41c445ff
JB		 8967 int err = 0;
8968 u32 len;
8a9eb7d3 8969 u32 i;
41c445ff
JB		 8970
8971 err = pci_enable_device_mem(pdev);
8972 if (err)
8973 return err;
8974
8975 /* set up for high or low dma */
6494294f 8976 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8977 if (err) {
e3e3bfdd
JS		 8978 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8979 if (err) {
8980 dev_err(&pdev->dev,
8981 "DMA configuration failed: 0x%x\n", err);
8982 goto err_dma;
8983 }
41c445ff
JB		 8984 }
8985
8986 /* set up pci connections */
8987 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8988 IORESOURCE_MEM), i40e_driver_name);
8989 if (err) {
8990 dev_info(&pdev->dev,
8991 "pci_request_selected_regions failed %d\n", err);
8992 goto err_pci_reg;
8993 }
8994
8995 pci_enable_pcie_error_reporting(pdev);
8996 pci_set_master(pdev);
8997
8998 /* Now that we have a PCI connection, we need to do the
8999 * low level device setup. This is primarily setting up
9000 * the Admin Queue structures and then querying for the
9001 * device's current profile information.
9002 */
9003 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9004 if (!pf) {
9005 err = -ENOMEM;
9006 goto err_pf_alloc;
9007 }
9008 pf->next_vsi = 0;
9009 pf->pdev = pdev;
9010 set_bit(__I40E_DOWN, &pf->state);
9011
9012 hw = &pf->hw;
9013 hw->back = pf;
9014 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9015 pci_resource_len(pdev, 0));
9016 if (!hw->hw_addr) {
9017 err = -EIO;
9018 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9019 (unsigned int)pci_resource_start(pdev, 0),
9020 (unsigned int)pci_resource_len(pdev, 0), err);
9021 goto err_ioremap;
9022 }
9023 hw->vendor_id = pdev->vendor;
9024 hw->device_id = pdev->device;
9025 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9026 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9027 hw->subsystem_device_id = pdev->subsystem_device;
9028 hw->bus.device = PCI_SLOT(pdev->devfn);
9029 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9030 pf->instance = pfs_found;
41c445ff 9031
5b5faa43
SN		 9032 if (debug != -1) {
9033 pf->msg_enable = pf->hw.debug_mask;
9034 pf->msg_enable = debug;
9035 }
9036
7134f9ce
JB		 9037 /* do a special CORER for clearing PXE mode once at init */
9038 if (hw->revision_id == 0 &&
9039 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9040 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9041 i40e_flush(hw);
9042 msleep(200);
9043 pf->corer_count++;
9044
9045 i40e_clear_pxe_mode(hw);
9046 }
9047
41c445ff 9048 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9049 i40e_clear_hw(hw);
41c445ff
JB		 9050 err = i40e_pf_reset(hw);
9051 if (err) {
9052 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9053 goto err_pf_reset;
9054 }
9055 pf->pfr_count++;
9056
9057 hw->aq.num_arq_entries = I40E_AQ_LEN;
9058 hw->aq.num_asq_entries = I40E_AQ_LEN;
9059 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9060 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9061 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
9062 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
9063 "%s-pf%d:misc",
9064 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
9065
9066 err = i40e_init_shared_code(hw);
9067 if (err) {
9068 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9069 goto err_pf_reset;
9070 }
9071
d52c20b7
JB		 9072 /* set up a default setting for link flow control */
9073 pf->hw.fc.requested_mode = I40E_FC_NONE;
9074
41c445ff
JB		 9075 err = i40e_init_adminq(hw);
9076 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9077 if (err) {
9078 dev_info(&pdev->dev,
7aa67613 9079 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9080 goto err_pf_reset;
9081 }
9082
7aa67613
CS		 9083 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9084 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9085 dev_info(&pdev->dev,
7aa67613
CS		 9086 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9087 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9088 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9089 dev_info(&pdev->dev,
7aa67613 9090 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62
SN		 9091
9092
4eb3f768
SN		 9093 i40e_verify_eeprom(pf);
9094
2c5fe33b
JB		 9095 /* Rev 0 hardware was never productized */
9096 if (hw->revision_id < 1)
9097 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9098
6ff4ef86 9099 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9100 err = i40e_get_capabilities(pf);
9101 if (err)
9102 goto err_adminq_setup;
9103
9104 err = i40e_sw_init(pf);
9105 if (err) {
9106 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9107 goto err_sw_init;
9108 }
9109
9110 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9111 hw->func_caps.num_rx_qp,
9112 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9113 if (err) {
9114 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9115 goto err_init_lan_hmc;
9116 }
9117
9118 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9119 if (err) {
9120 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9121 err = -ENOENT;
9122 goto err_configure_lan_hmc;
9123 }
9124
9125 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9126 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9127 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9128 err = -EIO;
9129 goto err_mac_addr;
9130 }
9131 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9132 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9133 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9134 if (is_valid_ether_addr(hw->mac.port_addr))
9135 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9136#ifdef I40E_FCOE
9137 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9138 if (err)
9139 dev_info(&pdev->dev,
9140 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9141 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9142 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9143 hw->mac.san_addr);
9144 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9145 }
9146 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9147#endif /* I40E_FCOE */
41c445ff
JB		 9148
9149 pci_set_drvdata(pdev, pf);
9150 pci_save_state(pdev);
4e3b35b0
NP		 9151#ifdef CONFIG_I40E_DCB
9152 err = i40e_init_pf_dcb(pf);
9153 if (err) {
9154 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
4d9b6043 9155 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9156 /* Continue without DCB enabled */
4e3b35b0
NP		 9157 }
9158#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9159
9160 /* set up periodic task facility */
9161 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9162 pf->service_timer_period = HZ;
9163
9164 INIT_WORK(&pf->service_task, i40e_service_task);
9165 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9166 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9167 pf->link_check_timeout = jiffies;
9168
8e2773ae
SN		 9169 /* WoL defaults to disabled */
9170 pf->wol_en = false;
9171 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9172
41c445ff
JB		 9173 /* set up the main switch operations */
9174 i40e_determine_queue_usage(pf);
9175 i40e_init_interrupt_scheme(pf);
9176
505682cd
MW		 9177 /* The number of VSIs reported by the FW is the minimum guaranteed
9178 * to us; HW supports far more and we share the remaining pool with
9179 * the other PFs. We allocate space for more than the guarantee with
9180 * the understanding that we might not get them all later.
41c445ff 9181 */
505682cd
MW		 9182 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9183 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9184 else
9185 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9186
9187 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9188 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9189 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9190 if (!pf->vsi) {
9191 err = -ENOMEM;
41c445ff 9192 goto err_switch_setup;
ed87ac09 9193 }
41c445ff 9194
bc7d338f 9195 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9196 if (err) {
9197 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9198 goto err_vsis;
9199 }
8a9eb7d3 9200 /* if FDIR VSI was set up, start it now */
505682cd 9201 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9202 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9203 i40e_vsi_open(pf->vsi[i]);
9204 break;
9205 }
9206 }
41c445ff 9207
7e2453fe
JB		 9208 /* driver is only interested in link up/down and module qualification
9209 * reports from firmware
9210 */
9211 err = i40e_aq_set_phy_int_mask(&pf->hw,
9212 I40E_AQ_EVENT_LINK_UPDOWN |
9213 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9214 if (err)
9215 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9216
cafa2ee6
ASJ		 9217 msleep(75);
9218 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9219 if (err) {
9220 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9221 pf->hw.aq.asq_last_status);
9222 }
9223
41c445ff
JB		 9224 /* The main driver is (mostly) up and happy. We need to set this state
9225 * before setting up the misc vector or we get a race and the vector
9226 * ends up disabled forever.
9227 */
9228 clear_bit(__I40E_DOWN, &pf->state);
9229
9230 /* In case of MSIX we are going to setup the misc vector right here
9231 * to handle admin queue events etc. In case of legacy and MSI
9232 * the misc functionality and queue processing is combined in
9233 * the same vector and that gets setup at open.
9234 */
9235 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9236 err = i40e_setup_misc_vector(pf);
9237 if (err) {
9238 dev_info(&pdev->dev,
9239 "setup of misc vector failed: %d\n", err);
9240 goto err_vsis;
9241 }
9242 }
9243
df805f62 9244#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9245 /* prep for VF support */
9246 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9247 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9248 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9249 u32 val;
9250
9251 /* disable link interrupts for VFs */
9252 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9253 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9254 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9255 i40e_flush(hw);
4aeec010
MW		 9256
9257 if (pci_num_vf(pdev)) {
9258 dev_info(&pdev->dev,
9259 "Active VFs found, allocating resources.\n");
9260 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9261 if (err)
9262 dev_info(&pdev->dev,
9263 "Error %d allocating resources for existing VFs\n",
9264 err);
9265 }
41c445ff 9266 }
df805f62 9267#endif /* CONFIG_PCI_IOV */
41c445ff 9268
93cd765b
ASJ		 9269 pfs_found++;
9270
41c445ff
JB		 9271 i40e_dbg_pf_init(pf);
9272
9273 /* tell the firmware that we're starting */
44033fac 9274 i40e_send_version(pf);
41c445ff
JB		 9275
9276 /* since everything's happy, start the service_task timer */
9277 mod_timer(&pf->service_timer,
9278 round_jiffies(jiffies + pf->service_timer_period));
9279
38e00438
VD		 9280#ifdef I40E_FCOE
9281 /* create FCoE interface */
9282 i40e_fcoe_vsi_setup(pf);
9283
9284#endif
d4dfb81a
CS		 9285 /* Get the negotiated link width and speed from PCI config space */
9286 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9287
9288 i40e_set_pci_config_data(hw, link_status);
9289
69bfb110 9290 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9291 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9292 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9293 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9294 "Unknown"),
9295 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9296 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9297 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9298 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9299 "Unknown"));
9300
9301 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9302 hw->bus.speed < i40e_bus_speed_8000) {
9303 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9304 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9305 }
9306
0c22b3dd
JB		 9307 /* print a string summarizing features */
9308 i40e_print_features(pf);
9309
41c445ff
JB		 9310 return 0;
9311
9312 /* Unwind what we've done if something failed in the setup */
9313err_vsis:
9314 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9315 i40e_clear_interrupt_scheme(pf);
9316 kfree(pf->vsi);
04b03013
SN		 9317err_switch_setup:
9318 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9319 del_timer_sync(&pf->service_timer);
9320err_mac_addr:
9321err_configure_lan_hmc:
9322 (void)i40e_shutdown_lan_hmc(hw);
9323err_init_lan_hmc:
9324 kfree(pf->qp_pile);
9325 kfree(pf->irq_pile);
9326err_sw_init:
9327err_adminq_setup:
9328 (void)i40e_shutdown_adminq(hw);
9329err_pf_reset:
9330 iounmap(hw->hw_addr);
9331err_ioremap:
9332 kfree(pf);
9333err_pf_alloc:
9334 pci_disable_pcie_error_reporting(pdev);
9335 pci_release_selected_regions(pdev,
9336 pci_select_bars(pdev, IORESOURCE_MEM));
9337err_pci_reg:
9338err_dma:
9339 pci_disable_device(pdev);
9340 return err;
9341}
9342
9343/**
9344 * i40e_remove - Device removal routine
9345 * @pdev: PCI device information struct
9346 *
9347 * i40e_remove is called by the PCI subsystem to alert the driver
9348 * that is should release a PCI device. This could be caused by a
9349 * Hot-Plug event, or because the driver is going to be removed from
9350 * memory.
9351 **/
9352static void i40e_remove(struct pci_dev *pdev)
9353{
9354 struct i40e_pf *pf = pci_get_drvdata(pdev);
9355 i40e_status ret_code;
41c445ff
JB		 9356 int i;
9357
9358 i40e_dbg_pf_exit(pf);
9359
beb0dff1
JK		 9360 i40e_ptp_stop(pf);
9361
41c445ff
JB		 9362 /* no more scheduling of any task */
9363 set_bit(__I40E_DOWN, &pf->state);
9364 del_timer_sync(&pf->service_timer);
9365 cancel_work_sync(&pf->service_task);
9366
eb2d80bc
MW		 9367 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
9368 i40e_free_vfs(pf);
9369 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
9370 }
9371
41c445ff
JB		 9372 i40e_fdir_teardown(pf);
9373
9374 /* If there is a switch structure or any orphans, remove them.
9375 * This will leave only the PF's VSI remaining.
9376 */
9377 for (i = 0; i < I40E_MAX_VEB; i++) {
9378 if (!pf->veb[i])
9379 continue;
9380
9381 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
9382 pf->veb[i]->uplink_seid == 0)
9383 i40e_switch_branch_release(pf->veb[i]);
9384 }
9385
9386 /* Now we can shutdown the PF's VSI, just before we kill
9387 * adminq and hmc.
9388 */
9389 if (pf->vsi[pf->lan_vsi])
9390 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
9391
9392 i40e_stop_misc_vector(pf);
9393 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9394 synchronize_irq(pf->msix_entries[0].vector);
9395 free_irq(pf->msix_entries[0].vector, pf);
9396 }
9397
9398 /* shutdown and destroy the HMC */
60442dea
SN		 9399 if (pf->hw.hmc.hmc_obj) {
9400 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
9401 if (ret_code)
9402 dev_warn(&pdev->dev,
9403 "Failed to destroy the HMC resources: %d\n",
9404 ret_code);
9405 }
41c445ff
JB		 9406
9407 /* shutdown the adminq */
41c445ff
JB		 9408 ret_code = i40e_shutdown_adminq(&pf->hw);
9409 if (ret_code)
9410 dev_warn(&pdev->dev,
9411 "Failed to destroy the Admin Queue resources: %d\n",
9412 ret_code);
9413
9414 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
9415 i40e_clear_interrupt_scheme(pf);
505682cd 9416 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9417 if (pf->vsi[i]) {
9418 i40e_vsi_clear_rings(pf->vsi[i]);
9419 i40e_vsi_clear(pf->vsi[i]);
9420 pf->vsi[i] = NULL;
9421 }
9422 }
9423
9424 for (i = 0; i < I40E_MAX_VEB; i++) {
9425 kfree(pf->veb[i]);
9426 pf->veb[i] = NULL;
9427 }
9428
9429 kfree(pf->qp_pile);
9430 kfree(pf->irq_pile);
41c445ff
JB		 9431 kfree(pf->vsi);
9432
41c445ff
JB		 9433 iounmap(pf->hw.hw_addr);
9434 kfree(pf);
9435 pci_release_selected_regions(pdev,
9436 pci_select_bars(pdev, IORESOURCE_MEM));
9437
9438 pci_disable_pcie_error_reporting(pdev);
9439 pci_disable_device(pdev);
9440}
9441
9442/**
9443 * i40e_pci_error_detected - warning that something funky happened in PCI land
9444 * @pdev: PCI device information struct
9445 *
9446 * Called to warn that something happened and the error handling steps
9447 * are in progress. Allows the driver to quiesce things, be ready for
9448 * remediation.
9449 **/
9450static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
9451 enum pci_channel_state error)
9452{
9453 struct i40e_pf *pf = pci_get_drvdata(pdev);
9454
9455 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9456
9457 /* shutdown all operations */
9007bccd
SN		 9458 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9459 rtnl_lock();
9460 i40e_prep_for_reset(pf);
9461 rtnl_unlock();
9462 }
41c445ff
JB		 9463
9464 /* Request a slot reset */
9465 return PCI_ERS_RESULT_NEED_RESET;
9466}
9467
9468/**
9469 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9470 * @pdev: PCI device information struct
9471 *
9472 * Called to find if the driver can work with the device now that
9473 * the pci slot has been reset. If a basic connection seems good
9474 * (registers are readable and have sane content) then return a
9475 * happy little PCI_ERS_RESULT_xxx.
9476 **/
9477static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9478{
9479 struct i40e_pf *pf = pci_get_drvdata(pdev);
9480 pci_ers_result_t result;
9481 int err;
9482 u32 reg;
9483
9484 dev_info(&pdev->dev, "%s\n", __func__);
9485 if (pci_enable_device_mem(pdev)) {
9486 dev_info(&pdev->dev,
9487 "Cannot re-enable PCI device after reset.\n");
9488 result = PCI_ERS_RESULT_DISCONNECT;
9489 } else {
9490 pci_set_master(pdev);
9491 pci_restore_state(pdev);
9492 pci_save_state(pdev);
9493 pci_wake_from_d3(pdev, false);
9494
9495 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9496 if (reg == 0)
9497 result = PCI_ERS_RESULT_RECOVERED;
9498 else
9499 result = PCI_ERS_RESULT_DISCONNECT;
9500 }
9501
9502 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9503 if (err) {
9504 dev_info(&pdev->dev,
9505 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9506 err);
9507 /* non-fatal, continue */
9508 }
9509
9510 return result;
9511}
9512
9513/**
9514 * i40e_pci_error_resume - restart operations after PCI error recovery
9515 * @pdev: PCI device information struct
9516 *
9517 * Called to allow the driver to bring things back up after PCI error
9518 * and/or reset recovery has finished.
9519 **/
9520static void i40e_pci_error_resume(struct pci_dev *pdev)
9521{
9522 struct i40e_pf *pf = pci_get_drvdata(pdev);
9523
9524 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 9525 if (test_bit(__I40E_SUSPENDED, &pf->state))
9526 return;
9527
9528 rtnl_lock();
41c445ff 9529 i40e_handle_reset_warning(pf);
9007bccd
SN		 9530 rtnl_lock();
9531}
9532
9533/**
9534 * i40e_shutdown - PCI callback for shutting down
9535 * @pdev: PCI device information struct
9536 **/
9537static void i40e_shutdown(struct pci_dev *pdev)
9538{
9539 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9540 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9541
9542 set_bit(__I40E_SUSPENDED, &pf->state);
9543 set_bit(__I40E_DOWN, &pf->state);
9544 rtnl_lock();
9545 i40e_prep_for_reset(pf);
9546 rtnl_unlock();
9547
8e2773ae
SN		 9548 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9549 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9550
9007bccd 9551 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 9552 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9553 pci_set_power_state(pdev, PCI_D3hot);
9554 }
9555}
9556
9557#ifdef CONFIG_PM
9558/**
9559 * i40e_suspend - PCI callback for moving to D3
9560 * @pdev: PCI device information struct
9561 **/
9562static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
9563{
9564 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9565 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9566
9567 set_bit(__I40E_SUSPENDED, &pf->state);
9568 set_bit(__I40E_DOWN, &pf->state);
9569 rtnl_lock();
9570 i40e_prep_for_reset(pf);
9571 rtnl_unlock();
9572
8e2773ae
SN		 9573 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9574 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9575
9576 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9577 pci_set_power_state(pdev, PCI_D3hot);
9578
9579 return 0;
41c445ff
JB		 9580}
9581
9007bccd
SN		 9582/**
9583 * i40e_resume - PCI callback for waking up from D3
9584 * @pdev: PCI device information struct
9585 **/
9586static int i40e_resume(struct pci_dev *pdev)
9587{
9588 struct i40e_pf *pf = pci_get_drvdata(pdev);
9589 u32 err;
9590
9591 pci_set_power_state(pdev, PCI_D0);
9592 pci_restore_state(pdev);
9593 /* pci_restore_state() clears dev->state_saves, so
9594 * call pci_save_state() again to restore it.
9595 */
9596 pci_save_state(pdev);
9597
9598 err = pci_enable_device_mem(pdev);
9599 if (err) {
9600 dev_err(&pdev->dev,
9601 "%s: Cannot enable PCI device from suspend\n",
9602 __func__);
9603 return err;
9604 }
9605 pci_set_master(pdev);
9606
9607 /* no wakeup events while running */
9608 pci_wake_from_d3(pdev, false);
9609
9610 /* handling the reset will rebuild the device state */
9611 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
9612 clear_bit(__I40E_DOWN, &pf->state);
9613 rtnl_lock();
9614 i40e_reset_and_rebuild(pf, false);
9615 rtnl_unlock();
9616 }
9617
9618 return 0;
9619}
9620
9621#endif
41c445ff
JB		 9622static const struct pci_error_handlers i40e_err_handler = {
9623 .error_detected = i40e_pci_error_detected,
9624 .slot_reset = i40e_pci_error_slot_reset,
9625 .resume = i40e_pci_error_resume,
9626};
9627
9628static struct pci_driver i40e_driver = {
9629 .name = i40e_driver_name,
9630 .id_table = i40e_pci_tbl,
9631 .probe = i40e_probe,
9632 .remove = i40e_remove,
9007bccd
SN		 9633#ifdef CONFIG_PM
9634 .suspend = i40e_suspend,
9635 .resume = i40e_resume,
9636#endif
9637 .shutdown = i40e_shutdown,
41c445ff
JB		 9638 .err_handler = &i40e_err_handler,
9639 .sriov_configure = i40e_pci_sriov_configure,
9640};
9641
9642/**
9643 * i40e_init_module - Driver registration routine
9644 *
9645 * i40e_init_module is the first routine called when the driver is
9646 * loaded. All it does is register with the PCI subsystem.
9647 **/
9648static int __init i40e_init_module(void)
9649{
9650 pr_info("%s: %s - version %s\n", i40e_driver_name,
9651 i40e_driver_string, i40e_driver_version_str);
9652 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
9653 i40e_dbg_init();
9654 return pci_register_driver(&i40e_driver);
9655}
9656module_init(i40e_init_module);
9657
9658/**
9659 * i40e_exit_module - Driver exit cleanup routine
9660 *
9661 * i40e_exit_module is called just before the driver is removed
9662 * from memory.
9663 **/
9664static void __exit i40e_exit_module(void)
9665{
9666 pci_unregister_driver(&i40e_driver);
9667 i40e_dbg_exit();
9668}
9669module_exit(i40e_exit_module);
Linux kernel - Deliverables
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