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ax25: Stop using magic neighbour cache operations.
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
a36fdd8e 41#define DRV_VERSION_MINOR 2
5b8eb176 42#define DRV_VERSION_BUILD 9
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
38e00438
VD		 273#ifdef I40E_FCOE
274void i40e_tx_timeout(struct net_device *netdev)
275#else
41c445ff 276static void i40e_tx_timeout(struct net_device *netdev)
38e00438 277#endif
41c445ff
JB		 278{
279 struct i40e_netdev_priv *np = netdev_priv(netdev);
280 struct i40e_vsi *vsi = np->vsi;
281 struct i40e_pf *pf = vsi->back;
282
283 pf->tx_timeout_count++;
284
285 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 286 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 287 pf->tx_timeout_last_recovery = jiffies;
288 netdev_info(netdev, "tx_timeout recovery level %d\n",
289 pf->tx_timeout_recovery_level);
290
291 switch (pf->tx_timeout_recovery_level) {
292 case 0:
293 /* disable and re-enable queues for the VSI */
294 if (in_interrupt()) {
295 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
296 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
297 } else {
298 i40e_vsi_reinit_locked(vsi);
299 }
300 break;
301 case 1:
302 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
303 break;
304 case 2:
305 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
306 break;
307 case 3:
308 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
309 break;
310 default:
311 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 312 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
313 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 314 break;
315 }
316 i40e_service_event_schedule(pf);
317 pf->tx_timeout_recovery_level++;
318}
319
320/**
321 * i40e_release_rx_desc - Store the new tail and head values
322 * @rx_ring: ring to bump
323 * @val: new head index
324 **/
325static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
326{
327 rx_ring->next_to_use = val;
328
329 /* Force memory writes to complete before letting h/w
330 * know there are new descriptors to fetch. (Only
331 * applicable for weak-ordered memory model archs,
332 * such as IA-64).
333 */
334 wmb();
335 writel(val, rx_ring->tail);
336}
337
338/**
339 * i40e_get_vsi_stats_struct - Get System Network Statistics
340 * @vsi: the VSI we care about
341 *
342 * Returns the address of the device statistics structure.
343 * The statistics are actually updated from the service task.
344 **/
345struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
346{
347 return &vsi->net_stats;
348}
349
350/**
351 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
352 * @netdev: network interface device structure
353 *
354 * Returns the address of the device statistics structure.
355 * The statistics are actually updated from the service task.
356 **/
38e00438
VD		 357#ifdef I40E_FCOE
358struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
359 struct net_device *netdev,
360 struct rtnl_link_stats64 *stats)
361#else
41c445ff
JB		 362static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
363 struct net_device *netdev,
980e9b11 364 struct rtnl_link_stats64 *stats)
38e00438 365#endif
41c445ff
JB		 366{
367 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 368 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 369 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 370 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
371 int i;
372
bc7d338f
ASJ		 373 if (test_bit(__I40E_DOWN, &vsi->state))
374 return stats;
375
3c325ced
JB		 376 if (!vsi->tx_rings)
377 return stats;
378
980e9b11
AD		 379 rcu_read_lock();
380 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 381 u64 bytes, packets;
382 unsigned int start;
383
384 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
385 if (!tx_ring)
386 continue;
387
388 do {
57a7744e 389 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 390 packets = tx_ring->stats.packets;
391 bytes = tx_ring->stats.bytes;
57a7744e 392 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 393
394 stats->tx_packets += packets;
395 stats->tx_bytes += bytes;
396 rx_ring = &tx_ring[1];
397
398 do {
57a7744e 399 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 400 packets = rx_ring->stats.packets;
401 bytes = rx_ring->stats.bytes;
57a7744e 402 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 403
980e9b11
AD		 404 stats->rx_packets += packets;
405 stats->rx_bytes += bytes;
406 }
407 rcu_read_unlock();
408
a5282f44 409 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 410 stats->multicast = vsi_stats->multicast;
411 stats->tx_errors = vsi_stats->tx_errors;
412 stats->tx_dropped = vsi_stats->tx_dropped;
413 stats->rx_errors = vsi_stats->rx_errors;
414 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
415 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 416
980e9b11 417 return stats;
41c445ff
JB		 418}
419
420/**
421 * i40e_vsi_reset_stats - Resets all stats of the given vsi
422 * @vsi: the VSI to have its stats reset
423 **/
424void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
425{
426 struct rtnl_link_stats64 *ns;
427 int i;
428
429 if (!vsi)
430 return;
431
432 ns = i40e_get_vsi_stats_struct(vsi);
433 memset(ns, 0, sizeof(*ns));
434 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
435 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
436 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 437 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 438 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 439 memset(&vsi->rx_rings[i]->stats, 0 ,
440 sizeof(vsi->rx_rings[i]->stats));
441 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
442 sizeof(vsi->rx_rings[i]->rx_stats));
443 memset(&vsi->tx_rings[i]->stats, 0 ,
444 sizeof(vsi->tx_rings[i]->stats));
445 memset(&vsi->tx_rings[i]->tx_stats, 0,
446 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 447 }
8e9dca53 448 }
41c445ff
JB		 449 vsi->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_pf_reset_stats - Reset all of the stats for the given pf
454 * @pf: the PF to be reset
455 **/
456void i40e_pf_reset_stats(struct i40e_pf *pf)
457{
e91fdf76
SN		 458 int i;
459
41c445ff
JB		 460 memset(&pf->stats, 0, sizeof(pf->stats));
461 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
462 pf->stat_offsets_loaded = false;
e91fdf76
SN		 463
464 for (i = 0; i < I40E_MAX_VEB; i++) {
465 if (pf->veb[i]) {
466 memset(&pf->veb[i]->stats, 0,
467 sizeof(pf->veb[i]->stats));
468 memset(&pf->veb[i]->stats_offsets, 0,
469 sizeof(pf->veb[i]->stats_offsets));
470 pf->veb[i]->stat_offsets_loaded = false;
471 }
472 }
41c445ff
JB		 473}
474
475/**
476 * i40e_stat_update48 - read and update a 48 bit stat from the chip
477 * @hw: ptr to the hardware info
478 * @hireg: the high 32 bit reg to read
479 * @loreg: the low 32 bit reg to read
480 * @offset_loaded: has the initial offset been loaded yet
481 * @offset: ptr to current offset value
482 * @stat: ptr to the stat
483 *
484 * Since the device stats are not reset at PFReset, they likely will not
485 * be zeroed when the driver starts. We'll save the first values read
486 * and use them as offsets to be subtracted from the raw values in order
487 * to report stats that count from zero. In the process, we also manage
488 * the potential roll-over.
489 **/
490static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
491 bool offset_loaded, u64 *offset, u64 *stat)
492{
493 u64 new_data;
494
ab60085e 495 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 496 new_data = rd32(hw, loreg);
497 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
498 } else {
499 new_data = rd64(hw, loreg);
500 }
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = new_data - *offset;
505 else
506 *stat = (new_data + ((u64)1 << 48)) - *offset;
507 *stat &= 0xFFFFFFFFFFFFULL;
508}
509
510/**
511 * i40e_stat_update32 - read and update a 32 bit stat from the chip
512 * @hw: ptr to the hardware info
513 * @reg: the hw reg to read
514 * @offset_loaded: has the initial offset been loaded yet
515 * @offset: ptr to current offset value
516 * @stat: ptr to the stat
517 **/
518static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
519 bool offset_loaded, u64 *offset, u64 *stat)
520{
521 u32 new_data;
522
523 new_data = rd32(hw, reg);
524 if (!offset_loaded)
525 *offset = new_data;
526 if (likely(new_data >= *offset))
527 *stat = (u32)(new_data - *offset);
528 else
529 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
530}
531
532/**
533 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
534 * @vsi: the VSI to be updated
535 **/
536void i40e_update_eth_stats(struct i40e_vsi *vsi)
537{
538 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
539 struct i40e_pf *pf = vsi->back;
540 struct i40e_hw *hw = &pf->hw;
541 struct i40e_eth_stats *oes;
542 struct i40e_eth_stats *es; /* device's eth stats */
543
544 es = &vsi->eth_stats;
545 oes = &vsi->eth_stats_offsets;
546
547 /* Gather up the stats that the hw collects */
548 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_errors, &es->tx_errors);
551 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 554 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
555 vsi->stat_offsets_loaded,
556 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
557 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 560
561 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
562 I40E_GLV_GORCL(stat_idx),
563 vsi->stat_offsets_loaded,
564 &oes->rx_bytes, &es->rx_bytes);
565 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
566 I40E_GLV_UPRCL(stat_idx),
567 vsi->stat_offsets_loaded,
568 &oes->rx_unicast, &es->rx_unicast);
569 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
570 I40E_GLV_MPRCL(stat_idx),
571 vsi->stat_offsets_loaded,
572 &oes->rx_multicast, &es->rx_multicast);
573 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
574 I40E_GLV_BPRCL(stat_idx),
575 vsi->stat_offsets_loaded,
576 &oes->rx_broadcast, &es->rx_broadcast);
577
578 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
579 I40E_GLV_GOTCL(stat_idx),
580 vsi->stat_offsets_loaded,
581 &oes->tx_bytes, &es->tx_bytes);
582 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
583 I40E_GLV_UPTCL(stat_idx),
584 vsi->stat_offsets_loaded,
585 &oes->tx_unicast, &es->tx_unicast);
586 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
587 I40E_GLV_MPTCL(stat_idx),
588 vsi->stat_offsets_loaded,
589 &oes->tx_multicast, &es->tx_multicast);
590 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
591 I40E_GLV_BPTCL(stat_idx),
592 vsi->stat_offsets_loaded,
593 &oes->tx_broadcast, &es->tx_broadcast);
594 vsi->stat_offsets_loaded = true;
595}
596
597/**
598 * i40e_update_veb_stats - Update Switch component statistics
599 * @veb: the VEB being updated
600 **/
601static void i40e_update_veb_stats(struct i40e_veb *veb)
602{
603 struct i40e_pf *pf = veb->pf;
604 struct i40e_hw *hw = &pf->hw;
605 struct i40e_eth_stats *oes;
606 struct i40e_eth_stats *es; /* device's eth stats */
607 int idx = 0;
608
609 idx = veb->stats_idx;
610 es = &veb->stats;
611 oes = &veb->stats_offsets;
612
613 /* Gather up the stats that the hw collects */
614 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 617 if (hw->revision_id > 0)
618 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
619 veb->stat_offsets_loaded,
620 &oes->rx_unknown_protocol,
621 &es->rx_unknown_protocol);
41c445ff
JB		 622 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
623 veb->stat_offsets_loaded,
624 &oes->rx_bytes, &es->rx_bytes);
625 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
626 veb->stat_offsets_loaded,
627 &oes->rx_unicast, &es->rx_unicast);
628 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
629 veb->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
632 veb->stat_offsets_loaded,
633 &oes->rx_broadcast, &es->rx_broadcast);
634
635 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
636 veb->stat_offsets_loaded,
637 &oes->tx_bytes, &es->tx_bytes);
638 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
639 veb->stat_offsets_loaded,
640 &oes->tx_unicast, &es->tx_unicast);
641 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
642 veb->stat_offsets_loaded,
643 &oes->tx_multicast, &es->tx_multicast);
644 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
645 veb->stat_offsets_loaded,
646 &oes->tx_broadcast, &es->tx_broadcast);
647 veb->stat_offsets_loaded = true;
648}
649
38e00438
VD		 650#ifdef I40E_FCOE
651/**
652 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
653 * @vsi: the VSI that is capable of doing FCoE
654 **/
655static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
656{
657 struct i40e_pf *pf = vsi->back;
658 struct i40e_hw *hw = &pf->hw;
659 struct i40e_fcoe_stats *ofs;
660 struct i40e_fcoe_stats *fs; /* device's eth stats */
661 int idx;
662
663 if (vsi->type != I40E_VSI_FCOE)
664 return;
665
666 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
667 fs = &vsi->fcoe_stats;
668 ofs = &vsi->fcoe_stats_offsets;
669
670 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
671 vsi->fcoe_stat_offsets_loaded,
672 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
673 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
674 vsi->fcoe_stat_offsets_loaded,
675 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
676 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
677 vsi->fcoe_stat_offsets_loaded,
678 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
679 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
680 vsi->fcoe_stat_offsets_loaded,
681 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
682 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
683 vsi->fcoe_stat_offsets_loaded,
684 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
685 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
686 vsi->fcoe_stat_offsets_loaded,
687 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
688 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
689 vsi->fcoe_stat_offsets_loaded,
690 &ofs->fcoe_last_error, &fs->fcoe_last_error);
691 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
692 vsi->fcoe_stat_offsets_loaded,
693 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
694
695 vsi->fcoe_stat_offsets_loaded = true;
696}
697
698#endif
41c445ff
JB		 699/**
700 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
701 * @pf: the corresponding PF
702 *
703 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
704 **/
705static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
706{
707 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
708 struct i40e_hw_port_stats *nsd = &pf->stats;
709 struct i40e_hw *hw = &pf->hw;
710 u64 xoff = 0;
711 u16 i, v;
712
713 if ((hw->fc.current_mode != I40E_FC_FULL) &&
714 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
715 return;
716
717 xoff = nsd->link_xoff_rx;
718 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
719 pf->stat_offsets_loaded,
720 &osd->link_xoff_rx, &nsd->link_xoff_rx);
721
722 /* No new LFC xoff rx */
723 if (!(nsd->link_xoff_rx - xoff))
724 return;
725
726 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 727 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 728 struct i40e_vsi *vsi = pf->vsi[v];
729
ddfda80f 730 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 731 continue;
732
733 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 734 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 735 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
736 }
737 }
738}
739
740/**
741 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
742 * @pf: the corresponding PF
743 *
744 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
745 **/
746static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
747{
748 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
749 struct i40e_hw_port_stats *nsd = &pf->stats;
750 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
751 struct i40e_dcbx_config *dcb_cfg;
752 struct i40e_hw *hw = &pf->hw;
753 u16 i, v;
754 u8 tc;
755
756 dcb_cfg = &hw->local_dcbx_config;
757
758 /* See if DCB enabled with PFC TC */
759 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
760 !(dcb_cfg->pfc.pfcenable)) {
761 i40e_update_link_xoff_rx(pf);
762 return;
763 }
764
765 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
766 u64 prio_xoff = nsd->priority_xoff_rx[i];
767 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
768 pf->stat_offsets_loaded,
769 &osd->priority_xoff_rx[i],
770 &nsd->priority_xoff_rx[i]);
771
772 /* No new PFC xoff rx */
773 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
774 continue;
775 /* Get the TC for given priority */
776 tc = dcb_cfg->etscfg.prioritytable[i];
777 xoff[tc] = true;
778 }
779
780 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 781 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 782 struct i40e_vsi *vsi = pf->vsi[v];
783
ddfda80f 784 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 785 continue;
786
787 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 788 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 789
790 tc = ring->dcb_tc;
791 if (xoff[tc])
792 clear_bit(__I40E_HANG_CHECK_ARMED,
793 &ring->state);
794 }
795 }
796}
797
798/**
7812fddc 799 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 800 * @vsi: the VSI to be updated
801 *
802 * There are a few instances where we store the same stat in a
803 * couple of different structs. This is partly because we have
804 * the netdev stats that need to be filled out, which is slightly
805 * different from the "eth_stats" defined by the chip and used in
7812fddc 806 * VF communications. We sort it out here.
41c445ff 807 **/
7812fddc 808static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 809{
810 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 811 struct rtnl_link_stats64 *ons;
812 struct rtnl_link_stats64 *ns; /* netdev stats */
813 struct i40e_eth_stats *oes;
814 struct i40e_eth_stats *es; /* device's eth stats */
815 u32 tx_restart, tx_busy;
bf00b376 816 struct i40e_ring *p;
41c445ff 817 u32 rx_page, rx_buf;
bf00b376
AA		 818 u64 bytes, packets;
819 unsigned int start;
41c445ff
JB		 820 u64 rx_p, rx_b;
821 u64 tx_p, tx_b;
41c445ff
JB		 822 u16 q;
823
824 if (test_bit(__I40E_DOWN, &vsi->state) ||
825 test_bit(__I40E_CONFIG_BUSY, &pf->state))
826 return;
827
828 ns = i40e_get_vsi_stats_struct(vsi);
829 ons = &vsi->net_stats_offsets;
830 es = &vsi->eth_stats;
831 oes = &vsi->eth_stats_offsets;
832
833 /* Gather up the netdev and vsi stats that the driver collects
834 * on the fly during packet processing
835 */
836 rx_b = rx_p = 0;
837 tx_b = tx_p = 0;
838 tx_restart = tx_busy = 0;
839 rx_page = 0;
840 rx_buf = 0;
980e9b11 841 rcu_read_lock();
41c445ff 842 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc
SN		 898/**
899 * i40e_update_pf_stats - Update the pf statistics counters.
900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
532d283d
SN		 922 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
923 I40E_GLPRT_UPRCL(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_unicast,
926 &nsd->eth.rx_unicast);
7812fddc
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
928 I40E_GLPRT_MPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_multicast,
931 &nsd->eth.rx_multicast);
532d283d
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
933 I40E_GLPRT_BPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_broadcast,
936 &nsd->eth.rx_broadcast);
937 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
938 I40E_GLPRT_UPTCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.tx_unicast,
941 &nsd->eth.tx_unicast);
942 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
943 I40E_GLPRT_MPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_multicast,
946 &nsd->eth.tx_multicast);
947 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
948 I40E_GLPRT_BPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_broadcast,
951 &nsd->eth.tx_broadcast);
41c445ff 952
7812fddc
SN		 953 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_dropped_link_down,
956 &nsd->tx_dropped_link_down);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->crc_errors, &nsd->crc_errors);
41c445ff 961
7812fddc
SN		 962 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 965
7812fddc
SN		 966 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->mac_local_faults,
969 &nsd->mac_local_faults);
970 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->mac_remote_faults,
973 &nsd->mac_remote_faults);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->rx_length_errors,
978 &nsd->rx_length_errors);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->link_xon_rx, &nsd->link_xon_rx);
983 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->link_xon_tx, &nsd->link_xon_tx);
986 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
987 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 990
7812fddc
SN		 991 for (i = 0; i < 8; i++) {
992 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 993 pf->stat_offsets_loaded,
7812fddc
SN		 994 &osd->priority_xon_rx[i],
995 &nsd->priority_xon_rx[i]);
996 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 997 pf->stat_offsets_loaded,
7812fddc
SN		 998 &osd->priority_xon_tx[i],
999 &nsd->priority_xon_tx[i]);
1000 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1001 pf->stat_offsets_loaded,
7812fddc
SN		 1002 &osd->priority_xoff_tx[i],
1003 &nsd->priority_xoff_tx[i]);
1004 i40e_stat_update32(hw,
1005 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xon_2_xoff[i],
1008 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1009 }
1010
7812fddc
SN		 1011 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1012 I40E_GLPRT_PRC64L(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->rx_size_64, &nsd->rx_size_64);
1015 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1016 I40E_GLPRT_PRC127L(hw->port),
1017 pf->stat_offsets_loaded,
1018 &osd->rx_size_127, &nsd->rx_size_127);
1019 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1020 I40E_GLPRT_PRC255L(hw->port),
1021 pf->stat_offsets_loaded,
1022 &osd->rx_size_255, &nsd->rx_size_255);
1023 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1024 I40E_GLPRT_PRC511L(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->rx_size_511, &nsd->rx_size_511);
1027 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1028 I40E_GLPRT_PRC1023L(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->rx_size_1023, &nsd->rx_size_1023);
1031 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1032 I40E_GLPRT_PRC1522L(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->rx_size_1522, &nsd->rx_size_1522);
1035 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1036 I40E_GLPRT_PRC9522L(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->rx_size_big, &nsd->rx_size_big);
1039
1040 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1041 I40E_GLPRT_PTC64L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->tx_size_64, &nsd->tx_size_64);
1044 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1045 I40E_GLPRT_PTC127L(hw->port),
1046 pf->stat_offsets_loaded,
1047 &osd->tx_size_127, &nsd->tx_size_127);
1048 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1049 I40E_GLPRT_PTC255L(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->tx_size_255, &nsd->tx_size_255);
1052 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1053 I40E_GLPRT_PTC511L(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->tx_size_511, &nsd->tx_size_511);
1056 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1057 I40E_GLPRT_PTC1023L(hw->port),
1058 pf->stat_offsets_loaded,
1059 &osd->tx_size_1023, &nsd->tx_size_1023);
1060 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1061 I40E_GLPRT_PTC1522L(hw->port),
1062 pf->stat_offsets_loaded,
1063 &osd->tx_size_1522, &nsd->tx_size_1522);
1064 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1065 I40E_GLPRT_PTC9522L(hw->port),
1066 pf->stat_offsets_loaded,
1067 &osd->tx_size_big, &nsd->tx_size_big);
1068
1069 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1070 pf->stat_offsets_loaded,
1071 &osd->rx_undersize, &nsd->rx_undersize);
1072 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->rx_fragments, &nsd->rx_fragments);
1075 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1076 pf->stat_offsets_loaded,
1077 &osd->rx_oversize, &nsd->rx_oversize);
1078 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_jabber, &nsd->rx_jabber);
1081
433c47de
ASJ		 1082 /* FDIR stats */
1083 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1084 pf->stat_offsets_loaded,
1085 &osd->fd_atr_match, &nsd->fd_atr_match);
1086 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1087 pf->stat_offsets_loaded,
1088 &osd->fd_sb_match, &nsd->fd_sb_match);
1089
7812fddc
SN		 1090 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1091 nsd->tx_lpi_status =
1092 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1093 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1094 nsd->rx_lpi_status =
1095 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1096 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1097 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1098 pf->stat_offsets_loaded,
1099 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1100 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1101 pf->stat_offsets_loaded,
1102 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1103
41c445ff
JB		 1104 pf->stat_offsets_loaded = true;
1105}
1106
7812fddc
SN		 1107/**
1108 * i40e_update_stats - Update the various statistics counters.
1109 * @vsi: the VSI to be updated
1110 *
1111 * Update the various stats for this VSI and its related entities.
1112 **/
1113void i40e_update_stats(struct i40e_vsi *vsi)
1114{
1115 struct i40e_pf *pf = vsi->back;
1116
1117 if (vsi == pf->vsi[pf->lan_vsi])
1118 i40e_update_pf_stats(pf);
1119
1120 i40e_update_vsi_stats(vsi);
38e00438
VD		 1121#ifdef I40E_FCOE
1122 i40e_update_fcoe_stats(vsi);
1123#endif
7812fddc
SN		 1124}
1125
41c445ff
JB		 1126/**
1127 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1128 * @vsi: the VSI to be searched
1129 * @macaddr: the MAC address
1130 * @vlan: the vlan
1131 * @is_vf: make sure its a vf filter, else doesn't matter
1132 * @is_netdev: make sure its a netdev filter, else doesn't matter
1133 *
1134 * Returns ptr to the filter object or NULL
1135 **/
1136static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1137 u8 *macaddr, s16 vlan,
1138 bool is_vf, bool is_netdev)
1139{
1140 struct i40e_mac_filter *f;
1141
1142 if (!vsi || !macaddr)
1143 return NULL;
1144
1145 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1146 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1147 (vlan == f->vlan) &&
1148 (!is_vf || f->is_vf) &&
1149 (!is_netdev || f->is_netdev))
1150 return f;
1151 }
1152 return NULL;
1153}
1154
1155/**
1156 * i40e_find_mac - Find a mac addr in the macvlan filters list
1157 * @vsi: the VSI to be searched
1158 * @macaddr: the MAC address we are searching for
1159 * @is_vf: make sure its a vf filter, else doesn't matter
1160 * @is_netdev: make sure its a netdev filter, else doesn't matter
1161 *
1162 * Returns the first filter with the provided MAC address or NULL if
1163 * MAC address was not found
1164 **/
1165struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1166 bool is_vf, bool is_netdev)
1167{
1168 struct i40e_mac_filter *f;
1169
1170 if (!vsi || !macaddr)
1171 return NULL;
1172
1173 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1174 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1175 (!is_vf || f->is_vf) &&
1176 (!is_netdev || f->is_netdev))
1177 return f;
1178 }
1179 return NULL;
1180}
1181
1182/**
1183 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1184 * @vsi: the VSI to be searched
1185 *
1186 * Returns true if VSI is in vlan mode or false otherwise
1187 **/
1188bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1189{
1190 struct i40e_mac_filter *f;
1191
1192 /* Only -1 for all the filters denotes not in vlan mode
1193 * so we have to go through all the list in order to make sure
1194 */
1195 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1196 if (f->vlan >= 0)
1197 return true;
1198 }
1199
1200 return false;
1201}
1202
1203/**
1204 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1205 * @vsi: the VSI to be searched
1206 * @macaddr: the mac address to be filtered
1207 * @is_vf: true if it is a vf
1208 * @is_netdev: true if it is a netdev
1209 *
1210 * Goes through all the macvlan filters and adds a
1211 * macvlan filter for each unique vlan that already exists
1212 *
1213 * Returns first filter found on success, else NULL
1214 **/
1215struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1216 bool is_vf, bool is_netdev)
1217{
1218 struct i40e_mac_filter *f;
1219
1220 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1221 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1222 is_vf, is_netdev)) {
1223 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1224 is_vf, is_netdev))
41c445ff
JB		 1225 return NULL;
1226 }
1227 }
1228
1229 return list_first_entry_or_null(&vsi->mac_filter_list,
1230 struct i40e_mac_filter, list);
1231}
1232
8c27d42e
GR		 1233/**
1234 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1235 * @vsi: the PF Main VSI - inappropriate for any other VSI
1236 * @macaddr: the MAC address
30650cc5
SN		 1237 *
1238 * Some older firmware configurations set up a default promiscuous VLAN
1239 * filter that needs to be removed.
8c27d42e 1240 **/
30650cc5 1241static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1242{
1243 struct i40e_aqc_remove_macvlan_element_data element;
1244 struct i40e_pf *pf = vsi->back;
1245 i40e_status aq_ret;
1246
1247 /* Only appropriate for the PF main VSI */
1248 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1249 return -EINVAL;
8c27d42e 1250
30650cc5 1251 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1252 ether_addr_copy(element.mac_addr, macaddr);
1253 element.vlan_tag = 0;
1254 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1255 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1256 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1257 if (aq_ret)
30650cc5
SN		 1258 return -ENOENT;
1259
1260 return 0;
8c27d42e
GR		 1261}
1262
41c445ff
JB		 1263/**
1264 * i40e_add_filter - Add a mac/vlan filter to the VSI
1265 * @vsi: the VSI to be searched
1266 * @macaddr: the MAC address
1267 * @vlan: the vlan
1268 * @is_vf: make sure its a vf filter, else doesn't matter
1269 * @is_netdev: make sure its a netdev filter, else doesn't matter
1270 *
1271 * Returns ptr to the filter object or NULL when no memory available.
1272 **/
1273struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1274 u8 *macaddr, s16 vlan,
1275 bool is_vf, bool is_netdev)
1276{
1277 struct i40e_mac_filter *f;
1278
1279 if (!vsi || !macaddr)
1280 return NULL;
1281
1282 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1283 if (!f) {
1284 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1285 if (!f)
1286 goto add_filter_out;
1287
9a173901 1288 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1289 f->vlan = vlan;
1290 f->changed = true;
1291
1292 INIT_LIST_HEAD(&f->list);
1293 list_add(&f->list, &vsi->mac_filter_list);
1294 }
1295
1296 /* increment counter and add a new flag if needed */
1297 if (is_vf) {
1298 if (!f->is_vf) {
1299 f->is_vf = true;
1300 f->counter++;
1301 }
1302 } else if (is_netdev) {
1303 if (!f->is_netdev) {
1304 f->is_netdev = true;
1305 f->counter++;
1306 }
1307 } else {
1308 f->counter++;
1309 }
1310
1311 /* changed tells sync_filters_subtask to
1312 * push the filter down to the firmware
1313 */
1314 if (f->changed) {
1315 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1316 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1317 }
1318
1319add_filter_out:
1320 return f;
1321}
1322
1323/**
1324 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1325 * @vsi: the VSI to be searched
1326 * @macaddr: the MAC address
1327 * @vlan: the vlan
1328 * @is_vf: make sure it's a vf filter, else doesn't matter
1329 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1330 **/
1331void i40e_del_filter(struct i40e_vsi *vsi,
1332 u8 *macaddr, s16 vlan,
1333 bool is_vf, bool is_netdev)
1334{
1335 struct i40e_mac_filter *f;
1336
1337 if (!vsi || !macaddr)
1338 return;
1339
1340 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1341 if (!f || f->counter == 0)
1342 return;
1343
1344 if (is_vf) {
1345 if (f->is_vf) {
1346 f->is_vf = false;
1347 f->counter--;
1348 }
1349 } else if (is_netdev) {
1350 if (f->is_netdev) {
1351 f->is_netdev = false;
1352 f->counter--;
1353 }
1354 } else {
1355 /* make sure we don't remove a filter in use by vf or netdev */
1356 int min_f = 0;
1357 min_f += (f->is_vf ? 1 : 0);
1358 min_f += (f->is_netdev ? 1 : 0);
1359
1360 if (f->counter > min_f)
1361 f->counter--;
1362 }
1363
1364 /* counter == 0 tells sync_filters_subtask to
1365 * remove the filter from the firmware's list
1366 */
1367 if (f->counter == 0) {
1368 f->changed = true;
1369 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1370 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1371 }
1372}
1373
1374/**
1375 * i40e_set_mac - NDO callback to set mac address
1376 * @netdev: network interface device structure
1377 * @p: pointer to an address structure
1378 *
1379 * Returns 0 on success, negative on failure
1380 **/
38e00438
VD		 1381#ifdef I40E_FCOE
1382int i40e_set_mac(struct net_device *netdev, void *p)
1383#else
41c445ff 1384static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1385#endif
41c445ff
JB		 1386{
1387 struct i40e_netdev_priv *np = netdev_priv(netdev);
1388 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1389 struct i40e_pf *pf = vsi->back;
1390 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1391 struct sockaddr *addr = p;
1392 struct i40e_mac_filter *f;
1393
1394 if (!is_valid_ether_addr(addr->sa_data))
1395 return -EADDRNOTAVAIL;
1396
30650cc5
SN		 1397 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1398 netdev_info(netdev, "already using mac address %pM\n",
1399 addr->sa_data);
1400 return 0;
1401 }
41c445ff 1402
80f6428f
ASJ		 1403 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1404 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1405 return -EADDRNOTAVAIL;
1406
30650cc5
SN		 1407 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1408 netdev_info(netdev, "returning to hw mac address %pM\n",
1409 hw->mac.addr);
1410 else
1411 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1412
41c445ff
JB		 1413 if (vsi->type == I40E_VSI_MAIN) {
1414 i40e_status ret;
1415 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1416 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1417 addr->sa_data, NULL);
1418 if (ret) {
1419 netdev_info(netdev,
1420 "Addr change for Main VSI failed: %d\n",
1421 ret);
1422 return -EADDRNOTAVAIL;
1423 }
41c445ff
JB		 1424 }
1425
30650cc5
SN		 1426 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1427 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1428
30650cc5
SN		 1429 memset(&element, 0, sizeof(element));
1430 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1431 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1432 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1433 } else {
6c8ad1ba
SN		 1434 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1435 false, false);
6c8ad1ba 1436 }
41c445ff 1437
30650cc5
SN		 1438 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1439 struct i40e_aqc_add_macvlan_element_data element;
1440
1441 memset(&element, 0, sizeof(element));
1442 ether_addr_copy(element.mac_addr, hw->mac.addr);
1443 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1444 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1445 } else {
1446 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1447 false, false);
1448 if (f)
1449 f->is_laa = true;
1450 }
1451
1452 i40e_sync_vsi_filters(vsi);
1453 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1454
1455 return 0;
1456}
1457
1458/**
1459 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1460 * @vsi: the VSI being setup
1461 * @ctxt: VSI context structure
1462 * @enabled_tc: Enabled TCs bitmap
1463 * @is_add: True if called before Add VSI
1464 *
1465 * Setup VSI queue mapping for enabled traffic classes.
1466 **/
38e00438
VD		 1467#ifdef I40E_FCOE
1468void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1469 struct i40e_vsi_context *ctxt,
1470 u8 enabled_tc,
1471 bool is_add)
1472#else
41c445ff
JB		 1473static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1474 struct i40e_vsi_context *ctxt,
1475 u8 enabled_tc,
1476 bool is_add)
38e00438 1477#endif
41c445ff
JB		 1478{
1479 struct i40e_pf *pf = vsi->back;
1480 u16 sections = 0;
1481 u8 netdev_tc = 0;
1482 u16 numtc = 0;
1483 u16 qcount;
1484 u8 offset;
1485 u16 qmap;
1486 int i;
4e3b35b0 1487 u16 num_tc_qps = 0;
41c445ff
JB		 1488
1489 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1490 offset = 0;
1491
1492 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1493 /* Find numtc from enabled TC bitmap */
1494 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1495 if (enabled_tc & (1 << i)) /* TC is enabled */
1496 numtc++;
1497 }
1498 if (!numtc) {
1499 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1500 numtc = 1;
1501 }
1502 } else {
1503 /* At least TC0 is enabled in case of non-DCB case */
1504 numtc = 1;
1505 }
1506
1507 vsi->tc_config.numtc = numtc;
1508 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1509 /* Number of queues per enabled TC */
eb051afe 1510 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1511 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1512
1513 /* Setup queue offset/count for all TCs for given VSI */
1514 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1515 /* See if the given TC is enabled for the given VSI */
1516 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1517 int pow, num_qps;
1518
41c445ff
JB		 1519 switch (vsi->type) {
1520 case I40E_VSI_MAIN:
4e3b35b0 1521 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1522 break;
38e00438
VD		 1523#ifdef I40E_FCOE
1524 case I40E_VSI_FCOE:
1525 qcount = num_tc_qps;
1526 break;
1527#endif
41c445ff
JB		 1528 case I40E_VSI_FDIR:
1529 case I40E_VSI_SRIOV:
1530 case I40E_VSI_VMDQ2:
1531 default:
4e3b35b0 1532 qcount = num_tc_qps;
41c445ff
JB		 1533 WARN_ON(i != 0);
1534 break;
1535 }
4e3b35b0
NP		 1536 vsi->tc_config.tc_info[i].qoffset = offset;
1537 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1538
1539 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1540 num_qps = qcount;
41c445ff 1541 pow = 0;
4e3b35b0 1542 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1543 pow++;
1544 num_qps >>= 1;
1545 }
1546
1547 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1548 qmap =
1549 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1550 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1551
4e3b35b0 1552 offset += qcount;
41c445ff
JB		 1553 } else {
1554 /* TC is not enabled so set the offset to
1555 * default queue and allocate one queue
1556 * for the given TC.
1557 */
1558 vsi->tc_config.tc_info[i].qoffset = 0;
1559 vsi->tc_config.tc_info[i].qcount = 1;
1560 vsi->tc_config.tc_info[i].netdev_tc = 0;
1561
1562 qmap = 0;
1563 }
1564 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1565 }
1566
1567 /* Set actual Tx/Rx queue pairs */
1568 vsi->num_queue_pairs = offset;
1569
1570 /* Scheduler section valid can only be set for ADD VSI */
1571 if (is_add) {
1572 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1573
1574 ctxt->info.up_enable_bits = enabled_tc;
1575 }
1576 if (vsi->type == I40E_VSI_SRIOV) {
1577 ctxt->info.mapping_flags |=
1578 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1579 for (i = 0; i < vsi->num_queue_pairs; i++)
1580 ctxt->info.queue_mapping[i] =
1581 cpu_to_le16(vsi->base_queue + i);
1582 } else {
1583 ctxt->info.mapping_flags |=
1584 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1585 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1586 }
1587 ctxt->info.valid_sections |= cpu_to_le16(sections);
1588}
1589
1590/**
1591 * i40e_set_rx_mode - NDO callback to set the netdev filters
1592 * @netdev: network interface device structure
1593 **/
38e00438
VD		 1594#ifdef I40E_FCOE
1595void i40e_set_rx_mode(struct net_device *netdev)
1596#else
41c445ff 1597static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1598#endif
41c445ff
JB		 1599{
1600 struct i40e_netdev_priv *np = netdev_priv(netdev);
1601 struct i40e_mac_filter *f, *ftmp;
1602 struct i40e_vsi *vsi = np->vsi;
1603 struct netdev_hw_addr *uca;
1604 struct netdev_hw_addr *mca;
1605 struct netdev_hw_addr *ha;
1606
1607 /* add addr if not already in the filter list */
1608 netdev_for_each_uc_addr(uca, netdev) {
1609 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1610 if (i40e_is_vsi_in_vlan(vsi))
1611 i40e_put_mac_in_vlan(vsi, uca->addr,
1612 false, true);
1613 else
1614 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1615 false, true);
1616 }
1617 }
1618
1619 netdev_for_each_mc_addr(mca, netdev) {
1620 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1621 if (i40e_is_vsi_in_vlan(vsi))
1622 i40e_put_mac_in_vlan(vsi, mca->addr,
1623 false, true);
1624 else
1625 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1626 false, true);
1627 }
1628 }
1629
1630 /* remove filter if not in netdev list */
1631 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1632 bool found = false;
1633
1634 if (!f->is_netdev)
1635 continue;
1636
1637 if (is_multicast_ether_addr(f->macaddr)) {
1638 netdev_for_each_mc_addr(mca, netdev) {
1639 if (ether_addr_equal(mca->addr, f->macaddr)) {
1640 found = true;
1641 break;
1642 }
1643 }
1644 } else {
1645 netdev_for_each_uc_addr(uca, netdev) {
1646 if (ether_addr_equal(uca->addr, f->macaddr)) {
1647 found = true;
1648 break;
1649 }
1650 }
1651
1652 for_each_dev_addr(netdev, ha) {
1653 if (ether_addr_equal(ha->addr, f->macaddr)) {
1654 found = true;
1655 break;
1656 }
1657 }
1658 }
1659 if (!found)
1660 i40e_del_filter(
1661 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1662 }
1663
1664 /* check for other flag changes */
1665 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1666 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1667 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1668 }
1669}
1670
1671/**
1672 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1673 * @vsi: ptr to the VSI
1674 *
1675 * Push any outstanding VSI filter changes through the AdminQ.
1676 *
1677 * Returns 0 or error value
1678 **/
1679int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1680{
1681 struct i40e_mac_filter *f, *ftmp;
1682 bool promisc_forced_on = false;
1683 bool add_happened = false;
1684 int filter_list_len = 0;
1685 u32 changed_flags = 0;
dcae29be 1686 i40e_status aq_ret = 0;
41c445ff
JB		 1687 struct i40e_pf *pf;
1688 int num_add = 0;
1689 int num_del = 0;
1690 u16 cmd_flags;
1691
1692 /* empty array typed pointers, kcalloc later */
1693 struct i40e_aqc_add_macvlan_element_data *add_list;
1694 struct i40e_aqc_remove_macvlan_element_data *del_list;
1695
1696 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1697 usleep_range(1000, 2000);
1698 pf = vsi->back;
1699
1700 if (vsi->netdev) {
1701 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1702 vsi->current_netdev_flags = vsi->netdev->flags;
1703 }
1704
1705 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1706 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1707
1708 filter_list_len = pf->hw.aq.asq_buf_size /
1709 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1710 del_list = kcalloc(filter_list_len,
1711 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1712 GFP_KERNEL);
1713 if (!del_list)
1714 return -ENOMEM;
1715
1716 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1717 if (!f->changed)
1718 continue;
1719
1720 if (f->counter != 0)
1721 continue;
1722 f->changed = false;
1723 cmd_flags = 0;
1724
1725 /* add to delete list */
9a173901 1726 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1727 del_list[num_del].vlan_tag =
1728 cpu_to_le16((u16)(f->vlan ==
1729 I40E_VLAN_ANY ? 0 : f->vlan));
1730
41c445ff
JB		 1731 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1732 del_list[num_del].flags = cmd_flags;
1733 num_del++;
1734
1735 /* unlink from filter list */
1736 list_del(&f->list);
1737 kfree(f);
1738
1739 /* flush a full buffer */
1740 if (num_del == filter_list_len) {
dcae29be 1741 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1742 vsi->seid, del_list, num_del,
1743 NULL);
1744 num_del = 0;
1745 memset(del_list, 0, sizeof(*del_list));
1746
fdfe9cbe
SN		 1747 if (aq_ret &&
1748 pf->hw.aq.asq_last_status !=
1749 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1750 dev_info(&pf->pdev->dev,
1751 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1752 aq_ret,
41c445ff
JB		 1753 pf->hw.aq.asq_last_status);
1754 }
1755 }
1756 if (num_del) {
dcae29be 1757 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1758 del_list, num_del, NULL);
1759 num_del = 0;
1760
fdfe9cbe
SN		 1761 if (aq_ret &&
1762 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1763 dev_info(&pf->pdev->dev,
1764 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1765 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1766 }
1767
1768 kfree(del_list);
1769 del_list = NULL;
1770
1771 /* do all the adds now */
1772 filter_list_len = pf->hw.aq.asq_buf_size /
1773 sizeof(struct i40e_aqc_add_macvlan_element_data),
1774 add_list = kcalloc(filter_list_len,
1775 sizeof(struct i40e_aqc_add_macvlan_element_data),
1776 GFP_KERNEL);
1777 if (!add_list)
1778 return -ENOMEM;
1779
1780 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1781 if (!f->changed)
1782 continue;
1783
1784 if (f->counter == 0)
1785 continue;
1786 f->changed = false;
1787 add_happened = true;
1788 cmd_flags = 0;
1789
1790 /* add to add array */
9a173901 1791 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1792 add_list[num_add].vlan_tag =
1793 cpu_to_le16(
1794 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1795 add_list[num_add].queue_number = 0;
1796
1797 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1798 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1799 num_add++;
1800
1801 /* flush a full buffer */
1802 if (num_add == filter_list_len) {
dcae29be
JB		 1803 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1804 add_list, num_add,
1805 NULL);
41c445ff
JB		 1806 num_add = 0;
1807
dcae29be 1808 if (aq_ret)
41c445ff
JB		 1809 break;
1810 memset(add_list, 0, sizeof(*add_list));
1811 }
1812 }
1813 if (num_add) {
dcae29be
JB		 1814 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1815 add_list, num_add, NULL);
41c445ff
JB		 1816 num_add = 0;
1817 }
1818 kfree(add_list);
1819 add_list = NULL;
1820
30650cc5
SN		 1821 if (add_happened && aq_ret &&
1822 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1823 dev_info(&pf->pdev->dev,
1824 "add filter failed, err %d, aq_err %d\n",
dcae29be 1825 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1826 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1827 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1828 &vsi->state)) {
1829 promisc_forced_on = true;
1830 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1831 &vsi->state);
1832 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1833 }
1834 }
1835 }
1836
1837 /* check for changes in promiscuous modes */
1838 if (changed_flags & IFF_ALLMULTI) {
1839 bool cur_multipromisc;
1840 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1841 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1842 vsi->seid,
1843 cur_multipromisc,
1844 NULL);
1845 if (aq_ret)
41c445ff
JB		 1846 dev_info(&pf->pdev->dev,
1847 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1848 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1849 }
1850 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1851 bool cur_promisc;
1852 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1853 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1854 &vsi->state));
dcae29be
JB		 1855 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1856 vsi->seid,
1857 cur_promisc, NULL);
1858 if (aq_ret)
41c445ff
JB		 1859 dev_info(&pf->pdev->dev,
1860 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1861 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1862 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1863 vsi->seid,
1864 cur_promisc, NULL);
1865 if (aq_ret)
1866 dev_info(&pf->pdev->dev,
1867 "set brdcast promisc failed, err %d, aq_err %d\n",
1868 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1869 }
1870
1871 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1872 return 0;
1873}
1874
1875/**
1876 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1877 * @pf: board private structure
1878 **/
1879static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1880{
1881 int v;
1882
1883 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1884 return;
1885 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1886
505682cd 1887 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1888 if (pf->vsi[v] &&
1889 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1890 i40e_sync_vsi_filters(pf->vsi[v]);
1891 }
1892}
1893
1894/**
1895 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1896 * @netdev: network interface device structure
1897 * @new_mtu: new value for maximum frame size
1898 *
1899 * Returns 0 on success, negative on failure
1900 **/
1901static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1902{
1903 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1904 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1905 struct i40e_vsi *vsi = np->vsi;
1906
1907 /* MTU < 68 is an error and causes problems on some kernels */
1908 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1909 return -EINVAL;
1910
1911 netdev_info(netdev, "changing MTU from %d to %d\n",
1912 netdev->mtu, new_mtu);
1913 netdev->mtu = new_mtu;
1914 if (netif_running(netdev))
1915 i40e_vsi_reinit_locked(vsi);
1916
1917 return 0;
1918}
1919
beb0dff1
JK		 1920/**
1921 * i40e_ioctl - Access the hwtstamp interface
1922 * @netdev: network interface device structure
1923 * @ifr: interface request data
1924 * @cmd: ioctl command
1925 **/
1926int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1927{
1928 struct i40e_netdev_priv *np = netdev_priv(netdev);
1929 struct i40e_pf *pf = np->vsi->back;
1930
1931 switch (cmd) {
1932 case SIOCGHWTSTAMP:
1933 return i40e_ptp_get_ts_config(pf, ifr);
1934 case SIOCSHWTSTAMP:
1935 return i40e_ptp_set_ts_config(pf, ifr);
1936 default:
1937 return -EOPNOTSUPP;
1938 }
1939}
1940
41c445ff
JB		 1941/**
1942 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1943 * @vsi: the vsi being adjusted
1944 **/
1945void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1946{
1947 struct i40e_vsi_context ctxt;
1948 i40e_status ret;
1949
1950 if ((vsi->info.valid_sections &
1951 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1952 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1953 return; /* already enabled */
1954
1955 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1956 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1957 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1958
1959 ctxt.seid = vsi->seid;
1960 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1961 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1962 if (ret) {
1963 dev_info(&vsi->back->pdev->dev,
1964 "%s: update vsi failed, aq_err=%d\n",
1965 __func__, vsi->back->hw.aq.asq_last_status);
1966 }
1967}
1968
1969/**
1970 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1971 * @vsi: the vsi being adjusted
1972 **/
1973void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1974{
1975 struct i40e_vsi_context ctxt;
1976 i40e_status ret;
1977
1978 if ((vsi->info.valid_sections &
1979 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1980 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1981 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1982 return; /* already disabled */
1983
1984 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1985 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1986 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1987
1988 ctxt.seid = vsi->seid;
1989 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1990 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1991 if (ret) {
1992 dev_info(&vsi->back->pdev->dev,
1993 "%s: update vsi failed, aq_err=%d\n",
1994 __func__, vsi->back->hw.aq.asq_last_status);
1995 }
1996}
1997
1998/**
1999 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2000 * @netdev: network interface to be adjusted
2001 * @features: netdev features to test if VLAN offload is enabled or not
2002 **/
2003static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2004{
2005 struct i40e_netdev_priv *np = netdev_priv(netdev);
2006 struct i40e_vsi *vsi = np->vsi;
2007
2008 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2009 i40e_vlan_stripping_enable(vsi);
2010 else
2011 i40e_vlan_stripping_disable(vsi);
2012}
2013
2014/**
2015 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2016 * @vsi: the vsi being configured
2017 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2018 **/
2019int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2020{
2021 struct i40e_mac_filter *f, *add_f;
2022 bool is_netdev, is_vf;
41c445ff
JB		 2023
2024 is_vf = (vsi->type == I40E_VSI_SRIOV);
2025 is_netdev = !!(vsi->netdev);
2026
2027 if (is_netdev) {
2028 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2029 is_vf, is_netdev);
2030 if (!add_f) {
2031 dev_info(&vsi->back->pdev->dev,
2032 "Could not add vlan filter %d for %pM\n",
2033 vid, vsi->netdev->dev_addr);
2034 return -ENOMEM;
2035 }
2036 }
2037
2038 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2039 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2040 if (!add_f) {
2041 dev_info(&vsi->back->pdev->dev,
2042 "Could not add vlan filter %d for %pM\n",
2043 vid, f->macaddr);
2044 return -ENOMEM;
2045 }
2046 }
2047
41c445ff
JB		 2048 /* Now if we add a vlan tag, make sure to check if it is the first
2049 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2050 * with 0, so we now accept untagged and specified tagged traffic
2051 * (and not any taged and untagged)
2052 */
2053 if (vid > 0) {
2054 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2055 I40E_VLAN_ANY,
2056 is_vf, is_netdev)) {
2057 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2058 I40E_VLAN_ANY, is_vf, is_netdev);
2059 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2060 is_vf, is_netdev);
2061 if (!add_f) {
2062 dev_info(&vsi->back->pdev->dev,
2063 "Could not add filter 0 for %pM\n",
2064 vsi->netdev->dev_addr);
2065 return -ENOMEM;
2066 }
2067 }
8d82a7c5 2068 }
41c445ff 2069
8d82a7c5
GR		 2070 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2071 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2072 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2073 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2074 is_vf, is_netdev)) {
2075 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2076 is_vf, is_netdev);
2077 add_f = i40e_add_filter(vsi, f->macaddr,
2078 0, is_vf, is_netdev);
2079 if (!add_f) {
2080 dev_info(&vsi->back->pdev->dev,
2081 "Could not add filter 0 for %pM\n",
2082 f->macaddr);
2083 return -ENOMEM;
2084 }
2085 }
2086 }
41c445ff
JB		 2087 }
2088
80f6428f
ASJ		 2089 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2090 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2091 return 0;
2092
2093 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2094}
2095
2096/**
2097 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2098 * @vsi: the vsi being configured
2099 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2100 *
2101 * Return: 0 on success or negative otherwise
41c445ff
JB		 2102 **/
2103int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2104{
2105 struct net_device *netdev = vsi->netdev;
2106 struct i40e_mac_filter *f, *add_f;
2107 bool is_vf, is_netdev;
2108 int filter_count = 0;
41c445ff
JB		 2109
2110 is_vf = (vsi->type == I40E_VSI_SRIOV);
2111 is_netdev = !!(netdev);
2112
2113 if (is_netdev)
2114 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2115
2116 list_for_each_entry(f, &vsi->mac_filter_list, list)
2117 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2118
41c445ff
JB		 2119 /* go through all the filters for this VSI and if there is only
2120 * vid == 0 it means there are no other filters, so vid 0 must
2121 * be replaced with -1. This signifies that we should from now
2122 * on accept any traffic (with any tag present, or untagged)
2123 */
2124 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2125 if (is_netdev) {
2126 if (f->vlan &&
2127 ether_addr_equal(netdev->dev_addr, f->macaddr))
2128 filter_count++;
2129 }
2130
2131 if (f->vlan)
2132 filter_count++;
2133 }
2134
2135 if (!filter_count && is_netdev) {
2136 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2137 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2138 is_vf, is_netdev);
2139 if (!f) {
2140 dev_info(&vsi->back->pdev->dev,
2141 "Could not add filter %d for %pM\n",
2142 I40E_VLAN_ANY, netdev->dev_addr);
2143 return -ENOMEM;
2144 }
2145 }
2146
2147 if (!filter_count) {
2148 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2149 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2150 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2151 is_vf, is_netdev);
2152 if (!add_f) {
2153 dev_info(&vsi->back->pdev->dev,
2154 "Could not add filter %d for %pM\n",
2155 I40E_VLAN_ANY, f->macaddr);
2156 return -ENOMEM;
2157 }
2158 }
2159 }
2160
80f6428f
ASJ		 2161 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2162 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2163 return 0;
2164
41c445ff
JB		 2165 return i40e_sync_vsi_filters(vsi);
2166}
2167
2168/**
2169 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2170 * @netdev: network interface to be adjusted
2171 * @vid: vlan id to be added
078b5876
JB		 2172 *
2173 * net_device_ops implementation for adding vlan ids
41c445ff 2174 **/
38e00438
VD		 2175#ifdef I40E_FCOE
2176int i40e_vlan_rx_add_vid(struct net_device *netdev,
2177 __always_unused __be16 proto, u16 vid)
2178#else
41c445ff
JB		 2179static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2180 __always_unused __be16 proto, u16 vid)
38e00438 2181#endif
41c445ff
JB		 2182{
2183 struct i40e_netdev_priv *np = netdev_priv(netdev);
2184 struct i40e_vsi *vsi = np->vsi;
078b5876 2185 int ret = 0;
41c445ff
JB		 2186
2187 if (vid > 4095)
078b5876
JB		 2188 return -EINVAL;
2189
2190 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2191
6982d429
ASJ		 2192 /* If the network stack called us with vid = 0 then
2193 * it is asking to receive priority tagged packets with
2194 * vlan id 0. Our HW receives them by default when configured
2195 * to receive untagged packets so there is no need to add an
2196 * extra filter for vlan 0 tagged packets.
41c445ff 2197 */
6982d429
ASJ		 2198 if (vid)
2199 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2200
078b5876
JB		 2201 if (!ret && (vid < VLAN_N_VID))
2202 set_bit(vid, vsi->active_vlans);
41c445ff 2203
078b5876 2204 return ret;
41c445ff
JB		 2205}
2206
2207/**
2208 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2209 * @netdev: network interface to be adjusted
2210 * @vid: vlan id to be removed
078b5876 2211 *
fdfd943e 2212 * net_device_ops implementation for removing vlan ids
41c445ff 2213 **/
38e00438
VD		 2214#ifdef I40E_FCOE
2215int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2216 __always_unused __be16 proto, u16 vid)
2217#else
41c445ff
JB		 2218static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2219 __always_unused __be16 proto, u16 vid)
38e00438 2220#endif
41c445ff
JB		 2221{
2222 struct i40e_netdev_priv *np = netdev_priv(netdev);
2223 struct i40e_vsi *vsi = np->vsi;
2224
078b5876
JB		 2225 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2226
41c445ff
JB		 2227 /* return code is ignored as there is nothing a user
2228 * can do about failure to remove and a log message was
078b5876 2229 * already printed from the other function
41c445ff
JB		 2230 */
2231 i40e_vsi_kill_vlan(vsi, vid);
2232
2233 clear_bit(vid, vsi->active_vlans);
078b5876 2234
41c445ff
JB		 2235 return 0;
2236}
2237
2238/**
2239 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2240 * @vsi: the vsi being brought back up
2241 **/
2242static void i40e_restore_vlan(struct i40e_vsi *vsi)
2243{
2244 u16 vid;
2245
2246 if (!vsi->netdev)
2247 return;
2248
2249 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2250
2251 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2252 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2253 vid);
2254}
2255
2256/**
2257 * i40e_vsi_add_pvid - Add pvid for the VSI
2258 * @vsi: the vsi being adjusted
2259 * @vid: the vlan id to set as a PVID
2260 **/
dcae29be 2261int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2262{
2263 struct i40e_vsi_context ctxt;
dcae29be 2264 i40e_status aq_ret;
41c445ff
JB		 2265
2266 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2267 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2268 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2269 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2270 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2271
2272 ctxt.seid = vsi->seid;
2273 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2274 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2275 if (aq_ret) {
41c445ff
JB		 2276 dev_info(&vsi->back->pdev->dev,
2277 "%s: update vsi failed, aq_err=%d\n",
2278 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2279 return -ENOENT;
41c445ff
JB		 2280 }
2281
dcae29be 2282 return 0;
41c445ff
JB		 2283}
2284
2285/**
2286 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2287 * @vsi: the vsi being adjusted
2288 *
2289 * Just use the vlan_rx_register() service to put it back to normal
2290 **/
2291void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2292{
6c12fcbf
GR		 2293 i40e_vlan_stripping_disable(vsi);
2294
41c445ff 2295 vsi->info.pvid = 0;
41c445ff
JB		 2296}
2297
2298/**
2299 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2300 * @vsi: ptr to the VSI
2301 *
2302 * If this function returns with an error, then it's possible one or
2303 * more of the rings is populated (while the rest are not). It is the
2304 * callers duty to clean those orphaned rings.
2305 *
2306 * Return 0 on success, negative on failure
2307 **/
2308static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2309{
2310 int i, err = 0;
2311
2312 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2313 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2314
2315 return err;
2316}
2317
2318/**
2319 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2320 * @vsi: ptr to the VSI
2321 *
2322 * Free VSI's transmit software resources
2323 **/
2324static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2325{
2326 int i;
2327
8e9dca53
GR		 2328 if (!vsi->tx_rings)
2329 return;
2330
41c445ff 2331 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2332 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2333 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2334}
2335
2336/**
2337 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2338 * @vsi: ptr to the VSI
2339 *
2340 * If this function returns with an error, then it's possible one or
2341 * more of the rings is populated (while the rest are not). It is the
2342 * callers duty to clean those orphaned rings.
2343 *
2344 * Return 0 on success, negative on failure
2345 **/
2346static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2347{
2348 int i, err = 0;
2349
2350 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2351 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2352#ifdef I40E_FCOE
2353 i40e_fcoe_setup_ddp_resources(vsi);
2354#endif
41c445ff
JB		 2355 return err;
2356}
2357
2358/**
2359 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2360 * @vsi: ptr to the VSI
2361 *
2362 * Free all receive software resources
2363 **/
2364static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2365{
2366 int i;
2367
8e9dca53
GR		 2368 if (!vsi->rx_rings)
2369 return;
2370
41c445ff 2371 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2372 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2373 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2374#ifdef I40E_FCOE
2375 i40e_fcoe_free_ddp_resources(vsi);
2376#endif
41c445ff
JB		 2377}
2378
3ffa037d
NP		 2379/**
2380 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2381 * @ring: The Tx ring to configure
2382 *
2383 * This enables/disables XPS for a given Tx descriptor ring
2384 * based on the TCs enabled for the VSI that ring belongs to.
2385 **/
2386static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2387{
2388 struct i40e_vsi *vsi = ring->vsi;
2389 cpumask_var_t mask;
2390
2391 if (ring->q_vector && ring->netdev) {
2392 /* Single TC mode enable XPS */
2393 if (vsi->tc_config.numtc <= 1 &&
2394 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state)) {
2395 netif_set_xps_queue(ring->netdev,
2396 &ring->q_vector->affinity_mask,
2397 ring->queue_index);
2398 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2399 /* Disable XPS to allow selection based on TC */
2400 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2401 netif_set_xps_queue(ring->netdev, mask,
2402 ring->queue_index);
2403 free_cpumask_var(mask);
2404 }
2405 }
2406}
2407
41c445ff
JB		 2408/**
2409 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2410 * @ring: The Tx ring to configure
2411 *
2412 * Configure the Tx descriptor ring in the HMC context.
2413 **/
2414static int i40e_configure_tx_ring(struct i40e_ring *ring)
2415{
2416 struct i40e_vsi *vsi = ring->vsi;
2417 u16 pf_q = vsi->base_queue + ring->queue_index;
2418 struct i40e_hw *hw = &vsi->back->hw;
2419 struct i40e_hmc_obj_txq tx_ctx;
2420 i40e_status err = 0;
2421 u32 qtx_ctl = 0;
2422
2423 /* some ATR related tx ring init */
60ea5f83 2424 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2425 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2426 ring->atr_count = 0;
2427 } else {
2428 ring->atr_sample_rate = 0;
2429 }
2430
3ffa037d
NP		 2431 /* configure XPS */
2432 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2433
2434 /* clear the context structure first */
2435 memset(&tx_ctx, 0, sizeof(tx_ctx));
2436
2437 tx_ctx.new_context = 1;
2438 tx_ctx.base = (ring->dma / 128);
2439 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2440 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2441 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2442#ifdef I40E_FCOE
2443 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2444#endif
beb0dff1 2445 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2446 /* FDIR VSI tx ring can still use RS bit and writebacks */
2447 if (vsi->type != I40E_VSI_FDIR)
2448 tx_ctx.head_wb_ena = 1;
2449 tx_ctx.head_wb_addr = ring->dma +
2450 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2451
2452 /* As part of VSI creation/update, FW allocates certain
2453 * Tx arbitration queue sets for each TC enabled for
2454 * the VSI. The FW returns the handles to these queue
2455 * sets as part of the response buffer to Add VSI,
2456 * Update VSI, etc. AQ commands. It is expected that
2457 * these queue set handles be associated with the Tx
2458 * queues by the driver as part of the TX queue context
2459 * initialization. This has to be done regardless of
2460 * DCB as by default everything is mapped to TC0.
2461 */
2462 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2463 tx_ctx.rdylist_act = 0;
2464
2465 /* clear the context in the HMC */
2466 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2467 if (err) {
2468 dev_info(&vsi->back->pdev->dev,
2469 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2470 ring->queue_index, pf_q, err);
2471 return -ENOMEM;
2472 }
2473
2474 /* set the context in the HMC */
2475 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2476 if (err) {
2477 dev_info(&vsi->back->pdev->dev,
2478 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2479 ring->queue_index, pf_q, err);
2480 return -ENOMEM;
2481 }
2482
2483 /* Now associate this queue with this PCI function */
7a28d885 2484 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2485 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2486 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2487 I40E_QTX_CTL_VFVM_INDX_MASK;
2488 } else {
9d8bf547 2489 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2490 }
2491
13fd9774
SN		 2492 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2493 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2494 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2495 i40e_flush(hw);
2496
2497 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2498
2499 /* cache tail off for easier writes later */
2500 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2501
2502 return 0;
2503}
2504
2505/**
2506 * i40e_configure_rx_ring - Configure a receive ring context
2507 * @ring: The Rx ring to configure
2508 *
2509 * Configure the Rx descriptor ring in the HMC context.
2510 **/
2511static int i40e_configure_rx_ring(struct i40e_ring *ring)
2512{
2513 struct i40e_vsi *vsi = ring->vsi;
2514 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2515 u16 pf_q = vsi->base_queue + ring->queue_index;
2516 struct i40e_hw *hw = &vsi->back->hw;
2517 struct i40e_hmc_obj_rxq rx_ctx;
2518 i40e_status err = 0;
2519
2520 ring->state = 0;
2521
2522 /* clear the context structure first */
2523 memset(&rx_ctx, 0, sizeof(rx_ctx));
2524
2525 ring->rx_buf_len = vsi->rx_buf_len;
2526 ring->rx_hdr_len = vsi->rx_hdr_len;
2527
2528 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2529 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2530
2531 rx_ctx.base = (ring->dma / 128);
2532 rx_ctx.qlen = ring->count;
2533
2534 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2535 set_ring_16byte_desc_enabled(ring);
2536 rx_ctx.dsize = 0;
2537 } else {
2538 rx_ctx.dsize = 1;
2539 }
2540
2541 rx_ctx.dtype = vsi->dtype;
2542 if (vsi->dtype) {
2543 set_ring_ps_enabled(ring);
2544 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2545 I40E_RX_SPLIT_IP |
2546 I40E_RX_SPLIT_TCP_UDP |
2547 I40E_RX_SPLIT_SCTP;
2548 } else {
2549 rx_ctx.hsplit_0 = 0;
2550 }
2551
2552 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2553 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2554 if (hw->revision_id == 0)
2555 rx_ctx.lrxqthresh = 0;
2556 else
2557 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2558 rx_ctx.crcstrip = 1;
2559 rx_ctx.l2tsel = 1;
2560 rx_ctx.showiv = 1;
38e00438
VD		 2561#ifdef I40E_FCOE
2562 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2563#endif
acb3676b
CS		 2564 /* set the prefena field to 1 because the manual says to */
2565 rx_ctx.prefena = 1;
41c445ff
JB		 2566
2567 /* clear the context in the HMC */
2568 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2569 if (err) {
2570 dev_info(&vsi->back->pdev->dev,
2571 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2572 ring->queue_index, pf_q, err);
2573 return -ENOMEM;
2574 }
2575
2576 /* set the context in the HMC */
2577 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2578 if (err) {
2579 dev_info(&vsi->back->pdev->dev,
2580 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2581 ring->queue_index, pf_q, err);
2582 return -ENOMEM;
2583 }
2584
2585 /* cache tail for quicker writes, and clear the reg before use */
2586 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2587 writel(0, ring->tail);
2588
a132af24
MW		 2589 if (ring_is_ps_enabled(ring)) {
2590 i40e_alloc_rx_headers(ring);
2591 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2592 } else {
2593 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2594 }
41c445ff
JB		 2595
2596 return 0;
2597}
2598
2599/**
2600 * i40e_vsi_configure_tx - Configure the VSI for Tx
2601 * @vsi: VSI structure describing this set of rings and resources
2602 *
2603 * Configure the Tx VSI for operation.
2604 **/
2605static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2606{
2607 int err = 0;
2608 u16 i;
2609
9f65e15b
AD		 2610 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2611 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2612
2613 return err;
2614}
2615
2616/**
2617 * i40e_vsi_configure_rx - Configure the VSI for Rx
2618 * @vsi: the VSI being configured
2619 *
2620 * Configure the Rx VSI for operation.
2621 **/
2622static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2623{
2624 int err = 0;
2625 u16 i;
2626
2627 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2628 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2629 + ETH_FCS_LEN + VLAN_HLEN;
2630 else
2631 vsi->max_frame = I40E_RXBUFFER_2048;
2632
2633 /* figure out correct receive buffer length */
2634 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2635 I40E_FLAG_RX_PS_ENABLED)) {
2636 case I40E_FLAG_RX_1BUF_ENABLED:
2637 vsi->rx_hdr_len = 0;
2638 vsi->rx_buf_len = vsi->max_frame;
2639 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2640 break;
2641 case I40E_FLAG_RX_PS_ENABLED:
2642 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2643 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2644 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2645 break;
2646 default:
2647 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2648 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2649 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2650 break;
2651 }
2652
38e00438
VD		 2653#ifdef I40E_FCOE
2654 /* setup rx buffer for FCoE */
2655 if ((vsi->type == I40E_VSI_FCOE) &&
2656 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2657 vsi->rx_hdr_len = 0;
2658 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2659 vsi->max_frame = I40E_RXBUFFER_3072;
2660 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2661 }
2662
2663#endif /* I40E_FCOE */
41c445ff
JB		 2664 /* round up for the chip's needs */
2665 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2666 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2667 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2668 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2669
2670 /* set up individual rings */
2671 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2672 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2673
2674 return err;
2675}
2676
2677/**
2678 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2679 * @vsi: ptr to the VSI
2680 **/
2681static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2682{
e7046ee1 2683 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2684 u16 qoffset, qcount;
2685 int i, n;
2686
2687 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2688 return;
2689
2690 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2691 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2692 continue;
2693
2694 qoffset = vsi->tc_config.tc_info[n].qoffset;
2695 qcount = vsi->tc_config.tc_info[n].qcount;
2696 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2697 rx_ring = vsi->rx_rings[i];
2698 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2699 rx_ring->dcb_tc = n;
2700 tx_ring->dcb_tc = n;
2701 }
2702 }
2703}
2704
2705/**
2706 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2707 * @vsi: ptr to the VSI
2708 **/
2709static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2710{
2711 if (vsi->netdev)
2712 i40e_set_rx_mode(vsi->netdev);
2713}
2714
17a73f6b
JG		 2715/**
2716 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2717 * @vsi: Pointer to the targeted VSI
2718 *
2719 * This function replays the hlist on the hw where all the SB Flow Director
2720 * filters were saved.
2721 **/
2722static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2723{
2724 struct i40e_fdir_filter *filter;
2725 struct i40e_pf *pf = vsi->back;
2726 struct hlist_node *node;
2727
55a5e60b
ASJ		 2728 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2729 return;
2730
17a73f6b
JG		 2731 hlist_for_each_entry_safe(filter, node,
2732 &pf->fdir_filter_list, fdir_node) {
2733 i40e_add_del_fdir(vsi, filter, true);
2734 }
2735}
2736
41c445ff
JB		 2737/**
2738 * i40e_vsi_configure - Set up the VSI for action
2739 * @vsi: the VSI being configured
2740 **/
2741static int i40e_vsi_configure(struct i40e_vsi *vsi)
2742{
2743 int err;
2744
2745 i40e_set_vsi_rx_mode(vsi);
2746 i40e_restore_vlan(vsi);
2747 i40e_vsi_config_dcb_rings(vsi);
2748 err = i40e_vsi_configure_tx(vsi);
2749 if (!err)
2750 err = i40e_vsi_configure_rx(vsi);
2751
2752 return err;
2753}
2754
2755/**
2756 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2757 * @vsi: the VSI being configured
2758 **/
2759static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2760{
2761 struct i40e_pf *pf = vsi->back;
2762 struct i40e_q_vector *q_vector;
2763 struct i40e_hw *hw = &pf->hw;
2764 u16 vector;
2765 int i, q;
2766 u32 val;
2767 u32 qp;
2768
2769 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2770 * and PFINT_LNKLSTn registers, e.g.:
2771 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2772 */
2773 qp = vsi->base_queue;
2774 vector = vsi->base_vector;
493fb300
AD		 2775 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2776 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2777 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2778 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2779 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2780 q_vector->rx.itr);
2781 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2782 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2783 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2784 q_vector->tx.itr);
2785
2786 /* Linked list for the queuepairs assigned to this vector */
2787 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2788 for (q = 0; q < q_vector->num_ringpairs; q++) {
2789 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2790 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2791 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2792 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2793 (I40E_QUEUE_TYPE_TX
2794 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2795
2796 wr32(hw, I40E_QINT_RQCTL(qp), val);
2797
2798 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2799 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2800 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2801 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2802 (I40E_QUEUE_TYPE_RX
2803 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2804
2805 /* Terminate the linked list */
2806 if (q == (q_vector->num_ringpairs - 1))
2807 val |= (I40E_QUEUE_END_OF_LIST
2808 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2809
2810 wr32(hw, I40E_QINT_TQCTL(qp), val);
2811 qp++;
2812 }
2813 }
2814
2815 i40e_flush(hw);
2816}
2817
2818/**
2819 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2820 * @hw: ptr to the hardware info
2821 **/
ab437b5a 2822static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2823{
ab437b5a 2824 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2825 u32 val;
2826
2827 /* clear things first */
2828 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2829 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2830
2831 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2832 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2833 I40E_PFINT_ICR0_ENA_GRST_MASK |
2834 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2835 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2836 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2837 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2838 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2839
ab437b5a
JK		 2840 if (pf->flags & I40E_FLAG_PTP)
2841 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2842
41c445ff
JB		 2843 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2844
2845 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2846 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2847 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2848
2849 /* OTHER_ITR_IDX = 0 */
2850 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2851}
2852
2853/**
2854 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2855 * @vsi: the VSI being configured
2856 **/
2857static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2858{
493fb300 2859 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2860 struct i40e_pf *pf = vsi->back;
2861 struct i40e_hw *hw = &pf->hw;
2862 u32 val;
2863
2864 /* set the ITR configuration */
2865 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2866 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2867 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2868 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2869 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2870 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2871
ab437b5a 2872 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 2873
2874 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2875 wr32(hw, I40E_PFINT_LNKLST0, 0);
2876
f29eaa3d 2877 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2878 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2879 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2880 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2881
2882 wr32(hw, I40E_QINT_RQCTL(0), val);
2883
2884 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2885 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2886 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2887
2888 wr32(hw, I40E_QINT_TQCTL(0), val);
2889 i40e_flush(hw);
2890}
2891
2ef28cfb
MW		 2892/**
2893 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2894 * @pf: board private structure
2895 **/
2896void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2897{
2898 struct i40e_hw *hw = &pf->hw;
2899
2900 wr32(hw, I40E_PFINT_DYN_CTL0,
2901 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2902 i40e_flush(hw);
2903}
2904
41c445ff
JB		 2905/**
2906 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2907 * @pf: board private structure
2908 **/
116a57d4 2909void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2910{
2911 struct i40e_hw *hw = &pf->hw;
2912 u32 val;
2913
2914 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2915 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2916 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2917
2918 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2919 i40e_flush(hw);
2920}
2921
2922/**
2923 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2924 * @vsi: pointer to a vsi
2925 * @vector: enable a particular Hw Interrupt vector
2926 **/
2927void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2928{
2929 struct i40e_pf *pf = vsi->back;
2930 struct i40e_hw *hw = &pf->hw;
2931 u32 val;
2932
2933 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2934 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2935 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2936 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2937 /* skip the flush */
41c445ff
JB		 2938}
2939
5c2cebda
CW		 2940/**
2941 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2942 * @vsi: pointer to a vsi
03147773 2943 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 2944 **/
2945void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2946{
2947 struct i40e_pf *pf = vsi->back;
2948 struct i40e_hw *hw = &pf->hw;
2949 u32 val;
2950
2951 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2952 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2953 i40e_flush(hw);
2954}
2955
41c445ff
JB		 2956/**
2957 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2958 * @irq: interrupt number
2959 * @data: pointer to a q_vector
2960 **/
2961static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2962{
2963 struct i40e_q_vector *q_vector = data;
2964
cd0b6fa6 2965 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2966 return IRQ_HANDLED;
2967
2968 napi_schedule(&q_vector->napi);
2969
2970 return IRQ_HANDLED;
2971}
2972
41c445ff
JB		 2973/**
2974 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2975 * @vsi: the VSI being configured
2976 * @basename: name for the vector
2977 *
2978 * Allocates MSI-X vectors and requests interrupts from the kernel.
2979 **/
2980static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2981{
2982 int q_vectors = vsi->num_q_vectors;
2983 struct i40e_pf *pf = vsi->back;
2984 int base = vsi->base_vector;
2985 int rx_int_idx = 0;
2986 int tx_int_idx = 0;
2987 int vector, err;
2988
2989 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2990 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2991
cd0b6fa6 2992 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2993 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2994 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2995 tx_int_idx++;
cd0b6fa6 2996 } else if (q_vector->rx.ring) {
41c445ff
JB		 2997 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2998 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2999 } else if (q_vector->tx.ring) {
41c445ff
JB		 3000 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3001 "%s-%s-%d", basename, "tx", tx_int_idx++);
3002 } else {
3003 /* skip this unused q_vector */
3004 continue;
3005 }
3006 err = request_irq(pf->msix_entries[base + vector].vector,
3007 vsi->irq_handler,
3008 0,
3009 q_vector->name,
3010 q_vector);
3011 if (err) {
3012 dev_info(&pf->pdev->dev,
3013 "%s: request_irq failed, error: %d\n",
3014 __func__, err);
3015 goto free_queue_irqs;
3016 }
3017 /* assign the mask for this irq */
3018 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3019 &q_vector->affinity_mask);
3020 }
3021
63741846 3022 vsi->irqs_ready = true;
41c445ff
JB		 3023 return 0;
3024
3025free_queue_irqs:
3026 while (vector) {
3027 vector--;
3028 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3029 NULL);
3030 free_irq(pf->msix_entries[base + vector].vector,
3031 &(vsi->q_vectors[vector]));
3032 }
3033 return err;
3034}
3035
3036/**
3037 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3038 * @vsi: the VSI being un-configured
3039 **/
3040static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3041{
3042 struct i40e_pf *pf = vsi->back;
3043 struct i40e_hw *hw = &pf->hw;
3044 int base = vsi->base_vector;
3045 int i;
3046
3047 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3048 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3049 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3050 }
3051
3052 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3053 for (i = vsi->base_vector;
3054 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3055 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3056
3057 i40e_flush(hw);
3058 for (i = 0; i < vsi->num_q_vectors; i++)
3059 synchronize_irq(pf->msix_entries[i + base].vector);
3060 } else {
3061 /* Legacy and MSI mode - this stops all interrupt handling */
3062 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3063 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3064 i40e_flush(hw);
3065 synchronize_irq(pf->pdev->irq);
3066 }
3067}
3068
3069/**
3070 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3071 * @vsi: the VSI being configured
3072 **/
3073static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3074{
3075 struct i40e_pf *pf = vsi->back;
3076 int i;
3077
3078 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3079 for (i = vsi->base_vector;
3080 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3081 i40e_irq_dynamic_enable(vsi, i);
3082 } else {
3083 i40e_irq_dynamic_enable_icr0(pf);
3084 }
3085
1022cb6c 3086 i40e_flush(&pf->hw);
41c445ff
JB		 3087 return 0;
3088}
3089
3090/**
3091 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3092 * @pf: board private structure
3093 **/
3094static void i40e_stop_misc_vector(struct i40e_pf *pf)
3095{
3096 /* Disable ICR 0 */
3097 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3098 i40e_flush(&pf->hw);
3099}
3100
3101/**
3102 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3103 * @irq: interrupt number
3104 * @data: pointer to a q_vector
3105 *
3106 * This is the handler used for all MSI/Legacy interrupts, and deals
3107 * with both queue and non-queue interrupts. This is also used in
3108 * MSIX mode to handle the non-queue interrupts.
3109 **/
3110static irqreturn_t i40e_intr(int irq, void *data)
3111{
3112 struct i40e_pf *pf = (struct i40e_pf *)data;
3113 struct i40e_hw *hw = &pf->hw;
5e823066 3114 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3115 u32 icr0, icr0_remaining;
3116 u32 val, ena_mask;
3117
3118 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3119 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3120
116a57d4
SN		 3121 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3122 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3123 goto enable_intr;
41c445ff 3124
cd92e72f
SN		 3125 /* if interrupt but no bits showing, must be SWINT */
3126 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3127 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3128 pf->sw_int_count++;
3129
41c445ff
JB		 3130 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3131 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3132
3133 /* temporarily disable queue cause for NAPI processing */
3134 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3135 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3136 wr32(hw, I40E_QINT_RQCTL(0), qval);
3137
3138 qval = rd32(hw, I40E_QINT_TQCTL(0));
3139 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3140 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3141
3142 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3143 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3144 }
3145
3146 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3147 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3148 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3149 }
3150
3151 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3152 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3153 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3154 }
3155
3156 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3157 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3158 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3159 }
3160
3161 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3162 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3163 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3164 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3165 val = rd32(hw, I40E_GLGEN_RSTAT);
3166 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3167 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3168 if (val == I40E_RESET_CORER) {
41c445ff 3169 pf->corer_count++;
4eb3f768 3170 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3171 pf->globr_count++;
4eb3f768 3172 } else if (val == I40E_RESET_EMPR) {
41c445ff 3173 pf->empr_count++;
9df42d1a 3174 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3175 }
41c445ff
JB		 3176 }
3177
9c010ee0
ASJ		 3178 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3179 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3180 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3181 }
3182
beb0dff1
JK		 3183 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3184 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3185
3186 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3187 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3188 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3189 }
beb0dff1
JK		 3190 }
3191
41c445ff
JB		 3192 /* If a critical error is pending we have no choice but to reset the
3193 * device.
3194 * Report and mask out any remaining unexpected interrupts.
3195 */
3196 icr0_remaining = icr0 & ena_mask;
3197 if (icr0_remaining) {
3198 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3199 icr0_remaining);
9c010ee0 3200 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3201 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3202 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3203 dev_info(&pf->pdev->dev, "device will be reset\n");
3204 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3205 i40e_service_event_schedule(pf);
41c445ff
JB		 3206 }
3207 ena_mask &= ~icr0_remaining;
3208 }
5e823066 3209 ret = IRQ_HANDLED;
41c445ff 3210
5e823066 3211enable_intr:
41c445ff
JB		 3212 /* re-enable interrupt causes */
3213 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3214 if (!test_bit(__I40E_DOWN, &pf->state)) {
3215 i40e_service_event_schedule(pf);
3216 i40e_irq_dynamic_enable_icr0(pf);
3217 }
3218
5e823066 3219 return ret;
41c445ff
JB		 3220}
3221
cbf61325
ASJ		 3222/**
3223 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3224 * @tx_ring: tx ring to clean
3225 * @budget: how many cleans we're allowed
3226 *
3227 * Returns true if there's any budget left (e.g. the clean is finished)
3228 **/
3229static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3230{
3231 struct i40e_vsi *vsi = tx_ring->vsi;
3232 u16 i = tx_ring->next_to_clean;
3233 struct i40e_tx_buffer *tx_buf;
3234 struct i40e_tx_desc *tx_desc;
3235
3236 tx_buf = &tx_ring->tx_bi[i];
3237 tx_desc = I40E_TX_DESC(tx_ring, i);
3238 i -= tx_ring->count;
3239
3240 do {
3241 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3242
3243 /* if next_to_watch is not set then there is no work pending */
3244 if (!eop_desc)
3245 break;
3246
3247 /* prevent any other reads prior to eop_desc */
3248 read_barrier_depends();
3249
3250 /* if the descriptor isn't done, no work yet to do */
3251 if (!(eop_desc->cmd_type_offset_bsz &
3252 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3253 break;
3254
3255 /* clear next_to_watch to prevent false hangs */
3256 tx_buf->next_to_watch = NULL;
3257
49d7d933
ASJ		 3258 tx_desc->buffer_addr = 0;
3259 tx_desc->cmd_type_offset_bsz = 0;
3260 /* move past filter desc */
3261 tx_buf++;
3262 tx_desc++;
3263 i++;
3264 if (unlikely(!i)) {
3265 i -= tx_ring->count;
3266 tx_buf = tx_ring->tx_bi;
3267 tx_desc = I40E_TX_DESC(tx_ring, 0);
3268 }
cbf61325
ASJ		 3269 /* unmap skb header data */
3270 dma_unmap_single(tx_ring->dev,
3271 dma_unmap_addr(tx_buf, dma),
3272 dma_unmap_len(tx_buf, len),
3273 DMA_TO_DEVICE);
49d7d933
ASJ		 3274 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3275 kfree(tx_buf->raw_buf);
cbf61325 3276
49d7d933
ASJ		 3277 tx_buf->raw_buf = NULL;
3278 tx_buf->tx_flags = 0;
3279 tx_buf->next_to_watch = NULL;
cbf61325 3280 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3281 tx_desc->buffer_addr = 0;
3282 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3283
49d7d933 3284 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3285 tx_buf++;
3286 tx_desc++;
3287 i++;
3288 if (unlikely(!i)) {
3289 i -= tx_ring->count;
3290 tx_buf = tx_ring->tx_bi;
3291 tx_desc = I40E_TX_DESC(tx_ring, 0);
3292 }
3293
3294 /* update budget accounting */
3295 budget--;
3296 } while (likely(budget));
3297
3298 i += tx_ring->count;
3299 tx_ring->next_to_clean = i;
3300
3301 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3302 i40e_irq_dynamic_enable(vsi,
3303 tx_ring->q_vector->v_idx + vsi->base_vector);
3304 }
3305 return budget > 0;
3306}
3307
3308/**
3309 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3310 * @irq: interrupt number
3311 * @data: pointer to a q_vector
3312 **/
3313static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3314{
3315 struct i40e_q_vector *q_vector = data;
3316 struct i40e_vsi *vsi;
3317
3318 if (!q_vector->tx.ring)
3319 return IRQ_HANDLED;
3320
3321 vsi = q_vector->tx.ring->vsi;
3322 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3323
3324 return IRQ_HANDLED;
3325}
3326
41c445ff 3327/**
cd0b6fa6 3328 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3329 * @vsi: the VSI being configured
3330 * @v_idx: vector index
cd0b6fa6 3331 * @qp_idx: queue pair index
41c445ff 3332 **/
cd0b6fa6 3333static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3334{
493fb300 3335 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3336 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3337 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3338
3339 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3340 tx_ring->next = q_vector->tx.ring;
3341 q_vector->tx.ring = tx_ring;
41c445ff 3342 q_vector->tx.count++;
cd0b6fa6
AD		 3343
3344 rx_ring->q_vector = q_vector;
3345 rx_ring->next = q_vector->rx.ring;
3346 q_vector->rx.ring = rx_ring;
3347 q_vector->rx.count++;
41c445ff
JB		 3348}
3349
3350/**
3351 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3352 * @vsi: the VSI being configured
3353 *
3354 * This function maps descriptor rings to the queue-specific vectors
3355 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3356 * one vector per queue pair, but on a constrained vector budget, we
3357 * group the queue pairs as "efficiently" as possible.
3358 **/
3359static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3360{
3361 int qp_remaining = vsi->num_queue_pairs;
3362 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3363 int num_ringpairs;
41c445ff
JB		 3364 int v_start = 0;
3365 int qp_idx = 0;
3366
3367 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3368 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3369 * It is also important to go through all the vectors available to be
3370 * sure that if we don't use all the vectors, that the remaining vectors
3371 * are cleared. This is especially important when decreasing the
3372 * number of queues in use.
41c445ff 3373 */
70114ec4 3374 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3375 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3376
3377 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3378
3379 q_vector->num_ringpairs = num_ringpairs;
3380
3381 q_vector->rx.count = 0;
3382 q_vector->tx.count = 0;
3383 q_vector->rx.ring = NULL;
3384 q_vector->tx.ring = NULL;
3385
3386 while (num_ringpairs--) {
3387 map_vector_to_qp(vsi, v_start, qp_idx);
3388 qp_idx++;
3389 qp_remaining--;
41c445ff
JB		 3390 }
3391 }
3392}
3393
3394/**
3395 * i40e_vsi_request_irq - Request IRQ from the OS
3396 * @vsi: the VSI being configured
3397 * @basename: name for the vector
3398 **/
3399static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3400{
3401 struct i40e_pf *pf = vsi->back;
3402 int err;
3403
3404 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3405 err = i40e_vsi_request_irq_msix(vsi, basename);
3406 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3407 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3408 pf->int_name, pf);
41c445ff
JB		 3409 else
3410 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3411 pf->int_name, pf);
41c445ff
JB		 3412
3413 if (err)
3414 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3415
3416 return err;
3417}
3418
3419#ifdef CONFIG_NET_POLL_CONTROLLER
3420/**
3421 * i40e_netpoll - A Polling 'interrupt'handler
3422 * @netdev: network interface device structure
3423 *
3424 * This is used by netconsole to send skbs without having to re-enable
3425 * interrupts. It's not called while the normal interrupt routine is executing.
3426 **/
38e00438
VD		 3427#ifdef I40E_FCOE
3428void i40e_netpoll(struct net_device *netdev)
3429#else
41c445ff 3430static void i40e_netpoll(struct net_device *netdev)
38e00438 3431#endif
41c445ff
JB		 3432{
3433 struct i40e_netdev_priv *np = netdev_priv(netdev);
3434 struct i40e_vsi *vsi = np->vsi;
3435 struct i40e_pf *pf = vsi->back;
3436 int i;
3437
3438 /* if interface is down do nothing */
3439 if (test_bit(__I40E_DOWN, &vsi->state))
3440 return;
3441
3442 pf->flags |= I40E_FLAG_IN_NETPOLL;
3443 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3444 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3445 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3446 } else {
3447 i40e_intr(pf->pdev->irq, netdev);
3448 }
3449 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3450}
3451#endif
3452
23527308
NP		 3453/**
3454 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3455 * @pf: the PF being configured
3456 * @pf_q: the PF queue
3457 * @enable: enable or disable state of the queue
3458 *
3459 * This routine will wait for the given Tx queue of the PF to reach the
3460 * enabled or disabled state.
3461 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3462 * multiple retries; else will return 0 in case of success.
3463 **/
3464static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3465{
3466 int i;
3467 u32 tx_reg;
3468
3469 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3470 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3471 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3472 break;
3473
f98a2006 3474 usleep_range(10, 20);
23527308
NP		 3475 }
3476 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3477 return -ETIMEDOUT;
3478
3479 return 0;
3480}
3481
41c445ff
JB		 3482/**
3483 * i40e_vsi_control_tx - Start or stop a VSI's rings
3484 * @vsi: the VSI being configured
3485 * @enable: start or stop the rings
3486 **/
3487static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3488{
3489 struct i40e_pf *pf = vsi->back;
3490 struct i40e_hw *hw = &pf->hw;
23527308 3491 int i, j, pf_q, ret = 0;
41c445ff
JB		 3492 u32 tx_reg;
3493
3494 pf_q = vsi->base_queue;
3495 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3496
3497 /* warn the TX unit of coming changes */
3498 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3499 if (!enable)
f98a2006 3500 usleep_range(10, 20);
351499ab 3501
6c5ef620 3502 for (j = 0; j < 50; j++) {
41c445ff 3503 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3504 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3505 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3506 break;
3507 usleep_range(1000, 2000);
3508 }
fda972f6 3509 /* Skip if the queue is already in the requested state */
7c122007 3510 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3511 continue;
41c445ff
JB		 3512
3513 /* turn on/off the queue */
c5c9eb9e
SN		 3514 if (enable) {
3515 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3516 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3517 } else {
41c445ff 3518 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3519 }
41c445ff
JB		 3520
3521 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3522 /* No waiting for the Tx queue to disable */
3523 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3524 continue;
41c445ff
JB		 3525
3526 /* wait for the change to finish */
23527308
NP		 3527 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3528 if (ret) {
3529 dev_info(&pf->pdev->dev,
3530 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3531 __func__, vsi->seid, pf_q,
3532 (enable ? "en" : "dis"));
3533 break;
41c445ff
JB		 3534 }
3535 }
3536
7134f9ce
JB		 3537 if (hw->revision_id == 0)
3538 mdelay(50);
23527308
NP		 3539 return ret;
3540}
3541
3542/**
3543 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3544 * @pf: the PF being configured
3545 * @pf_q: the PF queue
3546 * @enable: enable or disable state of the queue
3547 *
3548 * This routine will wait for the given Rx queue of the PF to reach the
3549 * enabled or disabled state.
3550 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3551 * multiple retries; else will return 0 in case of success.
3552 **/
3553static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3554{
3555 int i;
3556 u32 rx_reg;
3557
3558 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3559 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3560 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3561 break;
3562
f98a2006 3563 usleep_range(10, 20);
23527308
NP		 3564 }
3565 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3566 return -ETIMEDOUT;
7134f9ce 3567
41c445ff
JB		 3568 return 0;
3569}
3570
3571/**
3572 * i40e_vsi_control_rx - Start or stop a VSI's rings
3573 * @vsi: the VSI being configured
3574 * @enable: start or stop the rings
3575 **/
3576static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3577{
3578 struct i40e_pf *pf = vsi->back;
3579 struct i40e_hw *hw = &pf->hw;
23527308 3580 int i, j, pf_q, ret = 0;
41c445ff
JB		 3581 u32 rx_reg;
3582
3583 pf_q = vsi->base_queue;
3584 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3585 for (j = 0; j < 50; j++) {
41c445ff 3586 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3587 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3588 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3589 break;
3590 usleep_range(1000, 2000);
3591 }
41c445ff 3592
7c122007
CS		 3593 /* Skip if the queue is already in the requested state */
3594 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3595 continue;
41c445ff
JB		 3596
3597 /* turn on/off the queue */
3598 if (enable)
6c5ef620 3599 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3600 else
6c5ef620 3601 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3602 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3603
3604 /* wait for the change to finish */
23527308
NP		 3605 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3606 if (ret) {
3607 dev_info(&pf->pdev->dev,
3608 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3609 __func__, vsi->seid, pf_q,
3610 (enable ? "en" : "dis"));
3611 break;
41c445ff
JB		 3612 }
3613 }
3614
23527308 3615 return ret;
41c445ff
JB		 3616}
3617
3618/**
3619 * i40e_vsi_control_rings - Start or stop a VSI's rings
3620 * @vsi: the VSI being configured
3621 * @enable: start or stop the rings
3622 **/
fc18eaa0 3623int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3624{
3b867b28 3625 int ret = 0;
41c445ff
JB		 3626
3627 /* do rx first for enable and last for disable */
3628 if (request) {
3629 ret = i40e_vsi_control_rx(vsi, request);
3630 if (ret)
3631 return ret;
3632 ret = i40e_vsi_control_tx(vsi, request);
3633 } else {
3b867b28
ASJ		 3634 /* Ignore return value, we need to shutdown whatever we can */
3635 i40e_vsi_control_tx(vsi, request);
3636 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3637 }
3638
3639 return ret;
3640}
3641
3642/**
3643 * i40e_vsi_free_irq - Free the irq association with the OS
3644 * @vsi: the VSI being configured
3645 **/
3646static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3647{
3648 struct i40e_pf *pf = vsi->back;
3649 struct i40e_hw *hw = &pf->hw;
3650 int base = vsi->base_vector;
3651 u32 val, qp;
3652 int i;
3653
3654 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3655 if (!vsi->q_vectors)
3656 return;
3657
63741846
SN		 3658 if (!vsi->irqs_ready)
3659 return;
3660
3661 vsi->irqs_ready = false;
41c445ff
JB		 3662 for (i = 0; i < vsi->num_q_vectors; i++) {
3663 u16 vector = i + base;
3664
3665 /* free only the irqs that were actually requested */
78681b1f
SN		 3666 if (!vsi->q_vectors[i] ||
3667 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3668 continue;
3669
3670 /* clear the affinity_mask in the IRQ descriptor */
3671 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3672 NULL);
3673 free_irq(pf->msix_entries[vector].vector,
493fb300 3674 vsi->q_vectors[i]);
41c445ff
JB		 3675
3676 /* Tear down the interrupt queue link list
3677 *
3678 * We know that they come in pairs and always
3679 * the Rx first, then the Tx. To clear the
3680 * link list, stick the EOL value into the
3681 * next_q field of the registers.
3682 */
3683 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3684 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3685 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3686 val |= I40E_QUEUE_END_OF_LIST
3687 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3688 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3689
3690 while (qp != I40E_QUEUE_END_OF_LIST) {
3691 u32 next;
3692
3693 val = rd32(hw, I40E_QINT_RQCTL(qp));
3694
3695 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3696 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3697 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3698 I40E_QINT_RQCTL_INTEVENT_MASK);
3699
3700 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3701 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3702
3703 wr32(hw, I40E_QINT_RQCTL(qp), val);
3704
3705 val = rd32(hw, I40E_QINT_TQCTL(qp));
3706
3707 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3708 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3709
3710 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3711 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3712 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3713 I40E_QINT_TQCTL_INTEVENT_MASK);
3714
3715 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3716 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3717
3718 wr32(hw, I40E_QINT_TQCTL(qp), val);
3719 qp = next;
3720 }
3721 }
3722 } else {
3723 free_irq(pf->pdev->irq, pf);
3724
3725 val = rd32(hw, I40E_PFINT_LNKLST0);
3726 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3727 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3728 val |= I40E_QUEUE_END_OF_LIST
3729 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3730 wr32(hw, I40E_PFINT_LNKLST0, val);
3731
3732 val = rd32(hw, I40E_QINT_RQCTL(qp));
3733 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3734 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3735 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3736 I40E_QINT_RQCTL_INTEVENT_MASK);
3737
3738 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3739 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3740
3741 wr32(hw, I40E_QINT_RQCTL(qp), val);
3742
3743 val = rd32(hw, I40E_QINT_TQCTL(qp));
3744
3745 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3746 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3747 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3748 I40E_QINT_TQCTL_INTEVENT_MASK);
3749
3750 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3751 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3752
3753 wr32(hw, I40E_QINT_TQCTL(qp), val);
3754 }
3755}
3756
493fb300
AD		 3757/**
3758 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3759 * @vsi: the VSI being configured
3760 * @v_idx: Index of vector to be freed
3761 *
3762 * This function frees the memory allocated to the q_vector. In addition if
3763 * NAPI is enabled it will delete any references to the NAPI struct prior
3764 * to freeing the q_vector.
3765 **/
3766static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3767{
3768 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3769 struct i40e_ring *ring;
493fb300
AD		 3770
3771 if (!q_vector)
3772 return;
3773
3774 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3775 i40e_for_each_ring(ring, q_vector->tx)
3776 ring->q_vector = NULL;
3777
3778 i40e_for_each_ring(ring, q_vector->rx)
3779 ring->q_vector = NULL;
493fb300
AD		 3780
3781 /* only VSI w/ an associated netdev is set up w/ NAPI */
3782 if (vsi->netdev)
3783 netif_napi_del(&q_vector->napi);
3784
3785 vsi->q_vectors[v_idx] = NULL;
3786
3787 kfree_rcu(q_vector, rcu);
3788}
3789
41c445ff
JB		 3790/**
3791 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3792 * @vsi: the VSI being un-configured
3793 *
3794 * This frees the memory allocated to the q_vectors and
3795 * deletes references to the NAPI struct.
3796 **/
3797static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3798{
3799 int v_idx;
3800
493fb300
AD		 3801 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3802 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3803}
3804
3805/**
3806 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3807 * @pf: board private structure
3808 **/
3809static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3810{
3811 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3812 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3813 pci_disable_msix(pf->pdev);
3814 kfree(pf->msix_entries);
3815 pf->msix_entries = NULL;
3816 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3817 pci_disable_msi(pf->pdev);
3818 }
3819 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3820}
3821
3822/**
3823 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3824 * @pf: board private structure
3825 *
3826 * We go through and clear interrupt specific resources and reset the structure
3827 * to pre-load conditions
3828 **/
3829static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3830{
3831 int i;
3832
3833 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3834 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3835 if (pf->vsi[i])
3836 i40e_vsi_free_q_vectors(pf->vsi[i]);
3837 i40e_reset_interrupt_capability(pf);
3838}
3839
3840/**
3841 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3842 * @vsi: the VSI being configured
3843 **/
3844static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3845{
3846 int q_idx;
3847
3848 if (!vsi->netdev)
3849 return;
3850
3851 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3852 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3853}
3854
3855/**
3856 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3857 * @vsi: the VSI being configured
3858 **/
3859static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3860{
3861 int q_idx;
3862
3863 if (!vsi->netdev)
3864 return;
3865
3866 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3867 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3868}
3869
90ef8d47
SN		 3870/**
3871 * i40e_vsi_close - Shut down a VSI
3872 * @vsi: the vsi to be quelled
3873 **/
3874static void i40e_vsi_close(struct i40e_vsi *vsi)
3875{
3876 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3877 i40e_down(vsi);
3878 i40e_vsi_free_irq(vsi);
3879 i40e_vsi_free_tx_resources(vsi);
3880 i40e_vsi_free_rx_resources(vsi);
3881}
3882
41c445ff
JB		 3883/**
3884 * i40e_quiesce_vsi - Pause a given VSI
3885 * @vsi: the VSI being paused
3886 **/
3887static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3888{
3889 if (test_bit(__I40E_DOWN, &vsi->state))
3890 return;
3891
d341b7a5
NP		 3892 /* No need to disable FCoE VSI when Tx suspended */
3893 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
3894 vsi->type == I40E_VSI_FCOE) {
3895 dev_dbg(&vsi->back->pdev->dev,
3896 "%s: VSI seid %d skipping FCoE VSI disable\n",
3897 __func__, vsi->seid);
3898 return;
3899 }
3900
41c445ff
JB		 3901 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3902 if (vsi->netdev && netif_running(vsi->netdev)) {
3903 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3904 } else {
90ef8d47 3905 i40e_vsi_close(vsi);
41c445ff
JB		 3906 }
3907}
3908
3909/**
3910 * i40e_unquiesce_vsi - Resume a given VSI
3911 * @vsi: the VSI being resumed
3912 **/
3913static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3914{
3915 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3916 return;
3917
3918 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3919 if (vsi->netdev && netif_running(vsi->netdev))
3920 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3921 else
8276f757 3922 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3923}
3924
3925/**
3926 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3927 * @pf: the PF
3928 **/
3929static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3930{
3931 int v;
3932
505682cd 3933 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3934 if (pf->vsi[v])
3935 i40e_quiesce_vsi(pf->vsi[v]);
3936 }
3937}
3938
3939/**
3940 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3941 * @pf: the PF
3942 **/
3943static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3944{
3945 int v;
3946
505682cd 3947 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3948 if (pf->vsi[v])
3949 i40e_unquiesce_vsi(pf->vsi[v]);
3950 }
3951}
3952
69129dc3
NP		 3953#ifdef CONFIG_I40E_DCB
3954/**
3955 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
3956 * @vsi: the VSI being configured
3957 *
3958 * This function waits for the given VSI's Tx queues to be disabled.
3959 **/
3960static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
3961{
3962 struct i40e_pf *pf = vsi->back;
3963 int i, pf_q, ret;
3964
3965 pf_q = vsi->base_queue;
3966 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3967 /* Check and wait for the disable status of the queue */
3968 ret = i40e_pf_txq_wait(pf, pf_q, false);
3969 if (ret) {
3970 dev_info(&pf->pdev->dev,
3971 "%s: VSI seid %d Tx ring %d disable timeout\n",
3972 __func__, vsi->seid, pf_q);
3973 return ret;
3974 }
3975 }
3976
3977 return 0;
3978}
3979
3980/**
3981 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
3982 * @pf: the PF
3983 *
3984 * This function waits for the Tx queues to be in disabled state for all the
3985 * VSIs that are managed by this PF.
3986 **/
3987static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
3988{
3989 int v, ret = 0;
3990
3991 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 3992 /* No need to wait for FCoE VSI queues */
3993 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 3994 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
3995 if (ret)
3996 break;
3997 }
3998 }
3999
4000 return ret;
4001}
4002
4003#endif
63d7e5a4
NP		 4004/**
4005 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
4006 * @pf: pointer to pf
4007 *
4008 * Get TC map for ISCSI PF type that will include iSCSI TC
4009 * and LAN TC.
4010 **/
4011static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4012{
4013 struct i40e_dcb_app_priority_table app;
4014 struct i40e_hw *hw = &pf->hw;
4015 u8 enabled_tc = 1; /* TC0 is always enabled */
4016 u8 tc, i;
4017 /* Get the iSCSI APP TLV */
4018 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4019
4020 for (i = 0; i < dcbcfg->numapps; i++) {
4021 app = dcbcfg->app[i];
4022 if (app.selector == I40E_APP_SEL_TCPIP &&
4023 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4024 tc = dcbcfg->etscfg.prioritytable[app.priority];
4025 enabled_tc |= (1 << tc);
4026 break;
4027 }
4028 }
4029
4030 return enabled_tc;
4031}
4032
41c445ff
JB		 4033/**
4034 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4035 * @dcbcfg: the corresponding DCBx configuration structure
4036 *
4037 * Return the number of TCs from given DCBx configuration
4038 **/
4039static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4040{
078b5876
JB		 4041 u8 num_tc = 0;
4042 int i;
41c445ff
JB		 4043
4044 /* Scan the ETS Config Priority Table to find
4045 * traffic class enabled for a given priority
4046 * and use the traffic class index to get the
4047 * number of traffic classes enabled
4048 */
4049 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4050 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4051 num_tc = dcbcfg->etscfg.prioritytable[i];
4052 }
4053
4054 /* Traffic class index starts from zero so
4055 * increment to return the actual count
4056 */
078b5876 4057 return num_tc + 1;
41c445ff
JB		 4058}
4059
4060/**
4061 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4062 * @dcbcfg: the corresponding DCBx configuration structure
4063 *
4064 * Query the current DCB configuration and return the number of
4065 * traffic classes enabled from the given DCBX config
4066 **/
4067static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4068{
4069 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4070 u8 enabled_tc = 1;
4071 u8 i;
4072
4073 for (i = 0; i < num_tc; i++)
4074 enabled_tc |= 1 << i;
4075
4076 return enabled_tc;
4077}
4078
4079/**
4080 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4081 * @pf: PF being queried
4082 *
4083 * Return number of traffic classes enabled for the given PF
4084 **/
4085static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4086{
4087 struct i40e_hw *hw = &pf->hw;
4088 u8 i, enabled_tc;
4089 u8 num_tc = 0;
4090 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4091
4092 /* If DCB is not enabled then always in single TC */
4093 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4094 return 1;
4095
63d7e5a4
NP		 4096 /* SFP mode will be enabled for all TCs on port */
4097 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4098 return i40e_dcb_get_num_tc(dcbcfg);
4099
41c445ff 4100 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4101 if (pf->hw.func_caps.iscsi)
4102 enabled_tc = i40e_get_iscsi_tc_map(pf);
4103 else
41c445ff 4104 enabled_tc = pf->hw.func_caps.enabled_tcmap;
41c445ff 4105
63d7e5a4
NP		 4106 /* At least have TC0 */
4107 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4108 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4109 if (enabled_tc & (1 << i))
4110 num_tc++;
4111 }
4112 return num_tc;
41c445ff
JB		 4113}
4114
4115/**
4116 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4117 * @pf: PF being queried
4118 *
4119 * Return a bitmap for first enabled traffic class for this PF.
4120 **/
4121static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4122{
4123 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4124 u8 i = 0;
4125
4126 if (!enabled_tc)
4127 return 0x1; /* TC0 */
4128
4129 /* Find the first enabled TC */
4130 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4131 if (enabled_tc & (1 << i))
4132 break;
4133 }
4134
4135 return 1 << i;
4136}
4137
4138/**
4139 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4140 * @pf: PF being queried
4141 *
4142 * Return a bitmap for enabled traffic classes for this PF.
4143 **/
4144static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4145{
4146 /* If DCB is not enabled for this PF then just return default TC */
4147 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4148 return i40e_pf_get_default_tc(pf);
4149
41c445ff 4150 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4151 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4152 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4153
4154 /* MPF enabled and iSCSI PF type */
4155 if (pf->hw.func_caps.iscsi)
4156 return i40e_get_iscsi_tc_map(pf);
4157 else
4158 return pf->hw.func_caps.enabled_tcmap;
41c445ff
JB		 4159}
4160
4161/**
4162 * i40e_vsi_get_bw_info - Query VSI BW Information
4163 * @vsi: the VSI being queried
4164 *
4165 * Returns 0 on success, negative value on failure
4166 **/
4167static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4168{
4169 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4170 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4171 struct i40e_pf *pf = vsi->back;
4172 struct i40e_hw *hw = &pf->hw;
dcae29be 4173 i40e_status aq_ret;
41c445ff 4174 u32 tc_bw_max;
41c445ff
JB		 4175 int i;
4176
4177 /* Get the VSI level BW configuration */
dcae29be
JB		 4178 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4179 if (aq_ret) {
41c445ff
JB		 4180 dev_info(&pf->pdev->dev,
4181 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4182 aq_ret, pf->hw.aq.asq_last_status);
4183 return -EINVAL;
41c445ff
JB		 4184 }
4185
4186 /* Get the VSI level BW configuration per TC */
dcae29be 4187 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4188 NULL);
dcae29be 4189 if (aq_ret) {
41c445ff
JB		 4190 dev_info(&pf->pdev->dev,
4191 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4192 aq_ret, pf->hw.aq.asq_last_status);
4193 return -EINVAL;
41c445ff
JB		 4194 }
4195
4196 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4197 dev_info(&pf->pdev->dev,
4198 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4199 bw_config.tc_valid_bits,
4200 bw_ets_config.tc_valid_bits);
4201 /* Still continuing */
4202 }
4203
4204 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4205 vsi->bw_max_quanta = bw_config.max_bw;
4206 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4207 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4208 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4209 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4210 vsi->bw_ets_limit_credits[i] =
4211 le16_to_cpu(bw_ets_config.credits[i]);
4212 /* 3 bits out of 4 for each TC */
4213 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4214 }
078b5876 4215
dcae29be 4216 return 0;
41c445ff
JB		 4217}
4218
4219/**
4220 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4221 * @vsi: the VSI being configured
4222 * @enabled_tc: TC bitmap
4223 * @bw_credits: BW shared credits per TC
4224 *
4225 * Returns 0 on success, negative value on failure
4226 **/
dcae29be 4227static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4228 u8 *bw_share)
4229{
4230 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4231 i40e_status aq_ret;
4232 int i;
41c445ff
JB		 4233
4234 bw_data.tc_valid_bits = enabled_tc;
4235 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4236 bw_data.tc_bw_credits[i] = bw_share[i];
4237
dcae29be
JB		 4238 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4239 NULL);
4240 if (aq_ret) {
41c445ff 4241 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4242 "AQ command Config VSI BW allocation per TC failed = %d\n",
4243 vsi->back->hw.aq.asq_last_status);
dcae29be 4244 return -EINVAL;
41c445ff
JB		 4245 }
4246
4247 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4248 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4249
dcae29be 4250 return 0;
41c445ff
JB		 4251}
4252
4253/**
4254 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4255 * @vsi: the VSI being configured
4256 * @enabled_tc: TC map to be enabled
4257 *
4258 **/
4259static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4260{
4261 struct net_device *netdev = vsi->netdev;
4262 struct i40e_pf *pf = vsi->back;
4263 struct i40e_hw *hw = &pf->hw;
4264 u8 netdev_tc = 0;
4265 int i;
4266 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4267
4268 if (!netdev)
4269 return;
4270
4271 if (!enabled_tc) {
4272 netdev_reset_tc(netdev);
4273 return;
4274 }
4275
4276 /* Set up actual enabled TCs on the VSI */
4277 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4278 return;
4279
4280 /* set per TC queues for the VSI */
4281 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4282 /* Only set TC queues for enabled tcs
4283 *
4284 * e.g. For a VSI that has TC0 and TC3 enabled the
4285 * enabled_tc bitmap would be 0x00001001; the driver
4286 * will set the numtc for netdev as 2 that will be
4287 * referenced by the netdev layer as TC 0 and 1.
4288 */
4289 if (vsi->tc_config.enabled_tc & (1 << i))
4290 netdev_set_tc_queue(netdev,
4291 vsi->tc_config.tc_info[i].netdev_tc,
4292 vsi->tc_config.tc_info[i].qcount,
4293 vsi->tc_config.tc_info[i].qoffset);
4294 }
4295
4296 /* Assign UP2TC map for the VSI */
4297 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4298 /* Get the actual TC# for the UP */
4299 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4300 /* Get the mapped netdev TC# for the UP */
4301 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4302 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4303 }
4304}
4305
4306/**
4307 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4308 * @vsi: the VSI being configured
4309 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4310 **/
4311static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4312 struct i40e_vsi_context *ctxt)
4313{
4314 /* copy just the sections touched not the entire info
4315 * since not all sections are valid as returned by
4316 * update vsi params
4317 */
4318 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4319 memcpy(&vsi->info.queue_mapping,
4320 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4321 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4322 sizeof(vsi->info.tc_mapping));
4323}
4324
4325/**
4326 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4327 * @vsi: VSI to be configured
4328 * @enabled_tc: TC bitmap
4329 *
4330 * This configures a particular VSI for TCs that are mapped to the
4331 * given TC bitmap. It uses default bandwidth share for TCs across
4332 * VSIs to configure TC for a particular VSI.
4333 *
4334 * NOTE:
4335 * It is expected that the VSI queues have been quisced before calling
4336 * this function.
4337 **/
4338static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4339{
4340 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4341 struct i40e_vsi_context ctxt;
4342 int ret = 0;
4343 int i;
4344
4345 /* Check if enabled_tc is same as existing or new TCs */
4346 if (vsi->tc_config.enabled_tc == enabled_tc)
4347 return ret;
4348
4349 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4350 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4351 if (enabled_tc & (1 << i))
4352 bw_share[i] = 1;
4353 }
4354
4355 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4356 if (ret) {
4357 dev_info(&vsi->back->pdev->dev,
4358 "Failed configuring TC map %d for VSI %d\n",
4359 enabled_tc, vsi->seid);
4360 goto out;
4361 }
4362
4363 /* Update Queue Pairs Mapping for currently enabled UPs */
4364 ctxt.seid = vsi->seid;
4365 ctxt.pf_num = vsi->back->hw.pf_id;
4366 ctxt.vf_num = 0;
4367 ctxt.uplink_seid = vsi->uplink_seid;
4368 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4369 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4370
4371 /* Update the VSI after updating the VSI queue-mapping information */
4372 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4373 if (ret) {
4374 dev_info(&vsi->back->pdev->dev,
4375 "update vsi failed, aq_err=%d\n",
4376 vsi->back->hw.aq.asq_last_status);
4377 goto out;
4378 }
4379 /* update the local VSI info with updated queue map */
4380 i40e_vsi_update_queue_map(vsi, &ctxt);
4381 vsi->info.valid_sections = 0;
4382
4383 /* Update current VSI BW information */
4384 ret = i40e_vsi_get_bw_info(vsi);
4385 if (ret) {
4386 dev_info(&vsi->back->pdev->dev,
4387 "Failed updating vsi bw info, aq_err=%d\n",
4388 vsi->back->hw.aq.asq_last_status);
4389 goto out;
4390 }
4391
4392 /* Update the netdev TC setup */
4393 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4394out:
4395 return ret;
4396}
4397
4e3b35b0
NP		 4398/**
4399 * i40e_veb_config_tc - Configure TCs for given VEB
4400 * @veb: given VEB
4401 * @enabled_tc: TC bitmap
4402 *
4403 * Configures given TC bitmap for VEB (switching) element
4404 **/
4405int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4406{
4407 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4408 struct i40e_pf *pf = veb->pf;
4409 int ret = 0;
4410 int i;
4411
4412 /* No TCs or already enabled TCs just return */
4413 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4414 return ret;
4415
4416 bw_data.tc_valid_bits = enabled_tc;
4417 /* bw_data.absolute_credits is not set (relative) */
4418
4419 /* Enable ETS TCs with equal BW Share for now */
4420 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4421 if (enabled_tc & (1 << i))
4422 bw_data.tc_bw_share_credits[i] = 1;
4423 }
4424
4425 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4426 &bw_data, NULL);
4427 if (ret) {
4428 dev_info(&pf->pdev->dev,
4429 "veb bw config failed, aq_err=%d\n",
4430 pf->hw.aq.asq_last_status);
4431 goto out;
4432 }
4433
4434 /* Update the BW information */
4435 ret = i40e_veb_get_bw_info(veb);
4436 if (ret) {
4437 dev_info(&pf->pdev->dev,
4438 "Failed getting veb bw config, aq_err=%d\n",
4439 pf->hw.aq.asq_last_status);
4440 }
4441
4442out:
4443 return ret;
4444}
4445
4446#ifdef CONFIG_I40E_DCB
4447/**
4448 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4449 * @pf: PF struct
4450 *
4451 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4452 * the caller would've quiesce all the VSIs before calling
4453 * this function
4454 **/
4455static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4456{
4457 u8 tc_map = 0;
4458 int ret;
4459 u8 v;
4460
4461 /* Enable the TCs available on PF to all VEBs */
4462 tc_map = i40e_pf_get_tc_map(pf);
4463 for (v = 0; v < I40E_MAX_VEB; v++) {
4464 if (!pf->veb[v])
4465 continue;
4466 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4467 if (ret) {
4468 dev_info(&pf->pdev->dev,
4469 "Failed configuring TC for VEB seid=%d\n",
4470 pf->veb[v]->seid);
4471 /* Will try to configure as many components */
4472 }
4473 }
4474
4475 /* Update each VSI */
505682cd 4476 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4477 if (!pf->vsi[v])
4478 continue;
4479
4480 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4481#ifdef I40E_FCOE
4482 * - For FCoE VSI only enable the TC configured
4483 * as per the APP TLV
4484#endif
4e3b35b0
NP		 4485 * - For all others keep them at TC0 for now
4486 */
4487 if (v == pf->lan_vsi)
4488 tc_map = i40e_pf_get_tc_map(pf);
4489 else
4490 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4491#ifdef I40E_FCOE
4492 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4493 tc_map = i40e_get_fcoe_tc_map(pf);
4494#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4495
4496 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4497 if (ret) {
4498 dev_info(&pf->pdev->dev,
4499 "Failed configuring TC for VSI seid=%d\n",
4500 pf->vsi[v]->seid);
4501 /* Will try to configure as many components */
4502 } else {
0672a091
NP		 4503 /* Re-configure VSI vectors based on updated TC map */
4504 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4505 if (pf->vsi[v]->netdev)
4506 i40e_dcbnl_set_all(pf->vsi[v]);
4507 }
4508 }
4509}
4510
2fd75f31
NP		 4511/**
4512 * i40e_resume_port_tx - Resume port Tx
4513 * @pf: PF struct
4514 *
4515 * Resume a port's Tx and issue a PF reset in case of failure to
4516 * resume.
4517 **/
4518static int i40e_resume_port_tx(struct i40e_pf *pf)
4519{
4520 struct i40e_hw *hw = &pf->hw;
4521 int ret;
4522
4523 ret = i40e_aq_resume_port_tx(hw, NULL);
4524 if (ret) {
4525 dev_info(&pf->pdev->dev,
4526 "AQ command Resume Port Tx failed = %d\n",
4527 pf->hw.aq.asq_last_status);
4528 /* Schedule PF reset to recover */
4529 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4530 i40e_service_event_schedule(pf);
4531 }
4532
4533 return ret;
4534}
4535
4e3b35b0
NP		 4536/**
4537 * i40e_init_pf_dcb - Initialize DCB configuration
4538 * @pf: PF being configured
4539 *
4540 * Query the current DCB configuration and cache it
4541 * in the hardware structure
4542 **/
4543static int i40e_init_pf_dcb(struct i40e_pf *pf)
4544{
4545 struct i40e_hw *hw = &pf->hw;
4546 int err = 0;
4547
4e3b35b0
NP		 4548 /* Get the initial DCB configuration */
4549 err = i40e_init_dcb(hw);
4550 if (!err) {
4551 /* Device/Function is not DCBX capable */
4552 if ((!hw->func_caps.dcb) ||
4553 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4554 dev_info(&pf->pdev->dev,
4555 "DCBX offload is not supported or is disabled for this PF.\n");
4556
4557 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4558 goto out;
4559
4560 } else {
4561 /* When status is not DISABLED then DCBX in FW */
4562 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4563 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4564
4565 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4566 /* Enable DCB tagging only when more than one TC */
4567 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4568 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4569 dev_dbg(&pf->pdev->dev,
4570 "DCBX offload is supported for this PF.\n");
4e3b35b0 4571 }
014269ff 4572 } else {
aebfc816
SN		 4573 dev_info(&pf->pdev->dev,
4574 "AQ Querying DCB configuration failed: aq_err %d\n",
014269ff 4575 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4576 }
4577
4578out:
4579 return err;
4580}
4581#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4582#define SPEED_SIZE 14
4583#define FC_SIZE 8
4584/**
4585 * i40e_print_link_message - print link up or down
4586 * @vsi: the VSI for which link needs a message
4587 */
4588static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4589{
4590 char speed[SPEED_SIZE] = "Unknown";
4591 char fc[FC_SIZE] = "RX/TX";
4592
4593 if (!isup) {
4594 netdev_info(vsi->netdev, "NIC Link is Down\n");
4595 return;
4596 }
4597
148c2d80
GR		 4598 /* Warn user if link speed on NPAR enabled partition is not at
4599 * least 10GB
4600 */
4601 if (vsi->back->hw.func_caps.npar_enable &&
4602 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4603 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4604 netdev_warn(vsi->netdev,
4605 "The partition detected link speed that is less than 10Gbps\n");
4606
cf05ed08
JB		 4607 switch (vsi->back->hw.phy.link_info.link_speed) {
4608 case I40E_LINK_SPEED_40GB:
35a7d804 4609 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4610 break;
4611 case I40E_LINK_SPEED_10GB:
35a7d804 4612 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4613 break;
4614 case I40E_LINK_SPEED_1GB:
35a7d804 4615 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4616 break;
5960d33f
MW		 4617 case I40E_LINK_SPEED_100MB:
4618 strncpy(speed, "100 Mbps", SPEED_SIZE);
4619 break;
cf05ed08
JB		 4620 default:
4621 break;
4622 }
4623
4624 switch (vsi->back->hw.fc.current_mode) {
4625 case I40E_FC_FULL:
35a7d804 4626 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4627 break;
4628 case I40E_FC_TX_PAUSE:
35a7d804 4629 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4630 break;
4631 case I40E_FC_RX_PAUSE:
35a7d804 4632 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4633 break;
4634 default:
35a7d804 4635 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4636 break;
4637 }
4638
4639 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4640 speed, fc);
4641}
4e3b35b0 4642
41c445ff
JB		 4643/**
4644 * i40e_up_complete - Finish the last steps of bringing up a connection
4645 * @vsi: the VSI being configured
4646 **/
4647static int i40e_up_complete(struct i40e_vsi *vsi)
4648{
4649 struct i40e_pf *pf = vsi->back;
4650 int err;
4651
4652 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4653 i40e_vsi_configure_msix(vsi);
4654 else
4655 i40e_configure_msi_and_legacy(vsi);
4656
4657 /* start rings */
4658 err = i40e_vsi_control_rings(vsi, true);
4659 if (err)
4660 return err;
4661
4662 clear_bit(__I40E_DOWN, &vsi->state);
4663 i40e_napi_enable_all(vsi);
4664 i40e_vsi_enable_irq(vsi);
4665
4666 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4667 (vsi->netdev)) {
cf05ed08 4668 i40e_print_link_message(vsi, true);
41c445ff
JB		 4669 netif_tx_start_all_queues(vsi->netdev);
4670 netif_carrier_on(vsi->netdev);
6d779b41 4671 } else if (vsi->netdev) {
cf05ed08 4672 i40e_print_link_message(vsi, false);
7b592f61
CW		 4673 /* need to check for qualified module here*/
4674 if ((pf->hw.phy.link_info.link_info &
4675 I40E_AQ_MEDIA_AVAILABLE) &&
4676 (!(pf->hw.phy.link_info.an_info &
4677 I40E_AQ_QUALIFIED_MODULE)))
4678 netdev_err(vsi->netdev,
4679 "the driver failed to link because an unqualified module was detected.");
41c445ff 4680 }
ca64fa4e
ASJ		 4681
4682 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4683 if (vsi->type == I40E_VSI_FDIR) {
4684 /* reset fd counters */
4685 pf->fd_add_err = pf->fd_atr_cnt = 0;
4686 if (pf->fd_tcp_rule > 0) {
4687 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4688 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4689 pf->fd_tcp_rule = 0;
4690 }
ca64fa4e 4691 i40e_fdir_filter_restore(vsi);
1e1be8f6 4692 }
41c445ff
JB		 4693 i40e_service_event_schedule(pf);
4694
4695 return 0;
4696}
4697
4698/**
4699 * i40e_vsi_reinit_locked - Reset the VSI
4700 * @vsi: the VSI being configured
4701 *
4702 * Rebuild the ring structs after some configuration
4703 * has changed, e.g. MTU size.
4704 **/
4705static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4706{
4707 struct i40e_pf *pf = vsi->back;
4708
4709 WARN_ON(in_interrupt());
4710 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4711 usleep_range(1000, 2000);
4712 i40e_down(vsi);
4713
4714 /* Give a VF some time to respond to the reset. The
4715 * two second wait is based upon the watchdog cycle in
4716 * the VF driver.
4717 */
4718 if (vsi->type == I40E_VSI_SRIOV)
4719 msleep(2000);
4720 i40e_up(vsi);
4721 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4722}
4723
4724/**
4725 * i40e_up - Bring the connection back up after being down
4726 * @vsi: the VSI being configured
4727 **/
4728int i40e_up(struct i40e_vsi *vsi)
4729{
4730 int err;
4731
4732 err = i40e_vsi_configure(vsi);
4733 if (!err)
4734 err = i40e_up_complete(vsi);
4735
4736 return err;
4737}
4738
4739/**
4740 * i40e_down - Shutdown the connection processing
4741 * @vsi: the VSI being stopped
4742 **/
4743void i40e_down(struct i40e_vsi *vsi)
4744{
4745 int i;
4746
4747 /* It is assumed that the caller of this function
4748 * sets the vsi->state __I40E_DOWN bit.
4749 */
4750 if (vsi->netdev) {
4751 netif_carrier_off(vsi->netdev);
4752 netif_tx_disable(vsi->netdev);
4753 }
4754 i40e_vsi_disable_irq(vsi);
4755 i40e_vsi_control_rings(vsi, false);
4756 i40e_napi_disable_all(vsi);
4757
4758 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4759 i40e_clean_tx_ring(vsi->tx_rings[i]);
4760 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4761 }
4762}
4763
4764/**
4765 * i40e_setup_tc - configure multiple traffic classes
4766 * @netdev: net device to configure
4767 * @tc: number of traffic classes to enable
4768 **/
38e00438
VD		 4769#ifdef I40E_FCOE
4770int i40e_setup_tc(struct net_device *netdev, u8 tc)
4771#else
41c445ff 4772static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4773#endif
41c445ff
JB		 4774{
4775 struct i40e_netdev_priv *np = netdev_priv(netdev);
4776 struct i40e_vsi *vsi = np->vsi;
4777 struct i40e_pf *pf = vsi->back;
4778 u8 enabled_tc = 0;
4779 int ret = -EINVAL;
4780 int i;
4781
4782 /* Check if DCB enabled to continue */
4783 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4784 netdev_info(netdev, "DCB is not enabled for adapter\n");
4785 goto exit;
4786 }
4787
4788 /* Check if MFP enabled */
4789 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4790 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4791 goto exit;
4792 }
4793
4794 /* Check whether tc count is within enabled limit */
4795 if (tc > i40e_pf_get_num_tc(pf)) {
4796 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4797 goto exit;
4798 }
4799
4800 /* Generate TC map for number of tc requested */
4801 for (i = 0; i < tc; i++)
4802 enabled_tc |= (1 << i);
4803
4804 /* Requesting same TC configuration as already enabled */
4805 if (enabled_tc == vsi->tc_config.enabled_tc)
4806 return 0;
4807
4808 /* Quiesce VSI queues */
4809 i40e_quiesce_vsi(vsi);
4810
4811 /* Configure VSI for enabled TCs */
4812 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4813 if (ret) {
4814 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4815 vsi->seid);
4816 goto exit;
4817 }
4818
4819 /* Unquiesce VSI */
4820 i40e_unquiesce_vsi(vsi);
4821
4822exit:
4823 return ret;
4824}
4825
4826/**
4827 * i40e_open - Called when a network interface is made active
4828 * @netdev: network interface device structure
4829 *
4830 * The open entry point is called when a network interface is made
4831 * active by the system (IFF_UP). At this point all resources needed
4832 * for transmit and receive operations are allocated, the interrupt
4833 * handler is registered with the OS, the netdev watchdog subtask is
4834 * enabled, and the stack is notified that the interface is ready.
4835 *
4836 * Returns 0 on success, negative value on failure
4837 **/
38e00438 4838int i40e_open(struct net_device *netdev)
41c445ff
JB		 4839{
4840 struct i40e_netdev_priv *np = netdev_priv(netdev);
4841 struct i40e_vsi *vsi = np->vsi;
4842 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4843 int err;
4844
4eb3f768
SN		 4845 /* disallow open during test or if eeprom is broken */
4846 if (test_bit(__I40E_TESTING, &pf->state) ||
4847 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4848 return -EBUSY;
4849
4850 netif_carrier_off(netdev);
4851
6c167f58
EK		 4852 err = i40e_vsi_open(vsi);
4853 if (err)
4854 return err;
4855
059dab69
JB		 4856 /* configure global TSO hardware offload settings */
4857 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4858 TCP_FLAG_FIN) >> 16);
4859 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4860 TCP_FLAG_FIN |
4861 TCP_FLAG_CWR) >> 16);
4862 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4863
6c167f58
EK		 4864#ifdef CONFIG_I40E_VXLAN
4865 vxlan_get_rx_port(netdev);
4866#endif
4867
4868 return 0;
4869}
4870
4871/**
4872 * i40e_vsi_open -
4873 * @vsi: the VSI to open
4874 *
4875 * Finish initialization of the VSI.
4876 *
4877 * Returns 0 on success, negative value on failure
4878 **/
4879int i40e_vsi_open(struct i40e_vsi *vsi)
4880{
4881 struct i40e_pf *pf = vsi->back;
b294ac70 4882 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 4883 int err;
4884
41c445ff
JB		 4885 /* allocate descriptors */
4886 err = i40e_vsi_setup_tx_resources(vsi);
4887 if (err)
4888 goto err_setup_tx;
4889 err = i40e_vsi_setup_rx_resources(vsi);
4890 if (err)
4891 goto err_setup_rx;
4892
4893 err = i40e_vsi_configure(vsi);
4894 if (err)
4895 goto err_setup_rx;
4896
c22e3c6c
SN		 4897 if (vsi->netdev) {
4898 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4899 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4900 err = i40e_vsi_request_irq(vsi, int_name);
4901 if (err)
4902 goto err_setup_rx;
41c445ff 4903
c22e3c6c
SN		 4904 /* Notify the stack of the actual queue counts. */
4905 err = netif_set_real_num_tx_queues(vsi->netdev,
4906 vsi->num_queue_pairs);
4907 if (err)
4908 goto err_set_queues;
25946ddb 4909
c22e3c6c
SN		 4910 err = netif_set_real_num_rx_queues(vsi->netdev,
4911 vsi->num_queue_pairs);
4912 if (err)
4913 goto err_set_queues;
8a9eb7d3
SN		 4914
4915 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 4916 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 4917 dev_driver_string(&pf->pdev->dev),
4918 dev_name(&pf->pdev->dev));
8a9eb7d3 4919 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 4920
c22e3c6c 4921 } else {
ce9ccb17 4922 err = -EINVAL;
6c167f58
EK		 4923 goto err_setup_rx;
4924 }
25946ddb 4925
41c445ff
JB		 4926 err = i40e_up_complete(vsi);
4927 if (err)
4928 goto err_up_complete;
4929
41c445ff
JB		 4930 return 0;
4931
4932err_up_complete:
4933 i40e_down(vsi);
25946ddb 4934err_set_queues:
41c445ff
JB		 4935 i40e_vsi_free_irq(vsi);
4936err_setup_rx:
4937 i40e_vsi_free_rx_resources(vsi);
4938err_setup_tx:
4939 i40e_vsi_free_tx_resources(vsi);
4940 if (vsi == pf->vsi[pf->lan_vsi])
4941 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4942
4943 return err;
4944}
4945
17a73f6b
JG		 4946/**
4947 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4948 * @pf: Pointer to pf
4949 *
4950 * This function destroys the hlist where all the Flow Director
4951 * filters were saved.
4952 **/
4953static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4954{
4955 struct i40e_fdir_filter *filter;
4956 struct hlist_node *node2;
4957
4958 hlist_for_each_entry_safe(filter, node2,
4959 &pf->fdir_filter_list, fdir_node) {
4960 hlist_del(&filter->fdir_node);
4961 kfree(filter);
4962 }
4963 pf->fdir_pf_active_filters = 0;
4964}
4965
41c445ff
JB		 4966/**
4967 * i40e_close - Disables a network interface
4968 * @netdev: network interface device structure
4969 *
4970 * The close entry point is called when an interface is de-activated
4971 * by the OS. The hardware is still under the driver's control, but
4972 * this netdev interface is disabled.
4973 *
4974 * Returns 0, this is not allowed to fail
4975 **/
38e00438
VD		 4976#ifdef I40E_FCOE
4977int i40e_close(struct net_device *netdev)
4978#else
41c445ff 4979static int i40e_close(struct net_device *netdev)
38e00438 4980#endif
41c445ff
JB		 4981{
4982 struct i40e_netdev_priv *np = netdev_priv(netdev);
4983 struct i40e_vsi *vsi = np->vsi;
4984
90ef8d47 4985 i40e_vsi_close(vsi);
41c445ff
JB		 4986
4987 return 0;
4988}
4989
4990/**
4991 * i40e_do_reset - Start a PF or Core Reset sequence
4992 * @pf: board private structure
4993 * @reset_flags: which reset is requested
4994 *
4995 * The essential difference in resets is that the PF Reset
4996 * doesn't clear the packet buffers, doesn't reset the PE
4997 * firmware, and doesn't bother the other PFs on the chip.
4998 **/
4999void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5000{
5001 u32 val;
5002
5003 WARN_ON(in_interrupt());
5004
263fc48f
MW		 5005 if (i40e_check_asq_alive(&pf->hw))
5006 i40e_vc_notify_reset(pf);
5007
41c445ff
JB		 5008 /* do the biggest reset indicated */
5009 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
5010
5011 /* Request a Global Reset
5012 *
5013 * This will start the chip's countdown to the actual full
5014 * chip reset event, and a warning interrupt to be sent
5015 * to all PFs, including the requestor. Our handler
5016 * for the warning interrupt will deal with the shutdown
5017 * and recovery of the switch setup.
5018 */
69bfb110 5019 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5020 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5021 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5022 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5023
5024 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
5025
5026 /* Request a Core Reset
5027 *
5028 * Same as Global Reset, except does *not* include the MAC/PHY
5029 */
69bfb110 5030 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5031 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5032 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5033 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5034 i40e_flush(&pf->hw);
5035
5036 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
5037
5038 /* Request a PF Reset
5039 *
5040 * Resets only the PF-specific registers
5041 *
5042 * This goes directly to the tear-down and rebuild of
5043 * the switch, since we need to do all the recovery as
5044 * for the Core Reset.
5045 */
69bfb110 5046 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5047 i40e_handle_reset_warning(pf);
5048
5049 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
5050 int v;
5051
5052 /* Find the VSI(s) that requested a re-init */
5053 dev_info(&pf->pdev->dev,
5054 "VSI reinit requested\n");
505682cd 5055 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5056 struct i40e_vsi *vsi = pf->vsi[v];
5057 if (vsi != NULL &&
5058 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5059 i40e_vsi_reinit_locked(pf->vsi[v]);
5060 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5061 }
5062 }
5063
b5d06f05
NP		 5064 /* no further action needed, so return now */
5065 return;
5066 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
5067 int v;
5068
5069 /* Find the VSI(s) that needs to be brought down */
5070 dev_info(&pf->pdev->dev, "VSI down requested\n");
5071 for (v = 0; v < pf->num_alloc_vsi; v++) {
5072 struct i40e_vsi *vsi = pf->vsi[v];
5073 if (vsi != NULL &&
5074 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5075 set_bit(__I40E_DOWN, &vsi->state);
5076 i40e_down(vsi);
5077 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5078 }
5079 }
5080
41c445ff
JB		 5081 /* no further action needed, so return now */
5082 return;
5083 } else {
5084 dev_info(&pf->pdev->dev,
5085 "bad reset request 0x%08x\n", reset_flags);
5086 return;
5087 }
5088}
5089
4e3b35b0
NP		 5090#ifdef CONFIG_I40E_DCB
5091/**
5092 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5093 * @pf: board private structure
5094 * @old_cfg: current DCB config
5095 * @new_cfg: new DCB config
5096 **/
5097bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5098 struct i40e_dcbx_config *old_cfg,
5099 struct i40e_dcbx_config *new_cfg)
5100{
5101 bool need_reconfig = false;
5102
5103 /* Check if ETS configuration has changed */
5104 if (memcmp(&new_cfg->etscfg,
5105 &old_cfg->etscfg,
5106 sizeof(new_cfg->etscfg))) {
5107 /* If Priority Table has changed reconfig is needed */
5108 if (memcmp(&new_cfg->etscfg.prioritytable,
5109 &old_cfg->etscfg.prioritytable,
5110 sizeof(new_cfg->etscfg.prioritytable))) {
5111 need_reconfig = true;
69bfb110 5112 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5113 }
5114
5115 if (memcmp(&new_cfg->etscfg.tcbwtable,
5116 &old_cfg->etscfg.tcbwtable,
5117 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5118 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5119
5120 if (memcmp(&new_cfg->etscfg.tsatable,
5121 &old_cfg->etscfg.tsatable,
5122 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5123 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5124 }
5125
5126 /* Check if PFC configuration has changed */
5127 if (memcmp(&new_cfg->pfc,
5128 &old_cfg->pfc,
5129 sizeof(new_cfg->pfc))) {
5130 need_reconfig = true;
69bfb110 5131 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5132 }
5133
5134 /* Check if APP Table has changed */
5135 if (memcmp(&new_cfg->app,
5136 &old_cfg->app,
3d9667a9 5137 sizeof(new_cfg->app))) {
4e3b35b0 5138 need_reconfig = true;
69bfb110 5139 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5140 }
4e3b35b0 5141
9fa61dd2
NP		 5142 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5143 need_reconfig);
4e3b35b0
NP		 5144 return need_reconfig;
5145}
5146
5147/**
5148 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5149 * @pf: board private structure
5150 * @e: event info posted on ARQ
5151 **/
5152static int i40e_handle_lldp_event(struct i40e_pf *pf,
5153 struct i40e_arq_event_info *e)
5154{
5155 struct i40e_aqc_lldp_get_mib *mib =
5156 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5157 struct i40e_hw *hw = &pf->hw;
5158 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
5159 struct i40e_dcbx_config tmp_dcbx_cfg;
5160 bool need_reconfig = false;
5161 int ret = 0;
5162 u8 type;
5163
4d9b6043
NP		 5164 /* Not DCB capable or capability disabled */
5165 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5166 return ret;
5167
4e3b35b0
NP		 5168 /* Ignore if event is not for Nearest Bridge */
5169 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5170 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5171 dev_dbg(&pf->pdev->dev,
5172 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5173 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5174 return ret;
5175
5176 /* Check MIB Type and return if event for Remote MIB update */
5177 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5178 dev_dbg(&pf->pdev->dev,
5179 "%s: LLDP event mib type %s\n", __func__,
5180 type ? "remote" : "local");
4e3b35b0
NP		 5181 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5182 /* Update the remote cached instance and return */
5183 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5184 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5185 &hw->remote_dcbx_config);
5186 goto exit;
5187 }
5188
4e3b35b0 5189 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
9fa61dd2
NP		 5190 /* Store the old configuration */
5191 tmp_dcbx_cfg = *dcbx_cfg;
5192
5193 /* Get updated DCBX data from firmware */
5194 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5195 if (ret) {
9fa61dd2 5196 dev_info(&pf->pdev->dev, "Failed querying DCB configuration data from firmware.\n");
4e3b35b0
NP		 5197 goto exit;
5198 }
5199
5200 /* No change detected in DCBX configs */
5201 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 5202 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5203 goto exit;
5204 }
5205
9fa61dd2 5206 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, dcbx_cfg);
4e3b35b0 5207
9fa61dd2 5208 i40e_dcbnl_flush_apps(pf, dcbx_cfg);
4e3b35b0
NP		 5209
5210 if (!need_reconfig)
5211 goto exit;
5212
4d9b6043
NP		 5213 /* Enable DCB tagging only when more than one TC */
5214 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
5215 pf->flags |= I40E_FLAG_DCB_ENABLED;
5216 else
5217 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5218
69129dc3 5219 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5220 /* Reconfiguration needed quiesce all VSIs */
5221 i40e_pf_quiesce_all_vsi(pf);
5222
5223 /* Changes in configuration update VEB/VSI */
5224 i40e_dcb_reconfigure(pf);
5225
2fd75f31
NP		 5226 ret = i40e_resume_port_tx(pf);
5227
69129dc3 5228 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5229 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5230 if (ret)
5231 goto exit;
5232
5233 /* Wait for the PF's Tx queues to be disabled */
5234 ret = i40e_pf_wait_txq_disabled(pf);
2fd75f31
NP		 5235 if (!ret)
5236 i40e_pf_unquiesce_all_vsi(pf);
4e3b35b0
NP		 5237exit:
5238 return ret;
5239}
5240#endif /* CONFIG_I40E_DCB */
5241
23326186
ASJ		 5242/**
5243 * i40e_do_reset_safe - Protected reset path for userland calls.
5244 * @pf: board private structure
5245 * @reset_flags: which reset is requested
5246 *
5247 **/
5248void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5249{
5250 rtnl_lock();
5251 i40e_do_reset(pf, reset_flags);
5252 rtnl_unlock();
5253}
5254
41c445ff
JB		 5255/**
5256 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5257 * @pf: board private structure
5258 * @e: event info posted on ARQ
5259 *
5260 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5261 * and VF queues
5262 **/
5263static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5264 struct i40e_arq_event_info *e)
5265{
5266 struct i40e_aqc_lan_overflow *data =
5267 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5268 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5269 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5270 struct i40e_hw *hw = &pf->hw;
5271 struct i40e_vf *vf;
5272 u16 vf_id;
5273
69bfb110
JB		 5274 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5275 queue, qtx_ctl);
41c445ff
JB		 5276
5277 /* Queue belongs to VF, find the VF and issue VF reset */
5278 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5279 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5280 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5281 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5282 vf_id -= hw->func_caps.vf_base_id;
5283 vf = &pf->vf[vf_id];
5284 i40e_vc_notify_vf_reset(vf);
5285 /* Allow VF to process pending reset notification */
5286 msleep(20);
5287 i40e_reset_vf(vf, false);
5288 }
5289}
5290
5291/**
5292 * i40e_service_event_complete - Finish up the service event
5293 * @pf: board private structure
5294 **/
5295static void i40e_service_event_complete(struct i40e_pf *pf)
5296{
5297 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5298
5299 /* flush memory to make sure state is correct before next watchog */
4e857c58 5300 smp_mb__before_atomic();
41c445ff
JB		 5301 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5302}
5303
55a5e60b 5304/**
12957388
ASJ		 5305 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5306 * @pf: board private structure
5307 **/
5308int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
5309{
5310 int val, fcnt_prog;
5311
5312 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5313 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5314 return fcnt_prog;
5315}
5316
5317/**
5318 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 5319 * @pf: board private structure
5320 **/
5321int i40e_get_current_fd_count(struct i40e_pf *pf)
5322{
5323 int val, fcnt_prog;
5324 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5325 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5326 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5327 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5328 return fcnt_prog;
5329}
1e1be8f6 5330
55a5e60b
ASJ		 5331/**
5332 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5333 * @pf: board private structure
5334 **/
5335void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5336{
5337 u32 fcnt_prog, fcnt_avail;
5338
1e1be8f6
ASJ		 5339 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5340 return;
5341
55a5e60b
ASJ		 5342 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5343 * to re-enable
5344 */
12957388
ASJ		 5345 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5346 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5347 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5348 (pf->fd_add_err == 0) ||
5349 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5350 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5351 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5352 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5353 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5354 }
5355 }
5356 /* Wait for some more space to be available to turn on ATR */
5357 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5358 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5359 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5360 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5361 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5362 }
5363 }
5364}
5365
1e1be8f6
ASJ		 5366#define I40E_MIN_FD_FLUSH_INTERVAL 10
5367/**
5368 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5369 * @pf: board private structure
5370 **/
5371static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5372{
5373 int flush_wait_retry = 50;
5374 int reg;
5375
1790ed0c
AA		 5376 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5377 return;
5378
1e1be8f6
ASJ		 5379 if (time_after(jiffies, pf->fd_flush_timestamp +
5380 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
5381 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5382 pf->fd_flush_timestamp = jiffies;
5383 pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
5384 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5385 /* flush all filters */
5386 wr32(&pf->hw, I40E_PFQF_CTL_1,
5387 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5388 i40e_flush(&pf->hw);
60793f4a 5389 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5390 pf->fd_add_err = 0;
5391 do {
5392 /* Check FD flush status every 5-6msec */
5393 usleep_range(5000, 6000);
5394 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5395 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5396 break;
5397 } while (flush_wait_retry--);
5398 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5399 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5400 } else {
5401 /* replay sideband filters */
5402 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5403
5404 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5405 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5406 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5407 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5408 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5409 }
5410 }
5411}
5412
5413/**
5414 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5415 * @pf: board private structure
5416 **/
5417int i40e_get_current_atr_cnt(struct i40e_pf *pf)
5418{
5419 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5420}
5421
5422/* We can see up to 256 filter programming desc in transit if the filters are
5423 * being applied really fast; before we see the first
5424 * filter miss error on Rx queue 0. Accumulating enough error messages before
5425 * reacting will make sure we don't cause flush too often.
5426 */
5427#define I40E_MAX_FD_PROGRAM_ERROR 256
5428
41c445ff
JB		 5429/**
5430 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5431 * @pf: board private structure
5432 **/
5433static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5434{
41c445ff 5435
41c445ff
JB		 5436 /* if interface is down do nothing */
5437 if (test_bit(__I40E_DOWN, &pf->state))
5438 return;
1e1be8f6 5439
1790ed0c
AA		 5440 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5441 return;
5442
1e1be8f6
ASJ		 5443 if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
5444 (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
5445 (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
5446 i40e_fdir_flush_and_replay(pf);
5447
55a5e60b
ASJ		 5448 i40e_fdir_check_and_reenable(pf);
5449
41c445ff
JB		 5450}
5451
5452/**
5453 * i40e_vsi_link_event - notify VSI of a link event
5454 * @vsi: vsi to be notified
5455 * @link_up: link up or down
5456 **/
5457static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5458{
32b5b811 5459 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5460 return;
5461
5462 switch (vsi->type) {
5463 case I40E_VSI_MAIN:
38e00438
VD		 5464#ifdef I40E_FCOE
5465 case I40E_VSI_FCOE:
5466#endif
41c445ff
JB		 5467 if (!vsi->netdev || !vsi->netdev_registered)
5468 break;
5469
5470 if (link_up) {
5471 netif_carrier_on(vsi->netdev);
5472 netif_tx_wake_all_queues(vsi->netdev);
5473 } else {
5474 netif_carrier_off(vsi->netdev);
5475 netif_tx_stop_all_queues(vsi->netdev);
5476 }
5477 break;
5478
5479 case I40E_VSI_SRIOV:
41c445ff
JB		 5480 case I40E_VSI_VMDQ2:
5481 case I40E_VSI_CTRL:
5482 case I40E_VSI_MIRROR:
5483 default:
5484 /* there is no notification for other VSIs */
5485 break;
5486 }
5487}
5488
5489/**
5490 * i40e_veb_link_event - notify elements on the veb of a link event
5491 * @veb: veb to be notified
5492 * @link_up: link up or down
5493 **/
5494static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5495{
5496 struct i40e_pf *pf;
5497 int i;
5498
5499 if (!veb || !veb->pf)
5500 return;
5501 pf = veb->pf;
5502
5503 /* depth first... */
5504 for (i = 0; i < I40E_MAX_VEB; i++)
5505 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5506 i40e_veb_link_event(pf->veb[i], link_up);
5507
5508 /* ... now the local VSIs */
505682cd 5509 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5510 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5511 i40e_vsi_link_event(pf->vsi[i], link_up);
5512}
5513
5514/**
5515 * i40e_link_event - Update netif_carrier status
5516 * @pf: board private structure
5517 **/
5518static void i40e_link_event(struct i40e_pf *pf)
5519{
5520 bool new_link, old_link;
320684cd 5521 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5522 u8 new_link_speed, old_link_speed;
41c445ff 5523
1e701e09
JB		 5524 /* set this to force the get_link_status call to refresh state */
5525 pf->hw.phy.get_link_info = true;
5526
41c445ff 5527 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5528 new_link = i40e_get_link_status(&pf->hw);
fef59ddf
CS		 5529 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5530 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5531
1e701e09 5532 if (new_link == old_link &&
fef59ddf 5533 new_link_speed == old_link_speed &&
320684cd
MW		 5534 (test_bit(__I40E_DOWN, &vsi->state) ||
5535 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5536 return;
320684cd
MW		 5537
5538 if (!test_bit(__I40E_DOWN, &vsi->state))
5539 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5540
5541 /* Notify the base of the switch tree connected to
5542 * the link. Floating VEBs are not notified.
5543 */
5544 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5545 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5546 else
320684cd 5547 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5548
5549 if (pf->vf)
5550 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5551
5552 if (pf->flags & I40E_FLAG_PTP)
5553 i40e_ptp_set_increment(pf);
41c445ff
JB		 5554}
5555
5556/**
5557 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5558 * @pf: board private structure
5559 *
5560 * Set the per-queue flags to request a check for stuck queues in the irq
5561 * clean functions, then force interrupts to be sure the irq clean is called.
5562 **/
5563static void i40e_check_hang_subtask(struct i40e_pf *pf)
5564{
5565 int i, v;
5566
5567 /* If we're down or resetting, just bail */
5568 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5569 return;
5570
5571 /* for each VSI/netdev
5572 * for each Tx queue
5573 * set the check flag
5574 * for each q_vector
5575 * force an interrupt
5576 */
505682cd 5577 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5578 struct i40e_vsi *vsi = pf->vsi[v];
5579 int armed = 0;
5580
5581 if (!pf->vsi[v] ||
5582 test_bit(__I40E_DOWN, &vsi->state) ||
5583 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5584 continue;
5585
5586 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5587 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5588 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5589 &vsi->tx_rings[i]->state))
41c445ff
JB		 5590 armed++;
5591 }
5592
5593 if (armed) {
5594 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5595 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5596 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5d1ff106
SN		 5597 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
5598 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
5599 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
5600 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
41c445ff
JB		 5601 } else {
5602 u16 vec = vsi->base_vector - 1;
5603 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5d1ff106
SN		 5604 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
5605 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK |
5606 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK |
5607 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK);
41c445ff
JB		 5608 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5609 wr32(&vsi->back->hw,
5610 I40E_PFINT_DYN_CTLN(vec), val);
5611 }
5612 i40e_flush(&vsi->back->hw);
5613 }
5614 }
5615}
5616
5617/**
21536717 5618 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5619 * @pf: board private structure
5620 **/
5621static void i40e_watchdog_subtask(struct i40e_pf *pf)
5622{
5623 int i;
5624
5625 /* if interface is down do nothing */
5626 if (test_bit(__I40E_DOWN, &pf->state) ||
5627 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5628 return;
5629
21536717
SN		 5630 /* make sure we don't do these things too often */
5631 if (time_before(jiffies, (pf->service_timer_previous +
5632 pf->service_timer_period)))
5633 return;
5634 pf->service_timer_previous = jiffies;
5635
5636 i40e_check_hang_subtask(pf);
5637 i40e_link_event(pf);
5638
41c445ff
JB		 5639 /* Update the stats for active netdevs so the network stack
5640 * can look at updated numbers whenever it cares to
5641 */
505682cd 5642 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5643 if (pf->vsi[i] && pf->vsi[i]->netdev)
5644 i40e_update_stats(pf->vsi[i]);
5645
5646 /* Update the stats for the active switching components */
5647 for (i = 0; i < I40E_MAX_VEB; i++)
5648 if (pf->veb[i])
5649 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5650
5651 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5652}
5653
5654/**
5655 * i40e_reset_subtask - Set up for resetting the device and driver
5656 * @pf: board private structure
5657 **/
5658static void i40e_reset_subtask(struct i40e_pf *pf)
5659{
5660 u32 reset_flags = 0;
5661
23326186 5662 rtnl_lock();
41c445ff
JB		 5663 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5664 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5665 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5666 }
5667 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5668 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5669 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5670 }
5671 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5672 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5673 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5674 }
5675 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5676 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5677 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5678 }
b5d06f05
NP		 5679 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5680 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5681 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5682 }
41c445ff
JB		 5683
5684 /* If there's a recovery already waiting, it takes
5685 * precedence before starting a new reset sequence.
5686 */
5687 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5688 i40e_handle_reset_warning(pf);
23326186 5689 goto unlock;
41c445ff
JB		 5690 }
5691
5692 /* If we're already down or resetting, just bail */
5693 if (reset_flags &&
5694 !test_bit(__I40E_DOWN, &pf->state) &&
5695 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5696 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5697
5698unlock:
5699 rtnl_unlock();
41c445ff
JB		 5700}
5701
5702/**
5703 * i40e_handle_link_event - Handle link event
5704 * @pf: board private structure
5705 * @e: event info posted on ARQ
5706 **/
5707static void i40e_handle_link_event(struct i40e_pf *pf,
5708 struct i40e_arq_event_info *e)
5709{
5710 struct i40e_hw *hw = &pf->hw;
5711 struct i40e_aqc_get_link_status *status =
5712 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5713 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5714
5715 /* save off old link status information */
5716 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5717 sizeof(pf->hw.phy.link_info_old));
5718
1e701e09
JB		 5719 /* Do a new status request to re-enable LSE reporting
5720 * and load new status information into the hw struct
5721 * This completely ignores any state information
5722 * in the ARQ event info, instead choosing to always
5723 * issue the AQ update link status command.
5724 */
5725 i40e_link_event(pf);
5726
7b592f61
CW		 5727 /* check for unqualified module, if link is down */
5728 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5729 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5730 (!(status->link_info & I40E_AQ_LINK_UP)))
5731 dev_err(&pf->pdev->dev,
5732 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5733}
5734
5735/**
5736 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5737 * @pf: board private structure
5738 **/
5739static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5740{
5741 struct i40e_arq_event_info event;
5742 struct i40e_hw *hw = &pf->hw;
5743 u16 pending, i = 0;
5744 i40e_status ret;
5745 u16 opcode;
86df242b 5746 u32 oldval;
41c445ff
JB		 5747 u32 val;
5748
a316f651
ASJ		 5749 /* Do not run clean AQ when PF reset fails */
5750 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5751 return;
5752
86df242b
SN		 5753 /* check for error indications */
5754 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5755 oldval = val;
5756 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5757 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5758 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5759 }
5760 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5761 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5762 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5763 }
5764 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5765 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5766 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5767 }
5768 if (oldval != val)
5769 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5770
5771 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5772 oldval = val;
5773 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5774 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5775 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5776 }
5777 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5778 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5779 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5780 }
5781 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5782 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5783 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5784 }
5785 if (oldval != val)
5786 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5787
1001dc37
MW		 5788 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
5789 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 5790 if (!event.msg_buf)
5791 return;
5792
5793 do {
5794 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5795 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5796 break;
56497978 5797 else if (ret) {
41c445ff
JB		 5798 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5799 break;
5800 }
5801
5802 opcode = le16_to_cpu(event.desc.opcode);
5803 switch (opcode) {
5804
5805 case i40e_aqc_opc_get_link_status:
5806 i40e_handle_link_event(pf, &event);
5807 break;
5808 case i40e_aqc_opc_send_msg_to_pf:
5809 ret = i40e_vc_process_vf_msg(pf,
5810 le16_to_cpu(event.desc.retval),
5811 le32_to_cpu(event.desc.cookie_high),
5812 le32_to_cpu(event.desc.cookie_low),
5813 event.msg_buf,
1001dc37 5814 event.msg_len);
41c445ff
JB		 5815 break;
5816 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5817 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5818#ifdef CONFIG_I40E_DCB
5819 rtnl_lock();
5820 ret = i40e_handle_lldp_event(pf, &event);
5821 rtnl_unlock();
5822#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5823 break;
5824 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5825 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5826 i40e_handle_lan_overflow_event(pf, &event);
5827 break;
0467bc91
SN		 5828 case i40e_aqc_opc_send_msg_to_peer:
5829 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5830 break;
41c445ff
JB		 5831 default:
5832 dev_info(&pf->pdev->dev,
0467bc91
SN		 5833 "ARQ Error: Unknown event 0x%04x received\n",
5834 opcode);
41c445ff
JB		 5835 break;
5836 }
5837 } while (pending && (i++ < pf->adminq_work_limit));
5838
5839 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5840 /* re-enable Admin queue interrupt cause */
5841 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5842 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5843 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5844 i40e_flush(hw);
5845
5846 kfree(event.msg_buf);
5847}
5848
4eb3f768
SN		 5849/**
5850 * i40e_verify_eeprom - make sure eeprom is good to use
5851 * @pf: board private structure
5852 **/
5853static void i40e_verify_eeprom(struct i40e_pf *pf)
5854{
5855 int err;
5856
5857 err = i40e_diag_eeprom_test(&pf->hw);
5858 if (err) {
5859 /* retry in case of garbage read */
5860 err = i40e_diag_eeprom_test(&pf->hw);
5861 if (err) {
5862 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5863 err);
5864 set_bit(__I40E_BAD_EEPROM, &pf->state);
5865 }
5866 }
5867
5868 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5869 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5870 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5871 }
5872}
5873
51616018
NP		 5874/**
5875 * i40e_config_bridge_mode - Configure the HW bridge mode
5876 * @veb: pointer to the bridge instance
5877 *
5878 * Configure the loop back mode for the LAN VSI that is downlink to the
5879 * specified HW bridge instance. It is expected this function is called
5880 * when a new HW bridge is instantiated.
5881 **/
5882static void i40e_config_bridge_mode(struct i40e_veb *veb)
5883{
5884 struct i40e_pf *pf = veb->pf;
5885
5886 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
5887 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
5888 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
5889 i40e_disable_pf_switch_lb(pf);
5890 else
5891 i40e_enable_pf_switch_lb(pf);
5892}
5893
41c445ff
JB		 5894/**
5895 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5896 * @veb: pointer to the VEB instance
5897 *
5898 * This is a recursive function that first builds the attached VSIs then
5899 * recurses in to build the next layer of VEB. We track the connections
5900 * through our own index numbers because the seid's from the HW could
5901 * change across the reset.
5902 **/
5903static int i40e_reconstitute_veb(struct i40e_veb *veb)
5904{
5905 struct i40e_vsi *ctl_vsi = NULL;
5906 struct i40e_pf *pf = veb->pf;
5907 int v, veb_idx;
5908 int ret;
5909
5910 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5911 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5912 if (pf->vsi[v] &&
5913 pf->vsi[v]->veb_idx == veb->idx &&
5914 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5915 ctl_vsi = pf->vsi[v];
5916 break;
5917 }
5918 }
5919 if (!ctl_vsi) {
5920 dev_info(&pf->pdev->dev,
5921 "missing owner VSI for veb_idx %d\n", veb->idx);
5922 ret = -ENOENT;
5923 goto end_reconstitute;
5924 }
5925 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5926 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5927 ret = i40e_add_vsi(ctl_vsi);
5928 if (ret) {
5929 dev_info(&pf->pdev->dev,
5930 "rebuild of owner VSI failed: %d\n", ret);
5931 goto end_reconstitute;
5932 }
5933 i40e_vsi_reset_stats(ctl_vsi);
5934
5935 /* create the VEB in the switch and move the VSI onto the VEB */
5936 ret = i40e_add_veb(veb, ctl_vsi);
5937 if (ret)
5938 goto end_reconstitute;
5939
51616018 5940 i40e_config_bridge_mode(veb);
b64ba084 5941
41c445ff 5942 /* create the remaining VSIs attached to this VEB */
505682cd 5943 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5944 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5945 continue;
5946
5947 if (pf->vsi[v]->veb_idx == veb->idx) {
5948 struct i40e_vsi *vsi = pf->vsi[v];
5949 vsi->uplink_seid = veb->seid;
5950 ret = i40e_add_vsi(vsi);
5951 if (ret) {
5952 dev_info(&pf->pdev->dev,
5953 "rebuild of vsi_idx %d failed: %d\n",
5954 v, ret);
5955 goto end_reconstitute;
5956 }
5957 i40e_vsi_reset_stats(vsi);
5958 }
5959 }
5960
5961 /* create any VEBs attached to this VEB - RECURSION */
5962 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5963 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5964 pf->veb[veb_idx]->uplink_seid = veb->seid;
5965 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5966 if (ret)
5967 break;
5968 }
5969 }
5970
5971end_reconstitute:
5972 return ret;
5973}
5974
5975/**
5976 * i40e_get_capabilities - get info about the HW
5977 * @pf: the PF struct
5978 **/
5979static int i40e_get_capabilities(struct i40e_pf *pf)
5980{
5981 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5982 u16 data_size;
5983 int buf_len;
5984 int err;
5985
5986 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5987 do {
5988 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5989 if (!cap_buf)
5990 return -ENOMEM;
5991
5992 /* this loads the data into the hw struct for us */
5993 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5994 &data_size,
5995 i40e_aqc_opc_list_func_capabilities,
5996 NULL);
5997 /* data loaded, buffer no longer needed */
5998 kfree(cap_buf);
5999
6000 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6001 /* retry with a larger buffer */
6002 buf_len = data_size;
6003 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6004 dev_info(&pf->pdev->dev,
6005 "capability discovery failed: aq=%d\n",
6006 pf->hw.aq.asq_last_status);
6007 return -ENODEV;
6008 }
6009 } while (err);
6010
ac71b7ba
ASJ		 6011 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6012 (pf->hw.aq.fw_maj_ver < 2)) {
6013 pf->hw.func_caps.num_msix_vectors++;
6014 pf->hw.func_caps.num_msix_vectors_vf++;
6015 }
6016
41c445ff
JB		 6017 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6018 dev_info(&pf->pdev->dev,
6019 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6020 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6021 pf->hw.func_caps.num_msix_vectors,
6022 pf->hw.func_caps.num_msix_vectors_vf,
6023 pf->hw.func_caps.fd_filters_guaranteed,
6024 pf->hw.func_caps.fd_filters_best_effort,
6025 pf->hw.func_caps.num_tx_qp,
6026 pf->hw.func_caps.num_vsis);
6027
7134f9ce
JB		 6028#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6029 + pf->hw.func_caps.num_vfs)
6030 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6031 dev_info(&pf->pdev->dev,
6032 "got num_vsis %d, setting num_vsis to %d\n",
6033 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6034 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6035 }
6036
41c445ff
JB		 6037 return 0;
6038}
6039
cbf61325
ASJ		 6040static int i40e_vsi_clear(struct i40e_vsi *vsi);
6041
41c445ff 6042/**
cbf61325 6043 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6044 * @pf: board private structure
6045 **/
cbf61325 6046static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6047{
6048 struct i40e_vsi *vsi;
8a9eb7d3 6049 int i;
41c445ff 6050
407e063c
JB		 6051 /* quick workaround for an NVM issue that leaves a critical register
6052 * uninitialized
6053 */
6054 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6055 static const u32 hkey[] = {
6056 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6057 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6058 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6059 0x95b3a76d};
6060
6061 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6062 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6063 }
6064
cbf61325 6065 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6066 return;
6067
cbf61325 6068 /* find existing VSI and see if it needs configuring */
41c445ff 6069 vsi = NULL;
505682cd 6070 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6071 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6072 vsi = pf->vsi[i];
cbf61325
ASJ		 6073 break;
6074 }
6075 }
6076
6077 /* create a new VSI if none exists */
41c445ff 6078 if (!vsi) {
cbf61325
ASJ		 6079 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6080 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6081 if (!vsi) {
6082 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6083 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6084 return;
41c445ff 6085 }
cbf61325 6086 }
41c445ff 6087
8a9eb7d3 6088 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6089}
6090
6091/**
6092 * i40e_fdir_teardown - release the Flow Director resources
6093 * @pf: board private structure
6094 **/
6095static void i40e_fdir_teardown(struct i40e_pf *pf)
6096{
6097 int i;
6098
17a73f6b 6099 i40e_fdir_filter_exit(pf);
505682cd 6100 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6101 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6102 i40e_vsi_release(pf->vsi[i]);
6103 break;
6104 }
6105 }
6106}
6107
6108/**
f650a38b 6109 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6110 * @pf: board private structure
6111 *
f650a38b
ASJ		 6112 * Close up the VFs and other things in prep for pf Reset.
6113 **/
23cfbe07 6114static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6115{
41c445ff 6116 struct i40e_hw *hw = &pf->hw;
60442dea 6117 i40e_status ret = 0;
41c445ff
JB		 6118 u32 v;
6119
6120 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6121 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6122 return;
41c445ff 6123
69bfb110 6124 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6125
41c445ff
JB		 6126 /* quiesce the VSIs and their queues that are not already DOWN */
6127 i40e_pf_quiesce_all_vsi(pf);
6128
505682cd 6129 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6130 if (pf->vsi[v])
6131 pf->vsi[v]->seid = 0;
6132 }
6133
6134 i40e_shutdown_adminq(&pf->hw);
6135
f650a38b 6136 /* call shutdown HMC */
60442dea
SN		 6137 if (hw->hmc.hmc_obj) {
6138 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6139 if (ret)
60442dea
SN		 6140 dev_warn(&pf->pdev->dev,
6141 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6142 }
f650a38b
ASJ		 6143}
6144
44033fac
JB		 6145/**
6146 * i40e_send_version - update firmware with driver version
6147 * @pf: PF struct
6148 */
6149static void i40e_send_version(struct i40e_pf *pf)
6150{
6151 struct i40e_driver_version dv;
6152
6153 dv.major_version = DRV_VERSION_MAJOR;
6154 dv.minor_version = DRV_VERSION_MINOR;
6155 dv.build_version = DRV_VERSION_BUILD;
6156 dv.subbuild_version = 0;
35a7d804 6157 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6158 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6159}
6160
f650a38b 6161/**
4dda12e6 6162 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6163 * @pf: board private structure
bc7d338f 6164 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6165 **/
bc7d338f 6166static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6167{
f650a38b 6168 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6169 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6170 i40e_status ret;
6171 u32 v;
6172
41c445ff
JB		 6173 /* Now we wait for GRST to settle out.
6174 * We don't have to delete the VEBs or VSIs from the hw switch
6175 * because the reset will make them disappear.
6176 */
6177 ret = i40e_pf_reset(hw);
b5565400 6178 if (ret) {
41c445ff 6179 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6180 set_bit(__I40E_RESET_FAILED, &pf->state);
6181 goto clear_recovery;
b5565400 6182 }
41c445ff
JB		 6183 pf->pfr_count++;
6184
6185 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6186 goto clear_recovery;
69bfb110 6187 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6188
6189 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6190 ret = i40e_init_adminq(&pf->hw);
6191 if (ret) {
6192 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 6193 goto clear_recovery;
41c445ff
JB		 6194 }
6195
4eb3f768 6196 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6197 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6198 i40e_verify_eeprom(pf);
4eb3f768 6199
e78ac4bf 6200 i40e_clear_pxe_mode(hw);
41c445ff
JB		 6201 ret = i40e_get_capabilities(pf);
6202 if (ret) {
6203 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
6204 ret);
6205 goto end_core_reset;
6206 }
6207
41c445ff
JB		 6208 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6209 hw->func_caps.num_rx_qp,
6210 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6211 if (ret) {
6212 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6213 goto end_core_reset;
6214 }
6215 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6216 if (ret) {
6217 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6218 goto end_core_reset;
6219 }
6220
4e3b35b0
NP		 6221#ifdef CONFIG_I40E_DCB
6222 ret = i40e_init_pf_dcb(pf);
6223 if (ret) {
aebfc816
SN		 6224 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6225 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6226 /* Continue without DCB enabled */
4e3b35b0
NP		 6227 }
6228#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6229#ifdef I40E_FCOE
6230 ret = i40e_init_pf_fcoe(pf);
6231 if (ret)
6232 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6233
38e00438 6234#endif
41c445ff 6235 /* do basic switch setup */
bc7d338f 6236 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6237 if (ret)
6238 goto end_core_reset;
6239
7e2453fe
JB		 6240 /* driver is only interested in link up/down and module qualification
6241 * reports from firmware
6242 */
6243 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6244 I40E_AQ_EVENT_LINK_UPDOWN |
6245 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6246 if (ret)
6247 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6248
cafa2ee6
ASJ		 6249 /* make sure our flow control settings are restored */
6250 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6251 if (ret)
6252 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6253
41c445ff
JB		 6254 /* Rebuild the VSIs and VEBs that existed before reset.
6255 * They are still in our local switch element arrays, so only
6256 * need to rebuild the switch model in the HW.
6257 *
6258 * If there were VEBs but the reconstitution failed, we'll try
6259 * try to recover minimal use by getting the basic PF VSI working.
6260 */
6261 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6262 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6263 /* find the one VEB connected to the MAC, and find orphans */
6264 for (v = 0; v < I40E_MAX_VEB; v++) {
6265 if (!pf->veb[v])
6266 continue;
6267
6268 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6269 pf->veb[v]->uplink_seid == 0) {
6270 ret = i40e_reconstitute_veb(pf->veb[v]);
6271
6272 if (!ret)
6273 continue;
6274
6275 /* If Main VEB failed, we're in deep doodoo,
6276 * so give up rebuilding the switch and set up
6277 * for minimal rebuild of PF VSI.
6278 * If orphan failed, we'll report the error
6279 * but try to keep going.
6280 */
6281 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6282 dev_info(&pf->pdev->dev,
6283 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6284 ret);
6285 pf->vsi[pf->lan_vsi]->uplink_seid
6286 = pf->mac_seid;
6287 break;
6288 } else if (pf->veb[v]->uplink_seid == 0) {
6289 dev_info(&pf->pdev->dev,
6290 "rebuild of orphan VEB failed: %d\n",
6291 ret);
6292 }
6293 }
6294 }
6295 }
6296
6297 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6298 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6299 /* no VEB, so rebuild only the Main VSI */
6300 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6301 if (ret) {
6302 dev_info(&pf->pdev->dev,
6303 "rebuild of Main VSI failed: %d\n", ret);
6304 goto end_core_reset;
6305 }
6306 }
6307
cafa2ee6
ASJ		 6308 msleep(75);
6309 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6310 if (ret) {
6311 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6312 pf->hw.aq.asq_last_status);
6313 }
6314
41c445ff
JB		 6315 /* reinit the misc interrupt */
6316 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6317 ret = i40e_setup_misc_vector(pf);
6318
6319 /* restart the VSIs that were rebuilt and running before the reset */
6320 i40e_pf_unquiesce_all_vsi(pf);
6321
69f64b2b
MW		 6322 if (pf->num_alloc_vfs) {
6323 for (v = 0; v < pf->num_alloc_vfs; v++)
6324 i40e_reset_vf(&pf->vf[v], true);
6325 }
6326
41c445ff 6327 /* tell the firmware that we're starting */
44033fac 6328 i40e_send_version(pf);
41c445ff
JB		 6329
6330end_core_reset:
a316f651
ASJ		 6331 clear_bit(__I40E_RESET_FAILED, &pf->state);
6332clear_recovery:
41c445ff
JB		 6333 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6334}
6335
f650a38b
ASJ		 6336/**
6337 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
6338 * @pf: board private structure
6339 *
6340 * Close up the VFs and other things in prep for a Core Reset,
6341 * then get ready to rebuild the world.
6342 **/
6343static void i40e_handle_reset_warning(struct i40e_pf *pf)
6344{
23cfbe07
SN		 6345 i40e_prep_for_reset(pf);
6346 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6347}
6348
41c445ff
JB		 6349/**
6350 * i40e_handle_mdd_event
6351 * @pf: pointer to the pf structure
6352 *
6353 * Called from the MDD irq handler to identify possibly malicious vfs
6354 **/
6355static void i40e_handle_mdd_event(struct i40e_pf *pf)
6356{
6357 struct i40e_hw *hw = &pf->hw;
6358 bool mdd_detected = false;
df430b12 6359 bool pf_mdd_detected = false;
41c445ff
JB		 6360 struct i40e_vf *vf;
6361 u32 reg;
6362 int i;
6363
6364 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6365 return;
6366
6367 /* find what triggered the MDD event */
6368 reg = rd32(hw, I40E_GL_MDET_TX);
6369 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6370 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6371 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6372 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6373 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6374 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6375 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6376 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6377 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6378 pf->hw.func_caps.base_queue;
faf32978
JB		 6379 if (netif_msg_tx_err(pf))
6380 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
6381 event, queue, pf_num, vf_num);
41c445ff
JB		 6382 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6383 mdd_detected = true;
6384 }
6385 reg = rd32(hw, I40E_GL_MDET_RX);
6386 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6387 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6388 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6389 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6390 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6391 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6392 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6393 pf->hw.func_caps.base_queue;
faf32978
JB		 6394 if (netif_msg_rx_err(pf))
6395 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6396 event, queue, func);
41c445ff
JB		 6397 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6398 mdd_detected = true;
6399 }
6400
df430b12
NP		 6401 if (mdd_detected) {
6402 reg = rd32(hw, I40E_PF_MDET_TX);
6403 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6404 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6405 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6406 pf_mdd_detected = true;
6407 }
6408 reg = rd32(hw, I40E_PF_MDET_RX);
6409 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6410 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6411 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6412 pf_mdd_detected = true;
6413 }
6414 /* Queue belongs to the PF, initiate a reset */
6415 if (pf_mdd_detected) {
6416 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6417 i40e_service_event_schedule(pf);
6418 }
6419 }
6420
41c445ff
JB		 6421 /* see if one of the VFs needs its hand slapped */
6422 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6423 vf = &(pf->vf[i]);
6424 reg = rd32(hw, I40E_VP_MDET_TX(i));
6425 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6426 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6427 vf->num_mdd_events++;
faf32978
JB		 6428 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6429 i);
41c445ff
JB		 6430 }
6431
6432 reg = rd32(hw, I40E_VP_MDET_RX(i));
6433 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6434 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6435 vf->num_mdd_events++;
faf32978
JB		 6436 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6437 i);
41c445ff
JB		 6438 }
6439
6440 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6441 dev_info(&pf->pdev->dev,
6442 "Too many MDD events on VF %d, disabled\n", i);
6443 dev_info(&pf->pdev->dev,
6444 "Use PF Control I/F to re-enable the VF\n");
6445 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6446 }
6447 }
6448
6449 /* re-enable mdd interrupt cause */
6450 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6451 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6452 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6453 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6454 i40e_flush(hw);
6455}
6456
a1c9a9d9
JK		 6457#ifdef CONFIG_I40E_VXLAN
6458/**
6459 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6460 * @pf: board private structure
6461 **/
6462static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6463{
a1c9a9d9
JK		 6464 struct i40e_hw *hw = &pf->hw;
6465 i40e_status ret;
6466 u8 filter_index;
6467 __be16 port;
6468 int i;
6469
6470 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6471 return;
6472
6473 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6474
6475 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6476 if (pf->pending_vxlan_bitmap & (1 << i)) {
6477 pf->pending_vxlan_bitmap &= ~(1 << i);
6478 port = pf->vxlan_ports[i];
6479 ret = port ?
6480 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6481 I40E_AQC_TUNNEL_TYPE_VXLAN,
6482 &filter_index, NULL)
6483 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6484
6485 if (ret) {
6486 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6487 port ? "adding" : "deleting",
6488 ntohs(port), port ? i : i);
6489
6490 pf->vxlan_ports[i] = 0;
6491 } else {
6492 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6493 port ? "Added" : "Deleted",
6494 ntohs(port), port ? i : filter_index);
6495 }
6496 }
6497 }
6498}
6499
6500#endif
41c445ff
JB		 6501/**
6502 * i40e_service_task - Run the driver's async subtasks
6503 * @work: pointer to work_struct containing our data
6504 **/
6505static void i40e_service_task(struct work_struct *work)
6506{
6507 struct i40e_pf *pf = container_of(work,
6508 struct i40e_pf,
6509 service_task);
6510 unsigned long start_time = jiffies;
6511
e57a2fea
SN		 6512 /* don't bother with service tasks if a reset is in progress */
6513 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6514 i40e_service_event_complete(pf);
6515 return;
6516 }
6517
41c445ff
JB		 6518 i40e_reset_subtask(pf);
6519 i40e_handle_mdd_event(pf);
6520 i40e_vc_process_vflr_event(pf);
6521 i40e_watchdog_subtask(pf);
6522 i40e_fdir_reinit_subtask(pf);
41c445ff 6523 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6524#ifdef CONFIG_I40E_VXLAN
6525 i40e_sync_vxlan_filters_subtask(pf);
6526#endif
41c445ff
JB		 6527 i40e_clean_adminq_subtask(pf);
6528
6529 i40e_service_event_complete(pf);
6530
6531 /* If the tasks have taken longer than one timer cycle or there
6532 * is more work to be done, reschedule the service task now
6533 * rather than wait for the timer to tick again.
6534 */
6535 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6536 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6537 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6538 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6539 i40e_service_event_schedule(pf);
6540}
6541
6542/**
6543 * i40e_service_timer - timer callback
6544 * @data: pointer to PF struct
6545 **/
6546static void i40e_service_timer(unsigned long data)
6547{
6548 struct i40e_pf *pf = (struct i40e_pf *)data;
6549
6550 mod_timer(&pf->service_timer,
6551 round_jiffies(jiffies + pf->service_timer_period));
6552 i40e_service_event_schedule(pf);
6553}
6554
6555/**
6556 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6557 * @vsi: the VSI being configured
6558 **/
6559static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6560{
6561 struct i40e_pf *pf = vsi->back;
6562
6563 switch (vsi->type) {
6564 case I40E_VSI_MAIN:
6565 vsi->alloc_queue_pairs = pf->num_lan_qps;
6566 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6567 I40E_REQ_DESCRIPTOR_MULTIPLE);
6568 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6569 vsi->num_q_vectors = pf->num_lan_msix;
6570 else
6571 vsi->num_q_vectors = 1;
6572
6573 break;
6574
6575 case I40E_VSI_FDIR:
6576 vsi->alloc_queue_pairs = 1;
6577 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6578 I40E_REQ_DESCRIPTOR_MULTIPLE);
6579 vsi->num_q_vectors = 1;
6580 break;
6581
6582 case I40E_VSI_VMDQ2:
6583 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6584 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6585 I40E_REQ_DESCRIPTOR_MULTIPLE);
6586 vsi->num_q_vectors = pf->num_vmdq_msix;
6587 break;
6588
6589 case I40E_VSI_SRIOV:
6590 vsi->alloc_queue_pairs = pf->num_vf_qps;
6591 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6592 I40E_REQ_DESCRIPTOR_MULTIPLE);
6593 break;
6594
38e00438
VD		 6595#ifdef I40E_FCOE
6596 case I40E_VSI_FCOE:
6597 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6598 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6599 I40E_REQ_DESCRIPTOR_MULTIPLE);
6600 vsi->num_q_vectors = pf->num_fcoe_msix;
6601 break;
6602
6603#endif /* I40E_FCOE */
41c445ff
JB		 6604 default:
6605 WARN_ON(1);
6606 return -ENODATA;
6607 }
6608
6609 return 0;
6610}
6611
f650a38b
ASJ		 6612/**
6613 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6614 * @type: VSI pointer
bc7d338f 6615 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6616 *
6617 * On error: returns error code (negative)
6618 * On success: returns 0
6619 **/
bc7d338f 6620static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6621{
6622 int size;
6623 int ret = 0;
6624
ac6c5e3d 6625 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6626 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6627 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6628 if (!vsi->tx_rings)
6629 return -ENOMEM;
f650a38b
ASJ		 6630 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6631
bc7d338f
ASJ		 6632 if (alloc_qvectors) {
6633 /* allocate memory for q_vector pointers */
f57e4fbd 6634 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6635 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6636 if (!vsi->q_vectors) {
6637 ret = -ENOMEM;
6638 goto err_vectors;
6639 }
f650a38b
ASJ		 6640 }
6641 return ret;
6642
6643err_vectors:
6644 kfree(vsi->tx_rings);
6645 return ret;
6646}
6647
41c445ff
JB		 6648/**
6649 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6650 * @pf: board private structure
6651 * @type: type of VSI
6652 *
6653 * On error: returns error code (negative)
6654 * On success: returns vsi index in PF (positive)
6655 **/
6656static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6657{
6658 int ret = -ENODEV;
6659 struct i40e_vsi *vsi;
6660 int vsi_idx;
6661 int i;
6662
6663 /* Need to protect the allocation of the VSIs at the PF level */
6664 mutex_lock(&pf->switch_mutex);
6665
6666 /* VSI list may be fragmented if VSI creation/destruction has
6667 * been happening. We can afford to do a quick scan to look
6668 * for any free VSIs in the list.
6669 *
6670 * find next empty vsi slot, looping back around if necessary
6671 */
6672 i = pf->next_vsi;
505682cd 6673 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6674 i++;
505682cd 6675 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6676 i = 0;
6677 while (i < pf->next_vsi && pf->vsi[i])
6678 i++;
6679 }
6680
505682cd 6681 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6682 vsi_idx = i; /* Found one! */
6683 } else {
6684 ret = -ENODEV;
493fb300 6685 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6686 }
6687 pf->next_vsi = ++i;
6688
6689 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6690 if (!vsi) {
6691 ret = -ENOMEM;
493fb300 6692 goto unlock_pf;
41c445ff
JB		 6693 }
6694 vsi->type = type;
6695 vsi->back = pf;
6696 set_bit(__I40E_DOWN, &vsi->state);
6697 vsi->flags = 0;
6698 vsi->idx = vsi_idx;
6699 vsi->rx_itr_setting = pf->rx_itr_default;
6700 vsi->tx_itr_setting = pf->tx_itr_default;
6701 vsi->netdev_registered = false;
6702 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6703 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6704 vsi->irqs_ready = false;
41c445ff 6705
9f65e15b
AD		 6706 ret = i40e_set_num_rings_in_vsi(vsi);
6707 if (ret)
6708 goto err_rings;
6709
bc7d338f 6710 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6711 if (ret)
9f65e15b 6712 goto err_rings;
493fb300 6713
41c445ff
JB		 6714 /* Setup default MSIX irq handler for VSI */
6715 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6716
6717 pf->vsi[vsi_idx] = vsi;
6718 ret = vsi_idx;
493fb300
AD		 6719 goto unlock_pf;
6720
9f65e15b 6721err_rings:
493fb300
AD		 6722 pf->next_vsi = i - 1;
6723 kfree(vsi);
6724unlock_pf:
41c445ff
JB		 6725 mutex_unlock(&pf->switch_mutex);
6726 return ret;
6727}
6728
f650a38b
ASJ		 6729/**
6730 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6731 * @type: VSI pointer
bc7d338f 6732 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6733 *
6734 * On error: returns error code (negative)
6735 * On success: returns 0
6736 **/
bc7d338f 6737static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6738{
6739 /* free the ring and vector containers */
bc7d338f
ASJ		 6740 if (free_qvectors) {
6741 kfree(vsi->q_vectors);
6742 vsi->q_vectors = NULL;
6743 }
f650a38b
ASJ		 6744 kfree(vsi->tx_rings);
6745 vsi->tx_rings = NULL;
6746 vsi->rx_rings = NULL;
6747}
6748
41c445ff
JB		 6749/**
6750 * i40e_vsi_clear - Deallocate the VSI provided
6751 * @vsi: the VSI being un-configured
6752 **/
6753static int i40e_vsi_clear(struct i40e_vsi *vsi)
6754{
6755 struct i40e_pf *pf;
6756
6757 if (!vsi)
6758 return 0;
6759
6760 if (!vsi->back)
6761 goto free_vsi;
6762 pf = vsi->back;
6763
6764 mutex_lock(&pf->switch_mutex);
6765 if (!pf->vsi[vsi->idx]) {
6766 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6767 vsi->idx, vsi->idx, vsi, vsi->type);
6768 goto unlock_vsi;
6769 }
6770
6771 if (pf->vsi[vsi->idx] != vsi) {
6772 dev_err(&pf->pdev->dev,
6773 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6774 pf->vsi[vsi->idx]->idx,
6775 pf->vsi[vsi->idx],
6776 pf->vsi[vsi->idx]->type,
6777 vsi->idx, vsi, vsi->type);
6778 goto unlock_vsi;
6779 }
6780
6781 /* updates the pf for this cleared vsi */
6782 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6783 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6784
bc7d338f 6785 i40e_vsi_free_arrays(vsi, true);
493fb300 6786
41c445ff
JB		 6787 pf->vsi[vsi->idx] = NULL;
6788 if (vsi->idx < pf->next_vsi)
6789 pf->next_vsi = vsi->idx;
6790
6791unlock_vsi:
6792 mutex_unlock(&pf->switch_mutex);
6793free_vsi:
6794 kfree(vsi);
6795
6796 return 0;
6797}
6798
9f65e15b
AD		 6799/**
6800 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6801 * @vsi: the VSI being cleaned
6802 **/
be1d5eea 6803static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6804{
6805 int i;
6806
8e9dca53 6807 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6808 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6809 kfree_rcu(vsi->tx_rings[i], rcu);
6810 vsi->tx_rings[i] = NULL;
6811 vsi->rx_rings[i] = NULL;
6812 }
be1d5eea 6813 }
9f65e15b
AD		 6814}
6815
41c445ff
JB		 6816/**
6817 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6818 * @vsi: the VSI being configured
6819 **/
6820static int i40e_alloc_rings(struct i40e_vsi *vsi)
6821{
e7046ee1 6822 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6823 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6824 int i;
6825
41c445ff 6826 /* Set basic values in the rings to be used later during open() */
d7397644 6827 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6828 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6829 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6830 if (!tx_ring)
6831 goto err_out;
41c445ff
JB		 6832
6833 tx_ring->queue_index = i;
6834 tx_ring->reg_idx = vsi->base_queue + i;
6835 tx_ring->ring_active = false;
6836 tx_ring->vsi = vsi;
6837 tx_ring->netdev = vsi->netdev;
6838 tx_ring->dev = &pf->pdev->dev;
6839 tx_ring->count = vsi->num_desc;
6840 tx_ring->size = 0;
6841 tx_ring->dcb_tc = 0;
9f65e15b 6842 vsi->tx_rings[i] = tx_ring;
41c445ff 6843
9f65e15b 6844 rx_ring = &tx_ring[1];
41c445ff
JB		 6845 rx_ring->queue_index = i;
6846 rx_ring->reg_idx = vsi->base_queue + i;
6847 rx_ring->ring_active = false;
6848 rx_ring->vsi = vsi;
6849 rx_ring->netdev = vsi->netdev;
6850 rx_ring->dev = &pf->pdev->dev;
6851 rx_ring->count = vsi->num_desc;
6852 rx_ring->size = 0;
6853 rx_ring->dcb_tc = 0;
6854 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6855 set_ring_16byte_desc_enabled(rx_ring);
6856 else
6857 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6858 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6859 }
6860
6861 return 0;
9f65e15b
AD		 6862
6863err_out:
6864 i40e_vsi_clear_rings(vsi);
6865 return -ENOMEM;
41c445ff
JB		 6866}
6867
6868/**
6869 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6870 * @pf: board private structure
6871 * @vectors: the number of MSI-X vectors to request
6872 *
6873 * Returns the number of vectors reserved, or error
6874 **/
6875static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6876{
7b37f376
AG		 6877 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6878 I40E_MIN_MSIX, vectors);
6879 if (vectors < 0) {
41c445ff 6880 dev_info(&pf->pdev->dev,
7b37f376 6881 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6882 vectors = 0;
6883 }
6884
6885 return vectors;
6886}
6887
6888/**
6889 * i40e_init_msix - Setup the MSIX capability
6890 * @pf: board private structure
6891 *
6892 * Work with the OS to set up the MSIX vectors needed.
6893 *
6894 * Returns 0 on success, negative on failure
6895 **/
6896static int i40e_init_msix(struct i40e_pf *pf)
6897{
6898 i40e_status err = 0;
6899 struct i40e_hw *hw = &pf->hw;
c135b0de 6900 int other_vecs = 0;
41c445ff
JB		 6901 int v_budget, i;
6902 int vec;
6903
6904 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6905 return -ENODEV;
6906
6907 /* The number of vectors we'll request will be comprised of:
6908 * - Add 1 for "other" cause for Admin Queue events, etc.
6909 * - The number of LAN queue pairs
f8ff1464
ASJ		 6910 * - Queues being used for RSS.
6911 * We don't need as many as max_rss_size vectors.
6912 * use rss_size instead in the calculation since that
6913 * is governed by number of cpus in the system.
6914 * - assumes symmetric Tx/Rx pairing
41c445ff 6915 * - The number of VMDq pairs
38e00438
VD		 6916#ifdef I40E_FCOE
6917 * - The number of FCOE qps.
6918#endif
41c445ff
JB		 6919 * Once we count this up, try the request.
6920 *
6921 * If we can't get what we want, we'll simplify to nearly nothing
6922 * and try again. If that still fails, we punt.
6923 */
f8ff1464 6924 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff 6925 pf->num_vmdq_msix = pf->num_vmdq_qps;
c135b0de
SN		 6926 other_vecs = 1;
6927 other_vecs += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6928 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
c135b0de 6929 other_vecs++;
41c445ff 6930
83840e4b
JL		 6931 /* Scale down if necessary, and the rings will share vectors */
6932 pf->num_lan_msix = min_t(int, pf->num_lan_msix,
6933 (hw->func_caps.num_msix_vectors - other_vecs));
6934 v_budget = pf->num_lan_msix + other_vecs;
6935
38e00438
VD		 6936#ifdef I40E_FCOE
6937 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6938 pf->num_fcoe_msix = pf->num_fcoe_qps;
6939 v_budget += pf->num_fcoe_msix;
6940 }
38e00438 6941#endif
41c445ff
JB		 6942
6943 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6944 GFP_KERNEL);
6945 if (!pf->msix_entries)
6946 return -ENOMEM;
6947
6948 for (i = 0; i < v_budget; i++)
6949 pf->msix_entries[i].entry = i;
6950 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6951
6952 if (vec != v_budget) {
6953 /* If we have limited resources, we will start with no vectors
6954 * for the special features and then allocate vectors to some
6955 * of these features based on the policy and at the end disable
6956 * the features that did not get any vectors.
6957 */
38e00438
VD		 6958#ifdef I40E_FCOE
6959 pf->num_fcoe_qps = 0;
6960 pf->num_fcoe_msix = 0;
6961#endif
a34977ba
ASJ		 6962 pf->num_vmdq_msix = 0;
6963 }
6964
41c445ff
JB		 6965 if (vec < I40E_MIN_MSIX) {
6966 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6967 kfree(pf->msix_entries);
6968 pf->msix_entries = NULL;
6969 return -ENODEV;
6970
6971 } else if (vec == I40E_MIN_MSIX) {
6972 /* Adjust for minimal MSIX use */
41c445ff
JB		 6973 pf->num_vmdq_vsis = 0;
6974 pf->num_vmdq_qps = 0;
41c445ff
JB		 6975 pf->num_lan_qps = 1;
6976 pf->num_lan_msix = 1;
6977
6978 } else if (vec != v_budget) {
a34977ba
ASJ		 6979 /* reserve the misc vector */
6980 vec--;
6981
41c445ff
JB		 6982 /* Scale vector usage down */
6983 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6984 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6985
6986 /* partition out the remaining vectors */
6987 switch (vec) {
6988 case 2:
41c445ff
JB		 6989 pf->num_lan_msix = 1;
6990 break;
6991 case 3:
38e00438
VD		 6992#ifdef I40E_FCOE
6993 /* give one vector to FCoE */
6994 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6995 pf->num_lan_msix = 1;
6996 pf->num_fcoe_msix = 1;
6997 }
6998#else
41c445ff 6999 pf->num_lan_msix = 2;
38e00438 7000#endif
41c445ff
JB		 7001 break;
7002 default:
38e00438
VD		 7003#ifdef I40E_FCOE
7004 /* give one vector to FCoE */
7005 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7006 pf->num_fcoe_msix = 1;
7007 vec--;
7008 }
7009#endif
41c445ff
JB		 7010 pf->num_lan_msix = min_t(int, (vec / 2),
7011 pf->num_lan_qps);
7012 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
7013 I40E_DEFAULT_NUM_VMDQ_VSI);
7014 break;
7015 }
7016 }
7017
a34977ba
ASJ		 7018 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7019 (pf->num_vmdq_msix == 0)) {
7020 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7021 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7022 }
38e00438
VD		 7023#ifdef I40E_FCOE
7024
7025 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7026 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7027 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7028 }
7029#endif
41c445ff
JB		 7030 return err;
7031}
7032
493fb300 7033/**
90e04070 7034 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7035 * @vsi: the VSI being configured
7036 * @v_idx: index of the vector in the vsi struct
7037 *
7038 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7039 **/
90e04070 7040static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7041{
7042 struct i40e_q_vector *q_vector;
7043
7044 /* allocate q_vector */
7045 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7046 if (!q_vector)
7047 return -ENOMEM;
7048
7049 q_vector->vsi = vsi;
7050 q_vector->v_idx = v_idx;
7051 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7052 if (vsi->netdev)
7053 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7054 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7055
cd0b6fa6
AD		 7056 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7057 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7058
493fb300
AD		 7059 /* tie q_vector and vsi together */
7060 vsi->q_vectors[v_idx] = q_vector;
7061
7062 return 0;
7063}
7064
41c445ff 7065/**
90e04070 7066 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7067 * @vsi: the VSI being configured
7068 *
7069 * We allocate one q_vector per queue interrupt. If allocation fails we
7070 * return -ENOMEM.
7071 **/
90e04070 7072static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7073{
7074 struct i40e_pf *pf = vsi->back;
7075 int v_idx, num_q_vectors;
493fb300 7076 int err;
41c445ff
JB		 7077
7078 /* if not MSIX, give the one vector only to the LAN VSI */
7079 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7080 num_q_vectors = vsi->num_q_vectors;
7081 else if (vsi == pf->vsi[pf->lan_vsi])
7082 num_q_vectors = 1;
7083 else
7084 return -EINVAL;
7085
41c445ff 7086 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7087 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7088 if (err)
7089 goto err_out;
41c445ff
JB		 7090 }
7091
7092 return 0;
493fb300
AD		 7093
7094err_out:
7095 while (v_idx--)
7096 i40e_free_q_vector(vsi, v_idx);
7097
7098 return err;
41c445ff
JB		 7099}
7100
7101/**
7102 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7103 * @pf: board private structure to initialize
7104 **/
7105static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
7106{
7107 int err = 0;
7108
7109 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7110 err = i40e_init_msix(pf);
7111 if (err) {
60ea5f83 7112 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7113#ifdef I40E_FCOE
7114 I40E_FLAG_FCOE_ENABLED |
7115#endif
60ea5f83 7116 I40E_FLAG_RSS_ENABLED |
4d9b6043 7117 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7118 I40E_FLAG_SRIOV_ENABLED |
7119 I40E_FLAG_FD_SB_ENABLED |
7120 I40E_FLAG_FD_ATR_ENABLED |
7121 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7122
7123 /* rework the queue expectations without MSIX */
7124 i40e_determine_queue_usage(pf);
7125 }
7126 }
7127
7128 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7129 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7130 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 7131 err = pci_enable_msi(pf->pdev);
7132 if (err) {
958a3e3b 7133 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 7134 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7135 }
7136 }
7137
958a3e3b 7138 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7139 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7140
41c445ff
JB		 7141 /* track first vector for misc interrupts */
7142 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
7143}
7144
7145/**
7146 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7147 * @pf: board private structure
7148 *
7149 * This sets up the handler for MSIX 0, which is used to manage the
7150 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7151 * when in MSI or Legacy interrupt mode.
7152 **/
7153static int i40e_setup_misc_vector(struct i40e_pf *pf)
7154{
7155 struct i40e_hw *hw = &pf->hw;
7156 int err = 0;
7157
7158 /* Only request the irq if this is the first time through, and
7159 * not when we're rebuilding after a Reset
7160 */
7161 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7162 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7163 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7164 if (err) {
7165 dev_info(&pf->pdev->dev,
77fa28be 7166 "request_irq for %s failed: %d\n",
b294ac70 7167 pf->int_name, err);
41c445ff
JB		 7168 return -EFAULT;
7169 }
7170 }
7171
ab437b5a 7172 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7173
7174 /* associate no queues to the misc vector */
7175 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7176 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7177
7178 i40e_flush(hw);
7179
7180 i40e_irq_dynamic_enable_icr0(pf);
7181
7182 return err;
7183}
7184
7185/**
7186 * i40e_config_rss - Prepare for RSS if used
7187 * @pf: board private structure
7188 **/
7189static int i40e_config_rss(struct i40e_pf *pf)
7190{
22f258a1 7191 u32 rss_key[I40E_PFQF_HKEY_MAX_INDEX + 1];
4617e8c0
ASJ		 7192 struct i40e_hw *hw = &pf->hw;
7193 u32 lut = 0;
7194 int i, j;
7195 u64 hena;
e157ea30 7196 u32 reg_val;
41c445ff 7197
22f258a1 7198 netdev_rss_key_fill(rss_key, sizeof(rss_key));
41c445ff 7199 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
22f258a1 7200 wr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);
41c445ff
JB		 7201
7202 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7203 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7204 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7205 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7206 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7207 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7208
e157ea30
CW		 7209 /* Check capability and Set table size and register per hw expectation*/
7210 reg_val = rd32(hw, I40E_PFQF_CTL_0);
7211 if (hw->func_caps.rss_table_size == 512) {
7212 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7213 pf->rss_table_size = 512;
7214 } else {
7215 pf->rss_table_size = 128;
7216 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7217 }
7218 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7219
41c445ff 7220 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7221 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7222
7223 /* The assumption is that lan qp count will be the highest
7224 * qp count for any PF VSI that needs RSS.
7225 * If multiple VSIs need RSS support, all the qp counts
7226 * for those VSIs should be a power of 2 for RSS to work.
7227 * If LAN VSI is the only consumer for RSS then this requirement
7228 * is not necessary.
7229 */
7230 if (j == pf->rss_size)
7231 j = 0;
7232 /* lut = 4-byte sliding window of 4 lut entries */
7233 lut = (lut << 8) | (j &
7234 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7235 /* On i = 3, we have 4 entries in lut; write to the register */
7236 if ((i & 3) == 3)
7237 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7238 }
7239 i40e_flush(hw);
7240
7241 return 0;
7242}
7243
f8ff1464
ASJ		 7244/**
7245 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7246 * @pf: board private structure
7247 * @queue_count: the requested queue count for rss.
7248 *
7249 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7250 * count which may be different from the requested queue count.
7251 **/
7252int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7253{
7254 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7255 return 0;
7256
7257 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 7258
7259 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 7260 i40e_prep_for_reset(pf);
7261
f8ff1464
ASJ		 7262 pf->rss_size = queue_count;
7263
7264 i40e_reset_and_rebuild(pf, true);
7265 i40e_config_rss(pf);
7266 }
7267 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7268 return pf->rss_size;
7269}
7270
f4492db1
GR		 7271/**
7272 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7273 * @pf: board private structure
7274 **/
7275i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7276{
7277 i40e_status status;
7278 bool min_valid, max_valid;
7279 u32 max_bw, min_bw;
7280
7281 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7282 &min_valid, &max_valid);
7283
7284 if (!status) {
7285 if (min_valid)
7286 pf->npar_min_bw = min_bw;
7287 if (max_valid)
7288 pf->npar_max_bw = max_bw;
7289 }
7290
7291 return status;
7292}
7293
7294/**
7295 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7296 * @pf: board private structure
7297 **/
7298i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7299{
7300 struct i40e_aqc_configure_partition_bw_data bw_data;
7301 i40e_status status;
7302
7303 /* Set the valid bit for this pf */
7304 bw_data.pf_valid_bits = cpu_to_le16(1 << pf->hw.pf_id);
7305 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7306 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7307
7308 /* Set the new bandwidths */
7309 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7310
7311 return status;
7312}
7313
7314/**
7315 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7316 * @pf: board private structure
7317 **/
7318i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7319{
7320 /* Commit temporary BW setting to permanent NVM image */
7321 enum i40e_admin_queue_err last_aq_status;
7322 i40e_status ret;
7323 u16 nvm_word;
7324
7325 if (pf->hw.partition_id != 1) {
7326 dev_info(&pf->pdev->dev,
7327 "Commit BW only works on partition 1! This is partition %d",
7328 pf->hw.partition_id);
7329 ret = I40E_NOT_SUPPORTED;
7330 goto bw_commit_out;
7331 }
7332
7333 /* Acquire NVM for read access */
7334 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7335 last_aq_status = pf->hw.aq.asq_last_status;
7336 if (ret) {
7337 dev_info(&pf->pdev->dev,
7338 "Cannot acquire NVM for read access, err %d: aq_err %d\n",
7339 ret, last_aq_status);
7340 goto bw_commit_out;
7341 }
7342
7343 /* Read word 0x10 of NVM - SW compatibility word 1 */
7344 ret = i40e_aq_read_nvm(&pf->hw,
7345 I40E_SR_NVM_CONTROL_WORD,
7346 0x10, sizeof(nvm_word), &nvm_word,
7347 false, NULL);
7348 /* Save off last admin queue command status before releasing
7349 * the NVM
7350 */
7351 last_aq_status = pf->hw.aq.asq_last_status;
7352 i40e_release_nvm(&pf->hw);
7353 if (ret) {
7354 dev_info(&pf->pdev->dev, "NVM read error, err %d aq_err %d\n",
7355 ret, last_aq_status);
7356 goto bw_commit_out;
7357 }
7358
7359 /* Wait a bit for NVM release to complete */
7360 msleep(50);
7361
7362 /* Acquire NVM for write access */
7363 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7364 last_aq_status = pf->hw.aq.asq_last_status;
7365 if (ret) {
7366 dev_info(&pf->pdev->dev,
7367 "Cannot acquire NVM for write access, err %d: aq_err %d\n",
7368 ret, last_aq_status);
7369 goto bw_commit_out;
7370 }
7371 /* Write it back out unchanged to initiate update NVM,
7372 * which will force a write of the shadow (alt) RAM to
7373 * the NVM - thus storing the bandwidth values permanently.
7374 */
7375 ret = i40e_aq_update_nvm(&pf->hw,
7376 I40E_SR_NVM_CONTROL_WORD,
7377 0x10, sizeof(nvm_word),
7378 &nvm_word, true, NULL);
7379 /* Save off last admin queue command status before releasing
7380 * the NVM
7381 */
7382 last_aq_status = pf->hw.aq.asq_last_status;
7383 i40e_release_nvm(&pf->hw);
7384 if (ret)
7385 dev_info(&pf->pdev->dev,
7386 "BW settings NOT SAVED, err %d aq_err %d\n",
7387 ret, last_aq_status);
7388bw_commit_out:
7389
7390 return ret;
7391}
7392
41c445ff
JB		 7393/**
7394 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7395 * @pf: board private structure to initialize
7396 *
7397 * i40e_sw_init initializes the Adapter private data structure.
7398 * Fields are initialized based on PCI device information and
7399 * OS network device settings (MTU size).
7400 **/
7401static int i40e_sw_init(struct i40e_pf *pf)
7402{
7403 int err = 0;
7404 int size;
7405
7406 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7407 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7408 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7409 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7410 if (I40E_DEBUG_USER & debug)
7411 pf->hw.debug_mask = debug;
7412 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7413 I40E_DEFAULT_MSG_ENABLE);
7414 }
7415
7416 /* Set default capability flags */
7417 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7418 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 7419 I40E_FLAG_MSIX_ENABLED;
7420
7421 if (iommu_present(&pci_bus_type))
7422 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7423 else
7424 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7425
ca99eb99
MW		 7426 /* Set default ITR */
7427 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7428 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7429
7134f9ce
JB		 7430 /* Depending on PF configurations, it is possible that the RSS
7431 * maximum might end up larger than the available queues
7432 */
41c445ff 7433 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7434 pf->rss_size = 1;
7134f9ce
JB		 7435 pf->rss_size_max = min_t(int, pf->rss_size_max,
7436 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7437 if (pf->hw.func_caps.rss) {
7438 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7439 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7440 }
7441
2050bc65
CS		 7442 /* MFP mode enabled */
7443 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7444 pf->flags |= I40E_FLAG_MFP_ENABLED;
7445 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7446 if (i40e_get_npar_bw_setting(pf))
7447 dev_warn(&pf->pdev->dev,
7448 "Could not get NPAR bw settings\n");
7449 else
7450 dev_info(&pf->pdev->dev,
7451 "Min BW = %8.8x, Max BW = %8.8x\n",
7452 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7453 }
7454
cbf61325
ASJ		 7455 /* FW/NVM is not yet fixed in this regard */
7456 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7457 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7458 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7459 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 7460 /* Setup a counter for fd_atr per pf */
7461 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7462 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7463 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 7464 /* Setup a counter for fd_sb per pf */
7465 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7466 } else {
7467 dev_info(&pf->pdev->dev,
0b67584f 7468 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7469 }
cbf61325
ASJ		 7470 pf->fdir_pf_filter_count =
7471 pf->hw.func_caps.fd_filters_guaranteed;
7472 pf->hw.fdir_shared_filter_count =
7473 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7474 }
7475
7476 if (pf->hw.func_caps.vmdq) {
7477 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7478 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7479 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7480 }
7481
38e00438
VD		 7482#ifdef I40E_FCOE
7483 err = i40e_init_pf_fcoe(pf);
7484 if (err)
7485 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7486
7487#endif /* I40E_FCOE */
41c445ff 7488#ifdef CONFIG_PCI_IOV
ba252f13 7489 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7490 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7491 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7492 pf->num_req_vfs = min_t(int,
7493 pf->hw.func_caps.num_vfs,
7494 I40E_MAX_VF_COUNT);
7495 }
7496#endif /* CONFIG_PCI_IOV */
7497 pf->eeprom_version = 0xDEAD;
7498 pf->lan_veb = I40E_NO_VEB;
7499 pf->lan_vsi = I40E_NO_VSI;
7500
7501 /* set up queue assignment tracking */
7502 size = sizeof(struct i40e_lump_tracking)
7503 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7504 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7505 if (!pf->qp_pile) {
7506 err = -ENOMEM;
7507 goto sw_init_done;
7508 }
7509 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7510 pf->qp_pile->search_hint = 0;
7511
7512 /* set up vector assignment tracking */
7513 size = sizeof(struct i40e_lump_tracking)
7514 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
7515 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7516 if (!pf->irq_pile) {
7517 kfree(pf->qp_pile);
7518 err = -ENOMEM;
7519 goto sw_init_done;
7520 }
7521 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
7522 pf->irq_pile->search_hint = 0;
7523
327fe04b
ASJ		 7524 pf->tx_timeout_recovery_level = 1;
7525
41c445ff
JB		 7526 mutex_init(&pf->switch_mutex);
7527
7528sw_init_done:
7529 return err;
7530}
7531
7c3c288b
ASJ		 7532/**
7533 * i40e_set_ntuple - set the ntuple feature flag and take action
7534 * @pf: board private structure to initialize
7535 * @features: the feature set that the stack is suggesting
7536 *
7537 * returns a bool to indicate if reset needs to happen
7538 **/
7539bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7540{
7541 bool need_reset = false;
7542
7543 /* Check if Flow Director n-tuple support was enabled or disabled. If
7544 * the state changed, we need to reset.
7545 */
7546 if (features & NETIF_F_NTUPLE) {
7547 /* Enable filters and mark for reset */
7548 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7549 need_reset = true;
7550 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7551 } else {
7552 /* turn off filters, mark for reset and clear SW filter list */
7553 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7554 need_reset = true;
7555 i40e_fdir_filter_exit(pf);
7556 }
7557 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7558 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7559 /* reset fd counters */
7560 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7561 pf->fdir_pf_active_filters = 0;
7562 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7563 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7564 /* if ATR was auto disabled it can be re-enabled. */
7565 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7566 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7567 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7568 }
7569 return need_reset;
7570}
7571
41c445ff
JB		 7572/**
7573 * i40e_set_features - set the netdev feature flags
7574 * @netdev: ptr to the netdev being adjusted
7575 * @features: the feature set that the stack is suggesting
7576 **/
7577static int i40e_set_features(struct net_device *netdev,
7578 netdev_features_t features)
7579{
7580 struct i40e_netdev_priv *np = netdev_priv(netdev);
7581 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7582 struct i40e_pf *pf = vsi->back;
7583 bool need_reset;
41c445ff
JB		 7584
7585 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7586 i40e_vlan_stripping_enable(vsi);
7587 else
7588 i40e_vlan_stripping_disable(vsi);
7589
7c3c288b
ASJ		 7590 need_reset = i40e_set_ntuple(pf, features);
7591
7592 if (need_reset)
7593 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7594
41c445ff
JB		 7595 return 0;
7596}
7597
a1c9a9d9
JK		 7598#ifdef CONFIG_I40E_VXLAN
7599/**
7600 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7601 * @pf: board private structure
7602 * @port: The UDP port to look up
7603 *
7604 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7605 **/
7606static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7607{
7608 u8 i;
7609
7610 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7611 if (pf->vxlan_ports[i] == port)
7612 return i;
7613 }
7614
7615 return i;
7616}
7617
7618/**
7619 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7620 * @netdev: This physical port's netdev
7621 * @sa_family: Socket Family that VXLAN is notifying us about
7622 * @port: New UDP port number that VXLAN started listening to
7623 **/
7624static void i40e_add_vxlan_port(struct net_device *netdev,
7625 sa_family_t sa_family, __be16 port)
7626{
7627 struct i40e_netdev_priv *np = netdev_priv(netdev);
7628 struct i40e_vsi *vsi = np->vsi;
7629 struct i40e_pf *pf = vsi->back;
7630 u8 next_idx;
7631 u8 idx;
7632
7633 if (sa_family == AF_INET6)
7634 return;
7635
7636 idx = i40e_get_vxlan_port_idx(pf, port);
7637
7638 /* Check if port already exists */
7639 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7640 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7641 return;
7642 }
7643
7644 /* Now check if there is space to add the new port */
7645 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7646
7647 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7648 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7649 ntohs(port));
7650 return;
7651 }
7652
7653 /* New port: add it and mark its index in the bitmap */
7654 pf->vxlan_ports[next_idx] = port;
7655 pf->pending_vxlan_bitmap |= (1 << next_idx);
7656
7657 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7658}
7659
7660/**
7661 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7662 * @netdev: This physical port's netdev
7663 * @sa_family: Socket Family that VXLAN is notifying us about
7664 * @port: UDP port number that VXLAN stopped listening to
7665 **/
7666static void i40e_del_vxlan_port(struct net_device *netdev,
7667 sa_family_t sa_family, __be16 port)
7668{
7669 struct i40e_netdev_priv *np = netdev_priv(netdev);
7670 struct i40e_vsi *vsi = np->vsi;
7671 struct i40e_pf *pf = vsi->back;
7672 u8 idx;
7673
7674 if (sa_family == AF_INET6)
7675 return;
7676
7677 idx = i40e_get_vxlan_port_idx(pf, port);
7678
7679 /* Check if port already exists */
7680 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7681 /* if port exists, set it to 0 (mark for deletion)
7682 * and make it pending
7683 */
7684 pf->vxlan_ports[idx] = 0;
7685
7686 pf->pending_vxlan_bitmap |= (1 << idx);
7687
7688 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7689 } else {
7690 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7691 ntohs(port));
7692 }
7693}
7694
7695#endif
1f224ad2 7696static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 7697 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 7698{
7699 struct i40e_netdev_priv *np = netdev_priv(netdev);
7700 struct i40e_pf *pf = np->vsi->back;
7701 struct i40e_hw *hw = &pf->hw;
7702
7703 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7704 return -EOPNOTSUPP;
7705
7706 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7707 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7708
7709 return 0;
7710}
7711
2f90ade6
JB		 7712/**
7713 * i40e_ndo_fdb_add - add an entry to the hardware database
7714 * @ndm: the input from the stack
7715 * @tb: pointer to array of nladdr (unused)
7716 * @dev: the net device pointer
7717 * @addr: the MAC address entry being added
7718 * @flags: instructions from stack about fdb operation
7719 */
4ba0dea5
GR		 7720static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7721 struct net_device *dev,
f6f6424b 7722 const unsigned char *addr, u16 vid,
4ba0dea5 7723 u16 flags)
4ba0dea5
GR		 7724{
7725 struct i40e_netdev_priv *np = netdev_priv(dev);
7726 struct i40e_pf *pf = np->vsi->back;
7727 int err = 0;
7728
7729 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7730 return -EOPNOTSUPP;
7731
65891fea
OG		 7732 if (vid) {
7733 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
7734 return -EINVAL;
7735 }
7736
4ba0dea5
GR		 7737 /* Hardware does not support aging addresses so if a
7738 * ndm_state is given only allow permanent addresses
7739 */
7740 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7741 netdev_info(dev, "FDB only supports static addresses\n");
7742 return -EINVAL;
7743 }
7744
7745 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7746 err = dev_uc_add_excl(dev, addr);
7747 else if (is_multicast_ether_addr(addr))
7748 err = dev_mc_add_excl(dev, addr);
7749 else
7750 err = -EINVAL;
7751
7752 /* Only return duplicate errors if NLM_F_EXCL is set */
7753 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7754 err = 0;
7755
7756 return err;
7757}
7758
51616018
NP		 7759#ifdef HAVE_BRIDGE_ATTRIBS
7760/**
7761 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
7762 * @dev: the netdev being configured
7763 * @nlh: RTNL message
7764 *
7765 * Inserts a new hardware bridge if not already created and
7766 * enables the bridging mode requested (VEB or VEPA). If the
7767 * hardware bridge has already been inserted and the request
7768 * is to change the mode then that requires a PF reset to
7769 * allow rebuild of the components with required hardware
7770 * bridge mode enabled.
7771 **/
7772static int i40e_ndo_bridge_setlink(struct net_device *dev,
7773 struct nlmsghdr *nlh)
7774{
7775 struct i40e_netdev_priv *np = netdev_priv(dev);
7776 struct i40e_vsi *vsi = np->vsi;
7777 struct i40e_pf *pf = vsi->back;
7778 struct i40e_veb *veb = NULL;
7779 struct nlattr *attr, *br_spec;
7780 int i, rem;
7781
7782 /* Only for PF VSI for now */
7783 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
7784 return -EOPNOTSUPP;
7785
7786 /* Find the HW bridge for PF VSI */
7787 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7788 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7789 veb = pf->veb[i];
7790 }
7791
7792 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7793
7794 nla_for_each_nested(attr, br_spec, rem) {
7795 __u16 mode;
7796
7797 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7798 continue;
7799
7800 mode = nla_get_u16(attr);
7801 if ((mode != BRIDGE_MODE_VEPA) &&
7802 (mode != BRIDGE_MODE_VEB))
7803 return -EINVAL;
7804
7805 /* Insert a new HW bridge */
7806 if (!veb) {
7807 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7808 vsi->tc_config.enabled_tc);
7809 if (veb) {
7810 veb->bridge_mode = mode;
7811 i40e_config_bridge_mode(veb);
7812 } else {
7813 /* No Bridge HW offload available */
7814 return -ENOENT;
7815 }
7816 break;
7817 } else if (mode != veb->bridge_mode) {
7818 /* Existing HW bridge but different mode needs reset */
7819 veb->bridge_mode = mode;
7820 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7821 break;
7822 }
7823 }
7824
7825 return 0;
7826}
7827
7828/**
7829 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
7830 * @skb: skb buff
7831 * @pid: process id
7832 * @seq: RTNL message seq #
7833 * @dev: the netdev being configured
7834 * @filter_mask: unused
7835 *
7836 * Return the mode in which the hardware bridge is operating in
7837 * i.e VEB or VEPA.
7838 **/
7839#ifdef HAVE_BRIDGE_FILTER
7840static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7841 struct net_device *dev,
7842 u32 __always_unused filter_mask)
7843#else
7844static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7845 struct net_device *dev)
7846#endif /* HAVE_BRIDGE_FILTER */
7847{
7848 struct i40e_netdev_priv *np = netdev_priv(dev);
7849 struct i40e_vsi *vsi = np->vsi;
7850 struct i40e_pf *pf = vsi->back;
7851 struct i40e_veb *veb = NULL;
7852 int i;
7853
7854 /* Only for PF VSI for now */
7855 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
7856 return -EOPNOTSUPP;
7857
7858 /* Find the HW bridge for the PF VSI */
7859 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7860 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7861 veb = pf->veb[i];
7862 }
7863
7864 if (!veb)
7865 return 0;
7866
7867 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode);
7868}
7869#endif /* HAVE_BRIDGE_ATTRIBS */
7870
96664483 7871const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 7872 .ndo_open = i40e_open,
7873 .ndo_stop = i40e_close,
7874 .ndo_start_xmit = i40e_lan_xmit_frame,
7875 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7876 .ndo_set_rx_mode = i40e_set_rx_mode,
7877 .ndo_validate_addr = eth_validate_addr,
7878 .ndo_set_mac_address = i40e_set_mac,
7879 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7880 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7881 .ndo_tx_timeout = i40e_tx_timeout,
7882 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7883 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7884#ifdef CONFIG_NET_POLL_CONTROLLER
7885 .ndo_poll_controller = i40e_netpoll,
7886#endif
7887 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 7888#ifdef I40E_FCOE
7889 .ndo_fcoe_enable = i40e_fcoe_enable,
7890 .ndo_fcoe_disable = i40e_fcoe_disable,
7891#endif
41c445ff
JB		 7892 .ndo_set_features = i40e_set_features,
7893 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7894 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7895 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7896 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7897 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 7898 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 7899#ifdef CONFIG_I40E_VXLAN
7900 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7901 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7902#endif
1f224ad2 7903 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 7904 .ndo_fdb_add = i40e_ndo_fdb_add,
51616018
NP		 7905#ifdef HAVE_BRIDGE_ATTRIBS
7906 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
7907 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
7908#endif /* HAVE_BRIDGE_ATTRIBS */
41c445ff
JB		 7909};
7910
7911/**
7912 * i40e_config_netdev - Setup the netdev flags
7913 * @vsi: the VSI being configured
7914 *
7915 * Returns 0 on success, negative value on failure
7916 **/
7917static int i40e_config_netdev(struct i40e_vsi *vsi)
7918{
1a10370a 7919 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7920 struct i40e_pf *pf = vsi->back;
7921 struct i40e_hw *hw = &pf->hw;
7922 struct i40e_netdev_priv *np;
7923 struct net_device *netdev;
7924 u8 mac_addr[ETH_ALEN];
7925 int etherdev_size;
7926
7927 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7928 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7929 if (!netdev)
7930 return -ENOMEM;
7931
7932 vsi->netdev = netdev;
7933 np = netdev_priv(netdev);
7934 np->vsi = vsi;
7935
d70e941b 7936 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7937 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7938 NETIF_F_TSO;
41c445ff
JB		 7939
7940 netdev->features = NETIF_F_SG |
7941 NETIF_F_IP_CSUM |
7942 NETIF_F_SCTP_CSUM |
7943 NETIF_F_HIGHDMA |
7944 NETIF_F_GSO_UDP_TUNNEL |
7945 NETIF_F_HW_VLAN_CTAG_TX |
7946 NETIF_F_HW_VLAN_CTAG_RX |
7947 NETIF_F_HW_VLAN_CTAG_FILTER |
7948 NETIF_F_IPV6_CSUM |
7949 NETIF_F_TSO |
059dab69 7950 NETIF_F_TSO_ECN |
41c445ff
JB		 7951 NETIF_F_TSO6 |
7952 NETIF_F_RXCSUM |
7953 NETIF_F_RXHASH |
7954 0;
7955
2e86a0b6
ASJ		 7956 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7957 netdev->features |= NETIF_F_NTUPLE;
7958
41c445ff
JB		 7959 /* copy netdev features into list of user selectable features */
7960 netdev->hw_features |= netdev->features;
7961
7962 if (vsi->type == I40E_VSI_MAIN) {
7963 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7964 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 7965 /* The following steps are necessary to prevent reception
7966 * of tagged packets - some older NVM configurations load a
7967 * default a MAC-VLAN filter that accepts any tagged packet
7968 * which must be replaced by a normal filter.
8c27d42e 7969 */
30650cc5
SN		 7970 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
7971 i40e_add_filter(vsi, mac_addr,
7972 I40E_VLAN_ANY, false, true);
41c445ff
JB		 7973 } else {
7974 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7975 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7976 pf->vsi[pf->lan_vsi]->netdev->name);
7977 random_ether_addr(mac_addr);
7978 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7979 }
1a10370a 7980 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7981
9a173901
GR		 7982 ether_addr_copy(netdev->dev_addr, mac_addr);
7983 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7984 /* vlan gets same features (except vlan offload)
7985 * after any tweaks for specific VSI types
7986 */
7987 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7988 NETIF_F_HW_VLAN_CTAG_RX |
7989 NETIF_F_HW_VLAN_CTAG_FILTER);
7990 netdev->priv_flags |= IFF_UNICAST_FLT;
7991 netdev->priv_flags |= IFF_SUPP_NOFCS;
7992 /* Setup netdev TC information */
7993 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7994
7995 netdev->netdev_ops = &i40e_netdev_ops;
7996 netdev->watchdog_timeo = 5 * HZ;
7997 i40e_set_ethtool_ops(netdev);
38e00438
VD		 7998#ifdef I40E_FCOE
7999 i40e_fcoe_config_netdev(netdev, vsi);
8000#endif
41c445ff
JB		 8001
8002 return 0;
8003}
8004
8005/**
8006 * i40e_vsi_delete - Delete a VSI from the switch
8007 * @vsi: the VSI being removed
8008 *
8009 * Returns 0 on success, negative value on failure
8010 **/
8011static void i40e_vsi_delete(struct i40e_vsi *vsi)
8012{
8013 /* remove default VSI is not allowed */
8014 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8015 return;
8016
41c445ff 8017 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8018}
8019
51616018
NP		 8020/**
8021 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8022 * @vsi: the VSI being queried
8023 *
8024 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8025 **/
8026int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8027{
8028 struct i40e_veb *veb;
8029 struct i40e_pf *pf = vsi->back;
8030
8031 /* Uplink is not a bridge so default to VEB */
8032 if (vsi->veb_idx == I40E_NO_VEB)
8033 return 1;
8034
8035 veb = pf->veb[vsi->veb_idx];
8036 /* Uplink is a bridge in VEPA mode */
8037 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8038 return 0;
8039
8040 /* Uplink is a bridge in VEB mode */
8041 return 1;
8042}
8043
41c445ff
JB		 8044/**
8045 * i40e_add_vsi - Add a VSI to the switch
8046 * @vsi: the VSI being configured
8047 *
8048 * This initializes a VSI context depending on the VSI type to be added and
8049 * passes it down to the add_vsi aq command.
8050 **/
8051static int i40e_add_vsi(struct i40e_vsi *vsi)
8052{
8053 int ret = -ENODEV;
8054 struct i40e_mac_filter *f, *ftmp;
8055 struct i40e_pf *pf = vsi->back;
8056 struct i40e_hw *hw = &pf->hw;
8057 struct i40e_vsi_context ctxt;
8058 u8 enabled_tc = 0x1; /* TC0 enabled */
8059 int f_count = 0;
8060
8061 memset(&ctxt, 0, sizeof(ctxt));
8062 switch (vsi->type) {
8063 case I40E_VSI_MAIN:
8064 /* The PF's main VSI is already setup as part of the
8065 * device initialization, so we'll not bother with
8066 * the add_vsi call, but we will retrieve the current
8067 * VSI context.
8068 */
8069 ctxt.seid = pf->main_vsi_seid;
8070 ctxt.pf_num = pf->hw.pf_id;
8071 ctxt.vf_num = 0;
8072 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8073 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8074 if (ret) {
8075 dev_info(&pf->pdev->dev,
8076 "couldn't get pf vsi config, err %d, aq_err %d\n",
8077 ret, pf->hw.aq.asq_last_status);
8078 return -ENOENT;
8079 }
8080 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
8081 vsi->info.valid_sections = 0;
8082
8083 vsi->seid = ctxt.seid;
8084 vsi->id = ctxt.vsi_number;
8085
8086 enabled_tc = i40e_pf_get_tc_map(pf);
8087
8088 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8089 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8090 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8091 memset(&ctxt, 0, sizeof(ctxt));
8092 ctxt.seid = pf->main_vsi_seid;
8093 ctxt.pf_num = pf->hw.pf_id;
8094 ctxt.vf_num = 0;
8095 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8096 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8097 if (ret) {
8098 dev_info(&pf->pdev->dev,
8099 "update vsi failed, aq_err=%d\n",
8100 pf->hw.aq.asq_last_status);
8101 ret = -ENOENT;
8102 goto err;
8103 }
8104 /* update the local VSI info queue map */
8105 i40e_vsi_update_queue_map(vsi, &ctxt);
8106 vsi->info.valid_sections = 0;
8107 } else {
8108 /* Default/Main VSI is only enabled for TC0
8109 * reconfigure it to enable all TCs that are
8110 * available on the port in SFP mode.
63d7e5a4
NP		 8111 * For MFP case the iSCSI PF would use this
8112 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8113 */
8114 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8115 if (ret) {
8116 dev_info(&pf->pdev->dev,
8117 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
8118 enabled_tc, ret,
8119 pf->hw.aq.asq_last_status);
8120 ret = -ENOENT;
8121 }
8122 }
8123 break;
8124
8125 case I40E_VSI_FDIR:
cbf61325
ASJ		 8126 ctxt.pf_num = hw->pf_id;
8127 ctxt.vf_num = 0;
8128 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8129 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8130 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
51616018
NP		 8131 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8132 ctxt.info.valid_sections |=
79c21a82 8133 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8134 ctxt.info.switch_id =
79c21a82 8135 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8136 }
41c445ff 8137 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8138 break;
8139
8140 case I40E_VSI_VMDQ2:
8141 ctxt.pf_num = hw->pf_id;
8142 ctxt.vf_num = 0;
8143 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8144 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8145 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8146
41c445ff
JB		 8147 /* This VSI is connected to VEB so the switch_id
8148 * should be set to zero by default.
8149 */
51616018
NP		 8150 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8151 ctxt.info.valid_sections |=
8152 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8153 ctxt.info.switch_id =
8154 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8155 }
41c445ff
JB		 8156
8157 /* Setup the VSI tx/rx queue map for TC0 only for now */
8158 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8159 break;
8160
8161 case I40E_VSI_SRIOV:
8162 ctxt.pf_num = hw->pf_id;
8163 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8164 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8165 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8166 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8167
41c445ff
JB		 8168 /* This VSI is connected to VEB so the switch_id
8169 * should be set to zero by default.
8170 */
51616018
NP		 8171 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8172 ctxt.info.valid_sections |=
8173 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8174 ctxt.info.switch_id =
8175 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8176 }
41c445ff
JB		 8177
8178 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8179 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8180 if (pf->vf[vsi->vf_id].spoofchk) {
8181 ctxt.info.valid_sections |=
8182 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8183 ctxt.info.sec_flags |=
8184 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8185 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8186 }
41c445ff
JB		 8187 /* Setup the VSI tx/rx queue map for TC0 only for now */
8188 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8189 break;
8190
38e00438
VD		 8191#ifdef I40E_FCOE
8192 case I40E_VSI_FCOE:
8193 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8194 if (ret) {
8195 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8196 return ret;
8197 }
8198 break;
8199
8200#endif /* I40E_FCOE */
41c445ff
JB		 8201 default:
8202 return -ENODEV;
8203 }
8204
8205 if (vsi->type != I40E_VSI_MAIN) {
8206 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8207 if (ret) {
8208 dev_info(&vsi->back->pdev->dev,
8209 "add vsi failed, aq_err=%d\n",
8210 vsi->back->hw.aq.asq_last_status);
8211 ret = -ENOENT;
8212 goto err;
8213 }
8214 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
8215 vsi->info.valid_sections = 0;
8216 vsi->seid = ctxt.seid;
8217 vsi->id = ctxt.vsi_number;
8218 }
8219
8220 /* If macvlan filters already exist, force them to get loaded */
8221 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8222 f->changed = true;
8223 f_count++;
6252c7e4
SN		 8224
8225 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8226 struct i40e_aqc_remove_macvlan_element_data element;
8227
8228 memset(&element, 0, sizeof(element));
8229 ether_addr_copy(element.mac_addr, f->macaddr);
8230 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8231 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8232 &element, 1, NULL);
8233 if (ret) {
8234 /* some older FW has a different default */
8235 element.flags |=
8236 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8237 i40e_aq_remove_macvlan(hw, vsi->seid,
8238 &element, 1, NULL);
8239 }
8240
8241 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8242 I40E_AQC_WRITE_TYPE_LAA_WOL,
8243 f->macaddr, NULL);
8244 }
41c445ff
JB		 8245 }
8246 if (f_count) {
8247 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8248 pf->flags |= I40E_FLAG_FILTER_SYNC;
8249 }
8250
8251 /* Update VSI BW information */
8252 ret = i40e_vsi_get_bw_info(vsi);
8253 if (ret) {
8254 dev_info(&pf->pdev->dev,
8255 "couldn't get vsi bw info, err %d, aq_err %d\n",
8256 ret, pf->hw.aq.asq_last_status);
8257 /* VSI is already added so not tearing that up */
8258 ret = 0;
8259 }
8260
8261err:
8262 return ret;
8263}
8264
8265/**
8266 * i40e_vsi_release - Delete a VSI and free its resources
8267 * @vsi: the VSI being removed
8268 *
8269 * Returns 0 on success or < 0 on error
8270 **/
8271int i40e_vsi_release(struct i40e_vsi *vsi)
8272{
8273 struct i40e_mac_filter *f, *ftmp;
8274 struct i40e_veb *veb = NULL;
8275 struct i40e_pf *pf;
8276 u16 uplink_seid;
8277 int i, n;
8278
8279 pf = vsi->back;
8280
8281 /* release of a VEB-owner or last VSI is not allowed */
8282 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8283 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8284 vsi->seid, vsi->uplink_seid);
8285 return -ENODEV;
8286 }
8287 if (vsi == pf->vsi[pf->lan_vsi] &&
8288 !test_bit(__I40E_DOWN, &pf->state)) {
8289 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8290 return -ENODEV;
8291 }
8292
8293 uplink_seid = vsi->uplink_seid;
8294 if (vsi->type != I40E_VSI_SRIOV) {
8295 if (vsi->netdev_registered) {
8296 vsi->netdev_registered = false;
8297 if (vsi->netdev) {
8298 /* results in a call to i40e_close() */
8299 unregister_netdev(vsi->netdev);
41c445ff
JB		 8300 }
8301 } else {
90ef8d47 8302 i40e_vsi_close(vsi);
41c445ff
JB		 8303 }
8304 i40e_vsi_disable_irq(vsi);
8305 }
8306
8307 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8308 i40e_del_filter(vsi, f->macaddr, f->vlan,
8309 f->is_vf, f->is_netdev);
8310 i40e_sync_vsi_filters(vsi);
8311
8312 i40e_vsi_delete(vsi);
8313 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8314 if (vsi->netdev) {
8315 free_netdev(vsi->netdev);
8316 vsi->netdev = NULL;
8317 }
41c445ff
JB		 8318 i40e_vsi_clear_rings(vsi);
8319 i40e_vsi_clear(vsi);
8320
8321 /* If this was the last thing on the VEB, except for the
8322 * controlling VSI, remove the VEB, which puts the controlling
8323 * VSI onto the next level down in the switch.
8324 *
8325 * Well, okay, there's one more exception here: don't remove
8326 * the orphan VEBs yet. We'll wait for an explicit remove request
8327 * from up the network stack.
8328 */
505682cd 8329 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8330 if (pf->vsi[i] &&
8331 pf->vsi[i]->uplink_seid == uplink_seid &&
8332 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8333 n++; /* count the VSIs */
8334 }
8335 }
8336 for (i = 0; i < I40E_MAX_VEB; i++) {
8337 if (!pf->veb[i])
8338 continue;
8339 if (pf->veb[i]->uplink_seid == uplink_seid)
8340 n++; /* count the VEBs */
8341 if (pf->veb[i]->seid == uplink_seid)
8342 veb = pf->veb[i];
8343 }
8344 if (n == 0 && veb && veb->uplink_seid != 0)
8345 i40e_veb_release(veb);
8346
8347 return 0;
8348}
8349
8350/**
8351 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8352 * @vsi: ptr to the VSI
8353 *
8354 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8355 * corresponding SW VSI structure and initializes num_queue_pairs for the
8356 * newly allocated VSI.
8357 *
8358 * Returns 0 on success or negative on failure
8359 **/
8360static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8361{
8362 int ret = -ENOENT;
8363 struct i40e_pf *pf = vsi->back;
8364
493fb300 8365 if (vsi->q_vectors[0]) {
41c445ff
JB		 8366 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8367 vsi->seid);
8368 return -EEXIST;
8369 }
8370
8371 if (vsi->base_vector) {
f29eaa3d 8372 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8373 vsi->seid, vsi->base_vector);
8374 return -EEXIST;
8375 }
8376
90e04070 8377 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8378 if (ret) {
8379 dev_info(&pf->pdev->dev,
8380 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8381 vsi->num_q_vectors, vsi->seid, ret);
8382 vsi->num_q_vectors = 0;
8383 goto vector_setup_out;
8384 }
8385
958a3e3b
SN		 8386 if (vsi->num_q_vectors)
8387 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8388 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8389 if (vsi->base_vector < 0) {
8390 dev_info(&pf->pdev->dev,
049a2be8
SN		 8391 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8392 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8393 i40e_vsi_free_q_vectors(vsi);
8394 ret = -ENOENT;
8395 goto vector_setup_out;
8396 }
8397
8398vector_setup_out:
8399 return ret;
8400}
8401
bc7d338f
ASJ		 8402/**
8403 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8404 * @vsi: pointer to the vsi.
8405 *
8406 * This re-allocates a vsi's queue resources.
8407 *
8408 * Returns pointer to the successfully allocated and configured VSI sw struct
8409 * on success, otherwise returns NULL on failure.
8410 **/
8411static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8412{
8413 struct i40e_pf *pf = vsi->back;
8414 u8 enabled_tc;
8415 int ret;
8416
8417 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8418 i40e_vsi_clear_rings(vsi);
8419
8420 i40e_vsi_free_arrays(vsi, false);
8421 i40e_set_num_rings_in_vsi(vsi);
8422 ret = i40e_vsi_alloc_arrays(vsi, false);
8423 if (ret)
8424 goto err_vsi;
8425
8426 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8427 if (ret < 0) {
049a2be8
SN		 8428 dev_info(&pf->pdev->dev,
8429 "failed to get tracking for %d queues for VSI %d err=%d\n",
8430 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8431 goto err_vsi;
8432 }
8433 vsi->base_queue = ret;
8434
8435 /* Update the FW view of the VSI. Force a reset of TC and queue
8436 * layout configurations.
8437 */
8438 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8439 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8440 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8441 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8442
8443 /* assign it some queues */
8444 ret = i40e_alloc_rings(vsi);
8445 if (ret)
8446 goto err_rings;
8447
8448 /* map all of the rings to the q_vectors */
8449 i40e_vsi_map_rings_to_vectors(vsi);
8450 return vsi;
8451
8452err_rings:
8453 i40e_vsi_free_q_vectors(vsi);
8454 if (vsi->netdev_registered) {
8455 vsi->netdev_registered = false;
8456 unregister_netdev(vsi->netdev);
8457 free_netdev(vsi->netdev);
8458 vsi->netdev = NULL;
8459 }
8460 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8461err_vsi:
8462 i40e_vsi_clear(vsi);
8463 return NULL;
8464}
8465
41c445ff
JB		 8466/**
8467 * i40e_vsi_setup - Set up a VSI by a given type
8468 * @pf: board private structure
8469 * @type: VSI type
8470 * @uplink_seid: the switch element to link to
8471 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8472 *
8473 * This allocates the sw VSI structure and its queue resources, then add a VSI
8474 * to the identified VEB.
8475 *
8476 * Returns pointer to the successfully allocated and configure VSI sw struct on
8477 * success, otherwise returns NULL on failure.
8478 **/
8479struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8480 u16 uplink_seid, u32 param1)
8481{
8482 struct i40e_vsi *vsi = NULL;
8483 struct i40e_veb *veb = NULL;
8484 int ret, i;
8485 int v_idx;
8486
8487 /* The requested uplink_seid must be either
8488 * - the PF's port seid
8489 * no VEB is needed because this is the PF
8490 * or this is a Flow Director special case VSI
8491 * - seid of an existing VEB
8492 * - seid of a VSI that owns an existing VEB
8493 * - seid of a VSI that doesn't own a VEB
8494 * a new VEB is created and the VSI becomes the owner
8495 * - seid of the PF VSI, which is what creates the first VEB
8496 * this is a special case of the previous
8497 *
8498 * Find which uplink_seid we were given and create a new VEB if needed
8499 */
8500 for (i = 0; i < I40E_MAX_VEB; i++) {
8501 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8502 veb = pf->veb[i];
8503 break;
8504 }
8505 }
8506
8507 if (!veb && uplink_seid != pf->mac_seid) {
8508
505682cd 8509 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8510 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8511 vsi = pf->vsi[i];
8512 break;
8513 }
8514 }
8515 if (!vsi) {
8516 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8517 uplink_seid);
8518 return NULL;
8519 }
8520
8521 if (vsi->uplink_seid == pf->mac_seid)
8522 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8523 vsi->tc_config.enabled_tc);
8524 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8525 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8526 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 8527 if (veb) {
8528 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
8529 dev_info(&vsi->back->pdev->dev,
8530 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
8531 __func__);
8532 return NULL;
8533 }
51616018 8534 i40e_config_bridge_mode(veb);
79c21a82 8535 }
41c445ff
JB		 8536 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8537 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8538 veb = pf->veb[i];
8539 }
8540 if (!veb) {
8541 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8542 return NULL;
8543 }
8544
8545 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8546 uplink_seid = veb->seid;
8547 }
8548
8549 /* get vsi sw struct */
8550 v_idx = i40e_vsi_mem_alloc(pf, type);
8551 if (v_idx < 0)
8552 goto err_alloc;
8553 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8554 if (!vsi)
8555 goto err_alloc;
41c445ff
JB		 8556 vsi->type = type;
8557 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8558
8559 if (type == I40E_VSI_MAIN)
8560 pf->lan_vsi = v_idx;
8561 else if (type == I40E_VSI_SRIOV)
8562 vsi->vf_id = param1;
8563 /* assign it some queues */
cbf61325
ASJ		 8564 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8565 vsi->idx);
41c445ff 8566 if (ret < 0) {
049a2be8
SN		 8567 dev_info(&pf->pdev->dev,
8568 "failed to get tracking for %d queues for VSI %d err=%d\n",
8569 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 8570 goto err_vsi;
8571 }
8572 vsi->base_queue = ret;
8573
8574 /* get a VSI from the hardware */
8575 vsi->uplink_seid = uplink_seid;
8576 ret = i40e_add_vsi(vsi);
8577 if (ret)
8578 goto err_vsi;
8579
8580 switch (vsi->type) {
8581 /* setup the netdev if needed */
8582 case I40E_VSI_MAIN:
8583 case I40E_VSI_VMDQ2:
38e00438 8584 case I40E_VSI_FCOE:
41c445ff
JB		 8585 ret = i40e_config_netdev(vsi);
8586 if (ret)
8587 goto err_netdev;
8588 ret = register_netdev(vsi->netdev);
8589 if (ret)
8590 goto err_netdev;
8591 vsi->netdev_registered = true;
8592 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8593#ifdef CONFIG_I40E_DCB
8594 /* Setup DCB netlink interface */
8595 i40e_dcbnl_setup(vsi);
8596#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8597 /* fall through */
8598
8599 case I40E_VSI_FDIR:
8600 /* set up vectors and rings if needed */
8601 ret = i40e_vsi_setup_vectors(vsi);
8602 if (ret)
8603 goto err_msix;
8604
8605 ret = i40e_alloc_rings(vsi);
8606 if (ret)
8607 goto err_rings;
8608
8609 /* map all of the rings to the q_vectors */
8610 i40e_vsi_map_rings_to_vectors(vsi);
8611
8612 i40e_vsi_reset_stats(vsi);
8613 break;
8614
8615 default:
8616 /* no netdev or rings for the other VSI types */
8617 break;
8618 }
8619
8620 return vsi;
8621
8622err_rings:
8623 i40e_vsi_free_q_vectors(vsi);
8624err_msix:
8625 if (vsi->netdev_registered) {
8626 vsi->netdev_registered = false;
8627 unregister_netdev(vsi->netdev);
8628 free_netdev(vsi->netdev);
8629 vsi->netdev = NULL;
8630 }
8631err_netdev:
8632 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8633err_vsi:
8634 i40e_vsi_clear(vsi);
8635err_alloc:
8636 return NULL;
8637}
8638
8639/**
8640 * i40e_veb_get_bw_info - Query VEB BW information
8641 * @veb: the veb to query
8642 *
8643 * Query the Tx scheduler BW configuration data for given VEB
8644 **/
8645static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8646{
8647 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8648 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8649 struct i40e_pf *pf = veb->pf;
8650 struct i40e_hw *hw = &pf->hw;
8651 u32 tc_bw_max;
8652 int ret = 0;
8653 int i;
8654
8655 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8656 &bw_data, NULL);
8657 if (ret) {
8658 dev_info(&pf->pdev->dev,
8659 "query veb bw config failed, aq_err=%d\n",
8660 hw->aq.asq_last_status);
8661 goto out;
8662 }
8663
8664 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8665 &ets_data, NULL);
8666 if (ret) {
8667 dev_info(&pf->pdev->dev,
8668 "query veb bw ets config failed, aq_err=%d\n",
8669 hw->aq.asq_last_status);
8670 goto out;
8671 }
8672
8673 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8674 veb->bw_max_quanta = ets_data.tc_bw_max;
8675 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 8676 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 8677 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8678 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8679 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8680 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8681 veb->bw_tc_limit_credits[i] =
8682 le16_to_cpu(bw_data.tc_bw_limits[i]);
8683 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8684 }
8685
8686out:
8687 return ret;
8688}
8689
8690/**
8691 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8692 * @pf: board private structure
8693 *
8694 * On error: returns error code (negative)
8695 * On success: returns vsi index in PF (positive)
8696 **/
8697static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8698{
8699 int ret = -ENOENT;
8700 struct i40e_veb *veb;
8701 int i;
8702
8703 /* Need to protect the allocation of switch elements at the PF level */
8704 mutex_lock(&pf->switch_mutex);
8705
8706 /* VEB list may be fragmented if VEB creation/destruction has
8707 * been happening. We can afford to do a quick scan to look
8708 * for any free slots in the list.
8709 *
8710 * find next empty veb slot, looping back around if necessary
8711 */
8712 i = 0;
8713 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8714 i++;
8715 if (i >= I40E_MAX_VEB) {
8716 ret = -ENOMEM;
8717 goto err_alloc_veb; /* out of VEB slots! */
8718 }
8719
8720 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8721 if (!veb) {
8722 ret = -ENOMEM;
8723 goto err_alloc_veb;
8724 }
8725 veb->pf = pf;
8726 veb->idx = i;
8727 veb->enabled_tc = 1;
8728
8729 pf->veb[i] = veb;
8730 ret = i;
8731err_alloc_veb:
8732 mutex_unlock(&pf->switch_mutex);
8733 return ret;
8734}
8735
8736/**
8737 * i40e_switch_branch_release - Delete a branch of the switch tree
8738 * @branch: where to start deleting
8739 *
8740 * This uses recursion to find the tips of the branch to be
8741 * removed, deleting until we get back to and can delete this VEB.
8742 **/
8743static void i40e_switch_branch_release(struct i40e_veb *branch)
8744{
8745 struct i40e_pf *pf = branch->pf;
8746 u16 branch_seid = branch->seid;
8747 u16 veb_idx = branch->idx;
8748 int i;
8749
8750 /* release any VEBs on this VEB - RECURSION */
8751 for (i = 0; i < I40E_MAX_VEB; i++) {
8752 if (!pf->veb[i])
8753 continue;
8754 if (pf->veb[i]->uplink_seid == branch->seid)
8755 i40e_switch_branch_release(pf->veb[i]);
8756 }
8757
8758 /* Release the VSIs on this VEB, but not the owner VSI.
8759 *
8760 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8761 * the VEB itself, so don't use (*branch) after this loop.
8762 */
505682cd 8763 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8764 if (!pf->vsi[i])
8765 continue;
8766 if (pf->vsi[i]->uplink_seid == branch_seid &&
8767 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8768 i40e_vsi_release(pf->vsi[i]);
8769 }
8770 }
8771
8772 /* There's one corner case where the VEB might not have been
8773 * removed, so double check it here and remove it if needed.
8774 * This case happens if the veb was created from the debugfs
8775 * commands and no VSIs were added to it.
8776 */
8777 if (pf->veb[veb_idx])
8778 i40e_veb_release(pf->veb[veb_idx]);
8779}
8780
8781/**
8782 * i40e_veb_clear - remove veb struct
8783 * @veb: the veb to remove
8784 **/
8785static void i40e_veb_clear(struct i40e_veb *veb)
8786{
8787 if (!veb)
8788 return;
8789
8790 if (veb->pf) {
8791 struct i40e_pf *pf = veb->pf;
8792
8793 mutex_lock(&pf->switch_mutex);
8794 if (pf->veb[veb->idx] == veb)
8795 pf->veb[veb->idx] = NULL;
8796 mutex_unlock(&pf->switch_mutex);
8797 }
8798
8799 kfree(veb);
8800}
8801
8802/**
8803 * i40e_veb_release - Delete a VEB and free its resources
8804 * @veb: the VEB being removed
8805 **/
8806void i40e_veb_release(struct i40e_veb *veb)
8807{
8808 struct i40e_vsi *vsi = NULL;
8809 struct i40e_pf *pf;
8810 int i, n = 0;
8811
8812 pf = veb->pf;
8813
8814 /* find the remaining VSI and check for extras */
505682cd 8815 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8816 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
8817 n++;
8818 vsi = pf->vsi[i];
8819 }
8820 }
8821 if (n != 1) {
8822 dev_info(&pf->pdev->dev,
8823 "can't remove VEB %d with %d VSIs left\n",
8824 veb->seid, n);
8825 return;
8826 }
8827
8828 /* move the remaining VSI to uplink veb */
8829 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8830 if (veb->uplink_seid) {
8831 vsi->uplink_seid = veb->uplink_seid;
8832 if (veb->uplink_seid == pf->mac_seid)
8833 vsi->veb_idx = I40E_NO_VEB;
8834 else
8835 vsi->veb_idx = veb->veb_idx;
8836 } else {
8837 /* floating VEB */
8838 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8839 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8840 }
8841
8842 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8843 i40e_veb_clear(veb);
41c445ff
JB		 8844}
8845
8846/**
8847 * i40e_add_veb - create the VEB in the switch
8848 * @veb: the VEB to be instantiated
8849 * @vsi: the controlling VSI
8850 **/
8851static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8852{
56747264 8853 bool is_default = false;
e1c51b95 8854 bool is_cloud = false;
41c445ff
JB		 8855 int ret;
8856
8857 /* get a VEB from the hardware */
8858 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8859 veb->enabled_tc, is_default,
8860 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8861 if (ret) {
8862 dev_info(&veb->pf->pdev->dev,
8863 "couldn't add VEB, err %d, aq_err %d\n",
8864 ret, veb->pf->hw.aq.asq_last_status);
8865 return -EPERM;
8866 }
8867
8868 /* get statistics counter */
8869 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8870 &veb->stats_idx, NULL, NULL, NULL);
8871 if (ret) {
8872 dev_info(&veb->pf->pdev->dev,
8873 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8874 ret, veb->pf->hw.aq.asq_last_status);
8875 return -EPERM;
8876 }
8877 ret = i40e_veb_get_bw_info(veb);
8878 if (ret) {
8879 dev_info(&veb->pf->pdev->dev,
8880 "couldn't get VEB bw info, err %d, aq_err %d\n",
8881 ret, veb->pf->hw.aq.asq_last_status);
8882 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8883 return -ENOENT;
8884 }
8885
8886 vsi->uplink_seid = veb->seid;
8887 vsi->veb_idx = veb->idx;
8888 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8889
8890 return 0;
8891}
8892
8893/**
8894 * i40e_veb_setup - Set up a VEB
8895 * @pf: board private structure
8896 * @flags: VEB setup flags
8897 * @uplink_seid: the switch element to link to
8898 * @vsi_seid: the initial VSI seid
8899 * @enabled_tc: Enabled TC bit-map
8900 *
8901 * This allocates the sw VEB structure and links it into the switch
8902 * It is possible and legal for this to be a duplicate of an already
8903 * existing VEB. It is also possible for both uplink and vsi seids
8904 * to be zero, in order to create a floating VEB.
8905 *
8906 * Returns pointer to the successfully allocated VEB sw struct on
8907 * success, otherwise returns NULL on failure.
8908 **/
8909struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8910 u16 uplink_seid, u16 vsi_seid,
8911 u8 enabled_tc)
8912{
8913 struct i40e_veb *veb, *uplink_veb = NULL;
8914 int vsi_idx, veb_idx;
8915 int ret;
8916
8917 /* if one seid is 0, the other must be 0 to create a floating relay */
8918 if ((uplink_seid == 0 || vsi_seid == 0) &&
8919 (uplink_seid + vsi_seid != 0)) {
8920 dev_info(&pf->pdev->dev,
8921 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8922 uplink_seid, vsi_seid);
8923 return NULL;
8924 }
8925
8926 /* make sure there is such a vsi and uplink */
505682cd 8927 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8928 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8929 break;
505682cd 8930 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8931 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8932 vsi_seid);
8933 return NULL;
8934 }
8935
8936 if (uplink_seid && uplink_seid != pf->mac_seid) {
8937 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8938 if (pf->veb[veb_idx] &&
8939 pf->veb[veb_idx]->seid == uplink_seid) {
8940 uplink_veb = pf->veb[veb_idx];
8941 break;
8942 }
8943 }
8944 if (!uplink_veb) {
8945 dev_info(&pf->pdev->dev,
8946 "uplink seid %d not found\n", uplink_seid);
8947 return NULL;
8948 }
8949 }
8950
8951 /* get veb sw struct */
8952 veb_idx = i40e_veb_mem_alloc(pf);
8953 if (veb_idx < 0)
8954 goto err_alloc;
8955 veb = pf->veb[veb_idx];
8956 veb->flags = flags;
8957 veb->uplink_seid = uplink_seid;
8958 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8959 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8960
8961 /* create the VEB in the switch */
8962 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8963 if (ret)
8964 goto err_veb;
1bb8b935
SN		 8965 if (vsi_idx == pf->lan_vsi)
8966 pf->lan_veb = veb->idx;
41c445ff
JB		 8967
8968 return veb;
8969
8970err_veb:
8971 i40e_veb_clear(veb);
8972err_alloc:
8973 return NULL;
8974}
8975
8976/**
8977 * i40e_setup_pf_switch_element - set pf vars based on switch type
8978 * @pf: board private structure
8979 * @ele: element we are building info from
8980 * @num_reported: total number of elements
8981 * @printconfig: should we print the contents
8982 *
8983 * helper function to assist in extracting a few useful SEID values.
8984 **/
8985static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8986 struct i40e_aqc_switch_config_element_resp *ele,
8987 u16 num_reported, bool printconfig)
8988{
8989 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8990 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8991 u8 element_type = ele->element_type;
8992 u16 seid = le16_to_cpu(ele->seid);
8993
8994 if (printconfig)
8995 dev_info(&pf->pdev->dev,
8996 "type=%d seid=%d uplink=%d downlink=%d\n",
8997 element_type, seid, uplink_seid, downlink_seid);
8998
8999 switch (element_type) {
9000 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9001 pf->mac_seid = seid;
9002 break;
9003 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9004 /* Main VEB? */
9005 if (uplink_seid != pf->mac_seid)
9006 break;
9007 if (pf->lan_veb == I40E_NO_VEB) {
9008 int v;
9009
9010 /* find existing or else empty VEB */
9011 for (v = 0; v < I40E_MAX_VEB; v++) {
9012 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9013 pf->lan_veb = v;
9014 break;
9015 }
9016 }
9017 if (pf->lan_veb == I40E_NO_VEB) {
9018 v = i40e_veb_mem_alloc(pf);
9019 if (v < 0)
9020 break;
9021 pf->lan_veb = v;
9022 }
9023 }
9024
9025 pf->veb[pf->lan_veb]->seid = seid;
9026 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9027 pf->veb[pf->lan_veb]->pf = pf;
9028 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9029 break;
9030 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9031 if (num_reported != 1)
9032 break;
9033 /* This is immediately after a reset so we can assume this is
9034 * the PF's VSI
9035 */
9036 pf->mac_seid = uplink_seid;
9037 pf->pf_seid = downlink_seid;
9038 pf->main_vsi_seid = seid;
9039 if (printconfig)
9040 dev_info(&pf->pdev->dev,
9041 "pf_seid=%d main_vsi_seid=%d\n",
9042 pf->pf_seid, pf->main_vsi_seid);
9043 break;
9044 case I40E_SWITCH_ELEMENT_TYPE_PF:
9045 case I40E_SWITCH_ELEMENT_TYPE_VF:
9046 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9047 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9048 case I40E_SWITCH_ELEMENT_TYPE_PE:
9049 case I40E_SWITCH_ELEMENT_TYPE_PA:
9050 /* ignore these for now */
9051 break;
9052 default:
9053 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9054 element_type, seid);
9055 break;
9056 }
9057}
9058
9059/**
9060 * i40e_fetch_switch_configuration - Get switch config from firmware
9061 * @pf: board private structure
9062 * @printconfig: should we print the contents
9063 *
9064 * Get the current switch configuration from the device and
9065 * extract a few useful SEID values.
9066 **/
9067int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9068{
9069 struct i40e_aqc_get_switch_config_resp *sw_config;
9070 u16 next_seid = 0;
9071 int ret = 0;
9072 u8 *aq_buf;
9073 int i;
9074
9075 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9076 if (!aq_buf)
9077 return -ENOMEM;
9078
9079 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9080 do {
9081 u16 num_reported, num_total;
9082
9083 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9084 I40E_AQ_LARGE_BUF,
9085 &next_seid, NULL);
9086 if (ret) {
9087 dev_info(&pf->pdev->dev,
9088 "get switch config failed %d aq_err=%x\n",
9089 ret, pf->hw.aq.asq_last_status);
9090 kfree(aq_buf);
9091 return -ENOENT;
9092 }
9093
9094 num_reported = le16_to_cpu(sw_config->header.num_reported);
9095 num_total = le16_to_cpu(sw_config->header.num_total);
9096
9097 if (printconfig)
9098 dev_info(&pf->pdev->dev,
9099 "header: %d reported %d total\n",
9100 num_reported, num_total);
9101
41c445ff
JB		 9102 for (i = 0; i < num_reported; i++) {
9103 struct i40e_aqc_switch_config_element_resp *ele =
9104 &sw_config->element[i];
9105
9106 i40e_setup_pf_switch_element(pf, ele, num_reported,
9107 printconfig);
9108 }
9109 } while (next_seid != 0);
9110
9111 kfree(aq_buf);
9112 return ret;
9113}
9114
9115/**
9116 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9117 * @pf: board private structure
bc7d338f 9118 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9119 *
9120 * Returns 0 on success, negative value on failure
9121 **/
bc7d338f 9122static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9123{
9124 int ret;
9125
9126 /* find out what's out there already */
9127 ret = i40e_fetch_switch_configuration(pf, false);
9128 if (ret) {
9129 dev_info(&pf->pdev->dev,
9130 "couldn't fetch switch config, err %d, aq_err %d\n",
9131 ret, pf->hw.aq.asq_last_status);
9132 return ret;
9133 }
9134 i40e_pf_reset_stats(pf);
9135
41c445ff 9136 /* first time setup */
bc7d338f 9137 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9138 struct i40e_vsi *vsi = NULL;
9139 u16 uplink_seid;
9140
9141 /* Set up the PF VSI associated with the PF's main VSI
9142 * that is already in the HW switch
9143 */
9144 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9145 uplink_seid = pf->veb[pf->lan_veb]->seid;
9146 else
9147 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9148 if (pf->lan_vsi == I40E_NO_VSI)
9149 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9150 else if (reinit)
9151 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9152 if (!vsi) {
9153 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9154 i40e_fdir_teardown(pf);
9155 return -EAGAIN;
9156 }
41c445ff
JB		 9157 } else {
9158 /* force a reset of TC and queue layout configurations */
9159 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9160 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9161 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9162 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9163 }
9164 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9165
cbf61325
ASJ		 9166 i40e_fdir_sb_setup(pf);
9167
41c445ff
JB		 9168 /* Setup static PF queue filter control settings */
9169 ret = i40e_setup_pf_filter_control(pf);
9170 if (ret) {
9171 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9172 ret);
9173 /* Failure here should not stop continuing other steps */
9174 }
9175
9176 /* enable RSS in the HW, even for only one queue, as the stack can use
9177 * the hash
9178 */
9179 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9180 i40e_config_rss(pf);
9181
9182 /* fill in link information and enable LSE reporting */
21af70fb 9183 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9184 i40e_link_event(pf);
9185
9186 /* Initialize user-specific link properties */
9187 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9188 I40E_AQ_AN_COMPLETED) ? true : false);
9189
9190 /* fill in link information and enable LSE reporting */
21af70fb 9191 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
41c445ff
JB		 9192 i40e_link_event(pf);
9193
d52c20b7 9194 /* Initialize user-specific link properties */
41c445ff
JB		 9195 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9196 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9197
beb0dff1
JK		 9198 i40e_ptp_init(pf);
9199
41c445ff
JB		 9200 return ret;
9201}
9202
41c445ff
JB		 9203/**
9204 * i40e_determine_queue_usage - Work out queue distribution
9205 * @pf: board private structure
9206 **/
9207static void i40e_determine_queue_usage(struct i40e_pf *pf)
9208{
41c445ff
JB		 9209 int queues_left;
9210
9211 pf->num_lan_qps = 0;
38e00438
VD		 9212#ifdef I40E_FCOE
9213 pf->num_fcoe_qps = 0;
9214#endif
41c445ff
JB		 9215
9216 /* Find the max queues to be put into basic use. We'll always be
9217 * using TC0, whether or not DCB is running, and TC0 will get the
9218 * big RSS set.
9219 */
9220 queues_left = pf->hw.func_caps.num_tx_qp;
9221
cbf61325 9222 if ((queues_left == 1) ||
9aa7e935 9223 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9224 /* one qp for PF, no queues for anything else */
9225 queues_left = 0;
9226 pf->rss_size = pf->num_lan_qps = 1;
9227
9228 /* make sure all the fancies are disabled */
60ea5f83 9229 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9230#ifdef I40E_FCOE
9231 I40E_FLAG_FCOE_ENABLED |
9232#endif
60ea5f83
JB		 9233 I40E_FLAG_FD_SB_ENABLED |
9234 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9235 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9236 I40E_FLAG_SRIOV_ENABLED |
9237 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9238 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9239 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9240 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9241 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9242 /* one qp for PF */
9243 pf->rss_size = pf->num_lan_qps = 1;
9244 queues_left -= pf->num_lan_qps;
9245
9246 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9247#ifdef I40E_FCOE
9248 I40E_FLAG_FCOE_ENABLED |
9249#endif
9aa7e935
FZ		 9250 I40E_FLAG_FD_SB_ENABLED |
9251 I40E_FLAG_FD_ATR_ENABLED |
9252 I40E_FLAG_DCB_ENABLED |
9253 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9254 } else {
cbf61325 9255 /* Not enough queues for all TCs */
4d9b6043 9256 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9257 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9258 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9259 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9260 }
9261 pf->num_lan_qps = pf->rss_size_max;
9262 queues_left -= pf->num_lan_qps;
9263 }
9264
38e00438
VD		 9265#ifdef I40E_FCOE
9266 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9267 if (I40E_DEFAULT_FCOE <= queues_left) {
9268 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9269 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9270 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9271 } else {
9272 pf->num_fcoe_qps = 0;
9273 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9274 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9275 }
9276
9277 queues_left -= pf->num_fcoe_qps;
9278 }
9279
9280#endif
cbf61325
ASJ		 9281 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9282 if (queues_left > 1) {
9283 queues_left -= 1; /* save 1 queue for FD */
9284 } else {
9285 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9286 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9287 }
41c445ff
JB		 9288 }
9289
9290 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9291 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9292 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9293 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9294 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9295 }
9296
9297 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9298 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9299 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9300 (queues_left / pf->num_vmdq_qps));
9301 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9302 }
9303
f8ff1464 9304 pf->queues_left = queues_left;
38e00438
VD		 9305#ifdef I40E_FCOE
9306 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9307#endif
41c445ff
JB		 9308}
9309
9310/**
9311 * i40e_setup_pf_filter_control - Setup PF static filter control
9312 * @pf: PF to be setup
9313 *
9314 * i40e_setup_pf_filter_control sets up a pf's initial filter control
9315 * settings. If PE/FCoE are enabled then it will also set the per PF
9316 * based filter sizes required for them. It also enables Flow director,
9317 * ethertype and macvlan type filter settings for the pf.
9318 *
9319 * Returns 0 on success, negative on failure
9320 **/
9321static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9322{
9323 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9324
9325 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9326
9327 /* Flow Director is enabled */
60ea5f83 9328 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9329 settings->enable_fdir = true;
9330
9331 /* Ethtype and MACVLAN filters enabled for PF */
9332 settings->enable_ethtype = true;
9333 settings->enable_macvlan = true;
9334
9335 if (i40e_set_filter_control(&pf->hw, settings))
9336 return -ENOENT;
9337
9338 return 0;
9339}
9340
0c22b3dd
JB		 9341#define INFO_STRING_LEN 255
9342static void i40e_print_features(struct i40e_pf *pf)
9343{
9344 struct i40e_hw *hw = &pf->hw;
9345 char *buf, *string;
9346
9347 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9348 if (!string) {
9349 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9350 return;
9351 }
9352
9353 buf = string;
9354
9355 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9356#ifdef CONFIG_PCI_IOV
9357 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9358#endif
aba237d1
MW		 9359 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9360 pf->hw.func_caps.num_vsis,
9361 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9362 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9363
9364 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9365 buf += sprintf(buf, "RSS ");
0c22b3dd 9366 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9367 buf += sprintf(buf, "FD_ATR ");
9368 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9369 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9370 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9371 }
4d9b6043 9372 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9373 buf += sprintf(buf, "DCB ");
9374 if (pf->flags & I40E_FLAG_PTP)
9375 buf += sprintf(buf, "PTP ");
38e00438
VD		 9376#ifdef I40E_FCOE
9377 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9378 buf += sprintf(buf, "FCOE ");
9379#endif
0c22b3dd
JB		 9380
9381 BUG_ON(buf > (string + INFO_STRING_LEN));
9382 dev_info(&pf->pdev->dev, "%s\n", string);
9383 kfree(string);
9384}
9385
41c445ff
JB		 9386/**
9387 * i40e_probe - Device initialization routine
9388 * @pdev: PCI device information struct
9389 * @ent: entry in i40e_pci_tbl
9390 *
9391 * i40e_probe initializes a pf identified by a pci_dev structure.
9392 * The OS initialization, configuring of the pf private structure,
9393 * and a hardware reset occur.
9394 *
9395 * Returns 0 on success, negative on failure
9396 **/
9397static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9398{
e827845c 9399 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 9400 struct i40e_pf *pf;
9401 struct i40e_hw *hw;
93cd765b 9402 static u16 pfs_found;
d4dfb81a 9403 u16 link_status;
41c445ff
JB		 9404 int err = 0;
9405 u32 len;
8a9eb7d3 9406 u32 i;
41c445ff
JB		 9407
9408 err = pci_enable_device_mem(pdev);
9409 if (err)
9410 return err;
9411
9412 /* set up for high or low dma */
6494294f 9413 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9414 if (err) {
e3e3bfdd
JS		 9415 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9416 if (err) {
9417 dev_err(&pdev->dev,
9418 "DMA configuration failed: 0x%x\n", err);
9419 goto err_dma;
9420 }
41c445ff
JB		 9421 }
9422
9423 /* set up pci connections */
9424 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9425 IORESOURCE_MEM), i40e_driver_name);
9426 if (err) {
9427 dev_info(&pdev->dev,
9428 "pci_request_selected_regions failed %d\n", err);
9429 goto err_pci_reg;
9430 }
9431
9432 pci_enable_pcie_error_reporting(pdev);
9433 pci_set_master(pdev);
9434
9435 /* Now that we have a PCI connection, we need to do the
9436 * low level device setup. This is primarily setting up
9437 * the Admin Queue structures and then querying for the
9438 * device's current profile information.
9439 */
9440 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9441 if (!pf) {
9442 err = -ENOMEM;
9443 goto err_pf_alloc;
9444 }
9445 pf->next_vsi = 0;
9446 pf->pdev = pdev;
9447 set_bit(__I40E_DOWN, &pf->state);
9448
9449 hw = &pf->hw;
9450 hw->back = pf;
9451 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9452 pci_resource_len(pdev, 0));
9453 if (!hw->hw_addr) {
9454 err = -EIO;
9455 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9456 (unsigned int)pci_resource_start(pdev, 0),
9457 (unsigned int)pci_resource_len(pdev, 0), err);
9458 goto err_ioremap;
9459 }
9460 hw->vendor_id = pdev->vendor;
9461 hw->device_id = pdev->device;
9462 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9463 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9464 hw->subsystem_device_id = pdev->subsystem_device;
9465 hw->bus.device = PCI_SLOT(pdev->devfn);
9466 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9467 pf->instance = pfs_found;
41c445ff 9468
5b5faa43
SN		 9469 if (debug != -1) {
9470 pf->msg_enable = pf->hw.debug_mask;
9471 pf->msg_enable = debug;
9472 }
9473
7134f9ce
JB		 9474 /* do a special CORER for clearing PXE mode once at init */
9475 if (hw->revision_id == 0 &&
9476 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9477 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9478 i40e_flush(hw);
9479 msleep(200);
9480 pf->corer_count++;
9481
9482 i40e_clear_pxe_mode(hw);
9483 }
9484
41c445ff 9485 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9486 i40e_clear_hw(hw);
41c445ff
JB		 9487 err = i40e_pf_reset(hw);
9488 if (err) {
9489 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9490 goto err_pf_reset;
9491 }
9492 pf->pfr_count++;
9493
9494 hw->aq.num_arq_entries = I40E_AQ_LEN;
9495 hw->aq.num_asq_entries = I40E_AQ_LEN;
9496 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9497 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9498 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 9499
b294ac70 9500 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 9501 "%s-%s:misc",
9502 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 9503
9504 err = i40e_init_shared_code(hw);
9505 if (err) {
9506 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9507 goto err_pf_reset;
9508 }
9509
d52c20b7
JB		 9510 /* set up a default setting for link flow control */
9511 pf->hw.fc.requested_mode = I40E_FC_NONE;
9512
41c445ff
JB		 9513 err = i40e_init_adminq(hw);
9514 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9515 if (err) {
9516 dev_info(&pdev->dev,
7aa67613 9517 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9518 goto err_pf_reset;
9519 }
9520
7aa67613
CS		 9521 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9522 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9523 dev_info(&pdev->dev,
7aa67613
CS		 9524 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9525 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9526 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9527 dev_info(&pdev->dev,
7aa67613 9528 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62
SN		 9529
9530
4eb3f768
SN		 9531 i40e_verify_eeprom(pf);
9532
2c5fe33b
JB		 9533 /* Rev 0 hardware was never productized */
9534 if (hw->revision_id < 1)
9535 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9536
6ff4ef86 9537 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9538 err = i40e_get_capabilities(pf);
9539 if (err)
9540 goto err_adminq_setup;
9541
9542 err = i40e_sw_init(pf);
9543 if (err) {
9544 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9545 goto err_sw_init;
9546 }
9547
9548 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9549 hw->func_caps.num_rx_qp,
9550 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9551 if (err) {
9552 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9553 goto err_init_lan_hmc;
9554 }
9555
9556 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9557 if (err) {
9558 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9559 err = -ENOENT;
9560 goto err_configure_lan_hmc;
9561 }
9562
b686ece5
NP		 9563 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
9564 * Ignore error return codes because if it was already disabled via
9565 * hardware settings this will fail
9566 */
9567 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
9568 (pf->hw.aq.fw_maj_ver < 4)) {
9569 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
9570 i40e_aq_stop_lldp(hw, true, NULL);
9571 }
9572
41c445ff 9573 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9574 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9575 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9576 err = -EIO;
9577 goto err_mac_addr;
9578 }
9579 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9580 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9581 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9582 if (is_valid_ether_addr(hw->mac.port_addr))
9583 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9584#ifdef I40E_FCOE
9585 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9586 if (err)
9587 dev_info(&pdev->dev,
9588 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9589 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9590 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9591 hw->mac.san_addr);
9592 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9593 }
9594 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9595#endif /* I40E_FCOE */
41c445ff
JB		 9596
9597 pci_set_drvdata(pdev, pf);
9598 pci_save_state(pdev);
4e3b35b0
NP		 9599#ifdef CONFIG_I40E_DCB
9600 err = i40e_init_pf_dcb(pf);
9601 if (err) {
aebfc816 9602 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 9603 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9604 /* Continue without DCB enabled */
4e3b35b0
NP		 9605 }
9606#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9607
9608 /* set up periodic task facility */
9609 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9610 pf->service_timer_period = HZ;
9611
9612 INIT_WORK(&pf->service_task, i40e_service_task);
9613 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9614 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9615 pf->link_check_timeout = jiffies;
9616
8e2773ae
SN		 9617 /* WoL defaults to disabled */
9618 pf->wol_en = false;
9619 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9620
41c445ff
JB		 9621 /* set up the main switch operations */
9622 i40e_determine_queue_usage(pf);
9623 i40e_init_interrupt_scheme(pf);
9624
505682cd
MW		 9625 /* The number of VSIs reported by the FW is the minimum guaranteed
9626 * to us; HW supports far more and we share the remaining pool with
9627 * the other PFs. We allocate space for more than the guarantee with
9628 * the understanding that we might not get them all later.
41c445ff 9629 */
505682cd
MW		 9630 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9631 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9632 else
9633 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9634
9635 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9636 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9637 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9638 if (!pf->vsi) {
9639 err = -ENOMEM;
41c445ff 9640 goto err_switch_setup;
ed87ac09 9641 }
41c445ff 9642
bc7d338f 9643 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9644 if (err) {
9645 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9646 goto err_vsis;
9647 }
8a9eb7d3 9648 /* if FDIR VSI was set up, start it now */
505682cd 9649 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9650 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9651 i40e_vsi_open(pf->vsi[i]);
9652 break;
9653 }
9654 }
41c445ff 9655
7e2453fe
JB		 9656 /* driver is only interested in link up/down and module qualification
9657 * reports from firmware
9658 */
9659 err = i40e_aq_set_phy_int_mask(&pf->hw,
9660 I40E_AQ_EVENT_LINK_UPDOWN |
9661 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9662 if (err)
9663 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9664
cafa2ee6
ASJ		 9665 msleep(75);
9666 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9667 if (err) {
9668 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9669 pf->hw.aq.asq_last_status);
9670 }
9671
41c445ff
JB		 9672 /* The main driver is (mostly) up and happy. We need to set this state
9673 * before setting up the misc vector or we get a race and the vector
9674 * ends up disabled forever.
9675 */
9676 clear_bit(__I40E_DOWN, &pf->state);
9677
9678 /* In case of MSIX we are going to setup the misc vector right here
9679 * to handle admin queue events etc. In case of legacy and MSI
9680 * the misc functionality and queue processing is combined in
9681 * the same vector and that gets setup at open.
9682 */
9683 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9684 err = i40e_setup_misc_vector(pf);
9685 if (err) {
9686 dev_info(&pdev->dev,
9687 "setup of misc vector failed: %d\n", err);
9688 goto err_vsis;
9689 }
9690 }
9691
df805f62 9692#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9693 /* prep for VF support */
9694 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9695 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9696 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9697 u32 val;
9698
9699 /* disable link interrupts for VFs */
9700 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9701 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9702 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9703 i40e_flush(hw);
4aeec010
MW		 9704
9705 if (pci_num_vf(pdev)) {
9706 dev_info(&pdev->dev,
9707 "Active VFs found, allocating resources.\n");
9708 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9709 if (err)
9710 dev_info(&pdev->dev,
9711 "Error %d allocating resources for existing VFs\n",
9712 err);
9713 }
41c445ff 9714 }
df805f62 9715#endif /* CONFIG_PCI_IOV */
41c445ff 9716
93cd765b
ASJ		 9717 pfs_found++;
9718
41c445ff
JB		 9719 i40e_dbg_pf_init(pf);
9720
9721 /* tell the firmware that we're starting */
44033fac 9722 i40e_send_version(pf);
41c445ff
JB		 9723
9724 /* since everything's happy, start the service_task timer */
9725 mod_timer(&pf->service_timer,
9726 round_jiffies(jiffies + pf->service_timer_period));
9727
38e00438
VD		 9728#ifdef I40E_FCOE
9729 /* create FCoE interface */
9730 i40e_fcoe_vsi_setup(pf);
9731
9732#endif
d4dfb81a
CS		 9733 /* Get the negotiated link width and speed from PCI config space */
9734 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9735
9736 i40e_set_pci_config_data(hw, link_status);
9737
69bfb110 9738 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9739 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9740 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9741 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9742 "Unknown"),
9743 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9744 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9745 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9746 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9747 "Unknown"));
9748
9749 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9750 hw->bus.speed < i40e_bus_speed_8000) {
9751 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9752 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9753 }
9754
e827845c
CS		 9755 /* get the requested speeds from the fw */
9756 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
9757 if (err)
9758 dev_info(&pf->pdev->dev, "get phy abilities failed, aq_err %d, advertised speed settings may not be correct\n",
9759 err);
9760 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
9761
0c22b3dd
JB		 9762 /* print a string summarizing features */
9763 i40e_print_features(pf);
9764
41c445ff
JB		 9765 return 0;
9766
9767 /* Unwind what we've done if something failed in the setup */
9768err_vsis:
9769 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9770 i40e_clear_interrupt_scheme(pf);
9771 kfree(pf->vsi);
04b03013
SN		 9772err_switch_setup:
9773 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9774 del_timer_sync(&pf->service_timer);
9775err_mac_addr:
9776err_configure_lan_hmc:
9777 (void)i40e_shutdown_lan_hmc(hw);
9778err_init_lan_hmc:
9779 kfree(pf->qp_pile);
9780 kfree(pf->irq_pile);
9781err_sw_init:
9782err_adminq_setup:
9783 (void)i40e_shutdown_adminq(hw);
9784err_pf_reset:
9785 iounmap(hw->hw_addr);
9786err_ioremap:
9787 kfree(pf);
9788err_pf_alloc:
9789 pci_disable_pcie_error_reporting(pdev);
9790 pci_release_selected_regions(pdev,
9791 pci_select_bars(pdev, IORESOURCE_MEM));
9792err_pci_reg:
9793err_dma:
9794 pci_disable_device(pdev);
9795 return err;
9796}
9797
9798/**
9799 * i40e_remove - Device removal routine
9800 * @pdev: PCI device information struct
9801 *
9802 * i40e_remove is called by the PCI subsystem to alert the driver
9803 * that is should release a PCI device. This could be caused by a
9804 * Hot-Plug event, or because the driver is going to be removed from
9805 * memory.
9806 **/
9807static void i40e_remove(struct pci_dev *pdev)
9808{
9809 struct i40e_pf *pf = pci_get_drvdata(pdev);
9810 i40e_status ret_code;
41c445ff
JB		 9811 int i;
9812
9813 i40e_dbg_pf_exit(pf);
9814
beb0dff1
JK		 9815 i40e_ptp_stop(pf);
9816
41c445ff
JB		 9817 /* no more scheduling of any task */
9818 set_bit(__I40E_DOWN, &pf->state);
9819 del_timer_sync(&pf->service_timer);
9820 cancel_work_sync(&pf->service_task);
9821
eb2d80bc
MW		 9822 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
9823 i40e_free_vfs(pf);
9824 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
9825 }
9826
41c445ff
JB		 9827 i40e_fdir_teardown(pf);
9828
9829 /* If there is a switch structure or any orphans, remove them.
9830 * This will leave only the PF's VSI remaining.
9831 */
9832 for (i = 0; i < I40E_MAX_VEB; i++) {
9833 if (!pf->veb[i])
9834 continue;
9835
9836 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
9837 pf->veb[i]->uplink_seid == 0)
9838 i40e_switch_branch_release(pf->veb[i]);
9839 }
9840
9841 /* Now we can shutdown the PF's VSI, just before we kill
9842 * adminq and hmc.
9843 */
9844 if (pf->vsi[pf->lan_vsi])
9845 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
9846
9847 i40e_stop_misc_vector(pf);
9848 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9849 synchronize_irq(pf->msix_entries[0].vector);
9850 free_irq(pf->msix_entries[0].vector, pf);
9851 }
9852
9853 /* shutdown and destroy the HMC */
60442dea
SN		 9854 if (pf->hw.hmc.hmc_obj) {
9855 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
9856 if (ret_code)
9857 dev_warn(&pdev->dev,
9858 "Failed to destroy the HMC resources: %d\n",
9859 ret_code);
9860 }
41c445ff
JB		 9861
9862 /* shutdown the adminq */
41c445ff
JB		 9863 ret_code = i40e_shutdown_adminq(&pf->hw);
9864 if (ret_code)
9865 dev_warn(&pdev->dev,
9866 "Failed to destroy the Admin Queue resources: %d\n",
9867 ret_code);
9868
9869 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
9870 i40e_clear_interrupt_scheme(pf);
505682cd 9871 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9872 if (pf->vsi[i]) {
9873 i40e_vsi_clear_rings(pf->vsi[i]);
9874 i40e_vsi_clear(pf->vsi[i]);
9875 pf->vsi[i] = NULL;
9876 }
9877 }
9878
9879 for (i = 0; i < I40E_MAX_VEB; i++) {
9880 kfree(pf->veb[i]);
9881 pf->veb[i] = NULL;
9882 }
9883
9884 kfree(pf->qp_pile);
9885 kfree(pf->irq_pile);
41c445ff
JB		 9886 kfree(pf->vsi);
9887
41c445ff
JB		 9888 iounmap(pf->hw.hw_addr);
9889 kfree(pf);
9890 pci_release_selected_regions(pdev,
9891 pci_select_bars(pdev, IORESOURCE_MEM));
9892
9893 pci_disable_pcie_error_reporting(pdev);
9894 pci_disable_device(pdev);
9895}
9896
9897/**
9898 * i40e_pci_error_detected - warning that something funky happened in PCI land
9899 * @pdev: PCI device information struct
9900 *
9901 * Called to warn that something happened and the error handling steps
9902 * are in progress. Allows the driver to quiesce things, be ready for
9903 * remediation.
9904 **/
9905static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
9906 enum pci_channel_state error)
9907{
9908 struct i40e_pf *pf = pci_get_drvdata(pdev);
9909
9910 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9911
9912 /* shutdown all operations */
9007bccd
SN		 9913 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9914 rtnl_lock();
9915 i40e_prep_for_reset(pf);
9916 rtnl_unlock();
9917 }
41c445ff
JB		 9918
9919 /* Request a slot reset */
9920 return PCI_ERS_RESULT_NEED_RESET;
9921}
9922
9923/**
9924 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9925 * @pdev: PCI device information struct
9926 *
9927 * Called to find if the driver can work with the device now that
9928 * the pci slot has been reset. If a basic connection seems good
9929 * (registers are readable and have sane content) then return a
9930 * happy little PCI_ERS_RESULT_xxx.
9931 **/
9932static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9933{
9934 struct i40e_pf *pf = pci_get_drvdata(pdev);
9935 pci_ers_result_t result;
9936 int err;
9937 u32 reg;
9938
9939 dev_info(&pdev->dev, "%s\n", __func__);
9940 if (pci_enable_device_mem(pdev)) {
9941 dev_info(&pdev->dev,
9942 "Cannot re-enable PCI device after reset.\n");
9943 result = PCI_ERS_RESULT_DISCONNECT;
9944 } else {
9945 pci_set_master(pdev);
9946 pci_restore_state(pdev);
9947 pci_save_state(pdev);
9948 pci_wake_from_d3(pdev, false);
9949
9950 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9951 if (reg == 0)
9952 result = PCI_ERS_RESULT_RECOVERED;
9953 else
9954 result = PCI_ERS_RESULT_DISCONNECT;
9955 }
9956
9957 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9958 if (err) {
9959 dev_info(&pdev->dev,
9960 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9961 err);
9962 /* non-fatal, continue */
9963 }
9964
9965 return result;
9966}
9967
9968/**
9969 * i40e_pci_error_resume - restart operations after PCI error recovery
9970 * @pdev: PCI device information struct
9971 *
9972 * Called to allow the driver to bring things back up after PCI error
9973 * and/or reset recovery has finished.
9974 **/
9975static void i40e_pci_error_resume(struct pci_dev *pdev)
9976{
9977 struct i40e_pf *pf = pci_get_drvdata(pdev);
9978
9979 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 9980 if (test_bit(__I40E_SUSPENDED, &pf->state))
9981 return;
9982
9983 rtnl_lock();
41c445ff 9984 i40e_handle_reset_warning(pf);
9007bccd
SN		 9985 rtnl_lock();
9986}
9987
9988/**
9989 * i40e_shutdown - PCI callback for shutting down
9990 * @pdev: PCI device information struct
9991 **/
9992static void i40e_shutdown(struct pci_dev *pdev)
9993{
9994 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9995 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9996
9997 set_bit(__I40E_SUSPENDED, &pf->state);
9998 set_bit(__I40E_DOWN, &pf->state);
9999 rtnl_lock();
10000 i40e_prep_for_reset(pf);
10001 rtnl_unlock();
10002
8e2773ae
SN		 10003 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10004 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10005
9007bccd 10006 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10007 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10008 pci_set_power_state(pdev, PCI_D3hot);
10009 }
10010}
10011
10012#ifdef CONFIG_PM
10013/**
10014 * i40e_suspend - PCI callback for moving to D3
10015 * @pdev: PCI device information struct
10016 **/
10017static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10018{
10019 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10020 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10021
10022 set_bit(__I40E_SUSPENDED, &pf->state);
10023 set_bit(__I40E_DOWN, &pf->state);
88086e5d
MW		 10024 del_timer_sync(&pf->service_timer);
10025 cancel_work_sync(&pf->service_task);
9007bccd
SN		 10026 rtnl_lock();
10027 i40e_prep_for_reset(pf);
10028 rtnl_unlock();
10029
8e2773ae
SN		 10030 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10031 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10032
10033 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10034 pci_set_power_state(pdev, PCI_D3hot);
10035
10036 return 0;
41c445ff
JB		 10037}
10038
9007bccd
SN		 10039/**
10040 * i40e_resume - PCI callback for waking up from D3
10041 * @pdev: PCI device information struct
10042 **/
10043static int i40e_resume(struct pci_dev *pdev)
10044{
10045 struct i40e_pf *pf = pci_get_drvdata(pdev);
10046 u32 err;
10047
10048 pci_set_power_state(pdev, PCI_D0);
10049 pci_restore_state(pdev);
10050 /* pci_restore_state() clears dev->state_saves, so
10051 * call pci_save_state() again to restore it.
10052 */
10053 pci_save_state(pdev);
10054
10055 err = pci_enable_device_mem(pdev);
10056 if (err) {
10057 dev_err(&pdev->dev,
10058 "%s: Cannot enable PCI device from suspend\n",
10059 __func__);
10060 return err;
10061 }
10062 pci_set_master(pdev);
10063
10064 /* no wakeup events while running */
10065 pci_wake_from_d3(pdev, false);
10066
10067 /* handling the reset will rebuild the device state */
10068 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10069 clear_bit(__I40E_DOWN, &pf->state);
10070 rtnl_lock();
10071 i40e_reset_and_rebuild(pf, false);
10072 rtnl_unlock();
10073 }
10074
10075 return 0;
10076}
10077
10078#endif
41c445ff
JB		 10079static const struct pci_error_handlers i40e_err_handler = {
10080 .error_detected = i40e_pci_error_detected,
10081 .slot_reset = i40e_pci_error_slot_reset,
10082 .resume = i40e_pci_error_resume,
10083};
10084
10085static struct pci_driver i40e_driver = {
10086 .name = i40e_driver_name,
10087 .id_table = i40e_pci_tbl,
10088 .probe = i40e_probe,
10089 .remove = i40e_remove,
9007bccd
SN		 10090#ifdef CONFIG_PM
10091 .suspend = i40e_suspend,
10092 .resume = i40e_resume,
10093#endif
10094 .shutdown = i40e_shutdown,
41c445ff
JB		 10095 .err_handler = &i40e_err_handler,
10096 .sriov_configure = i40e_pci_sriov_configure,
10097};
10098
10099/**
10100 * i40e_init_module - Driver registration routine
10101 *
10102 * i40e_init_module is the first routine called when the driver is
10103 * loaded. All it does is register with the PCI subsystem.
10104 **/
10105static int __init i40e_init_module(void)
10106{
10107 pr_info("%s: %s - version %s\n", i40e_driver_name,
10108 i40e_driver_string, i40e_driver_version_str);
10109 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483
GR		 10110
10111#if IS_ENABLED(CONFIG_CONFIGFS_FS)
10112 i40e_configfs_init();
10113#endif /* CONFIG_CONFIGFS_FS */
41c445ff
JB		 10114 i40e_dbg_init();
10115 return pci_register_driver(&i40e_driver);
10116}
10117module_init(i40e_init_module);
10118
10119/**
10120 * i40e_exit_module - Driver exit cleanup routine
10121 *
10122 * i40e_exit_module is called just before the driver is removed
10123 * from memory.
10124 **/
10125static void __exit i40e_exit_module(void)
10126{
10127 pci_unregister_driver(&i40e_driver);
10128 i40e_dbg_exit();
96664483
GR		 10129#if IS_ENABLED(CONFIG_CONFIGFS_FS)
10130 i40e_configfs_exit();
10131#endif /* CONFIG_CONFIGFS_FS */
41c445ff
JB		 10132}
10133module_exit(i40e_exit_module);
Linux kernel - Deliverables
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