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i40e: add VSI info to macaddr messages
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
2818ccd9 4 * Copyright(c) 2013 - 2016 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
b499ffb0
SV		 27#include <linux/etherdevice.h>
28#include <linux/of_net.h>
29#include <linux/pci.h>
30
41c445ff
JB		 31/* Local includes */
32#include "i40e.h"
4eb3f768 33#include "i40e_diag.h"
06a5f7f1 34#include <net/udp_tunnel.h>
41c445ff
JB		 35
36const char i40e_driver_name[] = "i40e";
37static const char i40e_driver_string[] =
38 "Intel(R) Ethernet Connection XL710 Network Driver";
39
40#define DRV_KERN "-k"
41
e8e724db 42#define DRV_VERSION_MAJOR 1
50f26a50 43#define DRV_VERSION_MINOR 5
c74dff1a 44#define DRV_VERSION_BUILD 16
41c445ff
JB		 45#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
46 __stringify(DRV_VERSION_MINOR) "." \
47 __stringify(DRV_VERSION_BUILD) DRV_KERN
48const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 49static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 50
51/* a bit of forward declarations */
52static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
53static void i40e_handle_reset_warning(struct i40e_pf *pf);
54static int i40e_add_vsi(struct i40e_vsi *vsi);
55static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 56static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 57static int i40e_setup_misc_vector(struct i40e_pf *pf);
58static void i40e_determine_queue_usage(struct i40e_pf *pf);
59static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 60static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
61 u16 rss_table_size, u16 rss_size);
cbf61325 62static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 63static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 64
65/* i40e_pci_tbl - PCI Device ID Table
66 *
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
9baa3c34 72static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
ab60085e
SN		 75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
35dae51d
ASJ		 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
87e6c1d7
ASJ		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
d6bf58c2 88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},
a3aa5036 89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_I_X722), 0},
48a3b512
SN		 90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
91 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 92 /* required last entry */
93 {0, }
94};
95MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
96
97#define I40E_MAX_VF_COUNT 128
98static int debug = -1;
99module_param(debug, int, 0);
100MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
101
102MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
103MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
104MODULE_LICENSE("GPL");
105MODULE_VERSION(DRV_VERSION);
106
2803b16c
JB		 107static struct workqueue_struct *i40e_wq;
108
41c445ff
JB		 109/**
110 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
111 * @hw: pointer to the HW structure
112 * @mem: ptr to mem struct to fill out
113 * @size: size of memory requested
114 * @alignment: what to align the allocation to
115 **/
116int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
117 u64 size, u32 alignment)
118{
119 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
120
121 mem->size = ALIGN(size, alignment);
122 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
123 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 124 if (!mem->va)
125 return -ENOMEM;
41c445ff 126
93bc73b8 127 return 0;
41c445ff
JB		 128}
129
130/**
131 * i40e_free_dma_mem_d - OS specific memory free for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to free
134 **/
135int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
136{
137 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
138
139 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
140 mem->va = NULL;
141 mem->pa = 0;
142 mem->size = 0;
143
144 return 0;
145}
146
147/**
148 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
149 * @hw: pointer to the HW structure
150 * @mem: ptr to mem struct to fill out
151 * @size: size of memory requested
152 **/
153int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
154 u32 size)
155{
156 mem->size = size;
157 mem->va = kzalloc(size, GFP_KERNEL);
158
93bc73b8
JB		 159 if (!mem->va)
160 return -ENOMEM;
41c445ff 161
93bc73b8 162 return 0;
41c445ff
JB		 163}
164
165/**
166 * i40e_free_virt_mem_d - OS specific memory free for shared code
167 * @hw: pointer to the HW structure
168 * @mem: ptr to mem struct to free
169 **/
170int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
171{
172 /* it's ok to kfree a NULL pointer */
173 kfree(mem->va);
174 mem->va = NULL;
175 mem->size = 0;
176
177 return 0;
178}
179
180/**
181 * i40e_get_lump - find a lump of free generic resource
182 * @pf: board private structure
183 * @pile: the pile of resource to search
184 * @needed: the number of items needed
185 * @id: an owner id to stick on the items assigned
186 *
187 * Returns the base item index of the lump, or negative for error
188 *
189 * The search_hint trick and lack of advanced fit-finding only work
190 * because we're highly likely to have all the same size lump requests.
191 * Linear search time and any fragmentation should be minimal.
192 **/
193static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
194 u16 needed, u16 id)
195{
196 int ret = -ENOMEM;
ddf434ac 197 int i, j;
41c445ff
JB		 198
199 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
200 dev_info(&pf->pdev->dev,
201 "param err: pile=%p needed=%d id=0x%04x\n",
202 pile, needed, id);
203 return -EINVAL;
204 }
205
206 /* start the linear search with an imperfect hint */
207 i = pile->search_hint;
ddf434ac 208 while (i < pile->num_entries) {
41c445ff
JB		 209 /* skip already allocated entries */
210 if (pile->list[i] & I40E_PILE_VALID_BIT) {
211 i++;
212 continue;
213 }
214
215 /* do we have enough in this lump? */
216 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
217 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
218 break;
219 }
220
221 if (j == needed) {
222 /* there was enough, so assign it to the requestor */
223 for (j = 0; j < needed; j++)
224 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
225 ret = i;
226 pile->search_hint = i + j;
ddf434ac 227 break;
41c445ff 228 }
6995b36c
JB		 229
230 /* not enough, so skip over it and continue looking */
231 i += j;
41c445ff
JB		 232 }
233
234 return ret;
235}
236
237/**
238 * i40e_put_lump - return a lump of generic resource
239 * @pile: the pile of resource to search
240 * @index: the base item index
241 * @id: the owner id of the items assigned
242 *
243 * Returns the count of items in the lump
244 **/
245static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
246{
247 int valid_id = (id | I40E_PILE_VALID_BIT);
248 int count = 0;
249 int i;
250
251 if (!pile || index >= pile->num_entries)
252 return -EINVAL;
253
254 for (i = index;
255 i < pile->num_entries && pile->list[i] == valid_id;
256 i++) {
257 pile->list[i] = 0;
258 count++;
259 }
260
261 if (count && index < pile->search_hint)
262 pile->search_hint = index;
263
264 return count;
265}
266
fdf0e0bf
ASJ		 267/**
268 * i40e_find_vsi_from_id - searches for the vsi with the given id
269 * @pf - the pf structure to search for the vsi
270 * @id - id of the vsi it is searching for
271 **/
272struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
273{
274 int i;
275
276 for (i = 0; i < pf->num_alloc_vsi; i++)
277 if (pf->vsi[i] && (pf->vsi[i]->id == id))
278 return pf->vsi[i];
279
280 return NULL;
281}
282
41c445ff
JB		 283/**
284 * i40e_service_event_schedule - Schedule the service task to wake up
285 * @pf: board private structure
286 *
287 * If not already scheduled, this puts the task into the work queue
288 **/
e3219ce6 289void i40e_service_event_schedule(struct i40e_pf *pf)
41c445ff
JB		 290{
291 if (!test_bit(__I40E_DOWN, &pf->state) &&
292 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
293 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
2803b16c 294 queue_work(i40e_wq, &pf->service_task);
41c445ff
JB		 295}
296
297/**
298 * i40e_tx_timeout - Respond to a Tx Hang
299 * @netdev: network interface device structure
300 *
301 * If any port has noticed a Tx timeout, it is likely that the whole
302 * device is munged, not just the one netdev port, so go for the full
303 * reset.
304 **/
38e00438
VD		 305#ifdef I40E_FCOE
306void i40e_tx_timeout(struct net_device *netdev)
307#else
41c445ff 308static void i40e_tx_timeout(struct net_device *netdev)
38e00438 309#endif
41c445ff
JB		 310{
311 struct i40e_netdev_priv *np = netdev_priv(netdev);
312 struct i40e_vsi *vsi = np->vsi;
313 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 314 struct i40e_ring *tx_ring = NULL;
315 unsigned int i, hung_queue = 0;
316 u32 head, val;
41c445ff
JB		 317
318 pf->tx_timeout_count++;
319
b03a8c1f
KP		 320 /* find the stopped queue the same way the stack does */
321 for (i = 0; i < netdev->num_tx_queues; i++) {
322 struct netdev_queue *q;
323 unsigned long trans_start;
324
325 q = netdev_get_tx_queue(netdev, i);
9b36627a 326 trans_start = q->trans_start;
b03a8c1f
KP		 327 if (netif_xmit_stopped(q) &&
328 time_after(jiffies,
329 (trans_start + netdev->watchdog_timeo))) {
330 hung_queue = i;
331 break;
332 }
333 }
334
335 if (i == netdev->num_tx_queues) {
336 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
337 } else {
338 /* now that we have an index, find the tx_ring struct */
339 for (i = 0; i < vsi->num_queue_pairs; i++) {
340 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
341 if (hung_queue ==
342 vsi->tx_rings[i]->queue_index) {
343 tx_ring = vsi->tx_rings[i];
344 break;
345 }
346 }
347 }
348 }
349
41c445ff 350 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 351 pf->tx_timeout_recovery_level = 1; /* reset after some time */
352 else if (time_before(jiffies,
353 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
354 return; /* don't do any new action before the next timeout */
355
356 if (tx_ring) {
357 head = i40e_get_head(tx_ring);
358 /* Read interrupt register */
359 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
360 val = rd32(&pf->hw,
361 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
362 tx_ring->vsi->base_vector - 1));
363 else
364 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
365
366 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
367 vsi->seid, hung_queue, tx_ring->next_to_clean,
368 head, tx_ring->next_to_use,
369 readl(tx_ring->tail), val);
370 }
371
41c445ff 372 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 373 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
374 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 375
376 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 377 case 1:
378 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
379 break;
380 case 2:
381 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
382 break;
383 case 3:
384 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
385 break;
386 default:
387 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 388 break;
389 }
b03a8c1f 390
41c445ff
JB		 391 i40e_service_event_schedule(pf);
392 pf->tx_timeout_recovery_level++;
393}
394
41c445ff
JB		 395/**
396 * i40e_get_vsi_stats_struct - Get System Network Statistics
397 * @vsi: the VSI we care about
398 *
399 * Returns the address of the device statistics structure.
400 * The statistics are actually updated from the service task.
401 **/
402struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
403{
404 return &vsi->net_stats;
405}
406
407/**
408 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
409 * @netdev: network interface device structure
410 *
411 * Returns the address of the device statistics structure.
412 * The statistics are actually updated from the service task.
413 **/
38e00438
VD		 414#ifdef I40E_FCOE
415struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
416 struct net_device *netdev,
417 struct rtnl_link_stats64 *stats)
418#else
41c445ff
JB		 419static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
420 struct net_device *netdev,
980e9b11 421 struct rtnl_link_stats64 *stats)
38e00438 422#endif
41c445ff
JB		 423{
424 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 425 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 426 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 427 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
428 int i;
429
bc7d338f
ASJ		 430 if (test_bit(__I40E_DOWN, &vsi->state))
431 return stats;
432
3c325ced
JB		 433 if (!vsi->tx_rings)
434 return stats;
435
980e9b11
AD		 436 rcu_read_lock();
437 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 438 u64 bytes, packets;
439 unsigned int start;
440
441 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
442 if (!tx_ring)
443 continue;
444
445 do {
57a7744e 446 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 447 packets = tx_ring->stats.packets;
448 bytes = tx_ring->stats.bytes;
57a7744e 449 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 450
451 stats->tx_packets += packets;
452 stats->tx_bytes += bytes;
453 rx_ring = &tx_ring[1];
454
455 do {
57a7744e 456 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 457 packets = rx_ring->stats.packets;
458 bytes = rx_ring->stats.bytes;
57a7744e 459 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 460
980e9b11
AD		 461 stats->rx_packets += packets;
462 stats->rx_bytes += bytes;
463 }
464 rcu_read_unlock();
465
a5282f44 466 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 467 stats->multicast = vsi_stats->multicast;
468 stats->tx_errors = vsi_stats->tx_errors;
469 stats->tx_dropped = vsi_stats->tx_dropped;
470 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 471 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 472 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
473 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 474
980e9b11 475 return stats;
41c445ff
JB		 476}
477
478/**
479 * i40e_vsi_reset_stats - Resets all stats of the given vsi
480 * @vsi: the VSI to have its stats reset
481 **/
482void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
483{
484 struct rtnl_link_stats64 *ns;
485 int i;
486
487 if (!vsi)
488 return;
489
490 ns = i40e_get_vsi_stats_struct(vsi);
491 memset(ns, 0, sizeof(*ns));
492 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
493 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
494 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 495 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 496 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 497 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 498 sizeof(vsi->rx_rings[i]->stats));
6995b36c 499 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 500 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 501 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 502 sizeof(vsi->tx_rings[i]->stats));
503 memset(&vsi->tx_rings[i]->tx_stats, 0,
504 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 505 }
8e9dca53 506 }
41c445ff
JB		 507 vsi->stat_offsets_loaded = false;
508}
509
510/**
b40c82e6 511 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 512 * @pf: the PF to be reset
513 **/
514void i40e_pf_reset_stats(struct i40e_pf *pf)
515{
e91fdf76
SN		 516 int i;
517
41c445ff
JB		 518 memset(&pf->stats, 0, sizeof(pf->stats));
519 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
520 pf->stat_offsets_loaded = false;
e91fdf76
SN		 521
522 for (i = 0; i < I40E_MAX_VEB; i++) {
523 if (pf->veb[i]) {
524 memset(&pf->veb[i]->stats, 0,
525 sizeof(pf->veb[i]->stats));
526 memset(&pf->veb[i]->stats_offsets, 0,
527 sizeof(pf->veb[i]->stats_offsets));
528 pf->veb[i]->stat_offsets_loaded = false;
529 }
530 }
41c445ff
JB		 531}
532
533/**
534 * i40e_stat_update48 - read and update a 48 bit stat from the chip
535 * @hw: ptr to the hardware info
536 * @hireg: the high 32 bit reg to read
537 * @loreg: the low 32 bit reg to read
538 * @offset_loaded: has the initial offset been loaded yet
539 * @offset: ptr to current offset value
540 * @stat: ptr to the stat
541 *
542 * Since the device stats are not reset at PFReset, they likely will not
543 * be zeroed when the driver starts. We'll save the first values read
544 * and use them as offsets to be subtracted from the raw values in order
545 * to report stats that count from zero. In the process, we also manage
546 * the potential roll-over.
547 **/
548static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
549 bool offset_loaded, u64 *offset, u64 *stat)
550{
551 u64 new_data;
552
ab60085e 553 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 554 new_data = rd32(hw, loreg);
555 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
556 } else {
557 new_data = rd64(hw, loreg);
558 }
559 if (!offset_loaded)
560 *offset = new_data;
561 if (likely(new_data >= *offset))
562 *stat = new_data - *offset;
563 else
41a1d04b 564 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 565 *stat &= 0xFFFFFFFFFFFFULL;
566}
567
568/**
569 * i40e_stat_update32 - read and update a 32 bit stat from the chip
570 * @hw: ptr to the hardware info
571 * @reg: the hw reg to read
572 * @offset_loaded: has the initial offset been loaded yet
573 * @offset: ptr to current offset value
574 * @stat: ptr to the stat
575 **/
576static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
577 bool offset_loaded, u64 *offset, u64 *stat)
578{
579 u32 new_data;
580
581 new_data = rd32(hw, reg);
582 if (!offset_loaded)
583 *offset = new_data;
584 if (likely(new_data >= *offset))
585 *stat = (u32)(new_data - *offset);
586 else
41a1d04b 587 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 588}
589
590/**
591 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
592 * @vsi: the VSI to be updated
593 **/
594void i40e_update_eth_stats(struct i40e_vsi *vsi)
595{
596 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
597 struct i40e_pf *pf = vsi->back;
598 struct i40e_hw *hw = &pf->hw;
599 struct i40e_eth_stats *oes;
600 struct i40e_eth_stats *es; /* device's eth stats */
601
602 es = &vsi->eth_stats;
603 oes = &vsi->eth_stats_offsets;
604
605 /* Gather up the stats that the hw collects */
606 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
607 vsi->stat_offsets_loaded,
608 &oes->tx_errors, &es->tx_errors);
609 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
610 vsi->stat_offsets_loaded,
611 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 612 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
613 vsi->stat_offsets_loaded,
614 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
615 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
616 vsi->stat_offsets_loaded,
617 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 618
619 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
620 I40E_GLV_GORCL(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->rx_bytes, &es->rx_bytes);
623 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
624 I40E_GLV_UPRCL(stat_idx),
625 vsi->stat_offsets_loaded,
626 &oes->rx_unicast, &es->rx_unicast);
627 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
628 I40E_GLV_MPRCL(stat_idx),
629 vsi->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
632 I40E_GLV_BPRCL(stat_idx),
633 vsi->stat_offsets_loaded,
634 &oes->rx_broadcast, &es->rx_broadcast);
635
636 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
637 I40E_GLV_GOTCL(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->tx_bytes, &es->tx_bytes);
640 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
641 I40E_GLV_UPTCL(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->tx_unicast, &es->tx_unicast);
644 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
645 I40E_GLV_MPTCL(stat_idx),
646 vsi->stat_offsets_loaded,
647 &oes->tx_multicast, &es->tx_multicast);
648 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
649 I40E_GLV_BPTCL(stat_idx),
650 vsi->stat_offsets_loaded,
651 &oes->tx_broadcast, &es->tx_broadcast);
652 vsi->stat_offsets_loaded = true;
653}
654
655/**
656 * i40e_update_veb_stats - Update Switch component statistics
657 * @veb: the VEB being updated
658 **/
659static void i40e_update_veb_stats(struct i40e_veb *veb)
660{
661 struct i40e_pf *pf = veb->pf;
662 struct i40e_hw *hw = &pf->hw;
663 struct i40e_eth_stats *oes;
664 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 665 struct i40e_veb_tc_stats *veb_oes;
666 struct i40e_veb_tc_stats *veb_es;
667 int i, idx = 0;
41c445ff
JB		 668
669 idx = veb->stats_idx;
670 es = &veb->stats;
671 oes = &veb->stats_offsets;
fe860afb
NP		 672 veb_es = &veb->tc_stats;
673 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 674
675 /* Gather up the stats that the hw collects */
676 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
677 veb->stat_offsets_loaded,
678 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 679 if (hw->revision_id > 0)
680 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
681 veb->stat_offsets_loaded,
682 &oes->rx_unknown_protocol,
683 &es->rx_unknown_protocol);
41c445ff
JB		 684 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
685 veb->stat_offsets_loaded,
686 &oes->rx_bytes, &es->rx_bytes);
687 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
688 veb->stat_offsets_loaded,
689 &oes->rx_unicast, &es->rx_unicast);
690 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
691 veb->stat_offsets_loaded,
692 &oes->rx_multicast, &es->rx_multicast);
693 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
694 veb->stat_offsets_loaded,
695 &oes->rx_broadcast, &es->rx_broadcast);
696
697 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
698 veb->stat_offsets_loaded,
699 &oes->tx_bytes, &es->tx_bytes);
700 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
701 veb->stat_offsets_loaded,
702 &oes->tx_unicast, &es->tx_unicast);
703 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
704 veb->stat_offsets_loaded,
705 &oes->tx_multicast, &es->tx_multicast);
706 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 709 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
710 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
711 I40E_GLVEBTC_RPCL(i, idx),
712 veb->stat_offsets_loaded,
713 &veb_oes->tc_rx_packets[i],
714 &veb_es->tc_rx_packets[i]);
715 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
716 I40E_GLVEBTC_RBCL(i, idx),
717 veb->stat_offsets_loaded,
718 &veb_oes->tc_rx_bytes[i],
719 &veb_es->tc_rx_bytes[i]);
720 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
721 I40E_GLVEBTC_TPCL(i, idx),
722 veb->stat_offsets_loaded,
723 &veb_oes->tc_tx_packets[i],
724 &veb_es->tc_tx_packets[i]);
725 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
726 I40E_GLVEBTC_TBCL(i, idx),
727 veb->stat_offsets_loaded,
728 &veb_oes->tc_tx_bytes[i],
729 &veb_es->tc_tx_bytes[i]);
730 }
41c445ff
JB		 731 veb->stat_offsets_loaded = true;
732}
733
38e00438
VD		 734#ifdef I40E_FCOE
735/**
736 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
737 * @vsi: the VSI that is capable of doing FCoE
738 **/
739static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
740{
741 struct i40e_pf *pf = vsi->back;
742 struct i40e_hw *hw = &pf->hw;
743 struct i40e_fcoe_stats *ofs;
744 struct i40e_fcoe_stats *fs; /* device's eth stats */
745 int idx;
746
747 if (vsi->type != I40E_VSI_FCOE)
748 return;
749
4147e2c5 750 idx = hw->pf_id + I40E_FCOE_PF_STAT_OFFSET;
38e00438
VD		 751 fs = &vsi->fcoe_stats;
752 ofs = &vsi->fcoe_stats_offsets;
753
754 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
755 vsi->fcoe_stat_offsets_loaded,
756 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
757 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
758 vsi->fcoe_stat_offsets_loaded,
759 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
760 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
761 vsi->fcoe_stat_offsets_loaded,
762 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
763 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
764 vsi->fcoe_stat_offsets_loaded,
765 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
766 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
767 vsi->fcoe_stat_offsets_loaded,
768 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
769 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
770 vsi->fcoe_stat_offsets_loaded,
771 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
772 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
773 vsi->fcoe_stat_offsets_loaded,
774 &ofs->fcoe_last_error, &fs->fcoe_last_error);
775 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
778
779 vsi->fcoe_stat_offsets_loaded = true;
780}
781
782#endif
41c445ff 783/**
7812fddc 784 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 785 * @vsi: the VSI to be updated
786 *
787 * There are a few instances where we store the same stat in a
788 * couple of different structs. This is partly because we have
789 * the netdev stats that need to be filled out, which is slightly
790 * different from the "eth_stats" defined by the chip and used in
7812fddc 791 * VF communications. We sort it out here.
41c445ff 792 **/
7812fddc 793static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 794{
795 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 796 struct rtnl_link_stats64 *ons;
797 struct rtnl_link_stats64 *ns; /* netdev stats */
798 struct i40e_eth_stats *oes;
799 struct i40e_eth_stats *es; /* device's eth stats */
800 u32 tx_restart, tx_busy;
dd353109 801 u64 tx_lost_interrupt;
bf00b376 802 struct i40e_ring *p;
41c445ff 803 u32 rx_page, rx_buf;
bf00b376
AA		 804 u64 bytes, packets;
805 unsigned int start;
2fc3d715 806 u64 tx_linearize;
164c9f54 807 u64 tx_force_wb;
41c445ff
JB		 808 u64 rx_p, rx_b;
809 u64 tx_p, tx_b;
41c445ff
JB		 810 u16 q;
811
812 if (test_bit(__I40E_DOWN, &vsi->state) ||
813 test_bit(__I40E_CONFIG_BUSY, &pf->state))
814 return;
815
816 ns = i40e_get_vsi_stats_struct(vsi);
817 ons = &vsi->net_stats_offsets;
818 es = &vsi->eth_stats;
819 oes = &vsi->eth_stats_offsets;
820
821 /* Gather up the netdev and vsi stats that the driver collects
822 * on the fly during packet processing
823 */
824 rx_b = rx_p = 0;
825 tx_b = tx_p = 0;
164c9f54 826 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
dd353109 827 tx_lost_interrupt = 0;
41c445ff
JB		 828 rx_page = 0;
829 rx_buf = 0;
980e9b11 830 rcu_read_lock();
41c445ff 831 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 832 /* locate Tx ring */
833 p = ACCESS_ONCE(vsi->tx_rings[q]);
834
835 do {
57a7744e 836 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 837 packets = p->stats.packets;
838 bytes = p->stats.bytes;
57a7744e 839 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 840 tx_b += bytes;
841 tx_p += packets;
842 tx_restart += p->tx_stats.restart_queue;
843 tx_busy += p->tx_stats.tx_busy;
2fc3d715 844 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 845 tx_force_wb += p->tx_stats.tx_force_wb;
dd353109 846 tx_lost_interrupt += p->tx_stats.tx_lost_interrupt;
41c445ff 847
980e9b11
AD		 848 /* Rx queue is part of the same block as Tx queue */
849 p = &p[1];
850 do {
57a7744e 851 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 852 packets = p->stats.packets;
853 bytes = p->stats.bytes;
57a7744e 854 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 855 rx_b += bytes;
856 rx_p += packets;
420136cc
MW		 857 rx_buf += p->rx_stats.alloc_buff_failed;
858 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 859 }
980e9b11 860 rcu_read_unlock();
41c445ff
JB		 861 vsi->tx_restart = tx_restart;
862 vsi->tx_busy = tx_busy;
2fc3d715 863 vsi->tx_linearize = tx_linearize;
164c9f54 864 vsi->tx_force_wb = tx_force_wb;
dd353109 865 vsi->tx_lost_interrupt = tx_lost_interrupt;
41c445ff
JB		 866 vsi->rx_page_failed = rx_page;
867 vsi->rx_buf_failed = rx_buf;
868
869 ns->rx_packets = rx_p;
870 ns->rx_bytes = rx_b;
871 ns->tx_packets = tx_p;
872 ns->tx_bytes = tx_b;
873
41c445ff 874 /* update netdev stats from eth stats */
7812fddc 875 i40e_update_eth_stats(vsi);
41c445ff
JB		 876 ons->tx_errors = oes->tx_errors;
877 ns->tx_errors = es->tx_errors;
878 ons->multicast = oes->rx_multicast;
879 ns->multicast = es->rx_multicast;
41a9e55c
SN		 880 ons->rx_dropped = oes->rx_discards;
881 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 882 ons->tx_dropped = oes->tx_discards;
883 ns->tx_dropped = es->tx_discards;
884
7812fddc 885 /* pull in a couple PF stats if this is the main vsi */
41c445ff 886 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 887 ns->rx_crc_errors = pf->stats.crc_errors;
888 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
889 ns->rx_length_errors = pf->stats.rx_length_errors;
890 }
891}
41c445ff 892
7812fddc 893/**
b40c82e6 894 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 895 * @pf: the PF to be updated
896 **/
897static void i40e_update_pf_stats(struct i40e_pf *pf)
898{
899 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
900 struct i40e_hw_port_stats *nsd = &pf->stats;
901 struct i40e_hw *hw = &pf->hw;
902 u32 val;
903 int i;
41c445ff 904
7812fddc
SN		 905 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
906 I40E_GLPRT_GORCL(hw->port),
907 pf->stat_offsets_loaded,
908 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
909 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
910 I40E_GLPRT_GOTCL(hw->port),
911 pf->stat_offsets_loaded,
912 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
913 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
914 pf->stat_offsets_loaded,
915 &osd->eth.rx_discards,
916 &nsd->eth.rx_discards);
532d283d
SN		 917 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
918 I40E_GLPRT_UPRCL(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_unicast,
921 &nsd->eth.rx_unicast);
7812fddc
SN		 922 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
923 I40E_GLPRT_MPRCL(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_multicast,
926 &nsd->eth.rx_multicast);
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
928 I40E_GLPRT_BPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_broadcast,
931 &nsd->eth.rx_broadcast);
932 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
933 I40E_GLPRT_UPTCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.tx_unicast,
936 &nsd->eth.tx_unicast);
937 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
938 I40E_GLPRT_MPTCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.tx_multicast,
941 &nsd->eth.tx_multicast);
942 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
943 I40E_GLPRT_BPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_broadcast,
946 &nsd->eth.tx_broadcast);
41c445ff 947
7812fddc
SN		 948 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->tx_dropped_link_down,
951 &nsd->tx_dropped_link_down);
41c445ff 952
7812fddc
SN		 953 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->crc_errors, &nsd->crc_errors);
41c445ff 956
7812fddc
SN		 957 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 960
7812fddc
SN		 961 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->mac_local_faults,
964 &nsd->mac_local_faults);
965 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->mac_remote_faults,
968 &nsd->mac_remote_faults);
41c445ff 969
7812fddc
SN		 970 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_length_errors,
973 &nsd->rx_length_errors);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->link_xon_rx, &nsd->link_xon_rx);
978 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
979 pf->stat_offsets_loaded,
980 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 981 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
982 pf->stat_offsets_loaded,
983 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 984 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
985 pf->stat_offsets_loaded,
986 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 987
7812fddc 988 for (i = 0; i < 8; i++) {
95db239f
NP		 989 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
990 pf->stat_offsets_loaded,
991 &osd->priority_xoff_rx[i],
992 &nsd->priority_xoff_rx[i]);
7812fddc 993 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 994 pf->stat_offsets_loaded,
7812fddc
SN		 995 &osd->priority_xon_rx[i],
996 &nsd->priority_xon_rx[i]);
997 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_tx[i],
1000 &nsd->priority_xon_tx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xoff_tx[i],
1004 &nsd->priority_xoff_tx[i]);
1005 i40e_stat_update32(hw,
1006 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1007 pf->stat_offsets_loaded,
7812fddc
SN		 1008 &osd->priority_xon_2_xoff[i],
1009 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1010 }
1011
7812fddc
SN		 1012 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1013 I40E_GLPRT_PRC64L(hw->port),
1014 pf->stat_offsets_loaded,
1015 &osd->rx_size_64, &nsd->rx_size_64);
1016 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1017 I40E_GLPRT_PRC127L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_127, &nsd->rx_size_127);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1021 I40E_GLPRT_PRC255L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_255, &nsd->rx_size_255);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1025 I40E_GLPRT_PRC511L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_511, &nsd->rx_size_511);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1029 I40E_GLPRT_PRC1023L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_1023, &nsd->rx_size_1023);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1033 I40E_GLPRT_PRC1522L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1522, &nsd->rx_size_1522);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1037 I40E_GLPRT_PRC9522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_big, &nsd->rx_size_big);
1040
1041 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1042 I40E_GLPRT_PTC64L(hw->port),
1043 pf->stat_offsets_loaded,
1044 &osd->tx_size_64, &nsd->tx_size_64);
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1046 I40E_GLPRT_PTC127L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_127, &nsd->tx_size_127);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1050 I40E_GLPRT_PTC255L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_255, &nsd->tx_size_255);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1054 I40E_GLPRT_PTC511L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_511, &nsd->tx_size_511);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1058 I40E_GLPRT_PTC1023L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_1023, &nsd->tx_size_1023);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1062 I40E_GLPRT_PTC1522L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1522, &nsd->tx_size_1522);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1066 I40E_GLPRT_PTC9522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_big, &nsd->tx_size_big);
1069
1070 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->rx_undersize, &nsd->rx_undersize);
1073 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1074 pf->stat_offsets_loaded,
1075 &osd->rx_fragments, &nsd->rx_fragments);
1076 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1077 pf->stat_offsets_loaded,
1078 &osd->rx_oversize, &nsd->rx_oversize);
1079 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1080 pf->stat_offsets_loaded,
1081 &osd->rx_jabber, &nsd->rx_jabber);
1082
433c47de 1083 /* FDIR stats */
0bf4b1b0
ASJ		 1084 i40e_stat_update32(hw,
1085 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1086 pf->stat_offsets_loaded,
1087 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1088 i40e_stat_update32(hw,
1089 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1090 pf->stat_offsets_loaded,
1091 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1092 i40e_stat_update32(hw,
1093 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1094 pf->stat_offsets_loaded,
1095 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1096
7812fddc
SN		 1097 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1098 nsd->tx_lpi_status =
1099 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1100 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1101 nsd->rx_lpi_status =
1102 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1103 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1104 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1105 pf->stat_offsets_loaded,
1106 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1107 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1108 pf->stat_offsets_loaded,
1109 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1110
d0389e51
ASJ		 1111 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1112 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1113 nsd->fd_sb_status = true;
1114 else
1115 nsd->fd_sb_status = false;
1116
1117 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1118 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1119 nsd->fd_atr_status = true;
1120 else
1121 nsd->fd_atr_status = false;
1122
41c445ff
JB		 1123 pf->stat_offsets_loaded = true;
1124}
1125
7812fddc
SN		 1126/**
1127 * i40e_update_stats - Update the various statistics counters.
1128 * @vsi: the VSI to be updated
1129 *
1130 * Update the various stats for this VSI and its related entities.
1131 **/
1132void i40e_update_stats(struct i40e_vsi *vsi)
1133{
1134 struct i40e_pf *pf = vsi->back;
1135
1136 if (vsi == pf->vsi[pf->lan_vsi])
1137 i40e_update_pf_stats(pf);
1138
1139 i40e_update_vsi_stats(vsi);
38e00438
VD		 1140#ifdef I40E_FCOE
1141 i40e_update_fcoe_stats(vsi);
1142#endif
7812fddc
SN		 1143}
1144
41c445ff
JB		 1145/**
1146 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1147 * @vsi: the VSI to be searched
1148 * @macaddr: the MAC address
1149 * @vlan: the vlan
b40c82e6 1150 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1151 * @is_netdev: make sure its a netdev filter, else doesn't matter
1152 *
1153 * Returns ptr to the filter object or NULL
1154 **/
1155static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1156 u8 *macaddr, s16 vlan,
1157 bool is_vf, bool is_netdev)
1158{
1159 struct i40e_mac_filter *f;
1160
1161 if (!vsi || !macaddr)
1162 return NULL;
1163
1164 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1165 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1166 (vlan == f->vlan) &&
1167 (!is_vf || f->is_vf) &&
1168 (!is_netdev || f->is_netdev))
1169 return f;
1170 }
1171 return NULL;
1172}
1173
1174/**
1175 * i40e_find_mac - Find a mac addr in the macvlan filters list
1176 * @vsi: the VSI to be searched
1177 * @macaddr: the MAC address we are searching for
b40c82e6 1178 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1179 * @is_netdev: make sure its a netdev filter, else doesn't matter
1180 *
1181 * Returns the first filter with the provided MAC address or NULL if
1182 * MAC address was not found
1183 **/
1184struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1185 bool is_vf, bool is_netdev)
1186{
1187 struct i40e_mac_filter *f;
1188
1189 if (!vsi || !macaddr)
1190 return NULL;
1191
1192 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1193 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1194 (!is_vf || f->is_vf) &&
1195 (!is_netdev || f->is_netdev))
1196 return f;
1197 }
1198 return NULL;
1199}
1200
1201/**
1202 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1203 * @vsi: the VSI to be searched
1204 *
1205 * Returns true if VSI is in vlan mode or false otherwise
1206 **/
1207bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1208{
1209 struct i40e_mac_filter *f;
1210
1211 /* Only -1 for all the filters denotes not in vlan mode
1212 * so we have to go through all the list in order to make sure
1213 */
1214 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1215 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1216 return true;
1217 }
1218
1219 return false;
1220}
1221
1222/**
1223 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1224 * @vsi: the VSI to be searched
1225 * @macaddr: the mac address to be filtered
b40c82e6 1226 * @is_vf: true if it is a VF
41c445ff
JB		 1227 * @is_netdev: true if it is a netdev
1228 *
1229 * Goes through all the macvlan filters and adds a
1230 * macvlan filter for each unique vlan that already exists
1231 *
1232 * Returns first filter found on success, else NULL
1233 **/
1234struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1235 bool is_vf, bool is_netdev)
1236{
1237 struct i40e_mac_filter *f;
1238
1239 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1240 if (vsi->info.pvid)
1241 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1242 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1243 is_vf, is_netdev)) {
1244 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1245 is_vf, is_netdev))
41c445ff
JB		 1246 return NULL;
1247 }
1248 }
1249
1250 return list_first_entry_or_null(&vsi->mac_filter_list,
1251 struct i40e_mac_filter, list);
1252}
1253
b36e9ab5
MW		 1254/**
1255 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1256 * @vsi: the VSI to be searched
1257 * @macaddr: the mac address to be removed
1258 * @is_vf: true if it is a VF
1259 * @is_netdev: true if it is a netdev
1260 *
1261 * Removes a given MAC address from a VSI, regardless of VLAN
1262 *
1263 * Returns 0 for success, or error
1264 **/
1265int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1266 bool is_vf, bool is_netdev)
1267{
1268 struct i40e_mac_filter *f = NULL;
1269 int changed = 0;
1270
1271 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1272 "Missing mac_filter_list_lock\n");
1273 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1274 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1275 (is_vf == f->is_vf) &&
1276 (is_netdev == f->is_netdev)) {
1277 f->counter--;
1278 f->changed = true;
1279 changed = 1;
1280 }
1281 }
1282 if (changed) {
1283 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1284 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1285 return 0;
1286 }
1287 return -ENOENT;
1288}
1289
8c27d42e
GR		 1290/**
1291 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1292 * @vsi: the PF Main VSI - inappropriate for any other VSI
1293 * @macaddr: the MAC address
30650cc5
SN		 1294 *
1295 * Some older firmware configurations set up a default promiscuous VLAN
1296 * filter that needs to be removed.
8c27d42e 1297 **/
30650cc5 1298static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1299{
1300 struct i40e_aqc_remove_macvlan_element_data element;
1301 struct i40e_pf *pf = vsi->back;
f1c7e72e 1302 i40e_status ret;
8c27d42e
GR		 1303
1304 /* Only appropriate for the PF main VSI */
1305 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1306 return -EINVAL;
8c27d42e 1307
30650cc5 1308 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1309 ether_addr_copy(element.mac_addr, macaddr);
1310 element.vlan_tag = 0;
1311 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1312 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1313 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1314 if (ret)
30650cc5
SN		 1315 return -ENOENT;
1316
1317 return 0;
8c27d42e
GR		 1318}
1319
41c445ff
JB		 1320/**
1321 * i40e_add_filter - Add a mac/vlan filter to the VSI
1322 * @vsi: the VSI to be searched
1323 * @macaddr: the MAC address
1324 * @vlan: the vlan
b40c82e6 1325 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1326 * @is_netdev: make sure its a netdev filter, else doesn't matter
1327 *
1328 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1329 *
1330 * NOTE: This function is expected to be called with mac_filter_list_lock
1331 * being held.
41c445ff
JB		 1332 **/
1333struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1334 u8 *macaddr, s16 vlan,
1335 bool is_vf, bool is_netdev)
1336{
1337 struct i40e_mac_filter *f;
1338
1339 if (!vsi || !macaddr)
1340 return NULL;
1341
1342 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1343 if (!f) {
1344 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1345 if (!f)
1346 goto add_filter_out;
1347
9a173901 1348 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1349 f->vlan = vlan;
1350 f->changed = true;
1351
1352 INIT_LIST_HEAD(&f->list);
04d5a21d 1353 list_add_tail(&f->list, &vsi->mac_filter_list);
41c445ff
JB		 1354 }
1355
1356 /* increment counter and add a new flag if needed */
1357 if (is_vf) {
1358 if (!f->is_vf) {
1359 f->is_vf = true;
1360 f->counter++;
1361 }
1362 } else if (is_netdev) {
1363 if (!f->is_netdev) {
1364 f->is_netdev = true;
1365 f->counter++;
1366 }
1367 } else {
1368 f->counter++;
1369 }
1370
1371 /* changed tells sync_filters_subtask to
1372 * push the filter down to the firmware
1373 */
1374 if (f->changed) {
1375 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1376 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1377 }
1378
1379add_filter_out:
1380 return f;
1381}
1382
1383/**
1384 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1385 * @vsi: the VSI to be searched
1386 * @macaddr: the MAC address
1387 * @vlan: the vlan
b40c82e6 1388 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1389 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1390 *
1391 * NOTE: This function is expected to be called with mac_filter_list_lock
1392 * being held.
41c445ff
JB		 1393 **/
1394void i40e_del_filter(struct i40e_vsi *vsi,
1395 u8 *macaddr, s16 vlan,
1396 bool is_vf, bool is_netdev)
1397{
1398 struct i40e_mac_filter *f;
1399
1400 if (!vsi || !macaddr)
1401 return;
1402
1403 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1404 if (!f || f->counter == 0)
1405 return;
1406
1407 if (is_vf) {
1408 if (f->is_vf) {
1409 f->is_vf = false;
1410 f->counter--;
1411 }
1412 } else if (is_netdev) {
1413 if (f->is_netdev) {
1414 f->is_netdev = false;
1415 f->counter--;
1416 }
1417 } else {
b40c82e6 1418 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1419 int min_f = 0;
6995b36c 1420
41c445ff
JB		 1421 min_f += (f->is_vf ? 1 : 0);
1422 min_f += (f->is_netdev ? 1 : 0);
1423
1424 if (f->counter > min_f)
1425 f->counter--;
1426 }
1427
1428 /* counter == 0 tells sync_filters_subtask to
1429 * remove the filter from the firmware's list
1430 */
1431 if (f->counter == 0) {
1432 f->changed = true;
1433 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1434 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1435 }
1436}
1437
1438/**
1439 * i40e_set_mac - NDO callback to set mac address
1440 * @netdev: network interface device structure
1441 * @p: pointer to an address structure
1442 *
1443 * Returns 0 on success, negative on failure
1444 **/
38e00438
VD		 1445#ifdef I40E_FCOE
1446int i40e_set_mac(struct net_device *netdev, void *p)
1447#else
41c445ff 1448static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1449#endif
41c445ff
JB		 1450{
1451 struct i40e_netdev_priv *np = netdev_priv(netdev);
1452 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1453 struct i40e_pf *pf = vsi->back;
1454 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1455 struct sockaddr *addr = p;
1456 struct i40e_mac_filter *f;
1457
1458 if (!is_valid_ether_addr(addr->sa_data))
1459 return -EADDRNOTAVAIL;
1460
30650cc5
SN		 1461 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1462 netdev_info(netdev, "already using mac address %pM\n",
1463 addr->sa_data);
1464 return 0;
1465 }
41c445ff 1466
80f6428f
ASJ		 1467 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1468 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1469 return -EADDRNOTAVAIL;
1470
30650cc5
SN		 1471 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1472 netdev_info(netdev, "returning to hw mac address %pM\n",
1473 hw->mac.addr);
1474 else
1475 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1476
41c445ff
JB		 1477 if (vsi->type == I40E_VSI_MAIN) {
1478 i40e_status ret;
6995b36c 1479
41c445ff 1480 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1481 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1482 addr->sa_data, NULL);
1483 if (ret) {
1484 netdev_info(netdev,
1485 "Addr change for Main VSI failed: %d\n",
1486 ret);
1487 return -EADDRNOTAVAIL;
1488 }
41c445ff
JB		 1489 }
1490
30650cc5
SN		 1491 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1492 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1493
30650cc5
SN		 1494 memset(&element, 0, sizeof(element));
1495 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1496 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1497 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1498 } else {
21659035 1499 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1500 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1501 false, false);
21659035 1502 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1503 }
41c445ff 1504
30650cc5
SN		 1505 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1506 struct i40e_aqc_add_macvlan_element_data element;
1507
1508 memset(&element, 0, sizeof(element));
1509 ether_addr_copy(element.mac_addr, hw->mac.addr);
1510 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1511 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1512 } else {
21659035 1513 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1514 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1515 false, false);
1516 if (f)
1517 f->is_laa = true;
21659035 1518 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1519 }
1520
30650cc5 1521 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b 1522
c53934c6
JB		 1523 /* schedule our worker thread which will take care of
1524 * applying the new filter changes
1525 */
1526 i40e_service_event_schedule(vsi->back);
1527 return 0;
41c445ff
JB		 1528}
1529
1530/**
1531 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1532 * @vsi: the VSI being setup
1533 * @ctxt: VSI context structure
1534 * @enabled_tc: Enabled TCs bitmap
1535 * @is_add: True if called before Add VSI
1536 *
1537 * Setup VSI queue mapping for enabled traffic classes.
1538 **/
38e00438
VD		 1539#ifdef I40E_FCOE
1540void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1541 struct i40e_vsi_context *ctxt,
1542 u8 enabled_tc,
1543 bool is_add)
1544#else
41c445ff
JB		 1545static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1546 struct i40e_vsi_context *ctxt,
1547 u8 enabled_tc,
1548 bool is_add)
38e00438 1549#endif
41c445ff
JB		 1550{
1551 struct i40e_pf *pf = vsi->back;
1552 u16 sections = 0;
1553 u8 netdev_tc = 0;
1554 u16 numtc = 0;
1555 u16 qcount;
1556 u8 offset;
1557 u16 qmap;
1558 int i;
4e3b35b0 1559 u16 num_tc_qps = 0;
41c445ff
JB		 1560
1561 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1562 offset = 0;
1563
1564 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1565 /* Find numtc from enabled TC bitmap */
1566 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1567 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1568 numtc++;
1569 }
1570 if (!numtc) {
1571 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1572 numtc = 1;
1573 }
1574 } else {
1575 /* At least TC0 is enabled in case of non-DCB case */
1576 numtc = 1;
1577 }
1578
1579 vsi->tc_config.numtc = numtc;
1580 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1581 /* Number of queues per enabled TC */
7d64402f
CS		 1582 qcount = vsi->alloc_queue_pairs;
1583
7f9ff476 1584 num_tc_qps = qcount / numtc;
e25d00b8 1585 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1586
1587 /* Setup queue offset/count for all TCs for given VSI */
1588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1589 /* See if the given TC is enabled for the given VSI */
75f5cea9 1590 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1591 /* TC is enabled */
41c445ff
JB		 1592 int pow, num_qps;
1593
41c445ff
JB		 1594 switch (vsi->type) {
1595 case I40E_VSI_MAIN:
acd65448
HZ		 1596 qcount = min_t(int, pf->alloc_rss_size,
1597 num_tc_qps);
41c445ff 1598 break;
38e00438
VD		 1599#ifdef I40E_FCOE
1600 case I40E_VSI_FCOE:
1601 qcount = num_tc_qps;
1602 break;
1603#endif
41c445ff
JB		 1604 case I40E_VSI_FDIR:
1605 case I40E_VSI_SRIOV:
1606 case I40E_VSI_VMDQ2:
1607 default:
4e3b35b0 1608 qcount = num_tc_qps;
41c445ff
JB		 1609 WARN_ON(i != 0);
1610 break;
1611 }
4e3b35b0
NP		 1612 vsi->tc_config.tc_info[i].qoffset = offset;
1613 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1614
1e200e4a 1615 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1616 num_qps = qcount;
41c445ff 1617 pow = 0;
41a1d04b 1618 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1619 pow++;
1620 num_qps >>= 1;
1621 }
1622
1623 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1624 qmap =
1625 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1626 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1627
4e3b35b0 1628 offset += qcount;
41c445ff
JB		 1629 } else {
1630 /* TC is not enabled so set the offset to
1631 * default queue and allocate one queue
1632 * for the given TC.
1633 */
1634 vsi->tc_config.tc_info[i].qoffset = 0;
1635 vsi->tc_config.tc_info[i].qcount = 1;
1636 vsi->tc_config.tc_info[i].netdev_tc = 0;
1637
1638 qmap = 0;
1639 }
1640 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1641 }
1642
1643 /* Set actual Tx/Rx queue pairs */
1644 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1645 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1646 if (vsi->req_queue_pairs > 0)
1647 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1648 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1649 vsi->num_queue_pairs = pf->num_lan_msix;
1650 }
41c445ff
JB		 1651
1652 /* Scheduler section valid can only be set for ADD VSI */
1653 if (is_add) {
1654 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1655
1656 ctxt->info.up_enable_bits = enabled_tc;
1657 }
1658 if (vsi->type == I40E_VSI_SRIOV) {
1659 ctxt->info.mapping_flags |=
1660 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1661 for (i = 0; i < vsi->num_queue_pairs; i++)
1662 ctxt->info.queue_mapping[i] =
1663 cpu_to_le16(vsi->base_queue + i);
1664 } else {
1665 ctxt->info.mapping_flags |=
1666 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1667 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1668 }
1669 ctxt->info.valid_sections |= cpu_to_le16(sections);
1670}
1671
1672/**
1673 * i40e_set_rx_mode - NDO callback to set the netdev filters
1674 * @netdev: network interface device structure
1675 **/
38e00438
VD		 1676#ifdef I40E_FCOE
1677void i40e_set_rx_mode(struct net_device *netdev)
1678#else
41c445ff 1679static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1680#endif
41c445ff
JB		 1681{
1682 struct i40e_netdev_priv *np = netdev_priv(netdev);
1683 struct i40e_mac_filter *f, *ftmp;
1684 struct i40e_vsi *vsi = np->vsi;
1685 struct netdev_hw_addr *uca;
1686 struct netdev_hw_addr *mca;
1687 struct netdev_hw_addr *ha;
1688
21659035
KP		 1689 spin_lock_bh(&vsi->mac_filter_list_lock);
1690
41c445ff
JB		 1691 /* add addr if not already in the filter list */
1692 netdev_for_each_uc_addr(uca, netdev) {
1693 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1694 if (i40e_is_vsi_in_vlan(vsi))
1695 i40e_put_mac_in_vlan(vsi, uca->addr,
1696 false, true);
1697 else
1698 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1699 false, true);
1700 }
1701 }
1702
1703 netdev_for_each_mc_addr(mca, netdev) {
1704 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1705 if (i40e_is_vsi_in_vlan(vsi))
1706 i40e_put_mac_in_vlan(vsi, mca->addr,
1707 false, true);
1708 else
1709 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1710 false, true);
1711 }
1712 }
1713
1714 /* remove filter if not in netdev list */
1715 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1716
1717 if (!f->is_netdev)
1718 continue;
1719
2f41f335
SN		 1720 netdev_for_each_mc_addr(mca, netdev)
1721 if (ether_addr_equal(mca->addr, f->macaddr))
1722 goto bottom_of_search_loop;
41c445ff 1723
2f41f335
SN		 1724 netdev_for_each_uc_addr(uca, netdev)
1725 if (ether_addr_equal(uca->addr, f->macaddr))
1726 goto bottom_of_search_loop;
1727
1728 for_each_dev_addr(netdev, ha)
1729 if (ether_addr_equal(ha->addr, f->macaddr))
1730 goto bottom_of_search_loop;
1731
1732 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1733 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1734
1735bottom_of_search_loop:
1736 continue;
41c445ff 1737 }
21659035 1738 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1739
1740 /* check for other flag changes */
1741 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1742 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1743 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1744 }
c53934c6
JB		 1745
1746 /* schedule our worker thread which will take care of
1747 * applying the new filter changes
1748 */
1749 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1750}
1751
21659035
KP		 1752/**
1753 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1754 * @src: source MAC filter entry to be clones
1755 *
1756 * Returns the pointer to newly cloned MAC filter entry or NULL
1757 * in case of error
1758 **/
1759static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1760 struct i40e_mac_filter *src)
1761{
1762 struct i40e_mac_filter *f;
1763
1764 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1765 if (!f)
1766 return NULL;
1767 *f = *src;
1768
1769 INIT_LIST_HEAD(&f->list);
1770
1771 return f;
1772}
1773
1774/**
1775 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1776 * @vsi: pointer to vsi struct
1777 * @from: Pointer to list which contains MAC filter entries - changes to
1778 * those entries needs to be undone.
1779 *
1780 * MAC filter entries from list were slated to be removed from device.
1781 **/
1782static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1783 struct list_head *from)
1784{
1785 struct i40e_mac_filter *f, *ftmp;
1786
1787 list_for_each_entry_safe(f, ftmp, from, list) {
1788 f->changed = true;
1789 /* Move the element back into MAC filter list*/
1790 list_move_tail(&f->list, &vsi->mac_filter_list);
1791 }
1792}
1793
1794/**
1795 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1796 * @vsi: pointer to vsi struct
1797 *
1798 * MAC filter entries from list were slated to be added from device.
1799 **/
1800static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1801{
1802 struct i40e_mac_filter *f, *ftmp;
1803
1804 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1805 if (!f->changed && f->counter)
1806 f->changed = true;
1807 }
1808}
1809
1810/**
1811 * i40e_cleanup_add_list - Deletes the element from add list and release
1812 * memory
1813 * @add_list: Pointer to list which contains MAC filter entries
1814 **/
1815static void i40e_cleanup_add_list(struct list_head *add_list)
1816{
1817 struct i40e_mac_filter *f, *ftmp;
1818
1819 list_for_each_entry_safe(f, ftmp, add_list, list) {
1820 list_del(&f->list);
1821 kfree(f);
1822 }
1823}
1824
41c445ff
JB		 1825/**
1826 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1827 * @vsi: ptr to the VSI
1828 *
1829 * Push any outstanding VSI filter changes through the AdminQ.
1830 *
1831 * Returns 0 or error value
1832 **/
17652c63 1833int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1834{
21659035
KP		 1835 struct list_head tmp_del_list, tmp_add_list;
1836 struct i40e_mac_filter *f, *ftmp, *fclone;
3e25a8f3 1837 struct i40e_hw *hw = &vsi->back->hw;
41c445ff
JB		 1838 bool promisc_forced_on = false;
1839 bool add_happened = false;
2d1de828 1840 char vsi_name[16] = "PF";
41c445ff
JB		 1841 int filter_list_len = 0;
1842 u32 changed_flags = 0;
ea02e90b 1843 i40e_status aq_ret = 0;
21659035 1844 bool err_cond = false;
ea02e90b 1845 int retval = 0;
41c445ff
JB		 1846 struct i40e_pf *pf;
1847 int num_add = 0;
1848 int num_del = 0;
f1c7e72e 1849 int aq_err = 0;
41c445ff
JB		 1850 u16 cmd_flags;
1851
1852 /* empty array typed pointers, kcalloc later */
1853 struct i40e_aqc_add_macvlan_element_data *add_list;
1854 struct i40e_aqc_remove_macvlan_element_data *del_list;
1855
1856 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1857 usleep_range(1000, 2000);
1858 pf = vsi->back;
1859
1860 if (vsi->netdev) {
1861 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1862 vsi->current_netdev_flags = vsi->netdev->flags;
1863 }
1864
21659035
KP		 1865 INIT_LIST_HEAD(&tmp_del_list);
1866 INIT_LIST_HEAD(&tmp_add_list);
1867
2d1de828
SN		 1868 if (vsi->type == I40E_VSI_SRIOV)
1869 snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id);
1870 else if (vsi->type != I40E_VSI_MAIN)
1871 snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid);
1872
41c445ff
JB		 1873 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1874 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1875
21659035 1876 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1877 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1878 if (!f->changed)
1879 continue;
1880
1881 if (f->counter != 0)
1882 continue;
1883 f->changed = false;
21659035
KP		 1884
1885 /* Move the element into temporary del_list */
1886 list_move_tail(&f->list, &tmp_del_list);
1887 }
1888
1889 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1890 if (!f->changed)
1891 continue;
1892
1893 if (f->counter == 0)
1894 continue;
1895 f->changed = false;
1896
1897 /* Clone MAC filter entry and add into temporary list */
1898 fclone = i40e_mac_filter_entry_clone(f);
1899 if (!fclone) {
1900 err_cond = true;
1901 break;
1902 }
1903 list_add_tail(&fclone->list, &tmp_add_list);
1904 }
1905
1906 /* if failed to clone MAC filter entry - undo */
1907 if (err_cond) {
1908 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1909 i40e_undo_add_filter_entries(vsi);
1910 }
1911 spin_unlock_bh(&vsi->mac_filter_list_lock);
1912
ea02e90b 1913 if (err_cond) {
21659035 1914 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1915 retval = -ENOMEM;
1916 goto out;
1917 }
21659035
KP		 1918 }
1919
1920 /* Now process 'del_list' outside the lock */
1921 if (!list_empty(&tmp_del_list)) {
f1199998
SN		 1922 int del_list_size;
1923
3e25a8f3 1924 filter_list_len = hw->aq.asq_buf_size /
21659035 1925 sizeof(struct i40e_aqc_remove_macvlan_element_data);
f1199998
SN		 1926 del_list_size = filter_list_len *
1927 sizeof(struct i40e_aqc_remove_macvlan_element_data);
38c3cec7 1928 del_list = kzalloc(del_list_size, GFP_ATOMIC);
21659035
KP		 1929 if (!del_list) {
1930 i40e_cleanup_add_list(&tmp_add_list);
1931
1932 /* Undo VSI's MAC filter entry element updates */
1933 spin_lock_bh(&vsi->mac_filter_list_lock);
1934 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1935 i40e_undo_add_filter_entries(vsi);
1936 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1937 retval = -ENOMEM;
1938 goto out;
21659035
KP		 1939 }
1940
1941 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1942 cmd_flags = 0;
1943
1944 /* add to delete list */
9a173901 1945 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1946 del_list[num_del].vlan_tag =
1947 cpu_to_le16((u16)(f->vlan ==
1948 I40E_VLAN_ANY ? 0 : f->vlan));
1949
41c445ff
JB		 1950 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1951 del_list[num_del].flags = cmd_flags;
1952 num_del++;
1953
41c445ff
JB		 1954 /* flush a full buffer */
1955 if (num_del == filter_list_len) {
3e25a8f3
MW		 1956 aq_ret =
1957 i40e_aq_remove_macvlan(hw, vsi->seid,
1958 del_list,
1959 num_del, NULL);
1960 aq_err = hw->aq.asq_last_status;
41c445ff 1961 num_del = 0;
f1199998 1962 memset(del_list, 0, del_list_size);
41c445ff 1963
ea02e90b
MW		 1964 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1965 retval = -EIO;
21659035 1966 dev_err(&pf->pdev->dev,
2d1de828
SN		 1967 "ignoring delete macvlan error on %s, err %s, aq_err %s while flushing a full buffer\n",
1968 vsi_name,
3e25a8f3
MW		 1969 i40e_stat_str(hw, aq_ret),
1970 i40e_aq_str(hw, aq_err));
ea02e90b 1971 }
41c445ff 1972 }
21659035
KP		 1973 /* Release memory for MAC filter entries which were
1974 * synced up with HW.
1975 */
1976 list_del(&f->list);
1977 kfree(f);
41c445ff 1978 }
21659035 1979
41c445ff 1980 if (num_del) {
3e25a8f3
MW		 1981 aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, del_list,
1982 num_del, NULL);
1983 aq_err = hw->aq.asq_last_status;
41c445ff
JB		 1984 num_del = 0;
1985
ea02e90b 1986 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1987 dev_info(&pf->pdev->dev,
2d1de828
SN		 1988 "ignoring delete macvlan error on %s, err %s aq_err %s\n",
1989 vsi_name,
3e25a8f3
MW		 1990 i40e_stat_str(hw, aq_ret),
1991 i40e_aq_str(hw, aq_err));
41c445ff
JB		 1992 }
1993
1994 kfree(del_list);
1995 del_list = NULL;
21659035
KP		 1996 }
1997
1998 if (!list_empty(&tmp_add_list)) {
f1199998 1999 int add_list_size;
41c445ff
JB		 2000
2001 /* do all the adds now */
3e25a8f3 2002 filter_list_len = hw->aq.asq_buf_size /
41c445ff 2003 sizeof(struct i40e_aqc_add_macvlan_element_data),
f1199998
SN		 2004 add_list_size = filter_list_len *
2005 sizeof(struct i40e_aqc_add_macvlan_element_data);
38c3cec7 2006 add_list = kzalloc(add_list_size, GFP_ATOMIC);
21659035
KP		 2007 if (!add_list) {
2008 /* Purge element from temporary lists */
2009 i40e_cleanup_add_list(&tmp_add_list);
2010
2011 /* Undo add filter entries from VSI MAC filter list */
2012 spin_lock_bh(&vsi->mac_filter_list_lock);
2013 i40e_undo_add_filter_entries(vsi);
2014 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2015 retval = -ENOMEM;
2016 goto out;
21659035 2017 }
41c445ff 2018
21659035 2019 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2020
41c445ff
JB		 2021 add_happened = true;
2022 cmd_flags = 0;
2023
2024 /* add to add array */
9a173901 2025 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2026 add_list[num_add].vlan_tag =
2027 cpu_to_le16(
2028 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2029 add_list[num_add].queue_number = 0;
2030
2031 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2032 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2033 num_add++;
2034
2035 /* flush a full buffer */
2036 if (num_add == filter_list_len) {
3e25a8f3 2037 aq_ret = i40e_aq_add_macvlan(hw, vsi->seid,
ea02e90b
MW		 2038 add_list, num_add,
2039 NULL);
3e25a8f3 2040 aq_err = hw->aq.asq_last_status;
41c445ff
JB		 2041 num_add = 0;
2042
ea02e90b 2043 if (aq_ret)
41c445ff 2044 break;
f1199998 2045 memset(add_list, 0, add_list_size);
41c445ff 2046 }
21659035
KP		 2047 /* Entries from tmp_add_list were cloned from MAC
2048 * filter list, hence clean those cloned entries
2049 */
2050 list_del(&f->list);
2051 kfree(f);
41c445ff 2052 }
21659035 2053
41c445ff 2054 if (num_add) {
3e25a8f3 2055 aq_ret = i40e_aq_add_macvlan(hw, vsi->seid,
ea02e90b 2056 add_list, num_add, NULL);
3e25a8f3 2057 aq_err = hw->aq.asq_last_status;
41c445ff
JB		 2058 num_add = 0;
2059 }
2060 kfree(add_list);
2061 add_list = NULL;
2062
ea02e90b
MW		 2063 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2064 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2065 dev_info(&pf->pdev->dev,
2d1de828
SN		 2066 "add filter failed on %s, err %s aq_err %s\n",
2067 vsi_name,
3e25a8f3
MW		 2068 i40e_stat_str(hw, aq_ret),
2069 i40e_aq_str(hw, aq_err));
2070 if ((hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
41c445ff
JB		 2071 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2072 &vsi->state)) {
2073 promisc_forced_on = true;
2074 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2075 &vsi->state);
2d1de828
SN		 2076 dev_info(&pf->pdev->dev, "promiscuous mode forced on %s\n",
2077 vsi_name);
41c445ff
JB		 2078 }
2079 }
2080 }
2081
a856b5cb
ASJ		 2082 /* if the VF is not trusted do not do promisc */
2083 if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) {
2084 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state);
2085 goto out;
2086 }
2087
41c445ff
JB		 2088 /* check for changes in promiscuous modes */
2089 if (changed_flags & IFF_ALLMULTI) {
2090 bool cur_multipromisc;
6995b36c 2091
41c445ff 2092 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2093 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2094 vsi->seid,
2095 cur_multipromisc,
2096 NULL);
2097 if (aq_ret) {
2098 retval = i40e_aq_rc_to_posix(aq_ret,
3e25a8f3 2099 hw->aq.asq_last_status);
41c445ff 2100 dev_info(&pf->pdev->dev,
2d1de828
SN		 2101 "set multi promisc failed on %s, err %s aq_err %s\n",
2102 vsi_name,
3e25a8f3
MW		 2103 i40e_stat_str(hw, aq_ret),
2104 i40e_aq_str(hw, hw->aq.asq_last_status));
ea02e90b 2105 }
41c445ff
JB		 2106 }
2107 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2108 bool cur_promisc;
6995b36c 2109
41c445ff
JB		 2110 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2111 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2112 &vsi->state));
6784ed5a
ASJ		 2113 if ((vsi->type == I40E_VSI_MAIN) &&
2114 (pf->lan_veb != I40E_NO_VEB) &&
2115 !(pf->flags & I40E_FLAG_MFP_ENABLED)) {
92faef85
ASJ		 2116 /* set defport ON for Main VSI instead of true promisc
2117 * this way we will get all unicast/multicast and VLAN
2118 * promisc behavior but will not get VF or VMDq traffic
2119 * replicated on the Main VSI.
2120 */
2121 if (pf->cur_promisc != cur_promisc) {
2122 pf->cur_promisc = cur_promisc;
5bc16031
MW		 2123 if (cur_promisc)
2124 aq_ret =
2125 i40e_aq_set_default_vsi(hw,
2126 vsi->seid,
2127 NULL);
2128 else
2129 aq_ret =
2130 i40e_aq_clear_default_vsi(hw,
2131 vsi->seid,
2132 NULL);
2133 if (aq_ret) {
2134 retval = i40e_aq_rc_to_posix(aq_ret,
2135 hw->aq.asq_last_status);
2136 dev_info(&pf->pdev->dev,
2d1de828
SN		 2137 "Set default VSI failed on %s, err %s, aq_err %s\n",
2138 vsi_name,
5bc16031
MW		 2139 i40e_stat_str(hw, aq_ret),
2140 i40e_aq_str(hw,
2141 hw->aq.asq_last_status));
2142 }
92faef85
ASJ		 2143 }
2144 } else {
ea02e90b 2145 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
3e25a8f3 2146 hw,
f1c7e72e 2147 vsi->seid,
b5569892
ASJ		 2148 cur_promisc, NULL,
2149 true);
ea02e90b
MW		 2150 if (aq_ret) {
2151 retval =
2152 i40e_aq_rc_to_posix(aq_ret,
3e25a8f3 2153 hw->aq.asq_last_status);
92faef85 2154 dev_info(&pf->pdev->dev,
2d1de828
SN		 2155 "set unicast promisc failed on %s, err %s, aq_err %s\n",
2156 vsi_name,
3e25a8f3
MW		 2157 i40e_stat_str(hw, aq_ret),
2158 i40e_aq_str(hw,
2159 hw->aq.asq_last_status));
ea02e90b
MW		 2160 }
2161 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
3e25a8f3 2162 hw,
92faef85
ASJ		 2163 vsi->seid,
2164 cur_promisc, NULL);
ea02e90b
MW		 2165 if (aq_ret) {
2166 retval =
2167 i40e_aq_rc_to_posix(aq_ret,
3e25a8f3 2168 hw->aq.asq_last_status);
92faef85 2169 dev_info(&pf->pdev->dev,
2d1de828
SN		 2170 "set multicast promisc failed on %s, err %s, aq_err %s\n",
2171 vsi_name,
3e25a8f3
MW		 2172 i40e_stat_str(hw, aq_ret),
2173 i40e_aq_str(hw,
2174 hw->aq.asq_last_status));
ea02e90b 2175 }
92faef85 2176 }
ea02e90b
MW		 2177 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2178 vsi->seid,
2179 cur_promisc, NULL);
2180 if (aq_ret) {
2181 retval = i40e_aq_rc_to_posix(aq_ret,
2182 pf->hw.aq.asq_last_status);
1a10370a 2183 dev_info(&pf->pdev->dev,
f1c7e72e 2184 "set brdcast promisc failed, err %s, aq_err %s\n",
3e25a8f3
MW		 2185 i40e_stat_str(hw, aq_ret),
2186 i40e_aq_str(hw,
2187 hw->aq.asq_last_status));
ea02e90b 2188 }
41c445ff 2189 }
ea02e90b 2190out:
2818ccd9
JB		 2191 /* if something went wrong then set the changed flag so we try again */
2192 if (retval)
2193 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2194
41c445ff 2195 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2196 return retval;
41c445ff
JB		 2197}
2198
2199/**
2200 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2201 * @pf: board private structure
2202 **/
2203static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2204{
2205 int v;
2206
2207 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2208 return;
2209 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2210
505682cd 2211 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2212 if (pf->vsi[v] &&
17652c63
JB		 2213 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2214 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2215
2216 if (ret) {
2217 /* come back and try again later */
2218 pf->flags |= I40E_FLAG_FILTER_SYNC;
2219 break;
2220 }
2221 }
41c445ff
JB		 2222 }
2223}
2224
2225/**
2226 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2227 * @netdev: network interface device structure
2228 * @new_mtu: new value for maximum frame size
2229 *
2230 * Returns 0 on success, negative on failure
2231 **/
2232static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2233{
2234 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2235 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2236 struct i40e_vsi *vsi = np->vsi;
2237
2238 /* MTU < 68 is an error and causes problems on some kernels */
2239 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2240 return -EINVAL;
2241
2242 netdev_info(netdev, "changing MTU from %d to %d\n",
2243 netdev->mtu, new_mtu);
2244 netdev->mtu = new_mtu;
2245 if (netif_running(netdev))
2246 i40e_vsi_reinit_locked(vsi);
e3219ce6 2247 i40e_notify_client_of_l2_param_changes(vsi);
41c445ff
JB		 2248 return 0;
2249}
2250
beb0dff1
JK		 2251/**
2252 * i40e_ioctl - Access the hwtstamp interface
2253 * @netdev: network interface device structure
2254 * @ifr: interface request data
2255 * @cmd: ioctl command
2256 **/
2257int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2258{
2259 struct i40e_netdev_priv *np = netdev_priv(netdev);
2260 struct i40e_pf *pf = np->vsi->back;
2261
2262 switch (cmd) {
2263 case SIOCGHWTSTAMP:
2264 return i40e_ptp_get_ts_config(pf, ifr);
2265 case SIOCSHWTSTAMP:
2266 return i40e_ptp_set_ts_config(pf, ifr);
2267 default:
2268 return -EOPNOTSUPP;
2269 }
2270}
2271
41c445ff
JB		 2272/**
2273 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2274 * @vsi: the vsi being adjusted
2275 **/
2276void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2277{
2278 struct i40e_vsi_context ctxt;
2279 i40e_status ret;
2280
2281 if ((vsi->info.valid_sections &
2282 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2283 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2284 return; /* already enabled */
2285
2286 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2287 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2288 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2289
2290 ctxt.seid = vsi->seid;
1a2f6248 2291 ctxt.info = vsi->info;
41c445ff
JB		 2292 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2293 if (ret) {
2294 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2295 "update vlan stripping failed, err %s aq_err %s\n",
2296 i40e_stat_str(&vsi->back->hw, ret),
2297 i40e_aq_str(&vsi->back->hw,
2298 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2299 }
2300}
2301
2302/**
2303 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2304 * @vsi: the vsi being adjusted
2305 **/
2306void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2307{
2308 struct i40e_vsi_context ctxt;
2309 i40e_status ret;
2310
2311 if ((vsi->info.valid_sections &
2312 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2313 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2314 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2315 return; /* already disabled */
2316
2317 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2318 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2319 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2320
2321 ctxt.seid = vsi->seid;
1a2f6248 2322 ctxt.info = vsi->info;
41c445ff
JB		 2323 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2324 if (ret) {
2325 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2326 "update vlan stripping failed, err %s aq_err %s\n",
2327 i40e_stat_str(&vsi->back->hw, ret),
2328 i40e_aq_str(&vsi->back->hw,
2329 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2330 }
2331}
2332
2333/**
2334 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2335 * @netdev: network interface to be adjusted
2336 * @features: netdev features to test if VLAN offload is enabled or not
2337 **/
2338static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2339{
2340 struct i40e_netdev_priv *np = netdev_priv(netdev);
2341 struct i40e_vsi *vsi = np->vsi;
2342
2343 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2344 i40e_vlan_stripping_enable(vsi);
2345 else
2346 i40e_vlan_stripping_disable(vsi);
2347}
2348
2349/**
2350 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2351 * @vsi: the vsi being configured
2352 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2353 **/
2354int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2355{
2356 struct i40e_mac_filter *f, *add_f;
2357 bool is_netdev, is_vf;
41c445ff
JB		 2358
2359 is_vf = (vsi->type == I40E_VSI_SRIOV);
2360 is_netdev = !!(vsi->netdev);
2361
21659035
KP		 2362 /* Locked once because all functions invoked below iterates list*/
2363 spin_lock_bh(&vsi->mac_filter_list_lock);
2364
41c445ff
JB		 2365 if (is_netdev) {
2366 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2367 is_vf, is_netdev);
2368 if (!add_f) {
2369 dev_info(&vsi->back->pdev->dev,
2370 "Could not add vlan filter %d for %pM\n",
2371 vid, vsi->netdev->dev_addr);
21659035 2372 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2373 return -ENOMEM;
2374 }
2375 }
2376
2377 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2378 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2379 if (!add_f) {
2380 dev_info(&vsi->back->pdev->dev,
2381 "Could not add vlan filter %d for %pM\n",
2382 vid, f->macaddr);
21659035 2383 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2384 return -ENOMEM;
2385 }
2386 }
2387
41c445ff
JB		 2388 /* Now if we add a vlan tag, make sure to check if it is the first
2389 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2390 * with 0, so we now accept untagged and specified tagged traffic
2391 * (and not any taged and untagged)
2392 */
2393 if (vid > 0) {
2394 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2395 I40E_VLAN_ANY,
2396 is_vf, is_netdev)) {
2397 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2398 I40E_VLAN_ANY, is_vf, is_netdev);
2399 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2400 is_vf, is_netdev);
2401 if (!add_f) {
2402 dev_info(&vsi->back->pdev->dev,
2403 "Could not add filter 0 for %pM\n",
2404 vsi->netdev->dev_addr);
21659035 2405 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2406 return -ENOMEM;
2407 }
2408 }
8d82a7c5 2409 }
41c445ff 2410
8d82a7c5
GR		 2411 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2412 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2413 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2414 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2415 is_vf, is_netdev))
2416 continue;
2417 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2418 is_vf, is_netdev);
2419 add_f = i40e_add_filter(vsi, f->macaddr,
2420 0, is_vf, is_netdev);
2421 if (!add_f) {
2422 dev_info(&vsi->back->pdev->dev,
2423 "Could not add filter 0 for %pM\n",
2424 f->macaddr);
2425 spin_unlock_bh(&vsi->mac_filter_list_lock);
2426 return -ENOMEM;
41c445ff
JB		 2427 }
2428 }
41c445ff
JB		 2429 }
2430
21659035
KP		 2431 spin_unlock_bh(&vsi->mac_filter_list_lock);
2432
0e4425ed
JB		 2433 /* schedule our worker thread which will take care of
2434 * applying the new filter changes
2435 */
2436 i40e_service_event_schedule(vsi->back);
2437 return 0;
41c445ff
JB		 2438}
2439
2440/**
2441 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2442 * @vsi: the vsi being configured
2443 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2444 *
2445 * Return: 0 on success or negative otherwise
41c445ff
JB		 2446 **/
2447int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2448{
2449 struct net_device *netdev = vsi->netdev;
2450 struct i40e_mac_filter *f, *add_f;
2451 bool is_vf, is_netdev;
2452 int filter_count = 0;
41c445ff
JB		 2453
2454 is_vf = (vsi->type == I40E_VSI_SRIOV);
2455 is_netdev = !!(netdev);
2456
21659035
KP		 2457 /* Locked once because all functions invoked below iterates list */
2458 spin_lock_bh(&vsi->mac_filter_list_lock);
2459
41c445ff
JB		 2460 if (is_netdev)
2461 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2462
2463 list_for_each_entry(f, &vsi->mac_filter_list, list)
2464 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2465
41c445ff
JB		 2466 /* go through all the filters for this VSI and if there is only
2467 * vid == 0 it means there are no other filters, so vid 0 must
2468 * be replaced with -1. This signifies that we should from now
2469 * on accept any traffic (with any tag present, or untagged)
2470 */
2471 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2472 if (is_netdev) {
2473 if (f->vlan &&
2474 ether_addr_equal(netdev->dev_addr, f->macaddr))
2475 filter_count++;
2476 }
2477
2478 if (f->vlan)
2479 filter_count++;
2480 }
2481
2482 if (!filter_count && is_netdev) {
2483 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2484 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2485 is_vf, is_netdev);
2486 if (!f) {
2487 dev_info(&vsi->back->pdev->dev,
2488 "Could not add filter %d for %pM\n",
2489 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2490 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2491 return -ENOMEM;
2492 }
2493 }
2494
2495 if (!filter_count) {
2496 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2497 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2498 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2499 is_vf, is_netdev);
41c445ff
JB		 2500 if (!add_f) {
2501 dev_info(&vsi->back->pdev->dev,
2502 "Could not add filter %d for %pM\n",
2503 I40E_VLAN_ANY, f->macaddr);
21659035 2504 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2505 return -ENOMEM;
2506 }
2507 }
2508 }
2509
21659035
KP		 2510 spin_unlock_bh(&vsi->mac_filter_list_lock);
2511
0e4425ed
JB		 2512 /* schedule our worker thread which will take care of
2513 * applying the new filter changes
2514 */
2515 i40e_service_event_schedule(vsi->back);
2516 return 0;
41c445ff
JB		 2517}
2518
2519/**
2520 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2521 * @netdev: network interface to be adjusted
2522 * @vid: vlan id to be added
078b5876
JB		 2523 *
2524 * net_device_ops implementation for adding vlan ids
41c445ff 2525 **/
38e00438
VD		 2526#ifdef I40E_FCOE
2527int i40e_vlan_rx_add_vid(struct net_device *netdev,
2528 __always_unused __be16 proto, u16 vid)
2529#else
41c445ff
JB		 2530static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2531 __always_unused __be16 proto, u16 vid)
38e00438 2532#endif
41c445ff
JB		 2533{
2534 struct i40e_netdev_priv *np = netdev_priv(netdev);
2535 struct i40e_vsi *vsi = np->vsi;
078b5876 2536 int ret = 0;
41c445ff
JB		 2537
2538 if (vid > 4095)
078b5876
JB		 2539 return -EINVAL;
2540
2541 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2542
6982d429
ASJ		 2543 /* If the network stack called us with vid = 0 then
2544 * it is asking to receive priority tagged packets with
2545 * vlan id 0. Our HW receives them by default when configured
2546 * to receive untagged packets so there is no need to add an
2547 * extra filter for vlan 0 tagged packets.
41c445ff 2548 */
6982d429
ASJ		 2549 if (vid)
2550 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2551
078b5876
JB		 2552 if (!ret && (vid < VLAN_N_VID))
2553 set_bit(vid, vsi->active_vlans);
41c445ff 2554
078b5876 2555 return ret;
41c445ff
JB		 2556}
2557
2558/**
2559 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2560 * @netdev: network interface to be adjusted
2561 * @vid: vlan id to be removed
078b5876 2562 *
fdfd943e 2563 * net_device_ops implementation for removing vlan ids
41c445ff 2564 **/
38e00438
VD		 2565#ifdef I40E_FCOE
2566int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2567 __always_unused __be16 proto, u16 vid)
2568#else
41c445ff
JB		 2569static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2570 __always_unused __be16 proto, u16 vid)
38e00438 2571#endif
41c445ff
JB		 2572{
2573 struct i40e_netdev_priv *np = netdev_priv(netdev);
2574 struct i40e_vsi *vsi = np->vsi;
2575
078b5876
JB		 2576 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2577
41c445ff
JB		 2578 /* return code is ignored as there is nothing a user
2579 * can do about failure to remove and a log message was
078b5876 2580 * already printed from the other function
41c445ff
JB		 2581 */
2582 i40e_vsi_kill_vlan(vsi, vid);
2583
2584 clear_bit(vid, vsi->active_vlans);
078b5876 2585
41c445ff
JB		 2586 return 0;
2587}
2588
2589/**
2590 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2591 * @vsi: the vsi being brought back up
2592 **/
2593static void i40e_restore_vlan(struct i40e_vsi *vsi)
2594{
2595 u16 vid;
2596
2597 if (!vsi->netdev)
2598 return;
2599
2600 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2601
2602 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2603 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2604 vid);
2605}
2606
2607/**
2608 * i40e_vsi_add_pvid - Add pvid for the VSI
2609 * @vsi: the vsi being adjusted
2610 * @vid: the vlan id to set as a PVID
2611 **/
dcae29be 2612int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2613{
2614 struct i40e_vsi_context ctxt;
f1c7e72e 2615 i40e_status ret;
41c445ff
JB		 2616
2617 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2618 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2619 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2620 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2621 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2622
2623 ctxt.seid = vsi->seid;
1a2f6248 2624 ctxt.info = vsi->info;
f1c7e72e
SN		 2625 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2626 if (ret) {
41c445ff 2627 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2628 "add pvid failed, err %s aq_err %s\n",
2629 i40e_stat_str(&vsi->back->hw, ret),
2630 i40e_aq_str(&vsi->back->hw,
2631 vsi->back->hw.aq.asq_last_status));
dcae29be 2632 return -ENOENT;
41c445ff
JB		 2633 }
2634
dcae29be 2635 return 0;
41c445ff
JB		 2636}
2637
2638/**
2639 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2640 * @vsi: the vsi being adjusted
2641 *
2642 * Just use the vlan_rx_register() service to put it back to normal
2643 **/
2644void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2645{
6c12fcbf
GR		 2646 i40e_vlan_stripping_disable(vsi);
2647
41c445ff 2648 vsi->info.pvid = 0;
41c445ff
JB		 2649}
2650
2651/**
2652 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2653 * @vsi: ptr to the VSI
2654 *
2655 * If this function returns with an error, then it's possible one or
2656 * more of the rings is populated (while the rest are not). It is the
2657 * callers duty to clean those orphaned rings.
2658 *
2659 * Return 0 on success, negative on failure
2660 **/
2661static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2662{
2663 int i, err = 0;
2664
2665 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2666 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2667
2668 return err;
2669}
2670
2671/**
2672 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2673 * @vsi: ptr to the VSI
2674 *
2675 * Free VSI's transmit software resources
2676 **/
2677static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2678{
2679 int i;
2680
8e9dca53
GR		 2681 if (!vsi->tx_rings)
2682 return;
2683
41c445ff 2684 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2685 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2686 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2687}
2688
2689/**
2690 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2691 * @vsi: ptr to the VSI
2692 *
2693 * If this function returns with an error, then it's possible one or
2694 * more of the rings is populated (while the rest are not). It is the
2695 * callers duty to clean those orphaned rings.
2696 *
2697 * Return 0 on success, negative on failure
2698 **/
2699static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2700{
2701 int i, err = 0;
2702
2703 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2704 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2705#ifdef I40E_FCOE
2706 i40e_fcoe_setup_ddp_resources(vsi);
2707#endif
41c445ff
JB		 2708 return err;
2709}
2710
2711/**
2712 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2713 * @vsi: ptr to the VSI
2714 *
2715 * Free all receive software resources
2716 **/
2717static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2718{
2719 int i;
2720
8e9dca53
GR		 2721 if (!vsi->rx_rings)
2722 return;
2723
41c445ff 2724 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2725 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2726 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2727#ifdef I40E_FCOE
2728 i40e_fcoe_free_ddp_resources(vsi);
2729#endif
41c445ff
JB		 2730}
2731
3ffa037d
NP		 2732/**
2733 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2734 * @ring: The Tx ring to configure
2735 *
2736 * This enables/disables XPS for a given Tx descriptor ring
2737 * based on the TCs enabled for the VSI that ring belongs to.
2738 **/
2739static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2740{
2741 struct i40e_vsi *vsi = ring->vsi;
2742 cpumask_var_t mask;
2743
9a660eea
JB		 2744 if (!ring->q_vector || !ring->netdev)
2745 return;
2746
2747 /* Single TC mode enable XPS */
2748 if (vsi->tc_config.numtc <= 1) {
2749 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2750 netif_set_xps_queue(ring->netdev,
2751 &ring->q_vector->affinity_mask,
2752 ring->queue_index);
9a660eea
JB		 2753 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2754 /* Disable XPS to allow selection based on TC */
2755 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2756 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2757 free_cpumask_var(mask);
3ffa037d 2758 }
0e4425ed
JB		 2759
2760 /* schedule our worker thread which will take care of
2761 * applying the new filter changes
2762 */
2763 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2764}
2765
41c445ff
JB		 2766/**
2767 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2768 * @ring: The Tx ring to configure
2769 *
2770 * Configure the Tx descriptor ring in the HMC context.
2771 **/
2772static int i40e_configure_tx_ring(struct i40e_ring *ring)
2773{
2774 struct i40e_vsi *vsi = ring->vsi;
2775 u16 pf_q = vsi->base_queue + ring->queue_index;
2776 struct i40e_hw *hw = &vsi->back->hw;
2777 struct i40e_hmc_obj_txq tx_ctx;
2778 i40e_status err = 0;
2779 u32 qtx_ctl = 0;
2780
2781 /* some ATR related tx ring init */
60ea5f83 2782 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2783 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2784 ring->atr_count = 0;
2785 } else {
2786 ring->atr_sample_rate = 0;
2787 }
2788
3ffa037d
NP		 2789 /* configure XPS */
2790 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2791
2792 /* clear the context structure first */
2793 memset(&tx_ctx, 0, sizeof(tx_ctx));
2794
2795 tx_ctx.new_context = 1;
2796 tx_ctx.base = (ring->dma / 128);
2797 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2798 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2799 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2800#ifdef I40E_FCOE
2801 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2802#endif
beb0dff1 2803 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2804 /* FDIR VSI tx ring can still use RS bit and writebacks */
2805 if (vsi->type != I40E_VSI_FDIR)
2806 tx_ctx.head_wb_ena = 1;
2807 tx_ctx.head_wb_addr = ring->dma +
2808 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2809
2810 /* As part of VSI creation/update, FW allocates certain
2811 * Tx arbitration queue sets for each TC enabled for
2812 * the VSI. The FW returns the handles to these queue
2813 * sets as part of the response buffer to Add VSI,
2814 * Update VSI, etc. AQ commands. It is expected that
2815 * these queue set handles be associated with the Tx
2816 * queues by the driver as part of the TX queue context
2817 * initialization. This has to be done regardless of
2818 * DCB as by default everything is mapped to TC0.
2819 */
2820 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2821 tx_ctx.rdylist_act = 0;
2822
2823 /* clear the context in the HMC */
2824 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2825 if (err) {
2826 dev_info(&vsi->back->pdev->dev,
2827 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2828 ring->queue_index, pf_q, err);
2829 return -ENOMEM;
2830 }
2831
2832 /* set the context in the HMC */
2833 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2834 if (err) {
2835 dev_info(&vsi->back->pdev->dev,
2836 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2837 ring->queue_index, pf_q, err);
2838 return -ENOMEM;
2839 }
2840
2841 /* Now associate this queue with this PCI function */
7a28d885 2842 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2843 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2844 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2845 I40E_QTX_CTL_VFVM_INDX_MASK;
2846 } else {
9d8bf547 2847 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2848 }
2849
13fd9774
SN		 2850 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2851 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2852 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2853 i40e_flush(hw);
2854
41c445ff
JB		 2855 /* cache tail off for easier writes later */
2856 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2857
2858 return 0;
2859}
2860
2861/**
2862 * i40e_configure_rx_ring - Configure a receive ring context
2863 * @ring: The Rx ring to configure
2864 *
2865 * Configure the Rx descriptor ring in the HMC context.
2866 **/
2867static int i40e_configure_rx_ring(struct i40e_ring *ring)
2868{
2869 struct i40e_vsi *vsi = ring->vsi;
2870 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2871 u16 pf_q = vsi->base_queue + ring->queue_index;
2872 struct i40e_hw *hw = &vsi->back->hw;
2873 struct i40e_hmc_obj_rxq rx_ctx;
2874 i40e_status err = 0;
2875
2876 ring->state = 0;
2877
2878 /* clear the context structure first */
2879 memset(&rx_ctx, 0, sizeof(rx_ctx));
2880
2881 ring->rx_buf_len = vsi->rx_buf_len;
41c445ff
JB		 2882
2883 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
41c445ff
JB		 2884
2885 rx_ctx.base = (ring->dma / 128);
2886 rx_ctx.qlen = ring->count;
2887
bec60fc4
JB		 2888 /* use 32 byte descriptors */
2889 rx_ctx.dsize = 1;
41c445ff 2890
bec60fc4
JB		 2891 /* descriptor type is always zero
2892 * rx_ctx.dtype = 0;
2893 */
b32bfa17 2894 rx_ctx.hsplit_0 = 0;
41c445ff 2895
b32bfa17 2896 rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len);
7134f9ce
JB		 2897 if (hw->revision_id == 0)
2898 rx_ctx.lrxqthresh = 0;
2899 else
2900 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2901 rx_ctx.crcstrip = 1;
2902 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2903 /* this controls whether VLAN is stripped from inner headers */
2904 rx_ctx.showiv = 0;
38e00438
VD		 2905#ifdef I40E_FCOE
2906 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2907#endif
acb3676b
CS		 2908 /* set the prefena field to 1 because the manual says to */
2909 rx_ctx.prefena = 1;
41c445ff
JB		 2910
2911 /* clear the context in the HMC */
2912 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2913 if (err) {
2914 dev_info(&vsi->back->pdev->dev,
2915 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2916 ring->queue_index, pf_q, err);
2917 return -ENOMEM;
2918 }
2919
2920 /* set the context in the HMC */
2921 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2922 if (err) {
2923 dev_info(&vsi->back->pdev->dev,
2924 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2925 ring->queue_index, pf_q, err);
2926 return -ENOMEM;
2927 }
2928
2929 /* cache tail for quicker writes, and clear the reg before use */
2930 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2931 writel(0, ring->tail);
2932
1a557afc 2933 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
41c445ff
JB		 2934
2935 return 0;
2936}
2937
2938/**
2939 * i40e_vsi_configure_tx - Configure the VSI for Tx
2940 * @vsi: VSI structure describing this set of rings and resources
2941 *
2942 * Configure the Tx VSI for operation.
2943 **/
2944static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2945{
2946 int err = 0;
2947 u16 i;
2948
9f65e15b
AD		 2949 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2950 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2951
2952 return err;
2953}
2954
2955/**
2956 * i40e_vsi_configure_rx - Configure the VSI for Rx
2957 * @vsi: the VSI being configured
2958 *
2959 * Configure the Rx VSI for operation.
2960 **/
2961static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2962{
2963 int err = 0;
2964 u16 i;
2965
2966 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2967 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2968 + ETH_FCS_LEN + VLAN_HLEN;
2969 else
2970 vsi->max_frame = I40E_RXBUFFER_2048;
2971
1a557afc 2972 vsi->rx_buf_len = I40E_RXBUFFER_2048;
41c445ff 2973
38e00438
VD		 2974#ifdef I40E_FCOE
2975 /* setup rx buffer for FCoE */
2976 if ((vsi->type == I40E_VSI_FCOE) &&
2977 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
38e00438
VD		 2978 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2979 vsi->max_frame = I40E_RXBUFFER_3072;
38e00438
VD		 2980 }
2981
2982#endif /* I40E_FCOE */
41c445ff 2983 /* round up for the chip's needs */
41c445ff 2984 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2985 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2986
2987 /* set up individual rings */
2988 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2989 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2990
2991 return err;
2992}
2993
2994/**
2995 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2996 * @vsi: ptr to the VSI
2997 **/
2998static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2999{
e7046ee1 3000 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 3001 u16 qoffset, qcount;
3002 int i, n;
3003
cd238a3e
PN		 3004 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3005 /* Reset the TC information */
3006 for (i = 0; i < vsi->num_queue_pairs; i++) {
3007 rx_ring = vsi->rx_rings[i];
3008 tx_ring = vsi->tx_rings[i];
3009 rx_ring->dcb_tc = 0;
3010 tx_ring->dcb_tc = 0;
3011 }
3012 }
41c445ff
JB		 3013
3014 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3015 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3016 continue;
3017
3018 qoffset = vsi->tc_config.tc_info[n].qoffset;
3019 qcount = vsi->tc_config.tc_info[n].qcount;
3020 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3021 rx_ring = vsi->rx_rings[i];
3022 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3023 rx_ring->dcb_tc = n;
3024 tx_ring->dcb_tc = n;
3025 }
3026 }
3027}
3028
3029/**
3030 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3031 * @vsi: ptr to the VSI
3032 **/
3033static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3034{
3035 if (vsi->netdev)
3036 i40e_set_rx_mode(vsi->netdev);
3037}
3038
17a73f6b
JG		 3039/**
3040 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3041 * @vsi: Pointer to the targeted VSI
3042 *
3043 * This function replays the hlist on the hw where all the SB Flow Director
3044 * filters were saved.
3045 **/
3046static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3047{
3048 struct i40e_fdir_filter *filter;
3049 struct i40e_pf *pf = vsi->back;
3050 struct hlist_node *node;
3051
55a5e60b
ASJ		 3052 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3053 return;
3054
17a73f6b
JG		 3055 hlist_for_each_entry_safe(filter, node,
3056 &pf->fdir_filter_list, fdir_node) {
3057 i40e_add_del_fdir(vsi, filter, true);
3058 }
3059}
3060
41c445ff
JB		 3061/**
3062 * i40e_vsi_configure - Set up the VSI for action
3063 * @vsi: the VSI being configured
3064 **/
3065static int i40e_vsi_configure(struct i40e_vsi *vsi)
3066{
3067 int err;
3068
3069 i40e_set_vsi_rx_mode(vsi);
3070 i40e_restore_vlan(vsi);
3071 i40e_vsi_config_dcb_rings(vsi);
3072 err = i40e_vsi_configure_tx(vsi);
3073 if (!err)
3074 err = i40e_vsi_configure_rx(vsi);
3075
3076 return err;
3077}
3078
3079/**
3080 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3081 * @vsi: the VSI being configured
3082 **/
3083static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3084{
3085 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3086 struct i40e_hw *hw = &pf->hw;
3087 u16 vector;
3088 int i, q;
41c445ff
JB		 3089 u32 qp;
3090
3091 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3092 * and PFINT_LNKLSTn registers, e.g.:
3093 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3094 */
3095 qp = vsi->base_queue;
3096 vector = vsi->base_vector;
493fb300 3097 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3098 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3099
ee2319cf 3100 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3101 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting);
41c445ff
JB		 3102 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3103 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3104 q_vector->rx.itr);
a75e8005 3105 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting);
41c445ff
JB		 3106 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3107 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3108 q_vector->tx.itr);
ac26fc13
JB		 3109 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3110 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3111
3112 /* Linked list for the queuepairs assigned to this vector */
3113 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3114 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3115 u32 val;
3116
41c445ff
JB		 3117 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3118 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3119 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3120 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3121 (I40E_QUEUE_TYPE_TX
3122 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3123
3124 wr32(hw, I40E_QINT_RQCTL(qp), val);
3125
3126 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3127 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3128 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3129 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3130 (I40E_QUEUE_TYPE_RX
3131 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3132
3133 /* Terminate the linked list */
3134 if (q == (q_vector->num_ringpairs - 1))
3135 val |= (I40E_QUEUE_END_OF_LIST
3136 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3137
3138 wr32(hw, I40E_QINT_TQCTL(qp), val);
3139 qp++;
3140 }
3141 }
3142
3143 i40e_flush(hw);
3144}
3145
3146/**
3147 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3148 * @hw: ptr to the hardware info
3149 **/
ab437b5a 3150static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3151{
ab437b5a 3152 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3153 u32 val;
3154
3155 /* clear things first */
3156 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3157 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3158
3159 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3160 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3161 I40E_PFINT_ICR0_ENA_GRST_MASK |
3162 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3163 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3164 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3165 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3166 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3167
0d8e1439
ASJ		 3168 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3169 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3170
ab437b5a
JK		 3171 if (pf->flags & I40E_FLAG_PTP)
3172 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3173
41c445ff
JB		 3174 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3175
3176 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3177 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3178 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3179
3180 /* OTHER_ITR_IDX = 0 */
3181 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3182}
3183
3184/**
3185 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3186 * @vsi: the VSI being configured
3187 **/
3188static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3189{
493fb300 3190 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3191 struct i40e_pf *pf = vsi->back;
3192 struct i40e_hw *hw = &pf->hw;
3193 u32 val;
3194
3195 /* set the ITR configuration */
ee2319cf 3196 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3197 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting);
41c445ff
JB		 3198 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3199 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
a75e8005 3200 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting);
41c445ff
JB		 3201 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3202 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3203
ab437b5a 3204 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3205
3206 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3207 wr32(hw, I40E_PFINT_LNKLST0, 0);
3208
f29eaa3d 3209 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3210 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3211 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3212 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3213
3214 wr32(hw, I40E_QINT_RQCTL(0), val);
3215
3216 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3217 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3218 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3219
3220 wr32(hw, I40E_QINT_TQCTL(0), val);
3221 i40e_flush(hw);
3222}
3223
2ef28cfb
MW		 3224/**
3225 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3226 * @pf: board private structure
3227 **/
3228void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3229{
3230 struct i40e_hw *hw = &pf->hw;
3231
3232 wr32(hw, I40E_PFINT_DYN_CTL0,
3233 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3234 i40e_flush(hw);
3235}
3236
41c445ff
JB		 3237/**
3238 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3239 * @pf: board private structure
40d72a50 3240 * @clearpba: true when all pending interrupt events should be cleared
41c445ff 3241 **/
40d72a50 3242void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba)
41c445ff
JB		 3243{
3244 struct i40e_hw *hw = &pf->hw;
3245 u32 val;
3246
3247 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
40d72a50 3248 (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) |
41c445ff
JB		 3249 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3250
3251 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3252 i40e_flush(hw);
3253}
3254
41c445ff
JB		 3255/**
3256 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3257 * @irq: interrupt number
3258 * @data: pointer to a q_vector
3259 **/
3260static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3261{
3262 struct i40e_q_vector *q_vector = data;
3263
cd0b6fa6 3264 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3265 return IRQ_HANDLED;
3266
5d3465a1 3267 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3268
3269 return IRQ_HANDLED;
3270}
3271
41c445ff
JB		 3272/**
3273 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3274 * @vsi: the VSI being configured
3275 * @basename: name for the vector
3276 *
3277 * Allocates MSI-X vectors and requests interrupts from the kernel.
3278 **/
3279static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3280{
3281 int q_vectors = vsi->num_q_vectors;
3282 struct i40e_pf *pf = vsi->back;
3283 int base = vsi->base_vector;
3284 int rx_int_idx = 0;
3285 int tx_int_idx = 0;
3286 int vector, err;
3287
3288 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3289 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3290
cd0b6fa6 3291 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3292 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3293 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3294 tx_int_idx++;
cd0b6fa6 3295 } else if (q_vector->rx.ring) {
41c445ff
JB		 3296 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3297 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3298 } else if (q_vector->tx.ring) {
41c445ff
JB		 3299 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3300 "%s-%s-%d", basename, "tx", tx_int_idx++);
3301 } else {
3302 /* skip this unused q_vector */
3303 continue;
3304 }
3305 err = request_irq(pf->msix_entries[base + vector].vector,
3306 vsi->irq_handler,
3307 0,
3308 q_vector->name,
3309 q_vector);
3310 if (err) {
3311 dev_info(&pf->pdev->dev,
fb43201f 3312 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3313 goto free_queue_irqs;
3314 }
3315 /* assign the mask for this irq */
3316 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3317 &q_vector->affinity_mask);
3318 }
3319
63741846 3320 vsi->irqs_ready = true;
41c445ff
JB		 3321 return 0;
3322
3323free_queue_irqs:
3324 while (vector) {
3325 vector--;
3326 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3327 NULL);
3328 free_irq(pf->msix_entries[base + vector].vector,
3329 &(vsi->q_vectors[vector]));
3330 }
3331 return err;
3332}
3333
3334/**
3335 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3336 * @vsi: the VSI being un-configured
3337 **/
3338static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3339{
3340 struct i40e_pf *pf = vsi->back;
3341 struct i40e_hw *hw = &pf->hw;
3342 int base = vsi->base_vector;
3343 int i;
3344
3345 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3346 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3347 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3348 }
3349
3350 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3351 for (i = vsi->base_vector;
3352 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3353 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3354
3355 i40e_flush(hw);
3356 for (i = 0; i < vsi->num_q_vectors; i++)
3357 synchronize_irq(pf->msix_entries[i + base].vector);
3358 } else {
3359 /* Legacy and MSI mode - this stops all interrupt handling */
3360 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3361 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3362 i40e_flush(hw);
3363 synchronize_irq(pf->pdev->irq);
3364 }
3365}
3366
3367/**
3368 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3369 * @vsi: the VSI being configured
3370 **/
3371static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3372{
3373 struct i40e_pf *pf = vsi->back;
3374 int i;
3375
3376 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3377 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3378 i40e_irq_dynamic_enable(vsi, i);
3379 } else {
40d72a50 3380 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 3381 }
3382
1022cb6c 3383 i40e_flush(&pf->hw);
41c445ff
JB		 3384 return 0;
3385}
3386
3387/**
3388 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3389 * @pf: board private structure
3390 **/
3391static void i40e_stop_misc_vector(struct i40e_pf *pf)
3392{
3393 /* Disable ICR 0 */
3394 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3395 i40e_flush(&pf->hw);
3396}
3397
3398/**
3399 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3400 * @irq: interrupt number
3401 * @data: pointer to a q_vector
3402 *
3403 * This is the handler used for all MSI/Legacy interrupts, and deals
3404 * with both queue and non-queue interrupts. This is also used in
3405 * MSIX mode to handle the non-queue interrupts.
3406 **/
3407static irqreturn_t i40e_intr(int irq, void *data)
3408{
3409 struct i40e_pf *pf = (struct i40e_pf *)data;
3410 struct i40e_hw *hw = &pf->hw;
5e823066 3411 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3412 u32 icr0, icr0_remaining;
3413 u32 val, ena_mask;
3414
3415 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3416 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3417
116a57d4
SN		 3418 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3419 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3420 goto enable_intr;
41c445ff 3421
cd92e72f
SN		 3422 /* if interrupt but no bits showing, must be SWINT */
3423 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3424 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3425 pf->sw_int_count++;
3426
0d8e1439
ASJ		 3427 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3428 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3429 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3430 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3431 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3432 }
3433
41c445ff
JB		 3434 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3435 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3436 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3437 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff 3438
a16ae2d5
ASJ		 3439 /* We do not have a way to disarm Queue causes while leaving
3440 * interrupt enabled for all other causes, ideally
3441 * interrupt should be disabled while we are in NAPI but
3442 * this is not a performance path and napi_schedule()
3443 * can deal with rescheduling.
3444 */
41c445ff 3445 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3446 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3447 }
3448
3449 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3450 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3451 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6e93d0c9 3452 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n");
41c445ff
JB		 3453 }
3454
3455 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3456 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3457 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3458 }
3459
3460 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3461 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3462 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3463 }
3464
3465 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3466 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3467 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3468 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3469 val = rd32(hw, I40E_GLGEN_RSTAT);
3470 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3471 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3472 if (val == I40E_RESET_CORER) {
41c445ff 3473 pf->corer_count++;
4eb3f768 3474 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3475 pf->globr_count++;
4eb3f768 3476 } else if (val == I40E_RESET_EMPR) {
41c445ff 3477 pf->empr_count++;
9df42d1a 3478 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3479 }
41c445ff
JB		 3480 }
3481
9c010ee0
ASJ		 3482 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3483 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3484 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3485 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3486 rd32(hw, I40E_PFHMC_ERRORINFO),
3487 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3488 }
3489
beb0dff1
JK		 3490 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3491 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3492
3493 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3494 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3495 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3496 }
beb0dff1
JK		 3497 }
3498
41c445ff
JB		 3499 /* If a critical error is pending we have no choice but to reset the
3500 * device.
3501 * Report and mask out any remaining unexpected interrupts.
3502 */
3503 icr0_remaining = icr0 & ena_mask;
3504 if (icr0_remaining) {
3505 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3506 icr0_remaining);
9c010ee0 3507 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3508 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3509 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3510 dev_info(&pf->pdev->dev, "device will be reset\n");
3511 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3512 i40e_service_event_schedule(pf);
41c445ff
JB		 3513 }
3514 ena_mask &= ~icr0_remaining;
3515 }
5e823066 3516 ret = IRQ_HANDLED;
41c445ff 3517
5e823066 3518enable_intr:
41c445ff
JB		 3519 /* re-enable interrupt causes */
3520 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3521 if (!test_bit(__I40E_DOWN, &pf->state)) {
3522 i40e_service_event_schedule(pf);
40d72a50 3523 i40e_irq_dynamic_enable_icr0(pf, false);
41c445ff
JB		 3524 }
3525
5e823066 3526 return ret;
41c445ff
JB		 3527}
3528
cbf61325
ASJ		 3529/**
3530 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3531 * @tx_ring: tx ring to clean
3532 * @budget: how many cleans we're allowed
3533 *
3534 * Returns true if there's any budget left (e.g. the clean is finished)
3535 **/
3536static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3537{
3538 struct i40e_vsi *vsi = tx_ring->vsi;
3539 u16 i = tx_ring->next_to_clean;
3540 struct i40e_tx_buffer *tx_buf;
3541 struct i40e_tx_desc *tx_desc;
3542
3543 tx_buf = &tx_ring->tx_bi[i];
3544 tx_desc = I40E_TX_DESC(tx_ring, i);
3545 i -= tx_ring->count;
3546
3547 do {
3548 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3549
3550 /* if next_to_watch is not set then there is no work pending */
3551 if (!eop_desc)
3552 break;
3553
3554 /* prevent any other reads prior to eop_desc */
3555 read_barrier_depends();
3556
3557 /* if the descriptor isn't done, no work yet to do */
3558 if (!(eop_desc->cmd_type_offset_bsz &
3559 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3560 break;
3561
3562 /* clear next_to_watch to prevent false hangs */
3563 tx_buf->next_to_watch = NULL;
3564
49d7d933
ASJ		 3565 tx_desc->buffer_addr = 0;
3566 tx_desc->cmd_type_offset_bsz = 0;
3567 /* move past filter desc */
3568 tx_buf++;
3569 tx_desc++;
3570 i++;
3571 if (unlikely(!i)) {
3572 i -= tx_ring->count;
3573 tx_buf = tx_ring->tx_bi;
3574 tx_desc = I40E_TX_DESC(tx_ring, 0);
3575 }
cbf61325
ASJ		 3576 /* unmap skb header data */
3577 dma_unmap_single(tx_ring->dev,
3578 dma_unmap_addr(tx_buf, dma),
3579 dma_unmap_len(tx_buf, len),
3580 DMA_TO_DEVICE);
49d7d933
ASJ		 3581 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3582 kfree(tx_buf->raw_buf);
cbf61325 3583
49d7d933
ASJ		 3584 tx_buf->raw_buf = NULL;
3585 tx_buf->tx_flags = 0;
3586 tx_buf->next_to_watch = NULL;
cbf61325 3587 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3588 tx_desc->buffer_addr = 0;
3589 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3590
49d7d933 3591 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3592 tx_buf++;
3593 tx_desc++;
3594 i++;
3595 if (unlikely(!i)) {
3596 i -= tx_ring->count;
3597 tx_buf = tx_ring->tx_bi;
3598 tx_desc = I40E_TX_DESC(tx_ring, 0);
3599 }
3600
3601 /* update budget accounting */
3602 budget--;
3603 } while (likely(budget));
3604
3605 i += tx_ring->count;
3606 tx_ring->next_to_clean = i;
3607
6995b36c 3608 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3609 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3610
cbf61325
ASJ		 3611 return budget > 0;
3612}
3613
3614/**
3615 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3616 * @irq: interrupt number
3617 * @data: pointer to a q_vector
3618 **/
3619static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3620{
3621 struct i40e_q_vector *q_vector = data;
3622 struct i40e_vsi *vsi;
3623
3624 if (!q_vector->tx.ring)
3625 return IRQ_HANDLED;
3626
3627 vsi = q_vector->tx.ring->vsi;
3628 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3629
3630 return IRQ_HANDLED;
3631}
3632
41c445ff 3633/**
cd0b6fa6 3634 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3635 * @vsi: the VSI being configured
3636 * @v_idx: vector index
cd0b6fa6 3637 * @qp_idx: queue pair index
41c445ff 3638 **/
26cdc443 3639static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3640{
493fb300 3641 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3642 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3643 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3644
3645 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3646 tx_ring->next = q_vector->tx.ring;
3647 q_vector->tx.ring = tx_ring;
41c445ff 3648 q_vector->tx.count++;
cd0b6fa6
AD		 3649
3650 rx_ring->q_vector = q_vector;
3651 rx_ring->next = q_vector->rx.ring;
3652 q_vector->rx.ring = rx_ring;
3653 q_vector->rx.count++;
41c445ff
JB		 3654}
3655
3656/**
3657 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3658 * @vsi: the VSI being configured
3659 *
3660 * This function maps descriptor rings to the queue-specific vectors
3661 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3662 * one vector per queue pair, but on a constrained vector budget, we
3663 * group the queue pairs as "efficiently" as possible.
3664 **/
3665static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3666{
3667 int qp_remaining = vsi->num_queue_pairs;
3668 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3669 int num_ringpairs;
41c445ff
JB		 3670 int v_start = 0;
3671 int qp_idx = 0;
3672
3673 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3674 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3675 * It is also important to go through all the vectors available to be
3676 * sure that if we don't use all the vectors, that the remaining vectors
3677 * are cleared. This is especially important when decreasing the
3678 * number of queues in use.
41c445ff 3679 */
70114ec4 3680 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3681 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3682
3683 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3684
3685 q_vector->num_ringpairs = num_ringpairs;
3686
3687 q_vector->rx.count = 0;
3688 q_vector->tx.count = 0;
3689 q_vector->rx.ring = NULL;
3690 q_vector->tx.ring = NULL;
3691
3692 while (num_ringpairs--) {
26cdc443 3693 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3694 qp_idx++;
3695 qp_remaining--;
41c445ff
JB		 3696 }
3697 }
3698}
3699
3700/**
3701 * i40e_vsi_request_irq - Request IRQ from the OS
3702 * @vsi: the VSI being configured
3703 * @basename: name for the vector
3704 **/
3705static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3706{
3707 struct i40e_pf *pf = vsi->back;
3708 int err;
3709
3710 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3711 err = i40e_vsi_request_irq_msix(vsi, basename);
3712 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3713 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3714 pf->int_name, pf);
41c445ff
JB		 3715 else
3716 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3717 pf->int_name, pf);
41c445ff
JB		 3718
3719 if (err)
3720 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3721
3722 return err;
3723}
3724
3725#ifdef CONFIG_NET_POLL_CONTROLLER
3726/**
d89d967f 3727 * i40e_netpoll - A Polling 'interrupt' handler
41c445ff
JB		 3728 * @netdev: network interface device structure
3729 *
3730 * This is used by netconsole to send skbs without having to re-enable
3731 * interrupts. It's not called while the normal interrupt routine is executing.
3732 **/
38e00438
VD		 3733#ifdef I40E_FCOE
3734void i40e_netpoll(struct net_device *netdev)
3735#else
41c445ff 3736static void i40e_netpoll(struct net_device *netdev)
38e00438 3737#endif
41c445ff
JB		 3738{
3739 struct i40e_netdev_priv *np = netdev_priv(netdev);
3740 struct i40e_vsi *vsi = np->vsi;
3741 struct i40e_pf *pf = vsi->back;
3742 int i;
3743
3744 /* if interface is down do nothing */
3745 if (test_bit(__I40E_DOWN, &vsi->state))
3746 return;
3747
41c445ff
JB		 3748 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3749 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3750 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3751 } else {
3752 i40e_intr(pf->pdev->irq, netdev);
3753 }
41c445ff
JB		 3754}
3755#endif
3756
23527308
NP		 3757/**
3758 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3759 * @pf: the PF being configured
3760 * @pf_q: the PF queue
3761 * @enable: enable or disable state of the queue
3762 *
3763 * This routine will wait for the given Tx queue of the PF to reach the
3764 * enabled or disabled state.
3765 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3766 * multiple retries; else will return 0 in case of success.
3767 **/
3768static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3769{
3770 int i;
3771 u32 tx_reg;
3772
3773 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3774 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3775 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3776 break;
3777
f98a2006 3778 usleep_range(10, 20);
23527308
NP		 3779 }
3780 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3781 return -ETIMEDOUT;
3782
3783 return 0;
3784}
3785
41c445ff
JB		 3786/**
3787 * i40e_vsi_control_tx - Start or stop a VSI's rings
3788 * @vsi: the VSI being configured
3789 * @enable: start or stop the rings
3790 **/
3791static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3792{
3793 struct i40e_pf *pf = vsi->back;
3794 struct i40e_hw *hw = &pf->hw;
23527308 3795 int i, j, pf_q, ret = 0;
41c445ff
JB		 3796 u32 tx_reg;
3797
3798 pf_q = vsi->base_queue;
3799 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3800
3801 /* warn the TX unit of coming changes */
3802 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3803 if (!enable)
f98a2006 3804 usleep_range(10, 20);
351499ab 3805
6c5ef620 3806 for (j = 0; j < 50; j++) {
41c445ff 3807 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3808 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3809 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3810 break;
3811 usleep_range(1000, 2000);
3812 }
fda972f6 3813 /* Skip if the queue is already in the requested state */
7c122007 3814 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3815 continue;
41c445ff
JB		 3816
3817 /* turn on/off the queue */
c5c9eb9e
SN		 3818 if (enable) {
3819 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3820 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3821 } else {
41c445ff 3822 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3823 }
41c445ff
JB		 3824
3825 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3826 /* No waiting for the Tx queue to disable */
3827 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3828 continue;
41c445ff
JB		 3829
3830 /* wait for the change to finish */
23527308
NP		 3831 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3832 if (ret) {
3833 dev_info(&pf->pdev->dev,
fb43201f
SN		 3834 "VSI seid %d Tx ring %d %sable timeout\n",
3835 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3836 break;
41c445ff
JB		 3837 }
3838 }
3839
7134f9ce
JB		 3840 if (hw->revision_id == 0)
3841 mdelay(50);
23527308
NP		 3842 return ret;
3843}
3844
3845/**
3846 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3847 * @pf: the PF being configured
3848 * @pf_q: the PF queue
3849 * @enable: enable or disable state of the queue
3850 *
3851 * This routine will wait for the given Rx queue of the PF to reach the
3852 * enabled or disabled state.
3853 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3854 * multiple retries; else will return 0 in case of success.
3855 **/
3856static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3857{
3858 int i;
3859 u32 rx_reg;
3860
3861 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3862 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3863 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3864 break;
3865
f98a2006 3866 usleep_range(10, 20);
23527308
NP		 3867 }
3868 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3869 return -ETIMEDOUT;
7134f9ce 3870
41c445ff
JB		 3871 return 0;
3872}
3873
3874/**
3875 * i40e_vsi_control_rx - Start or stop a VSI's rings
3876 * @vsi: the VSI being configured
3877 * @enable: start or stop the rings
3878 **/
3879static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3880{
3881 struct i40e_pf *pf = vsi->back;
3882 struct i40e_hw *hw = &pf->hw;
23527308 3883 int i, j, pf_q, ret = 0;
41c445ff
JB		 3884 u32 rx_reg;
3885
3886 pf_q = vsi->base_queue;
3887 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3888 for (j = 0; j < 50; j++) {
41c445ff 3889 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3890 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3891 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3892 break;
3893 usleep_range(1000, 2000);
3894 }
41c445ff 3895
7c122007
CS		 3896 /* Skip if the queue is already in the requested state */
3897 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3898 continue;
41c445ff
JB		 3899
3900 /* turn on/off the queue */
3901 if (enable)
6c5ef620 3902 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3903 else
6c5ef620 3904 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3905 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3fe06f41
NP		 3906 /* No waiting for the Tx queue to disable */
3907 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3908 continue;
41c445ff
JB		 3909
3910 /* wait for the change to finish */
23527308
NP		 3911 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3912 if (ret) {
3913 dev_info(&pf->pdev->dev,
fb43201f
SN		 3914 "VSI seid %d Rx ring %d %sable timeout\n",
3915 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3916 break;
41c445ff
JB		 3917 }
3918 }
3919
23527308 3920 return ret;
41c445ff
JB		 3921}
3922
3923/**
3924 * i40e_vsi_control_rings - Start or stop a VSI's rings
3925 * @vsi: the VSI being configured
3926 * @enable: start or stop the rings
3927 **/
fc18eaa0 3928int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3929{
3b867b28 3930 int ret = 0;
41c445ff
JB		 3931
3932 /* do rx first for enable and last for disable */
3933 if (request) {
3934 ret = i40e_vsi_control_rx(vsi, request);
3935 if (ret)
3936 return ret;
3937 ret = i40e_vsi_control_tx(vsi, request);
3938 } else {
3b867b28
ASJ		 3939 /* Ignore return value, we need to shutdown whatever we can */
3940 i40e_vsi_control_tx(vsi, request);
3941 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3942 }
3943
3944 return ret;
3945}
3946
3947/**
3948 * i40e_vsi_free_irq - Free the irq association with the OS
3949 * @vsi: the VSI being configured
3950 **/
3951static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3952{
3953 struct i40e_pf *pf = vsi->back;
3954 struct i40e_hw *hw = &pf->hw;
3955 int base = vsi->base_vector;
3956 u32 val, qp;
3957 int i;
3958
3959 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3960 if (!vsi->q_vectors)
3961 return;
3962
63741846
SN		 3963 if (!vsi->irqs_ready)
3964 return;
3965
3966 vsi->irqs_ready = false;
41c445ff
JB		 3967 for (i = 0; i < vsi->num_q_vectors; i++) {
3968 u16 vector = i + base;
3969
3970 /* free only the irqs that were actually requested */
78681b1f
SN		 3971 if (!vsi->q_vectors[i] ||
3972 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3973 continue;
3974
3975 /* clear the affinity_mask in the IRQ descriptor */
3976 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3977 NULL);
b33d3b73 3978 synchronize_irq(pf->msix_entries[vector].vector);
41c445ff 3979 free_irq(pf->msix_entries[vector].vector,
493fb300 3980 vsi->q_vectors[i]);
41c445ff
JB		 3981
3982 /* Tear down the interrupt queue link list
3983 *
3984 * We know that they come in pairs and always
3985 * the Rx first, then the Tx. To clear the
3986 * link list, stick the EOL value into the
3987 * next_q field of the registers.
3988 */
3989 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3990 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3991 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3992 val |= I40E_QUEUE_END_OF_LIST
3993 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3994 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3995
3996 while (qp != I40E_QUEUE_END_OF_LIST) {
3997 u32 next;
3998
3999 val = rd32(hw, I40E_QINT_RQCTL(qp));
4000
4001 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4002 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4003 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4004 I40E_QINT_RQCTL_INTEVENT_MASK);
4005
4006 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4007 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4008
4009 wr32(hw, I40E_QINT_RQCTL(qp), val);
4010
4011 val = rd32(hw, I40E_QINT_TQCTL(qp));
4012
4013 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4014 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4015
4016 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4017 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4018 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4019 I40E_QINT_TQCTL_INTEVENT_MASK);
4020
4021 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4022 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4023
4024 wr32(hw, I40E_QINT_TQCTL(qp), val);
4025 qp = next;
4026 }
4027 }
4028 } else {
4029 free_irq(pf->pdev->irq, pf);
4030
4031 val = rd32(hw, I40E_PFINT_LNKLST0);
4032 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4033 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4034 val |= I40E_QUEUE_END_OF_LIST
4035 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4036 wr32(hw, I40E_PFINT_LNKLST0, val);
4037
4038 val = rd32(hw, I40E_QINT_RQCTL(qp));
4039 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4040 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4041 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4042 I40E_QINT_RQCTL_INTEVENT_MASK);
4043
4044 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4045 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4046
4047 wr32(hw, I40E_QINT_RQCTL(qp), val);
4048
4049 val = rd32(hw, I40E_QINT_TQCTL(qp));
4050
4051 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4052 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4053 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4054 I40E_QINT_TQCTL_INTEVENT_MASK);
4055
4056 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4057 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4058
4059 wr32(hw, I40E_QINT_TQCTL(qp), val);
4060 }
4061}
4062
493fb300
AD		 4063/**
4064 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4065 * @vsi: the VSI being configured
4066 * @v_idx: Index of vector to be freed
4067 *
4068 * This function frees the memory allocated to the q_vector. In addition if
4069 * NAPI is enabled it will delete any references to the NAPI struct prior
4070 * to freeing the q_vector.
4071 **/
4072static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4073{
4074 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4075 struct i40e_ring *ring;
493fb300
AD		 4076
4077 if (!q_vector)
4078 return;
4079
4080 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4081 i40e_for_each_ring(ring, q_vector->tx)
4082 ring->q_vector = NULL;
4083
4084 i40e_for_each_ring(ring, q_vector->rx)
4085 ring->q_vector = NULL;
493fb300
AD		 4086
4087 /* only VSI w/ an associated netdev is set up w/ NAPI */
4088 if (vsi->netdev)
4089 netif_napi_del(&q_vector->napi);
4090
4091 vsi->q_vectors[v_idx] = NULL;
4092
4093 kfree_rcu(q_vector, rcu);
4094}
4095
41c445ff
JB		 4096/**
4097 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4098 * @vsi: the VSI being un-configured
4099 *
4100 * This frees the memory allocated to the q_vectors and
4101 * deletes references to the NAPI struct.
4102 **/
4103static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4104{
4105 int v_idx;
4106
493fb300
AD		 4107 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4108 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4109}
4110
4111/**
4112 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4113 * @pf: board private structure
4114 **/
4115static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4116{
4117 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4118 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4119 pci_disable_msix(pf->pdev);
4120 kfree(pf->msix_entries);
4121 pf->msix_entries = NULL;
3b444399
SN		 4122 kfree(pf->irq_pile);
4123 pf->irq_pile = NULL;
41c445ff
JB		 4124 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4125 pci_disable_msi(pf->pdev);
4126 }
4127 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4128}
4129
4130/**
4131 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4132 * @pf: board private structure
4133 *
4134 * We go through and clear interrupt specific resources and reset the structure
4135 * to pre-load conditions
4136 **/
4137static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4138{
4139 int i;
4140
e147758d 4141 i40e_stop_misc_vector(pf);
69278398 4142 if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) {
e147758d
SN		 4143 synchronize_irq(pf->msix_entries[0].vector);
4144 free_irq(pf->msix_entries[0].vector, pf);
4145 }
4146
e3219ce6
ASJ		 4147 i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector,
4148 I40E_IWARP_IRQ_PILE_ID);
4149
41c445ff 4150 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4151 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4152 if (pf->vsi[i])
4153 i40e_vsi_free_q_vectors(pf->vsi[i]);
4154 i40e_reset_interrupt_capability(pf);
4155}
4156
4157/**
4158 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4159 * @vsi: the VSI being configured
4160 **/
4161static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4162{
4163 int q_idx;
4164
4165 if (!vsi->netdev)
4166 return;
4167
4168 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4169 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4170}
4171
4172/**
4173 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4174 * @vsi: the VSI being configured
4175 **/
4176static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4177{
4178 int q_idx;
4179
4180 if (!vsi->netdev)
4181 return;
4182
4183 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4184 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4185}
4186
90ef8d47
SN		 4187/**
4188 * i40e_vsi_close - Shut down a VSI
4189 * @vsi: the vsi to be quelled
4190 **/
4191static void i40e_vsi_close(struct i40e_vsi *vsi)
4192{
e3219ce6
ASJ		 4193 bool reset = false;
4194
90ef8d47
SN		 4195 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4196 i40e_down(vsi);
4197 i40e_vsi_free_irq(vsi);
4198 i40e_vsi_free_tx_resources(vsi);
4199 i40e_vsi_free_rx_resources(vsi);
92faef85 4200 vsi->current_netdev_flags = 0;
e3219ce6
ASJ		 4201 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4202 reset = true;
4203 i40e_notify_client_of_netdev_close(vsi, reset);
90ef8d47
SN		 4204}
4205
41c445ff
JB		 4206/**
4207 * i40e_quiesce_vsi - Pause a given VSI
4208 * @vsi: the VSI being paused
4209 **/
4210static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4211{
4212 if (test_bit(__I40E_DOWN, &vsi->state))
4213 return;
4214
d341b7a5
NP		 4215 /* No need to disable FCoE VSI when Tx suspended */
4216 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4217 vsi->type == I40E_VSI_FCOE) {
4218 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4219 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4220 return;
4221 }
4222
41c445ff 4223 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4224 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4225 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4226 else
90ef8d47 4227 i40e_vsi_close(vsi);
41c445ff
JB		 4228}
4229
4230/**
4231 * i40e_unquiesce_vsi - Resume a given VSI
4232 * @vsi: the VSI being resumed
4233 **/
4234static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4235{
4236 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4237 return;
4238
4239 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4240 if (vsi->netdev && netif_running(vsi->netdev))
4241 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4242 else
8276f757 4243 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4244}
4245
4246/**
4247 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4248 * @pf: the PF
4249 **/
4250static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4251{
4252 int v;
4253
505682cd 4254 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4255 if (pf->vsi[v])
4256 i40e_quiesce_vsi(pf->vsi[v]);
4257 }
4258}
4259
4260/**
4261 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4262 * @pf: the PF
4263 **/
4264static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4265{
4266 int v;
4267
505682cd 4268 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4269 if (pf->vsi[v])
4270 i40e_unquiesce_vsi(pf->vsi[v]);
4271 }
4272}
4273
69129dc3
NP		 4274#ifdef CONFIG_I40E_DCB
4275/**
3fe06f41 4276 * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled
69129dc3
NP		 4277 * @vsi: the VSI being configured
4278 *
3fe06f41 4279 * This function waits for the given VSI's queues to be disabled.
69129dc3 4280 **/
3fe06f41 4281static int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi)
69129dc3
NP		 4282{
4283 struct i40e_pf *pf = vsi->back;
4284 int i, pf_q, ret;
4285
4286 pf_q = vsi->base_queue;
4287 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4288 /* Check and wait for the disable status of the queue */
4289 ret = i40e_pf_txq_wait(pf, pf_q, false);
4290 if (ret) {
4291 dev_info(&pf->pdev->dev,
fb43201f
SN		 4292 "VSI seid %d Tx ring %d disable timeout\n",
4293 vsi->seid, pf_q);
69129dc3
NP		 4294 return ret;
4295 }
4296 }
4297
3fe06f41
NP		 4298 pf_q = vsi->base_queue;
4299 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4300 /* Check and wait for the disable status of the queue */
4301 ret = i40e_pf_rxq_wait(pf, pf_q, false);
4302 if (ret) {
4303 dev_info(&pf->pdev->dev,
4304 "VSI seid %d Rx ring %d disable timeout\n",
4305 vsi->seid, pf_q);
4306 return ret;
4307 }
4308 }
4309
69129dc3
NP		 4310 return 0;
4311}
4312
4313/**
3fe06f41 4314 * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled
69129dc3
NP		 4315 * @pf: the PF
4316 *
3fe06f41 4317 * This function waits for the queues to be in disabled state for all the
69129dc3
NP		 4318 * VSIs that are managed by this PF.
4319 **/
3fe06f41 4320static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf)
69129dc3
NP		 4321{
4322 int v, ret = 0;
4323
4324 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4325 /* No need to wait for FCoE VSI queues */
4326 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
3fe06f41 4327 ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]);
69129dc3
NP		 4328 if (ret)
4329 break;
4330 }
4331 }
4332
4333 return ret;
4334}
4335
4336#endif
b03a8c1f
KP		 4337
4338/**
4339 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4340 * @q_idx: TX queue number
4341 * @vsi: Pointer to VSI struct
4342 *
4343 * This function checks specified queue for given VSI. Detects hung condition.
4344 * Sets hung bit since it is two step process. Before next run of service task
4345 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4346 * hung condition remain unchanged and during subsequent run, this function
4347 * issues SW interrupt to recover from hung condition.
4348 **/
4349static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4350{
4351 struct i40e_ring *tx_ring = NULL;
4352 struct i40e_pf *pf;
dd353109 4353 u32 head, val, tx_pending_hw;
b03a8c1f
KP		 4354 int i;
4355
4356 pf = vsi->back;
4357
4358 /* now that we have an index, find the tx_ring struct */
4359 for (i = 0; i < vsi->num_queue_pairs; i++) {
4360 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4361 if (q_idx == vsi->tx_rings[i]->queue_index) {
4362 tx_ring = vsi->tx_rings[i];
4363 break;
4364 }
4365 }
4366 }
4367
4368 if (!tx_ring)
4369 return;
4370
4371 /* Read interrupt register */
4372 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4373 val = rd32(&pf->hw,
4374 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4375 tx_ring->vsi->base_vector - 1));
4376 else
4377 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4378
4379 head = i40e_get_head(tx_ring);
4380
dd353109 4381 tx_pending_hw = i40e_get_tx_pending(tx_ring, false);
b03a8c1f 4382
9c6c1259
KP		 4383 /* HW is done executing descriptors, updated HEAD write back,
4384 * but SW hasn't processed those descriptors. If interrupt is
4385 * not generated from this point ON, it could result into
4386 * dev_watchdog detecting timeout on those netdev_queue,
4387 * hence proactively trigger SW interrupt.
b03a8c1f 4388 */
dd353109 4389 if (tx_pending_hw && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
9c6c1259
KP		 4390 /* NAPI Poll didn't run and clear since it was set */
4391 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4392 &tx_ring->q_vector->hung_detected)) {
dd353109
ASJ		 4393 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending_hw: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4394 vsi->seid, q_idx, tx_pending_hw,
9c6c1259
KP		 4395 tx_ring->next_to_clean, head,
4396 tx_ring->next_to_use,
4397 readl(tx_ring->tail));
4398 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4399 vsi->seid, q_idx, val);
4400 i40e_force_wb(vsi, tx_ring->q_vector);
4401 } else {
4402 /* First Chance - detected possible hung */
4403 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4404 &tx_ring->q_vector->hung_detected);
4405 }
4406 }
dd353109
ASJ		 4407
4408 /* This is the case where we have interrupts missing,
4409 * so the tx_pending in HW will most likely be 0, but we
4410 * will have tx_pending in SW since the WB happened but the
4411 * interrupt got lost.
4412 */
4413 if ((!tx_pending_hw) && i40e_get_tx_pending(tx_ring, true) &&
4414 (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
4415 if (napi_reschedule(&tx_ring->q_vector->napi))
4416 tx_ring->tx_stats.tx_lost_interrupt++;
4417 }
b03a8c1f
KP		 4418}
4419
4420/**
4421 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4422 * @pf: pointer to PF struct
4423 *
4424 * LAN VSI has netdev and netdev has TX queues. This function is to check
4425 * each of those TX queues if they are hung, trigger recovery by issuing
4426 * SW interrupt.
4427 **/
4428static void i40e_detect_recover_hung(struct i40e_pf *pf)
4429{
4430 struct net_device *netdev;
4431 struct i40e_vsi *vsi;
4432 int i;
4433
4434 /* Only for LAN VSI */
4435 vsi = pf->vsi[pf->lan_vsi];
4436
4437 if (!vsi)
4438 return;
4439
4440 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4441 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4442 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4443 return;
4444
4445 /* Make sure type is MAIN VSI */
4446 if (vsi->type != I40E_VSI_MAIN)
4447 return;
4448
4449 netdev = vsi->netdev;
4450 if (!netdev)
4451 return;
4452
4453 /* Bail out if netif_carrier is not OK */
4454 if (!netif_carrier_ok(netdev))
4455 return;
4456
4457 /* Go thru' TX queues for netdev */
4458 for (i = 0; i < netdev->num_tx_queues; i++) {
4459 struct netdev_queue *q;
4460
4461 q = netdev_get_tx_queue(netdev, i);
4462 if (q)
4463 i40e_detect_recover_hung_queue(i, vsi);
4464 }
4465}
4466
63d7e5a4
NP		 4467/**
4468 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4469 * @pf: pointer to PF
63d7e5a4
NP		 4470 *
4471 * Get TC map for ISCSI PF type that will include iSCSI TC
4472 * and LAN TC.
4473 **/
4474static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4475{
4476 struct i40e_dcb_app_priority_table app;
4477 struct i40e_hw *hw = &pf->hw;
4478 u8 enabled_tc = 1; /* TC0 is always enabled */
4479 u8 tc, i;
4480 /* Get the iSCSI APP TLV */
4481 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4482
4483 for (i = 0; i < dcbcfg->numapps; i++) {
4484 app = dcbcfg->app[i];
4485 if (app.selector == I40E_APP_SEL_TCPIP &&
4486 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4487 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4488 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4489 break;
4490 }
4491 }
4492
4493 return enabled_tc;
4494}
4495
41c445ff
JB		 4496/**
4497 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4498 * @dcbcfg: the corresponding DCBx configuration structure
4499 *
4500 * Return the number of TCs from given DCBx configuration
4501 **/
4502static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4503{
078b5876
JB		 4504 u8 num_tc = 0;
4505 int i;
41c445ff
JB		 4506
4507 /* Scan the ETS Config Priority Table to find
4508 * traffic class enabled for a given priority
4509 * and use the traffic class index to get the
4510 * number of traffic classes enabled
4511 */
4512 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4513 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4514 num_tc = dcbcfg->etscfg.prioritytable[i];
4515 }
4516
4517 /* Traffic class index starts from zero so
4518 * increment to return the actual count
4519 */
078b5876 4520 return num_tc + 1;
41c445ff
JB		 4521}
4522
4523/**
4524 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4525 * @dcbcfg: the corresponding DCBx configuration structure
4526 *
4527 * Query the current DCB configuration and return the number of
4528 * traffic classes enabled from the given DCBX config
4529 **/
4530static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4531{
4532 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4533 u8 enabled_tc = 1;
4534 u8 i;
4535
4536 for (i = 0; i < num_tc; i++)
41a1d04b 4537 enabled_tc |= BIT(i);
41c445ff
JB		 4538
4539 return enabled_tc;
4540}
4541
4542/**
4543 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4544 * @pf: PF being queried
4545 *
4546 * Return number of traffic classes enabled for the given PF
4547 **/
4548static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4549{
4550 struct i40e_hw *hw = &pf->hw;
4551 u8 i, enabled_tc;
4552 u8 num_tc = 0;
4553 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4554
4555 /* If DCB is not enabled then always in single TC */
4556 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4557 return 1;
4558
63d7e5a4
NP		 4559 /* SFP mode will be enabled for all TCs on port */
4560 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4561 return i40e_dcb_get_num_tc(dcbcfg);
4562
41c445ff 4563 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4564 if (pf->hw.func_caps.iscsi)
4565 enabled_tc = i40e_get_iscsi_tc_map(pf);
4566 else
fc51de96 4567 return 1; /* Only TC0 */
41c445ff 4568
63d7e5a4
NP		 4569 /* At least have TC0 */
4570 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4571 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4572 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4573 num_tc++;
4574 }
4575 return num_tc;
41c445ff
JB		 4576}
4577
4578/**
4579 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4580 * @pf: PF being queried
4581 *
4582 * Return a bitmap for first enabled traffic class for this PF.
4583 **/
4584static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4585{
4586 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4587 u8 i = 0;
4588
4589 if (!enabled_tc)
4590 return 0x1; /* TC0 */
4591
4592 /* Find the first enabled TC */
4593 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4594 if (enabled_tc & BIT(i))
41c445ff
JB		 4595 break;
4596 }
4597
41a1d04b 4598 return BIT(i);
41c445ff
JB		 4599}
4600
4601/**
4602 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4603 * @pf: PF being queried
4604 *
4605 * Return a bitmap for enabled traffic classes for this PF.
4606 **/
4607static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4608{
4609 /* If DCB is not enabled for this PF then just return default TC */
4610 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4611 return i40e_pf_get_default_tc(pf);
4612
41c445ff 4613 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4614 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4615 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4616
fc51de96 4617 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4618 if (pf->hw.func_caps.iscsi)
4619 return i40e_get_iscsi_tc_map(pf);
4620 else
fc51de96 4621 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4622}
4623
4624/**
4625 * i40e_vsi_get_bw_info - Query VSI BW Information
4626 * @vsi: the VSI being queried
4627 *
4628 * Returns 0 on success, negative value on failure
4629 **/
4630static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4631{
4632 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4633 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4634 struct i40e_pf *pf = vsi->back;
4635 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4636 i40e_status ret;
41c445ff 4637 u32 tc_bw_max;
41c445ff
JB		 4638 int i;
4639
4640 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4641 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4642 if (ret) {
41c445ff 4643 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4644 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4645 i40e_stat_str(&pf->hw, ret),
4646 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4647 return -EINVAL;
41c445ff
JB		 4648 }
4649
4650 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4651 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4652 NULL);
4653 if (ret) {
41c445ff 4654 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4655 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4656 i40e_stat_str(&pf->hw, ret),
4657 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4658 return -EINVAL;
41c445ff
JB		 4659 }
4660
4661 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4662 dev_info(&pf->pdev->dev,
4663 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4664 bw_config.tc_valid_bits,
4665 bw_ets_config.tc_valid_bits);
4666 /* Still continuing */
4667 }
4668
4669 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4670 vsi->bw_max_quanta = bw_config.max_bw;
4671 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4672 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4673 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4674 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4675 vsi->bw_ets_limit_credits[i] =
4676 le16_to_cpu(bw_ets_config.credits[i]);
4677 /* 3 bits out of 4 for each TC */
4678 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4679 }
078b5876 4680
dcae29be 4681 return 0;
41c445ff
JB		 4682}
4683
4684/**
4685 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4686 * @vsi: the VSI being configured
4687 * @enabled_tc: TC bitmap
4688 * @bw_credits: BW shared credits per TC
4689 *
4690 * Returns 0 on success, negative value on failure
4691 **/
dcae29be 4692static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4693 u8 *bw_share)
4694{
4695 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4696 i40e_status ret;
dcae29be 4697 int i;
41c445ff
JB		 4698
4699 bw_data.tc_valid_bits = enabled_tc;
4700 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4701 bw_data.tc_bw_credits[i] = bw_share[i];
4702
f1c7e72e
SN		 4703 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4704 NULL);
4705 if (ret) {
41c445ff 4706 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4707 "AQ command Config VSI BW allocation per TC failed = %d\n",
4708 vsi->back->hw.aq.asq_last_status);
dcae29be 4709 return -EINVAL;
41c445ff
JB		 4710 }
4711
4712 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4713 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4714
dcae29be 4715 return 0;
41c445ff
JB		 4716}
4717
4718/**
4719 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4720 * @vsi: the VSI being configured
4721 * @enabled_tc: TC map to be enabled
4722 *
4723 **/
4724static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4725{
4726 struct net_device *netdev = vsi->netdev;
4727 struct i40e_pf *pf = vsi->back;
4728 struct i40e_hw *hw = &pf->hw;
4729 u8 netdev_tc = 0;
4730 int i;
4731 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4732
4733 if (!netdev)
4734 return;
4735
4736 if (!enabled_tc) {
4737 netdev_reset_tc(netdev);
4738 return;
4739 }
4740
4741 /* Set up actual enabled TCs on the VSI */
4742 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4743 return;
4744
4745 /* set per TC queues for the VSI */
4746 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4747 /* Only set TC queues for enabled tcs
4748 *
4749 * e.g. For a VSI that has TC0 and TC3 enabled the
4750 * enabled_tc bitmap would be 0x00001001; the driver
4751 * will set the numtc for netdev as 2 that will be
4752 * referenced by the netdev layer as TC 0 and 1.
4753 */
75f5cea9 4754 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4755 netdev_set_tc_queue(netdev,
4756 vsi->tc_config.tc_info[i].netdev_tc,
4757 vsi->tc_config.tc_info[i].qcount,
4758 vsi->tc_config.tc_info[i].qoffset);
4759 }
4760
4761 /* Assign UP2TC map for the VSI */
4762 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4763 /* Get the actual TC# for the UP */
4764 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4765 /* Get the mapped netdev TC# for the UP */
4766 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4767 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4768 }
4769}
4770
4771/**
4772 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4773 * @vsi: the VSI being configured
4774 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4775 **/
4776static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4777 struct i40e_vsi_context *ctxt)
4778{
4779 /* copy just the sections touched not the entire info
4780 * since not all sections are valid as returned by
4781 * update vsi params
4782 */
4783 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4784 memcpy(&vsi->info.queue_mapping,
4785 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4786 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4787 sizeof(vsi->info.tc_mapping));
4788}
4789
4790/**
4791 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4792 * @vsi: VSI to be configured
4793 * @enabled_tc: TC bitmap
4794 *
4795 * This configures a particular VSI for TCs that are mapped to the
4796 * given TC bitmap. It uses default bandwidth share for TCs across
4797 * VSIs to configure TC for a particular VSI.
4798 *
4799 * NOTE:
4800 * It is expected that the VSI queues have been quisced before calling
4801 * this function.
4802 **/
4803static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4804{
4805 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4806 struct i40e_vsi_context ctxt;
4807 int ret = 0;
4808 int i;
4809
4810 /* Check if enabled_tc is same as existing or new TCs */
4811 if (vsi->tc_config.enabled_tc == enabled_tc)
4812 return ret;
4813
4814 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4815 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4816 if (enabled_tc & BIT(i))
41c445ff
JB		 4817 bw_share[i] = 1;
4818 }
4819
4820 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4821 if (ret) {
4822 dev_info(&vsi->back->pdev->dev,
4823 "Failed configuring TC map %d for VSI %d\n",
4824 enabled_tc, vsi->seid);
4825 goto out;
4826 }
4827
4828 /* Update Queue Pairs Mapping for currently enabled UPs */
4829 ctxt.seid = vsi->seid;
4830 ctxt.pf_num = vsi->back->hw.pf_id;
4831 ctxt.vf_num = 0;
4832 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4833 ctxt.info = vsi->info;
41c445ff
JB		 4834 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4835
e3219ce6
ASJ		 4836 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
4837 ctxt.info.valid_sections |=
4838 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
4839 ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
4840 }
4841
41c445ff
JB		 4842 /* Update the VSI after updating the VSI queue-mapping information */
4843 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4844 if (ret) {
4845 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4846 "Update vsi tc config failed, err %s aq_err %s\n",
4847 i40e_stat_str(&vsi->back->hw, ret),
4848 i40e_aq_str(&vsi->back->hw,
4849 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4850 goto out;
4851 }
4852 /* update the local VSI info with updated queue map */
4853 i40e_vsi_update_queue_map(vsi, &ctxt);
4854 vsi->info.valid_sections = 0;
4855
4856 /* Update current VSI BW information */
4857 ret = i40e_vsi_get_bw_info(vsi);
4858 if (ret) {
4859 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4860 "Failed updating vsi bw info, err %s aq_err %s\n",
4861 i40e_stat_str(&vsi->back->hw, ret),
4862 i40e_aq_str(&vsi->back->hw,
4863 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4864 goto out;
4865 }
4866
4867 /* Update the netdev TC setup */
4868 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4869out:
4870 return ret;
4871}
4872
4e3b35b0
NP		 4873/**
4874 * i40e_veb_config_tc - Configure TCs for given VEB
4875 * @veb: given VEB
4876 * @enabled_tc: TC bitmap
4877 *
4878 * Configures given TC bitmap for VEB (switching) element
4879 **/
4880int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4881{
4882 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4883 struct i40e_pf *pf = veb->pf;
4884 int ret = 0;
4885 int i;
4886
4887 /* No TCs or already enabled TCs just return */
4888 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4889 return ret;
4890
4891 bw_data.tc_valid_bits = enabled_tc;
4892 /* bw_data.absolute_credits is not set (relative) */
4893
4894 /* Enable ETS TCs with equal BW Share for now */
4895 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4896 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4897 bw_data.tc_bw_share_credits[i] = 1;
4898 }
4899
4900 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4901 &bw_data, NULL);
4902 if (ret) {
4903 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4904 "VEB bw config failed, err %s aq_err %s\n",
4905 i40e_stat_str(&pf->hw, ret),
4906 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4907 goto out;
4908 }
4909
4910 /* Update the BW information */
4911 ret = i40e_veb_get_bw_info(veb);
4912 if (ret) {
4913 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4914 "Failed getting veb bw config, err %s aq_err %s\n",
4915 i40e_stat_str(&pf->hw, ret),
4916 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4917 }
4918
4919out:
4920 return ret;
4921}
4922
4923#ifdef CONFIG_I40E_DCB
4924/**
4925 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4926 * @pf: PF struct
4927 *
4928 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4929 * the caller would've quiesce all the VSIs before calling
4930 * this function
4931 **/
4932static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4933{
4934 u8 tc_map = 0;
4935 int ret;
4936 u8 v;
4937
4938 /* Enable the TCs available on PF to all VEBs */
4939 tc_map = i40e_pf_get_tc_map(pf);
4940 for (v = 0; v < I40E_MAX_VEB; v++) {
4941 if (!pf->veb[v])
4942 continue;
4943 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4944 if (ret) {
4945 dev_info(&pf->pdev->dev,
4946 "Failed configuring TC for VEB seid=%d\n",
4947 pf->veb[v]->seid);
4948 /* Will try to configure as many components */
4949 }
4950 }
4951
4952 /* Update each VSI */
505682cd 4953 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4954 if (!pf->vsi[v])
4955 continue;
4956
4957 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4958#ifdef I40E_FCOE
4959 * - For FCoE VSI only enable the TC configured
4960 * as per the APP TLV
4961#endif
4e3b35b0
NP		 4962 * - For all others keep them at TC0 for now
4963 */
4964 if (v == pf->lan_vsi)
4965 tc_map = i40e_pf_get_tc_map(pf);
4966 else
4967 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4968#ifdef I40E_FCOE
4969 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4970 tc_map = i40e_get_fcoe_tc_map(pf);
4971#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4972
4973 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4974 if (ret) {
4975 dev_info(&pf->pdev->dev,
4976 "Failed configuring TC for VSI seid=%d\n",
4977 pf->vsi[v]->seid);
4978 /* Will try to configure as many components */
4979 } else {
0672a091
NP		 4980 /* Re-configure VSI vectors based on updated TC map */
4981 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4982 if (pf->vsi[v]->netdev)
4983 i40e_dcbnl_set_all(pf->vsi[v]);
4984 }
e3219ce6 4985 i40e_notify_client_of_l2_param_changes(pf->vsi[v]);
4e3b35b0
NP		 4986 }
4987}
4988
2fd75f31
NP		 4989/**
4990 * i40e_resume_port_tx - Resume port Tx
4991 * @pf: PF struct
4992 *
4993 * Resume a port's Tx and issue a PF reset in case of failure to
4994 * resume.
4995 **/
4996static int i40e_resume_port_tx(struct i40e_pf *pf)
4997{
4998 struct i40e_hw *hw = &pf->hw;
4999 int ret;
5000
5001 ret = i40e_aq_resume_port_tx(hw, NULL);
5002 if (ret) {
5003 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5004 "Resume Port Tx failed, err %s aq_err %s\n",
5005 i40e_stat_str(&pf->hw, ret),
5006 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 5007 /* Schedule PF reset to recover */
5008 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5009 i40e_service_event_schedule(pf);
5010 }
5011
5012 return ret;
5013}
5014
4e3b35b0
NP		 5015/**
5016 * i40e_init_pf_dcb - Initialize DCB configuration
5017 * @pf: PF being configured
5018 *
5019 * Query the current DCB configuration and cache it
5020 * in the hardware structure
5021 **/
5022static int i40e_init_pf_dcb(struct i40e_pf *pf)
5023{
5024 struct i40e_hw *hw = &pf->hw;
5025 int err = 0;
5026
025b4a54 5027 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
f1bbad33 5028 if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT)
025b4a54
ASJ		 5029 goto out;
5030
4e3b35b0
NP		 5031 /* Get the initial DCB configuration */
5032 err = i40e_init_dcb(hw);
5033 if (!err) {
5034 /* Device/Function is not DCBX capable */
5035 if ((!hw->func_caps.dcb) ||
5036 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5037 dev_info(&pf->pdev->dev,
5038 "DCBX offload is not supported or is disabled for this PF.\n");
5039
5040 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5041 goto out;
5042
5043 } else {
5044 /* When status is not DISABLED then DCBX in FW */
5045 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5046 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5047
5048 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5049 /* Enable DCB tagging only when more than one TC */
5050 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5051 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5052 dev_dbg(&pf->pdev->dev,
5053 "DCBX offload is supported for this PF.\n");
4e3b35b0 5054 }
014269ff 5055 } else {
aebfc816 5056 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5057 "Query for DCB configuration failed, err %s aq_err %s\n",
5058 i40e_stat_str(&pf->hw, err),
5059 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5060 }
5061
5062out:
5063 return err;
5064}
5065#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5066#define SPEED_SIZE 14
5067#define FC_SIZE 8
5068/**
5069 * i40e_print_link_message - print link up or down
5070 * @vsi: the VSI for which link needs a message
5071 */
c156f856 5072void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5073{
a9165490
SN		 5074 char *speed = "Unknown";
5075 char *fc = "Unknown";
cf05ed08 5076
c156f856
MJ		 5077 if (vsi->current_isup == isup)
5078 return;
5079 vsi->current_isup = isup;
cf05ed08
JB		 5080 if (!isup) {
5081 netdev_info(vsi->netdev, "NIC Link is Down\n");
5082 return;
5083 }
5084
148c2d80
GR		 5085 /* Warn user if link speed on NPAR enabled partition is not at
5086 * least 10GB
5087 */
5088 if (vsi->back->hw.func_caps.npar_enable &&
5089 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5090 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5091 netdev_warn(vsi->netdev,
5092 "The partition detected link speed that is less than 10Gbps\n");
5093
cf05ed08
JB		 5094 switch (vsi->back->hw.phy.link_info.link_speed) {
5095 case I40E_LINK_SPEED_40GB:
a9165490 5096 speed = "40 G";
cf05ed08 5097 break;
ae24b409 5098 case I40E_LINK_SPEED_20GB:
a9165490 5099 speed = "20 G";
ae24b409 5100 break;
cf05ed08 5101 case I40E_LINK_SPEED_10GB:
a9165490 5102 speed = "10 G";
cf05ed08
JB		 5103 break;
5104 case I40E_LINK_SPEED_1GB:
a9165490 5105 speed = "1000 M";
cf05ed08 5106 break;
5960d33f 5107 case I40E_LINK_SPEED_100MB:
a9165490 5108 speed = "100 M";
5960d33f 5109 break;
cf05ed08
JB		 5110 default:
5111 break;
5112 }
5113
5114 switch (vsi->back->hw.fc.current_mode) {
5115 case I40E_FC_FULL:
a9165490 5116 fc = "RX/TX";
cf05ed08
JB		 5117 break;
5118 case I40E_FC_TX_PAUSE:
a9165490 5119 fc = "TX";
cf05ed08
JB		 5120 break;
5121 case I40E_FC_RX_PAUSE:
a9165490 5122 fc = "RX";
cf05ed08
JB		 5123 break;
5124 default:
a9165490 5125 fc = "None";
cf05ed08
JB		 5126 break;
5127 }
5128
a9165490 5129 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5130 speed, fc);
5131}
4e3b35b0 5132
41c445ff
JB		 5133/**
5134 * i40e_up_complete - Finish the last steps of bringing up a connection
5135 * @vsi: the VSI being configured
5136 **/
5137static int i40e_up_complete(struct i40e_vsi *vsi)
5138{
5139 struct i40e_pf *pf = vsi->back;
5140 int err;
5141
5142 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5143 i40e_vsi_configure_msix(vsi);
5144 else
5145 i40e_configure_msi_and_legacy(vsi);
5146
5147 /* start rings */
5148 err = i40e_vsi_control_rings(vsi, true);
5149 if (err)
5150 return err;
5151
5152 clear_bit(__I40E_DOWN, &vsi->state);
5153 i40e_napi_enable_all(vsi);
5154 i40e_vsi_enable_irq(vsi);
5155
5156 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5157 (vsi->netdev)) {
cf05ed08 5158 i40e_print_link_message(vsi, true);
41c445ff
JB		 5159 netif_tx_start_all_queues(vsi->netdev);
5160 netif_carrier_on(vsi->netdev);
6d779b41 5161 } else if (vsi->netdev) {
cf05ed08 5162 i40e_print_link_message(vsi, false);
7b592f61
CW		 5163 /* need to check for qualified module here*/
5164 if ((pf->hw.phy.link_info.link_info &
5165 I40E_AQ_MEDIA_AVAILABLE) &&
5166 (!(pf->hw.phy.link_info.an_info &
5167 I40E_AQ_QUALIFIED_MODULE)))
5168 netdev_err(vsi->netdev,
5169 "the driver failed to link because an unqualified module was detected.");
41c445ff 5170 }
ca64fa4e
ASJ		 5171
5172 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5173 if (vsi->type == I40E_VSI_FDIR) {
5174 /* reset fd counters */
5175 pf->fd_add_err = pf->fd_atr_cnt = 0;
5176 if (pf->fd_tcp_rule > 0) {
5177 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5178 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5179 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5180 pf->fd_tcp_rule = 0;
5181 }
ca64fa4e 5182 i40e_fdir_filter_restore(vsi);
1e1be8f6 5183 }
e3219ce6
ASJ		 5184
5185 /* On the next run of the service_task, notify any clients of the new
5186 * opened netdev
5187 */
5188 pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED;
41c445ff
JB		 5189 i40e_service_event_schedule(pf);
5190
5191 return 0;
5192}
5193
5194/**
5195 * i40e_vsi_reinit_locked - Reset the VSI
5196 * @vsi: the VSI being configured
5197 *
5198 * Rebuild the ring structs after some configuration
5199 * has changed, e.g. MTU size.
5200 **/
5201static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5202{
5203 struct i40e_pf *pf = vsi->back;
5204
5205 WARN_ON(in_interrupt());
5206 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5207 usleep_range(1000, 2000);
5208 i40e_down(vsi);
5209
41c445ff
JB		 5210 i40e_up(vsi);
5211 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5212}
5213
5214/**
5215 * i40e_up - Bring the connection back up after being down
5216 * @vsi: the VSI being configured
5217 **/
5218int i40e_up(struct i40e_vsi *vsi)
5219{
5220 int err;
5221
5222 err = i40e_vsi_configure(vsi);
5223 if (!err)
5224 err = i40e_up_complete(vsi);
5225
5226 return err;
5227}
5228
5229/**
5230 * i40e_down - Shutdown the connection processing
5231 * @vsi: the VSI being stopped
5232 **/
5233void i40e_down(struct i40e_vsi *vsi)
5234{
5235 int i;
5236
5237 /* It is assumed that the caller of this function
5238 * sets the vsi->state __I40E_DOWN bit.
5239 */
5240 if (vsi->netdev) {
5241 netif_carrier_off(vsi->netdev);
5242 netif_tx_disable(vsi->netdev);
5243 }
5244 i40e_vsi_disable_irq(vsi);
5245 i40e_vsi_control_rings(vsi, false);
5246 i40e_napi_disable_all(vsi);
5247
5248 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5249 i40e_clean_tx_ring(vsi->tx_rings[i]);
5250 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff 5251 }
f980d445
CS		 5252
5253 i40e_notify_client_of_netdev_close(vsi, false);
5254
41c445ff
JB		 5255}
5256
5257/**
5258 * i40e_setup_tc - configure multiple traffic classes
5259 * @netdev: net device to configure
5260 * @tc: number of traffic classes to enable
5261 **/
5262static int i40e_setup_tc(struct net_device *netdev, u8 tc)
5263{
5264 struct i40e_netdev_priv *np = netdev_priv(netdev);
5265 struct i40e_vsi *vsi = np->vsi;
5266 struct i40e_pf *pf = vsi->back;
5267 u8 enabled_tc = 0;
5268 int ret = -EINVAL;
5269 int i;
5270
5271 /* Check if DCB enabled to continue */
5272 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5273 netdev_info(netdev, "DCB is not enabled for adapter\n");
5274 goto exit;
5275 }
5276
5277 /* Check if MFP enabled */
5278 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5279 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5280 goto exit;
5281 }
5282
5283 /* Check whether tc count is within enabled limit */
5284 if (tc > i40e_pf_get_num_tc(pf)) {
5285 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5286 goto exit;
5287 }
5288
5289 /* Generate TC map for number of tc requested */
5290 for (i = 0; i < tc; i++)
75f5cea9 5291 enabled_tc |= BIT(i);
41c445ff
JB		 5292
5293 /* Requesting same TC configuration as already enabled */
5294 if (enabled_tc == vsi->tc_config.enabled_tc)
5295 return 0;
5296
5297 /* Quiesce VSI queues */
5298 i40e_quiesce_vsi(vsi);
5299
5300 /* Configure VSI for enabled TCs */
5301 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5302 if (ret) {
5303 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5304 vsi->seid);
5305 goto exit;
5306 }
5307
5308 /* Unquiesce VSI */
5309 i40e_unquiesce_vsi(vsi);
5310
5311exit:
5312 return ret;
5313}
5314
e4c6734e 5315#ifdef I40E_FCOE
16e5cc64
JF		 5316int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5317 struct tc_to_netdev *tc)
e4c6734e 5318#else
16e5cc64
JF		 5319static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5320 struct tc_to_netdev *tc)
e4c6734e
JF		 5321#endif
5322{
16e5cc64 5323 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
e4c6734e 5324 return -EINVAL;
16e5cc64 5325 return i40e_setup_tc(netdev, tc->tc);
e4c6734e
JF		 5326}
5327
41c445ff
JB		 5328/**
5329 * i40e_open - Called when a network interface is made active
5330 * @netdev: network interface device structure
5331 *
5332 * The open entry point is called when a network interface is made
5333 * active by the system (IFF_UP). At this point all resources needed
5334 * for transmit and receive operations are allocated, the interrupt
5335 * handler is registered with the OS, the netdev watchdog subtask is
5336 * enabled, and the stack is notified that the interface is ready.
5337 *
5338 * Returns 0 on success, negative value on failure
5339 **/
38e00438 5340int i40e_open(struct net_device *netdev)
41c445ff
JB		 5341{
5342 struct i40e_netdev_priv *np = netdev_priv(netdev);
5343 struct i40e_vsi *vsi = np->vsi;
5344 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5345 int err;
5346
4eb3f768
SN		 5347 /* disallow open during test or if eeprom is broken */
5348 if (test_bit(__I40E_TESTING, &pf->state) ||
5349 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5350 return -EBUSY;
5351
5352 netif_carrier_off(netdev);
5353
6c167f58
EK		 5354 err = i40e_vsi_open(vsi);
5355 if (err)
5356 return err;
5357
059dab69
JB		 5358 /* configure global TSO hardware offload settings */
5359 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5360 TCP_FLAG_FIN) >> 16);
5361 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5362 TCP_FLAG_FIN |
5363 TCP_FLAG_CWR) >> 16);
5364 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5365
06a5f7f1 5366 udp_tunnel_get_rx_info(netdev);
e3219ce6
ASJ		 5367 i40e_notify_client_of_netdev_open(vsi);
5368
6c167f58
EK		 5369 return 0;
5370}
5371
5372/**
5373 * i40e_vsi_open -
5374 * @vsi: the VSI to open
5375 *
5376 * Finish initialization of the VSI.
5377 *
5378 * Returns 0 on success, negative value on failure
5379 **/
5380int i40e_vsi_open(struct i40e_vsi *vsi)
5381{
5382 struct i40e_pf *pf = vsi->back;
b294ac70 5383 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5384 int err;
5385
41c445ff
JB		 5386 /* allocate descriptors */
5387 err = i40e_vsi_setup_tx_resources(vsi);
5388 if (err)
5389 goto err_setup_tx;
5390 err = i40e_vsi_setup_rx_resources(vsi);
5391 if (err)
5392 goto err_setup_rx;
5393
5394 err = i40e_vsi_configure(vsi);
5395 if (err)
5396 goto err_setup_rx;
5397
c22e3c6c
SN		 5398 if (vsi->netdev) {
5399 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5400 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5401 err = i40e_vsi_request_irq(vsi, int_name);
5402 if (err)
5403 goto err_setup_rx;
41c445ff 5404
c22e3c6c
SN		 5405 /* Notify the stack of the actual queue counts. */
5406 err = netif_set_real_num_tx_queues(vsi->netdev,
5407 vsi->num_queue_pairs);
5408 if (err)
5409 goto err_set_queues;
25946ddb 5410
c22e3c6c
SN		 5411 err = netif_set_real_num_rx_queues(vsi->netdev,
5412 vsi->num_queue_pairs);
5413 if (err)
5414 goto err_set_queues;
8a9eb7d3
SN		 5415
5416 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5417 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5418 dev_driver_string(&pf->pdev->dev),
5419 dev_name(&pf->pdev->dev));
8a9eb7d3 5420 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5421
c22e3c6c 5422 } else {
ce9ccb17 5423 err = -EINVAL;
6c167f58
EK		 5424 goto err_setup_rx;
5425 }
25946ddb 5426
41c445ff
JB		 5427 err = i40e_up_complete(vsi);
5428 if (err)
5429 goto err_up_complete;
5430
41c445ff
JB		 5431 return 0;
5432
5433err_up_complete:
5434 i40e_down(vsi);
25946ddb 5435err_set_queues:
41c445ff
JB		 5436 i40e_vsi_free_irq(vsi);
5437err_setup_rx:
5438 i40e_vsi_free_rx_resources(vsi);
5439err_setup_tx:
5440 i40e_vsi_free_tx_resources(vsi);
5441 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5442 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5443
5444 return err;
5445}
5446
17a73f6b
JG		 5447/**
5448 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5449 * @pf: Pointer to PF
17a73f6b
JG		 5450 *
5451 * This function destroys the hlist where all the Flow Director
5452 * filters were saved.
5453 **/
5454static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5455{
5456 struct i40e_fdir_filter *filter;
5457 struct hlist_node *node2;
5458
5459 hlist_for_each_entry_safe(filter, node2,
5460 &pf->fdir_filter_list, fdir_node) {
5461 hlist_del(&filter->fdir_node);
5462 kfree(filter);
5463 }
5464 pf->fdir_pf_active_filters = 0;
5465}
5466
41c445ff
JB		 5467/**
5468 * i40e_close - Disables a network interface
5469 * @netdev: network interface device structure
5470 *
5471 * The close entry point is called when an interface is de-activated
5472 * by the OS. The hardware is still under the driver's control, but
5473 * this netdev interface is disabled.
5474 *
5475 * Returns 0, this is not allowed to fail
5476 **/
38e00438 5477int i40e_close(struct net_device *netdev)
41c445ff
JB		 5478{
5479 struct i40e_netdev_priv *np = netdev_priv(netdev);
5480 struct i40e_vsi *vsi = np->vsi;
5481
90ef8d47 5482 i40e_vsi_close(vsi);
41c445ff
JB		 5483
5484 return 0;
5485}
5486
5487/**
5488 * i40e_do_reset - Start a PF or Core Reset sequence
5489 * @pf: board private structure
5490 * @reset_flags: which reset is requested
5491 *
5492 * The essential difference in resets is that the PF Reset
5493 * doesn't clear the packet buffers, doesn't reset the PE
5494 * firmware, and doesn't bother the other PFs on the chip.
5495 **/
5496void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5497{
5498 u32 val;
5499
5500 WARN_ON(in_interrupt());
5501
263fc48f 5502
41c445ff 5503 /* do the biggest reset indicated */
41a1d04b 5504 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5505
5506 /* Request a Global Reset
5507 *
5508 * This will start the chip's countdown to the actual full
5509 * chip reset event, and a warning interrupt to be sent
5510 * to all PFs, including the requestor. Our handler
5511 * for the warning interrupt will deal with the shutdown
5512 * and recovery of the switch setup.
5513 */
69bfb110 5514 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5515 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5516 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5517 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5518
41a1d04b 5519 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5520
5521 /* Request a Core Reset
5522 *
5523 * Same as Global Reset, except does *not* include the MAC/PHY
5524 */
69bfb110 5525 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5526 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5527 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5528 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5529 i40e_flush(&pf->hw);
5530
41a1d04b 5531 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5532
5533 /* Request a PF Reset
5534 *
5535 * Resets only the PF-specific registers
5536 *
5537 * This goes directly to the tear-down and rebuild of
5538 * the switch, since we need to do all the recovery as
5539 * for the Core Reset.
5540 */
69bfb110 5541 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5542 i40e_handle_reset_warning(pf);
5543
41a1d04b 5544 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5545 int v;
5546
5547 /* Find the VSI(s) that requested a re-init */
5548 dev_info(&pf->pdev->dev,
5549 "VSI reinit requested\n");
505682cd 5550 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5551 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5552
41c445ff
JB		 5553 if (vsi != NULL &&
5554 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5555 i40e_vsi_reinit_locked(pf->vsi[v]);
5556 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5557 }
5558 }
41a1d04b 5559 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5560 int v;
5561
5562 /* Find the VSI(s) that needs to be brought down */
5563 dev_info(&pf->pdev->dev, "VSI down requested\n");
5564 for (v = 0; v < pf->num_alloc_vsi; v++) {
5565 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5566
b5d06f05
NP		 5567 if (vsi != NULL &&
5568 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5569 set_bit(__I40E_DOWN, &vsi->state);
5570 i40e_down(vsi);
5571 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5572 }
5573 }
41c445ff
JB		 5574 } else {
5575 dev_info(&pf->pdev->dev,
5576 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5577 }
5578}
5579
4e3b35b0
NP		 5580#ifdef CONFIG_I40E_DCB
5581/**
5582 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5583 * @pf: board private structure
5584 * @old_cfg: current DCB config
5585 * @new_cfg: new DCB config
5586 **/
5587bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5588 struct i40e_dcbx_config *old_cfg,
5589 struct i40e_dcbx_config *new_cfg)
5590{
5591 bool need_reconfig = false;
5592
5593 /* Check if ETS configuration has changed */
5594 if (memcmp(&new_cfg->etscfg,
5595 &old_cfg->etscfg,
5596 sizeof(new_cfg->etscfg))) {
5597 /* If Priority Table has changed reconfig is needed */
5598 if (memcmp(&new_cfg->etscfg.prioritytable,
5599 &old_cfg->etscfg.prioritytable,
5600 sizeof(new_cfg->etscfg.prioritytable))) {
5601 need_reconfig = true;
69bfb110 5602 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5603 }
5604
5605 if (memcmp(&new_cfg->etscfg.tcbwtable,
5606 &old_cfg->etscfg.tcbwtable,
5607 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5608 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5609
5610 if (memcmp(&new_cfg->etscfg.tsatable,
5611 &old_cfg->etscfg.tsatable,
5612 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5613 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5614 }
5615
5616 /* Check if PFC configuration has changed */
5617 if (memcmp(&new_cfg->pfc,
5618 &old_cfg->pfc,
5619 sizeof(new_cfg->pfc))) {
5620 need_reconfig = true;
69bfb110 5621 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5622 }
5623
5624 /* Check if APP Table has changed */
5625 if (memcmp(&new_cfg->app,
5626 &old_cfg->app,
3d9667a9 5627 sizeof(new_cfg->app))) {
4e3b35b0 5628 need_reconfig = true;
69bfb110 5629 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5630 }
4e3b35b0 5631
fb43201f 5632 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5633 return need_reconfig;
5634}
5635
5636/**
5637 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5638 * @pf: board private structure
5639 * @e: event info posted on ARQ
5640 **/
5641static int i40e_handle_lldp_event(struct i40e_pf *pf,
5642 struct i40e_arq_event_info *e)
5643{
5644 struct i40e_aqc_lldp_get_mib *mib =
5645 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5646 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5647 struct i40e_dcbx_config tmp_dcbx_cfg;
5648 bool need_reconfig = false;
5649 int ret = 0;
5650 u8 type;
5651
4d9b6043
NP		 5652 /* Not DCB capable or capability disabled */
5653 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5654 return ret;
5655
4e3b35b0
NP		 5656 /* Ignore if event is not for Nearest Bridge */
5657 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5658 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5659 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5660 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5661 return ret;
5662
5663 /* Check MIB Type and return if event for Remote MIB update */
5664 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5665 dev_dbg(&pf->pdev->dev,
fb43201f 5666 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5667 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5668 /* Update the remote cached instance and return */
5669 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5670 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5671 &hw->remote_dcbx_config);
5672 goto exit;
5673 }
5674
9fa61dd2 5675 /* Store the old configuration */
1a2f6248 5676 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5677
750fcbcf
NP		 5678 /* Reset the old DCBx configuration data */
5679 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5680 /* Get updated DCBX data from firmware */
5681 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5682 if (ret) {
f1c7e72e
SN		 5683 dev_info(&pf->pdev->dev,
5684 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5685 i40e_stat_str(&pf->hw, ret),
5686 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5687 goto exit;
5688 }
5689
5690 /* No change detected in DCBX configs */
750fcbcf
NP		 5691 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5692 sizeof(tmp_dcbx_cfg))) {
69bfb110 5693 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5694 goto exit;
5695 }
5696
750fcbcf
NP		 5697 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5698 &hw->local_dcbx_config);
4e3b35b0 5699
750fcbcf 5700 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5701
5702 if (!need_reconfig)
5703 goto exit;
5704
4d9b6043 5705 /* Enable DCB tagging only when more than one TC */
750fcbcf 5706 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5707 pf->flags |= I40E_FLAG_DCB_ENABLED;
5708 else
5709 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5710
69129dc3 5711 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5712 /* Reconfiguration needed quiesce all VSIs */
5713 i40e_pf_quiesce_all_vsi(pf);
5714
5715 /* Changes in configuration update VEB/VSI */
5716 i40e_dcb_reconfigure(pf);
5717
2fd75f31
NP		 5718 ret = i40e_resume_port_tx(pf);
5719
69129dc3 5720 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5721 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5722 if (ret)
5723 goto exit;
5724
3fe06f41
NP		 5725 /* Wait for the PF's queues to be disabled */
5726 ret = i40e_pf_wait_queues_disabled(pf);
11e47708
PN		 5727 if (ret) {
5728 /* Schedule PF reset to recover */
5729 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5730 i40e_service_event_schedule(pf);
5731 } else {
2fd75f31 5732 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5733 }
5734
4e3b35b0
NP		 5735exit:
5736 return ret;
5737}
5738#endif /* CONFIG_I40E_DCB */
5739
23326186
ASJ		 5740/**
5741 * i40e_do_reset_safe - Protected reset path for userland calls.
5742 * @pf: board private structure
5743 * @reset_flags: which reset is requested
5744 *
5745 **/
5746void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5747{
5748 rtnl_lock();
5749 i40e_do_reset(pf, reset_flags);
5750 rtnl_unlock();
5751}
5752
41c445ff
JB		 5753/**
5754 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5755 * @pf: board private structure
5756 * @e: event info posted on ARQ
5757 *
5758 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5759 * and VF queues
5760 **/
5761static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5762 struct i40e_arq_event_info *e)
5763{
5764 struct i40e_aqc_lan_overflow *data =
5765 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5766 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5767 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5768 struct i40e_hw *hw = &pf->hw;
5769 struct i40e_vf *vf;
5770 u16 vf_id;
5771
69bfb110
JB		 5772 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5773 queue, qtx_ctl);
41c445ff
JB		 5774
5775 /* Queue belongs to VF, find the VF and issue VF reset */
5776 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5777 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5778 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5779 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5780 vf_id -= hw->func_caps.vf_base_id;
5781 vf = &pf->vf[vf_id];
5782 i40e_vc_notify_vf_reset(vf);
5783 /* Allow VF to process pending reset notification */
5784 msleep(20);
5785 i40e_reset_vf(vf, false);
5786 }
5787}
5788
5789/**
5790 * i40e_service_event_complete - Finish up the service event
5791 * @pf: board private structure
5792 **/
5793static void i40e_service_event_complete(struct i40e_pf *pf)
5794{
b875f99b 5795 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5796
5797 /* flush memory to make sure state is correct before next watchog */
4e857c58 5798 smp_mb__before_atomic();
41c445ff
JB		 5799 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5800}
5801
55a5e60b 5802/**
12957388
ASJ		 5803 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5804 * @pf: board private structure
5805 **/
04294e38 5806u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5807{
04294e38 5808 u32 val, fcnt_prog;
12957388
ASJ		 5809
5810 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5811 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5812 return fcnt_prog;
5813}
5814
5815/**
04294e38 5816 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5817 * @pf: board private structure
5818 **/
04294e38 5819u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5820{
04294e38
ASJ		 5821 u32 val, fcnt_prog;
5822
55a5e60b
ASJ		 5823 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5824 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5825 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5826 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5827 return fcnt_prog;
5828}
1e1be8f6 5829
04294e38
ASJ		 5830/**
5831 * i40e_get_global_fd_count - Get total FD filters programmed on device
5832 * @pf: board private structure
5833 **/
5834u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5835{
5836 u32 val, fcnt_prog;
5837
5838 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5839 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5840 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5841 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5842 return fcnt_prog;
5843}
5844
55a5e60b
ASJ		 5845/**
5846 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5847 * @pf: board private structure
5848 **/
5849void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5850{
3487b6c3 5851 struct i40e_fdir_filter *filter;
55a5e60b 5852 u32 fcnt_prog, fcnt_avail;
3487b6c3 5853 struct hlist_node *node;
55a5e60b 5854
1e1be8f6
ASJ		 5855 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5856 return;
5857
55a5e60b
ASJ		 5858 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5859 * to re-enable
5860 */
04294e38 5861 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5862 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5863 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5864 (pf->fd_add_err == 0) ||
5865 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5866 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5867 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5868 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5869 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5870 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5871 }
5872 }
5873 /* Wait for some more space to be available to turn on ATR */
5874 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5875 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5876 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5877 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5878 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5879 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5880 }
5881 }
3487b6c3
CW		 5882
5883 /* if hw had a problem adding a filter, delete it */
5884 if (pf->fd_inv > 0) {
5885 hlist_for_each_entry_safe(filter, node,
5886 &pf->fdir_filter_list, fdir_node) {
5887 if (filter->fd_id == pf->fd_inv) {
5888 hlist_del(&filter->fdir_node);
5889 kfree(filter);
5890 pf->fdir_pf_active_filters--;
5891 }
5892 }
5893 }
55a5e60b
ASJ		 5894}
5895
1e1be8f6 5896#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5897#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5898/**
5899 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5900 * @pf: board private structure
5901 **/
5902static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5903{
04294e38 5904 unsigned long min_flush_time;
1e1be8f6 5905 int flush_wait_retry = 50;
04294e38
ASJ		 5906 bool disable_atr = false;
5907 int fd_room;
1e1be8f6
ASJ		 5908 int reg;
5909
1790ed0c
AA		 5910 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5911 return;
5912
a5fdaf34
JB		 5913 if (!time_after(jiffies, pf->fd_flush_timestamp +
5914 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5915 return;
04294e38 5916
a5fdaf34
JB		 5917 /* If the flush is happening too quick and we have mostly SB rules we
5918 * should not re-enable ATR for some time.
5919 */
5920 min_flush_time = pf->fd_flush_timestamp +
5921 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5922 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5923
5924 if (!(time_after(jiffies, min_flush_time)) &&
5925 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5926 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5927 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5928 disable_atr = true;
5929 }
5930
5931 pf->fd_flush_timestamp = jiffies;
5932 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5933 /* flush all filters */
5934 wr32(&pf->hw, I40E_PFQF_CTL_1,
5935 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5936 i40e_flush(&pf->hw);
5937 pf->fd_flush_cnt++;
5938 pf->fd_add_err = 0;
5939 do {
5940 /* Check FD flush status every 5-6msec */
5941 usleep_range(5000, 6000);
5942 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5943 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5944 break;
5945 } while (flush_wait_retry--);
5946 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5947 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5948 } else {
5949 /* replay sideband filters */
5950 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5951 if (!disable_atr)
5952 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5953 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5954 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5955 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6
ASJ		 5956 }
5957}
5958
5959/**
5960 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5961 * @pf: board private structure
5962 **/
04294e38 5963u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5964{
5965 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5966}
5967
5968/* We can see up to 256 filter programming desc in transit if the filters are
5969 * being applied really fast; before we see the first
5970 * filter miss error on Rx queue 0. Accumulating enough error messages before
5971 * reacting will make sure we don't cause flush too often.
5972 */
5973#define I40E_MAX_FD_PROGRAM_ERROR 256
5974
41c445ff
JB		 5975/**
5976 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5977 * @pf: board private structure
5978 **/
5979static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5980{
41c445ff 5981
41c445ff
JB		 5982 /* if interface is down do nothing */
5983 if (test_bit(__I40E_DOWN, &pf->state))
5984 return;
1e1be8f6 5985
1790ed0c
AA		 5986 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5987 return;
5988
04294e38 5989 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5990 i40e_fdir_flush_and_replay(pf);
5991
55a5e60b
ASJ		 5992 i40e_fdir_check_and_reenable(pf);
5993
41c445ff
JB		 5994}
5995
5996/**
5997 * i40e_vsi_link_event - notify VSI of a link event
5998 * @vsi: vsi to be notified
5999 * @link_up: link up or down
6000 **/
6001static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
6002{
32b5b811 6003 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 6004 return;
6005
6006 switch (vsi->type) {
6007 case I40E_VSI_MAIN:
38e00438
VD		 6008#ifdef I40E_FCOE
6009 case I40E_VSI_FCOE:
6010#endif
41c445ff
JB		 6011 if (!vsi->netdev || !vsi->netdev_registered)
6012 break;
6013
6014 if (link_up) {
6015 netif_carrier_on(vsi->netdev);
6016 netif_tx_wake_all_queues(vsi->netdev);
6017 } else {
6018 netif_carrier_off(vsi->netdev);
6019 netif_tx_stop_all_queues(vsi->netdev);
6020 }
6021 break;
6022
6023 case I40E_VSI_SRIOV:
41c445ff
JB		 6024 case I40E_VSI_VMDQ2:
6025 case I40E_VSI_CTRL:
e3219ce6 6026 case I40E_VSI_IWARP:
41c445ff
JB		 6027 case I40E_VSI_MIRROR:
6028 default:
6029 /* there is no notification for other VSIs */
6030 break;
6031 }
6032}
6033
6034/**
6035 * i40e_veb_link_event - notify elements on the veb of a link event
6036 * @veb: veb to be notified
6037 * @link_up: link up or down
6038 **/
6039static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6040{
6041 struct i40e_pf *pf;
6042 int i;
6043
6044 if (!veb || !veb->pf)
6045 return;
6046 pf = veb->pf;
6047
6048 /* depth first... */
6049 for (i = 0; i < I40E_MAX_VEB; i++)
6050 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6051 i40e_veb_link_event(pf->veb[i], link_up);
6052
6053 /* ... now the local VSIs */
505682cd 6054 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6055 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6056 i40e_vsi_link_event(pf->vsi[i], link_up);
6057}
6058
6059/**
6060 * i40e_link_event - Update netif_carrier status
6061 * @pf: board private structure
6062 **/
6063static void i40e_link_event(struct i40e_pf *pf)
6064{
320684cd 6065 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6066 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6067 i40e_status status;
6068 bool new_link, old_link;
41c445ff 6069
1f9610e4
CS		 6070 /* save off old link status information */
6071 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6072
1e701e09
JB		 6073 /* set this to force the get_link_status call to refresh state */
6074 pf->hw.phy.get_link_info = true;
6075
41c445ff 6076 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6077
6078 status = i40e_get_link_status(&pf->hw, &new_link);
6079 if (status) {
6080 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6081 status);
6082 return;
6083 }
6084
fef59ddf
CS		 6085 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6086 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6087
1e701e09 6088 if (new_link == old_link &&
fef59ddf 6089 new_link_speed == old_link_speed &&
320684cd
MW		 6090 (test_bit(__I40E_DOWN, &vsi->state) ||
6091 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6092 return;
320684cd
MW		 6093
6094 if (!test_bit(__I40E_DOWN, &vsi->state))
6095 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6096
6097 /* Notify the base of the switch tree connected to
6098 * the link. Floating VEBs are not notified.
6099 */
6100 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6101 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6102 else
320684cd 6103 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6104
6105 if (pf->vf)
6106 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6107
6108 if (pf->flags & I40E_FLAG_PTP)
6109 i40e_ptp_set_increment(pf);
41c445ff
JB		 6110}
6111
41c445ff 6112/**
21536717 6113 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6114 * @pf: board private structure
6115 **/
6116static void i40e_watchdog_subtask(struct i40e_pf *pf)
6117{
6118 int i;
6119
6120 /* if interface is down do nothing */
6121 if (test_bit(__I40E_DOWN, &pf->state) ||
6122 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6123 return;
6124
21536717
SN		 6125 /* make sure we don't do these things too often */
6126 if (time_before(jiffies, (pf->service_timer_previous +
6127 pf->service_timer_period)))
6128 return;
6129 pf->service_timer_previous = jiffies;
6130
9ac77266
SN		 6131 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6132 i40e_link_event(pf);
21536717 6133
41c445ff
JB		 6134 /* Update the stats for active netdevs so the network stack
6135 * can look at updated numbers whenever it cares to
6136 */
505682cd 6137 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6138 if (pf->vsi[i] && pf->vsi[i]->netdev)
6139 i40e_update_stats(pf->vsi[i]);
6140
d1a8d275
ASJ		 6141 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6142 /* Update the stats for the active switching components */
6143 for (i = 0; i < I40E_MAX_VEB; i++)
6144 if (pf->veb[i])
6145 i40e_update_veb_stats(pf->veb[i]);
6146 }
beb0dff1
JK		 6147
6148 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6149}
6150
6151/**
6152 * i40e_reset_subtask - Set up for resetting the device and driver
6153 * @pf: board private structure
6154 **/
6155static void i40e_reset_subtask(struct i40e_pf *pf)
6156{
6157 u32 reset_flags = 0;
6158
23326186 6159 rtnl_lock();
41c445ff 6160 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6161 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6162 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6163 }
6164 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6165 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6166 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6167 }
6168 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6169 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6170 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6171 }
6172 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6173 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6174 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6175 }
b5d06f05 6176 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6177 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6178 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6179 }
41c445ff
JB		 6180
6181 /* If there's a recovery already waiting, it takes
6182 * precedence before starting a new reset sequence.
6183 */
6184 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6185 i40e_handle_reset_warning(pf);
23326186 6186 goto unlock;
41c445ff
JB		 6187 }
6188
6189 /* If we're already down or resetting, just bail */
6190 if (reset_flags &&
6191 !test_bit(__I40E_DOWN, &pf->state) &&
6192 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6193 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6194
6195unlock:
6196 rtnl_unlock();
41c445ff
JB		 6197}
6198
6199/**
6200 * i40e_handle_link_event - Handle link event
6201 * @pf: board private structure
6202 * @e: event info posted on ARQ
6203 **/
6204static void i40e_handle_link_event(struct i40e_pf *pf,
6205 struct i40e_arq_event_info *e)
6206{
41c445ff
JB		 6207 struct i40e_aqc_get_link_status *status =
6208 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6209
1e701e09
JB		 6210 /* Do a new status request to re-enable LSE reporting
6211 * and load new status information into the hw struct
6212 * This completely ignores any state information
6213 * in the ARQ event info, instead choosing to always
6214 * issue the AQ update link status command.
6215 */
6216 i40e_link_event(pf);
6217
7b592f61
CW		 6218 /* check for unqualified module, if link is down */
6219 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6220 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6221 (!(status->link_info & I40E_AQ_LINK_UP)))
6222 dev_err(&pf->pdev->dev,
6223 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6224}
6225
6226/**
6227 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6228 * @pf: board private structure
6229 **/
6230static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6231{
6232 struct i40e_arq_event_info event;
6233 struct i40e_hw *hw = &pf->hw;
6234 u16 pending, i = 0;
6235 i40e_status ret;
6236 u16 opcode;
86df242b 6237 u32 oldval;
41c445ff
JB		 6238 u32 val;
6239
a316f651
ASJ		 6240 /* Do not run clean AQ when PF reset fails */
6241 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6242 return;
6243
86df242b
SN		 6244 /* check for error indications */
6245 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6246 oldval = val;
6247 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6248 if (hw->debug_mask & I40E_DEBUG_AQ)
6249 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6250 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6251 }
6252 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6253 if (hw->debug_mask & I40E_DEBUG_AQ)
6254 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b 6255 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
1d0a4ada 6256 pf->arq_overflows++;
86df242b
SN		 6257 }
6258 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6259 if (hw->debug_mask & I40E_DEBUG_AQ)
6260 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6261 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6262 }
6263 if (oldval != val)
6264 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6265
6266 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6267 oldval = val;
6268 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6269 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6270 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6271 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6272 }
6273 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6274 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6275 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6276 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6277 }
6278 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6279 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6280 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6281 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6282 }
6283 if (oldval != val)
6284 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6285
1001dc37
MW		 6286 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6287 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6288 if (!event.msg_buf)
6289 return;
6290
6291 do {
6292 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6293 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6294 break;
56497978 6295 else if (ret) {
41c445ff
JB		 6296 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6297 break;
6298 }
6299
6300 opcode = le16_to_cpu(event.desc.opcode);
6301 switch (opcode) {
6302
6303 case i40e_aqc_opc_get_link_status:
6304 i40e_handle_link_event(pf, &event);
6305 break;
6306 case i40e_aqc_opc_send_msg_to_pf:
6307 ret = i40e_vc_process_vf_msg(pf,
6308 le16_to_cpu(event.desc.retval),
6309 le32_to_cpu(event.desc.cookie_high),
6310 le32_to_cpu(event.desc.cookie_low),
6311 event.msg_buf,
1001dc37 6312 event.msg_len);
41c445ff
JB		 6313 break;
6314 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6315 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6316#ifdef CONFIG_I40E_DCB
6317 rtnl_lock();
6318 ret = i40e_handle_lldp_event(pf, &event);
6319 rtnl_unlock();
6320#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6321 break;
6322 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6323 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6324 i40e_handle_lan_overflow_event(pf, &event);
6325 break;
0467bc91
SN		 6326 case i40e_aqc_opc_send_msg_to_peer:
6327 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6328 break;
91a0f930
SN		 6329 case i40e_aqc_opc_nvm_erase:
6330 case i40e_aqc_opc_nvm_update:
00ada50d 6331 case i40e_aqc_opc_oem_post_update:
6e93d0c9
SN		 6332 i40e_debug(&pf->hw, I40E_DEBUG_NVM,
6333 "ARQ NVM operation 0x%04x completed\n",
6334 opcode);
91a0f930 6335 break;
41c445ff
JB		 6336 default:
6337 dev_info(&pf->pdev->dev,
56e5ca68 6338 "ARQ: Unknown event 0x%04x ignored\n",
0467bc91 6339 opcode);
41c445ff
JB		 6340 break;
6341 }
6342 } while (pending && (i++ < pf->adminq_work_limit));
6343
6344 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6345 /* re-enable Admin queue interrupt cause */
6346 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6347 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6348 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6349 i40e_flush(hw);
6350
6351 kfree(event.msg_buf);
6352}
6353
4eb3f768
SN		 6354/**
6355 * i40e_verify_eeprom - make sure eeprom is good to use
6356 * @pf: board private structure
6357 **/
6358static void i40e_verify_eeprom(struct i40e_pf *pf)
6359{
6360 int err;
6361
6362 err = i40e_diag_eeprom_test(&pf->hw);
6363 if (err) {
6364 /* retry in case of garbage read */
6365 err = i40e_diag_eeprom_test(&pf->hw);
6366 if (err) {
6367 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6368 err);
6369 set_bit(__I40E_BAD_EEPROM, &pf->state);
6370 }
6371 }
6372
6373 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6374 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6375 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6376 }
6377}
6378
386a0afa
AA		 6379/**
6380 * i40e_enable_pf_switch_lb
b40c82e6 6381 * @pf: pointer to the PF structure
386a0afa
AA		 6382 *
6383 * enable switch loop back or die - no point in a return value
6384 **/
6385static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6386{
6387 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6388 struct i40e_vsi_context ctxt;
f1c7e72e 6389 int ret;
386a0afa
AA		 6390
6391 ctxt.seid = pf->main_vsi_seid;
6392 ctxt.pf_num = pf->hw.pf_id;
6393 ctxt.vf_num = 0;
f1c7e72e
SN		 6394 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6395 if (ret) {
386a0afa 6396 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6397 "couldn't get PF vsi config, err %s aq_err %s\n",
6398 i40e_stat_str(&pf->hw, ret),
6399 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6400 return;
6401 }
6402 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6403 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6404 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6405
f1c7e72e
SN		 6406 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6407 if (ret) {
386a0afa 6408 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6409 "update vsi switch failed, err %s aq_err %s\n",
6410 i40e_stat_str(&pf->hw, ret),
6411 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6412 }
6413}
6414
6415/**
6416 * i40e_disable_pf_switch_lb
b40c82e6 6417 * @pf: pointer to the PF structure
386a0afa
AA		 6418 *
6419 * disable switch loop back or die - no point in a return value
6420 **/
6421static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6422{
6423 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6424 struct i40e_vsi_context ctxt;
f1c7e72e 6425 int ret;
386a0afa
AA		 6426
6427 ctxt.seid = pf->main_vsi_seid;
6428 ctxt.pf_num = pf->hw.pf_id;
6429 ctxt.vf_num = 0;
f1c7e72e
SN		 6430 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6431 if (ret) {
386a0afa 6432 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6433 "couldn't get PF vsi config, err %s aq_err %s\n",
6434 i40e_stat_str(&pf->hw, ret),
6435 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6436 return;
6437 }
6438 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6439 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6440 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6441
f1c7e72e
SN		 6442 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6443 if (ret) {
386a0afa 6444 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6445 "update vsi switch failed, err %s aq_err %s\n",
6446 i40e_stat_str(&pf->hw, ret),
6447 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6448 }
6449}
6450
51616018
NP		 6451/**
6452 * i40e_config_bridge_mode - Configure the HW bridge mode
6453 * @veb: pointer to the bridge instance
6454 *
6455 * Configure the loop back mode for the LAN VSI that is downlink to the
6456 * specified HW bridge instance. It is expected this function is called
6457 * when a new HW bridge is instantiated.
6458 **/
6459static void i40e_config_bridge_mode(struct i40e_veb *veb)
6460{
6461 struct i40e_pf *pf = veb->pf;
6462
6dec1017
SN		 6463 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6464 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6465 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6466 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6467 i40e_disable_pf_switch_lb(pf);
6468 else
6469 i40e_enable_pf_switch_lb(pf);
6470}
6471
41c445ff
JB		 6472/**
6473 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6474 * @veb: pointer to the VEB instance
6475 *
6476 * This is a recursive function that first builds the attached VSIs then
6477 * recurses in to build the next layer of VEB. We track the connections
6478 * through our own index numbers because the seid's from the HW could
6479 * change across the reset.
6480 **/
6481static int i40e_reconstitute_veb(struct i40e_veb *veb)
6482{
6483 struct i40e_vsi *ctl_vsi = NULL;
6484 struct i40e_pf *pf = veb->pf;
6485 int v, veb_idx;
6486 int ret;
6487
6488 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6489 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6490 if (pf->vsi[v] &&
6491 pf->vsi[v]->veb_idx == veb->idx &&
6492 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6493 ctl_vsi = pf->vsi[v];
6494 break;
6495 }
6496 }
6497 if (!ctl_vsi) {
6498 dev_info(&pf->pdev->dev,
6499 "missing owner VSI for veb_idx %d\n", veb->idx);
6500 ret = -ENOENT;
6501 goto end_reconstitute;
6502 }
6503 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6504 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6505 ret = i40e_add_vsi(ctl_vsi);
6506 if (ret) {
6507 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6508 "rebuild of veb_idx %d owner VSI failed: %d\n",
6509 veb->idx, ret);
41c445ff
JB		 6510 goto end_reconstitute;
6511 }
6512 i40e_vsi_reset_stats(ctl_vsi);
6513
6514 /* create the VEB in the switch and move the VSI onto the VEB */
6515 ret = i40e_add_veb(veb, ctl_vsi);
6516 if (ret)
6517 goto end_reconstitute;
6518
fc60861e
ASJ		 6519 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6520 veb->bridge_mode = BRIDGE_MODE_VEB;
6521 else
6522 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6523 i40e_config_bridge_mode(veb);
b64ba084 6524
41c445ff 6525 /* create the remaining VSIs attached to this VEB */
505682cd 6526 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6527 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6528 continue;
6529
6530 if (pf->vsi[v]->veb_idx == veb->idx) {
6531 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6532
41c445ff
JB		 6533 vsi->uplink_seid = veb->seid;
6534 ret = i40e_add_vsi(vsi);
6535 if (ret) {
6536 dev_info(&pf->pdev->dev,
6537 "rebuild of vsi_idx %d failed: %d\n",
6538 v, ret);
6539 goto end_reconstitute;
6540 }
6541 i40e_vsi_reset_stats(vsi);
6542 }
6543 }
6544
6545 /* create any VEBs attached to this VEB - RECURSION */
6546 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6547 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6548 pf->veb[veb_idx]->uplink_seid = veb->seid;
6549 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6550 if (ret)
6551 break;
6552 }
6553 }
6554
6555end_reconstitute:
6556 return ret;
6557}
6558
6559/**
6560 * i40e_get_capabilities - get info about the HW
6561 * @pf: the PF struct
6562 **/
6563static int i40e_get_capabilities(struct i40e_pf *pf)
6564{
6565 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6566 u16 data_size;
6567 int buf_len;
6568 int err;
6569
6570 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6571 do {
6572 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6573 if (!cap_buf)
6574 return -ENOMEM;
6575
6576 /* this loads the data into the hw struct for us */
6577 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6578 &data_size,
6579 i40e_aqc_opc_list_func_capabilities,
6580 NULL);
6581 /* data loaded, buffer no longer needed */
6582 kfree(cap_buf);
6583
6584 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6585 /* retry with a larger buffer */
6586 buf_len = data_size;
6587 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6588 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6589 "capability discovery failed, err %s aq_err %s\n",
6590 i40e_stat_str(&pf->hw, err),
6591 i40e_aq_str(&pf->hw,
6592 pf->hw.aq.asq_last_status));
41c445ff
JB		 6593 return -ENODEV;
6594 }
6595 } while (err);
6596
6597 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6598 dev_info(&pf->pdev->dev,
6599 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6600 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6601 pf->hw.func_caps.num_msix_vectors,
6602 pf->hw.func_caps.num_msix_vectors_vf,
6603 pf->hw.func_caps.fd_filters_guaranteed,
6604 pf->hw.func_caps.fd_filters_best_effort,
6605 pf->hw.func_caps.num_tx_qp,
6606 pf->hw.func_caps.num_vsis);
6607
7134f9ce
JB		 6608#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6609 + pf->hw.func_caps.num_vfs)
6610 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6611 dev_info(&pf->pdev->dev,
6612 "got num_vsis %d, setting num_vsis to %d\n",
6613 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6614 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6615 }
6616
41c445ff
JB		 6617 return 0;
6618}
6619
cbf61325
ASJ		 6620static int i40e_vsi_clear(struct i40e_vsi *vsi);
6621
41c445ff 6622/**
cbf61325 6623 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6624 * @pf: board private structure
6625 **/
cbf61325 6626static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6627{
6628 struct i40e_vsi *vsi;
8a9eb7d3 6629 int i;
41c445ff 6630
407e063c
JB		 6631 /* quick workaround for an NVM issue that leaves a critical register
6632 * uninitialized
6633 */
6634 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6635 static const u32 hkey[] = {
6636 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6637 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6638 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6639 0x95b3a76d};
6640
6641 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6642 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6643 }
6644
cbf61325 6645 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6646 return;
6647
cbf61325 6648 /* find existing VSI and see if it needs configuring */
41c445ff 6649 vsi = NULL;
505682cd 6650 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6651 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6652 vsi = pf->vsi[i];
cbf61325
ASJ		 6653 break;
6654 }
6655 }
6656
6657 /* create a new VSI if none exists */
41c445ff 6658 if (!vsi) {
cbf61325
ASJ		 6659 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6660 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6661 if (!vsi) {
6662 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6663 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6664 return;
41c445ff 6665 }
cbf61325 6666 }
41c445ff 6667
8a9eb7d3 6668 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6669}
6670
6671/**
6672 * i40e_fdir_teardown - release the Flow Director resources
6673 * @pf: board private structure
6674 **/
6675static void i40e_fdir_teardown(struct i40e_pf *pf)
6676{
6677 int i;
6678
17a73f6b 6679 i40e_fdir_filter_exit(pf);
505682cd 6680 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6681 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6682 i40e_vsi_release(pf->vsi[i]);
6683 break;
6684 }
6685 }
6686}
6687
6688/**
f650a38b 6689 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6690 * @pf: board private structure
6691 *
b40c82e6 6692 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6693 **/
23cfbe07 6694static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6695{
41c445ff 6696 struct i40e_hw *hw = &pf->hw;
60442dea 6697 i40e_status ret = 0;
41c445ff
JB		 6698 u32 v;
6699
6700 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6701 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6702 return;
d3ce5734
MW		 6703 if (i40e_check_asq_alive(&pf->hw))
6704 i40e_vc_notify_reset(pf);
41c445ff 6705
69bfb110 6706 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6707
41c445ff
JB		 6708 /* quiesce the VSIs and their queues that are not already DOWN */
6709 i40e_pf_quiesce_all_vsi(pf);
6710
505682cd 6711 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6712 if (pf->vsi[v])
6713 pf->vsi[v]->seid = 0;
6714 }
6715
6716 i40e_shutdown_adminq(&pf->hw);
6717
f650a38b 6718 /* call shutdown HMC */
60442dea
SN		 6719 if (hw->hmc.hmc_obj) {
6720 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6721 if (ret)
60442dea
SN		 6722 dev_warn(&pf->pdev->dev,
6723 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6724 }
f650a38b
ASJ		 6725}
6726
44033fac
JB		 6727/**
6728 * i40e_send_version - update firmware with driver version
6729 * @pf: PF struct
6730 */
6731static void i40e_send_version(struct i40e_pf *pf)
6732{
6733 struct i40e_driver_version dv;
6734
6735 dv.major_version = DRV_VERSION_MAJOR;
6736 dv.minor_version = DRV_VERSION_MINOR;
6737 dv.build_version = DRV_VERSION_BUILD;
6738 dv.subbuild_version = 0;
35a7d804 6739 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6740 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6741}
6742
f650a38b 6743/**
4dda12e6 6744 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6745 * @pf: board private structure
bc7d338f 6746 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6747 **/
bc7d338f 6748static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6749{
f650a38b 6750 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6751 u8 set_fc_aq_fail = 0;
f650a38b 6752 i40e_status ret;
4f2f017c 6753 u32 val;
f650a38b
ASJ		 6754 u32 v;
6755
41c445ff
JB		 6756 /* Now we wait for GRST to settle out.
6757 * We don't have to delete the VEBs or VSIs from the hw switch
6758 * because the reset will make them disappear.
6759 */
6760 ret = i40e_pf_reset(hw);
b5565400 6761 if (ret) {
41c445ff 6762 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6763 set_bit(__I40E_RESET_FAILED, &pf->state);
6764 goto clear_recovery;
b5565400 6765 }
41c445ff
JB		 6766 pf->pfr_count++;
6767
6768 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6769 goto clear_recovery;
69bfb110 6770 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6771
6772 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6773 ret = i40e_init_adminq(&pf->hw);
6774 if (ret) {
f1c7e72e
SN		 6775 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6776 i40e_stat_str(&pf->hw, ret),
6777 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6778 goto clear_recovery;
41c445ff
JB		 6779 }
6780
4eb3f768 6781 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6782 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6783 i40e_verify_eeprom(pf);
4eb3f768 6784
e78ac4bf 6785 i40e_clear_pxe_mode(hw);
41c445ff 6786 ret = i40e_get_capabilities(pf);
f1c7e72e 6787 if (ret)
41c445ff 6788 goto end_core_reset;
41c445ff 6789
41c445ff
JB		 6790 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6791 hw->func_caps.num_rx_qp,
6792 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6793 if (ret) {
6794 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6795 goto end_core_reset;
6796 }
6797 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6798 if (ret) {
6799 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6800 goto end_core_reset;
6801 }
6802
4e3b35b0
NP		 6803#ifdef CONFIG_I40E_DCB
6804 ret = i40e_init_pf_dcb(pf);
6805 if (ret) {
aebfc816
SN		 6806 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6807 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6808 /* Continue without DCB enabled */
4e3b35b0
NP		 6809 }
6810#endif /* CONFIG_I40E_DCB */
38e00438 6811#ifdef I40E_FCOE
21364bcf 6812 i40e_init_pf_fcoe(pf);
4e3b35b0 6813
38e00438 6814#endif
41c445ff 6815 /* do basic switch setup */
bc7d338f 6816 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6817 if (ret)
6818 goto end_core_reset;
6819
2f0aff41
SN		 6820 /* The driver only wants link up/down and module qualification
6821 * reports from firmware. Note the negative logic.
7e2453fe
JB		 6822 */
6823 ret = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 6824 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 6825 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 6826 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 6827 if (ret)
f1c7e72e
SN		 6828 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6829 i40e_stat_str(&pf->hw, ret),
6830 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6831
cafa2ee6
ASJ		 6832 /* make sure our flow control settings are restored */
6833 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6834 if (ret)
8279e495
NP		 6835 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6836 i40e_stat_str(&pf->hw, ret),
6837 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6838
41c445ff
JB		 6839 /* Rebuild the VSIs and VEBs that existed before reset.
6840 * They are still in our local switch element arrays, so only
6841 * need to rebuild the switch model in the HW.
6842 *
6843 * If there were VEBs but the reconstitution failed, we'll try
6844 * try to recover minimal use by getting the basic PF VSI working.
6845 */
6846 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6847 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6848 /* find the one VEB connected to the MAC, and find orphans */
6849 for (v = 0; v < I40E_MAX_VEB; v++) {
6850 if (!pf->veb[v])
6851 continue;
6852
6853 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6854 pf->veb[v]->uplink_seid == 0) {
6855 ret = i40e_reconstitute_veb(pf->veb[v]);
6856
6857 if (!ret)
6858 continue;
6859
6860 /* If Main VEB failed, we're in deep doodoo,
6861 * so give up rebuilding the switch and set up
6862 * for minimal rebuild of PF VSI.
6863 * If orphan failed, we'll report the error
6864 * but try to keep going.
6865 */
6866 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6867 dev_info(&pf->pdev->dev,
6868 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6869 ret);
6870 pf->vsi[pf->lan_vsi]->uplink_seid
6871 = pf->mac_seid;
6872 break;
6873 } else if (pf->veb[v]->uplink_seid == 0) {
6874 dev_info(&pf->pdev->dev,
6875 "rebuild of orphan VEB failed: %d\n",
6876 ret);
6877 }
6878 }
6879 }
6880 }
6881
6882 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6883 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6884 /* no VEB, so rebuild only the Main VSI */
6885 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6886 if (ret) {
6887 dev_info(&pf->pdev->dev,
6888 "rebuild of Main VSI failed: %d\n", ret);
6889 goto end_core_reset;
6890 }
6891 }
6892
4f2f017c
ASJ		 6893 /* Reconfigure hardware for allowing smaller MSS in the case
6894 * of TSO, so that we avoid the MDD being fired and causing
6895 * a reset in the case of small MSS+TSO.
6896 */
6897#define I40E_REG_MSS 0x000E64DC
6898#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6899#define I40E_64BYTE_MSS 0x400000
6900 val = rd32(hw, I40E_REG_MSS);
6901 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6902 val &= ~I40E_REG_MSS_MIN_MASK;
6903 val |= I40E_64BYTE_MSS;
6904 wr32(hw, I40E_REG_MSS, val);
6905 }
6906
8eed76fa 6907 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 6908 msleep(75);
6909 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6910 if (ret)
f1c7e72e
SN		 6911 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6912 i40e_stat_str(&pf->hw, ret),
6913 i40e_aq_str(&pf->hw,
6914 pf->hw.aq.asq_last_status));
cafa2ee6 6915 }
41c445ff
JB		 6916 /* reinit the misc interrupt */
6917 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6918 ret = i40e_setup_misc_vector(pf);
6919
e7358f54
ASJ		 6920 /* Add a filter to drop all Flow control frames from any VSI from being
6921 * transmitted. By doing so we stop a malicious VF from sending out
6922 * PAUSE or PFC frames and potentially controlling traffic for other
6923 * PF/VF VSIs.
6924 * The FW can still send Flow control frames if enabled.
6925 */
6926 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6927 pf->main_vsi_seid);
6928
41c445ff
JB		 6929 /* restart the VSIs that were rebuilt and running before the reset */
6930 i40e_pf_unquiesce_all_vsi(pf);
6931
69f64b2b
MW		 6932 if (pf->num_alloc_vfs) {
6933 for (v = 0; v < pf->num_alloc_vfs; v++)
6934 i40e_reset_vf(&pf->vf[v], true);
6935 }
6936
41c445ff 6937 /* tell the firmware that we're starting */
44033fac 6938 i40e_send_version(pf);
41c445ff
JB		 6939
6940end_core_reset:
a316f651
ASJ		 6941 clear_bit(__I40E_RESET_FAILED, &pf->state);
6942clear_recovery:
41c445ff
JB		 6943 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6944}
6945
f650a38b 6946/**
b40c82e6 6947 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6948 * @pf: board private structure
6949 *
6950 * Close up the VFs and other things in prep for a Core Reset,
6951 * then get ready to rebuild the world.
6952 **/
6953static void i40e_handle_reset_warning(struct i40e_pf *pf)
6954{
23cfbe07
SN		 6955 i40e_prep_for_reset(pf);
6956 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6957}
6958
41c445ff
JB		 6959/**
6960 * i40e_handle_mdd_event
b40c82e6 6961 * @pf: pointer to the PF structure
41c445ff
JB		 6962 *
6963 * Called from the MDD irq handler to identify possibly malicious vfs
6964 **/
6965static void i40e_handle_mdd_event(struct i40e_pf *pf)
6966{
6967 struct i40e_hw *hw = &pf->hw;
6968 bool mdd_detected = false;
df430b12 6969 bool pf_mdd_detected = false;
41c445ff
JB		 6970 struct i40e_vf *vf;
6971 u32 reg;
6972 int i;
6973
6974 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6975 return;
6976
6977 /* find what triggered the MDD event */
6978 reg = rd32(hw, I40E_GL_MDET_TX);
6979 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6980 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6981 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6982 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6983 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6984 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6985 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6986 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6987 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6988 pf->hw.func_caps.base_queue;
faf32978 6989 if (netif_msg_tx_err(pf))
b40c82e6 6990 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6991 event, queue, pf_num, vf_num);
41c445ff
JB		 6992 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6993 mdd_detected = true;
6994 }
6995 reg = rd32(hw, I40E_GL_MDET_RX);
6996 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6997 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6998 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6999 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 7000 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 7001 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
7002 I40E_GL_MDET_RX_QUEUE_SHIFT) -
7003 pf->hw.func_caps.base_queue;
faf32978
JB		 7004 if (netif_msg_rx_err(pf))
7005 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
7006 event, queue, func);
41c445ff
JB		 7007 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
7008 mdd_detected = true;
7009 }
7010
df430b12
NP		 7011 if (mdd_detected) {
7012 reg = rd32(hw, I40E_PF_MDET_TX);
7013 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
7014 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 7015 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 7016 pf_mdd_detected = true;
7017 }
7018 reg = rd32(hw, I40E_PF_MDET_RX);
7019 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
7020 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 7021 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 7022 pf_mdd_detected = true;
7023 }
7024 /* Queue belongs to the PF, initiate a reset */
7025 if (pf_mdd_detected) {
7026 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7027 i40e_service_event_schedule(pf);
7028 }
7029 }
7030
41c445ff
JB		 7031 /* see if one of the VFs needs its hand slapped */
7032 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7033 vf = &(pf->vf[i]);
7034 reg = rd32(hw, I40E_VP_MDET_TX(i));
7035 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7036 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7037 vf->num_mdd_events++;
faf32978
JB		 7038 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7039 i);
41c445ff
JB		 7040 }
7041
7042 reg = rd32(hw, I40E_VP_MDET_RX(i));
7043 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7044 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7045 vf->num_mdd_events++;
faf32978
JB		 7046 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7047 i);
41c445ff
JB		 7048 }
7049
7050 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7051 dev_info(&pf->pdev->dev,
7052 "Too many MDD events on VF %d, disabled\n", i);
7053 dev_info(&pf->pdev->dev,
7054 "Use PF Control I/F to re-enable the VF\n");
7055 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7056 }
7057 }
7058
7059 /* re-enable mdd interrupt cause */
7060 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7061 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7062 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7063 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7064 i40e_flush(hw);
7065}
7066
a1c9a9d9 7067/**
6a899024 7068 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7069 * @pf: board private structure
7070 **/
6a899024 7071static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7072{
a1c9a9d9
JK		 7073 struct i40e_hw *hw = &pf->hw;
7074 i40e_status ret;
a1c9a9d9
JK		 7075 __be16 port;
7076 int i;
7077
6a899024 7078 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7079 return;
7080
6a899024 7081 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7082
7083 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7084 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7085 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7086 port = pf->udp_ports[i].index;
c22c06c8
SN		 7087 if (port)
7088 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7089 pf->udp_ports[i].type,
c22c06c8
SN		 7090 NULL, NULL);
7091 else
7092 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7093
7094 if (ret) {
730a8f87
CW		 7095 dev_dbg(&pf->pdev->dev,
7096 "%s %s port %d, index %d failed, err %s aq_err %s\n",
7097 pf->udp_ports[i].type ? "vxlan" : "geneve",
7098 port ? "add" : "delete",
7099 ntohs(port), i,
7100 i40e_stat_str(&pf->hw, ret),
7101 i40e_aq_str(&pf->hw,
f1c7e72e 7102 pf->hw.aq.asq_last_status));
6a899024 7103 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7104 }
7105 }
7106 }
7107}
7108
41c445ff
JB		 7109/**
7110 * i40e_service_task - Run the driver's async subtasks
7111 * @work: pointer to work_struct containing our data
7112 **/
7113static void i40e_service_task(struct work_struct *work)
7114{
7115 struct i40e_pf *pf = container_of(work,
7116 struct i40e_pf,
7117 service_task);
7118 unsigned long start_time = jiffies;
7119
e57a2fea
SN		 7120 /* don't bother with service tasks if a reset is in progress */
7121 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7122 i40e_service_event_complete(pf);
7123 return;
7124 }
7125
b03a8c1f 7126 i40e_detect_recover_hung(pf);
2818ccd9 7127 i40e_sync_filters_subtask(pf);
41c445ff
JB		 7128 i40e_reset_subtask(pf);
7129 i40e_handle_mdd_event(pf);
7130 i40e_vc_process_vflr_event(pf);
7131 i40e_watchdog_subtask(pf);
7132 i40e_fdir_reinit_subtask(pf);
e3219ce6 7133 i40e_client_subtask(pf);
41c445ff 7134 i40e_sync_filters_subtask(pf);
6a899024 7135 i40e_sync_udp_filters_subtask(pf);
41c445ff
JB		 7136 i40e_clean_adminq_subtask(pf);
7137
7138 i40e_service_event_complete(pf);
7139
7140 /* If the tasks have taken longer than one timer cycle or there
7141 * is more work to be done, reschedule the service task now
7142 * rather than wait for the timer to tick again.
7143 */
7144 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7145 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7146 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7147 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7148 i40e_service_event_schedule(pf);
7149}
7150
7151/**
7152 * i40e_service_timer - timer callback
7153 * @data: pointer to PF struct
7154 **/
7155static void i40e_service_timer(unsigned long data)
7156{
7157 struct i40e_pf *pf = (struct i40e_pf *)data;
7158
7159 mod_timer(&pf->service_timer,
7160 round_jiffies(jiffies + pf->service_timer_period));
7161 i40e_service_event_schedule(pf);
7162}
7163
7164/**
7165 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7166 * @vsi: the VSI being configured
7167 **/
7168static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7169{
7170 struct i40e_pf *pf = vsi->back;
7171
7172 switch (vsi->type) {
7173 case I40E_VSI_MAIN:
7174 vsi->alloc_queue_pairs = pf->num_lan_qps;
7175 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7176 I40E_REQ_DESCRIPTOR_MULTIPLE);
7177 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7178 vsi->num_q_vectors = pf->num_lan_msix;
7179 else
7180 vsi->num_q_vectors = 1;
7181
7182 break;
7183
7184 case I40E_VSI_FDIR:
7185 vsi->alloc_queue_pairs = 1;
7186 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7187 I40E_REQ_DESCRIPTOR_MULTIPLE);
7188 vsi->num_q_vectors = 1;
7189 break;
7190
7191 case I40E_VSI_VMDQ2:
7192 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7193 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7194 I40E_REQ_DESCRIPTOR_MULTIPLE);
7195 vsi->num_q_vectors = pf->num_vmdq_msix;
7196 break;
7197
7198 case I40E_VSI_SRIOV:
7199 vsi->alloc_queue_pairs = pf->num_vf_qps;
7200 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7201 I40E_REQ_DESCRIPTOR_MULTIPLE);
7202 break;
7203
38e00438
VD		 7204#ifdef I40E_FCOE
7205 case I40E_VSI_FCOE:
7206 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7207 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7208 I40E_REQ_DESCRIPTOR_MULTIPLE);
7209 vsi->num_q_vectors = pf->num_fcoe_msix;
7210 break;
7211
7212#endif /* I40E_FCOE */
41c445ff
JB		 7213 default:
7214 WARN_ON(1);
7215 return -ENODATA;
7216 }
7217
7218 return 0;
7219}
7220
f650a38b
ASJ		 7221/**
7222 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7223 * @type: VSI pointer
bc7d338f 7224 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7225 *
7226 * On error: returns error code (negative)
7227 * On success: returns 0
7228 **/
bc7d338f 7229static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7230{
7231 int size;
7232 int ret = 0;
7233
ac6c5e3d 7234 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7235 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7236 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7237 if (!vsi->tx_rings)
7238 return -ENOMEM;
f650a38b
ASJ		 7239 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7240
bc7d338f
ASJ		 7241 if (alloc_qvectors) {
7242 /* allocate memory for q_vector pointers */
f57e4fbd 7243 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7244 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7245 if (!vsi->q_vectors) {
7246 ret = -ENOMEM;
7247 goto err_vectors;
7248 }
f650a38b
ASJ		 7249 }
7250 return ret;
7251
7252err_vectors:
7253 kfree(vsi->tx_rings);
7254 return ret;
7255}
7256
41c445ff
JB		 7257/**
7258 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7259 * @pf: board private structure
7260 * @type: type of VSI
7261 *
7262 * On error: returns error code (negative)
7263 * On success: returns vsi index in PF (positive)
7264 **/
7265static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7266{
7267 int ret = -ENODEV;
7268 struct i40e_vsi *vsi;
7269 int vsi_idx;
7270 int i;
7271
7272 /* Need to protect the allocation of the VSIs at the PF level */
7273 mutex_lock(&pf->switch_mutex);
7274
7275 /* VSI list may be fragmented if VSI creation/destruction has
7276 * been happening. We can afford to do a quick scan to look
7277 * for any free VSIs in the list.
7278 *
7279 * find next empty vsi slot, looping back around if necessary
7280 */
7281 i = pf->next_vsi;
505682cd 7282 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7283 i++;
505682cd 7284 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7285 i = 0;
7286 while (i < pf->next_vsi && pf->vsi[i])
7287 i++;
7288 }
7289
505682cd 7290 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7291 vsi_idx = i; /* Found one! */
7292 } else {
7293 ret = -ENODEV;
493fb300 7294 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7295 }
7296 pf->next_vsi = ++i;
7297
7298 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7299 if (!vsi) {
7300 ret = -ENOMEM;
493fb300 7301 goto unlock_pf;
41c445ff
JB		 7302 }
7303 vsi->type = type;
7304 vsi->back = pf;
7305 set_bit(__I40E_DOWN, &vsi->state);
7306 vsi->flags = 0;
7307 vsi->idx = vsi_idx;
ac26fc13 7308 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7309 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7310 pf->rss_table_size : 64;
41c445ff
JB		 7311 vsi->netdev_registered = false;
7312 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7313 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7314 vsi->irqs_ready = false;
41c445ff 7315
9f65e15b
AD		 7316 ret = i40e_set_num_rings_in_vsi(vsi);
7317 if (ret)
7318 goto err_rings;
7319
bc7d338f 7320 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7321 if (ret)
9f65e15b 7322 goto err_rings;
493fb300 7323
41c445ff
JB		 7324 /* Setup default MSIX irq handler for VSI */
7325 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7326
21659035
KP		 7327 /* Initialize VSI lock */
7328 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7329 pf->vsi[vsi_idx] = vsi;
7330 ret = vsi_idx;
493fb300
AD		 7331 goto unlock_pf;
7332
9f65e15b 7333err_rings:
493fb300
AD		 7334 pf->next_vsi = i - 1;
7335 kfree(vsi);
7336unlock_pf:
41c445ff
JB		 7337 mutex_unlock(&pf->switch_mutex);
7338 return ret;
7339}
7340
f650a38b
ASJ		 7341/**
7342 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7343 * @type: VSI pointer
bc7d338f 7344 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7345 *
7346 * On error: returns error code (negative)
7347 * On success: returns 0
7348 **/
bc7d338f 7349static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7350{
7351 /* free the ring and vector containers */
bc7d338f
ASJ		 7352 if (free_qvectors) {
7353 kfree(vsi->q_vectors);
7354 vsi->q_vectors = NULL;
7355 }
f650a38b
ASJ		 7356 kfree(vsi->tx_rings);
7357 vsi->tx_rings = NULL;
7358 vsi->rx_rings = NULL;
7359}
7360
28c5869f
HZ		 7361/**
7362 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7363 * and lookup table
7364 * @vsi: Pointer to VSI structure
7365 */
7366static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7367{
7368 if (!vsi)
7369 return;
7370
7371 kfree(vsi->rss_hkey_user);
7372 vsi->rss_hkey_user = NULL;
7373
7374 kfree(vsi->rss_lut_user);
7375 vsi->rss_lut_user = NULL;
7376}
7377
41c445ff
JB		 7378/**
7379 * i40e_vsi_clear - Deallocate the VSI provided
7380 * @vsi: the VSI being un-configured
7381 **/
7382static int i40e_vsi_clear(struct i40e_vsi *vsi)
7383{
7384 struct i40e_pf *pf;
7385
7386 if (!vsi)
7387 return 0;
7388
7389 if (!vsi->back)
7390 goto free_vsi;
7391 pf = vsi->back;
7392
7393 mutex_lock(&pf->switch_mutex);
7394 if (!pf->vsi[vsi->idx]) {
7395 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7396 vsi->idx, vsi->idx, vsi, vsi->type);
7397 goto unlock_vsi;
7398 }
7399
7400 if (pf->vsi[vsi->idx] != vsi) {
7401 dev_err(&pf->pdev->dev,
7402 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7403 pf->vsi[vsi->idx]->idx,
7404 pf->vsi[vsi->idx],
7405 pf->vsi[vsi->idx]->type,
7406 vsi->idx, vsi, vsi->type);
7407 goto unlock_vsi;
7408 }
7409
b40c82e6 7410 /* updates the PF for this cleared vsi */
41c445ff
JB		 7411 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7412 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7413
bc7d338f 7414 i40e_vsi_free_arrays(vsi, true);
28c5869f 7415 i40e_clear_rss_config_user(vsi);
493fb300 7416
41c445ff
JB		 7417 pf->vsi[vsi->idx] = NULL;
7418 if (vsi->idx < pf->next_vsi)
7419 pf->next_vsi = vsi->idx;
7420
7421unlock_vsi:
7422 mutex_unlock(&pf->switch_mutex);
7423free_vsi:
7424 kfree(vsi);
7425
7426 return 0;
7427}
7428
9f65e15b
AD		 7429/**
7430 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7431 * @vsi: the VSI being cleaned
7432 **/
be1d5eea 7433static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7434{
7435 int i;
7436
8e9dca53 7437 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7438 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7439 kfree_rcu(vsi->tx_rings[i], rcu);
7440 vsi->tx_rings[i] = NULL;
7441 vsi->rx_rings[i] = NULL;
7442 }
be1d5eea 7443 }
9f65e15b
AD		 7444}
7445
41c445ff
JB		 7446/**
7447 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7448 * @vsi: the VSI being configured
7449 **/
7450static int i40e_alloc_rings(struct i40e_vsi *vsi)
7451{
e7046ee1 7452 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7453 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7454 int i;
7455
41c445ff 7456 /* Set basic values in the rings to be used later during open() */
d7397644 7457 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7458 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7459 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7460 if (!tx_ring)
7461 goto err_out;
41c445ff
JB		 7462
7463 tx_ring->queue_index = i;
7464 tx_ring->reg_idx = vsi->base_queue + i;
7465 tx_ring->ring_active = false;
7466 tx_ring->vsi = vsi;
7467 tx_ring->netdev = vsi->netdev;
7468 tx_ring->dev = &pf->pdev->dev;
7469 tx_ring->count = vsi->num_desc;
7470 tx_ring->size = 0;
7471 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7472 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7473 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
a75e8005 7474 tx_ring->tx_itr_setting = pf->tx_itr_default;
9f65e15b 7475 vsi->tx_rings[i] = tx_ring;
41c445ff 7476
9f65e15b 7477 rx_ring = &tx_ring[1];
41c445ff
JB		 7478 rx_ring->queue_index = i;
7479 rx_ring->reg_idx = vsi->base_queue + i;
7480 rx_ring->ring_active = false;
7481 rx_ring->vsi = vsi;
7482 rx_ring->netdev = vsi->netdev;
7483 rx_ring->dev = &pf->pdev->dev;
7484 rx_ring->count = vsi->num_desc;
7485 rx_ring->size = 0;
7486 rx_ring->dcb_tc = 0;
a75e8005 7487 rx_ring->rx_itr_setting = pf->rx_itr_default;
9f65e15b 7488 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7489 }
7490
7491 return 0;
9f65e15b
AD		 7492
7493err_out:
7494 i40e_vsi_clear_rings(vsi);
7495 return -ENOMEM;
41c445ff
JB		 7496}
7497
7498/**
7499 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7500 * @pf: board private structure
7501 * @vectors: the number of MSI-X vectors to request
7502 *
7503 * Returns the number of vectors reserved, or error
7504 **/
7505static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7506{
7b37f376
AG		 7507 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7508 I40E_MIN_MSIX, vectors);
7509 if (vectors < 0) {
41c445ff 7510 dev_info(&pf->pdev->dev,
7b37f376 7511 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7512 vectors = 0;
7513 }
7514
7515 return vectors;
7516}
7517
7518/**
7519 * i40e_init_msix - Setup the MSIX capability
7520 * @pf: board private structure
7521 *
7522 * Work with the OS to set up the MSIX vectors needed.
7523 *
3b444399 7524 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7525 **/
7526static int i40e_init_msix(struct i40e_pf *pf)
7527{
41c445ff 7528 struct i40e_hw *hw = &pf->hw;
1e200e4a 7529 int vectors_left;
41c445ff 7530 int v_budget, i;
3b444399 7531 int v_actual;
e3219ce6 7532 int iwarp_requested = 0;
41c445ff
JB		 7533
7534 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7535 return -ENODEV;
7536
7537 /* The number of vectors we'll request will be comprised of:
7538 * - Add 1 for "other" cause for Admin Queue events, etc.
7539 * - The number of LAN queue pairs
f8ff1464
ASJ		 7540 * - Queues being used for RSS.
7541 * We don't need as many as max_rss_size vectors.
7542 * use rss_size instead in the calculation since that
7543 * is governed by number of cpus in the system.
7544 * - assumes symmetric Tx/Rx pairing
41c445ff 7545 * - The number of VMDq pairs
e3219ce6 7546 * - The CPU count within the NUMA node if iWARP is enabled
38e00438
VD		 7547#ifdef I40E_FCOE
7548 * - The number of FCOE qps.
7549#endif
41c445ff
JB		 7550 * Once we count this up, try the request.
7551 *
7552 * If we can't get what we want, we'll simplify to nearly nothing
7553 * and try again. If that still fails, we punt.
7554 */
1e200e4a
SN		 7555 vectors_left = hw->func_caps.num_msix_vectors;
7556 v_budget = 0;
7557
7558 /* reserve one vector for miscellaneous handler */
7559 if (vectors_left) {
7560 v_budget++;
7561 vectors_left--;
7562 }
7563
7564 /* reserve vectors for the main PF traffic queues */
7565 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7566 vectors_left -= pf->num_lan_msix;
7567 v_budget += pf->num_lan_msix;
7568
7569 /* reserve one vector for sideband flow director */
7570 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7571 if (vectors_left) {
7572 v_budget++;
7573 vectors_left--;
7574 } else {
7575 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7576 }
7577 }
83840e4b 7578
38e00438 7579#ifdef I40E_FCOE
1e200e4a 7580 /* can we reserve enough for FCoE? */
38e00438 7581 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7582 if (!vectors_left)
7583 pf->num_fcoe_msix = 0;
7584 else if (vectors_left >= pf->num_fcoe_qps)
7585 pf->num_fcoe_msix = pf->num_fcoe_qps;
7586 else
7587 pf->num_fcoe_msix = 1;
38e00438 7588 v_budget += pf->num_fcoe_msix;
1e200e4a 7589 vectors_left -= pf->num_fcoe_msix;
38e00438 7590 }
1e200e4a 7591
38e00438 7592#endif
e3219ce6
ASJ		 7593 /* can we reserve enough for iWARP? */
7594 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7595 if (!vectors_left)
7596 pf->num_iwarp_msix = 0;
7597 else if (vectors_left < pf->num_iwarp_msix)
7598 pf->num_iwarp_msix = 1;
7599 v_budget += pf->num_iwarp_msix;
7600 vectors_left -= pf->num_iwarp_msix;
7601 }
7602
1e200e4a
SN		 7603 /* any vectors left over go for VMDq support */
7604 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7605 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7606 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7607
7608 /* if we're short on vectors for what's desired, we limit
7609 * the queues per vmdq. If this is still more than are
7610 * available, the user will need to change the number of
7611 * queues/vectors used by the PF later with the ethtool
7612 * channels command
7613 */
7614 if (vmdq_vecs < vmdq_vecs_wanted)
7615 pf->num_vmdq_qps = 1;
7616 pf->num_vmdq_msix = pf->num_vmdq_qps;
7617
7618 v_budget += vmdq_vecs;
7619 vectors_left -= vmdq_vecs;
7620 }
41c445ff
JB		 7621
7622 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7623 GFP_KERNEL);
7624 if (!pf->msix_entries)
7625 return -ENOMEM;
7626
7627 for (i = 0; i < v_budget; i++)
7628 pf->msix_entries[i].entry = i;
3b444399 7629 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7630
3b444399 7631 if (v_actual != v_budget) {
a34977ba
ASJ		 7632 /* If we have limited resources, we will start with no vectors
7633 * for the special features and then allocate vectors to some
7634 * of these features based on the policy and at the end disable
7635 * the features that did not get any vectors.
7636 */
e3219ce6
ASJ		 7637 iwarp_requested = pf->num_iwarp_msix;
7638 pf->num_iwarp_msix = 0;
38e00438
VD		 7639#ifdef I40E_FCOE
7640 pf->num_fcoe_qps = 0;
7641 pf->num_fcoe_msix = 0;
7642#endif
a34977ba
ASJ		 7643 pf->num_vmdq_msix = 0;
7644 }
7645
3b444399 7646 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7647 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7648 kfree(pf->msix_entries);
7649 pf->msix_entries = NULL;
7650 return -ENODEV;
7651
3b444399 7652 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7653 /* Adjust for minimal MSIX use */
41c445ff
JB		 7654 pf->num_vmdq_vsis = 0;
7655 pf->num_vmdq_qps = 0;
41c445ff
JB		 7656 pf->num_lan_qps = 1;
7657 pf->num_lan_msix = 1;
7658
3b444399
SN		 7659 } else if (v_actual != v_budget) {
7660 int vec;
7661
a34977ba 7662 /* reserve the misc vector */
3b444399 7663 vec = v_actual - 1;
a34977ba 7664
41c445ff
JB		 7665 /* Scale vector usage down */
7666 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7667 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7668 pf->num_vmdq_qps = 1;
7669 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7670
7671 /* partition out the remaining vectors */
7672 switch (vec) {
7673 case 2:
41c445ff
JB		 7674 pf->num_lan_msix = 1;
7675 break;
7676 case 3:
e3219ce6
ASJ		 7677 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7678 pf->num_lan_msix = 1;
7679 pf->num_iwarp_msix = 1;
7680 } else {
7681 pf->num_lan_msix = 2;
7682 }
38e00438
VD		 7683#ifdef I40E_FCOE
7684 /* give one vector to FCoE */
7685 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7686 pf->num_lan_msix = 1;
7687 pf->num_fcoe_msix = 1;
7688 }
38e00438 7689#endif
41c445ff
JB		 7690 break;
7691 default:
e3219ce6
ASJ		 7692 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7693 pf->num_iwarp_msix = min_t(int, (vec / 3),
7694 iwarp_requested);
7695 pf->num_vmdq_vsis = min_t(int, (vec / 3),
7696 I40E_DEFAULT_NUM_VMDQ_VSI);
7697 } else {
7698 pf->num_vmdq_vsis = min_t(int, (vec / 2),
7699 I40E_DEFAULT_NUM_VMDQ_VSI);
7700 }
7701 pf->num_lan_msix = min_t(int,
7702 (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)),
7703 pf->num_lan_msix);
38e00438
VD		 7704#ifdef I40E_FCOE
7705 /* give one vector to FCoE */
7706 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7707 pf->num_fcoe_msix = 1;
7708 vec--;
7709 }
7710#endif
41c445ff
JB		 7711 break;
7712 }
7713 }
7714
a34977ba
ASJ		 7715 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7716 (pf->num_vmdq_msix == 0)) {
7717 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7718 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7719 }
e3219ce6
ASJ		 7720
7721 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
7722 (pf->num_iwarp_msix == 0)) {
7723 dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n");
7724 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
7725 }
38e00438
VD		 7726#ifdef I40E_FCOE
7727
7728 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7729 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7730 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7731 }
7732#endif
3b444399 7733 return v_actual;
41c445ff
JB		 7734}
7735
493fb300 7736/**
90e04070 7737 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7738 * @vsi: the VSI being configured
7739 * @v_idx: index of the vector in the vsi struct
7740 *
7741 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7742 **/
90e04070 7743static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7744{
7745 struct i40e_q_vector *q_vector;
7746
7747 /* allocate q_vector */
7748 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7749 if (!q_vector)
7750 return -ENOMEM;
7751
7752 q_vector->vsi = vsi;
7753 q_vector->v_idx = v_idx;
7754 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7755 if (vsi->netdev)
7756 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7757 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7758
cd0b6fa6
AD		 7759 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7760 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7761
493fb300
AD		 7762 /* tie q_vector and vsi together */
7763 vsi->q_vectors[v_idx] = q_vector;
7764
7765 return 0;
7766}
7767
41c445ff 7768/**
90e04070 7769 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7770 * @vsi: the VSI being configured
7771 *
7772 * We allocate one q_vector per queue interrupt. If allocation fails we
7773 * return -ENOMEM.
7774 **/
90e04070 7775static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7776{
7777 struct i40e_pf *pf = vsi->back;
7778 int v_idx, num_q_vectors;
493fb300 7779 int err;
41c445ff
JB		 7780
7781 /* if not MSIX, give the one vector only to the LAN VSI */
7782 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7783 num_q_vectors = vsi->num_q_vectors;
7784 else if (vsi == pf->vsi[pf->lan_vsi])
7785 num_q_vectors = 1;
7786 else
7787 return -EINVAL;
7788
41c445ff 7789 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7790 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7791 if (err)
7792 goto err_out;
41c445ff
JB		 7793 }
7794
7795 return 0;
493fb300
AD		 7796
7797err_out:
7798 while (v_idx--)
7799 i40e_free_q_vector(vsi, v_idx);
7800
7801 return err;
41c445ff
JB		 7802}
7803
7804/**
7805 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7806 * @pf: board private structure to initialize
7807 **/
c1147280 7808static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7809{
3b444399
SN		 7810 int vectors = 0;
7811 ssize_t size;
41c445ff
JB		 7812
7813 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7814 vectors = i40e_init_msix(pf);
7815 if (vectors < 0) {
60ea5f83 7816 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
e3219ce6 7817 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 7818#ifdef I40E_FCOE
7819 I40E_FLAG_FCOE_ENABLED |
7820#endif
60ea5f83 7821 I40E_FLAG_RSS_ENABLED |
4d9b6043 7822 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7823 I40E_FLAG_SRIOV_ENABLED |
7824 I40E_FLAG_FD_SB_ENABLED |
7825 I40E_FLAG_FD_ATR_ENABLED |
7826 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7827
7828 /* rework the queue expectations without MSIX */
7829 i40e_determine_queue_usage(pf);
7830 }
7831 }
7832
7833 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7834 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7835 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7836 vectors = pci_enable_msi(pf->pdev);
7837 if (vectors < 0) {
7838 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7839 vectors);
41c445ff
JB		 7840 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7841 }
3b444399 7842 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7843 }
7844
958a3e3b 7845 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7846 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7847
3b444399
SN		 7848 /* set up vector assignment tracking */
7849 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7850 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7851 if (!pf->irq_pile) {
7852 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7853 return -ENOMEM;
7854 }
3b444399
SN		 7855 pf->irq_pile->num_entries = vectors;
7856 pf->irq_pile->search_hint = 0;
7857
c1147280 7858 /* track first vector for misc interrupts, ignore return */
3b444399 7859 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7860
7861 return 0;
41c445ff
JB		 7862}
7863
7864/**
7865 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7866 * @pf: board private structure
7867 *
7868 * This sets up the handler for MSIX 0, which is used to manage the
7869 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7870 * when in MSI or Legacy interrupt mode.
7871 **/
7872static int i40e_setup_misc_vector(struct i40e_pf *pf)
7873{
7874 struct i40e_hw *hw = &pf->hw;
7875 int err = 0;
7876
7877 /* Only request the irq if this is the first time through, and
7878 * not when we're rebuilding after a Reset
7879 */
7880 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7881 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7882 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7883 if (err) {
7884 dev_info(&pf->pdev->dev,
77fa28be 7885 "request_irq for %s failed: %d\n",
b294ac70 7886 pf->int_name, err);
41c445ff
JB		 7887 return -EFAULT;
7888 }
7889 }
7890
ab437b5a 7891 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7892
7893 /* associate no queues to the misc vector */
7894 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7895 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7896
7897 i40e_flush(hw);
7898
40d72a50 7899 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 7900
7901 return err;
7902}
7903
7904/**
e25d00b8
ASJ		 7905 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7906 * @vsi: vsi structure
7907 * @seed: RSS hash seed
7908 **/
e69ff813
HZ		 7909static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7910 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7911{
7912 struct i40e_aqc_get_set_rss_key_data rss_key;
7913 struct i40e_pf *pf = vsi->back;
7914 struct i40e_hw *hw = &pf->hw;
7915 bool pf_lut = false;
7916 u8 *rss_lut;
7917 int ret, i;
7918
7919 memset(&rss_key, 0, sizeof(rss_key));
7920 memcpy(&rss_key, seed, sizeof(rss_key));
7921
7922 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7923 if (!rss_lut)
7924 return -ENOMEM;
7925
7926 /* Populate the LUT with max no. of queues in round robin fashion */
7927 for (i = 0; i < vsi->rss_table_size; i++)
7928 rss_lut[i] = i % vsi->rss_size;
7929
7930 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7931 if (ret) {
7932 dev_info(&pf->pdev->dev,
7933 "Cannot set RSS key, err %s aq_err %s\n",
7934 i40e_stat_str(&pf->hw, ret),
7935 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7936 goto config_rss_aq_out;
e25d00b8
ASJ		 7937 }
7938
7939 if (vsi->type == I40E_VSI_MAIN)
7940 pf_lut = true;
7941
7942 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7943 vsi->rss_table_size);
7944 if (ret)
7945 dev_info(&pf->pdev->dev,
7946 "Cannot set RSS lut, err %s aq_err %s\n",
7947 i40e_stat_str(&pf->hw, ret),
7948 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7949
126b63d9
AS		 7950config_rss_aq_out:
7951 kfree(rss_lut);
e25d00b8
ASJ		 7952 return ret;
7953}
7954
7955/**
7956 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7957 * @vsi: VSI structure
7958 **/
7959static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7960{
7961 u8 seed[I40E_HKEY_ARRAY_SIZE];
7962 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7963 u8 *lut;
7964 int ret;
7965
7966 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7967 return 0;
7968
7969 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7970 if (!lut)
7971 return -ENOMEM;
e25d00b8 7972
e69ff813 7973 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7974 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7975 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7976 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7977 kfree(lut);
e25d00b8 7978
e69ff813 7979 return ret;
e25d00b8
ASJ		 7980}
7981
95a73780
ASJ		 7982/**
7983 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
7984 * @vsi: Pointer to vsi structure
7985 * @seed: Buffter to store the hash keys
7986 * @lut: Buffer to store the lookup table entries
7987 * @lut_size: Size of buffer to store the lookup table entries
7988 *
7989 * Return 0 on success, negative on failure
7990 */
7991static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7992 u8 *lut, u16 lut_size)
7993{
7994 struct i40e_pf *pf = vsi->back;
7995 struct i40e_hw *hw = &pf->hw;
7996 int ret = 0;
7997
7998 if (seed) {
7999 ret = i40e_aq_get_rss_key(hw, vsi->id,
8000 (struct i40e_aqc_get_set_rss_key_data *)seed);
8001 if (ret) {
8002 dev_info(&pf->pdev->dev,
8003 "Cannot get RSS key, err %s aq_err %s\n",
8004 i40e_stat_str(&pf->hw, ret),
8005 i40e_aq_str(&pf->hw,
8006 pf->hw.aq.asq_last_status));
8007 return ret;
8008 }
8009 }
8010
8011 if (lut) {
8012 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
8013
8014 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
8015 if (ret) {
8016 dev_info(&pf->pdev->dev,
8017 "Cannot get RSS lut, err %s aq_err %s\n",
8018 i40e_stat_str(&pf->hw, ret),
8019 i40e_aq_str(&pf->hw,
8020 pf->hw.aq.asq_last_status));
8021 return ret;
8022 }
8023 }
8024
8025 return ret;
8026}
8027
e25d00b8 8028/**
043dd650 8029 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 8030 * @vsi: Pointer to vsi structure
e25d00b8 8031 * @seed: RSS hash seed
e69ff813
HZ		 8032 * @lut: Lookup table
8033 * @lut_size: Lookup table size
8034 *
8035 * Returns 0 on success, negative on failure
41c445ff 8036 **/
e69ff813
HZ		 8037static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
8038 const u8 *lut, u16 lut_size)
41c445ff 8039{
e69ff813 8040 struct i40e_pf *pf = vsi->back;
4617e8c0 8041 struct i40e_hw *hw = &pf->hw;
c4e1868c 8042 u16 vf_id = vsi->vf_id;
e69ff813 8043 u8 i;
41c445ff 8044
e25d00b8 8045 /* Fill out hash function seed */
e69ff813
HZ		 8046 if (seed) {
8047 u32 *seed_dw = (u32 *)seed;
8048
c4e1868c
MW		 8049 if (vsi->type == I40E_VSI_MAIN) {
8050 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8051 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i),
8052 seed_dw[i]);
8053 } else if (vsi->type == I40E_VSI_SRIOV) {
8054 for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++)
8055 i40e_write_rx_ctl(hw,
8056 I40E_VFQF_HKEY1(i, vf_id),
8057 seed_dw[i]);
8058 } else {
8059 dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n");
8060 }
e69ff813
HZ		 8061 }
8062
8063 if (lut) {
8064 u32 *lut_dw = (u32 *)lut;
8065
c4e1868c
MW		 8066 if (vsi->type == I40E_VSI_MAIN) {
8067 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8068 return -EINVAL;
8069 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8070 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
8071 } else if (vsi->type == I40E_VSI_SRIOV) {
8072 if (lut_size != I40E_VF_HLUT_ARRAY_SIZE)
8073 return -EINVAL;
8074 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++)
8075 i40e_write_rx_ctl(hw,
8076 I40E_VFQF_HLUT1(i, vf_id),
8077 lut_dw[i]);
8078 } else {
8079 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n");
8080 }
e25d00b8
ASJ		 8081 }
8082 i40e_flush(hw);
8083
8084 return 0;
8085}
8086
043dd650
HZ		 8087/**
8088 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
8089 * @vsi: Pointer to VSI structure
8090 * @seed: Buffer to store the keys
8091 * @lut: Buffer to store the lookup table entries
8092 * @lut_size: Size of buffer to store the lookup table entries
8093 *
8094 * Returns 0 on success, negative on failure
8095 */
8096static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
8097 u8 *lut, u16 lut_size)
8098{
8099 struct i40e_pf *pf = vsi->back;
8100 struct i40e_hw *hw = &pf->hw;
8101 u16 i;
8102
8103 if (seed) {
8104 u32 *seed_dw = (u32 *)seed;
8105
8106 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
272cdaf2 8107 seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
043dd650
HZ		 8108 }
8109 if (lut) {
8110 u32 *lut_dw = (u32 *)lut;
8111
8112 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8113 return -EINVAL;
8114 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8115 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
8116 }
8117
8118 return 0;
8119}
8120
8121/**
8122 * i40e_config_rss - Configure RSS keys and lut
8123 * @vsi: Pointer to VSI structure
8124 * @seed: RSS hash seed
8125 * @lut: Lookup table
8126 * @lut_size: Lookup table size
8127 *
8128 * Returns 0 on success, negative on failure
8129 */
8130int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8131{
8132 struct i40e_pf *pf = vsi->back;
8133
8134 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8135 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8136 else
8137 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8138}
8139
8140/**
8141 * i40e_get_rss - Get RSS keys and lut
8142 * @vsi: Pointer to VSI structure
8143 * @seed: Buffer to store the keys
8144 * @lut: Buffer to store the lookup table entries
8145 * lut_size: Size of buffer to store the lookup table entries
8146 *
8147 * Returns 0 on success, negative on failure
8148 */
8149int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8150{
95a73780
ASJ		 8151 struct i40e_pf *pf = vsi->back;
8152
8153 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8154 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
8155 else
8156 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
043dd650
HZ		 8157}
8158
e69ff813
HZ		 8159/**
8160 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8161 * @pf: Pointer to board private structure
8162 * @lut: Lookup table
8163 * @rss_table_size: Lookup table size
8164 * @rss_size: Range of queue number for hashing
8165 */
8166static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8167 u16 rss_table_size, u16 rss_size)
8168{
8169 u16 i;
8170
8171 for (i = 0; i < rss_table_size; i++)
8172 lut[i] = i % rss_size;
8173}
8174
e25d00b8 8175/**
043dd650 8176 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8177 * @pf: board private structure
8178 **/
043dd650 8179static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8180{
8181 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8182 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8183 u8 *lut;
e25d00b8
ASJ		 8184 struct i40e_hw *hw = &pf->hw;
8185 u32 reg_val;
8186 u64 hena;
e69ff813 8187 int ret;
e25d00b8 8188
41c445ff 8189 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
272cdaf2
SN		 8190 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
8191 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8192 hena |= i40e_pf_get_default_rss_hena(pf);
8193
272cdaf2
SN		 8194 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
8195 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
41c445ff 8196
e25d00b8 8197 /* Determine the RSS table size based on the hardware capabilities */
272cdaf2 8198 reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8199 reg_val = (pf->rss_table_size == 512) ?
8200 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8201 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
272cdaf2 8202 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
e157ea30 8203
28c5869f
HZ		 8204 /* Determine the RSS size of the VSI */
8205 if (!vsi->rss_size)
acd65448
HZ		 8206 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8207 vsi->num_queue_pairs);
28c5869f 8208
e69ff813
HZ		 8209 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8210 if (!lut)
8211 return -ENOMEM;
8212
28c5869f
HZ		 8213 /* Use user configured lut if there is one, otherwise use default */
8214 if (vsi->rss_lut_user)
8215 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8216 else
8217 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8218
28c5869f
HZ		 8219 /* Use user configured hash key if there is one, otherwise
8220 * use default.
8221 */
8222 if (vsi->rss_hkey_user)
8223 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8224 else
8225 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8226 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8227 kfree(lut);
8228
8229 return ret;
41c445ff
JB		 8230}
8231
f8ff1464
ASJ		 8232/**
8233 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8234 * @pf: board private structure
8235 * @queue_count: the requested queue count for rss.
8236 *
8237 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8238 * count which may be different from the requested queue count.
8239 **/
8240int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8241{
9a3bd2f1
ASJ		 8242 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8243 int new_rss_size;
8244
f8ff1464
ASJ		 8245 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8246 return 0;
8247
9a3bd2f1 8248 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8249
9a3bd2f1
ASJ		 8250 if (queue_count != vsi->num_queue_pairs) {
8251 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8252 i40e_prep_for_reset(pf);
8253
acd65448 8254 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8255
8256 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8257
8258 /* Discard the user configured hash keys and lut, if less
8259 * queues are enabled.
8260 */
8261 if (queue_count < vsi->rss_size) {
8262 i40e_clear_rss_config_user(vsi);
8263 dev_dbg(&pf->pdev->dev,
8264 "discard user configured hash keys and lut\n");
8265 }
8266
8267 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8268 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8269 vsi->num_queue_pairs);
28c5869f 8270
043dd650 8271 i40e_pf_config_rss(pf);
f8ff1464 8272 }
e36b0b11
HZ		 8273 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8274 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8275 return pf->alloc_rss_size;
f8ff1464
ASJ		 8276}
8277
f4492db1
GR		 8278/**
8279 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8280 * @pf: board private structure
8281 **/
8282i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8283{
8284 i40e_status status;
8285 bool min_valid, max_valid;
8286 u32 max_bw, min_bw;
8287
8288 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8289 &min_valid, &max_valid);
8290
8291 if (!status) {
8292 if (min_valid)
8293 pf->npar_min_bw = min_bw;
8294 if (max_valid)
8295 pf->npar_max_bw = max_bw;
8296 }
8297
8298 return status;
8299}
8300
8301/**
8302 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8303 * @pf: board private structure
8304 **/
8305i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8306{
8307 struct i40e_aqc_configure_partition_bw_data bw_data;
8308 i40e_status status;
8309
b40c82e6 8310 /* Set the valid bit for this PF */
41a1d04b 8311 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8312 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8313 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8314
8315 /* Set the new bandwidths */
8316 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8317
8318 return status;
8319}
8320
8321/**
8322 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8323 * @pf: board private structure
8324 **/
8325i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8326{
8327 /* Commit temporary BW setting to permanent NVM image */
8328 enum i40e_admin_queue_err last_aq_status;
8329 i40e_status ret;
8330 u16 nvm_word;
8331
8332 if (pf->hw.partition_id != 1) {
8333 dev_info(&pf->pdev->dev,
8334 "Commit BW only works on partition 1! This is partition %d",
8335 pf->hw.partition_id);
8336 ret = I40E_NOT_SUPPORTED;
8337 goto bw_commit_out;
8338 }
8339
8340 /* Acquire NVM for read access */
8341 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8342 last_aq_status = pf->hw.aq.asq_last_status;
8343 if (ret) {
8344 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8345 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8346 i40e_stat_str(&pf->hw, ret),
8347 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8348 goto bw_commit_out;
8349 }
8350
8351 /* Read word 0x10 of NVM - SW compatibility word 1 */
8352 ret = i40e_aq_read_nvm(&pf->hw,
8353 I40E_SR_NVM_CONTROL_WORD,
8354 0x10, sizeof(nvm_word), &nvm_word,
8355 false, NULL);
8356 /* Save off last admin queue command status before releasing
8357 * the NVM
8358 */
8359 last_aq_status = pf->hw.aq.asq_last_status;
8360 i40e_release_nvm(&pf->hw);
8361 if (ret) {
f1c7e72e
SN		 8362 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8363 i40e_stat_str(&pf->hw, ret),
8364 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8365 goto bw_commit_out;
8366 }
8367
8368 /* Wait a bit for NVM release to complete */
8369 msleep(50);
8370
8371 /* Acquire NVM for write access */
8372 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8373 last_aq_status = pf->hw.aq.asq_last_status;
8374 if (ret) {
8375 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8376 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8377 i40e_stat_str(&pf->hw, ret),
8378 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8379 goto bw_commit_out;
8380 }
8381 /* Write it back out unchanged to initiate update NVM,
8382 * which will force a write of the shadow (alt) RAM to
8383 * the NVM - thus storing the bandwidth values permanently.
8384 */
8385 ret = i40e_aq_update_nvm(&pf->hw,
8386 I40E_SR_NVM_CONTROL_WORD,
8387 0x10, sizeof(nvm_word),
8388 &nvm_word, true, NULL);
8389 /* Save off last admin queue command status before releasing
8390 * the NVM
8391 */
8392 last_aq_status = pf->hw.aq.asq_last_status;
8393 i40e_release_nvm(&pf->hw);
8394 if (ret)
8395 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8396 "BW settings NOT SAVED, err %s aq_err %s\n",
8397 i40e_stat_str(&pf->hw, ret),
8398 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8399bw_commit_out:
8400
8401 return ret;
8402}
8403
41c445ff
JB		 8404/**
8405 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8406 * @pf: board private structure to initialize
8407 *
8408 * i40e_sw_init initializes the Adapter private data structure.
8409 * Fields are initialized based on PCI device information and
8410 * OS network device settings (MTU size).
8411 **/
8412static int i40e_sw_init(struct i40e_pf *pf)
8413{
8414 int err = 0;
8415 int size;
8416
8417 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8418 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
8419 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8420 if (I40E_DEBUG_USER & debug)
8421 pf->hw.debug_mask = debug;
8422 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8423 I40E_DEFAULT_MSG_ENABLE);
8424 }
8425
8426 /* Set default capability flags */
8427 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8428 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 8429 I40E_FLAG_MSIX_ENABLED;
8430
ca99eb99
MW		 8431 /* Set default ITR */
8432 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8433 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8434
7134f9ce
JB		 8435 /* Depending on PF configurations, it is possible that the RSS
8436 * maximum might end up larger than the available queues
8437 */
41a1d04b 8438 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8439 pf->alloc_rss_size = 1;
5db4cb59 8440 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8441 pf->rss_size_max = min_t(int, pf->rss_size_max,
8442 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8443 if (pf->hw.func_caps.rss) {
8444 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8445 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8446 num_online_cpus());
41c445ff
JB		 8447 }
8448
2050bc65 8449 /* MFP mode enabled */
c78b953e 8450 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8451 pf->flags |= I40E_FLAG_MFP_ENABLED;
8452 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8453 if (i40e_get_npar_bw_setting(pf))
8454 dev_warn(&pf->pdev->dev,
8455 "Could not get NPAR bw settings\n");
8456 else
8457 dev_info(&pf->pdev->dev,
8458 "Min BW = %8.8x, Max BW = %8.8x\n",
8459 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8460 }
8461
cbf61325
ASJ		 8462 /* FW/NVM is not yet fixed in this regard */
8463 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8464 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8465 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8466 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8467 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8468 pf->hw.num_partitions > 1)
cbf61325 8469 dev_info(&pf->pdev->dev,
0b67584f 8470 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8471 else
8472 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8473 pf->fdir_pf_filter_count =
8474 pf->hw.func_caps.fd_filters_guaranteed;
8475 pf->hw.fdir_shared_filter_count =
8476 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8477 }
8478
f1bbad33 8479 if (i40e_is_mac_710(&pf->hw) &&
8eed76fa 8480 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
f1bbad33 8481 (pf->hw.aq.fw_maj_ver < 4))) {
8eed76fa 8482 pf->flags |= I40E_FLAG_RESTART_AUTONEG;
f1bbad33
NP		 8483 /* No DCB support for FW < v4.33 */
8484 pf->flags |= I40E_FLAG_NO_DCB_SUPPORT;
8485 }
8486
8487 /* Disable FW LLDP if FW < v4.3 */
8488 if (i40e_is_mac_710(&pf->hw) &&
8489 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
8490 (pf->hw.aq.fw_maj_ver < 4)))
8491 pf->flags |= I40E_FLAG_STOP_FW_LLDP;
8492
8493 /* Use the FW Set LLDP MIB API if FW > v4.40 */
8494 if (i40e_is_mac_710(&pf->hw) &&
8495 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
8496 (pf->hw.aq.fw_maj_ver >= 5)))
8497 pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB;
8eed76fa 8498
41c445ff 8499 if (pf->hw.func_caps.vmdq) {
41c445ff 8500 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8501 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8502 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8503 }
8504
e3219ce6
ASJ		 8505 if (pf->hw.func_caps.iwarp) {
8506 pf->flags |= I40E_FLAG_IWARP_ENABLED;
8507 /* IWARP needs one extra vector for CQP just like MISC.*/
8508 pf->num_iwarp_msix = (int)num_online_cpus() + 1;
8509 }
8510
38e00438 8511#ifdef I40E_FCOE
21364bcf 8512 i40e_init_pf_fcoe(pf);
38e00438
VD		 8513
8514#endif /* I40E_FCOE */
41c445ff 8515#ifdef CONFIG_PCI_IOV
ba252f13 8516 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8517 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8518 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8519 pf->num_req_vfs = min_t(int,
8520 pf->hw.func_caps.num_vfs,
8521 I40E_MAX_VF_COUNT);
8522 }
8523#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8524 if (pf->hw.mac.type == I40E_MAC_X722) {
8525 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8526 I40E_FLAG_128_QP_RSS_CAPABLE |
8527 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8528 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8529 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024 8530 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
8e2cc0e6 8531 I40E_FLAG_NO_PCI_LINK_CHECK |
f8db54cc 8532 I40E_FLAG_100M_SGMII_CAPABLE |
f1bbad33 8533 I40E_FLAG_USE_SET_LLDP_MIB |
6a899024 8534 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
a340c789
AS		 8535 } else if ((pf->hw.aq.api_maj_ver > 1) ||
8536 ((pf->hw.aq.api_maj_ver == 1) &&
8537 (pf->hw.aq.api_min_ver > 4))) {
8538 /* Supported in FW API version higher than 1.4 */
8539 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
72b74869
ASJ		 8540 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
8541 } else {
8542 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
d502ce01 8543 }
a340c789 8544
41c445ff
JB		 8545 pf->eeprom_version = 0xDEAD;
8546 pf->lan_veb = I40E_NO_VEB;
8547 pf->lan_vsi = I40E_NO_VSI;
8548
d1a8d275
ASJ		 8549 /* By default FW has this off for performance reasons */
8550 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8551
41c445ff
JB		 8552 /* set up queue assignment tracking */
8553 size = sizeof(struct i40e_lump_tracking)
8554 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8555 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8556 if (!pf->qp_pile) {
8557 err = -ENOMEM;
8558 goto sw_init_done;
8559 }
8560 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8561 pf->qp_pile->search_hint = 0;
8562
327fe04b
ASJ		 8563 pf->tx_timeout_recovery_level = 1;
8564
41c445ff
JB		 8565 mutex_init(&pf->switch_mutex);
8566
c668a12c
GR		 8567 /* If NPAR is enabled nudge the Tx scheduler */
8568 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8569 i40e_set_npar_bw_setting(pf);
8570
41c445ff
JB		 8571sw_init_done:
8572 return err;
8573}
8574
7c3c288b
ASJ		 8575/**
8576 * i40e_set_ntuple - set the ntuple feature flag and take action
8577 * @pf: board private structure to initialize
8578 * @features: the feature set that the stack is suggesting
8579 *
8580 * returns a bool to indicate if reset needs to happen
8581 **/
8582bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8583{
8584 bool need_reset = false;
8585
8586 /* Check if Flow Director n-tuple support was enabled or disabled. If
8587 * the state changed, we need to reset.
8588 */
8589 if (features & NETIF_F_NTUPLE) {
8590 /* Enable filters and mark for reset */
8591 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8592 need_reset = true;
8593 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8594 } else {
8595 /* turn off filters, mark for reset and clear SW filter list */
8596 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8597 need_reset = true;
8598 i40e_fdir_filter_exit(pf);
8599 }
8600 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8601 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8602 /* reset fd counters */
8603 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8604 pf->fdir_pf_active_filters = 0;
8605 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8606 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8607 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8608 /* if ATR was auto disabled it can be re-enabled. */
8609 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8610 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8611 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8612 }
8613 return need_reset;
8614}
8615
41c445ff
JB		 8616/**
8617 * i40e_set_features - set the netdev feature flags
8618 * @netdev: ptr to the netdev being adjusted
8619 * @features: the feature set that the stack is suggesting
8620 **/
8621static int i40e_set_features(struct net_device *netdev,
8622 netdev_features_t features)
8623{
8624 struct i40e_netdev_priv *np = netdev_priv(netdev);
8625 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8626 struct i40e_pf *pf = vsi->back;
8627 bool need_reset;
41c445ff
JB		 8628
8629 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8630 i40e_vlan_stripping_enable(vsi);
8631 else
8632 i40e_vlan_stripping_disable(vsi);
8633
7c3c288b
ASJ		 8634 need_reset = i40e_set_ntuple(pf, features);
8635
8636 if (need_reset)
41a1d04b 8637 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8638
41c445ff
JB		 8639 return 0;
8640}
8641
a1c9a9d9 8642/**
6a899024 8643 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8644 * @pf: board private structure
8645 * @port: The UDP port to look up
8646 *
8647 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8648 **/
6a899024 8649static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8650{
8651 u8 i;
8652
8653 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8654 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8655 return i;
8656 }
8657
8658 return i;
8659}
8660
8661/**
06a5f7f1 8662 * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up
a1c9a9d9 8663 * @netdev: This physical port's netdev
06a5f7f1 8664 * @ti: Tunnel endpoint information
a1c9a9d9 8665 **/
06a5f7f1
AD		 8666static void i40e_udp_tunnel_add(struct net_device *netdev,
8667 struct udp_tunnel_info *ti)
a1c9a9d9
JK		 8668{
8669 struct i40e_netdev_priv *np = netdev_priv(netdev);
8670 struct i40e_vsi *vsi = np->vsi;
8671 struct i40e_pf *pf = vsi->back;
06a5f7f1 8672 __be16 port = ti->port;
a1c9a9d9
JK		 8673 u8 next_idx;
8674 u8 idx;
8675
6a899024 8676 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8677
8678 /* Check if port already exists */
8679 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
06a5f7f1 8680 netdev_info(netdev, "port %d already offloaded\n",
c22c06c8 8681 ntohs(port));
a1c9a9d9
JK		 8682 return;
8683 }
8684
8685 /* Now check if there is space to add the new port */
6a899024 8686 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8687
8688 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
06a5f7f1 8689 netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n",
6a899024
SA		 8690 ntohs(port));
8691 return;
8692 }
8693
06a5f7f1
AD		 8694 switch (ti->type) {
8695 case UDP_TUNNEL_TYPE_VXLAN:
8696 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8697 break;
8698 case UDP_TUNNEL_TYPE_GENEVE:
8699 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8700 return;
8701 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8702 break;
8703 default:
6a899024
SA		 8704 return;
8705 }
8706
8707 /* New port: add it and mark its index in the bitmap */
8708 pf->udp_ports[next_idx].index = port;
6a899024
SA		 8709 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8710 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 8711}
8712
6a899024 8713/**
06a5f7f1 8714 * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away
6a899024 8715 * @netdev: This physical port's netdev
06a5f7f1 8716 * @ti: Tunnel endpoint information
6a899024 8717 **/
06a5f7f1
AD		 8718static void i40e_udp_tunnel_del(struct net_device *netdev,
8719 struct udp_tunnel_info *ti)
6a899024 8720{
6a899024
SA		 8721 struct i40e_netdev_priv *np = netdev_priv(netdev);
8722 struct i40e_vsi *vsi = np->vsi;
8723 struct i40e_pf *pf = vsi->back;
06a5f7f1 8724 __be16 port = ti->port;
6a899024
SA		 8725 u8 idx;
8726
6a899024
SA		 8727 idx = i40e_get_udp_port_idx(pf, port);
8728
8729 /* Check if port already exists */
06a5f7f1
AD		 8730 if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS)
8731 goto not_found;
6a899024 8732
06a5f7f1
AD		 8733 switch (ti->type) {
8734 case UDP_TUNNEL_TYPE_VXLAN:
8735 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN)
8736 goto not_found;
8737 break;
8738 case UDP_TUNNEL_TYPE_GENEVE:
8739 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE)
8740 goto not_found;
8741 break;
8742 default:
8743 goto not_found;
6a899024 8744 }
06a5f7f1
AD		 8745
8746 /* if port exists, set it to 0 (mark for deletion)
8747 * and make it pending
8748 */
8749 pf->udp_ports[idx].index = 0;
8750 pf->pending_udp_bitmap |= BIT_ULL(idx);
8751 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8752
8753 return;
8754not_found:
8755 netdev_warn(netdev, "UDP port %d was not found, not deleting\n",
8756 ntohs(port));
6a899024
SA		 8757}
8758
1f224ad2 8759static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8760 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8761{
8762 struct i40e_netdev_priv *np = netdev_priv(netdev);
8763 struct i40e_pf *pf = np->vsi->back;
8764 struct i40e_hw *hw = &pf->hw;
8765
8766 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8767 return -EOPNOTSUPP;
8768
8769 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8770 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8771
8772 return 0;
8773}
8774
2f90ade6
JB		 8775/**
8776 * i40e_ndo_fdb_add - add an entry to the hardware database
8777 * @ndm: the input from the stack
8778 * @tb: pointer to array of nladdr (unused)
8779 * @dev: the net device pointer
8780 * @addr: the MAC address entry being added
8781 * @flags: instructions from stack about fdb operation
8782 */
4ba0dea5
GR		 8783static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8784 struct net_device *dev,
f6f6424b 8785 const unsigned char *addr, u16 vid,
4ba0dea5 8786 u16 flags)
4ba0dea5
GR		 8787{
8788 struct i40e_netdev_priv *np = netdev_priv(dev);
8789 struct i40e_pf *pf = np->vsi->back;
8790 int err = 0;
8791
8792 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8793 return -EOPNOTSUPP;
8794
65891fea
OG		 8795 if (vid) {
8796 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8797 return -EINVAL;
8798 }
8799
4ba0dea5
GR		 8800 /* Hardware does not support aging addresses so if a
8801 * ndm_state is given only allow permanent addresses
8802 */
8803 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8804 netdev_info(dev, "FDB only supports static addresses\n");
8805 return -EINVAL;
8806 }
8807
8808 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8809 err = dev_uc_add_excl(dev, addr);
8810 else if (is_multicast_ether_addr(addr))
8811 err = dev_mc_add_excl(dev, addr);
8812 else
8813 err = -EINVAL;
8814
8815 /* Only return duplicate errors if NLM_F_EXCL is set */
8816 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8817 err = 0;
8818
8819 return err;
8820}
8821
51616018
NP		 8822/**
8823 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8824 * @dev: the netdev being configured
8825 * @nlh: RTNL message
8826 *
8827 * Inserts a new hardware bridge if not already created and
8828 * enables the bridging mode requested (VEB or VEPA). If the
8829 * hardware bridge has already been inserted and the request
8830 * is to change the mode then that requires a PF reset to
8831 * allow rebuild of the components with required hardware
8832 * bridge mode enabled.
8833 **/
8834static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8835 struct nlmsghdr *nlh,
8836 u16 flags)
51616018
NP		 8837{
8838 struct i40e_netdev_priv *np = netdev_priv(dev);
8839 struct i40e_vsi *vsi = np->vsi;
8840 struct i40e_pf *pf = vsi->back;
8841 struct i40e_veb *veb = NULL;
8842 struct nlattr *attr, *br_spec;
8843 int i, rem;
8844
8845 /* Only for PF VSI for now */
8846 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8847 return -EOPNOTSUPP;
8848
8849 /* Find the HW bridge for PF VSI */
8850 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8851 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8852 veb = pf->veb[i];
8853 }
8854
8855 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8856
8857 nla_for_each_nested(attr, br_spec, rem) {
8858 __u16 mode;
8859
8860 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8861 continue;
8862
8863 mode = nla_get_u16(attr);
8864 if ((mode != BRIDGE_MODE_VEPA) &&
8865 (mode != BRIDGE_MODE_VEB))
8866 return -EINVAL;
8867
8868 /* Insert a new HW bridge */
8869 if (!veb) {
8870 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8871 vsi->tc_config.enabled_tc);
8872 if (veb) {
8873 veb->bridge_mode = mode;
8874 i40e_config_bridge_mode(veb);
8875 } else {
8876 /* No Bridge HW offload available */
8877 return -ENOENT;
8878 }
8879 break;
8880 } else if (mode != veb->bridge_mode) {
8881 /* Existing HW bridge but different mode needs reset */
8882 veb->bridge_mode = mode;
fc60861e
ASJ		 8883 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8884 if (mode == BRIDGE_MODE_VEB)
8885 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8886 else
8887 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8888 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8889 break;
8890 }
8891 }
8892
8893 return 0;
8894}
8895
8896/**
8897 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8898 * @skb: skb buff
8899 * @pid: process id
8900 * @seq: RTNL message seq #
8901 * @dev: the netdev being configured
8902 * @filter_mask: unused
d4b2f9fe 8903 * @nlflags: netlink flags passed in
51616018
NP		 8904 *
8905 * Return the mode in which the hardware bridge is operating in
8906 * i.e VEB or VEPA.
8907 **/
51616018
NP		 8908static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8909 struct net_device *dev,
9f4ffc44
CW		 8910 u32 __always_unused filter_mask,
8911 int nlflags)
51616018
NP		 8912{
8913 struct i40e_netdev_priv *np = netdev_priv(dev);
8914 struct i40e_vsi *vsi = np->vsi;
8915 struct i40e_pf *pf = vsi->back;
8916 struct i40e_veb *veb = NULL;
8917 int i;
8918
8919 /* Only for PF VSI for now */
8920 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8921 return -EOPNOTSUPP;
8922
8923 /* Find the HW bridge for the PF VSI */
8924 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8925 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8926 veb = pf->veb[i];
8927 }
8928
8929 if (!veb)
8930 return 0;
8931
46c264da 8932 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8933 nlflags, 0, 0, filter_mask, NULL);
51616018 8934}
51616018 8935
6a899024
SA		 8936/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
8937 * inner mac plus all inner ethertypes.
8938 */
8939#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 8940/**
8941 * i40e_features_check - Validate encapsulated packet conforms to limits
8942 * @skb: skb buff
2bc11c63 8943 * @dev: This physical port's netdev
f44a75e2
JS		 8944 * @features: Offload features that the stack believes apply
8945 **/
8946static netdev_features_t i40e_features_check(struct sk_buff *skb,
8947 struct net_device *dev,
8948 netdev_features_t features)
8949{
8950 if (skb->encapsulation &&
6a899024 8951 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 8952 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 8953 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 8954
8955 return features;
8956}
8957
37a2973a 8958static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8959 .ndo_open = i40e_open,
8960 .ndo_stop = i40e_close,
8961 .ndo_start_xmit = i40e_lan_xmit_frame,
8962 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8963 .ndo_set_rx_mode = i40e_set_rx_mode,
8964 .ndo_validate_addr = eth_validate_addr,
8965 .ndo_set_mac_address = i40e_set_mac,
8966 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8967 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8968 .ndo_tx_timeout = i40e_tx_timeout,
8969 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8970 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8971#ifdef CONFIG_NET_POLL_CONTROLLER
8972 .ndo_poll_controller = i40e_netpoll,
8973#endif
e4c6734e 8974 .ndo_setup_tc = __i40e_setup_tc,
38e00438
VD		 8975#ifdef I40E_FCOE
8976 .ndo_fcoe_enable = i40e_fcoe_enable,
8977 .ndo_fcoe_disable = i40e_fcoe_disable,
8978#endif
41c445ff
JB		 8979 .ndo_set_features = i40e_set_features,
8980 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8981 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8982 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8983 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8984 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8985 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
c3bbbd20 8986 .ndo_set_vf_trust = i40e_ndo_set_vf_trust,
06a5f7f1
AD		 8987 .ndo_udp_tunnel_add = i40e_udp_tunnel_add,
8988 .ndo_udp_tunnel_del = i40e_udp_tunnel_del,
1f224ad2 8989 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8990 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8991 .ndo_features_check = i40e_features_check,
51616018
NP		 8992 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8993 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8994};
8995
8996/**
8997 * i40e_config_netdev - Setup the netdev flags
8998 * @vsi: the VSI being configured
8999 *
9000 * Returns 0 on success, negative value on failure
9001 **/
9002static int i40e_config_netdev(struct i40e_vsi *vsi)
9003{
1a10370a 9004 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 9005 struct i40e_pf *pf = vsi->back;
9006 struct i40e_hw *hw = &pf->hw;
9007 struct i40e_netdev_priv *np;
9008 struct net_device *netdev;
9009 u8 mac_addr[ETH_ALEN];
9010 int etherdev_size;
9011
9012 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 9013 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 9014 if (!netdev)
9015 return -ENOMEM;
9016
9017 vsi->netdev = netdev;
9018 np = netdev_priv(netdev);
9019 np->vsi = vsi;
9020
b0fe3306
AD		 9021 netdev->hw_enc_features |= NETIF_F_SG |
9022 NETIF_F_IP_CSUM |
9023 NETIF_F_IPV6_CSUM |
9024 NETIF_F_HIGHDMA |
9025 NETIF_F_SOFT_FEATURES |
9026 NETIF_F_TSO |
9027 NETIF_F_TSO_ECN |
9028 NETIF_F_TSO6 |
9029 NETIF_F_GSO_GRE |
1c7b4a23 9030 NETIF_F_GSO_GRE_CSUM |
7e13318d 9031 NETIF_F_GSO_IPXIP4 |
bf2d1df3 9032 NETIF_F_GSO_IPXIP6 |
b0fe3306
AD		 9033 NETIF_F_GSO_UDP_TUNNEL |
9034 NETIF_F_GSO_UDP_TUNNEL_CSUM |
1c7b4a23 9035 NETIF_F_GSO_PARTIAL |
b0fe3306
AD		 9036 NETIF_F_SCTP_CRC |
9037 NETIF_F_RXHASH |
9038 NETIF_F_RXCSUM |
5afdaaa0 9039 0;
41c445ff 9040
b0fe3306 9041 if (!(pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE))
1c7b4a23
AD		 9042 netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
9043
9044 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
b0fe3306
AD		 9045
9046 /* record features VLANs can make use of */
1c7b4a23
AD		 9047 netdev->vlan_features |= netdev->hw_enc_features |
9048 NETIF_F_TSO_MANGLEID;
41c445ff 9049
2e86a0b6 9050 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
b0fe3306
AD		 9051 netdev->hw_features |= NETIF_F_NTUPLE;
9052
9053 netdev->hw_features |= netdev->hw_enc_features |
9054 NETIF_F_HW_VLAN_CTAG_TX |
9055 NETIF_F_HW_VLAN_CTAG_RX;
2e86a0b6 9056
b0fe3306 9057 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
1c7b4a23 9058 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
41c445ff
JB		 9059
9060 if (vsi->type == I40E_VSI_MAIN) {
9061 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 9062 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 9063 /* The following steps are necessary to prevent reception
9064 * of tagged packets - some older NVM configurations load a
9065 * default a MAC-VLAN filter that accepts any tagged packet
9066 * which must be replaced by a normal filter.
8c27d42e 9067 */
21659035
KP		 9068 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
9069 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 9070 i40e_add_filter(vsi, mac_addr,
9071 I40E_VLAN_ANY, false, true);
21659035
KP		 9072 spin_unlock_bh(&vsi->mac_filter_list_lock);
9073 }
3845ccea
ASJ		 9074 } else if ((pf->hw.aq.api_maj_ver > 1) ||
9075 ((pf->hw.aq.api_maj_ver == 1) &&
9076 (pf->hw.aq.api_min_ver > 4))) {
9077 /* Supported in FW API version higher than 1.4 */
9078 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
9079 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
41c445ff
JB		 9080 } else {
9081 /* relate the VSI_VMDQ name to the VSI_MAIN name */
9082 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
9083 pf->vsi[pf->lan_vsi]->netdev->name);
9084 random_ether_addr(mac_addr);
21659035
KP		 9085
9086 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 9087 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 9088 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9089 }
21659035
KP		 9090
9091 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 9092 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 9093 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9094
9a173901
GR		 9095 ether_addr_copy(netdev->dev_addr, mac_addr);
9096 ether_addr_copy(netdev->perm_addr, mac_addr);
b0fe3306 9097
41c445ff
JB		 9098 netdev->priv_flags |= IFF_UNICAST_FLT;
9099 netdev->priv_flags |= IFF_SUPP_NOFCS;
9100 /* Setup netdev TC information */
9101 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9102
9103 netdev->netdev_ops = &i40e_netdev_ops;
9104 netdev->watchdog_timeo = 5 * HZ;
9105 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9106#ifdef I40E_FCOE
9107 i40e_fcoe_config_netdev(netdev, vsi);
9108#endif
41c445ff
JB		 9109
9110 return 0;
9111}
9112
9113/**
9114 * i40e_vsi_delete - Delete a VSI from the switch
9115 * @vsi: the VSI being removed
9116 *
9117 * Returns 0 on success, negative value on failure
9118 **/
9119static void i40e_vsi_delete(struct i40e_vsi *vsi)
9120{
9121 /* remove default VSI is not allowed */
9122 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9123 return;
9124
41c445ff 9125 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9126}
9127
51616018
NP		 9128/**
9129 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9130 * @vsi: the VSI being queried
9131 *
9132 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9133 **/
9134int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9135{
9136 struct i40e_veb *veb;
9137 struct i40e_pf *pf = vsi->back;
9138
9139 /* Uplink is not a bridge so default to VEB */
9140 if (vsi->veb_idx == I40E_NO_VEB)
9141 return 1;
9142
9143 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9144 if (!veb) {
9145 dev_info(&pf->pdev->dev,
9146 "There is no veb associated with the bridge\n");
9147 return -ENOENT;
9148 }
9149
51616018 9150 /* Uplink is a bridge in VEPA mode */
09603eaa 9151 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9152 return 0;
09603eaa
AA		 9153 } else {
9154 /* Uplink is a bridge in VEB mode */
9155 return 1;
9156 }
51616018 9157
09603eaa
AA		 9158 /* VEPA is now default bridge, so return 0 */
9159 return 0;
51616018
NP		 9160}
9161
41c445ff
JB		 9162/**
9163 * i40e_add_vsi - Add a VSI to the switch
9164 * @vsi: the VSI being configured
9165 *
9166 * This initializes a VSI context depending on the VSI type to be added and
9167 * passes it down to the add_vsi aq command.
9168 **/
9169static int i40e_add_vsi(struct i40e_vsi *vsi)
9170{
9171 int ret = -ENODEV;
21659035
KP		 9172 u8 laa_macaddr[ETH_ALEN];
9173 bool found_laa_mac_filter = false;
41c445ff
JB		 9174 struct i40e_pf *pf = vsi->back;
9175 struct i40e_hw *hw = &pf->hw;
9176 struct i40e_vsi_context ctxt;
21659035
KP		 9177 struct i40e_mac_filter *f, *ftmp;
9178
41c445ff
JB		 9179 u8 enabled_tc = 0x1; /* TC0 enabled */
9180 int f_count = 0;
9181
9182 memset(&ctxt, 0, sizeof(ctxt));
9183 switch (vsi->type) {
9184 case I40E_VSI_MAIN:
9185 /* The PF's main VSI is already setup as part of the
9186 * device initialization, so we'll not bother with
9187 * the add_vsi call, but we will retrieve the current
9188 * VSI context.
9189 */
9190 ctxt.seid = pf->main_vsi_seid;
9191 ctxt.pf_num = pf->hw.pf_id;
9192 ctxt.vf_num = 0;
9193 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9194 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9195 if (ret) {
9196 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9197 "couldn't get PF vsi config, err %s aq_err %s\n",
9198 i40e_stat_str(&pf->hw, ret),
9199 i40e_aq_str(&pf->hw,
9200 pf->hw.aq.asq_last_status));
41c445ff
JB		 9201 return -ENOENT;
9202 }
1a2f6248 9203 vsi->info = ctxt.info;
41c445ff
JB		 9204 vsi->info.valid_sections = 0;
9205
9206 vsi->seid = ctxt.seid;
9207 vsi->id = ctxt.vsi_number;
9208
9209 enabled_tc = i40e_pf_get_tc_map(pf);
9210
9211 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9212 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9213 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9214 memset(&ctxt, 0, sizeof(ctxt));
9215 ctxt.seid = pf->main_vsi_seid;
9216 ctxt.pf_num = pf->hw.pf_id;
9217 ctxt.vf_num = 0;
9218 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9219 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9220 if (ret) {
9221 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9222 "update vsi failed, err %s aq_err %s\n",
9223 i40e_stat_str(&pf->hw, ret),
9224 i40e_aq_str(&pf->hw,
9225 pf->hw.aq.asq_last_status));
41c445ff
JB		 9226 ret = -ENOENT;
9227 goto err;
9228 }
9229 /* update the local VSI info queue map */
9230 i40e_vsi_update_queue_map(vsi, &ctxt);
9231 vsi->info.valid_sections = 0;
9232 } else {
9233 /* Default/Main VSI is only enabled for TC0
9234 * reconfigure it to enable all TCs that are
9235 * available on the port in SFP mode.
63d7e5a4
NP		 9236 * For MFP case the iSCSI PF would use this
9237 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9238 */
9239 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9240 if (ret) {
9241 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9242 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9243 enabled_tc,
9244 i40e_stat_str(&pf->hw, ret),
9245 i40e_aq_str(&pf->hw,
9246 pf->hw.aq.asq_last_status));
41c445ff
JB		 9247 ret = -ENOENT;
9248 }
9249 }
9250 break;
9251
9252 case I40E_VSI_FDIR:
cbf61325
ASJ		 9253 ctxt.pf_num = hw->pf_id;
9254 ctxt.vf_num = 0;
9255 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9256 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9257 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9258 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9259 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9260 ctxt.info.valid_sections |=
fc60861e 9261 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9262 ctxt.info.switch_id =
fc60861e 9263 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9264 }
41c445ff 9265 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9266 break;
9267
9268 case I40E_VSI_VMDQ2:
9269 ctxt.pf_num = hw->pf_id;
9270 ctxt.vf_num = 0;
9271 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9272 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9273 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9274
41c445ff
JB		 9275 /* This VSI is connected to VEB so the switch_id
9276 * should be set to zero by default.
9277 */
51616018
NP		 9278 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9279 ctxt.info.valid_sections |=
9280 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9281 ctxt.info.switch_id =
9282 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9283 }
41c445ff
JB		 9284
9285 /* Setup the VSI tx/rx queue map for TC0 only for now */
9286 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9287 break;
9288
9289 case I40E_VSI_SRIOV:
9290 ctxt.pf_num = hw->pf_id;
9291 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9292 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9293 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9294 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9295
41c445ff
JB		 9296 /* This VSI is connected to VEB so the switch_id
9297 * should be set to zero by default.
9298 */
51616018
NP		 9299 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9300 ctxt.info.valid_sections |=
9301 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9302 ctxt.info.switch_id =
9303 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9304 }
41c445ff 9305
e3219ce6
ASJ		 9306 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
9307 ctxt.info.valid_sections |=
9308 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
9309 ctxt.info.queueing_opt_flags |=
4b28cdba
AS		 9310 (I40E_AQ_VSI_QUE_OPT_TCP_ENA |
9311 I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI);
e3219ce6
ASJ		 9312 }
9313
41c445ff
JB		 9314 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9315 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9316 if (pf->vf[vsi->vf_id].spoofchk) {
9317 ctxt.info.valid_sections |=
9318 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9319 ctxt.info.sec_flags |=
9320 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9321 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9322 }
41c445ff
JB		 9323 /* Setup the VSI tx/rx queue map for TC0 only for now */
9324 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9325 break;
9326
38e00438
VD		 9327#ifdef I40E_FCOE
9328 case I40E_VSI_FCOE:
9329 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9330 if (ret) {
9331 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9332 return ret;
9333 }
9334 break;
9335
9336#endif /* I40E_FCOE */
e3219ce6
ASJ		 9337 case I40E_VSI_IWARP:
9338 /* send down message to iWARP */
9339 break;
9340
41c445ff
JB		 9341 default:
9342 return -ENODEV;
9343 }
9344
9345 if (vsi->type != I40E_VSI_MAIN) {
9346 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9347 if (ret) {
9348 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9349 "add vsi failed, err %s aq_err %s\n",
9350 i40e_stat_str(&pf->hw, ret),
9351 i40e_aq_str(&pf->hw,
9352 pf->hw.aq.asq_last_status));
41c445ff
JB		 9353 ret = -ENOENT;
9354 goto err;
9355 }
1a2f6248 9356 vsi->info = ctxt.info;
41c445ff
JB		 9357 vsi->info.valid_sections = 0;
9358 vsi->seid = ctxt.seid;
9359 vsi->id = ctxt.vsi_number;
9360 }
9361
21659035 9362 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9363 /* If macvlan filters already exist, force them to get loaded */
9364 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9365 f->changed = true;
9366 f_count++;
6252c7e4 9367
21659035 9368 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9369 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9370 ether_addr_copy(laa_macaddr, f->macaddr);
9371 found_laa_mac_filter = true;
9372 }
9373 }
9374 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9375
21659035
KP		 9376 if (found_laa_mac_filter) {
9377 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9378
21659035
KP		 9379 memset(&element, 0, sizeof(element));
9380 ether_addr_copy(element.mac_addr, laa_macaddr);
9381 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9382 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9383 &element, 1, NULL);
9384 if (ret) {
9385 /* some older FW has a different default */
9386 element.flags |=
9387 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9388 i40e_aq_remove_macvlan(hw, vsi->seid,
9389 &element, 1, NULL);
6252c7e4 9390 }
21659035
KP		 9391
9392 i40e_aq_mac_address_write(hw,
9393 I40E_AQC_WRITE_TYPE_LAA_WOL,
9394 laa_macaddr, NULL);
41c445ff 9395 }
21659035 9396
41c445ff
JB		 9397 if (f_count) {
9398 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9399 pf->flags |= I40E_FLAG_FILTER_SYNC;
9400 }
9401
9402 /* Update VSI BW information */
9403 ret = i40e_vsi_get_bw_info(vsi);
9404 if (ret) {
9405 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9406 "couldn't get vsi bw info, err %s aq_err %s\n",
9407 i40e_stat_str(&pf->hw, ret),
9408 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9409 /* VSI is already added so not tearing that up */
9410 ret = 0;
9411 }
9412
9413err:
9414 return ret;
9415}
9416
9417/**
9418 * i40e_vsi_release - Delete a VSI and free its resources
9419 * @vsi: the VSI being removed
9420 *
9421 * Returns 0 on success or < 0 on error
9422 **/
9423int i40e_vsi_release(struct i40e_vsi *vsi)
9424{
9425 struct i40e_mac_filter *f, *ftmp;
9426 struct i40e_veb *veb = NULL;
9427 struct i40e_pf *pf;
9428 u16 uplink_seid;
9429 int i, n;
9430
9431 pf = vsi->back;
9432
9433 /* release of a VEB-owner or last VSI is not allowed */
9434 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9435 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9436 vsi->seid, vsi->uplink_seid);
9437 return -ENODEV;
9438 }
9439 if (vsi == pf->vsi[pf->lan_vsi] &&
9440 !test_bit(__I40E_DOWN, &pf->state)) {
9441 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9442 return -ENODEV;
9443 }
9444
9445 uplink_seid = vsi->uplink_seid;
9446 if (vsi->type != I40E_VSI_SRIOV) {
9447 if (vsi->netdev_registered) {
9448 vsi->netdev_registered = false;
9449 if (vsi->netdev) {
9450 /* results in a call to i40e_close() */
9451 unregister_netdev(vsi->netdev);
41c445ff
JB		 9452 }
9453 } else {
90ef8d47 9454 i40e_vsi_close(vsi);
41c445ff
JB		 9455 }
9456 i40e_vsi_disable_irq(vsi);
9457 }
9458
21659035 9459 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9460 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9461 i40e_del_filter(vsi, f->macaddr, f->vlan,
9462 f->is_vf, f->is_netdev);
21659035
KP		 9463 spin_unlock_bh(&vsi->mac_filter_list_lock);
9464
17652c63 9465 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9466
9467 i40e_vsi_delete(vsi);
9468 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9469 if (vsi->netdev) {
9470 free_netdev(vsi->netdev);
9471 vsi->netdev = NULL;
9472 }
41c445ff
JB		 9473 i40e_vsi_clear_rings(vsi);
9474 i40e_vsi_clear(vsi);
9475
9476 /* If this was the last thing on the VEB, except for the
9477 * controlling VSI, remove the VEB, which puts the controlling
9478 * VSI onto the next level down in the switch.
9479 *
9480 * Well, okay, there's one more exception here: don't remove
9481 * the orphan VEBs yet. We'll wait for an explicit remove request
9482 * from up the network stack.
9483 */
505682cd 9484 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9485 if (pf->vsi[i] &&
9486 pf->vsi[i]->uplink_seid == uplink_seid &&
9487 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9488 n++; /* count the VSIs */
9489 }
9490 }
9491 for (i = 0; i < I40E_MAX_VEB; i++) {
9492 if (!pf->veb[i])
9493 continue;
9494 if (pf->veb[i]->uplink_seid == uplink_seid)
9495 n++; /* count the VEBs */
9496 if (pf->veb[i]->seid == uplink_seid)
9497 veb = pf->veb[i];
9498 }
9499 if (n == 0 && veb && veb->uplink_seid != 0)
9500 i40e_veb_release(veb);
9501
9502 return 0;
9503}
9504
9505/**
9506 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9507 * @vsi: ptr to the VSI
9508 *
9509 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9510 * corresponding SW VSI structure and initializes num_queue_pairs for the
9511 * newly allocated VSI.
9512 *
9513 * Returns 0 on success or negative on failure
9514 **/
9515static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9516{
9517 int ret = -ENOENT;
9518 struct i40e_pf *pf = vsi->back;
9519
493fb300 9520 if (vsi->q_vectors[0]) {
41c445ff
JB		 9521 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9522 vsi->seid);
9523 return -EEXIST;
9524 }
9525
9526 if (vsi->base_vector) {
f29eaa3d 9527 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9528 vsi->seid, vsi->base_vector);
9529 return -EEXIST;
9530 }
9531
90e04070 9532 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9533 if (ret) {
9534 dev_info(&pf->pdev->dev,
9535 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9536 vsi->num_q_vectors, vsi->seid, ret);
9537 vsi->num_q_vectors = 0;
9538 goto vector_setup_out;
9539 }
9540
26cdc443
ASJ		 9541 /* In Legacy mode, we do not have to get any other vector since we
9542 * piggyback on the misc/ICR0 for queue interrupts.
9543 */
9544 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9545 return ret;
958a3e3b
SN		 9546 if (vsi->num_q_vectors)
9547 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9548 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9549 if (vsi->base_vector < 0) {
9550 dev_info(&pf->pdev->dev,
049a2be8
SN		 9551 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9552 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9553 i40e_vsi_free_q_vectors(vsi);
9554 ret = -ENOENT;
9555 goto vector_setup_out;
9556 }
9557
9558vector_setup_out:
9559 return ret;
9560}
9561
bc7d338f
ASJ		 9562/**
9563 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9564 * @vsi: pointer to the vsi.
9565 *
9566 * This re-allocates a vsi's queue resources.
9567 *
9568 * Returns pointer to the successfully allocated and configured VSI sw struct
9569 * on success, otherwise returns NULL on failure.
9570 **/
9571static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9572{
f534039d 9573 struct i40e_pf *pf;
bc7d338f
ASJ		 9574 u8 enabled_tc;
9575 int ret;
9576
f534039d
JU		 9577 if (!vsi)
9578 return NULL;
9579
9580 pf = vsi->back;
9581
bc7d338f
ASJ		 9582 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9583 i40e_vsi_clear_rings(vsi);
9584
9585 i40e_vsi_free_arrays(vsi, false);
9586 i40e_set_num_rings_in_vsi(vsi);
9587 ret = i40e_vsi_alloc_arrays(vsi, false);
9588 if (ret)
9589 goto err_vsi;
9590
9591 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9592 if (ret < 0) {
049a2be8 9593 dev_info(&pf->pdev->dev,
f1c7e72e 9594 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9595 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9596 goto err_vsi;
9597 }
9598 vsi->base_queue = ret;
9599
9600 /* Update the FW view of the VSI. Force a reset of TC and queue
9601 * layout configurations.
9602 */
9603 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9604 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9605 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9606 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9607
9608 /* assign it some queues */
9609 ret = i40e_alloc_rings(vsi);
9610 if (ret)
9611 goto err_rings;
9612
9613 /* map all of the rings to the q_vectors */
9614 i40e_vsi_map_rings_to_vectors(vsi);
9615 return vsi;
9616
9617err_rings:
9618 i40e_vsi_free_q_vectors(vsi);
9619 if (vsi->netdev_registered) {
9620 vsi->netdev_registered = false;
9621 unregister_netdev(vsi->netdev);
9622 free_netdev(vsi->netdev);
9623 vsi->netdev = NULL;
9624 }
9625 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9626err_vsi:
9627 i40e_vsi_clear(vsi);
9628 return NULL;
9629}
9630
b499ffb0
SV		 9631/**
9632 * i40e_macaddr_init - explicitly write the mac address filters.
9633 *
9634 * @vsi: pointer to the vsi.
9635 * @macaddr: the MAC address
9636 *
9637 * This is needed when the macaddr has been obtained by other
9638 * means than the default, e.g., from Open Firmware or IDPROM.
9639 * Returns 0 on success, negative on failure
9640 **/
9641static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr)
9642{
9643 int ret;
9644 struct i40e_aqc_add_macvlan_element_data element;
9645
9646 ret = i40e_aq_mac_address_write(&vsi->back->hw,
9647 I40E_AQC_WRITE_TYPE_LAA_WOL,
9648 macaddr, NULL);
9649 if (ret) {
9650 dev_info(&vsi->back->pdev->dev,
9651 "Addr change for VSI failed: %d\n", ret);
9652 return -EADDRNOTAVAIL;
9653 }
9654
9655 memset(&element, 0, sizeof(element));
9656 ether_addr_copy(element.mac_addr, macaddr);
9657 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
9658 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL);
9659 if (ret) {
9660 dev_info(&vsi->back->pdev->dev,
9661 "add filter failed err %s aq_err %s\n",
9662 i40e_stat_str(&vsi->back->hw, ret),
9663 i40e_aq_str(&vsi->back->hw,
9664 vsi->back->hw.aq.asq_last_status));
9665 }
9666 return ret;
9667}
9668
41c445ff
JB		 9669/**
9670 * i40e_vsi_setup - Set up a VSI by a given type
9671 * @pf: board private structure
9672 * @type: VSI type
9673 * @uplink_seid: the switch element to link to
9674 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9675 *
9676 * This allocates the sw VSI structure and its queue resources, then add a VSI
9677 * to the identified VEB.
9678 *
9679 * Returns pointer to the successfully allocated and configure VSI sw struct on
9680 * success, otherwise returns NULL on failure.
9681 **/
9682struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9683 u16 uplink_seid, u32 param1)
9684{
9685 struct i40e_vsi *vsi = NULL;
9686 struct i40e_veb *veb = NULL;
9687 int ret, i;
9688 int v_idx;
9689
9690 /* The requested uplink_seid must be either
9691 * - the PF's port seid
9692 * no VEB is needed because this is the PF
9693 * or this is a Flow Director special case VSI
9694 * - seid of an existing VEB
9695 * - seid of a VSI that owns an existing VEB
9696 * - seid of a VSI that doesn't own a VEB
9697 * a new VEB is created and the VSI becomes the owner
9698 * - seid of the PF VSI, which is what creates the first VEB
9699 * this is a special case of the previous
9700 *
9701 * Find which uplink_seid we were given and create a new VEB if needed
9702 */
9703 for (i = 0; i < I40E_MAX_VEB; i++) {
9704 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9705 veb = pf->veb[i];
9706 break;
9707 }
9708 }
9709
9710 if (!veb && uplink_seid != pf->mac_seid) {
9711
505682cd 9712 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9713 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9714 vsi = pf->vsi[i];
9715 break;
9716 }
9717 }
9718 if (!vsi) {
9719 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9720 uplink_seid);
9721 return NULL;
9722 }
9723
9724 if (vsi->uplink_seid == pf->mac_seid)
9725 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9726 vsi->tc_config.enabled_tc);
9727 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9728 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9729 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9730 if (veb) {
9731 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9732 dev_info(&vsi->back->pdev->dev,
fb43201f 9733 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9734 return NULL;
9735 }
fa11cb3d
ASJ		 9736 /* We come up by default in VEPA mode if SRIOV is not
9737 * already enabled, in which case we can't force VEPA
9738 * mode.
9739 */
9740 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9741 veb->bridge_mode = BRIDGE_MODE_VEPA;
9742 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9743 }
51616018 9744 i40e_config_bridge_mode(veb);
79c21a82 9745 }
41c445ff
JB		 9746 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9747 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9748 veb = pf->veb[i];
9749 }
9750 if (!veb) {
9751 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9752 return NULL;
9753 }
9754
9755 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9756 uplink_seid = veb->seid;
9757 }
9758
9759 /* get vsi sw struct */
9760 v_idx = i40e_vsi_mem_alloc(pf, type);
9761 if (v_idx < 0)
9762 goto err_alloc;
9763 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9764 if (!vsi)
9765 goto err_alloc;
41c445ff
JB		 9766 vsi->type = type;
9767 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9768
9769 if (type == I40E_VSI_MAIN)
9770 pf->lan_vsi = v_idx;
9771 else if (type == I40E_VSI_SRIOV)
9772 vsi->vf_id = param1;
9773 /* assign it some queues */
cbf61325
ASJ		 9774 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9775 vsi->idx);
41c445ff 9776 if (ret < 0) {
049a2be8
SN		 9777 dev_info(&pf->pdev->dev,
9778 "failed to get tracking for %d queues for VSI %d err=%d\n",
9779 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9780 goto err_vsi;
9781 }
9782 vsi->base_queue = ret;
9783
9784 /* get a VSI from the hardware */
9785 vsi->uplink_seid = uplink_seid;
9786 ret = i40e_add_vsi(vsi);
9787 if (ret)
9788 goto err_vsi;
9789
9790 switch (vsi->type) {
9791 /* setup the netdev if needed */
9792 case I40E_VSI_MAIN:
b499ffb0
SV		 9793 /* Apply relevant filters if a platform-specific mac
9794 * address was selected.
9795 */
9796 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
9797 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr);
9798 if (ret) {
9799 dev_warn(&pf->pdev->dev,
9800 "could not set up macaddr; err %d\n",
9801 ret);
9802 }
9803 }
41c445ff 9804 case I40E_VSI_VMDQ2:
38e00438 9805 case I40E_VSI_FCOE:
41c445ff
JB		 9806 ret = i40e_config_netdev(vsi);
9807 if (ret)
9808 goto err_netdev;
9809 ret = register_netdev(vsi->netdev);
9810 if (ret)
9811 goto err_netdev;
9812 vsi->netdev_registered = true;
9813 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9814#ifdef CONFIG_I40E_DCB
9815 /* Setup DCB netlink interface */
9816 i40e_dcbnl_setup(vsi);
9817#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9818 /* fall through */
9819
9820 case I40E_VSI_FDIR:
9821 /* set up vectors and rings if needed */
9822 ret = i40e_vsi_setup_vectors(vsi);
9823 if (ret)
9824 goto err_msix;
9825
9826 ret = i40e_alloc_rings(vsi);
9827 if (ret)
9828 goto err_rings;
9829
9830 /* map all of the rings to the q_vectors */
9831 i40e_vsi_map_rings_to_vectors(vsi);
9832
9833 i40e_vsi_reset_stats(vsi);
9834 break;
9835
9836 default:
9837 /* no netdev or rings for the other VSI types */
9838 break;
9839 }
9840
e25d00b8
ASJ		 9841 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9842 (vsi->type == I40E_VSI_VMDQ2)) {
9843 ret = i40e_vsi_config_rss(vsi);
9844 }
41c445ff
JB		 9845 return vsi;
9846
9847err_rings:
9848 i40e_vsi_free_q_vectors(vsi);
9849err_msix:
9850 if (vsi->netdev_registered) {
9851 vsi->netdev_registered = false;
9852 unregister_netdev(vsi->netdev);
9853 free_netdev(vsi->netdev);
9854 vsi->netdev = NULL;
9855 }
9856err_netdev:
9857 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9858err_vsi:
9859 i40e_vsi_clear(vsi);
9860err_alloc:
9861 return NULL;
9862}
9863
9864/**
9865 * i40e_veb_get_bw_info - Query VEB BW information
9866 * @veb: the veb to query
9867 *
9868 * Query the Tx scheduler BW configuration data for given VEB
9869 **/
9870static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9871{
9872 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9873 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9874 struct i40e_pf *pf = veb->pf;
9875 struct i40e_hw *hw = &pf->hw;
9876 u32 tc_bw_max;
9877 int ret = 0;
9878 int i;
9879
9880 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9881 &bw_data, NULL);
9882 if (ret) {
9883 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9884 "query veb bw config failed, err %s aq_err %s\n",
9885 i40e_stat_str(&pf->hw, ret),
9886 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9887 goto out;
9888 }
9889
9890 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9891 &ets_data, NULL);
9892 if (ret) {
9893 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9894 "query veb bw ets config failed, err %s aq_err %s\n",
9895 i40e_stat_str(&pf->hw, ret),
9896 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9897 goto out;
9898 }
9899
9900 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9901 veb->bw_max_quanta = ets_data.tc_bw_max;
9902 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9903 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9904 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9905 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9906 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9907 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9908 veb->bw_tc_limit_credits[i] =
9909 le16_to_cpu(bw_data.tc_bw_limits[i]);
9910 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9911 }
9912
9913out:
9914 return ret;
9915}
9916
9917/**
9918 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9919 * @pf: board private structure
9920 *
9921 * On error: returns error code (negative)
9922 * On success: returns vsi index in PF (positive)
9923 **/
9924static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9925{
9926 int ret = -ENOENT;
9927 struct i40e_veb *veb;
9928 int i;
9929
9930 /* Need to protect the allocation of switch elements at the PF level */
9931 mutex_lock(&pf->switch_mutex);
9932
9933 /* VEB list may be fragmented if VEB creation/destruction has
9934 * been happening. We can afford to do a quick scan to look
9935 * for any free slots in the list.
9936 *
9937 * find next empty veb slot, looping back around if necessary
9938 */
9939 i = 0;
9940 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9941 i++;
9942 if (i >= I40E_MAX_VEB) {
9943 ret = -ENOMEM;
9944 goto err_alloc_veb; /* out of VEB slots! */
9945 }
9946
9947 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9948 if (!veb) {
9949 ret = -ENOMEM;
9950 goto err_alloc_veb;
9951 }
9952 veb->pf = pf;
9953 veb->idx = i;
9954 veb->enabled_tc = 1;
9955
9956 pf->veb[i] = veb;
9957 ret = i;
9958err_alloc_veb:
9959 mutex_unlock(&pf->switch_mutex);
9960 return ret;
9961}
9962
9963/**
9964 * i40e_switch_branch_release - Delete a branch of the switch tree
9965 * @branch: where to start deleting
9966 *
9967 * This uses recursion to find the tips of the branch to be
9968 * removed, deleting until we get back to and can delete this VEB.
9969 **/
9970static void i40e_switch_branch_release(struct i40e_veb *branch)
9971{
9972 struct i40e_pf *pf = branch->pf;
9973 u16 branch_seid = branch->seid;
9974 u16 veb_idx = branch->idx;
9975 int i;
9976
9977 /* release any VEBs on this VEB - RECURSION */
9978 for (i = 0; i < I40E_MAX_VEB; i++) {
9979 if (!pf->veb[i])
9980 continue;
9981 if (pf->veb[i]->uplink_seid == branch->seid)
9982 i40e_switch_branch_release(pf->veb[i]);
9983 }
9984
9985 /* Release the VSIs on this VEB, but not the owner VSI.
9986 *
9987 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9988 * the VEB itself, so don't use (*branch) after this loop.
9989 */
505682cd 9990 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9991 if (!pf->vsi[i])
9992 continue;
9993 if (pf->vsi[i]->uplink_seid == branch_seid &&
9994 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9995 i40e_vsi_release(pf->vsi[i]);
9996 }
9997 }
9998
9999 /* There's one corner case where the VEB might not have been
10000 * removed, so double check it here and remove it if needed.
10001 * This case happens if the veb was created from the debugfs
10002 * commands and no VSIs were added to it.
10003 */
10004 if (pf->veb[veb_idx])
10005 i40e_veb_release(pf->veb[veb_idx]);
10006}
10007
10008/**
10009 * i40e_veb_clear - remove veb struct
10010 * @veb: the veb to remove
10011 **/
10012static void i40e_veb_clear(struct i40e_veb *veb)
10013{
10014 if (!veb)
10015 return;
10016
10017 if (veb->pf) {
10018 struct i40e_pf *pf = veb->pf;
10019
10020 mutex_lock(&pf->switch_mutex);
10021 if (pf->veb[veb->idx] == veb)
10022 pf->veb[veb->idx] = NULL;
10023 mutex_unlock(&pf->switch_mutex);
10024 }
10025
10026 kfree(veb);
10027}
10028
10029/**
10030 * i40e_veb_release - Delete a VEB and free its resources
10031 * @veb: the VEB being removed
10032 **/
10033void i40e_veb_release(struct i40e_veb *veb)
10034{
10035 struct i40e_vsi *vsi = NULL;
10036 struct i40e_pf *pf;
10037 int i, n = 0;
10038
10039 pf = veb->pf;
10040
10041 /* find the remaining VSI and check for extras */
505682cd 10042 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10043 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
10044 n++;
10045 vsi = pf->vsi[i];
10046 }
10047 }
10048 if (n != 1) {
10049 dev_info(&pf->pdev->dev,
10050 "can't remove VEB %d with %d VSIs left\n",
10051 veb->seid, n);
10052 return;
10053 }
10054
10055 /* move the remaining VSI to uplink veb */
10056 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
10057 if (veb->uplink_seid) {
10058 vsi->uplink_seid = veb->uplink_seid;
10059 if (veb->uplink_seid == pf->mac_seid)
10060 vsi->veb_idx = I40E_NO_VEB;
10061 else
10062 vsi->veb_idx = veb->veb_idx;
10063 } else {
10064 /* floating VEB */
10065 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10066 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
10067 }
10068
10069 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
10070 i40e_veb_clear(veb);
41c445ff
JB		 10071}
10072
10073/**
10074 * i40e_add_veb - create the VEB in the switch
10075 * @veb: the VEB to be instantiated
10076 * @vsi: the controlling VSI
10077 **/
10078static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
10079{
f1c7e72e 10080 struct i40e_pf *pf = veb->pf;
66fc360a 10081 bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED);
41c445ff
JB		 10082 int ret;
10083
f1c7e72e 10084 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
5bc16031 10085 veb->enabled_tc, false,
66fc360a 10086 &veb->seid, enable_stats, NULL);
5bc16031
MW		 10087
10088 /* get a VEB from the hardware */
41c445ff 10089 if (ret) {
f1c7e72e
SN		 10090 dev_info(&pf->pdev->dev,
10091 "couldn't add VEB, err %s aq_err %s\n",
10092 i40e_stat_str(&pf->hw, ret),
10093 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10094 return -EPERM;
10095 }
10096
10097 /* get statistics counter */
f1c7e72e 10098 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 10099 &veb->stats_idx, NULL, NULL, NULL);
10100 if (ret) {
f1c7e72e
SN		 10101 dev_info(&pf->pdev->dev,
10102 "couldn't get VEB statistics idx, err %s aq_err %s\n",
10103 i40e_stat_str(&pf->hw, ret),
10104 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10105 return -EPERM;
10106 }
10107 ret = i40e_veb_get_bw_info(veb);
10108 if (ret) {
f1c7e72e
SN		 10109 dev_info(&pf->pdev->dev,
10110 "couldn't get VEB bw info, err %s aq_err %s\n",
10111 i40e_stat_str(&pf->hw, ret),
10112 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10113 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 10114 return -ENOENT;
10115 }
10116
10117 vsi->uplink_seid = veb->seid;
10118 vsi->veb_idx = veb->idx;
10119 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
10120
10121 return 0;
10122}
10123
10124/**
10125 * i40e_veb_setup - Set up a VEB
10126 * @pf: board private structure
10127 * @flags: VEB setup flags
10128 * @uplink_seid: the switch element to link to
10129 * @vsi_seid: the initial VSI seid
10130 * @enabled_tc: Enabled TC bit-map
10131 *
10132 * This allocates the sw VEB structure and links it into the switch
10133 * It is possible and legal for this to be a duplicate of an already
10134 * existing VEB. It is also possible for both uplink and vsi seids
10135 * to be zero, in order to create a floating VEB.
10136 *
10137 * Returns pointer to the successfully allocated VEB sw struct on
10138 * success, otherwise returns NULL on failure.
10139 **/
10140struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
10141 u16 uplink_seid, u16 vsi_seid,
10142 u8 enabled_tc)
10143{
10144 struct i40e_veb *veb, *uplink_veb = NULL;
10145 int vsi_idx, veb_idx;
10146 int ret;
10147
10148 /* if one seid is 0, the other must be 0 to create a floating relay */
10149 if ((uplink_seid == 0 || vsi_seid == 0) &&
10150 (uplink_seid + vsi_seid != 0)) {
10151 dev_info(&pf->pdev->dev,
10152 "one, not both seid's are 0: uplink=%d vsi=%d\n",
10153 uplink_seid, vsi_seid);
10154 return NULL;
10155 }
10156
10157 /* make sure there is such a vsi and uplink */
505682cd 10158 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10159 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10160 break;
505682cd 10161 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10162 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10163 vsi_seid);
10164 return NULL;
10165 }
10166
10167 if (uplink_seid && uplink_seid != pf->mac_seid) {
10168 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10169 if (pf->veb[veb_idx] &&
10170 pf->veb[veb_idx]->seid == uplink_seid) {
10171 uplink_veb = pf->veb[veb_idx];
10172 break;
10173 }
10174 }
10175 if (!uplink_veb) {
10176 dev_info(&pf->pdev->dev,
10177 "uplink seid %d not found\n", uplink_seid);
10178 return NULL;
10179 }
10180 }
10181
10182 /* get veb sw struct */
10183 veb_idx = i40e_veb_mem_alloc(pf);
10184 if (veb_idx < 0)
10185 goto err_alloc;
10186 veb = pf->veb[veb_idx];
10187 veb->flags = flags;
10188 veb->uplink_seid = uplink_seid;
10189 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10190 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10191
10192 /* create the VEB in the switch */
10193 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10194 if (ret)
10195 goto err_veb;
1bb8b935
SN		 10196 if (vsi_idx == pf->lan_vsi)
10197 pf->lan_veb = veb->idx;
41c445ff
JB		 10198
10199 return veb;
10200
10201err_veb:
10202 i40e_veb_clear(veb);
10203err_alloc:
10204 return NULL;
10205}
10206
10207/**
b40c82e6 10208 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10209 * @pf: board private structure
10210 * @ele: element we are building info from
10211 * @num_reported: total number of elements
10212 * @printconfig: should we print the contents
10213 *
10214 * helper function to assist in extracting a few useful SEID values.
10215 **/
10216static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10217 struct i40e_aqc_switch_config_element_resp *ele,
10218 u16 num_reported, bool printconfig)
10219{
10220 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10221 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10222 u8 element_type = ele->element_type;
10223 u16 seid = le16_to_cpu(ele->seid);
10224
10225 if (printconfig)
10226 dev_info(&pf->pdev->dev,
10227 "type=%d seid=%d uplink=%d downlink=%d\n",
10228 element_type, seid, uplink_seid, downlink_seid);
10229
10230 switch (element_type) {
10231 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10232 pf->mac_seid = seid;
10233 break;
10234 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10235 /* Main VEB? */
10236 if (uplink_seid != pf->mac_seid)
10237 break;
10238 if (pf->lan_veb == I40E_NO_VEB) {
10239 int v;
10240
10241 /* find existing or else empty VEB */
10242 for (v = 0; v < I40E_MAX_VEB; v++) {
10243 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10244 pf->lan_veb = v;
10245 break;
10246 }
10247 }
10248 if (pf->lan_veb == I40E_NO_VEB) {
10249 v = i40e_veb_mem_alloc(pf);
10250 if (v < 0)
10251 break;
10252 pf->lan_veb = v;
10253 }
10254 }
10255
10256 pf->veb[pf->lan_veb]->seid = seid;
10257 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10258 pf->veb[pf->lan_veb]->pf = pf;
10259 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10260 break;
10261 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10262 if (num_reported != 1)
10263 break;
10264 /* This is immediately after a reset so we can assume this is
10265 * the PF's VSI
10266 */
10267 pf->mac_seid = uplink_seid;
10268 pf->pf_seid = downlink_seid;
10269 pf->main_vsi_seid = seid;
10270 if (printconfig)
10271 dev_info(&pf->pdev->dev,
10272 "pf_seid=%d main_vsi_seid=%d\n",
10273 pf->pf_seid, pf->main_vsi_seid);
10274 break;
10275 case I40E_SWITCH_ELEMENT_TYPE_PF:
10276 case I40E_SWITCH_ELEMENT_TYPE_VF:
10277 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10278 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10279 case I40E_SWITCH_ELEMENT_TYPE_PE:
10280 case I40E_SWITCH_ELEMENT_TYPE_PA:
10281 /* ignore these for now */
10282 break;
10283 default:
10284 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10285 element_type, seid);
10286 break;
10287 }
10288}
10289
10290/**
10291 * i40e_fetch_switch_configuration - Get switch config from firmware
10292 * @pf: board private structure
10293 * @printconfig: should we print the contents
10294 *
10295 * Get the current switch configuration from the device and
10296 * extract a few useful SEID values.
10297 **/
10298int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10299{
10300 struct i40e_aqc_get_switch_config_resp *sw_config;
10301 u16 next_seid = 0;
10302 int ret = 0;
10303 u8 *aq_buf;
10304 int i;
10305
10306 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10307 if (!aq_buf)
10308 return -ENOMEM;
10309
10310 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10311 do {
10312 u16 num_reported, num_total;
10313
10314 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10315 I40E_AQ_LARGE_BUF,
10316 &next_seid, NULL);
10317 if (ret) {
10318 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10319 "get switch config failed err %s aq_err %s\n",
10320 i40e_stat_str(&pf->hw, ret),
10321 i40e_aq_str(&pf->hw,
10322 pf->hw.aq.asq_last_status));
41c445ff
JB		 10323 kfree(aq_buf);
10324 return -ENOENT;
10325 }
10326
10327 num_reported = le16_to_cpu(sw_config->header.num_reported);
10328 num_total = le16_to_cpu(sw_config->header.num_total);
10329
10330 if (printconfig)
10331 dev_info(&pf->pdev->dev,
10332 "header: %d reported %d total\n",
10333 num_reported, num_total);
10334
41c445ff
JB		 10335 for (i = 0; i < num_reported; i++) {
10336 struct i40e_aqc_switch_config_element_resp *ele =
10337 &sw_config->element[i];
10338
10339 i40e_setup_pf_switch_element(pf, ele, num_reported,
10340 printconfig);
10341 }
10342 } while (next_seid != 0);
10343
10344 kfree(aq_buf);
10345 return ret;
10346}
10347
10348/**
10349 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10350 * @pf: board private structure
bc7d338f 10351 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10352 *
10353 * Returns 0 on success, negative value on failure
10354 **/
bc7d338f 10355static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 10356{
b5569892 10357 u16 flags = 0;
41c445ff
JB		 10358 int ret;
10359
10360 /* find out what's out there already */
10361 ret = i40e_fetch_switch_configuration(pf, false);
10362 if (ret) {
10363 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10364 "couldn't fetch switch config, err %s aq_err %s\n",
10365 i40e_stat_str(&pf->hw, ret),
10366 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10367 return ret;
10368 }
10369 i40e_pf_reset_stats(pf);
10370
b5569892
ASJ		 10371 /* set the switch config bit for the whole device to
10372 * support limited promisc or true promisc
10373 * when user requests promisc. The default is limited
10374 * promisc.
10375 */
10376
10377 if ((pf->hw.pf_id == 0) &&
10378 !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT))
10379 flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
10380
10381 if (pf->hw.pf_id == 0) {
10382 u16 valid_flags;
10383
10384 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
10385 ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags,
10386 NULL);
10387 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
10388 dev_info(&pf->pdev->dev,
10389 "couldn't set switch config bits, err %s aq_err %s\n",
10390 i40e_stat_str(&pf->hw, ret),
10391 i40e_aq_str(&pf->hw,
10392 pf->hw.aq.asq_last_status));
10393 /* not a fatal problem, just keep going */
10394 }
10395 }
10396
41c445ff 10397 /* first time setup */
bc7d338f 10398 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10399 struct i40e_vsi *vsi = NULL;
10400 u16 uplink_seid;
10401
10402 /* Set up the PF VSI associated with the PF's main VSI
10403 * that is already in the HW switch
10404 */
10405 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10406 uplink_seid = pf->veb[pf->lan_veb]->seid;
10407 else
10408 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10409 if (pf->lan_vsi == I40E_NO_VSI)
10410 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10411 else if (reinit)
10412 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10413 if (!vsi) {
10414 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10415 i40e_fdir_teardown(pf);
10416 return -EAGAIN;
10417 }
41c445ff
JB		 10418 } else {
10419 /* force a reset of TC and queue layout configurations */
10420 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10421
41c445ff
JB		 10422 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10423 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10424 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10425 }
10426 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10427
cbf61325
ASJ		 10428 i40e_fdir_sb_setup(pf);
10429
41c445ff
JB		 10430 /* Setup static PF queue filter control settings */
10431 ret = i40e_setup_pf_filter_control(pf);
10432 if (ret) {
10433 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10434 ret);
10435 /* Failure here should not stop continuing other steps */
10436 }
10437
10438 /* enable RSS in the HW, even for only one queue, as the stack can use
10439 * the hash
10440 */
10441 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10442 i40e_pf_config_rss(pf);
41c445ff
JB		 10443
10444 /* fill in link information and enable LSE reporting */
0a862b43 10445 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10446 i40e_link_event(pf);
10447
d52c20b7 10448 /* Initialize user-specific link properties */
41c445ff
JB		 10449 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10450 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10451
beb0dff1
JK		 10452 i40e_ptp_init(pf);
10453
41c445ff
JB		 10454 return ret;
10455}
10456
41c445ff
JB		 10457/**
10458 * i40e_determine_queue_usage - Work out queue distribution
10459 * @pf: board private structure
10460 **/
10461static void i40e_determine_queue_usage(struct i40e_pf *pf)
10462{
41c445ff
JB		 10463 int queues_left;
10464
10465 pf->num_lan_qps = 0;
38e00438
VD		 10466#ifdef I40E_FCOE
10467 pf->num_fcoe_qps = 0;
10468#endif
41c445ff
JB		 10469
10470 /* Find the max queues to be put into basic use. We'll always be
10471 * using TC0, whether or not DCB is running, and TC0 will get the
10472 * big RSS set.
10473 */
10474 queues_left = pf->hw.func_caps.num_tx_qp;
10475
cbf61325 10476 if ((queues_left == 1) ||
9aa7e935 10477 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10478 /* one qp for PF, no queues for anything else */
10479 queues_left = 0;
acd65448 10480 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10481
10482 /* make sure all the fancies are disabled */
60ea5f83 10483 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10484 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10485#ifdef I40E_FCOE
10486 I40E_FLAG_FCOE_ENABLED |
10487#endif
60ea5f83
JB		 10488 I40E_FLAG_FD_SB_ENABLED |
10489 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10490 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10491 I40E_FLAG_SRIOV_ENABLED |
10492 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10493 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10494 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10495 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10496 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10497 /* one qp for PF */
acd65448 10498 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10499 queues_left -= pf->num_lan_qps;
10500
10501 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10502 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10503#ifdef I40E_FCOE
10504 I40E_FLAG_FCOE_ENABLED |
10505#endif
9aa7e935
FZ		 10506 I40E_FLAG_FD_SB_ENABLED |
10507 I40E_FLAG_FD_ATR_ENABLED |
10508 I40E_FLAG_DCB_ENABLED |
10509 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10510 } else {
cbf61325 10511 /* Not enough queues for all TCs */
4d9b6043 10512 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10513 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10514 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10515 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10516 }
9a3bd2f1
ASJ		 10517 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10518 num_online_cpus());
10519 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10520 pf->hw.func_caps.num_tx_qp);
10521
cbf61325
ASJ		 10522 queues_left -= pf->num_lan_qps;
10523 }
10524
38e00438
VD		 10525#ifdef I40E_FCOE
10526 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10527 if (I40E_DEFAULT_FCOE <= queues_left) {
10528 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10529 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10530 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10531 } else {
10532 pf->num_fcoe_qps = 0;
10533 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10534 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10535 }
10536
10537 queues_left -= pf->num_fcoe_qps;
10538 }
10539
10540#endif
cbf61325
ASJ		 10541 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10542 if (queues_left > 1) {
10543 queues_left -= 1; /* save 1 queue for FD */
10544 } else {
10545 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10546 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10547 }
41c445ff
JB		 10548 }
10549
10550 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10551 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10552 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10553 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10554 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10555 }
10556
10557 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10558 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10559 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10560 (queues_left / pf->num_vmdq_qps));
10561 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10562 }
10563
f8ff1464 10564 pf->queues_left = queues_left;
8279e495
NP		 10565 dev_dbg(&pf->pdev->dev,
10566 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10567 pf->hw.func_caps.num_tx_qp,
10568 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10569 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10570 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10571 queues_left);
38e00438 10572#ifdef I40E_FCOE
8279e495 10573 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10574#endif
41c445ff
JB		 10575}
10576
10577/**
10578 * i40e_setup_pf_filter_control - Setup PF static filter control
10579 * @pf: PF to be setup
10580 *
b40c82e6 10581 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10582 * settings. If PE/FCoE are enabled then it will also set the per PF
10583 * based filter sizes required for them. It also enables Flow director,
10584 * ethertype and macvlan type filter settings for the pf.
10585 *
10586 * Returns 0 on success, negative on failure
10587 **/
10588static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10589{
10590 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10591
10592 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10593
10594 /* Flow Director is enabled */
60ea5f83 10595 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10596 settings->enable_fdir = true;
10597
10598 /* Ethtype and MACVLAN filters enabled for PF */
10599 settings->enable_ethtype = true;
10600 settings->enable_macvlan = true;
10601
10602 if (i40e_set_filter_control(&pf->hw, settings))
10603 return -ENOENT;
10604
10605 return 0;
10606}
10607
0c22b3dd 10608#define INFO_STRING_LEN 255
7fd89545 10609#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10610static void i40e_print_features(struct i40e_pf *pf)
10611{
10612 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10613 char *buf;
10614 int i;
0c22b3dd 10615
3b195843
JP		 10616 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10617 if (!buf)
0c22b3dd 10618 return;
0c22b3dd 10619
3b195843 10620 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10621#ifdef CONFIG_PCI_IOV
3b195843 10622 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10623#endif
1a557afc 10624 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d",
7fd89545 10625 pf->hw.func_caps.num_vsis,
1a557afc 10626 pf->vsi[pf->lan_vsi]->num_queue_pairs);
0c22b3dd 10627 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10628 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10629 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10630 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10631 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10632 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10633 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10634 }
4d9b6043 10635 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10636 i += snprintf(&buf[i], REMAIN(i), " DCB");
3b195843 10637 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024 10638 i += snprintf(&buf[i], REMAIN(i), " Geneve");
0c22b3dd 10639 if (pf->flags & I40E_FLAG_PTP)
3b195843 10640 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10641#ifdef I40E_FCOE
10642 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10643 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10644#endif
6dec1017 10645 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10646 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10647 else
3b195843 10648 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10649
3b195843
JP		 10650 dev_info(&pf->pdev->dev, "%s\n", buf);
10651 kfree(buf);
7fd89545 10652 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10653}
10654
b499ffb0
SV		 10655/**
10656 * i40e_get_platform_mac_addr - get platform-specific MAC address
10657 *
10658 * @pdev: PCI device information struct
10659 * @pf: board private structure
10660 *
10661 * Look up the MAC address in Open Firmware on systems that support it,
10662 * and use IDPROM on SPARC if no OF address is found. On return, the
10663 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value
10664 * has been selected.
10665 **/
10666static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
10667{
b499ffb0 10668 pf->flags &= ~I40E_FLAG_PF_MAC;
ba94272d 10669 if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr))
b499ffb0 10670 pf->flags |= I40E_FLAG_PF_MAC;
b499ffb0
SV		 10671}
10672
41c445ff
JB		 10673/**
10674 * i40e_probe - Device initialization routine
10675 * @pdev: PCI device information struct
10676 * @ent: entry in i40e_pci_tbl
10677 *
b40c82e6
JK		 10678 * i40e_probe initializes a PF identified by a pci_dev structure.
10679 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10680 * and a hardware reset occur.
10681 *
10682 * Returns 0 on success, negative on failure
10683 **/
10684static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10685{
e827845c 10686 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10687 struct i40e_pf *pf;
10688 struct i40e_hw *hw;
93cd765b 10689 static u16 pfs_found;
1d5109d1 10690 u16 wol_nvm_bits;
d4dfb81a 10691 u16 link_status;
6f66a484 10692 int err;
4f2f017c 10693 u32 val;
8a9eb7d3 10694 u32 i;
58fc3267 10695 u8 set_fc_aq_fail;
41c445ff
JB		 10696
10697 err = pci_enable_device_mem(pdev);
10698 if (err)
10699 return err;
10700
10701 /* set up for high or low dma */
6494294f 10702 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10703 if (err) {
e3e3bfdd
JS		 10704 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10705 if (err) {
10706 dev_err(&pdev->dev,
10707 "DMA configuration failed: 0x%x\n", err);
10708 goto err_dma;
10709 }
41c445ff
JB		 10710 }
10711
10712 /* set up pci connections */
10713 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10714 IORESOURCE_MEM), i40e_driver_name);
10715 if (err) {
10716 dev_info(&pdev->dev,
10717 "pci_request_selected_regions failed %d\n", err);
10718 goto err_pci_reg;
10719 }
10720
10721 pci_enable_pcie_error_reporting(pdev);
10722 pci_set_master(pdev);
10723
10724 /* Now that we have a PCI connection, we need to do the
10725 * low level device setup. This is primarily setting up
10726 * the Admin Queue structures and then querying for the
10727 * device's current profile information.
10728 */
10729 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10730 if (!pf) {
10731 err = -ENOMEM;
10732 goto err_pf_alloc;
10733 }
10734 pf->next_vsi = 0;
10735 pf->pdev = pdev;
10736 set_bit(__I40E_DOWN, &pf->state);
10737
10738 hw = &pf->hw;
10739 hw->back = pf;
232f4706 10740
2ac8b675
SN		 10741 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10742 I40E_MAX_CSR_SPACE);
232f4706 10743
2ac8b675 10744 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10745 if (!hw->hw_addr) {
10746 err = -EIO;
10747 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10748 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10749 pf->ioremap_len, err);
41c445ff
JB		 10750 goto err_ioremap;
10751 }
10752 hw->vendor_id = pdev->vendor;
10753 hw->device_id = pdev->device;
10754 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10755 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10756 hw->subsystem_device_id = pdev->subsystem_device;
10757 hw->bus.device = PCI_SLOT(pdev->devfn);
10758 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10759 pf->instance = pfs_found;
41c445ff 10760
de03d2b0
SN		 10761 /* set up the locks for the AQ, do this only once in probe
10762 * and destroy them only once in remove
10763 */
10764 mutex_init(&hw->aq.asq_mutex);
10765 mutex_init(&hw->aq.arq_mutex);
10766
5b5faa43
SN		 10767 if (debug != -1) {
10768 pf->msg_enable = pf->hw.debug_mask;
10769 pf->msg_enable = debug;
10770 }
10771
7134f9ce
JB		 10772 /* do a special CORER for clearing PXE mode once at init */
10773 if (hw->revision_id == 0 &&
10774 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10775 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10776 i40e_flush(hw);
10777 msleep(200);
10778 pf->corer_count++;
10779
10780 i40e_clear_pxe_mode(hw);
10781 }
10782
41c445ff 10783 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10784 i40e_clear_hw(hw);
41c445ff
JB		 10785 err = i40e_pf_reset(hw);
10786 if (err) {
10787 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10788 goto err_pf_reset;
10789 }
10790 pf->pfr_count++;
10791
10792 hw->aq.num_arq_entries = I40E_AQ_LEN;
10793 hw->aq.num_asq_entries = I40E_AQ_LEN;
10794 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10795 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10796 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10797
b294ac70 10798 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10799 "%s-%s:misc",
10800 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10801
10802 err = i40e_init_shared_code(hw);
10803 if (err) {
b2a75c58
ASJ		 10804 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10805 err);
41c445ff
JB		 10806 goto err_pf_reset;
10807 }
10808
d52c20b7
JB		 10809 /* set up a default setting for link flow control */
10810 pf->hw.fc.requested_mode = I40E_FC_NONE;
10811
41c445ff 10812 err = i40e_init_adminq(hw);
2b2426a7
CW		 10813 if (err) {
10814 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10815 dev_info(&pdev->dev,
10816 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10817 else
10818 dev_info(&pdev->dev,
10819 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10820
10821 goto err_pf_reset;
10822 }
f0b44440 10823
6dec1017
SN		 10824 /* provide nvm, fw, api versions */
10825 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10826 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10827 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10828 i40e_nvm_version_str(hw));
f0b44440 10829
7aa67613
CS		 10830 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10831 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10832 dev_info(&pdev->dev,
7aa67613
CS		 10833 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10834 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10835 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10836 dev_info(&pdev->dev,
7aa67613 10837 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10838
4eb3f768
SN		 10839 i40e_verify_eeprom(pf);
10840
2c5fe33b
JB		 10841 /* Rev 0 hardware was never productized */
10842 if (hw->revision_id < 1)
10843 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10844
6ff4ef86 10845 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10846 err = i40e_get_capabilities(pf);
10847 if (err)
10848 goto err_adminq_setup;
10849
10850 err = i40e_sw_init(pf);
10851 if (err) {
10852 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10853 goto err_sw_init;
10854 }
10855
10856 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10857 hw->func_caps.num_rx_qp,
10858 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10859 if (err) {
10860 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10861 goto err_init_lan_hmc;
10862 }
10863
10864 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10865 if (err) {
10866 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10867 err = -ENOENT;
10868 goto err_configure_lan_hmc;
10869 }
10870
b686ece5
NP		 10871 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10872 * Ignore error return codes because if it was already disabled via
10873 * hardware settings this will fail
10874 */
f1bbad33 10875 if (pf->flags & I40E_FLAG_STOP_FW_LLDP) {
b686ece5
NP		 10876 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10877 i40e_aq_stop_lldp(hw, true, NULL);
10878 }
10879
41c445ff 10880 i40e_get_mac_addr(hw, hw->mac.addr);
b499ffb0
SV		 10881 /* allow a platform config to override the HW addr */
10882 i40e_get_platform_mac_addr(pdev, pf);
f62b5060 10883 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10884 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10885 err = -EIO;
10886 goto err_mac_addr;
10887 }
10888 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10889 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10890 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10891 if (is_valid_ether_addr(hw->mac.port_addr))
10892 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10893#ifdef I40E_FCOE
10894 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10895 if (err)
10896 dev_info(&pdev->dev,
10897 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10898 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10899 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10900 hw->mac.san_addr);
10901 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10902 }
10903 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10904#endif /* I40E_FCOE */
41c445ff
JB		 10905
10906 pci_set_drvdata(pdev, pf);
10907 pci_save_state(pdev);
4e3b35b0
NP		 10908#ifdef CONFIG_I40E_DCB
10909 err = i40e_init_pf_dcb(pf);
10910 if (err) {
aebfc816 10911 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10912 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10913 /* Continue without DCB enabled */
4e3b35b0
NP		 10914 }
10915#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10916
10917 /* set up periodic task facility */
10918 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10919 pf->service_timer_period = HZ;
10920
10921 INIT_WORK(&pf->service_task, i40e_service_task);
10922 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10923 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10924
1d5109d1
SN		 10925 /* NVM bit on means WoL disabled for the port */
10926 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10927 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10928 pf->wol_en = false;
10929 else
10930 pf->wol_en = true;
8e2773ae
SN		 10931 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10932
41c445ff
JB		 10933 /* set up the main switch operations */
10934 i40e_determine_queue_usage(pf);
c1147280
JB		 10935 err = i40e_init_interrupt_scheme(pf);
10936 if (err)
10937 goto err_switch_setup;
41c445ff 10938
505682cd
MW		 10939 /* The number of VSIs reported by the FW is the minimum guaranteed
10940 * to us; HW supports far more and we share the remaining pool with
10941 * the other PFs. We allocate space for more than the guarantee with
10942 * the understanding that we might not get them all later.
41c445ff 10943 */
505682cd
MW		 10944 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10945 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10946 else
10947 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10948
10949 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
d17038d6
JB		 10950 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
10951 GFP_KERNEL);
ed87ac09
WY		 10952 if (!pf->vsi) {
10953 err = -ENOMEM;
41c445ff 10954 goto err_switch_setup;
ed87ac09 10955 }
41c445ff 10956
fa11cb3d
ASJ		 10957#ifdef CONFIG_PCI_IOV
10958 /* prep for VF support */
10959 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10960 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10961 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10962 if (pci_num_vf(pdev))
10963 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10964 }
10965#endif
bc7d338f 10966 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10967 if (err) {
10968 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10969 goto err_vsis;
10970 }
58fc3267
HZ		 10971
10972 /* Make sure flow control is set according to current settings */
10973 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10974 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10975 dev_dbg(&pf->pdev->dev,
10976 "Set fc with err %s aq_err %s on get_phy_cap\n",
10977 i40e_stat_str(hw, err),
10978 i40e_aq_str(hw, hw->aq.asq_last_status));
10979 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10980 dev_dbg(&pf->pdev->dev,
10981 "Set fc with err %s aq_err %s on set_phy_config\n",
10982 i40e_stat_str(hw, err),
10983 i40e_aq_str(hw, hw->aq.asq_last_status));
10984 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10985 dev_dbg(&pf->pdev->dev,
10986 "Set fc with err %s aq_err %s on get_link_info\n",
10987 i40e_stat_str(hw, err),
10988 i40e_aq_str(hw, hw->aq.asq_last_status));
10989
8a9eb7d3 10990 /* if FDIR VSI was set up, start it now */
505682cd 10991 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10992 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10993 i40e_vsi_open(pf->vsi[i]);
10994 break;
10995 }
10996 }
41c445ff 10997
2f0aff41
SN		 10998 /* The driver only wants link up/down and module qualification
10999 * reports from firmware. Note the negative logic.
7e2453fe
JB		 11000 */
11001 err = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 11002 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 11003 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 11004 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 11005 if (err)
f1c7e72e
SN		 11006 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
11007 i40e_stat_str(&pf->hw, err),
11008 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 11009
4f2f017c
ASJ		 11010 /* Reconfigure hardware for allowing smaller MSS in the case
11011 * of TSO, so that we avoid the MDD being fired and causing
11012 * a reset in the case of small MSS+TSO.
11013 */
11014 val = rd32(hw, I40E_REG_MSS);
11015 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
11016 val &= ~I40E_REG_MSS_MIN_MASK;
11017 val |= I40E_64BYTE_MSS;
11018 wr32(hw, I40E_REG_MSS, val);
11019 }
11020
8eed76fa 11021 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 11022 msleep(75);
11023 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
11024 if (err)
f1c7e72e
SN		 11025 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
11026 i40e_stat_str(&pf->hw, err),
11027 i40e_aq_str(&pf->hw,
11028 pf->hw.aq.asq_last_status));
cafa2ee6 11029 }
41c445ff
JB		 11030 /* The main driver is (mostly) up and happy. We need to set this state
11031 * before setting up the misc vector or we get a race and the vector
11032 * ends up disabled forever.
11033 */
11034 clear_bit(__I40E_DOWN, &pf->state);
11035
11036 /* In case of MSIX we are going to setup the misc vector right here
11037 * to handle admin queue events etc. In case of legacy and MSI
11038 * the misc functionality and queue processing is combined in
11039 * the same vector and that gets setup at open.
11040 */
11041 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
11042 err = i40e_setup_misc_vector(pf);
11043 if (err) {
11044 dev_info(&pdev->dev,
11045 "setup of misc vector failed: %d\n", err);
11046 goto err_vsis;
11047 }
11048 }
11049
df805f62 11050#ifdef CONFIG_PCI_IOV
41c445ff
JB		 11051 /* prep for VF support */
11052 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 11053 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11054 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 11055 /* disable link interrupts for VFs */
11056 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
11057 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
11058 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
11059 i40e_flush(hw);
4aeec010
MW		 11060
11061 if (pci_num_vf(pdev)) {
11062 dev_info(&pdev->dev,
11063 "Active VFs found, allocating resources.\n");
11064 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
11065 if (err)
11066 dev_info(&pdev->dev,
11067 "Error %d allocating resources for existing VFs\n",
11068 err);
11069 }
41c445ff 11070 }
df805f62 11071#endif /* CONFIG_PCI_IOV */
41c445ff 11072
e3219ce6
ASJ		 11073 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
11074 pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile,
11075 pf->num_iwarp_msix,
11076 I40E_IWARP_IRQ_PILE_ID);
11077 if (pf->iwarp_base_vector < 0) {
11078 dev_info(&pdev->dev,
11079 "failed to get tracking for %d vectors for IWARP err=%d\n",
11080 pf->num_iwarp_msix, pf->iwarp_base_vector);
11081 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
11082 }
11083 }
93cd765b 11084
41c445ff
JB		 11085 i40e_dbg_pf_init(pf);
11086
11087 /* tell the firmware that we're starting */
44033fac 11088 i40e_send_version(pf);
41c445ff
JB		 11089
11090 /* since everything's happy, start the service_task timer */
11091 mod_timer(&pf->service_timer,
11092 round_jiffies(jiffies + pf->service_timer_period));
11093
e3219ce6
ASJ		 11094 /* add this PF to client device list and launch a client service task */
11095 err = i40e_lan_add_device(pf);
11096 if (err)
11097 dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n",
11098 err);
11099
38e00438
VD		 11100#ifdef I40E_FCOE
11101 /* create FCoE interface */
11102 i40e_fcoe_vsi_setup(pf);
11103
11104#endif
3fced535
ASJ		 11105#define PCI_SPEED_SIZE 8
11106#define PCI_WIDTH_SIZE 8
11107 /* Devices on the IOSF bus do not have this information
11108 * and will report PCI Gen 1 x 1 by default so don't bother
11109 * checking them.
11110 */
11111 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
11112 char speed[PCI_SPEED_SIZE] = "Unknown";
11113 char width[PCI_WIDTH_SIZE] = "Unknown";
11114
11115 /* Get the negotiated link width and speed from PCI config
11116 * space
11117 */
11118 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
11119 &link_status);
11120
11121 i40e_set_pci_config_data(hw, link_status);
11122
11123 switch (hw->bus.speed) {
11124 case i40e_bus_speed_8000:
11125 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
11126 case i40e_bus_speed_5000:
11127 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
11128 case i40e_bus_speed_2500:
11129 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
11130 default:
11131 break;
11132 }
11133 switch (hw->bus.width) {
11134 case i40e_bus_width_pcie_x8:
11135 strncpy(width, "8", PCI_WIDTH_SIZE); break;
11136 case i40e_bus_width_pcie_x4:
11137 strncpy(width, "4", PCI_WIDTH_SIZE); break;
11138 case i40e_bus_width_pcie_x2:
11139 strncpy(width, "2", PCI_WIDTH_SIZE); break;
11140 case i40e_bus_width_pcie_x1:
11141 strncpy(width, "1", PCI_WIDTH_SIZE); break;
11142 default:
11143 break;
11144 }
11145
11146 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
11147 speed, width);
11148
11149 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
11150 hw->bus.speed < i40e_bus_speed_8000) {
11151 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
11152 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
11153 }
d4dfb81a
CS		 11154 }
11155
e827845c
CS		 11156 /* get the requested speeds from the fw */
11157 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
11158 if (err)
8279e495
NP		 11159 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
11160 i40e_stat_str(&pf->hw, err),
11161 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 11162 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
11163
fc72dbce
CS		 11164 /* get the supported phy types from the fw */
11165 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
11166 if (err)
11167 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
11168 i40e_stat_str(&pf->hw, err),
11169 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11170 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
11171
e7358f54
ASJ		 11172 /* Add a filter to drop all Flow control frames from any VSI from being
11173 * transmitted. By doing so we stop a malicious VF from sending out
11174 * PAUSE or PFC frames and potentially controlling traffic for other
11175 * PF/VF VSIs.
11176 * The FW can still send Flow control frames if enabled.
11177 */
11178 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11179 pf->main_vsi_seid);
11180
31b606d0
CW		 11181 if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
11182 (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
11183 pf->flags |= I40E_FLAG_HAVE_10GBASET_PHY;
11184
0c22b3dd
JB		 11185 /* print a string summarizing features */
11186 i40e_print_features(pf);
11187
41c445ff
JB		 11188 return 0;
11189
11190 /* Unwind what we've done if something failed in the setup */
11191err_vsis:
11192 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 11193 i40e_clear_interrupt_scheme(pf);
11194 kfree(pf->vsi);
04b03013
SN		 11195err_switch_setup:
11196 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 11197 del_timer_sync(&pf->service_timer);
11198err_mac_addr:
11199err_configure_lan_hmc:
11200 (void)i40e_shutdown_lan_hmc(hw);
11201err_init_lan_hmc:
11202 kfree(pf->qp_pile);
41c445ff
JB		 11203err_sw_init:
11204err_adminq_setup:
41c445ff
JB		 11205err_pf_reset:
11206 iounmap(hw->hw_addr);
11207err_ioremap:
11208 kfree(pf);
11209err_pf_alloc:
11210 pci_disable_pcie_error_reporting(pdev);
11211 pci_release_selected_regions(pdev,
11212 pci_select_bars(pdev, IORESOURCE_MEM));
11213err_pci_reg:
11214err_dma:
11215 pci_disable_device(pdev);
11216 return err;
11217}
11218
11219/**
11220 * i40e_remove - Device removal routine
11221 * @pdev: PCI device information struct
11222 *
11223 * i40e_remove is called by the PCI subsystem to alert the driver
11224 * that is should release a PCI device. This could be caused by a
11225 * Hot-Plug event, or because the driver is going to be removed from
11226 * memory.
11227 **/
11228static void i40e_remove(struct pci_dev *pdev)
11229{
11230 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11231 struct i40e_hw *hw = &pf->hw;
41c445ff 11232 i40e_status ret_code;
41c445ff
JB		 11233 int i;
11234
11235 i40e_dbg_pf_exit(pf);
11236
beb0dff1
JK		 11237 i40e_ptp_stop(pf);
11238
bcab2db9 11239 /* Disable RSS in hw */
272cdaf2
SN		 11240 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
11241 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
bcab2db9 11242
41c445ff 11243 /* no more scheduling of any task */
a4618ec8 11244 set_bit(__I40E_SUSPENDED, &pf->state);
41c445ff 11245 set_bit(__I40E_DOWN, &pf->state);
c99abb4c
SN		 11246 if (pf->service_timer.data)
11247 del_timer_sync(&pf->service_timer);
11248 if (pf->service_task.func)
11249 cancel_work_sync(&pf->service_task);
41c445ff 11250
eb2d80bc
MW		 11251 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11252 i40e_free_vfs(pf);
11253 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11254 }
11255
41c445ff
JB		 11256 i40e_fdir_teardown(pf);
11257
11258 /* If there is a switch structure or any orphans, remove them.
11259 * This will leave only the PF's VSI remaining.
11260 */
11261 for (i = 0; i < I40E_MAX_VEB; i++) {
11262 if (!pf->veb[i])
11263 continue;
11264
11265 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11266 pf->veb[i]->uplink_seid == 0)
11267 i40e_switch_branch_release(pf->veb[i]);
11268 }
11269
11270 /* Now we can shutdown the PF's VSI, just before we kill
11271 * adminq and hmc.
11272 */
11273 if (pf->vsi[pf->lan_vsi])
11274 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11275
e3219ce6
ASJ		 11276 /* remove attached clients */
11277 ret_code = i40e_lan_del_device(pf);
11278 if (ret_code) {
11279 dev_warn(&pdev->dev, "Failed to delete client device: %d\n",
11280 ret_code);
11281 }
11282
41c445ff 11283 /* shutdown and destroy the HMC */
f734dfff
JB		 11284 if (hw->hmc.hmc_obj) {
11285 ret_code = i40e_shutdown_lan_hmc(hw);
60442dea
SN		 11286 if (ret_code)
11287 dev_warn(&pdev->dev,
11288 "Failed to destroy the HMC resources: %d\n",
11289 ret_code);
11290 }
41c445ff
JB		 11291
11292 /* shutdown the adminq */
f734dfff 11293 ret_code = i40e_shutdown_adminq(hw);
41c445ff
JB		 11294 if (ret_code)
11295 dev_warn(&pdev->dev,
11296 "Failed to destroy the Admin Queue resources: %d\n",
11297 ret_code);
11298
8ddb3326
JB		 11299 /* destroy the locks only once, here */
11300 mutex_destroy(&hw->aq.arq_mutex);
11301 mutex_destroy(&hw->aq.asq_mutex);
11302
41c445ff
JB		 11303 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11304 i40e_clear_interrupt_scheme(pf);
505682cd 11305 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11306 if (pf->vsi[i]) {
11307 i40e_vsi_clear_rings(pf->vsi[i]);
11308 i40e_vsi_clear(pf->vsi[i]);
11309 pf->vsi[i] = NULL;
11310 }
11311 }
11312
11313 for (i = 0; i < I40E_MAX_VEB; i++) {
11314 kfree(pf->veb[i]);
11315 pf->veb[i] = NULL;
11316 }
11317
11318 kfree(pf->qp_pile);
41c445ff
JB		 11319 kfree(pf->vsi);
11320
f734dfff 11321 iounmap(hw->hw_addr);
41c445ff
JB		 11322 kfree(pf);
11323 pci_release_selected_regions(pdev,
11324 pci_select_bars(pdev, IORESOURCE_MEM));
11325
11326 pci_disable_pcie_error_reporting(pdev);
11327 pci_disable_device(pdev);
11328}
11329
11330/**
11331 * i40e_pci_error_detected - warning that something funky happened in PCI land
11332 * @pdev: PCI device information struct
11333 *
11334 * Called to warn that something happened and the error handling steps
11335 * are in progress. Allows the driver to quiesce things, be ready for
11336 * remediation.
11337 **/
11338static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11339 enum pci_channel_state error)
11340{
11341 struct i40e_pf *pf = pci_get_drvdata(pdev);
11342
11343 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11344
11345 /* shutdown all operations */
9007bccd
SN		 11346 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11347 rtnl_lock();
11348 i40e_prep_for_reset(pf);
11349 rtnl_unlock();
11350 }
41c445ff
JB		 11351
11352 /* Request a slot reset */
11353 return PCI_ERS_RESULT_NEED_RESET;
11354}
11355
11356/**
11357 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11358 * @pdev: PCI device information struct
11359 *
11360 * Called to find if the driver can work with the device now that
11361 * the pci slot has been reset. If a basic connection seems good
11362 * (registers are readable and have sane content) then return a
11363 * happy little PCI_ERS_RESULT_xxx.
11364 **/
11365static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11366{
11367 struct i40e_pf *pf = pci_get_drvdata(pdev);
11368 pci_ers_result_t result;
11369 int err;
11370 u32 reg;
11371
fb43201f 11372 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11373 if (pci_enable_device_mem(pdev)) {
11374 dev_info(&pdev->dev,
11375 "Cannot re-enable PCI device after reset.\n");
11376 result = PCI_ERS_RESULT_DISCONNECT;
11377 } else {
11378 pci_set_master(pdev);
11379 pci_restore_state(pdev);
11380 pci_save_state(pdev);
11381 pci_wake_from_d3(pdev, false);
11382
11383 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11384 if (reg == 0)
11385 result = PCI_ERS_RESULT_RECOVERED;
11386 else
11387 result = PCI_ERS_RESULT_DISCONNECT;
11388 }
11389
11390 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11391 if (err) {
11392 dev_info(&pdev->dev,
11393 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11394 err);
11395 /* non-fatal, continue */
11396 }
11397
11398 return result;
11399}
11400
11401/**
11402 * i40e_pci_error_resume - restart operations after PCI error recovery
11403 * @pdev: PCI device information struct
11404 *
11405 * Called to allow the driver to bring things back up after PCI error
11406 * and/or reset recovery has finished.
11407 **/
11408static void i40e_pci_error_resume(struct pci_dev *pdev)
11409{
11410 struct i40e_pf *pf = pci_get_drvdata(pdev);
11411
fb43201f 11412 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11413 if (test_bit(__I40E_SUSPENDED, &pf->state))
11414 return;
11415
11416 rtnl_lock();
41c445ff 11417 i40e_handle_reset_warning(pf);
4c4935a9 11418 rtnl_unlock();
9007bccd
SN		 11419}
11420
11421/**
11422 * i40e_shutdown - PCI callback for shutting down
11423 * @pdev: PCI device information struct
11424 **/
11425static void i40e_shutdown(struct pci_dev *pdev)
11426{
11427 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11428 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11429
11430 set_bit(__I40E_SUSPENDED, &pf->state);
11431 set_bit(__I40E_DOWN, &pf->state);
11432 rtnl_lock();
11433 i40e_prep_for_reset(pf);
11434 rtnl_unlock();
11435
8e2773ae
SN		 11436 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11437 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11438
02b42498
CS		 11439 del_timer_sync(&pf->service_timer);
11440 cancel_work_sync(&pf->service_task);
11441 i40e_fdir_teardown(pf);
11442
11443 rtnl_lock();
11444 i40e_prep_for_reset(pf);
11445 rtnl_unlock();
11446
11447 wr32(hw, I40E_PFPM_APM,
11448 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11449 wr32(hw, I40E_PFPM_WUFC,
11450 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11451
e147758d
SN		 11452 i40e_clear_interrupt_scheme(pf);
11453
9007bccd 11454 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11455 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11456 pci_set_power_state(pdev, PCI_D3hot);
11457 }
11458}
11459
11460#ifdef CONFIG_PM
11461/**
11462 * i40e_suspend - PCI callback for moving to D3
11463 * @pdev: PCI device information struct
11464 **/
11465static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11466{
11467 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11468 struct i40e_hw *hw = &pf->hw;
059ff69b 11469 int retval = 0;
9007bccd
SN		 11470
11471 set_bit(__I40E_SUSPENDED, &pf->state);
11472 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11473
9007bccd
SN		 11474 rtnl_lock();
11475 i40e_prep_for_reset(pf);
11476 rtnl_unlock();
11477
8e2773ae
SN		 11478 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11479 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11480
b33d3b73
GR		 11481 i40e_stop_misc_vector(pf);
11482
059ff69b
GR		 11483 retval = pci_save_state(pdev);
11484 if (retval)
11485 return retval;
11486
8e2773ae 11487 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11488 pci_set_power_state(pdev, PCI_D3hot);
11489
059ff69b 11490 return retval;
41c445ff
JB		 11491}
11492
9007bccd
SN		 11493/**
11494 * i40e_resume - PCI callback for waking up from D3
11495 * @pdev: PCI device information struct
11496 **/
11497static int i40e_resume(struct pci_dev *pdev)
11498{
11499 struct i40e_pf *pf = pci_get_drvdata(pdev);
11500 u32 err;
11501
11502 pci_set_power_state(pdev, PCI_D0);
11503 pci_restore_state(pdev);
11504 /* pci_restore_state() clears dev->state_saves, so
11505 * call pci_save_state() again to restore it.
11506 */
11507 pci_save_state(pdev);
11508
11509 err = pci_enable_device_mem(pdev);
11510 if (err) {
fb43201f 11511 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11512 return err;
11513 }
11514 pci_set_master(pdev);
11515
11516 /* no wakeup events while running */
11517 pci_wake_from_d3(pdev, false);
11518
11519 /* handling the reset will rebuild the device state */
11520 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11521 clear_bit(__I40E_DOWN, &pf->state);
11522 rtnl_lock();
11523 i40e_reset_and_rebuild(pf, false);
11524 rtnl_unlock();
11525 }
11526
11527 return 0;
11528}
11529
11530#endif
41c445ff
JB		 11531static const struct pci_error_handlers i40e_err_handler = {
11532 .error_detected = i40e_pci_error_detected,
11533 .slot_reset = i40e_pci_error_slot_reset,
11534 .resume = i40e_pci_error_resume,
11535};
11536
11537static struct pci_driver i40e_driver = {
11538 .name = i40e_driver_name,
11539 .id_table = i40e_pci_tbl,
11540 .probe = i40e_probe,
11541 .remove = i40e_remove,
9007bccd
SN		 11542#ifdef CONFIG_PM
11543 .suspend = i40e_suspend,
11544 .resume = i40e_resume,
11545#endif
11546 .shutdown = i40e_shutdown,
41c445ff
JB		 11547 .err_handler = &i40e_err_handler,
11548 .sriov_configure = i40e_pci_sriov_configure,
11549};
11550
11551/**
11552 * i40e_init_module - Driver registration routine
11553 *
11554 * i40e_init_module is the first routine called when the driver is
11555 * loaded. All it does is register with the PCI subsystem.
11556 **/
11557static int __init i40e_init_module(void)
11558{
11559 pr_info("%s: %s - version %s\n", i40e_driver_name,
11560 i40e_driver_string, i40e_driver_version_str);
11561 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11562
2803b16c
JB		 11563 /* we will see if single thread per module is enough for now,
11564 * it can't be any worse than using the system workqueue which
11565 * was already single threaded
11566 */
11567 i40e_wq = create_singlethread_workqueue(i40e_driver_name);
11568 if (!i40e_wq) {
11569 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
11570 return -ENOMEM;
11571 }
11572
41c445ff
JB		 11573 i40e_dbg_init();
11574 return pci_register_driver(&i40e_driver);
11575}
11576module_init(i40e_init_module);
11577
11578/**
11579 * i40e_exit_module - Driver exit cleanup routine
11580 *
11581 * i40e_exit_module is called just before the driver is removed
11582 * from memory.
11583 **/
11584static void __exit i40e_exit_module(void)
11585{
11586 pci_unregister_driver(&i40e_driver);
2803b16c 11587 destroy_workqueue(i40e_wq);
41c445ff
JB		 11588 i40e_dbg_exit();
11589}
11590module_exit(i40e_exit_module);
Linux kernel - Deliverables
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