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i40e/i40evf: bump version to 1.4.12/1.4.8
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
b499ffb0
SV		 27#include <linux/etherdevice.h>
28#include <linux/of_net.h>
29#include <linux/pci.h>
30
31#ifdef CONFIG_SPARC
32#include <asm/idprom.h>
33#include <asm/prom.h>
34#endif
35
41c445ff
JB		 36/* Local includes */
37#include "i40e.h"
4eb3f768 38#include "i40e_diag.h"
6a899024 39#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 40#include <net/vxlan.h>
41#endif
6a899024
SA		 42#if IS_ENABLED(CONFIG_GENEVE)
43#include <net/geneve.h>
44#endif
41c445ff
JB		 45
46const char i40e_driver_name[] = "i40e";
47static const char i40e_driver_string[] =
48 "Intel(R) Ethernet Connection XL710 Network Driver";
49
50#define DRV_KERN "-k"
51
e8e724db 52#define DRV_VERSION_MAJOR 1
1c2df9e5 53#define DRV_VERSION_MINOR 4
4580de0d 54#define DRV_VERSION_BUILD 12
41c445ff
JB		 55#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
56 __stringify(DRV_VERSION_MINOR) "." \
57 __stringify(DRV_VERSION_BUILD) DRV_KERN
58const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 59static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 60
61/* a bit of forward declarations */
62static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
63static void i40e_handle_reset_warning(struct i40e_pf *pf);
64static int i40e_add_vsi(struct i40e_vsi *vsi);
65static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 66static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 67static int i40e_setup_misc_vector(struct i40e_pf *pf);
68static void i40e_determine_queue_usage(struct i40e_pf *pf);
69static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 70static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
71 u16 rss_table_size, u16 rss_size);
cbf61325 72static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 73static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 74
75/* i40e_pci_tbl - PCI Device ID Table
76 *
77 * Last entry must be all 0s
78 *
79 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
80 * Class, Class Mask, private data (not used) }
81 */
9baa3c34 82static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e 84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
ab60085e
SN		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 91 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 92 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
35dae51d
ASJ		 93 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
94 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
87e6c1d7
ASJ		 95 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
96 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
97 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 98 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
99 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 100 /* required last entry */
101 {0, }
102};
103MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
104
105#define I40E_MAX_VF_COUNT 128
106static int debug = -1;
107module_param(debug, int, 0);
108MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
109
110MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
111MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
2803b16c
JB		 115static struct workqueue_struct *i40e_wq;
116
41c445ff
JB		 117/**
118 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
119 * @hw: pointer to the HW structure
120 * @mem: ptr to mem struct to fill out
121 * @size: size of memory requested
122 * @alignment: what to align the allocation to
123 **/
124int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
125 u64 size, u32 alignment)
126{
127 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
128
129 mem->size = ALIGN(size, alignment);
130 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
131 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 132 if (!mem->va)
133 return -ENOMEM;
41c445ff 134
93bc73b8 135 return 0;
41c445ff
JB		 136}
137
138/**
139 * i40e_free_dma_mem_d - OS specific memory free for shared code
140 * @hw: pointer to the HW structure
141 * @mem: ptr to mem struct to free
142 **/
143int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
144{
145 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
146
147 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
148 mem->va = NULL;
149 mem->pa = 0;
150 mem->size = 0;
151
152 return 0;
153}
154
155/**
156 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
157 * @hw: pointer to the HW structure
158 * @mem: ptr to mem struct to fill out
159 * @size: size of memory requested
160 **/
161int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
162 u32 size)
163{
164 mem->size = size;
165 mem->va = kzalloc(size, GFP_KERNEL);
166
93bc73b8
JB		 167 if (!mem->va)
168 return -ENOMEM;
41c445ff 169
93bc73b8 170 return 0;
41c445ff
JB		 171}
172
173/**
174 * i40e_free_virt_mem_d - OS specific memory free for shared code
175 * @hw: pointer to the HW structure
176 * @mem: ptr to mem struct to free
177 **/
178int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
179{
180 /* it's ok to kfree a NULL pointer */
181 kfree(mem->va);
182 mem->va = NULL;
183 mem->size = 0;
184
185 return 0;
186}
187
188/**
189 * i40e_get_lump - find a lump of free generic resource
190 * @pf: board private structure
191 * @pile: the pile of resource to search
192 * @needed: the number of items needed
193 * @id: an owner id to stick on the items assigned
194 *
195 * Returns the base item index of the lump, or negative for error
196 *
197 * The search_hint trick and lack of advanced fit-finding only work
198 * because we're highly likely to have all the same size lump requests.
199 * Linear search time and any fragmentation should be minimal.
200 **/
201static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
202 u16 needed, u16 id)
203{
204 int ret = -ENOMEM;
ddf434ac 205 int i, j;
41c445ff
JB		 206
207 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
208 dev_info(&pf->pdev->dev,
209 "param err: pile=%p needed=%d id=0x%04x\n",
210 pile, needed, id);
211 return -EINVAL;
212 }
213
214 /* start the linear search with an imperfect hint */
215 i = pile->search_hint;
ddf434ac 216 while (i < pile->num_entries) {
41c445ff
JB		 217 /* skip already allocated entries */
218 if (pile->list[i] & I40E_PILE_VALID_BIT) {
219 i++;
220 continue;
221 }
222
223 /* do we have enough in this lump? */
224 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
225 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
226 break;
227 }
228
229 if (j == needed) {
230 /* there was enough, so assign it to the requestor */
231 for (j = 0; j < needed; j++)
232 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
233 ret = i;
234 pile->search_hint = i + j;
ddf434ac 235 break;
41c445ff 236 }
6995b36c
JB		 237
238 /* not enough, so skip over it and continue looking */
239 i += j;
41c445ff
JB		 240 }
241
242 return ret;
243}
244
245/**
246 * i40e_put_lump - return a lump of generic resource
247 * @pile: the pile of resource to search
248 * @index: the base item index
249 * @id: the owner id of the items assigned
250 *
251 * Returns the count of items in the lump
252 **/
253static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
254{
255 int valid_id = (id | I40E_PILE_VALID_BIT);
256 int count = 0;
257 int i;
258
259 if (!pile || index >= pile->num_entries)
260 return -EINVAL;
261
262 for (i = index;
263 i < pile->num_entries && pile->list[i] == valid_id;
264 i++) {
265 pile->list[i] = 0;
266 count++;
267 }
268
269 if (count && index < pile->search_hint)
270 pile->search_hint = index;
271
272 return count;
273}
274
fdf0e0bf
ASJ		 275/**
276 * i40e_find_vsi_from_id - searches for the vsi with the given id
277 * @pf - the pf structure to search for the vsi
278 * @id - id of the vsi it is searching for
279 **/
280struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
281{
282 int i;
283
284 for (i = 0; i < pf->num_alloc_vsi; i++)
285 if (pf->vsi[i] && (pf->vsi[i]->id == id))
286 return pf->vsi[i];
287
288 return NULL;
289}
290
41c445ff
JB		 291/**
292 * i40e_service_event_schedule - Schedule the service task to wake up
293 * @pf: board private structure
294 *
295 * If not already scheduled, this puts the task into the work queue
296 **/
297static void i40e_service_event_schedule(struct i40e_pf *pf)
298{
299 if (!test_bit(__I40E_DOWN, &pf->state) &&
300 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
301 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
2803b16c 302 queue_work(i40e_wq, &pf->service_task);
41c445ff
JB		 303}
304
305/**
306 * i40e_tx_timeout - Respond to a Tx Hang
307 * @netdev: network interface device structure
308 *
309 * If any port has noticed a Tx timeout, it is likely that the whole
310 * device is munged, not just the one netdev port, so go for the full
311 * reset.
312 **/
38e00438
VD		 313#ifdef I40E_FCOE
314void i40e_tx_timeout(struct net_device *netdev)
315#else
41c445ff 316static void i40e_tx_timeout(struct net_device *netdev)
38e00438 317#endif
41c445ff
JB		 318{
319 struct i40e_netdev_priv *np = netdev_priv(netdev);
320 struct i40e_vsi *vsi = np->vsi;
321 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 322 struct i40e_ring *tx_ring = NULL;
323 unsigned int i, hung_queue = 0;
324 u32 head, val;
41c445ff
JB		 325
326 pf->tx_timeout_count++;
327
b03a8c1f
KP		 328 /* find the stopped queue the same way the stack does */
329 for (i = 0; i < netdev->num_tx_queues; i++) {
330 struct netdev_queue *q;
331 unsigned long trans_start;
332
333 q = netdev_get_tx_queue(netdev, i);
334 trans_start = q->trans_start ? : netdev->trans_start;
335 if (netif_xmit_stopped(q) &&
336 time_after(jiffies,
337 (trans_start + netdev->watchdog_timeo))) {
338 hung_queue = i;
339 break;
340 }
341 }
342
343 if (i == netdev->num_tx_queues) {
344 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
345 } else {
346 /* now that we have an index, find the tx_ring struct */
347 for (i = 0; i < vsi->num_queue_pairs; i++) {
348 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
349 if (hung_queue ==
350 vsi->tx_rings[i]->queue_index) {
351 tx_ring = vsi->tx_rings[i];
352 break;
353 }
354 }
355 }
356 }
357
41c445ff 358 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 359 pf->tx_timeout_recovery_level = 1; /* reset after some time */
360 else if (time_before(jiffies,
361 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
362 return; /* don't do any new action before the next timeout */
363
364 if (tx_ring) {
365 head = i40e_get_head(tx_ring);
366 /* Read interrupt register */
367 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
368 val = rd32(&pf->hw,
369 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
370 tx_ring->vsi->base_vector - 1));
371 else
372 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
373
374 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
375 vsi->seid, hung_queue, tx_ring->next_to_clean,
376 head, tx_ring->next_to_use,
377 readl(tx_ring->tail), val);
378 }
379
41c445ff 380 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 381 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
382 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 383
384 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 385 case 1:
386 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
387 break;
388 case 2:
389 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
390 break;
391 case 3:
392 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
393 break;
394 default:
395 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 396 break;
397 }
b03a8c1f 398
41c445ff
JB		 399 i40e_service_event_schedule(pf);
400 pf->tx_timeout_recovery_level++;
401}
402
403/**
404 * i40e_release_rx_desc - Store the new tail and head values
405 * @rx_ring: ring to bump
406 * @val: new head index
407 **/
408static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
409{
410 rx_ring->next_to_use = val;
411
412 /* Force memory writes to complete before letting h/w
413 * know there are new descriptors to fetch. (Only
414 * applicable for weak-ordered memory model archs,
415 * such as IA-64).
416 */
417 wmb();
418 writel(val, rx_ring->tail);
419}
420
421/**
422 * i40e_get_vsi_stats_struct - Get System Network Statistics
423 * @vsi: the VSI we care about
424 *
425 * Returns the address of the device statistics structure.
426 * The statistics are actually updated from the service task.
427 **/
428struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
429{
430 return &vsi->net_stats;
431}
432
433/**
434 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
435 * @netdev: network interface device structure
436 *
437 * Returns the address of the device statistics structure.
438 * The statistics are actually updated from the service task.
439 **/
38e00438
VD		 440#ifdef I40E_FCOE
441struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
442 struct net_device *netdev,
443 struct rtnl_link_stats64 *stats)
444#else
41c445ff
JB		 445static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
446 struct net_device *netdev,
980e9b11 447 struct rtnl_link_stats64 *stats)
38e00438 448#endif
41c445ff
JB		 449{
450 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 451 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 452 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 453 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
454 int i;
455
bc7d338f
ASJ		 456 if (test_bit(__I40E_DOWN, &vsi->state))
457 return stats;
458
3c325ced
JB		 459 if (!vsi->tx_rings)
460 return stats;
461
980e9b11
AD		 462 rcu_read_lock();
463 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 464 u64 bytes, packets;
465 unsigned int start;
466
467 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
468 if (!tx_ring)
469 continue;
470
471 do {
57a7744e 472 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 473 packets = tx_ring->stats.packets;
474 bytes = tx_ring->stats.bytes;
57a7744e 475 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 476
477 stats->tx_packets += packets;
478 stats->tx_bytes += bytes;
479 rx_ring = &tx_ring[1];
480
481 do {
57a7744e 482 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 483 packets = rx_ring->stats.packets;
484 bytes = rx_ring->stats.bytes;
57a7744e 485 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 486
980e9b11
AD		 487 stats->rx_packets += packets;
488 stats->rx_bytes += bytes;
489 }
490 rcu_read_unlock();
491
a5282f44 492 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 493 stats->multicast = vsi_stats->multicast;
494 stats->tx_errors = vsi_stats->tx_errors;
495 stats->tx_dropped = vsi_stats->tx_dropped;
496 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 497 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 498 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
499 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 500
980e9b11 501 return stats;
41c445ff
JB		 502}
503
504/**
505 * i40e_vsi_reset_stats - Resets all stats of the given vsi
506 * @vsi: the VSI to have its stats reset
507 **/
508void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
509{
510 struct rtnl_link_stats64 *ns;
511 int i;
512
513 if (!vsi)
514 return;
515
516 ns = i40e_get_vsi_stats_struct(vsi);
517 memset(ns, 0, sizeof(*ns));
518 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
519 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
520 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 521 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 522 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 523 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 524 sizeof(vsi->rx_rings[i]->stats));
6995b36c 525 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 526 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 527 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 528 sizeof(vsi->tx_rings[i]->stats));
529 memset(&vsi->tx_rings[i]->tx_stats, 0,
530 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 531 }
8e9dca53 532 }
41c445ff
JB		 533 vsi->stat_offsets_loaded = false;
534}
535
536/**
b40c82e6 537 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 538 * @pf: the PF to be reset
539 **/
540void i40e_pf_reset_stats(struct i40e_pf *pf)
541{
e91fdf76
SN		 542 int i;
543
41c445ff
JB		 544 memset(&pf->stats, 0, sizeof(pf->stats));
545 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
546 pf->stat_offsets_loaded = false;
e91fdf76
SN		 547
548 for (i = 0; i < I40E_MAX_VEB; i++) {
549 if (pf->veb[i]) {
550 memset(&pf->veb[i]->stats, 0,
551 sizeof(pf->veb[i]->stats));
552 memset(&pf->veb[i]->stats_offsets, 0,
553 sizeof(pf->veb[i]->stats_offsets));
554 pf->veb[i]->stat_offsets_loaded = false;
555 }
556 }
41c445ff
JB		 557}
558
559/**
560 * i40e_stat_update48 - read and update a 48 bit stat from the chip
561 * @hw: ptr to the hardware info
562 * @hireg: the high 32 bit reg to read
563 * @loreg: the low 32 bit reg to read
564 * @offset_loaded: has the initial offset been loaded yet
565 * @offset: ptr to current offset value
566 * @stat: ptr to the stat
567 *
568 * Since the device stats are not reset at PFReset, they likely will not
569 * be zeroed when the driver starts. We'll save the first values read
570 * and use them as offsets to be subtracted from the raw values in order
571 * to report stats that count from zero. In the process, we also manage
572 * the potential roll-over.
573 **/
574static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
575 bool offset_loaded, u64 *offset, u64 *stat)
576{
577 u64 new_data;
578
ab60085e 579 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 580 new_data = rd32(hw, loreg);
581 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
582 } else {
583 new_data = rd64(hw, loreg);
584 }
585 if (!offset_loaded)
586 *offset = new_data;
587 if (likely(new_data >= *offset))
588 *stat = new_data - *offset;
589 else
41a1d04b 590 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 591 *stat &= 0xFFFFFFFFFFFFULL;
592}
593
594/**
595 * i40e_stat_update32 - read and update a 32 bit stat from the chip
596 * @hw: ptr to the hardware info
597 * @reg: the hw reg to read
598 * @offset_loaded: has the initial offset been loaded yet
599 * @offset: ptr to current offset value
600 * @stat: ptr to the stat
601 **/
602static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
603 bool offset_loaded, u64 *offset, u64 *stat)
604{
605 u32 new_data;
606
607 new_data = rd32(hw, reg);
608 if (!offset_loaded)
609 *offset = new_data;
610 if (likely(new_data >= *offset))
611 *stat = (u32)(new_data - *offset);
612 else
41a1d04b 613 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 614}
615
616/**
617 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
618 * @vsi: the VSI to be updated
619 **/
620void i40e_update_eth_stats(struct i40e_vsi *vsi)
621{
622 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
623 struct i40e_pf *pf = vsi->back;
624 struct i40e_hw *hw = &pf->hw;
625 struct i40e_eth_stats *oes;
626 struct i40e_eth_stats *es; /* device's eth stats */
627
628 es = &vsi->eth_stats;
629 oes = &vsi->eth_stats_offsets;
630
631 /* Gather up the stats that the hw collects */
632 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
633 vsi->stat_offsets_loaded,
634 &oes->tx_errors, &es->tx_errors);
635 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
636 vsi->stat_offsets_loaded,
637 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 638 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
639 vsi->stat_offsets_loaded,
640 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
641 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 644
645 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
646 I40E_GLV_GORCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->rx_bytes, &es->rx_bytes);
649 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
650 I40E_GLV_UPRCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->rx_unicast, &es->rx_unicast);
653 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
654 I40E_GLV_MPRCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->rx_multicast, &es->rx_multicast);
657 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
658 I40E_GLV_BPRCL(stat_idx),
659 vsi->stat_offsets_loaded,
660 &oes->rx_broadcast, &es->rx_broadcast);
661
662 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
663 I40E_GLV_GOTCL(stat_idx),
664 vsi->stat_offsets_loaded,
665 &oes->tx_bytes, &es->tx_bytes);
666 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
667 I40E_GLV_UPTCL(stat_idx),
668 vsi->stat_offsets_loaded,
669 &oes->tx_unicast, &es->tx_unicast);
670 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
671 I40E_GLV_MPTCL(stat_idx),
672 vsi->stat_offsets_loaded,
673 &oes->tx_multicast, &es->tx_multicast);
674 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
675 I40E_GLV_BPTCL(stat_idx),
676 vsi->stat_offsets_loaded,
677 &oes->tx_broadcast, &es->tx_broadcast);
678 vsi->stat_offsets_loaded = true;
679}
680
681/**
682 * i40e_update_veb_stats - Update Switch component statistics
683 * @veb: the VEB being updated
684 **/
685static void i40e_update_veb_stats(struct i40e_veb *veb)
686{
687 struct i40e_pf *pf = veb->pf;
688 struct i40e_hw *hw = &pf->hw;
689 struct i40e_eth_stats *oes;
690 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 691 struct i40e_veb_tc_stats *veb_oes;
692 struct i40e_veb_tc_stats *veb_es;
693 int i, idx = 0;
41c445ff
JB		 694
695 idx = veb->stats_idx;
696 es = &veb->stats;
697 oes = &veb->stats_offsets;
fe860afb
NP		 698 veb_es = &veb->tc_stats;
699 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 700
701 /* Gather up the stats that the hw collects */
702 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
703 veb->stat_offsets_loaded,
704 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 705 if (hw->revision_id > 0)
706 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
707 veb->stat_offsets_loaded,
708 &oes->rx_unknown_protocol,
709 &es->rx_unknown_protocol);
41c445ff
JB		 710 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
711 veb->stat_offsets_loaded,
712 &oes->rx_bytes, &es->rx_bytes);
713 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
714 veb->stat_offsets_loaded,
715 &oes->rx_unicast, &es->rx_unicast);
716 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
717 veb->stat_offsets_loaded,
718 &oes->rx_multicast, &es->rx_multicast);
719 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
720 veb->stat_offsets_loaded,
721 &oes->rx_broadcast, &es->rx_broadcast);
722
723 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
724 veb->stat_offsets_loaded,
725 &oes->tx_bytes, &es->tx_bytes);
726 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
727 veb->stat_offsets_loaded,
728 &oes->tx_unicast, &es->tx_unicast);
729 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
730 veb->stat_offsets_loaded,
731 &oes->tx_multicast, &es->tx_multicast);
732 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
733 veb->stat_offsets_loaded,
734 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 735 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
736 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
737 I40E_GLVEBTC_RPCL(i, idx),
738 veb->stat_offsets_loaded,
739 &veb_oes->tc_rx_packets[i],
740 &veb_es->tc_rx_packets[i]);
741 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
742 I40E_GLVEBTC_RBCL(i, idx),
743 veb->stat_offsets_loaded,
744 &veb_oes->tc_rx_bytes[i],
745 &veb_es->tc_rx_bytes[i]);
746 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
747 I40E_GLVEBTC_TPCL(i, idx),
748 veb->stat_offsets_loaded,
749 &veb_oes->tc_tx_packets[i],
750 &veb_es->tc_tx_packets[i]);
751 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
752 I40E_GLVEBTC_TBCL(i, idx),
753 veb->stat_offsets_loaded,
754 &veb_oes->tc_tx_bytes[i],
755 &veb_es->tc_tx_bytes[i]);
756 }
41c445ff
JB		 757 veb->stat_offsets_loaded = true;
758}
759
38e00438
VD		 760#ifdef I40E_FCOE
761/**
762 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
763 * @vsi: the VSI that is capable of doing FCoE
764 **/
765static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
766{
767 struct i40e_pf *pf = vsi->back;
768 struct i40e_hw *hw = &pf->hw;
769 struct i40e_fcoe_stats *ofs;
770 struct i40e_fcoe_stats *fs; /* device's eth stats */
771 int idx;
772
773 if (vsi->type != I40E_VSI_FCOE)
774 return;
775
776 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
777 fs = &vsi->fcoe_stats;
778 ofs = &vsi->fcoe_stats_offsets;
779
780 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
781 vsi->fcoe_stat_offsets_loaded,
782 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
783 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
784 vsi->fcoe_stat_offsets_loaded,
785 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
786 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
787 vsi->fcoe_stat_offsets_loaded,
788 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
789 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
790 vsi->fcoe_stat_offsets_loaded,
791 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
792 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
793 vsi->fcoe_stat_offsets_loaded,
794 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
795 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
796 vsi->fcoe_stat_offsets_loaded,
797 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
798 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
799 vsi->fcoe_stat_offsets_loaded,
800 &ofs->fcoe_last_error, &fs->fcoe_last_error);
801 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
802 vsi->fcoe_stat_offsets_loaded,
803 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
804
805 vsi->fcoe_stat_offsets_loaded = true;
806}
807
808#endif
41c445ff 809/**
7812fddc 810 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 811 * @vsi: the VSI to be updated
812 *
813 * There are a few instances where we store the same stat in a
814 * couple of different structs. This is partly because we have
815 * the netdev stats that need to be filled out, which is slightly
816 * different from the "eth_stats" defined by the chip and used in
7812fddc 817 * VF communications. We sort it out here.
41c445ff 818 **/
7812fddc 819static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 820{
821 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 822 struct rtnl_link_stats64 *ons;
823 struct rtnl_link_stats64 *ns; /* netdev stats */
824 struct i40e_eth_stats *oes;
825 struct i40e_eth_stats *es; /* device's eth stats */
826 u32 tx_restart, tx_busy;
bf00b376 827 struct i40e_ring *p;
41c445ff 828 u32 rx_page, rx_buf;
bf00b376
AA		 829 u64 bytes, packets;
830 unsigned int start;
2fc3d715 831 u64 tx_linearize;
164c9f54 832 u64 tx_force_wb;
41c445ff
JB		 833 u64 rx_p, rx_b;
834 u64 tx_p, tx_b;
41c445ff
JB		 835 u16 q;
836
837 if (test_bit(__I40E_DOWN, &vsi->state) ||
838 test_bit(__I40E_CONFIG_BUSY, &pf->state))
839 return;
840
841 ns = i40e_get_vsi_stats_struct(vsi);
842 ons = &vsi->net_stats_offsets;
843 es = &vsi->eth_stats;
844 oes = &vsi->eth_stats_offsets;
845
846 /* Gather up the netdev and vsi stats that the driver collects
847 * on the fly during packet processing
848 */
849 rx_b = rx_p = 0;
850 tx_b = tx_p = 0;
164c9f54 851 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
41c445ff
JB		 852 rx_page = 0;
853 rx_buf = 0;
980e9b11 854 rcu_read_lock();
41c445ff 855 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 856 /* locate Tx ring */
857 p = ACCESS_ONCE(vsi->tx_rings[q]);
858
859 do {
57a7744e 860 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 861 packets = p->stats.packets;
862 bytes = p->stats.bytes;
57a7744e 863 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 864 tx_b += bytes;
865 tx_p += packets;
866 tx_restart += p->tx_stats.restart_queue;
867 tx_busy += p->tx_stats.tx_busy;
2fc3d715 868 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 869 tx_force_wb += p->tx_stats.tx_force_wb;
41c445ff 870
980e9b11
AD		 871 /* Rx queue is part of the same block as Tx queue */
872 p = &p[1];
873 do {
57a7744e 874 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 875 packets = p->stats.packets;
876 bytes = p->stats.bytes;
57a7744e 877 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 878 rx_b += bytes;
879 rx_p += packets;
420136cc
MW		 880 rx_buf += p->rx_stats.alloc_buff_failed;
881 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 882 }
980e9b11 883 rcu_read_unlock();
41c445ff
JB		 884 vsi->tx_restart = tx_restart;
885 vsi->tx_busy = tx_busy;
2fc3d715 886 vsi->tx_linearize = tx_linearize;
164c9f54 887 vsi->tx_force_wb = tx_force_wb;
41c445ff
JB		 888 vsi->rx_page_failed = rx_page;
889 vsi->rx_buf_failed = rx_buf;
890
891 ns->rx_packets = rx_p;
892 ns->rx_bytes = rx_b;
893 ns->tx_packets = tx_p;
894 ns->tx_bytes = tx_b;
895
41c445ff 896 /* update netdev stats from eth stats */
7812fddc 897 i40e_update_eth_stats(vsi);
41c445ff
JB		 898 ons->tx_errors = oes->tx_errors;
899 ns->tx_errors = es->tx_errors;
900 ons->multicast = oes->rx_multicast;
901 ns->multicast = es->rx_multicast;
41a9e55c
SN		 902 ons->rx_dropped = oes->rx_discards;
903 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 904 ons->tx_dropped = oes->tx_discards;
905 ns->tx_dropped = es->tx_discards;
906
7812fddc 907 /* pull in a couple PF stats if this is the main vsi */
41c445ff 908 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 909 ns->rx_crc_errors = pf->stats.crc_errors;
910 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
911 ns->rx_length_errors = pf->stats.rx_length_errors;
912 }
913}
41c445ff 914
7812fddc 915/**
b40c82e6 916 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 917 * @pf: the PF to be updated
918 **/
919static void i40e_update_pf_stats(struct i40e_pf *pf)
920{
921 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
922 struct i40e_hw_port_stats *nsd = &pf->stats;
923 struct i40e_hw *hw = &pf->hw;
924 u32 val;
925 int i;
41c445ff 926
7812fddc
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
928 I40E_GLPRT_GORCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
931 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
932 I40E_GLPRT_GOTCL(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
935 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
936 pf->stat_offsets_loaded,
937 &osd->eth.rx_discards,
938 &nsd->eth.rx_discards);
532d283d
SN		 939 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
940 I40E_GLPRT_UPRCL(hw->port),
941 pf->stat_offsets_loaded,
942 &osd->eth.rx_unicast,
943 &nsd->eth.rx_unicast);
7812fddc
SN		 944 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
945 I40E_GLPRT_MPRCL(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->eth.rx_multicast,
948 &nsd->eth.rx_multicast);
532d283d
SN		 949 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
950 I40E_GLPRT_BPRCL(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->eth.rx_broadcast,
953 &nsd->eth.rx_broadcast);
954 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
955 I40E_GLPRT_UPTCL(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->eth.tx_unicast,
958 &nsd->eth.tx_unicast);
959 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
960 I40E_GLPRT_MPTCL(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->eth.tx_multicast,
963 &nsd->eth.tx_multicast);
964 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
965 I40E_GLPRT_BPTCL(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->eth.tx_broadcast,
968 &nsd->eth.tx_broadcast);
41c445ff 969
7812fddc
SN		 970 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->tx_dropped_link_down,
973 &nsd->tx_dropped_link_down);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->crc_errors, &nsd->crc_errors);
41c445ff 978
7812fddc
SN		 979 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
980 pf->stat_offsets_loaded,
981 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 982
7812fddc
SN		 983 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->mac_local_faults,
986 &nsd->mac_local_faults);
987 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->mac_remote_faults,
990 &nsd->mac_remote_faults);
41c445ff 991
7812fddc
SN		 992 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->rx_length_errors,
995 &nsd->rx_length_errors);
41c445ff 996
7812fddc
SN		 997 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
998 pf->stat_offsets_loaded,
999 &osd->link_xon_rx, &nsd->link_xon_rx);
1000 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1001 pf->stat_offsets_loaded,
1002 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 1003 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1004 pf->stat_offsets_loaded,
1005 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 1006 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1007 pf->stat_offsets_loaded,
1008 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1009
7812fddc 1010 for (i = 0; i < 8; i++) {
95db239f
NP		 1011 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1012 pf->stat_offsets_loaded,
1013 &osd->priority_xoff_rx[i],
1014 &nsd->priority_xoff_rx[i]);
7812fddc 1015 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1016 pf->stat_offsets_loaded,
7812fddc
SN		 1017 &osd->priority_xon_rx[i],
1018 &nsd->priority_xon_rx[i]);
1019 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1020 pf->stat_offsets_loaded,
7812fddc
SN		 1021 &osd->priority_xon_tx[i],
1022 &nsd->priority_xon_tx[i]);
1023 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1024 pf->stat_offsets_loaded,
7812fddc
SN		 1025 &osd->priority_xoff_tx[i],
1026 &nsd->priority_xoff_tx[i]);
1027 i40e_stat_update32(hw,
1028 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1029 pf->stat_offsets_loaded,
7812fddc
SN		 1030 &osd->priority_xon_2_xoff[i],
1031 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1032 }
1033
7812fddc
SN		 1034 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1035 I40E_GLPRT_PRC64L(hw->port),
1036 pf->stat_offsets_loaded,
1037 &osd->rx_size_64, &nsd->rx_size_64);
1038 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1039 I40E_GLPRT_PRC127L(hw->port),
1040 pf->stat_offsets_loaded,
1041 &osd->rx_size_127, &nsd->rx_size_127);
1042 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1043 I40E_GLPRT_PRC255L(hw->port),
1044 pf->stat_offsets_loaded,
1045 &osd->rx_size_255, &nsd->rx_size_255);
1046 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1047 I40E_GLPRT_PRC511L(hw->port),
1048 pf->stat_offsets_loaded,
1049 &osd->rx_size_511, &nsd->rx_size_511);
1050 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1051 I40E_GLPRT_PRC1023L(hw->port),
1052 pf->stat_offsets_loaded,
1053 &osd->rx_size_1023, &nsd->rx_size_1023);
1054 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1055 I40E_GLPRT_PRC1522L(hw->port),
1056 pf->stat_offsets_loaded,
1057 &osd->rx_size_1522, &nsd->rx_size_1522);
1058 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1059 I40E_GLPRT_PRC9522L(hw->port),
1060 pf->stat_offsets_loaded,
1061 &osd->rx_size_big, &nsd->rx_size_big);
1062
1063 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1064 I40E_GLPRT_PTC64L(hw->port),
1065 pf->stat_offsets_loaded,
1066 &osd->tx_size_64, &nsd->tx_size_64);
1067 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1068 I40E_GLPRT_PTC127L(hw->port),
1069 pf->stat_offsets_loaded,
1070 &osd->tx_size_127, &nsd->tx_size_127);
1071 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1072 I40E_GLPRT_PTC255L(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->tx_size_255, &nsd->tx_size_255);
1075 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1076 I40E_GLPRT_PTC511L(hw->port),
1077 pf->stat_offsets_loaded,
1078 &osd->tx_size_511, &nsd->tx_size_511);
1079 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1080 I40E_GLPRT_PTC1023L(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->tx_size_1023, &nsd->tx_size_1023);
1083 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1084 I40E_GLPRT_PTC1522L(hw->port),
1085 pf->stat_offsets_loaded,
1086 &osd->tx_size_1522, &nsd->tx_size_1522);
1087 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1088 I40E_GLPRT_PTC9522L(hw->port),
1089 pf->stat_offsets_loaded,
1090 &osd->tx_size_big, &nsd->tx_size_big);
1091
1092 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1093 pf->stat_offsets_loaded,
1094 &osd->rx_undersize, &nsd->rx_undersize);
1095 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1096 pf->stat_offsets_loaded,
1097 &osd->rx_fragments, &nsd->rx_fragments);
1098 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1099 pf->stat_offsets_loaded,
1100 &osd->rx_oversize, &nsd->rx_oversize);
1101 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1102 pf->stat_offsets_loaded,
1103 &osd->rx_jabber, &nsd->rx_jabber);
1104
433c47de 1105 /* FDIR stats */
0bf4b1b0
ASJ		 1106 i40e_stat_update32(hw,
1107 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1108 pf->stat_offsets_loaded,
1109 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1110 i40e_stat_update32(hw,
1111 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1112 pf->stat_offsets_loaded,
1113 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1114 i40e_stat_update32(hw,
1115 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1116 pf->stat_offsets_loaded,
1117 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1118
7812fddc
SN		 1119 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1120 nsd->tx_lpi_status =
1121 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1122 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1123 nsd->rx_lpi_status =
1124 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1125 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1126 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1127 pf->stat_offsets_loaded,
1128 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1129 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1130 pf->stat_offsets_loaded,
1131 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1132
d0389e51
ASJ		 1133 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1134 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1135 nsd->fd_sb_status = true;
1136 else
1137 nsd->fd_sb_status = false;
1138
1139 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1140 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1141 nsd->fd_atr_status = true;
1142 else
1143 nsd->fd_atr_status = false;
1144
41c445ff
JB		 1145 pf->stat_offsets_loaded = true;
1146}
1147
7812fddc
SN		 1148/**
1149 * i40e_update_stats - Update the various statistics counters.
1150 * @vsi: the VSI to be updated
1151 *
1152 * Update the various stats for this VSI and its related entities.
1153 **/
1154void i40e_update_stats(struct i40e_vsi *vsi)
1155{
1156 struct i40e_pf *pf = vsi->back;
1157
1158 if (vsi == pf->vsi[pf->lan_vsi])
1159 i40e_update_pf_stats(pf);
1160
1161 i40e_update_vsi_stats(vsi);
38e00438
VD		 1162#ifdef I40E_FCOE
1163 i40e_update_fcoe_stats(vsi);
1164#endif
7812fddc
SN		 1165}
1166
41c445ff
JB		 1167/**
1168 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1169 * @vsi: the VSI to be searched
1170 * @macaddr: the MAC address
1171 * @vlan: the vlan
b40c82e6 1172 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1173 * @is_netdev: make sure its a netdev filter, else doesn't matter
1174 *
1175 * Returns ptr to the filter object or NULL
1176 **/
1177static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1178 u8 *macaddr, s16 vlan,
1179 bool is_vf, bool is_netdev)
1180{
1181 struct i40e_mac_filter *f;
1182
1183 if (!vsi || !macaddr)
1184 return NULL;
1185
1186 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1187 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1188 (vlan == f->vlan) &&
1189 (!is_vf || f->is_vf) &&
1190 (!is_netdev || f->is_netdev))
1191 return f;
1192 }
1193 return NULL;
1194}
1195
1196/**
1197 * i40e_find_mac - Find a mac addr in the macvlan filters list
1198 * @vsi: the VSI to be searched
1199 * @macaddr: the MAC address we are searching for
b40c82e6 1200 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1201 * @is_netdev: make sure its a netdev filter, else doesn't matter
1202 *
1203 * Returns the first filter with the provided MAC address or NULL if
1204 * MAC address was not found
1205 **/
1206struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1207 bool is_vf, bool is_netdev)
1208{
1209 struct i40e_mac_filter *f;
1210
1211 if (!vsi || !macaddr)
1212 return NULL;
1213
1214 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1215 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1216 (!is_vf || f->is_vf) &&
1217 (!is_netdev || f->is_netdev))
1218 return f;
1219 }
1220 return NULL;
1221}
1222
1223/**
1224 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1225 * @vsi: the VSI to be searched
1226 *
1227 * Returns true if VSI is in vlan mode or false otherwise
1228 **/
1229bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1230{
1231 struct i40e_mac_filter *f;
1232
1233 /* Only -1 for all the filters denotes not in vlan mode
1234 * so we have to go through all the list in order to make sure
1235 */
1236 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1237 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1238 return true;
1239 }
1240
1241 return false;
1242}
1243
1244/**
1245 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1246 * @vsi: the VSI to be searched
1247 * @macaddr: the mac address to be filtered
b40c82e6 1248 * @is_vf: true if it is a VF
41c445ff
JB		 1249 * @is_netdev: true if it is a netdev
1250 *
1251 * Goes through all the macvlan filters and adds a
1252 * macvlan filter for each unique vlan that already exists
1253 *
1254 * Returns first filter found on success, else NULL
1255 **/
1256struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1257 bool is_vf, bool is_netdev)
1258{
1259 struct i40e_mac_filter *f;
1260
1261 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1262 if (vsi->info.pvid)
1263 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1264 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1265 is_vf, is_netdev)) {
1266 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1267 is_vf, is_netdev))
41c445ff
JB		 1268 return NULL;
1269 }
1270 }
1271
1272 return list_first_entry_or_null(&vsi->mac_filter_list,
1273 struct i40e_mac_filter, list);
1274}
1275
b36e9ab5
MW		 1276/**
1277 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1278 * @vsi: the VSI to be searched
1279 * @macaddr: the mac address to be removed
1280 * @is_vf: true if it is a VF
1281 * @is_netdev: true if it is a netdev
1282 *
1283 * Removes a given MAC address from a VSI, regardless of VLAN
1284 *
1285 * Returns 0 for success, or error
1286 **/
1287int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1288 bool is_vf, bool is_netdev)
1289{
1290 struct i40e_mac_filter *f = NULL;
1291 int changed = 0;
1292
1293 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1294 "Missing mac_filter_list_lock\n");
1295 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1296 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1297 (is_vf == f->is_vf) &&
1298 (is_netdev == f->is_netdev)) {
1299 f->counter--;
1300 f->changed = true;
1301 changed = 1;
1302 }
1303 }
1304 if (changed) {
1305 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1306 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1307 return 0;
1308 }
1309 return -ENOENT;
1310}
1311
8c27d42e
GR		 1312/**
1313 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1314 * @vsi: the PF Main VSI - inappropriate for any other VSI
1315 * @macaddr: the MAC address
30650cc5
SN		 1316 *
1317 * Some older firmware configurations set up a default promiscuous VLAN
1318 * filter that needs to be removed.
8c27d42e 1319 **/
30650cc5 1320static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1321{
1322 struct i40e_aqc_remove_macvlan_element_data element;
1323 struct i40e_pf *pf = vsi->back;
f1c7e72e 1324 i40e_status ret;
8c27d42e
GR		 1325
1326 /* Only appropriate for the PF main VSI */
1327 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1328 return -EINVAL;
8c27d42e 1329
30650cc5 1330 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1331 ether_addr_copy(element.mac_addr, macaddr);
1332 element.vlan_tag = 0;
1333 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1334 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1335 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1336 if (ret)
30650cc5
SN		 1337 return -ENOENT;
1338
1339 return 0;
8c27d42e
GR		 1340}
1341
41c445ff
JB		 1342/**
1343 * i40e_add_filter - Add a mac/vlan filter to the VSI
1344 * @vsi: the VSI to be searched
1345 * @macaddr: the MAC address
1346 * @vlan: the vlan
b40c82e6 1347 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1348 * @is_netdev: make sure its a netdev filter, else doesn't matter
1349 *
1350 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1351 *
1352 * NOTE: This function is expected to be called with mac_filter_list_lock
1353 * being held.
41c445ff
JB		 1354 **/
1355struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1356 u8 *macaddr, s16 vlan,
1357 bool is_vf, bool is_netdev)
1358{
1359 struct i40e_mac_filter *f;
1360
1361 if (!vsi || !macaddr)
1362 return NULL;
1363
1364 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1365 if (!f) {
1366 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1367 if (!f)
1368 goto add_filter_out;
1369
9a173901 1370 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1371 f->vlan = vlan;
1372 f->changed = true;
1373
1374 INIT_LIST_HEAD(&f->list);
04d5a21d 1375 list_add_tail(&f->list, &vsi->mac_filter_list);
41c445ff
JB		 1376 }
1377
1378 /* increment counter and add a new flag if needed */
1379 if (is_vf) {
1380 if (!f->is_vf) {
1381 f->is_vf = true;
1382 f->counter++;
1383 }
1384 } else if (is_netdev) {
1385 if (!f->is_netdev) {
1386 f->is_netdev = true;
1387 f->counter++;
1388 }
1389 } else {
1390 f->counter++;
1391 }
1392
1393 /* changed tells sync_filters_subtask to
1394 * push the filter down to the firmware
1395 */
1396 if (f->changed) {
1397 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1398 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1399 }
1400
1401add_filter_out:
1402 return f;
1403}
1404
1405/**
1406 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1407 * @vsi: the VSI to be searched
1408 * @macaddr: the MAC address
1409 * @vlan: the vlan
b40c82e6 1410 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1411 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1412 *
1413 * NOTE: This function is expected to be called with mac_filter_list_lock
1414 * being held.
41c445ff
JB		 1415 **/
1416void i40e_del_filter(struct i40e_vsi *vsi,
1417 u8 *macaddr, s16 vlan,
1418 bool is_vf, bool is_netdev)
1419{
1420 struct i40e_mac_filter *f;
1421
1422 if (!vsi || !macaddr)
1423 return;
1424
1425 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1426 if (!f || f->counter == 0)
1427 return;
1428
1429 if (is_vf) {
1430 if (f->is_vf) {
1431 f->is_vf = false;
1432 f->counter--;
1433 }
1434 } else if (is_netdev) {
1435 if (f->is_netdev) {
1436 f->is_netdev = false;
1437 f->counter--;
1438 }
1439 } else {
b40c82e6 1440 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1441 int min_f = 0;
6995b36c 1442
41c445ff
JB		 1443 min_f += (f->is_vf ? 1 : 0);
1444 min_f += (f->is_netdev ? 1 : 0);
1445
1446 if (f->counter > min_f)
1447 f->counter--;
1448 }
1449
1450 /* counter == 0 tells sync_filters_subtask to
1451 * remove the filter from the firmware's list
1452 */
1453 if (f->counter == 0) {
1454 f->changed = true;
1455 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1456 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1457 }
1458}
1459
1460/**
1461 * i40e_set_mac - NDO callback to set mac address
1462 * @netdev: network interface device structure
1463 * @p: pointer to an address structure
1464 *
1465 * Returns 0 on success, negative on failure
1466 **/
38e00438
VD		 1467#ifdef I40E_FCOE
1468int i40e_set_mac(struct net_device *netdev, void *p)
1469#else
41c445ff 1470static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1471#endif
41c445ff
JB		 1472{
1473 struct i40e_netdev_priv *np = netdev_priv(netdev);
1474 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1475 struct i40e_pf *pf = vsi->back;
1476 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1477 struct sockaddr *addr = p;
1478 struct i40e_mac_filter *f;
1479
1480 if (!is_valid_ether_addr(addr->sa_data))
1481 return -EADDRNOTAVAIL;
1482
30650cc5
SN		 1483 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1484 netdev_info(netdev, "already using mac address %pM\n",
1485 addr->sa_data);
1486 return 0;
1487 }
41c445ff 1488
80f6428f
ASJ		 1489 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1490 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1491 return -EADDRNOTAVAIL;
1492
30650cc5
SN		 1493 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1494 netdev_info(netdev, "returning to hw mac address %pM\n",
1495 hw->mac.addr);
1496 else
1497 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1498
41c445ff
JB		 1499 if (vsi->type == I40E_VSI_MAIN) {
1500 i40e_status ret;
6995b36c 1501
41c445ff 1502 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1503 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1504 addr->sa_data, NULL);
1505 if (ret) {
1506 netdev_info(netdev,
1507 "Addr change for Main VSI failed: %d\n",
1508 ret);
1509 return -EADDRNOTAVAIL;
1510 }
41c445ff
JB		 1511 }
1512
30650cc5
SN		 1513 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1514 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1515
30650cc5
SN		 1516 memset(&element, 0, sizeof(element));
1517 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1518 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1519 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1520 } else {
21659035 1521 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1522 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1523 false, false);
21659035 1524 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1525 }
41c445ff 1526
30650cc5
SN		 1527 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1528 struct i40e_aqc_add_macvlan_element_data element;
1529
1530 memset(&element, 0, sizeof(element));
1531 ether_addr_copy(element.mac_addr, hw->mac.addr);
1532 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1533 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1534 } else {
21659035 1535 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1536 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1537 false, false);
1538 if (f)
1539 f->is_laa = true;
21659035 1540 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1541 }
1542
30650cc5 1543 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b 1544
c53934c6
JB		 1545 /* schedule our worker thread which will take care of
1546 * applying the new filter changes
1547 */
1548 i40e_service_event_schedule(vsi->back);
1549 return 0;
41c445ff
JB		 1550}
1551
1552/**
1553 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1554 * @vsi: the VSI being setup
1555 * @ctxt: VSI context structure
1556 * @enabled_tc: Enabled TCs bitmap
1557 * @is_add: True if called before Add VSI
1558 *
1559 * Setup VSI queue mapping for enabled traffic classes.
1560 **/
38e00438
VD		 1561#ifdef I40E_FCOE
1562void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1563 struct i40e_vsi_context *ctxt,
1564 u8 enabled_tc,
1565 bool is_add)
1566#else
41c445ff
JB		 1567static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1568 struct i40e_vsi_context *ctxt,
1569 u8 enabled_tc,
1570 bool is_add)
38e00438 1571#endif
41c445ff
JB		 1572{
1573 struct i40e_pf *pf = vsi->back;
1574 u16 sections = 0;
1575 u8 netdev_tc = 0;
1576 u16 numtc = 0;
1577 u16 qcount;
1578 u8 offset;
1579 u16 qmap;
1580 int i;
4e3b35b0 1581 u16 num_tc_qps = 0;
41c445ff
JB		 1582
1583 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1584 offset = 0;
1585
1586 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1587 /* Find numtc from enabled TC bitmap */
1588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1589 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1590 numtc++;
1591 }
1592 if (!numtc) {
1593 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1594 numtc = 1;
1595 }
1596 } else {
1597 /* At least TC0 is enabled in case of non-DCB case */
1598 numtc = 1;
1599 }
1600
1601 vsi->tc_config.numtc = numtc;
1602 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1603 /* Number of queues per enabled TC */
7f9ff476
AS		 1604 /* In MFP case we can have a much lower count of MSIx
1605 * vectors available and so we need to lower the used
1606 * q count.
1607 */
26cdc443
ASJ		 1608 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1609 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1610 else
1611 qcount = vsi->alloc_queue_pairs;
7f9ff476 1612 num_tc_qps = qcount / numtc;
e25d00b8 1613 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1614
1615 /* Setup queue offset/count for all TCs for given VSI */
1616 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1617 /* See if the given TC is enabled for the given VSI */
75f5cea9 1618 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1619 /* TC is enabled */
41c445ff
JB		 1620 int pow, num_qps;
1621
41c445ff
JB		 1622 switch (vsi->type) {
1623 case I40E_VSI_MAIN:
acd65448
HZ		 1624 qcount = min_t(int, pf->alloc_rss_size,
1625 num_tc_qps);
41c445ff 1626 break;
38e00438
VD		 1627#ifdef I40E_FCOE
1628 case I40E_VSI_FCOE:
1629 qcount = num_tc_qps;
1630 break;
1631#endif
41c445ff
JB		 1632 case I40E_VSI_FDIR:
1633 case I40E_VSI_SRIOV:
1634 case I40E_VSI_VMDQ2:
1635 default:
4e3b35b0 1636 qcount = num_tc_qps;
41c445ff
JB		 1637 WARN_ON(i != 0);
1638 break;
1639 }
4e3b35b0
NP		 1640 vsi->tc_config.tc_info[i].qoffset = offset;
1641 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1642
1e200e4a 1643 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1644 num_qps = qcount;
41c445ff 1645 pow = 0;
41a1d04b 1646 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1647 pow++;
1648 num_qps >>= 1;
1649 }
1650
1651 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1652 qmap =
1653 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1654 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1655
4e3b35b0 1656 offset += qcount;
41c445ff
JB		 1657 } else {
1658 /* TC is not enabled so set the offset to
1659 * default queue and allocate one queue
1660 * for the given TC.
1661 */
1662 vsi->tc_config.tc_info[i].qoffset = 0;
1663 vsi->tc_config.tc_info[i].qcount = 1;
1664 vsi->tc_config.tc_info[i].netdev_tc = 0;
1665
1666 qmap = 0;
1667 }
1668 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1669 }
1670
1671 /* Set actual Tx/Rx queue pairs */
1672 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1673 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1674 if (vsi->req_queue_pairs > 0)
1675 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1676 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1677 vsi->num_queue_pairs = pf->num_lan_msix;
1678 }
41c445ff
JB		 1679
1680 /* Scheduler section valid can only be set for ADD VSI */
1681 if (is_add) {
1682 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1683
1684 ctxt->info.up_enable_bits = enabled_tc;
1685 }
1686 if (vsi->type == I40E_VSI_SRIOV) {
1687 ctxt->info.mapping_flags |=
1688 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1689 for (i = 0; i < vsi->num_queue_pairs; i++)
1690 ctxt->info.queue_mapping[i] =
1691 cpu_to_le16(vsi->base_queue + i);
1692 } else {
1693 ctxt->info.mapping_flags |=
1694 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1695 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1696 }
1697 ctxt->info.valid_sections |= cpu_to_le16(sections);
1698}
1699
1700/**
1701 * i40e_set_rx_mode - NDO callback to set the netdev filters
1702 * @netdev: network interface device structure
1703 **/
38e00438
VD		 1704#ifdef I40E_FCOE
1705void i40e_set_rx_mode(struct net_device *netdev)
1706#else
41c445ff 1707static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1708#endif
41c445ff
JB		 1709{
1710 struct i40e_netdev_priv *np = netdev_priv(netdev);
1711 struct i40e_mac_filter *f, *ftmp;
1712 struct i40e_vsi *vsi = np->vsi;
1713 struct netdev_hw_addr *uca;
1714 struct netdev_hw_addr *mca;
1715 struct netdev_hw_addr *ha;
1716
21659035
KP		 1717 spin_lock_bh(&vsi->mac_filter_list_lock);
1718
41c445ff
JB		 1719 /* add addr if not already in the filter list */
1720 netdev_for_each_uc_addr(uca, netdev) {
1721 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1722 if (i40e_is_vsi_in_vlan(vsi))
1723 i40e_put_mac_in_vlan(vsi, uca->addr,
1724 false, true);
1725 else
1726 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1727 false, true);
1728 }
1729 }
1730
1731 netdev_for_each_mc_addr(mca, netdev) {
1732 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1733 if (i40e_is_vsi_in_vlan(vsi))
1734 i40e_put_mac_in_vlan(vsi, mca->addr,
1735 false, true);
1736 else
1737 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1738 false, true);
1739 }
1740 }
1741
1742 /* remove filter if not in netdev list */
1743 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1744
1745 if (!f->is_netdev)
1746 continue;
1747
2f41f335
SN		 1748 netdev_for_each_mc_addr(mca, netdev)
1749 if (ether_addr_equal(mca->addr, f->macaddr))
1750 goto bottom_of_search_loop;
41c445ff 1751
2f41f335
SN		 1752 netdev_for_each_uc_addr(uca, netdev)
1753 if (ether_addr_equal(uca->addr, f->macaddr))
1754 goto bottom_of_search_loop;
1755
1756 for_each_dev_addr(netdev, ha)
1757 if (ether_addr_equal(ha->addr, f->macaddr))
1758 goto bottom_of_search_loop;
1759
1760 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1761 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1762
1763bottom_of_search_loop:
1764 continue;
41c445ff 1765 }
21659035 1766 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1767
1768 /* check for other flag changes */
1769 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1770 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1771 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1772 }
c53934c6
JB		 1773
1774 /* schedule our worker thread which will take care of
1775 * applying the new filter changes
1776 */
1777 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1778}
1779
21659035
KP		 1780/**
1781 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1782 * @src: source MAC filter entry to be clones
1783 *
1784 * Returns the pointer to newly cloned MAC filter entry or NULL
1785 * in case of error
1786 **/
1787static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1788 struct i40e_mac_filter *src)
1789{
1790 struct i40e_mac_filter *f;
1791
1792 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1793 if (!f)
1794 return NULL;
1795 *f = *src;
1796
1797 INIT_LIST_HEAD(&f->list);
1798
1799 return f;
1800}
1801
1802/**
1803 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1804 * @vsi: pointer to vsi struct
1805 * @from: Pointer to list which contains MAC filter entries - changes to
1806 * those entries needs to be undone.
1807 *
1808 * MAC filter entries from list were slated to be removed from device.
1809 **/
1810static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1811 struct list_head *from)
1812{
1813 struct i40e_mac_filter *f, *ftmp;
1814
1815 list_for_each_entry_safe(f, ftmp, from, list) {
1816 f->changed = true;
1817 /* Move the element back into MAC filter list*/
1818 list_move_tail(&f->list, &vsi->mac_filter_list);
1819 }
1820}
1821
1822/**
1823 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1824 * @vsi: pointer to vsi struct
1825 *
1826 * MAC filter entries from list were slated to be added from device.
1827 **/
1828static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1829{
1830 struct i40e_mac_filter *f, *ftmp;
1831
1832 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1833 if (!f->changed && f->counter)
1834 f->changed = true;
1835 }
1836}
1837
1838/**
1839 * i40e_cleanup_add_list - Deletes the element from add list and release
1840 * memory
1841 * @add_list: Pointer to list which contains MAC filter entries
1842 **/
1843static void i40e_cleanup_add_list(struct list_head *add_list)
1844{
1845 struct i40e_mac_filter *f, *ftmp;
1846
1847 list_for_each_entry_safe(f, ftmp, add_list, list) {
1848 list_del(&f->list);
1849 kfree(f);
1850 }
1851}
1852
41c445ff
JB		 1853/**
1854 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1855 * @vsi: ptr to the VSI
1856 *
1857 * Push any outstanding VSI filter changes through the AdminQ.
1858 *
1859 * Returns 0 or error value
1860 **/
17652c63 1861int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1862{
21659035
KP		 1863 struct list_head tmp_del_list, tmp_add_list;
1864 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1865 bool promisc_forced_on = false;
1866 bool add_happened = false;
1867 int filter_list_len = 0;
1868 u32 changed_flags = 0;
ea02e90b 1869 i40e_status aq_ret = 0;
21659035 1870 bool err_cond = false;
ea02e90b 1871 int retval = 0;
41c445ff
JB		 1872 struct i40e_pf *pf;
1873 int num_add = 0;
1874 int num_del = 0;
f1c7e72e 1875 int aq_err = 0;
41c445ff
JB		 1876 u16 cmd_flags;
1877
1878 /* empty array typed pointers, kcalloc later */
1879 struct i40e_aqc_add_macvlan_element_data *add_list;
1880 struct i40e_aqc_remove_macvlan_element_data *del_list;
1881
1882 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1883 usleep_range(1000, 2000);
1884 pf = vsi->back;
1885
1886 if (vsi->netdev) {
1887 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1888 vsi->current_netdev_flags = vsi->netdev->flags;
1889 }
1890
21659035
KP		 1891 INIT_LIST_HEAD(&tmp_del_list);
1892 INIT_LIST_HEAD(&tmp_add_list);
1893
41c445ff
JB		 1894 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1895 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1896
21659035 1897 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1898 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1899 if (!f->changed)
1900 continue;
1901
1902 if (f->counter != 0)
1903 continue;
1904 f->changed = false;
21659035
KP		 1905
1906 /* Move the element into temporary del_list */
1907 list_move_tail(&f->list, &tmp_del_list);
1908 }
1909
1910 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1911 if (!f->changed)
1912 continue;
1913
1914 if (f->counter == 0)
1915 continue;
1916 f->changed = false;
1917
1918 /* Clone MAC filter entry and add into temporary list */
1919 fclone = i40e_mac_filter_entry_clone(f);
1920 if (!fclone) {
1921 err_cond = true;
1922 break;
1923 }
1924 list_add_tail(&fclone->list, &tmp_add_list);
1925 }
1926
1927 /* if failed to clone MAC filter entry - undo */
1928 if (err_cond) {
1929 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1930 i40e_undo_add_filter_entries(vsi);
1931 }
1932 spin_unlock_bh(&vsi->mac_filter_list_lock);
1933
ea02e90b 1934 if (err_cond) {
21659035 1935 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1936 retval = -ENOMEM;
1937 goto out;
1938 }
21659035
KP		 1939 }
1940
1941 /* Now process 'del_list' outside the lock */
1942 if (!list_empty(&tmp_del_list)) {
f1199998
SN		 1943 int del_list_size;
1944
21659035
KP		 1945 filter_list_len = pf->hw.aq.asq_buf_size /
1946 sizeof(struct i40e_aqc_remove_macvlan_element_data);
f1199998
SN		 1947 del_list_size = filter_list_len *
1948 sizeof(struct i40e_aqc_remove_macvlan_element_data);
38c3cec7 1949 del_list = kzalloc(del_list_size, GFP_ATOMIC);
21659035
KP		 1950 if (!del_list) {
1951 i40e_cleanup_add_list(&tmp_add_list);
1952
1953 /* Undo VSI's MAC filter entry element updates */
1954 spin_lock_bh(&vsi->mac_filter_list_lock);
1955 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1956 i40e_undo_add_filter_entries(vsi);
1957 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1958 retval = -ENOMEM;
1959 goto out;
21659035
KP		 1960 }
1961
1962 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1963 cmd_flags = 0;
1964
1965 /* add to delete list */
9a173901 1966 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1967 del_list[num_del].vlan_tag =
1968 cpu_to_le16((u16)(f->vlan ==
1969 I40E_VLAN_ANY ? 0 : f->vlan));
1970
41c445ff
JB		 1971 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1972 del_list[num_del].flags = cmd_flags;
1973 num_del++;
1974
41c445ff
JB		 1975 /* flush a full buffer */
1976 if (num_del == filter_list_len) {
ea02e90b
MW		 1977 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1978 vsi->seid,
1979 del_list,
1980 num_del,
1981 NULL);
f1c7e72e 1982 aq_err = pf->hw.aq.asq_last_status;
41c445ff 1983 num_del = 0;
f1199998 1984 memset(del_list, 0, del_list_size);
41c445ff 1985
ea02e90b
MW		 1986 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1987 retval = -EIO;
21659035
KP		 1988 dev_err(&pf->pdev->dev,
1989 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
ea02e90b 1990 i40e_stat_str(&pf->hw, aq_ret),
21659035 1991 i40e_aq_str(&pf->hw, aq_err));
ea02e90b 1992 }
41c445ff 1993 }
21659035
KP		 1994 /* Release memory for MAC filter entries which were
1995 * synced up with HW.
1996 */
1997 list_del(&f->list);
1998 kfree(f);
41c445ff 1999 }
21659035 2000
41c445ff 2001 if (num_del) {
ea02e90b
MW		 2002 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
2003 del_list, num_del,
2004 NULL);
f1c7e72e 2005 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2006 num_del = 0;
2007
ea02e90b 2008 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 2009 dev_info(&pf->pdev->dev,
f1c7e72e 2010 "ignoring delete macvlan error, err %s aq_err %s\n",
ea02e90b 2011 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2012 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2013 }
2014
2015 kfree(del_list);
2016 del_list = NULL;
21659035
KP		 2017 }
2018
2019 if (!list_empty(&tmp_add_list)) {
f1199998 2020 int add_list_size;
41c445ff
JB		 2021
2022 /* do all the adds now */
2023 filter_list_len = pf->hw.aq.asq_buf_size /
2024 sizeof(struct i40e_aqc_add_macvlan_element_data),
f1199998
SN		 2025 add_list_size = filter_list_len *
2026 sizeof(struct i40e_aqc_add_macvlan_element_data);
38c3cec7 2027 add_list = kzalloc(add_list_size, GFP_ATOMIC);
21659035
KP		 2028 if (!add_list) {
2029 /* Purge element from temporary lists */
2030 i40e_cleanup_add_list(&tmp_add_list);
2031
2032 /* Undo add filter entries from VSI MAC filter list */
2033 spin_lock_bh(&vsi->mac_filter_list_lock);
2034 i40e_undo_add_filter_entries(vsi);
2035 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2036 retval = -ENOMEM;
2037 goto out;
21659035 2038 }
41c445ff 2039
21659035 2040 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2041
41c445ff
JB		 2042 add_happened = true;
2043 cmd_flags = 0;
2044
2045 /* add to add array */
9a173901 2046 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2047 add_list[num_add].vlan_tag =
2048 cpu_to_le16(
2049 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2050 add_list[num_add].queue_number = 0;
2051
2052 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2053 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2054 num_add++;
2055
2056 /* flush a full buffer */
2057 if (num_add == filter_list_len) {
ea02e90b
MW		 2058 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2059 add_list, num_add,
2060 NULL);
f1c7e72e 2061 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2062 num_add = 0;
2063
ea02e90b 2064 if (aq_ret)
41c445ff 2065 break;
f1199998 2066 memset(add_list, 0, add_list_size);
41c445ff 2067 }
21659035
KP		 2068 /* Entries from tmp_add_list were cloned from MAC
2069 * filter list, hence clean those cloned entries
2070 */
2071 list_del(&f->list);
2072 kfree(f);
41c445ff 2073 }
21659035 2074
41c445ff 2075 if (num_add) {
ea02e90b
MW		 2076 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2077 add_list, num_add, NULL);
f1c7e72e 2078 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2079 num_add = 0;
2080 }
2081 kfree(add_list);
2082 add_list = NULL;
2083
ea02e90b
MW		 2084 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2085 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2086 dev_info(&pf->pdev->dev,
f1c7e72e 2087 "add filter failed, err %s aq_err %s\n",
ea02e90b 2088 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2089 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2090 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2091 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2092 &vsi->state)) {
2093 promisc_forced_on = true;
2094 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2095 &vsi->state);
2096 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2097 }
2098 }
2099 }
2100
2101 /* check for changes in promiscuous modes */
2102 if (changed_flags & IFF_ALLMULTI) {
2103 bool cur_multipromisc;
6995b36c 2104
41c445ff 2105 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2106 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2107 vsi->seid,
2108 cur_multipromisc,
2109 NULL);
2110 if (aq_ret) {
2111 retval = i40e_aq_rc_to_posix(aq_ret,
2112 pf->hw.aq.asq_last_status);
41c445ff 2113 dev_info(&pf->pdev->dev,
f1c7e72e 2114 "set multi promisc failed, err %s aq_err %s\n",
ea02e90b 2115 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2116 i40e_aq_str(&pf->hw,
2117 pf->hw.aq.asq_last_status));
ea02e90b 2118 }
41c445ff
JB		 2119 }
2120 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2121 bool cur_promisc;
6995b36c 2122
41c445ff
JB		 2123 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2124 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2125 &vsi->state));
92faef85
ASJ		 2126 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
2127 /* set defport ON for Main VSI instead of true promisc
2128 * this way we will get all unicast/multicast and VLAN
2129 * promisc behavior but will not get VF or VMDq traffic
2130 * replicated on the Main VSI.
2131 */
2132 if (pf->cur_promisc != cur_promisc) {
2133 pf->cur_promisc = cur_promisc;
0e4425ed 2134 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2135 }
2136 } else {
ea02e90b 2137 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
92faef85 2138 &vsi->back->hw,
f1c7e72e
SN		 2139 vsi->seid,
2140 cur_promisc, NULL);
ea02e90b
MW		 2141 if (aq_ret) {
2142 retval =
2143 i40e_aq_rc_to_posix(aq_ret,
2144 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2145 dev_info(&pf->pdev->dev,
2146 "set unicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2147 aq_ret, pf->hw.aq.asq_last_status);
2148 }
2149 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
92faef85
ASJ		 2150 &vsi->back->hw,
2151 vsi->seid,
2152 cur_promisc, NULL);
ea02e90b
MW		 2153 if (aq_ret) {
2154 retval =
2155 i40e_aq_rc_to_posix(aq_ret,
2156 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2157 dev_info(&pf->pdev->dev,
2158 "set multicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2159 aq_ret, pf->hw.aq.asq_last_status);
2160 }
92faef85 2161 }
ea02e90b
MW		 2162 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2163 vsi->seid,
2164 cur_promisc, NULL);
2165 if (aq_ret) {
2166 retval = i40e_aq_rc_to_posix(aq_ret,
2167 pf->hw.aq.asq_last_status);
1a10370a 2168 dev_info(&pf->pdev->dev,
f1c7e72e 2169 "set brdcast promisc failed, err %s, aq_err %s\n",
ea02e90b 2170 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2171 i40e_aq_str(&pf->hw,
2172 pf->hw.aq.asq_last_status));
ea02e90b 2173 }
41c445ff 2174 }
ea02e90b 2175out:
41c445ff 2176 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2177 return retval;
41c445ff
JB		 2178}
2179
2180/**
2181 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2182 * @pf: board private structure
2183 **/
2184static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2185{
2186 int v;
2187
2188 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2189 return;
2190 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2191
505682cd 2192 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2193 if (pf->vsi[v] &&
17652c63
JB		 2194 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2195 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2196
2197 if (ret) {
2198 /* come back and try again later */
2199 pf->flags |= I40E_FLAG_FILTER_SYNC;
2200 break;
2201 }
2202 }
41c445ff
JB		 2203 }
2204}
2205
2206/**
2207 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2208 * @netdev: network interface device structure
2209 * @new_mtu: new value for maximum frame size
2210 *
2211 * Returns 0 on success, negative on failure
2212 **/
2213static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2214{
2215 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2216 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2217 struct i40e_vsi *vsi = np->vsi;
2218
2219 /* MTU < 68 is an error and causes problems on some kernels */
2220 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2221 return -EINVAL;
2222
2223 netdev_info(netdev, "changing MTU from %d to %d\n",
2224 netdev->mtu, new_mtu);
2225 netdev->mtu = new_mtu;
2226 if (netif_running(netdev))
2227 i40e_vsi_reinit_locked(vsi);
2228
2229 return 0;
2230}
2231
beb0dff1
JK		 2232/**
2233 * i40e_ioctl - Access the hwtstamp interface
2234 * @netdev: network interface device structure
2235 * @ifr: interface request data
2236 * @cmd: ioctl command
2237 **/
2238int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2239{
2240 struct i40e_netdev_priv *np = netdev_priv(netdev);
2241 struct i40e_pf *pf = np->vsi->back;
2242
2243 switch (cmd) {
2244 case SIOCGHWTSTAMP:
2245 return i40e_ptp_get_ts_config(pf, ifr);
2246 case SIOCSHWTSTAMP:
2247 return i40e_ptp_set_ts_config(pf, ifr);
2248 default:
2249 return -EOPNOTSUPP;
2250 }
2251}
2252
41c445ff
JB		 2253/**
2254 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2255 * @vsi: the vsi being adjusted
2256 **/
2257void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2258{
2259 struct i40e_vsi_context ctxt;
2260 i40e_status ret;
2261
2262 if ((vsi->info.valid_sections &
2263 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2264 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2265 return; /* already enabled */
2266
2267 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2268 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2269 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2270
2271 ctxt.seid = vsi->seid;
1a2f6248 2272 ctxt.info = vsi->info;
41c445ff
JB		 2273 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2274 if (ret) {
2275 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2276 "update vlan stripping failed, err %s aq_err %s\n",
2277 i40e_stat_str(&vsi->back->hw, ret),
2278 i40e_aq_str(&vsi->back->hw,
2279 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2280 }
2281}
2282
2283/**
2284 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2285 * @vsi: the vsi being adjusted
2286 **/
2287void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2288{
2289 struct i40e_vsi_context ctxt;
2290 i40e_status ret;
2291
2292 if ((vsi->info.valid_sections &
2293 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2294 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2295 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2296 return; /* already disabled */
2297
2298 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2299 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2300 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2301
2302 ctxt.seid = vsi->seid;
1a2f6248 2303 ctxt.info = vsi->info;
41c445ff
JB		 2304 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2305 if (ret) {
2306 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2307 "update vlan stripping failed, err %s aq_err %s\n",
2308 i40e_stat_str(&vsi->back->hw, ret),
2309 i40e_aq_str(&vsi->back->hw,
2310 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2311 }
2312}
2313
2314/**
2315 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2316 * @netdev: network interface to be adjusted
2317 * @features: netdev features to test if VLAN offload is enabled or not
2318 **/
2319static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2320{
2321 struct i40e_netdev_priv *np = netdev_priv(netdev);
2322 struct i40e_vsi *vsi = np->vsi;
2323
2324 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2325 i40e_vlan_stripping_enable(vsi);
2326 else
2327 i40e_vlan_stripping_disable(vsi);
2328}
2329
2330/**
2331 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2332 * @vsi: the vsi being configured
2333 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2334 **/
2335int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2336{
2337 struct i40e_mac_filter *f, *add_f;
2338 bool is_netdev, is_vf;
41c445ff
JB		 2339
2340 is_vf = (vsi->type == I40E_VSI_SRIOV);
2341 is_netdev = !!(vsi->netdev);
2342
21659035
KP		 2343 /* Locked once because all functions invoked below iterates list*/
2344 spin_lock_bh(&vsi->mac_filter_list_lock);
2345
41c445ff
JB		 2346 if (is_netdev) {
2347 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2348 is_vf, is_netdev);
2349 if (!add_f) {
2350 dev_info(&vsi->back->pdev->dev,
2351 "Could not add vlan filter %d for %pM\n",
2352 vid, vsi->netdev->dev_addr);
21659035 2353 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2354 return -ENOMEM;
2355 }
2356 }
2357
2358 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2359 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2360 if (!add_f) {
2361 dev_info(&vsi->back->pdev->dev,
2362 "Could not add vlan filter %d for %pM\n",
2363 vid, f->macaddr);
21659035 2364 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2365 return -ENOMEM;
2366 }
2367 }
2368
41c445ff
JB		 2369 /* Now if we add a vlan tag, make sure to check if it is the first
2370 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2371 * with 0, so we now accept untagged and specified tagged traffic
2372 * (and not any taged and untagged)
2373 */
2374 if (vid > 0) {
2375 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2376 I40E_VLAN_ANY,
2377 is_vf, is_netdev)) {
2378 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2379 I40E_VLAN_ANY, is_vf, is_netdev);
2380 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2381 is_vf, is_netdev);
2382 if (!add_f) {
2383 dev_info(&vsi->back->pdev->dev,
2384 "Could not add filter 0 for %pM\n",
2385 vsi->netdev->dev_addr);
21659035 2386 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2387 return -ENOMEM;
2388 }
2389 }
8d82a7c5 2390 }
41c445ff 2391
8d82a7c5
GR		 2392 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2393 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2394 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2395 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2396 is_vf, is_netdev))
2397 continue;
2398 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2399 is_vf, is_netdev);
2400 add_f = i40e_add_filter(vsi, f->macaddr,
2401 0, is_vf, is_netdev);
2402 if (!add_f) {
2403 dev_info(&vsi->back->pdev->dev,
2404 "Could not add filter 0 for %pM\n",
2405 f->macaddr);
2406 spin_unlock_bh(&vsi->mac_filter_list_lock);
2407 return -ENOMEM;
41c445ff
JB		 2408 }
2409 }
41c445ff
JB		 2410 }
2411
21659035
KP		 2412 spin_unlock_bh(&vsi->mac_filter_list_lock);
2413
0e4425ed
JB		 2414 /* schedule our worker thread which will take care of
2415 * applying the new filter changes
2416 */
2417 i40e_service_event_schedule(vsi->back);
2418 return 0;
41c445ff
JB		 2419}
2420
2421/**
2422 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2423 * @vsi: the vsi being configured
2424 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2425 *
2426 * Return: 0 on success or negative otherwise
41c445ff
JB		 2427 **/
2428int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2429{
2430 struct net_device *netdev = vsi->netdev;
2431 struct i40e_mac_filter *f, *add_f;
2432 bool is_vf, is_netdev;
2433 int filter_count = 0;
41c445ff
JB		 2434
2435 is_vf = (vsi->type == I40E_VSI_SRIOV);
2436 is_netdev = !!(netdev);
2437
21659035
KP		 2438 /* Locked once because all functions invoked below iterates list */
2439 spin_lock_bh(&vsi->mac_filter_list_lock);
2440
41c445ff
JB		 2441 if (is_netdev)
2442 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2443
2444 list_for_each_entry(f, &vsi->mac_filter_list, list)
2445 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2446
41c445ff
JB		 2447 /* go through all the filters for this VSI and if there is only
2448 * vid == 0 it means there are no other filters, so vid 0 must
2449 * be replaced with -1. This signifies that we should from now
2450 * on accept any traffic (with any tag present, or untagged)
2451 */
2452 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2453 if (is_netdev) {
2454 if (f->vlan &&
2455 ether_addr_equal(netdev->dev_addr, f->macaddr))
2456 filter_count++;
2457 }
2458
2459 if (f->vlan)
2460 filter_count++;
2461 }
2462
2463 if (!filter_count && is_netdev) {
2464 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2465 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2466 is_vf, is_netdev);
2467 if (!f) {
2468 dev_info(&vsi->back->pdev->dev,
2469 "Could not add filter %d for %pM\n",
2470 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2471 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2472 return -ENOMEM;
2473 }
2474 }
2475
2476 if (!filter_count) {
2477 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2478 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2479 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2480 is_vf, is_netdev);
41c445ff
JB		 2481 if (!add_f) {
2482 dev_info(&vsi->back->pdev->dev,
2483 "Could not add filter %d for %pM\n",
2484 I40E_VLAN_ANY, f->macaddr);
21659035 2485 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2486 return -ENOMEM;
2487 }
2488 }
2489 }
2490
21659035
KP		 2491 spin_unlock_bh(&vsi->mac_filter_list_lock);
2492
0e4425ed
JB		 2493 /* schedule our worker thread which will take care of
2494 * applying the new filter changes
2495 */
2496 i40e_service_event_schedule(vsi->back);
2497 return 0;
41c445ff
JB		 2498}
2499
2500/**
2501 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2502 * @netdev: network interface to be adjusted
2503 * @vid: vlan id to be added
078b5876
JB		 2504 *
2505 * net_device_ops implementation for adding vlan ids
41c445ff 2506 **/
38e00438
VD		 2507#ifdef I40E_FCOE
2508int i40e_vlan_rx_add_vid(struct net_device *netdev,
2509 __always_unused __be16 proto, u16 vid)
2510#else
41c445ff
JB		 2511static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2512 __always_unused __be16 proto, u16 vid)
38e00438 2513#endif
41c445ff
JB		 2514{
2515 struct i40e_netdev_priv *np = netdev_priv(netdev);
2516 struct i40e_vsi *vsi = np->vsi;
078b5876 2517 int ret = 0;
41c445ff
JB		 2518
2519 if (vid > 4095)
078b5876
JB		 2520 return -EINVAL;
2521
2522 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2523
6982d429
ASJ		 2524 /* If the network stack called us with vid = 0 then
2525 * it is asking to receive priority tagged packets with
2526 * vlan id 0. Our HW receives them by default when configured
2527 * to receive untagged packets so there is no need to add an
2528 * extra filter for vlan 0 tagged packets.
41c445ff 2529 */
6982d429
ASJ		 2530 if (vid)
2531 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2532
078b5876
JB		 2533 if (!ret && (vid < VLAN_N_VID))
2534 set_bit(vid, vsi->active_vlans);
41c445ff 2535
078b5876 2536 return ret;
41c445ff
JB		 2537}
2538
2539/**
2540 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2541 * @netdev: network interface to be adjusted
2542 * @vid: vlan id to be removed
078b5876 2543 *
fdfd943e 2544 * net_device_ops implementation for removing vlan ids
41c445ff 2545 **/
38e00438
VD		 2546#ifdef I40E_FCOE
2547int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2548 __always_unused __be16 proto, u16 vid)
2549#else
41c445ff
JB		 2550static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2551 __always_unused __be16 proto, u16 vid)
38e00438 2552#endif
41c445ff
JB		 2553{
2554 struct i40e_netdev_priv *np = netdev_priv(netdev);
2555 struct i40e_vsi *vsi = np->vsi;
2556
078b5876
JB		 2557 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2558
41c445ff
JB		 2559 /* return code is ignored as there is nothing a user
2560 * can do about failure to remove and a log message was
078b5876 2561 * already printed from the other function
41c445ff
JB		 2562 */
2563 i40e_vsi_kill_vlan(vsi, vid);
2564
2565 clear_bit(vid, vsi->active_vlans);
078b5876 2566
41c445ff
JB		 2567 return 0;
2568}
2569
2570/**
2571 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2572 * @vsi: the vsi being brought back up
2573 **/
2574static void i40e_restore_vlan(struct i40e_vsi *vsi)
2575{
2576 u16 vid;
2577
2578 if (!vsi->netdev)
2579 return;
2580
2581 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2582
2583 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2584 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2585 vid);
2586}
2587
2588/**
2589 * i40e_vsi_add_pvid - Add pvid for the VSI
2590 * @vsi: the vsi being adjusted
2591 * @vid: the vlan id to set as a PVID
2592 **/
dcae29be 2593int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2594{
2595 struct i40e_vsi_context ctxt;
f1c7e72e 2596 i40e_status ret;
41c445ff
JB		 2597
2598 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2599 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2600 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2601 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2602 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2603
2604 ctxt.seid = vsi->seid;
1a2f6248 2605 ctxt.info = vsi->info;
f1c7e72e
SN		 2606 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2607 if (ret) {
41c445ff 2608 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2609 "add pvid failed, err %s aq_err %s\n",
2610 i40e_stat_str(&vsi->back->hw, ret),
2611 i40e_aq_str(&vsi->back->hw,
2612 vsi->back->hw.aq.asq_last_status));
dcae29be 2613 return -ENOENT;
41c445ff
JB		 2614 }
2615
dcae29be 2616 return 0;
41c445ff
JB		 2617}
2618
2619/**
2620 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2621 * @vsi: the vsi being adjusted
2622 *
2623 * Just use the vlan_rx_register() service to put it back to normal
2624 **/
2625void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2626{
6c12fcbf
GR		 2627 i40e_vlan_stripping_disable(vsi);
2628
41c445ff 2629 vsi->info.pvid = 0;
41c445ff
JB		 2630}
2631
2632/**
2633 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2634 * @vsi: ptr to the VSI
2635 *
2636 * If this function returns with an error, then it's possible one or
2637 * more of the rings is populated (while the rest are not). It is the
2638 * callers duty to clean those orphaned rings.
2639 *
2640 * Return 0 on success, negative on failure
2641 **/
2642static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2643{
2644 int i, err = 0;
2645
2646 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2647 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2648
2649 return err;
2650}
2651
2652/**
2653 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2654 * @vsi: ptr to the VSI
2655 *
2656 * Free VSI's transmit software resources
2657 **/
2658static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2659{
2660 int i;
2661
8e9dca53
GR		 2662 if (!vsi->tx_rings)
2663 return;
2664
41c445ff 2665 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2666 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2667 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2668}
2669
2670/**
2671 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2672 * @vsi: ptr to the VSI
2673 *
2674 * If this function returns with an error, then it's possible one or
2675 * more of the rings is populated (while the rest are not). It is the
2676 * callers duty to clean those orphaned rings.
2677 *
2678 * Return 0 on success, negative on failure
2679 **/
2680static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2681{
2682 int i, err = 0;
2683
2684 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2685 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2686#ifdef I40E_FCOE
2687 i40e_fcoe_setup_ddp_resources(vsi);
2688#endif
41c445ff
JB		 2689 return err;
2690}
2691
2692/**
2693 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2694 * @vsi: ptr to the VSI
2695 *
2696 * Free all receive software resources
2697 **/
2698static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2699{
2700 int i;
2701
8e9dca53
GR		 2702 if (!vsi->rx_rings)
2703 return;
2704
41c445ff 2705 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2706 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2707 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2708#ifdef I40E_FCOE
2709 i40e_fcoe_free_ddp_resources(vsi);
2710#endif
41c445ff
JB		 2711}
2712
3ffa037d
NP		 2713/**
2714 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2715 * @ring: The Tx ring to configure
2716 *
2717 * This enables/disables XPS for a given Tx descriptor ring
2718 * based on the TCs enabled for the VSI that ring belongs to.
2719 **/
2720static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2721{
2722 struct i40e_vsi *vsi = ring->vsi;
2723 cpumask_var_t mask;
2724
9a660eea
JB		 2725 if (!ring->q_vector || !ring->netdev)
2726 return;
2727
2728 /* Single TC mode enable XPS */
2729 if (vsi->tc_config.numtc <= 1) {
2730 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2731 netif_set_xps_queue(ring->netdev,
2732 &ring->q_vector->affinity_mask,
2733 ring->queue_index);
9a660eea
JB		 2734 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2735 /* Disable XPS to allow selection based on TC */
2736 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2737 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2738 free_cpumask_var(mask);
3ffa037d 2739 }
0e4425ed
JB		 2740
2741 /* schedule our worker thread which will take care of
2742 * applying the new filter changes
2743 */
2744 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2745}
2746
41c445ff
JB		 2747/**
2748 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2749 * @ring: The Tx ring to configure
2750 *
2751 * Configure the Tx descriptor ring in the HMC context.
2752 **/
2753static int i40e_configure_tx_ring(struct i40e_ring *ring)
2754{
2755 struct i40e_vsi *vsi = ring->vsi;
2756 u16 pf_q = vsi->base_queue + ring->queue_index;
2757 struct i40e_hw *hw = &vsi->back->hw;
2758 struct i40e_hmc_obj_txq tx_ctx;
2759 i40e_status err = 0;
2760 u32 qtx_ctl = 0;
2761
2762 /* some ATR related tx ring init */
60ea5f83 2763 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2764 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2765 ring->atr_count = 0;
2766 } else {
2767 ring->atr_sample_rate = 0;
2768 }
2769
3ffa037d
NP		 2770 /* configure XPS */
2771 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2772
2773 /* clear the context structure first */
2774 memset(&tx_ctx, 0, sizeof(tx_ctx));
2775
2776 tx_ctx.new_context = 1;
2777 tx_ctx.base = (ring->dma / 128);
2778 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2779 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2780 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2781#ifdef I40E_FCOE
2782 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2783#endif
beb0dff1 2784 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2785 /* FDIR VSI tx ring can still use RS bit and writebacks */
2786 if (vsi->type != I40E_VSI_FDIR)
2787 tx_ctx.head_wb_ena = 1;
2788 tx_ctx.head_wb_addr = ring->dma +
2789 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2790
2791 /* As part of VSI creation/update, FW allocates certain
2792 * Tx arbitration queue sets for each TC enabled for
2793 * the VSI. The FW returns the handles to these queue
2794 * sets as part of the response buffer to Add VSI,
2795 * Update VSI, etc. AQ commands. It is expected that
2796 * these queue set handles be associated with the Tx
2797 * queues by the driver as part of the TX queue context
2798 * initialization. This has to be done regardless of
2799 * DCB as by default everything is mapped to TC0.
2800 */
2801 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2802 tx_ctx.rdylist_act = 0;
2803
2804 /* clear the context in the HMC */
2805 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2806 if (err) {
2807 dev_info(&vsi->back->pdev->dev,
2808 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2809 ring->queue_index, pf_q, err);
2810 return -ENOMEM;
2811 }
2812
2813 /* set the context in the HMC */
2814 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2815 if (err) {
2816 dev_info(&vsi->back->pdev->dev,
2817 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2818 ring->queue_index, pf_q, err);
2819 return -ENOMEM;
2820 }
2821
2822 /* Now associate this queue with this PCI function */
7a28d885 2823 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2824 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2825 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2826 I40E_QTX_CTL_VFVM_INDX_MASK;
2827 } else {
9d8bf547 2828 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2829 }
2830
13fd9774
SN		 2831 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2832 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2833 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2834 i40e_flush(hw);
2835
41c445ff
JB		 2836 /* cache tail off for easier writes later */
2837 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2838
2839 return 0;
2840}
2841
2842/**
2843 * i40e_configure_rx_ring - Configure a receive ring context
2844 * @ring: The Rx ring to configure
2845 *
2846 * Configure the Rx descriptor ring in the HMC context.
2847 **/
2848static int i40e_configure_rx_ring(struct i40e_ring *ring)
2849{
2850 struct i40e_vsi *vsi = ring->vsi;
2851 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2852 u16 pf_q = vsi->base_queue + ring->queue_index;
2853 struct i40e_hw *hw = &vsi->back->hw;
2854 struct i40e_hmc_obj_rxq rx_ctx;
2855 i40e_status err = 0;
2856
2857 ring->state = 0;
2858
2859 /* clear the context structure first */
2860 memset(&rx_ctx, 0, sizeof(rx_ctx));
2861
2862 ring->rx_buf_len = vsi->rx_buf_len;
2863 ring->rx_hdr_len = vsi->rx_hdr_len;
2864
2865 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2866 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2867
2868 rx_ctx.base = (ring->dma / 128);
2869 rx_ctx.qlen = ring->count;
2870
2871 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2872 set_ring_16byte_desc_enabled(ring);
2873 rx_ctx.dsize = 0;
2874 } else {
2875 rx_ctx.dsize = 1;
2876 }
2877
2878 rx_ctx.dtype = vsi->dtype;
2879 if (vsi->dtype) {
2880 set_ring_ps_enabled(ring);
2881 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2882 I40E_RX_SPLIT_IP |
2883 I40E_RX_SPLIT_TCP_UDP |
2884 I40E_RX_SPLIT_SCTP;
2885 } else {
2886 rx_ctx.hsplit_0 = 0;
2887 }
2888
2889 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2890 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2891 if (hw->revision_id == 0)
2892 rx_ctx.lrxqthresh = 0;
2893 else
2894 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2895 rx_ctx.crcstrip = 1;
2896 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2897 /* this controls whether VLAN is stripped from inner headers */
2898 rx_ctx.showiv = 0;
38e00438
VD		 2899#ifdef I40E_FCOE
2900 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2901#endif
acb3676b
CS		 2902 /* set the prefena field to 1 because the manual says to */
2903 rx_ctx.prefena = 1;
41c445ff
JB		 2904
2905 /* clear the context in the HMC */
2906 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2907 if (err) {
2908 dev_info(&vsi->back->pdev->dev,
2909 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2910 ring->queue_index, pf_q, err);
2911 return -ENOMEM;
2912 }
2913
2914 /* set the context in the HMC */
2915 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2916 if (err) {
2917 dev_info(&vsi->back->pdev->dev,
2918 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2919 ring->queue_index, pf_q, err);
2920 return -ENOMEM;
2921 }
2922
2923 /* cache tail for quicker writes, and clear the reg before use */
2924 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2925 writel(0, ring->tail);
2926
a132af24
MW		 2927 if (ring_is_ps_enabled(ring)) {
2928 i40e_alloc_rx_headers(ring);
2929 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2930 } else {
2931 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2932 }
41c445ff
JB		 2933
2934 return 0;
2935}
2936
2937/**
2938 * i40e_vsi_configure_tx - Configure the VSI for Tx
2939 * @vsi: VSI structure describing this set of rings and resources
2940 *
2941 * Configure the Tx VSI for operation.
2942 **/
2943static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2944{
2945 int err = 0;
2946 u16 i;
2947
9f65e15b
AD		 2948 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2949 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2950
2951 return err;
2952}
2953
2954/**
2955 * i40e_vsi_configure_rx - Configure the VSI for Rx
2956 * @vsi: the VSI being configured
2957 *
2958 * Configure the Rx VSI for operation.
2959 **/
2960static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2961{
2962 int err = 0;
2963 u16 i;
2964
2965 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2966 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2967 + ETH_FCS_LEN + VLAN_HLEN;
2968 else
2969 vsi->max_frame = I40E_RXBUFFER_2048;
2970
2971 /* figure out correct receive buffer length */
2972 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2973 I40E_FLAG_RX_PS_ENABLED)) {
2974 case I40E_FLAG_RX_1BUF_ENABLED:
2975 vsi->rx_hdr_len = 0;
2976 vsi->rx_buf_len = vsi->max_frame;
2977 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2978 break;
2979 case I40E_FLAG_RX_PS_ENABLED:
2980 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2981 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2982 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2983 break;
2984 default:
2985 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2986 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2987 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2988 break;
2989 }
2990
38e00438
VD		 2991#ifdef I40E_FCOE
2992 /* setup rx buffer for FCoE */
2993 if ((vsi->type == I40E_VSI_FCOE) &&
2994 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2995 vsi->rx_hdr_len = 0;
2996 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2997 vsi->max_frame = I40E_RXBUFFER_3072;
2998 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2999 }
3000
3001#endif /* I40E_FCOE */
41c445ff
JB		 3002 /* round up for the chip's needs */
3003 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 3004 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 3005 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 3006 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 3007
3008 /* set up individual rings */
3009 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 3010 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3011
3012 return err;
3013}
3014
3015/**
3016 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
3017 * @vsi: ptr to the VSI
3018 **/
3019static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
3020{
e7046ee1 3021 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 3022 u16 qoffset, qcount;
3023 int i, n;
3024
cd238a3e
PN		 3025 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3026 /* Reset the TC information */
3027 for (i = 0; i < vsi->num_queue_pairs; i++) {
3028 rx_ring = vsi->rx_rings[i];
3029 tx_ring = vsi->tx_rings[i];
3030 rx_ring->dcb_tc = 0;
3031 tx_ring->dcb_tc = 0;
3032 }
3033 }
41c445ff
JB		 3034
3035 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3036 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3037 continue;
3038
3039 qoffset = vsi->tc_config.tc_info[n].qoffset;
3040 qcount = vsi->tc_config.tc_info[n].qcount;
3041 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3042 rx_ring = vsi->rx_rings[i];
3043 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3044 rx_ring->dcb_tc = n;
3045 tx_ring->dcb_tc = n;
3046 }
3047 }
3048}
3049
3050/**
3051 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3052 * @vsi: ptr to the VSI
3053 **/
3054static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3055{
3056 if (vsi->netdev)
3057 i40e_set_rx_mode(vsi->netdev);
3058}
3059
17a73f6b
JG		 3060/**
3061 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3062 * @vsi: Pointer to the targeted VSI
3063 *
3064 * This function replays the hlist on the hw where all the SB Flow Director
3065 * filters were saved.
3066 **/
3067static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3068{
3069 struct i40e_fdir_filter *filter;
3070 struct i40e_pf *pf = vsi->back;
3071 struct hlist_node *node;
3072
55a5e60b
ASJ		 3073 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3074 return;
3075
17a73f6b
JG		 3076 hlist_for_each_entry_safe(filter, node,
3077 &pf->fdir_filter_list, fdir_node) {
3078 i40e_add_del_fdir(vsi, filter, true);
3079 }
3080}
3081
41c445ff
JB		 3082/**
3083 * i40e_vsi_configure - Set up the VSI for action
3084 * @vsi: the VSI being configured
3085 **/
3086static int i40e_vsi_configure(struct i40e_vsi *vsi)
3087{
3088 int err;
3089
3090 i40e_set_vsi_rx_mode(vsi);
3091 i40e_restore_vlan(vsi);
3092 i40e_vsi_config_dcb_rings(vsi);
3093 err = i40e_vsi_configure_tx(vsi);
3094 if (!err)
3095 err = i40e_vsi_configure_rx(vsi);
3096
3097 return err;
3098}
3099
3100/**
3101 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3102 * @vsi: the VSI being configured
3103 **/
3104static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3105{
3106 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3107 struct i40e_hw *hw = &pf->hw;
3108 u16 vector;
3109 int i, q;
41c445ff
JB		 3110 u32 qp;
3111
3112 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3113 * and PFINT_LNKLSTn registers, e.g.:
3114 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3115 */
3116 qp = vsi->base_queue;
3117 vector = vsi->base_vector;
493fb300 3118 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3119 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3120
ee2319cf 3121 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3122 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3123 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3124 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3125 q_vector->rx.itr);
3126 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3127 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3128 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3129 q_vector->tx.itr);
ac26fc13
JB		 3130 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3131 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3132
3133 /* Linked list for the queuepairs assigned to this vector */
3134 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3135 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3136 u32 val;
3137
41c445ff
JB		 3138 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3139 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3140 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3141 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3142 (I40E_QUEUE_TYPE_TX
3143 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3144
3145 wr32(hw, I40E_QINT_RQCTL(qp), val);
3146
3147 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3148 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3149 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3150 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3151 (I40E_QUEUE_TYPE_RX
3152 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3153
3154 /* Terminate the linked list */
3155 if (q == (q_vector->num_ringpairs - 1))
3156 val |= (I40E_QUEUE_END_OF_LIST
3157 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3158
3159 wr32(hw, I40E_QINT_TQCTL(qp), val);
3160 qp++;
3161 }
3162 }
3163
3164 i40e_flush(hw);
3165}
3166
3167/**
3168 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3169 * @hw: ptr to the hardware info
3170 **/
ab437b5a 3171static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3172{
ab437b5a 3173 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3174 u32 val;
3175
3176 /* clear things first */
3177 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3178 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3179
3180 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3181 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3182 I40E_PFINT_ICR0_ENA_GRST_MASK |
3183 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3184 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3185 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3186 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3187 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3188
0d8e1439
ASJ		 3189 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3190 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3191
ab437b5a
JK		 3192 if (pf->flags & I40E_FLAG_PTP)
3193 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3194
41c445ff
JB		 3195 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3196
3197 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3198 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3199 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3200
3201 /* OTHER_ITR_IDX = 0 */
3202 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3203}
3204
3205/**
3206 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3207 * @vsi: the VSI being configured
3208 **/
3209static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3210{
493fb300 3211 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3212 struct i40e_pf *pf = vsi->back;
3213 struct i40e_hw *hw = &pf->hw;
3214 u32 val;
3215
3216 /* set the ITR configuration */
ee2319cf 3217 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3218 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3219 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3220 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3221 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3222 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3223 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3224
ab437b5a 3225 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3226
3227 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3228 wr32(hw, I40E_PFINT_LNKLST0, 0);
3229
f29eaa3d 3230 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3231 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3232 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3233 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3234
3235 wr32(hw, I40E_QINT_RQCTL(0), val);
3236
3237 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3238 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3239 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3240
3241 wr32(hw, I40E_QINT_TQCTL(0), val);
3242 i40e_flush(hw);
3243}
3244
2ef28cfb
MW		 3245/**
3246 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3247 * @pf: board private structure
3248 **/
3249void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3250{
3251 struct i40e_hw *hw = &pf->hw;
3252
3253 wr32(hw, I40E_PFINT_DYN_CTL0,
3254 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3255 i40e_flush(hw);
3256}
3257
41c445ff
JB		 3258/**
3259 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3260 * @pf: board private structure
3261 **/
116a57d4 3262void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3263{
3264 struct i40e_hw *hw = &pf->hw;
3265 u32 val;
3266
3267 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3268 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3269 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3270
3271 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3272 i40e_flush(hw);
3273}
3274
41c445ff
JB		 3275/**
3276 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3277 * @irq: interrupt number
3278 * @data: pointer to a q_vector
3279 **/
3280static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3281{
3282 struct i40e_q_vector *q_vector = data;
3283
cd0b6fa6 3284 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3285 return IRQ_HANDLED;
3286
5d3465a1 3287 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3288
3289 return IRQ_HANDLED;
3290}
3291
41c445ff
JB		 3292/**
3293 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3294 * @vsi: the VSI being configured
3295 * @basename: name for the vector
3296 *
3297 * Allocates MSI-X vectors and requests interrupts from the kernel.
3298 **/
3299static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3300{
3301 int q_vectors = vsi->num_q_vectors;
3302 struct i40e_pf *pf = vsi->back;
3303 int base = vsi->base_vector;
3304 int rx_int_idx = 0;
3305 int tx_int_idx = 0;
3306 int vector, err;
3307
3308 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3309 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3310
cd0b6fa6 3311 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3312 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3313 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3314 tx_int_idx++;
cd0b6fa6 3315 } else if (q_vector->rx.ring) {
41c445ff
JB		 3316 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3317 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3318 } else if (q_vector->tx.ring) {
41c445ff
JB		 3319 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3320 "%s-%s-%d", basename, "tx", tx_int_idx++);
3321 } else {
3322 /* skip this unused q_vector */
3323 continue;
3324 }
3325 err = request_irq(pf->msix_entries[base + vector].vector,
3326 vsi->irq_handler,
3327 0,
3328 q_vector->name,
3329 q_vector);
3330 if (err) {
3331 dev_info(&pf->pdev->dev,
fb43201f 3332 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3333 goto free_queue_irqs;
3334 }
3335 /* assign the mask for this irq */
3336 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3337 &q_vector->affinity_mask);
3338 }
3339
63741846 3340 vsi->irqs_ready = true;
41c445ff
JB		 3341 return 0;
3342
3343free_queue_irqs:
3344 while (vector) {
3345 vector--;
3346 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3347 NULL);
3348 free_irq(pf->msix_entries[base + vector].vector,
3349 &(vsi->q_vectors[vector]));
3350 }
3351 return err;
3352}
3353
3354/**
3355 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3356 * @vsi: the VSI being un-configured
3357 **/
3358static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3359{
3360 struct i40e_pf *pf = vsi->back;
3361 struct i40e_hw *hw = &pf->hw;
3362 int base = vsi->base_vector;
3363 int i;
3364
3365 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3366 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3367 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3368 }
3369
3370 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3371 for (i = vsi->base_vector;
3372 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3373 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3374
3375 i40e_flush(hw);
3376 for (i = 0; i < vsi->num_q_vectors; i++)
3377 synchronize_irq(pf->msix_entries[i + base].vector);
3378 } else {
3379 /* Legacy and MSI mode - this stops all interrupt handling */
3380 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3381 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3382 i40e_flush(hw);
3383 synchronize_irq(pf->pdev->irq);
3384 }
3385}
3386
3387/**
3388 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3389 * @vsi: the VSI being configured
3390 **/
3391static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3392{
3393 struct i40e_pf *pf = vsi->back;
3394 int i;
3395
3396 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3397 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3398 i40e_irq_dynamic_enable(vsi, i);
3399 } else {
3400 i40e_irq_dynamic_enable_icr0(pf);
3401 }
3402
1022cb6c 3403 i40e_flush(&pf->hw);
41c445ff
JB		 3404 return 0;
3405}
3406
3407/**
3408 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3409 * @pf: board private structure
3410 **/
3411static void i40e_stop_misc_vector(struct i40e_pf *pf)
3412{
3413 /* Disable ICR 0 */
3414 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3415 i40e_flush(&pf->hw);
3416}
3417
3418/**
3419 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3420 * @irq: interrupt number
3421 * @data: pointer to a q_vector
3422 *
3423 * This is the handler used for all MSI/Legacy interrupts, and deals
3424 * with both queue and non-queue interrupts. This is also used in
3425 * MSIX mode to handle the non-queue interrupts.
3426 **/
3427static irqreturn_t i40e_intr(int irq, void *data)
3428{
3429 struct i40e_pf *pf = (struct i40e_pf *)data;
3430 struct i40e_hw *hw = &pf->hw;
5e823066 3431 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3432 u32 icr0, icr0_remaining;
3433 u32 val, ena_mask;
3434
3435 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3436 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3437
116a57d4
SN		 3438 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3439 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3440 goto enable_intr;
41c445ff 3441
cd92e72f
SN		 3442 /* if interrupt but no bits showing, must be SWINT */
3443 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3444 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3445 pf->sw_int_count++;
3446
0d8e1439
ASJ		 3447 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3448 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3449 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3450 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3451 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3452 }
3453
41c445ff
JB		 3454 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3455 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3456 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3457 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3458
3459 /* temporarily disable queue cause for NAPI processing */
3460 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3461
41c445ff
JB		 3462 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3463 wr32(hw, I40E_QINT_RQCTL(0), qval);
3464
3465 qval = rd32(hw, I40E_QINT_TQCTL(0));
3466 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3467 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3468
3469 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3470 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3471 }
3472
3473 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3474 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3475 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3476 }
3477
3478 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3479 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3480 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3481 }
3482
3483 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3484 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3485 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3486 }
3487
3488 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3489 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3490 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3491 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3492 val = rd32(hw, I40E_GLGEN_RSTAT);
3493 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3494 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3495 if (val == I40E_RESET_CORER) {
41c445ff 3496 pf->corer_count++;
4eb3f768 3497 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3498 pf->globr_count++;
4eb3f768 3499 } else if (val == I40E_RESET_EMPR) {
41c445ff 3500 pf->empr_count++;
9df42d1a 3501 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3502 }
41c445ff
JB		 3503 }
3504
9c010ee0
ASJ		 3505 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3506 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3507 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3508 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3509 rd32(hw, I40E_PFHMC_ERRORINFO),
3510 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3511 }
3512
beb0dff1
JK		 3513 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3514 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3515
3516 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3517 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3518 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3519 }
beb0dff1
JK		 3520 }
3521
41c445ff
JB		 3522 /* If a critical error is pending we have no choice but to reset the
3523 * device.
3524 * Report and mask out any remaining unexpected interrupts.
3525 */
3526 icr0_remaining = icr0 & ena_mask;
3527 if (icr0_remaining) {
3528 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3529 icr0_remaining);
9c010ee0 3530 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3531 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3532 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3533 dev_info(&pf->pdev->dev, "device will be reset\n");
3534 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3535 i40e_service_event_schedule(pf);
41c445ff
JB		 3536 }
3537 ena_mask &= ~icr0_remaining;
3538 }
5e823066 3539 ret = IRQ_HANDLED;
41c445ff 3540
5e823066 3541enable_intr:
41c445ff
JB		 3542 /* re-enable interrupt causes */
3543 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3544 if (!test_bit(__I40E_DOWN, &pf->state)) {
3545 i40e_service_event_schedule(pf);
3546 i40e_irq_dynamic_enable_icr0(pf);
3547 }
3548
5e823066 3549 return ret;
41c445ff
JB		 3550}
3551
cbf61325
ASJ		 3552/**
3553 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3554 * @tx_ring: tx ring to clean
3555 * @budget: how many cleans we're allowed
3556 *
3557 * Returns true if there's any budget left (e.g. the clean is finished)
3558 **/
3559static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3560{
3561 struct i40e_vsi *vsi = tx_ring->vsi;
3562 u16 i = tx_ring->next_to_clean;
3563 struct i40e_tx_buffer *tx_buf;
3564 struct i40e_tx_desc *tx_desc;
3565
3566 tx_buf = &tx_ring->tx_bi[i];
3567 tx_desc = I40E_TX_DESC(tx_ring, i);
3568 i -= tx_ring->count;
3569
3570 do {
3571 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3572
3573 /* if next_to_watch is not set then there is no work pending */
3574 if (!eop_desc)
3575 break;
3576
3577 /* prevent any other reads prior to eop_desc */
3578 read_barrier_depends();
3579
3580 /* if the descriptor isn't done, no work yet to do */
3581 if (!(eop_desc->cmd_type_offset_bsz &
3582 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3583 break;
3584
3585 /* clear next_to_watch to prevent false hangs */
3586 tx_buf->next_to_watch = NULL;
3587
49d7d933
ASJ		 3588 tx_desc->buffer_addr = 0;
3589 tx_desc->cmd_type_offset_bsz = 0;
3590 /* move past filter desc */
3591 tx_buf++;
3592 tx_desc++;
3593 i++;
3594 if (unlikely(!i)) {
3595 i -= tx_ring->count;
3596 tx_buf = tx_ring->tx_bi;
3597 tx_desc = I40E_TX_DESC(tx_ring, 0);
3598 }
cbf61325
ASJ		 3599 /* unmap skb header data */
3600 dma_unmap_single(tx_ring->dev,
3601 dma_unmap_addr(tx_buf, dma),
3602 dma_unmap_len(tx_buf, len),
3603 DMA_TO_DEVICE);
49d7d933
ASJ		 3604 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3605 kfree(tx_buf->raw_buf);
cbf61325 3606
49d7d933
ASJ		 3607 tx_buf->raw_buf = NULL;
3608 tx_buf->tx_flags = 0;
3609 tx_buf->next_to_watch = NULL;
cbf61325 3610 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3611 tx_desc->buffer_addr = 0;
3612 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3613
49d7d933 3614 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3615 tx_buf++;
3616 tx_desc++;
3617 i++;
3618 if (unlikely(!i)) {
3619 i -= tx_ring->count;
3620 tx_buf = tx_ring->tx_bi;
3621 tx_desc = I40E_TX_DESC(tx_ring, 0);
3622 }
3623
3624 /* update budget accounting */
3625 budget--;
3626 } while (likely(budget));
3627
3628 i += tx_ring->count;
3629 tx_ring->next_to_clean = i;
3630
6995b36c 3631 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3632 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3633
cbf61325
ASJ		 3634 return budget > 0;
3635}
3636
3637/**
3638 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3639 * @irq: interrupt number
3640 * @data: pointer to a q_vector
3641 **/
3642static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3643{
3644 struct i40e_q_vector *q_vector = data;
3645 struct i40e_vsi *vsi;
3646
3647 if (!q_vector->tx.ring)
3648 return IRQ_HANDLED;
3649
3650 vsi = q_vector->tx.ring->vsi;
3651 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3652
3653 return IRQ_HANDLED;
3654}
3655
41c445ff 3656/**
cd0b6fa6 3657 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3658 * @vsi: the VSI being configured
3659 * @v_idx: vector index
cd0b6fa6 3660 * @qp_idx: queue pair index
41c445ff 3661 **/
26cdc443 3662static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3663{
493fb300 3664 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3665 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3666 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3667
3668 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3669 tx_ring->next = q_vector->tx.ring;
3670 q_vector->tx.ring = tx_ring;
41c445ff 3671 q_vector->tx.count++;
cd0b6fa6
AD		 3672
3673 rx_ring->q_vector = q_vector;
3674 rx_ring->next = q_vector->rx.ring;
3675 q_vector->rx.ring = rx_ring;
3676 q_vector->rx.count++;
41c445ff
JB		 3677}
3678
3679/**
3680 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3681 * @vsi: the VSI being configured
3682 *
3683 * This function maps descriptor rings to the queue-specific vectors
3684 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3685 * one vector per queue pair, but on a constrained vector budget, we
3686 * group the queue pairs as "efficiently" as possible.
3687 **/
3688static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3689{
3690 int qp_remaining = vsi->num_queue_pairs;
3691 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3692 int num_ringpairs;
41c445ff
JB		 3693 int v_start = 0;
3694 int qp_idx = 0;
3695
3696 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3697 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3698 * It is also important to go through all the vectors available to be
3699 * sure that if we don't use all the vectors, that the remaining vectors
3700 * are cleared. This is especially important when decreasing the
3701 * number of queues in use.
41c445ff 3702 */
70114ec4 3703 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3704 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3705
3706 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3707
3708 q_vector->num_ringpairs = num_ringpairs;
3709
3710 q_vector->rx.count = 0;
3711 q_vector->tx.count = 0;
3712 q_vector->rx.ring = NULL;
3713 q_vector->tx.ring = NULL;
3714
3715 while (num_ringpairs--) {
26cdc443 3716 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3717 qp_idx++;
3718 qp_remaining--;
41c445ff
JB		 3719 }
3720 }
3721}
3722
3723/**
3724 * i40e_vsi_request_irq - Request IRQ from the OS
3725 * @vsi: the VSI being configured
3726 * @basename: name for the vector
3727 **/
3728static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3729{
3730 struct i40e_pf *pf = vsi->back;
3731 int err;
3732
3733 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3734 err = i40e_vsi_request_irq_msix(vsi, basename);
3735 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3736 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3737 pf->int_name, pf);
41c445ff
JB		 3738 else
3739 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3740 pf->int_name, pf);
41c445ff
JB		 3741
3742 if (err)
3743 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3744
3745 return err;
3746}
3747
3748#ifdef CONFIG_NET_POLL_CONTROLLER
3749/**
d89d967f 3750 * i40e_netpoll - A Polling 'interrupt' handler
41c445ff
JB		 3751 * @netdev: network interface device structure
3752 *
3753 * This is used by netconsole to send skbs without having to re-enable
3754 * interrupts. It's not called while the normal interrupt routine is executing.
3755 **/
38e00438
VD		 3756#ifdef I40E_FCOE
3757void i40e_netpoll(struct net_device *netdev)
3758#else
41c445ff 3759static void i40e_netpoll(struct net_device *netdev)
38e00438 3760#endif
41c445ff
JB		 3761{
3762 struct i40e_netdev_priv *np = netdev_priv(netdev);
3763 struct i40e_vsi *vsi = np->vsi;
3764 struct i40e_pf *pf = vsi->back;
3765 int i;
3766
3767 /* if interface is down do nothing */
3768 if (test_bit(__I40E_DOWN, &vsi->state))
3769 return;
3770
41c445ff
JB		 3771 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3772 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3773 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3774 } else {
3775 i40e_intr(pf->pdev->irq, netdev);
3776 }
41c445ff
JB		 3777}
3778#endif
3779
23527308
NP		 3780/**
3781 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3782 * @pf: the PF being configured
3783 * @pf_q: the PF queue
3784 * @enable: enable or disable state of the queue
3785 *
3786 * This routine will wait for the given Tx queue of the PF to reach the
3787 * enabled or disabled state.
3788 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3789 * multiple retries; else will return 0 in case of success.
3790 **/
3791static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3792{
3793 int i;
3794 u32 tx_reg;
3795
3796 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3797 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3798 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3799 break;
3800
f98a2006 3801 usleep_range(10, 20);
23527308
NP		 3802 }
3803 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3804 return -ETIMEDOUT;
3805
3806 return 0;
3807}
3808
41c445ff
JB		 3809/**
3810 * i40e_vsi_control_tx - Start or stop a VSI's rings
3811 * @vsi: the VSI being configured
3812 * @enable: start or stop the rings
3813 **/
3814static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3815{
3816 struct i40e_pf *pf = vsi->back;
3817 struct i40e_hw *hw = &pf->hw;
23527308 3818 int i, j, pf_q, ret = 0;
41c445ff
JB		 3819 u32 tx_reg;
3820
3821 pf_q = vsi->base_queue;
3822 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3823
3824 /* warn the TX unit of coming changes */
3825 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3826 if (!enable)
f98a2006 3827 usleep_range(10, 20);
351499ab 3828
6c5ef620 3829 for (j = 0; j < 50; j++) {
41c445ff 3830 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3831 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3832 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3833 break;
3834 usleep_range(1000, 2000);
3835 }
fda972f6 3836 /* Skip if the queue is already in the requested state */
7c122007 3837 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3838 continue;
41c445ff
JB		 3839
3840 /* turn on/off the queue */
c5c9eb9e
SN		 3841 if (enable) {
3842 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3843 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3844 } else {
41c445ff 3845 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3846 }
41c445ff
JB		 3847
3848 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3849 /* No waiting for the Tx queue to disable */
3850 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3851 continue;
41c445ff
JB		 3852
3853 /* wait for the change to finish */
23527308
NP		 3854 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3855 if (ret) {
3856 dev_info(&pf->pdev->dev,
fb43201f
SN		 3857 "VSI seid %d Tx ring %d %sable timeout\n",
3858 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3859 break;
41c445ff
JB		 3860 }
3861 }
3862
7134f9ce
JB		 3863 if (hw->revision_id == 0)
3864 mdelay(50);
23527308
NP		 3865 return ret;
3866}
3867
3868/**
3869 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3870 * @pf: the PF being configured
3871 * @pf_q: the PF queue
3872 * @enable: enable or disable state of the queue
3873 *
3874 * This routine will wait for the given Rx queue of the PF to reach the
3875 * enabled or disabled state.
3876 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3877 * multiple retries; else will return 0 in case of success.
3878 **/
3879static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3880{
3881 int i;
3882 u32 rx_reg;
3883
3884 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3885 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3886 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3887 break;
3888
f98a2006 3889 usleep_range(10, 20);
23527308
NP		 3890 }
3891 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3892 return -ETIMEDOUT;
7134f9ce 3893
41c445ff
JB		 3894 return 0;
3895}
3896
3897/**
3898 * i40e_vsi_control_rx - Start or stop a VSI's rings
3899 * @vsi: the VSI being configured
3900 * @enable: start or stop the rings
3901 **/
3902static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3903{
3904 struct i40e_pf *pf = vsi->back;
3905 struct i40e_hw *hw = &pf->hw;
23527308 3906 int i, j, pf_q, ret = 0;
41c445ff
JB		 3907 u32 rx_reg;
3908
3909 pf_q = vsi->base_queue;
3910 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3911 for (j = 0; j < 50; j++) {
41c445ff 3912 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3913 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3914 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3915 break;
3916 usleep_range(1000, 2000);
3917 }
41c445ff 3918
7c122007
CS		 3919 /* Skip if the queue is already in the requested state */
3920 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3921 continue;
41c445ff
JB		 3922
3923 /* turn on/off the queue */
3924 if (enable)
6c5ef620 3925 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3926 else
6c5ef620 3927 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3928 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3929
3930 /* wait for the change to finish */
23527308
NP		 3931 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3932 if (ret) {
3933 dev_info(&pf->pdev->dev,
fb43201f
SN		 3934 "VSI seid %d Rx ring %d %sable timeout\n",
3935 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3936 break;
41c445ff
JB		 3937 }
3938 }
3939
23527308 3940 return ret;
41c445ff
JB		 3941}
3942
3943/**
3944 * i40e_vsi_control_rings - Start or stop a VSI's rings
3945 * @vsi: the VSI being configured
3946 * @enable: start or stop the rings
3947 **/
fc18eaa0 3948int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3949{
3b867b28 3950 int ret = 0;
41c445ff
JB		 3951
3952 /* do rx first for enable and last for disable */
3953 if (request) {
3954 ret = i40e_vsi_control_rx(vsi, request);
3955 if (ret)
3956 return ret;
3957 ret = i40e_vsi_control_tx(vsi, request);
3958 } else {
3b867b28
ASJ		 3959 /* Ignore return value, we need to shutdown whatever we can */
3960 i40e_vsi_control_tx(vsi, request);
3961 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3962 }
3963
3964 return ret;
3965}
3966
3967/**
3968 * i40e_vsi_free_irq - Free the irq association with the OS
3969 * @vsi: the VSI being configured
3970 **/
3971static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3972{
3973 struct i40e_pf *pf = vsi->back;
3974 struct i40e_hw *hw = &pf->hw;
3975 int base = vsi->base_vector;
3976 u32 val, qp;
3977 int i;
3978
3979 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3980 if (!vsi->q_vectors)
3981 return;
3982
63741846
SN		 3983 if (!vsi->irqs_ready)
3984 return;
3985
3986 vsi->irqs_ready = false;
41c445ff
JB		 3987 for (i = 0; i < vsi->num_q_vectors; i++) {
3988 u16 vector = i + base;
3989
3990 /* free only the irqs that were actually requested */
78681b1f
SN		 3991 if (!vsi->q_vectors[i] ||
3992 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3993 continue;
3994
3995 /* clear the affinity_mask in the IRQ descriptor */
3996 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3997 NULL);
3998 free_irq(pf->msix_entries[vector].vector,
493fb300 3999 vsi->q_vectors[i]);
41c445ff
JB		 4000
4001 /* Tear down the interrupt queue link list
4002 *
4003 * We know that they come in pairs and always
4004 * the Rx first, then the Tx. To clear the
4005 * link list, stick the EOL value into the
4006 * next_q field of the registers.
4007 */
4008 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
4009 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4010 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4011 val |= I40E_QUEUE_END_OF_LIST
4012 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4013 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4014
4015 while (qp != I40E_QUEUE_END_OF_LIST) {
4016 u32 next;
4017
4018 val = rd32(hw, I40E_QINT_RQCTL(qp));
4019
4020 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4021 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4022 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4023 I40E_QINT_RQCTL_INTEVENT_MASK);
4024
4025 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4026 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4027
4028 wr32(hw, I40E_QINT_RQCTL(qp), val);
4029
4030 val = rd32(hw, I40E_QINT_TQCTL(qp));
4031
4032 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4033 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4034
4035 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4036 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4037 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4038 I40E_QINT_TQCTL_INTEVENT_MASK);
4039
4040 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4041 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4042
4043 wr32(hw, I40E_QINT_TQCTL(qp), val);
4044 qp = next;
4045 }
4046 }
4047 } else {
4048 free_irq(pf->pdev->irq, pf);
4049
4050 val = rd32(hw, I40E_PFINT_LNKLST0);
4051 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4052 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4053 val |= I40E_QUEUE_END_OF_LIST
4054 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4055 wr32(hw, I40E_PFINT_LNKLST0, val);
4056
4057 val = rd32(hw, I40E_QINT_RQCTL(qp));
4058 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4059 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4060 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4061 I40E_QINT_RQCTL_INTEVENT_MASK);
4062
4063 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4064 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4065
4066 wr32(hw, I40E_QINT_RQCTL(qp), val);
4067
4068 val = rd32(hw, I40E_QINT_TQCTL(qp));
4069
4070 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4071 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4072 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4073 I40E_QINT_TQCTL_INTEVENT_MASK);
4074
4075 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4076 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4077
4078 wr32(hw, I40E_QINT_TQCTL(qp), val);
4079 }
4080}
4081
493fb300
AD		 4082/**
4083 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4084 * @vsi: the VSI being configured
4085 * @v_idx: Index of vector to be freed
4086 *
4087 * This function frees the memory allocated to the q_vector. In addition if
4088 * NAPI is enabled it will delete any references to the NAPI struct prior
4089 * to freeing the q_vector.
4090 **/
4091static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4092{
4093 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4094 struct i40e_ring *ring;
493fb300
AD		 4095
4096 if (!q_vector)
4097 return;
4098
4099 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4100 i40e_for_each_ring(ring, q_vector->tx)
4101 ring->q_vector = NULL;
4102
4103 i40e_for_each_ring(ring, q_vector->rx)
4104 ring->q_vector = NULL;
493fb300
AD		 4105
4106 /* only VSI w/ an associated netdev is set up w/ NAPI */
4107 if (vsi->netdev)
4108 netif_napi_del(&q_vector->napi);
4109
4110 vsi->q_vectors[v_idx] = NULL;
4111
4112 kfree_rcu(q_vector, rcu);
4113}
4114
41c445ff
JB		 4115/**
4116 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4117 * @vsi: the VSI being un-configured
4118 *
4119 * This frees the memory allocated to the q_vectors and
4120 * deletes references to the NAPI struct.
4121 **/
4122static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4123{
4124 int v_idx;
4125
493fb300
AD		 4126 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4127 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4128}
4129
4130/**
4131 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4132 * @pf: board private structure
4133 **/
4134static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4135{
4136 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4137 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4138 pci_disable_msix(pf->pdev);
4139 kfree(pf->msix_entries);
4140 pf->msix_entries = NULL;
3b444399
SN		 4141 kfree(pf->irq_pile);
4142 pf->irq_pile = NULL;
41c445ff
JB		 4143 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4144 pci_disable_msi(pf->pdev);
4145 }
4146 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4147}
4148
4149/**
4150 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4151 * @pf: board private structure
4152 *
4153 * We go through and clear interrupt specific resources and reset the structure
4154 * to pre-load conditions
4155 **/
4156static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4157{
4158 int i;
4159
e147758d
SN		 4160 i40e_stop_misc_vector(pf);
4161 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4162 synchronize_irq(pf->msix_entries[0].vector);
4163 free_irq(pf->msix_entries[0].vector, pf);
4164 }
4165
41c445ff 4166 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4167 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4168 if (pf->vsi[i])
4169 i40e_vsi_free_q_vectors(pf->vsi[i]);
4170 i40e_reset_interrupt_capability(pf);
4171}
4172
4173/**
4174 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4175 * @vsi: the VSI being configured
4176 **/
4177static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4178{
4179 int q_idx;
4180
4181 if (!vsi->netdev)
4182 return;
4183
4184 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4185 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4186}
4187
4188/**
4189 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4190 * @vsi: the VSI being configured
4191 **/
4192static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4193{
4194 int q_idx;
4195
4196 if (!vsi->netdev)
4197 return;
4198
4199 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4200 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4201}
4202
90ef8d47
SN		 4203/**
4204 * i40e_vsi_close - Shut down a VSI
4205 * @vsi: the vsi to be quelled
4206 **/
4207static void i40e_vsi_close(struct i40e_vsi *vsi)
4208{
4209 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4210 i40e_down(vsi);
4211 i40e_vsi_free_irq(vsi);
4212 i40e_vsi_free_tx_resources(vsi);
4213 i40e_vsi_free_rx_resources(vsi);
92faef85 4214 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4215}
4216
41c445ff
JB		 4217/**
4218 * i40e_quiesce_vsi - Pause a given VSI
4219 * @vsi: the VSI being paused
4220 **/
4221static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4222{
4223 if (test_bit(__I40E_DOWN, &vsi->state))
4224 return;
4225
d341b7a5
NP		 4226 /* No need to disable FCoE VSI when Tx suspended */
4227 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4228 vsi->type == I40E_VSI_FCOE) {
4229 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4230 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4231 return;
4232 }
4233
41c445ff 4234 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4235 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4236 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4237 else
90ef8d47 4238 i40e_vsi_close(vsi);
41c445ff
JB		 4239}
4240
4241/**
4242 * i40e_unquiesce_vsi - Resume a given VSI
4243 * @vsi: the VSI being resumed
4244 **/
4245static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4246{
4247 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4248 return;
4249
4250 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4251 if (vsi->netdev && netif_running(vsi->netdev))
4252 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4253 else
8276f757 4254 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4255}
4256
4257/**
4258 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4259 * @pf: the PF
4260 **/
4261static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4262{
4263 int v;
4264
505682cd 4265 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4266 if (pf->vsi[v])
4267 i40e_quiesce_vsi(pf->vsi[v]);
4268 }
4269}
4270
4271/**
4272 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4273 * @pf: the PF
4274 **/
4275static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4276{
4277 int v;
4278
505682cd 4279 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4280 if (pf->vsi[v])
4281 i40e_unquiesce_vsi(pf->vsi[v]);
4282 }
4283}
4284
69129dc3
NP		 4285#ifdef CONFIG_I40E_DCB
4286/**
4287 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4288 * @vsi: the VSI being configured
4289 *
4290 * This function waits for the given VSI's Tx queues to be disabled.
4291 **/
4292static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4293{
4294 struct i40e_pf *pf = vsi->back;
4295 int i, pf_q, ret;
4296
4297 pf_q = vsi->base_queue;
4298 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4299 /* Check and wait for the disable status of the queue */
4300 ret = i40e_pf_txq_wait(pf, pf_q, false);
4301 if (ret) {
4302 dev_info(&pf->pdev->dev,
fb43201f
SN		 4303 "VSI seid %d Tx ring %d disable timeout\n",
4304 vsi->seid, pf_q);
69129dc3
NP		 4305 return ret;
4306 }
4307 }
4308
4309 return 0;
4310}
4311
4312/**
4313 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4314 * @pf: the PF
4315 *
4316 * This function waits for the Tx queues to be in disabled state for all the
4317 * VSIs that are managed by this PF.
4318 **/
4319static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4320{
4321 int v, ret = 0;
4322
4323 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4324 /* No need to wait for FCoE VSI queues */
4325 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4326 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4327 if (ret)
4328 break;
4329 }
4330 }
4331
4332 return ret;
4333}
4334
4335#endif
b03a8c1f
KP		 4336
4337/**
4338 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4339 * @q_idx: TX queue number
4340 * @vsi: Pointer to VSI struct
4341 *
4342 * This function checks specified queue for given VSI. Detects hung condition.
4343 * Sets hung bit since it is two step process. Before next run of service task
4344 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4345 * hung condition remain unchanged and during subsequent run, this function
4346 * issues SW interrupt to recover from hung condition.
4347 **/
4348static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4349{
4350 struct i40e_ring *tx_ring = NULL;
4351 struct i40e_pf *pf;
4352 u32 head, val, tx_pending;
4353 int i;
4354
4355 pf = vsi->back;
4356
4357 /* now that we have an index, find the tx_ring struct */
4358 for (i = 0; i < vsi->num_queue_pairs; i++) {
4359 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4360 if (q_idx == vsi->tx_rings[i]->queue_index) {
4361 tx_ring = vsi->tx_rings[i];
4362 break;
4363 }
4364 }
4365 }
4366
4367 if (!tx_ring)
4368 return;
4369
4370 /* Read interrupt register */
4371 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4372 val = rd32(&pf->hw,
4373 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4374 tx_ring->vsi->base_vector - 1));
4375 else
4376 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4377
9c6c1259
KP		 4378 /* Bail out if interrupts are disabled because napi_poll
4379 * execution in-progress or will get scheduled soon.
4380 * napi_poll cleans TX and RX queues and updates 'next_to_clean'.
4381 */
4382 if (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))
4383 return;
4384
b03a8c1f
KP		 4385 head = i40e_get_head(tx_ring);
4386
4387 tx_pending = i40e_get_tx_pending(tx_ring);
4388
9c6c1259
KP		 4389 /* HW is done executing descriptors, updated HEAD write back,
4390 * but SW hasn't processed those descriptors. If interrupt is
4391 * not generated from this point ON, it could result into
4392 * dev_watchdog detecting timeout on those netdev_queue,
4393 * hence proactively trigger SW interrupt.
b03a8c1f 4394 */
9c6c1259
KP		 4395 if (tx_pending) {
4396 /* NAPI Poll didn't run and clear since it was set */
4397 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4398 &tx_ring->q_vector->hung_detected)) {
4399 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4400 vsi->seid, q_idx, tx_pending,
4401 tx_ring->next_to_clean, head,
4402 tx_ring->next_to_use,
4403 readl(tx_ring->tail));
4404 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4405 vsi->seid, q_idx, val);
4406 i40e_force_wb(vsi, tx_ring->q_vector);
4407 } else {
4408 /* First Chance - detected possible hung */
4409 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4410 &tx_ring->q_vector->hung_detected);
4411 }
4412 }
b03a8c1f
KP		 4413}
4414
4415/**
4416 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4417 * @pf: pointer to PF struct
4418 *
4419 * LAN VSI has netdev and netdev has TX queues. This function is to check
4420 * each of those TX queues if they are hung, trigger recovery by issuing
4421 * SW interrupt.
4422 **/
4423static void i40e_detect_recover_hung(struct i40e_pf *pf)
4424{
4425 struct net_device *netdev;
4426 struct i40e_vsi *vsi;
4427 int i;
4428
4429 /* Only for LAN VSI */
4430 vsi = pf->vsi[pf->lan_vsi];
4431
4432 if (!vsi)
4433 return;
4434
4435 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4436 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4437 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4438 return;
4439
4440 /* Make sure type is MAIN VSI */
4441 if (vsi->type != I40E_VSI_MAIN)
4442 return;
4443
4444 netdev = vsi->netdev;
4445 if (!netdev)
4446 return;
4447
4448 /* Bail out if netif_carrier is not OK */
4449 if (!netif_carrier_ok(netdev))
4450 return;
4451
4452 /* Go thru' TX queues for netdev */
4453 for (i = 0; i < netdev->num_tx_queues; i++) {
4454 struct netdev_queue *q;
4455
4456 q = netdev_get_tx_queue(netdev, i);
4457 if (q)
4458 i40e_detect_recover_hung_queue(i, vsi);
4459 }
4460}
4461
63d7e5a4
NP		 4462/**
4463 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4464 * @pf: pointer to PF
63d7e5a4
NP		 4465 *
4466 * Get TC map for ISCSI PF type that will include iSCSI TC
4467 * and LAN TC.
4468 **/
4469static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4470{
4471 struct i40e_dcb_app_priority_table app;
4472 struct i40e_hw *hw = &pf->hw;
4473 u8 enabled_tc = 1; /* TC0 is always enabled */
4474 u8 tc, i;
4475 /* Get the iSCSI APP TLV */
4476 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4477
4478 for (i = 0; i < dcbcfg->numapps; i++) {
4479 app = dcbcfg->app[i];
4480 if (app.selector == I40E_APP_SEL_TCPIP &&
4481 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4482 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4483 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4484 break;
4485 }
4486 }
4487
4488 return enabled_tc;
4489}
4490
41c445ff
JB		 4491/**
4492 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4493 * @dcbcfg: the corresponding DCBx configuration structure
4494 *
4495 * Return the number of TCs from given DCBx configuration
4496 **/
4497static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4498{
078b5876
JB		 4499 u8 num_tc = 0;
4500 int i;
41c445ff
JB		 4501
4502 /* Scan the ETS Config Priority Table to find
4503 * traffic class enabled for a given priority
4504 * and use the traffic class index to get the
4505 * number of traffic classes enabled
4506 */
4507 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4508 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4509 num_tc = dcbcfg->etscfg.prioritytable[i];
4510 }
4511
4512 /* Traffic class index starts from zero so
4513 * increment to return the actual count
4514 */
078b5876 4515 return num_tc + 1;
41c445ff
JB		 4516}
4517
4518/**
4519 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4520 * @dcbcfg: the corresponding DCBx configuration structure
4521 *
4522 * Query the current DCB configuration and return the number of
4523 * traffic classes enabled from the given DCBX config
4524 **/
4525static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4526{
4527 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4528 u8 enabled_tc = 1;
4529 u8 i;
4530
4531 for (i = 0; i < num_tc; i++)
41a1d04b 4532 enabled_tc |= BIT(i);
41c445ff
JB		 4533
4534 return enabled_tc;
4535}
4536
4537/**
4538 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4539 * @pf: PF being queried
4540 *
4541 * Return number of traffic classes enabled for the given PF
4542 **/
4543static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4544{
4545 struct i40e_hw *hw = &pf->hw;
4546 u8 i, enabled_tc;
4547 u8 num_tc = 0;
4548 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4549
4550 /* If DCB is not enabled then always in single TC */
4551 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4552 return 1;
4553
63d7e5a4
NP		 4554 /* SFP mode will be enabled for all TCs on port */
4555 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4556 return i40e_dcb_get_num_tc(dcbcfg);
4557
41c445ff 4558 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4559 if (pf->hw.func_caps.iscsi)
4560 enabled_tc = i40e_get_iscsi_tc_map(pf);
4561 else
fc51de96 4562 return 1; /* Only TC0 */
41c445ff 4563
63d7e5a4
NP		 4564 /* At least have TC0 */
4565 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4566 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4567 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4568 num_tc++;
4569 }
4570 return num_tc;
41c445ff
JB		 4571}
4572
4573/**
4574 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4575 * @pf: PF being queried
4576 *
4577 * Return a bitmap for first enabled traffic class for this PF.
4578 **/
4579static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4580{
4581 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4582 u8 i = 0;
4583
4584 if (!enabled_tc)
4585 return 0x1; /* TC0 */
4586
4587 /* Find the first enabled TC */
4588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4589 if (enabled_tc & BIT(i))
41c445ff
JB		 4590 break;
4591 }
4592
41a1d04b 4593 return BIT(i);
41c445ff
JB		 4594}
4595
4596/**
4597 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4598 * @pf: PF being queried
4599 *
4600 * Return a bitmap for enabled traffic classes for this PF.
4601 **/
4602static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4603{
4604 /* If DCB is not enabled for this PF then just return default TC */
4605 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4606 return i40e_pf_get_default_tc(pf);
4607
41c445ff 4608 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4609 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4610 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4611
fc51de96 4612 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4613 if (pf->hw.func_caps.iscsi)
4614 return i40e_get_iscsi_tc_map(pf);
4615 else
fc51de96 4616 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4617}
4618
4619/**
4620 * i40e_vsi_get_bw_info - Query VSI BW Information
4621 * @vsi: the VSI being queried
4622 *
4623 * Returns 0 on success, negative value on failure
4624 **/
4625static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4626{
4627 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4628 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4629 struct i40e_pf *pf = vsi->back;
4630 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4631 i40e_status ret;
41c445ff 4632 u32 tc_bw_max;
41c445ff
JB		 4633 int i;
4634
4635 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4636 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4637 if (ret) {
41c445ff 4638 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4639 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4640 i40e_stat_str(&pf->hw, ret),
4641 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4642 return -EINVAL;
41c445ff
JB		 4643 }
4644
4645 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4646 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4647 NULL);
4648 if (ret) {
41c445ff 4649 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4650 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4651 i40e_stat_str(&pf->hw, ret),
4652 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4653 return -EINVAL;
41c445ff
JB		 4654 }
4655
4656 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4657 dev_info(&pf->pdev->dev,
4658 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4659 bw_config.tc_valid_bits,
4660 bw_ets_config.tc_valid_bits);
4661 /* Still continuing */
4662 }
4663
4664 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4665 vsi->bw_max_quanta = bw_config.max_bw;
4666 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4667 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4668 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4669 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4670 vsi->bw_ets_limit_credits[i] =
4671 le16_to_cpu(bw_ets_config.credits[i]);
4672 /* 3 bits out of 4 for each TC */
4673 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4674 }
078b5876 4675
dcae29be 4676 return 0;
41c445ff
JB		 4677}
4678
4679/**
4680 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4681 * @vsi: the VSI being configured
4682 * @enabled_tc: TC bitmap
4683 * @bw_credits: BW shared credits per TC
4684 *
4685 * Returns 0 on success, negative value on failure
4686 **/
dcae29be 4687static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4688 u8 *bw_share)
4689{
4690 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4691 i40e_status ret;
dcae29be 4692 int i;
41c445ff
JB		 4693
4694 bw_data.tc_valid_bits = enabled_tc;
4695 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4696 bw_data.tc_bw_credits[i] = bw_share[i];
4697
f1c7e72e
SN		 4698 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4699 NULL);
4700 if (ret) {
41c445ff 4701 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4702 "AQ command Config VSI BW allocation per TC failed = %d\n",
4703 vsi->back->hw.aq.asq_last_status);
dcae29be 4704 return -EINVAL;
41c445ff
JB		 4705 }
4706
4707 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4708 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4709
dcae29be 4710 return 0;
41c445ff
JB		 4711}
4712
4713/**
4714 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4715 * @vsi: the VSI being configured
4716 * @enabled_tc: TC map to be enabled
4717 *
4718 **/
4719static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4720{
4721 struct net_device *netdev = vsi->netdev;
4722 struct i40e_pf *pf = vsi->back;
4723 struct i40e_hw *hw = &pf->hw;
4724 u8 netdev_tc = 0;
4725 int i;
4726 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4727
4728 if (!netdev)
4729 return;
4730
4731 if (!enabled_tc) {
4732 netdev_reset_tc(netdev);
4733 return;
4734 }
4735
4736 /* Set up actual enabled TCs on the VSI */
4737 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4738 return;
4739
4740 /* set per TC queues for the VSI */
4741 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4742 /* Only set TC queues for enabled tcs
4743 *
4744 * e.g. For a VSI that has TC0 and TC3 enabled the
4745 * enabled_tc bitmap would be 0x00001001; the driver
4746 * will set the numtc for netdev as 2 that will be
4747 * referenced by the netdev layer as TC 0 and 1.
4748 */
75f5cea9 4749 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4750 netdev_set_tc_queue(netdev,
4751 vsi->tc_config.tc_info[i].netdev_tc,
4752 vsi->tc_config.tc_info[i].qcount,
4753 vsi->tc_config.tc_info[i].qoffset);
4754 }
4755
4756 /* Assign UP2TC map for the VSI */
4757 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4758 /* Get the actual TC# for the UP */
4759 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4760 /* Get the mapped netdev TC# for the UP */
4761 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4762 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4763 }
4764}
4765
4766/**
4767 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4768 * @vsi: the VSI being configured
4769 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4770 **/
4771static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4772 struct i40e_vsi_context *ctxt)
4773{
4774 /* copy just the sections touched not the entire info
4775 * since not all sections are valid as returned by
4776 * update vsi params
4777 */
4778 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4779 memcpy(&vsi->info.queue_mapping,
4780 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4781 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4782 sizeof(vsi->info.tc_mapping));
4783}
4784
4785/**
4786 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4787 * @vsi: VSI to be configured
4788 * @enabled_tc: TC bitmap
4789 *
4790 * This configures a particular VSI for TCs that are mapped to the
4791 * given TC bitmap. It uses default bandwidth share for TCs across
4792 * VSIs to configure TC for a particular VSI.
4793 *
4794 * NOTE:
4795 * It is expected that the VSI queues have been quisced before calling
4796 * this function.
4797 **/
4798static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4799{
4800 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4801 struct i40e_vsi_context ctxt;
4802 int ret = 0;
4803 int i;
4804
4805 /* Check if enabled_tc is same as existing or new TCs */
4806 if (vsi->tc_config.enabled_tc == enabled_tc)
4807 return ret;
4808
4809 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4810 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4811 if (enabled_tc & BIT(i))
41c445ff
JB		 4812 bw_share[i] = 1;
4813 }
4814
4815 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4816 if (ret) {
4817 dev_info(&vsi->back->pdev->dev,
4818 "Failed configuring TC map %d for VSI %d\n",
4819 enabled_tc, vsi->seid);
4820 goto out;
4821 }
4822
4823 /* Update Queue Pairs Mapping for currently enabled UPs */
4824 ctxt.seid = vsi->seid;
4825 ctxt.pf_num = vsi->back->hw.pf_id;
4826 ctxt.vf_num = 0;
4827 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4828 ctxt.info = vsi->info;
41c445ff
JB		 4829 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4830
4831 /* Update the VSI after updating the VSI queue-mapping information */
4832 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4833 if (ret) {
4834 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4835 "Update vsi tc config failed, err %s aq_err %s\n",
4836 i40e_stat_str(&vsi->back->hw, ret),
4837 i40e_aq_str(&vsi->back->hw,
4838 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4839 goto out;
4840 }
4841 /* update the local VSI info with updated queue map */
4842 i40e_vsi_update_queue_map(vsi, &ctxt);
4843 vsi->info.valid_sections = 0;
4844
4845 /* Update current VSI BW information */
4846 ret = i40e_vsi_get_bw_info(vsi);
4847 if (ret) {
4848 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4849 "Failed updating vsi bw info, err %s aq_err %s\n",
4850 i40e_stat_str(&vsi->back->hw, ret),
4851 i40e_aq_str(&vsi->back->hw,
4852 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4853 goto out;
4854 }
4855
4856 /* Update the netdev TC setup */
4857 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4858out:
4859 return ret;
4860}
4861
4e3b35b0
NP		 4862/**
4863 * i40e_veb_config_tc - Configure TCs for given VEB
4864 * @veb: given VEB
4865 * @enabled_tc: TC bitmap
4866 *
4867 * Configures given TC bitmap for VEB (switching) element
4868 **/
4869int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4870{
4871 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4872 struct i40e_pf *pf = veb->pf;
4873 int ret = 0;
4874 int i;
4875
4876 /* No TCs or already enabled TCs just return */
4877 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4878 return ret;
4879
4880 bw_data.tc_valid_bits = enabled_tc;
4881 /* bw_data.absolute_credits is not set (relative) */
4882
4883 /* Enable ETS TCs with equal BW Share for now */
4884 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4885 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4886 bw_data.tc_bw_share_credits[i] = 1;
4887 }
4888
4889 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4890 &bw_data, NULL);
4891 if (ret) {
4892 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4893 "VEB bw config failed, err %s aq_err %s\n",
4894 i40e_stat_str(&pf->hw, ret),
4895 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4896 goto out;
4897 }
4898
4899 /* Update the BW information */
4900 ret = i40e_veb_get_bw_info(veb);
4901 if (ret) {
4902 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4903 "Failed getting veb bw config, err %s aq_err %s\n",
4904 i40e_stat_str(&pf->hw, ret),
4905 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4906 }
4907
4908out:
4909 return ret;
4910}
4911
4912#ifdef CONFIG_I40E_DCB
4913/**
4914 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4915 * @pf: PF struct
4916 *
4917 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4918 * the caller would've quiesce all the VSIs before calling
4919 * this function
4920 **/
4921static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4922{
4923 u8 tc_map = 0;
4924 int ret;
4925 u8 v;
4926
4927 /* Enable the TCs available on PF to all VEBs */
4928 tc_map = i40e_pf_get_tc_map(pf);
4929 for (v = 0; v < I40E_MAX_VEB; v++) {
4930 if (!pf->veb[v])
4931 continue;
4932 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4933 if (ret) {
4934 dev_info(&pf->pdev->dev,
4935 "Failed configuring TC for VEB seid=%d\n",
4936 pf->veb[v]->seid);
4937 /* Will try to configure as many components */
4938 }
4939 }
4940
4941 /* Update each VSI */
505682cd 4942 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4943 if (!pf->vsi[v])
4944 continue;
4945
4946 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4947#ifdef I40E_FCOE
4948 * - For FCoE VSI only enable the TC configured
4949 * as per the APP TLV
4950#endif
4e3b35b0
NP		 4951 * - For all others keep them at TC0 for now
4952 */
4953 if (v == pf->lan_vsi)
4954 tc_map = i40e_pf_get_tc_map(pf);
4955 else
4956 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4957#ifdef I40E_FCOE
4958 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4959 tc_map = i40e_get_fcoe_tc_map(pf);
4960#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4961
4962 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4963 if (ret) {
4964 dev_info(&pf->pdev->dev,
4965 "Failed configuring TC for VSI seid=%d\n",
4966 pf->vsi[v]->seid);
4967 /* Will try to configure as many components */
4968 } else {
0672a091
NP		 4969 /* Re-configure VSI vectors based on updated TC map */
4970 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4971 if (pf->vsi[v]->netdev)
4972 i40e_dcbnl_set_all(pf->vsi[v]);
4973 }
4974 }
4975}
4976
2fd75f31
NP		 4977/**
4978 * i40e_resume_port_tx - Resume port Tx
4979 * @pf: PF struct
4980 *
4981 * Resume a port's Tx and issue a PF reset in case of failure to
4982 * resume.
4983 **/
4984static int i40e_resume_port_tx(struct i40e_pf *pf)
4985{
4986 struct i40e_hw *hw = &pf->hw;
4987 int ret;
4988
4989 ret = i40e_aq_resume_port_tx(hw, NULL);
4990 if (ret) {
4991 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4992 "Resume Port Tx failed, err %s aq_err %s\n",
4993 i40e_stat_str(&pf->hw, ret),
4994 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4995 /* Schedule PF reset to recover */
4996 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4997 i40e_service_event_schedule(pf);
4998 }
4999
5000 return ret;
5001}
5002
4e3b35b0
NP		 5003/**
5004 * i40e_init_pf_dcb - Initialize DCB configuration
5005 * @pf: PF being configured
5006 *
5007 * Query the current DCB configuration and cache it
5008 * in the hardware structure
5009 **/
5010static int i40e_init_pf_dcb(struct i40e_pf *pf)
5011{
5012 struct i40e_hw *hw = &pf->hw;
5013 int err = 0;
5014
025b4a54
ASJ		 5015 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
5016 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
5017 (pf->hw.aq.fw_maj_ver < 4))
5018 goto out;
5019
4e3b35b0
NP		 5020 /* Get the initial DCB configuration */
5021 err = i40e_init_dcb(hw);
5022 if (!err) {
5023 /* Device/Function is not DCBX capable */
5024 if ((!hw->func_caps.dcb) ||
5025 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5026 dev_info(&pf->pdev->dev,
5027 "DCBX offload is not supported or is disabled for this PF.\n");
5028
5029 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5030 goto out;
5031
5032 } else {
5033 /* When status is not DISABLED then DCBX in FW */
5034 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5035 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5036
5037 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5038 /* Enable DCB tagging only when more than one TC */
5039 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5040 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5041 dev_dbg(&pf->pdev->dev,
5042 "DCBX offload is supported for this PF.\n");
4e3b35b0 5043 }
014269ff 5044 } else {
aebfc816 5045 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5046 "Query for DCB configuration failed, err %s aq_err %s\n",
5047 i40e_stat_str(&pf->hw, err),
5048 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5049 }
5050
5051out:
5052 return err;
5053}
5054#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5055#define SPEED_SIZE 14
5056#define FC_SIZE 8
5057/**
5058 * i40e_print_link_message - print link up or down
5059 * @vsi: the VSI for which link needs a message
5060 */
c156f856 5061void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5062{
a9165490
SN		 5063 char *speed = "Unknown";
5064 char *fc = "Unknown";
cf05ed08 5065
c156f856
MJ		 5066 if (vsi->current_isup == isup)
5067 return;
5068 vsi->current_isup = isup;
cf05ed08
JB		 5069 if (!isup) {
5070 netdev_info(vsi->netdev, "NIC Link is Down\n");
5071 return;
5072 }
5073
148c2d80
GR		 5074 /* Warn user if link speed on NPAR enabled partition is not at
5075 * least 10GB
5076 */
5077 if (vsi->back->hw.func_caps.npar_enable &&
5078 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5079 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5080 netdev_warn(vsi->netdev,
5081 "The partition detected link speed that is less than 10Gbps\n");
5082
cf05ed08
JB		 5083 switch (vsi->back->hw.phy.link_info.link_speed) {
5084 case I40E_LINK_SPEED_40GB:
a9165490 5085 speed = "40 G";
cf05ed08 5086 break;
ae24b409 5087 case I40E_LINK_SPEED_20GB:
a9165490 5088 speed = "20 G";
ae24b409 5089 break;
cf05ed08 5090 case I40E_LINK_SPEED_10GB:
a9165490 5091 speed = "10 G";
cf05ed08
JB		 5092 break;
5093 case I40E_LINK_SPEED_1GB:
a9165490 5094 speed = "1000 M";
cf05ed08 5095 break;
5960d33f 5096 case I40E_LINK_SPEED_100MB:
a9165490 5097 speed = "100 M";
5960d33f 5098 break;
cf05ed08
JB		 5099 default:
5100 break;
5101 }
5102
5103 switch (vsi->back->hw.fc.current_mode) {
5104 case I40E_FC_FULL:
a9165490 5105 fc = "RX/TX";
cf05ed08
JB		 5106 break;
5107 case I40E_FC_TX_PAUSE:
a9165490 5108 fc = "TX";
cf05ed08
JB		 5109 break;
5110 case I40E_FC_RX_PAUSE:
a9165490 5111 fc = "RX";
cf05ed08
JB		 5112 break;
5113 default:
a9165490 5114 fc = "None";
cf05ed08
JB		 5115 break;
5116 }
5117
a9165490 5118 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5119 speed, fc);
5120}
4e3b35b0 5121
41c445ff
JB		 5122/**
5123 * i40e_up_complete - Finish the last steps of bringing up a connection
5124 * @vsi: the VSI being configured
5125 **/
5126static int i40e_up_complete(struct i40e_vsi *vsi)
5127{
5128 struct i40e_pf *pf = vsi->back;
5129 int err;
5130
5131 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5132 i40e_vsi_configure_msix(vsi);
5133 else
5134 i40e_configure_msi_and_legacy(vsi);
5135
5136 /* start rings */
5137 err = i40e_vsi_control_rings(vsi, true);
5138 if (err)
5139 return err;
5140
5141 clear_bit(__I40E_DOWN, &vsi->state);
5142 i40e_napi_enable_all(vsi);
5143 i40e_vsi_enable_irq(vsi);
5144
5145 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5146 (vsi->netdev)) {
cf05ed08 5147 i40e_print_link_message(vsi, true);
41c445ff
JB		 5148 netif_tx_start_all_queues(vsi->netdev);
5149 netif_carrier_on(vsi->netdev);
6d779b41 5150 } else if (vsi->netdev) {
cf05ed08 5151 i40e_print_link_message(vsi, false);
7b592f61
CW		 5152 /* need to check for qualified module here*/
5153 if ((pf->hw.phy.link_info.link_info &
5154 I40E_AQ_MEDIA_AVAILABLE) &&
5155 (!(pf->hw.phy.link_info.an_info &
5156 I40E_AQ_QUALIFIED_MODULE)))
5157 netdev_err(vsi->netdev,
5158 "the driver failed to link because an unqualified module was detected.");
41c445ff 5159 }
ca64fa4e
ASJ		 5160
5161 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5162 if (vsi->type == I40E_VSI_FDIR) {
5163 /* reset fd counters */
5164 pf->fd_add_err = pf->fd_atr_cnt = 0;
5165 if (pf->fd_tcp_rule > 0) {
5166 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5167 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5168 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5169 pf->fd_tcp_rule = 0;
5170 }
ca64fa4e 5171 i40e_fdir_filter_restore(vsi);
1e1be8f6 5172 }
41c445ff
JB		 5173 i40e_service_event_schedule(pf);
5174
5175 return 0;
5176}
5177
5178/**
5179 * i40e_vsi_reinit_locked - Reset the VSI
5180 * @vsi: the VSI being configured
5181 *
5182 * Rebuild the ring structs after some configuration
5183 * has changed, e.g. MTU size.
5184 **/
5185static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5186{
5187 struct i40e_pf *pf = vsi->back;
5188
5189 WARN_ON(in_interrupt());
5190 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5191 usleep_range(1000, 2000);
5192 i40e_down(vsi);
5193
5194 /* Give a VF some time to respond to the reset. The
5195 * two second wait is based upon the watchdog cycle in
5196 * the VF driver.
5197 */
5198 if (vsi->type == I40E_VSI_SRIOV)
5199 msleep(2000);
5200 i40e_up(vsi);
5201 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5202}
5203
5204/**
5205 * i40e_up - Bring the connection back up after being down
5206 * @vsi: the VSI being configured
5207 **/
5208int i40e_up(struct i40e_vsi *vsi)
5209{
5210 int err;
5211
5212 err = i40e_vsi_configure(vsi);
5213 if (!err)
5214 err = i40e_up_complete(vsi);
5215
5216 return err;
5217}
5218
5219/**
5220 * i40e_down - Shutdown the connection processing
5221 * @vsi: the VSI being stopped
5222 **/
5223void i40e_down(struct i40e_vsi *vsi)
5224{
5225 int i;
5226
5227 /* It is assumed that the caller of this function
5228 * sets the vsi->state __I40E_DOWN bit.
5229 */
5230 if (vsi->netdev) {
5231 netif_carrier_off(vsi->netdev);
5232 netif_tx_disable(vsi->netdev);
5233 }
5234 i40e_vsi_disable_irq(vsi);
5235 i40e_vsi_control_rings(vsi, false);
5236 i40e_napi_disable_all(vsi);
5237
5238 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5239 i40e_clean_tx_ring(vsi->tx_rings[i]);
5240 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5241 }
5242}
5243
5244/**
5245 * i40e_setup_tc - configure multiple traffic classes
5246 * @netdev: net device to configure
5247 * @tc: number of traffic classes to enable
5248 **/
5249static int i40e_setup_tc(struct net_device *netdev, u8 tc)
5250{
5251 struct i40e_netdev_priv *np = netdev_priv(netdev);
5252 struct i40e_vsi *vsi = np->vsi;
5253 struct i40e_pf *pf = vsi->back;
5254 u8 enabled_tc = 0;
5255 int ret = -EINVAL;
5256 int i;
5257
5258 /* Check if DCB enabled to continue */
5259 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5260 netdev_info(netdev, "DCB is not enabled for adapter\n");
5261 goto exit;
5262 }
5263
5264 /* Check if MFP enabled */
5265 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5266 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5267 goto exit;
5268 }
5269
5270 /* Check whether tc count is within enabled limit */
5271 if (tc > i40e_pf_get_num_tc(pf)) {
5272 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5273 goto exit;
5274 }
5275
5276 /* Generate TC map for number of tc requested */
5277 for (i = 0; i < tc; i++)
75f5cea9 5278 enabled_tc |= BIT(i);
41c445ff
JB		 5279
5280 /* Requesting same TC configuration as already enabled */
5281 if (enabled_tc == vsi->tc_config.enabled_tc)
5282 return 0;
5283
5284 /* Quiesce VSI queues */
5285 i40e_quiesce_vsi(vsi);
5286
5287 /* Configure VSI for enabled TCs */
5288 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5289 if (ret) {
5290 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5291 vsi->seid);
5292 goto exit;
5293 }
5294
5295 /* Unquiesce VSI */
5296 i40e_unquiesce_vsi(vsi);
5297
5298exit:
5299 return ret;
5300}
5301
e4c6734e 5302#ifdef I40E_FCOE
16e5cc64
JF		 5303int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5304 struct tc_to_netdev *tc)
e4c6734e 5305#else
16e5cc64
JF		 5306static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5307 struct tc_to_netdev *tc)
e4c6734e
JF		 5308#endif
5309{
16e5cc64 5310 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
e4c6734e 5311 return -EINVAL;
16e5cc64 5312 return i40e_setup_tc(netdev, tc->tc);
e4c6734e
JF		 5313}
5314
41c445ff
JB		 5315/**
5316 * i40e_open - Called when a network interface is made active
5317 * @netdev: network interface device structure
5318 *
5319 * The open entry point is called when a network interface is made
5320 * active by the system (IFF_UP). At this point all resources needed
5321 * for transmit and receive operations are allocated, the interrupt
5322 * handler is registered with the OS, the netdev watchdog subtask is
5323 * enabled, and the stack is notified that the interface is ready.
5324 *
5325 * Returns 0 on success, negative value on failure
5326 **/
38e00438 5327int i40e_open(struct net_device *netdev)
41c445ff
JB		 5328{
5329 struct i40e_netdev_priv *np = netdev_priv(netdev);
5330 struct i40e_vsi *vsi = np->vsi;
5331 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5332 int err;
5333
4eb3f768
SN		 5334 /* disallow open during test or if eeprom is broken */
5335 if (test_bit(__I40E_TESTING, &pf->state) ||
5336 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5337 return -EBUSY;
5338
5339 netif_carrier_off(netdev);
5340
6c167f58
EK		 5341 err = i40e_vsi_open(vsi);
5342 if (err)
5343 return err;
5344
059dab69
JB		 5345 /* configure global TSO hardware offload settings */
5346 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5347 TCP_FLAG_FIN) >> 16);
5348 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5349 TCP_FLAG_FIN |
5350 TCP_FLAG_CWR) >> 16);
5351 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5352
6633d381 5353#ifdef CONFIG_I40E_VXLAN
6c167f58
EK		 5354 vxlan_get_rx_port(netdev);
5355#endif
cd866606
SA		 5356#ifdef CONFIG_I40E_GENEVE
5357 geneve_get_rx_port(netdev);
5358#endif
6c167f58
EK		 5359
5360 return 0;
5361}
5362
5363/**
5364 * i40e_vsi_open -
5365 * @vsi: the VSI to open
5366 *
5367 * Finish initialization of the VSI.
5368 *
5369 * Returns 0 on success, negative value on failure
5370 **/
5371int i40e_vsi_open(struct i40e_vsi *vsi)
5372{
5373 struct i40e_pf *pf = vsi->back;
b294ac70 5374 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5375 int err;
5376
41c445ff
JB		 5377 /* allocate descriptors */
5378 err = i40e_vsi_setup_tx_resources(vsi);
5379 if (err)
5380 goto err_setup_tx;
5381 err = i40e_vsi_setup_rx_resources(vsi);
5382 if (err)
5383 goto err_setup_rx;
5384
5385 err = i40e_vsi_configure(vsi);
5386 if (err)
5387 goto err_setup_rx;
5388
c22e3c6c
SN		 5389 if (vsi->netdev) {
5390 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5391 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5392 err = i40e_vsi_request_irq(vsi, int_name);
5393 if (err)
5394 goto err_setup_rx;
41c445ff 5395
c22e3c6c
SN		 5396 /* Notify the stack of the actual queue counts. */
5397 err = netif_set_real_num_tx_queues(vsi->netdev,
5398 vsi->num_queue_pairs);
5399 if (err)
5400 goto err_set_queues;
25946ddb 5401
c22e3c6c
SN		 5402 err = netif_set_real_num_rx_queues(vsi->netdev,
5403 vsi->num_queue_pairs);
5404 if (err)
5405 goto err_set_queues;
8a9eb7d3
SN		 5406
5407 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5408 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5409 dev_driver_string(&pf->pdev->dev),
5410 dev_name(&pf->pdev->dev));
8a9eb7d3 5411 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5412
c22e3c6c 5413 } else {
ce9ccb17 5414 err = -EINVAL;
6c167f58
EK		 5415 goto err_setup_rx;
5416 }
25946ddb 5417
41c445ff
JB		 5418 err = i40e_up_complete(vsi);
5419 if (err)
5420 goto err_up_complete;
5421
41c445ff
JB		 5422 return 0;
5423
5424err_up_complete:
5425 i40e_down(vsi);
25946ddb 5426err_set_queues:
41c445ff
JB		 5427 i40e_vsi_free_irq(vsi);
5428err_setup_rx:
5429 i40e_vsi_free_rx_resources(vsi);
5430err_setup_tx:
5431 i40e_vsi_free_tx_resources(vsi);
5432 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5433 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5434
5435 return err;
5436}
5437
17a73f6b
JG		 5438/**
5439 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5440 * @pf: Pointer to PF
17a73f6b
JG		 5441 *
5442 * This function destroys the hlist where all the Flow Director
5443 * filters were saved.
5444 **/
5445static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5446{
5447 struct i40e_fdir_filter *filter;
5448 struct hlist_node *node2;
5449
5450 hlist_for_each_entry_safe(filter, node2,
5451 &pf->fdir_filter_list, fdir_node) {
5452 hlist_del(&filter->fdir_node);
5453 kfree(filter);
5454 }
5455 pf->fdir_pf_active_filters = 0;
5456}
5457
41c445ff
JB		 5458/**
5459 * i40e_close - Disables a network interface
5460 * @netdev: network interface device structure
5461 *
5462 * The close entry point is called when an interface is de-activated
5463 * by the OS. The hardware is still under the driver's control, but
5464 * this netdev interface is disabled.
5465 *
5466 * Returns 0, this is not allowed to fail
5467 **/
38e00438
VD		 5468#ifdef I40E_FCOE
5469int i40e_close(struct net_device *netdev)
5470#else
41c445ff 5471static int i40e_close(struct net_device *netdev)
38e00438 5472#endif
41c445ff
JB		 5473{
5474 struct i40e_netdev_priv *np = netdev_priv(netdev);
5475 struct i40e_vsi *vsi = np->vsi;
5476
90ef8d47 5477 i40e_vsi_close(vsi);
41c445ff
JB		 5478
5479 return 0;
5480}
5481
5482/**
5483 * i40e_do_reset - Start a PF or Core Reset sequence
5484 * @pf: board private structure
5485 * @reset_flags: which reset is requested
5486 *
5487 * The essential difference in resets is that the PF Reset
5488 * doesn't clear the packet buffers, doesn't reset the PE
5489 * firmware, and doesn't bother the other PFs on the chip.
5490 **/
5491void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5492{
5493 u32 val;
5494
5495 WARN_ON(in_interrupt());
5496
263fc48f
MW		 5497 if (i40e_check_asq_alive(&pf->hw))
5498 i40e_vc_notify_reset(pf);
5499
41c445ff 5500 /* do the biggest reset indicated */
41a1d04b 5501 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5502
5503 /* Request a Global Reset
5504 *
5505 * This will start the chip's countdown to the actual full
5506 * chip reset event, and a warning interrupt to be sent
5507 * to all PFs, including the requestor. Our handler
5508 * for the warning interrupt will deal with the shutdown
5509 * and recovery of the switch setup.
5510 */
69bfb110 5511 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5512 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5513 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5514 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5515
41a1d04b 5516 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5517
5518 /* Request a Core Reset
5519 *
5520 * Same as Global Reset, except does *not* include the MAC/PHY
5521 */
69bfb110 5522 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5523 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5524 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5525 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5526 i40e_flush(&pf->hw);
5527
41a1d04b 5528 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5529
5530 /* Request a PF Reset
5531 *
5532 * Resets only the PF-specific registers
5533 *
5534 * This goes directly to the tear-down and rebuild of
5535 * the switch, since we need to do all the recovery as
5536 * for the Core Reset.
5537 */
69bfb110 5538 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5539 i40e_handle_reset_warning(pf);
5540
41a1d04b 5541 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5542 int v;
5543
5544 /* Find the VSI(s) that requested a re-init */
5545 dev_info(&pf->pdev->dev,
5546 "VSI reinit requested\n");
505682cd 5547 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5548 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5549
41c445ff
JB		 5550 if (vsi != NULL &&
5551 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5552 i40e_vsi_reinit_locked(pf->vsi[v]);
5553 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5554 }
5555 }
41a1d04b 5556 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5557 int v;
5558
5559 /* Find the VSI(s) that needs to be brought down */
5560 dev_info(&pf->pdev->dev, "VSI down requested\n");
5561 for (v = 0; v < pf->num_alloc_vsi; v++) {
5562 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5563
b5d06f05
NP		 5564 if (vsi != NULL &&
5565 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5566 set_bit(__I40E_DOWN, &vsi->state);
5567 i40e_down(vsi);
5568 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5569 }
5570 }
41c445ff
JB		 5571 } else {
5572 dev_info(&pf->pdev->dev,
5573 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5574 }
5575}
5576
4e3b35b0
NP		 5577#ifdef CONFIG_I40E_DCB
5578/**
5579 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5580 * @pf: board private structure
5581 * @old_cfg: current DCB config
5582 * @new_cfg: new DCB config
5583 **/
5584bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5585 struct i40e_dcbx_config *old_cfg,
5586 struct i40e_dcbx_config *new_cfg)
5587{
5588 bool need_reconfig = false;
5589
5590 /* Check if ETS configuration has changed */
5591 if (memcmp(&new_cfg->etscfg,
5592 &old_cfg->etscfg,
5593 sizeof(new_cfg->etscfg))) {
5594 /* If Priority Table has changed reconfig is needed */
5595 if (memcmp(&new_cfg->etscfg.prioritytable,
5596 &old_cfg->etscfg.prioritytable,
5597 sizeof(new_cfg->etscfg.prioritytable))) {
5598 need_reconfig = true;
69bfb110 5599 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5600 }
5601
5602 if (memcmp(&new_cfg->etscfg.tcbwtable,
5603 &old_cfg->etscfg.tcbwtable,
5604 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5605 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5606
5607 if (memcmp(&new_cfg->etscfg.tsatable,
5608 &old_cfg->etscfg.tsatable,
5609 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5610 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5611 }
5612
5613 /* Check if PFC configuration has changed */
5614 if (memcmp(&new_cfg->pfc,
5615 &old_cfg->pfc,
5616 sizeof(new_cfg->pfc))) {
5617 need_reconfig = true;
69bfb110 5618 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5619 }
5620
5621 /* Check if APP Table has changed */
5622 if (memcmp(&new_cfg->app,
5623 &old_cfg->app,
3d9667a9 5624 sizeof(new_cfg->app))) {
4e3b35b0 5625 need_reconfig = true;
69bfb110 5626 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5627 }
4e3b35b0 5628
fb43201f 5629 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5630 return need_reconfig;
5631}
5632
5633/**
5634 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5635 * @pf: board private structure
5636 * @e: event info posted on ARQ
5637 **/
5638static int i40e_handle_lldp_event(struct i40e_pf *pf,
5639 struct i40e_arq_event_info *e)
5640{
5641 struct i40e_aqc_lldp_get_mib *mib =
5642 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5643 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5644 struct i40e_dcbx_config tmp_dcbx_cfg;
5645 bool need_reconfig = false;
5646 int ret = 0;
5647 u8 type;
5648
4d9b6043
NP		 5649 /* Not DCB capable or capability disabled */
5650 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5651 return ret;
5652
4e3b35b0
NP		 5653 /* Ignore if event is not for Nearest Bridge */
5654 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5655 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5656 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5657 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5658 return ret;
5659
5660 /* Check MIB Type and return if event for Remote MIB update */
5661 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5662 dev_dbg(&pf->pdev->dev,
fb43201f 5663 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5664 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5665 /* Update the remote cached instance and return */
5666 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5667 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5668 &hw->remote_dcbx_config);
5669 goto exit;
5670 }
5671
9fa61dd2 5672 /* Store the old configuration */
1a2f6248 5673 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5674
750fcbcf
NP		 5675 /* Reset the old DCBx configuration data */
5676 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5677 /* Get updated DCBX data from firmware */
5678 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5679 if (ret) {
f1c7e72e
SN		 5680 dev_info(&pf->pdev->dev,
5681 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5682 i40e_stat_str(&pf->hw, ret),
5683 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5684 goto exit;
5685 }
5686
5687 /* No change detected in DCBX configs */
750fcbcf
NP		 5688 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5689 sizeof(tmp_dcbx_cfg))) {
69bfb110 5690 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5691 goto exit;
5692 }
5693
750fcbcf
NP		 5694 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5695 &hw->local_dcbx_config);
4e3b35b0 5696
750fcbcf 5697 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5698
5699 if (!need_reconfig)
5700 goto exit;
5701
4d9b6043 5702 /* Enable DCB tagging only when more than one TC */
750fcbcf 5703 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5704 pf->flags |= I40E_FLAG_DCB_ENABLED;
5705 else
5706 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5707
69129dc3 5708 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5709 /* Reconfiguration needed quiesce all VSIs */
5710 i40e_pf_quiesce_all_vsi(pf);
5711
5712 /* Changes in configuration update VEB/VSI */
5713 i40e_dcb_reconfigure(pf);
5714
2fd75f31
NP		 5715 ret = i40e_resume_port_tx(pf);
5716
69129dc3 5717 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5718 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5719 if (ret)
5720 goto exit;
5721
5722 /* Wait for the PF's Tx queues to be disabled */
5723 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5724 if (ret) {
5725 /* Schedule PF reset to recover */
5726 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5727 i40e_service_event_schedule(pf);
5728 } else {
2fd75f31 5729 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5730 }
5731
4e3b35b0
NP		 5732exit:
5733 return ret;
5734}
5735#endif /* CONFIG_I40E_DCB */
5736
23326186
ASJ		 5737/**
5738 * i40e_do_reset_safe - Protected reset path for userland calls.
5739 * @pf: board private structure
5740 * @reset_flags: which reset is requested
5741 *
5742 **/
5743void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5744{
5745 rtnl_lock();
5746 i40e_do_reset(pf, reset_flags);
5747 rtnl_unlock();
5748}
5749
41c445ff
JB		 5750/**
5751 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5752 * @pf: board private structure
5753 * @e: event info posted on ARQ
5754 *
5755 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5756 * and VF queues
5757 **/
5758static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5759 struct i40e_arq_event_info *e)
5760{
5761 struct i40e_aqc_lan_overflow *data =
5762 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5763 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5764 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5765 struct i40e_hw *hw = &pf->hw;
5766 struct i40e_vf *vf;
5767 u16 vf_id;
5768
69bfb110
JB		 5769 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5770 queue, qtx_ctl);
41c445ff
JB		 5771
5772 /* Queue belongs to VF, find the VF and issue VF reset */
5773 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5774 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5775 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5776 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5777 vf_id -= hw->func_caps.vf_base_id;
5778 vf = &pf->vf[vf_id];
5779 i40e_vc_notify_vf_reset(vf);
5780 /* Allow VF to process pending reset notification */
5781 msleep(20);
5782 i40e_reset_vf(vf, false);
5783 }
5784}
5785
5786/**
5787 * i40e_service_event_complete - Finish up the service event
5788 * @pf: board private structure
5789 **/
5790static void i40e_service_event_complete(struct i40e_pf *pf)
5791{
b875f99b 5792 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5793
5794 /* flush memory to make sure state is correct before next watchog */
4e857c58 5795 smp_mb__before_atomic();
41c445ff
JB		 5796 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5797}
5798
55a5e60b 5799/**
12957388
ASJ		 5800 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5801 * @pf: board private structure
5802 **/
04294e38 5803u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5804{
04294e38 5805 u32 val, fcnt_prog;
12957388
ASJ		 5806
5807 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5808 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5809 return fcnt_prog;
5810}
5811
5812/**
04294e38 5813 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5814 * @pf: board private structure
5815 **/
04294e38 5816u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5817{
04294e38
ASJ		 5818 u32 val, fcnt_prog;
5819
55a5e60b
ASJ		 5820 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5821 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5822 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5823 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5824 return fcnt_prog;
5825}
1e1be8f6 5826
04294e38
ASJ		 5827/**
5828 * i40e_get_global_fd_count - Get total FD filters programmed on device
5829 * @pf: board private structure
5830 **/
5831u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5832{
5833 u32 val, fcnt_prog;
5834
5835 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5836 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5837 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5838 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5839 return fcnt_prog;
5840}
5841
55a5e60b
ASJ		 5842/**
5843 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5844 * @pf: board private structure
5845 **/
5846void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5847{
3487b6c3 5848 struct i40e_fdir_filter *filter;
55a5e60b 5849 u32 fcnt_prog, fcnt_avail;
3487b6c3 5850 struct hlist_node *node;
55a5e60b 5851
1e1be8f6
ASJ		 5852 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5853 return;
5854
55a5e60b
ASJ		 5855 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5856 * to re-enable
5857 */
04294e38 5858 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5859 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5860 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5861 (pf->fd_add_err == 0) ||
5862 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5863 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5864 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5865 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5866 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5867 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5868 }
5869 }
5870 /* Wait for some more space to be available to turn on ATR */
5871 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5872 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5873 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5874 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5875 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5876 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5877 }
5878 }
3487b6c3
CW		 5879
5880 /* if hw had a problem adding a filter, delete it */
5881 if (pf->fd_inv > 0) {
5882 hlist_for_each_entry_safe(filter, node,
5883 &pf->fdir_filter_list, fdir_node) {
5884 if (filter->fd_id == pf->fd_inv) {
5885 hlist_del(&filter->fdir_node);
5886 kfree(filter);
5887 pf->fdir_pf_active_filters--;
5888 }
5889 }
5890 }
55a5e60b
ASJ		 5891}
5892
1e1be8f6 5893#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5894#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5895/**
5896 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5897 * @pf: board private structure
5898 **/
5899static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5900{
04294e38 5901 unsigned long min_flush_time;
1e1be8f6 5902 int flush_wait_retry = 50;
04294e38
ASJ		 5903 bool disable_atr = false;
5904 int fd_room;
1e1be8f6
ASJ		 5905 int reg;
5906
1790ed0c
AA		 5907 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5908 return;
5909
a5fdaf34
JB		 5910 if (!time_after(jiffies, pf->fd_flush_timestamp +
5911 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5912 return;
04294e38 5913
a5fdaf34
JB		 5914 /* If the flush is happening too quick and we have mostly SB rules we
5915 * should not re-enable ATR for some time.
5916 */
5917 min_flush_time = pf->fd_flush_timestamp +
5918 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5919 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5920
5921 if (!(time_after(jiffies, min_flush_time)) &&
5922 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5923 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5924 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5925 disable_atr = true;
5926 }
5927
5928 pf->fd_flush_timestamp = jiffies;
5929 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5930 /* flush all filters */
5931 wr32(&pf->hw, I40E_PFQF_CTL_1,
5932 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5933 i40e_flush(&pf->hw);
5934 pf->fd_flush_cnt++;
5935 pf->fd_add_err = 0;
5936 do {
5937 /* Check FD flush status every 5-6msec */
5938 usleep_range(5000, 6000);
5939 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5940 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5941 break;
5942 } while (flush_wait_retry--);
5943 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5944 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5945 } else {
5946 /* replay sideband filters */
5947 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5948 if (!disable_atr)
5949 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5950 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5951 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5952 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5953 }
a5fdaf34 5954
1e1be8f6
ASJ		 5955}
5956
5957/**
5958 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5959 * @pf: board private structure
5960 **/
04294e38 5961u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5962{
5963 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5964}
5965
5966/* We can see up to 256 filter programming desc in transit if the filters are
5967 * being applied really fast; before we see the first
5968 * filter miss error on Rx queue 0. Accumulating enough error messages before
5969 * reacting will make sure we don't cause flush too often.
5970 */
5971#define I40E_MAX_FD_PROGRAM_ERROR 256
5972
41c445ff
JB		 5973/**
5974 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5975 * @pf: board private structure
5976 **/
5977static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5978{
41c445ff 5979
41c445ff
JB		 5980 /* if interface is down do nothing */
5981 if (test_bit(__I40E_DOWN, &pf->state))
5982 return;
1e1be8f6 5983
1790ed0c
AA		 5984 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5985 return;
5986
04294e38 5987 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5988 i40e_fdir_flush_and_replay(pf);
5989
55a5e60b
ASJ		 5990 i40e_fdir_check_and_reenable(pf);
5991
41c445ff
JB		 5992}
5993
5994/**
5995 * i40e_vsi_link_event - notify VSI of a link event
5996 * @vsi: vsi to be notified
5997 * @link_up: link up or down
5998 **/
5999static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
6000{
32b5b811 6001 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 6002 return;
6003
6004 switch (vsi->type) {
6005 case I40E_VSI_MAIN:
38e00438
VD		 6006#ifdef I40E_FCOE
6007 case I40E_VSI_FCOE:
6008#endif
41c445ff
JB		 6009 if (!vsi->netdev || !vsi->netdev_registered)
6010 break;
6011
6012 if (link_up) {
6013 netif_carrier_on(vsi->netdev);
6014 netif_tx_wake_all_queues(vsi->netdev);
6015 } else {
6016 netif_carrier_off(vsi->netdev);
6017 netif_tx_stop_all_queues(vsi->netdev);
6018 }
6019 break;
6020
6021 case I40E_VSI_SRIOV:
41c445ff
JB		 6022 case I40E_VSI_VMDQ2:
6023 case I40E_VSI_CTRL:
6024 case I40E_VSI_MIRROR:
6025 default:
6026 /* there is no notification for other VSIs */
6027 break;
6028 }
6029}
6030
6031/**
6032 * i40e_veb_link_event - notify elements on the veb of a link event
6033 * @veb: veb to be notified
6034 * @link_up: link up or down
6035 **/
6036static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6037{
6038 struct i40e_pf *pf;
6039 int i;
6040
6041 if (!veb || !veb->pf)
6042 return;
6043 pf = veb->pf;
6044
6045 /* depth first... */
6046 for (i = 0; i < I40E_MAX_VEB; i++)
6047 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6048 i40e_veb_link_event(pf->veb[i], link_up);
6049
6050 /* ... now the local VSIs */
505682cd 6051 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6052 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6053 i40e_vsi_link_event(pf->vsi[i], link_up);
6054}
6055
6056/**
6057 * i40e_link_event - Update netif_carrier status
6058 * @pf: board private structure
6059 **/
6060static void i40e_link_event(struct i40e_pf *pf)
6061{
320684cd 6062 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6063 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6064 i40e_status status;
6065 bool new_link, old_link;
41c445ff 6066
1f9610e4
CS		 6067 /* save off old link status information */
6068 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6069
1e701e09
JB		 6070 /* set this to force the get_link_status call to refresh state */
6071 pf->hw.phy.get_link_info = true;
6072
41c445ff 6073 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6074
6075 status = i40e_get_link_status(&pf->hw, &new_link);
6076 if (status) {
6077 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6078 status);
6079 return;
6080 }
6081
fef59ddf
CS		 6082 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6083 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6084
1e701e09 6085 if (new_link == old_link &&
fef59ddf 6086 new_link_speed == old_link_speed &&
320684cd
MW		 6087 (test_bit(__I40E_DOWN, &vsi->state) ||
6088 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6089 return;
320684cd
MW		 6090
6091 if (!test_bit(__I40E_DOWN, &vsi->state))
6092 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6093
6094 /* Notify the base of the switch tree connected to
6095 * the link. Floating VEBs are not notified.
6096 */
6097 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6098 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6099 else
320684cd 6100 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6101
6102 if (pf->vf)
6103 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6104
6105 if (pf->flags & I40E_FLAG_PTP)
6106 i40e_ptp_set_increment(pf);
41c445ff
JB		 6107}
6108
41c445ff 6109/**
21536717 6110 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6111 * @pf: board private structure
6112 **/
6113static void i40e_watchdog_subtask(struct i40e_pf *pf)
6114{
6115 int i;
6116
6117 /* if interface is down do nothing */
6118 if (test_bit(__I40E_DOWN, &pf->state) ||
6119 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6120 return;
6121
21536717
SN		 6122 /* make sure we don't do these things too often */
6123 if (time_before(jiffies, (pf->service_timer_previous +
6124 pf->service_timer_period)))
6125 return;
6126 pf->service_timer_previous = jiffies;
6127
9ac77266
SN		 6128 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6129 i40e_link_event(pf);
21536717 6130
41c445ff
JB		 6131 /* Update the stats for active netdevs so the network stack
6132 * can look at updated numbers whenever it cares to
6133 */
505682cd 6134 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6135 if (pf->vsi[i] && pf->vsi[i]->netdev)
6136 i40e_update_stats(pf->vsi[i]);
6137
d1a8d275
ASJ		 6138 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6139 /* Update the stats for the active switching components */
6140 for (i = 0; i < I40E_MAX_VEB; i++)
6141 if (pf->veb[i])
6142 i40e_update_veb_stats(pf->veb[i]);
6143 }
beb0dff1
JK		 6144
6145 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6146}
6147
6148/**
6149 * i40e_reset_subtask - Set up for resetting the device and driver
6150 * @pf: board private structure
6151 **/
6152static void i40e_reset_subtask(struct i40e_pf *pf)
6153{
6154 u32 reset_flags = 0;
6155
23326186 6156 rtnl_lock();
41c445ff 6157 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6158 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6159 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6160 }
6161 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6162 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6163 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6164 }
6165 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6166 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6167 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6168 }
6169 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6170 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6171 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6172 }
b5d06f05 6173 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6174 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6175 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6176 }
41c445ff
JB		 6177
6178 /* If there's a recovery already waiting, it takes
6179 * precedence before starting a new reset sequence.
6180 */
6181 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6182 i40e_handle_reset_warning(pf);
23326186 6183 goto unlock;
41c445ff
JB		 6184 }
6185
6186 /* If we're already down or resetting, just bail */
6187 if (reset_flags &&
6188 !test_bit(__I40E_DOWN, &pf->state) &&
6189 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6190 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6191
6192unlock:
6193 rtnl_unlock();
41c445ff
JB		 6194}
6195
6196/**
6197 * i40e_handle_link_event - Handle link event
6198 * @pf: board private structure
6199 * @e: event info posted on ARQ
6200 **/
6201static void i40e_handle_link_event(struct i40e_pf *pf,
6202 struct i40e_arq_event_info *e)
6203{
41c445ff
JB		 6204 struct i40e_aqc_get_link_status *status =
6205 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6206
1e701e09
JB		 6207 /* Do a new status request to re-enable LSE reporting
6208 * and load new status information into the hw struct
6209 * This completely ignores any state information
6210 * in the ARQ event info, instead choosing to always
6211 * issue the AQ update link status command.
6212 */
6213 i40e_link_event(pf);
6214
7b592f61
CW		 6215 /* check for unqualified module, if link is down */
6216 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6217 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6218 (!(status->link_info & I40E_AQ_LINK_UP)))
6219 dev_err(&pf->pdev->dev,
6220 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6221}
6222
6223/**
6224 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6225 * @pf: board private structure
6226 **/
6227static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6228{
6229 struct i40e_arq_event_info event;
6230 struct i40e_hw *hw = &pf->hw;
6231 u16 pending, i = 0;
6232 i40e_status ret;
6233 u16 opcode;
86df242b 6234 u32 oldval;
41c445ff
JB		 6235 u32 val;
6236
a316f651
ASJ		 6237 /* Do not run clean AQ when PF reset fails */
6238 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6239 return;
6240
86df242b
SN		 6241 /* check for error indications */
6242 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6243 oldval = val;
6244 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6245 if (hw->debug_mask & I40E_DEBUG_AQ)
6246 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6247 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6248 }
6249 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6250 if (hw->debug_mask & I40E_DEBUG_AQ)
6251 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b 6252 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
1d0a4ada 6253 pf->arq_overflows++;
86df242b
SN		 6254 }
6255 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6256 if (hw->debug_mask & I40E_DEBUG_AQ)
6257 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6258 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6259 }
6260 if (oldval != val)
6261 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6262
6263 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6264 oldval = val;
6265 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6266 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6267 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6268 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6269 }
6270 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6271 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6272 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6273 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6274 }
6275 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6276 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6277 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6278 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6279 }
6280 if (oldval != val)
6281 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6282
1001dc37
MW		 6283 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6284 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6285 if (!event.msg_buf)
6286 return;
6287
6288 do {
6289 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6290 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6291 break;
56497978 6292 else if (ret) {
41c445ff
JB		 6293 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6294 break;
6295 }
6296
6297 opcode = le16_to_cpu(event.desc.opcode);
6298 switch (opcode) {
6299
6300 case i40e_aqc_opc_get_link_status:
6301 i40e_handle_link_event(pf, &event);
6302 break;
6303 case i40e_aqc_opc_send_msg_to_pf:
6304 ret = i40e_vc_process_vf_msg(pf,
6305 le16_to_cpu(event.desc.retval),
6306 le32_to_cpu(event.desc.cookie_high),
6307 le32_to_cpu(event.desc.cookie_low),
6308 event.msg_buf,
1001dc37 6309 event.msg_len);
41c445ff
JB		 6310 break;
6311 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6312 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6313#ifdef CONFIG_I40E_DCB
6314 rtnl_lock();
6315 ret = i40e_handle_lldp_event(pf, &event);
6316 rtnl_unlock();
6317#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6318 break;
6319 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6320 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6321 i40e_handle_lan_overflow_event(pf, &event);
6322 break;
0467bc91
SN		 6323 case i40e_aqc_opc_send_msg_to_peer:
6324 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6325 break;
91a0f930
SN		 6326 case i40e_aqc_opc_nvm_erase:
6327 case i40e_aqc_opc_nvm_update:
00ada50d 6328 case i40e_aqc_opc_oem_post_update:
91a0f930
SN		 6329 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6330 break;
41c445ff
JB		 6331 default:
6332 dev_info(&pf->pdev->dev,
0467bc91
SN		 6333 "ARQ Error: Unknown event 0x%04x received\n",
6334 opcode);
41c445ff
JB		 6335 break;
6336 }
6337 } while (pending && (i++ < pf->adminq_work_limit));
6338
6339 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6340 /* re-enable Admin queue interrupt cause */
6341 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6342 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6343 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6344 i40e_flush(hw);
6345
6346 kfree(event.msg_buf);
6347}
6348
4eb3f768
SN		 6349/**
6350 * i40e_verify_eeprom - make sure eeprom is good to use
6351 * @pf: board private structure
6352 **/
6353static void i40e_verify_eeprom(struct i40e_pf *pf)
6354{
6355 int err;
6356
6357 err = i40e_diag_eeprom_test(&pf->hw);
6358 if (err) {
6359 /* retry in case of garbage read */
6360 err = i40e_diag_eeprom_test(&pf->hw);
6361 if (err) {
6362 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6363 err);
6364 set_bit(__I40E_BAD_EEPROM, &pf->state);
6365 }
6366 }
6367
6368 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6369 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6370 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6371 }
6372}
6373
386a0afa
AA		 6374/**
6375 * i40e_enable_pf_switch_lb
b40c82e6 6376 * @pf: pointer to the PF structure
386a0afa
AA		 6377 *
6378 * enable switch loop back or die - no point in a return value
6379 **/
6380static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6381{
6382 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6383 struct i40e_vsi_context ctxt;
f1c7e72e 6384 int ret;
386a0afa
AA		 6385
6386 ctxt.seid = pf->main_vsi_seid;
6387 ctxt.pf_num = pf->hw.pf_id;
6388 ctxt.vf_num = 0;
f1c7e72e
SN		 6389 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6390 if (ret) {
386a0afa 6391 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6392 "couldn't get PF vsi config, err %s aq_err %s\n",
6393 i40e_stat_str(&pf->hw, ret),
6394 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6395 return;
6396 }
6397 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6398 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6399 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6400
f1c7e72e
SN		 6401 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6402 if (ret) {
386a0afa 6403 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6404 "update vsi switch failed, err %s aq_err %s\n",
6405 i40e_stat_str(&pf->hw, ret),
6406 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6407 }
6408}
6409
6410/**
6411 * i40e_disable_pf_switch_lb
b40c82e6 6412 * @pf: pointer to the PF structure
386a0afa
AA		 6413 *
6414 * disable switch loop back or die - no point in a return value
6415 **/
6416static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6417{
6418 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6419 struct i40e_vsi_context ctxt;
f1c7e72e 6420 int ret;
386a0afa
AA		 6421
6422 ctxt.seid = pf->main_vsi_seid;
6423 ctxt.pf_num = pf->hw.pf_id;
6424 ctxt.vf_num = 0;
f1c7e72e
SN		 6425 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6426 if (ret) {
386a0afa 6427 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6428 "couldn't get PF vsi config, err %s aq_err %s\n",
6429 i40e_stat_str(&pf->hw, ret),
6430 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6431 return;
6432 }
6433 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6434 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6435 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6436
f1c7e72e
SN		 6437 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6438 if (ret) {
386a0afa 6439 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6440 "update vsi switch failed, err %s aq_err %s\n",
6441 i40e_stat_str(&pf->hw, ret),
6442 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6443 }
6444}
6445
51616018
NP		 6446/**
6447 * i40e_config_bridge_mode - Configure the HW bridge mode
6448 * @veb: pointer to the bridge instance
6449 *
6450 * Configure the loop back mode for the LAN VSI that is downlink to the
6451 * specified HW bridge instance. It is expected this function is called
6452 * when a new HW bridge is instantiated.
6453 **/
6454static void i40e_config_bridge_mode(struct i40e_veb *veb)
6455{
6456 struct i40e_pf *pf = veb->pf;
6457
6dec1017
SN		 6458 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6459 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6460 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6461 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6462 i40e_disable_pf_switch_lb(pf);
6463 else
6464 i40e_enable_pf_switch_lb(pf);
6465}
6466
41c445ff
JB		 6467/**
6468 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6469 * @veb: pointer to the VEB instance
6470 *
6471 * This is a recursive function that first builds the attached VSIs then
6472 * recurses in to build the next layer of VEB. We track the connections
6473 * through our own index numbers because the seid's from the HW could
6474 * change across the reset.
6475 **/
6476static int i40e_reconstitute_veb(struct i40e_veb *veb)
6477{
6478 struct i40e_vsi *ctl_vsi = NULL;
6479 struct i40e_pf *pf = veb->pf;
6480 int v, veb_idx;
6481 int ret;
6482
6483 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6484 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6485 if (pf->vsi[v] &&
6486 pf->vsi[v]->veb_idx == veb->idx &&
6487 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6488 ctl_vsi = pf->vsi[v];
6489 break;
6490 }
6491 }
6492 if (!ctl_vsi) {
6493 dev_info(&pf->pdev->dev,
6494 "missing owner VSI for veb_idx %d\n", veb->idx);
6495 ret = -ENOENT;
6496 goto end_reconstitute;
6497 }
6498 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6499 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6500 ret = i40e_add_vsi(ctl_vsi);
6501 if (ret) {
6502 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6503 "rebuild of veb_idx %d owner VSI failed: %d\n",
6504 veb->idx, ret);
41c445ff
JB		 6505 goto end_reconstitute;
6506 }
6507 i40e_vsi_reset_stats(ctl_vsi);
6508
6509 /* create the VEB in the switch and move the VSI onto the VEB */
6510 ret = i40e_add_veb(veb, ctl_vsi);
6511 if (ret)
6512 goto end_reconstitute;
6513
fc60861e
ASJ		 6514 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6515 veb->bridge_mode = BRIDGE_MODE_VEB;
6516 else
6517 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6518 i40e_config_bridge_mode(veb);
b64ba084 6519
41c445ff 6520 /* create the remaining VSIs attached to this VEB */
505682cd 6521 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6522 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6523 continue;
6524
6525 if (pf->vsi[v]->veb_idx == veb->idx) {
6526 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6527
41c445ff
JB		 6528 vsi->uplink_seid = veb->seid;
6529 ret = i40e_add_vsi(vsi);
6530 if (ret) {
6531 dev_info(&pf->pdev->dev,
6532 "rebuild of vsi_idx %d failed: %d\n",
6533 v, ret);
6534 goto end_reconstitute;
6535 }
6536 i40e_vsi_reset_stats(vsi);
6537 }
6538 }
6539
6540 /* create any VEBs attached to this VEB - RECURSION */
6541 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6542 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6543 pf->veb[veb_idx]->uplink_seid = veb->seid;
6544 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6545 if (ret)
6546 break;
6547 }
6548 }
6549
6550end_reconstitute:
6551 return ret;
6552}
6553
6554/**
6555 * i40e_get_capabilities - get info about the HW
6556 * @pf: the PF struct
6557 **/
6558static int i40e_get_capabilities(struct i40e_pf *pf)
6559{
6560 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6561 u16 data_size;
6562 int buf_len;
6563 int err;
6564
6565 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6566 do {
6567 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6568 if (!cap_buf)
6569 return -ENOMEM;
6570
6571 /* this loads the data into the hw struct for us */
6572 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6573 &data_size,
6574 i40e_aqc_opc_list_func_capabilities,
6575 NULL);
6576 /* data loaded, buffer no longer needed */
6577 kfree(cap_buf);
6578
6579 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6580 /* retry with a larger buffer */
6581 buf_len = data_size;
6582 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6583 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6584 "capability discovery failed, err %s aq_err %s\n",
6585 i40e_stat_str(&pf->hw, err),
6586 i40e_aq_str(&pf->hw,
6587 pf->hw.aq.asq_last_status));
41c445ff
JB		 6588 return -ENODEV;
6589 }
6590 } while (err);
6591
6592 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6593 dev_info(&pf->pdev->dev,
6594 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6595 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6596 pf->hw.func_caps.num_msix_vectors,
6597 pf->hw.func_caps.num_msix_vectors_vf,
6598 pf->hw.func_caps.fd_filters_guaranteed,
6599 pf->hw.func_caps.fd_filters_best_effort,
6600 pf->hw.func_caps.num_tx_qp,
6601 pf->hw.func_caps.num_vsis);
6602
7134f9ce
JB		 6603#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6604 + pf->hw.func_caps.num_vfs)
6605 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6606 dev_info(&pf->pdev->dev,
6607 "got num_vsis %d, setting num_vsis to %d\n",
6608 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6609 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6610 }
6611
41c445ff
JB		 6612 return 0;
6613}
6614
cbf61325
ASJ		 6615static int i40e_vsi_clear(struct i40e_vsi *vsi);
6616
41c445ff 6617/**
cbf61325 6618 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6619 * @pf: board private structure
6620 **/
cbf61325 6621static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6622{
6623 struct i40e_vsi *vsi;
8a9eb7d3 6624 int i;
41c445ff 6625
407e063c
JB		 6626 /* quick workaround for an NVM issue that leaves a critical register
6627 * uninitialized
6628 */
6629 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6630 static const u32 hkey[] = {
6631 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6632 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6633 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6634 0x95b3a76d};
6635
6636 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6637 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6638 }
6639
cbf61325 6640 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6641 return;
6642
cbf61325 6643 /* find existing VSI and see if it needs configuring */
41c445ff 6644 vsi = NULL;
505682cd 6645 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6646 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6647 vsi = pf->vsi[i];
cbf61325
ASJ		 6648 break;
6649 }
6650 }
6651
6652 /* create a new VSI if none exists */
41c445ff 6653 if (!vsi) {
cbf61325
ASJ		 6654 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6655 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6656 if (!vsi) {
6657 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6658 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6659 return;
41c445ff 6660 }
cbf61325 6661 }
41c445ff 6662
8a9eb7d3 6663 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6664}
6665
6666/**
6667 * i40e_fdir_teardown - release the Flow Director resources
6668 * @pf: board private structure
6669 **/
6670static void i40e_fdir_teardown(struct i40e_pf *pf)
6671{
6672 int i;
6673
17a73f6b 6674 i40e_fdir_filter_exit(pf);
505682cd 6675 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6676 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6677 i40e_vsi_release(pf->vsi[i]);
6678 break;
6679 }
6680 }
6681}
6682
6683/**
f650a38b 6684 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6685 * @pf: board private structure
6686 *
b40c82e6 6687 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6688 **/
23cfbe07 6689static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6690{
41c445ff 6691 struct i40e_hw *hw = &pf->hw;
60442dea 6692 i40e_status ret = 0;
41c445ff
JB		 6693 u32 v;
6694
6695 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6696 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6697 return;
41c445ff 6698
69bfb110 6699 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6700
41c445ff
JB		 6701 /* quiesce the VSIs and their queues that are not already DOWN */
6702 i40e_pf_quiesce_all_vsi(pf);
6703
505682cd 6704 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6705 if (pf->vsi[v])
6706 pf->vsi[v]->seid = 0;
6707 }
6708
6709 i40e_shutdown_adminq(&pf->hw);
6710
f650a38b 6711 /* call shutdown HMC */
60442dea
SN		 6712 if (hw->hmc.hmc_obj) {
6713 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6714 if (ret)
60442dea
SN		 6715 dev_warn(&pf->pdev->dev,
6716 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6717 }
f650a38b
ASJ		 6718}
6719
44033fac
JB		 6720/**
6721 * i40e_send_version - update firmware with driver version
6722 * @pf: PF struct
6723 */
6724static void i40e_send_version(struct i40e_pf *pf)
6725{
6726 struct i40e_driver_version dv;
6727
6728 dv.major_version = DRV_VERSION_MAJOR;
6729 dv.minor_version = DRV_VERSION_MINOR;
6730 dv.build_version = DRV_VERSION_BUILD;
6731 dv.subbuild_version = 0;
35a7d804 6732 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6733 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6734}
6735
f650a38b 6736/**
4dda12e6 6737 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6738 * @pf: board private structure
bc7d338f 6739 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6740 **/
bc7d338f 6741static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6742{
f650a38b 6743 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6744 u8 set_fc_aq_fail = 0;
f650a38b 6745 i40e_status ret;
4f2f017c 6746 u32 val;
f650a38b
ASJ		 6747 u32 v;
6748
41c445ff
JB		 6749 /* Now we wait for GRST to settle out.
6750 * We don't have to delete the VEBs or VSIs from the hw switch
6751 * because the reset will make them disappear.
6752 */
6753 ret = i40e_pf_reset(hw);
b5565400 6754 if (ret) {
41c445ff 6755 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6756 set_bit(__I40E_RESET_FAILED, &pf->state);
6757 goto clear_recovery;
b5565400 6758 }
41c445ff
JB		 6759 pf->pfr_count++;
6760
6761 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6762 goto clear_recovery;
69bfb110 6763 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6764
6765 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6766 ret = i40e_init_adminq(&pf->hw);
6767 if (ret) {
f1c7e72e
SN		 6768 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6769 i40e_stat_str(&pf->hw, ret),
6770 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6771 goto clear_recovery;
41c445ff
JB		 6772 }
6773
4eb3f768 6774 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6775 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6776 i40e_verify_eeprom(pf);
4eb3f768 6777
e78ac4bf 6778 i40e_clear_pxe_mode(hw);
41c445ff 6779 ret = i40e_get_capabilities(pf);
f1c7e72e 6780 if (ret)
41c445ff 6781 goto end_core_reset;
41c445ff 6782
41c445ff
JB		 6783 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6784 hw->func_caps.num_rx_qp,
6785 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6786 if (ret) {
6787 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6788 goto end_core_reset;
6789 }
6790 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6791 if (ret) {
6792 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6793 goto end_core_reset;
6794 }
6795
4e3b35b0
NP		 6796#ifdef CONFIG_I40E_DCB
6797 ret = i40e_init_pf_dcb(pf);
6798 if (ret) {
aebfc816
SN		 6799 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6800 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6801 /* Continue without DCB enabled */
4e3b35b0
NP		 6802 }
6803#endif /* CONFIG_I40E_DCB */
38e00438 6804#ifdef I40E_FCOE
21364bcf 6805 i40e_init_pf_fcoe(pf);
4e3b35b0 6806
38e00438 6807#endif
41c445ff 6808 /* do basic switch setup */
bc7d338f 6809 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6810 if (ret)
6811 goto end_core_reset;
6812
2f0aff41
SN		 6813 /* The driver only wants link up/down and module qualification
6814 * reports from firmware. Note the negative logic.
7e2453fe
JB		 6815 */
6816 ret = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41
SN		 6817 ~(I40E_AQ_EVENT_LINK_UPDOWN |
6818 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 6819 if (ret)
f1c7e72e
SN		 6820 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6821 i40e_stat_str(&pf->hw, ret),
6822 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6823
cafa2ee6
ASJ		 6824 /* make sure our flow control settings are restored */
6825 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6826 if (ret)
8279e495
NP		 6827 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6828 i40e_stat_str(&pf->hw, ret),
6829 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6830
41c445ff
JB		 6831 /* Rebuild the VSIs and VEBs that existed before reset.
6832 * They are still in our local switch element arrays, so only
6833 * need to rebuild the switch model in the HW.
6834 *
6835 * If there were VEBs but the reconstitution failed, we'll try
6836 * try to recover minimal use by getting the basic PF VSI working.
6837 */
6838 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6839 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6840 /* find the one VEB connected to the MAC, and find orphans */
6841 for (v = 0; v < I40E_MAX_VEB; v++) {
6842 if (!pf->veb[v])
6843 continue;
6844
6845 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6846 pf->veb[v]->uplink_seid == 0) {
6847 ret = i40e_reconstitute_veb(pf->veb[v]);
6848
6849 if (!ret)
6850 continue;
6851
6852 /* If Main VEB failed, we're in deep doodoo,
6853 * so give up rebuilding the switch and set up
6854 * for minimal rebuild of PF VSI.
6855 * If orphan failed, we'll report the error
6856 * but try to keep going.
6857 */
6858 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6859 dev_info(&pf->pdev->dev,
6860 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6861 ret);
6862 pf->vsi[pf->lan_vsi]->uplink_seid
6863 = pf->mac_seid;
6864 break;
6865 } else if (pf->veb[v]->uplink_seid == 0) {
6866 dev_info(&pf->pdev->dev,
6867 "rebuild of orphan VEB failed: %d\n",
6868 ret);
6869 }
6870 }
6871 }
6872 }
6873
6874 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6875 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6876 /* no VEB, so rebuild only the Main VSI */
6877 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6878 if (ret) {
6879 dev_info(&pf->pdev->dev,
6880 "rebuild of Main VSI failed: %d\n", ret);
6881 goto end_core_reset;
6882 }
6883 }
6884
4f2f017c
ASJ		 6885 /* Reconfigure hardware for allowing smaller MSS in the case
6886 * of TSO, so that we avoid the MDD being fired and causing
6887 * a reset in the case of small MSS+TSO.
6888 */
6889#define I40E_REG_MSS 0x000E64DC
6890#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6891#define I40E_64BYTE_MSS 0x400000
6892 val = rd32(hw, I40E_REG_MSS);
6893 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6894 val &= ~I40E_REG_MSS_MIN_MASK;
6895 val |= I40E_64BYTE_MSS;
6896 wr32(hw, I40E_REG_MSS, val);
6897 }
6898
8eed76fa 6899 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 6900 msleep(75);
6901 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6902 if (ret)
f1c7e72e
SN		 6903 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6904 i40e_stat_str(&pf->hw, ret),
6905 i40e_aq_str(&pf->hw,
6906 pf->hw.aq.asq_last_status));
cafa2ee6 6907 }
41c445ff
JB		 6908 /* reinit the misc interrupt */
6909 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6910 ret = i40e_setup_misc_vector(pf);
6911
e7358f54
ASJ		 6912 /* Add a filter to drop all Flow control frames from any VSI from being
6913 * transmitted. By doing so we stop a malicious VF from sending out
6914 * PAUSE or PFC frames and potentially controlling traffic for other
6915 * PF/VF VSIs.
6916 * The FW can still send Flow control frames if enabled.
6917 */
6918 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6919 pf->main_vsi_seid);
6920
41c445ff
JB		 6921 /* restart the VSIs that were rebuilt and running before the reset */
6922 i40e_pf_unquiesce_all_vsi(pf);
6923
69f64b2b
MW		 6924 if (pf->num_alloc_vfs) {
6925 for (v = 0; v < pf->num_alloc_vfs; v++)
6926 i40e_reset_vf(&pf->vf[v], true);
6927 }
6928
41c445ff 6929 /* tell the firmware that we're starting */
44033fac 6930 i40e_send_version(pf);
41c445ff
JB		 6931
6932end_core_reset:
a316f651
ASJ		 6933 clear_bit(__I40E_RESET_FAILED, &pf->state);
6934clear_recovery:
41c445ff
JB		 6935 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6936}
6937
f650a38b 6938/**
b40c82e6 6939 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6940 * @pf: board private structure
6941 *
6942 * Close up the VFs and other things in prep for a Core Reset,
6943 * then get ready to rebuild the world.
6944 **/
6945static void i40e_handle_reset_warning(struct i40e_pf *pf)
6946{
23cfbe07
SN		 6947 i40e_prep_for_reset(pf);
6948 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6949}
6950
41c445ff
JB		 6951/**
6952 * i40e_handle_mdd_event
b40c82e6 6953 * @pf: pointer to the PF structure
41c445ff
JB		 6954 *
6955 * Called from the MDD irq handler to identify possibly malicious vfs
6956 **/
6957static void i40e_handle_mdd_event(struct i40e_pf *pf)
6958{
6959 struct i40e_hw *hw = &pf->hw;
6960 bool mdd_detected = false;
df430b12 6961 bool pf_mdd_detected = false;
41c445ff
JB		 6962 struct i40e_vf *vf;
6963 u32 reg;
6964 int i;
6965
6966 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6967 return;
6968
6969 /* find what triggered the MDD event */
6970 reg = rd32(hw, I40E_GL_MDET_TX);
6971 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6972 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6973 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6974 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6975 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6976 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6977 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6978 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6979 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6980 pf->hw.func_caps.base_queue;
faf32978 6981 if (netif_msg_tx_err(pf))
b40c82e6 6982 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6983 event, queue, pf_num, vf_num);
41c445ff
JB		 6984 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6985 mdd_detected = true;
6986 }
6987 reg = rd32(hw, I40E_GL_MDET_RX);
6988 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6989 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6990 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6991 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6992 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6993 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6994 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6995 pf->hw.func_caps.base_queue;
faf32978
JB		 6996 if (netif_msg_rx_err(pf))
6997 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6998 event, queue, func);
41c445ff
JB		 6999 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
7000 mdd_detected = true;
7001 }
7002
df430b12
NP		 7003 if (mdd_detected) {
7004 reg = rd32(hw, I40E_PF_MDET_TX);
7005 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
7006 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 7007 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 7008 pf_mdd_detected = true;
7009 }
7010 reg = rd32(hw, I40E_PF_MDET_RX);
7011 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
7012 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 7013 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 7014 pf_mdd_detected = true;
7015 }
7016 /* Queue belongs to the PF, initiate a reset */
7017 if (pf_mdd_detected) {
7018 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7019 i40e_service_event_schedule(pf);
7020 }
7021 }
7022
41c445ff
JB		 7023 /* see if one of the VFs needs its hand slapped */
7024 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7025 vf = &(pf->vf[i]);
7026 reg = rd32(hw, I40E_VP_MDET_TX(i));
7027 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7028 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7029 vf->num_mdd_events++;
faf32978
JB		 7030 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7031 i);
41c445ff
JB		 7032 }
7033
7034 reg = rd32(hw, I40E_VP_MDET_RX(i));
7035 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7036 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7037 vf->num_mdd_events++;
faf32978
JB		 7038 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7039 i);
41c445ff
JB		 7040 }
7041
7042 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7043 dev_info(&pf->pdev->dev,
7044 "Too many MDD events on VF %d, disabled\n", i);
7045 dev_info(&pf->pdev->dev,
7046 "Use PF Control I/F to re-enable the VF\n");
7047 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7048 }
7049 }
7050
7051 /* re-enable mdd interrupt cause */
7052 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7053 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7054 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7055 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7056 i40e_flush(hw);
7057}
7058
a1c9a9d9 7059/**
6a899024 7060 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7061 * @pf: board private structure
7062 **/
6a899024 7063static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7064{
6a899024 7065#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9
JK		 7066 struct i40e_hw *hw = &pf->hw;
7067 i40e_status ret;
a1c9a9d9
JK		 7068 __be16 port;
7069 int i;
7070
6a899024 7071 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7072 return;
7073
6a899024 7074 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7075
7076 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7077 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7078 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7079 port = pf->udp_ports[i].index;
c22c06c8
SN		 7080 if (port)
7081 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7082 pf->udp_ports[i].type,
c22c06c8
SN		 7083 NULL, NULL);
7084 else
7085 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7086
7087 if (ret) {
c22c06c8 7088 dev_info(&pf->pdev->dev,
f1c7e72e 7089 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 7090 port ? "add" : "delete",
f1c7e72e
SN		 7091 ntohs(port), i,
7092 i40e_stat_str(&pf->hw, ret),
7093 i40e_aq_str(&pf->hw,
7094 pf->hw.aq.asq_last_status));
6a899024 7095 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7096 }
7097 }
7098 }
6a899024 7099#endif
a1c9a9d9
JK		 7100}
7101
41c445ff
JB		 7102/**
7103 * i40e_service_task - Run the driver's async subtasks
7104 * @work: pointer to work_struct containing our data
7105 **/
7106static void i40e_service_task(struct work_struct *work)
7107{
7108 struct i40e_pf *pf = container_of(work,
7109 struct i40e_pf,
7110 service_task);
7111 unsigned long start_time = jiffies;
7112
e57a2fea
SN		 7113 /* don't bother with service tasks if a reset is in progress */
7114 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7115 i40e_service_event_complete(pf);
7116 return;
7117 }
7118
b03a8c1f 7119 i40e_detect_recover_hung(pf);
41c445ff
JB		 7120 i40e_reset_subtask(pf);
7121 i40e_handle_mdd_event(pf);
7122 i40e_vc_process_vflr_event(pf);
7123 i40e_watchdog_subtask(pf);
7124 i40e_fdir_reinit_subtask(pf);
41c445ff 7125 i40e_sync_filters_subtask(pf);
6a899024 7126 i40e_sync_udp_filters_subtask(pf);
41c445ff
JB		 7127 i40e_clean_adminq_subtask(pf);
7128
7129 i40e_service_event_complete(pf);
7130
7131 /* If the tasks have taken longer than one timer cycle or there
7132 * is more work to be done, reschedule the service task now
7133 * rather than wait for the timer to tick again.
7134 */
7135 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7136 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7137 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7138 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7139 i40e_service_event_schedule(pf);
7140}
7141
7142/**
7143 * i40e_service_timer - timer callback
7144 * @data: pointer to PF struct
7145 **/
7146static void i40e_service_timer(unsigned long data)
7147{
7148 struct i40e_pf *pf = (struct i40e_pf *)data;
7149
7150 mod_timer(&pf->service_timer,
7151 round_jiffies(jiffies + pf->service_timer_period));
7152 i40e_service_event_schedule(pf);
7153}
7154
7155/**
7156 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7157 * @vsi: the VSI being configured
7158 **/
7159static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7160{
7161 struct i40e_pf *pf = vsi->back;
7162
7163 switch (vsi->type) {
7164 case I40E_VSI_MAIN:
7165 vsi->alloc_queue_pairs = pf->num_lan_qps;
7166 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7167 I40E_REQ_DESCRIPTOR_MULTIPLE);
7168 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7169 vsi->num_q_vectors = pf->num_lan_msix;
7170 else
7171 vsi->num_q_vectors = 1;
7172
7173 break;
7174
7175 case I40E_VSI_FDIR:
7176 vsi->alloc_queue_pairs = 1;
7177 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7178 I40E_REQ_DESCRIPTOR_MULTIPLE);
7179 vsi->num_q_vectors = 1;
7180 break;
7181
7182 case I40E_VSI_VMDQ2:
7183 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7184 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7185 I40E_REQ_DESCRIPTOR_MULTIPLE);
7186 vsi->num_q_vectors = pf->num_vmdq_msix;
7187 break;
7188
7189 case I40E_VSI_SRIOV:
7190 vsi->alloc_queue_pairs = pf->num_vf_qps;
7191 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7192 I40E_REQ_DESCRIPTOR_MULTIPLE);
7193 break;
7194
38e00438
VD		 7195#ifdef I40E_FCOE
7196 case I40E_VSI_FCOE:
7197 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7198 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7199 I40E_REQ_DESCRIPTOR_MULTIPLE);
7200 vsi->num_q_vectors = pf->num_fcoe_msix;
7201 break;
7202
7203#endif /* I40E_FCOE */
41c445ff
JB		 7204 default:
7205 WARN_ON(1);
7206 return -ENODATA;
7207 }
7208
7209 return 0;
7210}
7211
f650a38b
ASJ		 7212/**
7213 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7214 * @type: VSI pointer
bc7d338f 7215 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7216 *
7217 * On error: returns error code (negative)
7218 * On success: returns 0
7219 **/
bc7d338f 7220static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7221{
7222 int size;
7223 int ret = 0;
7224
ac6c5e3d 7225 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7226 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7227 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7228 if (!vsi->tx_rings)
7229 return -ENOMEM;
f650a38b
ASJ		 7230 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7231
bc7d338f
ASJ		 7232 if (alloc_qvectors) {
7233 /* allocate memory for q_vector pointers */
f57e4fbd 7234 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7235 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7236 if (!vsi->q_vectors) {
7237 ret = -ENOMEM;
7238 goto err_vectors;
7239 }
f650a38b
ASJ		 7240 }
7241 return ret;
7242
7243err_vectors:
7244 kfree(vsi->tx_rings);
7245 return ret;
7246}
7247
41c445ff
JB		 7248/**
7249 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7250 * @pf: board private structure
7251 * @type: type of VSI
7252 *
7253 * On error: returns error code (negative)
7254 * On success: returns vsi index in PF (positive)
7255 **/
7256static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7257{
7258 int ret = -ENODEV;
7259 struct i40e_vsi *vsi;
7260 int vsi_idx;
7261 int i;
7262
7263 /* Need to protect the allocation of the VSIs at the PF level */
7264 mutex_lock(&pf->switch_mutex);
7265
7266 /* VSI list may be fragmented if VSI creation/destruction has
7267 * been happening. We can afford to do a quick scan to look
7268 * for any free VSIs in the list.
7269 *
7270 * find next empty vsi slot, looping back around if necessary
7271 */
7272 i = pf->next_vsi;
505682cd 7273 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7274 i++;
505682cd 7275 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7276 i = 0;
7277 while (i < pf->next_vsi && pf->vsi[i])
7278 i++;
7279 }
7280
505682cd 7281 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7282 vsi_idx = i; /* Found one! */
7283 } else {
7284 ret = -ENODEV;
493fb300 7285 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7286 }
7287 pf->next_vsi = ++i;
7288
7289 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7290 if (!vsi) {
7291 ret = -ENOMEM;
493fb300 7292 goto unlock_pf;
41c445ff
JB		 7293 }
7294 vsi->type = type;
7295 vsi->back = pf;
7296 set_bit(__I40E_DOWN, &vsi->state);
7297 vsi->flags = 0;
7298 vsi->idx = vsi_idx;
7299 vsi->rx_itr_setting = pf->rx_itr_default;
7300 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7301 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7302 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7303 pf->rss_table_size : 64;
41c445ff
JB		 7304 vsi->netdev_registered = false;
7305 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7306 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7307 vsi->irqs_ready = false;
41c445ff 7308
9f65e15b
AD		 7309 ret = i40e_set_num_rings_in_vsi(vsi);
7310 if (ret)
7311 goto err_rings;
7312
bc7d338f 7313 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7314 if (ret)
9f65e15b 7315 goto err_rings;
493fb300 7316
41c445ff
JB		 7317 /* Setup default MSIX irq handler for VSI */
7318 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7319
21659035
KP		 7320 /* Initialize VSI lock */
7321 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7322 pf->vsi[vsi_idx] = vsi;
7323 ret = vsi_idx;
493fb300
AD		 7324 goto unlock_pf;
7325
9f65e15b 7326err_rings:
493fb300
AD		 7327 pf->next_vsi = i - 1;
7328 kfree(vsi);
7329unlock_pf:
41c445ff
JB		 7330 mutex_unlock(&pf->switch_mutex);
7331 return ret;
7332}
7333
f650a38b
ASJ		 7334/**
7335 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7336 * @type: VSI pointer
bc7d338f 7337 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7338 *
7339 * On error: returns error code (negative)
7340 * On success: returns 0
7341 **/
bc7d338f 7342static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7343{
7344 /* free the ring and vector containers */
bc7d338f
ASJ		 7345 if (free_qvectors) {
7346 kfree(vsi->q_vectors);
7347 vsi->q_vectors = NULL;
7348 }
f650a38b
ASJ		 7349 kfree(vsi->tx_rings);
7350 vsi->tx_rings = NULL;
7351 vsi->rx_rings = NULL;
7352}
7353
28c5869f
HZ		 7354/**
7355 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7356 * and lookup table
7357 * @vsi: Pointer to VSI structure
7358 */
7359static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7360{
7361 if (!vsi)
7362 return;
7363
7364 kfree(vsi->rss_hkey_user);
7365 vsi->rss_hkey_user = NULL;
7366
7367 kfree(vsi->rss_lut_user);
7368 vsi->rss_lut_user = NULL;
7369}
7370
41c445ff
JB		 7371/**
7372 * i40e_vsi_clear - Deallocate the VSI provided
7373 * @vsi: the VSI being un-configured
7374 **/
7375static int i40e_vsi_clear(struct i40e_vsi *vsi)
7376{
7377 struct i40e_pf *pf;
7378
7379 if (!vsi)
7380 return 0;
7381
7382 if (!vsi->back)
7383 goto free_vsi;
7384 pf = vsi->back;
7385
7386 mutex_lock(&pf->switch_mutex);
7387 if (!pf->vsi[vsi->idx]) {
7388 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7389 vsi->idx, vsi->idx, vsi, vsi->type);
7390 goto unlock_vsi;
7391 }
7392
7393 if (pf->vsi[vsi->idx] != vsi) {
7394 dev_err(&pf->pdev->dev,
7395 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7396 pf->vsi[vsi->idx]->idx,
7397 pf->vsi[vsi->idx],
7398 pf->vsi[vsi->idx]->type,
7399 vsi->idx, vsi, vsi->type);
7400 goto unlock_vsi;
7401 }
7402
b40c82e6 7403 /* updates the PF for this cleared vsi */
41c445ff
JB		 7404 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7405 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7406
bc7d338f 7407 i40e_vsi_free_arrays(vsi, true);
28c5869f 7408 i40e_clear_rss_config_user(vsi);
493fb300 7409
41c445ff
JB		 7410 pf->vsi[vsi->idx] = NULL;
7411 if (vsi->idx < pf->next_vsi)
7412 pf->next_vsi = vsi->idx;
7413
7414unlock_vsi:
7415 mutex_unlock(&pf->switch_mutex);
7416free_vsi:
7417 kfree(vsi);
7418
7419 return 0;
7420}
7421
9f65e15b
AD		 7422/**
7423 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7424 * @vsi: the VSI being cleaned
7425 **/
be1d5eea 7426static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7427{
7428 int i;
7429
8e9dca53 7430 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7431 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7432 kfree_rcu(vsi->tx_rings[i], rcu);
7433 vsi->tx_rings[i] = NULL;
7434 vsi->rx_rings[i] = NULL;
7435 }
be1d5eea 7436 }
9f65e15b
AD		 7437}
7438
41c445ff
JB		 7439/**
7440 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7441 * @vsi: the VSI being configured
7442 **/
7443static int i40e_alloc_rings(struct i40e_vsi *vsi)
7444{
e7046ee1 7445 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7446 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7447 int i;
7448
41c445ff 7449 /* Set basic values in the rings to be used later during open() */
d7397644 7450 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7451 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7452 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7453 if (!tx_ring)
7454 goto err_out;
41c445ff
JB		 7455
7456 tx_ring->queue_index = i;
7457 tx_ring->reg_idx = vsi->base_queue + i;
7458 tx_ring->ring_active = false;
7459 tx_ring->vsi = vsi;
7460 tx_ring->netdev = vsi->netdev;
7461 tx_ring->dev = &pf->pdev->dev;
7462 tx_ring->count = vsi->num_desc;
7463 tx_ring->size = 0;
7464 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7465 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7466 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7467 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7468 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7469 vsi->tx_rings[i] = tx_ring;
41c445ff 7470
9f65e15b 7471 rx_ring = &tx_ring[1];
41c445ff
JB		 7472 rx_ring->queue_index = i;
7473 rx_ring->reg_idx = vsi->base_queue + i;
7474 rx_ring->ring_active = false;
7475 rx_ring->vsi = vsi;
7476 rx_ring->netdev = vsi->netdev;
7477 rx_ring->dev = &pf->pdev->dev;
7478 rx_ring->count = vsi->num_desc;
7479 rx_ring->size = 0;
7480 rx_ring->dcb_tc = 0;
7481 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7482 set_ring_16byte_desc_enabled(rx_ring);
7483 else
7484 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7485 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7486 }
7487
7488 return 0;
9f65e15b
AD		 7489
7490err_out:
7491 i40e_vsi_clear_rings(vsi);
7492 return -ENOMEM;
41c445ff
JB		 7493}
7494
7495/**
7496 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7497 * @pf: board private structure
7498 * @vectors: the number of MSI-X vectors to request
7499 *
7500 * Returns the number of vectors reserved, or error
7501 **/
7502static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7503{
7b37f376
AG		 7504 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7505 I40E_MIN_MSIX, vectors);
7506 if (vectors < 0) {
41c445ff 7507 dev_info(&pf->pdev->dev,
7b37f376 7508 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7509 vectors = 0;
7510 }
7511
7512 return vectors;
7513}
7514
7515/**
7516 * i40e_init_msix - Setup the MSIX capability
7517 * @pf: board private structure
7518 *
7519 * Work with the OS to set up the MSIX vectors needed.
7520 *
3b444399 7521 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7522 **/
7523static int i40e_init_msix(struct i40e_pf *pf)
7524{
41c445ff 7525 struct i40e_hw *hw = &pf->hw;
1e200e4a 7526 int vectors_left;
41c445ff 7527 int v_budget, i;
3b444399 7528 int v_actual;
41c445ff
JB		 7529
7530 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7531 return -ENODEV;
7532
7533 /* The number of vectors we'll request will be comprised of:
7534 * - Add 1 for "other" cause for Admin Queue events, etc.
7535 * - The number of LAN queue pairs
f8ff1464
ASJ		 7536 * - Queues being used for RSS.
7537 * We don't need as many as max_rss_size vectors.
7538 * use rss_size instead in the calculation since that
7539 * is governed by number of cpus in the system.
7540 * - assumes symmetric Tx/Rx pairing
41c445ff 7541 * - The number of VMDq pairs
38e00438
VD		 7542#ifdef I40E_FCOE
7543 * - The number of FCOE qps.
7544#endif
41c445ff
JB		 7545 * Once we count this up, try the request.
7546 *
7547 * If we can't get what we want, we'll simplify to nearly nothing
7548 * and try again. If that still fails, we punt.
7549 */
1e200e4a
SN		 7550 vectors_left = hw->func_caps.num_msix_vectors;
7551 v_budget = 0;
7552
7553 /* reserve one vector for miscellaneous handler */
7554 if (vectors_left) {
7555 v_budget++;
7556 vectors_left--;
7557 }
7558
7559 /* reserve vectors for the main PF traffic queues */
7560 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7561 vectors_left -= pf->num_lan_msix;
7562 v_budget += pf->num_lan_msix;
7563
7564 /* reserve one vector for sideband flow director */
7565 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7566 if (vectors_left) {
7567 v_budget++;
7568 vectors_left--;
7569 } else {
7570 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7571 }
7572 }
83840e4b 7573
38e00438 7574#ifdef I40E_FCOE
1e200e4a 7575 /* can we reserve enough for FCoE? */
38e00438 7576 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7577 if (!vectors_left)
7578 pf->num_fcoe_msix = 0;
7579 else if (vectors_left >= pf->num_fcoe_qps)
7580 pf->num_fcoe_msix = pf->num_fcoe_qps;
7581 else
7582 pf->num_fcoe_msix = 1;
38e00438 7583 v_budget += pf->num_fcoe_msix;
1e200e4a 7584 vectors_left -= pf->num_fcoe_msix;
38e00438 7585 }
1e200e4a 7586
38e00438 7587#endif
1e200e4a
SN		 7588 /* any vectors left over go for VMDq support */
7589 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7590 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7591 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7592
7593 /* if we're short on vectors for what's desired, we limit
7594 * the queues per vmdq. If this is still more than are
7595 * available, the user will need to change the number of
7596 * queues/vectors used by the PF later with the ethtool
7597 * channels command
7598 */
7599 if (vmdq_vecs < vmdq_vecs_wanted)
7600 pf->num_vmdq_qps = 1;
7601 pf->num_vmdq_msix = pf->num_vmdq_qps;
7602
7603 v_budget += vmdq_vecs;
7604 vectors_left -= vmdq_vecs;
7605 }
41c445ff
JB		 7606
7607 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7608 GFP_KERNEL);
7609 if (!pf->msix_entries)
7610 return -ENOMEM;
7611
7612 for (i = 0; i < v_budget; i++)
7613 pf->msix_entries[i].entry = i;
3b444399 7614 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7615
3b444399 7616 if (v_actual != v_budget) {
a34977ba
ASJ		 7617 /* If we have limited resources, we will start with no vectors
7618 * for the special features and then allocate vectors to some
7619 * of these features based on the policy and at the end disable
7620 * the features that did not get any vectors.
7621 */
38e00438
VD		 7622#ifdef I40E_FCOE
7623 pf->num_fcoe_qps = 0;
7624 pf->num_fcoe_msix = 0;
7625#endif
a34977ba
ASJ		 7626 pf->num_vmdq_msix = 0;
7627 }
7628
3b444399 7629 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7630 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7631 kfree(pf->msix_entries);
7632 pf->msix_entries = NULL;
7633 return -ENODEV;
7634
3b444399 7635 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7636 /* Adjust for minimal MSIX use */
41c445ff
JB		 7637 pf->num_vmdq_vsis = 0;
7638 pf->num_vmdq_qps = 0;
41c445ff
JB		 7639 pf->num_lan_qps = 1;
7640 pf->num_lan_msix = 1;
7641
3b444399
SN		 7642 } else if (v_actual != v_budget) {
7643 int vec;
7644
a34977ba 7645 /* reserve the misc vector */
3b444399 7646 vec = v_actual - 1;
a34977ba 7647
41c445ff
JB		 7648 /* Scale vector usage down */
7649 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7650 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7651 pf->num_vmdq_qps = 1;
7652 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7653
7654 /* partition out the remaining vectors */
7655 switch (vec) {
7656 case 2:
41c445ff
JB		 7657 pf->num_lan_msix = 1;
7658 break;
7659 case 3:
38e00438
VD		 7660#ifdef I40E_FCOE
7661 /* give one vector to FCoE */
7662 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7663 pf->num_lan_msix = 1;
7664 pf->num_fcoe_msix = 1;
7665 }
7666#else
41c445ff 7667 pf->num_lan_msix = 2;
38e00438 7668#endif
41c445ff
JB		 7669 break;
7670 default:
38e00438
VD		 7671#ifdef I40E_FCOE
7672 /* give one vector to FCoE */
7673 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7674 pf->num_fcoe_msix = 1;
7675 vec--;
7676 }
7677#endif
1e200e4a
SN		 7678 /* give the rest to the PF */
7679 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7680 break;
7681 }
7682 }
7683
a34977ba
ASJ		 7684 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7685 (pf->num_vmdq_msix == 0)) {
7686 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7687 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7688 }
38e00438
VD		 7689#ifdef I40E_FCOE
7690
7691 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7692 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7693 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7694 }
7695#endif
3b444399 7696 return v_actual;
41c445ff
JB		 7697}
7698
493fb300 7699/**
90e04070 7700 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7701 * @vsi: the VSI being configured
7702 * @v_idx: index of the vector in the vsi struct
7703 *
7704 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7705 **/
90e04070 7706static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7707{
7708 struct i40e_q_vector *q_vector;
7709
7710 /* allocate q_vector */
7711 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7712 if (!q_vector)
7713 return -ENOMEM;
7714
7715 q_vector->vsi = vsi;
7716 q_vector->v_idx = v_idx;
7717 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7718 if (vsi->netdev)
7719 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7720 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7721
cd0b6fa6
AD		 7722 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7723 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7724
493fb300
AD		 7725 /* tie q_vector and vsi together */
7726 vsi->q_vectors[v_idx] = q_vector;
7727
7728 return 0;
7729}
7730
41c445ff 7731/**
90e04070 7732 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7733 * @vsi: the VSI being configured
7734 *
7735 * We allocate one q_vector per queue interrupt. If allocation fails we
7736 * return -ENOMEM.
7737 **/
90e04070 7738static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7739{
7740 struct i40e_pf *pf = vsi->back;
7741 int v_idx, num_q_vectors;
493fb300 7742 int err;
41c445ff
JB		 7743
7744 /* if not MSIX, give the one vector only to the LAN VSI */
7745 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7746 num_q_vectors = vsi->num_q_vectors;
7747 else if (vsi == pf->vsi[pf->lan_vsi])
7748 num_q_vectors = 1;
7749 else
7750 return -EINVAL;
7751
41c445ff 7752 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7753 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7754 if (err)
7755 goto err_out;
41c445ff
JB		 7756 }
7757
7758 return 0;
493fb300
AD		 7759
7760err_out:
7761 while (v_idx--)
7762 i40e_free_q_vector(vsi, v_idx);
7763
7764 return err;
41c445ff
JB		 7765}
7766
7767/**
7768 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7769 * @pf: board private structure to initialize
7770 **/
c1147280 7771static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7772{
3b444399
SN		 7773 int vectors = 0;
7774 ssize_t size;
41c445ff
JB		 7775
7776 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7777 vectors = i40e_init_msix(pf);
7778 if (vectors < 0) {
60ea5f83 7779 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7780#ifdef I40E_FCOE
7781 I40E_FLAG_FCOE_ENABLED |
7782#endif
60ea5f83 7783 I40E_FLAG_RSS_ENABLED |
4d9b6043 7784 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7785 I40E_FLAG_SRIOV_ENABLED |
7786 I40E_FLAG_FD_SB_ENABLED |
7787 I40E_FLAG_FD_ATR_ENABLED |
7788 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7789
7790 /* rework the queue expectations without MSIX */
7791 i40e_determine_queue_usage(pf);
7792 }
7793 }
7794
7795 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7796 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7797 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7798 vectors = pci_enable_msi(pf->pdev);
7799 if (vectors < 0) {
7800 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7801 vectors);
41c445ff
JB		 7802 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7803 }
3b444399 7804 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7805 }
7806
958a3e3b 7807 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7808 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7809
3b444399
SN		 7810 /* set up vector assignment tracking */
7811 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7812 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7813 if (!pf->irq_pile) {
7814 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7815 return -ENOMEM;
7816 }
3b444399
SN		 7817 pf->irq_pile->num_entries = vectors;
7818 pf->irq_pile->search_hint = 0;
7819
c1147280 7820 /* track first vector for misc interrupts, ignore return */
3b444399 7821 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7822
7823 return 0;
41c445ff
JB		 7824}
7825
7826/**
7827 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7828 * @pf: board private structure
7829 *
7830 * This sets up the handler for MSIX 0, which is used to manage the
7831 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7832 * when in MSI or Legacy interrupt mode.
7833 **/
7834static int i40e_setup_misc_vector(struct i40e_pf *pf)
7835{
7836 struct i40e_hw *hw = &pf->hw;
7837 int err = 0;
7838
7839 /* Only request the irq if this is the first time through, and
7840 * not when we're rebuilding after a Reset
7841 */
7842 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7843 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7844 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7845 if (err) {
7846 dev_info(&pf->pdev->dev,
77fa28be 7847 "request_irq for %s failed: %d\n",
b294ac70 7848 pf->int_name, err);
41c445ff
JB		 7849 return -EFAULT;
7850 }
7851 }
7852
ab437b5a 7853 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7854
7855 /* associate no queues to the misc vector */
7856 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7857 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7858
7859 i40e_flush(hw);
7860
7861 i40e_irq_dynamic_enable_icr0(pf);
7862
7863 return err;
7864}
7865
7866/**
e25d00b8
ASJ		 7867 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7868 * @vsi: vsi structure
7869 * @seed: RSS hash seed
7870 **/
e69ff813
HZ		 7871static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7872 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7873{
7874 struct i40e_aqc_get_set_rss_key_data rss_key;
7875 struct i40e_pf *pf = vsi->back;
7876 struct i40e_hw *hw = &pf->hw;
7877 bool pf_lut = false;
7878 u8 *rss_lut;
7879 int ret, i;
7880
7881 memset(&rss_key, 0, sizeof(rss_key));
7882 memcpy(&rss_key, seed, sizeof(rss_key));
7883
7884 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7885 if (!rss_lut)
7886 return -ENOMEM;
7887
7888 /* Populate the LUT with max no. of queues in round robin fashion */
7889 for (i = 0; i < vsi->rss_table_size; i++)
7890 rss_lut[i] = i % vsi->rss_size;
7891
7892 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7893 if (ret) {
7894 dev_info(&pf->pdev->dev,
7895 "Cannot set RSS key, err %s aq_err %s\n",
7896 i40e_stat_str(&pf->hw, ret),
7897 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7898 goto config_rss_aq_out;
e25d00b8
ASJ		 7899 }
7900
7901 if (vsi->type == I40E_VSI_MAIN)
7902 pf_lut = true;
7903
7904 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7905 vsi->rss_table_size);
7906 if (ret)
7907 dev_info(&pf->pdev->dev,
7908 "Cannot set RSS lut, err %s aq_err %s\n",
7909 i40e_stat_str(&pf->hw, ret),
7910 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7911
126b63d9
AS		 7912config_rss_aq_out:
7913 kfree(rss_lut);
e25d00b8
ASJ		 7914 return ret;
7915}
7916
7917/**
7918 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7919 * @vsi: VSI structure
7920 **/
7921static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7922{
7923 u8 seed[I40E_HKEY_ARRAY_SIZE];
7924 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7925 u8 *lut;
7926 int ret;
7927
7928 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7929 return 0;
7930
7931 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7932 if (!lut)
7933 return -ENOMEM;
e25d00b8 7934
e69ff813 7935 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7936 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7937 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7938 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7939 kfree(lut);
e25d00b8 7940
e69ff813 7941 return ret;
e25d00b8
ASJ		 7942}
7943
95a73780
ASJ		 7944/**
7945 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
7946 * @vsi: Pointer to vsi structure
7947 * @seed: Buffter to store the hash keys
7948 * @lut: Buffer to store the lookup table entries
7949 * @lut_size: Size of buffer to store the lookup table entries
7950 *
7951 * Return 0 on success, negative on failure
7952 */
7953static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7954 u8 *lut, u16 lut_size)
7955{
7956 struct i40e_pf *pf = vsi->back;
7957 struct i40e_hw *hw = &pf->hw;
7958 int ret = 0;
7959
7960 if (seed) {
7961 ret = i40e_aq_get_rss_key(hw, vsi->id,
7962 (struct i40e_aqc_get_set_rss_key_data *)seed);
7963 if (ret) {
7964 dev_info(&pf->pdev->dev,
7965 "Cannot get RSS key, err %s aq_err %s\n",
7966 i40e_stat_str(&pf->hw, ret),
7967 i40e_aq_str(&pf->hw,
7968 pf->hw.aq.asq_last_status));
7969 return ret;
7970 }
7971 }
7972
7973 if (lut) {
7974 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
7975
7976 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
7977 if (ret) {
7978 dev_info(&pf->pdev->dev,
7979 "Cannot get RSS lut, err %s aq_err %s\n",
7980 i40e_stat_str(&pf->hw, ret),
7981 i40e_aq_str(&pf->hw,
7982 pf->hw.aq.asq_last_status));
7983 return ret;
7984 }
7985 }
7986
7987 return ret;
7988}
7989
e25d00b8 7990/**
043dd650 7991 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 7992 * @vsi: Pointer to vsi structure
e25d00b8 7993 * @seed: RSS hash seed
e69ff813
HZ		 7994 * @lut: Lookup table
7995 * @lut_size: Lookup table size
7996 *
7997 * Returns 0 on success, negative on failure
41c445ff 7998 **/
e69ff813
HZ		 7999static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
8000 const u8 *lut, u16 lut_size)
41c445ff 8001{
e69ff813 8002 struct i40e_pf *pf = vsi->back;
4617e8c0 8003 struct i40e_hw *hw = &pf->hw;
e69ff813 8004 u8 i;
41c445ff 8005
e25d00b8 8006 /* Fill out hash function seed */
e69ff813
HZ		 8007 if (seed) {
8008 u32 *seed_dw = (u32 *)seed;
8009
8010 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8011 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
8012 }
8013
8014 if (lut) {
8015 u32 *lut_dw = (u32 *)lut;
8016
8017 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8018 return -EINVAL;
8019
8020 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8021 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
e25d00b8
ASJ		 8022 }
8023 i40e_flush(hw);
8024
8025 return 0;
8026}
8027
043dd650
HZ		 8028/**
8029 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
8030 * @vsi: Pointer to VSI structure
8031 * @seed: Buffer to store the keys
8032 * @lut: Buffer to store the lookup table entries
8033 * @lut_size: Size of buffer to store the lookup table entries
8034 *
8035 * Returns 0 on success, negative on failure
8036 */
8037static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
8038 u8 *lut, u16 lut_size)
8039{
8040 struct i40e_pf *pf = vsi->back;
8041 struct i40e_hw *hw = &pf->hw;
8042 u16 i;
8043
8044 if (seed) {
8045 u32 *seed_dw = (u32 *)seed;
8046
8047 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8048 seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
8049 }
8050 if (lut) {
8051 u32 *lut_dw = (u32 *)lut;
8052
8053 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8054 return -EINVAL;
8055 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8056 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
8057 }
8058
8059 return 0;
8060}
8061
8062/**
8063 * i40e_config_rss - Configure RSS keys and lut
8064 * @vsi: Pointer to VSI structure
8065 * @seed: RSS hash seed
8066 * @lut: Lookup table
8067 * @lut_size: Lookup table size
8068 *
8069 * Returns 0 on success, negative on failure
8070 */
8071int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8072{
8073 struct i40e_pf *pf = vsi->back;
8074
8075 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8076 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8077 else
8078 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8079}
8080
8081/**
8082 * i40e_get_rss - Get RSS keys and lut
8083 * @vsi: Pointer to VSI structure
8084 * @seed: Buffer to store the keys
8085 * @lut: Buffer to store the lookup table entries
8086 * lut_size: Size of buffer to store the lookup table entries
8087 *
8088 * Returns 0 on success, negative on failure
8089 */
8090int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8091{
95a73780
ASJ		 8092 struct i40e_pf *pf = vsi->back;
8093
8094 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8095 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
8096 else
8097 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
043dd650
HZ		 8098}
8099
e69ff813
HZ		 8100/**
8101 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8102 * @pf: Pointer to board private structure
8103 * @lut: Lookup table
8104 * @rss_table_size: Lookup table size
8105 * @rss_size: Range of queue number for hashing
8106 */
8107static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8108 u16 rss_table_size, u16 rss_size)
8109{
8110 u16 i;
8111
8112 for (i = 0; i < rss_table_size; i++)
8113 lut[i] = i % rss_size;
8114}
8115
e25d00b8 8116/**
043dd650 8117 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8118 * @pf: board private structure
8119 **/
043dd650 8120static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8121{
8122 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8123 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8124 u8 *lut;
e25d00b8
ASJ		 8125 struct i40e_hw *hw = &pf->hw;
8126 u32 reg_val;
8127 u64 hena;
e69ff813 8128 int ret;
e25d00b8 8129
41c445ff
JB		 8130 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
8131 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
8132 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8133 hena |= i40e_pf_get_default_rss_hena(pf);
8134
41c445ff
JB		 8135 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
8136 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
8137
e25d00b8 8138 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 8139 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8140 reg_val = (pf->rss_table_size == 512) ?
8141 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8142 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 8143 wr32(hw, I40E_PFQF_CTL_0, reg_val);
8144
28c5869f
HZ		 8145 /* Determine the RSS size of the VSI */
8146 if (!vsi->rss_size)
acd65448
HZ		 8147 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8148 vsi->num_queue_pairs);
28c5869f 8149
e69ff813
HZ		 8150 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8151 if (!lut)
8152 return -ENOMEM;
8153
28c5869f
HZ		 8154 /* Use user configured lut if there is one, otherwise use default */
8155 if (vsi->rss_lut_user)
8156 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8157 else
8158 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8159
28c5869f
HZ		 8160 /* Use user configured hash key if there is one, otherwise
8161 * use default.
8162 */
8163 if (vsi->rss_hkey_user)
8164 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8165 else
8166 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8167 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8168 kfree(lut);
8169
8170 return ret;
41c445ff
JB		 8171}
8172
f8ff1464
ASJ		 8173/**
8174 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8175 * @pf: board private structure
8176 * @queue_count: the requested queue count for rss.
8177 *
8178 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8179 * count which may be different from the requested queue count.
8180 **/
8181int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8182{
9a3bd2f1
ASJ		 8183 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8184 int new_rss_size;
8185
f8ff1464
ASJ		 8186 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8187 return 0;
8188
9a3bd2f1 8189 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8190
9a3bd2f1
ASJ		 8191 if (queue_count != vsi->num_queue_pairs) {
8192 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8193 i40e_prep_for_reset(pf);
8194
acd65448 8195 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8196
8197 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8198
8199 /* Discard the user configured hash keys and lut, if less
8200 * queues are enabled.
8201 */
8202 if (queue_count < vsi->rss_size) {
8203 i40e_clear_rss_config_user(vsi);
8204 dev_dbg(&pf->pdev->dev,
8205 "discard user configured hash keys and lut\n");
8206 }
8207
8208 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8209 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8210 vsi->num_queue_pairs);
28c5869f 8211
043dd650 8212 i40e_pf_config_rss(pf);
f8ff1464 8213 }
e36b0b11
HZ		 8214 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8215 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8216 return pf->alloc_rss_size;
f8ff1464
ASJ		 8217}
8218
f4492db1
GR		 8219/**
8220 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8221 * @pf: board private structure
8222 **/
8223i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8224{
8225 i40e_status status;
8226 bool min_valid, max_valid;
8227 u32 max_bw, min_bw;
8228
8229 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8230 &min_valid, &max_valid);
8231
8232 if (!status) {
8233 if (min_valid)
8234 pf->npar_min_bw = min_bw;
8235 if (max_valid)
8236 pf->npar_max_bw = max_bw;
8237 }
8238
8239 return status;
8240}
8241
8242/**
8243 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8244 * @pf: board private structure
8245 **/
8246i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8247{
8248 struct i40e_aqc_configure_partition_bw_data bw_data;
8249 i40e_status status;
8250
b40c82e6 8251 /* Set the valid bit for this PF */
41a1d04b 8252 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8253 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8254 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8255
8256 /* Set the new bandwidths */
8257 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8258
8259 return status;
8260}
8261
8262/**
8263 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8264 * @pf: board private structure
8265 **/
8266i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8267{
8268 /* Commit temporary BW setting to permanent NVM image */
8269 enum i40e_admin_queue_err last_aq_status;
8270 i40e_status ret;
8271 u16 nvm_word;
8272
8273 if (pf->hw.partition_id != 1) {
8274 dev_info(&pf->pdev->dev,
8275 "Commit BW only works on partition 1! This is partition %d",
8276 pf->hw.partition_id);
8277 ret = I40E_NOT_SUPPORTED;
8278 goto bw_commit_out;
8279 }
8280
8281 /* Acquire NVM for read access */
8282 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8283 last_aq_status = pf->hw.aq.asq_last_status;
8284 if (ret) {
8285 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8286 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8287 i40e_stat_str(&pf->hw, ret),
8288 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8289 goto bw_commit_out;
8290 }
8291
8292 /* Read word 0x10 of NVM - SW compatibility word 1 */
8293 ret = i40e_aq_read_nvm(&pf->hw,
8294 I40E_SR_NVM_CONTROL_WORD,
8295 0x10, sizeof(nvm_word), &nvm_word,
8296 false, NULL);
8297 /* Save off last admin queue command status before releasing
8298 * the NVM
8299 */
8300 last_aq_status = pf->hw.aq.asq_last_status;
8301 i40e_release_nvm(&pf->hw);
8302 if (ret) {
f1c7e72e
SN		 8303 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8304 i40e_stat_str(&pf->hw, ret),
8305 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8306 goto bw_commit_out;
8307 }
8308
8309 /* Wait a bit for NVM release to complete */
8310 msleep(50);
8311
8312 /* Acquire NVM for write access */
8313 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8314 last_aq_status = pf->hw.aq.asq_last_status;
8315 if (ret) {
8316 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8317 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8318 i40e_stat_str(&pf->hw, ret),
8319 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8320 goto bw_commit_out;
8321 }
8322 /* Write it back out unchanged to initiate update NVM,
8323 * which will force a write of the shadow (alt) RAM to
8324 * the NVM - thus storing the bandwidth values permanently.
8325 */
8326 ret = i40e_aq_update_nvm(&pf->hw,
8327 I40E_SR_NVM_CONTROL_WORD,
8328 0x10, sizeof(nvm_word),
8329 &nvm_word, true, NULL);
8330 /* Save off last admin queue command status before releasing
8331 * the NVM
8332 */
8333 last_aq_status = pf->hw.aq.asq_last_status;
8334 i40e_release_nvm(&pf->hw);
8335 if (ret)
8336 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8337 "BW settings NOT SAVED, err %s aq_err %s\n",
8338 i40e_stat_str(&pf->hw, ret),
8339 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8340bw_commit_out:
8341
8342 return ret;
8343}
8344
41c445ff
JB		 8345/**
8346 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8347 * @pf: board private structure to initialize
8348 *
8349 * i40e_sw_init initializes the Adapter private data structure.
8350 * Fields are initialized based on PCI device information and
8351 * OS network device settings (MTU size).
8352 **/
8353static int i40e_sw_init(struct i40e_pf *pf)
8354{
8355 int err = 0;
8356 int size;
8357
8358 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8359 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 8360 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 8361 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8362 if (I40E_DEBUG_USER & debug)
8363 pf->hw.debug_mask = debug;
8364 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8365 I40E_DEFAULT_MSG_ENABLE);
8366 }
8367
8368 /* Set default capability flags */
8369 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8370 I40E_FLAG_MSI_ENABLED |
9ac77266 8371 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 8372 I40E_FLAG_MSIX_ENABLED;
8373
8374 if (iommu_present(&pci_bus_type))
8375 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8376 else
8377 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8378
ca99eb99
MW		 8379 /* Set default ITR */
8380 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8381 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8382
7134f9ce
JB		 8383 /* Depending on PF configurations, it is possible that the RSS
8384 * maximum might end up larger than the available queues
8385 */
41a1d04b 8386 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8387 pf->alloc_rss_size = 1;
5db4cb59 8388 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8389 pf->rss_size_max = min_t(int, pf->rss_size_max,
8390 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8391 if (pf->hw.func_caps.rss) {
8392 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8393 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8394 num_online_cpus());
41c445ff
JB		 8395 }
8396
2050bc65 8397 /* MFP mode enabled */
c78b953e 8398 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8399 pf->flags |= I40E_FLAG_MFP_ENABLED;
8400 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8401 if (i40e_get_npar_bw_setting(pf))
8402 dev_warn(&pf->pdev->dev,
8403 "Could not get NPAR bw settings\n");
8404 else
8405 dev_info(&pf->pdev->dev,
8406 "Min BW = %8.8x, Max BW = %8.8x\n",
8407 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8408 }
8409
cbf61325
ASJ		 8410 /* FW/NVM is not yet fixed in this regard */
8411 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8412 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8413 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8414 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8415 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8416 pf->hw.num_partitions > 1)
cbf61325 8417 dev_info(&pf->pdev->dev,
0b67584f 8418 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8419 else
8420 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8421 pf->fdir_pf_filter_count =
8422 pf->hw.func_caps.fd_filters_guaranteed;
8423 pf->hw.fdir_shared_filter_count =
8424 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8425 }
8426
8eed76fa
ASJ		 8427 if (((pf->hw.mac.type == I40E_MAC_X710) ||
8428 (pf->hw.mac.type == I40E_MAC_XL710)) &&
8429 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
8430 (pf->hw.aq.fw_maj_ver < 4)))
8431 pf->flags |= I40E_FLAG_RESTART_AUTONEG;
8432
41c445ff 8433 if (pf->hw.func_caps.vmdq) {
41c445ff 8434 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8435 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8436 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8437 }
8438
38e00438 8439#ifdef I40E_FCOE
21364bcf 8440 i40e_init_pf_fcoe(pf);
38e00438
VD		 8441
8442#endif /* I40E_FCOE */
41c445ff 8443#ifdef CONFIG_PCI_IOV
ba252f13 8444 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8445 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8446 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8447 pf->num_req_vfs = min_t(int,
8448 pf->hw.func_caps.num_vfs,
8449 I40E_MAX_VF_COUNT);
8450 }
8451#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8452 if (pf->hw.mac.type == I40E_MAC_X722) {
8453 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8454 I40E_FLAG_128_QP_RSS_CAPABLE |
8455 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8456 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8457 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024 8458 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
f8db54cc 8459 I40E_FLAG_100M_SGMII_CAPABLE |
6a899024 8460 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
d502ce01 8461 }
41c445ff
JB		 8462 pf->eeprom_version = 0xDEAD;
8463 pf->lan_veb = I40E_NO_VEB;
8464 pf->lan_vsi = I40E_NO_VSI;
8465
d1a8d275
ASJ		 8466 /* By default FW has this off for performance reasons */
8467 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8468
41c445ff
JB		 8469 /* set up queue assignment tracking */
8470 size = sizeof(struct i40e_lump_tracking)
8471 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8472 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8473 if (!pf->qp_pile) {
8474 err = -ENOMEM;
8475 goto sw_init_done;
8476 }
8477 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8478 pf->qp_pile->search_hint = 0;
8479
327fe04b
ASJ		 8480 pf->tx_timeout_recovery_level = 1;
8481
41c445ff
JB		 8482 mutex_init(&pf->switch_mutex);
8483
c668a12c
GR		 8484 /* If NPAR is enabled nudge the Tx scheduler */
8485 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8486 i40e_set_npar_bw_setting(pf);
8487
41c445ff
JB		 8488sw_init_done:
8489 return err;
8490}
8491
7c3c288b
ASJ		 8492/**
8493 * i40e_set_ntuple - set the ntuple feature flag and take action
8494 * @pf: board private structure to initialize
8495 * @features: the feature set that the stack is suggesting
8496 *
8497 * returns a bool to indicate if reset needs to happen
8498 **/
8499bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8500{
8501 bool need_reset = false;
8502
8503 /* Check if Flow Director n-tuple support was enabled or disabled. If
8504 * the state changed, we need to reset.
8505 */
8506 if (features & NETIF_F_NTUPLE) {
8507 /* Enable filters and mark for reset */
8508 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8509 need_reset = true;
8510 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8511 } else {
8512 /* turn off filters, mark for reset and clear SW filter list */
8513 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8514 need_reset = true;
8515 i40e_fdir_filter_exit(pf);
8516 }
8517 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8518 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8519 /* reset fd counters */
8520 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8521 pf->fdir_pf_active_filters = 0;
8522 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8523 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8524 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8525 /* if ATR was auto disabled it can be re-enabled. */
8526 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8527 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8528 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8529 }
8530 return need_reset;
8531}
8532
41c445ff
JB		 8533/**
8534 * i40e_set_features - set the netdev feature flags
8535 * @netdev: ptr to the netdev being adjusted
8536 * @features: the feature set that the stack is suggesting
8537 **/
8538static int i40e_set_features(struct net_device *netdev,
8539 netdev_features_t features)
8540{
8541 struct i40e_netdev_priv *np = netdev_priv(netdev);
8542 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8543 struct i40e_pf *pf = vsi->back;
8544 bool need_reset;
41c445ff
JB		 8545
8546 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8547 i40e_vlan_stripping_enable(vsi);
8548 else
8549 i40e_vlan_stripping_disable(vsi);
8550
7c3c288b
ASJ		 8551 need_reset = i40e_set_ntuple(pf, features);
8552
8553 if (need_reset)
41a1d04b 8554 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8555
41c445ff
JB		 8556 return 0;
8557}
8558
6a899024 8559#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9 8560/**
6a899024 8561 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8562 * @pf: board private structure
8563 * @port: The UDP port to look up
8564 *
8565 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8566 **/
6a899024 8567static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8568{
8569 u8 i;
8570
8571 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8572 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8573 return i;
8574 }
8575
8576 return i;
8577}
8578
6a899024 8579#endif
5cae7615
ED		 8580
8581#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8582/**
8583 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8584 * @netdev: This physical port's netdev
8585 * @sa_family: Socket Family that VXLAN is notifying us about
8586 * @port: New UDP port number that VXLAN started listening to
8587 **/
8588static void i40e_add_vxlan_port(struct net_device *netdev,
8589 sa_family_t sa_family, __be16 port)
8590{
8591 struct i40e_netdev_priv *np = netdev_priv(netdev);
8592 struct i40e_vsi *vsi = np->vsi;
8593 struct i40e_pf *pf = vsi->back;
8594 u8 next_idx;
8595 u8 idx;
8596
8597 if (sa_family == AF_INET6)
8598 return;
8599
6a899024 8600 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8601
8602 /* Check if port already exists */
8603 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8604 netdev_info(netdev, "vxlan port %d already offloaded\n",
8605 ntohs(port));
a1c9a9d9
JK		 8606 return;
8607 }
8608
8609 /* Now check if there is space to add the new port */
6a899024 8610 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8611
8612 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8613 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8614 ntohs(port));
8615 return;
8616 }
8617
8618 /* New port: add it and mark its index in the bitmap */
6a899024
SA		 8619 pf->udp_ports[next_idx].index = port;
8620 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8621 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8622 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 8623}
8624
8625/**
8626 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8627 * @netdev: This physical port's netdev
8628 * @sa_family: Socket Family that VXLAN is notifying us about
8629 * @port: UDP port number that VXLAN stopped listening to
8630 **/
8631static void i40e_del_vxlan_port(struct net_device *netdev,
8632 sa_family_t sa_family, __be16 port)
8633{
8634 struct i40e_netdev_priv *np = netdev_priv(netdev);
8635 struct i40e_vsi *vsi = np->vsi;
8636 struct i40e_pf *pf = vsi->back;
8637 u8 idx;
8638
8639 if (sa_family == AF_INET6)
8640 return;
8641
6a899024 8642 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8643
8644 /* Check if port already exists */
8645 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8646 /* if port exists, set it to 0 (mark for deletion)
8647 * and make it pending
8648 */
6a899024
SA		 8649 pf->udp_ports[idx].index = 0;
8650 pf->pending_udp_bitmap |= BIT_ULL(idx);
8651 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9 8652 } else {
c22c06c8 8653 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8654 ntohs(port));
8655 }
6a899024 8656}
5cae7615 8657#endif
6a899024 8658
5cae7615 8659#if IS_ENABLED(CONFIG_GENEVE)
6a899024
SA		 8660/**
8661 * i40e_add_geneve_port - Get notifications about GENEVE ports that come up
8662 * @netdev: This physical port's netdev
8663 * @sa_family: Socket Family that GENEVE is notifying us about
8664 * @port: New UDP port number that GENEVE started listening to
8665 **/
8666static void i40e_add_geneve_port(struct net_device *netdev,
8667 sa_family_t sa_family, __be16 port)
8668{
6a899024
SA		 8669 struct i40e_netdev_priv *np = netdev_priv(netdev);
8670 struct i40e_vsi *vsi = np->vsi;
8671 struct i40e_pf *pf = vsi->back;
8672 u8 next_idx;
8673 u8 idx;
8674
8675 if (sa_family == AF_INET6)
8676 return;
8677
8678 idx = i40e_get_udp_port_idx(pf, port);
8679
8680 /* Check if port already exists */
8681 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8682 netdev_info(netdev, "udp port %d already offloaded\n",
8683 ntohs(port));
8684 return;
8685 }
8686
8687 /* Now check if there is space to add the new port */
8688 next_idx = i40e_get_udp_port_idx(pf, 0);
8689
8690 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8691 netdev_info(netdev, "maximum number of UDP ports reached, not adding port %d\n",
8692 ntohs(port));
8693 return;
8694 }
8695
8696 /* New port: add it and mark its index in the bitmap */
8697 pf->udp_ports[next_idx].index = port;
8698 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8699 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8700 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8701
8702 dev_info(&pf->pdev->dev, "adding geneve port %d\n", ntohs(port));
a1c9a9d9
JK		 8703}
8704
6a899024
SA		 8705/**
8706 * i40e_del_geneve_port - Get notifications about GENEVE ports that go away
8707 * @netdev: This physical port's netdev
8708 * @sa_family: Socket Family that GENEVE is notifying us about
8709 * @port: UDP port number that GENEVE stopped listening to
8710 **/
8711static void i40e_del_geneve_port(struct net_device *netdev,
8712 sa_family_t sa_family, __be16 port)
8713{
6a899024
SA		 8714 struct i40e_netdev_priv *np = netdev_priv(netdev);
8715 struct i40e_vsi *vsi = np->vsi;
8716 struct i40e_pf *pf = vsi->back;
8717 u8 idx;
8718
8719 if (sa_family == AF_INET6)
8720 return;
8721
8722 idx = i40e_get_udp_port_idx(pf, port);
8723
8724 /* Check if port already exists */
8725 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8726 /* if port exists, set it to 0 (mark for deletion)
8727 * and make it pending
8728 */
8729 pf->udp_ports[idx].index = 0;
8730 pf->pending_udp_bitmap |= BIT_ULL(idx);
8731 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8732
8733 dev_info(&pf->pdev->dev, "deleting geneve port %d\n",
8734 ntohs(port));
8735 } else {
8736 netdev_warn(netdev, "geneve port %d was not found, not deleting\n",
8737 ntohs(port));
8738 }
6a899024 8739}
5cae7615 8740#endif
6a899024 8741
1f224ad2 8742static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8743 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8744{
8745 struct i40e_netdev_priv *np = netdev_priv(netdev);
8746 struct i40e_pf *pf = np->vsi->back;
8747 struct i40e_hw *hw = &pf->hw;
8748
8749 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8750 return -EOPNOTSUPP;
8751
8752 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8753 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8754
8755 return 0;
8756}
8757
2f90ade6
JB		 8758/**
8759 * i40e_ndo_fdb_add - add an entry to the hardware database
8760 * @ndm: the input from the stack
8761 * @tb: pointer to array of nladdr (unused)
8762 * @dev: the net device pointer
8763 * @addr: the MAC address entry being added
8764 * @flags: instructions from stack about fdb operation
8765 */
4ba0dea5
GR		 8766static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8767 struct net_device *dev,
f6f6424b 8768 const unsigned char *addr, u16 vid,
4ba0dea5 8769 u16 flags)
4ba0dea5
GR		 8770{
8771 struct i40e_netdev_priv *np = netdev_priv(dev);
8772 struct i40e_pf *pf = np->vsi->back;
8773 int err = 0;
8774
8775 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8776 return -EOPNOTSUPP;
8777
65891fea
OG		 8778 if (vid) {
8779 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8780 return -EINVAL;
8781 }
8782
4ba0dea5
GR		 8783 /* Hardware does not support aging addresses so if a
8784 * ndm_state is given only allow permanent addresses
8785 */
8786 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8787 netdev_info(dev, "FDB only supports static addresses\n");
8788 return -EINVAL;
8789 }
8790
8791 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8792 err = dev_uc_add_excl(dev, addr);
8793 else if (is_multicast_ether_addr(addr))
8794 err = dev_mc_add_excl(dev, addr);
8795 else
8796 err = -EINVAL;
8797
8798 /* Only return duplicate errors if NLM_F_EXCL is set */
8799 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8800 err = 0;
8801
8802 return err;
8803}
8804
51616018
NP		 8805/**
8806 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8807 * @dev: the netdev being configured
8808 * @nlh: RTNL message
8809 *
8810 * Inserts a new hardware bridge if not already created and
8811 * enables the bridging mode requested (VEB or VEPA). If the
8812 * hardware bridge has already been inserted and the request
8813 * is to change the mode then that requires a PF reset to
8814 * allow rebuild of the components with required hardware
8815 * bridge mode enabled.
8816 **/
8817static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8818 struct nlmsghdr *nlh,
8819 u16 flags)
51616018
NP		 8820{
8821 struct i40e_netdev_priv *np = netdev_priv(dev);
8822 struct i40e_vsi *vsi = np->vsi;
8823 struct i40e_pf *pf = vsi->back;
8824 struct i40e_veb *veb = NULL;
8825 struct nlattr *attr, *br_spec;
8826 int i, rem;
8827
8828 /* Only for PF VSI for now */
8829 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8830 return -EOPNOTSUPP;
8831
8832 /* Find the HW bridge for PF VSI */
8833 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8834 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8835 veb = pf->veb[i];
8836 }
8837
8838 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8839
8840 nla_for_each_nested(attr, br_spec, rem) {
8841 __u16 mode;
8842
8843 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8844 continue;
8845
8846 mode = nla_get_u16(attr);
8847 if ((mode != BRIDGE_MODE_VEPA) &&
8848 (mode != BRIDGE_MODE_VEB))
8849 return -EINVAL;
8850
8851 /* Insert a new HW bridge */
8852 if (!veb) {
8853 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8854 vsi->tc_config.enabled_tc);
8855 if (veb) {
8856 veb->bridge_mode = mode;
8857 i40e_config_bridge_mode(veb);
8858 } else {
8859 /* No Bridge HW offload available */
8860 return -ENOENT;
8861 }
8862 break;
8863 } else if (mode != veb->bridge_mode) {
8864 /* Existing HW bridge but different mode needs reset */
8865 veb->bridge_mode = mode;
fc60861e
ASJ		 8866 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8867 if (mode == BRIDGE_MODE_VEB)
8868 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8869 else
8870 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8871 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8872 break;
8873 }
8874 }
8875
8876 return 0;
8877}
8878
8879/**
8880 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8881 * @skb: skb buff
8882 * @pid: process id
8883 * @seq: RTNL message seq #
8884 * @dev: the netdev being configured
8885 * @filter_mask: unused
d4b2f9fe 8886 * @nlflags: netlink flags passed in
51616018
NP		 8887 *
8888 * Return the mode in which the hardware bridge is operating in
8889 * i.e VEB or VEPA.
8890 **/
51616018
NP		 8891static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8892 struct net_device *dev,
9f4ffc44
CW		 8893 u32 __always_unused filter_mask,
8894 int nlflags)
51616018
NP		 8895{
8896 struct i40e_netdev_priv *np = netdev_priv(dev);
8897 struct i40e_vsi *vsi = np->vsi;
8898 struct i40e_pf *pf = vsi->back;
8899 struct i40e_veb *veb = NULL;
8900 int i;
8901
8902 /* Only for PF VSI for now */
8903 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8904 return -EOPNOTSUPP;
8905
8906 /* Find the HW bridge for the PF VSI */
8907 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8908 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8909 veb = pf->veb[i];
8910 }
8911
8912 if (!veb)
8913 return 0;
8914
46c264da 8915 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8916 nlflags, 0, 0, filter_mask, NULL);
51616018 8917}
51616018 8918
6a899024
SA		 8919/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
8920 * inner mac plus all inner ethertypes.
8921 */
8922#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 8923/**
8924 * i40e_features_check - Validate encapsulated packet conforms to limits
8925 * @skb: skb buff
2bc11c63 8926 * @dev: This physical port's netdev
f44a75e2
JS		 8927 * @features: Offload features that the stack believes apply
8928 **/
8929static netdev_features_t i40e_features_check(struct sk_buff *skb,
8930 struct net_device *dev,
8931 netdev_features_t features)
8932{
8933 if (skb->encapsulation &&
6a899024 8934 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 8935 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 8936 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 8937
8938 return features;
8939}
8940
37a2973a 8941static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8942 .ndo_open = i40e_open,
8943 .ndo_stop = i40e_close,
8944 .ndo_start_xmit = i40e_lan_xmit_frame,
8945 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8946 .ndo_set_rx_mode = i40e_set_rx_mode,
8947 .ndo_validate_addr = eth_validate_addr,
8948 .ndo_set_mac_address = i40e_set_mac,
8949 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8950 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8951 .ndo_tx_timeout = i40e_tx_timeout,
8952 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8953 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8954#ifdef CONFIG_NET_POLL_CONTROLLER
8955 .ndo_poll_controller = i40e_netpoll,
8956#endif
e4c6734e 8957 .ndo_setup_tc = __i40e_setup_tc,
38e00438
VD		 8958#ifdef I40E_FCOE
8959 .ndo_fcoe_enable = i40e_fcoe_enable,
8960 .ndo_fcoe_disable = i40e_fcoe_disable,
8961#endif
41c445ff
JB		 8962 .ndo_set_features = i40e_set_features,
8963 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8964 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8965 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8966 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8967 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8968 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
6a899024 8969#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8970 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8971 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6a899024
SA		 8972#endif
8973#if IS_ENABLED(CONFIG_GENEVE)
8974 .ndo_add_geneve_port = i40e_add_geneve_port,
8975 .ndo_del_geneve_port = i40e_del_geneve_port,
a1c9a9d9 8976#endif
1f224ad2 8977 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8978 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8979 .ndo_features_check = i40e_features_check,
51616018
NP		 8980 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8981 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8982};
8983
8984/**
8985 * i40e_config_netdev - Setup the netdev flags
8986 * @vsi: the VSI being configured
8987 *
8988 * Returns 0 on success, negative value on failure
8989 **/
8990static int i40e_config_netdev(struct i40e_vsi *vsi)
8991{
1a10370a 8992 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8993 struct i40e_pf *pf = vsi->back;
8994 struct i40e_hw *hw = &pf->hw;
8995 struct i40e_netdev_priv *np;
8996 struct net_device *netdev;
8997 u8 mac_addr[ETH_ALEN];
8998 int etherdev_size;
8999
9000 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 9001 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 9002 if (!netdev)
9003 return -ENOMEM;
9004
9005 vsi->netdev = netdev;
9006 np = netdev_priv(netdev);
9007 np->vsi = vsi;
9008
5afdaaa0
JB		 9009 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
9010 NETIF_F_GSO_UDP_TUNNEL |
9011 NETIF_F_GSO_GRE |
9012 NETIF_F_TSO |
9013 0;
41c445ff
JB		 9014
9015 netdev->features = NETIF_F_SG |
9016 NETIF_F_IP_CSUM |
53692b1d 9017 NETIF_F_SCTP_CRC |
41c445ff
JB		 9018 NETIF_F_HIGHDMA |
9019 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 9020 NETIF_F_GSO_GRE |
41c445ff
JB		 9021 NETIF_F_HW_VLAN_CTAG_TX |
9022 NETIF_F_HW_VLAN_CTAG_RX |
9023 NETIF_F_HW_VLAN_CTAG_FILTER |
9024 NETIF_F_IPV6_CSUM |
9025 NETIF_F_TSO |
059dab69 9026 NETIF_F_TSO_ECN |
41c445ff
JB		 9027 NETIF_F_TSO6 |
9028 NETIF_F_RXCSUM |
9029 NETIF_F_RXHASH |
9030 0;
9031
2e86a0b6
ASJ		 9032 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
9033 netdev->features |= NETIF_F_NTUPLE;
9034
41c445ff
JB		 9035 /* copy netdev features into list of user selectable features */
9036 netdev->hw_features |= netdev->features;
9037
9038 if (vsi->type == I40E_VSI_MAIN) {
9039 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 9040 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 9041 /* The following steps are necessary to prevent reception
9042 * of tagged packets - some older NVM configurations load a
9043 * default a MAC-VLAN filter that accepts any tagged packet
9044 * which must be replaced by a normal filter.
8c27d42e 9045 */
21659035
KP		 9046 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
9047 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 9048 i40e_add_filter(vsi, mac_addr,
9049 I40E_VLAN_ANY, false, true);
21659035
KP		 9050 spin_unlock_bh(&vsi->mac_filter_list_lock);
9051 }
41c445ff
JB		 9052 } else {
9053 /* relate the VSI_VMDQ name to the VSI_MAIN name */
9054 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
9055 pf->vsi[pf->lan_vsi]->netdev->name);
9056 random_ether_addr(mac_addr);
21659035
KP		 9057
9058 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 9059 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 9060 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9061 }
21659035
KP		 9062
9063 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 9064 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 9065 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9066
9a173901
GR		 9067 ether_addr_copy(netdev->dev_addr, mac_addr);
9068 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 9069 /* vlan gets same features (except vlan offload)
9070 * after any tweaks for specific VSI types
9071 */
9072 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
9073 NETIF_F_HW_VLAN_CTAG_RX |
9074 NETIF_F_HW_VLAN_CTAG_FILTER);
9075 netdev->priv_flags |= IFF_UNICAST_FLT;
9076 netdev->priv_flags |= IFF_SUPP_NOFCS;
9077 /* Setup netdev TC information */
9078 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9079
9080 netdev->netdev_ops = &i40e_netdev_ops;
9081 netdev->watchdog_timeo = 5 * HZ;
9082 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9083#ifdef I40E_FCOE
9084 i40e_fcoe_config_netdev(netdev, vsi);
9085#endif
41c445ff
JB		 9086
9087 return 0;
9088}
9089
9090/**
9091 * i40e_vsi_delete - Delete a VSI from the switch
9092 * @vsi: the VSI being removed
9093 *
9094 * Returns 0 on success, negative value on failure
9095 **/
9096static void i40e_vsi_delete(struct i40e_vsi *vsi)
9097{
9098 /* remove default VSI is not allowed */
9099 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9100 return;
9101
41c445ff 9102 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9103}
9104
51616018
NP		 9105/**
9106 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9107 * @vsi: the VSI being queried
9108 *
9109 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9110 **/
9111int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9112{
9113 struct i40e_veb *veb;
9114 struct i40e_pf *pf = vsi->back;
9115
9116 /* Uplink is not a bridge so default to VEB */
9117 if (vsi->veb_idx == I40E_NO_VEB)
9118 return 1;
9119
9120 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9121 if (!veb) {
9122 dev_info(&pf->pdev->dev,
9123 "There is no veb associated with the bridge\n");
9124 return -ENOENT;
9125 }
9126
51616018 9127 /* Uplink is a bridge in VEPA mode */
09603eaa 9128 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9129 return 0;
09603eaa
AA		 9130 } else {
9131 /* Uplink is a bridge in VEB mode */
9132 return 1;
9133 }
51616018 9134
09603eaa
AA		 9135 /* VEPA is now default bridge, so return 0 */
9136 return 0;
51616018
NP		 9137}
9138
41c445ff
JB		 9139/**
9140 * i40e_add_vsi - Add a VSI to the switch
9141 * @vsi: the VSI being configured
9142 *
9143 * This initializes a VSI context depending on the VSI type to be added and
9144 * passes it down to the add_vsi aq command.
9145 **/
9146static int i40e_add_vsi(struct i40e_vsi *vsi)
9147{
9148 int ret = -ENODEV;
21659035
KP		 9149 u8 laa_macaddr[ETH_ALEN];
9150 bool found_laa_mac_filter = false;
41c445ff
JB		 9151 struct i40e_pf *pf = vsi->back;
9152 struct i40e_hw *hw = &pf->hw;
9153 struct i40e_vsi_context ctxt;
21659035
KP		 9154 struct i40e_mac_filter *f, *ftmp;
9155
41c445ff
JB		 9156 u8 enabled_tc = 0x1; /* TC0 enabled */
9157 int f_count = 0;
9158
9159 memset(&ctxt, 0, sizeof(ctxt));
9160 switch (vsi->type) {
9161 case I40E_VSI_MAIN:
9162 /* The PF's main VSI is already setup as part of the
9163 * device initialization, so we'll not bother with
9164 * the add_vsi call, but we will retrieve the current
9165 * VSI context.
9166 */
9167 ctxt.seid = pf->main_vsi_seid;
9168 ctxt.pf_num = pf->hw.pf_id;
9169 ctxt.vf_num = 0;
9170 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9171 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9172 if (ret) {
9173 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9174 "couldn't get PF vsi config, err %s aq_err %s\n",
9175 i40e_stat_str(&pf->hw, ret),
9176 i40e_aq_str(&pf->hw,
9177 pf->hw.aq.asq_last_status));
41c445ff
JB		 9178 return -ENOENT;
9179 }
1a2f6248 9180 vsi->info = ctxt.info;
41c445ff
JB		 9181 vsi->info.valid_sections = 0;
9182
9183 vsi->seid = ctxt.seid;
9184 vsi->id = ctxt.vsi_number;
9185
9186 enabled_tc = i40e_pf_get_tc_map(pf);
9187
9188 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9189 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9190 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9191 memset(&ctxt, 0, sizeof(ctxt));
9192 ctxt.seid = pf->main_vsi_seid;
9193 ctxt.pf_num = pf->hw.pf_id;
9194 ctxt.vf_num = 0;
9195 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9196 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9197 if (ret) {
9198 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9199 "update vsi failed, err %s aq_err %s\n",
9200 i40e_stat_str(&pf->hw, ret),
9201 i40e_aq_str(&pf->hw,
9202 pf->hw.aq.asq_last_status));
41c445ff
JB		 9203 ret = -ENOENT;
9204 goto err;
9205 }
9206 /* update the local VSI info queue map */
9207 i40e_vsi_update_queue_map(vsi, &ctxt);
9208 vsi->info.valid_sections = 0;
9209 } else {
9210 /* Default/Main VSI is only enabled for TC0
9211 * reconfigure it to enable all TCs that are
9212 * available on the port in SFP mode.
63d7e5a4
NP		 9213 * For MFP case the iSCSI PF would use this
9214 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9215 */
9216 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9217 if (ret) {
9218 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9219 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9220 enabled_tc,
9221 i40e_stat_str(&pf->hw, ret),
9222 i40e_aq_str(&pf->hw,
9223 pf->hw.aq.asq_last_status));
41c445ff
JB		 9224 ret = -ENOENT;
9225 }
9226 }
9227 break;
9228
9229 case I40E_VSI_FDIR:
cbf61325
ASJ		 9230 ctxt.pf_num = hw->pf_id;
9231 ctxt.vf_num = 0;
9232 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9233 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9234 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9235 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9236 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9237 ctxt.info.valid_sections |=
fc60861e 9238 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9239 ctxt.info.switch_id =
fc60861e 9240 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9241 }
41c445ff 9242 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9243 break;
9244
9245 case I40E_VSI_VMDQ2:
9246 ctxt.pf_num = hw->pf_id;
9247 ctxt.vf_num = 0;
9248 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9249 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9250 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9251
41c445ff
JB		 9252 /* This VSI is connected to VEB so the switch_id
9253 * should be set to zero by default.
9254 */
51616018
NP		 9255 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9256 ctxt.info.valid_sections |=
9257 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9258 ctxt.info.switch_id =
9259 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9260 }
41c445ff
JB		 9261
9262 /* Setup the VSI tx/rx queue map for TC0 only for now */
9263 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9264 break;
9265
9266 case I40E_VSI_SRIOV:
9267 ctxt.pf_num = hw->pf_id;
9268 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9269 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9270 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9271 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9272
41c445ff
JB		 9273 /* This VSI is connected to VEB so the switch_id
9274 * should be set to zero by default.
9275 */
51616018
NP		 9276 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9277 ctxt.info.valid_sections |=
9278 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9279 ctxt.info.switch_id =
9280 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9281 }
41c445ff
JB		 9282
9283 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9284 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9285 if (pf->vf[vsi->vf_id].spoofchk) {
9286 ctxt.info.valid_sections |=
9287 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9288 ctxt.info.sec_flags |=
9289 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9290 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9291 }
41c445ff
JB		 9292 /* Setup the VSI tx/rx queue map for TC0 only for now */
9293 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9294 break;
9295
38e00438
VD		 9296#ifdef I40E_FCOE
9297 case I40E_VSI_FCOE:
9298 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9299 if (ret) {
9300 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9301 return ret;
9302 }
9303 break;
9304
9305#endif /* I40E_FCOE */
41c445ff
JB		 9306 default:
9307 return -ENODEV;
9308 }
9309
9310 if (vsi->type != I40E_VSI_MAIN) {
9311 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9312 if (ret) {
9313 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9314 "add vsi failed, err %s aq_err %s\n",
9315 i40e_stat_str(&pf->hw, ret),
9316 i40e_aq_str(&pf->hw,
9317 pf->hw.aq.asq_last_status));
41c445ff
JB		 9318 ret = -ENOENT;
9319 goto err;
9320 }
1a2f6248 9321 vsi->info = ctxt.info;
41c445ff
JB		 9322 vsi->info.valid_sections = 0;
9323 vsi->seid = ctxt.seid;
9324 vsi->id = ctxt.vsi_number;
9325 }
9326
21659035 9327 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9328 /* If macvlan filters already exist, force them to get loaded */
9329 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9330 f->changed = true;
9331 f_count++;
6252c7e4 9332
21659035 9333 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9334 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9335 ether_addr_copy(laa_macaddr, f->macaddr);
9336 found_laa_mac_filter = true;
9337 }
9338 }
9339 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9340
21659035
KP		 9341 if (found_laa_mac_filter) {
9342 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9343
21659035
KP		 9344 memset(&element, 0, sizeof(element));
9345 ether_addr_copy(element.mac_addr, laa_macaddr);
9346 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9347 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9348 &element, 1, NULL);
9349 if (ret) {
9350 /* some older FW has a different default */
9351 element.flags |=
9352 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9353 i40e_aq_remove_macvlan(hw, vsi->seid,
9354 &element, 1, NULL);
6252c7e4 9355 }
21659035
KP		 9356
9357 i40e_aq_mac_address_write(hw,
9358 I40E_AQC_WRITE_TYPE_LAA_WOL,
9359 laa_macaddr, NULL);
41c445ff 9360 }
21659035 9361
41c445ff
JB		 9362 if (f_count) {
9363 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9364 pf->flags |= I40E_FLAG_FILTER_SYNC;
9365 }
9366
9367 /* Update VSI BW information */
9368 ret = i40e_vsi_get_bw_info(vsi);
9369 if (ret) {
9370 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9371 "couldn't get vsi bw info, err %s aq_err %s\n",
9372 i40e_stat_str(&pf->hw, ret),
9373 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9374 /* VSI is already added so not tearing that up */
9375 ret = 0;
9376 }
9377
9378err:
9379 return ret;
9380}
9381
9382/**
9383 * i40e_vsi_release - Delete a VSI and free its resources
9384 * @vsi: the VSI being removed
9385 *
9386 * Returns 0 on success or < 0 on error
9387 **/
9388int i40e_vsi_release(struct i40e_vsi *vsi)
9389{
9390 struct i40e_mac_filter *f, *ftmp;
9391 struct i40e_veb *veb = NULL;
9392 struct i40e_pf *pf;
9393 u16 uplink_seid;
9394 int i, n;
9395
9396 pf = vsi->back;
9397
9398 /* release of a VEB-owner or last VSI is not allowed */
9399 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9400 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9401 vsi->seid, vsi->uplink_seid);
9402 return -ENODEV;
9403 }
9404 if (vsi == pf->vsi[pf->lan_vsi] &&
9405 !test_bit(__I40E_DOWN, &pf->state)) {
9406 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9407 return -ENODEV;
9408 }
9409
9410 uplink_seid = vsi->uplink_seid;
9411 if (vsi->type != I40E_VSI_SRIOV) {
9412 if (vsi->netdev_registered) {
9413 vsi->netdev_registered = false;
9414 if (vsi->netdev) {
9415 /* results in a call to i40e_close() */
9416 unregister_netdev(vsi->netdev);
41c445ff
JB		 9417 }
9418 } else {
90ef8d47 9419 i40e_vsi_close(vsi);
41c445ff
JB		 9420 }
9421 i40e_vsi_disable_irq(vsi);
9422 }
9423
21659035 9424 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9425 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9426 i40e_del_filter(vsi, f->macaddr, f->vlan,
9427 f->is_vf, f->is_netdev);
21659035
KP		 9428 spin_unlock_bh(&vsi->mac_filter_list_lock);
9429
17652c63 9430 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9431
9432 i40e_vsi_delete(vsi);
9433 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9434 if (vsi->netdev) {
9435 free_netdev(vsi->netdev);
9436 vsi->netdev = NULL;
9437 }
41c445ff
JB		 9438 i40e_vsi_clear_rings(vsi);
9439 i40e_vsi_clear(vsi);
9440
9441 /* If this was the last thing on the VEB, except for the
9442 * controlling VSI, remove the VEB, which puts the controlling
9443 * VSI onto the next level down in the switch.
9444 *
9445 * Well, okay, there's one more exception here: don't remove
9446 * the orphan VEBs yet. We'll wait for an explicit remove request
9447 * from up the network stack.
9448 */
505682cd 9449 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9450 if (pf->vsi[i] &&
9451 pf->vsi[i]->uplink_seid == uplink_seid &&
9452 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9453 n++; /* count the VSIs */
9454 }
9455 }
9456 for (i = 0; i < I40E_MAX_VEB; i++) {
9457 if (!pf->veb[i])
9458 continue;
9459 if (pf->veb[i]->uplink_seid == uplink_seid)
9460 n++; /* count the VEBs */
9461 if (pf->veb[i]->seid == uplink_seid)
9462 veb = pf->veb[i];
9463 }
9464 if (n == 0 && veb && veb->uplink_seid != 0)
9465 i40e_veb_release(veb);
9466
9467 return 0;
9468}
9469
9470/**
9471 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9472 * @vsi: ptr to the VSI
9473 *
9474 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9475 * corresponding SW VSI structure and initializes num_queue_pairs for the
9476 * newly allocated VSI.
9477 *
9478 * Returns 0 on success or negative on failure
9479 **/
9480static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9481{
9482 int ret = -ENOENT;
9483 struct i40e_pf *pf = vsi->back;
9484
493fb300 9485 if (vsi->q_vectors[0]) {
41c445ff
JB		 9486 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9487 vsi->seid);
9488 return -EEXIST;
9489 }
9490
9491 if (vsi->base_vector) {
f29eaa3d 9492 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9493 vsi->seid, vsi->base_vector);
9494 return -EEXIST;
9495 }
9496
90e04070 9497 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9498 if (ret) {
9499 dev_info(&pf->pdev->dev,
9500 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9501 vsi->num_q_vectors, vsi->seid, ret);
9502 vsi->num_q_vectors = 0;
9503 goto vector_setup_out;
9504 }
9505
26cdc443
ASJ		 9506 /* In Legacy mode, we do not have to get any other vector since we
9507 * piggyback on the misc/ICR0 for queue interrupts.
9508 */
9509 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9510 return ret;
958a3e3b
SN		 9511 if (vsi->num_q_vectors)
9512 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9513 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9514 if (vsi->base_vector < 0) {
9515 dev_info(&pf->pdev->dev,
049a2be8
SN		 9516 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9517 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9518 i40e_vsi_free_q_vectors(vsi);
9519 ret = -ENOENT;
9520 goto vector_setup_out;
9521 }
9522
9523vector_setup_out:
9524 return ret;
9525}
9526
bc7d338f
ASJ		 9527/**
9528 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9529 * @vsi: pointer to the vsi.
9530 *
9531 * This re-allocates a vsi's queue resources.
9532 *
9533 * Returns pointer to the successfully allocated and configured VSI sw struct
9534 * on success, otherwise returns NULL on failure.
9535 **/
9536static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9537{
9538 struct i40e_pf *pf = vsi->back;
9539 u8 enabled_tc;
9540 int ret;
9541
9542 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9543 i40e_vsi_clear_rings(vsi);
9544
9545 i40e_vsi_free_arrays(vsi, false);
9546 i40e_set_num_rings_in_vsi(vsi);
9547 ret = i40e_vsi_alloc_arrays(vsi, false);
9548 if (ret)
9549 goto err_vsi;
9550
9551 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9552 if (ret < 0) {
049a2be8 9553 dev_info(&pf->pdev->dev,
f1c7e72e 9554 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9555 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9556 goto err_vsi;
9557 }
9558 vsi->base_queue = ret;
9559
9560 /* Update the FW view of the VSI. Force a reset of TC and queue
9561 * layout configurations.
9562 */
9563 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9564 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9565 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9566 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9567
9568 /* assign it some queues */
9569 ret = i40e_alloc_rings(vsi);
9570 if (ret)
9571 goto err_rings;
9572
9573 /* map all of the rings to the q_vectors */
9574 i40e_vsi_map_rings_to_vectors(vsi);
9575 return vsi;
9576
9577err_rings:
9578 i40e_vsi_free_q_vectors(vsi);
9579 if (vsi->netdev_registered) {
9580 vsi->netdev_registered = false;
9581 unregister_netdev(vsi->netdev);
9582 free_netdev(vsi->netdev);
9583 vsi->netdev = NULL;
9584 }
9585 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9586err_vsi:
9587 i40e_vsi_clear(vsi);
9588 return NULL;
9589}
9590
b499ffb0
SV		 9591/**
9592 * i40e_macaddr_init - explicitly write the mac address filters.
9593 *
9594 * @vsi: pointer to the vsi.
9595 * @macaddr: the MAC address
9596 *
9597 * This is needed when the macaddr has been obtained by other
9598 * means than the default, e.g., from Open Firmware or IDPROM.
9599 * Returns 0 on success, negative on failure
9600 **/
9601static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr)
9602{
9603 int ret;
9604 struct i40e_aqc_add_macvlan_element_data element;
9605
9606 ret = i40e_aq_mac_address_write(&vsi->back->hw,
9607 I40E_AQC_WRITE_TYPE_LAA_WOL,
9608 macaddr, NULL);
9609 if (ret) {
9610 dev_info(&vsi->back->pdev->dev,
9611 "Addr change for VSI failed: %d\n", ret);
9612 return -EADDRNOTAVAIL;
9613 }
9614
9615 memset(&element, 0, sizeof(element));
9616 ether_addr_copy(element.mac_addr, macaddr);
9617 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
9618 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL);
9619 if (ret) {
9620 dev_info(&vsi->back->pdev->dev,
9621 "add filter failed err %s aq_err %s\n",
9622 i40e_stat_str(&vsi->back->hw, ret),
9623 i40e_aq_str(&vsi->back->hw,
9624 vsi->back->hw.aq.asq_last_status));
9625 }
9626 return ret;
9627}
9628
41c445ff
JB		 9629/**
9630 * i40e_vsi_setup - Set up a VSI by a given type
9631 * @pf: board private structure
9632 * @type: VSI type
9633 * @uplink_seid: the switch element to link to
9634 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9635 *
9636 * This allocates the sw VSI structure and its queue resources, then add a VSI
9637 * to the identified VEB.
9638 *
9639 * Returns pointer to the successfully allocated and configure VSI sw struct on
9640 * success, otherwise returns NULL on failure.
9641 **/
9642struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9643 u16 uplink_seid, u32 param1)
9644{
9645 struct i40e_vsi *vsi = NULL;
9646 struct i40e_veb *veb = NULL;
9647 int ret, i;
9648 int v_idx;
9649
9650 /* The requested uplink_seid must be either
9651 * - the PF's port seid
9652 * no VEB is needed because this is the PF
9653 * or this is a Flow Director special case VSI
9654 * - seid of an existing VEB
9655 * - seid of a VSI that owns an existing VEB
9656 * - seid of a VSI that doesn't own a VEB
9657 * a new VEB is created and the VSI becomes the owner
9658 * - seid of the PF VSI, which is what creates the first VEB
9659 * this is a special case of the previous
9660 *
9661 * Find which uplink_seid we were given and create a new VEB if needed
9662 */
9663 for (i = 0; i < I40E_MAX_VEB; i++) {
9664 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9665 veb = pf->veb[i];
9666 break;
9667 }
9668 }
9669
9670 if (!veb && uplink_seid != pf->mac_seid) {
9671
505682cd 9672 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9673 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9674 vsi = pf->vsi[i];
9675 break;
9676 }
9677 }
9678 if (!vsi) {
9679 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9680 uplink_seid);
9681 return NULL;
9682 }
9683
9684 if (vsi->uplink_seid == pf->mac_seid)
9685 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9686 vsi->tc_config.enabled_tc);
9687 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9688 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9689 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9690 if (veb) {
9691 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9692 dev_info(&vsi->back->pdev->dev,
fb43201f 9693 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9694 return NULL;
9695 }
fa11cb3d
ASJ		 9696 /* We come up by default in VEPA mode if SRIOV is not
9697 * already enabled, in which case we can't force VEPA
9698 * mode.
9699 */
9700 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9701 veb->bridge_mode = BRIDGE_MODE_VEPA;
9702 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9703 }
51616018 9704 i40e_config_bridge_mode(veb);
79c21a82 9705 }
41c445ff
JB		 9706 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9707 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9708 veb = pf->veb[i];
9709 }
9710 if (!veb) {
9711 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9712 return NULL;
9713 }
9714
9715 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9716 uplink_seid = veb->seid;
9717 }
9718
9719 /* get vsi sw struct */
9720 v_idx = i40e_vsi_mem_alloc(pf, type);
9721 if (v_idx < 0)
9722 goto err_alloc;
9723 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9724 if (!vsi)
9725 goto err_alloc;
41c445ff
JB		 9726 vsi->type = type;
9727 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9728
9729 if (type == I40E_VSI_MAIN)
9730 pf->lan_vsi = v_idx;
9731 else if (type == I40E_VSI_SRIOV)
9732 vsi->vf_id = param1;
9733 /* assign it some queues */
cbf61325
ASJ		 9734 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9735 vsi->idx);
41c445ff 9736 if (ret < 0) {
049a2be8
SN		 9737 dev_info(&pf->pdev->dev,
9738 "failed to get tracking for %d queues for VSI %d err=%d\n",
9739 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9740 goto err_vsi;
9741 }
9742 vsi->base_queue = ret;
9743
9744 /* get a VSI from the hardware */
9745 vsi->uplink_seid = uplink_seid;
9746 ret = i40e_add_vsi(vsi);
9747 if (ret)
9748 goto err_vsi;
9749
9750 switch (vsi->type) {
9751 /* setup the netdev if needed */
9752 case I40E_VSI_MAIN:
b499ffb0
SV		 9753 /* Apply relevant filters if a platform-specific mac
9754 * address was selected.
9755 */
9756 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
9757 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr);
9758 if (ret) {
9759 dev_warn(&pf->pdev->dev,
9760 "could not set up macaddr; err %d\n",
9761 ret);
9762 }
9763 }
41c445ff 9764 case I40E_VSI_VMDQ2:
38e00438 9765 case I40E_VSI_FCOE:
41c445ff
JB		 9766 ret = i40e_config_netdev(vsi);
9767 if (ret)
9768 goto err_netdev;
9769 ret = register_netdev(vsi->netdev);
9770 if (ret)
9771 goto err_netdev;
9772 vsi->netdev_registered = true;
9773 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9774#ifdef CONFIG_I40E_DCB
9775 /* Setup DCB netlink interface */
9776 i40e_dcbnl_setup(vsi);
9777#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9778 /* fall through */
9779
9780 case I40E_VSI_FDIR:
9781 /* set up vectors and rings if needed */
9782 ret = i40e_vsi_setup_vectors(vsi);
9783 if (ret)
9784 goto err_msix;
9785
9786 ret = i40e_alloc_rings(vsi);
9787 if (ret)
9788 goto err_rings;
9789
9790 /* map all of the rings to the q_vectors */
9791 i40e_vsi_map_rings_to_vectors(vsi);
9792
9793 i40e_vsi_reset_stats(vsi);
9794 break;
9795
9796 default:
9797 /* no netdev or rings for the other VSI types */
9798 break;
9799 }
9800
e25d00b8
ASJ		 9801 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9802 (vsi->type == I40E_VSI_VMDQ2)) {
9803 ret = i40e_vsi_config_rss(vsi);
9804 }
41c445ff
JB		 9805 return vsi;
9806
9807err_rings:
9808 i40e_vsi_free_q_vectors(vsi);
9809err_msix:
9810 if (vsi->netdev_registered) {
9811 vsi->netdev_registered = false;
9812 unregister_netdev(vsi->netdev);
9813 free_netdev(vsi->netdev);
9814 vsi->netdev = NULL;
9815 }
9816err_netdev:
9817 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9818err_vsi:
9819 i40e_vsi_clear(vsi);
9820err_alloc:
9821 return NULL;
9822}
9823
9824/**
9825 * i40e_veb_get_bw_info - Query VEB BW information
9826 * @veb: the veb to query
9827 *
9828 * Query the Tx scheduler BW configuration data for given VEB
9829 **/
9830static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9831{
9832 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9833 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9834 struct i40e_pf *pf = veb->pf;
9835 struct i40e_hw *hw = &pf->hw;
9836 u32 tc_bw_max;
9837 int ret = 0;
9838 int i;
9839
9840 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9841 &bw_data, NULL);
9842 if (ret) {
9843 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9844 "query veb bw config failed, err %s aq_err %s\n",
9845 i40e_stat_str(&pf->hw, ret),
9846 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9847 goto out;
9848 }
9849
9850 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9851 &ets_data, NULL);
9852 if (ret) {
9853 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9854 "query veb bw ets config failed, err %s aq_err %s\n",
9855 i40e_stat_str(&pf->hw, ret),
9856 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9857 goto out;
9858 }
9859
9860 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9861 veb->bw_max_quanta = ets_data.tc_bw_max;
9862 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9863 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9864 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9865 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9866 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9867 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9868 veb->bw_tc_limit_credits[i] =
9869 le16_to_cpu(bw_data.tc_bw_limits[i]);
9870 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9871 }
9872
9873out:
9874 return ret;
9875}
9876
9877/**
9878 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9879 * @pf: board private structure
9880 *
9881 * On error: returns error code (negative)
9882 * On success: returns vsi index in PF (positive)
9883 **/
9884static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9885{
9886 int ret = -ENOENT;
9887 struct i40e_veb *veb;
9888 int i;
9889
9890 /* Need to protect the allocation of switch elements at the PF level */
9891 mutex_lock(&pf->switch_mutex);
9892
9893 /* VEB list may be fragmented if VEB creation/destruction has
9894 * been happening. We can afford to do a quick scan to look
9895 * for any free slots in the list.
9896 *
9897 * find next empty veb slot, looping back around if necessary
9898 */
9899 i = 0;
9900 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9901 i++;
9902 if (i >= I40E_MAX_VEB) {
9903 ret = -ENOMEM;
9904 goto err_alloc_veb; /* out of VEB slots! */
9905 }
9906
9907 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9908 if (!veb) {
9909 ret = -ENOMEM;
9910 goto err_alloc_veb;
9911 }
9912 veb->pf = pf;
9913 veb->idx = i;
9914 veb->enabled_tc = 1;
9915
9916 pf->veb[i] = veb;
9917 ret = i;
9918err_alloc_veb:
9919 mutex_unlock(&pf->switch_mutex);
9920 return ret;
9921}
9922
9923/**
9924 * i40e_switch_branch_release - Delete a branch of the switch tree
9925 * @branch: where to start deleting
9926 *
9927 * This uses recursion to find the tips of the branch to be
9928 * removed, deleting until we get back to and can delete this VEB.
9929 **/
9930static void i40e_switch_branch_release(struct i40e_veb *branch)
9931{
9932 struct i40e_pf *pf = branch->pf;
9933 u16 branch_seid = branch->seid;
9934 u16 veb_idx = branch->idx;
9935 int i;
9936
9937 /* release any VEBs on this VEB - RECURSION */
9938 for (i = 0; i < I40E_MAX_VEB; i++) {
9939 if (!pf->veb[i])
9940 continue;
9941 if (pf->veb[i]->uplink_seid == branch->seid)
9942 i40e_switch_branch_release(pf->veb[i]);
9943 }
9944
9945 /* Release the VSIs on this VEB, but not the owner VSI.
9946 *
9947 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9948 * the VEB itself, so don't use (*branch) after this loop.
9949 */
505682cd 9950 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9951 if (!pf->vsi[i])
9952 continue;
9953 if (pf->vsi[i]->uplink_seid == branch_seid &&
9954 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9955 i40e_vsi_release(pf->vsi[i]);
9956 }
9957 }
9958
9959 /* There's one corner case where the VEB might not have been
9960 * removed, so double check it here and remove it if needed.
9961 * This case happens if the veb was created from the debugfs
9962 * commands and no VSIs were added to it.
9963 */
9964 if (pf->veb[veb_idx])
9965 i40e_veb_release(pf->veb[veb_idx]);
9966}
9967
9968/**
9969 * i40e_veb_clear - remove veb struct
9970 * @veb: the veb to remove
9971 **/
9972static void i40e_veb_clear(struct i40e_veb *veb)
9973{
9974 if (!veb)
9975 return;
9976
9977 if (veb->pf) {
9978 struct i40e_pf *pf = veb->pf;
9979
9980 mutex_lock(&pf->switch_mutex);
9981 if (pf->veb[veb->idx] == veb)
9982 pf->veb[veb->idx] = NULL;
9983 mutex_unlock(&pf->switch_mutex);
9984 }
9985
9986 kfree(veb);
9987}
9988
9989/**
9990 * i40e_veb_release - Delete a VEB and free its resources
9991 * @veb: the VEB being removed
9992 **/
9993void i40e_veb_release(struct i40e_veb *veb)
9994{
9995 struct i40e_vsi *vsi = NULL;
9996 struct i40e_pf *pf;
9997 int i, n = 0;
9998
9999 pf = veb->pf;
10000
10001 /* find the remaining VSI and check for extras */
505682cd 10002 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10003 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
10004 n++;
10005 vsi = pf->vsi[i];
10006 }
10007 }
10008 if (n != 1) {
10009 dev_info(&pf->pdev->dev,
10010 "can't remove VEB %d with %d VSIs left\n",
10011 veb->seid, n);
10012 return;
10013 }
10014
10015 /* move the remaining VSI to uplink veb */
10016 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
10017 if (veb->uplink_seid) {
10018 vsi->uplink_seid = veb->uplink_seid;
10019 if (veb->uplink_seid == pf->mac_seid)
10020 vsi->veb_idx = I40E_NO_VEB;
10021 else
10022 vsi->veb_idx = veb->veb_idx;
10023 } else {
10024 /* floating VEB */
10025 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10026 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
10027 }
10028
10029 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
10030 i40e_veb_clear(veb);
41c445ff
JB		 10031}
10032
10033/**
10034 * i40e_add_veb - create the VEB in the switch
10035 * @veb: the VEB to be instantiated
10036 * @vsi: the controlling VSI
10037 **/
10038static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
10039{
f1c7e72e 10040 struct i40e_pf *pf = veb->pf;
92faef85 10041 bool is_default = veb->pf->cur_promisc;
e1c51b95 10042 bool is_cloud = false;
41c445ff
JB		 10043 int ret;
10044
10045 /* get a VEB from the hardware */
f1c7e72e 10046 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 10047 veb->enabled_tc, is_default,
10048 is_cloud, &veb->seid, NULL);
41c445ff 10049 if (ret) {
f1c7e72e
SN		 10050 dev_info(&pf->pdev->dev,
10051 "couldn't add VEB, err %s aq_err %s\n",
10052 i40e_stat_str(&pf->hw, ret),
10053 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10054 return -EPERM;
10055 }
10056
10057 /* get statistics counter */
f1c7e72e 10058 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 10059 &veb->stats_idx, NULL, NULL, NULL);
10060 if (ret) {
f1c7e72e
SN		 10061 dev_info(&pf->pdev->dev,
10062 "couldn't get VEB statistics idx, err %s aq_err %s\n",
10063 i40e_stat_str(&pf->hw, ret),
10064 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10065 return -EPERM;
10066 }
10067 ret = i40e_veb_get_bw_info(veb);
10068 if (ret) {
f1c7e72e
SN		 10069 dev_info(&pf->pdev->dev,
10070 "couldn't get VEB bw info, err %s aq_err %s\n",
10071 i40e_stat_str(&pf->hw, ret),
10072 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10073 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 10074 return -ENOENT;
10075 }
10076
10077 vsi->uplink_seid = veb->seid;
10078 vsi->veb_idx = veb->idx;
10079 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
10080
10081 return 0;
10082}
10083
10084/**
10085 * i40e_veb_setup - Set up a VEB
10086 * @pf: board private structure
10087 * @flags: VEB setup flags
10088 * @uplink_seid: the switch element to link to
10089 * @vsi_seid: the initial VSI seid
10090 * @enabled_tc: Enabled TC bit-map
10091 *
10092 * This allocates the sw VEB structure and links it into the switch
10093 * It is possible and legal for this to be a duplicate of an already
10094 * existing VEB. It is also possible for both uplink and vsi seids
10095 * to be zero, in order to create a floating VEB.
10096 *
10097 * Returns pointer to the successfully allocated VEB sw struct on
10098 * success, otherwise returns NULL on failure.
10099 **/
10100struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
10101 u16 uplink_seid, u16 vsi_seid,
10102 u8 enabled_tc)
10103{
10104 struct i40e_veb *veb, *uplink_veb = NULL;
10105 int vsi_idx, veb_idx;
10106 int ret;
10107
10108 /* if one seid is 0, the other must be 0 to create a floating relay */
10109 if ((uplink_seid == 0 || vsi_seid == 0) &&
10110 (uplink_seid + vsi_seid != 0)) {
10111 dev_info(&pf->pdev->dev,
10112 "one, not both seid's are 0: uplink=%d vsi=%d\n",
10113 uplink_seid, vsi_seid);
10114 return NULL;
10115 }
10116
10117 /* make sure there is such a vsi and uplink */
505682cd 10118 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10119 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10120 break;
505682cd 10121 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10122 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10123 vsi_seid);
10124 return NULL;
10125 }
10126
10127 if (uplink_seid && uplink_seid != pf->mac_seid) {
10128 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10129 if (pf->veb[veb_idx] &&
10130 pf->veb[veb_idx]->seid == uplink_seid) {
10131 uplink_veb = pf->veb[veb_idx];
10132 break;
10133 }
10134 }
10135 if (!uplink_veb) {
10136 dev_info(&pf->pdev->dev,
10137 "uplink seid %d not found\n", uplink_seid);
10138 return NULL;
10139 }
10140 }
10141
10142 /* get veb sw struct */
10143 veb_idx = i40e_veb_mem_alloc(pf);
10144 if (veb_idx < 0)
10145 goto err_alloc;
10146 veb = pf->veb[veb_idx];
10147 veb->flags = flags;
10148 veb->uplink_seid = uplink_seid;
10149 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10150 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10151
10152 /* create the VEB in the switch */
10153 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10154 if (ret)
10155 goto err_veb;
1bb8b935
SN		 10156 if (vsi_idx == pf->lan_vsi)
10157 pf->lan_veb = veb->idx;
41c445ff
JB		 10158
10159 return veb;
10160
10161err_veb:
10162 i40e_veb_clear(veb);
10163err_alloc:
10164 return NULL;
10165}
10166
10167/**
b40c82e6 10168 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10169 * @pf: board private structure
10170 * @ele: element we are building info from
10171 * @num_reported: total number of elements
10172 * @printconfig: should we print the contents
10173 *
10174 * helper function to assist in extracting a few useful SEID values.
10175 **/
10176static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10177 struct i40e_aqc_switch_config_element_resp *ele,
10178 u16 num_reported, bool printconfig)
10179{
10180 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10181 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10182 u8 element_type = ele->element_type;
10183 u16 seid = le16_to_cpu(ele->seid);
10184
10185 if (printconfig)
10186 dev_info(&pf->pdev->dev,
10187 "type=%d seid=%d uplink=%d downlink=%d\n",
10188 element_type, seid, uplink_seid, downlink_seid);
10189
10190 switch (element_type) {
10191 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10192 pf->mac_seid = seid;
10193 break;
10194 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10195 /* Main VEB? */
10196 if (uplink_seid != pf->mac_seid)
10197 break;
10198 if (pf->lan_veb == I40E_NO_VEB) {
10199 int v;
10200
10201 /* find existing or else empty VEB */
10202 for (v = 0; v < I40E_MAX_VEB; v++) {
10203 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10204 pf->lan_veb = v;
10205 break;
10206 }
10207 }
10208 if (pf->lan_veb == I40E_NO_VEB) {
10209 v = i40e_veb_mem_alloc(pf);
10210 if (v < 0)
10211 break;
10212 pf->lan_veb = v;
10213 }
10214 }
10215
10216 pf->veb[pf->lan_veb]->seid = seid;
10217 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10218 pf->veb[pf->lan_veb]->pf = pf;
10219 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10220 break;
10221 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10222 if (num_reported != 1)
10223 break;
10224 /* This is immediately after a reset so we can assume this is
10225 * the PF's VSI
10226 */
10227 pf->mac_seid = uplink_seid;
10228 pf->pf_seid = downlink_seid;
10229 pf->main_vsi_seid = seid;
10230 if (printconfig)
10231 dev_info(&pf->pdev->dev,
10232 "pf_seid=%d main_vsi_seid=%d\n",
10233 pf->pf_seid, pf->main_vsi_seid);
10234 break;
10235 case I40E_SWITCH_ELEMENT_TYPE_PF:
10236 case I40E_SWITCH_ELEMENT_TYPE_VF:
10237 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10238 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10239 case I40E_SWITCH_ELEMENT_TYPE_PE:
10240 case I40E_SWITCH_ELEMENT_TYPE_PA:
10241 /* ignore these for now */
10242 break;
10243 default:
10244 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10245 element_type, seid);
10246 break;
10247 }
10248}
10249
10250/**
10251 * i40e_fetch_switch_configuration - Get switch config from firmware
10252 * @pf: board private structure
10253 * @printconfig: should we print the contents
10254 *
10255 * Get the current switch configuration from the device and
10256 * extract a few useful SEID values.
10257 **/
10258int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10259{
10260 struct i40e_aqc_get_switch_config_resp *sw_config;
10261 u16 next_seid = 0;
10262 int ret = 0;
10263 u8 *aq_buf;
10264 int i;
10265
10266 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10267 if (!aq_buf)
10268 return -ENOMEM;
10269
10270 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10271 do {
10272 u16 num_reported, num_total;
10273
10274 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10275 I40E_AQ_LARGE_BUF,
10276 &next_seid, NULL);
10277 if (ret) {
10278 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10279 "get switch config failed err %s aq_err %s\n",
10280 i40e_stat_str(&pf->hw, ret),
10281 i40e_aq_str(&pf->hw,
10282 pf->hw.aq.asq_last_status));
41c445ff
JB		 10283 kfree(aq_buf);
10284 return -ENOENT;
10285 }
10286
10287 num_reported = le16_to_cpu(sw_config->header.num_reported);
10288 num_total = le16_to_cpu(sw_config->header.num_total);
10289
10290 if (printconfig)
10291 dev_info(&pf->pdev->dev,
10292 "header: %d reported %d total\n",
10293 num_reported, num_total);
10294
41c445ff
JB		 10295 for (i = 0; i < num_reported; i++) {
10296 struct i40e_aqc_switch_config_element_resp *ele =
10297 &sw_config->element[i];
10298
10299 i40e_setup_pf_switch_element(pf, ele, num_reported,
10300 printconfig);
10301 }
10302 } while (next_seid != 0);
10303
10304 kfree(aq_buf);
10305 return ret;
10306}
10307
10308/**
10309 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10310 * @pf: board private structure
bc7d338f 10311 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10312 *
10313 * Returns 0 on success, negative value on failure
10314 **/
bc7d338f 10315static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10316{
10317 int ret;
10318
10319 /* find out what's out there already */
10320 ret = i40e_fetch_switch_configuration(pf, false);
10321 if (ret) {
10322 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10323 "couldn't fetch switch config, err %s aq_err %s\n",
10324 i40e_stat_str(&pf->hw, ret),
10325 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10326 return ret;
10327 }
10328 i40e_pf_reset_stats(pf);
10329
41c445ff 10330 /* first time setup */
bc7d338f 10331 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10332 struct i40e_vsi *vsi = NULL;
10333 u16 uplink_seid;
10334
10335 /* Set up the PF VSI associated with the PF's main VSI
10336 * that is already in the HW switch
10337 */
10338 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10339 uplink_seid = pf->veb[pf->lan_veb]->seid;
10340 else
10341 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10342 if (pf->lan_vsi == I40E_NO_VSI)
10343 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10344 else if (reinit)
10345 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10346 if (!vsi) {
10347 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10348 i40e_fdir_teardown(pf);
10349 return -EAGAIN;
10350 }
41c445ff
JB		 10351 } else {
10352 /* force a reset of TC and queue layout configurations */
10353 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10354
41c445ff
JB		 10355 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10356 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10357 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10358 }
10359 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10360
cbf61325
ASJ		 10361 i40e_fdir_sb_setup(pf);
10362
41c445ff
JB		 10363 /* Setup static PF queue filter control settings */
10364 ret = i40e_setup_pf_filter_control(pf);
10365 if (ret) {
10366 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10367 ret);
10368 /* Failure here should not stop continuing other steps */
10369 }
10370
10371 /* enable RSS in the HW, even for only one queue, as the stack can use
10372 * the hash
10373 */
10374 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10375 i40e_pf_config_rss(pf);
41c445ff
JB		 10376
10377 /* fill in link information and enable LSE reporting */
0a862b43 10378 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10379 i40e_link_event(pf);
10380
d52c20b7 10381 /* Initialize user-specific link properties */
41c445ff
JB		 10382 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10383 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10384
beb0dff1
JK		 10385 i40e_ptp_init(pf);
10386
41c445ff
JB		 10387 return ret;
10388}
10389
41c445ff
JB		 10390/**
10391 * i40e_determine_queue_usage - Work out queue distribution
10392 * @pf: board private structure
10393 **/
10394static void i40e_determine_queue_usage(struct i40e_pf *pf)
10395{
41c445ff
JB		 10396 int queues_left;
10397
10398 pf->num_lan_qps = 0;
38e00438
VD		 10399#ifdef I40E_FCOE
10400 pf->num_fcoe_qps = 0;
10401#endif
41c445ff
JB		 10402
10403 /* Find the max queues to be put into basic use. We'll always be
10404 * using TC0, whether or not DCB is running, and TC0 will get the
10405 * big RSS set.
10406 */
10407 queues_left = pf->hw.func_caps.num_tx_qp;
10408
cbf61325 10409 if ((queues_left == 1) ||
9aa7e935 10410 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10411 /* one qp for PF, no queues for anything else */
10412 queues_left = 0;
acd65448 10413 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10414
10415 /* make sure all the fancies are disabled */
60ea5f83 10416 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10417#ifdef I40E_FCOE
10418 I40E_FLAG_FCOE_ENABLED |
10419#endif
60ea5f83
JB		 10420 I40E_FLAG_FD_SB_ENABLED |
10421 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10422 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10423 I40E_FLAG_SRIOV_ENABLED |
10424 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10425 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10426 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10427 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10428 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10429 /* one qp for PF */
acd65448 10430 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10431 queues_left -= pf->num_lan_qps;
10432
10433 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10434#ifdef I40E_FCOE
10435 I40E_FLAG_FCOE_ENABLED |
10436#endif
9aa7e935
FZ		 10437 I40E_FLAG_FD_SB_ENABLED |
10438 I40E_FLAG_FD_ATR_ENABLED |
10439 I40E_FLAG_DCB_ENABLED |
10440 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10441 } else {
cbf61325 10442 /* Not enough queues for all TCs */
4d9b6043 10443 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10444 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10445 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10446 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10447 }
9a3bd2f1
ASJ		 10448 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10449 num_online_cpus());
10450 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10451 pf->hw.func_caps.num_tx_qp);
10452
cbf61325
ASJ		 10453 queues_left -= pf->num_lan_qps;
10454 }
10455
38e00438
VD		 10456#ifdef I40E_FCOE
10457 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10458 if (I40E_DEFAULT_FCOE <= queues_left) {
10459 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10460 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10461 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10462 } else {
10463 pf->num_fcoe_qps = 0;
10464 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10465 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10466 }
10467
10468 queues_left -= pf->num_fcoe_qps;
10469 }
10470
10471#endif
cbf61325
ASJ		 10472 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10473 if (queues_left > 1) {
10474 queues_left -= 1; /* save 1 queue for FD */
10475 } else {
10476 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10477 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10478 }
41c445ff
JB		 10479 }
10480
10481 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10482 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10483 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10484 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10485 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10486 }
10487
10488 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10489 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10490 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10491 (queues_left / pf->num_vmdq_qps));
10492 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10493 }
10494
f8ff1464 10495 pf->queues_left = queues_left;
8279e495
NP		 10496 dev_dbg(&pf->pdev->dev,
10497 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10498 pf->hw.func_caps.num_tx_qp,
10499 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10500 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10501 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10502 queues_left);
38e00438 10503#ifdef I40E_FCOE
8279e495 10504 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10505#endif
41c445ff
JB		 10506}
10507
10508/**
10509 * i40e_setup_pf_filter_control - Setup PF static filter control
10510 * @pf: PF to be setup
10511 *
b40c82e6 10512 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10513 * settings. If PE/FCoE are enabled then it will also set the per PF
10514 * based filter sizes required for them. It also enables Flow director,
10515 * ethertype and macvlan type filter settings for the pf.
10516 *
10517 * Returns 0 on success, negative on failure
10518 **/
10519static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10520{
10521 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10522
10523 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10524
10525 /* Flow Director is enabled */
60ea5f83 10526 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10527 settings->enable_fdir = true;
10528
10529 /* Ethtype and MACVLAN filters enabled for PF */
10530 settings->enable_ethtype = true;
10531 settings->enable_macvlan = true;
10532
10533 if (i40e_set_filter_control(&pf->hw, settings))
10534 return -ENOENT;
10535
10536 return 0;
10537}
10538
0c22b3dd 10539#define INFO_STRING_LEN 255
7fd89545 10540#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10541static void i40e_print_features(struct i40e_pf *pf)
10542{
10543 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10544 char *buf;
10545 int i;
0c22b3dd 10546
3b195843
JP		 10547 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10548 if (!buf)
0c22b3dd 10549 return;
0c22b3dd 10550
3b195843 10551 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10552#ifdef CONFIG_PCI_IOV
3b195843 10553 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10554#endif
3b195843 10555 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d RX: %s",
7fd89545
SN		 10556 pf->hw.func_caps.num_vsis,
10557 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10558 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10559
10560 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10561 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10562 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10563 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10564 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10565 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10566 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10567 }
4d9b6043 10568 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10569 i += snprintf(&buf[i], REMAIN(i), " DCB");
ce6fcb3f 10570#if IS_ENABLED(CONFIG_VXLAN)
3b195843 10571 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024
SA		 10572#endif
10573#if IS_ENABLED(CONFIG_GENEVE)
10574 i += snprintf(&buf[i], REMAIN(i), " Geneve");
ce6fcb3f 10575#endif
0c22b3dd 10576 if (pf->flags & I40E_FLAG_PTP)
3b195843 10577 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10578#ifdef I40E_FCOE
10579 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10580 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10581#endif
6dec1017 10582 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10583 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10584 else
3b195843 10585 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10586
3b195843
JP		 10587 dev_info(&pf->pdev->dev, "%s\n", buf);
10588 kfree(buf);
7fd89545 10589 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10590}
10591
b499ffb0
SV		 10592/**
10593 * i40e_get_platform_mac_addr - get platform-specific MAC address
10594 *
10595 * @pdev: PCI device information struct
10596 * @pf: board private structure
10597 *
10598 * Look up the MAC address in Open Firmware on systems that support it,
10599 * and use IDPROM on SPARC if no OF address is found. On return, the
10600 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value
10601 * has been selected.
10602 **/
10603static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
10604{
10605 struct device_node *dp = pci_device_to_OF_node(pdev);
10606 const unsigned char *addr;
10607 u8 *mac_addr = pf->hw.mac.addr;
10608
10609 pf->flags &= ~I40E_FLAG_PF_MAC;
10610 addr = of_get_mac_address(dp);
10611 if (addr) {
10612 ether_addr_copy(mac_addr, addr);
10613 pf->flags |= I40E_FLAG_PF_MAC;
10614#ifdef CONFIG_SPARC
10615 } else {
10616 ether_addr_copy(mac_addr, idprom->id_ethaddr);
10617 pf->flags |= I40E_FLAG_PF_MAC;
10618#endif /* CONFIG_SPARC */
10619 }
10620}
10621
41c445ff
JB		 10622/**
10623 * i40e_probe - Device initialization routine
10624 * @pdev: PCI device information struct
10625 * @ent: entry in i40e_pci_tbl
10626 *
b40c82e6
JK		 10627 * i40e_probe initializes a PF identified by a pci_dev structure.
10628 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10629 * and a hardware reset occur.
10630 *
10631 * Returns 0 on success, negative on failure
10632 **/
10633static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10634{
e827845c 10635 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10636 struct i40e_pf *pf;
10637 struct i40e_hw *hw;
93cd765b 10638 static u16 pfs_found;
1d5109d1 10639 u16 wol_nvm_bits;
d4dfb81a 10640 u16 link_status;
6f66a484 10641 int err;
4f2f017c 10642 u32 val;
8a9eb7d3 10643 u32 i;
58fc3267 10644 u8 set_fc_aq_fail;
41c445ff
JB		 10645
10646 err = pci_enable_device_mem(pdev);
10647 if (err)
10648 return err;
10649
10650 /* set up for high or low dma */
6494294f 10651 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10652 if (err) {
e3e3bfdd
JS		 10653 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10654 if (err) {
10655 dev_err(&pdev->dev,
10656 "DMA configuration failed: 0x%x\n", err);
10657 goto err_dma;
10658 }
41c445ff
JB		 10659 }
10660
10661 /* set up pci connections */
10662 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10663 IORESOURCE_MEM), i40e_driver_name);
10664 if (err) {
10665 dev_info(&pdev->dev,
10666 "pci_request_selected_regions failed %d\n", err);
10667 goto err_pci_reg;
10668 }
10669
10670 pci_enable_pcie_error_reporting(pdev);
10671 pci_set_master(pdev);
10672
10673 /* Now that we have a PCI connection, we need to do the
10674 * low level device setup. This is primarily setting up
10675 * the Admin Queue structures and then querying for the
10676 * device's current profile information.
10677 */
10678 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10679 if (!pf) {
10680 err = -ENOMEM;
10681 goto err_pf_alloc;
10682 }
10683 pf->next_vsi = 0;
10684 pf->pdev = pdev;
10685 set_bit(__I40E_DOWN, &pf->state);
10686
10687 hw = &pf->hw;
10688 hw->back = pf;
232f4706 10689
2ac8b675
SN		 10690 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10691 I40E_MAX_CSR_SPACE);
232f4706 10692
2ac8b675 10693 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10694 if (!hw->hw_addr) {
10695 err = -EIO;
10696 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10697 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10698 pf->ioremap_len, err);
41c445ff
JB		 10699 goto err_ioremap;
10700 }
10701 hw->vendor_id = pdev->vendor;
10702 hw->device_id = pdev->device;
10703 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10704 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10705 hw->subsystem_device_id = pdev->subsystem_device;
10706 hw->bus.device = PCI_SLOT(pdev->devfn);
10707 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10708 pf->instance = pfs_found;
41c445ff 10709
5b5faa43
SN		 10710 if (debug != -1) {
10711 pf->msg_enable = pf->hw.debug_mask;
10712 pf->msg_enable = debug;
10713 }
10714
7134f9ce
JB		 10715 /* do a special CORER for clearing PXE mode once at init */
10716 if (hw->revision_id == 0 &&
10717 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10718 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10719 i40e_flush(hw);
10720 msleep(200);
10721 pf->corer_count++;
10722
10723 i40e_clear_pxe_mode(hw);
10724 }
10725
41c445ff 10726 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10727 i40e_clear_hw(hw);
41c445ff
JB		 10728 err = i40e_pf_reset(hw);
10729 if (err) {
10730 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10731 goto err_pf_reset;
10732 }
10733 pf->pfr_count++;
10734
10735 hw->aq.num_arq_entries = I40E_AQ_LEN;
10736 hw->aq.num_asq_entries = I40E_AQ_LEN;
10737 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10738 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10739 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10740
b294ac70 10741 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10742 "%s-%s:misc",
10743 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10744
10745 err = i40e_init_shared_code(hw);
10746 if (err) {
b2a75c58
ASJ		 10747 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10748 err);
41c445ff
JB		 10749 goto err_pf_reset;
10750 }
10751
d52c20b7
JB		 10752 /* set up a default setting for link flow control */
10753 pf->hw.fc.requested_mode = I40E_FC_NONE;
10754
8ddb3326
JB		 10755 /* set up the locks for the AQ, do this only once in probe
10756 * and destroy them only once in remove
10757 */
10758 mutex_init(&hw->aq.asq_mutex);
10759 mutex_init(&hw->aq.arq_mutex);
10760
41c445ff 10761 err = i40e_init_adminq(hw);
2b2426a7
CW		 10762 if (err) {
10763 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10764 dev_info(&pdev->dev,
10765 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10766 else
10767 dev_info(&pdev->dev,
10768 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10769
10770 goto err_pf_reset;
10771 }
f0b44440 10772
6dec1017
SN		 10773 /* provide nvm, fw, api versions */
10774 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10775 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10776 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10777 i40e_nvm_version_str(hw));
f0b44440 10778
7aa67613
CS		 10779 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10780 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10781 dev_info(&pdev->dev,
7aa67613
CS		 10782 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10783 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10784 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10785 dev_info(&pdev->dev,
7aa67613 10786 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10787
4eb3f768
SN		 10788 i40e_verify_eeprom(pf);
10789
2c5fe33b
JB		 10790 /* Rev 0 hardware was never productized */
10791 if (hw->revision_id < 1)
10792 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10793
6ff4ef86 10794 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10795 err = i40e_get_capabilities(pf);
10796 if (err)
10797 goto err_adminq_setup;
10798
10799 err = i40e_sw_init(pf);
10800 if (err) {
10801 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10802 goto err_sw_init;
10803 }
10804
10805 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10806 hw->func_caps.num_rx_qp,
10807 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10808 if (err) {
10809 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10810 goto err_init_lan_hmc;
10811 }
10812
10813 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10814 if (err) {
10815 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10816 err = -ENOENT;
10817 goto err_configure_lan_hmc;
10818 }
10819
b686ece5
NP		 10820 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10821 * Ignore error return codes because if it was already disabled via
10822 * hardware settings this will fail
10823 */
10824 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10825 (pf->hw.aq.fw_maj_ver < 4)) {
10826 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10827 i40e_aq_stop_lldp(hw, true, NULL);
10828 }
10829
41c445ff 10830 i40e_get_mac_addr(hw, hw->mac.addr);
b499ffb0
SV		 10831 /* allow a platform config to override the HW addr */
10832 i40e_get_platform_mac_addr(pdev, pf);
f62b5060 10833 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10834 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10835 err = -EIO;
10836 goto err_mac_addr;
10837 }
10838 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10839 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10840 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10841 if (is_valid_ether_addr(hw->mac.port_addr))
10842 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10843#ifdef I40E_FCOE
10844 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10845 if (err)
10846 dev_info(&pdev->dev,
10847 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10848 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10849 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10850 hw->mac.san_addr);
10851 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10852 }
10853 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10854#endif /* I40E_FCOE */
41c445ff
JB		 10855
10856 pci_set_drvdata(pdev, pf);
10857 pci_save_state(pdev);
4e3b35b0
NP		 10858#ifdef CONFIG_I40E_DCB
10859 err = i40e_init_pf_dcb(pf);
10860 if (err) {
aebfc816 10861 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10862 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10863 /* Continue without DCB enabled */
4e3b35b0
NP		 10864 }
10865#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10866
10867 /* set up periodic task facility */
10868 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10869 pf->service_timer_period = HZ;
10870
10871 INIT_WORK(&pf->service_task, i40e_service_task);
10872 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10873 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10874
1d5109d1
SN		 10875 /* NVM bit on means WoL disabled for the port */
10876 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10877 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10878 pf->wol_en = false;
10879 else
10880 pf->wol_en = true;
8e2773ae
SN		 10881 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10882
41c445ff
JB		 10883 /* set up the main switch operations */
10884 i40e_determine_queue_usage(pf);
c1147280
JB		 10885 err = i40e_init_interrupt_scheme(pf);
10886 if (err)
10887 goto err_switch_setup;
41c445ff 10888
505682cd
MW		 10889 /* The number of VSIs reported by the FW is the minimum guaranteed
10890 * to us; HW supports far more and we share the remaining pool with
10891 * the other PFs. We allocate space for more than the guarantee with
10892 * the understanding that we might not get them all later.
41c445ff 10893 */
505682cd
MW		 10894 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10895 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10896 else
10897 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10898
10899 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
d17038d6
JB		 10900 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
10901 GFP_KERNEL);
ed87ac09
WY		 10902 if (!pf->vsi) {
10903 err = -ENOMEM;
41c445ff 10904 goto err_switch_setup;
ed87ac09 10905 }
41c445ff 10906
fa11cb3d
ASJ		 10907#ifdef CONFIG_PCI_IOV
10908 /* prep for VF support */
10909 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10910 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10911 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10912 if (pci_num_vf(pdev))
10913 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10914 }
10915#endif
bc7d338f 10916 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10917 if (err) {
10918 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10919 goto err_vsis;
10920 }
58fc3267
HZ		 10921
10922 /* Make sure flow control is set according to current settings */
10923 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10924 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10925 dev_dbg(&pf->pdev->dev,
10926 "Set fc with err %s aq_err %s on get_phy_cap\n",
10927 i40e_stat_str(hw, err),
10928 i40e_aq_str(hw, hw->aq.asq_last_status));
10929 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10930 dev_dbg(&pf->pdev->dev,
10931 "Set fc with err %s aq_err %s on set_phy_config\n",
10932 i40e_stat_str(hw, err),
10933 i40e_aq_str(hw, hw->aq.asq_last_status));
10934 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10935 dev_dbg(&pf->pdev->dev,
10936 "Set fc with err %s aq_err %s on get_link_info\n",
10937 i40e_stat_str(hw, err),
10938 i40e_aq_str(hw, hw->aq.asq_last_status));
10939
8a9eb7d3 10940 /* if FDIR VSI was set up, start it now */
505682cd 10941 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10942 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10943 i40e_vsi_open(pf->vsi[i]);
10944 break;
10945 }
10946 }
41c445ff 10947
2f0aff41
SN		 10948 /* The driver only wants link up/down and module qualification
10949 * reports from firmware. Note the negative logic.
7e2453fe
JB		 10950 */
10951 err = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41
SN		 10952 ~(I40E_AQ_EVENT_LINK_UPDOWN |
10953 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 10954 if (err)
f1c7e72e
SN		 10955 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10956 i40e_stat_str(&pf->hw, err),
10957 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10958
4f2f017c
ASJ		 10959 /* Reconfigure hardware for allowing smaller MSS in the case
10960 * of TSO, so that we avoid the MDD being fired and causing
10961 * a reset in the case of small MSS+TSO.
10962 */
10963 val = rd32(hw, I40E_REG_MSS);
10964 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10965 val &= ~I40E_REG_MSS_MIN_MASK;
10966 val |= I40E_64BYTE_MSS;
10967 wr32(hw, I40E_REG_MSS, val);
10968 }
10969
8eed76fa 10970 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 10971 msleep(75);
10972 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10973 if (err)
f1c7e72e
SN		 10974 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10975 i40e_stat_str(&pf->hw, err),
10976 i40e_aq_str(&pf->hw,
10977 pf->hw.aq.asq_last_status));
cafa2ee6 10978 }
41c445ff
JB		 10979 /* The main driver is (mostly) up and happy. We need to set this state
10980 * before setting up the misc vector or we get a race and the vector
10981 * ends up disabled forever.
10982 */
10983 clear_bit(__I40E_DOWN, &pf->state);
10984
10985 /* In case of MSIX we are going to setup the misc vector right here
10986 * to handle admin queue events etc. In case of legacy and MSI
10987 * the misc functionality and queue processing is combined in
10988 * the same vector and that gets setup at open.
10989 */
10990 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10991 err = i40e_setup_misc_vector(pf);
10992 if (err) {
10993 dev_info(&pdev->dev,
10994 "setup of misc vector failed: %d\n", err);
10995 goto err_vsis;
10996 }
10997 }
10998
df805f62 10999#ifdef CONFIG_PCI_IOV
41c445ff
JB		 11000 /* prep for VF support */
11001 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 11002 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11003 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 11004 /* disable link interrupts for VFs */
11005 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
11006 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
11007 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
11008 i40e_flush(hw);
4aeec010
MW		 11009
11010 if (pci_num_vf(pdev)) {
11011 dev_info(&pdev->dev,
11012 "Active VFs found, allocating resources.\n");
11013 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
11014 if (err)
11015 dev_info(&pdev->dev,
11016 "Error %d allocating resources for existing VFs\n",
11017 err);
11018 }
41c445ff 11019 }
df805f62 11020#endif /* CONFIG_PCI_IOV */
41c445ff 11021
93cd765b
ASJ		 11022 pfs_found++;
11023
41c445ff
JB		 11024 i40e_dbg_pf_init(pf);
11025
11026 /* tell the firmware that we're starting */
44033fac 11027 i40e_send_version(pf);
41c445ff
JB		 11028
11029 /* since everything's happy, start the service_task timer */
11030 mod_timer(&pf->service_timer,
11031 round_jiffies(jiffies + pf->service_timer_period));
11032
38e00438
VD		 11033#ifdef I40E_FCOE
11034 /* create FCoE interface */
11035 i40e_fcoe_vsi_setup(pf);
11036
11037#endif
3fced535
ASJ		 11038#define PCI_SPEED_SIZE 8
11039#define PCI_WIDTH_SIZE 8
11040 /* Devices on the IOSF bus do not have this information
11041 * and will report PCI Gen 1 x 1 by default so don't bother
11042 * checking them.
11043 */
11044 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
11045 char speed[PCI_SPEED_SIZE] = "Unknown";
11046 char width[PCI_WIDTH_SIZE] = "Unknown";
11047
11048 /* Get the negotiated link width and speed from PCI config
11049 * space
11050 */
11051 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
11052 &link_status);
11053
11054 i40e_set_pci_config_data(hw, link_status);
11055
11056 switch (hw->bus.speed) {
11057 case i40e_bus_speed_8000:
11058 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
11059 case i40e_bus_speed_5000:
11060 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
11061 case i40e_bus_speed_2500:
11062 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
11063 default:
11064 break;
11065 }
11066 switch (hw->bus.width) {
11067 case i40e_bus_width_pcie_x8:
11068 strncpy(width, "8", PCI_WIDTH_SIZE); break;
11069 case i40e_bus_width_pcie_x4:
11070 strncpy(width, "4", PCI_WIDTH_SIZE); break;
11071 case i40e_bus_width_pcie_x2:
11072 strncpy(width, "2", PCI_WIDTH_SIZE); break;
11073 case i40e_bus_width_pcie_x1:
11074 strncpy(width, "1", PCI_WIDTH_SIZE); break;
11075 default:
11076 break;
11077 }
11078
11079 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
11080 speed, width);
11081
11082 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
11083 hw->bus.speed < i40e_bus_speed_8000) {
11084 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
11085 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
11086 }
d4dfb81a
CS		 11087 }
11088
e827845c
CS		 11089 /* get the requested speeds from the fw */
11090 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
11091 if (err)
8279e495
NP		 11092 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
11093 i40e_stat_str(&pf->hw, err),
11094 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 11095 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
11096
fc72dbce
CS		 11097 /* get the supported phy types from the fw */
11098 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
11099 if (err)
11100 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
11101 i40e_stat_str(&pf->hw, err),
11102 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11103 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
11104
e7358f54
ASJ		 11105 /* Add a filter to drop all Flow control frames from any VSI from being
11106 * transmitted. By doing so we stop a malicious VF from sending out
11107 * PAUSE or PFC frames and potentially controlling traffic for other
11108 * PF/VF VSIs.
11109 * The FW can still send Flow control frames if enabled.
11110 */
11111 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11112 pf->main_vsi_seid);
11113
0c22b3dd
JB		 11114 /* print a string summarizing features */
11115 i40e_print_features(pf);
11116
41c445ff
JB		 11117 return 0;
11118
11119 /* Unwind what we've done if something failed in the setup */
11120err_vsis:
11121 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 11122 i40e_clear_interrupt_scheme(pf);
11123 kfree(pf->vsi);
04b03013
SN		 11124err_switch_setup:
11125 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 11126 del_timer_sync(&pf->service_timer);
11127err_mac_addr:
11128err_configure_lan_hmc:
11129 (void)i40e_shutdown_lan_hmc(hw);
11130err_init_lan_hmc:
11131 kfree(pf->qp_pile);
41c445ff
JB		 11132err_sw_init:
11133err_adminq_setup:
11134 (void)i40e_shutdown_adminq(hw);
11135err_pf_reset:
11136 iounmap(hw->hw_addr);
11137err_ioremap:
11138 kfree(pf);
11139err_pf_alloc:
11140 pci_disable_pcie_error_reporting(pdev);
11141 pci_release_selected_regions(pdev,
11142 pci_select_bars(pdev, IORESOURCE_MEM));
11143err_pci_reg:
11144err_dma:
11145 pci_disable_device(pdev);
11146 return err;
11147}
11148
11149/**
11150 * i40e_remove - Device removal routine
11151 * @pdev: PCI device information struct
11152 *
11153 * i40e_remove is called by the PCI subsystem to alert the driver
11154 * that is should release a PCI device. This could be caused by a
11155 * Hot-Plug event, or because the driver is going to be removed from
11156 * memory.
11157 **/
11158static void i40e_remove(struct pci_dev *pdev)
11159{
11160 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11161 struct i40e_hw *hw = &pf->hw;
41c445ff 11162 i40e_status ret_code;
41c445ff
JB		 11163 int i;
11164
11165 i40e_dbg_pf_exit(pf);
11166
beb0dff1
JK		 11167 i40e_ptp_stop(pf);
11168
bcab2db9
CW		 11169 /* Disable RSS in hw */
11170 wr32(hw, I40E_PFQF_HENA(0), 0);
11171 wr32(hw, I40E_PFQF_HENA(1), 0);
11172
41c445ff
JB		 11173 /* no more scheduling of any task */
11174 set_bit(__I40E_DOWN, &pf->state);
11175 del_timer_sync(&pf->service_timer);
11176 cancel_work_sync(&pf->service_task);
11177
eb2d80bc
MW		 11178 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11179 i40e_free_vfs(pf);
11180 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11181 }
11182
41c445ff
JB		 11183 i40e_fdir_teardown(pf);
11184
11185 /* If there is a switch structure or any orphans, remove them.
11186 * This will leave only the PF's VSI remaining.
11187 */
11188 for (i = 0; i < I40E_MAX_VEB; i++) {
11189 if (!pf->veb[i])
11190 continue;
11191
11192 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11193 pf->veb[i]->uplink_seid == 0)
11194 i40e_switch_branch_release(pf->veb[i]);
11195 }
11196
11197 /* Now we can shutdown the PF's VSI, just before we kill
11198 * adminq and hmc.
11199 */
11200 if (pf->vsi[pf->lan_vsi])
11201 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11202
41c445ff 11203 /* shutdown and destroy the HMC */
60442dea
SN		 11204 if (pf->hw.hmc.hmc_obj) {
11205 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
11206 if (ret_code)
11207 dev_warn(&pdev->dev,
11208 "Failed to destroy the HMC resources: %d\n",
11209 ret_code);
11210 }
41c445ff
JB		 11211
11212 /* shutdown the adminq */
41c445ff
JB		 11213 ret_code = i40e_shutdown_adminq(&pf->hw);
11214 if (ret_code)
11215 dev_warn(&pdev->dev,
11216 "Failed to destroy the Admin Queue resources: %d\n",
11217 ret_code);
11218
8ddb3326
JB		 11219 /* destroy the locks only once, here */
11220 mutex_destroy(&hw->aq.arq_mutex);
11221 mutex_destroy(&hw->aq.asq_mutex);
11222
41c445ff
JB		 11223 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11224 i40e_clear_interrupt_scheme(pf);
505682cd 11225 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11226 if (pf->vsi[i]) {
11227 i40e_vsi_clear_rings(pf->vsi[i]);
11228 i40e_vsi_clear(pf->vsi[i]);
11229 pf->vsi[i] = NULL;
11230 }
11231 }
11232
11233 for (i = 0; i < I40E_MAX_VEB; i++) {
11234 kfree(pf->veb[i]);
11235 pf->veb[i] = NULL;
11236 }
11237
11238 kfree(pf->qp_pile);
41c445ff
JB		 11239 kfree(pf->vsi);
11240
41c445ff
JB		 11241 iounmap(pf->hw.hw_addr);
11242 kfree(pf);
11243 pci_release_selected_regions(pdev,
11244 pci_select_bars(pdev, IORESOURCE_MEM));
11245
11246 pci_disable_pcie_error_reporting(pdev);
11247 pci_disable_device(pdev);
11248}
11249
11250/**
11251 * i40e_pci_error_detected - warning that something funky happened in PCI land
11252 * @pdev: PCI device information struct
11253 *
11254 * Called to warn that something happened and the error handling steps
11255 * are in progress. Allows the driver to quiesce things, be ready for
11256 * remediation.
11257 **/
11258static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11259 enum pci_channel_state error)
11260{
11261 struct i40e_pf *pf = pci_get_drvdata(pdev);
11262
11263 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11264
11265 /* shutdown all operations */
9007bccd
SN		 11266 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11267 rtnl_lock();
11268 i40e_prep_for_reset(pf);
11269 rtnl_unlock();
11270 }
41c445ff
JB		 11271
11272 /* Request a slot reset */
11273 return PCI_ERS_RESULT_NEED_RESET;
11274}
11275
11276/**
11277 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11278 * @pdev: PCI device information struct
11279 *
11280 * Called to find if the driver can work with the device now that
11281 * the pci slot has been reset. If a basic connection seems good
11282 * (registers are readable and have sane content) then return a
11283 * happy little PCI_ERS_RESULT_xxx.
11284 **/
11285static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11286{
11287 struct i40e_pf *pf = pci_get_drvdata(pdev);
11288 pci_ers_result_t result;
11289 int err;
11290 u32 reg;
11291
fb43201f 11292 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11293 if (pci_enable_device_mem(pdev)) {
11294 dev_info(&pdev->dev,
11295 "Cannot re-enable PCI device after reset.\n");
11296 result = PCI_ERS_RESULT_DISCONNECT;
11297 } else {
11298 pci_set_master(pdev);
11299 pci_restore_state(pdev);
11300 pci_save_state(pdev);
11301 pci_wake_from_d3(pdev, false);
11302
11303 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11304 if (reg == 0)
11305 result = PCI_ERS_RESULT_RECOVERED;
11306 else
11307 result = PCI_ERS_RESULT_DISCONNECT;
11308 }
11309
11310 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11311 if (err) {
11312 dev_info(&pdev->dev,
11313 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11314 err);
11315 /* non-fatal, continue */
11316 }
11317
11318 return result;
11319}
11320
11321/**
11322 * i40e_pci_error_resume - restart operations after PCI error recovery
11323 * @pdev: PCI device information struct
11324 *
11325 * Called to allow the driver to bring things back up after PCI error
11326 * and/or reset recovery has finished.
11327 **/
11328static void i40e_pci_error_resume(struct pci_dev *pdev)
11329{
11330 struct i40e_pf *pf = pci_get_drvdata(pdev);
11331
fb43201f 11332 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11333 if (test_bit(__I40E_SUSPENDED, &pf->state))
11334 return;
11335
11336 rtnl_lock();
41c445ff 11337 i40e_handle_reset_warning(pf);
4c4935a9 11338 rtnl_unlock();
9007bccd
SN		 11339}
11340
11341/**
11342 * i40e_shutdown - PCI callback for shutting down
11343 * @pdev: PCI device information struct
11344 **/
11345static void i40e_shutdown(struct pci_dev *pdev)
11346{
11347 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11348 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11349
11350 set_bit(__I40E_SUSPENDED, &pf->state);
11351 set_bit(__I40E_DOWN, &pf->state);
11352 rtnl_lock();
11353 i40e_prep_for_reset(pf);
11354 rtnl_unlock();
11355
8e2773ae
SN		 11356 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11357 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11358
02b42498
CS		 11359 del_timer_sync(&pf->service_timer);
11360 cancel_work_sync(&pf->service_task);
11361 i40e_fdir_teardown(pf);
11362
11363 rtnl_lock();
11364 i40e_prep_for_reset(pf);
11365 rtnl_unlock();
11366
11367 wr32(hw, I40E_PFPM_APM,
11368 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11369 wr32(hw, I40E_PFPM_WUFC,
11370 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11371
e147758d
SN		 11372 i40e_clear_interrupt_scheme(pf);
11373
9007bccd 11374 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11375 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11376 pci_set_power_state(pdev, PCI_D3hot);
11377 }
11378}
11379
11380#ifdef CONFIG_PM
11381/**
11382 * i40e_suspend - PCI callback for moving to D3
11383 * @pdev: PCI device information struct
11384 **/
11385static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11386{
11387 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11388 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11389
11390 set_bit(__I40E_SUSPENDED, &pf->state);
11391 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11392
9007bccd
SN		 11393 rtnl_lock();
11394 i40e_prep_for_reset(pf);
11395 rtnl_unlock();
11396
8e2773ae
SN		 11397 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11398 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11399
11400 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11401 pci_set_power_state(pdev, PCI_D3hot);
11402
11403 return 0;
41c445ff
JB		 11404}
11405
9007bccd
SN		 11406/**
11407 * i40e_resume - PCI callback for waking up from D3
11408 * @pdev: PCI device information struct
11409 **/
11410static int i40e_resume(struct pci_dev *pdev)
11411{
11412 struct i40e_pf *pf = pci_get_drvdata(pdev);
11413 u32 err;
11414
11415 pci_set_power_state(pdev, PCI_D0);
11416 pci_restore_state(pdev);
11417 /* pci_restore_state() clears dev->state_saves, so
11418 * call pci_save_state() again to restore it.
11419 */
11420 pci_save_state(pdev);
11421
11422 err = pci_enable_device_mem(pdev);
11423 if (err) {
fb43201f 11424 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11425 return err;
11426 }
11427 pci_set_master(pdev);
11428
11429 /* no wakeup events while running */
11430 pci_wake_from_d3(pdev, false);
11431
11432 /* handling the reset will rebuild the device state */
11433 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11434 clear_bit(__I40E_DOWN, &pf->state);
11435 rtnl_lock();
11436 i40e_reset_and_rebuild(pf, false);
11437 rtnl_unlock();
11438 }
11439
11440 return 0;
11441}
11442
11443#endif
41c445ff
JB		 11444static const struct pci_error_handlers i40e_err_handler = {
11445 .error_detected = i40e_pci_error_detected,
11446 .slot_reset = i40e_pci_error_slot_reset,
11447 .resume = i40e_pci_error_resume,
11448};
11449
11450static struct pci_driver i40e_driver = {
11451 .name = i40e_driver_name,
11452 .id_table = i40e_pci_tbl,
11453 .probe = i40e_probe,
11454 .remove = i40e_remove,
9007bccd
SN		 11455#ifdef CONFIG_PM
11456 .suspend = i40e_suspend,
11457 .resume = i40e_resume,
11458#endif
11459 .shutdown = i40e_shutdown,
41c445ff
JB		 11460 .err_handler = &i40e_err_handler,
11461 .sriov_configure = i40e_pci_sriov_configure,
11462};
11463
11464/**
11465 * i40e_init_module - Driver registration routine
11466 *
11467 * i40e_init_module is the first routine called when the driver is
11468 * loaded. All it does is register with the PCI subsystem.
11469 **/
11470static int __init i40e_init_module(void)
11471{
11472 pr_info("%s: %s - version %s\n", i40e_driver_name,
11473 i40e_driver_string, i40e_driver_version_str);
11474 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11475
2803b16c
JB		 11476 /* we will see if single thread per module is enough for now,
11477 * it can't be any worse than using the system workqueue which
11478 * was already single threaded
11479 */
11480 i40e_wq = create_singlethread_workqueue(i40e_driver_name);
11481 if (!i40e_wq) {
11482 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
11483 return -ENOMEM;
11484 }
11485
41c445ff
JB		 11486 i40e_dbg_init();
11487 return pci_register_driver(&i40e_driver);
11488}
11489module_init(i40e_init_module);
11490
11491/**
11492 * i40e_exit_module - Driver exit cleanup routine
11493 *
11494 * i40e_exit_module is called just before the driver is removed
11495 * from memory.
11496 **/
11497static void __exit i40e_exit_module(void)
11498{
11499 pci_unregister_driver(&i40e_driver);
2803b16c 11500 destroy_workqueue(i40e_wq);
41c445ff
JB		 11501 i40e_dbg_exit();
11502}
11503module_exit(i40e_exit_module);
Linux kernel - Deliverables
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