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net: bcmgenet: simplify __bcmgenet_tx_reclaim()
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
a36fdd8e 41#define DRV_VERSION_MINOR 2
ce458fcf 42#define DRV_VERSION_BUILD 10
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
38e00438
VD		 273#ifdef I40E_FCOE
274void i40e_tx_timeout(struct net_device *netdev)
275#else
41c445ff 276static void i40e_tx_timeout(struct net_device *netdev)
38e00438 277#endif
41c445ff
JB		 278{
279 struct i40e_netdev_priv *np = netdev_priv(netdev);
280 struct i40e_vsi *vsi = np->vsi;
281 struct i40e_pf *pf = vsi->back;
282
283 pf->tx_timeout_count++;
284
285 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 286 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 287 pf->tx_timeout_last_recovery = jiffies;
288 netdev_info(netdev, "tx_timeout recovery level %d\n",
289 pf->tx_timeout_recovery_level);
290
291 switch (pf->tx_timeout_recovery_level) {
292 case 0:
293 /* disable and re-enable queues for the VSI */
294 if (in_interrupt()) {
295 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
296 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
297 } else {
298 i40e_vsi_reinit_locked(vsi);
299 }
300 break;
301 case 1:
302 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
303 break;
304 case 2:
305 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
306 break;
307 case 3:
308 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
309 break;
310 default:
311 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 312 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
313 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 314 break;
315 }
316 i40e_service_event_schedule(pf);
317 pf->tx_timeout_recovery_level++;
318}
319
320/**
321 * i40e_release_rx_desc - Store the new tail and head values
322 * @rx_ring: ring to bump
323 * @val: new head index
324 **/
325static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
326{
327 rx_ring->next_to_use = val;
328
329 /* Force memory writes to complete before letting h/w
330 * know there are new descriptors to fetch. (Only
331 * applicable for weak-ordered memory model archs,
332 * such as IA-64).
333 */
334 wmb();
335 writel(val, rx_ring->tail);
336}
337
338/**
339 * i40e_get_vsi_stats_struct - Get System Network Statistics
340 * @vsi: the VSI we care about
341 *
342 * Returns the address of the device statistics structure.
343 * The statistics are actually updated from the service task.
344 **/
345struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
346{
347 return &vsi->net_stats;
348}
349
350/**
351 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
352 * @netdev: network interface device structure
353 *
354 * Returns the address of the device statistics structure.
355 * The statistics are actually updated from the service task.
356 **/
38e00438
VD		 357#ifdef I40E_FCOE
358struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
359 struct net_device *netdev,
360 struct rtnl_link_stats64 *stats)
361#else
41c445ff
JB		 362static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
363 struct net_device *netdev,
980e9b11 364 struct rtnl_link_stats64 *stats)
38e00438 365#endif
41c445ff
JB		 366{
367 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 368 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 369 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 370 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
371 int i;
372
bc7d338f
ASJ		 373 if (test_bit(__I40E_DOWN, &vsi->state))
374 return stats;
375
3c325ced
JB		 376 if (!vsi->tx_rings)
377 return stats;
378
980e9b11
AD		 379 rcu_read_lock();
380 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 381 u64 bytes, packets;
382 unsigned int start;
383
384 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
385 if (!tx_ring)
386 continue;
387
388 do {
57a7744e 389 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 390 packets = tx_ring->stats.packets;
391 bytes = tx_ring->stats.bytes;
57a7744e 392 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 393
394 stats->tx_packets += packets;
395 stats->tx_bytes += bytes;
396 rx_ring = &tx_ring[1];
397
398 do {
57a7744e 399 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 400 packets = rx_ring->stats.packets;
401 bytes = rx_ring->stats.bytes;
57a7744e 402 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 403
980e9b11
AD		 404 stats->rx_packets += packets;
405 stats->rx_bytes += bytes;
406 }
407 rcu_read_unlock();
408
a5282f44 409 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 410 stats->multicast = vsi_stats->multicast;
411 stats->tx_errors = vsi_stats->tx_errors;
412 stats->tx_dropped = vsi_stats->tx_dropped;
413 stats->rx_errors = vsi_stats->rx_errors;
414 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
415 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 416
980e9b11 417 return stats;
41c445ff
JB		 418}
419
420/**
421 * i40e_vsi_reset_stats - Resets all stats of the given vsi
422 * @vsi: the VSI to have its stats reset
423 **/
424void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
425{
426 struct rtnl_link_stats64 *ns;
427 int i;
428
429 if (!vsi)
430 return;
431
432 ns = i40e_get_vsi_stats_struct(vsi);
433 memset(ns, 0, sizeof(*ns));
434 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
435 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
436 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 437 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 438 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 439 memset(&vsi->rx_rings[i]->stats, 0 ,
440 sizeof(vsi->rx_rings[i]->stats));
441 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
442 sizeof(vsi->rx_rings[i]->rx_stats));
443 memset(&vsi->tx_rings[i]->stats, 0 ,
444 sizeof(vsi->tx_rings[i]->stats));
445 memset(&vsi->tx_rings[i]->tx_stats, 0,
446 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 447 }
8e9dca53 448 }
41c445ff
JB		 449 vsi->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_pf_reset_stats - Reset all of the stats for the given pf
454 * @pf: the PF to be reset
455 **/
456void i40e_pf_reset_stats(struct i40e_pf *pf)
457{
e91fdf76
SN		 458 int i;
459
41c445ff
JB		 460 memset(&pf->stats, 0, sizeof(pf->stats));
461 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
462 pf->stat_offsets_loaded = false;
e91fdf76
SN		 463
464 for (i = 0; i < I40E_MAX_VEB; i++) {
465 if (pf->veb[i]) {
466 memset(&pf->veb[i]->stats, 0,
467 sizeof(pf->veb[i]->stats));
468 memset(&pf->veb[i]->stats_offsets, 0,
469 sizeof(pf->veb[i]->stats_offsets));
470 pf->veb[i]->stat_offsets_loaded = false;
471 }
472 }
41c445ff
JB		 473}
474
475/**
476 * i40e_stat_update48 - read and update a 48 bit stat from the chip
477 * @hw: ptr to the hardware info
478 * @hireg: the high 32 bit reg to read
479 * @loreg: the low 32 bit reg to read
480 * @offset_loaded: has the initial offset been loaded yet
481 * @offset: ptr to current offset value
482 * @stat: ptr to the stat
483 *
484 * Since the device stats are not reset at PFReset, they likely will not
485 * be zeroed when the driver starts. We'll save the first values read
486 * and use them as offsets to be subtracted from the raw values in order
487 * to report stats that count from zero. In the process, we also manage
488 * the potential roll-over.
489 **/
490static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
491 bool offset_loaded, u64 *offset, u64 *stat)
492{
493 u64 new_data;
494
ab60085e 495 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 496 new_data = rd32(hw, loreg);
497 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
498 } else {
499 new_data = rd64(hw, loreg);
500 }
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = new_data - *offset;
505 else
506 *stat = (new_data + ((u64)1 << 48)) - *offset;
507 *stat &= 0xFFFFFFFFFFFFULL;
508}
509
510/**
511 * i40e_stat_update32 - read and update a 32 bit stat from the chip
512 * @hw: ptr to the hardware info
513 * @reg: the hw reg to read
514 * @offset_loaded: has the initial offset been loaded yet
515 * @offset: ptr to current offset value
516 * @stat: ptr to the stat
517 **/
518static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
519 bool offset_loaded, u64 *offset, u64 *stat)
520{
521 u32 new_data;
522
523 new_data = rd32(hw, reg);
524 if (!offset_loaded)
525 *offset = new_data;
526 if (likely(new_data >= *offset))
527 *stat = (u32)(new_data - *offset);
528 else
529 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
530}
531
532/**
533 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
534 * @vsi: the VSI to be updated
535 **/
536void i40e_update_eth_stats(struct i40e_vsi *vsi)
537{
538 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
539 struct i40e_pf *pf = vsi->back;
540 struct i40e_hw *hw = &pf->hw;
541 struct i40e_eth_stats *oes;
542 struct i40e_eth_stats *es; /* device's eth stats */
543
544 es = &vsi->eth_stats;
545 oes = &vsi->eth_stats_offsets;
546
547 /* Gather up the stats that the hw collects */
548 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_errors, &es->tx_errors);
551 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 554 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
555 vsi->stat_offsets_loaded,
556 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
557 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 560
561 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
562 I40E_GLV_GORCL(stat_idx),
563 vsi->stat_offsets_loaded,
564 &oes->rx_bytes, &es->rx_bytes);
565 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
566 I40E_GLV_UPRCL(stat_idx),
567 vsi->stat_offsets_loaded,
568 &oes->rx_unicast, &es->rx_unicast);
569 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
570 I40E_GLV_MPRCL(stat_idx),
571 vsi->stat_offsets_loaded,
572 &oes->rx_multicast, &es->rx_multicast);
573 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
574 I40E_GLV_BPRCL(stat_idx),
575 vsi->stat_offsets_loaded,
576 &oes->rx_broadcast, &es->rx_broadcast);
577
578 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
579 I40E_GLV_GOTCL(stat_idx),
580 vsi->stat_offsets_loaded,
581 &oes->tx_bytes, &es->tx_bytes);
582 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
583 I40E_GLV_UPTCL(stat_idx),
584 vsi->stat_offsets_loaded,
585 &oes->tx_unicast, &es->tx_unicast);
586 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
587 I40E_GLV_MPTCL(stat_idx),
588 vsi->stat_offsets_loaded,
589 &oes->tx_multicast, &es->tx_multicast);
590 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
591 I40E_GLV_BPTCL(stat_idx),
592 vsi->stat_offsets_loaded,
593 &oes->tx_broadcast, &es->tx_broadcast);
594 vsi->stat_offsets_loaded = true;
595}
596
597/**
598 * i40e_update_veb_stats - Update Switch component statistics
599 * @veb: the VEB being updated
600 **/
601static void i40e_update_veb_stats(struct i40e_veb *veb)
602{
603 struct i40e_pf *pf = veb->pf;
604 struct i40e_hw *hw = &pf->hw;
605 struct i40e_eth_stats *oes;
606 struct i40e_eth_stats *es; /* device's eth stats */
607 int idx = 0;
608
609 idx = veb->stats_idx;
610 es = &veb->stats;
611 oes = &veb->stats_offsets;
612
613 /* Gather up the stats that the hw collects */
614 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 617 if (hw->revision_id > 0)
618 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
619 veb->stat_offsets_loaded,
620 &oes->rx_unknown_protocol,
621 &es->rx_unknown_protocol);
41c445ff
JB		 622 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
623 veb->stat_offsets_loaded,
624 &oes->rx_bytes, &es->rx_bytes);
625 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
626 veb->stat_offsets_loaded,
627 &oes->rx_unicast, &es->rx_unicast);
628 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
629 veb->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
632 veb->stat_offsets_loaded,
633 &oes->rx_broadcast, &es->rx_broadcast);
634
635 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
636 veb->stat_offsets_loaded,
637 &oes->tx_bytes, &es->tx_bytes);
638 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
639 veb->stat_offsets_loaded,
640 &oes->tx_unicast, &es->tx_unicast);
641 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
642 veb->stat_offsets_loaded,
643 &oes->tx_multicast, &es->tx_multicast);
644 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
645 veb->stat_offsets_loaded,
646 &oes->tx_broadcast, &es->tx_broadcast);
647 veb->stat_offsets_loaded = true;
648}
649
38e00438
VD		 650#ifdef I40E_FCOE
651/**
652 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
653 * @vsi: the VSI that is capable of doing FCoE
654 **/
655static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
656{
657 struct i40e_pf *pf = vsi->back;
658 struct i40e_hw *hw = &pf->hw;
659 struct i40e_fcoe_stats *ofs;
660 struct i40e_fcoe_stats *fs; /* device's eth stats */
661 int idx;
662
663 if (vsi->type != I40E_VSI_FCOE)
664 return;
665
666 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
667 fs = &vsi->fcoe_stats;
668 ofs = &vsi->fcoe_stats_offsets;
669
670 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
671 vsi->fcoe_stat_offsets_loaded,
672 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
673 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
674 vsi->fcoe_stat_offsets_loaded,
675 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
676 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
677 vsi->fcoe_stat_offsets_loaded,
678 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
679 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
680 vsi->fcoe_stat_offsets_loaded,
681 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
682 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
683 vsi->fcoe_stat_offsets_loaded,
684 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
685 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
686 vsi->fcoe_stat_offsets_loaded,
687 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
688 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
689 vsi->fcoe_stat_offsets_loaded,
690 &ofs->fcoe_last_error, &fs->fcoe_last_error);
691 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
692 vsi->fcoe_stat_offsets_loaded,
693 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
694
695 vsi->fcoe_stat_offsets_loaded = true;
696}
697
698#endif
41c445ff
JB		 699/**
700 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
701 * @pf: the corresponding PF
702 *
703 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
704 **/
705static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
706{
707 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
708 struct i40e_hw_port_stats *nsd = &pf->stats;
709 struct i40e_hw *hw = &pf->hw;
710 u64 xoff = 0;
711 u16 i, v;
712
713 if ((hw->fc.current_mode != I40E_FC_FULL) &&
714 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
715 return;
716
717 xoff = nsd->link_xoff_rx;
718 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
719 pf->stat_offsets_loaded,
720 &osd->link_xoff_rx, &nsd->link_xoff_rx);
721
722 /* No new LFC xoff rx */
723 if (!(nsd->link_xoff_rx - xoff))
724 return;
725
726 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 727 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 728 struct i40e_vsi *vsi = pf->vsi[v];
729
ddfda80f 730 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 731 continue;
732
733 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 734 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 735 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
736 }
737 }
738}
739
740/**
741 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
742 * @pf: the corresponding PF
743 *
744 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
745 **/
746static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
747{
748 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
749 struct i40e_hw_port_stats *nsd = &pf->stats;
750 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
751 struct i40e_dcbx_config *dcb_cfg;
752 struct i40e_hw *hw = &pf->hw;
753 u16 i, v;
754 u8 tc;
755
756 dcb_cfg = &hw->local_dcbx_config;
757
758 /* See if DCB enabled with PFC TC */
759 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
760 !(dcb_cfg->pfc.pfcenable)) {
761 i40e_update_link_xoff_rx(pf);
762 return;
763 }
764
765 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
766 u64 prio_xoff = nsd->priority_xoff_rx[i];
767 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
768 pf->stat_offsets_loaded,
769 &osd->priority_xoff_rx[i],
770 &nsd->priority_xoff_rx[i]);
771
772 /* No new PFC xoff rx */
773 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
774 continue;
775 /* Get the TC for given priority */
776 tc = dcb_cfg->etscfg.prioritytable[i];
777 xoff[tc] = true;
778 }
779
780 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 781 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 782 struct i40e_vsi *vsi = pf->vsi[v];
783
ddfda80f 784 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 785 continue;
786
787 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 788 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 789
790 tc = ring->dcb_tc;
791 if (xoff[tc])
792 clear_bit(__I40E_HANG_CHECK_ARMED,
793 &ring->state);
794 }
795 }
796}
797
798/**
7812fddc 799 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 800 * @vsi: the VSI to be updated
801 *
802 * There are a few instances where we store the same stat in a
803 * couple of different structs. This is partly because we have
804 * the netdev stats that need to be filled out, which is slightly
805 * different from the "eth_stats" defined by the chip and used in
7812fddc 806 * VF communications. We sort it out here.
41c445ff 807 **/
7812fddc 808static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 809{
810 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 811 struct rtnl_link_stats64 *ons;
812 struct rtnl_link_stats64 *ns; /* netdev stats */
813 struct i40e_eth_stats *oes;
814 struct i40e_eth_stats *es; /* device's eth stats */
815 u32 tx_restart, tx_busy;
bf00b376 816 struct i40e_ring *p;
41c445ff 817 u32 rx_page, rx_buf;
bf00b376
AA		 818 u64 bytes, packets;
819 unsigned int start;
41c445ff
JB		 820 u64 rx_p, rx_b;
821 u64 tx_p, tx_b;
41c445ff
JB		 822 u16 q;
823
824 if (test_bit(__I40E_DOWN, &vsi->state) ||
825 test_bit(__I40E_CONFIG_BUSY, &pf->state))
826 return;
827
828 ns = i40e_get_vsi_stats_struct(vsi);
829 ons = &vsi->net_stats_offsets;
830 es = &vsi->eth_stats;
831 oes = &vsi->eth_stats_offsets;
832
833 /* Gather up the netdev and vsi stats that the driver collects
834 * on the fly during packet processing
835 */
836 rx_b = rx_p = 0;
837 tx_b = tx_p = 0;
838 tx_restart = tx_busy = 0;
839 rx_page = 0;
840 rx_buf = 0;
980e9b11 841 rcu_read_lock();
41c445ff 842 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc
SN		 898/**
899 * i40e_update_pf_stats - Update the pf statistics counters.
900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
532d283d
SN		 922 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
923 I40E_GLPRT_UPRCL(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_unicast,
926 &nsd->eth.rx_unicast);
7812fddc
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
928 I40E_GLPRT_MPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_multicast,
931 &nsd->eth.rx_multicast);
532d283d
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
933 I40E_GLPRT_BPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_broadcast,
936 &nsd->eth.rx_broadcast);
937 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
938 I40E_GLPRT_UPTCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.tx_unicast,
941 &nsd->eth.tx_unicast);
942 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
943 I40E_GLPRT_MPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_multicast,
946 &nsd->eth.tx_multicast);
947 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
948 I40E_GLPRT_BPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_broadcast,
951 &nsd->eth.tx_broadcast);
41c445ff 952
7812fddc
SN		 953 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_dropped_link_down,
956 &nsd->tx_dropped_link_down);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->crc_errors, &nsd->crc_errors);
41c445ff 961
7812fddc
SN		 962 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 965
7812fddc
SN		 966 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->mac_local_faults,
969 &nsd->mac_local_faults);
970 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->mac_remote_faults,
973 &nsd->mac_remote_faults);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->rx_length_errors,
978 &nsd->rx_length_errors);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->link_xon_rx, &nsd->link_xon_rx);
983 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->link_xon_tx, &nsd->link_xon_tx);
986 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
987 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 990
7812fddc
SN		 991 for (i = 0; i < 8; i++) {
992 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 993 pf->stat_offsets_loaded,
7812fddc
SN		 994 &osd->priority_xon_rx[i],
995 &nsd->priority_xon_rx[i]);
996 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 997 pf->stat_offsets_loaded,
7812fddc
SN		 998 &osd->priority_xon_tx[i],
999 &nsd->priority_xon_tx[i]);
1000 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1001 pf->stat_offsets_loaded,
7812fddc
SN		 1002 &osd->priority_xoff_tx[i],
1003 &nsd->priority_xoff_tx[i]);
1004 i40e_stat_update32(hw,
1005 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xon_2_xoff[i],
1008 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1009 }
1010
7812fddc
SN		 1011 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1012 I40E_GLPRT_PRC64L(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->rx_size_64, &nsd->rx_size_64);
1015 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1016 I40E_GLPRT_PRC127L(hw->port),
1017 pf->stat_offsets_loaded,
1018 &osd->rx_size_127, &nsd->rx_size_127);
1019 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1020 I40E_GLPRT_PRC255L(hw->port),
1021 pf->stat_offsets_loaded,
1022 &osd->rx_size_255, &nsd->rx_size_255);
1023 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1024 I40E_GLPRT_PRC511L(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->rx_size_511, &nsd->rx_size_511);
1027 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1028 I40E_GLPRT_PRC1023L(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->rx_size_1023, &nsd->rx_size_1023);
1031 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1032 I40E_GLPRT_PRC1522L(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->rx_size_1522, &nsd->rx_size_1522);
1035 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1036 I40E_GLPRT_PRC9522L(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->rx_size_big, &nsd->rx_size_big);
1039
1040 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1041 I40E_GLPRT_PTC64L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->tx_size_64, &nsd->tx_size_64);
1044 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1045 I40E_GLPRT_PTC127L(hw->port),
1046 pf->stat_offsets_loaded,
1047 &osd->tx_size_127, &nsd->tx_size_127);
1048 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1049 I40E_GLPRT_PTC255L(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->tx_size_255, &nsd->tx_size_255);
1052 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1053 I40E_GLPRT_PTC511L(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->tx_size_511, &nsd->tx_size_511);
1056 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1057 I40E_GLPRT_PTC1023L(hw->port),
1058 pf->stat_offsets_loaded,
1059 &osd->tx_size_1023, &nsd->tx_size_1023);
1060 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1061 I40E_GLPRT_PTC1522L(hw->port),
1062 pf->stat_offsets_loaded,
1063 &osd->tx_size_1522, &nsd->tx_size_1522);
1064 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1065 I40E_GLPRT_PTC9522L(hw->port),
1066 pf->stat_offsets_loaded,
1067 &osd->tx_size_big, &nsd->tx_size_big);
1068
1069 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1070 pf->stat_offsets_loaded,
1071 &osd->rx_undersize, &nsd->rx_undersize);
1072 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->rx_fragments, &nsd->rx_fragments);
1075 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1076 pf->stat_offsets_loaded,
1077 &osd->rx_oversize, &nsd->rx_oversize);
1078 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_jabber, &nsd->rx_jabber);
1081
433c47de
ASJ		 1082 /* FDIR stats */
1083 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1084 pf->stat_offsets_loaded,
1085 &osd->fd_atr_match, &nsd->fd_atr_match);
1086 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1087 pf->stat_offsets_loaded,
1088 &osd->fd_sb_match, &nsd->fd_sb_match);
1089
7812fddc
SN		 1090 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1091 nsd->tx_lpi_status =
1092 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1093 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1094 nsd->rx_lpi_status =
1095 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1096 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1097 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1098 pf->stat_offsets_loaded,
1099 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1100 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1101 pf->stat_offsets_loaded,
1102 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1103
41c445ff
JB		 1104 pf->stat_offsets_loaded = true;
1105}
1106
7812fddc
SN		 1107/**
1108 * i40e_update_stats - Update the various statistics counters.
1109 * @vsi: the VSI to be updated
1110 *
1111 * Update the various stats for this VSI and its related entities.
1112 **/
1113void i40e_update_stats(struct i40e_vsi *vsi)
1114{
1115 struct i40e_pf *pf = vsi->back;
1116
1117 if (vsi == pf->vsi[pf->lan_vsi])
1118 i40e_update_pf_stats(pf);
1119
1120 i40e_update_vsi_stats(vsi);
38e00438
VD		 1121#ifdef I40E_FCOE
1122 i40e_update_fcoe_stats(vsi);
1123#endif
7812fddc
SN		 1124}
1125
41c445ff
JB		 1126/**
1127 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1128 * @vsi: the VSI to be searched
1129 * @macaddr: the MAC address
1130 * @vlan: the vlan
1131 * @is_vf: make sure its a vf filter, else doesn't matter
1132 * @is_netdev: make sure its a netdev filter, else doesn't matter
1133 *
1134 * Returns ptr to the filter object or NULL
1135 **/
1136static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1137 u8 *macaddr, s16 vlan,
1138 bool is_vf, bool is_netdev)
1139{
1140 struct i40e_mac_filter *f;
1141
1142 if (!vsi || !macaddr)
1143 return NULL;
1144
1145 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1146 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1147 (vlan == f->vlan) &&
1148 (!is_vf || f->is_vf) &&
1149 (!is_netdev || f->is_netdev))
1150 return f;
1151 }
1152 return NULL;
1153}
1154
1155/**
1156 * i40e_find_mac - Find a mac addr in the macvlan filters list
1157 * @vsi: the VSI to be searched
1158 * @macaddr: the MAC address we are searching for
1159 * @is_vf: make sure its a vf filter, else doesn't matter
1160 * @is_netdev: make sure its a netdev filter, else doesn't matter
1161 *
1162 * Returns the first filter with the provided MAC address or NULL if
1163 * MAC address was not found
1164 **/
1165struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1166 bool is_vf, bool is_netdev)
1167{
1168 struct i40e_mac_filter *f;
1169
1170 if (!vsi || !macaddr)
1171 return NULL;
1172
1173 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1174 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1175 (!is_vf || f->is_vf) &&
1176 (!is_netdev || f->is_netdev))
1177 return f;
1178 }
1179 return NULL;
1180}
1181
1182/**
1183 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1184 * @vsi: the VSI to be searched
1185 *
1186 * Returns true if VSI is in vlan mode or false otherwise
1187 **/
1188bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1189{
1190 struct i40e_mac_filter *f;
1191
1192 /* Only -1 for all the filters denotes not in vlan mode
1193 * so we have to go through all the list in order to make sure
1194 */
1195 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1196 if (f->vlan >= 0)
1197 return true;
1198 }
1199
1200 return false;
1201}
1202
1203/**
1204 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1205 * @vsi: the VSI to be searched
1206 * @macaddr: the mac address to be filtered
1207 * @is_vf: true if it is a vf
1208 * @is_netdev: true if it is a netdev
1209 *
1210 * Goes through all the macvlan filters and adds a
1211 * macvlan filter for each unique vlan that already exists
1212 *
1213 * Returns first filter found on success, else NULL
1214 **/
1215struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1216 bool is_vf, bool is_netdev)
1217{
1218 struct i40e_mac_filter *f;
1219
1220 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1221 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1222 is_vf, is_netdev)) {
1223 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1224 is_vf, is_netdev))
41c445ff
JB		 1225 return NULL;
1226 }
1227 }
1228
1229 return list_first_entry_or_null(&vsi->mac_filter_list,
1230 struct i40e_mac_filter, list);
1231}
1232
8c27d42e
GR		 1233/**
1234 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1235 * @vsi: the PF Main VSI - inappropriate for any other VSI
1236 * @macaddr: the MAC address
30650cc5
SN		 1237 *
1238 * Some older firmware configurations set up a default promiscuous VLAN
1239 * filter that needs to be removed.
8c27d42e 1240 **/
30650cc5 1241static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1242{
1243 struct i40e_aqc_remove_macvlan_element_data element;
1244 struct i40e_pf *pf = vsi->back;
1245 i40e_status aq_ret;
1246
1247 /* Only appropriate for the PF main VSI */
1248 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1249 return -EINVAL;
8c27d42e 1250
30650cc5 1251 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1252 ether_addr_copy(element.mac_addr, macaddr);
1253 element.vlan_tag = 0;
1254 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1255 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1256 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1257 if (aq_ret)
30650cc5
SN		 1258 return -ENOENT;
1259
1260 return 0;
8c27d42e
GR		 1261}
1262
41c445ff
JB		 1263/**
1264 * i40e_add_filter - Add a mac/vlan filter to the VSI
1265 * @vsi: the VSI to be searched
1266 * @macaddr: the MAC address
1267 * @vlan: the vlan
1268 * @is_vf: make sure its a vf filter, else doesn't matter
1269 * @is_netdev: make sure its a netdev filter, else doesn't matter
1270 *
1271 * Returns ptr to the filter object or NULL when no memory available.
1272 **/
1273struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1274 u8 *macaddr, s16 vlan,
1275 bool is_vf, bool is_netdev)
1276{
1277 struct i40e_mac_filter *f;
1278
1279 if (!vsi || !macaddr)
1280 return NULL;
1281
1282 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1283 if (!f) {
1284 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1285 if (!f)
1286 goto add_filter_out;
1287
9a173901 1288 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1289 f->vlan = vlan;
1290 f->changed = true;
1291
1292 INIT_LIST_HEAD(&f->list);
1293 list_add(&f->list, &vsi->mac_filter_list);
1294 }
1295
1296 /* increment counter and add a new flag if needed */
1297 if (is_vf) {
1298 if (!f->is_vf) {
1299 f->is_vf = true;
1300 f->counter++;
1301 }
1302 } else if (is_netdev) {
1303 if (!f->is_netdev) {
1304 f->is_netdev = true;
1305 f->counter++;
1306 }
1307 } else {
1308 f->counter++;
1309 }
1310
1311 /* changed tells sync_filters_subtask to
1312 * push the filter down to the firmware
1313 */
1314 if (f->changed) {
1315 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1316 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1317 }
1318
1319add_filter_out:
1320 return f;
1321}
1322
1323/**
1324 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1325 * @vsi: the VSI to be searched
1326 * @macaddr: the MAC address
1327 * @vlan: the vlan
1328 * @is_vf: make sure it's a vf filter, else doesn't matter
1329 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1330 **/
1331void i40e_del_filter(struct i40e_vsi *vsi,
1332 u8 *macaddr, s16 vlan,
1333 bool is_vf, bool is_netdev)
1334{
1335 struct i40e_mac_filter *f;
1336
1337 if (!vsi || !macaddr)
1338 return;
1339
1340 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1341 if (!f || f->counter == 0)
1342 return;
1343
1344 if (is_vf) {
1345 if (f->is_vf) {
1346 f->is_vf = false;
1347 f->counter--;
1348 }
1349 } else if (is_netdev) {
1350 if (f->is_netdev) {
1351 f->is_netdev = false;
1352 f->counter--;
1353 }
1354 } else {
1355 /* make sure we don't remove a filter in use by vf or netdev */
1356 int min_f = 0;
1357 min_f += (f->is_vf ? 1 : 0);
1358 min_f += (f->is_netdev ? 1 : 0);
1359
1360 if (f->counter > min_f)
1361 f->counter--;
1362 }
1363
1364 /* counter == 0 tells sync_filters_subtask to
1365 * remove the filter from the firmware's list
1366 */
1367 if (f->counter == 0) {
1368 f->changed = true;
1369 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1370 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1371 }
1372}
1373
1374/**
1375 * i40e_set_mac - NDO callback to set mac address
1376 * @netdev: network interface device structure
1377 * @p: pointer to an address structure
1378 *
1379 * Returns 0 on success, negative on failure
1380 **/
38e00438
VD		 1381#ifdef I40E_FCOE
1382int i40e_set_mac(struct net_device *netdev, void *p)
1383#else
41c445ff 1384static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1385#endif
41c445ff
JB		 1386{
1387 struct i40e_netdev_priv *np = netdev_priv(netdev);
1388 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1389 struct i40e_pf *pf = vsi->back;
1390 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1391 struct sockaddr *addr = p;
1392 struct i40e_mac_filter *f;
1393
1394 if (!is_valid_ether_addr(addr->sa_data))
1395 return -EADDRNOTAVAIL;
1396
30650cc5
SN		 1397 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1398 netdev_info(netdev, "already using mac address %pM\n",
1399 addr->sa_data);
1400 return 0;
1401 }
41c445ff 1402
80f6428f
ASJ		 1403 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1404 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1405 return -EADDRNOTAVAIL;
1406
30650cc5
SN		 1407 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1408 netdev_info(netdev, "returning to hw mac address %pM\n",
1409 hw->mac.addr);
1410 else
1411 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1412
41c445ff
JB		 1413 if (vsi->type == I40E_VSI_MAIN) {
1414 i40e_status ret;
1415 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1416 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1417 addr->sa_data, NULL);
1418 if (ret) {
1419 netdev_info(netdev,
1420 "Addr change for Main VSI failed: %d\n",
1421 ret);
1422 return -EADDRNOTAVAIL;
1423 }
41c445ff
JB		 1424 }
1425
30650cc5
SN		 1426 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1427 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1428
30650cc5
SN		 1429 memset(&element, 0, sizeof(element));
1430 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1431 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1432 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1433 } else {
6c8ad1ba
SN		 1434 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1435 false, false);
6c8ad1ba 1436 }
41c445ff 1437
30650cc5
SN		 1438 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1439 struct i40e_aqc_add_macvlan_element_data element;
1440
1441 memset(&element, 0, sizeof(element));
1442 ether_addr_copy(element.mac_addr, hw->mac.addr);
1443 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1444 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1445 } else {
1446 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1447 false, false);
1448 if (f)
1449 f->is_laa = true;
1450 }
1451
1452 i40e_sync_vsi_filters(vsi);
1453 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1454
1455 return 0;
1456}
1457
1458/**
1459 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1460 * @vsi: the VSI being setup
1461 * @ctxt: VSI context structure
1462 * @enabled_tc: Enabled TCs bitmap
1463 * @is_add: True if called before Add VSI
1464 *
1465 * Setup VSI queue mapping for enabled traffic classes.
1466 **/
38e00438
VD		 1467#ifdef I40E_FCOE
1468void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1469 struct i40e_vsi_context *ctxt,
1470 u8 enabled_tc,
1471 bool is_add)
1472#else
41c445ff
JB		 1473static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1474 struct i40e_vsi_context *ctxt,
1475 u8 enabled_tc,
1476 bool is_add)
38e00438 1477#endif
41c445ff
JB		 1478{
1479 struct i40e_pf *pf = vsi->back;
1480 u16 sections = 0;
1481 u8 netdev_tc = 0;
1482 u16 numtc = 0;
1483 u16 qcount;
1484 u8 offset;
1485 u16 qmap;
1486 int i;
4e3b35b0 1487 u16 num_tc_qps = 0;
41c445ff
JB		 1488
1489 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1490 offset = 0;
1491
1492 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1493 /* Find numtc from enabled TC bitmap */
1494 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1495 if (enabled_tc & (1 << i)) /* TC is enabled */
1496 numtc++;
1497 }
1498 if (!numtc) {
1499 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1500 numtc = 1;
1501 }
1502 } else {
1503 /* At least TC0 is enabled in case of non-DCB case */
1504 numtc = 1;
1505 }
1506
1507 vsi->tc_config.numtc = numtc;
1508 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1509 /* Number of queues per enabled TC */
7f9ff476
AS		 1510 /* In MFP case we can have a much lower count of MSIx
1511 * vectors available and so we need to lower the used
1512 * q count.
1513 */
1514 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1515 num_tc_qps = qcount / numtc;
4e3b35b0 1516 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1517
1518 /* Setup queue offset/count for all TCs for given VSI */
1519 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1520 /* See if the given TC is enabled for the given VSI */
1521 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1522 int pow, num_qps;
1523
41c445ff
JB		 1524 switch (vsi->type) {
1525 case I40E_VSI_MAIN:
4e3b35b0 1526 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1527 break;
38e00438
VD		 1528#ifdef I40E_FCOE
1529 case I40E_VSI_FCOE:
1530 qcount = num_tc_qps;
1531 break;
1532#endif
41c445ff
JB		 1533 case I40E_VSI_FDIR:
1534 case I40E_VSI_SRIOV:
1535 case I40E_VSI_VMDQ2:
1536 default:
4e3b35b0 1537 qcount = num_tc_qps;
41c445ff
JB		 1538 WARN_ON(i != 0);
1539 break;
1540 }
4e3b35b0
NP		 1541 vsi->tc_config.tc_info[i].qoffset = offset;
1542 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1543
1544 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1545 num_qps = qcount;
41c445ff 1546 pow = 0;
4e3b35b0 1547 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1548 pow++;
1549 num_qps >>= 1;
1550 }
1551
1552 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1553 qmap =
1554 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1555 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1556
4e3b35b0 1557 offset += qcount;
41c445ff
JB		 1558 } else {
1559 /* TC is not enabled so set the offset to
1560 * default queue and allocate one queue
1561 * for the given TC.
1562 */
1563 vsi->tc_config.tc_info[i].qoffset = 0;
1564 vsi->tc_config.tc_info[i].qcount = 1;
1565 vsi->tc_config.tc_info[i].netdev_tc = 0;
1566
1567 qmap = 0;
1568 }
1569 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1570 }
1571
1572 /* Set actual Tx/Rx queue pairs */
1573 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1574 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1575 if (vsi->req_queue_pairs > 0)
1576 vsi->num_queue_pairs = vsi->req_queue_pairs;
1577 else
1578 vsi->num_queue_pairs = pf->num_lan_msix;
1579 }
41c445ff
JB		 1580
1581 /* Scheduler section valid can only be set for ADD VSI */
1582 if (is_add) {
1583 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1584
1585 ctxt->info.up_enable_bits = enabled_tc;
1586 }
1587 if (vsi->type == I40E_VSI_SRIOV) {
1588 ctxt->info.mapping_flags |=
1589 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1590 for (i = 0; i < vsi->num_queue_pairs; i++)
1591 ctxt->info.queue_mapping[i] =
1592 cpu_to_le16(vsi->base_queue + i);
1593 } else {
1594 ctxt->info.mapping_flags |=
1595 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1596 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1597 }
1598 ctxt->info.valid_sections |= cpu_to_le16(sections);
1599}
1600
1601/**
1602 * i40e_set_rx_mode - NDO callback to set the netdev filters
1603 * @netdev: network interface device structure
1604 **/
38e00438
VD		 1605#ifdef I40E_FCOE
1606void i40e_set_rx_mode(struct net_device *netdev)
1607#else
41c445ff 1608static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1609#endif
41c445ff
JB		 1610{
1611 struct i40e_netdev_priv *np = netdev_priv(netdev);
1612 struct i40e_mac_filter *f, *ftmp;
1613 struct i40e_vsi *vsi = np->vsi;
1614 struct netdev_hw_addr *uca;
1615 struct netdev_hw_addr *mca;
1616 struct netdev_hw_addr *ha;
1617
1618 /* add addr if not already in the filter list */
1619 netdev_for_each_uc_addr(uca, netdev) {
1620 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1621 if (i40e_is_vsi_in_vlan(vsi))
1622 i40e_put_mac_in_vlan(vsi, uca->addr,
1623 false, true);
1624 else
1625 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1626 false, true);
1627 }
1628 }
1629
1630 netdev_for_each_mc_addr(mca, netdev) {
1631 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1632 if (i40e_is_vsi_in_vlan(vsi))
1633 i40e_put_mac_in_vlan(vsi, mca->addr,
1634 false, true);
1635 else
1636 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1637 false, true);
1638 }
1639 }
1640
1641 /* remove filter if not in netdev list */
1642 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1643 bool found = false;
1644
1645 if (!f->is_netdev)
1646 continue;
1647
1648 if (is_multicast_ether_addr(f->macaddr)) {
1649 netdev_for_each_mc_addr(mca, netdev) {
1650 if (ether_addr_equal(mca->addr, f->macaddr)) {
1651 found = true;
1652 break;
1653 }
1654 }
1655 } else {
1656 netdev_for_each_uc_addr(uca, netdev) {
1657 if (ether_addr_equal(uca->addr, f->macaddr)) {
1658 found = true;
1659 break;
1660 }
1661 }
1662
1663 for_each_dev_addr(netdev, ha) {
1664 if (ether_addr_equal(ha->addr, f->macaddr)) {
1665 found = true;
1666 break;
1667 }
1668 }
1669 }
1670 if (!found)
1671 i40e_del_filter(
1672 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1673 }
1674
1675 /* check for other flag changes */
1676 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1677 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1678 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1679 }
1680}
1681
1682/**
1683 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1684 * @vsi: ptr to the VSI
1685 *
1686 * Push any outstanding VSI filter changes through the AdminQ.
1687 *
1688 * Returns 0 or error value
1689 **/
1690int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1691{
1692 struct i40e_mac_filter *f, *ftmp;
1693 bool promisc_forced_on = false;
1694 bool add_happened = false;
1695 int filter_list_len = 0;
1696 u32 changed_flags = 0;
dcae29be 1697 i40e_status aq_ret = 0;
41c445ff
JB		 1698 struct i40e_pf *pf;
1699 int num_add = 0;
1700 int num_del = 0;
1701 u16 cmd_flags;
1702
1703 /* empty array typed pointers, kcalloc later */
1704 struct i40e_aqc_add_macvlan_element_data *add_list;
1705 struct i40e_aqc_remove_macvlan_element_data *del_list;
1706
1707 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1708 usleep_range(1000, 2000);
1709 pf = vsi->back;
1710
1711 if (vsi->netdev) {
1712 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1713 vsi->current_netdev_flags = vsi->netdev->flags;
1714 }
1715
1716 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1717 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1718
1719 filter_list_len = pf->hw.aq.asq_buf_size /
1720 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1721 del_list = kcalloc(filter_list_len,
1722 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1723 GFP_KERNEL);
1724 if (!del_list)
1725 return -ENOMEM;
1726
1727 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1728 if (!f->changed)
1729 continue;
1730
1731 if (f->counter != 0)
1732 continue;
1733 f->changed = false;
1734 cmd_flags = 0;
1735
1736 /* add to delete list */
9a173901 1737 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1738 del_list[num_del].vlan_tag =
1739 cpu_to_le16((u16)(f->vlan ==
1740 I40E_VLAN_ANY ? 0 : f->vlan));
1741
41c445ff
JB		 1742 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1743 del_list[num_del].flags = cmd_flags;
1744 num_del++;
1745
1746 /* unlink from filter list */
1747 list_del(&f->list);
1748 kfree(f);
1749
1750 /* flush a full buffer */
1751 if (num_del == filter_list_len) {
dcae29be 1752 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1753 vsi->seid, del_list, num_del,
1754 NULL);
1755 num_del = 0;
1756 memset(del_list, 0, sizeof(*del_list));
1757
fdfe9cbe
SN		 1758 if (aq_ret &&
1759 pf->hw.aq.asq_last_status !=
1760 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1761 dev_info(&pf->pdev->dev,
1762 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1763 aq_ret,
41c445ff
JB		 1764 pf->hw.aq.asq_last_status);
1765 }
1766 }
1767 if (num_del) {
dcae29be 1768 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1769 del_list, num_del, NULL);
1770 num_del = 0;
1771
fdfe9cbe
SN		 1772 if (aq_ret &&
1773 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1774 dev_info(&pf->pdev->dev,
1775 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1776 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1777 }
1778
1779 kfree(del_list);
1780 del_list = NULL;
1781
1782 /* do all the adds now */
1783 filter_list_len = pf->hw.aq.asq_buf_size /
1784 sizeof(struct i40e_aqc_add_macvlan_element_data),
1785 add_list = kcalloc(filter_list_len,
1786 sizeof(struct i40e_aqc_add_macvlan_element_data),
1787 GFP_KERNEL);
1788 if (!add_list)
1789 return -ENOMEM;
1790
1791 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1792 if (!f->changed)
1793 continue;
1794
1795 if (f->counter == 0)
1796 continue;
1797 f->changed = false;
1798 add_happened = true;
1799 cmd_flags = 0;
1800
1801 /* add to add array */
9a173901 1802 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1803 add_list[num_add].vlan_tag =
1804 cpu_to_le16(
1805 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1806 add_list[num_add].queue_number = 0;
1807
1808 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1809 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1810 num_add++;
1811
1812 /* flush a full buffer */
1813 if (num_add == filter_list_len) {
dcae29be
JB		 1814 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1815 add_list, num_add,
1816 NULL);
41c445ff
JB		 1817 num_add = 0;
1818
dcae29be 1819 if (aq_ret)
41c445ff
JB		 1820 break;
1821 memset(add_list, 0, sizeof(*add_list));
1822 }
1823 }
1824 if (num_add) {
dcae29be
JB		 1825 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1826 add_list, num_add, NULL);
41c445ff
JB		 1827 num_add = 0;
1828 }
1829 kfree(add_list);
1830 add_list = NULL;
1831
30650cc5
SN		 1832 if (add_happened && aq_ret &&
1833 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1834 dev_info(&pf->pdev->dev,
1835 "add filter failed, err %d, aq_err %d\n",
dcae29be 1836 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1837 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1838 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1839 &vsi->state)) {
1840 promisc_forced_on = true;
1841 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1842 &vsi->state);
1843 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1844 }
1845 }
1846 }
1847
1848 /* check for changes in promiscuous modes */
1849 if (changed_flags & IFF_ALLMULTI) {
1850 bool cur_multipromisc;
1851 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1852 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1853 vsi->seid,
1854 cur_multipromisc,
1855 NULL);
1856 if (aq_ret)
41c445ff
JB		 1857 dev_info(&pf->pdev->dev,
1858 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1859 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1860 }
1861 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1862 bool cur_promisc;
1863 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1864 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1865 &vsi->state));
dcae29be
JB		 1866 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1867 vsi->seid,
1868 cur_promisc, NULL);
1869 if (aq_ret)
41c445ff
JB		 1870 dev_info(&pf->pdev->dev,
1871 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1872 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1873 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1874 vsi->seid,
1875 cur_promisc, NULL);
1876 if (aq_ret)
1877 dev_info(&pf->pdev->dev,
1878 "set brdcast promisc failed, err %d, aq_err %d\n",
1879 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1880 }
1881
1882 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1883 return 0;
1884}
1885
1886/**
1887 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1888 * @pf: board private structure
1889 **/
1890static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1891{
1892 int v;
1893
1894 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1895 return;
1896 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1897
505682cd 1898 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1899 if (pf->vsi[v] &&
1900 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1901 i40e_sync_vsi_filters(pf->vsi[v]);
1902 }
1903}
1904
1905/**
1906 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1907 * @netdev: network interface device structure
1908 * @new_mtu: new value for maximum frame size
1909 *
1910 * Returns 0 on success, negative on failure
1911 **/
1912static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1913{
1914 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1915 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1916 struct i40e_vsi *vsi = np->vsi;
1917
1918 /* MTU < 68 is an error and causes problems on some kernels */
1919 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1920 return -EINVAL;
1921
1922 netdev_info(netdev, "changing MTU from %d to %d\n",
1923 netdev->mtu, new_mtu);
1924 netdev->mtu = new_mtu;
1925 if (netif_running(netdev))
1926 i40e_vsi_reinit_locked(vsi);
1927
1928 return 0;
1929}
1930
beb0dff1
JK		 1931/**
1932 * i40e_ioctl - Access the hwtstamp interface
1933 * @netdev: network interface device structure
1934 * @ifr: interface request data
1935 * @cmd: ioctl command
1936 **/
1937int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1938{
1939 struct i40e_netdev_priv *np = netdev_priv(netdev);
1940 struct i40e_pf *pf = np->vsi->back;
1941
1942 switch (cmd) {
1943 case SIOCGHWTSTAMP:
1944 return i40e_ptp_get_ts_config(pf, ifr);
1945 case SIOCSHWTSTAMP:
1946 return i40e_ptp_set_ts_config(pf, ifr);
1947 default:
1948 return -EOPNOTSUPP;
1949 }
1950}
1951
41c445ff
JB		 1952/**
1953 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1954 * @vsi: the vsi being adjusted
1955 **/
1956void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1957{
1958 struct i40e_vsi_context ctxt;
1959 i40e_status ret;
1960
1961 if ((vsi->info.valid_sections &
1962 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1963 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1964 return; /* already enabled */
1965
1966 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1967 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1968 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1969
1970 ctxt.seid = vsi->seid;
1971 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1972 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1973 if (ret) {
1974 dev_info(&vsi->back->pdev->dev,
1975 "%s: update vsi failed, aq_err=%d\n",
1976 __func__, vsi->back->hw.aq.asq_last_status);
1977 }
1978}
1979
1980/**
1981 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1982 * @vsi: the vsi being adjusted
1983 **/
1984void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1985{
1986 struct i40e_vsi_context ctxt;
1987 i40e_status ret;
1988
1989 if ((vsi->info.valid_sections &
1990 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1991 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1992 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1993 return; /* already disabled */
1994
1995 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1996 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1997 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1998
1999 ctxt.seid = vsi->seid;
2000 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2001 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2002 if (ret) {
2003 dev_info(&vsi->back->pdev->dev,
2004 "%s: update vsi failed, aq_err=%d\n",
2005 __func__, vsi->back->hw.aq.asq_last_status);
2006 }
2007}
2008
2009/**
2010 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2011 * @netdev: network interface to be adjusted
2012 * @features: netdev features to test if VLAN offload is enabled or not
2013 **/
2014static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2015{
2016 struct i40e_netdev_priv *np = netdev_priv(netdev);
2017 struct i40e_vsi *vsi = np->vsi;
2018
2019 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2020 i40e_vlan_stripping_enable(vsi);
2021 else
2022 i40e_vlan_stripping_disable(vsi);
2023}
2024
2025/**
2026 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2027 * @vsi: the vsi being configured
2028 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2029 **/
2030int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2031{
2032 struct i40e_mac_filter *f, *add_f;
2033 bool is_netdev, is_vf;
41c445ff
JB		 2034
2035 is_vf = (vsi->type == I40E_VSI_SRIOV);
2036 is_netdev = !!(vsi->netdev);
2037
2038 if (is_netdev) {
2039 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2040 is_vf, is_netdev);
2041 if (!add_f) {
2042 dev_info(&vsi->back->pdev->dev,
2043 "Could not add vlan filter %d for %pM\n",
2044 vid, vsi->netdev->dev_addr);
2045 return -ENOMEM;
2046 }
2047 }
2048
2049 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2050 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2051 if (!add_f) {
2052 dev_info(&vsi->back->pdev->dev,
2053 "Could not add vlan filter %d for %pM\n",
2054 vid, f->macaddr);
2055 return -ENOMEM;
2056 }
2057 }
2058
41c445ff
JB		 2059 /* Now if we add a vlan tag, make sure to check if it is the first
2060 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2061 * with 0, so we now accept untagged and specified tagged traffic
2062 * (and not any taged and untagged)
2063 */
2064 if (vid > 0) {
2065 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2066 I40E_VLAN_ANY,
2067 is_vf, is_netdev)) {
2068 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2069 I40E_VLAN_ANY, is_vf, is_netdev);
2070 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2071 is_vf, is_netdev);
2072 if (!add_f) {
2073 dev_info(&vsi->back->pdev->dev,
2074 "Could not add filter 0 for %pM\n",
2075 vsi->netdev->dev_addr);
2076 return -ENOMEM;
2077 }
2078 }
8d82a7c5 2079 }
41c445ff 2080
8d82a7c5
GR		 2081 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2082 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2083 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2084 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2085 is_vf, is_netdev)) {
2086 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2087 is_vf, is_netdev);
2088 add_f = i40e_add_filter(vsi, f->macaddr,
2089 0, is_vf, is_netdev);
2090 if (!add_f) {
2091 dev_info(&vsi->back->pdev->dev,
2092 "Could not add filter 0 for %pM\n",
2093 f->macaddr);
2094 return -ENOMEM;
2095 }
2096 }
2097 }
41c445ff
JB		 2098 }
2099
80f6428f
ASJ		 2100 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2101 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2102 return 0;
2103
2104 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2105}
2106
2107/**
2108 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2109 * @vsi: the vsi being configured
2110 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2111 *
2112 * Return: 0 on success or negative otherwise
41c445ff
JB		 2113 **/
2114int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2115{
2116 struct net_device *netdev = vsi->netdev;
2117 struct i40e_mac_filter *f, *add_f;
2118 bool is_vf, is_netdev;
2119 int filter_count = 0;
41c445ff
JB		 2120
2121 is_vf = (vsi->type == I40E_VSI_SRIOV);
2122 is_netdev = !!(netdev);
2123
2124 if (is_netdev)
2125 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2126
2127 list_for_each_entry(f, &vsi->mac_filter_list, list)
2128 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2129
41c445ff
JB		 2130 /* go through all the filters for this VSI and if there is only
2131 * vid == 0 it means there are no other filters, so vid 0 must
2132 * be replaced with -1. This signifies that we should from now
2133 * on accept any traffic (with any tag present, or untagged)
2134 */
2135 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2136 if (is_netdev) {
2137 if (f->vlan &&
2138 ether_addr_equal(netdev->dev_addr, f->macaddr))
2139 filter_count++;
2140 }
2141
2142 if (f->vlan)
2143 filter_count++;
2144 }
2145
2146 if (!filter_count && is_netdev) {
2147 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2148 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2149 is_vf, is_netdev);
2150 if (!f) {
2151 dev_info(&vsi->back->pdev->dev,
2152 "Could not add filter %d for %pM\n",
2153 I40E_VLAN_ANY, netdev->dev_addr);
2154 return -ENOMEM;
2155 }
2156 }
2157
2158 if (!filter_count) {
2159 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2160 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2161 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2162 is_vf, is_netdev);
2163 if (!add_f) {
2164 dev_info(&vsi->back->pdev->dev,
2165 "Could not add filter %d for %pM\n",
2166 I40E_VLAN_ANY, f->macaddr);
2167 return -ENOMEM;
2168 }
2169 }
2170 }
2171
80f6428f
ASJ		 2172 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2173 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2174 return 0;
2175
41c445ff
JB		 2176 return i40e_sync_vsi_filters(vsi);
2177}
2178
2179/**
2180 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2181 * @netdev: network interface to be adjusted
2182 * @vid: vlan id to be added
078b5876
JB		 2183 *
2184 * net_device_ops implementation for adding vlan ids
41c445ff 2185 **/
38e00438
VD		 2186#ifdef I40E_FCOE
2187int i40e_vlan_rx_add_vid(struct net_device *netdev,
2188 __always_unused __be16 proto, u16 vid)
2189#else
41c445ff
JB		 2190static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2191 __always_unused __be16 proto, u16 vid)
38e00438 2192#endif
41c445ff
JB		 2193{
2194 struct i40e_netdev_priv *np = netdev_priv(netdev);
2195 struct i40e_vsi *vsi = np->vsi;
078b5876 2196 int ret = 0;
41c445ff
JB		 2197
2198 if (vid > 4095)
078b5876
JB		 2199 return -EINVAL;
2200
2201 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2202
6982d429
ASJ		 2203 /* If the network stack called us with vid = 0 then
2204 * it is asking to receive priority tagged packets with
2205 * vlan id 0. Our HW receives them by default when configured
2206 * to receive untagged packets so there is no need to add an
2207 * extra filter for vlan 0 tagged packets.
41c445ff 2208 */
6982d429
ASJ		 2209 if (vid)
2210 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2211
078b5876
JB		 2212 if (!ret && (vid < VLAN_N_VID))
2213 set_bit(vid, vsi->active_vlans);
41c445ff 2214
078b5876 2215 return ret;
41c445ff
JB		 2216}
2217
2218/**
2219 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2220 * @netdev: network interface to be adjusted
2221 * @vid: vlan id to be removed
078b5876 2222 *
fdfd943e 2223 * net_device_ops implementation for removing vlan ids
41c445ff 2224 **/
38e00438
VD		 2225#ifdef I40E_FCOE
2226int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2227 __always_unused __be16 proto, u16 vid)
2228#else
41c445ff
JB		 2229static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2230 __always_unused __be16 proto, u16 vid)
38e00438 2231#endif
41c445ff
JB		 2232{
2233 struct i40e_netdev_priv *np = netdev_priv(netdev);
2234 struct i40e_vsi *vsi = np->vsi;
2235
078b5876
JB		 2236 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2237
41c445ff
JB		 2238 /* return code is ignored as there is nothing a user
2239 * can do about failure to remove and a log message was
078b5876 2240 * already printed from the other function
41c445ff
JB		 2241 */
2242 i40e_vsi_kill_vlan(vsi, vid);
2243
2244 clear_bit(vid, vsi->active_vlans);
078b5876 2245
41c445ff
JB		 2246 return 0;
2247}
2248
2249/**
2250 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2251 * @vsi: the vsi being brought back up
2252 **/
2253static void i40e_restore_vlan(struct i40e_vsi *vsi)
2254{
2255 u16 vid;
2256
2257 if (!vsi->netdev)
2258 return;
2259
2260 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2261
2262 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2263 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2264 vid);
2265}
2266
2267/**
2268 * i40e_vsi_add_pvid - Add pvid for the VSI
2269 * @vsi: the vsi being adjusted
2270 * @vid: the vlan id to set as a PVID
2271 **/
dcae29be 2272int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2273{
2274 struct i40e_vsi_context ctxt;
dcae29be 2275 i40e_status aq_ret;
41c445ff
JB		 2276
2277 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2278 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2279 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2280 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2281 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2282
2283 ctxt.seid = vsi->seid;
2284 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2285 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2286 if (aq_ret) {
41c445ff
JB		 2287 dev_info(&vsi->back->pdev->dev,
2288 "%s: update vsi failed, aq_err=%d\n",
2289 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2290 return -ENOENT;
41c445ff
JB		 2291 }
2292
dcae29be 2293 return 0;
41c445ff
JB		 2294}
2295
2296/**
2297 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2298 * @vsi: the vsi being adjusted
2299 *
2300 * Just use the vlan_rx_register() service to put it back to normal
2301 **/
2302void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2303{
6c12fcbf
GR		 2304 i40e_vlan_stripping_disable(vsi);
2305
41c445ff 2306 vsi->info.pvid = 0;
41c445ff
JB		 2307}
2308
2309/**
2310 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2311 * @vsi: ptr to the VSI
2312 *
2313 * If this function returns with an error, then it's possible one or
2314 * more of the rings is populated (while the rest are not). It is the
2315 * callers duty to clean those orphaned rings.
2316 *
2317 * Return 0 on success, negative on failure
2318 **/
2319static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2320{
2321 int i, err = 0;
2322
2323 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2324 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2325
2326 return err;
2327}
2328
2329/**
2330 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2331 * @vsi: ptr to the VSI
2332 *
2333 * Free VSI's transmit software resources
2334 **/
2335static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2336{
2337 int i;
2338
8e9dca53
GR		 2339 if (!vsi->tx_rings)
2340 return;
2341
41c445ff 2342 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2343 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2344 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2345}
2346
2347/**
2348 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2349 * @vsi: ptr to the VSI
2350 *
2351 * If this function returns with an error, then it's possible one or
2352 * more of the rings is populated (while the rest are not). It is the
2353 * callers duty to clean those orphaned rings.
2354 *
2355 * Return 0 on success, negative on failure
2356 **/
2357static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2358{
2359 int i, err = 0;
2360
2361 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2362 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2363#ifdef I40E_FCOE
2364 i40e_fcoe_setup_ddp_resources(vsi);
2365#endif
41c445ff
JB		 2366 return err;
2367}
2368
2369/**
2370 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2371 * @vsi: ptr to the VSI
2372 *
2373 * Free all receive software resources
2374 **/
2375static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2376{
2377 int i;
2378
8e9dca53
GR		 2379 if (!vsi->rx_rings)
2380 return;
2381
41c445ff 2382 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2383 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2384 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2385#ifdef I40E_FCOE
2386 i40e_fcoe_free_ddp_resources(vsi);
2387#endif
41c445ff
JB		 2388}
2389
3ffa037d
NP		 2390/**
2391 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2392 * @ring: The Tx ring to configure
2393 *
2394 * This enables/disables XPS for a given Tx descriptor ring
2395 * based on the TCs enabled for the VSI that ring belongs to.
2396 **/
2397static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2398{
2399 struct i40e_vsi *vsi = ring->vsi;
2400 cpumask_var_t mask;
2401
2402 if (ring->q_vector && ring->netdev) {
2403 /* Single TC mode enable XPS */
2404 if (vsi->tc_config.numtc <= 1 &&
2405 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state)) {
2406 netif_set_xps_queue(ring->netdev,
2407 &ring->q_vector->affinity_mask,
2408 ring->queue_index);
2409 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2410 /* Disable XPS to allow selection based on TC */
2411 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2412 netif_set_xps_queue(ring->netdev, mask,
2413 ring->queue_index);
2414 free_cpumask_var(mask);
2415 }
2416 }
2417}
2418
41c445ff
JB		 2419/**
2420 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2421 * @ring: The Tx ring to configure
2422 *
2423 * Configure the Tx descriptor ring in the HMC context.
2424 **/
2425static int i40e_configure_tx_ring(struct i40e_ring *ring)
2426{
2427 struct i40e_vsi *vsi = ring->vsi;
2428 u16 pf_q = vsi->base_queue + ring->queue_index;
2429 struct i40e_hw *hw = &vsi->back->hw;
2430 struct i40e_hmc_obj_txq tx_ctx;
2431 i40e_status err = 0;
2432 u32 qtx_ctl = 0;
2433
2434 /* some ATR related tx ring init */
60ea5f83 2435 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2436 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2437 ring->atr_count = 0;
2438 } else {
2439 ring->atr_sample_rate = 0;
2440 }
2441
3ffa037d
NP		 2442 /* configure XPS */
2443 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2444
2445 /* clear the context structure first */
2446 memset(&tx_ctx, 0, sizeof(tx_ctx));
2447
2448 tx_ctx.new_context = 1;
2449 tx_ctx.base = (ring->dma / 128);
2450 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2451 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2452 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2453#ifdef I40E_FCOE
2454 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2455#endif
beb0dff1 2456 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2457 /* FDIR VSI tx ring can still use RS bit and writebacks */
2458 if (vsi->type != I40E_VSI_FDIR)
2459 tx_ctx.head_wb_ena = 1;
2460 tx_ctx.head_wb_addr = ring->dma +
2461 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2462
2463 /* As part of VSI creation/update, FW allocates certain
2464 * Tx arbitration queue sets for each TC enabled for
2465 * the VSI. The FW returns the handles to these queue
2466 * sets as part of the response buffer to Add VSI,
2467 * Update VSI, etc. AQ commands. It is expected that
2468 * these queue set handles be associated with the Tx
2469 * queues by the driver as part of the TX queue context
2470 * initialization. This has to be done regardless of
2471 * DCB as by default everything is mapped to TC0.
2472 */
2473 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2474 tx_ctx.rdylist_act = 0;
2475
2476 /* clear the context in the HMC */
2477 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2478 if (err) {
2479 dev_info(&vsi->back->pdev->dev,
2480 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2481 ring->queue_index, pf_q, err);
2482 return -ENOMEM;
2483 }
2484
2485 /* set the context in the HMC */
2486 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2487 if (err) {
2488 dev_info(&vsi->back->pdev->dev,
2489 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2490 ring->queue_index, pf_q, err);
2491 return -ENOMEM;
2492 }
2493
2494 /* Now associate this queue with this PCI function */
7a28d885 2495 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2496 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2497 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2498 I40E_QTX_CTL_VFVM_INDX_MASK;
2499 } else {
9d8bf547 2500 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2501 }
2502
13fd9774
SN		 2503 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2504 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2505 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2506 i40e_flush(hw);
2507
2508 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2509
2510 /* cache tail off for easier writes later */
2511 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2512
2513 return 0;
2514}
2515
2516/**
2517 * i40e_configure_rx_ring - Configure a receive ring context
2518 * @ring: The Rx ring to configure
2519 *
2520 * Configure the Rx descriptor ring in the HMC context.
2521 **/
2522static int i40e_configure_rx_ring(struct i40e_ring *ring)
2523{
2524 struct i40e_vsi *vsi = ring->vsi;
2525 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2526 u16 pf_q = vsi->base_queue + ring->queue_index;
2527 struct i40e_hw *hw = &vsi->back->hw;
2528 struct i40e_hmc_obj_rxq rx_ctx;
2529 i40e_status err = 0;
2530
2531 ring->state = 0;
2532
2533 /* clear the context structure first */
2534 memset(&rx_ctx, 0, sizeof(rx_ctx));
2535
2536 ring->rx_buf_len = vsi->rx_buf_len;
2537 ring->rx_hdr_len = vsi->rx_hdr_len;
2538
2539 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2540 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2541
2542 rx_ctx.base = (ring->dma / 128);
2543 rx_ctx.qlen = ring->count;
2544
2545 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2546 set_ring_16byte_desc_enabled(ring);
2547 rx_ctx.dsize = 0;
2548 } else {
2549 rx_ctx.dsize = 1;
2550 }
2551
2552 rx_ctx.dtype = vsi->dtype;
2553 if (vsi->dtype) {
2554 set_ring_ps_enabled(ring);
2555 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2556 I40E_RX_SPLIT_IP |
2557 I40E_RX_SPLIT_TCP_UDP |
2558 I40E_RX_SPLIT_SCTP;
2559 } else {
2560 rx_ctx.hsplit_0 = 0;
2561 }
2562
2563 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2564 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2565 if (hw->revision_id == 0)
2566 rx_ctx.lrxqthresh = 0;
2567 else
2568 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2569 rx_ctx.crcstrip = 1;
2570 rx_ctx.l2tsel = 1;
2571 rx_ctx.showiv = 1;
38e00438
VD		 2572#ifdef I40E_FCOE
2573 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2574#endif
acb3676b
CS		 2575 /* set the prefena field to 1 because the manual says to */
2576 rx_ctx.prefena = 1;
41c445ff
JB		 2577
2578 /* clear the context in the HMC */
2579 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2580 if (err) {
2581 dev_info(&vsi->back->pdev->dev,
2582 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2583 ring->queue_index, pf_q, err);
2584 return -ENOMEM;
2585 }
2586
2587 /* set the context in the HMC */
2588 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2589 if (err) {
2590 dev_info(&vsi->back->pdev->dev,
2591 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2592 ring->queue_index, pf_q, err);
2593 return -ENOMEM;
2594 }
2595
2596 /* cache tail for quicker writes, and clear the reg before use */
2597 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2598 writel(0, ring->tail);
2599
a132af24
MW		 2600 if (ring_is_ps_enabled(ring)) {
2601 i40e_alloc_rx_headers(ring);
2602 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2603 } else {
2604 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2605 }
41c445ff
JB		 2606
2607 return 0;
2608}
2609
2610/**
2611 * i40e_vsi_configure_tx - Configure the VSI for Tx
2612 * @vsi: VSI structure describing this set of rings and resources
2613 *
2614 * Configure the Tx VSI for operation.
2615 **/
2616static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2617{
2618 int err = 0;
2619 u16 i;
2620
9f65e15b
AD		 2621 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2622 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2623
2624 return err;
2625}
2626
2627/**
2628 * i40e_vsi_configure_rx - Configure the VSI for Rx
2629 * @vsi: the VSI being configured
2630 *
2631 * Configure the Rx VSI for operation.
2632 **/
2633static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2634{
2635 int err = 0;
2636 u16 i;
2637
2638 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2639 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2640 + ETH_FCS_LEN + VLAN_HLEN;
2641 else
2642 vsi->max_frame = I40E_RXBUFFER_2048;
2643
2644 /* figure out correct receive buffer length */
2645 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2646 I40E_FLAG_RX_PS_ENABLED)) {
2647 case I40E_FLAG_RX_1BUF_ENABLED:
2648 vsi->rx_hdr_len = 0;
2649 vsi->rx_buf_len = vsi->max_frame;
2650 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2651 break;
2652 case I40E_FLAG_RX_PS_ENABLED:
2653 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2654 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2655 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2656 break;
2657 default:
2658 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2659 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2660 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2661 break;
2662 }
2663
38e00438
VD		 2664#ifdef I40E_FCOE
2665 /* setup rx buffer for FCoE */
2666 if ((vsi->type == I40E_VSI_FCOE) &&
2667 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2668 vsi->rx_hdr_len = 0;
2669 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2670 vsi->max_frame = I40E_RXBUFFER_3072;
2671 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2672 }
2673
2674#endif /* I40E_FCOE */
41c445ff
JB		 2675 /* round up for the chip's needs */
2676 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2677 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2678 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2679 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2680
2681 /* set up individual rings */
2682 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2683 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2684
2685 return err;
2686}
2687
2688/**
2689 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2690 * @vsi: ptr to the VSI
2691 **/
2692static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2693{
e7046ee1 2694 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2695 u16 qoffset, qcount;
2696 int i, n;
2697
cd238a3e
PN		 2698 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2699 /* Reset the TC information */
2700 for (i = 0; i < vsi->num_queue_pairs; i++) {
2701 rx_ring = vsi->rx_rings[i];
2702 tx_ring = vsi->tx_rings[i];
2703 rx_ring->dcb_tc = 0;
2704 tx_ring->dcb_tc = 0;
2705 }
2706 }
41c445ff
JB		 2707
2708 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2709 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2710 continue;
2711
2712 qoffset = vsi->tc_config.tc_info[n].qoffset;
2713 qcount = vsi->tc_config.tc_info[n].qcount;
2714 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2715 rx_ring = vsi->rx_rings[i];
2716 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2717 rx_ring->dcb_tc = n;
2718 tx_ring->dcb_tc = n;
2719 }
2720 }
2721}
2722
2723/**
2724 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2725 * @vsi: ptr to the VSI
2726 **/
2727static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2728{
2729 if (vsi->netdev)
2730 i40e_set_rx_mode(vsi->netdev);
2731}
2732
17a73f6b
JG		 2733/**
2734 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2735 * @vsi: Pointer to the targeted VSI
2736 *
2737 * This function replays the hlist on the hw where all the SB Flow Director
2738 * filters were saved.
2739 **/
2740static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2741{
2742 struct i40e_fdir_filter *filter;
2743 struct i40e_pf *pf = vsi->back;
2744 struct hlist_node *node;
2745
55a5e60b
ASJ		 2746 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2747 return;
2748
17a73f6b
JG		 2749 hlist_for_each_entry_safe(filter, node,
2750 &pf->fdir_filter_list, fdir_node) {
2751 i40e_add_del_fdir(vsi, filter, true);
2752 }
2753}
2754
41c445ff
JB		 2755/**
2756 * i40e_vsi_configure - Set up the VSI for action
2757 * @vsi: the VSI being configured
2758 **/
2759static int i40e_vsi_configure(struct i40e_vsi *vsi)
2760{
2761 int err;
2762
2763 i40e_set_vsi_rx_mode(vsi);
2764 i40e_restore_vlan(vsi);
2765 i40e_vsi_config_dcb_rings(vsi);
2766 err = i40e_vsi_configure_tx(vsi);
2767 if (!err)
2768 err = i40e_vsi_configure_rx(vsi);
2769
2770 return err;
2771}
2772
2773/**
2774 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2775 * @vsi: the VSI being configured
2776 **/
2777static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2778{
2779 struct i40e_pf *pf = vsi->back;
2780 struct i40e_q_vector *q_vector;
2781 struct i40e_hw *hw = &pf->hw;
2782 u16 vector;
2783 int i, q;
2784 u32 val;
2785 u32 qp;
2786
2787 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2788 * and PFINT_LNKLSTn registers, e.g.:
2789 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2790 */
2791 qp = vsi->base_queue;
2792 vector = vsi->base_vector;
493fb300
AD		 2793 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2794 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2795 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2796 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2797 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2798 q_vector->rx.itr);
2799 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2800 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2801 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2802 q_vector->tx.itr);
2803
2804 /* Linked list for the queuepairs assigned to this vector */
2805 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2806 for (q = 0; q < q_vector->num_ringpairs; q++) {
2807 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2808 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2809 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2810 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2811 (I40E_QUEUE_TYPE_TX
2812 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2813
2814 wr32(hw, I40E_QINT_RQCTL(qp), val);
2815
2816 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2817 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2818 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2819 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2820 (I40E_QUEUE_TYPE_RX
2821 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2822
2823 /* Terminate the linked list */
2824 if (q == (q_vector->num_ringpairs - 1))
2825 val |= (I40E_QUEUE_END_OF_LIST
2826 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2827
2828 wr32(hw, I40E_QINT_TQCTL(qp), val);
2829 qp++;
2830 }
2831 }
2832
2833 i40e_flush(hw);
2834}
2835
2836/**
2837 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2838 * @hw: ptr to the hardware info
2839 **/
ab437b5a 2840static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2841{
ab437b5a 2842 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2843 u32 val;
2844
2845 /* clear things first */
2846 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2847 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2848
2849 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2850 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2851 I40E_PFINT_ICR0_ENA_GRST_MASK |
2852 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2853 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2854 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2855 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2856 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2857
ab437b5a
JK		 2858 if (pf->flags & I40E_FLAG_PTP)
2859 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2860
41c445ff
JB		 2861 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2862
2863 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2864 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2865 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2866
2867 /* OTHER_ITR_IDX = 0 */
2868 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2869}
2870
2871/**
2872 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2873 * @vsi: the VSI being configured
2874 **/
2875static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2876{
493fb300 2877 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2878 struct i40e_pf *pf = vsi->back;
2879 struct i40e_hw *hw = &pf->hw;
2880 u32 val;
2881
2882 /* set the ITR configuration */
2883 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2884 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2885 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2886 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2887 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2888 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2889
ab437b5a 2890 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 2891
2892 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2893 wr32(hw, I40E_PFINT_LNKLST0, 0);
2894
f29eaa3d 2895 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2896 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2897 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2898 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2899
2900 wr32(hw, I40E_QINT_RQCTL(0), val);
2901
2902 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2903 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2904 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2905
2906 wr32(hw, I40E_QINT_TQCTL(0), val);
2907 i40e_flush(hw);
2908}
2909
2ef28cfb
MW		 2910/**
2911 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2912 * @pf: board private structure
2913 **/
2914void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2915{
2916 struct i40e_hw *hw = &pf->hw;
2917
2918 wr32(hw, I40E_PFINT_DYN_CTL0,
2919 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2920 i40e_flush(hw);
2921}
2922
41c445ff
JB		 2923/**
2924 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2925 * @pf: board private structure
2926 **/
116a57d4 2927void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2928{
2929 struct i40e_hw *hw = &pf->hw;
2930 u32 val;
2931
2932 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2933 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2934 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2935
2936 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2937 i40e_flush(hw);
2938}
2939
2940/**
2941 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2942 * @vsi: pointer to a vsi
2943 * @vector: enable a particular Hw Interrupt vector
2944 **/
2945void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2946{
2947 struct i40e_pf *pf = vsi->back;
2948 struct i40e_hw *hw = &pf->hw;
2949 u32 val;
2950
2951 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2952 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2953 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2954 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2955 /* skip the flush */
41c445ff
JB		 2956}
2957
5c2cebda
CW		 2958/**
2959 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2960 * @vsi: pointer to a vsi
03147773 2961 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 2962 **/
2963void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2964{
2965 struct i40e_pf *pf = vsi->back;
2966 struct i40e_hw *hw = &pf->hw;
2967 u32 val;
2968
2969 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2970 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2971 i40e_flush(hw);
2972}
2973
41c445ff
JB		 2974/**
2975 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2976 * @irq: interrupt number
2977 * @data: pointer to a q_vector
2978 **/
2979static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2980{
2981 struct i40e_q_vector *q_vector = data;
2982
cd0b6fa6 2983 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2984 return IRQ_HANDLED;
2985
2986 napi_schedule(&q_vector->napi);
2987
2988 return IRQ_HANDLED;
2989}
2990
41c445ff
JB		 2991/**
2992 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2993 * @vsi: the VSI being configured
2994 * @basename: name for the vector
2995 *
2996 * Allocates MSI-X vectors and requests interrupts from the kernel.
2997 **/
2998static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2999{
3000 int q_vectors = vsi->num_q_vectors;
3001 struct i40e_pf *pf = vsi->back;
3002 int base = vsi->base_vector;
3003 int rx_int_idx = 0;
3004 int tx_int_idx = 0;
3005 int vector, err;
3006
3007 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3008 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3009
cd0b6fa6 3010 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3011 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3012 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3013 tx_int_idx++;
cd0b6fa6 3014 } else if (q_vector->rx.ring) {
41c445ff
JB		 3015 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3016 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3017 } else if (q_vector->tx.ring) {
41c445ff
JB		 3018 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3019 "%s-%s-%d", basename, "tx", tx_int_idx++);
3020 } else {
3021 /* skip this unused q_vector */
3022 continue;
3023 }
3024 err = request_irq(pf->msix_entries[base + vector].vector,
3025 vsi->irq_handler,
3026 0,
3027 q_vector->name,
3028 q_vector);
3029 if (err) {
3030 dev_info(&pf->pdev->dev,
3031 "%s: request_irq failed, error: %d\n",
3032 __func__, err);
3033 goto free_queue_irqs;
3034 }
3035 /* assign the mask for this irq */
3036 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3037 &q_vector->affinity_mask);
3038 }
3039
63741846 3040 vsi->irqs_ready = true;
41c445ff
JB		 3041 return 0;
3042
3043free_queue_irqs:
3044 while (vector) {
3045 vector--;
3046 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3047 NULL);
3048 free_irq(pf->msix_entries[base + vector].vector,
3049 &(vsi->q_vectors[vector]));
3050 }
3051 return err;
3052}
3053
3054/**
3055 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3056 * @vsi: the VSI being un-configured
3057 **/
3058static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3059{
3060 struct i40e_pf *pf = vsi->back;
3061 struct i40e_hw *hw = &pf->hw;
3062 int base = vsi->base_vector;
3063 int i;
3064
3065 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3066 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3067 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3068 }
3069
3070 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3071 for (i = vsi->base_vector;
3072 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3073 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3074
3075 i40e_flush(hw);
3076 for (i = 0; i < vsi->num_q_vectors; i++)
3077 synchronize_irq(pf->msix_entries[i + base].vector);
3078 } else {
3079 /* Legacy and MSI mode - this stops all interrupt handling */
3080 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3081 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3082 i40e_flush(hw);
3083 synchronize_irq(pf->pdev->irq);
3084 }
3085}
3086
3087/**
3088 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3089 * @vsi: the VSI being configured
3090 **/
3091static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3092{
3093 struct i40e_pf *pf = vsi->back;
3094 int i;
3095
3096 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3097 for (i = vsi->base_vector;
3098 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3099 i40e_irq_dynamic_enable(vsi, i);
3100 } else {
3101 i40e_irq_dynamic_enable_icr0(pf);
3102 }
3103
1022cb6c 3104 i40e_flush(&pf->hw);
41c445ff
JB		 3105 return 0;
3106}
3107
3108/**
3109 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3110 * @pf: board private structure
3111 **/
3112static void i40e_stop_misc_vector(struct i40e_pf *pf)
3113{
3114 /* Disable ICR 0 */
3115 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3116 i40e_flush(&pf->hw);
3117}
3118
3119/**
3120 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3121 * @irq: interrupt number
3122 * @data: pointer to a q_vector
3123 *
3124 * This is the handler used for all MSI/Legacy interrupts, and deals
3125 * with both queue and non-queue interrupts. This is also used in
3126 * MSIX mode to handle the non-queue interrupts.
3127 **/
3128static irqreturn_t i40e_intr(int irq, void *data)
3129{
3130 struct i40e_pf *pf = (struct i40e_pf *)data;
3131 struct i40e_hw *hw = &pf->hw;
5e823066 3132 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3133 u32 icr0, icr0_remaining;
3134 u32 val, ena_mask;
3135
3136 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3137 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3138
116a57d4
SN		 3139 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3140 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3141 goto enable_intr;
41c445ff 3142
cd92e72f
SN		 3143 /* if interrupt but no bits showing, must be SWINT */
3144 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3145 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3146 pf->sw_int_count++;
3147
41c445ff
JB		 3148 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3149 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3150
3151 /* temporarily disable queue cause for NAPI processing */
3152 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3153 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3154 wr32(hw, I40E_QINT_RQCTL(0), qval);
3155
3156 qval = rd32(hw, I40E_QINT_TQCTL(0));
3157 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3158 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3159
3160 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3161 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3162 }
3163
3164 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3165 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3166 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3167 }
3168
3169 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3170 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3171 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3172 }
3173
3174 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3175 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3176 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3177 }
3178
3179 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3180 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3181 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3182 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3183 val = rd32(hw, I40E_GLGEN_RSTAT);
3184 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3185 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3186 if (val == I40E_RESET_CORER) {
41c445ff 3187 pf->corer_count++;
4eb3f768 3188 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3189 pf->globr_count++;
4eb3f768 3190 } else if (val == I40E_RESET_EMPR) {
41c445ff 3191 pf->empr_count++;
9df42d1a 3192 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3193 }
41c445ff
JB		 3194 }
3195
9c010ee0
ASJ		 3196 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3197 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3198 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3199 }
3200
beb0dff1
JK		 3201 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3202 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3203
3204 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3205 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3206 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3207 }
beb0dff1
JK		 3208 }
3209
41c445ff
JB		 3210 /* If a critical error is pending we have no choice but to reset the
3211 * device.
3212 * Report and mask out any remaining unexpected interrupts.
3213 */
3214 icr0_remaining = icr0 & ena_mask;
3215 if (icr0_remaining) {
3216 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3217 icr0_remaining);
9c010ee0 3218 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3219 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3220 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3221 dev_info(&pf->pdev->dev, "device will be reset\n");
3222 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3223 i40e_service_event_schedule(pf);
41c445ff
JB		 3224 }
3225 ena_mask &= ~icr0_remaining;
3226 }
5e823066 3227 ret = IRQ_HANDLED;
41c445ff 3228
5e823066 3229enable_intr:
41c445ff
JB		 3230 /* re-enable interrupt causes */
3231 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3232 if (!test_bit(__I40E_DOWN, &pf->state)) {
3233 i40e_service_event_schedule(pf);
3234 i40e_irq_dynamic_enable_icr0(pf);
3235 }
3236
5e823066 3237 return ret;
41c445ff
JB		 3238}
3239
cbf61325
ASJ		 3240/**
3241 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3242 * @tx_ring: tx ring to clean
3243 * @budget: how many cleans we're allowed
3244 *
3245 * Returns true if there's any budget left (e.g. the clean is finished)
3246 **/
3247static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3248{
3249 struct i40e_vsi *vsi = tx_ring->vsi;
3250 u16 i = tx_ring->next_to_clean;
3251 struct i40e_tx_buffer *tx_buf;
3252 struct i40e_tx_desc *tx_desc;
3253
3254 tx_buf = &tx_ring->tx_bi[i];
3255 tx_desc = I40E_TX_DESC(tx_ring, i);
3256 i -= tx_ring->count;
3257
3258 do {
3259 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3260
3261 /* if next_to_watch is not set then there is no work pending */
3262 if (!eop_desc)
3263 break;
3264
3265 /* prevent any other reads prior to eop_desc */
3266 read_barrier_depends();
3267
3268 /* if the descriptor isn't done, no work yet to do */
3269 if (!(eop_desc->cmd_type_offset_bsz &
3270 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3271 break;
3272
3273 /* clear next_to_watch to prevent false hangs */
3274 tx_buf->next_to_watch = NULL;
3275
49d7d933
ASJ		 3276 tx_desc->buffer_addr = 0;
3277 tx_desc->cmd_type_offset_bsz = 0;
3278 /* move past filter desc */
3279 tx_buf++;
3280 tx_desc++;
3281 i++;
3282 if (unlikely(!i)) {
3283 i -= tx_ring->count;
3284 tx_buf = tx_ring->tx_bi;
3285 tx_desc = I40E_TX_DESC(tx_ring, 0);
3286 }
cbf61325
ASJ		 3287 /* unmap skb header data */
3288 dma_unmap_single(tx_ring->dev,
3289 dma_unmap_addr(tx_buf, dma),
3290 dma_unmap_len(tx_buf, len),
3291 DMA_TO_DEVICE);
49d7d933
ASJ		 3292 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3293 kfree(tx_buf->raw_buf);
cbf61325 3294
49d7d933
ASJ		 3295 tx_buf->raw_buf = NULL;
3296 tx_buf->tx_flags = 0;
3297 tx_buf->next_to_watch = NULL;
cbf61325 3298 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3299 tx_desc->buffer_addr = 0;
3300 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3301
49d7d933 3302 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3303 tx_buf++;
3304 tx_desc++;
3305 i++;
3306 if (unlikely(!i)) {
3307 i -= tx_ring->count;
3308 tx_buf = tx_ring->tx_bi;
3309 tx_desc = I40E_TX_DESC(tx_ring, 0);
3310 }
3311
3312 /* update budget accounting */
3313 budget--;
3314 } while (likely(budget));
3315
3316 i += tx_ring->count;
3317 tx_ring->next_to_clean = i;
3318
3319 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3320 i40e_irq_dynamic_enable(vsi,
3321 tx_ring->q_vector->v_idx + vsi->base_vector);
3322 }
3323 return budget > 0;
3324}
3325
3326/**
3327 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3328 * @irq: interrupt number
3329 * @data: pointer to a q_vector
3330 **/
3331static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3332{
3333 struct i40e_q_vector *q_vector = data;
3334 struct i40e_vsi *vsi;
3335
3336 if (!q_vector->tx.ring)
3337 return IRQ_HANDLED;
3338
3339 vsi = q_vector->tx.ring->vsi;
3340 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3341
3342 return IRQ_HANDLED;
3343}
3344
41c445ff 3345/**
cd0b6fa6 3346 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3347 * @vsi: the VSI being configured
3348 * @v_idx: vector index
cd0b6fa6 3349 * @qp_idx: queue pair index
41c445ff 3350 **/
cd0b6fa6 3351static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3352{
493fb300 3353 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3354 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3355 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3356
3357 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3358 tx_ring->next = q_vector->tx.ring;
3359 q_vector->tx.ring = tx_ring;
41c445ff 3360 q_vector->tx.count++;
cd0b6fa6
AD		 3361
3362 rx_ring->q_vector = q_vector;
3363 rx_ring->next = q_vector->rx.ring;
3364 q_vector->rx.ring = rx_ring;
3365 q_vector->rx.count++;
41c445ff
JB		 3366}
3367
3368/**
3369 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3370 * @vsi: the VSI being configured
3371 *
3372 * This function maps descriptor rings to the queue-specific vectors
3373 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3374 * one vector per queue pair, but on a constrained vector budget, we
3375 * group the queue pairs as "efficiently" as possible.
3376 **/
3377static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3378{
3379 int qp_remaining = vsi->num_queue_pairs;
3380 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3381 int num_ringpairs;
41c445ff
JB		 3382 int v_start = 0;
3383 int qp_idx = 0;
3384
3385 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3386 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3387 * It is also important to go through all the vectors available to be
3388 * sure that if we don't use all the vectors, that the remaining vectors
3389 * are cleared. This is especially important when decreasing the
3390 * number of queues in use.
41c445ff 3391 */
70114ec4 3392 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3393 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3394
3395 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3396
3397 q_vector->num_ringpairs = num_ringpairs;
3398
3399 q_vector->rx.count = 0;
3400 q_vector->tx.count = 0;
3401 q_vector->rx.ring = NULL;
3402 q_vector->tx.ring = NULL;
3403
3404 while (num_ringpairs--) {
3405 map_vector_to_qp(vsi, v_start, qp_idx);
3406 qp_idx++;
3407 qp_remaining--;
41c445ff
JB		 3408 }
3409 }
3410}
3411
3412/**
3413 * i40e_vsi_request_irq - Request IRQ from the OS
3414 * @vsi: the VSI being configured
3415 * @basename: name for the vector
3416 **/
3417static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3418{
3419 struct i40e_pf *pf = vsi->back;
3420 int err;
3421
3422 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3423 err = i40e_vsi_request_irq_msix(vsi, basename);
3424 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3425 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3426 pf->int_name, pf);
41c445ff
JB		 3427 else
3428 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3429 pf->int_name, pf);
41c445ff
JB		 3430
3431 if (err)
3432 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3433
3434 return err;
3435}
3436
3437#ifdef CONFIG_NET_POLL_CONTROLLER
3438/**
3439 * i40e_netpoll - A Polling 'interrupt'handler
3440 * @netdev: network interface device structure
3441 *
3442 * This is used by netconsole to send skbs without having to re-enable
3443 * interrupts. It's not called while the normal interrupt routine is executing.
3444 **/
38e00438
VD		 3445#ifdef I40E_FCOE
3446void i40e_netpoll(struct net_device *netdev)
3447#else
41c445ff 3448static void i40e_netpoll(struct net_device *netdev)
38e00438 3449#endif
41c445ff
JB		 3450{
3451 struct i40e_netdev_priv *np = netdev_priv(netdev);
3452 struct i40e_vsi *vsi = np->vsi;
3453 struct i40e_pf *pf = vsi->back;
3454 int i;
3455
3456 /* if interface is down do nothing */
3457 if (test_bit(__I40E_DOWN, &vsi->state))
3458 return;
3459
3460 pf->flags |= I40E_FLAG_IN_NETPOLL;
3461 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3462 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3463 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3464 } else {
3465 i40e_intr(pf->pdev->irq, netdev);
3466 }
3467 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3468}
3469#endif
3470
23527308
NP		 3471/**
3472 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3473 * @pf: the PF being configured
3474 * @pf_q: the PF queue
3475 * @enable: enable or disable state of the queue
3476 *
3477 * This routine will wait for the given Tx queue of the PF to reach the
3478 * enabled or disabled state.
3479 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3480 * multiple retries; else will return 0 in case of success.
3481 **/
3482static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3483{
3484 int i;
3485 u32 tx_reg;
3486
3487 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3488 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3489 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3490 break;
3491
f98a2006 3492 usleep_range(10, 20);
23527308
NP		 3493 }
3494 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3495 return -ETIMEDOUT;
3496
3497 return 0;
3498}
3499
41c445ff
JB		 3500/**
3501 * i40e_vsi_control_tx - Start or stop a VSI's rings
3502 * @vsi: the VSI being configured
3503 * @enable: start or stop the rings
3504 **/
3505static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3506{
3507 struct i40e_pf *pf = vsi->back;
3508 struct i40e_hw *hw = &pf->hw;
23527308 3509 int i, j, pf_q, ret = 0;
41c445ff
JB		 3510 u32 tx_reg;
3511
3512 pf_q = vsi->base_queue;
3513 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3514
3515 /* warn the TX unit of coming changes */
3516 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3517 if (!enable)
f98a2006 3518 usleep_range(10, 20);
351499ab 3519
6c5ef620 3520 for (j = 0; j < 50; j++) {
41c445ff 3521 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3522 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3523 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3524 break;
3525 usleep_range(1000, 2000);
3526 }
fda972f6 3527 /* Skip if the queue is already in the requested state */
7c122007 3528 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3529 continue;
41c445ff
JB		 3530
3531 /* turn on/off the queue */
c5c9eb9e
SN		 3532 if (enable) {
3533 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3534 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3535 } else {
41c445ff 3536 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3537 }
41c445ff
JB		 3538
3539 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3540 /* No waiting for the Tx queue to disable */
3541 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3542 continue;
41c445ff
JB		 3543
3544 /* wait for the change to finish */
23527308
NP		 3545 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3546 if (ret) {
3547 dev_info(&pf->pdev->dev,
3548 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3549 __func__, vsi->seid, pf_q,
3550 (enable ? "en" : "dis"));
3551 break;
41c445ff
JB		 3552 }
3553 }
3554
7134f9ce
JB		 3555 if (hw->revision_id == 0)
3556 mdelay(50);
23527308
NP		 3557 return ret;
3558}
3559
3560/**
3561 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3562 * @pf: the PF being configured
3563 * @pf_q: the PF queue
3564 * @enable: enable or disable state of the queue
3565 *
3566 * This routine will wait for the given Rx queue of the PF to reach the
3567 * enabled or disabled state.
3568 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3569 * multiple retries; else will return 0 in case of success.
3570 **/
3571static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3572{
3573 int i;
3574 u32 rx_reg;
3575
3576 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3577 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3578 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3579 break;
3580
f98a2006 3581 usleep_range(10, 20);
23527308
NP		 3582 }
3583 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3584 return -ETIMEDOUT;
7134f9ce 3585
41c445ff
JB		 3586 return 0;
3587}
3588
3589/**
3590 * i40e_vsi_control_rx - Start or stop a VSI's rings
3591 * @vsi: the VSI being configured
3592 * @enable: start or stop the rings
3593 **/
3594static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3595{
3596 struct i40e_pf *pf = vsi->back;
3597 struct i40e_hw *hw = &pf->hw;
23527308 3598 int i, j, pf_q, ret = 0;
41c445ff
JB		 3599 u32 rx_reg;
3600
3601 pf_q = vsi->base_queue;
3602 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3603 for (j = 0; j < 50; j++) {
41c445ff 3604 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3605 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3606 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3607 break;
3608 usleep_range(1000, 2000);
3609 }
41c445ff 3610
7c122007
CS		 3611 /* Skip if the queue is already in the requested state */
3612 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3613 continue;
41c445ff
JB		 3614
3615 /* turn on/off the queue */
3616 if (enable)
6c5ef620 3617 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3618 else
6c5ef620 3619 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3620 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3621
3622 /* wait for the change to finish */
23527308
NP		 3623 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3624 if (ret) {
3625 dev_info(&pf->pdev->dev,
3626 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3627 __func__, vsi->seid, pf_q,
3628 (enable ? "en" : "dis"));
3629 break;
41c445ff
JB		 3630 }
3631 }
3632
23527308 3633 return ret;
41c445ff
JB		 3634}
3635
3636/**
3637 * i40e_vsi_control_rings - Start or stop a VSI's rings
3638 * @vsi: the VSI being configured
3639 * @enable: start or stop the rings
3640 **/
fc18eaa0 3641int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3642{
3b867b28 3643 int ret = 0;
41c445ff
JB		 3644
3645 /* do rx first for enable and last for disable */
3646 if (request) {
3647 ret = i40e_vsi_control_rx(vsi, request);
3648 if (ret)
3649 return ret;
3650 ret = i40e_vsi_control_tx(vsi, request);
3651 } else {
3b867b28
ASJ		 3652 /* Ignore return value, we need to shutdown whatever we can */
3653 i40e_vsi_control_tx(vsi, request);
3654 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3655 }
3656
3657 return ret;
3658}
3659
3660/**
3661 * i40e_vsi_free_irq - Free the irq association with the OS
3662 * @vsi: the VSI being configured
3663 **/
3664static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3665{
3666 struct i40e_pf *pf = vsi->back;
3667 struct i40e_hw *hw = &pf->hw;
3668 int base = vsi->base_vector;
3669 u32 val, qp;
3670 int i;
3671
3672 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3673 if (!vsi->q_vectors)
3674 return;
3675
63741846
SN		 3676 if (!vsi->irqs_ready)
3677 return;
3678
3679 vsi->irqs_ready = false;
41c445ff
JB		 3680 for (i = 0; i < vsi->num_q_vectors; i++) {
3681 u16 vector = i + base;
3682
3683 /* free only the irqs that were actually requested */
78681b1f
SN		 3684 if (!vsi->q_vectors[i] ||
3685 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3686 continue;
3687
3688 /* clear the affinity_mask in the IRQ descriptor */
3689 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3690 NULL);
3691 free_irq(pf->msix_entries[vector].vector,
493fb300 3692 vsi->q_vectors[i]);
41c445ff
JB		 3693
3694 /* Tear down the interrupt queue link list
3695 *
3696 * We know that they come in pairs and always
3697 * the Rx first, then the Tx. To clear the
3698 * link list, stick the EOL value into the
3699 * next_q field of the registers.
3700 */
3701 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3702 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3703 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3704 val |= I40E_QUEUE_END_OF_LIST
3705 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3706 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3707
3708 while (qp != I40E_QUEUE_END_OF_LIST) {
3709 u32 next;
3710
3711 val = rd32(hw, I40E_QINT_RQCTL(qp));
3712
3713 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3714 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3715 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3716 I40E_QINT_RQCTL_INTEVENT_MASK);
3717
3718 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3719 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3720
3721 wr32(hw, I40E_QINT_RQCTL(qp), val);
3722
3723 val = rd32(hw, I40E_QINT_TQCTL(qp));
3724
3725 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3726 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3727
3728 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3729 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3730 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3731 I40E_QINT_TQCTL_INTEVENT_MASK);
3732
3733 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3734 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3735
3736 wr32(hw, I40E_QINT_TQCTL(qp), val);
3737 qp = next;
3738 }
3739 }
3740 } else {
3741 free_irq(pf->pdev->irq, pf);
3742
3743 val = rd32(hw, I40E_PFINT_LNKLST0);
3744 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3745 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3746 val |= I40E_QUEUE_END_OF_LIST
3747 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3748 wr32(hw, I40E_PFINT_LNKLST0, val);
3749
3750 val = rd32(hw, I40E_QINT_RQCTL(qp));
3751 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3752 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3753 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3754 I40E_QINT_RQCTL_INTEVENT_MASK);
3755
3756 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3757 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3758
3759 wr32(hw, I40E_QINT_RQCTL(qp), val);
3760
3761 val = rd32(hw, I40E_QINT_TQCTL(qp));
3762
3763 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3764 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3765 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3766 I40E_QINT_TQCTL_INTEVENT_MASK);
3767
3768 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3769 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3770
3771 wr32(hw, I40E_QINT_TQCTL(qp), val);
3772 }
3773}
3774
493fb300
AD		 3775/**
3776 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3777 * @vsi: the VSI being configured
3778 * @v_idx: Index of vector to be freed
3779 *
3780 * This function frees the memory allocated to the q_vector. In addition if
3781 * NAPI is enabled it will delete any references to the NAPI struct prior
3782 * to freeing the q_vector.
3783 **/
3784static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3785{
3786 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3787 struct i40e_ring *ring;
493fb300
AD		 3788
3789 if (!q_vector)
3790 return;
3791
3792 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3793 i40e_for_each_ring(ring, q_vector->tx)
3794 ring->q_vector = NULL;
3795
3796 i40e_for_each_ring(ring, q_vector->rx)
3797 ring->q_vector = NULL;
493fb300
AD		 3798
3799 /* only VSI w/ an associated netdev is set up w/ NAPI */
3800 if (vsi->netdev)
3801 netif_napi_del(&q_vector->napi);
3802
3803 vsi->q_vectors[v_idx] = NULL;
3804
3805 kfree_rcu(q_vector, rcu);
3806}
3807
41c445ff
JB		 3808/**
3809 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3810 * @vsi: the VSI being un-configured
3811 *
3812 * This frees the memory allocated to the q_vectors and
3813 * deletes references to the NAPI struct.
3814 **/
3815static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3816{
3817 int v_idx;
3818
493fb300
AD		 3819 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3820 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3821}
3822
3823/**
3824 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3825 * @pf: board private structure
3826 **/
3827static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3828{
3829 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3830 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3831 pci_disable_msix(pf->pdev);
3832 kfree(pf->msix_entries);
3833 pf->msix_entries = NULL;
3834 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3835 pci_disable_msi(pf->pdev);
3836 }
3837 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3838}
3839
3840/**
3841 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3842 * @pf: board private structure
3843 *
3844 * We go through and clear interrupt specific resources and reset the structure
3845 * to pre-load conditions
3846 **/
3847static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3848{
3849 int i;
3850
e147758d
SN		 3851 i40e_stop_misc_vector(pf);
3852 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3853 synchronize_irq(pf->msix_entries[0].vector);
3854 free_irq(pf->msix_entries[0].vector, pf);
3855 }
3856
41c445ff 3857 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3858 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3859 if (pf->vsi[i])
3860 i40e_vsi_free_q_vectors(pf->vsi[i]);
3861 i40e_reset_interrupt_capability(pf);
3862}
3863
3864/**
3865 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3866 * @vsi: the VSI being configured
3867 **/
3868static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3869{
3870 int q_idx;
3871
3872 if (!vsi->netdev)
3873 return;
3874
3875 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3876 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3877}
3878
3879/**
3880 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3881 * @vsi: the VSI being configured
3882 **/
3883static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3884{
3885 int q_idx;
3886
3887 if (!vsi->netdev)
3888 return;
3889
3890 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3891 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3892}
3893
90ef8d47
SN		 3894/**
3895 * i40e_vsi_close - Shut down a VSI
3896 * @vsi: the vsi to be quelled
3897 **/
3898static void i40e_vsi_close(struct i40e_vsi *vsi)
3899{
3900 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3901 i40e_down(vsi);
3902 i40e_vsi_free_irq(vsi);
3903 i40e_vsi_free_tx_resources(vsi);
3904 i40e_vsi_free_rx_resources(vsi);
3905}
3906
41c445ff
JB		 3907/**
3908 * i40e_quiesce_vsi - Pause a given VSI
3909 * @vsi: the VSI being paused
3910 **/
3911static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3912{
3913 if (test_bit(__I40E_DOWN, &vsi->state))
3914 return;
3915
d341b7a5
NP		 3916 /* No need to disable FCoE VSI when Tx suspended */
3917 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
3918 vsi->type == I40E_VSI_FCOE) {
3919 dev_dbg(&vsi->back->pdev->dev,
3920 "%s: VSI seid %d skipping FCoE VSI disable\n",
3921 __func__, vsi->seid);
3922 return;
3923 }
3924
41c445ff
JB		 3925 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3926 if (vsi->netdev && netif_running(vsi->netdev)) {
3927 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3928 } else {
90ef8d47 3929 i40e_vsi_close(vsi);
41c445ff
JB		 3930 }
3931}
3932
3933/**
3934 * i40e_unquiesce_vsi - Resume a given VSI
3935 * @vsi: the VSI being resumed
3936 **/
3937static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3938{
3939 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3940 return;
3941
3942 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3943 if (vsi->netdev && netif_running(vsi->netdev))
3944 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3945 else
8276f757 3946 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3947}
3948
3949/**
3950 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3951 * @pf: the PF
3952 **/
3953static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3954{
3955 int v;
3956
505682cd 3957 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3958 if (pf->vsi[v])
3959 i40e_quiesce_vsi(pf->vsi[v]);
3960 }
3961}
3962
3963/**
3964 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3965 * @pf: the PF
3966 **/
3967static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3968{
3969 int v;
3970
505682cd 3971 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3972 if (pf->vsi[v])
3973 i40e_unquiesce_vsi(pf->vsi[v]);
3974 }
3975}
3976
69129dc3
NP		 3977#ifdef CONFIG_I40E_DCB
3978/**
3979 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
3980 * @vsi: the VSI being configured
3981 *
3982 * This function waits for the given VSI's Tx queues to be disabled.
3983 **/
3984static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
3985{
3986 struct i40e_pf *pf = vsi->back;
3987 int i, pf_q, ret;
3988
3989 pf_q = vsi->base_queue;
3990 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3991 /* Check and wait for the disable status of the queue */
3992 ret = i40e_pf_txq_wait(pf, pf_q, false);
3993 if (ret) {
3994 dev_info(&pf->pdev->dev,
3995 "%s: VSI seid %d Tx ring %d disable timeout\n",
3996 __func__, vsi->seid, pf_q);
3997 return ret;
3998 }
3999 }
4000
4001 return 0;
4002}
4003
4004/**
4005 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4006 * @pf: the PF
4007 *
4008 * This function waits for the Tx queues to be in disabled state for all the
4009 * VSIs that are managed by this PF.
4010 **/
4011static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4012{
4013 int v, ret = 0;
4014
4015 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4016 /* No need to wait for FCoE VSI queues */
4017 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4018 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4019 if (ret)
4020 break;
4021 }
4022 }
4023
4024 return ret;
4025}
4026
4027#endif
63d7e5a4
NP		 4028/**
4029 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
4030 * @pf: pointer to pf
4031 *
4032 * Get TC map for ISCSI PF type that will include iSCSI TC
4033 * and LAN TC.
4034 **/
4035static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4036{
4037 struct i40e_dcb_app_priority_table app;
4038 struct i40e_hw *hw = &pf->hw;
4039 u8 enabled_tc = 1; /* TC0 is always enabled */
4040 u8 tc, i;
4041 /* Get the iSCSI APP TLV */
4042 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4043
4044 for (i = 0; i < dcbcfg->numapps; i++) {
4045 app = dcbcfg->app[i];
4046 if (app.selector == I40E_APP_SEL_TCPIP &&
4047 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4048 tc = dcbcfg->etscfg.prioritytable[app.priority];
4049 enabled_tc |= (1 << tc);
4050 break;
4051 }
4052 }
4053
4054 return enabled_tc;
4055}
4056
41c445ff
JB		 4057/**
4058 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4059 * @dcbcfg: the corresponding DCBx configuration structure
4060 *
4061 * Return the number of TCs from given DCBx configuration
4062 **/
4063static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4064{
078b5876
JB		 4065 u8 num_tc = 0;
4066 int i;
41c445ff
JB		 4067
4068 /* Scan the ETS Config Priority Table to find
4069 * traffic class enabled for a given priority
4070 * and use the traffic class index to get the
4071 * number of traffic classes enabled
4072 */
4073 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4074 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4075 num_tc = dcbcfg->etscfg.prioritytable[i];
4076 }
4077
4078 /* Traffic class index starts from zero so
4079 * increment to return the actual count
4080 */
078b5876 4081 return num_tc + 1;
41c445ff
JB		 4082}
4083
4084/**
4085 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4086 * @dcbcfg: the corresponding DCBx configuration structure
4087 *
4088 * Query the current DCB configuration and return the number of
4089 * traffic classes enabled from the given DCBX config
4090 **/
4091static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4092{
4093 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4094 u8 enabled_tc = 1;
4095 u8 i;
4096
4097 for (i = 0; i < num_tc; i++)
4098 enabled_tc |= 1 << i;
4099
4100 return enabled_tc;
4101}
4102
4103/**
4104 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4105 * @pf: PF being queried
4106 *
4107 * Return number of traffic classes enabled for the given PF
4108 **/
4109static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4110{
4111 struct i40e_hw *hw = &pf->hw;
4112 u8 i, enabled_tc;
4113 u8 num_tc = 0;
4114 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4115
4116 /* If DCB is not enabled then always in single TC */
4117 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4118 return 1;
4119
63d7e5a4
NP		 4120 /* SFP mode will be enabled for all TCs on port */
4121 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4122 return i40e_dcb_get_num_tc(dcbcfg);
4123
41c445ff 4124 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4125 if (pf->hw.func_caps.iscsi)
4126 enabled_tc = i40e_get_iscsi_tc_map(pf);
4127 else
fc51de96 4128 return 1; /* Only TC0 */
41c445ff 4129
63d7e5a4
NP		 4130 /* At least have TC0 */
4131 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4132 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4133 if (enabled_tc & (1 << i))
4134 num_tc++;
4135 }
4136 return num_tc;
41c445ff
JB		 4137}
4138
4139/**
4140 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4141 * @pf: PF being queried
4142 *
4143 * Return a bitmap for first enabled traffic class for this PF.
4144 **/
4145static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4146{
4147 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4148 u8 i = 0;
4149
4150 if (!enabled_tc)
4151 return 0x1; /* TC0 */
4152
4153 /* Find the first enabled TC */
4154 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4155 if (enabled_tc & (1 << i))
4156 break;
4157 }
4158
4159 return 1 << i;
4160}
4161
4162/**
4163 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4164 * @pf: PF being queried
4165 *
4166 * Return a bitmap for enabled traffic classes for this PF.
4167 **/
4168static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4169{
4170 /* If DCB is not enabled for this PF then just return default TC */
4171 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4172 return i40e_pf_get_default_tc(pf);
4173
41c445ff 4174 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4175 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4176 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4177
fc51de96 4178 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4179 if (pf->hw.func_caps.iscsi)
4180 return i40e_get_iscsi_tc_map(pf);
4181 else
fc51de96 4182 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4183}
4184
4185/**
4186 * i40e_vsi_get_bw_info - Query VSI BW Information
4187 * @vsi: the VSI being queried
4188 *
4189 * Returns 0 on success, negative value on failure
4190 **/
4191static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4192{
4193 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4194 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4195 struct i40e_pf *pf = vsi->back;
4196 struct i40e_hw *hw = &pf->hw;
dcae29be 4197 i40e_status aq_ret;
41c445ff 4198 u32 tc_bw_max;
41c445ff
JB		 4199 int i;
4200
4201 /* Get the VSI level BW configuration */
dcae29be
JB		 4202 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4203 if (aq_ret) {
41c445ff
JB		 4204 dev_info(&pf->pdev->dev,
4205 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4206 aq_ret, pf->hw.aq.asq_last_status);
4207 return -EINVAL;
41c445ff
JB		 4208 }
4209
4210 /* Get the VSI level BW configuration per TC */
dcae29be 4211 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4212 NULL);
dcae29be 4213 if (aq_ret) {
41c445ff
JB		 4214 dev_info(&pf->pdev->dev,
4215 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4216 aq_ret, pf->hw.aq.asq_last_status);
4217 return -EINVAL;
41c445ff
JB		 4218 }
4219
4220 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4221 dev_info(&pf->pdev->dev,
4222 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4223 bw_config.tc_valid_bits,
4224 bw_ets_config.tc_valid_bits);
4225 /* Still continuing */
4226 }
4227
4228 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4229 vsi->bw_max_quanta = bw_config.max_bw;
4230 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4231 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4232 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4233 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4234 vsi->bw_ets_limit_credits[i] =
4235 le16_to_cpu(bw_ets_config.credits[i]);
4236 /* 3 bits out of 4 for each TC */
4237 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4238 }
078b5876 4239
dcae29be 4240 return 0;
41c445ff
JB		 4241}
4242
4243/**
4244 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4245 * @vsi: the VSI being configured
4246 * @enabled_tc: TC bitmap
4247 * @bw_credits: BW shared credits per TC
4248 *
4249 * Returns 0 on success, negative value on failure
4250 **/
dcae29be 4251static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4252 u8 *bw_share)
4253{
4254 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4255 i40e_status aq_ret;
4256 int i;
41c445ff
JB		 4257
4258 bw_data.tc_valid_bits = enabled_tc;
4259 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4260 bw_data.tc_bw_credits[i] = bw_share[i];
4261
dcae29be
JB		 4262 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4263 NULL);
4264 if (aq_ret) {
41c445ff 4265 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4266 "AQ command Config VSI BW allocation per TC failed = %d\n",
4267 vsi->back->hw.aq.asq_last_status);
dcae29be 4268 return -EINVAL;
41c445ff
JB		 4269 }
4270
4271 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4272 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4273
dcae29be 4274 return 0;
41c445ff
JB		 4275}
4276
4277/**
4278 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4279 * @vsi: the VSI being configured
4280 * @enabled_tc: TC map to be enabled
4281 *
4282 **/
4283static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4284{
4285 struct net_device *netdev = vsi->netdev;
4286 struct i40e_pf *pf = vsi->back;
4287 struct i40e_hw *hw = &pf->hw;
4288 u8 netdev_tc = 0;
4289 int i;
4290 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4291
4292 if (!netdev)
4293 return;
4294
4295 if (!enabled_tc) {
4296 netdev_reset_tc(netdev);
4297 return;
4298 }
4299
4300 /* Set up actual enabled TCs on the VSI */
4301 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4302 return;
4303
4304 /* set per TC queues for the VSI */
4305 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4306 /* Only set TC queues for enabled tcs
4307 *
4308 * e.g. For a VSI that has TC0 and TC3 enabled the
4309 * enabled_tc bitmap would be 0x00001001; the driver
4310 * will set the numtc for netdev as 2 that will be
4311 * referenced by the netdev layer as TC 0 and 1.
4312 */
4313 if (vsi->tc_config.enabled_tc & (1 << i))
4314 netdev_set_tc_queue(netdev,
4315 vsi->tc_config.tc_info[i].netdev_tc,
4316 vsi->tc_config.tc_info[i].qcount,
4317 vsi->tc_config.tc_info[i].qoffset);
4318 }
4319
4320 /* Assign UP2TC map for the VSI */
4321 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4322 /* Get the actual TC# for the UP */
4323 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4324 /* Get the mapped netdev TC# for the UP */
4325 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4326 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4327 }
4328}
4329
4330/**
4331 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4332 * @vsi: the VSI being configured
4333 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4334 **/
4335static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4336 struct i40e_vsi_context *ctxt)
4337{
4338 /* copy just the sections touched not the entire info
4339 * since not all sections are valid as returned by
4340 * update vsi params
4341 */
4342 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4343 memcpy(&vsi->info.queue_mapping,
4344 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4345 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4346 sizeof(vsi->info.tc_mapping));
4347}
4348
4349/**
4350 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4351 * @vsi: VSI to be configured
4352 * @enabled_tc: TC bitmap
4353 *
4354 * This configures a particular VSI for TCs that are mapped to the
4355 * given TC bitmap. It uses default bandwidth share for TCs across
4356 * VSIs to configure TC for a particular VSI.
4357 *
4358 * NOTE:
4359 * It is expected that the VSI queues have been quisced before calling
4360 * this function.
4361 **/
4362static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4363{
4364 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4365 struct i40e_vsi_context ctxt;
4366 int ret = 0;
4367 int i;
4368
4369 /* Check if enabled_tc is same as existing or new TCs */
4370 if (vsi->tc_config.enabled_tc == enabled_tc)
4371 return ret;
4372
4373 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4374 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4375 if (enabled_tc & (1 << i))
4376 bw_share[i] = 1;
4377 }
4378
4379 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4380 if (ret) {
4381 dev_info(&vsi->back->pdev->dev,
4382 "Failed configuring TC map %d for VSI %d\n",
4383 enabled_tc, vsi->seid);
4384 goto out;
4385 }
4386
4387 /* Update Queue Pairs Mapping for currently enabled UPs */
4388 ctxt.seid = vsi->seid;
4389 ctxt.pf_num = vsi->back->hw.pf_id;
4390 ctxt.vf_num = 0;
4391 ctxt.uplink_seid = vsi->uplink_seid;
4392 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4393 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4394
4395 /* Update the VSI after updating the VSI queue-mapping information */
4396 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4397 if (ret) {
4398 dev_info(&vsi->back->pdev->dev,
4399 "update vsi failed, aq_err=%d\n",
4400 vsi->back->hw.aq.asq_last_status);
4401 goto out;
4402 }
4403 /* update the local VSI info with updated queue map */
4404 i40e_vsi_update_queue_map(vsi, &ctxt);
4405 vsi->info.valid_sections = 0;
4406
4407 /* Update current VSI BW information */
4408 ret = i40e_vsi_get_bw_info(vsi);
4409 if (ret) {
4410 dev_info(&vsi->back->pdev->dev,
4411 "Failed updating vsi bw info, aq_err=%d\n",
4412 vsi->back->hw.aq.asq_last_status);
4413 goto out;
4414 }
4415
4416 /* Update the netdev TC setup */
4417 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4418out:
4419 return ret;
4420}
4421
4e3b35b0
NP		 4422/**
4423 * i40e_veb_config_tc - Configure TCs for given VEB
4424 * @veb: given VEB
4425 * @enabled_tc: TC bitmap
4426 *
4427 * Configures given TC bitmap for VEB (switching) element
4428 **/
4429int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4430{
4431 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4432 struct i40e_pf *pf = veb->pf;
4433 int ret = 0;
4434 int i;
4435
4436 /* No TCs or already enabled TCs just return */
4437 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4438 return ret;
4439
4440 bw_data.tc_valid_bits = enabled_tc;
4441 /* bw_data.absolute_credits is not set (relative) */
4442
4443 /* Enable ETS TCs with equal BW Share for now */
4444 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4445 if (enabled_tc & (1 << i))
4446 bw_data.tc_bw_share_credits[i] = 1;
4447 }
4448
4449 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4450 &bw_data, NULL);
4451 if (ret) {
4452 dev_info(&pf->pdev->dev,
4453 "veb bw config failed, aq_err=%d\n",
4454 pf->hw.aq.asq_last_status);
4455 goto out;
4456 }
4457
4458 /* Update the BW information */
4459 ret = i40e_veb_get_bw_info(veb);
4460 if (ret) {
4461 dev_info(&pf->pdev->dev,
4462 "Failed getting veb bw config, aq_err=%d\n",
4463 pf->hw.aq.asq_last_status);
4464 }
4465
4466out:
4467 return ret;
4468}
4469
4470#ifdef CONFIG_I40E_DCB
4471/**
4472 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4473 * @pf: PF struct
4474 *
4475 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4476 * the caller would've quiesce all the VSIs before calling
4477 * this function
4478 **/
4479static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4480{
4481 u8 tc_map = 0;
4482 int ret;
4483 u8 v;
4484
4485 /* Enable the TCs available on PF to all VEBs */
4486 tc_map = i40e_pf_get_tc_map(pf);
4487 for (v = 0; v < I40E_MAX_VEB; v++) {
4488 if (!pf->veb[v])
4489 continue;
4490 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4491 if (ret) {
4492 dev_info(&pf->pdev->dev,
4493 "Failed configuring TC for VEB seid=%d\n",
4494 pf->veb[v]->seid);
4495 /* Will try to configure as many components */
4496 }
4497 }
4498
4499 /* Update each VSI */
505682cd 4500 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4501 if (!pf->vsi[v])
4502 continue;
4503
4504 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4505#ifdef I40E_FCOE
4506 * - For FCoE VSI only enable the TC configured
4507 * as per the APP TLV
4508#endif
4e3b35b0
NP		 4509 * - For all others keep them at TC0 for now
4510 */
4511 if (v == pf->lan_vsi)
4512 tc_map = i40e_pf_get_tc_map(pf);
4513 else
4514 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4515#ifdef I40E_FCOE
4516 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4517 tc_map = i40e_get_fcoe_tc_map(pf);
4518#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4519
4520 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4521 if (ret) {
4522 dev_info(&pf->pdev->dev,
4523 "Failed configuring TC for VSI seid=%d\n",
4524 pf->vsi[v]->seid);
4525 /* Will try to configure as many components */
4526 } else {
0672a091
NP		 4527 /* Re-configure VSI vectors based on updated TC map */
4528 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4529 if (pf->vsi[v]->netdev)
4530 i40e_dcbnl_set_all(pf->vsi[v]);
4531 }
4532 }
4533}
4534
2fd75f31
NP		 4535/**
4536 * i40e_resume_port_tx - Resume port Tx
4537 * @pf: PF struct
4538 *
4539 * Resume a port's Tx and issue a PF reset in case of failure to
4540 * resume.
4541 **/
4542static int i40e_resume_port_tx(struct i40e_pf *pf)
4543{
4544 struct i40e_hw *hw = &pf->hw;
4545 int ret;
4546
4547 ret = i40e_aq_resume_port_tx(hw, NULL);
4548 if (ret) {
4549 dev_info(&pf->pdev->dev,
4550 "AQ command Resume Port Tx failed = %d\n",
4551 pf->hw.aq.asq_last_status);
4552 /* Schedule PF reset to recover */
4553 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4554 i40e_service_event_schedule(pf);
4555 }
4556
4557 return ret;
4558}
4559
4e3b35b0
NP		 4560/**
4561 * i40e_init_pf_dcb - Initialize DCB configuration
4562 * @pf: PF being configured
4563 *
4564 * Query the current DCB configuration and cache it
4565 * in the hardware structure
4566 **/
4567static int i40e_init_pf_dcb(struct i40e_pf *pf)
4568{
4569 struct i40e_hw *hw = &pf->hw;
4570 int err = 0;
4571
025b4a54
ASJ		 4572 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4573 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4574 (pf->hw.aq.fw_maj_ver < 4))
4575 goto out;
4576
4e3b35b0
NP		 4577 /* Get the initial DCB configuration */
4578 err = i40e_init_dcb(hw);
4579 if (!err) {
4580 /* Device/Function is not DCBX capable */
4581 if ((!hw->func_caps.dcb) ||
4582 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4583 dev_info(&pf->pdev->dev,
4584 "DCBX offload is not supported or is disabled for this PF.\n");
4585
4586 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4587 goto out;
4588
4589 } else {
4590 /* When status is not DISABLED then DCBX in FW */
4591 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4592 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4593
4594 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4595 /* Enable DCB tagging only when more than one TC */
4596 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4597 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4598 dev_dbg(&pf->pdev->dev,
4599 "DCBX offload is supported for this PF.\n");
4e3b35b0 4600 }
014269ff 4601 } else {
aebfc816
SN		 4602 dev_info(&pf->pdev->dev,
4603 "AQ Querying DCB configuration failed: aq_err %d\n",
014269ff 4604 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4605 }
4606
4607out:
4608 return err;
4609}
4610#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4611#define SPEED_SIZE 14
4612#define FC_SIZE 8
4613/**
4614 * i40e_print_link_message - print link up or down
4615 * @vsi: the VSI for which link needs a message
4616 */
4617static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4618{
4619 char speed[SPEED_SIZE] = "Unknown";
4620 char fc[FC_SIZE] = "RX/TX";
4621
4622 if (!isup) {
4623 netdev_info(vsi->netdev, "NIC Link is Down\n");
4624 return;
4625 }
4626
148c2d80
GR		 4627 /* Warn user if link speed on NPAR enabled partition is not at
4628 * least 10GB
4629 */
4630 if (vsi->back->hw.func_caps.npar_enable &&
4631 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4632 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4633 netdev_warn(vsi->netdev,
4634 "The partition detected link speed that is less than 10Gbps\n");
4635
cf05ed08
JB		 4636 switch (vsi->back->hw.phy.link_info.link_speed) {
4637 case I40E_LINK_SPEED_40GB:
35a7d804 4638 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4639 break;
4640 case I40E_LINK_SPEED_10GB:
35a7d804 4641 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4642 break;
4643 case I40E_LINK_SPEED_1GB:
35a7d804 4644 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4645 break;
5960d33f
MW		 4646 case I40E_LINK_SPEED_100MB:
4647 strncpy(speed, "100 Mbps", SPEED_SIZE);
4648 break;
cf05ed08
JB		 4649 default:
4650 break;
4651 }
4652
4653 switch (vsi->back->hw.fc.current_mode) {
4654 case I40E_FC_FULL:
35a7d804 4655 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4656 break;
4657 case I40E_FC_TX_PAUSE:
35a7d804 4658 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4659 break;
4660 case I40E_FC_RX_PAUSE:
35a7d804 4661 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4662 break;
4663 default:
35a7d804 4664 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4665 break;
4666 }
4667
4668 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4669 speed, fc);
4670}
4e3b35b0 4671
41c445ff
JB		 4672/**
4673 * i40e_up_complete - Finish the last steps of bringing up a connection
4674 * @vsi: the VSI being configured
4675 **/
4676static int i40e_up_complete(struct i40e_vsi *vsi)
4677{
4678 struct i40e_pf *pf = vsi->back;
4679 int err;
4680
4681 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4682 i40e_vsi_configure_msix(vsi);
4683 else
4684 i40e_configure_msi_and_legacy(vsi);
4685
4686 /* start rings */
4687 err = i40e_vsi_control_rings(vsi, true);
4688 if (err)
4689 return err;
4690
4691 clear_bit(__I40E_DOWN, &vsi->state);
4692 i40e_napi_enable_all(vsi);
4693 i40e_vsi_enable_irq(vsi);
4694
4695 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4696 (vsi->netdev)) {
cf05ed08 4697 i40e_print_link_message(vsi, true);
41c445ff
JB		 4698 netif_tx_start_all_queues(vsi->netdev);
4699 netif_carrier_on(vsi->netdev);
6d779b41 4700 } else if (vsi->netdev) {
cf05ed08 4701 i40e_print_link_message(vsi, false);
7b592f61
CW		 4702 /* need to check for qualified module here*/
4703 if ((pf->hw.phy.link_info.link_info &
4704 I40E_AQ_MEDIA_AVAILABLE) &&
4705 (!(pf->hw.phy.link_info.an_info &
4706 I40E_AQ_QUALIFIED_MODULE)))
4707 netdev_err(vsi->netdev,
4708 "the driver failed to link because an unqualified module was detected.");
41c445ff 4709 }
ca64fa4e
ASJ		 4710
4711 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4712 if (vsi->type == I40E_VSI_FDIR) {
4713 /* reset fd counters */
4714 pf->fd_add_err = pf->fd_atr_cnt = 0;
4715 if (pf->fd_tcp_rule > 0) {
4716 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4717 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4718 pf->fd_tcp_rule = 0;
4719 }
ca64fa4e 4720 i40e_fdir_filter_restore(vsi);
1e1be8f6 4721 }
41c445ff
JB		 4722 i40e_service_event_schedule(pf);
4723
4724 return 0;
4725}
4726
4727/**
4728 * i40e_vsi_reinit_locked - Reset the VSI
4729 * @vsi: the VSI being configured
4730 *
4731 * Rebuild the ring structs after some configuration
4732 * has changed, e.g. MTU size.
4733 **/
4734static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4735{
4736 struct i40e_pf *pf = vsi->back;
4737
4738 WARN_ON(in_interrupt());
4739 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4740 usleep_range(1000, 2000);
4741 i40e_down(vsi);
4742
4743 /* Give a VF some time to respond to the reset. The
4744 * two second wait is based upon the watchdog cycle in
4745 * the VF driver.
4746 */
4747 if (vsi->type == I40E_VSI_SRIOV)
4748 msleep(2000);
4749 i40e_up(vsi);
4750 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4751}
4752
4753/**
4754 * i40e_up - Bring the connection back up after being down
4755 * @vsi: the VSI being configured
4756 **/
4757int i40e_up(struct i40e_vsi *vsi)
4758{
4759 int err;
4760
4761 err = i40e_vsi_configure(vsi);
4762 if (!err)
4763 err = i40e_up_complete(vsi);
4764
4765 return err;
4766}
4767
4768/**
4769 * i40e_down - Shutdown the connection processing
4770 * @vsi: the VSI being stopped
4771 **/
4772void i40e_down(struct i40e_vsi *vsi)
4773{
4774 int i;
4775
4776 /* It is assumed that the caller of this function
4777 * sets the vsi->state __I40E_DOWN bit.
4778 */
4779 if (vsi->netdev) {
4780 netif_carrier_off(vsi->netdev);
4781 netif_tx_disable(vsi->netdev);
4782 }
4783 i40e_vsi_disable_irq(vsi);
4784 i40e_vsi_control_rings(vsi, false);
4785 i40e_napi_disable_all(vsi);
4786
4787 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4788 i40e_clean_tx_ring(vsi->tx_rings[i]);
4789 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4790 }
4791}
4792
4793/**
4794 * i40e_setup_tc - configure multiple traffic classes
4795 * @netdev: net device to configure
4796 * @tc: number of traffic classes to enable
4797 **/
38e00438
VD		 4798#ifdef I40E_FCOE
4799int i40e_setup_tc(struct net_device *netdev, u8 tc)
4800#else
41c445ff 4801static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4802#endif
41c445ff
JB		 4803{
4804 struct i40e_netdev_priv *np = netdev_priv(netdev);
4805 struct i40e_vsi *vsi = np->vsi;
4806 struct i40e_pf *pf = vsi->back;
4807 u8 enabled_tc = 0;
4808 int ret = -EINVAL;
4809 int i;
4810
4811 /* Check if DCB enabled to continue */
4812 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4813 netdev_info(netdev, "DCB is not enabled for adapter\n");
4814 goto exit;
4815 }
4816
4817 /* Check if MFP enabled */
4818 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4819 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4820 goto exit;
4821 }
4822
4823 /* Check whether tc count is within enabled limit */
4824 if (tc > i40e_pf_get_num_tc(pf)) {
4825 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4826 goto exit;
4827 }
4828
4829 /* Generate TC map for number of tc requested */
4830 for (i = 0; i < tc; i++)
4831 enabled_tc |= (1 << i);
4832
4833 /* Requesting same TC configuration as already enabled */
4834 if (enabled_tc == vsi->tc_config.enabled_tc)
4835 return 0;
4836
4837 /* Quiesce VSI queues */
4838 i40e_quiesce_vsi(vsi);
4839
4840 /* Configure VSI for enabled TCs */
4841 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4842 if (ret) {
4843 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4844 vsi->seid);
4845 goto exit;
4846 }
4847
4848 /* Unquiesce VSI */
4849 i40e_unquiesce_vsi(vsi);
4850
4851exit:
4852 return ret;
4853}
4854
4855/**
4856 * i40e_open - Called when a network interface is made active
4857 * @netdev: network interface device structure
4858 *
4859 * The open entry point is called when a network interface is made
4860 * active by the system (IFF_UP). At this point all resources needed
4861 * for transmit and receive operations are allocated, the interrupt
4862 * handler is registered with the OS, the netdev watchdog subtask is
4863 * enabled, and the stack is notified that the interface is ready.
4864 *
4865 * Returns 0 on success, negative value on failure
4866 **/
38e00438 4867int i40e_open(struct net_device *netdev)
41c445ff
JB		 4868{
4869 struct i40e_netdev_priv *np = netdev_priv(netdev);
4870 struct i40e_vsi *vsi = np->vsi;
4871 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4872 int err;
4873
4eb3f768
SN		 4874 /* disallow open during test or if eeprom is broken */
4875 if (test_bit(__I40E_TESTING, &pf->state) ||
4876 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4877 return -EBUSY;
4878
4879 netif_carrier_off(netdev);
4880
6c167f58
EK		 4881 err = i40e_vsi_open(vsi);
4882 if (err)
4883 return err;
4884
059dab69
JB		 4885 /* configure global TSO hardware offload settings */
4886 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4887 TCP_FLAG_FIN) >> 16);
4888 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4889 TCP_FLAG_FIN |
4890 TCP_FLAG_CWR) >> 16);
4891 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4892
6c167f58
EK		 4893#ifdef CONFIG_I40E_VXLAN
4894 vxlan_get_rx_port(netdev);
4895#endif
4896
4897 return 0;
4898}
4899
4900/**
4901 * i40e_vsi_open -
4902 * @vsi: the VSI to open
4903 *
4904 * Finish initialization of the VSI.
4905 *
4906 * Returns 0 on success, negative value on failure
4907 **/
4908int i40e_vsi_open(struct i40e_vsi *vsi)
4909{
4910 struct i40e_pf *pf = vsi->back;
b294ac70 4911 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 4912 int err;
4913
41c445ff
JB		 4914 /* allocate descriptors */
4915 err = i40e_vsi_setup_tx_resources(vsi);
4916 if (err)
4917 goto err_setup_tx;
4918 err = i40e_vsi_setup_rx_resources(vsi);
4919 if (err)
4920 goto err_setup_rx;
4921
4922 err = i40e_vsi_configure(vsi);
4923 if (err)
4924 goto err_setup_rx;
4925
c22e3c6c
SN		 4926 if (vsi->netdev) {
4927 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4928 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4929 err = i40e_vsi_request_irq(vsi, int_name);
4930 if (err)
4931 goto err_setup_rx;
41c445ff 4932
c22e3c6c
SN		 4933 /* Notify the stack of the actual queue counts. */
4934 err = netif_set_real_num_tx_queues(vsi->netdev,
4935 vsi->num_queue_pairs);
4936 if (err)
4937 goto err_set_queues;
25946ddb 4938
c22e3c6c
SN		 4939 err = netif_set_real_num_rx_queues(vsi->netdev,
4940 vsi->num_queue_pairs);
4941 if (err)
4942 goto err_set_queues;
8a9eb7d3
SN		 4943
4944 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 4945 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 4946 dev_driver_string(&pf->pdev->dev),
4947 dev_name(&pf->pdev->dev));
8a9eb7d3 4948 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 4949
c22e3c6c 4950 } else {
ce9ccb17 4951 err = -EINVAL;
6c167f58
EK		 4952 goto err_setup_rx;
4953 }
25946ddb 4954
41c445ff
JB		 4955 err = i40e_up_complete(vsi);
4956 if (err)
4957 goto err_up_complete;
4958
41c445ff
JB		 4959 return 0;
4960
4961err_up_complete:
4962 i40e_down(vsi);
25946ddb 4963err_set_queues:
41c445ff
JB		 4964 i40e_vsi_free_irq(vsi);
4965err_setup_rx:
4966 i40e_vsi_free_rx_resources(vsi);
4967err_setup_tx:
4968 i40e_vsi_free_tx_resources(vsi);
4969 if (vsi == pf->vsi[pf->lan_vsi])
4970 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4971
4972 return err;
4973}
4974
17a73f6b
JG		 4975/**
4976 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4977 * @pf: Pointer to pf
4978 *
4979 * This function destroys the hlist where all the Flow Director
4980 * filters were saved.
4981 **/
4982static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4983{
4984 struct i40e_fdir_filter *filter;
4985 struct hlist_node *node2;
4986
4987 hlist_for_each_entry_safe(filter, node2,
4988 &pf->fdir_filter_list, fdir_node) {
4989 hlist_del(&filter->fdir_node);
4990 kfree(filter);
4991 }
4992 pf->fdir_pf_active_filters = 0;
4993}
4994
41c445ff
JB		 4995/**
4996 * i40e_close - Disables a network interface
4997 * @netdev: network interface device structure
4998 *
4999 * The close entry point is called when an interface is de-activated
5000 * by the OS. The hardware is still under the driver's control, but
5001 * this netdev interface is disabled.
5002 *
5003 * Returns 0, this is not allowed to fail
5004 **/
38e00438
VD		 5005#ifdef I40E_FCOE
5006int i40e_close(struct net_device *netdev)
5007#else
41c445ff 5008static int i40e_close(struct net_device *netdev)
38e00438 5009#endif
41c445ff
JB		 5010{
5011 struct i40e_netdev_priv *np = netdev_priv(netdev);
5012 struct i40e_vsi *vsi = np->vsi;
5013
90ef8d47 5014 i40e_vsi_close(vsi);
41c445ff
JB		 5015
5016 return 0;
5017}
5018
5019/**
5020 * i40e_do_reset - Start a PF or Core Reset sequence
5021 * @pf: board private structure
5022 * @reset_flags: which reset is requested
5023 *
5024 * The essential difference in resets is that the PF Reset
5025 * doesn't clear the packet buffers, doesn't reset the PE
5026 * firmware, and doesn't bother the other PFs on the chip.
5027 **/
5028void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5029{
5030 u32 val;
5031
5032 WARN_ON(in_interrupt());
5033
263fc48f
MW		 5034 if (i40e_check_asq_alive(&pf->hw))
5035 i40e_vc_notify_reset(pf);
5036
41c445ff
JB		 5037 /* do the biggest reset indicated */
5038 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
5039
5040 /* Request a Global Reset
5041 *
5042 * This will start the chip's countdown to the actual full
5043 * chip reset event, and a warning interrupt to be sent
5044 * to all PFs, including the requestor. Our handler
5045 * for the warning interrupt will deal with the shutdown
5046 * and recovery of the switch setup.
5047 */
69bfb110 5048 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5049 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5050 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5051 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5052
5053 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
5054
5055 /* Request a Core Reset
5056 *
5057 * Same as Global Reset, except does *not* include the MAC/PHY
5058 */
69bfb110 5059 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5060 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5061 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5062 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5063 i40e_flush(&pf->hw);
5064
5065 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
5066
5067 /* Request a PF Reset
5068 *
5069 * Resets only the PF-specific registers
5070 *
5071 * This goes directly to the tear-down and rebuild of
5072 * the switch, since we need to do all the recovery as
5073 * for the Core Reset.
5074 */
69bfb110 5075 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5076 i40e_handle_reset_warning(pf);
5077
5078 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
5079 int v;
5080
5081 /* Find the VSI(s) that requested a re-init */
5082 dev_info(&pf->pdev->dev,
5083 "VSI reinit requested\n");
505682cd 5084 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5085 struct i40e_vsi *vsi = pf->vsi[v];
5086 if (vsi != NULL &&
5087 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5088 i40e_vsi_reinit_locked(pf->vsi[v]);
5089 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5090 }
5091 }
5092
b5d06f05
NP		 5093 /* no further action needed, so return now */
5094 return;
5095 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
5096 int v;
5097
5098 /* Find the VSI(s) that needs to be brought down */
5099 dev_info(&pf->pdev->dev, "VSI down requested\n");
5100 for (v = 0; v < pf->num_alloc_vsi; v++) {
5101 struct i40e_vsi *vsi = pf->vsi[v];
5102 if (vsi != NULL &&
5103 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5104 set_bit(__I40E_DOWN, &vsi->state);
5105 i40e_down(vsi);
5106 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5107 }
5108 }
5109
41c445ff
JB		 5110 /* no further action needed, so return now */
5111 return;
5112 } else {
5113 dev_info(&pf->pdev->dev,
5114 "bad reset request 0x%08x\n", reset_flags);
5115 return;
5116 }
5117}
5118
4e3b35b0
NP		 5119#ifdef CONFIG_I40E_DCB
5120/**
5121 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5122 * @pf: board private structure
5123 * @old_cfg: current DCB config
5124 * @new_cfg: new DCB config
5125 **/
5126bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5127 struct i40e_dcbx_config *old_cfg,
5128 struct i40e_dcbx_config *new_cfg)
5129{
5130 bool need_reconfig = false;
5131
5132 /* Check if ETS configuration has changed */
5133 if (memcmp(&new_cfg->etscfg,
5134 &old_cfg->etscfg,
5135 sizeof(new_cfg->etscfg))) {
5136 /* If Priority Table has changed reconfig is needed */
5137 if (memcmp(&new_cfg->etscfg.prioritytable,
5138 &old_cfg->etscfg.prioritytable,
5139 sizeof(new_cfg->etscfg.prioritytable))) {
5140 need_reconfig = true;
69bfb110 5141 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5142 }
5143
5144 if (memcmp(&new_cfg->etscfg.tcbwtable,
5145 &old_cfg->etscfg.tcbwtable,
5146 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5147 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5148
5149 if (memcmp(&new_cfg->etscfg.tsatable,
5150 &old_cfg->etscfg.tsatable,
5151 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5152 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5153 }
5154
5155 /* Check if PFC configuration has changed */
5156 if (memcmp(&new_cfg->pfc,
5157 &old_cfg->pfc,
5158 sizeof(new_cfg->pfc))) {
5159 need_reconfig = true;
69bfb110 5160 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5161 }
5162
5163 /* Check if APP Table has changed */
5164 if (memcmp(&new_cfg->app,
5165 &old_cfg->app,
3d9667a9 5166 sizeof(new_cfg->app))) {
4e3b35b0 5167 need_reconfig = true;
69bfb110 5168 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5169 }
4e3b35b0 5170
9fa61dd2
NP		 5171 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5172 need_reconfig);
4e3b35b0
NP		 5173 return need_reconfig;
5174}
5175
5176/**
5177 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5178 * @pf: board private structure
5179 * @e: event info posted on ARQ
5180 **/
5181static int i40e_handle_lldp_event(struct i40e_pf *pf,
5182 struct i40e_arq_event_info *e)
5183{
5184 struct i40e_aqc_lldp_get_mib *mib =
5185 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5186 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5187 struct i40e_dcbx_config tmp_dcbx_cfg;
5188 bool need_reconfig = false;
5189 int ret = 0;
5190 u8 type;
5191
4d9b6043
NP		 5192 /* Not DCB capable or capability disabled */
5193 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5194 return ret;
5195
4e3b35b0
NP		 5196 /* Ignore if event is not for Nearest Bridge */
5197 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5198 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5199 dev_dbg(&pf->pdev->dev,
5200 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5201 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5202 return ret;
5203
5204 /* Check MIB Type and return if event for Remote MIB update */
5205 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5206 dev_dbg(&pf->pdev->dev,
5207 "%s: LLDP event mib type %s\n", __func__,
5208 type ? "remote" : "local");
4e3b35b0
NP		 5209 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5210 /* Update the remote cached instance and return */
5211 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5212 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5213 &hw->remote_dcbx_config);
5214 goto exit;
5215 }
5216
4e3b35b0 5217 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
9fa61dd2 5218 /* Store the old configuration */
750fcbcf 5219 memcpy(&tmp_dcbx_cfg, &hw->local_dcbx_config, sizeof(tmp_dcbx_cfg));
9fa61dd2 5220
750fcbcf
NP		 5221 /* Reset the old DCBx configuration data */
5222 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5223 /* Get updated DCBX data from firmware */
5224 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5225 if (ret) {
9fa61dd2 5226 dev_info(&pf->pdev->dev, "Failed querying DCB configuration data from firmware.\n");
4e3b35b0
NP		 5227 goto exit;
5228 }
5229
5230 /* No change detected in DCBX configs */
750fcbcf
NP		 5231 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5232 sizeof(tmp_dcbx_cfg))) {
69bfb110 5233 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5234 goto exit;
5235 }
5236
750fcbcf
NP		 5237 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5238 &hw->local_dcbx_config);
4e3b35b0 5239
750fcbcf 5240 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5241
5242 if (!need_reconfig)
5243 goto exit;
5244
4d9b6043 5245 /* Enable DCB tagging only when more than one TC */
750fcbcf 5246 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5247 pf->flags |= I40E_FLAG_DCB_ENABLED;
5248 else
5249 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5250
69129dc3 5251 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5252 /* Reconfiguration needed quiesce all VSIs */
5253 i40e_pf_quiesce_all_vsi(pf);
5254
5255 /* Changes in configuration update VEB/VSI */
5256 i40e_dcb_reconfigure(pf);
5257
2fd75f31
NP		 5258 ret = i40e_resume_port_tx(pf);
5259
69129dc3 5260 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5261 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5262 if (ret)
5263 goto exit;
5264
5265 /* Wait for the PF's Tx queues to be disabled */
5266 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5267 if (ret) {
5268 /* Schedule PF reset to recover */
5269 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5270 i40e_service_event_schedule(pf);
5271 } else {
2fd75f31 5272 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5273 }
5274
4e3b35b0
NP		 5275exit:
5276 return ret;
5277}
5278#endif /* CONFIG_I40E_DCB */
5279
23326186
ASJ		 5280/**
5281 * i40e_do_reset_safe - Protected reset path for userland calls.
5282 * @pf: board private structure
5283 * @reset_flags: which reset is requested
5284 *
5285 **/
5286void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5287{
5288 rtnl_lock();
5289 i40e_do_reset(pf, reset_flags);
5290 rtnl_unlock();
5291}
5292
41c445ff
JB		 5293/**
5294 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5295 * @pf: board private structure
5296 * @e: event info posted on ARQ
5297 *
5298 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5299 * and VF queues
5300 **/
5301static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5302 struct i40e_arq_event_info *e)
5303{
5304 struct i40e_aqc_lan_overflow *data =
5305 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5306 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5307 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5308 struct i40e_hw *hw = &pf->hw;
5309 struct i40e_vf *vf;
5310 u16 vf_id;
5311
69bfb110
JB		 5312 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5313 queue, qtx_ctl);
41c445ff
JB		 5314
5315 /* Queue belongs to VF, find the VF and issue VF reset */
5316 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5317 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5318 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5319 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5320 vf_id -= hw->func_caps.vf_base_id;
5321 vf = &pf->vf[vf_id];
5322 i40e_vc_notify_vf_reset(vf);
5323 /* Allow VF to process pending reset notification */
5324 msleep(20);
5325 i40e_reset_vf(vf, false);
5326 }
5327}
5328
5329/**
5330 * i40e_service_event_complete - Finish up the service event
5331 * @pf: board private structure
5332 **/
5333static void i40e_service_event_complete(struct i40e_pf *pf)
5334{
5335 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5336
5337 /* flush memory to make sure state is correct before next watchog */
4e857c58 5338 smp_mb__before_atomic();
41c445ff
JB		 5339 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5340}
5341
55a5e60b 5342/**
12957388
ASJ		 5343 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5344 * @pf: board private structure
5345 **/
5346int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
5347{
5348 int val, fcnt_prog;
5349
5350 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5351 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5352 return fcnt_prog;
5353}
5354
5355/**
5356 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 5357 * @pf: board private structure
5358 **/
5359int i40e_get_current_fd_count(struct i40e_pf *pf)
5360{
5361 int val, fcnt_prog;
5362 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5363 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5364 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5365 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5366 return fcnt_prog;
5367}
1e1be8f6 5368
55a5e60b
ASJ		 5369/**
5370 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5371 * @pf: board private structure
5372 **/
5373void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5374{
5375 u32 fcnt_prog, fcnt_avail;
5376
1e1be8f6
ASJ		 5377 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5378 return;
5379
55a5e60b
ASJ		 5380 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5381 * to re-enable
5382 */
12957388
ASJ		 5383 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5384 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5385 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5386 (pf->fd_add_err == 0) ||
5387 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5388 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5389 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5390 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5391 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5392 }
5393 }
5394 /* Wait for some more space to be available to turn on ATR */
5395 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5396 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5397 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5398 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5399 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5400 }
5401 }
5402}
5403
1e1be8f6
ASJ		 5404#define I40E_MIN_FD_FLUSH_INTERVAL 10
5405/**
5406 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5407 * @pf: board private structure
5408 **/
5409static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5410{
5411 int flush_wait_retry = 50;
5412 int reg;
5413
1790ed0c
AA		 5414 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5415 return;
5416
1e1be8f6
ASJ		 5417 if (time_after(jiffies, pf->fd_flush_timestamp +
5418 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
5419 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5420 pf->fd_flush_timestamp = jiffies;
5421 pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
5422 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5423 /* flush all filters */
5424 wr32(&pf->hw, I40E_PFQF_CTL_1,
5425 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5426 i40e_flush(&pf->hw);
60793f4a 5427 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5428 pf->fd_add_err = 0;
5429 do {
5430 /* Check FD flush status every 5-6msec */
5431 usleep_range(5000, 6000);
5432 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5433 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5434 break;
5435 } while (flush_wait_retry--);
5436 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5437 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5438 } else {
5439 /* replay sideband filters */
5440 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5441
5442 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5443 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5444 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5445 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5446 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5447 }
5448 }
5449}
5450
5451/**
5452 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5453 * @pf: board private structure
5454 **/
5455int i40e_get_current_atr_cnt(struct i40e_pf *pf)
5456{
5457 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5458}
5459
5460/* We can see up to 256 filter programming desc in transit if the filters are
5461 * being applied really fast; before we see the first
5462 * filter miss error on Rx queue 0. Accumulating enough error messages before
5463 * reacting will make sure we don't cause flush too often.
5464 */
5465#define I40E_MAX_FD_PROGRAM_ERROR 256
5466
41c445ff
JB		 5467/**
5468 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5469 * @pf: board private structure
5470 **/
5471static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5472{
41c445ff 5473
41c445ff
JB		 5474 /* if interface is down do nothing */
5475 if (test_bit(__I40E_DOWN, &pf->state))
5476 return;
1e1be8f6 5477
1790ed0c
AA		 5478 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5479 return;
5480
1e1be8f6
ASJ		 5481 if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
5482 (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
5483 (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
5484 i40e_fdir_flush_and_replay(pf);
5485
55a5e60b
ASJ		 5486 i40e_fdir_check_and_reenable(pf);
5487
41c445ff
JB		 5488}
5489
5490/**
5491 * i40e_vsi_link_event - notify VSI of a link event
5492 * @vsi: vsi to be notified
5493 * @link_up: link up or down
5494 **/
5495static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5496{
32b5b811 5497 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5498 return;
5499
5500 switch (vsi->type) {
5501 case I40E_VSI_MAIN:
38e00438
VD		 5502#ifdef I40E_FCOE
5503 case I40E_VSI_FCOE:
5504#endif
41c445ff
JB		 5505 if (!vsi->netdev || !vsi->netdev_registered)
5506 break;
5507
5508 if (link_up) {
5509 netif_carrier_on(vsi->netdev);
5510 netif_tx_wake_all_queues(vsi->netdev);
5511 } else {
5512 netif_carrier_off(vsi->netdev);
5513 netif_tx_stop_all_queues(vsi->netdev);
5514 }
5515 break;
5516
5517 case I40E_VSI_SRIOV:
41c445ff
JB		 5518 case I40E_VSI_VMDQ2:
5519 case I40E_VSI_CTRL:
5520 case I40E_VSI_MIRROR:
5521 default:
5522 /* there is no notification for other VSIs */
5523 break;
5524 }
5525}
5526
5527/**
5528 * i40e_veb_link_event - notify elements on the veb of a link event
5529 * @veb: veb to be notified
5530 * @link_up: link up or down
5531 **/
5532static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5533{
5534 struct i40e_pf *pf;
5535 int i;
5536
5537 if (!veb || !veb->pf)
5538 return;
5539 pf = veb->pf;
5540
5541 /* depth first... */
5542 for (i = 0; i < I40E_MAX_VEB; i++)
5543 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5544 i40e_veb_link_event(pf->veb[i], link_up);
5545
5546 /* ... now the local VSIs */
505682cd 5547 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5548 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5549 i40e_vsi_link_event(pf->vsi[i], link_up);
5550}
5551
5552/**
5553 * i40e_link_event - Update netif_carrier status
5554 * @pf: board private structure
5555 **/
5556static void i40e_link_event(struct i40e_pf *pf)
5557{
5558 bool new_link, old_link;
320684cd 5559 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5560 u8 new_link_speed, old_link_speed;
41c445ff 5561
1e701e09
JB		 5562 /* set this to force the get_link_status call to refresh state */
5563 pf->hw.phy.get_link_info = true;
5564
41c445ff 5565 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5566 new_link = i40e_get_link_status(&pf->hw);
fef59ddf
CS		 5567 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5568 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5569
1e701e09 5570 if (new_link == old_link &&
fef59ddf 5571 new_link_speed == old_link_speed &&
320684cd
MW		 5572 (test_bit(__I40E_DOWN, &vsi->state) ||
5573 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5574 return;
320684cd
MW		 5575
5576 if (!test_bit(__I40E_DOWN, &vsi->state))
5577 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5578
5579 /* Notify the base of the switch tree connected to
5580 * the link. Floating VEBs are not notified.
5581 */
5582 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5583 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5584 else
320684cd 5585 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5586
5587 if (pf->vf)
5588 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5589
5590 if (pf->flags & I40E_FLAG_PTP)
5591 i40e_ptp_set_increment(pf);
41c445ff
JB		 5592}
5593
5594/**
5595 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5596 * @pf: board private structure
5597 *
5598 * Set the per-queue flags to request a check for stuck queues in the irq
5599 * clean functions, then force interrupts to be sure the irq clean is called.
5600 **/
5601static void i40e_check_hang_subtask(struct i40e_pf *pf)
5602{
5603 int i, v;
5604
5605 /* If we're down or resetting, just bail */
b67a0335
AA		 5606 if (test_bit(__I40E_DOWN, &pf->state) ||
5607 test_bit(__I40E_CONFIG_BUSY, &pf->state))
41c445ff
JB		 5608 return;
5609
5610 /* for each VSI/netdev
5611 * for each Tx queue
5612 * set the check flag
5613 * for each q_vector
5614 * force an interrupt
5615 */
505682cd 5616 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5617 struct i40e_vsi *vsi = pf->vsi[v];
5618 int armed = 0;
5619
5620 if (!pf->vsi[v] ||
5621 test_bit(__I40E_DOWN, &vsi->state) ||
5622 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5623 continue;
5624
5625 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5626 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5627 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5628 &vsi->tx_rings[i]->state))
41c445ff
JB		 5629 armed++;
5630 }
5631
5632 if (armed) {
5633 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5634 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5635 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5d1ff106
SN		 5636 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
5637 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
5638 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
5639 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
41c445ff
JB		 5640 } else {
5641 u16 vec = vsi->base_vector - 1;
5642 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5d1ff106
SN		 5643 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
5644 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK |
5645 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK |
5646 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK);
41c445ff
JB		 5647 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5648 wr32(&vsi->back->hw,
5649 I40E_PFINT_DYN_CTLN(vec), val);
5650 }
5651 i40e_flush(&vsi->back->hw);
5652 }
5653 }
5654}
5655
5656/**
21536717 5657 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5658 * @pf: board private structure
5659 **/
5660static void i40e_watchdog_subtask(struct i40e_pf *pf)
5661{
5662 int i;
5663
5664 /* if interface is down do nothing */
5665 if (test_bit(__I40E_DOWN, &pf->state) ||
5666 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5667 return;
5668
21536717
SN		 5669 /* make sure we don't do these things too often */
5670 if (time_before(jiffies, (pf->service_timer_previous +
5671 pf->service_timer_period)))
5672 return;
5673 pf->service_timer_previous = jiffies;
5674
5675 i40e_check_hang_subtask(pf);
5676 i40e_link_event(pf);
5677
41c445ff
JB		 5678 /* Update the stats for active netdevs so the network stack
5679 * can look at updated numbers whenever it cares to
5680 */
505682cd 5681 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5682 if (pf->vsi[i] && pf->vsi[i]->netdev)
5683 i40e_update_stats(pf->vsi[i]);
5684
5685 /* Update the stats for the active switching components */
5686 for (i = 0; i < I40E_MAX_VEB; i++)
5687 if (pf->veb[i])
5688 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5689
5690 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5691}
5692
5693/**
5694 * i40e_reset_subtask - Set up for resetting the device and driver
5695 * @pf: board private structure
5696 **/
5697static void i40e_reset_subtask(struct i40e_pf *pf)
5698{
5699 u32 reset_flags = 0;
5700
23326186 5701 rtnl_lock();
41c445ff
JB		 5702 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5703 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5704 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5705 }
5706 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5707 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5708 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5709 }
5710 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5711 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5712 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5713 }
5714 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5715 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5716 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5717 }
b5d06f05
NP		 5718 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5719 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5720 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5721 }
41c445ff
JB		 5722
5723 /* If there's a recovery already waiting, it takes
5724 * precedence before starting a new reset sequence.
5725 */
5726 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5727 i40e_handle_reset_warning(pf);
23326186 5728 goto unlock;
41c445ff
JB		 5729 }
5730
5731 /* If we're already down or resetting, just bail */
5732 if (reset_flags &&
5733 !test_bit(__I40E_DOWN, &pf->state) &&
5734 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5735 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5736
5737unlock:
5738 rtnl_unlock();
41c445ff
JB		 5739}
5740
5741/**
5742 * i40e_handle_link_event - Handle link event
5743 * @pf: board private structure
5744 * @e: event info posted on ARQ
5745 **/
5746static void i40e_handle_link_event(struct i40e_pf *pf,
5747 struct i40e_arq_event_info *e)
5748{
5749 struct i40e_hw *hw = &pf->hw;
5750 struct i40e_aqc_get_link_status *status =
5751 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5752 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5753
5754 /* save off old link status information */
5755 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5756 sizeof(pf->hw.phy.link_info_old));
5757
1e701e09
JB		 5758 /* Do a new status request to re-enable LSE reporting
5759 * and load new status information into the hw struct
5760 * This completely ignores any state information
5761 * in the ARQ event info, instead choosing to always
5762 * issue the AQ update link status command.
5763 */
5764 i40e_link_event(pf);
5765
7b592f61
CW		 5766 /* check for unqualified module, if link is down */
5767 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5768 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5769 (!(status->link_info & I40E_AQ_LINK_UP)))
5770 dev_err(&pf->pdev->dev,
5771 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5772}
5773
5774/**
5775 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5776 * @pf: board private structure
5777 **/
5778static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5779{
5780 struct i40e_arq_event_info event;
5781 struct i40e_hw *hw = &pf->hw;
5782 u16 pending, i = 0;
5783 i40e_status ret;
5784 u16 opcode;
86df242b 5785 u32 oldval;
41c445ff
JB		 5786 u32 val;
5787
a316f651
ASJ		 5788 /* Do not run clean AQ when PF reset fails */
5789 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5790 return;
5791
86df242b
SN		 5792 /* check for error indications */
5793 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5794 oldval = val;
5795 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5796 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5797 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5798 }
5799 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5800 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5801 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5802 }
5803 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5804 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5805 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5806 }
5807 if (oldval != val)
5808 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5809
5810 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5811 oldval = val;
5812 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5813 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5814 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5815 }
5816 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5817 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5818 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5819 }
5820 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5821 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5822 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5823 }
5824 if (oldval != val)
5825 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5826
1001dc37
MW		 5827 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
5828 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 5829 if (!event.msg_buf)
5830 return;
5831
5832 do {
5833 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5834 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5835 break;
56497978 5836 else if (ret) {
41c445ff
JB		 5837 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5838 break;
5839 }
5840
5841 opcode = le16_to_cpu(event.desc.opcode);
5842 switch (opcode) {
5843
5844 case i40e_aqc_opc_get_link_status:
5845 i40e_handle_link_event(pf, &event);
5846 break;
5847 case i40e_aqc_opc_send_msg_to_pf:
5848 ret = i40e_vc_process_vf_msg(pf,
5849 le16_to_cpu(event.desc.retval),
5850 le32_to_cpu(event.desc.cookie_high),
5851 le32_to_cpu(event.desc.cookie_low),
5852 event.msg_buf,
1001dc37 5853 event.msg_len);
41c445ff
JB		 5854 break;
5855 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5856 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5857#ifdef CONFIG_I40E_DCB
5858 rtnl_lock();
5859 ret = i40e_handle_lldp_event(pf, &event);
5860 rtnl_unlock();
5861#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5862 break;
5863 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5864 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5865 i40e_handle_lan_overflow_event(pf, &event);
5866 break;
0467bc91
SN		 5867 case i40e_aqc_opc_send_msg_to_peer:
5868 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5869 break;
41c445ff
JB		 5870 default:
5871 dev_info(&pf->pdev->dev,
0467bc91
SN		 5872 "ARQ Error: Unknown event 0x%04x received\n",
5873 opcode);
41c445ff
JB		 5874 break;
5875 }
5876 } while (pending && (i++ < pf->adminq_work_limit));
5877
5878 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5879 /* re-enable Admin queue interrupt cause */
5880 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5881 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5882 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5883 i40e_flush(hw);
5884
5885 kfree(event.msg_buf);
5886}
5887
4eb3f768
SN		 5888/**
5889 * i40e_verify_eeprom - make sure eeprom is good to use
5890 * @pf: board private structure
5891 **/
5892static void i40e_verify_eeprom(struct i40e_pf *pf)
5893{
5894 int err;
5895
5896 err = i40e_diag_eeprom_test(&pf->hw);
5897 if (err) {
5898 /* retry in case of garbage read */
5899 err = i40e_diag_eeprom_test(&pf->hw);
5900 if (err) {
5901 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5902 err);
5903 set_bit(__I40E_BAD_EEPROM, &pf->state);
5904 }
5905 }
5906
5907 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5908 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5909 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5910 }
5911}
5912
51616018
NP		 5913/**
5914 * i40e_config_bridge_mode - Configure the HW bridge mode
5915 * @veb: pointer to the bridge instance
5916 *
5917 * Configure the loop back mode for the LAN VSI that is downlink to the
5918 * specified HW bridge instance. It is expected this function is called
5919 * when a new HW bridge is instantiated.
5920 **/
5921static void i40e_config_bridge_mode(struct i40e_veb *veb)
5922{
5923 struct i40e_pf *pf = veb->pf;
5924
5925 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
5926 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
5927 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
5928 i40e_disable_pf_switch_lb(pf);
5929 else
5930 i40e_enable_pf_switch_lb(pf);
5931}
5932
41c445ff
JB		 5933/**
5934 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5935 * @veb: pointer to the VEB instance
5936 *
5937 * This is a recursive function that first builds the attached VSIs then
5938 * recurses in to build the next layer of VEB. We track the connections
5939 * through our own index numbers because the seid's from the HW could
5940 * change across the reset.
5941 **/
5942static int i40e_reconstitute_veb(struct i40e_veb *veb)
5943{
5944 struct i40e_vsi *ctl_vsi = NULL;
5945 struct i40e_pf *pf = veb->pf;
5946 int v, veb_idx;
5947 int ret;
5948
5949 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5950 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5951 if (pf->vsi[v] &&
5952 pf->vsi[v]->veb_idx == veb->idx &&
5953 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5954 ctl_vsi = pf->vsi[v];
5955 break;
5956 }
5957 }
5958 if (!ctl_vsi) {
5959 dev_info(&pf->pdev->dev,
5960 "missing owner VSI for veb_idx %d\n", veb->idx);
5961 ret = -ENOENT;
5962 goto end_reconstitute;
5963 }
5964 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5965 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5966 ret = i40e_add_vsi(ctl_vsi);
5967 if (ret) {
5968 dev_info(&pf->pdev->dev,
5969 "rebuild of owner VSI failed: %d\n", ret);
5970 goto end_reconstitute;
5971 }
5972 i40e_vsi_reset_stats(ctl_vsi);
5973
5974 /* create the VEB in the switch and move the VSI onto the VEB */
5975 ret = i40e_add_veb(veb, ctl_vsi);
5976 if (ret)
5977 goto end_reconstitute;
5978
51616018 5979 i40e_config_bridge_mode(veb);
b64ba084 5980
41c445ff 5981 /* create the remaining VSIs attached to this VEB */
505682cd 5982 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5983 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5984 continue;
5985
5986 if (pf->vsi[v]->veb_idx == veb->idx) {
5987 struct i40e_vsi *vsi = pf->vsi[v];
5988 vsi->uplink_seid = veb->seid;
5989 ret = i40e_add_vsi(vsi);
5990 if (ret) {
5991 dev_info(&pf->pdev->dev,
5992 "rebuild of vsi_idx %d failed: %d\n",
5993 v, ret);
5994 goto end_reconstitute;
5995 }
5996 i40e_vsi_reset_stats(vsi);
5997 }
5998 }
5999
6000 /* create any VEBs attached to this VEB - RECURSION */
6001 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6002 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6003 pf->veb[veb_idx]->uplink_seid = veb->seid;
6004 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6005 if (ret)
6006 break;
6007 }
6008 }
6009
6010end_reconstitute:
6011 return ret;
6012}
6013
6014/**
6015 * i40e_get_capabilities - get info about the HW
6016 * @pf: the PF struct
6017 **/
6018static int i40e_get_capabilities(struct i40e_pf *pf)
6019{
6020 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6021 u16 data_size;
6022 int buf_len;
6023 int err;
6024
6025 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6026 do {
6027 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6028 if (!cap_buf)
6029 return -ENOMEM;
6030
6031 /* this loads the data into the hw struct for us */
6032 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6033 &data_size,
6034 i40e_aqc_opc_list_func_capabilities,
6035 NULL);
6036 /* data loaded, buffer no longer needed */
6037 kfree(cap_buf);
6038
6039 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6040 /* retry with a larger buffer */
6041 buf_len = data_size;
6042 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6043 dev_info(&pf->pdev->dev,
6044 "capability discovery failed: aq=%d\n",
6045 pf->hw.aq.asq_last_status);
6046 return -ENODEV;
6047 }
6048 } while (err);
6049
ac71b7ba
ASJ		 6050 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6051 (pf->hw.aq.fw_maj_ver < 2)) {
6052 pf->hw.func_caps.num_msix_vectors++;
6053 pf->hw.func_caps.num_msix_vectors_vf++;
6054 }
6055
41c445ff
JB		 6056 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6057 dev_info(&pf->pdev->dev,
6058 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6059 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6060 pf->hw.func_caps.num_msix_vectors,
6061 pf->hw.func_caps.num_msix_vectors_vf,
6062 pf->hw.func_caps.fd_filters_guaranteed,
6063 pf->hw.func_caps.fd_filters_best_effort,
6064 pf->hw.func_caps.num_tx_qp,
6065 pf->hw.func_caps.num_vsis);
6066
7134f9ce
JB		 6067#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6068 + pf->hw.func_caps.num_vfs)
6069 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6070 dev_info(&pf->pdev->dev,
6071 "got num_vsis %d, setting num_vsis to %d\n",
6072 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6073 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6074 }
6075
41c445ff
JB		 6076 return 0;
6077}
6078
cbf61325
ASJ		 6079static int i40e_vsi_clear(struct i40e_vsi *vsi);
6080
41c445ff 6081/**
cbf61325 6082 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6083 * @pf: board private structure
6084 **/
cbf61325 6085static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6086{
6087 struct i40e_vsi *vsi;
8a9eb7d3 6088 int i;
41c445ff 6089
407e063c
JB		 6090 /* quick workaround for an NVM issue that leaves a critical register
6091 * uninitialized
6092 */
6093 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6094 static const u32 hkey[] = {
6095 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6096 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6097 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6098 0x95b3a76d};
6099
6100 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6101 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6102 }
6103
cbf61325 6104 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6105 return;
6106
cbf61325 6107 /* find existing VSI and see if it needs configuring */
41c445ff 6108 vsi = NULL;
505682cd 6109 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6110 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6111 vsi = pf->vsi[i];
cbf61325
ASJ		 6112 break;
6113 }
6114 }
6115
6116 /* create a new VSI if none exists */
41c445ff 6117 if (!vsi) {
cbf61325
ASJ		 6118 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6119 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6120 if (!vsi) {
6121 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6122 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6123 return;
41c445ff 6124 }
cbf61325 6125 }
41c445ff 6126
8a9eb7d3 6127 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6128}
6129
6130/**
6131 * i40e_fdir_teardown - release the Flow Director resources
6132 * @pf: board private structure
6133 **/
6134static void i40e_fdir_teardown(struct i40e_pf *pf)
6135{
6136 int i;
6137
17a73f6b 6138 i40e_fdir_filter_exit(pf);
505682cd 6139 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6140 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6141 i40e_vsi_release(pf->vsi[i]);
6142 break;
6143 }
6144 }
6145}
6146
6147/**
f650a38b 6148 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6149 * @pf: board private structure
6150 *
f650a38b
ASJ		 6151 * Close up the VFs and other things in prep for pf Reset.
6152 **/
23cfbe07 6153static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6154{
41c445ff 6155 struct i40e_hw *hw = &pf->hw;
60442dea 6156 i40e_status ret = 0;
41c445ff
JB		 6157 u32 v;
6158
6159 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6160 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6161 return;
41c445ff 6162
69bfb110 6163 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6164
41c445ff
JB		 6165 /* quiesce the VSIs and their queues that are not already DOWN */
6166 i40e_pf_quiesce_all_vsi(pf);
6167
505682cd 6168 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6169 if (pf->vsi[v])
6170 pf->vsi[v]->seid = 0;
6171 }
6172
6173 i40e_shutdown_adminq(&pf->hw);
6174
f650a38b 6175 /* call shutdown HMC */
60442dea
SN		 6176 if (hw->hmc.hmc_obj) {
6177 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6178 if (ret)
60442dea
SN		 6179 dev_warn(&pf->pdev->dev,
6180 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6181 }
f650a38b
ASJ		 6182}
6183
44033fac
JB		 6184/**
6185 * i40e_send_version - update firmware with driver version
6186 * @pf: PF struct
6187 */
6188static void i40e_send_version(struct i40e_pf *pf)
6189{
6190 struct i40e_driver_version dv;
6191
6192 dv.major_version = DRV_VERSION_MAJOR;
6193 dv.minor_version = DRV_VERSION_MINOR;
6194 dv.build_version = DRV_VERSION_BUILD;
6195 dv.subbuild_version = 0;
35a7d804 6196 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6197 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6198}
6199
f650a38b 6200/**
4dda12e6 6201 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6202 * @pf: board private structure
bc7d338f 6203 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6204 **/
bc7d338f 6205static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6206{
f650a38b 6207 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6208 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6209 i40e_status ret;
6210 u32 v;
6211
41c445ff
JB		 6212 /* Now we wait for GRST to settle out.
6213 * We don't have to delete the VEBs or VSIs from the hw switch
6214 * because the reset will make them disappear.
6215 */
6216 ret = i40e_pf_reset(hw);
b5565400 6217 if (ret) {
41c445ff 6218 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6219 set_bit(__I40E_RESET_FAILED, &pf->state);
6220 goto clear_recovery;
b5565400 6221 }
41c445ff
JB		 6222 pf->pfr_count++;
6223
6224 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6225 goto clear_recovery;
69bfb110 6226 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6227
6228 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6229 ret = i40e_init_adminq(&pf->hw);
6230 if (ret) {
6231 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 6232 goto clear_recovery;
41c445ff
JB		 6233 }
6234
4eb3f768 6235 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6236 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6237 i40e_verify_eeprom(pf);
4eb3f768 6238
e78ac4bf 6239 i40e_clear_pxe_mode(hw);
41c445ff
JB		 6240 ret = i40e_get_capabilities(pf);
6241 if (ret) {
6242 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
6243 ret);
6244 goto end_core_reset;
6245 }
6246
41c445ff
JB		 6247 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6248 hw->func_caps.num_rx_qp,
6249 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6250 if (ret) {
6251 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6252 goto end_core_reset;
6253 }
6254 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6255 if (ret) {
6256 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6257 goto end_core_reset;
6258 }
6259
4e3b35b0
NP		 6260#ifdef CONFIG_I40E_DCB
6261 ret = i40e_init_pf_dcb(pf);
6262 if (ret) {
aebfc816
SN		 6263 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6264 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6265 /* Continue without DCB enabled */
4e3b35b0
NP		 6266 }
6267#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6268#ifdef I40E_FCOE
6269 ret = i40e_init_pf_fcoe(pf);
6270 if (ret)
6271 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6272
38e00438 6273#endif
41c445ff 6274 /* do basic switch setup */
bc7d338f 6275 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6276 if (ret)
6277 goto end_core_reset;
6278
7e2453fe
JB		 6279 /* driver is only interested in link up/down and module qualification
6280 * reports from firmware
6281 */
6282 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6283 I40E_AQ_EVENT_LINK_UPDOWN |
6284 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6285 if (ret)
6286 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6287
cafa2ee6
ASJ		 6288 /* make sure our flow control settings are restored */
6289 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6290 if (ret)
6291 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6292
41c445ff
JB		 6293 /* Rebuild the VSIs and VEBs that existed before reset.
6294 * They are still in our local switch element arrays, so only
6295 * need to rebuild the switch model in the HW.
6296 *
6297 * If there were VEBs but the reconstitution failed, we'll try
6298 * try to recover minimal use by getting the basic PF VSI working.
6299 */
6300 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6301 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6302 /* find the one VEB connected to the MAC, and find orphans */
6303 for (v = 0; v < I40E_MAX_VEB; v++) {
6304 if (!pf->veb[v])
6305 continue;
6306
6307 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6308 pf->veb[v]->uplink_seid == 0) {
6309 ret = i40e_reconstitute_veb(pf->veb[v]);
6310
6311 if (!ret)
6312 continue;
6313
6314 /* If Main VEB failed, we're in deep doodoo,
6315 * so give up rebuilding the switch and set up
6316 * for minimal rebuild of PF VSI.
6317 * If orphan failed, we'll report the error
6318 * but try to keep going.
6319 */
6320 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6321 dev_info(&pf->pdev->dev,
6322 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6323 ret);
6324 pf->vsi[pf->lan_vsi]->uplink_seid
6325 = pf->mac_seid;
6326 break;
6327 } else if (pf->veb[v]->uplink_seid == 0) {
6328 dev_info(&pf->pdev->dev,
6329 "rebuild of orphan VEB failed: %d\n",
6330 ret);
6331 }
6332 }
6333 }
6334 }
6335
6336 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6337 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6338 /* no VEB, so rebuild only the Main VSI */
6339 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6340 if (ret) {
6341 dev_info(&pf->pdev->dev,
6342 "rebuild of Main VSI failed: %d\n", ret);
6343 goto end_core_reset;
6344 }
6345 }
6346
025b4a54
ASJ		 6347 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6348 (pf->hw.aq.fw_maj_ver < 4)) {
6349 msleep(75);
6350 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6351 if (ret)
6352 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6353 pf->hw.aq.asq_last_status);
cafa2ee6 6354 }
41c445ff
JB		 6355 /* reinit the misc interrupt */
6356 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6357 ret = i40e_setup_misc_vector(pf);
6358
6359 /* restart the VSIs that were rebuilt and running before the reset */
6360 i40e_pf_unquiesce_all_vsi(pf);
6361
69f64b2b
MW		 6362 if (pf->num_alloc_vfs) {
6363 for (v = 0; v < pf->num_alloc_vfs; v++)
6364 i40e_reset_vf(&pf->vf[v], true);
6365 }
6366
41c445ff 6367 /* tell the firmware that we're starting */
44033fac 6368 i40e_send_version(pf);
41c445ff
JB		 6369
6370end_core_reset:
a316f651
ASJ		 6371 clear_bit(__I40E_RESET_FAILED, &pf->state);
6372clear_recovery:
41c445ff
JB		 6373 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6374}
6375
f650a38b
ASJ		 6376/**
6377 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
6378 * @pf: board private structure
6379 *
6380 * Close up the VFs and other things in prep for a Core Reset,
6381 * then get ready to rebuild the world.
6382 **/
6383static void i40e_handle_reset_warning(struct i40e_pf *pf)
6384{
23cfbe07
SN		 6385 i40e_prep_for_reset(pf);
6386 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6387}
6388
41c445ff
JB		 6389/**
6390 * i40e_handle_mdd_event
6391 * @pf: pointer to the pf structure
6392 *
6393 * Called from the MDD irq handler to identify possibly malicious vfs
6394 **/
6395static void i40e_handle_mdd_event(struct i40e_pf *pf)
6396{
6397 struct i40e_hw *hw = &pf->hw;
6398 bool mdd_detected = false;
df430b12 6399 bool pf_mdd_detected = false;
41c445ff
JB		 6400 struct i40e_vf *vf;
6401 u32 reg;
6402 int i;
6403
6404 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6405 return;
6406
6407 /* find what triggered the MDD event */
6408 reg = rd32(hw, I40E_GL_MDET_TX);
6409 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6410 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6411 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6412 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6413 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6414 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6415 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6416 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6417 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6418 pf->hw.func_caps.base_queue;
faf32978
JB		 6419 if (netif_msg_tx_err(pf))
6420 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
6421 event, queue, pf_num, vf_num);
41c445ff
JB		 6422 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6423 mdd_detected = true;
6424 }
6425 reg = rd32(hw, I40E_GL_MDET_RX);
6426 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6427 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6428 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6429 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6430 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6431 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6432 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6433 pf->hw.func_caps.base_queue;
faf32978
JB		 6434 if (netif_msg_rx_err(pf))
6435 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6436 event, queue, func);
41c445ff
JB		 6437 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6438 mdd_detected = true;
6439 }
6440
df430b12
NP		 6441 if (mdd_detected) {
6442 reg = rd32(hw, I40E_PF_MDET_TX);
6443 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6444 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6445 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6446 pf_mdd_detected = true;
6447 }
6448 reg = rd32(hw, I40E_PF_MDET_RX);
6449 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6450 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6451 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6452 pf_mdd_detected = true;
6453 }
6454 /* Queue belongs to the PF, initiate a reset */
6455 if (pf_mdd_detected) {
6456 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6457 i40e_service_event_schedule(pf);
6458 }
6459 }
6460
41c445ff
JB		 6461 /* see if one of the VFs needs its hand slapped */
6462 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6463 vf = &(pf->vf[i]);
6464 reg = rd32(hw, I40E_VP_MDET_TX(i));
6465 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6466 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6467 vf->num_mdd_events++;
faf32978
JB		 6468 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6469 i);
41c445ff
JB		 6470 }
6471
6472 reg = rd32(hw, I40E_VP_MDET_RX(i));
6473 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6474 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6475 vf->num_mdd_events++;
faf32978
JB		 6476 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6477 i);
41c445ff
JB		 6478 }
6479
6480 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6481 dev_info(&pf->pdev->dev,
6482 "Too many MDD events on VF %d, disabled\n", i);
6483 dev_info(&pf->pdev->dev,
6484 "Use PF Control I/F to re-enable the VF\n");
6485 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6486 }
6487 }
6488
6489 /* re-enable mdd interrupt cause */
6490 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6491 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6492 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6493 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6494 i40e_flush(hw);
6495}
6496
a1c9a9d9
JK		 6497#ifdef CONFIG_I40E_VXLAN
6498/**
6499 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6500 * @pf: board private structure
6501 **/
6502static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6503{
a1c9a9d9
JK		 6504 struct i40e_hw *hw = &pf->hw;
6505 i40e_status ret;
6506 u8 filter_index;
6507 __be16 port;
6508 int i;
6509
6510 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6511 return;
6512
6513 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6514
6515 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6516 if (pf->pending_vxlan_bitmap & (1 << i)) {
6517 pf->pending_vxlan_bitmap &= ~(1 << i);
6518 port = pf->vxlan_ports[i];
6519 ret = port ?
6520 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6521 I40E_AQC_TUNNEL_TYPE_VXLAN,
6522 &filter_index, NULL)
6523 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6524
6525 if (ret) {
6526 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6527 port ? "adding" : "deleting",
6528 ntohs(port), port ? i : i);
6529
6530 pf->vxlan_ports[i] = 0;
6531 } else {
6532 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6533 port ? "Added" : "Deleted",
6534 ntohs(port), port ? i : filter_index);
6535 }
6536 }
6537 }
6538}
6539
6540#endif
41c445ff
JB		 6541/**
6542 * i40e_service_task - Run the driver's async subtasks
6543 * @work: pointer to work_struct containing our data
6544 **/
6545static void i40e_service_task(struct work_struct *work)
6546{
6547 struct i40e_pf *pf = container_of(work,
6548 struct i40e_pf,
6549 service_task);
6550 unsigned long start_time = jiffies;
6551
e57a2fea
SN		 6552 /* don't bother with service tasks if a reset is in progress */
6553 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6554 i40e_service_event_complete(pf);
6555 return;
6556 }
6557
41c445ff
JB		 6558 i40e_reset_subtask(pf);
6559 i40e_handle_mdd_event(pf);
6560 i40e_vc_process_vflr_event(pf);
6561 i40e_watchdog_subtask(pf);
6562 i40e_fdir_reinit_subtask(pf);
41c445ff 6563 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6564#ifdef CONFIG_I40E_VXLAN
6565 i40e_sync_vxlan_filters_subtask(pf);
6566#endif
41c445ff
JB		 6567 i40e_clean_adminq_subtask(pf);
6568
6569 i40e_service_event_complete(pf);
6570
6571 /* If the tasks have taken longer than one timer cycle or there
6572 * is more work to be done, reschedule the service task now
6573 * rather than wait for the timer to tick again.
6574 */
6575 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6576 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6577 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6578 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6579 i40e_service_event_schedule(pf);
6580}
6581
6582/**
6583 * i40e_service_timer - timer callback
6584 * @data: pointer to PF struct
6585 **/
6586static void i40e_service_timer(unsigned long data)
6587{
6588 struct i40e_pf *pf = (struct i40e_pf *)data;
6589
6590 mod_timer(&pf->service_timer,
6591 round_jiffies(jiffies + pf->service_timer_period));
6592 i40e_service_event_schedule(pf);
6593}
6594
6595/**
6596 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6597 * @vsi: the VSI being configured
6598 **/
6599static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6600{
6601 struct i40e_pf *pf = vsi->back;
6602
6603 switch (vsi->type) {
6604 case I40E_VSI_MAIN:
6605 vsi->alloc_queue_pairs = pf->num_lan_qps;
6606 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6607 I40E_REQ_DESCRIPTOR_MULTIPLE);
6608 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6609 vsi->num_q_vectors = pf->num_lan_msix;
6610 else
6611 vsi->num_q_vectors = 1;
6612
6613 break;
6614
6615 case I40E_VSI_FDIR:
6616 vsi->alloc_queue_pairs = 1;
6617 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6618 I40E_REQ_DESCRIPTOR_MULTIPLE);
6619 vsi->num_q_vectors = 1;
6620 break;
6621
6622 case I40E_VSI_VMDQ2:
6623 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6624 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6625 I40E_REQ_DESCRIPTOR_MULTIPLE);
6626 vsi->num_q_vectors = pf->num_vmdq_msix;
6627 break;
6628
6629 case I40E_VSI_SRIOV:
6630 vsi->alloc_queue_pairs = pf->num_vf_qps;
6631 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6632 I40E_REQ_DESCRIPTOR_MULTIPLE);
6633 break;
6634
38e00438
VD		 6635#ifdef I40E_FCOE
6636 case I40E_VSI_FCOE:
6637 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6638 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6639 I40E_REQ_DESCRIPTOR_MULTIPLE);
6640 vsi->num_q_vectors = pf->num_fcoe_msix;
6641 break;
6642
6643#endif /* I40E_FCOE */
41c445ff
JB		 6644 default:
6645 WARN_ON(1);
6646 return -ENODATA;
6647 }
6648
6649 return 0;
6650}
6651
f650a38b
ASJ		 6652/**
6653 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6654 * @type: VSI pointer
bc7d338f 6655 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6656 *
6657 * On error: returns error code (negative)
6658 * On success: returns 0
6659 **/
bc7d338f 6660static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6661{
6662 int size;
6663 int ret = 0;
6664
ac6c5e3d 6665 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6666 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6667 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6668 if (!vsi->tx_rings)
6669 return -ENOMEM;
f650a38b
ASJ		 6670 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6671
bc7d338f
ASJ		 6672 if (alloc_qvectors) {
6673 /* allocate memory for q_vector pointers */
f57e4fbd 6674 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6675 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6676 if (!vsi->q_vectors) {
6677 ret = -ENOMEM;
6678 goto err_vectors;
6679 }
f650a38b
ASJ		 6680 }
6681 return ret;
6682
6683err_vectors:
6684 kfree(vsi->tx_rings);
6685 return ret;
6686}
6687
41c445ff
JB		 6688/**
6689 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6690 * @pf: board private structure
6691 * @type: type of VSI
6692 *
6693 * On error: returns error code (negative)
6694 * On success: returns vsi index in PF (positive)
6695 **/
6696static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6697{
6698 int ret = -ENODEV;
6699 struct i40e_vsi *vsi;
6700 int vsi_idx;
6701 int i;
6702
6703 /* Need to protect the allocation of the VSIs at the PF level */
6704 mutex_lock(&pf->switch_mutex);
6705
6706 /* VSI list may be fragmented if VSI creation/destruction has
6707 * been happening. We can afford to do a quick scan to look
6708 * for any free VSIs in the list.
6709 *
6710 * find next empty vsi slot, looping back around if necessary
6711 */
6712 i = pf->next_vsi;
505682cd 6713 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6714 i++;
505682cd 6715 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6716 i = 0;
6717 while (i < pf->next_vsi && pf->vsi[i])
6718 i++;
6719 }
6720
505682cd 6721 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6722 vsi_idx = i; /* Found one! */
6723 } else {
6724 ret = -ENODEV;
493fb300 6725 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6726 }
6727 pf->next_vsi = ++i;
6728
6729 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6730 if (!vsi) {
6731 ret = -ENOMEM;
493fb300 6732 goto unlock_pf;
41c445ff
JB		 6733 }
6734 vsi->type = type;
6735 vsi->back = pf;
6736 set_bit(__I40E_DOWN, &vsi->state);
6737 vsi->flags = 0;
6738 vsi->idx = vsi_idx;
6739 vsi->rx_itr_setting = pf->rx_itr_default;
6740 vsi->tx_itr_setting = pf->tx_itr_default;
5db4cb59
ASJ		 6741 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
6742 pf->rss_table_size : 64;
41c445ff
JB		 6743 vsi->netdev_registered = false;
6744 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6745 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6746 vsi->irqs_ready = false;
41c445ff 6747
9f65e15b
AD		 6748 ret = i40e_set_num_rings_in_vsi(vsi);
6749 if (ret)
6750 goto err_rings;
6751
bc7d338f 6752 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6753 if (ret)
9f65e15b 6754 goto err_rings;
493fb300 6755
41c445ff
JB		 6756 /* Setup default MSIX irq handler for VSI */
6757 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6758
6759 pf->vsi[vsi_idx] = vsi;
6760 ret = vsi_idx;
493fb300
AD		 6761 goto unlock_pf;
6762
9f65e15b 6763err_rings:
493fb300
AD		 6764 pf->next_vsi = i - 1;
6765 kfree(vsi);
6766unlock_pf:
41c445ff
JB		 6767 mutex_unlock(&pf->switch_mutex);
6768 return ret;
6769}
6770
f650a38b
ASJ		 6771/**
6772 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6773 * @type: VSI pointer
bc7d338f 6774 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6775 *
6776 * On error: returns error code (negative)
6777 * On success: returns 0
6778 **/
bc7d338f 6779static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6780{
6781 /* free the ring and vector containers */
bc7d338f
ASJ		 6782 if (free_qvectors) {
6783 kfree(vsi->q_vectors);
6784 vsi->q_vectors = NULL;
6785 }
f650a38b
ASJ		 6786 kfree(vsi->tx_rings);
6787 vsi->tx_rings = NULL;
6788 vsi->rx_rings = NULL;
6789}
6790
41c445ff
JB		 6791/**
6792 * i40e_vsi_clear - Deallocate the VSI provided
6793 * @vsi: the VSI being un-configured
6794 **/
6795static int i40e_vsi_clear(struct i40e_vsi *vsi)
6796{
6797 struct i40e_pf *pf;
6798
6799 if (!vsi)
6800 return 0;
6801
6802 if (!vsi->back)
6803 goto free_vsi;
6804 pf = vsi->back;
6805
6806 mutex_lock(&pf->switch_mutex);
6807 if (!pf->vsi[vsi->idx]) {
6808 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6809 vsi->idx, vsi->idx, vsi, vsi->type);
6810 goto unlock_vsi;
6811 }
6812
6813 if (pf->vsi[vsi->idx] != vsi) {
6814 dev_err(&pf->pdev->dev,
6815 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6816 pf->vsi[vsi->idx]->idx,
6817 pf->vsi[vsi->idx],
6818 pf->vsi[vsi->idx]->type,
6819 vsi->idx, vsi, vsi->type);
6820 goto unlock_vsi;
6821 }
6822
6823 /* updates the pf for this cleared vsi */
6824 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6825 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6826
bc7d338f 6827 i40e_vsi_free_arrays(vsi, true);
493fb300 6828
41c445ff
JB		 6829 pf->vsi[vsi->idx] = NULL;
6830 if (vsi->idx < pf->next_vsi)
6831 pf->next_vsi = vsi->idx;
6832
6833unlock_vsi:
6834 mutex_unlock(&pf->switch_mutex);
6835free_vsi:
6836 kfree(vsi);
6837
6838 return 0;
6839}
6840
9f65e15b
AD		 6841/**
6842 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6843 * @vsi: the VSI being cleaned
6844 **/
be1d5eea 6845static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6846{
6847 int i;
6848
8e9dca53 6849 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6850 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6851 kfree_rcu(vsi->tx_rings[i], rcu);
6852 vsi->tx_rings[i] = NULL;
6853 vsi->rx_rings[i] = NULL;
6854 }
be1d5eea 6855 }
9f65e15b
AD		 6856}
6857
41c445ff
JB		 6858/**
6859 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6860 * @vsi: the VSI being configured
6861 **/
6862static int i40e_alloc_rings(struct i40e_vsi *vsi)
6863{
e7046ee1 6864 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6865 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6866 int i;
6867
41c445ff 6868 /* Set basic values in the rings to be used later during open() */
d7397644 6869 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6870 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6871 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6872 if (!tx_ring)
6873 goto err_out;
41c445ff
JB		 6874
6875 tx_ring->queue_index = i;
6876 tx_ring->reg_idx = vsi->base_queue + i;
6877 tx_ring->ring_active = false;
6878 tx_ring->vsi = vsi;
6879 tx_ring->netdev = vsi->netdev;
6880 tx_ring->dev = &pf->pdev->dev;
6881 tx_ring->count = vsi->num_desc;
6882 tx_ring->size = 0;
6883 tx_ring->dcb_tc = 0;
9f65e15b 6884 vsi->tx_rings[i] = tx_ring;
41c445ff 6885
9f65e15b 6886 rx_ring = &tx_ring[1];
41c445ff
JB		 6887 rx_ring->queue_index = i;
6888 rx_ring->reg_idx = vsi->base_queue + i;
6889 rx_ring->ring_active = false;
6890 rx_ring->vsi = vsi;
6891 rx_ring->netdev = vsi->netdev;
6892 rx_ring->dev = &pf->pdev->dev;
6893 rx_ring->count = vsi->num_desc;
6894 rx_ring->size = 0;
6895 rx_ring->dcb_tc = 0;
6896 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6897 set_ring_16byte_desc_enabled(rx_ring);
6898 else
6899 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6900 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6901 }
6902
6903 return 0;
9f65e15b
AD		 6904
6905err_out:
6906 i40e_vsi_clear_rings(vsi);
6907 return -ENOMEM;
41c445ff
JB		 6908}
6909
6910/**
6911 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6912 * @pf: board private structure
6913 * @vectors: the number of MSI-X vectors to request
6914 *
6915 * Returns the number of vectors reserved, or error
6916 **/
6917static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6918{
7b37f376
AG		 6919 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6920 I40E_MIN_MSIX, vectors);
6921 if (vectors < 0) {
41c445ff 6922 dev_info(&pf->pdev->dev,
7b37f376 6923 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6924 vectors = 0;
6925 }
6926
6927 return vectors;
6928}
6929
6930/**
6931 * i40e_init_msix - Setup the MSIX capability
6932 * @pf: board private structure
6933 *
6934 * Work with the OS to set up the MSIX vectors needed.
6935 *
6936 * Returns 0 on success, negative on failure
6937 **/
6938static int i40e_init_msix(struct i40e_pf *pf)
6939{
6940 i40e_status err = 0;
6941 struct i40e_hw *hw = &pf->hw;
c135b0de 6942 int other_vecs = 0;
41c445ff
JB		 6943 int v_budget, i;
6944 int vec;
6945
6946 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6947 return -ENODEV;
6948
6949 /* The number of vectors we'll request will be comprised of:
6950 * - Add 1 for "other" cause for Admin Queue events, etc.
6951 * - The number of LAN queue pairs
f8ff1464
ASJ		 6952 * - Queues being used for RSS.
6953 * We don't need as many as max_rss_size vectors.
6954 * use rss_size instead in the calculation since that
6955 * is governed by number of cpus in the system.
6956 * - assumes symmetric Tx/Rx pairing
41c445ff 6957 * - The number of VMDq pairs
38e00438
VD		 6958#ifdef I40E_FCOE
6959 * - The number of FCOE qps.
6960#endif
41c445ff
JB		 6961 * Once we count this up, try the request.
6962 *
6963 * If we can't get what we want, we'll simplify to nearly nothing
6964 * and try again. If that still fails, we punt.
6965 */
9a3bd2f1
ASJ		 6966 pf->num_lan_msix = min_t(int, num_online_cpus(),
6967 hw->func_caps.num_msix_vectors);
41c445ff 6968 pf->num_vmdq_msix = pf->num_vmdq_qps;
c135b0de
SN		 6969 other_vecs = 1;
6970 other_vecs += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6971 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
c135b0de 6972 other_vecs++;
41c445ff 6973
83840e4b
JL		 6974 /* Scale down if necessary, and the rings will share vectors */
6975 pf->num_lan_msix = min_t(int, pf->num_lan_msix,
6976 (hw->func_caps.num_msix_vectors - other_vecs));
6977 v_budget = pf->num_lan_msix + other_vecs;
6978
38e00438
VD		 6979#ifdef I40E_FCOE
6980 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6981 pf->num_fcoe_msix = pf->num_fcoe_qps;
6982 v_budget += pf->num_fcoe_msix;
6983 }
38e00438 6984#endif
41c445ff
JB		 6985
6986 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6987 GFP_KERNEL);
6988 if (!pf->msix_entries)
6989 return -ENOMEM;
6990
6991 for (i = 0; i < v_budget; i++)
6992 pf->msix_entries[i].entry = i;
6993 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6994
6995 if (vec != v_budget) {
6996 /* If we have limited resources, we will start with no vectors
6997 * for the special features and then allocate vectors to some
6998 * of these features based on the policy and at the end disable
6999 * the features that did not get any vectors.
7000 */
38e00438
VD		 7001#ifdef I40E_FCOE
7002 pf->num_fcoe_qps = 0;
7003 pf->num_fcoe_msix = 0;
7004#endif
a34977ba
ASJ		 7005 pf->num_vmdq_msix = 0;
7006 }
7007
41c445ff
JB		 7008 if (vec < I40E_MIN_MSIX) {
7009 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7010 kfree(pf->msix_entries);
7011 pf->msix_entries = NULL;
7012 return -ENODEV;
7013
7014 } else if (vec == I40E_MIN_MSIX) {
7015 /* Adjust for minimal MSIX use */
41c445ff
JB		 7016 pf->num_vmdq_vsis = 0;
7017 pf->num_vmdq_qps = 0;
41c445ff
JB		 7018 pf->num_lan_qps = 1;
7019 pf->num_lan_msix = 1;
7020
7021 } else if (vec != v_budget) {
a34977ba
ASJ		 7022 /* reserve the misc vector */
7023 vec--;
7024
41c445ff
JB		 7025 /* Scale vector usage down */
7026 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7027 pf->num_vmdq_vsis = 1;
41c445ff
JB		 7028
7029 /* partition out the remaining vectors */
7030 switch (vec) {
7031 case 2:
41c445ff
JB		 7032 pf->num_lan_msix = 1;
7033 break;
7034 case 3:
38e00438
VD		 7035#ifdef I40E_FCOE
7036 /* give one vector to FCoE */
7037 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7038 pf->num_lan_msix = 1;
7039 pf->num_fcoe_msix = 1;
7040 }
7041#else
41c445ff 7042 pf->num_lan_msix = 2;
38e00438 7043#endif
41c445ff
JB		 7044 break;
7045 default:
38e00438
VD		 7046#ifdef I40E_FCOE
7047 /* give one vector to FCoE */
7048 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7049 pf->num_fcoe_msix = 1;
7050 vec--;
7051 }
7052#endif
41c445ff
JB		 7053 pf->num_lan_msix = min_t(int, (vec / 2),
7054 pf->num_lan_qps);
7055 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
7056 I40E_DEFAULT_NUM_VMDQ_VSI);
7057 break;
7058 }
7059 }
7060
a34977ba
ASJ		 7061 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7062 (pf->num_vmdq_msix == 0)) {
7063 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7064 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7065 }
38e00438
VD		 7066#ifdef I40E_FCOE
7067
7068 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7069 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7070 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7071 }
7072#endif
41c445ff
JB		 7073 return err;
7074}
7075
493fb300 7076/**
90e04070 7077 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7078 * @vsi: the VSI being configured
7079 * @v_idx: index of the vector in the vsi struct
7080 *
7081 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7082 **/
90e04070 7083static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7084{
7085 struct i40e_q_vector *q_vector;
7086
7087 /* allocate q_vector */
7088 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7089 if (!q_vector)
7090 return -ENOMEM;
7091
7092 q_vector->vsi = vsi;
7093 q_vector->v_idx = v_idx;
7094 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7095 if (vsi->netdev)
7096 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7097 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7098
cd0b6fa6
AD		 7099 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7100 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7101
493fb300
AD		 7102 /* tie q_vector and vsi together */
7103 vsi->q_vectors[v_idx] = q_vector;
7104
7105 return 0;
7106}
7107
41c445ff 7108/**
90e04070 7109 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7110 * @vsi: the VSI being configured
7111 *
7112 * We allocate one q_vector per queue interrupt. If allocation fails we
7113 * return -ENOMEM.
7114 **/
90e04070 7115static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7116{
7117 struct i40e_pf *pf = vsi->back;
7118 int v_idx, num_q_vectors;
493fb300 7119 int err;
41c445ff
JB		 7120
7121 /* if not MSIX, give the one vector only to the LAN VSI */
7122 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7123 num_q_vectors = vsi->num_q_vectors;
7124 else if (vsi == pf->vsi[pf->lan_vsi])
7125 num_q_vectors = 1;
7126 else
7127 return -EINVAL;
7128
41c445ff 7129 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7130 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7131 if (err)
7132 goto err_out;
41c445ff
JB		 7133 }
7134
7135 return 0;
493fb300
AD		 7136
7137err_out:
7138 while (v_idx--)
7139 i40e_free_q_vector(vsi, v_idx);
7140
7141 return err;
41c445ff
JB		 7142}
7143
7144/**
7145 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7146 * @pf: board private structure to initialize
7147 **/
7148static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
7149{
7150 int err = 0;
7151
7152 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7153 err = i40e_init_msix(pf);
7154 if (err) {
60ea5f83 7155 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7156#ifdef I40E_FCOE
7157 I40E_FLAG_FCOE_ENABLED |
7158#endif
60ea5f83 7159 I40E_FLAG_RSS_ENABLED |
4d9b6043 7160 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7161 I40E_FLAG_SRIOV_ENABLED |
7162 I40E_FLAG_FD_SB_ENABLED |
7163 I40E_FLAG_FD_ATR_ENABLED |
7164 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7165
7166 /* rework the queue expectations without MSIX */
7167 i40e_determine_queue_usage(pf);
7168 }
7169 }
7170
7171 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7172 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7173 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 7174 err = pci_enable_msi(pf->pdev);
7175 if (err) {
958a3e3b 7176 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 7177 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7178 }
7179 }
7180
958a3e3b 7181 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7182 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7183
41c445ff
JB		 7184 /* track first vector for misc interrupts */
7185 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
7186}
7187
7188/**
7189 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7190 * @pf: board private structure
7191 *
7192 * This sets up the handler for MSIX 0, which is used to manage the
7193 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7194 * when in MSI or Legacy interrupt mode.
7195 **/
7196static int i40e_setup_misc_vector(struct i40e_pf *pf)
7197{
7198 struct i40e_hw *hw = &pf->hw;
7199 int err = 0;
7200
7201 /* Only request the irq if this is the first time through, and
7202 * not when we're rebuilding after a Reset
7203 */
7204 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7205 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7206 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7207 if (err) {
7208 dev_info(&pf->pdev->dev,
77fa28be 7209 "request_irq for %s failed: %d\n",
b294ac70 7210 pf->int_name, err);
41c445ff
JB		 7211 return -EFAULT;
7212 }
7213 }
7214
ab437b5a 7215 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7216
7217 /* associate no queues to the misc vector */
7218 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7219 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7220
7221 i40e_flush(hw);
7222
7223 i40e_irq_dynamic_enable_icr0(pf);
7224
7225 return err;
7226}
7227
7228/**
7229 * i40e_config_rss - Prepare for RSS if used
7230 * @pf: board private structure
7231 **/
7232static int i40e_config_rss(struct i40e_pf *pf)
7233{
22f258a1 7234 u32 rss_key[I40E_PFQF_HKEY_MAX_INDEX + 1];
66ddcffb 7235 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0
ASJ		 7236 struct i40e_hw *hw = &pf->hw;
7237 u32 lut = 0;
7238 int i, j;
7239 u64 hena;
e157ea30 7240 u32 reg_val;
41c445ff 7241
22f258a1 7242 netdev_rss_key_fill(rss_key, sizeof(rss_key));
41c445ff 7243 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
22f258a1 7244 wr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);
41c445ff
JB		 7245
7246 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7247 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7248 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7249 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7250 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7251 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7252
66ddcffb
ASJ		 7253 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7254
e157ea30
CW		 7255 /* Check capability and Set table size and register per hw expectation*/
7256 reg_val = rd32(hw, I40E_PFQF_CTL_0);
7257 if (hw->func_caps.rss_table_size == 512) {
7258 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7259 pf->rss_table_size = 512;
7260 } else {
7261 pf->rss_table_size = 128;
7262 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7263 }
7264 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7265
41c445ff 7266 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7267 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7268
7269 /* The assumption is that lan qp count will be the highest
7270 * qp count for any PF VSI that needs RSS.
7271 * If multiple VSIs need RSS support, all the qp counts
7272 * for those VSIs should be a power of 2 for RSS to work.
7273 * If LAN VSI is the only consumer for RSS then this requirement
7274 * is not necessary.
7275 */
66ddcffb 7276 if (j == vsi->rss_size)
41c445ff
JB		 7277 j = 0;
7278 /* lut = 4-byte sliding window of 4 lut entries */
7279 lut = (lut << 8) | (j &
7280 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7281 /* On i = 3, we have 4 entries in lut; write to the register */
7282 if ((i & 3) == 3)
7283 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7284 }
7285 i40e_flush(hw);
7286
7287 return 0;
7288}
7289
f8ff1464
ASJ		 7290/**
7291 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7292 * @pf: board private structure
7293 * @queue_count: the requested queue count for rss.
7294 *
7295 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7296 * count which may be different from the requested queue count.
7297 **/
7298int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7299{
9a3bd2f1
ASJ		 7300 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7301 int new_rss_size;
7302
f8ff1464
ASJ		 7303 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7304 return 0;
7305
9a3bd2f1 7306 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7307
9a3bd2f1
ASJ		 7308 if (queue_count != vsi->num_queue_pairs) {
7309 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7310 i40e_prep_for_reset(pf);
7311
9a3bd2f1 7312 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7313
7314 i40e_reset_and_rebuild(pf, true);
7315 i40e_config_rss(pf);
7316 }
7317 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7318 return pf->rss_size;
7319}
7320
f4492db1
GR		 7321/**
7322 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7323 * @pf: board private structure
7324 **/
7325i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7326{
7327 i40e_status status;
7328 bool min_valid, max_valid;
7329 u32 max_bw, min_bw;
7330
7331 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7332 &min_valid, &max_valid);
7333
7334 if (!status) {
7335 if (min_valid)
7336 pf->npar_min_bw = min_bw;
7337 if (max_valid)
7338 pf->npar_max_bw = max_bw;
7339 }
7340
7341 return status;
7342}
7343
7344/**
7345 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7346 * @pf: board private structure
7347 **/
7348i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7349{
7350 struct i40e_aqc_configure_partition_bw_data bw_data;
7351 i40e_status status;
7352
7353 /* Set the valid bit for this pf */
7354 bw_data.pf_valid_bits = cpu_to_le16(1 << pf->hw.pf_id);
7355 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7356 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7357
7358 /* Set the new bandwidths */
7359 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7360
7361 return status;
7362}
7363
7364/**
7365 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7366 * @pf: board private structure
7367 **/
7368i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7369{
7370 /* Commit temporary BW setting to permanent NVM image */
7371 enum i40e_admin_queue_err last_aq_status;
7372 i40e_status ret;
7373 u16 nvm_word;
7374
7375 if (pf->hw.partition_id != 1) {
7376 dev_info(&pf->pdev->dev,
7377 "Commit BW only works on partition 1! This is partition %d",
7378 pf->hw.partition_id);
7379 ret = I40E_NOT_SUPPORTED;
7380 goto bw_commit_out;
7381 }
7382
7383 /* Acquire NVM for read access */
7384 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7385 last_aq_status = pf->hw.aq.asq_last_status;
7386 if (ret) {
7387 dev_info(&pf->pdev->dev,
7388 "Cannot acquire NVM for read access, err %d: aq_err %d\n",
7389 ret, last_aq_status);
7390 goto bw_commit_out;
7391 }
7392
7393 /* Read word 0x10 of NVM - SW compatibility word 1 */
7394 ret = i40e_aq_read_nvm(&pf->hw,
7395 I40E_SR_NVM_CONTROL_WORD,
7396 0x10, sizeof(nvm_word), &nvm_word,
7397 false, NULL);
7398 /* Save off last admin queue command status before releasing
7399 * the NVM
7400 */
7401 last_aq_status = pf->hw.aq.asq_last_status;
7402 i40e_release_nvm(&pf->hw);
7403 if (ret) {
7404 dev_info(&pf->pdev->dev, "NVM read error, err %d aq_err %d\n",
7405 ret, last_aq_status);
7406 goto bw_commit_out;
7407 }
7408
7409 /* Wait a bit for NVM release to complete */
7410 msleep(50);
7411
7412 /* Acquire NVM for write access */
7413 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7414 last_aq_status = pf->hw.aq.asq_last_status;
7415 if (ret) {
7416 dev_info(&pf->pdev->dev,
7417 "Cannot acquire NVM for write access, err %d: aq_err %d\n",
7418 ret, last_aq_status);
7419 goto bw_commit_out;
7420 }
7421 /* Write it back out unchanged to initiate update NVM,
7422 * which will force a write of the shadow (alt) RAM to
7423 * the NVM - thus storing the bandwidth values permanently.
7424 */
7425 ret = i40e_aq_update_nvm(&pf->hw,
7426 I40E_SR_NVM_CONTROL_WORD,
7427 0x10, sizeof(nvm_word),
7428 &nvm_word, true, NULL);
7429 /* Save off last admin queue command status before releasing
7430 * the NVM
7431 */
7432 last_aq_status = pf->hw.aq.asq_last_status;
7433 i40e_release_nvm(&pf->hw);
7434 if (ret)
7435 dev_info(&pf->pdev->dev,
7436 "BW settings NOT SAVED, err %d aq_err %d\n",
7437 ret, last_aq_status);
7438bw_commit_out:
7439
7440 return ret;
7441}
7442
41c445ff
JB		 7443/**
7444 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7445 * @pf: board private structure to initialize
7446 *
7447 * i40e_sw_init initializes the Adapter private data structure.
7448 * Fields are initialized based on PCI device information and
7449 * OS network device settings (MTU size).
7450 **/
7451static int i40e_sw_init(struct i40e_pf *pf)
7452{
7453 int err = 0;
7454 int size;
7455
7456 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7457 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7458 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7459 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7460 if (I40E_DEBUG_USER & debug)
7461 pf->hw.debug_mask = debug;
7462 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7463 I40E_DEFAULT_MSG_ENABLE);
7464 }
7465
7466 /* Set default capability flags */
7467 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7468 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 7469 I40E_FLAG_MSIX_ENABLED;
7470
7471 if (iommu_present(&pci_bus_type))
7472 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7473 else
7474 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7475
ca99eb99
MW		 7476 /* Set default ITR */
7477 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7478 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7479
7134f9ce
JB		 7480 /* Depending on PF configurations, it is possible that the RSS
7481 * maximum might end up larger than the available queues
7482 */
41c445ff 7483 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7484 pf->rss_size = 1;
5db4cb59 7485 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7486 pf->rss_size_max = min_t(int, pf->rss_size_max,
7487 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7488 if (pf->hw.func_caps.rss) {
7489 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7490 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7491 }
7492
2050bc65
CS		 7493 /* MFP mode enabled */
7494 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7495 pf->flags |= I40E_FLAG_MFP_ENABLED;
7496 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7497 if (i40e_get_npar_bw_setting(pf))
7498 dev_warn(&pf->pdev->dev,
7499 "Could not get NPAR bw settings\n");
7500 else
7501 dev_info(&pf->pdev->dev,
7502 "Min BW = %8.8x, Max BW = %8.8x\n",
7503 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7504 }
7505
cbf61325
ASJ		 7506 /* FW/NVM is not yet fixed in this regard */
7507 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7508 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7509 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7510 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 7511 /* Setup a counter for fd_atr per pf */
7512 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7513 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7514 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 7515 /* Setup a counter for fd_sb per pf */
7516 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7517 } else {
7518 dev_info(&pf->pdev->dev,
0b67584f 7519 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7520 }
cbf61325
ASJ		 7521 pf->fdir_pf_filter_count =
7522 pf->hw.func_caps.fd_filters_guaranteed;
7523 pf->hw.fdir_shared_filter_count =
7524 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7525 }
7526
7527 if (pf->hw.func_caps.vmdq) {
7528 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7529 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7530 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7531 }
7532
38e00438
VD		 7533#ifdef I40E_FCOE
7534 err = i40e_init_pf_fcoe(pf);
7535 if (err)
7536 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7537
7538#endif /* I40E_FCOE */
41c445ff 7539#ifdef CONFIG_PCI_IOV
ba252f13 7540 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7541 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7542 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7543 pf->num_req_vfs = min_t(int,
7544 pf->hw.func_caps.num_vfs,
7545 I40E_MAX_VF_COUNT);
7546 }
7547#endif /* CONFIG_PCI_IOV */
7548 pf->eeprom_version = 0xDEAD;
7549 pf->lan_veb = I40E_NO_VEB;
7550 pf->lan_vsi = I40E_NO_VSI;
7551
7552 /* set up queue assignment tracking */
7553 size = sizeof(struct i40e_lump_tracking)
7554 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7555 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7556 if (!pf->qp_pile) {
7557 err = -ENOMEM;
7558 goto sw_init_done;
7559 }
7560 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7561 pf->qp_pile->search_hint = 0;
7562
7563 /* set up vector assignment tracking */
7564 size = sizeof(struct i40e_lump_tracking)
7565 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
7566 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7567 if (!pf->irq_pile) {
7568 kfree(pf->qp_pile);
7569 err = -ENOMEM;
7570 goto sw_init_done;
7571 }
7572 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
7573 pf->irq_pile->search_hint = 0;
7574
327fe04b
ASJ		 7575 pf->tx_timeout_recovery_level = 1;
7576
41c445ff
JB		 7577 mutex_init(&pf->switch_mutex);
7578
7579sw_init_done:
7580 return err;
7581}
7582
7c3c288b
ASJ		 7583/**
7584 * i40e_set_ntuple - set the ntuple feature flag and take action
7585 * @pf: board private structure to initialize
7586 * @features: the feature set that the stack is suggesting
7587 *
7588 * returns a bool to indicate if reset needs to happen
7589 **/
7590bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7591{
7592 bool need_reset = false;
7593
7594 /* Check if Flow Director n-tuple support was enabled or disabled. If
7595 * the state changed, we need to reset.
7596 */
7597 if (features & NETIF_F_NTUPLE) {
7598 /* Enable filters and mark for reset */
7599 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7600 need_reset = true;
7601 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7602 } else {
7603 /* turn off filters, mark for reset and clear SW filter list */
7604 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7605 need_reset = true;
7606 i40e_fdir_filter_exit(pf);
7607 }
7608 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7609 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7610 /* reset fd counters */
7611 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7612 pf->fdir_pf_active_filters = 0;
7613 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7614 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7615 /* if ATR was auto disabled it can be re-enabled. */
7616 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7617 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7618 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7619 }
7620 return need_reset;
7621}
7622
41c445ff
JB		 7623/**
7624 * i40e_set_features - set the netdev feature flags
7625 * @netdev: ptr to the netdev being adjusted
7626 * @features: the feature set that the stack is suggesting
7627 **/
7628static int i40e_set_features(struct net_device *netdev,
7629 netdev_features_t features)
7630{
7631 struct i40e_netdev_priv *np = netdev_priv(netdev);
7632 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7633 struct i40e_pf *pf = vsi->back;
7634 bool need_reset;
41c445ff
JB		 7635
7636 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7637 i40e_vlan_stripping_enable(vsi);
7638 else
7639 i40e_vlan_stripping_disable(vsi);
7640
7c3c288b
ASJ		 7641 need_reset = i40e_set_ntuple(pf, features);
7642
7643 if (need_reset)
7644 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7645
41c445ff
JB		 7646 return 0;
7647}
7648
a1c9a9d9
JK		 7649#ifdef CONFIG_I40E_VXLAN
7650/**
7651 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7652 * @pf: board private structure
7653 * @port: The UDP port to look up
7654 *
7655 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7656 **/
7657static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7658{
7659 u8 i;
7660
7661 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7662 if (pf->vxlan_ports[i] == port)
7663 return i;
7664 }
7665
7666 return i;
7667}
7668
7669/**
7670 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7671 * @netdev: This physical port's netdev
7672 * @sa_family: Socket Family that VXLAN is notifying us about
7673 * @port: New UDP port number that VXLAN started listening to
7674 **/
7675static void i40e_add_vxlan_port(struct net_device *netdev,
7676 sa_family_t sa_family, __be16 port)
7677{
7678 struct i40e_netdev_priv *np = netdev_priv(netdev);
7679 struct i40e_vsi *vsi = np->vsi;
7680 struct i40e_pf *pf = vsi->back;
7681 u8 next_idx;
7682 u8 idx;
7683
7684 if (sa_family == AF_INET6)
7685 return;
7686
7687 idx = i40e_get_vxlan_port_idx(pf, port);
7688
7689 /* Check if port already exists */
7690 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7691 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7692 return;
7693 }
7694
7695 /* Now check if there is space to add the new port */
7696 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7697
7698 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7699 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7700 ntohs(port));
7701 return;
7702 }
7703
7704 /* New port: add it and mark its index in the bitmap */
7705 pf->vxlan_ports[next_idx] = port;
7706 pf->pending_vxlan_bitmap |= (1 << next_idx);
7707
7708 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7709}
7710
7711/**
7712 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7713 * @netdev: This physical port's netdev
7714 * @sa_family: Socket Family that VXLAN is notifying us about
7715 * @port: UDP port number that VXLAN stopped listening to
7716 **/
7717static void i40e_del_vxlan_port(struct net_device *netdev,
7718 sa_family_t sa_family, __be16 port)
7719{
7720 struct i40e_netdev_priv *np = netdev_priv(netdev);
7721 struct i40e_vsi *vsi = np->vsi;
7722 struct i40e_pf *pf = vsi->back;
7723 u8 idx;
7724
7725 if (sa_family == AF_INET6)
7726 return;
7727
7728 idx = i40e_get_vxlan_port_idx(pf, port);
7729
7730 /* Check if port already exists */
7731 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7732 /* if port exists, set it to 0 (mark for deletion)
7733 * and make it pending
7734 */
7735 pf->vxlan_ports[idx] = 0;
7736
7737 pf->pending_vxlan_bitmap |= (1 << idx);
7738
7739 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7740 } else {
7741 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7742 ntohs(port));
7743 }
7744}
7745
7746#endif
1f224ad2 7747static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 7748 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 7749{
7750 struct i40e_netdev_priv *np = netdev_priv(netdev);
7751 struct i40e_pf *pf = np->vsi->back;
7752 struct i40e_hw *hw = &pf->hw;
7753
7754 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7755 return -EOPNOTSUPP;
7756
7757 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7758 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7759
7760 return 0;
7761}
7762
2f90ade6
JB		 7763/**
7764 * i40e_ndo_fdb_add - add an entry to the hardware database
7765 * @ndm: the input from the stack
7766 * @tb: pointer to array of nladdr (unused)
7767 * @dev: the net device pointer
7768 * @addr: the MAC address entry being added
7769 * @flags: instructions from stack about fdb operation
7770 */
4ba0dea5
GR		 7771static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7772 struct net_device *dev,
f6f6424b 7773 const unsigned char *addr, u16 vid,
4ba0dea5 7774 u16 flags)
4ba0dea5
GR		 7775{
7776 struct i40e_netdev_priv *np = netdev_priv(dev);
7777 struct i40e_pf *pf = np->vsi->back;
7778 int err = 0;
7779
7780 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7781 return -EOPNOTSUPP;
7782
65891fea
OG		 7783 if (vid) {
7784 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
7785 return -EINVAL;
7786 }
7787
4ba0dea5
GR		 7788 /* Hardware does not support aging addresses so if a
7789 * ndm_state is given only allow permanent addresses
7790 */
7791 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7792 netdev_info(dev, "FDB only supports static addresses\n");
7793 return -EINVAL;
7794 }
7795
7796 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7797 err = dev_uc_add_excl(dev, addr);
7798 else if (is_multicast_ether_addr(addr))
7799 err = dev_mc_add_excl(dev, addr);
7800 else
7801 err = -EINVAL;
7802
7803 /* Only return duplicate errors if NLM_F_EXCL is set */
7804 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7805 err = 0;
7806
7807 return err;
7808}
7809
51616018
NP		 7810#ifdef HAVE_BRIDGE_ATTRIBS
7811/**
7812 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
7813 * @dev: the netdev being configured
7814 * @nlh: RTNL message
7815 *
7816 * Inserts a new hardware bridge if not already created and
7817 * enables the bridging mode requested (VEB or VEPA). If the
7818 * hardware bridge has already been inserted and the request
7819 * is to change the mode then that requires a PF reset to
7820 * allow rebuild of the components with required hardware
7821 * bridge mode enabled.
7822 **/
7823static int i40e_ndo_bridge_setlink(struct net_device *dev,
7824 struct nlmsghdr *nlh)
7825{
7826 struct i40e_netdev_priv *np = netdev_priv(dev);
7827 struct i40e_vsi *vsi = np->vsi;
7828 struct i40e_pf *pf = vsi->back;
7829 struct i40e_veb *veb = NULL;
7830 struct nlattr *attr, *br_spec;
7831 int i, rem;
7832
7833 /* Only for PF VSI for now */
7834 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
7835 return -EOPNOTSUPP;
7836
7837 /* Find the HW bridge for PF VSI */
7838 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7839 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7840 veb = pf->veb[i];
7841 }
7842
7843 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7844
7845 nla_for_each_nested(attr, br_spec, rem) {
7846 __u16 mode;
7847
7848 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7849 continue;
7850
7851 mode = nla_get_u16(attr);
7852 if ((mode != BRIDGE_MODE_VEPA) &&
7853 (mode != BRIDGE_MODE_VEB))
7854 return -EINVAL;
7855
7856 /* Insert a new HW bridge */
7857 if (!veb) {
7858 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7859 vsi->tc_config.enabled_tc);
7860 if (veb) {
7861 veb->bridge_mode = mode;
7862 i40e_config_bridge_mode(veb);
7863 } else {
7864 /* No Bridge HW offload available */
7865 return -ENOENT;
7866 }
7867 break;
7868 } else if (mode != veb->bridge_mode) {
7869 /* Existing HW bridge but different mode needs reset */
7870 veb->bridge_mode = mode;
7871 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7872 break;
7873 }
7874 }
7875
7876 return 0;
7877}
7878
7879/**
7880 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
7881 * @skb: skb buff
7882 * @pid: process id
7883 * @seq: RTNL message seq #
7884 * @dev: the netdev being configured
7885 * @filter_mask: unused
7886 *
7887 * Return the mode in which the hardware bridge is operating in
7888 * i.e VEB or VEPA.
7889 **/
7890#ifdef HAVE_BRIDGE_FILTER
7891static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7892 struct net_device *dev,
7893 u32 __always_unused filter_mask)
7894#else
7895static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7896 struct net_device *dev)
7897#endif /* HAVE_BRIDGE_FILTER */
7898{
7899 struct i40e_netdev_priv *np = netdev_priv(dev);
7900 struct i40e_vsi *vsi = np->vsi;
7901 struct i40e_pf *pf = vsi->back;
7902 struct i40e_veb *veb = NULL;
7903 int i;
7904
7905 /* Only for PF VSI for now */
7906 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
7907 return -EOPNOTSUPP;
7908
7909 /* Find the HW bridge for the PF VSI */
7910 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7911 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7912 veb = pf->veb[i];
7913 }
7914
7915 if (!veb)
7916 return 0;
7917
7918 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode);
7919}
7920#endif /* HAVE_BRIDGE_ATTRIBS */
7921
96664483 7922const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 7923 .ndo_open = i40e_open,
7924 .ndo_stop = i40e_close,
7925 .ndo_start_xmit = i40e_lan_xmit_frame,
7926 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7927 .ndo_set_rx_mode = i40e_set_rx_mode,
7928 .ndo_validate_addr = eth_validate_addr,
7929 .ndo_set_mac_address = i40e_set_mac,
7930 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7931 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7932 .ndo_tx_timeout = i40e_tx_timeout,
7933 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7934 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7935#ifdef CONFIG_NET_POLL_CONTROLLER
7936 .ndo_poll_controller = i40e_netpoll,
7937#endif
7938 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 7939#ifdef I40E_FCOE
7940 .ndo_fcoe_enable = i40e_fcoe_enable,
7941 .ndo_fcoe_disable = i40e_fcoe_disable,
7942#endif
41c445ff
JB		 7943 .ndo_set_features = i40e_set_features,
7944 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7945 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7946 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7947 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7948 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 7949 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 7950#ifdef CONFIG_I40E_VXLAN
7951 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7952 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7953#endif
1f224ad2 7954 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 7955 .ndo_fdb_add = i40e_ndo_fdb_add,
51616018
NP		 7956#ifdef HAVE_BRIDGE_ATTRIBS
7957 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
7958 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
7959#endif /* HAVE_BRIDGE_ATTRIBS */
41c445ff
JB		 7960};
7961
7962/**
7963 * i40e_config_netdev - Setup the netdev flags
7964 * @vsi: the VSI being configured
7965 *
7966 * Returns 0 on success, negative value on failure
7967 **/
7968static int i40e_config_netdev(struct i40e_vsi *vsi)
7969{
1a10370a 7970 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7971 struct i40e_pf *pf = vsi->back;
7972 struct i40e_hw *hw = &pf->hw;
7973 struct i40e_netdev_priv *np;
7974 struct net_device *netdev;
7975 u8 mac_addr[ETH_ALEN];
7976 int etherdev_size;
7977
7978 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7979 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7980 if (!netdev)
7981 return -ENOMEM;
7982
7983 vsi->netdev = netdev;
7984 np = netdev_priv(netdev);
7985 np->vsi = vsi;
7986
d70e941b 7987 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7988 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7989 NETIF_F_TSO;
41c445ff
JB		 7990
7991 netdev->features = NETIF_F_SG |
7992 NETIF_F_IP_CSUM |
7993 NETIF_F_SCTP_CSUM |
7994 NETIF_F_HIGHDMA |
7995 NETIF_F_GSO_UDP_TUNNEL |
7996 NETIF_F_HW_VLAN_CTAG_TX |
7997 NETIF_F_HW_VLAN_CTAG_RX |
7998 NETIF_F_HW_VLAN_CTAG_FILTER |
7999 NETIF_F_IPV6_CSUM |
8000 NETIF_F_TSO |
059dab69 8001 NETIF_F_TSO_ECN |
41c445ff
JB		 8002 NETIF_F_TSO6 |
8003 NETIF_F_RXCSUM |
8004 NETIF_F_RXHASH |
8005 0;
8006
2e86a0b6
ASJ		 8007 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8008 netdev->features |= NETIF_F_NTUPLE;
8009
41c445ff
JB		 8010 /* copy netdev features into list of user selectable features */
8011 netdev->hw_features |= netdev->features;
8012
8013 if (vsi->type == I40E_VSI_MAIN) {
8014 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8015 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8016 /* The following steps are necessary to prevent reception
8017 * of tagged packets - some older NVM configurations load a
8018 * default a MAC-VLAN filter that accepts any tagged packet
8019 * which must be replaced by a normal filter.
8c27d42e 8020 */
30650cc5
SN		 8021 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8022 i40e_add_filter(vsi, mac_addr,
8023 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8024 } else {
8025 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8026 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8027 pf->vsi[pf->lan_vsi]->netdev->name);
8028 random_ether_addr(mac_addr);
8029 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8030 }
1a10370a 8031 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8032
9a173901
GR		 8033 ether_addr_copy(netdev->dev_addr, mac_addr);
8034 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8035 /* vlan gets same features (except vlan offload)
8036 * after any tweaks for specific VSI types
8037 */
8038 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8039 NETIF_F_HW_VLAN_CTAG_RX |
8040 NETIF_F_HW_VLAN_CTAG_FILTER);
8041 netdev->priv_flags |= IFF_UNICAST_FLT;
8042 netdev->priv_flags |= IFF_SUPP_NOFCS;
8043 /* Setup netdev TC information */
8044 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8045
8046 netdev->netdev_ops = &i40e_netdev_ops;
8047 netdev->watchdog_timeo = 5 * HZ;
8048 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8049#ifdef I40E_FCOE
8050 i40e_fcoe_config_netdev(netdev, vsi);
8051#endif
41c445ff
JB		 8052
8053 return 0;
8054}
8055
8056/**
8057 * i40e_vsi_delete - Delete a VSI from the switch
8058 * @vsi: the VSI being removed
8059 *
8060 * Returns 0 on success, negative value on failure
8061 **/
8062static void i40e_vsi_delete(struct i40e_vsi *vsi)
8063{
8064 /* remove default VSI is not allowed */
8065 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8066 return;
8067
41c445ff 8068 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8069}
8070
51616018
NP		 8071/**
8072 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8073 * @vsi: the VSI being queried
8074 *
8075 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8076 **/
8077int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8078{
8079 struct i40e_veb *veb;
8080 struct i40e_pf *pf = vsi->back;
8081
8082 /* Uplink is not a bridge so default to VEB */
8083 if (vsi->veb_idx == I40E_NO_VEB)
8084 return 1;
8085
8086 veb = pf->veb[vsi->veb_idx];
8087 /* Uplink is a bridge in VEPA mode */
8088 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8089 return 0;
8090
8091 /* Uplink is a bridge in VEB mode */
8092 return 1;
8093}
8094
41c445ff
JB		 8095/**
8096 * i40e_add_vsi - Add a VSI to the switch
8097 * @vsi: the VSI being configured
8098 *
8099 * This initializes a VSI context depending on the VSI type to be added and
8100 * passes it down to the add_vsi aq command.
8101 **/
8102static int i40e_add_vsi(struct i40e_vsi *vsi)
8103{
8104 int ret = -ENODEV;
8105 struct i40e_mac_filter *f, *ftmp;
8106 struct i40e_pf *pf = vsi->back;
8107 struct i40e_hw *hw = &pf->hw;
8108 struct i40e_vsi_context ctxt;
8109 u8 enabled_tc = 0x1; /* TC0 enabled */
8110 int f_count = 0;
8111
8112 memset(&ctxt, 0, sizeof(ctxt));
8113 switch (vsi->type) {
8114 case I40E_VSI_MAIN:
8115 /* The PF's main VSI is already setup as part of the
8116 * device initialization, so we'll not bother with
8117 * the add_vsi call, but we will retrieve the current
8118 * VSI context.
8119 */
8120 ctxt.seid = pf->main_vsi_seid;
8121 ctxt.pf_num = pf->hw.pf_id;
8122 ctxt.vf_num = 0;
8123 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8124 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8125 if (ret) {
8126 dev_info(&pf->pdev->dev,
8127 "couldn't get pf vsi config, err %d, aq_err %d\n",
8128 ret, pf->hw.aq.asq_last_status);
8129 return -ENOENT;
8130 }
8131 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
8132 vsi->info.valid_sections = 0;
8133
8134 vsi->seid = ctxt.seid;
8135 vsi->id = ctxt.vsi_number;
8136
8137 enabled_tc = i40e_pf_get_tc_map(pf);
8138
8139 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8140 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8141 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8142 memset(&ctxt, 0, sizeof(ctxt));
8143 ctxt.seid = pf->main_vsi_seid;
8144 ctxt.pf_num = pf->hw.pf_id;
8145 ctxt.vf_num = 0;
8146 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8147 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8148 if (ret) {
8149 dev_info(&pf->pdev->dev,
8150 "update vsi failed, aq_err=%d\n",
8151 pf->hw.aq.asq_last_status);
8152 ret = -ENOENT;
8153 goto err;
8154 }
8155 /* update the local VSI info queue map */
8156 i40e_vsi_update_queue_map(vsi, &ctxt);
8157 vsi->info.valid_sections = 0;
8158 } else {
8159 /* Default/Main VSI is only enabled for TC0
8160 * reconfigure it to enable all TCs that are
8161 * available on the port in SFP mode.
63d7e5a4
NP		 8162 * For MFP case the iSCSI PF would use this
8163 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8164 */
8165 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8166 if (ret) {
8167 dev_info(&pf->pdev->dev,
8168 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
8169 enabled_tc, ret,
8170 pf->hw.aq.asq_last_status);
8171 ret = -ENOENT;
8172 }
8173 }
8174 break;
8175
8176 case I40E_VSI_FDIR:
cbf61325
ASJ		 8177 ctxt.pf_num = hw->pf_id;
8178 ctxt.vf_num = 0;
8179 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8180 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8181 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
51616018
NP		 8182 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8183 ctxt.info.valid_sections |=
79c21a82 8184 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8185 ctxt.info.switch_id =
79c21a82 8186 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8187 }
41c445ff 8188 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8189 break;
8190
8191 case I40E_VSI_VMDQ2:
8192 ctxt.pf_num = hw->pf_id;
8193 ctxt.vf_num = 0;
8194 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8195 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8196 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8197
41c445ff
JB		 8198 /* This VSI is connected to VEB so the switch_id
8199 * should be set to zero by default.
8200 */
51616018
NP		 8201 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8202 ctxt.info.valid_sections |=
8203 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8204 ctxt.info.switch_id =
8205 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8206 }
41c445ff
JB		 8207
8208 /* Setup the VSI tx/rx queue map for TC0 only for now */
8209 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8210 break;
8211
8212 case I40E_VSI_SRIOV:
8213 ctxt.pf_num = hw->pf_id;
8214 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8215 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8216 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8217 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8218
41c445ff
JB		 8219 /* This VSI is connected to VEB so the switch_id
8220 * should be set to zero by default.
8221 */
51616018
NP		 8222 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8223 ctxt.info.valid_sections |=
8224 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8225 ctxt.info.switch_id =
8226 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8227 }
41c445ff
JB		 8228
8229 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8230 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8231 if (pf->vf[vsi->vf_id].spoofchk) {
8232 ctxt.info.valid_sections |=
8233 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8234 ctxt.info.sec_flags |=
8235 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8236 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8237 }
41c445ff
JB		 8238 /* Setup the VSI tx/rx queue map for TC0 only for now */
8239 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8240 break;
8241
38e00438
VD		 8242#ifdef I40E_FCOE
8243 case I40E_VSI_FCOE:
8244 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8245 if (ret) {
8246 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8247 return ret;
8248 }
8249 break;
8250
8251#endif /* I40E_FCOE */
41c445ff
JB		 8252 default:
8253 return -ENODEV;
8254 }
8255
8256 if (vsi->type != I40E_VSI_MAIN) {
8257 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8258 if (ret) {
8259 dev_info(&vsi->back->pdev->dev,
8260 "add vsi failed, aq_err=%d\n",
8261 vsi->back->hw.aq.asq_last_status);
8262 ret = -ENOENT;
8263 goto err;
8264 }
8265 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
8266 vsi->info.valid_sections = 0;
8267 vsi->seid = ctxt.seid;
8268 vsi->id = ctxt.vsi_number;
8269 }
8270
8271 /* If macvlan filters already exist, force them to get loaded */
8272 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8273 f->changed = true;
8274 f_count++;
6252c7e4
SN		 8275
8276 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8277 struct i40e_aqc_remove_macvlan_element_data element;
8278
8279 memset(&element, 0, sizeof(element));
8280 ether_addr_copy(element.mac_addr, f->macaddr);
8281 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8282 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8283 &element, 1, NULL);
8284 if (ret) {
8285 /* some older FW has a different default */
8286 element.flags |=
8287 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8288 i40e_aq_remove_macvlan(hw, vsi->seid,
8289 &element, 1, NULL);
8290 }
8291
8292 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8293 I40E_AQC_WRITE_TYPE_LAA_WOL,
8294 f->macaddr, NULL);
8295 }
41c445ff
JB		 8296 }
8297 if (f_count) {
8298 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8299 pf->flags |= I40E_FLAG_FILTER_SYNC;
8300 }
8301
8302 /* Update VSI BW information */
8303 ret = i40e_vsi_get_bw_info(vsi);
8304 if (ret) {
8305 dev_info(&pf->pdev->dev,
8306 "couldn't get vsi bw info, err %d, aq_err %d\n",
8307 ret, pf->hw.aq.asq_last_status);
8308 /* VSI is already added so not tearing that up */
8309 ret = 0;
8310 }
8311
8312err:
8313 return ret;
8314}
8315
8316/**
8317 * i40e_vsi_release - Delete a VSI and free its resources
8318 * @vsi: the VSI being removed
8319 *
8320 * Returns 0 on success or < 0 on error
8321 **/
8322int i40e_vsi_release(struct i40e_vsi *vsi)
8323{
8324 struct i40e_mac_filter *f, *ftmp;
8325 struct i40e_veb *veb = NULL;
8326 struct i40e_pf *pf;
8327 u16 uplink_seid;
8328 int i, n;
8329
8330 pf = vsi->back;
8331
8332 /* release of a VEB-owner or last VSI is not allowed */
8333 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8334 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8335 vsi->seid, vsi->uplink_seid);
8336 return -ENODEV;
8337 }
8338 if (vsi == pf->vsi[pf->lan_vsi] &&
8339 !test_bit(__I40E_DOWN, &pf->state)) {
8340 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8341 return -ENODEV;
8342 }
8343
8344 uplink_seid = vsi->uplink_seid;
8345 if (vsi->type != I40E_VSI_SRIOV) {
8346 if (vsi->netdev_registered) {
8347 vsi->netdev_registered = false;
8348 if (vsi->netdev) {
8349 /* results in a call to i40e_close() */
8350 unregister_netdev(vsi->netdev);
41c445ff
JB		 8351 }
8352 } else {
90ef8d47 8353 i40e_vsi_close(vsi);
41c445ff
JB		 8354 }
8355 i40e_vsi_disable_irq(vsi);
8356 }
8357
8358 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8359 i40e_del_filter(vsi, f->macaddr, f->vlan,
8360 f->is_vf, f->is_netdev);
8361 i40e_sync_vsi_filters(vsi);
8362
8363 i40e_vsi_delete(vsi);
8364 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8365 if (vsi->netdev) {
8366 free_netdev(vsi->netdev);
8367 vsi->netdev = NULL;
8368 }
41c445ff
JB		 8369 i40e_vsi_clear_rings(vsi);
8370 i40e_vsi_clear(vsi);
8371
8372 /* If this was the last thing on the VEB, except for the
8373 * controlling VSI, remove the VEB, which puts the controlling
8374 * VSI onto the next level down in the switch.
8375 *
8376 * Well, okay, there's one more exception here: don't remove
8377 * the orphan VEBs yet. We'll wait for an explicit remove request
8378 * from up the network stack.
8379 */
505682cd 8380 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8381 if (pf->vsi[i] &&
8382 pf->vsi[i]->uplink_seid == uplink_seid &&
8383 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8384 n++; /* count the VSIs */
8385 }
8386 }
8387 for (i = 0; i < I40E_MAX_VEB; i++) {
8388 if (!pf->veb[i])
8389 continue;
8390 if (pf->veb[i]->uplink_seid == uplink_seid)
8391 n++; /* count the VEBs */
8392 if (pf->veb[i]->seid == uplink_seid)
8393 veb = pf->veb[i];
8394 }
8395 if (n == 0 && veb && veb->uplink_seid != 0)
8396 i40e_veb_release(veb);
8397
8398 return 0;
8399}
8400
8401/**
8402 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8403 * @vsi: ptr to the VSI
8404 *
8405 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8406 * corresponding SW VSI structure and initializes num_queue_pairs for the
8407 * newly allocated VSI.
8408 *
8409 * Returns 0 on success or negative on failure
8410 **/
8411static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8412{
8413 int ret = -ENOENT;
8414 struct i40e_pf *pf = vsi->back;
8415
493fb300 8416 if (vsi->q_vectors[0]) {
41c445ff
JB		 8417 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8418 vsi->seid);
8419 return -EEXIST;
8420 }
8421
8422 if (vsi->base_vector) {
f29eaa3d 8423 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8424 vsi->seid, vsi->base_vector);
8425 return -EEXIST;
8426 }
8427
90e04070 8428 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8429 if (ret) {
8430 dev_info(&pf->pdev->dev,
8431 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8432 vsi->num_q_vectors, vsi->seid, ret);
8433 vsi->num_q_vectors = 0;
8434 goto vector_setup_out;
8435 }
8436
958a3e3b
SN		 8437 if (vsi->num_q_vectors)
8438 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8439 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8440 if (vsi->base_vector < 0) {
8441 dev_info(&pf->pdev->dev,
049a2be8
SN		 8442 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8443 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8444 i40e_vsi_free_q_vectors(vsi);
8445 ret = -ENOENT;
8446 goto vector_setup_out;
8447 }
8448
8449vector_setup_out:
8450 return ret;
8451}
8452
bc7d338f
ASJ		 8453/**
8454 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8455 * @vsi: pointer to the vsi.
8456 *
8457 * This re-allocates a vsi's queue resources.
8458 *
8459 * Returns pointer to the successfully allocated and configured VSI sw struct
8460 * on success, otherwise returns NULL on failure.
8461 **/
8462static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8463{
8464 struct i40e_pf *pf = vsi->back;
8465 u8 enabled_tc;
8466 int ret;
8467
8468 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8469 i40e_vsi_clear_rings(vsi);
8470
8471 i40e_vsi_free_arrays(vsi, false);
8472 i40e_set_num_rings_in_vsi(vsi);
8473 ret = i40e_vsi_alloc_arrays(vsi, false);
8474 if (ret)
8475 goto err_vsi;
8476
8477 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8478 if (ret < 0) {
049a2be8
SN		 8479 dev_info(&pf->pdev->dev,
8480 "failed to get tracking for %d queues for VSI %d err=%d\n",
8481 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8482 goto err_vsi;
8483 }
8484 vsi->base_queue = ret;
8485
8486 /* Update the FW view of the VSI. Force a reset of TC and queue
8487 * layout configurations.
8488 */
8489 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8490 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8491 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8492 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8493
8494 /* assign it some queues */
8495 ret = i40e_alloc_rings(vsi);
8496 if (ret)
8497 goto err_rings;
8498
8499 /* map all of the rings to the q_vectors */
8500 i40e_vsi_map_rings_to_vectors(vsi);
8501 return vsi;
8502
8503err_rings:
8504 i40e_vsi_free_q_vectors(vsi);
8505 if (vsi->netdev_registered) {
8506 vsi->netdev_registered = false;
8507 unregister_netdev(vsi->netdev);
8508 free_netdev(vsi->netdev);
8509 vsi->netdev = NULL;
8510 }
8511 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8512err_vsi:
8513 i40e_vsi_clear(vsi);
8514 return NULL;
8515}
8516
41c445ff
JB		 8517/**
8518 * i40e_vsi_setup - Set up a VSI by a given type
8519 * @pf: board private structure
8520 * @type: VSI type
8521 * @uplink_seid: the switch element to link to
8522 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8523 *
8524 * This allocates the sw VSI structure and its queue resources, then add a VSI
8525 * to the identified VEB.
8526 *
8527 * Returns pointer to the successfully allocated and configure VSI sw struct on
8528 * success, otherwise returns NULL on failure.
8529 **/
8530struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8531 u16 uplink_seid, u32 param1)
8532{
8533 struct i40e_vsi *vsi = NULL;
8534 struct i40e_veb *veb = NULL;
8535 int ret, i;
8536 int v_idx;
8537
8538 /* The requested uplink_seid must be either
8539 * - the PF's port seid
8540 * no VEB is needed because this is the PF
8541 * or this is a Flow Director special case VSI
8542 * - seid of an existing VEB
8543 * - seid of a VSI that owns an existing VEB
8544 * - seid of a VSI that doesn't own a VEB
8545 * a new VEB is created and the VSI becomes the owner
8546 * - seid of the PF VSI, which is what creates the first VEB
8547 * this is a special case of the previous
8548 *
8549 * Find which uplink_seid we were given and create a new VEB if needed
8550 */
8551 for (i = 0; i < I40E_MAX_VEB; i++) {
8552 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8553 veb = pf->veb[i];
8554 break;
8555 }
8556 }
8557
8558 if (!veb && uplink_seid != pf->mac_seid) {
8559
505682cd 8560 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8561 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8562 vsi = pf->vsi[i];
8563 break;
8564 }
8565 }
8566 if (!vsi) {
8567 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8568 uplink_seid);
8569 return NULL;
8570 }
8571
8572 if (vsi->uplink_seid == pf->mac_seid)
8573 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8574 vsi->tc_config.enabled_tc);
8575 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8576 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8577 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 8578 if (veb) {
8579 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
8580 dev_info(&vsi->back->pdev->dev,
8581 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
8582 __func__);
8583 return NULL;
8584 }
51616018 8585 i40e_config_bridge_mode(veb);
79c21a82 8586 }
41c445ff
JB		 8587 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8588 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8589 veb = pf->veb[i];
8590 }
8591 if (!veb) {
8592 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8593 return NULL;
8594 }
8595
8596 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8597 uplink_seid = veb->seid;
8598 }
8599
8600 /* get vsi sw struct */
8601 v_idx = i40e_vsi_mem_alloc(pf, type);
8602 if (v_idx < 0)
8603 goto err_alloc;
8604 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8605 if (!vsi)
8606 goto err_alloc;
41c445ff
JB		 8607 vsi->type = type;
8608 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8609
8610 if (type == I40E_VSI_MAIN)
8611 pf->lan_vsi = v_idx;
8612 else if (type == I40E_VSI_SRIOV)
8613 vsi->vf_id = param1;
8614 /* assign it some queues */
cbf61325
ASJ		 8615 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8616 vsi->idx);
41c445ff 8617 if (ret < 0) {
049a2be8
SN		 8618 dev_info(&pf->pdev->dev,
8619 "failed to get tracking for %d queues for VSI %d err=%d\n",
8620 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 8621 goto err_vsi;
8622 }
8623 vsi->base_queue = ret;
8624
8625 /* get a VSI from the hardware */
8626 vsi->uplink_seid = uplink_seid;
8627 ret = i40e_add_vsi(vsi);
8628 if (ret)
8629 goto err_vsi;
8630
8631 switch (vsi->type) {
8632 /* setup the netdev if needed */
8633 case I40E_VSI_MAIN:
8634 case I40E_VSI_VMDQ2:
38e00438 8635 case I40E_VSI_FCOE:
41c445ff
JB		 8636 ret = i40e_config_netdev(vsi);
8637 if (ret)
8638 goto err_netdev;
8639 ret = register_netdev(vsi->netdev);
8640 if (ret)
8641 goto err_netdev;
8642 vsi->netdev_registered = true;
8643 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8644#ifdef CONFIG_I40E_DCB
8645 /* Setup DCB netlink interface */
8646 i40e_dcbnl_setup(vsi);
8647#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8648 /* fall through */
8649
8650 case I40E_VSI_FDIR:
8651 /* set up vectors and rings if needed */
8652 ret = i40e_vsi_setup_vectors(vsi);
8653 if (ret)
8654 goto err_msix;
8655
8656 ret = i40e_alloc_rings(vsi);
8657 if (ret)
8658 goto err_rings;
8659
8660 /* map all of the rings to the q_vectors */
8661 i40e_vsi_map_rings_to_vectors(vsi);
8662
8663 i40e_vsi_reset_stats(vsi);
8664 break;
8665
8666 default:
8667 /* no netdev or rings for the other VSI types */
8668 break;
8669 }
8670
8671 return vsi;
8672
8673err_rings:
8674 i40e_vsi_free_q_vectors(vsi);
8675err_msix:
8676 if (vsi->netdev_registered) {
8677 vsi->netdev_registered = false;
8678 unregister_netdev(vsi->netdev);
8679 free_netdev(vsi->netdev);
8680 vsi->netdev = NULL;
8681 }
8682err_netdev:
8683 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8684err_vsi:
8685 i40e_vsi_clear(vsi);
8686err_alloc:
8687 return NULL;
8688}
8689
8690/**
8691 * i40e_veb_get_bw_info - Query VEB BW information
8692 * @veb: the veb to query
8693 *
8694 * Query the Tx scheduler BW configuration data for given VEB
8695 **/
8696static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8697{
8698 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8699 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8700 struct i40e_pf *pf = veb->pf;
8701 struct i40e_hw *hw = &pf->hw;
8702 u32 tc_bw_max;
8703 int ret = 0;
8704 int i;
8705
8706 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8707 &bw_data, NULL);
8708 if (ret) {
8709 dev_info(&pf->pdev->dev,
8710 "query veb bw config failed, aq_err=%d\n",
8711 hw->aq.asq_last_status);
8712 goto out;
8713 }
8714
8715 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8716 &ets_data, NULL);
8717 if (ret) {
8718 dev_info(&pf->pdev->dev,
8719 "query veb bw ets config failed, aq_err=%d\n",
8720 hw->aq.asq_last_status);
8721 goto out;
8722 }
8723
8724 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8725 veb->bw_max_quanta = ets_data.tc_bw_max;
8726 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 8727 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 8728 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8729 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8730 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8731 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8732 veb->bw_tc_limit_credits[i] =
8733 le16_to_cpu(bw_data.tc_bw_limits[i]);
8734 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8735 }
8736
8737out:
8738 return ret;
8739}
8740
8741/**
8742 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8743 * @pf: board private structure
8744 *
8745 * On error: returns error code (negative)
8746 * On success: returns vsi index in PF (positive)
8747 **/
8748static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8749{
8750 int ret = -ENOENT;
8751 struct i40e_veb *veb;
8752 int i;
8753
8754 /* Need to protect the allocation of switch elements at the PF level */
8755 mutex_lock(&pf->switch_mutex);
8756
8757 /* VEB list may be fragmented if VEB creation/destruction has
8758 * been happening. We can afford to do a quick scan to look
8759 * for any free slots in the list.
8760 *
8761 * find next empty veb slot, looping back around if necessary
8762 */
8763 i = 0;
8764 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8765 i++;
8766 if (i >= I40E_MAX_VEB) {
8767 ret = -ENOMEM;
8768 goto err_alloc_veb; /* out of VEB slots! */
8769 }
8770
8771 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8772 if (!veb) {
8773 ret = -ENOMEM;
8774 goto err_alloc_veb;
8775 }
8776 veb->pf = pf;
8777 veb->idx = i;
8778 veb->enabled_tc = 1;
8779
8780 pf->veb[i] = veb;
8781 ret = i;
8782err_alloc_veb:
8783 mutex_unlock(&pf->switch_mutex);
8784 return ret;
8785}
8786
8787/**
8788 * i40e_switch_branch_release - Delete a branch of the switch tree
8789 * @branch: where to start deleting
8790 *
8791 * This uses recursion to find the tips of the branch to be
8792 * removed, deleting until we get back to and can delete this VEB.
8793 **/
8794static void i40e_switch_branch_release(struct i40e_veb *branch)
8795{
8796 struct i40e_pf *pf = branch->pf;
8797 u16 branch_seid = branch->seid;
8798 u16 veb_idx = branch->idx;
8799 int i;
8800
8801 /* release any VEBs on this VEB - RECURSION */
8802 for (i = 0; i < I40E_MAX_VEB; i++) {
8803 if (!pf->veb[i])
8804 continue;
8805 if (pf->veb[i]->uplink_seid == branch->seid)
8806 i40e_switch_branch_release(pf->veb[i]);
8807 }
8808
8809 /* Release the VSIs on this VEB, but not the owner VSI.
8810 *
8811 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8812 * the VEB itself, so don't use (*branch) after this loop.
8813 */
505682cd 8814 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8815 if (!pf->vsi[i])
8816 continue;
8817 if (pf->vsi[i]->uplink_seid == branch_seid &&
8818 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8819 i40e_vsi_release(pf->vsi[i]);
8820 }
8821 }
8822
8823 /* There's one corner case where the VEB might not have been
8824 * removed, so double check it here and remove it if needed.
8825 * This case happens if the veb was created from the debugfs
8826 * commands and no VSIs were added to it.
8827 */
8828 if (pf->veb[veb_idx])
8829 i40e_veb_release(pf->veb[veb_idx]);
8830}
8831
8832/**
8833 * i40e_veb_clear - remove veb struct
8834 * @veb: the veb to remove
8835 **/
8836static void i40e_veb_clear(struct i40e_veb *veb)
8837{
8838 if (!veb)
8839 return;
8840
8841 if (veb->pf) {
8842 struct i40e_pf *pf = veb->pf;
8843
8844 mutex_lock(&pf->switch_mutex);
8845 if (pf->veb[veb->idx] == veb)
8846 pf->veb[veb->idx] = NULL;
8847 mutex_unlock(&pf->switch_mutex);
8848 }
8849
8850 kfree(veb);
8851}
8852
8853/**
8854 * i40e_veb_release - Delete a VEB and free its resources
8855 * @veb: the VEB being removed
8856 **/
8857void i40e_veb_release(struct i40e_veb *veb)
8858{
8859 struct i40e_vsi *vsi = NULL;
8860 struct i40e_pf *pf;
8861 int i, n = 0;
8862
8863 pf = veb->pf;
8864
8865 /* find the remaining VSI and check for extras */
505682cd 8866 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8867 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
8868 n++;
8869 vsi = pf->vsi[i];
8870 }
8871 }
8872 if (n != 1) {
8873 dev_info(&pf->pdev->dev,
8874 "can't remove VEB %d with %d VSIs left\n",
8875 veb->seid, n);
8876 return;
8877 }
8878
8879 /* move the remaining VSI to uplink veb */
8880 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8881 if (veb->uplink_seid) {
8882 vsi->uplink_seid = veb->uplink_seid;
8883 if (veb->uplink_seid == pf->mac_seid)
8884 vsi->veb_idx = I40E_NO_VEB;
8885 else
8886 vsi->veb_idx = veb->veb_idx;
8887 } else {
8888 /* floating VEB */
8889 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8890 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8891 }
8892
8893 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8894 i40e_veb_clear(veb);
41c445ff
JB		 8895}
8896
8897/**
8898 * i40e_add_veb - create the VEB in the switch
8899 * @veb: the VEB to be instantiated
8900 * @vsi: the controlling VSI
8901 **/
8902static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8903{
56747264 8904 bool is_default = false;
e1c51b95 8905 bool is_cloud = false;
41c445ff
JB		 8906 int ret;
8907
8908 /* get a VEB from the hardware */
8909 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8910 veb->enabled_tc, is_default,
8911 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8912 if (ret) {
8913 dev_info(&veb->pf->pdev->dev,
8914 "couldn't add VEB, err %d, aq_err %d\n",
8915 ret, veb->pf->hw.aq.asq_last_status);
8916 return -EPERM;
8917 }
8918
8919 /* get statistics counter */
8920 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8921 &veb->stats_idx, NULL, NULL, NULL);
8922 if (ret) {
8923 dev_info(&veb->pf->pdev->dev,
8924 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8925 ret, veb->pf->hw.aq.asq_last_status);
8926 return -EPERM;
8927 }
8928 ret = i40e_veb_get_bw_info(veb);
8929 if (ret) {
8930 dev_info(&veb->pf->pdev->dev,
8931 "couldn't get VEB bw info, err %d, aq_err %d\n",
8932 ret, veb->pf->hw.aq.asq_last_status);
8933 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8934 return -ENOENT;
8935 }
8936
8937 vsi->uplink_seid = veb->seid;
8938 vsi->veb_idx = veb->idx;
8939 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8940
8941 return 0;
8942}
8943
8944/**
8945 * i40e_veb_setup - Set up a VEB
8946 * @pf: board private structure
8947 * @flags: VEB setup flags
8948 * @uplink_seid: the switch element to link to
8949 * @vsi_seid: the initial VSI seid
8950 * @enabled_tc: Enabled TC bit-map
8951 *
8952 * This allocates the sw VEB structure and links it into the switch
8953 * It is possible and legal for this to be a duplicate of an already
8954 * existing VEB. It is also possible for both uplink and vsi seids
8955 * to be zero, in order to create a floating VEB.
8956 *
8957 * Returns pointer to the successfully allocated VEB sw struct on
8958 * success, otherwise returns NULL on failure.
8959 **/
8960struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8961 u16 uplink_seid, u16 vsi_seid,
8962 u8 enabled_tc)
8963{
8964 struct i40e_veb *veb, *uplink_veb = NULL;
8965 int vsi_idx, veb_idx;
8966 int ret;
8967
8968 /* if one seid is 0, the other must be 0 to create a floating relay */
8969 if ((uplink_seid == 0 || vsi_seid == 0) &&
8970 (uplink_seid + vsi_seid != 0)) {
8971 dev_info(&pf->pdev->dev,
8972 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8973 uplink_seid, vsi_seid);
8974 return NULL;
8975 }
8976
8977 /* make sure there is such a vsi and uplink */
505682cd 8978 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8979 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8980 break;
505682cd 8981 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8982 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8983 vsi_seid);
8984 return NULL;
8985 }
8986
8987 if (uplink_seid && uplink_seid != pf->mac_seid) {
8988 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8989 if (pf->veb[veb_idx] &&
8990 pf->veb[veb_idx]->seid == uplink_seid) {
8991 uplink_veb = pf->veb[veb_idx];
8992 break;
8993 }
8994 }
8995 if (!uplink_veb) {
8996 dev_info(&pf->pdev->dev,
8997 "uplink seid %d not found\n", uplink_seid);
8998 return NULL;
8999 }
9000 }
9001
9002 /* get veb sw struct */
9003 veb_idx = i40e_veb_mem_alloc(pf);
9004 if (veb_idx < 0)
9005 goto err_alloc;
9006 veb = pf->veb[veb_idx];
9007 veb->flags = flags;
9008 veb->uplink_seid = uplink_seid;
9009 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9010 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9011
9012 /* create the VEB in the switch */
9013 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9014 if (ret)
9015 goto err_veb;
1bb8b935
SN		 9016 if (vsi_idx == pf->lan_vsi)
9017 pf->lan_veb = veb->idx;
41c445ff
JB		 9018
9019 return veb;
9020
9021err_veb:
9022 i40e_veb_clear(veb);
9023err_alloc:
9024 return NULL;
9025}
9026
9027/**
9028 * i40e_setup_pf_switch_element - set pf vars based on switch type
9029 * @pf: board private structure
9030 * @ele: element we are building info from
9031 * @num_reported: total number of elements
9032 * @printconfig: should we print the contents
9033 *
9034 * helper function to assist in extracting a few useful SEID values.
9035 **/
9036static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9037 struct i40e_aqc_switch_config_element_resp *ele,
9038 u16 num_reported, bool printconfig)
9039{
9040 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9041 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9042 u8 element_type = ele->element_type;
9043 u16 seid = le16_to_cpu(ele->seid);
9044
9045 if (printconfig)
9046 dev_info(&pf->pdev->dev,
9047 "type=%d seid=%d uplink=%d downlink=%d\n",
9048 element_type, seid, uplink_seid, downlink_seid);
9049
9050 switch (element_type) {
9051 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9052 pf->mac_seid = seid;
9053 break;
9054 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9055 /* Main VEB? */
9056 if (uplink_seid != pf->mac_seid)
9057 break;
9058 if (pf->lan_veb == I40E_NO_VEB) {
9059 int v;
9060
9061 /* find existing or else empty VEB */
9062 for (v = 0; v < I40E_MAX_VEB; v++) {
9063 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9064 pf->lan_veb = v;
9065 break;
9066 }
9067 }
9068 if (pf->lan_veb == I40E_NO_VEB) {
9069 v = i40e_veb_mem_alloc(pf);
9070 if (v < 0)
9071 break;
9072 pf->lan_veb = v;
9073 }
9074 }
9075
9076 pf->veb[pf->lan_veb]->seid = seid;
9077 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9078 pf->veb[pf->lan_veb]->pf = pf;
9079 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9080 break;
9081 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9082 if (num_reported != 1)
9083 break;
9084 /* This is immediately after a reset so we can assume this is
9085 * the PF's VSI
9086 */
9087 pf->mac_seid = uplink_seid;
9088 pf->pf_seid = downlink_seid;
9089 pf->main_vsi_seid = seid;
9090 if (printconfig)
9091 dev_info(&pf->pdev->dev,
9092 "pf_seid=%d main_vsi_seid=%d\n",
9093 pf->pf_seid, pf->main_vsi_seid);
9094 break;
9095 case I40E_SWITCH_ELEMENT_TYPE_PF:
9096 case I40E_SWITCH_ELEMENT_TYPE_VF:
9097 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9098 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9099 case I40E_SWITCH_ELEMENT_TYPE_PE:
9100 case I40E_SWITCH_ELEMENT_TYPE_PA:
9101 /* ignore these for now */
9102 break;
9103 default:
9104 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9105 element_type, seid);
9106 break;
9107 }
9108}
9109
9110/**
9111 * i40e_fetch_switch_configuration - Get switch config from firmware
9112 * @pf: board private structure
9113 * @printconfig: should we print the contents
9114 *
9115 * Get the current switch configuration from the device and
9116 * extract a few useful SEID values.
9117 **/
9118int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9119{
9120 struct i40e_aqc_get_switch_config_resp *sw_config;
9121 u16 next_seid = 0;
9122 int ret = 0;
9123 u8 *aq_buf;
9124 int i;
9125
9126 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9127 if (!aq_buf)
9128 return -ENOMEM;
9129
9130 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9131 do {
9132 u16 num_reported, num_total;
9133
9134 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9135 I40E_AQ_LARGE_BUF,
9136 &next_seid, NULL);
9137 if (ret) {
9138 dev_info(&pf->pdev->dev,
9139 "get switch config failed %d aq_err=%x\n",
9140 ret, pf->hw.aq.asq_last_status);
9141 kfree(aq_buf);
9142 return -ENOENT;
9143 }
9144
9145 num_reported = le16_to_cpu(sw_config->header.num_reported);
9146 num_total = le16_to_cpu(sw_config->header.num_total);
9147
9148 if (printconfig)
9149 dev_info(&pf->pdev->dev,
9150 "header: %d reported %d total\n",
9151 num_reported, num_total);
9152
41c445ff
JB		 9153 for (i = 0; i < num_reported; i++) {
9154 struct i40e_aqc_switch_config_element_resp *ele =
9155 &sw_config->element[i];
9156
9157 i40e_setup_pf_switch_element(pf, ele, num_reported,
9158 printconfig);
9159 }
9160 } while (next_seid != 0);
9161
9162 kfree(aq_buf);
9163 return ret;
9164}
9165
9166/**
9167 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9168 * @pf: board private structure
bc7d338f 9169 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9170 *
9171 * Returns 0 on success, negative value on failure
9172 **/
bc7d338f 9173static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9174{
9175 int ret;
9176
9177 /* find out what's out there already */
9178 ret = i40e_fetch_switch_configuration(pf, false);
9179 if (ret) {
9180 dev_info(&pf->pdev->dev,
9181 "couldn't fetch switch config, err %d, aq_err %d\n",
9182 ret, pf->hw.aq.asq_last_status);
9183 return ret;
9184 }
9185 i40e_pf_reset_stats(pf);
9186
41c445ff 9187 /* first time setup */
bc7d338f 9188 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9189 struct i40e_vsi *vsi = NULL;
9190 u16 uplink_seid;
9191
9192 /* Set up the PF VSI associated with the PF's main VSI
9193 * that is already in the HW switch
9194 */
9195 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9196 uplink_seid = pf->veb[pf->lan_veb]->seid;
9197 else
9198 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9199 if (pf->lan_vsi == I40E_NO_VSI)
9200 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9201 else if (reinit)
9202 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9203 if (!vsi) {
9204 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9205 i40e_fdir_teardown(pf);
9206 return -EAGAIN;
9207 }
41c445ff
JB		 9208 } else {
9209 /* force a reset of TC and queue layout configurations */
9210 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9211 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9212 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9213 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9214 }
9215 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9216
cbf61325
ASJ		 9217 i40e_fdir_sb_setup(pf);
9218
41c445ff
JB		 9219 /* Setup static PF queue filter control settings */
9220 ret = i40e_setup_pf_filter_control(pf);
9221 if (ret) {
9222 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9223 ret);
9224 /* Failure here should not stop continuing other steps */
9225 }
9226
9227 /* enable RSS in the HW, even for only one queue, as the stack can use
9228 * the hash
9229 */
9230 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9231 i40e_config_rss(pf);
9232
9233 /* fill in link information and enable LSE reporting */
21af70fb 9234 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9235 i40e_link_event(pf);
9236
9237 /* Initialize user-specific link properties */
9238 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9239 I40E_AQ_AN_COMPLETED) ? true : false);
9240
9241 /* fill in link information and enable LSE reporting */
21af70fb 9242 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
41c445ff
JB		 9243 i40e_link_event(pf);
9244
d52c20b7 9245 /* Initialize user-specific link properties */
41c445ff
JB		 9246 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9247 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9248
beb0dff1
JK		 9249 i40e_ptp_init(pf);
9250
41c445ff
JB		 9251 return ret;
9252}
9253
41c445ff
JB		 9254/**
9255 * i40e_determine_queue_usage - Work out queue distribution
9256 * @pf: board private structure
9257 **/
9258static void i40e_determine_queue_usage(struct i40e_pf *pf)
9259{
41c445ff
JB		 9260 int queues_left;
9261
9262 pf->num_lan_qps = 0;
38e00438
VD		 9263#ifdef I40E_FCOE
9264 pf->num_fcoe_qps = 0;
9265#endif
41c445ff
JB		 9266
9267 /* Find the max queues to be put into basic use. We'll always be
9268 * using TC0, whether or not DCB is running, and TC0 will get the
9269 * big RSS set.
9270 */
9271 queues_left = pf->hw.func_caps.num_tx_qp;
9272
cbf61325 9273 if ((queues_left == 1) ||
9aa7e935 9274 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9275 /* one qp for PF, no queues for anything else */
9276 queues_left = 0;
9277 pf->rss_size = pf->num_lan_qps = 1;
9278
9279 /* make sure all the fancies are disabled */
60ea5f83 9280 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9281#ifdef I40E_FCOE
9282 I40E_FLAG_FCOE_ENABLED |
9283#endif
60ea5f83
JB		 9284 I40E_FLAG_FD_SB_ENABLED |
9285 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9286 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9287 I40E_FLAG_SRIOV_ENABLED |
9288 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9289 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9290 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9291 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9292 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9293 /* one qp for PF */
9294 pf->rss_size = pf->num_lan_qps = 1;
9295 queues_left -= pf->num_lan_qps;
9296
9297 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9298#ifdef I40E_FCOE
9299 I40E_FLAG_FCOE_ENABLED |
9300#endif
9aa7e935
FZ		 9301 I40E_FLAG_FD_SB_ENABLED |
9302 I40E_FLAG_FD_ATR_ENABLED |
9303 I40E_FLAG_DCB_ENABLED |
9304 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9305 } else {
cbf61325 9306 /* Not enough queues for all TCs */
4d9b6043 9307 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9308 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9309 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9310 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9311 }
9a3bd2f1
ASJ		 9312 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9313 num_online_cpus());
9314 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9315 pf->hw.func_caps.num_tx_qp);
9316
cbf61325
ASJ		 9317 queues_left -= pf->num_lan_qps;
9318 }
9319
38e00438
VD		 9320#ifdef I40E_FCOE
9321 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9322 if (I40E_DEFAULT_FCOE <= queues_left) {
9323 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9324 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9325 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9326 } else {
9327 pf->num_fcoe_qps = 0;
9328 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9329 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9330 }
9331
9332 queues_left -= pf->num_fcoe_qps;
9333 }
9334
9335#endif
cbf61325
ASJ		 9336 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9337 if (queues_left > 1) {
9338 queues_left -= 1; /* save 1 queue for FD */
9339 } else {
9340 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9341 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9342 }
41c445ff
JB		 9343 }
9344
9345 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9346 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9347 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9348 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9349 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9350 }
9351
9352 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9353 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9354 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9355 (queues_left / pf->num_vmdq_qps));
9356 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9357 }
9358
f8ff1464 9359 pf->queues_left = queues_left;
38e00438
VD		 9360#ifdef I40E_FCOE
9361 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9362#endif
41c445ff
JB		 9363}
9364
9365/**
9366 * i40e_setup_pf_filter_control - Setup PF static filter control
9367 * @pf: PF to be setup
9368 *
9369 * i40e_setup_pf_filter_control sets up a pf's initial filter control
9370 * settings. If PE/FCoE are enabled then it will also set the per PF
9371 * based filter sizes required for them. It also enables Flow director,
9372 * ethertype and macvlan type filter settings for the pf.
9373 *
9374 * Returns 0 on success, negative on failure
9375 **/
9376static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9377{
9378 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9379
9380 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9381
9382 /* Flow Director is enabled */
60ea5f83 9383 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9384 settings->enable_fdir = true;
9385
9386 /* Ethtype and MACVLAN filters enabled for PF */
9387 settings->enable_ethtype = true;
9388 settings->enable_macvlan = true;
9389
9390 if (i40e_set_filter_control(&pf->hw, settings))
9391 return -ENOENT;
9392
9393 return 0;
9394}
9395
0c22b3dd
JB		 9396#define INFO_STRING_LEN 255
9397static void i40e_print_features(struct i40e_pf *pf)
9398{
9399 struct i40e_hw *hw = &pf->hw;
9400 char *buf, *string;
9401
9402 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9403 if (!string) {
9404 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9405 return;
9406 }
9407
9408 buf = string;
9409
9410 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9411#ifdef CONFIG_PCI_IOV
9412 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9413#endif
aba237d1
MW		 9414 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9415 pf->hw.func_caps.num_vsis,
9416 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9417 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9418
9419 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9420 buf += sprintf(buf, "RSS ");
0c22b3dd 9421 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9422 buf += sprintf(buf, "FD_ATR ");
9423 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9424 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9425 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9426 }
4d9b6043 9427 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9428 buf += sprintf(buf, "DCB ");
9429 if (pf->flags & I40E_FLAG_PTP)
9430 buf += sprintf(buf, "PTP ");
38e00438
VD		 9431#ifdef I40E_FCOE
9432 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9433 buf += sprintf(buf, "FCOE ");
9434#endif
0c22b3dd
JB		 9435
9436 BUG_ON(buf > (string + INFO_STRING_LEN));
9437 dev_info(&pf->pdev->dev, "%s\n", string);
9438 kfree(string);
9439}
9440
41c445ff
JB		 9441/**
9442 * i40e_probe - Device initialization routine
9443 * @pdev: PCI device information struct
9444 * @ent: entry in i40e_pci_tbl
9445 *
9446 * i40e_probe initializes a pf identified by a pci_dev structure.
9447 * The OS initialization, configuring of the pf private structure,
9448 * and a hardware reset occur.
9449 *
9450 * Returns 0 on success, negative on failure
9451 **/
9452static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9453{
e827845c 9454 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 9455 struct i40e_pf *pf;
9456 struct i40e_hw *hw;
93cd765b 9457 static u16 pfs_found;
d4dfb81a 9458 u16 link_status;
41c445ff
JB		 9459 int err = 0;
9460 u32 len;
8a9eb7d3 9461 u32 i;
41c445ff
JB		 9462
9463 err = pci_enable_device_mem(pdev);
9464 if (err)
9465 return err;
9466
9467 /* set up for high or low dma */
6494294f 9468 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9469 if (err) {
e3e3bfdd
JS		 9470 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9471 if (err) {
9472 dev_err(&pdev->dev,
9473 "DMA configuration failed: 0x%x\n", err);
9474 goto err_dma;
9475 }
41c445ff
JB		 9476 }
9477
9478 /* set up pci connections */
9479 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9480 IORESOURCE_MEM), i40e_driver_name);
9481 if (err) {
9482 dev_info(&pdev->dev,
9483 "pci_request_selected_regions failed %d\n", err);
9484 goto err_pci_reg;
9485 }
9486
9487 pci_enable_pcie_error_reporting(pdev);
9488 pci_set_master(pdev);
9489
9490 /* Now that we have a PCI connection, we need to do the
9491 * low level device setup. This is primarily setting up
9492 * the Admin Queue structures and then querying for the
9493 * device's current profile information.
9494 */
9495 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9496 if (!pf) {
9497 err = -ENOMEM;
9498 goto err_pf_alloc;
9499 }
9500 pf->next_vsi = 0;
9501 pf->pdev = pdev;
9502 set_bit(__I40E_DOWN, &pf->state);
9503
9504 hw = &pf->hw;
9505 hw->back = pf;
9506 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9507 pci_resource_len(pdev, 0));
9508 if (!hw->hw_addr) {
9509 err = -EIO;
9510 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9511 (unsigned int)pci_resource_start(pdev, 0),
9512 (unsigned int)pci_resource_len(pdev, 0), err);
9513 goto err_ioremap;
9514 }
9515 hw->vendor_id = pdev->vendor;
9516 hw->device_id = pdev->device;
9517 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9518 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9519 hw->subsystem_device_id = pdev->subsystem_device;
9520 hw->bus.device = PCI_SLOT(pdev->devfn);
9521 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9522 pf->instance = pfs_found;
41c445ff 9523
5b5faa43
SN		 9524 if (debug != -1) {
9525 pf->msg_enable = pf->hw.debug_mask;
9526 pf->msg_enable = debug;
9527 }
9528
7134f9ce
JB		 9529 /* do a special CORER for clearing PXE mode once at init */
9530 if (hw->revision_id == 0 &&
9531 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9532 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9533 i40e_flush(hw);
9534 msleep(200);
9535 pf->corer_count++;
9536
9537 i40e_clear_pxe_mode(hw);
9538 }
9539
41c445ff 9540 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9541 i40e_clear_hw(hw);
41c445ff
JB		 9542 err = i40e_pf_reset(hw);
9543 if (err) {
9544 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9545 goto err_pf_reset;
9546 }
9547 pf->pfr_count++;
9548
9549 hw->aq.num_arq_entries = I40E_AQ_LEN;
9550 hw->aq.num_asq_entries = I40E_AQ_LEN;
9551 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9552 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9553 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 9554
b294ac70 9555 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 9556 "%s-%s:misc",
9557 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 9558
9559 err = i40e_init_shared_code(hw);
9560 if (err) {
9561 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9562 goto err_pf_reset;
9563 }
9564
d52c20b7
JB		 9565 /* set up a default setting for link flow control */
9566 pf->hw.fc.requested_mode = I40E_FC_NONE;
9567
41c445ff
JB		 9568 err = i40e_init_adminq(hw);
9569 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9570 if (err) {
9571 dev_info(&pdev->dev,
7aa67613 9572 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9573 goto err_pf_reset;
9574 }
9575
7aa67613
CS		 9576 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9577 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9578 dev_info(&pdev->dev,
7aa67613
CS		 9579 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9580 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9581 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9582 dev_info(&pdev->dev,
7aa67613 9583 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62
SN		 9584
9585
4eb3f768
SN		 9586 i40e_verify_eeprom(pf);
9587
2c5fe33b
JB		 9588 /* Rev 0 hardware was never productized */
9589 if (hw->revision_id < 1)
9590 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9591
6ff4ef86 9592 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9593 err = i40e_get_capabilities(pf);
9594 if (err)
9595 goto err_adminq_setup;
9596
9597 err = i40e_sw_init(pf);
9598 if (err) {
9599 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9600 goto err_sw_init;
9601 }
9602
9603 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9604 hw->func_caps.num_rx_qp,
9605 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9606 if (err) {
9607 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9608 goto err_init_lan_hmc;
9609 }
9610
9611 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9612 if (err) {
9613 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9614 err = -ENOENT;
9615 goto err_configure_lan_hmc;
9616 }
9617
b686ece5
NP		 9618 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
9619 * Ignore error return codes because if it was already disabled via
9620 * hardware settings this will fail
9621 */
9622 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
9623 (pf->hw.aq.fw_maj_ver < 4)) {
9624 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
9625 i40e_aq_stop_lldp(hw, true, NULL);
9626 }
9627
41c445ff 9628 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9629 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9630 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9631 err = -EIO;
9632 goto err_mac_addr;
9633 }
9634 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9635 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9636 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9637 if (is_valid_ether_addr(hw->mac.port_addr))
9638 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9639#ifdef I40E_FCOE
9640 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9641 if (err)
9642 dev_info(&pdev->dev,
9643 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9644 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9645 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9646 hw->mac.san_addr);
9647 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9648 }
9649 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9650#endif /* I40E_FCOE */
41c445ff
JB		 9651
9652 pci_set_drvdata(pdev, pf);
9653 pci_save_state(pdev);
4e3b35b0
NP		 9654#ifdef CONFIG_I40E_DCB
9655 err = i40e_init_pf_dcb(pf);
9656 if (err) {
aebfc816 9657 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 9658 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9659 /* Continue without DCB enabled */
4e3b35b0
NP		 9660 }
9661#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9662
9663 /* set up periodic task facility */
9664 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9665 pf->service_timer_period = HZ;
9666
9667 INIT_WORK(&pf->service_task, i40e_service_task);
9668 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9669 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9670 pf->link_check_timeout = jiffies;
9671
8e2773ae
SN		 9672 /* WoL defaults to disabled */
9673 pf->wol_en = false;
9674 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9675
41c445ff
JB		 9676 /* set up the main switch operations */
9677 i40e_determine_queue_usage(pf);
9678 i40e_init_interrupt_scheme(pf);
9679
505682cd
MW		 9680 /* The number of VSIs reported by the FW is the minimum guaranteed
9681 * to us; HW supports far more and we share the remaining pool with
9682 * the other PFs. We allocate space for more than the guarantee with
9683 * the understanding that we might not get them all later.
41c445ff 9684 */
505682cd
MW		 9685 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9686 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9687 else
9688 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9689
9690 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9691 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9692 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9693 if (!pf->vsi) {
9694 err = -ENOMEM;
41c445ff 9695 goto err_switch_setup;
ed87ac09 9696 }
41c445ff 9697
bc7d338f 9698 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9699 if (err) {
9700 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9701 goto err_vsis;
9702 }
8a9eb7d3 9703 /* if FDIR VSI was set up, start it now */
505682cd 9704 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9705 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9706 i40e_vsi_open(pf->vsi[i]);
9707 break;
9708 }
9709 }
41c445ff 9710
7e2453fe
JB		 9711 /* driver is only interested in link up/down and module qualification
9712 * reports from firmware
9713 */
9714 err = i40e_aq_set_phy_int_mask(&pf->hw,
9715 I40E_AQ_EVENT_LINK_UPDOWN |
9716 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9717 if (err)
9718 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9719
025b4a54
ASJ		 9720 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
9721 (pf->hw.aq.fw_maj_ver < 4)) {
9722 msleep(75);
9723 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9724 if (err)
9725 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9726 pf->hw.aq.asq_last_status);
cafa2ee6 9727 }
41c445ff
JB		 9728 /* The main driver is (mostly) up and happy. We need to set this state
9729 * before setting up the misc vector or we get a race and the vector
9730 * ends up disabled forever.
9731 */
9732 clear_bit(__I40E_DOWN, &pf->state);
9733
9734 /* In case of MSIX we are going to setup the misc vector right here
9735 * to handle admin queue events etc. In case of legacy and MSI
9736 * the misc functionality and queue processing is combined in
9737 * the same vector and that gets setup at open.
9738 */
9739 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9740 err = i40e_setup_misc_vector(pf);
9741 if (err) {
9742 dev_info(&pdev->dev,
9743 "setup of misc vector failed: %d\n", err);
9744 goto err_vsis;
9745 }
9746 }
9747
df805f62 9748#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9749 /* prep for VF support */
9750 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9751 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9752 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9753 u32 val;
9754
9755 /* disable link interrupts for VFs */
9756 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9757 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9758 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9759 i40e_flush(hw);
4aeec010
MW		 9760
9761 if (pci_num_vf(pdev)) {
9762 dev_info(&pdev->dev,
9763 "Active VFs found, allocating resources.\n");
9764 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9765 if (err)
9766 dev_info(&pdev->dev,
9767 "Error %d allocating resources for existing VFs\n",
9768 err);
9769 }
41c445ff 9770 }
df805f62 9771#endif /* CONFIG_PCI_IOV */
41c445ff 9772
93cd765b
ASJ		 9773 pfs_found++;
9774
41c445ff
JB		 9775 i40e_dbg_pf_init(pf);
9776
9777 /* tell the firmware that we're starting */
44033fac 9778 i40e_send_version(pf);
41c445ff
JB		 9779
9780 /* since everything's happy, start the service_task timer */
9781 mod_timer(&pf->service_timer,
9782 round_jiffies(jiffies + pf->service_timer_period));
9783
38e00438
VD		 9784#ifdef I40E_FCOE
9785 /* create FCoE interface */
9786 i40e_fcoe_vsi_setup(pf);
9787
9788#endif
d4dfb81a
CS		 9789 /* Get the negotiated link width and speed from PCI config space */
9790 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9791
9792 i40e_set_pci_config_data(hw, link_status);
9793
69bfb110 9794 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9795 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9796 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9797 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9798 "Unknown"),
9799 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9800 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9801 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9802 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9803 "Unknown"));
9804
9805 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9806 hw->bus.speed < i40e_bus_speed_8000) {
9807 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9808 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9809 }
9810
e827845c
CS		 9811 /* get the requested speeds from the fw */
9812 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
9813 if (err)
9814 dev_info(&pf->pdev->dev, "get phy abilities failed, aq_err %d, advertised speed settings may not be correct\n",
9815 err);
9816 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
9817
0c22b3dd
JB		 9818 /* print a string summarizing features */
9819 i40e_print_features(pf);
9820
41c445ff
JB		 9821 return 0;
9822
9823 /* Unwind what we've done if something failed in the setup */
9824err_vsis:
9825 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9826 i40e_clear_interrupt_scheme(pf);
9827 kfree(pf->vsi);
04b03013
SN		 9828err_switch_setup:
9829 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9830 del_timer_sync(&pf->service_timer);
9831err_mac_addr:
9832err_configure_lan_hmc:
9833 (void)i40e_shutdown_lan_hmc(hw);
9834err_init_lan_hmc:
9835 kfree(pf->qp_pile);
9836 kfree(pf->irq_pile);
9837err_sw_init:
9838err_adminq_setup:
9839 (void)i40e_shutdown_adminq(hw);
9840err_pf_reset:
9841 iounmap(hw->hw_addr);
9842err_ioremap:
9843 kfree(pf);
9844err_pf_alloc:
9845 pci_disable_pcie_error_reporting(pdev);
9846 pci_release_selected_regions(pdev,
9847 pci_select_bars(pdev, IORESOURCE_MEM));
9848err_pci_reg:
9849err_dma:
9850 pci_disable_device(pdev);
9851 return err;
9852}
9853
9854/**
9855 * i40e_remove - Device removal routine
9856 * @pdev: PCI device information struct
9857 *
9858 * i40e_remove is called by the PCI subsystem to alert the driver
9859 * that is should release a PCI device. This could be caused by a
9860 * Hot-Plug event, or because the driver is going to be removed from
9861 * memory.
9862 **/
9863static void i40e_remove(struct pci_dev *pdev)
9864{
9865 struct i40e_pf *pf = pci_get_drvdata(pdev);
9866 i40e_status ret_code;
41c445ff
JB		 9867 int i;
9868
9869 i40e_dbg_pf_exit(pf);
9870
beb0dff1
JK		 9871 i40e_ptp_stop(pf);
9872
41c445ff
JB		 9873 /* no more scheduling of any task */
9874 set_bit(__I40E_DOWN, &pf->state);
9875 del_timer_sync(&pf->service_timer);
9876 cancel_work_sync(&pf->service_task);
33c62b34 9877 i40e_fdir_teardown(pf);
41c445ff 9878
eb2d80bc
MW		 9879 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
9880 i40e_free_vfs(pf);
9881 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
9882 }
9883
41c445ff
JB		 9884 i40e_fdir_teardown(pf);
9885
9886 /* If there is a switch structure or any orphans, remove them.
9887 * This will leave only the PF's VSI remaining.
9888 */
9889 for (i = 0; i < I40E_MAX_VEB; i++) {
9890 if (!pf->veb[i])
9891 continue;
9892
9893 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
9894 pf->veb[i]->uplink_seid == 0)
9895 i40e_switch_branch_release(pf->veb[i]);
9896 }
9897
9898 /* Now we can shutdown the PF's VSI, just before we kill
9899 * adminq and hmc.
9900 */
9901 if (pf->vsi[pf->lan_vsi])
9902 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
9903
41c445ff 9904 /* shutdown and destroy the HMC */
60442dea
SN		 9905 if (pf->hw.hmc.hmc_obj) {
9906 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
9907 if (ret_code)
9908 dev_warn(&pdev->dev,
9909 "Failed to destroy the HMC resources: %d\n",
9910 ret_code);
9911 }
41c445ff
JB		 9912
9913 /* shutdown the adminq */
41c445ff
JB		 9914 ret_code = i40e_shutdown_adminq(&pf->hw);
9915 if (ret_code)
9916 dev_warn(&pdev->dev,
9917 "Failed to destroy the Admin Queue resources: %d\n",
9918 ret_code);
9919
9920 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
9921 i40e_clear_interrupt_scheme(pf);
505682cd 9922 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9923 if (pf->vsi[i]) {
9924 i40e_vsi_clear_rings(pf->vsi[i]);
9925 i40e_vsi_clear(pf->vsi[i]);
9926 pf->vsi[i] = NULL;
9927 }
9928 }
9929
9930 for (i = 0; i < I40E_MAX_VEB; i++) {
9931 kfree(pf->veb[i]);
9932 pf->veb[i] = NULL;
9933 }
9934
9935 kfree(pf->qp_pile);
9936 kfree(pf->irq_pile);
41c445ff
JB		 9937 kfree(pf->vsi);
9938
41c445ff
JB		 9939 iounmap(pf->hw.hw_addr);
9940 kfree(pf);
9941 pci_release_selected_regions(pdev,
9942 pci_select_bars(pdev, IORESOURCE_MEM));
9943
9944 pci_disable_pcie_error_reporting(pdev);
9945 pci_disable_device(pdev);
9946}
9947
9948/**
9949 * i40e_pci_error_detected - warning that something funky happened in PCI land
9950 * @pdev: PCI device information struct
9951 *
9952 * Called to warn that something happened and the error handling steps
9953 * are in progress. Allows the driver to quiesce things, be ready for
9954 * remediation.
9955 **/
9956static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
9957 enum pci_channel_state error)
9958{
9959 struct i40e_pf *pf = pci_get_drvdata(pdev);
9960
9961 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9962
9963 /* shutdown all operations */
9007bccd
SN		 9964 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9965 rtnl_lock();
9966 i40e_prep_for_reset(pf);
9967 rtnl_unlock();
9968 }
41c445ff
JB		 9969
9970 /* Request a slot reset */
9971 return PCI_ERS_RESULT_NEED_RESET;
9972}
9973
9974/**
9975 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9976 * @pdev: PCI device information struct
9977 *
9978 * Called to find if the driver can work with the device now that
9979 * the pci slot has been reset. If a basic connection seems good
9980 * (registers are readable and have sane content) then return a
9981 * happy little PCI_ERS_RESULT_xxx.
9982 **/
9983static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9984{
9985 struct i40e_pf *pf = pci_get_drvdata(pdev);
9986 pci_ers_result_t result;
9987 int err;
9988 u32 reg;
9989
9990 dev_info(&pdev->dev, "%s\n", __func__);
9991 if (pci_enable_device_mem(pdev)) {
9992 dev_info(&pdev->dev,
9993 "Cannot re-enable PCI device after reset.\n");
9994 result = PCI_ERS_RESULT_DISCONNECT;
9995 } else {
9996 pci_set_master(pdev);
9997 pci_restore_state(pdev);
9998 pci_save_state(pdev);
9999 pci_wake_from_d3(pdev, false);
10000
10001 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10002 if (reg == 0)
10003 result = PCI_ERS_RESULT_RECOVERED;
10004 else
10005 result = PCI_ERS_RESULT_DISCONNECT;
10006 }
10007
10008 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10009 if (err) {
10010 dev_info(&pdev->dev,
10011 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10012 err);
10013 /* non-fatal, continue */
10014 }
10015
10016 return result;
10017}
10018
10019/**
10020 * i40e_pci_error_resume - restart operations after PCI error recovery
10021 * @pdev: PCI device information struct
10022 *
10023 * Called to allow the driver to bring things back up after PCI error
10024 * and/or reset recovery has finished.
10025 **/
10026static void i40e_pci_error_resume(struct pci_dev *pdev)
10027{
10028 struct i40e_pf *pf = pci_get_drvdata(pdev);
10029
10030 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10031 if (test_bit(__I40E_SUSPENDED, &pf->state))
10032 return;
10033
10034 rtnl_lock();
41c445ff 10035 i40e_handle_reset_warning(pf);
9007bccd
SN		 10036 rtnl_lock();
10037}
10038
10039/**
10040 * i40e_shutdown - PCI callback for shutting down
10041 * @pdev: PCI device information struct
10042 **/
10043static void i40e_shutdown(struct pci_dev *pdev)
10044{
10045 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10046 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10047
10048 set_bit(__I40E_SUSPENDED, &pf->state);
10049 set_bit(__I40E_DOWN, &pf->state);
10050 rtnl_lock();
10051 i40e_prep_for_reset(pf);
10052 rtnl_unlock();
10053
8e2773ae
SN		 10054 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10055 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10056
e147758d
SN		 10057 i40e_clear_interrupt_scheme(pf);
10058
9007bccd 10059 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10060 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10061 pci_set_power_state(pdev, PCI_D3hot);
10062 }
10063}
10064
10065#ifdef CONFIG_PM
10066/**
10067 * i40e_suspend - PCI callback for moving to D3
10068 * @pdev: PCI device information struct
10069 **/
10070static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10071{
10072 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10073 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10074
10075 set_bit(__I40E_SUSPENDED, &pf->state);
10076 set_bit(__I40E_DOWN, &pf->state);
88086e5d
MW		 10077 del_timer_sync(&pf->service_timer);
10078 cancel_work_sync(&pf->service_task);
9007bccd
SN		 10079 rtnl_lock();
10080 i40e_prep_for_reset(pf);
10081 rtnl_unlock();
10082
8e2773ae
SN		 10083 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10084 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10085
10086 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10087 pci_set_power_state(pdev, PCI_D3hot);
10088
10089 return 0;
41c445ff
JB		 10090}
10091
9007bccd
SN		 10092/**
10093 * i40e_resume - PCI callback for waking up from D3
10094 * @pdev: PCI device information struct
10095 **/
10096static int i40e_resume(struct pci_dev *pdev)
10097{
10098 struct i40e_pf *pf = pci_get_drvdata(pdev);
10099 u32 err;
10100
10101 pci_set_power_state(pdev, PCI_D0);
10102 pci_restore_state(pdev);
10103 /* pci_restore_state() clears dev->state_saves, so
10104 * call pci_save_state() again to restore it.
10105 */
10106 pci_save_state(pdev);
10107
10108 err = pci_enable_device_mem(pdev);
10109 if (err) {
10110 dev_err(&pdev->dev,
10111 "%s: Cannot enable PCI device from suspend\n",
10112 __func__);
10113 return err;
10114 }
10115 pci_set_master(pdev);
10116
10117 /* no wakeup events while running */
10118 pci_wake_from_d3(pdev, false);
10119
10120 /* handling the reset will rebuild the device state */
10121 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10122 clear_bit(__I40E_DOWN, &pf->state);
10123 rtnl_lock();
10124 i40e_reset_and_rebuild(pf, false);
10125 rtnl_unlock();
10126 }
10127
10128 return 0;
10129}
10130
10131#endif
41c445ff
JB		 10132static const struct pci_error_handlers i40e_err_handler = {
10133 .error_detected = i40e_pci_error_detected,
10134 .slot_reset = i40e_pci_error_slot_reset,
10135 .resume = i40e_pci_error_resume,
10136};
10137
10138static struct pci_driver i40e_driver = {
10139 .name = i40e_driver_name,
10140 .id_table = i40e_pci_tbl,
10141 .probe = i40e_probe,
10142 .remove = i40e_remove,
9007bccd
SN		 10143#ifdef CONFIG_PM
10144 .suspend = i40e_suspend,
10145 .resume = i40e_resume,
10146#endif
10147 .shutdown = i40e_shutdown,
41c445ff
JB		 10148 .err_handler = &i40e_err_handler,
10149 .sriov_configure = i40e_pci_sriov_configure,
10150};
10151
10152/**
10153 * i40e_init_module - Driver registration routine
10154 *
10155 * i40e_init_module is the first routine called when the driver is
10156 * loaded. All it does is register with the PCI subsystem.
10157 **/
10158static int __init i40e_init_module(void)
10159{
10160 pr_info("%s: %s - version %s\n", i40e_driver_name,
10161 i40e_driver_string, i40e_driver_version_str);
10162 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10163
e8ab38cf 10164#if IS_ENABLED(CONFIG_I40E_CONFIGFS_FS)
96664483 10165 i40e_configfs_init();
e8ab38cf 10166#endif /* CONFIG_I40E_CONFIGFS_FS */
41c445ff
JB		 10167 i40e_dbg_init();
10168 return pci_register_driver(&i40e_driver);
10169}
10170module_init(i40e_init_module);
10171
10172/**
10173 * i40e_exit_module - Driver exit cleanup routine
10174 *
10175 * i40e_exit_module is called just before the driver is removed
10176 * from memory.
10177 **/
10178static void __exit i40e_exit_module(void)
10179{
10180 pci_unregister_driver(&i40e_driver);
10181 i40e_dbg_exit();
e8ab38cf 10182#if IS_ENABLED(CONFIG_I40E_CONFIGFS_FS)
96664483 10183 i40e_configfs_exit();
e8ab38cf 10184#endif /* CONFIG_I40E_CONFIGFS_FS */
41c445ff
JB		 10185}
10186module_exit(i40e_exit_module);
Linux kernel - Deliverables
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