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i40e: fix bad CEE status shift value
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
42d255ce 41#define DRV_VERSION_MINOR 3
f91638af 42#define DRV_VERSION_BUILD 21
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 85 /* required last entry */
86 {0, }
87};
88MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
89
90#define I40E_MAX_VF_COUNT 128
91static int debug = -1;
92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
96MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
97MODULE_LICENSE("GPL");
98MODULE_VERSION(DRV_VERSION);
99
100/**
101 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
102 * @hw: pointer to the HW structure
103 * @mem: ptr to mem struct to fill out
104 * @size: size of memory requested
105 * @alignment: what to align the allocation to
106 **/
107int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
108 u64 size, u32 alignment)
109{
110 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
111
112 mem->size = ALIGN(size, alignment);
113 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
114 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 115 if (!mem->va)
116 return -ENOMEM;
41c445ff 117
93bc73b8 118 return 0;
41c445ff
JB		 119}
120
121/**
122 * i40e_free_dma_mem_d - OS specific memory free for shared code
123 * @hw: pointer to the HW structure
124 * @mem: ptr to mem struct to free
125 **/
126int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
127{
128 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
129
130 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
131 mem->va = NULL;
132 mem->pa = 0;
133 mem->size = 0;
134
135 return 0;
136}
137
138/**
139 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
140 * @hw: pointer to the HW structure
141 * @mem: ptr to mem struct to fill out
142 * @size: size of memory requested
143 **/
144int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
145 u32 size)
146{
147 mem->size = size;
148 mem->va = kzalloc(size, GFP_KERNEL);
149
93bc73b8
JB		 150 if (!mem->va)
151 return -ENOMEM;
41c445ff 152
93bc73b8 153 return 0;
41c445ff
JB		 154}
155
156/**
157 * i40e_free_virt_mem_d - OS specific memory free for shared code
158 * @hw: pointer to the HW structure
159 * @mem: ptr to mem struct to free
160 **/
161int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
162{
163 /* it's ok to kfree a NULL pointer */
164 kfree(mem->va);
165 mem->va = NULL;
166 mem->size = 0;
167
168 return 0;
169}
170
171/**
172 * i40e_get_lump - find a lump of free generic resource
173 * @pf: board private structure
174 * @pile: the pile of resource to search
175 * @needed: the number of items needed
176 * @id: an owner id to stick on the items assigned
177 *
178 * Returns the base item index of the lump, or negative for error
179 *
180 * The search_hint trick and lack of advanced fit-finding only work
181 * because we're highly likely to have all the same size lump requests.
182 * Linear search time and any fragmentation should be minimal.
183 **/
184static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
185 u16 needed, u16 id)
186{
187 int ret = -ENOMEM;
ddf434ac 188 int i, j;
41c445ff
JB		 189
190 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
191 dev_info(&pf->pdev->dev,
192 "param err: pile=%p needed=%d id=0x%04x\n",
193 pile, needed, id);
194 return -EINVAL;
195 }
196
197 /* start the linear search with an imperfect hint */
198 i = pile->search_hint;
ddf434ac 199 while (i < pile->num_entries) {
41c445ff
JB		 200 /* skip already allocated entries */
201 if (pile->list[i] & I40E_PILE_VALID_BIT) {
202 i++;
203 continue;
204 }
205
206 /* do we have enough in this lump? */
207 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
208 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
209 break;
210 }
211
212 if (j == needed) {
213 /* there was enough, so assign it to the requestor */
214 for (j = 0; j < needed; j++)
215 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
216 ret = i;
217 pile->search_hint = i + j;
ddf434ac 218 break;
41c445ff
JB		 219 } else {
220 /* not enough, so skip over it and continue looking */
221 i += j;
222 }
223 }
224
225 return ret;
226}
227
228/**
229 * i40e_put_lump - return a lump of generic resource
230 * @pile: the pile of resource to search
231 * @index: the base item index
232 * @id: the owner id of the items assigned
233 *
234 * Returns the count of items in the lump
235 **/
236static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
237{
238 int valid_id = (id | I40E_PILE_VALID_BIT);
239 int count = 0;
240 int i;
241
242 if (!pile || index >= pile->num_entries)
243 return -EINVAL;
244
245 for (i = index;
246 i < pile->num_entries && pile->list[i] == valid_id;
247 i++) {
248 pile->list[i] = 0;
249 count++;
250 }
251
252 if (count && index < pile->search_hint)
253 pile->search_hint = index;
254
255 return count;
256}
257
fdf0e0bf
ASJ		 258/**
259 * i40e_find_vsi_from_id - searches for the vsi with the given id
260 * @pf - the pf structure to search for the vsi
261 * @id - id of the vsi it is searching for
262 **/
263struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
264{
265 int i;
266
267 for (i = 0; i < pf->num_alloc_vsi; i++)
268 if (pf->vsi[i] && (pf->vsi[i]->id == id))
269 return pf->vsi[i];
270
271 return NULL;
272}
273
41c445ff
JB		 274/**
275 * i40e_service_event_schedule - Schedule the service task to wake up
276 * @pf: board private structure
277 *
278 * If not already scheduled, this puts the task into the work queue
279 **/
280static void i40e_service_event_schedule(struct i40e_pf *pf)
281{
282 if (!test_bit(__I40E_DOWN, &pf->state) &&
283 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
284 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
285 schedule_work(&pf->service_task);
286}
287
288/**
289 * i40e_tx_timeout - Respond to a Tx Hang
290 * @netdev: network interface device structure
291 *
292 * If any port has noticed a Tx timeout, it is likely that the whole
293 * device is munged, not just the one netdev port, so go for the full
294 * reset.
295 **/
38e00438
VD		 296#ifdef I40E_FCOE
297void i40e_tx_timeout(struct net_device *netdev)
298#else
41c445ff 299static void i40e_tx_timeout(struct net_device *netdev)
38e00438 300#endif
41c445ff
JB		 301{
302 struct i40e_netdev_priv *np = netdev_priv(netdev);
303 struct i40e_vsi *vsi = np->vsi;
304 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 305 struct i40e_ring *tx_ring = NULL;
306 unsigned int i, hung_queue = 0;
307 u32 head, val;
41c445ff
JB		 308
309 pf->tx_timeout_count++;
310
b03a8c1f
KP		 311 /* find the stopped queue the same way the stack does */
312 for (i = 0; i < netdev->num_tx_queues; i++) {
313 struct netdev_queue *q;
314 unsigned long trans_start;
315
316 q = netdev_get_tx_queue(netdev, i);
317 trans_start = q->trans_start ? : netdev->trans_start;
318 if (netif_xmit_stopped(q) &&
319 time_after(jiffies,
320 (trans_start + netdev->watchdog_timeo))) {
321 hung_queue = i;
322 break;
323 }
324 }
325
326 if (i == netdev->num_tx_queues) {
327 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
328 } else {
329 /* now that we have an index, find the tx_ring struct */
330 for (i = 0; i < vsi->num_queue_pairs; i++) {
331 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
332 if (hung_queue ==
333 vsi->tx_rings[i]->queue_index) {
334 tx_ring = vsi->tx_rings[i];
335 break;
336 }
337 }
338 }
339 }
340
41c445ff 341 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 342 pf->tx_timeout_recovery_level = 1; /* reset after some time */
343 else if (time_before(jiffies,
344 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
345 return; /* don't do any new action before the next timeout */
346
347 if (tx_ring) {
348 head = i40e_get_head(tx_ring);
349 /* Read interrupt register */
350 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
351 val = rd32(&pf->hw,
352 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
353 tx_ring->vsi->base_vector - 1));
354 else
355 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
356
357 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
358 vsi->seid, hung_queue, tx_ring->next_to_clean,
359 head, tx_ring->next_to_use,
360 readl(tx_ring->tail), val);
361 }
362
41c445ff 363 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 364 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
365 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 366
367 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 368 case 1:
369 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
370 break;
371 case 2:
372 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
373 break;
374 case 3:
375 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
376 break;
377 default:
378 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 379 break;
380 }
b03a8c1f 381
41c445ff
JB		 382 i40e_service_event_schedule(pf);
383 pf->tx_timeout_recovery_level++;
384}
385
386/**
387 * i40e_release_rx_desc - Store the new tail and head values
388 * @rx_ring: ring to bump
389 * @val: new head index
390 **/
391static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
392{
393 rx_ring->next_to_use = val;
394
395 /* Force memory writes to complete before letting h/w
396 * know there are new descriptors to fetch. (Only
397 * applicable for weak-ordered memory model archs,
398 * such as IA-64).
399 */
400 wmb();
401 writel(val, rx_ring->tail);
402}
403
404/**
405 * i40e_get_vsi_stats_struct - Get System Network Statistics
406 * @vsi: the VSI we care about
407 *
408 * Returns the address of the device statistics structure.
409 * The statistics are actually updated from the service task.
410 **/
411struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
412{
413 return &vsi->net_stats;
414}
415
416/**
417 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
418 * @netdev: network interface device structure
419 *
420 * Returns the address of the device statistics structure.
421 * The statistics are actually updated from the service task.
422 **/
38e00438
VD		 423#ifdef I40E_FCOE
424struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
425 struct net_device *netdev,
426 struct rtnl_link_stats64 *stats)
427#else
41c445ff
JB		 428static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
429 struct net_device *netdev,
980e9b11 430 struct rtnl_link_stats64 *stats)
38e00438 431#endif
41c445ff
JB		 432{
433 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 434 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 435 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 436 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
437 int i;
438
bc7d338f
ASJ		 439 if (test_bit(__I40E_DOWN, &vsi->state))
440 return stats;
441
3c325ced
JB		 442 if (!vsi->tx_rings)
443 return stats;
444
980e9b11
AD		 445 rcu_read_lock();
446 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 447 u64 bytes, packets;
448 unsigned int start;
449
450 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
451 if (!tx_ring)
452 continue;
453
454 do {
57a7744e 455 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 456 packets = tx_ring->stats.packets;
457 bytes = tx_ring->stats.bytes;
57a7744e 458 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 459
460 stats->tx_packets += packets;
461 stats->tx_bytes += bytes;
462 rx_ring = &tx_ring[1];
463
464 do {
57a7744e 465 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 466 packets = rx_ring->stats.packets;
467 bytes = rx_ring->stats.bytes;
57a7744e 468 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 469
980e9b11
AD		 470 stats->rx_packets += packets;
471 stats->rx_bytes += bytes;
472 }
473 rcu_read_unlock();
474
a5282f44 475 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 476 stats->multicast = vsi_stats->multicast;
477 stats->tx_errors = vsi_stats->tx_errors;
478 stats->tx_dropped = vsi_stats->tx_dropped;
479 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 480 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 481 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
482 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 483
980e9b11 484 return stats;
41c445ff
JB		 485}
486
487/**
488 * i40e_vsi_reset_stats - Resets all stats of the given vsi
489 * @vsi: the VSI to have its stats reset
490 **/
491void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
492{
493 struct rtnl_link_stats64 *ns;
494 int i;
495
496 if (!vsi)
497 return;
498
499 ns = i40e_get_vsi_stats_struct(vsi);
500 memset(ns, 0, sizeof(*ns));
501 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
502 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
503 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 504 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 505 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 506 memset(&vsi->rx_rings[i]->stats, 0 ,
507 sizeof(vsi->rx_rings[i]->stats));
508 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
509 sizeof(vsi->rx_rings[i]->rx_stats));
510 memset(&vsi->tx_rings[i]->stats, 0 ,
511 sizeof(vsi->tx_rings[i]->stats));
512 memset(&vsi->tx_rings[i]->tx_stats, 0,
513 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 514 }
8e9dca53 515 }
41c445ff
JB		 516 vsi->stat_offsets_loaded = false;
517}
518
519/**
b40c82e6 520 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 521 * @pf: the PF to be reset
522 **/
523void i40e_pf_reset_stats(struct i40e_pf *pf)
524{
e91fdf76
SN		 525 int i;
526
41c445ff
JB		 527 memset(&pf->stats, 0, sizeof(pf->stats));
528 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
529 pf->stat_offsets_loaded = false;
e91fdf76
SN		 530
531 for (i = 0; i < I40E_MAX_VEB; i++) {
532 if (pf->veb[i]) {
533 memset(&pf->veb[i]->stats, 0,
534 sizeof(pf->veb[i]->stats));
535 memset(&pf->veb[i]->stats_offsets, 0,
536 sizeof(pf->veb[i]->stats_offsets));
537 pf->veb[i]->stat_offsets_loaded = false;
538 }
539 }
41c445ff
JB		 540}
541
542/**
543 * i40e_stat_update48 - read and update a 48 bit stat from the chip
544 * @hw: ptr to the hardware info
545 * @hireg: the high 32 bit reg to read
546 * @loreg: the low 32 bit reg to read
547 * @offset_loaded: has the initial offset been loaded yet
548 * @offset: ptr to current offset value
549 * @stat: ptr to the stat
550 *
551 * Since the device stats are not reset at PFReset, they likely will not
552 * be zeroed when the driver starts. We'll save the first values read
553 * and use them as offsets to be subtracted from the raw values in order
554 * to report stats that count from zero. In the process, we also manage
555 * the potential roll-over.
556 **/
557static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
558 bool offset_loaded, u64 *offset, u64 *stat)
559{
560 u64 new_data;
561
ab60085e 562 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 563 new_data = rd32(hw, loreg);
564 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
565 } else {
566 new_data = rd64(hw, loreg);
567 }
568 if (!offset_loaded)
569 *offset = new_data;
570 if (likely(new_data >= *offset))
571 *stat = new_data - *offset;
572 else
41a1d04b 573 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 574 *stat &= 0xFFFFFFFFFFFFULL;
575}
576
577/**
578 * i40e_stat_update32 - read and update a 32 bit stat from the chip
579 * @hw: ptr to the hardware info
580 * @reg: the hw reg to read
581 * @offset_loaded: has the initial offset been loaded yet
582 * @offset: ptr to current offset value
583 * @stat: ptr to the stat
584 **/
585static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
586 bool offset_loaded, u64 *offset, u64 *stat)
587{
588 u32 new_data;
589
590 new_data = rd32(hw, reg);
591 if (!offset_loaded)
592 *offset = new_data;
593 if (likely(new_data >= *offset))
594 *stat = (u32)(new_data - *offset);
595 else
41a1d04b 596 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 597}
598
599/**
600 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
601 * @vsi: the VSI to be updated
602 **/
603void i40e_update_eth_stats(struct i40e_vsi *vsi)
604{
605 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
606 struct i40e_pf *pf = vsi->back;
607 struct i40e_hw *hw = &pf->hw;
608 struct i40e_eth_stats *oes;
609 struct i40e_eth_stats *es; /* device's eth stats */
610
611 es = &vsi->eth_stats;
612 oes = &vsi->eth_stats_offsets;
613
614 /* Gather up the stats that the hw collects */
615 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
616 vsi->stat_offsets_loaded,
617 &oes->tx_errors, &es->tx_errors);
618 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
619 vsi->stat_offsets_loaded,
620 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 621 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
622 vsi->stat_offsets_loaded,
623 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
624 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
625 vsi->stat_offsets_loaded,
626 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 627
628 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
629 I40E_GLV_GORCL(stat_idx),
630 vsi->stat_offsets_loaded,
631 &oes->rx_bytes, &es->rx_bytes);
632 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
633 I40E_GLV_UPRCL(stat_idx),
634 vsi->stat_offsets_loaded,
635 &oes->rx_unicast, &es->rx_unicast);
636 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
637 I40E_GLV_MPRCL(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->rx_multicast, &es->rx_multicast);
640 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
641 I40E_GLV_BPRCL(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->rx_broadcast, &es->rx_broadcast);
644
645 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
646 I40E_GLV_GOTCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->tx_bytes, &es->tx_bytes);
649 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
650 I40E_GLV_UPTCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->tx_unicast, &es->tx_unicast);
653 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
654 I40E_GLV_MPTCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->tx_multicast, &es->tx_multicast);
657 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
658 I40E_GLV_BPTCL(stat_idx),
659 vsi->stat_offsets_loaded,
660 &oes->tx_broadcast, &es->tx_broadcast);
661 vsi->stat_offsets_loaded = true;
662}
663
664/**
665 * i40e_update_veb_stats - Update Switch component statistics
666 * @veb: the VEB being updated
667 **/
668static void i40e_update_veb_stats(struct i40e_veb *veb)
669{
670 struct i40e_pf *pf = veb->pf;
671 struct i40e_hw *hw = &pf->hw;
672 struct i40e_eth_stats *oes;
673 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 674 struct i40e_veb_tc_stats *veb_oes;
675 struct i40e_veb_tc_stats *veb_es;
676 int i, idx = 0;
41c445ff
JB		 677
678 idx = veb->stats_idx;
679 es = &veb->stats;
680 oes = &veb->stats_offsets;
fe860afb
NP		 681 veb_es = &veb->tc_stats;
682 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 683
684 /* Gather up the stats that the hw collects */
685 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
686 veb->stat_offsets_loaded,
687 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 688 if (hw->revision_id > 0)
689 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
690 veb->stat_offsets_loaded,
691 &oes->rx_unknown_protocol,
692 &es->rx_unknown_protocol);
41c445ff
JB		 693 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
694 veb->stat_offsets_loaded,
695 &oes->rx_bytes, &es->rx_bytes);
696 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
697 veb->stat_offsets_loaded,
698 &oes->rx_unicast, &es->rx_unicast);
699 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
700 veb->stat_offsets_loaded,
701 &oes->rx_multicast, &es->rx_multicast);
702 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
703 veb->stat_offsets_loaded,
704 &oes->rx_broadcast, &es->rx_broadcast);
705
706 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_bytes, &es->tx_bytes);
709 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
710 veb->stat_offsets_loaded,
711 &oes->tx_unicast, &es->tx_unicast);
712 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
713 veb->stat_offsets_loaded,
714 &oes->tx_multicast, &es->tx_multicast);
715 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
716 veb->stat_offsets_loaded,
717 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 718 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
719 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
720 I40E_GLVEBTC_RPCL(i, idx),
721 veb->stat_offsets_loaded,
722 &veb_oes->tc_rx_packets[i],
723 &veb_es->tc_rx_packets[i]);
724 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
725 I40E_GLVEBTC_RBCL(i, idx),
726 veb->stat_offsets_loaded,
727 &veb_oes->tc_rx_bytes[i],
728 &veb_es->tc_rx_bytes[i]);
729 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
730 I40E_GLVEBTC_TPCL(i, idx),
731 veb->stat_offsets_loaded,
732 &veb_oes->tc_tx_packets[i],
733 &veb_es->tc_tx_packets[i]);
734 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
735 I40E_GLVEBTC_TBCL(i, idx),
736 veb->stat_offsets_loaded,
737 &veb_oes->tc_tx_bytes[i],
738 &veb_es->tc_tx_bytes[i]);
739 }
41c445ff
JB		 740 veb->stat_offsets_loaded = true;
741}
742
38e00438
VD		 743#ifdef I40E_FCOE
744/**
745 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
746 * @vsi: the VSI that is capable of doing FCoE
747 **/
748static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
749{
750 struct i40e_pf *pf = vsi->back;
751 struct i40e_hw *hw = &pf->hw;
752 struct i40e_fcoe_stats *ofs;
753 struct i40e_fcoe_stats *fs; /* device's eth stats */
754 int idx;
755
756 if (vsi->type != I40E_VSI_FCOE)
757 return;
758
759 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
760 fs = &vsi->fcoe_stats;
761 ofs = &vsi->fcoe_stats_offsets;
762
763 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
764 vsi->fcoe_stat_offsets_loaded,
765 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
766 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
767 vsi->fcoe_stat_offsets_loaded,
768 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
769 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
770 vsi->fcoe_stat_offsets_loaded,
771 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
772 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
773 vsi->fcoe_stat_offsets_loaded,
774 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
775 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
778 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
779 vsi->fcoe_stat_offsets_loaded,
780 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
781 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
782 vsi->fcoe_stat_offsets_loaded,
783 &ofs->fcoe_last_error, &fs->fcoe_last_error);
784 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
785 vsi->fcoe_stat_offsets_loaded,
786 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
787
788 vsi->fcoe_stat_offsets_loaded = true;
789}
790
791#endif
41c445ff
JB		 792/**
793 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
794 * @pf: the corresponding PF
795 *
796 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
797 **/
798static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
799{
800 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
801 struct i40e_hw_port_stats *nsd = &pf->stats;
802 struct i40e_hw *hw = &pf->hw;
803 u64 xoff = 0;
41c445ff
JB		 804
805 if ((hw->fc.current_mode != I40E_FC_FULL) &&
806 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
807 return;
808
809 xoff = nsd->link_xoff_rx;
810 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
811 pf->stat_offsets_loaded,
812 &osd->link_xoff_rx, &nsd->link_xoff_rx);
813
814 /* No new LFC xoff rx */
815 if (!(nsd->link_xoff_rx - xoff))
816 return;
817
41c445ff
JB		 818}
819
820/**
821 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
822 * @pf: the corresponding PF
823 *
824 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
825 **/
826static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
827{
828 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
829 struct i40e_hw_port_stats *nsd = &pf->stats;
830 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
831 struct i40e_dcbx_config *dcb_cfg;
832 struct i40e_hw *hw = &pf->hw;
b03a8c1f 833 u16 i;
41c445ff
JB		 834 u8 tc;
835
836 dcb_cfg = &hw->local_dcbx_config;
837
e120814d
NP		 838 /* Collect Link XOFF stats when PFC is disabled */
839 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 840 i40e_update_link_xoff_rx(pf);
841 return;
842 }
843
844 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
845 u64 prio_xoff = nsd->priority_xoff_rx[i];
846 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
847 pf->stat_offsets_loaded,
848 &osd->priority_xoff_rx[i],
849 &nsd->priority_xoff_rx[i]);
850
851 /* No new PFC xoff rx */
852 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
853 continue;
854 /* Get the TC for given priority */
855 tc = dcb_cfg->etscfg.prioritytable[i];
856 xoff[tc] = true;
857 }
41c445ff
JB		 858}
859
860/**
7812fddc 861 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 862 * @vsi: the VSI to be updated
863 *
864 * There are a few instances where we store the same stat in a
865 * couple of different structs. This is partly because we have
866 * the netdev stats that need to be filled out, which is slightly
867 * different from the "eth_stats" defined by the chip and used in
7812fddc 868 * VF communications. We sort it out here.
41c445ff 869 **/
7812fddc 870static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 871{
872 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 873 struct rtnl_link_stats64 *ons;
874 struct rtnl_link_stats64 *ns; /* netdev stats */
875 struct i40e_eth_stats *oes;
876 struct i40e_eth_stats *es; /* device's eth stats */
877 u32 tx_restart, tx_busy;
bf00b376 878 struct i40e_ring *p;
41c445ff 879 u32 rx_page, rx_buf;
bf00b376
AA		 880 u64 bytes, packets;
881 unsigned int start;
41c445ff
JB		 882 u64 rx_p, rx_b;
883 u64 tx_p, tx_b;
41c445ff
JB		 884 u16 q;
885
886 if (test_bit(__I40E_DOWN, &vsi->state) ||
887 test_bit(__I40E_CONFIG_BUSY, &pf->state))
888 return;
889
890 ns = i40e_get_vsi_stats_struct(vsi);
891 ons = &vsi->net_stats_offsets;
892 es = &vsi->eth_stats;
893 oes = &vsi->eth_stats_offsets;
894
895 /* Gather up the netdev and vsi stats that the driver collects
896 * on the fly during packet processing
897 */
898 rx_b = rx_p = 0;
899 tx_b = tx_p = 0;
900 tx_restart = tx_busy = 0;
901 rx_page = 0;
902 rx_buf = 0;
980e9b11 903 rcu_read_lock();
41c445ff 904 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 905 /* locate Tx ring */
906 p = ACCESS_ONCE(vsi->tx_rings[q]);
907
908 do {
57a7744e 909 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 910 packets = p->stats.packets;
911 bytes = p->stats.bytes;
57a7744e 912 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 913 tx_b += bytes;
914 tx_p += packets;
915 tx_restart += p->tx_stats.restart_queue;
916 tx_busy += p->tx_stats.tx_busy;
41c445ff 917
980e9b11
AD		 918 /* Rx queue is part of the same block as Tx queue */
919 p = &p[1];
920 do {
57a7744e 921 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 922 packets = p->stats.packets;
923 bytes = p->stats.bytes;
57a7744e 924 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 925 rx_b += bytes;
926 rx_p += packets;
420136cc
MW		 927 rx_buf += p->rx_stats.alloc_buff_failed;
928 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 929 }
980e9b11 930 rcu_read_unlock();
41c445ff
JB		 931 vsi->tx_restart = tx_restart;
932 vsi->tx_busy = tx_busy;
933 vsi->rx_page_failed = rx_page;
934 vsi->rx_buf_failed = rx_buf;
935
936 ns->rx_packets = rx_p;
937 ns->rx_bytes = rx_b;
938 ns->tx_packets = tx_p;
939 ns->tx_bytes = tx_b;
940
41c445ff 941 /* update netdev stats from eth stats */
7812fddc 942 i40e_update_eth_stats(vsi);
41c445ff
JB		 943 ons->tx_errors = oes->tx_errors;
944 ns->tx_errors = es->tx_errors;
945 ons->multicast = oes->rx_multicast;
946 ns->multicast = es->rx_multicast;
41a9e55c
SN		 947 ons->rx_dropped = oes->rx_discards;
948 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 949 ons->tx_dropped = oes->tx_discards;
950 ns->tx_dropped = es->tx_discards;
951
7812fddc 952 /* pull in a couple PF stats if this is the main vsi */
41c445ff 953 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 954 ns->rx_crc_errors = pf->stats.crc_errors;
955 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
956 ns->rx_length_errors = pf->stats.rx_length_errors;
957 }
958}
41c445ff 959
7812fddc 960/**
b40c82e6 961 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 962 * @pf: the PF to be updated
963 **/
964static void i40e_update_pf_stats(struct i40e_pf *pf)
965{
966 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
967 struct i40e_hw_port_stats *nsd = &pf->stats;
968 struct i40e_hw *hw = &pf->hw;
969 u32 val;
970 int i;
41c445ff 971
7812fddc
SN		 972 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
973 I40E_GLPRT_GORCL(hw->port),
974 pf->stat_offsets_loaded,
975 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
976 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
977 I40E_GLPRT_GOTCL(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
980 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->eth.rx_discards,
983 &nsd->eth.rx_discards);
532d283d
SN		 984 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
985 I40E_GLPRT_UPRCL(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->eth.rx_unicast,
988 &nsd->eth.rx_unicast);
7812fddc
SN		 989 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
990 I40E_GLPRT_MPRCL(hw->port),
991 pf->stat_offsets_loaded,
992 &osd->eth.rx_multicast,
993 &nsd->eth.rx_multicast);
532d283d
SN		 994 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
995 I40E_GLPRT_BPRCL(hw->port),
996 pf->stat_offsets_loaded,
997 &osd->eth.rx_broadcast,
998 &nsd->eth.rx_broadcast);
999 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
1000 I40E_GLPRT_UPTCL(hw->port),
1001 pf->stat_offsets_loaded,
1002 &osd->eth.tx_unicast,
1003 &nsd->eth.tx_unicast);
1004 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1005 I40E_GLPRT_MPTCL(hw->port),
1006 pf->stat_offsets_loaded,
1007 &osd->eth.tx_multicast,
1008 &nsd->eth.tx_multicast);
1009 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1010 I40E_GLPRT_BPTCL(hw->port),
1011 pf->stat_offsets_loaded,
1012 &osd->eth.tx_broadcast,
1013 &nsd->eth.tx_broadcast);
41c445ff 1014
7812fddc
SN		 1015 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1016 pf->stat_offsets_loaded,
1017 &osd->tx_dropped_link_down,
1018 &nsd->tx_dropped_link_down);
41c445ff 1019
7812fddc
SN		 1020 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1021 pf->stat_offsets_loaded,
1022 &osd->crc_errors, &nsd->crc_errors);
41c445ff 1023
7812fddc
SN		 1024 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 1027
7812fddc
SN		 1028 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->mac_local_faults,
1031 &nsd->mac_local_faults);
1032 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->mac_remote_faults,
1035 &nsd->mac_remote_faults);
41c445ff 1036
7812fddc
SN		 1037 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_length_errors,
1040 &nsd->rx_length_errors);
41c445ff 1041
7812fddc
SN		 1042 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1043 pf->stat_offsets_loaded,
1044 &osd->link_xon_rx, &nsd->link_xon_rx);
1045 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1046 pf->stat_offsets_loaded,
1047 &osd->link_xon_tx, &nsd->link_xon_tx);
1048 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1049 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1052
7812fddc
SN		 1053 for (i = 0; i < 8; i++) {
1054 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1055 pf->stat_offsets_loaded,
7812fddc
SN		 1056 &osd->priority_xon_rx[i],
1057 &nsd->priority_xon_rx[i]);
1058 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1059 pf->stat_offsets_loaded,
7812fddc
SN		 1060 &osd->priority_xon_tx[i],
1061 &nsd->priority_xon_tx[i]);
1062 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1063 pf->stat_offsets_loaded,
7812fddc
SN		 1064 &osd->priority_xoff_tx[i],
1065 &nsd->priority_xoff_tx[i]);
1066 i40e_stat_update32(hw,
1067 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1068 pf->stat_offsets_loaded,
7812fddc
SN		 1069 &osd->priority_xon_2_xoff[i],
1070 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1071 }
1072
7812fddc
SN		 1073 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1074 I40E_GLPRT_PRC64L(hw->port),
1075 pf->stat_offsets_loaded,
1076 &osd->rx_size_64, &nsd->rx_size_64);
1077 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1078 I40E_GLPRT_PRC127L(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_size_127, &nsd->rx_size_127);
1081 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1082 I40E_GLPRT_PRC255L(hw->port),
1083 pf->stat_offsets_loaded,
1084 &osd->rx_size_255, &nsd->rx_size_255);
1085 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1086 I40E_GLPRT_PRC511L(hw->port),
1087 pf->stat_offsets_loaded,
1088 &osd->rx_size_511, &nsd->rx_size_511);
1089 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1090 I40E_GLPRT_PRC1023L(hw->port),
1091 pf->stat_offsets_loaded,
1092 &osd->rx_size_1023, &nsd->rx_size_1023);
1093 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1094 I40E_GLPRT_PRC1522L(hw->port),
1095 pf->stat_offsets_loaded,
1096 &osd->rx_size_1522, &nsd->rx_size_1522);
1097 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1098 I40E_GLPRT_PRC9522L(hw->port),
1099 pf->stat_offsets_loaded,
1100 &osd->rx_size_big, &nsd->rx_size_big);
1101
1102 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1103 I40E_GLPRT_PTC64L(hw->port),
1104 pf->stat_offsets_loaded,
1105 &osd->tx_size_64, &nsd->tx_size_64);
1106 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1107 I40E_GLPRT_PTC127L(hw->port),
1108 pf->stat_offsets_loaded,
1109 &osd->tx_size_127, &nsd->tx_size_127);
1110 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1111 I40E_GLPRT_PTC255L(hw->port),
1112 pf->stat_offsets_loaded,
1113 &osd->tx_size_255, &nsd->tx_size_255);
1114 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1115 I40E_GLPRT_PTC511L(hw->port),
1116 pf->stat_offsets_loaded,
1117 &osd->tx_size_511, &nsd->tx_size_511);
1118 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1119 I40E_GLPRT_PTC1023L(hw->port),
1120 pf->stat_offsets_loaded,
1121 &osd->tx_size_1023, &nsd->tx_size_1023);
1122 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1123 I40E_GLPRT_PTC1522L(hw->port),
1124 pf->stat_offsets_loaded,
1125 &osd->tx_size_1522, &nsd->tx_size_1522);
1126 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1127 I40E_GLPRT_PTC9522L(hw->port),
1128 pf->stat_offsets_loaded,
1129 &osd->tx_size_big, &nsd->tx_size_big);
1130
1131 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1132 pf->stat_offsets_loaded,
1133 &osd->rx_undersize, &nsd->rx_undersize);
1134 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1135 pf->stat_offsets_loaded,
1136 &osd->rx_fragments, &nsd->rx_fragments);
1137 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1138 pf->stat_offsets_loaded,
1139 &osd->rx_oversize, &nsd->rx_oversize);
1140 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1141 pf->stat_offsets_loaded,
1142 &osd->rx_jabber, &nsd->rx_jabber);
1143
433c47de 1144 /* FDIR stats */
0bf4b1b0
ASJ		 1145 i40e_stat_update32(hw,
1146 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1147 pf->stat_offsets_loaded,
1148 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1149 i40e_stat_update32(hw,
1150 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1151 pf->stat_offsets_loaded,
1152 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1153 i40e_stat_update32(hw,
1154 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1155 pf->stat_offsets_loaded,
1156 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1157
7812fddc
SN		 1158 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1159 nsd->tx_lpi_status =
1160 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1161 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1162 nsd->rx_lpi_status =
1163 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1164 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1165 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1166 pf->stat_offsets_loaded,
1167 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1168 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1169 pf->stat_offsets_loaded,
1170 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1171
d0389e51
ASJ		 1172 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1173 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1174 nsd->fd_sb_status = true;
1175 else
1176 nsd->fd_sb_status = false;
1177
1178 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1179 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1180 nsd->fd_atr_status = true;
1181 else
1182 nsd->fd_atr_status = false;
1183
41c445ff
JB		 1184 pf->stat_offsets_loaded = true;
1185}
1186
7812fddc
SN		 1187/**
1188 * i40e_update_stats - Update the various statistics counters.
1189 * @vsi: the VSI to be updated
1190 *
1191 * Update the various stats for this VSI and its related entities.
1192 **/
1193void i40e_update_stats(struct i40e_vsi *vsi)
1194{
1195 struct i40e_pf *pf = vsi->back;
1196
1197 if (vsi == pf->vsi[pf->lan_vsi])
1198 i40e_update_pf_stats(pf);
1199
1200 i40e_update_vsi_stats(vsi);
38e00438
VD		 1201#ifdef I40E_FCOE
1202 i40e_update_fcoe_stats(vsi);
1203#endif
7812fddc
SN		 1204}
1205
41c445ff
JB		 1206/**
1207 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1208 * @vsi: the VSI to be searched
1209 * @macaddr: the MAC address
1210 * @vlan: the vlan
b40c82e6 1211 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1212 * @is_netdev: make sure its a netdev filter, else doesn't matter
1213 *
1214 * Returns ptr to the filter object or NULL
1215 **/
1216static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1217 u8 *macaddr, s16 vlan,
1218 bool is_vf, bool is_netdev)
1219{
1220 struct i40e_mac_filter *f;
1221
1222 if (!vsi || !macaddr)
1223 return NULL;
1224
1225 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1226 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1227 (vlan == f->vlan) &&
1228 (!is_vf || f->is_vf) &&
1229 (!is_netdev || f->is_netdev))
1230 return f;
1231 }
1232 return NULL;
1233}
1234
1235/**
1236 * i40e_find_mac - Find a mac addr in the macvlan filters list
1237 * @vsi: the VSI to be searched
1238 * @macaddr: the MAC address we are searching for
b40c82e6 1239 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1240 * @is_netdev: make sure its a netdev filter, else doesn't matter
1241 *
1242 * Returns the first filter with the provided MAC address or NULL if
1243 * MAC address was not found
1244 **/
1245struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1246 bool is_vf, bool is_netdev)
1247{
1248 struct i40e_mac_filter *f;
1249
1250 if (!vsi || !macaddr)
1251 return NULL;
1252
1253 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1254 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1255 (!is_vf || f->is_vf) &&
1256 (!is_netdev || f->is_netdev))
1257 return f;
1258 }
1259 return NULL;
1260}
1261
1262/**
1263 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1264 * @vsi: the VSI to be searched
1265 *
1266 * Returns true if VSI is in vlan mode or false otherwise
1267 **/
1268bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1269{
1270 struct i40e_mac_filter *f;
1271
1272 /* Only -1 for all the filters denotes not in vlan mode
1273 * so we have to go through all the list in order to make sure
1274 */
1275 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1276 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1277 return true;
1278 }
1279
1280 return false;
1281}
1282
1283/**
1284 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1285 * @vsi: the VSI to be searched
1286 * @macaddr: the mac address to be filtered
b40c82e6 1287 * @is_vf: true if it is a VF
41c445ff
JB		 1288 * @is_netdev: true if it is a netdev
1289 *
1290 * Goes through all the macvlan filters and adds a
1291 * macvlan filter for each unique vlan that already exists
1292 *
1293 * Returns first filter found on success, else NULL
1294 **/
1295struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1296 bool is_vf, bool is_netdev)
1297{
1298 struct i40e_mac_filter *f;
1299
1300 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1301 if (vsi->info.pvid)
1302 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1303 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1304 is_vf, is_netdev)) {
1305 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1306 is_vf, is_netdev))
41c445ff
JB		 1307 return NULL;
1308 }
1309 }
1310
1311 return list_first_entry_or_null(&vsi->mac_filter_list,
1312 struct i40e_mac_filter, list);
1313}
1314
8c27d42e
GR		 1315/**
1316 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1317 * @vsi: the PF Main VSI - inappropriate for any other VSI
1318 * @macaddr: the MAC address
30650cc5
SN		 1319 *
1320 * Some older firmware configurations set up a default promiscuous VLAN
1321 * filter that needs to be removed.
8c27d42e 1322 **/
30650cc5 1323static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1324{
1325 struct i40e_aqc_remove_macvlan_element_data element;
1326 struct i40e_pf *pf = vsi->back;
f1c7e72e 1327 i40e_status ret;
8c27d42e
GR		 1328
1329 /* Only appropriate for the PF main VSI */
1330 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1331 return -EINVAL;
8c27d42e 1332
30650cc5 1333 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1334 ether_addr_copy(element.mac_addr, macaddr);
1335 element.vlan_tag = 0;
1336 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1337 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1338 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1339 if (ret)
30650cc5
SN		 1340 return -ENOENT;
1341
1342 return 0;
8c27d42e
GR		 1343}
1344
41c445ff
JB		 1345/**
1346 * i40e_add_filter - Add a mac/vlan filter to the VSI
1347 * @vsi: the VSI to be searched
1348 * @macaddr: the MAC address
1349 * @vlan: the vlan
b40c82e6 1350 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1351 * @is_netdev: make sure its a netdev filter, else doesn't matter
1352 *
1353 * Returns ptr to the filter object or NULL when no memory available.
1354 **/
1355struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1356 u8 *macaddr, s16 vlan,
1357 bool is_vf, bool is_netdev)
1358{
1359 struct i40e_mac_filter *f;
1360
1361 if (!vsi || !macaddr)
1362 return NULL;
1363
1364 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1365 if (!f) {
1366 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1367 if (!f)
1368 goto add_filter_out;
1369
9a173901 1370 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1371 f->vlan = vlan;
1372 f->changed = true;
1373
1374 INIT_LIST_HEAD(&f->list);
1375 list_add(&f->list, &vsi->mac_filter_list);
1376 }
1377
1378 /* increment counter and add a new flag if needed */
1379 if (is_vf) {
1380 if (!f->is_vf) {
1381 f->is_vf = true;
1382 f->counter++;
1383 }
1384 } else if (is_netdev) {
1385 if (!f->is_netdev) {
1386 f->is_netdev = true;
1387 f->counter++;
1388 }
1389 } else {
1390 f->counter++;
1391 }
1392
1393 /* changed tells sync_filters_subtask to
1394 * push the filter down to the firmware
1395 */
1396 if (f->changed) {
1397 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1398 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1399 }
1400
1401add_filter_out:
1402 return f;
1403}
1404
1405/**
1406 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1407 * @vsi: the VSI to be searched
1408 * @macaddr: the MAC address
1409 * @vlan: the vlan
b40c82e6 1410 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff
JB		 1411 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1412 **/
1413void i40e_del_filter(struct i40e_vsi *vsi,
1414 u8 *macaddr, s16 vlan,
1415 bool is_vf, bool is_netdev)
1416{
1417 struct i40e_mac_filter *f;
1418
1419 if (!vsi || !macaddr)
1420 return;
1421
1422 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1423 if (!f || f->counter == 0)
1424 return;
1425
1426 if (is_vf) {
1427 if (f->is_vf) {
1428 f->is_vf = false;
1429 f->counter--;
1430 }
1431 } else if (is_netdev) {
1432 if (f->is_netdev) {
1433 f->is_netdev = false;
1434 f->counter--;
1435 }
1436 } else {
b40c82e6 1437 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff
JB		 1438 int min_f = 0;
1439 min_f += (f->is_vf ? 1 : 0);
1440 min_f += (f->is_netdev ? 1 : 0);
1441
1442 if (f->counter > min_f)
1443 f->counter--;
1444 }
1445
1446 /* counter == 0 tells sync_filters_subtask to
1447 * remove the filter from the firmware's list
1448 */
1449 if (f->counter == 0) {
1450 f->changed = true;
1451 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1452 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1453 }
1454}
1455
1456/**
1457 * i40e_set_mac - NDO callback to set mac address
1458 * @netdev: network interface device structure
1459 * @p: pointer to an address structure
1460 *
1461 * Returns 0 on success, negative on failure
1462 **/
38e00438
VD		 1463#ifdef I40E_FCOE
1464int i40e_set_mac(struct net_device *netdev, void *p)
1465#else
41c445ff 1466static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1467#endif
41c445ff
JB		 1468{
1469 struct i40e_netdev_priv *np = netdev_priv(netdev);
1470 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1471 struct i40e_pf *pf = vsi->back;
1472 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1473 struct sockaddr *addr = p;
1474 struct i40e_mac_filter *f;
1475
1476 if (!is_valid_ether_addr(addr->sa_data))
1477 return -EADDRNOTAVAIL;
1478
30650cc5
SN		 1479 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1480 netdev_info(netdev, "already using mac address %pM\n",
1481 addr->sa_data);
1482 return 0;
1483 }
41c445ff 1484
80f6428f
ASJ		 1485 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1486 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1487 return -EADDRNOTAVAIL;
1488
30650cc5
SN		 1489 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1490 netdev_info(netdev, "returning to hw mac address %pM\n",
1491 hw->mac.addr);
1492 else
1493 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1494
41c445ff
JB		 1495 if (vsi->type == I40E_VSI_MAIN) {
1496 i40e_status ret;
1497 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1498 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1499 addr->sa_data, NULL);
1500 if (ret) {
1501 netdev_info(netdev,
1502 "Addr change for Main VSI failed: %d\n",
1503 ret);
1504 return -EADDRNOTAVAIL;
1505 }
41c445ff
JB		 1506 }
1507
30650cc5
SN		 1508 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1509 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1510
30650cc5
SN		 1511 memset(&element, 0, sizeof(element));
1512 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1513 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1514 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1515 } else {
6c8ad1ba
SN		 1516 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1517 false, false);
6c8ad1ba 1518 }
41c445ff 1519
30650cc5
SN		 1520 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1521 struct i40e_aqc_add_macvlan_element_data element;
1522
1523 memset(&element, 0, sizeof(element));
1524 ether_addr_copy(element.mac_addr, hw->mac.addr);
1525 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1526 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1527 } else {
1528 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1529 false, false);
1530 if (f)
1531 f->is_laa = true;
1532 }
1533
30e2561b 1534 i40e_sync_vsi_filters(vsi, false);
30650cc5 1535 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1536
1537 return 0;
1538}
1539
1540/**
1541 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1542 * @vsi: the VSI being setup
1543 * @ctxt: VSI context structure
1544 * @enabled_tc: Enabled TCs bitmap
1545 * @is_add: True if called before Add VSI
1546 *
1547 * Setup VSI queue mapping for enabled traffic classes.
1548 **/
38e00438
VD		 1549#ifdef I40E_FCOE
1550void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1551 struct i40e_vsi_context *ctxt,
1552 u8 enabled_tc,
1553 bool is_add)
1554#else
41c445ff
JB		 1555static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1556 struct i40e_vsi_context *ctxt,
1557 u8 enabled_tc,
1558 bool is_add)
38e00438 1559#endif
41c445ff
JB		 1560{
1561 struct i40e_pf *pf = vsi->back;
1562 u16 sections = 0;
1563 u8 netdev_tc = 0;
1564 u16 numtc = 0;
1565 u16 qcount;
1566 u8 offset;
1567 u16 qmap;
1568 int i;
4e3b35b0 1569 u16 num_tc_qps = 0;
41c445ff
JB		 1570
1571 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1572 offset = 0;
1573
1574 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1575 /* Find numtc from enabled TC bitmap */
1576 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1577 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1578 numtc++;
1579 }
1580 if (!numtc) {
1581 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1582 numtc = 1;
1583 }
1584 } else {
1585 /* At least TC0 is enabled in case of non-DCB case */
1586 numtc = 1;
1587 }
1588
1589 vsi->tc_config.numtc = numtc;
1590 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1591 /* Number of queues per enabled TC */
7f9ff476
AS		 1592 /* In MFP case we can have a much lower count of MSIx
1593 * vectors available and so we need to lower the used
1594 * q count.
1595 */
26cdc443
ASJ		 1596 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1597 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1598 else
1599 qcount = vsi->alloc_queue_pairs;
7f9ff476 1600 num_tc_qps = qcount / numtc;
e25d00b8 1601 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1602
1603 /* Setup queue offset/count for all TCs for given VSI */
1604 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1605 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1606 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1607 /* TC is enabled */
41c445ff
JB		 1608 int pow, num_qps;
1609
41c445ff
JB		 1610 switch (vsi->type) {
1611 case I40E_VSI_MAIN:
4e3b35b0 1612 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1613 break;
38e00438
VD		 1614#ifdef I40E_FCOE
1615 case I40E_VSI_FCOE:
1616 qcount = num_tc_qps;
1617 break;
1618#endif
41c445ff
JB		 1619 case I40E_VSI_FDIR:
1620 case I40E_VSI_SRIOV:
1621 case I40E_VSI_VMDQ2:
1622 default:
4e3b35b0 1623 qcount = num_tc_qps;
41c445ff
JB		 1624 WARN_ON(i != 0);
1625 break;
1626 }
4e3b35b0
NP		 1627 vsi->tc_config.tc_info[i].qoffset = offset;
1628 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1629
1e200e4a 1630 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1631 num_qps = qcount;
41c445ff 1632 pow = 0;
41a1d04b 1633 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1634 pow++;
1635 num_qps >>= 1;
1636 }
1637
1638 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1639 qmap =
1640 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1641 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1642
4e3b35b0 1643 offset += qcount;
41c445ff
JB		 1644 } else {
1645 /* TC is not enabled so set the offset to
1646 * default queue and allocate one queue
1647 * for the given TC.
1648 */
1649 vsi->tc_config.tc_info[i].qoffset = 0;
1650 vsi->tc_config.tc_info[i].qcount = 1;
1651 vsi->tc_config.tc_info[i].netdev_tc = 0;
1652
1653 qmap = 0;
1654 }
1655 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1656 }
1657
1658 /* Set actual Tx/Rx queue pairs */
1659 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1660 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1661 if (vsi->req_queue_pairs > 0)
1662 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1663 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1664 vsi->num_queue_pairs = pf->num_lan_msix;
1665 }
41c445ff
JB		 1666
1667 /* Scheduler section valid can only be set for ADD VSI */
1668 if (is_add) {
1669 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1670
1671 ctxt->info.up_enable_bits = enabled_tc;
1672 }
1673 if (vsi->type == I40E_VSI_SRIOV) {
1674 ctxt->info.mapping_flags |=
1675 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1676 for (i = 0; i < vsi->num_queue_pairs; i++)
1677 ctxt->info.queue_mapping[i] =
1678 cpu_to_le16(vsi->base_queue + i);
1679 } else {
1680 ctxt->info.mapping_flags |=
1681 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1682 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1683 }
1684 ctxt->info.valid_sections |= cpu_to_le16(sections);
1685}
1686
1687/**
1688 * i40e_set_rx_mode - NDO callback to set the netdev filters
1689 * @netdev: network interface device structure
1690 **/
38e00438
VD		 1691#ifdef I40E_FCOE
1692void i40e_set_rx_mode(struct net_device *netdev)
1693#else
41c445ff 1694static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1695#endif
41c445ff
JB		 1696{
1697 struct i40e_netdev_priv *np = netdev_priv(netdev);
1698 struct i40e_mac_filter *f, *ftmp;
1699 struct i40e_vsi *vsi = np->vsi;
1700 struct netdev_hw_addr *uca;
1701 struct netdev_hw_addr *mca;
1702 struct netdev_hw_addr *ha;
1703
1704 /* add addr if not already in the filter list */
1705 netdev_for_each_uc_addr(uca, netdev) {
1706 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1707 if (i40e_is_vsi_in_vlan(vsi))
1708 i40e_put_mac_in_vlan(vsi, uca->addr,
1709 false, true);
1710 else
1711 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1712 false, true);
1713 }
1714 }
1715
1716 netdev_for_each_mc_addr(mca, netdev) {
1717 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1718 if (i40e_is_vsi_in_vlan(vsi))
1719 i40e_put_mac_in_vlan(vsi, mca->addr,
1720 false, true);
1721 else
1722 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1723 false, true);
1724 }
1725 }
1726
1727 /* remove filter if not in netdev list */
1728 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1729 bool found = false;
1730
1731 if (!f->is_netdev)
1732 continue;
1733
1734 if (is_multicast_ether_addr(f->macaddr)) {
1735 netdev_for_each_mc_addr(mca, netdev) {
1736 if (ether_addr_equal(mca->addr, f->macaddr)) {
1737 found = true;
1738 break;
1739 }
1740 }
1741 } else {
1742 netdev_for_each_uc_addr(uca, netdev) {
1743 if (ether_addr_equal(uca->addr, f->macaddr)) {
1744 found = true;
1745 break;
1746 }
1747 }
1748
1749 for_each_dev_addr(netdev, ha) {
1750 if (ether_addr_equal(ha->addr, f->macaddr)) {
1751 found = true;
1752 break;
1753 }
1754 }
1755 }
1756 if (!found)
1757 i40e_del_filter(
1758 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1759 }
1760
1761 /* check for other flag changes */
1762 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1763 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1764 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1765 }
1766}
1767
1768/**
1769 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1770 * @vsi: ptr to the VSI
30e2561b 1771 * @grab_rtnl: whether RTNL needs to be grabbed
41c445ff
JB		 1772 *
1773 * Push any outstanding VSI filter changes through the AdminQ.
1774 *
1775 * Returns 0 or error value
1776 **/
30e2561b 1777int i40e_sync_vsi_filters(struct i40e_vsi *vsi, bool grab_rtnl)
41c445ff
JB		 1778{
1779 struct i40e_mac_filter *f, *ftmp;
1780 bool promisc_forced_on = false;
1781 bool add_happened = false;
1782 int filter_list_len = 0;
1783 u32 changed_flags = 0;
f1c7e72e 1784 i40e_status ret = 0;
41c445ff
JB		 1785 struct i40e_pf *pf;
1786 int num_add = 0;
1787 int num_del = 0;
f1c7e72e 1788 int aq_err = 0;
41c445ff
JB		 1789 u16 cmd_flags;
1790
1791 /* empty array typed pointers, kcalloc later */
1792 struct i40e_aqc_add_macvlan_element_data *add_list;
1793 struct i40e_aqc_remove_macvlan_element_data *del_list;
1794
1795 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1796 usleep_range(1000, 2000);
1797 pf = vsi->back;
1798
1799 if (vsi->netdev) {
1800 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1801 vsi->current_netdev_flags = vsi->netdev->flags;
1802 }
1803
1804 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1805 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1806
1807 filter_list_len = pf->hw.aq.asq_buf_size /
1808 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1809 del_list = kcalloc(filter_list_len,
1810 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1811 GFP_KERNEL);
1812 if (!del_list)
1813 return -ENOMEM;
1814
1815 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1816 if (!f->changed)
1817 continue;
1818
1819 if (f->counter != 0)
1820 continue;
1821 f->changed = false;
1822 cmd_flags = 0;
1823
1824 /* add to delete list */
9a173901 1825 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1826 del_list[num_del].vlan_tag =
1827 cpu_to_le16((u16)(f->vlan ==
1828 I40E_VLAN_ANY ? 0 : f->vlan));
1829
41c445ff
JB		 1830 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1831 del_list[num_del].flags = cmd_flags;
1832 num_del++;
1833
1834 /* unlink from filter list */
1835 list_del(&f->list);
1836 kfree(f);
1837
1838 /* flush a full buffer */
1839 if (num_del == filter_list_len) {
f1c7e72e
SN		 1840 ret = i40e_aq_remove_macvlan(&pf->hw,
1841 vsi->seid, del_list, num_del,
1842 NULL);
1843 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1844 num_del = 0;
1845 memset(del_list, 0, sizeof(*del_list));
1846
f1c7e72e 1847 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1848 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1849 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1850 i40e_stat_str(&pf->hw, ret),
1851 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1852 }
1853 }
1854 if (num_del) {
f1c7e72e 1855 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1856 del_list, num_del, NULL);
f1c7e72e 1857 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1858 num_del = 0;
1859
f1c7e72e 1860 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1861 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1862 "ignoring delete macvlan error, err %s aq_err %s\n",
1863 i40e_stat_str(&pf->hw, ret),
1864 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1865 }
1866
1867 kfree(del_list);
1868 del_list = NULL;
1869
1870 /* do all the adds now */
1871 filter_list_len = pf->hw.aq.asq_buf_size /
1872 sizeof(struct i40e_aqc_add_macvlan_element_data),
1873 add_list = kcalloc(filter_list_len,
1874 sizeof(struct i40e_aqc_add_macvlan_element_data),
1875 GFP_KERNEL);
1876 if (!add_list)
1877 return -ENOMEM;
1878
1879 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1880 if (!f->changed)
1881 continue;
1882
1883 if (f->counter == 0)
1884 continue;
1885 f->changed = false;
1886 add_happened = true;
1887 cmd_flags = 0;
1888
1889 /* add to add array */
9a173901 1890 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1891 add_list[num_add].vlan_tag =
1892 cpu_to_le16(
1893 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1894 add_list[num_add].queue_number = 0;
1895
1896 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1897 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1898 num_add++;
1899
1900 /* flush a full buffer */
1901 if (num_add == filter_list_len) {
f1c7e72e
SN		 1902 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1903 add_list, num_add,
1904 NULL);
1905 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1906 num_add = 0;
1907
f1c7e72e 1908 if (ret)
41c445ff
JB		 1909 break;
1910 memset(add_list, 0, sizeof(*add_list));
1911 }
1912 }
1913 if (num_add) {
f1c7e72e
SN		 1914 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1915 add_list, num_add, NULL);
1916 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1917 num_add = 0;
1918 }
1919 kfree(add_list);
1920 add_list = NULL;
1921
f1c7e72e 1922 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 1923 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1924 "add filter failed, err %s aq_err %s\n",
1925 i40e_stat_str(&pf->hw, ret),
1926 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1927 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1928 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1929 &vsi->state)) {
1930 promisc_forced_on = true;
1931 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1932 &vsi->state);
1933 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1934 }
1935 }
1936 }
1937
1938 /* check for changes in promiscuous modes */
1939 if (changed_flags & IFF_ALLMULTI) {
1940 bool cur_multipromisc;
1941 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 1942 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1943 vsi->seid,
1944 cur_multipromisc,
1945 NULL);
1946 if (ret)
41c445ff 1947 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1948 "set multi promisc failed, err %s aq_err %s\n",
1949 i40e_stat_str(&pf->hw, ret),
1950 i40e_aq_str(&pf->hw,
1951 pf->hw.aq.asq_last_status));
41c445ff
JB		 1952 }
1953 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1954 bool cur_promisc;
1955 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1956 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1957 &vsi->state));
92faef85
ASJ		 1958 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
1959 /* set defport ON for Main VSI instead of true promisc
1960 * this way we will get all unicast/multicast and VLAN
1961 * promisc behavior but will not get VF or VMDq traffic
1962 * replicated on the Main VSI.
1963 */
1964 if (pf->cur_promisc != cur_promisc) {
1965 pf->cur_promisc = cur_promisc;
30e2561b
AS		 1966 if (grab_rtnl)
1967 i40e_do_reset_safe(pf,
1968 BIT(__I40E_PF_RESET_REQUESTED));
1969 else
1970 i40e_do_reset(pf,
92faef85
ASJ		 1971 BIT(__I40E_PF_RESET_REQUESTED));
1972 }
1973 } else {
1974 ret = i40e_aq_set_vsi_unicast_promiscuous(
1975 &vsi->back->hw,
f1c7e72e
SN		 1976 vsi->seid,
1977 cur_promisc, NULL);
92faef85
ASJ		 1978 if (ret)
1979 dev_info(&pf->pdev->dev,
1980 "set unicast promisc failed, err %d, aq_err %d\n",
1981 ret, pf->hw.aq.asq_last_status);
1982 ret = i40e_aq_set_vsi_multicast_promiscuous(
1983 &vsi->back->hw,
1984 vsi->seid,
1985 cur_promisc, NULL);
1986 if (ret)
1987 dev_info(&pf->pdev->dev,
1988 "set multicast promisc failed, err %d, aq_err %d\n",
1989 ret, pf->hw.aq.asq_last_status);
1990 }
f1c7e72e
SN		 1991 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1992 vsi->seid,
1993 cur_promisc, NULL);
1994 if (ret)
1a10370a 1995 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1996 "set brdcast promisc failed, err %s, aq_err %s\n",
1997 i40e_stat_str(&pf->hw, ret),
1998 i40e_aq_str(&pf->hw,
1999 pf->hw.aq.asq_last_status));
41c445ff
JB		 2000 }
2001
2002 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
2003 return 0;
2004}
2005
2006/**
2007 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2008 * @pf: board private structure
2009 **/
2010static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2011{
2012 int v;
2013
2014 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2015 return;
2016 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2017
505682cd 2018 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 2019 if (pf->vsi[v] &&
2020 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
30e2561b 2021 i40e_sync_vsi_filters(pf->vsi[v], true);
41c445ff
JB		 2022 }
2023}
2024
2025/**
2026 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2027 * @netdev: network interface device structure
2028 * @new_mtu: new value for maximum frame size
2029 *
2030 * Returns 0 on success, negative on failure
2031 **/
2032static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2033{
2034 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2035 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2036 struct i40e_vsi *vsi = np->vsi;
2037
2038 /* MTU < 68 is an error and causes problems on some kernels */
2039 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2040 return -EINVAL;
2041
2042 netdev_info(netdev, "changing MTU from %d to %d\n",
2043 netdev->mtu, new_mtu);
2044 netdev->mtu = new_mtu;
2045 if (netif_running(netdev))
2046 i40e_vsi_reinit_locked(vsi);
2047
2048 return 0;
2049}
2050
beb0dff1
JK		 2051/**
2052 * i40e_ioctl - Access the hwtstamp interface
2053 * @netdev: network interface device structure
2054 * @ifr: interface request data
2055 * @cmd: ioctl command
2056 **/
2057int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2058{
2059 struct i40e_netdev_priv *np = netdev_priv(netdev);
2060 struct i40e_pf *pf = np->vsi->back;
2061
2062 switch (cmd) {
2063 case SIOCGHWTSTAMP:
2064 return i40e_ptp_get_ts_config(pf, ifr);
2065 case SIOCSHWTSTAMP:
2066 return i40e_ptp_set_ts_config(pf, ifr);
2067 default:
2068 return -EOPNOTSUPP;
2069 }
2070}
2071
41c445ff
JB		 2072/**
2073 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2074 * @vsi: the vsi being adjusted
2075 **/
2076void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2077{
2078 struct i40e_vsi_context ctxt;
2079 i40e_status ret;
2080
2081 if ((vsi->info.valid_sections &
2082 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2083 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2084 return; /* already enabled */
2085
2086 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2087 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2088 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2089
2090 ctxt.seid = vsi->seid;
1a2f6248 2091 ctxt.info = vsi->info;
41c445ff
JB		 2092 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2093 if (ret) {
2094 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2095 "update vlan stripping failed, err %s aq_err %s\n",
2096 i40e_stat_str(&vsi->back->hw, ret),
2097 i40e_aq_str(&vsi->back->hw,
2098 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2099 }
2100}
2101
2102/**
2103 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2104 * @vsi: the vsi being adjusted
2105 **/
2106void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2107{
2108 struct i40e_vsi_context ctxt;
2109 i40e_status ret;
2110
2111 if ((vsi->info.valid_sections &
2112 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2113 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2114 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2115 return; /* already disabled */
2116
2117 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2118 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2119 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2120
2121 ctxt.seid = vsi->seid;
1a2f6248 2122 ctxt.info = vsi->info;
41c445ff
JB		 2123 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2124 if (ret) {
2125 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2126 "update vlan stripping failed, err %s aq_err %s\n",
2127 i40e_stat_str(&vsi->back->hw, ret),
2128 i40e_aq_str(&vsi->back->hw,
2129 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2130 }
2131}
2132
2133/**
2134 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2135 * @netdev: network interface to be adjusted
2136 * @features: netdev features to test if VLAN offload is enabled or not
2137 **/
2138static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2139{
2140 struct i40e_netdev_priv *np = netdev_priv(netdev);
2141 struct i40e_vsi *vsi = np->vsi;
2142
2143 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2144 i40e_vlan_stripping_enable(vsi);
2145 else
2146 i40e_vlan_stripping_disable(vsi);
2147}
2148
2149/**
2150 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2151 * @vsi: the vsi being configured
2152 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2153 **/
2154int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2155{
2156 struct i40e_mac_filter *f, *add_f;
2157 bool is_netdev, is_vf;
41c445ff
JB		 2158
2159 is_vf = (vsi->type == I40E_VSI_SRIOV);
2160 is_netdev = !!(vsi->netdev);
2161
2162 if (is_netdev) {
2163 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2164 is_vf, is_netdev);
2165 if (!add_f) {
2166 dev_info(&vsi->back->pdev->dev,
2167 "Could not add vlan filter %d for %pM\n",
2168 vid, vsi->netdev->dev_addr);
2169 return -ENOMEM;
2170 }
2171 }
2172
2173 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2174 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2175 if (!add_f) {
2176 dev_info(&vsi->back->pdev->dev,
2177 "Could not add vlan filter %d for %pM\n",
2178 vid, f->macaddr);
2179 return -ENOMEM;
2180 }
2181 }
2182
41c445ff
JB		 2183 /* Now if we add a vlan tag, make sure to check if it is the first
2184 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2185 * with 0, so we now accept untagged and specified tagged traffic
2186 * (and not any taged and untagged)
2187 */
2188 if (vid > 0) {
2189 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2190 I40E_VLAN_ANY,
2191 is_vf, is_netdev)) {
2192 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2193 I40E_VLAN_ANY, is_vf, is_netdev);
2194 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2195 is_vf, is_netdev);
2196 if (!add_f) {
2197 dev_info(&vsi->back->pdev->dev,
2198 "Could not add filter 0 for %pM\n",
2199 vsi->netdev->dev_addr);
2200 return -ENOMEM;
2201 }
2202 }
8d82a7c5 2203 }
41c445ff 2204
8d82a7c5
GR		 2205 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2206 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2207 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2208 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2209 is_vf, is_netdev)) {
2210 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2211 is_vf, is_netdev);
2212 add_f = i40e_add_filter(vsi, f->macaddr,
2213 0, is_vf, is_netdev);
2214 if (!add_f) {
2215 dev_info(&vsi->back->pdev->dev,
2216 "Could not add filter 0 for %pM\n",
2217 f->macaddr);
2218 return -ENOMEM;
2219 }
2220 }
2221 }
41c445ff
JB		 2222 }
2223
80f6428f
ASJ		 2224 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2225 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2226 return 0;
2227
30e2561b 2228 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2229}
2230
2231/**
2232 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2233 * @vsi: the vsi being configured
2234 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2235 *
2236 * Return: 0 on success or negative otherwise
41c445ff
JB		 2237 **/
2238int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2239{
2240 struct net_device *netdev = vsi->netdev;
2241 struct i40e_mac_filter *f, *add_f;
2242 bool is_vf, is_netdev;
2243 int filter_count = 0;
41c445ff
JB		 2244
2245 is_vf = (vsi->type == I40E_VSI_SRIOV);
2246 is_netdev = !!(netdev);
2247
2248 if (is_netdev)
2249 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2250
2251 list_for_each_entry(f, &vsi->mac_filter_list, list)
2252 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2253
41c445ff
JB		 2254 /* go through all the filters for this VSI and if there is only
2255 * vid == 0 it means there are no other filters, so vid 0 must
2256 * be replaced with -1. This signifies that we should from now
2257 * on accept any traffic (with any tag present, or untagged)
2258 */
2259 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2260 if (is_netdev) {
2261 if (f->vlan &&
2262 ether_addr_equal(netdev->dev_addr, f->macaddr))
2263 filter_count++;
2264 }
2265
2266 if (f->vlan)
2267 filter_count++;
2268 }
2269
2270 if (!filter_count && is_netdev) {
2271 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2272 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2273 is_vf, is_netdev);
2274 if (!f) {
2275 dev_info(&vsi->back->pdev->dev,
2276 "Could not add filter %d for %pM\n",
2277 I40E_VLAN_ANY, netdev->dev_addr);
2278 return -ENOMEM;
2279 }
2280 }
2281
2282 if (!filter_count) {
2283 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2284 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2285 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2286 is_vf, is_netdev);
2287 if (!add_f) {
2288 dev_info(&vsi->back->pdev->dev,
2289 "Could not add filter %d for %pM\n",
2290 I40E_VLAN_ANY, f->macaddr);
2291 return -ENOMEM;
2292 }
2293 }
2294 }
2295
80f6428f
ASJ		 2296 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2297 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2298 return 0;
2299
30e2561b 2300 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2301}
2302
2303/**
2304 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2305 * @netdev: network interface to be adjusted
2306 * @vid: vlan id to be added
078b5876
JB		 2307 *
2308 * net_device_ops implementation for adding vlan ids
41c445ff 2309 **/
38e00438
VD		 2310#ifdef I40E_FCOE
2311int i40e_vlan_rx_add_vid(struct net_device *netdev,
2312 __always_unused __be16 proto, u16 vid)
2313#else
41c445ff
JB		 2314static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2315 __always_unused __be16 proto, u16 vid)
38e00438 2316#endif
41c445ff
JB		 2317{
2318 struct i40e_netdev_priv *np = netdev_priv(netdev);
2319 struct i40e_vsi *vsi = np->vsi;
078b5876 2320 int ret = 0;
41c445ff
JB		 2321
2322 if (vid > 4095)
078b5876
JB		 2323 return -EINVAL;
2324
2325 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2326
6982d429
ASJ		 2327 /* If the network stack called us with vid = 0 then
2328 * it is asking to receive priority tagged packets with
2329 * vlan id 0. Our HW receives them by default when configured
2330 * to receive untagged packets so there is no need to add an
2331 * extra filter for vlan 0 tagged packets.
41c445ff 2332 */
6982d429
ASJ		 2333 if (vid)
2334 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2335
078b5876
JB		 2336 if (!ret && (vid < VLAN_N_VID))
2337 set_bit(vid, vsi->active_vlans);
41c445ff 2338
078b5876 2339 return ret;
41c445ff
JB		 2340}
2341
2342/**
2343 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2344 * @netdev: network interface to be adjusted
2345 * @vid: vlan id to be removed
078b5876 2346 *
fdfd943e 2347 * net_device_ops implementation for removing vlan ids
41c445ff 2348 **/
38e00438
VD		 2349#ifdef I40E_FCOE
2350int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2351 __always_unused __be16 proto, u16 vid)
2352#else
41c445ff
JB		 2353static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2354 __always_unused __be16 proto, u16 vid)
38e00438 2355#endif
41c445ff
JB		 2356{
2357 struct i40e_netdev_priv *np = netdev_priv(netdev);
2358 struct i40e_vsi *vsi = np->vsi;
2359
078b5876
JB		 2360 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2361
41c445ff
JB		 2362 /* return code is ignored as there is nothing a user
2363 * can do about failure to remove and a log message was
078b5876 2364 * already printed from the other function
41c445ff
JB		 2365 */
2366 i40e_vsi_kill_vlan(vsi, vid);
2367
2368 clear_bit(vid, vsi->active_vlans);
078b5876 2369
41c445ff
JB		 2370 return 0;
2371}
2372
2373/**
2374 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2375 * @vsi: the vsi being brought back up
2376 **/
2377static void i40e_restore_vlan(struct i40e_vsi *vsi)
2378{
2379 u16 vid;
2380
2381 if (!vsi->netdev)
2382 return;
2383
2384 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2385
2386 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2387 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2388 vid);
2389}
2390
2391/**
2392 * i40e_vsi_add_pvid - Add pvid for the VSI
2393 * @vsi: the vsi being adjusted
2394 * @vid: the vlan id to set as a PVID
2395 **/
dcae29be 2396int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2397{
2398 struct i40e_vsi_context ctxt;
f1c7e72e 2399 i40e_status ret;
41c445ff
JB		 2400
2401 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2402 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2403 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2404 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2405 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2406
2407 ctxt.seid = vsi->seid;
1a2f6248 2408 ctxt.info = vsi->info;
f1c7e72e
SN		 2409 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2410 if (ret) {
41c445ff 2411 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2412 "add pvid failed, err %s aq_err %s\n",
2413 i40e_stat_str(&vsi->back->hw, ret),
2414 i40e_aq_str(&vsi->back->hw,
2415 vsi->back->hw.aq.asq_last_status));
dcae29be 2416 return -ENOENT;
41c445ff
JB		 2417 }
2418
dcae29be 2419 return 0;
41c445ff
JB		 2420}
2421
2422/**
2423 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2424 * @vsi: the vsi being adjusted
2425 *
2426 * Just use the vlan_rx_register() service to put it back to normal
2427 **/
2428void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2429{
6c12fcbf
GR		 2430 i40e_vlan_stripping_disable(vsi);
2431
41c445ff 2432 vsi->info.pvid = 0;
41c445ff
JB		 2433}
2434
2435/**
2436 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2437 * @vsi: ptr to the VSI
2438 *
2439 * If this function returns with an error, then it's possible one or
2440 * more of the rings is populated (while the rest are not). It is the
2441 * callers duty to clean those orphaned rings.
2442 *
2443 * Return 0 on success, negative on failure
2444 **/
2445static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2446{
2447 int i, err = 0;
2448
2449 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2450 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2451
2452 return err;
2453}
2454
2455/**
2456 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2457 * @vsi: ptr to the VSI
2458 *
2459 * Free VSI's transmit software resources
2460 **/
2461static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2462{
2463 int i;
2464
8e9dca53
GR		 2465 if (!vsi->tx_rings)
2466 return;
2467
41c445ff 2468 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2469 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2470 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2471}
2472
2473/**
2474 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2475 * @vsi: ptr to the VSI
2476 *
2477 * If this function returns with an error, then it's possible one or
2478 * more of the rings is populated (while the rest are not). It is the
2479 * callers duty to clean those orphaned rings.
2480 *
2481 * Return 0 on success, negative on failure
2482 **/
2483static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2484{
2485 int i, err = 0;
2486
2487 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2488 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2489#ifdef I40E_FCOE
2490 i40e_fcoe_setup_ddp_resources(vsi);
2491#endif
41c445ff
JB		 2492 return err;
2493}
2494
2495/**
2496 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2497 * @vsi: ptr to the VSI
2498 *
2499 * Free all receive software resources
2500 **/
2501static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2502{
2503 int i;
2504
8e9dca53
GR		 2505 if (!vsi->rx_rings)
2506 return;
2507
41c445ff 2508 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2509 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2510 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2511#ifdef I40E_FCOE
2512 i40e_fcoe_free_ddp_resources(vsi);
2513#endif
41c445ff
JB		 2514}
2515
3ffa037d
NP		 2516/**
2517 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2518 * @ring: The Tx ring to configure
2519 *
2520 * This enables/disables XPS for a given Tx descriptor ring
2521 * based on the TCs enabled for the VSI that ring belongs to.
2522 **/
2523static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2524{
2525 struct i40e_vsi *vsi = ring->vsi;
2526 cpumask_var_t mask;
2527
9a660eea
JB		 2528 if (!ring->q_vector || !ring->netdev)
2529 return;
2530
2531 /* Single TC mode enable XPS */
2532 if (vsi->tc_config.numtc <= 1) {
2533 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2534 netif_set_xps_queue(ring->netdev,
2535 &ring->q_vector->affinity_mask,
2536 ring->queue_index);
9a660eea
JB		 2537 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2538 /* Disable XPS to allow selection based on TC */
2539 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2540 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2541 free_cpumask_var(mask);
3ffa037d
NP		 2542 }
2543}
2544
41c445ff
JB		 2545/**
2546 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2547 * @ring: The Tx ring to configure
2548 *
2549 * Configure the Tx descriptor ring in the HMC context.
2550 **/
2551static int i40e_configure_tx_ring(struct i40e_ring *ring)
2552{
2553 struct i40e_vsi *vsi = ring->vsi;
2554 u16 pf_q = vsi->base_queue + ring->queue_index;
2555 struct i40e_hw *hw = &vsi->back->hw;
2556 struct i40e_hmc_obj_txq tx_ctx;
2557 i40e_status err = 0;
2558 u32 qtx_ctl = 0;
2559
2560 /* some ATR related tx ring init */
60ea5f83 2561 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2562 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2563 ring->atr_count = 0;
2564 } else {
2565 ring->atr_sample_rate = 0;
2566 }
2567
3ffa037d
NP		 2568 /* configure XPS */
2569 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2570
2571 /* clear the context structure first */
2572 memset(&tx_ctx, 0, sizeof(tx_ctx));
2573
2574 tx_ctx.new_context = 1;
2575 tx_ctx.base = (ring->dma / 128);
2576 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2577 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2578 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2579#ifdef I40E_FCOE
2580 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2581#endif
beb0dff1 2582 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2583 /* FDIR VSI tx ring can still use RS bit and writebacks */
2584 if (vsi->type != I40E_VSI_FDIR)
2585 tx_ctx.head_wb_ena = 1;
2586 tx_ctx.head_wb_addr = ring->dma +
2587 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2588
2589 /* As part of VSI creation/update, FW allocates certain
2590 * Tx arbitration queue sets for each TC enabled for
2591 * the VSI. The FW returns the handles to these queue
2592 * sets as part of the response buffer to Add VSI,
2593 * Update VSI, etc. AQ commands. It is expected that
2594 * these queue set handles be associated with the Tx
2595 * queues by the driver as part of the TX queue context
2596 * initialization. This has to be done regardless of
2597 * DCB as by default everything is mapped to TC0.
2598 */
2599 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2600 tx_ctx.rdylist_act = 0;
2601
2602 /* clear the context in the HMC */
2603 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2604 if (err) {
2605 dev_info(&vsi->back->pdev->dev,
2606 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2607 ring->queue_index, pf_q, err);
2608 return -ENOMEM;
2609 }
2610
2611 /* set the context in the HMC */
2612 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2613 if (err) {
2614 dev_info(&vsi->back->pdev->dev,
2615 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2616 ring->queue_index, pf_q, err);
2617 return -ENOMEM;
2618 }
2619
2620 /* Now associate this queue with this PCI function */
7a28d885 2621 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2622 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2623 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2624 I40E_QTX_CTL_VFVM_INDX_MASK;
2625 } else {
9d8bf547 2626 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2627 }
2628
13fd9774
SN		 2629 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2630 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2631 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2632 i40e_flush(hw);
2633
41c445ff
JB		 2634 /* cache tail off for easier writes later */
2635 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2636
2637 return 0;
2638}
2639
2640/**
2641 * i40e_configure_rx_ring - Configure a receive ring context
2642 * @ring: The Rx ring to configure
2643 *
2644 * Configure the Rx descriptor ring in the HMC context.
2645 **/
2646static int i40e_configure_rx_ring(struct i40e_ring *ring)
2647{
2648 struct i40e_vsi *vsi = ring->vsi;
2649 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2650 u16 pf_q = vsi->base_queue + ring->queue_index;
2651 struct i40e_hw *hw = &vsi->back->hw;
2652 struct i40e_hmc_obj_rxq rx_ctx;
2653 i40e_status err = 0;
2654
2655 ring->state = 0;
2656
2657 /* clear the context structure first */
2658 memset(&rx_ctx, 0, sizeof(rx_ctx));
2659
2660 ring->rx_buf_len = vsi->rx_buf_len;
2661 ring->rx_hdr_len = vsi->rx_hdr_len;
2662
2663 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2664 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2665
2666 rx_ctx.base = (ring->dma / 128);
2667 rx_ctx.qlen = ring->count;
2668
2669 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2670 set_ring_16byte_desc_enabled(ring);
2671 rx_ctx.dsize = 0;
2672 } else {
2673 rx_ctx.dsize = 1;
2674 }
2675
2676 rx_ctx.dtype = vsi->dtype;
2677 if (vsi->dtype) {
2678 set_ring_ps_enabled(ring);
2679 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2680 I40E_RX_SPLIT_IP |
2681 I40E_RX_SPLIT_TCP_UDP |
2682 I40E_RX_SPLIT_SCTP;
2683 } else {
2684 rx_ctx.hsplit_0 = 0;
2685 }
2686
2687 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2688 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2689 if (hw->revision_id == 0)
2690 rx_ctx.lrxqthresh = 0;
2691 else
2692 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2693 rx_ctx.crcstrip = 1;
2694 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2695 /* this controls whether VLAN is stripped from inner headers */
2696 rx_ctx.showiv = 0;
38e00438
VD		 2697#ifdef I40E_FCOE
2698 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2699#endif
acb3676b
CS		 2700 /* set the prefena field to 1 because the manual says to */
2701 rx_ctx.prefena = 1;
41c445ff
JB		 2702
2703 /* clear the context in the HMC */
2704 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2705 if (err) {
2706 dev_info(&vsi->back->pdev->dev,
2707 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2708 ring->queue_index, pf_q, err);
2709 return -ENOMEM;
2710 }
2711
2712 /* set the context in the HMC */
2713 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2714 if (err) {
2715 dev_info(&vsi->back->pdev->dev,
2716 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2717 ring->queue_index, pf_q, err);
2718 return -ENOMEM;
2719 }
2720
2721 /* cache tail for quicker writes, and clear the reg before use */
2722 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2723 writel(0, ring->tail);
2724
a132af24
MW		 2725 if (ring_is_ps_enabled(ring)) {
2726 i40e_alloc_rx_headers(ring);
2727 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2728 } else {
2729 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2730 }
41c445ff
JB		 2731
2732 return 0;
2733}
2734
2735/**
2736 * i40e_vsi_configure_tx - Configure the VSI for Tx
2737 * @vsi: VSI structure describing this set of rings and resources
2738 *
2739 * Configure the Tx VSI for operation.
2740 **/
2741static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2742{
2743 int err = 0;
2744 u16 i;
2745
9f65e15b
AD		 2746 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2747 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2748
2749 return err;
2750}
2751
2752/**
2753 * i40e_vsi_configure_rx - Configure the VSI for Rx
2754 * @vsi: the VSI being configured
2755 *
2756 * Configure the Rx VSI for operation.
2757 **/
2758static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2759{
2760 int err = 0;
2761 u16 i;
2762
2763 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2764 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2765 + ETH_FCS_LEN + VLAN_HLEN;
2766 else
2767 vsi->max_frame = I40E_RXBUFFER_2048;
2768
2769 /* figure out correct receive buffer length */
2770 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2771 I40E_FLAG_RX_PS_ENABLED)) {
2772 case I40E_FLAG_RX_1BUF_ENABLED:
2773 vsi->rx_hdr_len = 0;
2774 vsi->rx_buf_len = vsi->max_frame;
2775 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2776 break;
2777 case I40E_FLAG_RX_PS_ENABLED:
2778 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2779 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2780 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2781 break;
2782 default:
2783 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2784 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2785 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2786 break;
2787 }
2788
38e00438
VD		 2789#ifdef I40E_FCOE
2790 /* setup rx buffer for FCoE */
2791 if ((vsi->type == I40E_VSI_FCOE) &&
2792 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2793 vsi->rx_hdr_len = 0;
2794 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2795 vsi->max_frame = I40E_RXBUFFER_3072;
2796 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2797 }
2798
2799#endif /* I40E_FCOE */
41c445ff
JB		 2800 /* round up for the chip's needs */
2801 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2802 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2803 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2804 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2805
2806 /* set up individual rings */
2807 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2808 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2809
2810 return err;
2811}
2812
2813/**
2814 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2815 * @vsi: ptr to the VSI
2816 **/
2817static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2818{
e7046ee1 2819 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2820 u16 qoffset, qcount;
2821 int i, n;
2822
cd238a3e
PN		 2823 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2824 /* Reset the TC information */
2825 for (i = 0; i < vsi->num_queue_pairs; i++) {
2826 rx_ring = vsi->rx_rings[i];
2827 tx_ring = vsi->tx_rings[i];
2828 rx_ring->dcb_tc = 0;
2829 tx_ring->dcb_tc = 0;
2830 }
2831 }
41c445ff
JB		 2832
2833 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2834 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2835 continue;
2836
2837 qoffset = vsi->tc_config.tc_info[n].qoffset;
2838 qcount = vsi->tc_config.tc_info[n].qcount;
2839 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2840 rx_ring = vsi->rx_rings[i];
2841 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2842 rx_ring->dcb_tc = n;
2843 tx_ring->dcb_tc = n;
2844 }
2845 }
2846}
2847
2848/**
2849 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2850 * @vsi: ptr to the VSI
2851 **/
2852static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2853{
2854 if (vsi->netdev)
2855 i40e_set_rx_mode(vsi->netdev);
2856}
2857
17a73f6b
JG		 2858/**
2859 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2860 * @vsi: Pointer to the targeted VSI
2861 *
2862 * This function replays the hlist on the hw where all the SB Flow Director
2863 * filters were saved.
2864 **/
2865static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2866{
2867 struct i40e_fdir_filter *filter;
2868 struct i40e_pf *pf = vsi->back;
2869 struct hlist_node *node;
2870
55a5e60b
ASJ		 2871 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2872 return;
2873
17a73f6b
JG		 2874 hlist_for_each_entry_safe(filter, node,
2875 &pf->fdir_filter_list, fdir_node) {
2876 i40e_add_del_fdir(vsi, filter, true);
2877 }
2878}
2879
41c445ff
JB		 2880/**
2881 * i40e_vsi_configure - Set up the VSI for action
2882 * @vsi: the VSI being configured
2883 **/
2884static int i40e_vsi_configure(struct i40e_vsi *vsi)
2885{
2886 int err;
2887
2888 i40e_set_vsi_rx_mode(vsi);
2889 i40e_restore_vlan(vsi);
2890 i40e_vsi_config_dcb_rings(vsi);
2891 err = i40e_vsi_configure_tx(vsi);
2892 if (!err)
2893 err = i40e_vsi_configure_rx(vsi);
2894
2895 return err;
2896}
2897
2898/**
2899 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2900 * @vsi: the VSI being configured
2901 **/
2902static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2903{
2904 struct i40e_pf *pf = vsi->back;
2905 struct i40e_q_vector *q_vector;
2906 struct i40e_hw *hw = &pf->hw;
2907 u16 vector;
2908 int i, q;
2909 u32 val;
2910 u32 qp;
2911
2912 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2913 * and PFINT_LNKLSTn registers, e.g.:
2914 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2915 */
2916 qp = vsi->base_queue;
2917 vector = vsi->base_vector;
493fb300
AD		 2918 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2919 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2920 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2921 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2922 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2923 q_vector->rx.itr);
2924 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2925 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2926 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2927 q_vector->tx.itr);
2928
2929 /* Linked list for the queuepairs assigned to this vector */
2930 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2931 for (q = 0; q < q_vector->num_ringpairs; q++) {
2932 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2933 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2934 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2935 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2936 (I40E_QUEUE_TYPE_TX
2937 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2938
2939 wr32(hw, I40E_QINT_RQCTL(qp), val);
2940
2941 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2942 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2943 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2944 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2945 (I40E_QUEUE_TYPE_RX
2946 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2947
2948 /* Terminate the linked list */
2949 if (q == (q_vector->num_ringpairs - 1))
2950 val |= (I40E_QUEUE_END_OF_LIST
2951 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2952
2953 wr32(hw, I40E_QINT_TQCTL(qp), val);
2954 qp++;
2955 }
2956 }
2957
2958 i40e_flush(hw);
2959}
2960
2961/**
2962 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2963 * @hw: ptr to the hardware info
2964 **/
ab437b5a 2965static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2966{
ab437b5a 2967 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2968 u32 val;
2969
2970 /* clear things first */
2971 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2972 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2973
2974 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2975 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2976 I40E_PFINT_ICR0_ENA_GRST_MASK |
2977 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2978 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2979 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2980 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2981 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2982
0d8e1439
ASJ		 2983 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
2984 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
2985
ab437b5a
JK		 2986 if (pf->flags & I40E_FLAG_PTP)
2987 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2988
41c445ff
JB		 2989 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2990
2991 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2992 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2993 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2994
2995 /* OTHER_ITR_IDX = 0 */
2996 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2997}
2998
2999/**
3000 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3001 * @vsi: the VSI being configured
3002 **/
3003static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3004{
493fb300 3005 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3006 struct i40e_pf *pf = vsi->back;
3007 struct i40e_hw *hw = &pf->hw;
3008 u32 val;
3009
3010 /* set the ITR configuration */
3011 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3012 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3013 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3014 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3015 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3016 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3017
ab437b5a 3018 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3019
3020 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3021 wr32(hw, I40E_PFINT_LNKLST0, 0);
3022
f29eaa3d 3023 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3024 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3025 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3026 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3027
3028 wr32(hw, I40E_QINT_RQCTL(0), val);
3029
3030 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3031 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3032 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3033
3034 wr32(hw, I40E_QINT_TQCTL(0), val);
3035 i40e_flush(hw);
3036}
3037
2ef28cfb
MW		 3038/**
3039 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3040 * @pf: board private structure
3041 **/
3042void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3043{
3044 struct i40e_hw *hw = &pf->hw;
3045
3046 wr32(hw, I40E_PFINT_DYN_CTL0,
3047 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3048 i40e_flush(hw);
3049}
3050
41c445ff
JB		 3051/**
3052 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3053 * @pf: board private structure
3054 **/
116a57d4 3055void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3056{
3057 struct i40e_hw *hw = &pf->hw;
3058 u32 val;
3059
3060 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3061 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3062 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3063
3064 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3065 i40e_flush(hw);
3066}
3067
3068/**
3069 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
3070 * @vsi: pointer to a vsi
7845548d 3071 * @vector: enable a particular Hw Interrupt vector, without base_vector
41c445ff
JB		 3072 **/
3073void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
3074{
3075 struct i40e_pf *pf = vsi->back;
3076 struct i40e_hw *hw = &pf->hw;
3077 u32 val;
3078
3079 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
3080 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
3081 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
7845548d 3082 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1022cb6c 3083 /* skip the flush */
41c445ff
JB		 3084}
3085
5c2cebda
CW		 3086/**
3087 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3088 * @vsi: pointer to a vsi
03147773 3089 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3090 **/
3091void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3092{
3093 struct i40e_pf *pf = vsi->back;
3094 struct i40e_hw *hw = &pf->hw;
3095 u32 val;
3096
3097 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3098 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3099 i40e_flush(hw);
3100}
3101
41c445ff
JB		 3102/**
3103 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3104 * @irq: interrupt number
3105 * @data: pointer to a q_vector
3106 **/
3107static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3108{
3109 struct i40e_q_vector *q_vector = data;
3110
cd0b6fa6 3111 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3112 return IRQ_HANDLED;
3113
3114 napi_schedule(&q_vector->napi);
3115
3116 return IRQ_HANDLED;
3117}
3118
41c445ff
JB		 3119/**
3120 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3121 * @vsi: the VSI being configured
3122 * @basename: name for the vector
3123 *
3124 * Allocates MSI-X vectors and requests interrupts from the kernel.
3125 **/
3126static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3127{
3128 int q_vectors = vsi->num_q_vectors;
3129 struct i40e_pf *pf = vsi->back;
3130 int base = vsi->base_vector;
3131 int rx_int_idx = 0;
3132 int tx_int_idx = 0;
3133 int vector, err;
3134
3135 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3136 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3137
cd0b6fa6 3138 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3139 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3140 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3141 tx_int_idx++;
cd0b6fa6 3142 } else if (q_vector->rx.ring) {
41c445ff
JB		 3143 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3144 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3145 } else if (q_vector->tx.ring) {
41c445ff
JB		 3146 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3147 "%s-%s-%d", basename, "tx", tx_int_idx++);
3148 } else {
3149 /* skip this unused q_vector */
3150 continue;
3151 }
3152 err = request_irq(pf->msix_entries[base + vector].vector,
3153 vsi->irq_handler,
3154 0,
3155 q_vector->name,
3156 q_vector);
3157 if (err) {
3158 dev_info(&pf->pdev->dev,
3159 "%s: request_irq failed, error: %d\n",
3160 __func__, err);
3161 goto free_queue_irqs;
3162 }
3163 /* assign the mask for this irq */
3164 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3165 &q_vector->affinity_mask);
3166 }
3167
63741846 3168 vsi->irqs_ready = true;
41c445ff
JB		 3169 return 0;
3170
3171free_queue_irqs:
3172 while (vector) {
3173 vector--;
3174 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3175 NULL);
3176 free_irq(pf->msix_entries[base + vector].vector,
3177 &(vsi->q_vectors[vector]));
3178 }
3179 return err;
3180}
3181
3182/**
3183 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3184 * @vsi: the VSI being un-configured
3185 **/
3186static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3187{
3188 struct i40e_pf *pf = vsi->back;
3189 struct i40e_hw *hw = &pf->hw;
3190 int base = vsi->base_vector;
3191 int i;
3192
3193 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3194 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3195 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3196 }
3197
3198 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3199 for (i = vsi->base_vector;
3200 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3201 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3202
3203 i40e_flush(hw);
3204 for (i = 0; i < vsi->num_q_vectors; i++)
3205 synchronize_irq(pf->msix_entries[i + base].vector);
3206 } else {
3207 /* Legacy and MSI mode - this stops all interrupt handling */
3208 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3209 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3210 i40e_flush(hw);
3211 synchronize_irq(pf->pdev->irq);
3212 }
3213}
3214
3215/**
3216 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3217 * @vsi: the VSI being configured
3218 **/
3219static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3220{
3221 struct i40e_pf *pf = vsi->back;
3222 int i;
3223
3224 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3225 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3226 i40e_irq_dynamic_enable(vsi, i);
3227 } else {
3228 i40e_irq_dynamic_enable_icr0(pf);
3229 }
3230
1022cb6c 3231 i40e_flush(&pf->hw);
41c445ff
JB		 3232 return 0;
3233}
3234
3235/**
3236 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3237 * @pf: board private structure
3238 **/
3239static void i40e_stop_misc_vector(struct i40e_pf *pf)
3240{
3241 /* Disable ICR 0 */
3242 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3243 i40e_flush(&pf->hw);
3244}
3245
3246/**
3247 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3248 * @irq: interrupt number
3249 * @data: pointer to a q_vector
3250 *
3251 * This is the handler used for all MSI/Legacy interrupts, and deals
3252 * with both queue and non-queue interrupts. This is also used in
3253 * MSIX mode to handle the non-queue interrupts.
3254 **/
3255static irqreturn_t i40e_intr(int irq, void *data)
3256{
3257 struct i40e_pf *pf = (struct i40e_pf *)data;
3258 struct i40e_hw *hw = &pf->hw;
5e823066 3259 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3260 u32 icr0, icr0_remaining;
3261 u32 val, ena_mask;
3262
3263 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3264 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3265
116a57d4
SN		 3266 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3267 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3268 goto enable_intr;
41c445ff 3269
cd92e72f
SN		 3270 /* if interrupt but no bits showing, must be SWINT */
3271 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3272 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3273 pf->sw_int_count++;
3274
0d8e1439
ASJ		 3275 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3276 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3277 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3278 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3279 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3280 }
3281
41c445ff
JB		 3282 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3283 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3284
3285 /* temporarily disable queue cause for NAPI processing */
3286 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3287 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3288 wr32(hw, I40E_QINT_RQCTL(0), qval);
3289
3290 qval = rd32(hw, I40E_QINT_TQCTL(0));
3291 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3292 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3293
3294 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3295 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3296 }
3297
3298 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3299 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3300 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3301 }
3302
3303 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3304 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3305 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3306 }
3307
3308 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3309 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3310 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3311 }
3312
3313 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3314 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3315 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3316 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3317 val = rd32(hw, I40E_GLGEN_RSTAT);
3318 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3319 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3320 if (val == I40E_RESET_CORER) {
41c445ff 3321 pf->corer_count++;
4eb3f768 3322 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3323 pf->globr_count++;
4eb3f768 3324 } else if (val == I40E_RESET_EMPR) {
41c445ff 3325 pf->empr_count++;
9df42d1a 3326 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3327 }
41c445ff
JB		 3328 }
3329
9c010ee0
ASJ		 3330 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3331 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3332 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3333 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3334 rd32(hw, I40E_PFHMC_ERRORINFO),
3335 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3336 }
3337
beb0dff1
JK		 3338 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3339 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3340
3341 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3342 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3343 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3344 }
beb0dff1
JK		 3345 }
3346
41c445ff
JB		 3347 /* If a critical error is pending we have no choice but to reset the
3348 * device.
3349 * Report and mask out any remaining unexpected interrupts.
3350 */
3351 icr0_remaining = icr0 & ena_mask;
3352 if (icr0_remaining) {
3353 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3354 icr0_remaining);
9c010ee0 3355 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3356 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3357 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3358 dev_info(&pf->pdev->dev, "device will be reset\n");
3359 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3360 i40e_service_event_schedule(pf);
41c445ff
JB		 3361 }
3362 ena_mask &= ~icr0_remaining;
3363 }
5e823066 3364 ret = IRQ_HANDLED;
41c445ff 3365
5e823066 3366enable_intr:
41c445ff
JB		 3367 /* re-enable interrupt causes */
3368 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3369 if (!test_bit(__I40E_DOWN, &pf->state)) {
3370 i40e_service_event_schedule(pf);
3371 i40e_irq_dynamic_enable_icr0(pf);
3372 }
3373
5e823066 3374 return ret;
41c445ff
JB		 3375}
3376
cbf61325
ASJ		 3377/**
3378 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3379 * @tx_ring: tx ring to clean
3380 * @budget: how many cleans we're allowed
3381 *
3382 * Returns true if there's any budget left (e.g. the clean is finished)
3383 **/
3384static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3385{
3386 struct i40e_vsi *vsi = tx_ring->vsi;
3387 u16 i = tx_ring->next_to_clean;
3388 struct i40e_tx_buffer *tx_buf;
3389 struct i40e_tx_desc *tx_desc;
3390
3391 tx_buf = &tx_ring->tx_bi[i];
3392 tx_desc = I40E_TX_DESC(tx_ring, i);
3393 i -= tx_ring->count;
3394
3395 do {
3396 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3397
3398 /* if next_to_watch is not set then there is no work pending */
3399 if (!eop_desc)
3400 break;
3401
3402 /* prevent any other reads prior to eop_desc */
3403 read_barrier_depends();
3404
3405 /* if the descriptor isn't done, no work yet to do */
3406 if (!(eop_desc->cmd_type_offset_bsz &
3407 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3408 break;
3409
3410 /* clear next_to_watch to prevent false hangs */
3411 tx_buf->next_to_watch = NULL;
3412
49d7d933
ASJ		 3413 tx_desc->buffer_addr = 0;
3414 tx_desc->cmd_type_offset_bsz = 0;
3415 /* move past filter desc */
3416 tx_buf++;
3417 tx_desc++;
3418 i++;
3419 if (unlikely(!i)) {
3420 i -= tx_ring->count;
3421 tx_buf = tx_ring->tx_bi;
3422 tx_desc = I40E_TX_DESC(tx_ring, 0);
3423 }
cbf61325
ASJ		 3424 /* unmap skb header data */
3425 dma_unmap_single(tx_ring->dev,
3426 dma_unmap_addr(tx_buf, dma),
3427 dma_unmap_len(tx_buf, len),
3428 DMA_TO_DEVICE);
49d7d933
ASJ		 3429 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3430 kfree(tx_buf->raw_buf);
cbf61325 3431
49d7d933
ASJ		 3432 tx_buf->raw_buf = NULL;
3433 tx_buf->tx_flags = 0;
3434 tx_buf->next_to_watch = NULL;
cbf61325 3435 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3436 tx_desc->buffer_addr = 0;
3437 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3438
49d7d933 3439 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3440 tx_buf++;
3441 tx_desc++;
3442 i++;
3443 if (unlikely(!i)) {
3444 i -= tx_ring->count;
3445 tx_buf = tx_ring->tx_bi;
3446 tx_desc = I40E_TX_DESC(tx_ring, 0);
3447 }
3448
3449 /* update budget accounting */
3450 budget--;
3451 } while (likely(budget));
3452
3453 i += tx_ring->count;
3454 tx_ring->next_to_clean = i;
3455
3456 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3457 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
cbf61325
ASJ		 3458 }
3459 return budget > 0;
3460}
3461
3462/**
3463 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3464 * @irq: interrupt number
3465 * @data: pointer to a q_vector
3466 **/
3467static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3468{
3469 struct i40e_q_vector *q_vector = data;
3470 struct i40e_vsi *vsi;
3471
3472 if (!q_vector->tx.ring)
3473 return IRQ_HANDLED;
3474
3475 vsi = q_vector->tx.ring->vsi;
3476 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3477
3478 return IRQ_HANDLED;
3479}
3480
41c445ff 3481/**
cd0b6fa6 3482 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3483 * @vsi: the VSI being configured
3484 * @v_idx: vector index
cd0b6fa6 3485 * @qp_idx: queue pair index
41c445ff 3486 **/
26cdc443 3487static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3488{
493fb300 3489 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3490 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3491 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3492
3493 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3494 tx_ring->next = q_vector->tx.ring;
3495 q_vector->tx.ring = tx_ring;
41c445ff 3496 q_vector->tx.count++;
cd0b6fa6
AD		 3497
3498 rx_ring->q_vector = q_vector;
3499 rx_ring->next = q_vector->rx.ring;
3500 q_vector->rx.ring = rx_ring;
3501 q_vector->rx.count++;
41c445ff
JB		 3502}
3503
3504/**
3505 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3506 * @vsi: the VSI being configured
3507 *
3508 * This function maps descriptor rings to the queue-specific vectors
3509 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3510 * one vector per queue pair, but on a constrained vector budget, we
3511 * group the queue pairs as "efficiently" as possible.
3512 **/
3513static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3514{
3515 int qp_remaining = vsi->num_queue_pairs;
3516 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3517 int num_ringpairs;
41c445ff
JB		 3518 int v_start = 0;
3519 int qp_idx = 0;
3520
3521 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3522 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3523 * It is also important to go through all the vectors available to be
3524 * sure that if we don't use all the vectors, that the remaining vectors
3525 * are cleared. This is especially important when decreasing the
3526 * number of queues in use.
41c445ff 3527 */
70114ec4 3528 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3529 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3530
3531 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3532
3533 q_vector->num_ringpairs = num_ringpairs;
3534
3535 q_vector->rx.count = 0;
3536 q_vector->tx.count = 0;
3537 q_vector->rx.ring = NULL;
3538 q_vector->tx.ring = NULL;
3539
3540 while (num_ringpairs--) {
26cdc443 3541 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3542 qp_idx++;
3543 qp_remaining--;
41c445ff
JB		 3544 }
3545 }
3546}
3547
3548/**
3549 * i40e_vsi_request_irq - Request IRQ from the OS
3550 * @vsi: the VSI being configured
3551 * @basename: name for the vector
3552 **/
3553static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3554{
3555 struct i40e_pf *pf = vsi->back;
3556 int err;
3557
3558 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3559 err = i40e_vsi_request_irq_msix(vsi, basename);
3560 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3561 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3562 pf->int_name, pf);
41c445ff
JB		 3563 else
3564 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3565 pf->int_name, pf);
41c445ff
JB		 3566
3567 if (err)
3568 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3569
3570 return err;
3571}
3572
3573#ifdef CONFIG_NET_POLL_CONTROLLER
3574/**
3575 * i40e_netpoll - A Polling 'interrupt'handler
3576 * @netdev: network interface device structure
3577 *
3578 * This is used by netconsole to send skbs without having to re-enable
3579 * interrupts. It's not called while the normal interrupt routine is executing.
3580 **/
38e00438
VD		 3581#ifdef I40E_FCOE
3582void i40e_netpoll(struct net_device *netdev)
3583#else
41c445ff 3584static void i40e_netpoll(struct net_device *netdev)
38e00438 3585#endif
41c445ff
JB		 3586{
3587 struct i40e_netdev_priv *np = netdev_priv(netdev);
3588 struct i40e_vsi *vsi = np->vsi;
3589 struct i40e_pf *pf = vsi->back;
3590 int i;
3591
3592 /* if interface is down do nothing */
3593 if (test_bit(__I40E_DOWN, &vsi->state))
3594 return;
3595
3596 pf->flags |= I40E_FLAG_IN_NETPOLL;
3597 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3598 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3599 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3600 } else {
3601 i40e_intr(pf->pdev->irq, netdev);
3602 }
3603 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3604}
3605#endif
3606
23527308
NP		 3607/**
3608 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3609 * @pf: the PF being configured
3610 * @pf_q: the PF queue
3611 * @enable: enable or disable state of the queue
3612 *
3613 * This routine will wait for the given Tx queue of the PF to reach the
3614 * enabled or disabled state.
3615 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3616 * multiple retries; else will return 0 in case of success.
3617 **/
3618static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3619{
3620 int i;
3621 u32 tx_reg;
3622
3623 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3624 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3625 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3626 break;
3627
f98a2006 3628 usleep_range(10, 20);
23527308
NP		 3629 }
3630 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3631 return -ETIMEDOUT;
3632
3633 return 0;
3634}
3635
41c445ff
JB		 3636/**
3637 * i40e_vsi_control_tx - Start or stop a VSI's rings
3638 * @vsi: the VSI being configured
3639 * @enable: start or stop the rings
3640 **/
3641static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3642{
3643 struct i40e_pf *pf = vsi->back;
3644 struct i40e_hw *hw = &pf->hw;
23527308 3645 int i, j, pf_q, ret = 0;
41c445ff
JB		 3646 u32 tx_reg;
3647
3648 pf_q = vsi->base_queue;
3649 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3650
3651 /* warn the TX unit of coming changes */
3652 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3653 if (!enable)
f98a2006 3654 usleep_range(10, 20);
351499ab 3655
6c5ef620 3656 for (j = 0; j < 50; j++) {
41c445ff 3657 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3658 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3659 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3660 break;
3661 usleep_range(1000, 2000);
3662 }
fda972f6 3663 /* Skip if the queue is already in the requested state */
7c122007 3664 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3665 continue;
41c445ff
JB		 3666
3667 /* turn on/off the queue */
c5c9eb9e
SN		 3668 if (enable) {
3669 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3670 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3671 } else {
41c445ff 3672 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3673 }
41c445ff
JB		 3674
3675 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3676 /* No waiting for the Tx queue to disable */
3677 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3678 continue;
41c445ff
JB		 3679
3680 /* wait for the change to finish */
23527308
NP		 3681 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3682 if (ret) {
3683 dev_info(&pf->pdev->dev,
3684 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3685 __func__, vsi->seid, pf_q,
3686 (enable ? "en" : "dis"));
3687 break;
41c445ff
JB		 3688 }
3689 }
3690
7134f9ce
JB		 3691 if (hw->revision_id == 0)
3692 mdelay(50);
23527308
NP		 3693 return ret;
3694}
3695
3696/**
3697 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3698 * @pf: the PF being configured
3699 * @pf_q: the PF queue
3700 * @enable: enable or disable state of the queue
3701 *
3702 * This routine will wait for the given Rx queue of the PF to reach the
3703 * enabled or disabled state.
3704 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3705 * multiple retries; else will return 0 in case of success.
3706 **/
3707static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3708{
3709 int i;
3710 u32 rx_reg;
3711
3712 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3713 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3714 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3715 break;
3716
f98a2006 3717 usleep_range(10, 20);
23527308
NP		 3718 }
3719 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3720 return -ETIMEDOUT;
7134f9ce 3721
41c445ff
JB		 3722 return 0;
3723}
3724
3725/**
3726 * i40e_vsi_control_rx - Start or stop a VSI's rings
3727 * @vsi: the VSI being configured
3728 * @enable: start or stop the rings
3729 **/
3730static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3731{
3732 struct i40e_pf *pf = vsi->back;
3733 struct i40e_hw *hw = &pf->hw;
23527308 3734 int i, j, pf_q, ret = 0;
41c445ff
JB		 3735 u32 rx_reg;
3736
3737 pf_q = vsi->base_queue;
3738 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3739 for (j = 0; j < 50; j++) {
41c445ff 3740 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3741 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3742 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3743 break;
3744 usleep_range(1000, 2000);
3745 }
41c445ff 3746
7c122007
CS		 3747 /* Skip if the queue is already in the requested state */
3748 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3749 continue;
41c445ff
JB		 3750
3751 /* turn on/off the queue */
3752 if (enable)
6c5ef620 3753 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3754 else
6c5ef620 3755 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3756 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3757
3758 /* wait for the change to finish */
23527308
NP		 3759 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3760 if (ret) {
3761 dev_info(&pf->pdev->dev,
3762 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3763 __func__, vsi->seid, pf_q,
3764 (enable ? "en" : "dis"));
3765 break;
41c445ff
JB		 3766 }
3767 }
3768
23527308 3769 return ret;
41c445ff
JB		 3770}
3771
3772/**
3773 * i40e_vsi_control_rings - Start or stop a VSI's rings
3774 * @vsi: the VSI being configured
3775 * @enable: start or stop the rings
3776 **/
fc18eaa0 3777int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3778{
3b867b28 3779 int ret = 0;
41c445ff
JB		 3780
3781 /* do rx first for enable and last for disable */
3782 if (request) {
3783 ret = i40e_vsi_control_rx(vsi, request);
3784 if (ret)
3785 return ret;
3786 ret = i40e_vsi_control_tx(vsi, request);
3787 } else {
3b867b28
ASJ		 3788 /* Ignore return value, we need to shutdown whatever we can */
3789 i40e_vsi_control_tx(vsi, request);
3790 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3791 }
3792
3793 return ret;
3794}
3795
3796/**
3797 * i40e_vsi_free_irq - Free the irq association with the OS
3798 * @vsi: the VSI being configured
3799 **/
3800static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3801{
3802 struct i40e_pf *pf = vsi->back;
3803 struct i40e_hw *hw = &pf->hw;
3804 int base = vsi->base_vector;
3805 u32 val, qp;
3806 int i;
3807
3808 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3809 if (!vsi->q_vectors)
3810 return;
3811
63741846
SN		 3812 if (!vsi->irqs_ready)
3813 return;
3814
3815 vsi->irqs_ready = false;
41c445ff
JB		 3816 for (i = 0; i < vsi->num_q_vectors; i++) {
3817 u16 vector = i + base;
3818
3819 /* free only the irqs that were actually requested */
78681b1f
SN		 3820 if (!vsi->q_vectors[i] ||
3821 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3822 continue;
3823
3824 /* clear the affinity_mask in the IRQ descriptor */
3825 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3826 NULL);
3827 free_irq(pf->msix_entries[vector].vector,
493fb300 3828 vsi->q_vectors[i]);
41c445ff
JB		 3829
3830 /* Tear down the interrupt queue link list
3831 *
3832 * We know that they come in pairs and always
3833 * the Rx first, then the Tx. To clear the
3834 * link list, stick the EOL value into the
3835 * next_q field of the registers.
3836 */
3837 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3838 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3839 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3840 val |= I40E_QUEUE_END_OF_LIST
3841 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3842 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3843
3844 while (qp != I40E_QUEUE_END_OF_LIST) {
3845 u32 next;
3846
3847 val = rd32(hw, I40E_QINT_RQCTL(qp));
3848
3849 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3850 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3851 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3852 I40E_QINT_RQCTL_INTEVENT_MASK);
3853
3854 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3855 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3856
3857 wr32(hw, I40E_QINT_RQCTL(qp), val);
3858
3859 val = rd32(hw, I40E_QINT_TQCTL(qp));
3860
3861 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3862 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3863
3864 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3865 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3866 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3867 I40E_QINT_TQCTL_INTEVENT_MASK);
3868
3869 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3870 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3871
3872 wr32(hw, I40E_QINT_TQCTL(qp), val);
3873 qp = next;
3874 }
3875 }
3876 } else {
3877 free_irq(pf->pdev->irq, pf);
3878
3879 val = rd32(hw, I40E_PFINT_LNKLST0);
3880 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3881 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3882 val |= I40E_QUEUE_END_OF_LIST
3883 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3884 wr32(hw, I40E_PFINT_LNKLST0, val);
3885
3886 val = rd32(hw, I40E_QINT_RQCTL(qp));
3887 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3888 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3889 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3890 I40E_QINT_RQCTL_INTEVENT_MASK);
3891
3892 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3893 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3894
3895 wr32(hw, I40E_QINT_RQCTL(qp), val);
3896
3897 val = rd32(hw, I40E_QINT_TQCTL(qp));
3898
3899 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3900 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3901 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3902 I40E_QINT_TQCTL_INTEVENT_MASK);
3903
3904 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3905 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3906
3907 wr32(hw, I40E_QINT_TQCTL(qp), val);
3908 }
3909}
3910
493fb300
AD		 3911/**
3912 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3913 * @vsi: the VSI being configured
3914 * @v_idx: Index of vector to be freed
3915 *
3916 * This function frees the memory allocated to the q_vector. In addition if
3917 * NAPI is enabled it will delete any references to the NAPI struct prior
3918 * to freeing the q_vector.
3919 **/
3920static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3921{
3922 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3923 struct i40e_ring *ring;
493fb300
AD		 3924
3925 if (!q_vector)
3926 return;
3927
3928 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3929 i40e_for_each_ring(ring, q_vector->tx)
3930 ring->q_vector = NULL;
3931
3932 i40e_for_each_ring(ring, q_vector->rx)
3933 ring->q_vector = NULL;
493fb300
AD		 3934
3935 /* only VSI w/ an associated netdev is set up w/ NAPI */
3936 if (vsi->netdev)
3937 netif_napi_del(&q_vector->napi);
3938
3939 vsi->q_vectors[v_idx] = NULL;
3940
3941 kfree_rcu(q_vector, rcu);
3942}
3943
41c445ff
JB		 3944/**
3945 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3946 * @vsi: the VSI being un-configured
3947 *
3948 * This frees the memory allocated to the q_vectors and
3949 * deletes references to the NAPI struct.
3950 **/
3951static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3952{
3953 int v_idx;
3954
493fb300
AD		 3955 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3956 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3957}
3958
3959/**
3960 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3961 * @pf: board private structure
3962 **/
3963static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3964{
3965 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3966 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3967 pci_disable_msix(pf->pdev);
3968 kfree(pf->msix_entries);
3969 pf->msix_entries = NULL;
3b444399
SN		 3970 kfree(pf->irq_pile);
3971 pf->irq_pile = NULL;
41c445ff
JB		 3972 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3973 pci_disable_msi(pf->pdev);
3974 }
3975 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3976}
3977
3978/**
3979 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3980 * @pf: board private structure
3981 *
3982 * We go through and clear interrupt specific resources and reset the structure
3983 * to pre-load conditions
3984 **/
3985static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3986{
3987 int i;
3988
e147758d
SN		 3989 i40e_stop_misc_vector(pf);
3990 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3991 synchronize_irq(pf->msix_entries[0].vector);
3992 free_irq(pf->msix_entries[0].vector, pf);
3993 }
3994
41c445ff 3995 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3996 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3997 if (pf->vsi[i])
3998 i40e_vsi_free_q_vectors(pf->vsi[i]);
3999 i40e_reset_interrupt_capability(pf);
4000}
4001
4002/**
4003 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4004 * @vsi: the VSI being configured
4005 **/
4006static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4007{
4008 int q_idx;
4009
4010 if (!vsi->netdev)
4011 return;
4012
4013 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4014 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4015}
4016
4017/**
4018 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4019 * @vsi: the VSI being configured
4020 **/
4021static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4022{
4023 int q_idx;
4024
4025 if (!vsi->netdev)
4026 return;
4027
4028 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4029 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4030}
4031
90ef8d47
SN		 4032/**
4033 * i40e_vsi_close - Shut down a VSI
4034 * @vsi: the vsi to be quelled
4035 **/
4036static void i40e_vsi_close(struct i40e_vsi *vsi)
4037{
4038 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4039 i40e_down(vsi);
4040 i40e_vsi_free_irq(vsi);
4041 i40e_vsi_free_tx_resources(vsi);
4042 i40e_vsi_free_rx_resources(vsi);
92faef85 4043 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4044}
4045
41c445ff
JB		 4046/**
4047 * i40e_quiesce_vsi - Pause a given VSI
4048 * @vsi: the VSI being paused
4049 **/
4050static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4051{
4052 if (test_bit(__I40E_DOWN, &vsi->state))
4053 return;
4054
d341b7a5
NP		 4055 /* No need to disable FCoE VSI when Tx suspended */
4056 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4057 vsi->type == I40E_VSI_FCOE) {
4058 dev_dbg(&vsi->back->pdev->dev,
4059 "%s: VSI seid %d skipping FCoE VSI disable\n",
4060 __func__, vsi->seid);
4061 return;
4062 }
4063
41c445ff
JB		 4064 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
4065 if (vsi->netdev && netif_running(vsi->netdev)) {
4066 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
4067 } else {
90ef8d47 4068 i40e_vsi_close(vsi);
41c445ff
JB		 4069 }
4070}
4071
4072/**
4073 * i40e_unquiesce_vsi - Resume a given VSI
4074 * @vsi: the VSI being resumed
4075 **/
4076static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4077{
4078 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4079 return;
4080
4081 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4082 if (vsi->netdev && netif_running(vsi->netdev))
4083 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4084 else
8276f757 4085 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4086}
4087
4088/**
4089 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4090 * @pf: the PF
4091 **/
4092static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4093{
4094 int v;
4095
505682cd 4096 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4097 if (pf->vsi[v])
4098 i40e_quiesce_vsi(pf->vsi[v]);
4099 }
4100}
4101
4102/**
4103 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4104 * @pf: the PF
4105 **/
4106static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4107{
4108 int v;
4109
505682cd 4110 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4111 if (pf->vsi[v])
4112 i40e_unquiesce_vsi(pf->vsi[v]);
4113 }
4114}
4115
69129dc3
NP		 4116#ifdef CONFIG_I40E_DCB
4117/**
4118 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4119 * @vsi: the VSI being configured
4120 *
4121 * This function waits for the given VSI's Tx queues to be disabled.
4122 **/
4123static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4124{
4125 struct i40e_pf *pf = vsi->back;
4126 int i, pf_q, ret;
4127
4128 pf_q = vsi->base_queue;
4129 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4130 /* Check and wait for the disable status of the queue */
4131 ret = i40e_pf_txq_wait(pf, pf_q, false);
4132 if (ret) {
4133 dev_info(&pf->pdev->dev,
4134 "%s: VSI seid %d Tx ring %d disable timeout\n",
4135 __func__, vsi->seid, pf_q);
4136 return ret;
4137 }
4138 }
4139
4140 return 0;
4141}
4142
4143/**
4144 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4145 * @pf: the PF
4146 *
4147 * This function waits for the Tx queues to be in disabled state for all the
4148 * VSIs that are managed by this PF.
4149 **/
4150static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4151{
4152 int v, ret = 0;
4153
4154 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4155 /* No need to wait for FCoE VSI queues */
4156 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4157 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4158 if (ret)
4159 break;
4160 }
4161 }
4162
4163 return ret;
4164}
4165
4166#endif
b03a8c1f
KP		 4167
4168/**
4169 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4170 * @q_idx: TX queue number
4171 * @vsi: Pointer to VSI struct
4172 *
4173 * This function checks specified queue for given VSI. Detects hung condition.
4174 * Sets hung bit since it is two step process. Before next run of service task
4175 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4176 * hung condition remain unchanged and during subsequent run, this function
4177 * issues SW interrupt to recover from hung condition.
4178 **/
4179static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4180{
4181 struct i40e_ring *tx_ring = NULL;
4182 struct i40e_pf *pf;
4183 u32 head, val, tx_pending;
4184 int i;
4185
4186 pf = vsi->back;
4187
4188 /* now that we have an index, find the tx_ring struct */
4189 for (i = 0; i < vsi->num_queue_pairs; i++) {
4190 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4191 if (q_idx == vsi->tx_rings[i]->queue_index) {
4192 tx_ring = vsi->tx_rings[i];
4193 break;
4194 }
4195 }
4196 }
4197
4198 if (!tx_ring)
4199 return;
4200
4201 /* Read interrupt register */
4202 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4203 val = rd32(&pf->hw,
4204 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4205 tx_ring->vsi->base_vector - 1));
4206 else
4207 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4208
4209 head = i40e_get_head(tx_ring);
4210
4211 tx_pending = i40e_get_tx_pending(tx_ring);
4212
4213 /* Interrupts are disabled and TX pending is non-zero,
4214 * trigger the SW interrupt (don't wait). Worst case
4215 * there will be one extra interrupt which may result
4216 * into not cleaning any queues because queues are cleaned.
4217 */
4218 if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK)))
4219 i40e_force_wb(vsi, tx_ring->q_vector);
4220}
4221
4222/**
4223 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4224 * @pf: pointer to PF struct
4225 *
4226 * LAN VSI has netdev and netdev has TX queues. This function is to check
4227 * each of those TX queues if they are hung, trigger recovery by issuing
4228 * SW interrupt.
4229 **/
4230static void i40e_detect_recover_hung(struct i40e_pf *pf)
4231{
4232 struct net_device *netdev;
4233 struct i40e_vsi *vsi;
4234 int i;
4235
4236 /* Only for LAN VSI */
4237 vsi = pf->vsi[pf->lan_vsi];
4238
4239 if (!vsi)
4240 return;
4241
4242 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4243 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4244 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4245 return;
4246
4247 /* Make sure type is MAIN VSI */
4248 if (vsi->type != I40E_VSI_MAIN)
4249 return;
4250
4251 netdev = vsi->netdev;
4252 if (!netdev)
4253 return;
4254
4255 /* Bail out if netif_carrier is not OK */
4256 if (!netif_carrier_ok(netdev))
4257 return;
4258
4259 /* Go thru' TX queues for netdev */
4260 for (i = 0; i < netdev->num_tx_queues; i++) {
4261 struct netdev_queue *q;
4262
4263 q = netdev_get_tx_queue(netdev, i);
4264 if (q)
4265 i40e_detect_recover_hung_queue(i, vsi);
4266 }
4267}
4268
63d7e5a4
NP		 4269/**
4270 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4271 * @pf: pointer to PF
63d7e5a4
NP		 4272 *
4273 * Get TC map for ISCSI PF type that will include iSCSI TC
4274 * and LAN TC.
4275 **/
4276static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4277{
4278 struct i40e_dcb_app_priority_table app;
4279 struct i40e_hw *hw = &pf->hw;
4280 u8 enabled_tc = 1; /* TC0 is always enabled */
4281 u8 tc, i;
4282 /* Get the iSCSI APP TLV */
4283 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4284
4285 for (i = 0; i < dcbcfg->numapps; i++) {
4286 app = dcbcfg->app[i];
4287 if (app.selector == I40E_APP_SEL_TCPIP &&
4288 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4289 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4290 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4291 break;
4292 }
4293 }
4294
4295 return enabled_tc;
4296}
4297
41c445ff
JB		 4298/**
4299 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4300 * @dcbcfg: the corresponding DCBx configuration structure
4301 *
4302 * Return the number of TCs from given DCBx configuration
4303 **/
4304static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4305{
078b5876
JB		 4306 u8 num_tc = 0;
4307 int i;
41c445ff
JB		 4308
4309 /* Scan the ETS Config Priority Table to find
4310 * traffic class enabled for a given priority
4311 * and use the traffic class index to get the
4312 * number of traffic classes enabled
4313 */
4314 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4315 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4316 num_tc = dcbcfg->etscfg.prioritytable[i];
4317 }
4318
4319 /* Traffic class index starts from zero so
4320 * increment to return the actual count
4321 */
078b5876 4322 return num_tc + 1;
41c445ff
JB		 4323}
4324
4325/**
4326 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4327 * @dcbcfg: the corresponding DCBx configuration structure
4328 *
4329 * Query the current DCB configuration and return the number of
4330 * traffic classes enabled from the given DCBX config
4331 **/
4332static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4333{
4334 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4335 u8 enabled_tc = 1;
4336 u8 i;
4337
4338 for (i = 0; i < num_tc; i++)
41a1d04b 4339 enabled_tc |= BIT(i);
41c445ff
JB		 4340
4341 return enabled_tc;
4342}
4343
4344/**
4345 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4346 * @pf: PF being queried
4347 *
4348 * Return number of traffic classes enabled for the given PF
4349 **/
4350static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4351{
4352 struct i40e_hw *hw = &pf->hw;
4353 u8 i, enabled_tc;
4354 u8 num_tc = 0;
4355 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4356
4357 /* If DCB is not enabled then always in single TC */
4358 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4359 return 1;
4360
63d7e5a4
NP		 4361 /* SFP mode will be enabled for all TCs on port */
4362 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4363 return i40e_dcb_get_num_tc(dcbcfg);
4364
41c445ff 4365 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4366 if (pf->hw.func_caps.iscsi)
4367 enabled_tc = i40e_get_iscsi_tc_map(pf);
4368 else
fc51de96 4369 return 1; /* Only TC0 */
41c445ff 4370
63d7e5a4
NP		 4371 /* At least have TC0 */
4372 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4373 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4374 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4375 num_tc++;
4376 }
4377 return num_tc;
41c445ff
JB		 4378}
4379
4380/**
4381 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4382 * @pf: PF being queried
4383 *
4384 * Return a bitmap for first enabled traffic class for this PF.
4385 **/
4386static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4387{
4388 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4389 u8 i = 0;
4390
4391 if (!enabled_tc)
4392 return 0x1; /* TC0 */
4393
4394 /* Find the first enabled TC */
4395 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4396 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4397 break;
4398 }
4399
41a1d04b 4400 return BIT(i);
41c445ff
JB		 4401}
4402
4403/**
4404 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4405 * @pf: PF being queried
4406 *
4407 * Return a bitmap for enabled traffic classes for this PF.
4408 **/
4409static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4410{
4411 /* If DCB is not enabled for this PF then just return default TC */
4412 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4413 return i40e_pf_get_default_tc(pf);
4414
41c445ff 4415 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4416 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4417 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4418
fc51de96 4419 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4420 if (pf->hw.func_caps.iscsi)
4421 return i40e_get_iscsi_tc_map(pf);
4422 else
fc51de96 4423 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4424}
4425
4426/**
4427 * i40e_vsi_get_bw_info - Query VSI BW Information
4428 * @vsi: the VSI being queried
4429 *
4430 * Returns 0 on success, negative value on failure
4431 **/
4432static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4433{
4434 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4435 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4436 struct i40e_pf *pf = vsi->back;
4437 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4438 i40e_status ret;
41c445ff 4439 u32 tc_bw_max;
41c445ff
JB		 4440 int i;
4441
4442 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4443 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4444 if (ret) {
41c445ff 4445 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4446 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4447 i40e_stat_str(&pf->hw, ret),
4448 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4449 return -EINVAL;
41c445ff
JB		 4450 }
4451
4452 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4453 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4454 NULL);
4455 if (ret) {
41c445ff 4456 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4457 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4458 i40e_stat_str(&pf->hw, ret),
4459 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4460 return -EINVAL;
41c445ff
JB		 4461 }
4462
4463 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4464 dev_info(&pf->pdev->dev,
4465 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4466 bw_config.tc_valid_bits,
4467 bw_ets_config.tc_valid_bits);
4468 /* Still continuing */
4469 }
4470
4471 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4472 vsi->bw_max_quanta = bw_config.max_bw;
4473 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4474 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4475 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4476 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4477 vsi->bw_ets_limit_credits[i] =
4478 le16_to_cpu(bw_ets_config.credits[i]);
4479 /* 3 bits out of 4 for each TC */
4480 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4481 }
078b5876 4482
dcae29be 4483 return 0;
41c445ff
JB		 4484}
4485
4486/**
4487 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4488 * @vsi: the VSI being configured
4489 * @enabled_tc: TC bitmap
4490 * @bw_credits: BW shared credits per TC
4491 *
4492 * Returns 0 on success, negative value on failure
4493 **/
dcae29be 4494static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4495 u8 *bw_share)
4496{
4497 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4498 i40e_status ret;
dcae29be 4499 int i;
41c445ff
JB		 4500
4501 bw_data.tc_valid_bits = enabled_tc;
4502 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4503 bw_data.tc_bw_credits[i] = bw_share[i];
4504
f1c7e72e
SN		 4505 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4506 NULL);
4507 if (ret) {
41c445ff 4508 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4509 "AQ command Config VSI BW allocation per TC failed = %d\n",
4510 vsi->back->hw.aq.asq_last_status);
dcae29be 4511 return -EINVAL;
41c445ff
JB		 4512 }
4513
4514 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4515 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4516
dcae29be 4517 return 0;
41c445ff
JB		 4518}
4519
4520/**
4521 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4522 * @vsi: the VSI being configured
4523 * @enabled_tc: TC map to be enabled
4524 *
4525 **/
4526static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4527{
4528 struct net_device *netdev = vsi->netdev;
4529 struct i40e_pf *pf = vsi->back;
4530 struct i40e_hw *hw = &pf->hw;
4531 u8 netdev_tc = 0;
4532 int i;
4533 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4534
4535 if (!netdev)
4536 return;
4537
4538 if (!enabled_tc) {
4539 netdev_reset_tc(netdev);
4540 return;
4541 }
4542
4543 /* Set up actual enabled TCs on the VSI */
4544 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4545 return;
4546
4547 /* set per TC queues for the VSI */
4548 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4549 /* Only set TC queues for enabled tcs
4550 *
4551 * e.g. For a VSI that has TC0 and TC3 enabled the
4552 * enabled_tc bitmap would be 0x00001001; the driver
4553 * will set the numtc for netdev as 2 that will be
4554 * referenced by the netdev layer as TC 0 and 1.
4555 */
41a1d04b 4556 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4557 netdev_set_tc_queue(netdev,
4558 vsi->tc_config.tc_info[i].netdev_tc,
4559 vsi->tc_config.tc_info[i].qcount,
4560 vsi->tc_config.tc_info[i].qoffset);
4561 }
4562
4563 /* Assign UP2TC map for the VSI */
4564 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4565 /* Get the actual TC# for the UP */
4566 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4567 /* Get the mapped netdev TC# for the UP */
4568 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4569 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4570 }
4571}
4572
4573/**
4574 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4575 * @vsi: the VSI being configured
4576 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4577 **/
4578static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4579 struct i40e_vsi_context *ctxt)
4580{
4581 /* copy just the sections touched not the entire info
4582 * since not all sections are valid as returned by
4583 * update vsi params
4584 */
4585 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4586 memcpy(&vsi->info.queue_mapping,
4587 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4588 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4589 sizeof(vsi->info.tc_mapping));
4590}
4591
4592/**
4593 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4594 * @vsi: VSI to be configured
4595 * @enabled_tc: TC bitmap
4596 *
4597 * This configures a particular VSI for TCs that are mapped to the
4598 * given TC bitmap. It uses default bandwidth share for TCs across
4599 * VSIs to configure TC for a particular VSI.
4600 *
4601 * NOTE:
4602 * It is expected that the VSI queues have been quisced before calling
4603 * this function.
4604 **/
4605static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4606{
4607 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4608 struct i40e_vsi_context ctxt;
4609 int ret = 0;
4610 int i;
4611
4612 /* Check if enabled_tc is same as existing or new TCs */
4613 if (vsi->tc_config.enabled_tc == enabled_tc)
4614 return ret;
4615
4616 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4617 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4618 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4619 bw_share[i] = 1;
4620 }
4621
4622 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4623 if (ret) {
4624 dev_info(&vsi->back->pdev->dev,
4625 "Failed configuring TC map %d for VSI %d\n",
4626 enabled_tc, vsi->seid);
4627 goto out;
4628 }
4629
4630 /* Update Queue Pairs Mapping for currently enabled UPs */
4631 ctxt.seid = vsi->seid;
4632 ctxt.pf_num = vsi->back->hw.pf_id;
4633 ctxt.vf_num = 0;
4634 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4635 ctxt.info = vsi->info;
41c445ff
JB		 4636 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4637
4638 /* Update the VSI after updating the VSI queue-mapping information */
4639 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4640 if (ret) {
4641 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4642 "Update vsi tc config failed, err %s aq_err %s\n",
4643 i40e_stat_str(&vsi->back->hw, ret),
4644 i40e_aq_str(&vsi->back->hw,
4645 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4646 goto out;
4647 }
4648 /* update the local VSI info with updated queue map */
4649 i40e_vsi_update_queue_map(vsi, &ctxt);
4650 vsi->info.valid_sections = 0;
4651
4652 /* Update current VSI BW information */
4653 ret = i40e_vsi_get_bw_info(vsi);
4654 if (ret) {
4655 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4656 "Failed updating vsi bw info, err %s aq_err %s\n",
4657 i40e_stat_str(&vsi->back->hw, ret),
4658 i40e_aq_str(&vsi->back->hw,
4659 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4660 goto out;
4661 }
4662
4663 /* Update the netdev TC setup */
4664 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4665out:
4666 return ret;
4667}
4668
4e3b35b0
NP		 4669/**
4670 * i40e_veb_config_tc - Configure TCs for given VEB
4671 * @veb: given VEB
4672 * @enabled_tc: TC bitmap
4673 *
4674 * Configures given TC bitmap for VEB (switching) element
4675 **/
4676int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4677{
4678 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4679 struct i40e_pf *pf = veb->pf;
4680 int ret = 0;
4681 int i;
4682
4683 /* No TCs or already enabled TCs just return */
4684 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4685 return ret;
4686
4687 bw_data.tc_valid_bits = enabled_tc;
4688 /* bw_data.absolute_credits is not set (relative) */
4689
4690 /* Enable ETS TCs with equal BW Share for now */
4691 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4692 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4693 bw_data.tc_bw_share_credits[i] = 1;
4694 }
4695
4696 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4697 &bw_data, NULL);
4698 if (ret) {
4699 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4700 "VEB bw config failed, err %s aq_err %s\n",
4701 i40e_stat_str(&pf->hw, ret),
4702 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4703 goto out;
4704 }
4705
4706 /* Update the BW information */
4707 ret = i40e_veb_get_bw_info(veb);
4708 if (ret) {
4709 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4710 "Failed getting veb bw config, err %s aq_err %s\n",
4711 i40e_stat_str(&pf->hw, ret),
4712 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4713 }
4714
4715out:
4716 return ret;
4717}
4718
4719#ifdef CONFIG_I40E_DCB
4720/**
4721 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4722 * @pf: PF struct
4723 *
4724 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4725 * the caller would've quiesce all the VSIs before calling
4726 * this function
4727 **/
4728static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4729{
4730 u8 tc_map = 0;
4731 int ret;
4732 u8 v;
4733
4734 /* Enable the TCs available on PF to all VEBs */
4735 tc_map = i40e_pf_get_tc_map(pf);
4736 for (v = 0; v < I40E_MAX_VEB; v++) {
4737 if (!pf->veb[v])
4738 continue;
4739 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4740 if (ret) {
4741 dev_info(&pf->pdev->dev,
4742 "Failed configuring TC for VEB seid=%d\n",
4743 pf->veb[v]->seid);
4744 /* Will try to configure as many components */
4745 }
4746 }
4747
4748 /* Update each VSI */
505682cd 4749 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4750 if (!pf->vsi[v])
4751 continue;
4752
4753 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4754#ifdef I40E_FCOE
4755 * - For FCoE VSI only enable the TC configured
4756 * as per the APP TLV
4757#endif
4e3b35b0
NP		 4758 * - For all others keep them at TC0 for now
4759 */
4760 if (v == pf->lan_vsi)
4761 tc_map = i40e_pf_get_tc_map(pf);
4762 else
4763 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4764#ifdef I40E_FCOE
4765 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4766 tc_map = i40e_get_fcoe_tc_map(pf);
4767#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4768
4769 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4770 if (ret) {
4771 dev_info(&pf->pdev->dev,
4772 "Failed configuring TC for VSI seid=%d\n",
4773 pf->vsi[v]->seid);
4774 /* Will try to configure as many components */
4775 } else {
0672a091
NP		 4776 /* Re-configure VSI vectors based on updated TC map */
4777 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4778 if (pf->vsi[v]->netdev)
4779 i40e_dcbnl_set_all(pf->vsi[v]);
4780 }
4781 }
4782}
4783
2fd75f31
NP		 4784/**
4785 * i40e_resume_port_tx - Resume port Tx
4786 * @pf: PF struct
4787 *
4788 * Resume a port's Tx and issue a PF reset in case of failure to
4789 * resume.
4790 **/
4791static int i40e_resume_port_tx(struct i40e_pf *pf)
4792{
4793 struct i40e_hw *hw = &pf->hw;
4794 int ret;
4795
4796 ret = i40e_aq_resume_port_tx(hw, NULL);
4797 if (ret) {
4798 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4799 "Resume Port Tx failed, err %s aq_err %s\n",
4800 i40e_stat_str(&pf->hw, ret),
4801 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4802 /* Schedule PF reset to recover */
4803 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4804 i40e_service_event_schedule(pf);
4805 }
4806
4807 return ret;
4808}
4809
4e3b35b0
NP		 4810/**
4811 * i40e_init_pf_dcb - Initialize DCB configuration
4812 * @pf: PF being configured
4813 *
4814 * Query the current DCB configuration and cache it
4815 * in the hardware structure
4816 **/
4817static int i40e_init_pf_dcb(struct i40e_pf *pf)
4818{
4819 struct i40e_hw *hw = &pf->hw;
4820 int err = 0;
4821
025b4a54
ASJ		 4822 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4823 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4824 (pf->hw.aq.fw_maj_ver < 4))
4825 goto out;
4826
4e3b35b0
NP		 4827 /* Get the initial DCB configuration */
4828 err = i40e_init_dcb(hw);
4829 if (!err) {
4830 /* Device/Function is not DCBX capable */
4831 if ((!hw->func_caps.dcb) ||
4832 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4833 dev_info(&pf->pdev->dev,
4834 "DCBX offload is not supported or is disabled for this PF.\n");
4835
4836 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4837 goto out;
4838
4839 } else {
4840 /* When status is not DISABLED then DCBX in FW */
4841 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4842 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4843
4844 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4845 /* Enable DCB tagging only when more than one TC */
4846 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4847 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4848 dev_dbg(&pf->pdev->dev,
4849 "DCBX offload is supported for this PF.\n");
4e3b35b0 4850 }
014269ff 4851 } else {
aebfc816 4852 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4853 "Query for DCB configuration failed, err %s aq_err %s\n",
4854 i40e_stat_str(&pf->hw, err),
4855 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4856 }
4857
4858out:
4859 return err;
4860}
4861#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4862#define SPEED_SIZE 14
4863#define FC_SIZE 8
4864/**
4865 * i40e_print_link_message - print link up or down
4866 * @vsi: the VSI for which link needs a message
4867 */
4868static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4869{
4870 char speed[SPEED_SIZE] = "Unknown";
4871 char fc[FC_SIZE] = "RX/TX";
4872
4873 if (!isup) {
4874 netdev_info(vsi->netdev, "NIC Link is Down\n");
4875 return;
4876 }
4877
148c2d80
GR		 4878 /* Warn user if link speed on NPAR enabled partition is not at
4879 * least 10GB
4880 */
4881 if (vsi->back->hw.func_caps.npar_enable &&
4882 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4883 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4884 netdev_warn(vsi->netdev,
4885 "The partition detected link speed that is less than 10Gbps\n");
4886
cf05ed08
JB		 4887 switch (vsi->back->hw.phy.link_info.link_speed) {
4888 case I40E_LINK_SPEED_40GB:
35a7d804 4889 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08 4890 break;
ae24b409
JB		 4891 case I40E_LINK_SPEED_20GB:
4892 strncpy(speed, "20 Gbps", SPEED_SIZE);
4893 break;
cf05ed08 4894 case I40E_LINK_SPEED_10GB:
35a7d804 4895 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4896 break;
4897 case I40E_LINK_SPEED_1GB:
35a7d804 4898 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4899 break;
5960d33f
MW		 4900 case I40E_LINK_SPEED_100MB:
4901 strncpy(speed, "100 Mbps", SPEED_SIZE);
4902 break;
cf05ed08
JB		 4903 default:
4904 break;
4905 }
4906
4907 switch (vsi->back->hw.fc.current_mode) {
4908 case I40E_FC_FULL:
35a7d804 4909 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4910 break;
4911 case I40E_FC_TX_PAUSE:
35a7d804 4912 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4913 break;
4914 case I40E_FC_RX_PAUSE:
35a7d804 4915 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4916 break;
4917 default:
35a7d804 4918 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4919 break;
4920 }
4921
4922 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4923 speed, fc);
4924}
4e3b35b0 4925
41c445ff
JB		 4926/**
4927 * i40e_up_complete - Finish the last steps of bringing up a connection
4928 * @vsi: the VSI being configured
4929 **/
4930static int i40e_up_complete(struct i40e_vsi *vsi)
4931{
4932 struct i40e_pf *pf = vsi->back;
4933 int err;
4934
4935 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4936 i40e_vsi_configure_msix(vsi);
4937 else
4938 i40e_configure_msi_and_legacy(vsi);
4939
4940 /* start rings */
4941 err = i40e_vsi_control_rings(vsi, true);
4942 if (err)
4943 return err;
4944
4945 clear_bit(__I40E_DOWN, &vsi->state);
4946 i40e_napi_enable_all(vsi);
4947 i40e_vsi_enable_irq(vsi);
4948
4949 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4950 (vsi->netdev)) {
cf05ed08 4951 i40e_print_link_message(vsi, true);
41c445ff
JB		 4952 netif_tx_start_all_queues(vsi->netdev);
4953 netif_carrier_on(vsi->netdev);
6d779b41 4954 } else if (vsi->netdev) {
cf05ed08 4955 i40e_print_link_message(vsi, false);
7b592f61
CW		 4956 /* need to check for qualified module here*/
4957 if ((pf->hw.phy.link_info.link_info &
4958 I40E_AQ_MEDIA_AVAILABLE) &&
4959 (!(pf->hw.phy.link_info.an_info &
4960 I40E_AQ_QUALIFIED_MODULE)))
4961 netdev_err(vsi->netdev,
4962 "the driver failed to link because an unqualified module was detected.");
41c445ff 4963 }
ca64fa4e
ASJ		 4964
4965 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4966 if (vsi->type == I40E_VSI_FDIR) {
4967 /* reset fd counters */
4968 pf->fd_add_err = pf->fd_atr_cnt = 0;
4969 if (pf->fd_tcp_rule > 0) {
4970 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 4971 if (I40E_DEBUG_FD & pf->hw.debug_mask)
4972 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 4973 pf->fd_tcp_rule = 0;
4974 }
ca64fa4e 4975 i40e_fdir_filter_restore(vsi);
1e1be8f6 4976 }
41c445ff
JB		 4977 i40e_service_event_schedule(pf);
4978
4979 return 0;
4980}
4981
4982/**
4983 * i40e_vsi_reinit_locked - Reset the VSI
4984 * @vsi: the VSI being configured
4985 *
4986 * Rebuild the ring structs after some configuration
4987 * has changed, e.g. MTU size.
4988 **/
4989static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4990{
4991 struct i40e_pf *pf = vsi->back;
4992
4993 WARN_ON(in_interrupt());
4994 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4995 usleep_range(1000, 2000);
4996 i40e_down(vsi);
4997
4998 /* Give a VF some time to respond to the reset. The
4999 * two second wait is based upon the watchdog cycle in
5000 * the VF driver.
5001 */
5002 if (vsi->type == I40E_VSI_SRIOV)
5003 msleep(2000);
5004 i40e_up(vsi);
5005 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5006}
5007
5008/**
5009 * i40e_up - Bring the connection back up after being down
5010 * @vsi: the VSI being configured
5011 **/
5012int i40e_up(struct i40e_vsi *vsi)
5013{
5014 int err;
5015
5016 err = i40e_vsi_configure(vsi);
5017 if (!err)
5018 err = i40e_up_complete(vsi);
5019
5020 return err;
5021}
5022
5023/**
5024 * i40e_down - Shutdown the connection processing
5025 * @vsi: the VSI being stopped
5026 **/
5027void i40e_down(struct i40e_vsi *vsi)
5028{
5029 int i;
5030
5031 /* It is assumed that the caller of this function
5032 * sets the vsi->state __I40E_DOWN bit.
5033 */
5034 if (vsi->netdev) {
5035 netif_carrier_off(vsi->netdev);
5036 netif_tx_disable(vsi->netdev);
5037 }
5038 i40e_vsi_disable_irq(vsi);
5039 i40e_vsi_control_rings(vsi, false);
5040 i40e_napi_disable_all(vsi);
5041
5042 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5043 i40e_clean_tx_ring(vsi->tx_rings[i]);
5044 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5045 }
5046}
5047
5048/**
5049 * i40e_setup_tc - configure multiple traffic classes
5050 * @netdev: net device to configure
5051 * @tc: number of traffic classes to enable
5052 **/
38e00438
VD		 5053#ifdef I40E_FCOE
5054int i40e_setup_tc(struct net_device *netdev, u8 tc)
5055#else
41c445ff 5056static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5057#endif
41c445ff
JB		 5058{
5059 struct i40e_netdev_priv *np = netdev_priv(netdev);
5060 struct i40e_vsi *vsi = np->vsi;
5061 struct i40e_pf *pf = vsi->back;
5062 u8 enabled_tc = 0;
5063 int ret = -EINVAL;
5064 int i;
5065
5066 /* Check if DCB enabled to continue */
5067 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5068 netdev_info(netdev, "DCB is not enabled for adapter\n");
5069 goto exit;
5070 }
5071
5072 /* Check if MFP enabled */
5073 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5074 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5075 goto exit;
5076 }
5077
5078 /* Check whether tc count is within enabled limit */
5079 if (tc > i40e_pf_get_num_tc(pf)) {
5080 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5081 goto exit;
5082 }
5083
5084 /* Generate TC map for number of tc requested */
5085 for (i = 0; i < tc; i++)
41a1d04b 5086 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5087
5088 /* Requesting same TC configuration as already enabled */
5089 if (enabled_tc == vsi->tc_config.enabled_tc)
5090 return 0;
5091
5092 /* Quiesce VSI queues */
5093 i40e_quiesce_vsi(vsi);
5094
5095 /* Configure VSI for enabled TCs */
5096 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5097 if (ret) {
5098 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5099 vsi->seid);
5100 goto exit;
5101 }
5102
5103 /* Unquiesce VSI */
5104 i40e_unquiesce_vsi(vsi);
5105
5106exit:
5107 return ret;
5108}
5109
5110/**
5111 * i40e_open - Called when a network interface is made active
5112 * @netdev: network interface device structure
5113 *
5114 * The open entry point is called when a network interface is made
5115 * active by the system (IFF_UP). At this point all resources needed
5116 * for transmit and receive operations are allocated, the interrupt
5117 * handler is registered with the OS, the netdev watchdog subtask is
5118 * enabled, and the stack is notified that the interface is ready.
5119 *
5120 * Returns 0 on success, negative value on failure
5121 **/
38e00438 5122int i40e_open(struct net_device *netdev)
41c445ff
JB		 5123{
5124 struct i40e_netdev_priv *np = netdev_priv(netdev);
5125 struct i40e_vsi *vsi = np->vsi;
5126 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5127 int err;
5128
4eb3f768
SN		 5129 /* disallow open during test or if eeprom is broken */
5130 if (test_bit(__I40E_TESTING, &pf->state) ||
5131 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5132 return -EBUSY;
5133
5134 netif_carrier_off(netdev);
5135
6c167f58
EK		 5136 err = i40e_vsi_open(vsi);
5137 if (err)
5138 return err;
5139
059dab69
JB		 5140 /* configure global TSO hardware offload settings */
5141 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5142 TCP_FLAG_FIN) >> 16);
5143 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5144 TCP_FLAG_FIN |
5145 TCP_FLAG_CWR) >> 16);
5146 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5147
6c167f58
EK		 5148#ifdef CONFIG_I40E_VXLAN
5149 vxlan_get_rx_port(netdev);
5150#endif
5151
5152 return 0;
5153}
5154
5155/**
5156 * i40e_vsi_open -
5157 * @vsi: the VSI to open
5158 *
5159 * Finish initialization of the VSI.
5160 *
5161 * Returns 0 on success, negative value on failure
5162 **/
5163int i40e_vsi_open(struct i40e_vsi *vsi)
5164{
5165 struct i40e_pf *pf = vsi->back;
b294ac70 5166 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5167 int err;
5168
41c445ff
JB		 5169 /* allocate descriptors */
5170 err = i40e_vsi_setup_tx_resources(vsi);
5171 if (err)
5172 goto err_setup_tx;
5173 err = i40e_vsi_setup_rx_resources(vsi);
5174 if (err)
5175 goto err_setup_rx;
5176
5177 err = i40e_vsi_configure(vsi);
5178 if (err)
5179 goto err_setup_rx;
5180
c22e3c6c
SN		 5181 if (vsi->netdev) {
5182 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5183 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5184 err = i40e_vsi_request_irq(vsi, int_name);
5185 if (err)
5186 goto err_setup_rx;
41c445ff 5187
c22e3c6c
SN		 5188 /* Notify the stack of the actual queue counts. */
5189 err = netif_set_real_num_tx_queues(vsi->netdev,
5190 vsi->num_queue_pairs);
5191 if (err)
5192 goto err_set_queues;
25946ddb 5193
c22e3c6c
SN		 5194 err = netif_set_real_num_rx_queues(vsi->netdev,
5195 vsi->num_queue_pairs);
5196 if (err)
5197 goto err_set_queues;
8a9eb7d3
SN		 5198
5199 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5200 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5201 dev_driver_string(&pf->pdev->dev),
5202 dev_name(&pf->pdev->dev));
8a9eb7d3 5203 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5204
c22e3c6c 5205 } else {
ce9ccb17 5206 err = -EINVAL;
6c167f58
EK		 5207 goto err_setup_rx;
5208 }
25946ddb 5209
41c445ff
JB		 5210 err = i40e_up_complete(vsi);
5211 if (err)
5212 goto err_up_complete;
5213
41c445ff
JB		 5214 return 0;
5215
5216err_up_complete:
5217 i40e_down(vsi);
25946ddb 5218err_set_queues:
41c445ff
JB		 5219 i40e_vsi_free_irq(vsi);
5220err_setup_rx:
5221 i40e_vsi_free_rx_resources(vsi);
5222err_setup_tx:
5223 i40e_vsi_free_tx_resources(vsi);
5224 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5225 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5226
5227 return err;
5228}
5229
17a73f6b
JG		 5230/**
5231 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5232 * @pf: Pointer to PF
17a73f6b
JG		 5233 *
5234 * This function destroys the hlist where all the Flow Director
5235 * filters were saved.
5236 **/
5237static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5238{
5239 struct i40e_fdir_filter *filter;
5240 struct hlist_node *node2;
5241
5242 hlist_for_each_entry_safe(filter, node2,
5243 &pf->fdir_filter_list, fdir_node) {
5244 hlist_del(&filter->fdir_node);
5245 kfree(filter);
5246 }
5247 pf->fdir_pf_active_filters = 0;
5248}
5249
41c445ff
JB		 5250/**
5251 * i40e_close - Disables a network interface
5252 * @netdev: network interface device structure
5253 *
5254 * The close entry point is called when an interface is de-activated
5255 * by the OS. The hardware is still under the driver's control, but
5256 * this netdev interface is disabled.
5257 *
5258 * Returns 0, this is not allowed to fail
5259 **/
38e00438
VD		 5260#ifdef I40E_FCOE
5261int i40e_close(struct net_device *netdev)
5262#else
41c445ff 5263static int i40e_close(struct net_device *netdev)
38e00438 5264#endif
41c445ff
JB		 5265{
5266 struct i40e_netdev_priv *np = netdev_priv(netdev);
5267 struct i40e_vsi *vsi = np->vsi;
5268
90ef8d47 5269 i40e_vsi_close(vsi);
41c445ff
JB		 5270
5271 return 0;
5272}
5273
5274/**
5275 * i40e_do_reset - Start a PF or Core Reset sequence
5276 * @pf: board private structure
5277 * @reset_flags: which reset is requested
5278 *
5279 * The essential difference in resets is that the PF Reset
5280 * doesn't clear the packet buffers, doesn't reset the PE
5281 * firmware, and doesn't bother the other PFs on the chip.
5282 **/
5283void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5284{
5285 u32 val;
5286
5287 WARN_ON(in_interrupt());
5288
263fc48f
MW		 5289 if (i40e_check_asq_alive(&pf->hw))
5290 i40e_vc_notify_reset(pf);
5291
41c445ff 5292 /* do the biggest reset indicated */
41a1d04b 5293 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5294
5295 /* Request a Global Reset
5296 *
5297 * This will start the chip's countdown to the actual full
5298 * chip reset event, and a warning interrupt to be sent
5299 * to all PFs, including the requestor. Our handler
5300 * for the warning interrupt will deal with the shutdown
5301 * and recovery of the switch setup.
5302 */
69bfb110 5303 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5304 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5305 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5306 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5307
41a1d04b 5308 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5309
5310 /* Request a Core Reset
5311 *
5312 * Same as Global Reset, except does *not* include the MAC/PHY
5313 */
69bfb110 5314 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5315 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5316 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5317 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5318 i40e_flush(&pf->hw);
5319
41a1d04b 5320 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5321
5322 /* Request a PF Reset
5323 *
5324 * Resets only the PF-specific registers
5325 *
5326 * This goes directly to the tear-down and rebuild of
5327 * the switch, since we need to do all the recovery as
5328 * for the Core Reset.
5329 */
69bfb110 5330 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5331 i40e_handle_reset_warning(pf);
5332
41a1d04b 5333 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5334 int v;
5335
5336 /* Find the VSI(s) that requested a re-init */
5337 dev_info(&pf->pdev->dev,
5338 "VSI reinit requested\n");
505682cd 5339 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5340 struct i40e_vsi *vsi = pf->vsi[v];
5341 if (vsi != NULL &&
5342 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5343 i40e_vsi_reinit_locked(pf->vsi[v]);
5344 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5345 }
5346 }
5347
b5d06f05
NP		 5348 /* no further action needed, so return now */
5349 return;
41a1d04b 5350 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5351 int v;
5352
5353 /* Find the VSI(s) that needs to be brought down */
5354 dev_info(&pf->pdev->dev, "VSI down requested\n");
5355 for (v = 0; v < pf->num_alloc_vsi; v++) {
5356 struct i40e_vsi *vsi = pf->vsi[v];
5357 if (vsi != NULL &&
5358 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5359 set_bit(__I40E_DOWN, &vsi->state);
5360 i40e_down(vsi);
5361 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5362 }
5363 }
5364
41c445ff
JB		 5365 /* no further action needed, so return now */
5366 return;
5367 } else {
5368 dev_info(&pf->pdev->dev,
5369 "bad reset request 0x%08x\n", reset_flags);
5370 return;
5371 }
5372}
5373
4e3b35b0
NP		 5374#ifdef CONFIG_I40E_DCB
5375/**
5376 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5377 * @pf: board private structure
5378 * @old_cfg: current DCB config
5379 * @new_cfg: new DCB config
5380 **/
5381bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5382 struct i40e_dcbx_config *old_cfg,
5383 struct i40e_dcbx_config *new_cfg)
5384{
5385 bool need_reconfig = false;
5386
5387 /* Check if ETS configuration has changed */
5388 if (memcmp(&new_cfg->etscfg,
5389 &old_cfg->etscfg,
5390 sizeof(new_cfg->etscfg))) {
5391 /* If Priority Table has changed reconfig is needed */
5392 if (memcmp(&new_cfg->etscfg.prioritytable,
5393 &old_cfg->etscfg.prioritytable,
5394 sizeof(new_cfg->etscfg.prioritytable))) {
5395 need_reconfig = true;
69bfb110 5396 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5397 }
5398
5399 if (memcmp(&new_cfg->etscfg.tcbwtable,
5400 &old_cfg->etscfg.tcbwtable,
5401 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5402 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5403
5404 if (memcmp(&new_cfg->etscfg.tsatable,
5405 &old_cfg->etscfg.tsatable,
5406 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5407 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5408 }
5409
5410 /* Check if PFC configuration has changed */
5411 if (memcmp(&new_cfg->pfc,
5412 &old_cfg->pfc,
5413 sizeof(new_cfg->pfc))) {
5414 need_reconfig = true;
69bfb110 5415 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5416 }
5417
5418 /* Check if APP Table has changed */
5419 if (memcmp(&new_cfg->app,
5420 &old_cfg->app,
3d9667a9 5421 sizeof(new_cfg->app))) {
4e3b35b0 5422 need_reconfig = true;
69bfb110 5423 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5424 }
4e3b35b0 5425
9fa61dd2
NP		 5426 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5427 need_reconfig);
4e3b35b0
NP		 5428 return need_reconfig;
5429}
5430
5431/**
5432 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5433 * @pf: board private structure
5434 * @e: event info posted on ARQ
5435 **/
5436static int i40e_handle_lldp_event(struct i40e_pf *pf,
5437 struct i40e_arq_event_info *e)
5438{
5439 struct i40e_aqc_lldp_get_mib *mib =
5440 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5441 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5442 struct i40e_dcbx_config tmp_dcbx_cfg;
5443 bool need_reconfig = false;
5444 int ret = 0;
5445 u8 type;
5446
4d9b6043
NP		 5447 /* Not DCB capable or capability disabled */
5448 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5449 return ret;
5450
4e3b35b0
NP		 5451 /* Ignore if event is not for Nearest Bridge */
5452 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5453 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5454 dev_dbg(&pf->pdev->dev,
5455 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5456 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5457 return ret;
5458
5459 /* Check MIB Type and return if event for Remote MIB update */
5460 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5461 dev_dbg(&pf->pdev->dev,
5462 "%s: LLDP event mib type %s\n", __func__,
5463 type ? "remote" : "local");
4e3b35b0
NP		 5464 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5465 /* Update the remote cached instance and return */
5466 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5467 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5468 &hw->remote_dcbx_config);
5469 goto exit;
5470 }
5471
9fa61dd2 5472 /* Store the old configuration */
1a2f6248 5473 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5474
750fcbcf
NP		 5475 /* Reset the old DCBx configuration data */
5476 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5477 /* Get updated DCBX data from firmware */
5478 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5479 if (ret) {
f1c7e72e
SN		 5480 dev_info(&pf->pdev->dev,
5481 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5482 i40e_stat_str(&pf->hw, ret),
5483 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5484 goto exit;
5485 }
5486
5487 /* No change detected in DCBX configs */
750fcbcf
NP		 5488 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5489 sizeof(tmp_dcbx_cfg))) {
69bfb110 5490 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5491 goto exit;
5492 }
5493
750fcbcf
NP		 5494 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5495 &hw->local_dcbx_config);
4e3b35b0 5496
750fcbcf 5497 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5498
5499 if (!need_reconfig)
5500 goto exit;
5501
4d9b6043 5502 /* Enable DCB tagging only when more than one TC */
750fcbcf 5503 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5504 pf->flags |= I40E_FLAG_DCB_ENABLED;
5505 else
5506 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5507
69129dc3 5508 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5509 /* Reconfiguration needed quiesce all VSIs */
5510 i40e_pf_quiesce_all_vsi(pf);
5511
5512 /* Changes in configuration update VEB/VSI */
5513 i40e_dcb_reconfigure(pf);
5514
2fd75f31
NP		 5515 ret = i40e_resume_port_tx(pf);
5516
69129dc3 5517 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5518 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5519 if (ret)
5520 goto exit;
5521
5522 /* Wait for the PF's Tx queues to be disabled */
5523 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5524 if (ret) {
5525 /* Schedule PF reset to recover */
5526 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5527 i40e_service_event_schedule(pf);
5528 } else {
2fd75f31 5529 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5530 }
5531
4e3b35b0
NP		 5532exit:
5533 return ret;
5534}
5535#endif /* CONFIG_I40E_DCB */
5536
23326186
ASJ		 5537/**
5538 * i40e_do_reset_safe - Protected reset path for userland calls.
5539 * @pf: board private structure
5540 * @reset_flags: which reset is requested
5541 *
5542 **/
5543void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5544{
5545 rtnl_lock();
5546 i40e_do_reset(pf, reset_flags);
5547 rtnl_unlock();
5548}
5549
41c445ff
JB		 5550/**
5551 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5552 * @pf: board private structure
5553 * @e: event info posted on ARQ
5554 *
5555 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5556 * and VF queues
5557 **/
5558static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5559 struct i40e_arq_event_info *e)
5560{
5561 struct i40e_aqc_lan_overflow *data =
5562 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5563 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5564 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5565 struct i40e_hw *hw = &pf->hw;
5566 struct i40e_vf *vf;
5567 u16 vf_id;
5568
69bfb110
JB		 5569 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5570 queue, qtx_ctl);
41c445ff
JB		 5571
5572 /* Queue belongs to VF, find the VF and issue VF reset */
5573 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5574 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5575 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5576 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5577 vf_id -= hw->func_caps.vf_base_id;
5578 vf = &pf->vf[vf_id];
5579 i40e_vc_notify_vf_reset(vf);
5580 /* Allow VF to process pending reset notification */
5581 msleep(20);
5582 i40e_reset_vf(vf, false);
5583 }
5584}
5585
5586/**
5587 * i40e_service_event_complete - Finish up the service event
5588 * @pf: board private structure
5589 **/
5590static void i40e_service_event_complete(struct i40e_pf *pf)
5591{
5592 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5593
5594 /* flush memory to make sure state is correct before next watchog */
4e857c58 5595 smp_mb__before_atomic();
41c445ff
JB		 5596 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5597}
5598
55a5e60b 5599/**
12957388
ASJ		 5600 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5601 * @pf: board private structure
5602 **/
04294e38 5603u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5604{
04294e38 5605 u32 val, fcnt_prog;
12957388
ASJ		 5606
5607 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5608 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5609 return fcnt_prog;
5610}
5611
5612/**
04294e38 5613 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5614 * @pf: board private structure
5615 **/
04294e38 5616u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5617{
04294e38
ASJ		 5618 u32 val, fcnt_prog;
5619
55a5e60b
ASJ		 5620 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5621 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5622 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5623 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5624 return fcnt_prog;
5625}
1e1be8f6 5626
04294e38
ASJ		 5627/**
5628 * i40e_get_global_fd_count - Get total FD filters programmed on device
5629 * @pf: board private structure
5630 **/
5631u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5632{
5633 u32 val, fcnt_prog;
5634
5635 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5636 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5637 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5638 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5639 return fcnt_prog;
5640}
5641
55a5e60b
ASJ		 5642/**
5643 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5644 * @pf: board private structure
5645 **/
5646void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5647{
5648 u32 fcnt_prog, fcnt_avail;
5649
1e1be8f6
ASJ		 5650 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5651 return;
5652
55a5e60b
ASJ		 5653 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5654 * to re-enable
5655 */
04294e38 5656 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5657 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5658 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5659 (pf->fd_add_err == 0) ||
5660 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5661 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5662 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5663 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5664 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5665 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5666 }
5667 }
5668 /* Wait for some more space to be available to turn on ATR */
5669 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5670 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5671 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5672 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5673 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5674 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5675 }
5676 }
5677}
5678
1e1be8f6 5679#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5680#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5681/**
5682 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5683 * @pf: board private structure
5684 **/
5685static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5686{
04294e38 5687 unsigned long min_flush_time;
1e1be8f6 5688 int flush_wait_retry = 50;
04294e38
ASJ		 5689 bool disable_atr = false;
5690 int fd_room;
1e1be8f6
ASJ		 5691 int reg;
5692
1790ed0c
AA		 5693 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5694 return;
5695
1e1be8f6
ASJ		 5696 if (time_after(jiffies, pf->fd_flush_timestamp +
5697 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
04294e38
ASJ		 5698 /* If the flush is happening too quick and we have mostly
5699 * SB rules we should not re-enable ATR for some time.
5700 */
5701 min_flush_time = pf->fd_flush_timestamp
5702 + (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5703 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5704
5705 if (!(time_after(jiffies, min_flush_time)) &&
5706 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
2e4875e3
ASJ		 5707 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5708 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
04294e38
ASJ		 5709 disable_atr = true;
5710 }
5711
1e1be8f6 5712 pf->fd_flush_timestamp = jiffies;
1e1be8f6
ASJ		 5713 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5714 /* flush all filters */
5715 wr32(&pf->hw, I40E_PFQF_CTL_1,
5716 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5717 i40e_flush(&pf->hw);
60793f4a 5718 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5719 pf->fd_add_err = 0;
5720 do {
5721 /* Check FD flush status every 5-6msec */
5722 usleep_range(5000, 6000);
5723 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5724 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5725 break;
5726 } while (flush_wait_retry--);
5727 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5728 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5729 } else {
5730 /* replay sideband filters */
5731 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
04294e38
ASJ		 5732 if (!disable_atr)
5733 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
1e1be8f6 5734 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
2e4875e3
ASJ		 5735 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5736 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6
ASJ		 5737 }
5738 }
5739}
5740
5741/**
5742 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5743 * @pf: board private structure
5744 **/
04294e38 5745u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5746{
5747 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5748}
5749
5750/* We can see up to 256 filter programming desc in transit if the filters are
5751 * being applied really fast; before we see the first
5752 * filter miss error on Rx queue 0. Accumulating enough error messages before
5753 * reacting will make sure we don't cause flush too often.
5754 */
5755#define I40E_MAX_FD_PROGRAM_ERROR 256
5756
41c445ff
JB		 5757/**
5758 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5759 * @pf: board private structure
5760 **/
5761static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5762{
41c445ff 5763
41c445ff
JB		 5764 /* if interface is down do nothing */
5765 if (test_bit(__I40E_DOWN, &pf->state))
5766 return;
1e1be8f6 5767
1790ed0c
AA		 5768 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5769 return;
5770
04294e38 5771 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5772 i40e_fdir_flush_and_replay(pf);
5773
55a5e60b
ASJ		 5774 i40e_fdir_check_and_reenable(pf);
5775
41c445ff
JB		 5776}
5777
5778/**
5779 * i40e_vsi_link_event - notify VSI of a link event
5780 * @vsi: vsi to be notified
5781 * @link_up: link up or down
5782 **/
5783static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5784{
32b5b811 5785 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5786 return;
5787
5788 switch (vsi->type) {
5789 case I40E_VSI_MAIN:
38e00438
VD		 5790#ifdef I40E_FCOE
5791 case I40E_VSI_FCOE:
5792#endif
41c445ff
JB		 5793 if (!vsi->netdev || !vsi->netdev_registered)
5794 break;
5795
5796 if (link_up) {
5797 netif_carrier_on(vsi->netdev);
5798 netif_tx_wake_all_queues(vsi->netdev);
5799 } else {
5800 netif_carrier_off(vsi->netdev);
5801 netif_tx_stop_all_queues(vsi->netdev);
5802 }
5803 break;
5804
5805 case I40E_VSI_SRIOV:
41c445ff
JB		 5806 case I40E_VSI_VMDQ2:
5807 case I40E_VSI_CTRL:
5808 case I40E_VSI_MIRROR:
5809 default:
5810 /* there is no notification for other VSIs */
5811 break;
5812 }
5813}
5814
5815/**
5816 * i40e_veb_link_event - notify elements on the veb of a link event
5817 * @veb: veb to be notified
5818 * @link_up: link up or down
5819 **/
5820static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5821{
5822 struct i40e_pf *pf;
5823 int i;
5824
5825 if (!veb || !veb->pf)
5826 return;
5827 pf = veb->pf;
5828
5829 /* depth first... */
5830 for (i = 0; i < I40E_MAX_VEB; i++)
5831 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5832 i40e_veb_link_event(pf->veb[i], link_up);
5833
5834 /* ... now the local VSIs */
505682cd 5835 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5836 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5837 i40e_vsi_link_event(pf->vsi[i], link_up);
5838}
5839
5840/**
5841 * i40e_link_event - Update netif_carrier status
5842 * @pf: board private structure
5843 **/
5844static void i40e_link_event(struct i40e_pf *pf)
5845{
5846 bool new_link, old_link;
320684cd 5847 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5848 u8 new_link_speed, old_link_speed;
41c445ff 5849
1e701e09
JB		 5850 /* set this to force the get_link_status call to refresh state */
5851 pf->hw.phy.get_link_info = true;
5852
41c445ff 5853 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5854 new_link = i40e_get_link_status(&pf->hw);
fef59ddf
CS		 5855 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5856 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5857
1e701e09 5858 if (new_link == old_link &&
fef59ddf 5859 new_link_speed == old_link_speed &&
320684cd
MW		 5860 (test_bit(__I40E_DOWN, &vsi->state) ||
5861 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5862 return;
320684cd
MW		 5863
5864 if (!test_bit(__I40E_DOWN, &vsi->state))
5865 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5866
5867 /* Notify the base of the switch tree connected to
5868 * the link. Floating VEBs are not notified.
5869 */
5870 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5871 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5872 else
320684cd 5873 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5874
5875 if (pf->vf)
5876 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5877
5878 if (pf->flags & I40E_FLAG_PTP)
5879 i40e_ptp_set_increment(pf);
41c445ff
JB		 5880}
5881
41c445ff 5882/**
21536717 5883 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5884 * @pf: board private structure
5885 **/
5886static void i40e_watchdog_subtask(struct i40e_pf *pf)
5887{
5888 int i;
5889
5890 /* if interface is down do nothing */
5891 if (test_bit(__I40E_DOWN, &pf->state) ||
5892 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5893 return;
5894
21536717
SN		 5895 /* make sure we don't do these things too often */
5896 if (time_before(jiffies, (pf->service_timer_previous +
5897 pf->service_timer_period)))
5898 return;
5899 pf->service_timer_previous = jiffies;
5900
21536717
SN		 5901 i40e_link_event(pf);
5902
41c445ff
JB		 5903 /* Update the stats for active netdevs so the network stack
5904 * can look at updated numbers whenever it cares to
5905 */
505682cd 5906 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5907 if (pf->vsi[i] && pf->vsi[i]->netdev)
5908 i40e_update_stats(pf->vsi[i]);
5909
d1a8d275
ASJ		 5910 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
5911 /* Update the stats for the active switching components */
5912 for (i = 0; i < I40E_MAX_VEB; i++)
5913 if (pf->veb[i])
5914 i40e_update_veb_stats(pf->veb[i]);
5915 }
beb0dff1
JK		 5916
5917 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5918}
5919
5920/**
5921 * i40e_reset_subtask - Set up for resetting the device and driver
5922 * @pf: board private structure
5923 **/
5924static void i40e_reset_subtask(struct i40e_pf *pf)
5925{
5926 u32 reset_flags = 0;
5927
23326186 5928 rtnl_lock();
41c445ff 5929 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 5930 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 5931 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5932 }
5933 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 5934 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 5935 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5936 }
5937 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 5938 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 5939 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5940 }
5941 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 5942 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 5943 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5944 }
b5d06f05 5945 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 5946 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 5947 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5948 }
41c445ff
JB		 5949
5950 /* If there's a recovery already waiting, it takes
5951 * precedence before starting a new reset sequence.
5952 */
5953 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5954 i40e_handle_reset_warning(pf);
23326186 5955 goto unlock;
41c445ff
JB		 5956 }
5957
5958 /* If we're already down or resetting, just bail */
5959 if (reset_flags &&
5960 !test_bit(__I40E_DOWN, &pf->state) &&
5961 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5962 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5963
5964unlock:
5965 rtnl_unlock();
41c445ff
JB		 5966}
5967
5968/**
5969 * i40e_handle_link_event - Handle link event
5970 * @pf: board private structure
5971 * @e: event info posted on ARQ
5972 **/
5973static void i40e_handle_link_event(struct i40e_pf *pf,
5974 struct i40e_arq_event_info *e)
5975{
5976 struct i40e_hw *hw = &pf->hw;
5977 struct i40e_aqc_get_link_status *status =
5978 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff
JB		 5979
5980 /* save off old link status information */
1a2f6248 5981 hw->phy.link_info_old = hw->phy.link_info;
41c445ff 5982
1e701e09
JB		 5983 /* Do a new status request to re-enable LSE reporting
5984 * and load new status information into the hw struct
5985 * This completely ignores any state information
5986 * in the ARQ event info, instead choosing to always
5987 * issue the AQ update link status command.
5988 */
5989 i40e_link_event(pf);
5990
7b592f61
CW		 5991 /* check for unqualified module, if link is down */
5992 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5993 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5994 (!(status->link_info & I40E_AQ_LINK_UP)))
5995 dev_err(&pf->pdev->dev,
5996 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5997}
5998
5999/**
6000 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6001 * @pf: board private structure
6002 **/
6003static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6004{
6005 struct i40e_arq_event_info event;
6006 struct i40e_hw *hw = &pf->hw;
6007 u16 pending, i = 0;
6008 i40e_status ret;
6009 u16 opcode;
86df242b 6010 u32 oldval;
41c445ff
JB		 6011 u32 val;
6012
a316f651
ASJ		 6013 /* Do not run clean AQ when PF reset fails */
6014 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6015 return;
6016
86df242b
SN		 6017 /* check for error indications */
6018 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6019 oldval = val;
6020 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6021 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6022 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6023 }
6024 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6025 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6026 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6027 }
6028 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6029 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6030 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6031 }
6032 if (oldval != val)
6033 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6034
6035 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6036 oldval = val;
6037 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6038 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6039 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6040 }
6041 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6042 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6043 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6044 }
6045 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6046 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6047 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6048 }
6049 if (oldval != val)
6050 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6051
1001dc37
MW		 6052 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6053 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6054 if (!event.msg_buf)
6055 return;
6056
6057 do {
6058 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6059 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6060 break;
56497978 6061 else if (ret) {
41c445ff
JB		 6062 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6063 break;
6064 }
6065
6066 opcode = le16_to_cpu(event.desc.opcode);
6067 switch (opcode) {
6068
6069 case i40e_aqc_opc_get_link_status:
6070 i40e_handle_link_event(pf, &event);
6071 break;
6072 case i40e_aqc_opc_send_msg_to_pf:
6073 ret = i40e_vc_process_vf_msg(pf,
6074 le16_to_cpu(event.desc.retval),
6075 le32_to_cpu(event.desc.cookie_high),
6076 le32_to_cpu(event.desc.cookie_low),
6077 event.msg_buf,
1001dc37 6078 event.msg_len);
41c445ff
JB		 6079 break;
6080 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6081 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6082#ifdef CONFIG_I40E_DCB
6083 rtnl_lock();
6084 ret = i40e_handle_lldp_event(pf, &event);
6085 rtnl_unlock();
6086#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6087 break;
6088 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6089 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6090 i40e_handle_lan_overflow_event(pf, &event);
6091 break;
0467bc91
SN		 6092 case i40e_aqc_opc_send_msg_to_peer:
6093 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6094 break;
91a0f930
SN		 6095 case i40e_aqc_opc_nvm_erase:
6096 case i40e_aqc_opc_nvm_update:
6097 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6098 break;
41c445ff
JB		 6099 default:
6100 dev_info(&pf->pdev->dev,
0467bc91
SN		 6101 "ARQ Error: Unknown event 0x%04x received\n",
6102 opcode);
41c445ff
JB		 6103 break;
6104 }
6105 } while (pending && (i++ < pf->adminq_work_limit));
6106
6107 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6108 /* re-enable Admin queue interrupt cause */
6109 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6110 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6111 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6112 i40e_flush(hw);
6113
6114 kfree(event.msg_buf);
6115}
6116
4eb3f768
SN		 6117/**
6118 * i40e_verify_eeprom - make sure eeprom is good to use
6119 * @pf: board private structure
6120 **/
6121static void i40e_verify_eeprom(struct i40e_pf *pf)
6122{
6123 int err;
6124
6125 err = i40e_diag_eeprom_test(&pf->hw);
6126 if (err) {
6127 /* retry in case of garbage read */
6128 err = i40e_diag_eeprom_test(&pf->hw);
6129 if (err) {
6130 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6131 err);
6132 set_bit(__I40E_BAD_EEPROM, &pf->state);
6133 }
6134 }
6135
6136 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6137 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6138 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6139 }
6140}
6141
386a0afa
AA		 6142/**
6143 * i40e_enable_pf_switch_lb
b40c82e6 6144 * @pf: pointer to the PF structure
386a0afa
AA		 6145 *
6146 * enable switch loop back or die - no point in a return value
6147 **/
6148static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6149{
6150 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6151 struct i40e_vsi_context ctxt;
f1c7e72e 6152 int ret;
386a0afa
AA		 6153
6154 ctxt.seid = pf->main_vsi_seid;
6155 ctxt.pf_num = pf->hw.pf_id;
6156 ctxt.vf_num = 0;
f1c7e72e
SN		 6157 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6158 if (ret) {
386a0afa 6159 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6160 "couldn't get PF vsi config, err %s aq_err %s\n",
6161 i40e_stat_str(&pf->hw, ret),
6162 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6163 return;
6164 }
6165 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6166 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6167 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6168
f1c7e72e
SN		 6169 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6170 if (ret) {
386a0afa 6171 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6172 "update vsi switch failed, err %s aq_err %s\n",
6173 i40e_stat_str(&pf->hw, ret),
6174 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6175 }
6176}
6177
6178/**
6179 * i40e_disable_pf_switch_lb
b40c82e6 6180 * @pf: pointer to the PF structure
386a0afa
AA		 6181 *
6182 * disable switch loop back or die - no point in a return value
6183 **/
6184static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6185{
6186 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6187 struct i40e_vsi_context ctxt;
f1c7e72e 6188 int ret;
386a0afa
AA		 6189
6190 ctxt.seid = pf->main_vsi_seid;
6191 ctxt.pf_num = pf->hw.pf_id;
6192 ctxt.vf_num = 0;
f1c7e72e
SN		 6193 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6194 if (ret) {
386a0afa 6195 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6196 "couldn't get PF vsi config, err %s aq_err %s\n",
6197 i40e_stat_str(&pf->hw, ret),
6198 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6199 return;
6200 }
6201 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6202 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6203 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6204
f1c7e72e
SN		 6205 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6206 if (ret) {
386a0afa 6207 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6208 "update vsi switch failed, err %s aq_err %s\n",
6209 i40e_stat_str(&pf->hw, ret),
6210 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6211 }
6212}
6213
51616018
NP		 6214/**
6215 * i40e_config_bridge_mode - Configure the HW bridge mode
6216 * @veb: pointer to the bridge instance
6217 *
6218 * Configure the loop back mode for the LAN VSI that is downlink to the
6219 * specified HW bridge instance. It is expected this function is called
6220 * when a new HW bridge is instantiated.
6221 **/
6222static void i40e_config_bridge_mode(struct i40e_veb *veb)
6223{
6224 struct i40e_pf *pf = veb->pf;
6225
6226 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6227 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
6228 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6229 i40e_disable_pf_switch_lb(pf);
6230 else
6231 i40e_enable_pf_switch_lb(pf);
6232}
6233
41c445ff
JB		 6234/**
6235 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6236 * @veb: pointer to the VEB instance
6237 *
6238 * This is a recursive function that first builds the attached VSIs then
6239 * recurses in to build the next layer of VEB. We track the connections
6240 * through our own index numbers because the seid's from the HW could
6241 * change across the reset.
6242 **/
6243static int i40e_reconstitute_veb(struct i40e_veb *veb)
6244{
6245 struct i40e_vsi *ctl_vsi = NULL;
6246 struct i40e_pf *pf = veb->pf;
6247 int v, veb_idx;
6248 int ret;
6249
6250 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6251 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6252 if (pf->vsi[v] &&
6253 pf->vsi[v]->veb_idx == veb->idx &&
6254 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6255 ctl_vsi = pf->vsi[v];
6256 break;
6257 }
6258 }
6259 if (!ctl_vsi) {
6260 dev_info(&pf->pdev->dev,
6261 "missing owner VSI for veb_idx %d\n", veb->idx);
6262 ret = -ENOENT;
6263 goto end_reconstitute;
6264 }
6265 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6266 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6267 ret = i40e_add_vsi(ctl_vsi);
6268 if (ret) {
6269 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6270 "rebuild of veb_idx %d owner VSI failed: %d\n",
6271 veb->idx, ret);
41c445ff
JB		 6272 goto end_reconstitute;
6273 }
6274 i40e_vsi_reset_stats(ctl_vsi);
6275
6276 /* create the VEB in the switch and move the VSI onto the VEB */
6277 ret = i40e_add_veb(veb, ctl_vsi);
6278 if (ret)
6279 goto end_reconstitute;
6280
fc60861e
ASJ		 6281 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6282 veb->bridge_mode = BRIDGE_MODE_VEB;
6283 else
6284 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6285 i40e_config_bridge_mode(veb);
b64ba084 6286
41c445ff 6287 /* create the remaining VSIs attached to this VEB */
505682cd 6288 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6289 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6290 continue;
6291
6292 if (pf->vsi[v]->veb_idx == veb->idx) {
6293 struct i40e_vsi *vsi = pf->vsi[v];
6294 vsi->uplink_seid = veb->seid;
6295 ret = i40e_add_vsi(vsi);
6296 if (ret) {
6297 dev_info(&pf->pdev->dev,
6298 "rebuild of vsi_idx %d failed: %d\n",
6299 v, ret);
6300 goto end_reconstitute;
6301 }
6302 i40e_vsi_reset_stats(vsi);
6303 }
6304 }
6305
6306 /* create any VEBs attached to this VEB - RECURSION */
6307 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6308 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6309 pf->veb[veb_idx]->uplink_seid = veb->seid;
6310 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6311 if (ret)
6312 break;
6313 }
6314 }
6315
6316end_reconstitute:
6317 return ret;
6318}
6319
6320/**
6321 * i40e_get_capabilities - get info about the HW
6322 * @pf: the PF struct
6323 **/
6324static int i40e_get_capabilities(struct i40e_pf *pf)
6325{
6326 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6327 u16 data_size;
6328 int buf_len;
6329 int err;
6330
6331 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6332 do {
6333 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6334 if (!cap_buf)
6335 return -ENOMEM;
6336
6337 /* this loads the data into the hw struct for us */
6338 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6339 &data_size,
6340 i40e_aqc_opc_list_func_capabilities,
6341 NULL);
6342 /* data loaded, buffer no longer needed */
6343 kfree(cap_buf);
6344
6345 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6346 /* retry with a larger buffer */
6347 buf_len = data_size;
6348 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6349 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6350 "capability discovery failed, err %s aq_err %s\n",
6351 i40e_stat_str(&pf->hw, err),
6352 i40e_aq_str(&pf->hw,
6353 pf->hw.aq.asq_last_status));
41c445ff
JB		 6354 return -ENODEV;
6355 }
6356 } while (err);
6357
ac71b7ba
ASJ		 6358 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6359 (pf->hw.aq.fw_maj_ver < 2)) {
6360 pf->hw.func_caps.num_msix_vectors++;
6361 pf->hw.func_caps.num_msix_vectors_vf++;
6362 }
6363
41c445ff
JB		 6364 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6365 dev_info(&pf->pdev->dev,
6366 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6367 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6368 pf->hw.func_caps.num_msix_vectors,
6369 pf->hw.func_caps.num_msix_vectors_vf,
6370 pf->hw.func_caps.fd_filters_guaranteed,
6371 pf->hw.func_caps.fd_filters_best_effort,
6372 pf->hw.func_caps.num_tx_qp,
6373 pf->hw.func_caps.num_vsis);
6374
7134f9ce
JB		 6375#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6376 + pf->hw.func_caps.num_vfs)
6377 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6378 dev_info(&pf->pdev->dev,
6379 "got num_vsis %d, setting num_vsis to %d\n",
6380 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6381 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6382 }
6383
41c445ff
JB		 6384 return 0;
6385}
6386
cbf61325
ASJ		 6387static int i40e_vsi_clear(struct i40e_vsi *vsi);
6388
41c445ff 6389/**
cbf61325 6390 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6391 * @pf: board private structure
6392 **/
cbf61325 6393static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6394{
6395 struct i40e_vsi *vsi;
8a9eb7d3 6396 int i;
41c445ff 6397
407e063c
JB		 6398 /* quick workaround for an NVM issue that leaves a critical register
6399 * uninitialized
6400 */
6401 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6402 static const u32 hkey[] = {
6403 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6404 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6405 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6406 0x95b3a76d};
6407
6408 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6409 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6410 }
6411
cbf61325 6412 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6413 return;
6414
cbf61325 6415 /* find existing VSI and see if it needs configuring */
41c445ff 6416 vsi = NULL;
505682cd 6417 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6418 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6419 vsi = pf->vsi[i];
cbf61325
ASJ		 6420 break;
6421 }
6422 }
6423
6424 /* create a new VSI if none exists */
41c445ff 6425 if (!vsi) {
cbf61325
ASJ		 6426 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6427 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6428 if (!vsi) {
6429 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6430 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6431 return;
41c445ff 6432 }
cbf61325 6433 }
41c445ff 6434
8a9eb7d3 6435 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6436}
6437
6438/**
6439 * i40e_fdir_teardown - release the Flow Director resources
6440 * @pf: board private structure
6441 **/
6442static void i40e_fdir_teardown(struct i40e_pf *pf)
6443{
6444 int i;
6445
17a73f6b 6446 i40e_fdir_filter_exit(pf);
505682cd 6447 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6448 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6449 i40e_vsi_release(pf->vsi[i]);
6450 break;
6451 }
6452 }
6453}
6454
6455/**
f650a38b 6456 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6457 * @pf: board private structure
6458 *
b40c82e6 6459 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6460 **/
23cfbe07 6461static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6462{
41c445ff 6463 struct i40e_hw *hw = &pf->hw;
60442dea 6464 i40e_status ret = 0;
41c445ff
JB		 6465 u32 v;
6466
6467 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6468 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6469 return;
41c445ff 6470
69bfb110 6471 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6472
41c445ff
JB		 6473 /* quiesce the VSIs and their queues that are not already DOWN */
6474 i40e_pf_quiesce_all_vsi(pf);
6475
505682cd 6476 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6477 if (pf->vsi[v])
6478 pf->vsi[v]->seid = 0;
6479 }
6480
6481 i40e_shutdown_adminq(&pf->hw);
6482
f650a38b 6483 /* call shutdown HMC */
60442dea
SN		 6484 if (hw->hmc.hmc_obj) {
6485 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6486 if (ret)
60442dea
SN		 6487 dev_warn(&pf->pdev->dev,
6488 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6489 }
f650a38b
ASJ		 6490}
6491
44033fac
JB		 6492/**
6493 * i40e_send_version - update firmware with driver version
6494 * @pf: PF struct
6495 */
6496static void i40e_send_version(struct i40e_pf *pf)
6497{
6498 struct i40e_driver_version dv;
6499
6500 dv.major_version = DRV_VERSION_MAJOR;
6501 dv.minor_version = DRV_VERSION_MINOR;
6502 dv.build_version = DRV_VERSION_BUILD;
6503 dv.subbuild_version = 0;
35a7d804 6504 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6505 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6506}
6507
f650a38b 6508/**
4dda12e6 6509 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6510 * @pf: board private structure
bc7d338f 6511 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6512 **/
bc7d338f 6513static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6514{
f650a38b 6515 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6516 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6517 i40e_status ret;
6518 u32 v;
6519
41c445ff
JB		 6520 /* Now we wait for GRST to settle out.
6521 * We don't have to delete the VEBs or VSIs from the hw switch
6522 * because the reset will make them disappear.
6523 */
6524 ret = i40e_pf_reset(hw);
b5565400 6525 if (ret) {
41c445ff 6526 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6527 set_bit(__I40E_RESET_FAILED, &pf->state);
6528 goto clear_recovery;
b5565400 6529 }
41c445ff
JB		 6530 pf->pfr_count++;
6531
6532 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6533 goto clear_recovery;
69bfb110 6534 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6535
6536 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6537 ret = i40e_init_adminq(&pf->hw);
6538 if (ret) {
f1c7e72e
SN		 6539 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6540 i40e_stat_str(&pf->hw, ret),
6541 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6542 goto clear_recovery;
41c445ff
JB		 6543 }
6544
4eb3f768 6545 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6546 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6547 i40e_verify_eeprom(pf);
4eb3f768 6548
e78ac4bf 6549 i40e_clear_pxe_mode(hw);
41c445ff 6550 ret = i40e_get_capabilities(pf);
f1c7e72e 6551 if (ret)
41c445ff 6552 goto end_core_reset;
41c445ff 6553
41c445ff
JB		 6554 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6555 hw->func_caps.num_rx_qp,
6556 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6557 if (ret) {
6558 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6559 goto end_core_reset;
6560 }
6561 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6562 if (ret) {
6563 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6564 goto end_core_reset;
6565 }
6566
4e3b35b0
NP		 6567#ifdef CONFIG_I40E_DCB
6568 ret = i40e_init_pf_dcb(pf);
6569 if (ret) {
aebfc816
SN		 6570 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6571 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6572 /* Continue without DCB enabled */
4e3b35b0
NP		 6573 }
6574#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6575#ifdef I40E_FCOE
6576 ret = i40e_init_pf_fcoe(pf);
6577 if (ret)
6578 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6579
38e00438 6580#endif
41c445ff 6581 /* do basic switch setup */
bc7d338f 6582 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6583 if (ret)
6584 goto end_core_reset;
6585
7e2453fe
JB		 6586 /* driver is only interested in link up/down and module qualification
6587 * reports from firmware
6588 */
6589 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6590 I40E_AQ_EVENT_LINK_UPDOWN |
6591 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6592 if (ret)
f1c7e72e
SN		 6593 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6594 i40e_stat_str(&pf->hw, ret),
6595 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6596
cafa2ee6
ASJ		 6597 /* make sure our flow control settings are restored */
6598 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6599 if (ret)
f1c7e72e
SN		 6600 dev_info(&pf->pdev->dev, "set fc fail, err %s aq_err %s\n",
6601 i40e_stat_str(&pf->hw, ret),
6602 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6603
41c445ff
JB		 6604 /* Rebuild the VSIs and VEBs that existed before reset.
6605 * They are still in our local switch element arrays, so only
6606 * need to rebuild the switch model in the HW.
6607 *
6608 * If there were VEBs but the reconstitution failed, we'll try
6609 * try to recover minimal use by getting the basic PF VSI working.
6610 */
6611 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6612 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6613 /* find the one VEB connected to the MAC, and find orphans */
6614 for (v = 0; v < I40E_MAX_VEB; v++) {
6615 if (!pf->veb[v])
6616 continue;
6617
6618 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6619 pf->veb[v]->uplink_seid == 0) {
6620 ret = i40e_reconstitute_veb(pf->veb[v]);
6621
6622 if (!ret)
6623 continue;
6624
6625 /* If Main VEB failed, we're in deep doodoo,
6626 * so give up rebuilding the switch and set up
6627 * for minimal rebuild of PF VSI.
6628 * If orphan failed, we'll report the error
6629 * but try to keep going.
6630 */
6631 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6632 dev_info(&pf->pdev->dev,
6633 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6634 ret);
6635 pf->vsi[pf->lan_vsi]->uplink_seid
6636 = pf->mac_seid;
6637 break;
6638 } else if (pf->veb[v]->uplink_seid == 0) {
6639 dev_info(&pf->pdev->dev,
6640 "rebuild of orphan VEB failed: %d\n",
6641 ret);
6642 }
6643 }
6644 }
6645 }
6646
6647 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6648 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6649 /* no VEB, so rebuild only the Main VSI */
6650 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6651 if (ret) {
6652 dev_info(&pf->pdev->dev,
6653 "rebuild of Main VSI failed: %d\n", ret);
6654 goto end_core_reset;
6655 }
6656 }
6657
025b4a54
ASJ		 6658 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6659 (pf->hw.aq.fw_maj_ver < 4)) {
6660 msleep(75);
6661 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6662 if (ret)
f1c7e72e
SN		 6663 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6664 i40e_stat_str(&pf->hw, ret),
6665 i40e_aq_str(&pf->hw,
6666 pf->hw.aq.asq_last_status));
cafa2ee6 6667 }
41c445ff
JB		 6668 /* reinit the misc interrupt */
6669 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6670 ret = i40e_setup_misc_vector(pf);
6671
6672 /* restart the VSIs that were rebuilt and running before the reset */
6673 i40e_pf_unquiesce_all_vsi(pf);
6674
69f64b2b
MW		 6675 if (pf->num_alloc_vfs) {
6676 for (v = 0; v < pf->num_alloc_vfs; v++)
6677 i40e_reset_vf(&pf->vf[v], true);
6678 }
6679
41c445ff 6680 /* tell the firmware that we're starting */
44033fac 6681 i40e_send_version(pf);
41c445ff
JB		 6682
6683end_core_reset:
a316f651
ASJ		 6684 clear_bit(__I40E_RESET_FAILED, &pf->state);
6685clear_recovery:
41c445ff
JB		 6686 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6687}
6688
f650a38b 6689/**
b40c82e6 6690 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6691 * @pf: board private structure
6692 *
6693 * Close up the VFs and other things in prep for a Core Reset,
6694 * then get ready to rebuild the world.
6695 **/
6696static void i40e_handle_reset_warning(struct i40e_pf *pf)
6697{
23cfbe07
SN		 6698 i40e_prep_for_reset(pf);
6699 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6700}
6701
41c445ff
JB		 6702/**
6703 * i40e_handle_mdd_event
b40c82e6 6704 * @pf: pointer to the PF structure
41c445ff
JB		 6705 *
6706 * Called from the MDD irq handler to identify possibly malicious vfs
6707 **/
6708static void i40e_handle_mdd_event(struct i40e_pf *pf)
6709{
6710 struct i40e_hw *hw = &pf->hw;
6711 bool mdd_detected = false;
df430b12 6712 bool pf_mdd_detected = false;
41c445ff
JB		 6713 struct i40e_vf *vf;
6714 u32 reg;
6715 int i;
6716
6717 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6718 return;
6719
6720 /* find what triggered the MDD event */
6721 reg = rd32(hw, I40E_GL_MDET_TX);
6722 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6723 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6724 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6725 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6726 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6727 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6728 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6729 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6730 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6731 pf->hw.func_caps.base_queue;
faf32978 6732 if (netif_msg_tx_err(pf))
b40c82e6 6733 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6734 event, queue, pf_num, vf_num);
41c445ff
JB		 6735 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6736 mdd_detected = true;
6737 }
6738 reg = rd32(hw, I40E_GL_MDET_RX);
6739 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6740 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6741 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6742 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6743 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6744 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6745 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6746 pf->hw.func_caps.base_queue;
faf32978
JB		 6747 if (netif_msg_rx_err(pf))
6748 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6749 event, queue, func);
41c445ff
JB		 6750 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6751 mdd_detected = true;
6752 }
6753
df430b12
NP		 6754 if (mdd_detected) {
6755 reg = rd32(hw, I40E_PF_MDET_TX);
6756 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6757 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6758 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6759 pf_mdd_detected = true;
6760 }
6761 reg = rd32(hw, I40E_PF_MDET_RX);
6762 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6763 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6764 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6765 pf_mdd_detected = true;
6766 }
6767 /* Queue belongs to the PF, initiate a reset */
6768 if (pf_mdd_detected) {
6769 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6770 i40e_service_event_schedule(pf);
6771 }
6772 }
6773
41c445ff
JB		 6774 /* see if one of the VFs needs its hand slapped */
6775 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6776 vf = &(pf->vf[i]);
6777 reg = rd32(hw, I40E_VP_MDET_TX(i));
6778 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6779 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6780 vf->num_mdd_events++;
faf32978
JB		 6781 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6782 i);
41c445ff
JB		 6783 }
6784
6785 reg = rd32(hw, I40E_VP_MDET_RX(i));
6786 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6787 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6788 vf->num_mdd_events++;
faf32978
JB		 6789 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6790 i);
41c445ff
JB		 6791 }
6792
6793 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6794 dev_info(&pf->pdev->dev,
6795 "Too many MDD events on VF %d, disabled\n", i);
6796 dev_info(&pf->pdev->dev,
6797 "Use PF Control I/F to re-enable the VF\n");
6798 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6799 }
6800 }
6801
6802 /* re-enable mdd interrupt cause */
6803 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6804 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6805 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6806 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6807 i40e_flush(hw);
6808}
6809
a1c9a9d9
JK		 6810#ifdef CONFIG_I40E_VXLAN
6811/**
6812 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6813 * @pf: board private structure
6814 **/
6815static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6816{
a1c9a9d9
JK		 6817 struct i40e_hw *hw = &pf->hw;
6818 i40e_status ret;
a1c9a9d9
JK		 6819 __be16 port;
6820 int i;
6821
6822 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6823 return;
6824
6825 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6826
6827 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 6828 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
6829 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 6830 port = pf->vxlan_ports[i];
c22c06c8
SN		 6831 if (port)
6832 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 6833 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 6834 NULL, NULL);
6835 else
6836 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 6837
6838 if (ret) {
c22c06c8 6839 dev_info(&pf->pdev->dev,
f1c7e72e 6840 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 6841 port ? "add" : "delete",
f1c7e72e
SN		 6842 ntohs(port), i,
6843 i40e_stat_str(&pf->hw, ret),
6844 i40e_aq_str(&pf->hw,
6845 pf->hw.aq.asq_last_status));
a1c9a9d9 6846 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 6847 }
6848 }
6849 }
6850}
6851
6852#endif
41c445ff
JB		 6853/**
6854 * i40e_service_task - Run the driver's async subtasks
6855 * @work: pointer to work_struct containing our data
6856 **/
6857static void i40e_service_task(struct work_struct *work)
6858{
6859 struct i40e_pf *pf = container_of(work,
6860 struct i40e_pf,
6861 service_task);
6862 unsigned long start_time = jiffies;
6863
e57a2fea
SN		 6864 /* don't bother with service tasks if a reset is in progress */
6865 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6866 i40e_service_event_complete(pf);
6867 return;
6868 }
6869
b03a8c1f 6870 i40e_detect_recover_hung(pf);
41c445ff
JB		 6871 i40e_reset_subtask(pf);
6872 i40e_handle_mdd_event(pf);
6873 i40e_vc_process_vflr_event(pf);
6874 i40e_watchdog_subtask(pf);
6875 i40e_fdir_reinit_subtask(pf);
41c445ff 6876 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6877#ifdef CONFIG_I40E_VXLAN
6878 i40e_sync_vxlan_filters_subtask(pf);
6879#endif
41c445ff
JB		 6880 i40e_clean_adminq_subtask(pf);
6881
6882 i40e_service_event_complete(pf);
6883
6884 /* If the tasks have taken longer than one timer cycle or there
6885 * is more work to be done, reschedule the service task now
6886 * rather than wait for the timer to tick again.
6887 */
6888 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6889 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6890 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6891 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6892 i40e_service_event_schedule(pf);
6893}
6894
6895/**
6896 * i40e_service_timer - timer callback
6897 * @data: pointer to PF struct
6898 **/
6899static void i40e_service_timer(unsigned long data)
6900{
6901 struct i40e_pf *pf = (struct i40e_pf *)data;
6902
6903 mod_timer(&pf->service_timer,
6904 round_jiffies(jiffies + pf->service_timer_period));
6905 i40e_service_event_schedule(pf);
6906}
6907
6908/**
6909 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6910 * @vsi: the VSI being configured
6911 **/
6912static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6913{
6914 struct i40e_pf *pf = vsi->back;
6915
6916 switch (vsi->type) {
6917 case I40E_VSI_MAIN:
6918 vsi->alloc_queue_pairs = pf->num_lan_qps;
6919 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6920 I40E_REQ_DESCRIPTOR_MULTIPLE);
6921 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6922 vsi->num_q_vectors = pf->num_lan_msix;
6923 else
6924 vsi->num_q_vectors = 1;
6925
6926 break;
6927
6928 case I40E_VSI_FDIR:
6929 vsi->alloc_queue_pairs = 1;
6930 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6931 I40E_REQ_DESCRIPTOR_MULTIPLE);
6932 vsi->num_q_vectors = 1;
6933 break;
6934
6935 case I40E_VSI_VMDQ2:
6936 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6937 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6938 I40E_REQ_DESCRIPTOR_MULTIPLE);
6939 vsi->num_q_vectors = pf->num_vmdq_msix;
6940 break;
6941
6942 case I40E_VSI_SRIOV:
6943 vsi->alloc_queue_pairs = pf->num_vf_qps;
6944 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6945 I40E_REQ_DESCRIPTOR_MULTIPLE);
6946 break;
6947
38e00438
VD		 6948#ifdef I40E_FCOE
6949 case I40E_VSI_FCOE:
6950 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6951 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6952 I40E_REQ_DESCRIPTOR_MULTIPLE);
6953 vsi->num_q_vectors = pf->num_fcoe_msix;
6954 break;
6955
6956#endif /* I40E_FCOE */
41c445ff
JB		 6957 default:
6958 WARN_ON(1);
6959 return -ENODATA;
6960 }
6961
6962 return 0;
6963}
6964
f650a38b
ASJ		 6965/**
6966 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6967 * @type: VSI pointer
bc7d338f 6968 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6969 *
6970 * On error: returns error code (negative)
6971 * On success: returns 0
6972 **/
bc7d338f 6973static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6974{
6975 int size;
6976 int ret = 0;
6977
ac6c5e3d 6978 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6979 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6980 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6981 if (!vsi->tx_rings)
6982 return -ENOMEM;
f650a38b
ASJ		 6983 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6984
bc7d338f
ASJ		 6985 if (alloc_qvectors) {
6986 /* allocate memory for q_vector pointers */
f57e4fbd 6987 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6988 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6989 if (!vsi->q_vectors) {
6990 ret = -ENOMEM;
6991 goto err_vectors;
6992 }
f650a38b
ASJ		 6993 }
6994 return ret;
6995
6996err_vectors:
6997 kfree(vsi->tx_rings);
6998 return ret;
6999}
7000
41c445ff
JB		 7001/**
7002 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7003 * @pf: board private structure
7004 * @type: type of VSI
7005 *
7006 * On error: returns error code (negative)
7007 * On success: returns vsi index in PF (positive)
7008 **/
7009static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7010{
7011 int ret = -ENODEV;
7012 struct i40e_vsi *vsi;
7013 int vsi_idx;
7014 int i;
7015
7016 /* Need to protect the allocation of the VSIs at the PF level */
7017 mutex_lock(&pf->switch_mutex);
7018
7019 /* VSI list may be fragmented if VSI creation/destruction has
7020 * been happening. We can afford to do a quick scan to look
7021 * for any free VSIs in the list.
7022 *
7023 * find next empty vsi slot, looping back around if necessary
7024 */
7025 i = pf->next_vsi;
505682cd 7026 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7027 i++;
505682cd 7028 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7029 i = 0;
7030 while (i < pf->next_vsi && pf->vsi[i])
7031 i++;
7032 }
7033
505682cd 7034 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7035 vsi_idx = i; /* Found one! */
7036 } else {
7037 ret = -ENODEV;
493fb300 7038 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7039 }
7040 pf->next_vsi = ++i;
7041
7042 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7043 if (!vsi) {
7044 ret = -ENOMEM;
493fb300 7045 goto unlock_pf;
41c445ff
JB		 7046 }
7047 vsi->type = type;
7048 vsi->back = pf;
7049 set_bit(__I40E_DOWN, &vsi->state);
7050 vsi->flags = 0;
7051 vsi->idx = vsi_idx;
7052 vsi->rx_itr_setting = pf->rx_itr_default;
7053 vsi->tx_itr_setting = pf->tx_itr_default;
5db4cb59
ASJ		 7054 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7055 pf->rss_table_size : 64;
41c445ff
JB		 7056 vsi->netdev_registered = false;
7057 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7058 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7059 vsi->irqs_ready = false;
41c445ff 7060
9f65e15b
AD		 7061 ret = i40e_set_num_rings_in_vsi(vsi);
7062 if (ret)
7063 goto err_rings;
7064
bc7d338f 7065 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7066 if (ret)
9f65e15b 7067 goto err_rings;
493fb300 7068
41c445ff
JB		 7069 /* Setup default MSIX irq handler for VSI */
7070 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7071
7072 pf->vsi[vsi_idx] = vsi;
7073 ret = vsi_idx;
493fb300
AD		 7074 goto unlock_pf;
7075
9f65e15b 7076err_rings:
493fb300
AD		 7077 pf->next_vsi = i - 1;
7078 kfree(vsi);
7079unlock_pf:
41c445ff
JB		 7080 mutex_unlock(&pf->switch_mutex);
7081 return ret;
7082}
7083
f650a38b
ASJ		 7084/**
7085 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7086 * @type: VSI pointer
bc7d338f 7087 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7088 *
7089 * On error: returns error code (negative)
7090 * On success: returns 0
7091 **/
bc7d338f 7092static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7093{
7094 /* free the ring and vector containers */
bc7d338f
ASJ		 7095 if (free_qvectors) {
7096 kfree(vsi->q_vectors);
7097 vsi->q_vectors = NULL;
7098 }
f650a38b
ASJ		 7099 kfree(vsi->tx_rings);
7100 vsi->tx_rings = NULL;
7101 vsi->rx_rings = NULL;
7102}
7103
41c445ff
JB		 7104/**
7105 * i40e_vsi_clear - Deallocate the VSI provided
7106 * @vsi: the VSI being un-configured
7107 **/
7108static int i40e_vsi_clear(struct i40e_vsi *vsi)
7109{
7110 struct i40e_pf *pf;
7111
7112 if (!vsi)
7113 return 0;
7114
7115 if (!vsi->back)
7116 goto free_vsi;
7117 pf = vsi->back;
7118
7119 mutex_lock(&pf->switch_mutex);
7120 if (!pf->vsi[vsi->idx]) {
7121 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7122 vsi->idx, vsi->idx, vsi, vsi->type);
7123 goto unlock_vsi;
7124 }
7125
7126 if (pf->vsi[vsi->idx] != vsi) {
7127 dev_err(&pf->pdev->dev,
7128 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7129 pf->vsi[vsi->idx]->idx,
7130 pf->vsi[vsi->idx],
7131 pf->vsi[vsi->idx]->type,
7132 vsi->idx, vsi, vsi->type);
7133 goto unlock_vsi;
7134 }
7135
b40c82e6 7136 /* updates the PF for this cleared vsi */
41c445ff
JB		 7137 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7138 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7139
bc7d338f 7140 i40e_vsi_free_arrays(vsi, true);
493fb300 7141
41c445ff
JB		 7142 pf->vsi[vsi->idx] = NULL;
7143 if (vsi->idx < pf->next_vsi)
7144 pf->next_vsi = vsi->idx;
7145
7146unlock_vsi:
7147 mutex_unlock(&pf->switch_mutex);
7148free_vsi:
7149 kfree(vsi);
7150
7151 return 0;
7152}
7153
9f65e15b
AD		 7154/**
7155 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7156 * @vsi: the VSI being cleaned
7157 **/
be1d5eea 7158static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7159{
7160 int i;
7161
8e9dca53 7162 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7163 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7164 kfree_rcu(vsi->tx_rings[i], rcu);
7165 vsi->tx_rings[i] = NULL;
7166 vsi->rx_rings[i] = NULL;
7167 }
be1d5eea 7168 }
9f65e15b
AD		 7169}
7170
41c445ff
JB		 7171/**
7172 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7173 * @vsi: the VSI being configured
7174 **/
7175static int i40e_alloc_rings(struct i40e_vsi *vsi)
7176{
e7046ee1 7177 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7178 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7179 int i;
7180
41c445ff 7181 /* Set basic values in the rings to be used later during open() */
d7397644 7182 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7183 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7184 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7185 if (!tx_ring)
7186 goto err_out;
41c445ff
JB		 7187
7188 tx_ring->queue_index = i;
7189 tx_ring->reg_idx = vsi->base_queue + i;
7190 tx_ring->ring_active = false;
7191 tx_ring->vsi = vsi;
7192 tx_ring->netdev = vsi->netdev;
7193 tx_ring->dev = &pf->pdev->dev;
7194 tx_ring->count = vsi->num_desc;
7195 tx_ring->size = 0;
7196 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7197 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7198 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7199 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7200 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7201 vsi->tx_rings[i] = tx_ring;
41c445ff 7202
9f65e15b 7203 rx_ring = &tx_ring[1];
41c445ff
JB		 7204 rx_ring->queue_index = i;
7205 rx_ring->reg_idx = vsi->base_queue + i;
7206 rx_ring->ring_active = false;
7207 rx_ring->vsi = vsi;
7208 rx_ring->netdev = vsi->netdev;
7209 rx_ring->dev = &pf->pdev->dev;
7210 rx_ring->count = vsi->num_desc;
7211 rx_ring->size = 0;
7212 rx_ring->dcb_tc = 0;
7213 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7214 set_ring_16byte_desc_enabled(rx_ring);
7215 else
7216 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7217 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7218 }
7219
7220 return 0;
9f65e15b
AD		 7221
7222err_out:
7223 i40e_vsi_clear_rings(vsi);
7224 return -ENOMEM;
41c445ff
JB		 7225}
7226
7227/**
7228 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7229 * @pf: board private structure
7230 * @vectors: the number of MSI-X vectors to request
7231 *
7232 * Returns the number of vectors reserved, or error
7233 **/
7234static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7235{
7b37f376
AG		 7236 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7237 I40E_MIN_MSIX, vectors);
7238 if (vectors < 0) {
41c445ff 7239 dev_info(&pf->pdev->dev,
7b37f376 7240 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7241 vectors = 0;
7242 }
7243
7244 return vectors;
7245}
7246
7247/**
7248 * i40e_init_msix - Setup the MSIX capability
7249 * @pf: board private structure
7250 *
7251 * Work with the OS to set up the MSIX vectors needed.
7252 *
3b444399 7253 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7254 **/
7255static int i40e_init_msix(struct i40e_pf *pf)
7256{
41c445ff 7257 struct i40e_hw *hw = &pf->hw;
1e200e4a 7258 int vectors_left;
41c445ff 7259 int v_budget, i;
3b444399 7260 int v_actual;
41c445ff
JB		 7261
7262 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7263 return -ENODEV;
7264
7265 /* The number of vectors we'll request will be comprised of:
7266 * - Add 1 for "other" cause for Admin Queue events, etc.
7267 * - The number of LAN queue pairs
f8ff1464
ASJ		 7268 * - Queues being used for RSS.
7269 * We don't need as many as max_rss_size vectors.
7270 * use rss_size instead in the calculation since that
7271 * is governed by number of cpus in the system.
7272 * - assumes symmetric Tx/Rx pairing
41c445ff 7273 * - The number of VMDq pairs
38e00438
VD		 7274#ifdef I40E_FCOE
7275 * - The number of FCOE qps.
7276#endif
41c445ff
JB		 7277 * Once we count this up, try the request.
7278 *
7279 * If we can't get what we want, we'll simplify to nearly nothing
7280 * and try again. If that still fails, we punt.
7281 */
1e200e4a
SN		 7282 vectors_left = hw->func_caps.num_msix_vectors;
7283 v_budget = 0;
7284
7285 /* reserve one vector for miscellaneous handler */
7286 if (vectors_left) {
7287 v_budget++;
7288 vectors_left--;
7289 }
7290
7291 /* reserve vectors for the main PF traffic queues */
7292 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7293 vectors_left -= pf->num_lan_msix;
7294 v_budget += pf->num_lan_msix;
7295
7296 /* reserve one vector for sideband flow director */
7297 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7298 if (vectors_left) {
7299 v_budget++;
7300 vectors_left--;
7301 } else {
7302 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7303 }
7304 }
83840e4b 7305
38e00438 7306#ifdef I40E_FCOE
1e200e4a 7307 /* can we reserve enough for FCoE? */
38e00438 7308 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7309 if (!vectors_left)
7310 pf->num_fcoe_msix = 0;
7311 else if (vectors_left >= pf->num_fcoe_qps)
7312 pf->num_fcoe_msix = pf->num_fcoe_qps;
7313 else
7314 pf->num_fcoe_msix = 1;
38e00438 7315 v_budget += pf->num_fcoe_msix;
1e200e4a 7316 vectors_left -= pf->num_fcoe_msix;
38e00438 7317 }
1e200e4a 7318
38e00438 7319#endif
1e200e4a
SN		 7320 /* any vectors left over go for VMDq support */
7321 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7322 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7323 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7324
7325 /* if we're short on vectors for what's desired, we limit
7326 * the queues per vmdq. If this is still more than are
7327 * available, the user will need to change the number of
7328 * queues/vectors used by the PF later with the ethtool
7329 * channels command
7330 */
7331 if (vmdq_vecs < vmdq_vecs_wanted)
7332 pf->num_vmdq_qps = 1;
7333 pf->num_vmdq_msix = pf->num_vmdq_qps;
7334
7335 v_budget += vmdq_vecs;
7336 vectors_left -= vmdq_vecs;
7337 }
41c445ff
JB		 7338
7339 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7340 GFP_KERNEL);
7341 if (!pf->msix_entries)
7342 return -ENOMEM;
7343
7344 for (i = 0; i < v_budget; i++)
7345 pf->msix_entries[i].entry = i;
3b444399 7346 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7347
3b444399 7348 if (v_actual != v_budget) {
a34977ba
ASJ		 7349 /* If we have limited resources, we will start with no vectors
7350 * for the special features and then allocate vectors to some
7351 * of these features based on the policy and at the end disable
7352 * the features that did not get any vectors.
7353 */
38e00438
VD		 7354#ifdef I40E_FCOE
7355 pf->num_fcoe_qps = 0;
7356 pf->num_fcoe_msix = 0;
7357#endif
a34977ba
ASJ		 7358 pf->num_vmdq_msix = 0;
7359 }
7360
3b444399 7361 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7362 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7363 kfree(pf->msix_entries);
7364 pf->msix_entries = NULL;
7365 return -ENODEV;
7366
3b444399 7367 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7368 /* Adjust for minimal MSIX use */
41c445ff
JB		 7369 pf->num_vmdq_vsis = 0;
7370 pf->num_vmdq_qps = 0;
41c445ff
JB		 7371 pf->num_lan_qps = 1;
7372 pf->num_lan_msix = 1;
7373
3b444399
SN		 7374 } else if (v_actual != v_budget) {
7375 int vec;
7376
a34977ba 7377 /* reserve the misc vector */
3b444399 7378 vec = v_actual - 1;
a34977ba 7379
41c445ff
JB		 7380 /* Scale vector usage down */
7381 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7382 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7383 pf->num_vmdq_qps = 1;
7384 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7385
7386 /* partition out the remaining vectors */
7387 switch (vec) {
7388 case 2:
41c445ff
JB		 7389 pf->num_lan_msix = 1;
7390 break;
7391 case 3:
38e00438
VD		 7392#ifdef I40E_FCOE
7393 /* give one vector to FCoE */
7394 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7395 pf->num_lan_msix = 1;
7396 pf->num_fcoe_msix = 1;
7397 }
7398#else
41c445ff 7399 pf->num_lan_msix = 2;
38e00438 7400#endif
41c445ff
JB		 7401 break;
7402 default:
38e00438
VD		 7403#ifdef I40E_FCOE
7404 /* give one vector to FCoE */
7405 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7406 pf->num_fcoe_msix = 1;
7407 vec--;
7408 }
7409#endif
1e200e4a
SN		 7410 /* give the rest to the PF */
7411 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7412 break;
7413 }
7414 }
7415
a34977ba
ASJ		 7416 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7417 (pf->num_vmdq_msix == 0)) {
7418 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7419 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7420 }
38e00438
VD		 7421#ifdef I40E_FCOE
7422
7423 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7424 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7425 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7426 }
7427#endif
3b444399 7428 return v_actual;
41c445ff
JB		 7429}
7430
493fb300 7431/**
90e04070 7432 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7433 * @vsi: the VSI being configured
7434 * @v_idx: index of the vector in the vsi struct
7435 *
7436 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7437 **/
90e04070 7438static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7439{
7440 struct i40e_q_vector *q_vector;
7441
7442 /* allocate q_vector */
7443 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7444 if (!q_vector)
7445 return -ENOMEM;
7446
7447 q_vector->vsi = vsi;
7448 q_vector->v_idx = v_idx;
7449 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7450 if (vsi->netdev)
7451 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7452 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7453
cd0b6fa6
AD		 7454 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7455 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7456
493fb300
AD		 7457 /* tie q_vector and vsi together */
7458 vsi->q_vectors[v_idx] = q_vector;
7459
7460 return 0;
7461}
7462
41c445ff 7463/**
90e04070 7464 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7465 * @vsi: the VSI being configured
7466 *
7467 * We allocate one q_vector per queue interrupt. If allocation fails we
7468 * return -ENOMEM.
7469 **/
90e04070 7470static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7471{
7472 struct i40e_pf *pf = vsi->back;
7473 int v_idx, num_q_vectors;
493fb300 7474 int err;
41c445ff
JB		 7475
7476 /* if not MSIX, give the one vector only to the LAN VSI */
7477 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7478 num_q_vectors = vsi->num_q_vectors;
7479 else if (vsi == pf->vsi[pf->lan_vsi])
7480 num_q_vectors = 1;
7481 else
7482 return -EINVAL;
7483
41c445ff 7484 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7485 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7486 if (err)
7487 goto err_out;
41c445ff
JB		 7488 }
7489
7490 return 0;
493fb300
AD		 7491
7492err_out:
7493 while (v_idx--)
7494 i40e_free_q_vector(vsi, v_idx);
7495
7496 return err;
41c445ff
JB		 7497}
7498
7499/**
7500 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7501 * @pf: board private structure to initialize
7502 **/
c1147280 7503static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7504{
3b444399
SN		 7505 int vectors = 0;
7506 ssize_t size;
41c445ff
JB		 7507
7508 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7509 vectors = i40e_init_msix(pf);
7510 if (vectors < 0) {
60ea5f83 7511 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7512#ifdef I40E_FCOE
7513 I40E_FLAG_FCOE_ENABLED |
7514#endif
60ea5f83 7515 I40E_FLAG_RSS_ENABLED |
4d9b6043 7516 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7517 I40E_FLAG_SRIOV_ENABLED |
7518 I40E_FLAG_FD_SB_ENABLED |
7519 I40E_FLAG_FD_ATR_ENABLED |
7520 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7521
7522 /* rework the queue expectations without MSIX */
7523 i40e_determine_queue_usage(pf);
7524 }
7525 }
7526
7527 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7528 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7529 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7530 vectors = pci_enable_msi(pf->pdev);
7531 if (vectors < 0) {
7532 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7533 vectors);
41c445ff
JB		 7534 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7535 }
3b444399 7536 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7537 }
7538
958a3e3b 7539 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7540 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7541
3b444399
SN		 7542 /* set up vector assignment tracking */
7543 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7544 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7545 if (!pf->irq_pile) {
7546 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7547 return -ENOMEM;
7548 }
3b444399
SN		 7549 pf->irq_pile->num_entries = vectors;
7550 pf->irq_pile->search_hint = 0;
7551
c1147280 7552 /* track first vector for misc interrupts, ignore return */
3b444399 7553 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7554
7555 return 0;
41c445ff
JB		 7556}
7557
7558/**
7559 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7560 * @pf: board private structure
7561 *
7562 * This sets up the handler for MSIX 0, which is used to manage the
7563 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7564 * when in MSI or Legacy interrupt mode.
7565 **/
7566static int i40e_setup_misc_vector(struct i40e_pf *pf)
7567{
7568 struct i40e_hw *hw = &pf->hw;
7569 int err = 0;
7570
7571 /* Only request the irq if this is the first time through, and
7572 * not when we're rebuilding after a Reset
7573 */
7574 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7575 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7576 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7577 if (err) {
7578 dev_info(&pf->pdev->dev,
77fa28be 7579 "request_irq for %s failed: %d\n",
b294ac70 7580 pf->int_name, err);
41c445ff
JB		 7581 return -EFAULT;
7582 }
7583 }
7584
ab437b5a 7585 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7586
7587 /* associate no queues to the misc vector */
7588 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7589 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7590
7591 i40e_flush(hw);
7592
7593 i40e_irq_dynamic_enable_icr0(pf);
7594
7595 return err;
7596}
7597
7598/**
e25d00b8
ASJ		 7599 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7600 * @vsi: vsi structure
7601 * @seed: RSS hash seed
7602 **/
7603static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed)
7604{
7605 struct i40e_aqc_get_set_rss_key_data rss_key;
7606 struct i40e_pf *pf = vsi->back;
7607 struct i40e_hw *hw = &pf->hw;
7608 bool pf_lut = false;
7609 u8 *rss_lut;
7610 int ret, i;
7611
7612 memset(&rss_key, 0, sizeof(rss_key));
7613 memcpy(&rss_key, seed, sizeof(rss_key));
7614
7615 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7616 if (!rss_lut)
7617 return -ENOMEM;
7618
7619 /* Populate the LUT with max no. of queues in round robin fashion */
7620 for (i = 0; i < vsi->rss_table_size; i++)
7621 rss_lut[i] = i % vsi->rss_size;
7622
7623 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7624 if (ret) {
7625 dev_info(&pf->pdev->dev,
7626 "Cannot set RSS key, err %s aq_err %s\n",
7627 i40e_stat_str(&pf->hw, ret),
7628 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7629 goto config_rss_aq_out;
e25d00b8
ASJ		 7630 }
7631
7632 if (vsi->type == I40E_VSI_MAIN)
7633 pf_lut = true;
7634
7635 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7636 vsi->rss_table_size);
7637 if (ret)
7638 dev_info(&pf->pdev->dev,
7639 "Cannot set RSS lut, err %s aq_err %s\n",
7640 i40e_stat_str(&pf->hw, ret),
7641 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7642
126b63d9
AS		 7643config_rss_aq_out:
7644 kfree(rss_lut);
e25d00b8
ASJ		 7645 return ret;
7646}
7647
7648/**
7649 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7650 * @vsi: VSI structure
7651 **/
7652static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7653{
7654 u8 seed[I40E_HKEY_ARRAY_SIZE];
7655 struct i40e_pf *pf = vsi->back;
7656
7657 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
7658 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7659
7660 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7661 return i40e_config_rss_aq(vsi, seed);
7662
7663 return 0;
7664}
7665
7666/**
7667 * i40e_config_rss_reg - Prepare for RSS if used
41c445ff 7668 * @pf: board private structure
e25d00b8 7669 * @seed: RSS hash seed
41c445ff 7670 **/
e25d00b8 7671static int i40e_config_rss_reg(struct i40e_pf *pf, const u8 *seed)
41c445ff 7672{
66ddcffb 7673 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0 7674 struct i40e_hw *hw = &pf->hw;
e25d00b8
ASJ		 7675 u32 *seed_dw = (u32 *)seed;
7676 u32 current_queue = 0;
4617e8c0
ASJ		 7677 u32 lut = 0;
7678 int i, j;
41c445ff 7679
e25d00b8 7680 /* Fill out hash function seed */
41c445ff 7681 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
e25d00b8
ASJ		 7682 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7683
7684 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) {
7685 lut = 0;
7686 for (j = 0; j < 4; j++) {
7687 if (current_queue == vsi->rss_size)
7688 current_queue = 0;
7689 lut |= ((current_queue) << (8 * j));
7690 current_queue++;
7691 }
7692 wr32(&pf->hw, I40E_PFQF_HLUT(i), lut);
7693 }
7694 i40e_flush(hw);
7695
7696 return 0;
7697}
7698
7699/**
7700 * i40e_config_rss - Prepare for RSS if used
7701 * @pf: board private structure
7702 **/
7703static int i40e_config_rss(struct i40e_pf *pf)
7704{
7705 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7706 u8 seed[I40E_HKEY_ARRAY_SIZE];
7707 struct i40e_hw *hw = &pf->hw;
7708 u32 reg_val;
7709 u64 hena;
7710
7711 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
41c445ff
JB		 7712
7713 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7714 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7715 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 7716 hena |= i40e_pf_get_default_rss_hena(pf);
7717
41c445ff
JB		 7718 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7719 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7720
66ddcffb
ASJ		 7721 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7722
e25d00b8 7723 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 7724 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 7725 reg_val = (pf->rss_table_size == 512) ?
7726 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
7727 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 7728 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7729
e25d00b8
ASJ		 7730 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7731 return i40e_config_rss_aq(pf->vsi[pf->lan_vsi], seed);
7732 else
7733 return i40e_config_rss_reg(pf, seed);
41c445ff
JB		 7734}
7735
f8ff1464
ASJ		 7736/**
7737 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7738 * @pf: board private structure
7739 * @queue_count: the requested queue count for rss.
7740 *
7741 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7742 * count which may be different from the requested queue count.
7743 **/
7744int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7745{
9a3bd2f1
ASJ		 7746 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7747 int new_rss_size;
7748
f8ff1464
ASJ		 7749 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7750 return 0;
7751
9a3bd2f1 7752 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7753
9a3bd2f1
ASJ		 7754 if (queue_count != vsi->num_queue_pairs) {
7755 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7756 i40e_prep_for_reset(pf);
7757
9a3bd2f1 7758 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7759
7760 i40e_reset_and_rebuild(pf, true);
7761 i40e_config_rss(pf);
7762 }
7763 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7764 return pf->rss_size;
7765}
7766
f4492db1
GR		 7767/**
7768 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7769 * @pf: board private structure
7770 **/
7771i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7772{
7773 i40e_status status;
7774 bool min_valid, max_valid;
7775 u32 max_bw, min_bw;
7776
7777 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7778 &min_valid, &max_valid);
7779
7780 if (!status) {
7781 if (min_valid)
7782 pf->npar_min_bw = min_bw;
7783 if (max_valid)
7784 pf->npar_max_bw = max_bw;
7785 }
7786
7787 return status;
7788}
7789
7790/**
7791 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7792 * @pf: board private structure
7793 **/
7794i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7795{
7796 struct i40e_aqc_configure_partition_bw_data bw_data;
7797 i40e_status status;
7798
b40c82e6 7799 /* Set the valid bit for this PF */
41a1d04b 7800 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 7801 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7802 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7803
7804 /* Set the new bandwidths */
7805 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7806
7807 return status;
7808}
7809
7810/**
7811 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7812 * @pf: board private structure
7813 **/
7814i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7815{
7816 /* Commit temporary BW setting to permanent NVM image */
7817 enum i40e_admin_queue_err last_aq_status;
7818 i40e_status ret;
7819 u16 nvm_word;
7820
7821 if (pf->hw.partition_id != 1) {
7822 dev_info(&pf->pdev->dev,
7823 "Commit BW only works on partition 1! This is partition %d",
7824 pf->hw.partition_id);
7825 ret = I40E_NOT_SUPPORTED;
7826 goto bw_commit_out;
7827 }
7828
7829 /* Acquire NVM for read access */
7830 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7831 last_aq_status = pf->hw.aq.asq_last_status;
7832 if (ret) {
7833 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7834 "Cannot acquire NVM for read access, err %s aq_err %s\n",
7835 i40e_stat_str(&pf->hw, ret),
7836 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7837 goto bw_commit_out;
7838 }
7839
7840 /* Read word 0x10 of NVM - SW compatibility word 1 */
7841 ret = i40e_aq_read_nvm(&pf->hw,
7842 I40E_SR_NVM_CONTROL_WORD,
7843 0x10, sizeof(nvm_word), &nvm_word,
7844 false, NULL);
7845 /* Save off last admin queue command status before releasing
7846 * the NVM
7847 */
7848 last_aq_status = pf->hw.aq.asq_last_status;
7849 i40e_release_nvm(&pf->hw);
7850 if (ret) {
f1c7e72e
SN		 7851 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
7852 i40e_stat_str(&pf->hw, ret),
7853 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7854 goto bw_commit_out;
7855 }
7856
7857 /* Wait a bit for NVM release to complete */
7858 msleep(50);
7859
7860 /* Acquire NVM for write access */
7861 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7862 last_aq_status = pf->hw.aq.asq_last_status;
7863 if (ret) {
7864 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7865 "Cannot acquire NVM for write access, err %s aq_err %s\n",
7866 i40e_stat_str(&pf->hw, ret),
7867 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7868 goto bw_commit_out;
7869 }
7870 /* Write it back out unchanged to initiate update NVM,
7871 * which will force a write of the shadow (alt) RAM to
7872 * the NVM - thus storing the bandwidth values permanently.
7873 */
7874 ret = i40e_aq_update_nvm(&pf->hw,
7875 I40E_SR_NVM_CONTROL_WORD,
7876 0x10, sizeof(nvm_word),
7877 &nvm_word, true, NULL);
7878 /* Save off last admin queue command status before releasing
7879 * the NVM
7880 */
7881 last_aq_status = pf->hw.aq.asq_last_status;
7882 i40e_release_nvm(&pf->hw);
7883 if (ret)
7884 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7885 "BW settings NOT SAVED, err %s aq_err %s\n",
7886 i40e_stat_str(&pf->hw, ret),
7887 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7888bw_commit_out:
7889
7890 return ret;
7891}
7892
41c445ff
JB		 7893/**
7894 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7895 * @pf: board private structure to initialize
7896 *
7897 * i40e_sw_init initializes the Adapter private data structure.
7898 * Fields are initialized based on PCI device information and
7899 * OS network device settings (MTU size).
7900 **/
7901static int i40e_sw_init(struct i40e_pf *pf)
7902{
7903 int err = 0;
7904 int size;
7905
7906 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7907 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7908 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7909 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7910 if (I40E_DEBUG_USER & debug)
7911 pf->hw.debug_mask = debug;
7912 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7913 I40E_DEFAULT_MSG_ENABLE);
7914 }
7915
7916 /* Set default capability flags */
7917 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7918 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 7919 I40E_FLAG_MSIX_ENABLED;
7920
7921 if (iommu_present(&pci_bus_type))
7922 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7923 else
7924 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7925
ca99eb99
MW		 7926 /* Set default ITR */
7927 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7928 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7929
7134f9ce
JB		 7930 /* Depending on PF configurations, it is possible that the RSS
7931 * maximum might end up larger than the available queues
7932 */
41a1d04b 7933 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
ec9a7db7 7934 pf->rss_size = 1;
5db4cb59 7935 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7936 pf->rss_size_max = min_t(int, pf->rss_size_max,
7937 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7938 if (pf->hw.func_caps.rss) {
7939 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7940 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7941 }
7942
2050bc65 7943 /* MFP mode enabled */
c78b953e 7944 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 7945 pf->flags |= I40E_FLAG_MFP_ENABLED;
7946 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7947 if (i40e_get_npar_bw_setting(pf))
7948 dev_warn(&pf->pdev->dev,
7949 "Could not get NPAR bw settings\n");
7950 else
7951 dev_info(&pf->pdev->dev,
7952 "Min BW = %8.8x, Max BW = %8.8x\n",
7953 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7954 }
7955
cbf61325
ASJ		 7956 /* FW/NVM is not yet fixed in this regard */
7957 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7958 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7959 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7960 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 7961 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7962 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 7963 } else {
7964 dev_info(&pf->pdev->dev,
0b67584f 7965 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7966 }
cbf61325
ASJ		 7967 pf->fdir_pf_filter_count =
7968 pf->hw.func_caps.fd_filters_guaranteed;
7969 pf->hw.fdir_shared_filter_count =
7970 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7971 }
7972
7973 if (pf->hw.func_caps.vmdq) {
41c445ff 7974 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 7975 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
41c445ff
JB		 7976 }
7977
38e00438
VD		 7978#ifdef I40E_FCOE
7979 err = i40e_init_pf_fcoe(pf);
7980 if (err)
7981 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7982
7983#endif /* I40E_FCOE */
41c445ff 7984#ifdef CONFIG_PCI_IOV
ba252f13 7985 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7986 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7987 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7988 pf->num_req_vfs = min_t(int,
7989 pf->hw.func_caps.num_vfs,
7990 I40E_MAX_VF_COUNT);
7991 }
7992#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 7993 if (pf->hw.mac.type == I40E_MAC_X722) {
7994 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
7995 I40E_FLAG_128_QP_RSS_CAPABLE |
7996 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
7997 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
7998 I40E_FLAG_WB_ON_ITR_CAPABLE |
7999 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
8000 }
41c445ff
JB		 8001 pf->eeprom_version = 0xDEAD;
8002 pf->lan_veb = I40E_NO_VEB;
8003 pf->lan_vsi = I40E_NO_VSI;
8004
d1a8d275
ASJ		 8005 /* By default FW has this off for performance reasons */
8006 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8007
41c445ff
JB		 8008 /* set up queue assignment tracking */
8009 size = sizeof(struct i40e_lump_tracking)
8010 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8011 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8012 if (!pf->qp_pile) {
8013 err = -ENOMEM;
8014 goto sw_init_done;
8015 }
8016 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8017 pf->qp_pile->search_hint = 0;
8018
327fe04b
ASJ		 8019 pf->tx_timeout_recovery_level = 1;
8020
41c445ff
JB		 8021 mutex_init(&pf->switch_mutex);
8022
c668a12c
GR		 8023 /* If NPAR is enabled nudge the Tx scheduler */
8024 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8025 i40e_set_npar_bw_setting(pf);
8026
41c445ff
JB		 8027sw_init_done:
8028 return err;
8029}
8030
7c3c288b
ASJ		 8031/**
8032 * i40e_set_ntuple - set the ntuple feature flag and take action
8033 * @pf: board private structure to initialize
8034 * @features: the feature set that the stack is suggesting
8035 *
8036 * returns a bool to indicate if reset needs to happen
8037 **/
8038bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8039{
8040 bool need_reset = false;
8041
8042 /* Check if Flow Director n-tuple support was enabled or disabled. If
8043 * the state changed, we need to reset.
8044 */
8045 if (features & NETIF_F_NTUPLE) {
8046 /* Enable filters and mark for reset */
8047 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8048 need_reset = true;
8049 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8050 } else {
8051 /* turn off filters, mark for reset and clear SW filter list */
8052 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8053 need_reset = true;
8054 i40e_fdir_filter_exit(pf);
8055 }
8056 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8057 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8058 /* reset fd counters */
8059 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8060 pf->fdir_pf_active_filters = 0;
8061 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8062 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8063 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8064 /* if ATR was auto disabled it can be re-enabled. */
8065 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8066 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8067 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8068 }
8069 return need_reset;
8070}
8071
41c445ff
JB		 8072/**
8073 * i40e_set_features - set the netdev feature flags
8074 * @netdev: ptr to the netdev being adjusted
8075 * @features: the feature set that the stack is suggesting
8076 **/
8077static int i40e_set_features(struct net_device *netdev,
8078 netdev_features_t features)
8079{
8080 struct i40e_netdev_priv *np = netdev_priv(netdev);
8081 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8082 struct i40e_pf *pf = vsi->back;
8083 bool need_reset;
41c445ff
JB		 8084
8085 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8086 i40e_vlan_stripping_enable(vsi);
8087 else
8088 i40e_vlan_stripping_disable(vsi);
8089
7c3c288b
ASJ		 8090 need_reset = i40e_set_ntuple(pf, features);
8091
8092 if (need_reset)
41a1d04b 8093 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8094
41c445ff
JB		 8095 return 0;
8096}
8097
a1c9a9d9
JK		 8098#ifdef CONFIG_I40E_VXLAN
8099/**
8100 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8101 * @pf: board private structure
8102 * @port: The UDP port to look up
8103 *
8104 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8105 **/
8106static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8107{
8108 u8 i;
8109
8110 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8111 if (pf->vxlan_ports[i] == port)
8112 return i;
8113 }
8114
8115 return i;
8116}
8117
8118/**
8119 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8120 * @netdev: This physical port's netdev
8121 * @sa_family: Socket Family that VXLAN is notifying us about
8122 * @port: New UDP port number that VXLAN started listening to
8123 **/
8124static void i40e_add_vxlan_port(struct net_device *netdev,
8125 sa_family_t sa_family, __be16 port)
8126{
8127 struct i40e_netdev_priv *np = netdev_priv(netdev);
8128 struct i40e_vsi *vsi = np->vsi;
8129 struct i40e_pf *pf = vsi->back;
8130 u8 next_idx;
8131 u8 idx;
8132
8133 if (sa_family == AF_INET6)
8134 return;
8135
8136 idx = i40e_get_vxlan_port_idx(pf, port);
8137
8138 /* Check if port already exists */
8139 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8140 netdev_info(netdev, "vxlan port %d already offloaded\n",
8141 ntohs(port));
a1c9a9d9
JK		 8142 return;
8143 }
8144
8145 /* Now check if there is space to add the new port */
8146 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8147
8148 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8149 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8150 ntohs(port));
8151 return;
8152 }
8153
8154 /* New port: add it and mark its index in the bitmap */
8155 pf->vxlan_ports[next_idx] = port;
41a1d04b 8156 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8157 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8158}
8159
8160/**
8161 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8162 * @netdev: This physical port's netdev
8163 * @sa_family: Socket Family that VXLAN is notifying us about
8164 * @port: UDP port number that VXLAN stopped listening to
8165 **/
8166static void i40e_del_vxlan_port(struct net_device *netdev,
8167 sa_family_t sa_family, __be16 port)
8168{
8169 struct i40e_netdev_priv *np = netdev_priv(netdev);
8170 struct i40e_vsi *vsi = np->vsi;
8171 struct i40e_pf *pf = vsi->back;
8172 u8 idx;
8173
8174 if (sa_family == AF_INET6)
8175 return;
8176
8177 idx = i40e_get_vxlan_port_idx(pf, port);
8178
8179 /* Check if port already exists */
8180 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8181 /* if port exists, set it to 0 (mark for deletion)
8182 * and make it pending
8183 */
8184 pf->vxlan_ports[idx] = 0;
41a1d04b 8185 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8186 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8187 } else {
c22c06c8 8188 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8189 ntohs(port));
8190 }
8191}
8192
8193#endif
1f224ad2 8194static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8195 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8196{
8197 struct i40e_netdev_priv *np = netdev_priv(netdev);
8198 struct i40e_pf *pf = np->vsi->back;
8199 struct i40e_hw *hw = &pf->hw;
8200
8201 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8202 return -EOPNOTSUPP;
8203
8204 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8205 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8206
8207 return 0;
8208}
8209
2f90ade6
JB		 8210/**
8211 * i40e_ndo_fdb_add - add an entry to the hardware database
8212 * @ndm: the input from the stack
8213 * @tb: pointer to array of nladdr (unused)
8214 * @dev: the net device pointer
8215 * @addr: the MAC address entry being added
8216 * @flags: instructions from stack about fdb operation
8217 */
4ba0dea5
GR		 8218static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8219 struct net_device *dev,
f6f6424b 8220 const unsigned char *addr, u16 vid,
4ba0dea5 8221 u16 flags)
4ba0dea5
GR		 8222{
8223 struct i40e_netdev_priv *np = netdev_priv(dev);
8224 struct i40e_pf *pf = np->vsi->back;
8225 int err = 0;
8226
8227 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8228 return -EOPNOTSUPP;
8229
65891fea
OG		 8230 if (vid) {
8231 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8232 return -EINVAL;
8233 }
8234
4ba0dea5
GR		 8235 /* Hardware does not support aging addresses so if a
8236 * ndm_state is given only allow permanent addresses
8237 */
8238 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8239 netdev_info(dev, "FDB only supports static addresses\n");
8240 return -EINVAL;
8241 }
8242
8243 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8244 err = dev_uc_add_excl(dev, addr);
8245 else if (is_multicast_ether_addr(addr))
8246 err = dev_mc_add_excl(dev, addr);
8247 else
8248 err = -EINVAL;
8249
8250 /* Only return duplicate errors if NLM_F_EXCL is set */
8251 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8252 err = 0;
8253
8254 return err;
8255}
8256
51616018
NP		 8257/**
8258 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8259 * @dev: the netdev being configured
8260 * @nlh: RTNL message
8261 *
8262 * Inserts a new hardware bridge if not already created and
8263 * enables the bridging mode requested (VEB or VEPA). If the
8264 * hardware bridge has already been inserted and the request
8265 * is to change the mode then that requires a PF reset to
8266 * allow rebuild of the components with required hardware
8267 * bridge mode enabled.
8268 **/
8269static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8270 struct nlmsghdr *nlh,
8271 u16 flags)
51616018
NP		 8272{
8273 struct i40e_netdev_priv *np = netdev_priv(dev);
8274 struct i40e_vsi *vsi = np->vsi;
8275 struct i40e_pf *pf = vsi->back;
8276 struct i40e_veb *veb = NULL;
8277 struct nlattr *attr, *br_spec;
8278 int i, rem;
8279
8280 /* Only for PF VSI for now */
8281 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8282 return -EOPNOTSUPP;
8283
8284 /* Find the HW bridge for PF VSI */
8285 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8286 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8287 veb = pf->veb[i];
8288 }
8289
8290 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8291
8292 nla_for_each_nested(attr, br_spec, rem) {
8293 __u16 mode;
8294
8295 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8296 continue;
8297
8298 mode = nla_get_u16(attr);
8299 if ((mode != BRIDGE_MODE_VEPA) &&
8300 (mode != BRIDGE_MODE_VEB))
8301 return -EINVAL;
8302
8303 /* Insert a new HW bridge */
8304 if (!veb) {
8305 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8306 vsi->tc_config.enabled_tc);
8307 if (veb) {
8308 veb->bridge_mode = mode;
8309 i40e_config_bridge_mode(veb);
8310 } else {
8311 /* No Bridge HW offload available */
8312 return -ENOENT;
8313 }
8314 break;
8315 } else if (mode != veb->bridge_mode) {
8316 /* Existing HW bridge but different mode needs reset */
8317 veb->bridge_mode = mode;
fc60861e
ASJ		 8318 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8319 if (mode == BRIDGE_MODE_VEB)
8320 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8321 else
8322 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8323 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8324 break;
8325 }
8326 }
8327
8328 return 0;
8329}
8330
8331/**
8332 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8333 * @skb: skb buff
8334 * @pid: process id
8335 * @seq: RTNL message seq #
8336 * @dev: the netdev being configured
8337 * @filter_mask: unused
8338 *
8339 * Return the mode in which the hardware bridge is operating in
8340 * i.e VEB or VEPA.
8341 **/
51616018
NP		 8342static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8343 struct net_device *dev,
7d4f8d87 8344 u32 filter_mask, int nlflags)
51616018
NP		 8345{
8346 struct i40e_netdev_priv *np = netdev_priv(dev);
8347 struct i40e_vsi *vsi = np->vsi;
8348 struct i40e_pf *pf = vsi->back;
8349 struct i40e_veb *veb = NULL;
8350 int i;
8351
8352 /* Only for PF VSI for now */
8353 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8354 return -EOPNOTSUPP;
8355
8356 /* Find the HW bridge for the PF VSI */
8357 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8358 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8359 veb = pf->veb[i];
8360 }
8361
8362 if (!veb)
8363 return 0;
8364
46c264da 8365 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8366 nlflags, 0, 0, filter_mask, NULL);
51616018 8367}
51616018 8368
f44a75e2
JS		 8369#define I40E_MAX_TUNNEL_HDR_LEN 80
8370/**
8371 * i40e_features_check - Validate encapsulated packet conforms to limits
8372 * @skb: skb buff
8373 * @netdev: This physical port's netdev
8374 * @features: Offload features that the stack believes apply
8375 **/
8376static netdev_features_t i40e_features_check(struct sk_buff *skb,
8377 struct net_device *dev,
8378 netdev_features_t features)
8379{
8380 if (skb->encapsulation &&
8381 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8382 I40E_MAX_TUNNEL_HDR_LEN))
8383 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8384
8385 return features;
8386}
8387
37a2973a 8388static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8389 .ndo_open = i40e_open,
8390 .ndo_stop = i40e_close,
8391 .ndo_start_xmit = i40e_lan_xmit_frame,
8392 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8393 .ndo_set_rx_mode = i40e_set_rx_mode,
8394 .ndo_validate_addr = eth_validate_addr,
8395 .ndo_set_mac_address = i40e_set_mac,
8396 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8397 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8398 .ndo_tx_timeout = i40e_tx_timeout,
8399 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8400 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8401#ifdef CONFIG_NET_POLL_CONTROLLER
8402 .ndo_poll_controller = i40e_netpoll,
8403#endif
8404 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8405#ifdef I40E_FCOE
8406 .ndo_fcoe_enable = i40e_fcoe_enable,
8407 .ndo_fcoe_disable = i40e_fcoe_disable,
8408#endif
41c445ff
JB		 8409 .ndo_set_features = i40e_set_features,
8410 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8411 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8412 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8413 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8414 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8415 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8416#ifdef CONFIG_I40E_VXLAN
8417 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8418 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8419#endif
1f224ad2 8420 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8421 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8422 .ndo_features_check = i40e_features_check,
51616018
NP		 8423 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8424 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8425};
8426
8427/**
8428 * i40e_config_netdev - Setup the netdev flags
8429 * @vsi: the VSI being configured
8430 *
8431 * Returns 0 on success, negative value on failure
8432 **/
8433static int i40e_config_netdev(struct i40e_vsi *vsi)
8434{
1a10370a 8435 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8436 struct i40e_pf *pf = vsi->back;
8437 struct i40e_hw *hw = &pf->hw;
8438 struct i40e_netdev_priv *np;
8439 struct net_device *netdev;
8440 u8 mac_addr[ETH_ALEN];
8441 int etherdev_size;
8442
8443 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8444 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8445 if (!netdev)
8446 return -ENOMEM;
8447
8448 vsi->netdev = netdev;
8449 np = netdev_priv(netdev);
8450 np->vsi = vsi;
8451
d70e941b 8452 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8453 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 8454 NETIF_F_TSO;
41c445ff
JB		 8455
8456 netdev->features = NETIF_F_SG |
8457 NETIF_F_IP_CSUM |
8458 NETIF_F_SCTP_CSUM |
8459 NETIF_F_HIGHDMA |
8460 NETIF_F_GSO_UDP_TUNNEL |
8461 NETIF_F_HW_VLAN_CTAG_TX |
8462 NETIF_F_HW_VLAN_CTAG_RX |
8463 NETIF_F_HW_VLAN_CTAG_FILTER |
8464 NETIF_F_IPV6_CSUM |
8465 NETIF_F_TSO |
059dab69 8466 NETIF_F_TSO_ECN |
41c445ff
JB		 8467 NETIF_F_TSO6 |
8468 NETIF_F_RXCSUM |
8469 NETIF_F_RXHASH |
8470 0;
8471
2e86a0b6
ASJ		 8472 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8473 netdev->features |= NETIF_F_NTUPLE;
8474
41c445ff
JB		 8475 /* copy netdev features into list of user selectable features */
8476 netdev->hw_features |= netdev->features;
8477
8478 if (vsi->type == I40E_VSI_MAIN) {
8479 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8480 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8481 /* The following steps are necessary to prevent reception
8482 * of tagged packets - some older NVM configurations load a
8483 * default a MAC-VLAN filter that accepts any tagged packet
8484 * which must be replaced by a normal filter.
8c27d42e 8485 */
30650cc5
SN		 8486 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8487 i40e_add_filter(vsi, mac_addr,
8488 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8489 } else {
8490 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8491 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8492 pf->vsi[pf->lan_vsi]->netdev->name);
8493 random_ether_addr(mac_addr);
8494 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8495 }
1a10370a 8496 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8497
9a173901
GR		 8498 ether_addr_copy(netdev->dev_addr, mac_addr);
8499 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8500 /* vlan gets same features (except vlan offload)
8501 * after any tweaks for specific VSI types
8502 */
8503 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8504 NETIF_F_HW_VLAN_CTAG_RX |
8505 NETIF_F_HW_VLAN_CTAG_FILTER);
8506 netdev->priv_flags |= IFF_UNICAST_FLT;
8507 netdev->priv_flags |= IFF_SUPP_NOFCS;
8508 /* Setup netdev TC information */
8509 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8510
8511 netdev->netdev_ops = &i40e_netdev_ops;
8512 netdev->watchdog_timeo = 5 * HZ;
8513 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8514#ifdef I40E_FCOE
8515 i40e_fcoe_config_netdev(netdev, vsi);
8516#endif
41c445ff
JB		 8517
8518 return 0;
8519}
8520
8521/**
8522 * i40e_vsi_delete - Delete a VSI from the switch
8523 * @vsi: the VSI being removed
8524 *
8525 * Returns 0 on success, negative value on failure
8526 **/
8527static void i40e_vsi_delete(struct i40e_vsi *vsi)
8528{
8529 /* remove default VSI is not allowed */
8530 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8531 return;
8532
41c445ff 8533 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8534}
8535
51616018
NP		 8536/**
8537 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8538 * @vsi: the VSI being queried
8539 *
8540 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8541 **/
8542int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8543{
8544 struct i40e_veb *veb;
8545 struct i40e_pf *pf = vsi->back;
8546
8547 /* Uplink is not a bridge so default to VEB */
8548 if (vsi->veb_idx == I40E_NO_VEB)
8549 return 1;
8550
8551 veb = pf->veb[vsi->veb_idx];
8552 /* Uplink is a bridge in VEPA mode */
8553 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8554 return 0;
8555
8556 /* Uplink is a bridge in VEB mode */
8557 return 1;
8558}
8559
41c445ff
JB		 8560/**
8561 * i40e_add_vsi - Add a VSI to the switch
8562 * @vsi: the VSI being configured
8563 *
8564 * This initializes a VSI context depending on the VSI type to be added and
8565 * passes it down to the add_vsi aq command.
8566 **/
8567static int i40e_add_vsi(struct i40e_vsi *vsi)
8568{
8569 int ret = -ENODEV;
8570 struct i40e_mac_filter *f, *ftmp;
8571 struct i40e_pf *pf = vsi->back;
8572 struct i40e_hw *hw = &pf->hw;
8573 struct i40e_vsi_context ctxt;
8574 u8 enabled_tc = 0x1; /* TC0 enabled */
8575 int f_count = 0;
8576
8577 memset(&ctxt, 0, sizeof(ctxt));
8578 switch (vsi->type) {
8579 case I40E_VSI_MAIN:
8580 /* The PF's main VSI is already setup as part of the
8581 * device initialization, so we'll not bother with
8582 * the add_vsi call, but we will retrieve the current
8583 * VSI context.
8584 */
8585 ctxt.seid = pf->main_vsi_seid;
8586 ctxt.pf_num = pf->hw.pf_id;
8587 ctxt.vf_num = 0;
8588 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8589 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8590 if (ret) {
8591 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8592 "couldn't get PF vsi config, err %s aq_err %s\n",
8593 i40e_stat_str(&pf->hw, ret),
8594 i40e_aq_str(&pf->hw,
8595 pf->hw.aq.asq_last_status));
41c445ff
JB		 8596 return -ENOENT;
8597 }
1a2f6248 8598 vsi->info = ctxt.info;
41c445ff
JB		 8599 vsi->info.valid_sections = 0;
8600
8601 vsi->seid = ctxt.seid;
8602 vsi->id = ctxt.vsi_number;
8603
8604 enabled_tc = i40e_pf_get_tc_map(pf);
8605
8606 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8607 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8608 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8609 memset(&ctxt, 0, sizeof(ctxt));
8610 ctxt.seid = pf->main_vsi_seid;
8611 ctxt.pf_num = pf->hw.pf_id;
8612 ctxt.vf_num = 0;
8613 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8614 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8615 if (ret) {
8616 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8617 "update vsi failed, err %s aq_err %s\n",
8618 i40e_stat_str(&pf->hw, ret),
8619 i40e_aq_str(&pf->hw,
8620 pf->hw.aq.asq_last_status));
41c445ff
JB		 8621 ret = -ENOENT;
8622 goto err;
8623 }
8624 /* update the local VSI info queue map */
8625 i40e_vsi_update_queue_map(vsi, &ctxt);
8626 vsi->info.valid_sections = 0;
8627 } else {
8628 /* Default/Main VSI is only enabled for TC0
8629 * reconfigure it to enable all TCs that are
8630 * available on the port in SFP mode.
63d7e5a4
NP		 8631 * For MFP case the iSCSI PF would use this
8632 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8633 */
8634 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8635 if (ret) {
8636 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8637 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
8638 enabled_tc,
8639 i40e_stat_str(&pf->hw, ret),
8640 i40e_aq_str(&pf->hw,
8641 pf->hw.aq.asq_last_status));
41c445ff
JB		 8642 ret = -ENOENT;
8643 }
8644 }
8645 break;
8646
8647 case I40E_VSI_FDIR:
cbf61325
ASJ		 8648 ctxt.pf_num = hw->pf_id;
8649 ctxt.vf_num = 0;
8650 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8651 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8652 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 8653 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
8654 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 8655 ctxt.info.valid_sections |=
fc60861e 8656 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8657 ctxt.info.switch_id =
fc60861e 8658 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8659 }
41c445ff 8660 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8661 break;
8662
8663 case I40E_VSI_VMDQ2:
8664 ctxt.pf_num = hw->pf_id;
8665 ctxt.vf_num = 0;
8666 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8667 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8668 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8669
41c445ff
JB		 8670 /* This VSI is connected to VEB so the switch_id
8671 * should be set to zero by default.
8672 */
51616018
NP		 8673 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8674 ctxt.info.valid_sections |=
8675 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8676 ctxt.info.switch_id =
8677 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8678 }
41c445ff
JB		 8679
8680 /* Setup the VSI tx/rx queue map for TC0 only for now */
8681 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8682 break;
8683
8684 case I40E_VSI_SRIOV:
8685 ctxt.pf_num = hw->pf_id;
8686 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8687 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8688 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8689 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8690
41c445ff
JB		 8691 /* This VSI is connected to VEB so the switch_id
8692 * should be set to zero by default.
8693 */
51616018
NP		 8694 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8695 ctxt.info.valid_sections |=
8696 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8697 ctxt.info.switch_id =
8698 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8699 }
41c445ff
JB		 8700
8701 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8702 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8703 if (pf->vf[vsi->vf_id].spoofchk) {
8704 ctxt.info.valid_sections |=
8705 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8706 ctxt.info.sec_flags |=
8707 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8708 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8709 }
41c445ff
JB		 8710 /* Setup the VSI tx/rx queue map for TC0 only for now */
8711 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8712 break;
8713
38e00438
VD		 8714#ifdef I40E_FCOE
8715 case I40E_VSI_FCOE:
8716 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8717 if (ret) {
8718 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8719 return ret;
8720 }
8721 break;
8722
8723#endif /* I40E_FCOE */
41c445ff
JB		 8724 default:
8725 return -ENODEV;
8726 }
8727
8728 if (vsi->type != I40E_VSI_MAIN) {
8729 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8730 if (ret) {
8731 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 8732 "add vsi failed, err %s aq_err %s\n",
8733 i40e_stat_str(&pf->hw, ret),
8734 i40e_aq_str(&pf->hw,
8735 pf->hw.aq.asq_last_status));
41c445ff
JB		 8736 ret = -ENOENT;
8737 goto err;
8738 }
1a2f6248 8739 vsi->info = ctxt.info;
41c445ff
JB		 8740 vsi->info.valid_sections = 0;
8741 vsi->seid = ctxt.seid;
8742 vsi->id = ctxt.vsi_number;
8743 }
8744
8745 /* If macvlan filters already exist, force them to get loaded */
8746 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8747 f->changed = true;
8748 f_count++;
6252c7e4
SN		 8749
8750 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8751 struct i40e_aqc_remove_macvlan_element_data element;
8752
8753 memset(&element, 0, sizeof(element));
8754 ether_addr_copy(element.mac_addr, f->macaddr);
8755 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8756 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8757 &element, 1, NULL);
8758 if (ret) {
8759 /* some older FW has a different default */
8760 element.flags |=
8761 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8762 i40e_aq_remove_macvlan(hw, vsi->seid,
8763 &element, 1, NULL);
8764 }
8765
8766 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8767 I40E_AQC_WRITE_TYPE_LAA_WOL,
8768 f->macaddr, NULL);
8769 }
41c445ff
JB		 8770 }
8771 if (f_count) {
8772 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8773 pf->flags |= I40E_FLAG_FILTER_SYNC;
8774 }
8775
8776 /* Update VSI BW information */
8777 ret = i40e_vsi_get_bw_info(vsi);
8778 if (ret) {
8779 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8780 "couldn't get vsi bw info, err %s aq_err %s\n",
8781 i40e_stat_str(&pf->hw, ret),
8782 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 8783 /* VSI is already added so not tearing that up */
8784 ret = 0;
8785 }
8786
8787err:
8788 return ret;
8789}
8790
8791/**
8792 * i40e_vsi_release - Delete a VSI and free its resources
8793 * @vsi: the VSI being removed
8794 *
8795 * Returns 0 on success or < 0 on error
8796 **/
8797int i40e_vsi_release(struct i40e_vsi *vsi)
8798{
8799 struct i40e_mac_filter *f, *ftmp;
8800 struct i40e_veb *veb = NULL;
8801 struct i40e_pf *pf;
8802 u16 uplink_seid;
8803 int i, n;
8804
8805 pf = vsi->back;
8806
8807 /* release of a VEB-owner or last VSI is not allowed */
8808 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8809 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8810 vsi->seid, vsi->uplink_seid);
8811 return -ENODEV;
8812 }
8813 if (vsi == pf->vsi[pf->lan_vsi] &&
8814 !test_bit(__I40E_DOWN, &pf->state)) {
8815 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8816 return -ENODEV;
8817 }
8818
8819 uplink_seid = vsi->uplink_seid;
8820 if (vsi->type != I40E_VSI_SRIOV) {
8821 if (vsi->netdev_registered) {
8822 vsi->netdev_registered = false;
8823 if (vsi->netdev) {
8824 /* results in a call to i40e_close() */
8825 unregister_netdev(vsi->netdev);
41c445ff
JB		 8826 }
8827 } else {
90ef8d47 8828 i40e_vsi_close(vsi);
41c445ff
JB		 8829 }
8830 i40e_vsi_disable_irq(vsi);
8831 }
8832
8833 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8834 i40e_del_filter(vsi, f->macaddr, f->vlan,
8835 f->is_vf, f->is_netdev);
30e2561b 8836 i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 8837
8838 i40e_vsi_delete(vsi);
8839 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8840 if (vsi->netdev) {
8841 free_netdev(vsi->netdev);
8842 vsi->netdev = NULL;
8843 }
41c445ff
JB		 8844 i40e_vsi_clear_rings(vsi);
8845 i40e_vsi_clear(vsi);
8846
8847 /* If this was the last thing on the VEB, except for the
8848 * controlling VSI, remove the VEB, which puts the controlling
8849 * VSI onto the next level down in the switch.
8850 *
8851 * Well, okay, there's one more exception here: don't remove
8852 * the orphan VEBs yet. We'll wait for an explicit remove request
8853 * from up the network stack.
8854 */
505682cd 8855 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8856 if (pf->vsi[i] &&
8857 pf->vsi[i]->uplink_seid == uplink_seid &&
8858 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8859 n++; /* count the VSIs */
8860 }
8861 }
8862 for (i = 0; i < I40E_MAX_VEB; i++) {
8863 if (!pf->veb[i])
8864 continue;
8865 if (pf->veb[i]->uplink_seid == uplink_seid)
8866 n++; /* count the VEBs */
8867 if (pf->veb[i]->seid == uplink_seid)
8868 veb = pf->veb[i];
8869 }
8870 if (n == 0 && veb && veb->uplink_seid != 0)
8871 i40e_veb_release(veb);
8872
8873 return 0;
8874}
8875
8876/**
8877 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8878 * @vsi: ptr to the VSI
8879 *
8880 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8881 * corresponding SW VSI structure and initializes num_queue_pairs for the
8882 * newly allocated VSI.
8883 *
8884 * Returns 0 on success or negative on failure
8885 **/
8886static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8887{
8888 int ret = -ENOENT;
8889 struct i40e_pf *pf = vsi->back;
8890
493fb300 8891 if (vsi->q_vectors[0]) {
41c445ff
JB		 8892 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8893 vsi->seid);
8894 return -EEXIST;
8895 }
8896
8897 if (vsi->base_vector) {
f29eaa3d 8898 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8899 vsi->seid, vsi->base_vector);
8900 return -EEXIST;
8901 }
8902
90e04070 8903 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8904 if (ret) {
8905 dev_info(&pf->pdev->dev,
8906 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8907 vsi->num_q_vectors, vsi->seid, ret);
8908 vsi->num_q_vectors = 0;
8909 goto vector_setup_out;
8910 }
8911
26cdc443
ASJ		 8912 /* In Legacy mode, we do not have to get any other vector since we
8913 * piggyback on the misc/ICR0 for queue interrupts.
8914 */
8915 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
8916 return ret;
958a3e3b
SN		 8917 if (vsi->num_q_vectors)
8918 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8919 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8920 if (vsi->base_vector < 0) {
8921 dev_info(&pf->pdev->dev,
049a2be8
SN		 8922 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8923 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8924 i40e_vsi_free_q_vectors(vsi);
8925 ret = -ENOENT;
8926 goto vector_setup_out;
8927 }
8928
8929vector_setup_out:
8930 return ret;
8931}
8932
bc7d338f
ASJ		 8933/**
8934 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8935 * @vsi: pointer to the vsi.
8936 *
8937 * This re-allocates a vsi's queue resources.
8938 *
8939 * Returns pointer to the successfully allocated and configured VSI sw struct
8940 * on success, otherwise returns NULL on failure.
8941 **/
8942static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8943{
8944 struct i40e_pf *pf = vsi->back;
8945 u8 enabled_tc;
8946 int ret;
8947
8948 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8949 i40e_vsi_clear_rings(vsi);
8950
8951 i40e_vsi_free_arrays(vsi, false);
8952 i40e_set_num_rings_in_vsi(vsi);
8953 ret = i40e_vsi_alloc_arrays(vsi, false);
8954 if (ret)
8955 goto err_vsi;
8956
8957 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8958 if (ret < 0) {
049a2be8 8959 dev_info(&pf->pdev->dev,
f1c7e72e 8960 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 8961 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8962 goto err_vsi;
8963 }
8964 vsi->base_queue = ret;
8965
8966 /* Update the FW view of the VSI. Force a reset of TC and queue
8967 * layout configurations.
8968 */
8969 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8970 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8971 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8972 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8973
8974 /* assign it some queues */
8975 ret = i40e_alloc_rings(vsi);
8976 if (ret)
8977 goto err_rings;
8978
8979 /* map all of the rings to the q_vectors */
8980 i40e_vsi_map_rings_to_vectors(vsi);
8981 return vsi;
8982
8983err_rings:
8984 i40e_vsi_free_q_vectors(vsi);
8985 if (vsi->netdev_registered) {
8986 vsi->netdev_registered = false;
8987 unregister_netdev(vsi->netdev);
8988 free_netdev(vsi->netdev);
8989 vsi->netdev = NULL;
8990 }
8991 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8992err_vsi:
8993 i40e_vsi_clear(vsi);
8994 return NULL;
8995}
8996
41c445ff
JB		 8997/**
8998 * i40e_vsi_setup - Set up a VSI by a given type
8999 * @pf: board private structure
9000 * @type: VSI type
9001 * @uplink_seid: the switch element to link to
9002 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9003 *
9004 * This allocates the sw VSI structure and its queue resources, then add a VSI
9005 * to the identified VEB.
9006 *
9007 * Returns pointer to the successfully allocated and configure VSI sw struct on
9008 * success, otherwise returns NULL on failure.
9009 **/
9010struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9011 u16 uplink_seid, u32 param1)
9012{
9013 struct i40e_vsi *vsi = NULL;
9014 struct i40e_veb *veb = NULL;
9015 int ret, i;
9016 int v_idx;
9017
9018 /* The requested uplink_seid must be either
9019 * - the PF's port seid
9020 * no VEB is needed because this is the PF
9021 * or this is a Flow Director special case VSI
9022 * - seid of an existing VEB
9023 * - seid of a VSI that owns an existing VEB
9024 * - seid of a VSI that doesn't own a VEB
9025 * a new VEB is created and the VSI becomes the owner
9026 * - seid of the PF VSI, which is what creates the first VEB
9027 * this is a special case of the previous
9028 *
9029 * Find which uplink_seid we were given and create a new VEB if needed
9030 */
9031 for (i = 0; i < I40E_MAX_VEB; i++) {
9032 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9033 veb = pf->veb[i];
9034 break;
9035 }
9036 }
9037
9038 if (!veb && uplink_seid != pf->mac_seid) {
9039
505682cd 9040 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9041 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9042 vsi = pf->vsi[i];
9043 break;
9044 }
9045 }
9046 if (!vsi) {
9047 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9048 uplink_seid);
9049 return NULL;
9050 }
9051
9052 if (vsi->uplink_seid == pf->mac_seid)
9053 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9054 vsi->tc_config.enabled_tc);
9055 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9056 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9057 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9058 if (veb) {
9059 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9060 dev_info(&vsi->back->pdev->dev,
9061 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
9062 __func__);
9063 return NULL;
9064 }
fa11cb3d
ASJ		 9065 /* We come up by default in VEPA mode if SRIOV is not
9066 * already enabled, in which case we can't force VEPA
9067 * mode.
9068 */
9069 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9070 veb->bridge_mode = BRIDGE_MODE_VEPA;
9071 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9072 }
51616018 9073 i40e_config_bridge_mode(veb);
79c21a82 9074 }
41c445ff
JB		 9075 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9076 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9077 veb = pf->veb[i];
9078 }
9079 if (!veb) {
9080 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9081 return NULL;
9082 }
9083
9084 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9085 uplink_seid = veb->seid;
9086 }
9087
9088 /* get vsi sw struct */
9089 v_idx = i40e_vsi_mem_alloc(pf, type);
9090 if (v_idx < 0)
9091 goto err_alloc;
9092 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9093 if (!vsi)
9094 goto err_alloc;
41c445ff
JB		 9095 vsi->type = type;
9096 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9097
9098 if (type == I40E_VSI_MAIN)
9099 pf->lan_vsi = v_idx;
9100 else if (type == I40E_VSI_SRIOV)
9101 vsi->vf_id = param1;
9102 /* assign it some queues */
cbf61325
ASJ		 9103 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9104 vsi->idx);
41c445ff 9105 if (ret < 0) {
049a2be8
SN		 9106 dev_info(&pf->pdev->dev,
9107 "failed to get tracking for %d queues for VSI %d err=%d\n",
9108 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9109 goto err_vsi;
9110 }
9111 vsi->base_queue = ret;
9112
9113 /* get a VSI from the hardware */
9114 vsi->uplink_seid = uplink_seid;
9115 ret = i40e_add_vsi(vsi);
9116 if (ret)
9117 goto err_vsi;
9118
9119 switch (vsi->type) {
9120 /* setup the netdev if needed */
9121 case I40E_VSI_MAIN:
9122 case I40E_VSI_VMDQ2:
38e00438 9123 case I40E_VSI_FCOE:
41c445ff
JB		 9124 ret = i40e_config_netdev(vsi);
9125 if (ret)
9126 goto err_netdev;
9127 ret = register_netdev(vsi->netdev);
9128 if (ret)
9129 goto err_netdev;
9130 vsi->netdev_registered = true;
9131 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9132#ifdef CONFIG_I40E_DCB
9133 /* Setup DCB netlink interface */
9134 i40e_dcbnl_setup(vsi);
9135#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9136 /* fall through */
9137
9138 case I40E_VSI_FDIR:
9139 /* set up vectors and rings if needed */
9140 ret = i40e_vsi_setup_vectors(vsi);
9141 if (ret)
9142 goto err_msix;
9143
9144 ret = i40e_alloc_rings(vsi);
9145 if (ret)
9146 goto err_rings;
9147
9148 /* map all of the rings to the q_vectors */
9149 i40e_vsi_map_rings_to_vectors(vsi);
9150
9151 i40e_vsi_reset_stats(vsi);
9152 break;
9153
9154 default:
9155 /* no netdev or rings for the other VSI types */
9156 break;
9157 }
9158
e25d00b8
ASJ		 9159 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9160 (vsi->type == I40E_VSI_VMDQ2)) {
9161 ret = i40e_vsi_config_rss(vsi);
9162 }
41c445ff
JB		 9163 return vsi;
9164
9165err_rings:
9166 i40e_vsi_free_q_vectors(vsi);
9167err_msix:
9168 if (vsi->netdev_registered) {
9169 vsi->netdev_registered = false;
9170 unregister_netdev(vsi->netdev);
9171 free_netdev(vsi->netdev);
9172 vsi->netdev = NULL;
9173 }
9174err_netdev:
9175 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9176err_vsi:
9177 i40e_vsi_clear(vsi);
9178err_alloc:
9179 return NULL;
9180}
9181
9182/**
9183 * i40e_veb_get_bw_info - Query VEB BW information
9184 * @veb: the veb to query
9185 *
9186 * Query the Tx scheduler BW configuration data for given VEB
9187 **/
9188static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9189{
9190 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9191 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9192 struct i40e_pf *pf = veb->pf;
9193 struct i40e_hw *hw = &pf->hw;
9194 u32 tc_bw_max;
9195 int ret = 0;
9196 int i;
9197
9198 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9199 &bw_data, NULL);
9200 if (ret) {
9201 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9202 "query veb bw config failed, err %s aq_err %s\n",
9203 i40e_stat_str(&pf->hw, ret),
9204 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9205 goto out;
9206 }
9207
9208 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9209 &ets_data, NULL);
9210 if (ret) {
9211 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9212 "query veb bw ets config failed, err %s aq_err %s\n",
9213 i40e_stat_str(&pf->hw, ret),
9214 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9215 goto out;
9216 }
9217
9218 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9219 veb->bw_max_quanta = ets_data.tc_bw_max;
9220 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9221 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9222 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9223 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9224 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9225 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9226 veb->bw_tc_limit_credits[i] =
9227 le16_to_cpu(bw_data.tc_bw_limits[i]);
9228 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9229 }
9230
9231out:
9232 return ret;
9233}
9234
9235/**
9236 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9237 * @pf: board private structure
9238 *
9239 * On error: returns error code (negative)
9240 * On success: returns vsi index in PF (positive)
9241 **/
9242static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9243{
9244 int ret = -ENOENT;
9245 struct i40e_veb *veb;
9246 int i;
9247
9248 /* Need to protect the allocation of switch elements at the PF level */
9249 mutex_lock(&pf->switch_mutex);
9250
9251 /* VEB list may be fragmented if VEB creation/destruction has
9252 * been happening. We can afford to do a quick scan to look
9253 * for any free slots in the list.
9254 *
9255 * find next empty veb slot, looping back around if necessary
9256 */
9257 i = 0;
9258 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9259 i++;
9260 if (i >= I40E_MAX_VEB) {
9261 ret = -ENOMEM;
9262 goto err_alloc_veb; /* out of VEB slots! */
9263 }
9264
9265 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9266 if (!veb) {
9267 ret = -ENOMEM;
9268 goto err_alloc_veb;
9269 }
9270 veb->pf = pf;
9271 veb->idx = i;
9272 veb->enabled_tc = 1;
9273
9274 pf->veb[i] = veb;
9275 ret = i;
9276err_alloc_veb:
9277 mutex_unlock(&pf->switch_mutex);
9278 return ret;
9279}
9280
9281/**
9282 * i40e_switch_branch_release - Delete a branch of the switch tree
9283 * @branch: where to start deleting
9284 *
9285 * This uses recursion to find the tips of the branch to be
9286 * removed, deleting until we get back to and can delete this VEB.
9287 **/
9288static void i40e_switch_branch_release(struct i40e_veb *branch)
9289{
9290 struct i40e_pf *pf = branch->pf;
9291 u16 branch_seid = branch->seid;
9292 u16 veb_idx = branch->idx;
9293 int i;
9294
9295 /* release any VEBs on this VEB - RECURSION */
9296 for (i = 0; i < I40E_MAX_VEB; i++) {
9297 if (!pf->veb[i])
9298 continue;
9299 if (pf->veb[i]->uplink_seid == branch->seid)
9300 i40e_switch_branch_release(pf->veb[i]);
9301 }
9302
9303 /* Release the VSIs on this VEB, but not the owner VSI.
9304 *
9305 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9306 * the VEB itself, so don't use (*branch) after this loop.
9307 */
505682cd 9308 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9309 if (!pf->vsi[i])
9310 continue;
9311 if (pf->vsi[i]->uplink_seid == branch_seid &&
9312 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9313 i40e_vsi_release(pf->vsi[i]);
9314 }
9315 }
9316
9317 /* There's one corner case where the VEB might not have been
9318 * removed, so double check it here and remove it if needed.
9319 * This case happens if the veb was created from the debugfs
9320 * commands and no VSIs were added to it.
9321 */
9322 if (pf->veb[veb_idx])
9323 i40e_veb_release(pf->veb[veb_idx]);
9324}
9325
9326/**
9327 * i40e_veb_clear - remove veb struct
9328 * @veb: the veb to remove
9329 **/
9330static void i40e_veb_clear(struct i40e_veb *veb)
9331{
9332 if (!veb)
9333 return;
9334
9335 if (veb->pf) {
9336 struct i40e_pf *pf = veb->pf;
9337
9338 mutex_lock(&pf->switch_mutex);
9339 if (pf->veb[veb->idx] == veb)
9340 pf->veb[veb->idx] = NULL;
9341 mutex_unlock(&pf->switch_mutex);
9342 }
9343
9344 kfree(veb);
9345}
9346
9347/**
9348 * i40e_veb_release - Delete a VEB and free its resources
9349 * @veb: the VEB being removed
9350 **/
9351void i40e_veb_release(struct i40e_veb *veb)
9352{
9353 struct i40e_vsi *vsi = NULL;
9354 struct i40e_pf *pf;
9355 int i, n = 0;
9356
9357 pf = veb->pf;
9358
9359 /* find the remaining VSI and check for extras */
505682cd 9360 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9361 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9362 n++;
9363 vsi = pf->vsi[i];
9364 }
9365 }
9366 if (n != 1) {
9367 dev_info(&pf->pdev->dev,
9368 "can't remove VEB %d with %d VSIs left\n",
9369 veb->seid, n);
9370 return;
9371 }
9372
9373 /* move the remaining VSI to uplink veb */
9374 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9375 if (veb->uplink_seid) {
9376 vsi->uplink_seid = veb->uplink_seid;
9377 if (veb->uplink_seid == pf->mac_seid)
9378 vsi->veb_idx = I40E_NO_VEB;
9379 else
9380 vsi->veb_idx = veb->veb_idx;
9381 } else {
9382 /* floating VEB */
9383 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9384 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9385 }
9386
9387 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9388 i40e_veb_clear(veb);
41c445ff
JB		 9389}
9390
9391/**
9392 * i40e_add_veb - create the VEB in the switch
9393 * @veb: the VEB to be instantiated
9394 * @vsi: the controlling VSI
9395 **/
9396static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9397{
f1c7e72e 9398 struct i40e_pf *pf = veb->pf;
92faef85 9399 bool is_default = veb->pf->cur_promisc;
e1c51b95 9400 bool is_cloud = false;
41c445ff
JB		 9401 int ret;
9402
9403 /* get a VEB from the hardware */
f1c7e72e 9404 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9405 veb->enabled_tc, is_default,
9406 is_cloud, &veb->seid, NULL);
41c445ff 9407 if (ret) {
f1c7e72e
SN		 9408 dev_info(&pf->pdev->dev,
9409 "couldn't add VEB, err %s aq_err %s\n",
9410 i40e_stat_str(&pf->hw, ret),
9411 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9412 return -EPERM;
9413 }
9414
9415 /* get statistics counter */
f1c7e72e 9416 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9417 &veb->stats_idx, NULL, NULL, NULL);
9418 if (ret) {
f1c7e72e
SN		 9419 dev_info(&pf->pdev->dev,
9420 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9421 i40e_stat_str(&pf->hw, ret),
9422 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9423 return -EPERM;
9424 }
9425 ret = i40e_veb_get_bw_info(veb);
9426 if (ret) {
f1c7e72e
SN		 9427 dev_info(&pf->pdev->dev,
9428 "couldn't get VEB bw info, err %s aq_err %s\n",
9429 i40e_stat_str(&pf->hw, ret),
9430 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9431 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9432 return -ENOENT;
9433 }
9434
9435 vsi->uplink_seid = veb->seid;
9436 vsi->veb_idx = veb->idx;
9437 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9438
9439 return 0;
9440}
9441
9442/**
9443 * i40e_veb_setup - Set up a VEB
9444 * @pf: board private structure
9445 * @flags: VEB setup flags
9446 * @uplink_seid: the switch element to link to
9447 * @vsi_seid: the initial VSI seid
9448 * @enabled_tc: Enabled TC bit-map
9449 *
9450 * This allocates the sw VEB structure and links it into the switch
9451 * It is possible and legal for this to be a duplicate of an already
9452 * existing VEB. It is also possible for both uplink and vsi seids
9453 * to be zero, in order to create a floating VEB.
9454 *
9455 * Returns pointer to the successfully allocated VEB sw struct on
9456 * success, otherwise returns NULL on failure.
9457 **/
9458struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9459 u16 uplink_seid, u16 vsi_seid,
9460 u8 enabled_tc)
9461{
9462 struct i40e_veb *veb, *uplink_veb = NULL;
9463 int vsi_idx, veb_idx;
9464 int ret;
9465
9466 /* if one seid is 0, the other must be 0 to create a floating relay */
9467 if ((uplink_seid == 0 || vsi_seid == 0) &&
9468 (uplink_seid + vsi_seid != 0)) {
9469 dev_info(&pf->pdev->dev,
9470 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9471 uplink_seid, vsi_seid);
9472 return NULL;
9473 }
9474
9475 /* make sure there is such a vsi and uplink */
505682cd 9476 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9477 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9478 break;
505682cd 9479 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9480 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9481 vsi_seid);
9482 return NULL;
9483 }
9484
9485 if (uplink_seid && uplink_seid != pf->mac_seid) {
9486 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9487 if (pf->veb[veb_idx] &&
9488 pf->veb[veb_idx]->seid == uplink_seid) {
9489 uplink_veb = pf->veb[veb_idx];
9490 break;
9491 }
9492 }
9493 if (!uplink_veb) {
9494 dev_info(&pf->pdev->dev,
9495 "uplink seid %d not found\n", uplink_seid);
9496 return NULL;
9497 }
9498 }
9499
9500 /* get veb sw struct */
9501 veb_idx = i40e_veb_mem_alloc(pf);
9502 if (veb_idx < 0)
9503 goto err_alloc;
9504 veb = pf->veb[veb_idx];
9505 veb->flags = flags;
9506 veb->uplink_seid = uplink_seid;
9507 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9508 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9509
9510 /* create the VEB in the switch */
9511 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9512 if (ret)
9513 goto err_veb;
1bb8b935
SN		 9514 if (vsi_idx == pf->lan_vsi)
9515 pf->lan_veb = veb->idx;
41c445ff
JB		 9516
9517 return veb;
9518
9519err_veb:
9520 i40e_veb_clear(veb);
9521err_alloc:
9522 return NULL;
9523}
9524
9525/**
b40c82e6 9526 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9527 * @pf: board private structure
9528 * @ele: element we are building info from
9529 * @num_reported: total number of elements
9530 * @printconfig: should we print the contents
9531 *
9532 * helper function to assist in extracting a few useful SEID values.
9533 **/
9534static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9535 struct i40e_aqc_switch_config_element_resp *ele,
9536 u16 num_reported, bool printconfig)
9537{
9538 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9539 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9540 u8 element_type = ele->element_type;
9541 u16 seid = le16_to_cpu(ele->seid);
9542
9543 if (printconfig)
9544 dev_info(&pf->pdev->dev,
9545 "type=%d seid=%d uplink=%d downlink=%d\n",
9546 element_type, seid, uplink_seid, downlink_seid);
9547
9548 switch (element_type) {
9549 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9550 pf->mac_seid = seid;
9551 break;
9552 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9553 /* Main VEB? */
9554 if (uplink_seid != pf->mac_seid)
9555 break;
9556 if (pf->lan_veb == I40E_NO_VEB) {
9557 int v;
9558
9559 /* find existing or else empty VEB */
9560 for (v = 0; v < I40E_MAX_VEB; v++) {
9561 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9562 pf->lan_veb = v;
9563 break;
9564 }
9565 }
9566 if (pf->lan_veb == I40E_NO_VEB) {
9567 v = i40e_veb_mem_alloc(pf);
9568 if (v < 0)
9569 break;
9570 pf->lan_veb = v;
9571 }
9572 }
9573
9574 pf->veb[pf->lan_veb]->seid = seid;
9575 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9576 pf->veb[pf->lan_veb]->pf = pf;
9577 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9578 break;
9579 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9580 if (num_reported != 1)
9581 break;
9582 /* This is immediately after a reset so we can assume this is
9583 * the PF's VSI
9584 */
9585 pf->mac_seid = uplink_seid;
9586 pf->pf_seid = downlink_seid;
9587 pf->main_vsi_seid = seid;
9588 if (printconfig)
9589 dev_info(&pf->pdev->dev,
9590 "pf_seid=%d main_vsi_seid=%d\n",
9591 pf->pf_seid, pf->main_vsi_seid);
9592 break;
9593 case I40E_SWITCH_ELEMENT_TYPE_PF:
9594 case I40E_SWITCH_ELEMENT_TYPE_VF:
9595 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9596 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9597 case I40E_SWITCH_ELEMENT_TYPE_PE:
9598 case I40E_SWITCH_ELEMENT_TYPE_PA:
9599 /* ignore these for now */
9600 break;
9601 default:
9602 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9603 element_type, seid);
9604 break;
9605 }
9606}
9607
9608/**
9609 * i40e_fetch_switch_configuration - Get switch config from firmware
9610 * @pf: board private structure
9611 * @printconfig: should we print the contents
9612 *
9613 * Get the current switch configuration from the device and
9614 * extract a few useful SEID values.
9615 **/
9616int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9617{
9618 struct i40e_aqc_get_switch_config_resp *sw_config;
9619 u16 next_seid = 0;
9620 int ret = 0;
9621 u8 *aq_buf;
9622 int i;
9623
9624 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9625 if (!aq_buf)
9626 return -ENOMEM;
9627
9628 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9629 do {
9630 u16 num_reported, num_total;
9631
9632 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9633 I40E_AQ_LARGE_BUF,
9634 &next_seid, NULL);
9635 if (ret) {
9636 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9637 "get switch config failed err %s aq_err %s\n",
9638 i40e_stat_str(&pf->hw, ret),
9639 i40e_aq_str(&pf->hw,
9640 pf->hw.aq.asq_last_status));
41c445ff
JB		 9641 kfree(aq_buf);
9642 return -ENOENT;
9643 }
9644
9645 num_reported = le16_to_cpu(sw_config->header.num_reported);
9646 num_total = le16_to_cpu(sw_config->header.num_total);
9647
9648 if (printconfig)
9649 dev_info(&pf->pdev->dev,
9650 "header: %d reported %d total\n",
9651 num_reported, num_total);
9652
41c445ff
JB		 9653 for (i = 0; i < num_reported; i++) {
9654 struct i40e_aqc_switch_config_element_resp *ele =
9655 &sw_config->element[i];
9656
9657 i40e_setup_pf_switch_element(pf, ele, num_reported,
9658 printconfig);
9659 }
9660 } while (next_seid != 0);
9661
9662 kfree(aq_buf);
9663 return ret;
9664}
9665
9666/**
9667 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9668 * @pf: board private structure
bc7d338f 9669 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9670 *
9671 * Returns 0 on success, negative value on failure
9672 **/
bc7d338f 9673static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9674{
9675 int ret;
9676
9677 /* find out what's out there already */
9678 ret = i40e_fetch_switch_configuration(pf, false);
9679 if (ret) {
9680 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9681 "couldn't fetch switch config, err %s aq_err %s\n",
9682 i40e_stat_str(&pf->hw, ret),
9683 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9684 return ret;
9685 }
9686 i40e_pf_reset_stats(pf);
9687
41c445ff 9688 /* first time setup */
bc7d338f 9689 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9690 struct i40e_vsi *vsi = NULL;
9691 u16 uplink_seid;
9692
9693 /* Set up the PF VSI associated with the PF's main VSI
9694 * that is already in the HW switch
9695 */
9696 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9697 uplink_seid = pf->veb[pf->lan_veb]->seid;
9698 else
9699 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9700 if (pf->lan_vsi == I40E_NO_VSI)
9701 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9702 else if (reinit)
9703 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9704 if (!vsi) {
9705 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9706 i40e_fdir_teardown(pf);
9707 return -EAGAIN;
9708 }
41c445ff
JB		 9709 } else {
9710 /* force a reset of TC and queue layout configurations */
9711 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9712 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9713 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9714 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9715 }
9716 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9717
cbf61325
ASJ		 9718 i40e_fdir_sb_setup(pf);
9719
41c445ff
JB		 9720 /* Setup static PF queue filter control settings */
9721 ret = i40e_setup_pf_filter_control(pf);
9722 if (ret) {
9723 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9724 ret);
9725 /* Failure here should not stop continuing other steps */
9726 }
9727
9728 /* enable RSS in the HW, even for only one queue, as the stack can use
9729 * the hash
9730 */
9731 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9732 i40e_config_rss(pf);
9733
9734 /* fill in link information and enable LSE reporting */
21af70fb 9735 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9736 i40e_link_event(pf);
9737
d52c20b7 9738 /* Initialize user-specific link properties */
41c445ff
JB		 9739 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9740 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9741
beb0dff1
JK		 9742 i40e_ptp_init(pf);
9743
41c445ff
JB		 9744 return ret;
9745}
9746
41c445ff
JB		 9747/**
9748 * i40e_determine_queue_usage - Work out queue distribution
9749 * @pf: board private structure
9750 **/
9751static void i40e_determine_queue_usage(struct i40e_pf *pf)
9752{
41c445ff
JB		 9753 int queues_left;
9754
9755 pf->num_lan_qps = 0;
38e00438
VD		 9756#ifdef I40E_FCOE
9757 pf->num_fcoe_qps = 0;
9758#endif
41c445ff
JB		 9759
9760 /* Find the max queues to be put into basic use. We'll always be
9761 * using TC0, whether or not DCB is running, and TC0 will get the
9762 * big RSS set.
9763 */
9764 queues_left = pf->hw.func_caps.num_tx_qp;
9765
cbf61325 9766 if ((queues_left == 1) ||
9aa7e935 9767 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9768 /* one qp for PF, no queues for anything else */
9769 queues_left = 0;
9770 pf->rss_size = pf->num_lan_qps = 1;
9771
9772 /* make sure all the fancies are disabled */
60ea5f83 9773 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9774#ifdef I40E_FCOE
9775 I40E_FLAG_FCOE_ENABLED |
9776#endif
60ea5f83
JB		 9777 I40E_FLAG_FD_SB_ENABLED |
9778 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9779 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9780 I40E_FLAG_SRIOV_ENABLED |
9781 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9782 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9783 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9784 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9785 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9786 /* one qp for PF */
9787 pf->rss_size = pf->num_lan_qps = 1;
9788 queues_left -= pf->num_lan_qps;
9789
9790 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9791#ifdef I40E_FCOE
9792 I40E_FLAG_FCOE_ENABLED |
9793#endif
9aa7e935
FZ		 9794 I40E_FLAG_FD_SB_ENABLED |
9795 I40E_FLAG_FD_ATR_ENABLED |
9796 I40E_FLAG_DCB_ENABLED |
9797 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9798 } else {
cbf61325 9799 /* Not enough queues for all TCs */
4d9b6043 9800 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9801 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9802 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9803 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9804 }
9a3bd2f1
ASJ		 9805 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9806 num_online_cpus());
9807 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9808 pf->hw.func_caps.num_tx_qp);
9809
cbf61325
ASJ		 9810 queues_left -= pf->num_lan_qps;
9811 }
9812
38e00438
VD		 9813#ifdef I40E_FCOE
9814 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9815 if (I40E_DEFAULT_FCOE <= queues_left) {
9816 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9817 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9818 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9819 } else {
9820 pf->num_fcoe_qps = 0;
9821 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9822 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9823 }
9824
9825 queues_left -= pf->num_fcoe_qps;
9826 }
9827
9828#endif
cbf61325
ASJ		 9829 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9830 if (queues_left > 1) {
9831 queues_left -= 1; /* save 1 queue for FD */
9832 } else {
9833 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9834 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9835 }
41c445ff
JB		 9836 }
9837
9838 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9839 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9840 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9841 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9842 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9843 }
9844
9845 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9846 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9847 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9848 (queues_left / pf->num_vmdq_qps));
9849 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9850 }
9851
f8ff1464 9852 pf->queues_left = queues_left;
38e00438
VD		 9853#ifdef I40E_FCOE
9854 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9855#endif
41c445ff
JB		 9856}
9857
9858/**
9859 * i40e_setup_pf_filter_control - Setup PF static filter control
9860 * @pf: PF to be setup
9861 *
b40c82e6 9862 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 9863 * settings. If PE/FCoE are enabled then it will also set the per PF
9864 * based filter sizes required for them. It also enables Flow director,
9865 * ethertype and macvlan type filter settings for the pf.
9866 *
9867 * Returns 0 on success, negative on failure
9868 **/
9869static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9870{
9871 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9872
9873 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9874
9875 /* Flow Director is enabled */
60ea5f83 9876 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9877 settings->enable_fdir = true;
9878
9879 /* Ethtype and MACVLAN filters enabled for PF */
9880 settings->enable_ethtype = true;
9881 settings->enable_macvlan = true;
9882
9883 if (i40e_set_filter_control(&pf->hw, settings))
9884 return -ENOENT;
9885
9886 return 0;
9887}
9888
0c22b3dd
JB		 9889#define INFO_STRING_LEN 255
9890static void i40e_print_features(struct i40e_pf *pf)
9891{
9892 struct i40e_hw *hw = &pf->hw;
9893 char *buf, *string;
9894
9895 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9896 if (!string) {
9897 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9898 return;
9899 }
9900
9901 buf = string;
9902
9903 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9904#ifdef CONFIG_PCI_IOV
9905 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9906#endif
aba237d1
MW		 9907 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9908 pf->hw.func_caps.num_vsis,
9909 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9910 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9911
9912 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9913 buf += sprintf(buf, "RSS ");
0c22b3dd 9914 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9915 buf += sprintf(buf, "FD_ATR ");
9916 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9917 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9918 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9919 }
4d9b6043 9920 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9921 buf += sprintf(buf, "DCB ");
9922 if (pf->flags & I40E_FLAG_PTP)
9923 buf += sprintf(buf, "PTP ");
38e00438
VD		 9924#ifdef I40E_FCOE
9925 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9926 buf += sprintf(buf, "FCOE ");
9927#endif
0c22b3dd
JB		 9928
9929 BUG_ON(buf > (string + INFO_STRING_LEN));
9930 dev_info(&pf->pdev->dev, "%s\n", string);
9931 kfree(string);
9932}
9933
41c445ff
JB		 9934/**
9935 * i40e_probe - Device initialization routine
9936 * @pdev: PCI device information struct
9937 * @ent: entry in i40e_pci_tbl
9938 *
b40c82e6
JK		 9939 * i40e_probe initializes a PF identified by a pci_dev structure.
9940 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 9941 * and a hardware reset occur.
9942 *
9943 * Returns 0 on success, negative on failure
9944 **/
9945static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9946{
e827845c 9947 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 9948 struct i40e_pf *pf;
9949 struct i40e_hw *hw;
93cd765b 9950 static u16 pfs_found;
1d5109d1 9951 u16 wol_nvm_bits;
d4dfb81a 9952 u16 link_status;
41c445ff
JB		 9953 int err = 0;
9954 u32 len;
8a9eb7d3 9955 u32 i;
41c445ff
JB		 9956
9957 err = pci_enable_device_mem(pdev);
9958 if (err)
9959 return err;
9960
9961 /* set up for high or low dma */
6494294f 9962 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9963 if (err) {
e3e3bfdd
JS		 9964 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9965 if (err) {
9966 dev_err(&pdev->dev,
9967 "DMA configuration failed: 0x%x\n", err);
9968 goto err_dma;
9969 }
41c445ff
JB		 9970 }
9971
9972 /* set up pci connections */
9973 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9974 IORESOURCE_MEM), i40e_driver_name);
9975 if (err) {
9976 dev_info(&pdev->dev,
9977 "pci_request_selected_regions failed %d\n", err);
9978 goto err_pci_reg;
9979 }
9980
9981 pci_enable_pcie_error_reporting(pdev);
9982 pci_set_master(pdev);
9983
9984 /* Now that we have a PCI connection, we need to do the
9985 * low level device setup. This is primarily setting up
9986 * the Admin Queue structures and then querying for the
9987 * device's current profile information.
9988 */
9989 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9990 if (!pf) {
9991 err = -ENOMEM;
9992 goto err_pf_alloc;
9993 }
9994 pf->next_vsi = 0;
9995 pf->pdev = pdev;
9996 set_bit(__I40E_DOWN, &pf->state);
9997
9998 hw = &pf->hw;
9999 hw->back = pf;
232f4706 10000
2ac8b675
SN		 10001 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10002 I40E_MAX_CSR_SPACE);
232f4706 10003
2ac8b675 10004 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10005 if (!hw->hw_addr) {
10006 err = -EIO;
10007 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10008 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10009 pf->ioremap_len, err);
41c445ff
JB		 10010 goto err_ioremap;
10011 }
10012 hw->vendor_id = pdev->vendor;
10013 hw->device_id = pdev->device;
10014 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10015 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10016 hw->subsystem_device_id = pdev->subsystem_device;
10017 hw->bus.device = PCI_SLOT(pdev->devfn);
10018 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10019 pf->instance = pfs_found;
41c445ff 10020
5b5faa43
SN		 10021 if (debug != -1) {
10022 pf->msg_enable = pf->hw.debug_mask;
10023 pf->msg_enable = debug;
10024 }
10025
7134f9ce
JB		 10026 /* do a special CORER for clearing PXE mode once at init */
10027 if (hw->revision_id == 0 &&
10028 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10029 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10030 i40e_flush(hw);
10031 msleep(200);
10032 pf->corer_count++;
10033
10034 i40e_clear_pxe_mode(hw);
10035 }
10036
41c445ff 10037 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10038 i40e_clear_hw(hw);
41c445ff
JB		 10039 err = i40e_pf_reset(hw);
10040 if (err) {
10041 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10042 goto err_pf_reset;
10043 }
10044 pf->pfr_count++;
10045
10046 hw->aq.num_arq_entries = I40E_AQ_LEN;
10047 hw->aq.num_asq_entries = I40E_AQ_LEN;
10048 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10049 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10050 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10051
b294ac70 10052 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10053 "%s-%s:misc",
10054 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10055
10056 err = i40e_init_shared_code(hw);
10057 if (err) {
b2a75c58
ASJ		 10058 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10059 err);
41c445ff
JB		 10060 goto err_pf_reset;
10061 }
10062
d52c20b7
JB		 10063 /* set up a default setting for link flow control */
10064 pf->hw.fc.requested_mode = I40E_FC_NONE;
10065
41c445ff
JB		 10066 err = i40e_init_adminq(hw);
10067 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
10068 if (err) {
10069 dev_info(&pdev->dev,
7aa67613 10070 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 10071 goto err_pf_reset;
10072 }
10073
7aa67613
CS		 10074 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10075 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10076 dev_info(&pdev->dev,
7aa67613
CS		 10077 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10078 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10079 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10080 dev_info(&pdev->dev,
7aa67613 10081 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10082
4eb3f768
SN		 10083 i40e_verify_eeprom(pf);
10084
2c5fe33b
JB		 10085 /* Rev 0 hardware was never productized */
10086 if (hw->revision_id < 1)
10087 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10088
6ff4ef86 10089 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10090 err = i40e_get_capabilities(pf);
10091 if (err)
10092 goto err_adminq_setup;
10093
10094 err = i40e_sw_init(pf);
10095 if (err) {
10096 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10097 goto err_sw_init;
10098 }
10099
10100 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10101 hw->func_caps.num_rx_qp,
10102 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10103 if (err) {
10104 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10105 goto err_init_lan_hmc;
10106 }
10107
10108 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10109 if (err) {
10110 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10111 err = -ENOENT;
10112 goto err_configure_lan_hmc;
10113 }
10114
b686ece5
NP		 10115 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10116 * Ignore error return codes because if it was already disabled via
10117 * hardware settings this will fail
10118 */
10119 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10120 (pf->hw.aq.fw_maj_ver < 4)) {
10121 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10122 i40e_aq_stop_lldp(hw, true, NULL);
10123 }
10124
41c445ff 10125 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10126 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10127 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10128 err = -EIO;
10129 goto err_mac_addr;
10130 }
10131 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10132 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10133 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10134 if (is_valid_ether_addr(hw->mac.port_addr))
10135 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10136#ifdef I40E_FCOE
10137 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10138 if (err)
10139 dev_info(&pdev->dev,
10140 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10141 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10142 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10143 hw->mac.san_addr);
10144 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10145 }
10146 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10147#endif /* I40E_FCOE */
41c445ff
JB		 10148
10149 pci_set_drvdata(pdev, pf);
10150 pci_save_state(pdev);
4e3b35b0
NP		 10151#ifdef CONFIG_I40E_DCB
10152 err = i40e_init_pf_dcb(pf);
10153 if (err) {
aebfc816 10154 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10155 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10156 /* Continue without DCB enabled */
4e3b35b0
NP		 10157 }
10158#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10159
10160 /* set up periodic task facility */
10161 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10162 pf->service_timer_period = HZ;
10163
10164 INIT_WORK(&pf->service_task, i40e_service_task);
10165 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10166 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10167
1d5109d1
SN		 10168 /* NVM bit on means WoL disabled for the port */
10169 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
10170 if ((1 << hw->port) & wol_nvm_bits || hw->partition_id != 1)
10171 pf->wol_en = false;
10172 else
10173 pf->wol_en = true;
8e2773ae
SN		 10174 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10175
41c445ff
JB		 10176 /* set up the main switch operations */
10177 i40e_determine_queue_usage(pf);
c1147280
JB		 10178 err = i40e_init_interrupt_scheme(pf);
10179 if (err)
10180 goto err_switch_setup;
41c445ff 10181
505682cd
MW		 10182 /* The number of VSIs reported by the FW is the minimum guaranteed
10183 * to us; HW supports far more and we share the remaining pool with
10184 * the other PFs. We allocate space for more than the guarantee with
10185 * the understanding that we might not get them all later.
41c445ff 10186 */
505682cd
MW		 10187 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10188 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10189 else
10190 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10191
10192 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10193 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10194 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10195 if (!pf->vsi) {
10196 err = -ENOMEM;
41c445ff 10197 goto err_switch_setup;
ed87ac09 10198 }
41c445ff 10199
fa11cb3d
ASJ		 10200#ifdef CONFIG_PCI_IOV
10201 /* prep for VF support */
10202 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10203 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10204 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10205 if (pci_num_vf(pdev))
10206 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10207 }
10208#endif
bc7d338f 10209 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10210 if (err) {
10211 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10212 goto err_vsis;
10213 }
8a9eb7d3 10214 /* if FDIR VSI was set up, start it now */
505682cd 10215 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10216 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10217 i40e_vsi_open(pf->vsi[i]);
10218 break;
10219 }
10220 }
41c445ff 10221
7e2453fe
JB		 10222 /* driver is only interested in link up/down and module qualification
10223 * reports from firmware
10224 */
10225 err = i40e_aq_set_phy_int_mask(&pf->hw,
10226 I40E_AQ_EVENT_LINK_UPDOWN |
10227 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10228 if (err)
f1c7e72e
SN		 10229 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10230 i40e_stat_str(&pf->hw, err),
10231 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10232
025b4a54
ASJ		 10233 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10234 (pf->hw.aq.fw_maj_ver < 4)) {
10235 msleep(75);
10236 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10237 if (err)
f1c7e72e
SN		 10238 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10239 i40e_stat_str(&pf->hw, err),
10240 i40e_aq_str(&pf->hw,
10241 pf->hw.aq.asq_last_status));
cafa2ee6 10242 }
41c445ff
JB		 10243 /* The main driver is (mostly) up and happy. We need to set this state
10244 * before setting up the misc vector or we get a race and the vector
10245 * ends up disabled forever.
10246 */
10247 clear_bit(__I40E_DOWN, &pf->state);
10248
10249 /* In case of MSIX we are going to setup the misc vector right here
10250 * to handle admin queue events etc. In case of legacy and MSI
10251 * the misc functionality and queue processing is combined in
10252 * the same vector and that gets setup at open.
10253 */
10254 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10255 err = i40e_setup_misc_vector(pf);
10256 if (err) {
10257 dev_info(&pdev->dev,
10258 "setup of misc vector failed: %d\n", err);
10259 goto err_vsis;
10260 }
10261 }
10262
df805f62 10263#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10264 /* prep for VF support */
10265 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10266 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10267 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10268 u32 val;
10269
10270 /* disable link interrupts for VFs */
10271 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10272 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10273 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10274 i40e_flush(hw);
4aeec010
MW		 10275
10276 if (pci_num_vf(pdev)) {
10277 dev_info(&pdev->dev,
10278 "Active VFs found, allocating resources.\n");
10279 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10280 if (err)
10281 dev_info(&pdev->dev,
10282 "Error %d allocating resources for existing VFs\n",
10283 err);
10284 }
41c445ff 10285 }
df805f62 10286#endif /* CONFIG_PCI_IOV */
41c445ff 10287
93cd765b
ASJ		 10288 pfs_found++;
10289
41c445ff
JB		 10290 i40e_dbg_pf_init(pf);
10291
10292 /* tell the firmware that we're starting */
44033fac 10293 i40e_send_version(pf);
41c445ff
JB		 10294
10295 /* since everything's happy, start the service_task timer */
10296 mod_timer(&pf->service_timer,
10297 round_jiffies(jiffies + pf->service_timer_period));
10298
38e00438
VD		 10299#ifdef I40E_FCOE
10300 /* create FCoE interface */
10301 i40e_fcoe_vsi_setup(pf);
10302
10303#endif
d4dfb81a
CS		 10304 /* Get the negotiated link width and speed from PCI config space */
10305 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
10306
10307 i40e_set_pci_config_data(hw, link_status);
10308
69bfb110 10309 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 10310 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
10311 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
10312 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
10313 "Unknown"),
10314 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
10315 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
10316 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
10317 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
10318 "Unknown"));
10319
10320 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10321 hw->bus.speed < i40e_bus_speed_8000) {
10322 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10323 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10324 }
10325
e827845c
CS		 10326 /* get the requested speeds from the fw */
10327 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10328 if (err)
f1c7e72e
SN		 10329 dev_info(&pf->pdev->dev,
10330 "get phy capabilities failed, err %s aq_err %s, advertised speed settings may not be correct\n",
10331 i40e_stat_str(&pf->hw, err),
10332 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10333 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10334
0c22b3dd
JB		 10335 /* print a string summarizing features */
10336 i40e_print_features(pf);
10337
41c445ff
JB		 10338 return 0;
10339
10340 /* Unwind what we've done if something failed in the setup */
10341err_vsis:
10342 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10343 i40e_clear_interrupt_scheme(pf);
10344 kfree(pf->vsi);
04b03013
SN		 10345err_switch_setup:
10346 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10347 del_timer_sync(&pf->service_timer);
10348err_mac_addr:
10349err_configure_lan_hmc:
10350 (void)i40e_shutdown_lan_hmc(hw);
10351err_init_lan_hmc:
10352 kfree(pf->qp_pile);
41c445ff
JB		 10353err_sw_init:
10354err_adminq_setup:
10355 (void)i40e_shutdown_adminq(hw);
10356err_pf_reset:
10357 iounmap(hw->hw_addr);
10358err_ioremap:
10359 kfree(pf);
10360err_pf_alloc:
10361 pci_disable_pcie_error_reporting(pdev);
10362 pci_release_selected_regions(pdev,
10363 pci_select_bars(pdev, IORESOURCE_MEM));
10364err_pci_reg:
10365err_dma:
10366 pci_disable_device(pdev);
10367 return err;
10368}
10369
10370/**
10371 * i40e_remove - Device removal routine
10372 * @pdev: PCI device information struct
10373 *
10374 * i40e_remove is called by the PCI subsystem to alert the driver
10375 * that is should release a PCI device. This could be caused by a
10376 * Hot-Plug event, or because the driver is going to be removed from
10377 * memory.
10378 **/
10379static void i40e_remove(struct pci_dev *pdev)
10380{
10381 struct i40e_pf *pf = pci_get_drvdata(pdev);
10382 i40e_status ret_code;
41c445ff
JB		 10383 int i;
10384
10385 i40e_dbg_pf_exit(pf);
10386
beb0dff1
JK		 10387 i40e_ptp_stop(pf);
10388
41c445ff
JB		 10389 /* no more scheduling of any task */
10390 set_bit(__I40E_DOWN, &pf->state);
10391 del_timer_sync(&pf->service_timer);
10392 cancel_work_sync(&pf->service_task);
33c62b34 10393 i40e_fdir_teardown(pf);
41c445ff 10394
eb2d80bc
MW		 10395 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10396 i40e_free_vfs(pf);
10397 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10398 }
10399
41c445ff
JB		 10400 i40e_fdir_teardown(pf);
10401
10402 /* If there is a switch structure or any orphans, remove them.
10403 * This will leave only the PF's VSI remaining.
10404 */
10405 for (i = 0; i < I40E_MAX_VEB; i++) {
10406 if (!pf->veb[i])
10407 continue;
10408
10409 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10410 pf->veb[i]->uplink_seid == 0)
10411 i40e_switch_branch_release(pf->veb[i]);
10412 }
10413
10414 /* Now we can shutdown the PF's VSI, just before we kill
10415 * adminq and hmc.
10416 */
10417 if (pf->vsi[pf->lan_vsi])
10418 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10419
41c445ff 10420 /* shutdown and destroy the HMC */
60442dea
SN		 10421 if (pf->hw.hmc.hmc_obj) {
10422 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10423 if (ret_code)
10424 dev_warn(&pdev->dev,
10425 "Failed to destroy the HMC resources: %d\n",
10426 ret_code);
10427 }
41c445ff
JB		 10428
10429 /* shutdown the adminq */
41c445ff
JB		 10430 ret_code = i40e_shutdown_adminq(&pf->hw);
10431 if (ret_code)
10432 dev_warn(&pdev->dev,
10433 "Failed to destroy the Admin Queue resources: %d\n",
10434 ret_code);
10435
10436 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10437 i40e_clear_interrupt_scheme(pf);
505682cd 10438 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10439 if (pf->vsi[i]) {
10440 i40e_vsi_clear_rings(pf->vsi[i]);
10441 i40e_vsi_clear(pf->vsi[i]);
10442 pf->vsi[i] = NULL;
10443 }
10444 }
10445
10446 for (i = 0; i < I40E_MAX_VEB; i++) {
10447 kfree(pf->veb[i]);
10448 pf->veb[i] = NULL;
10449 }
10450
10451 kfree(pf->qp_pile);
41c445ff
JB		 10452 kfree(pf->vsi);
10453
41c445ff
JB		 10454 iounmap(pf->hw.hw_addr);
10455 kfree(pf);
10456 pci_release_selected_regions(pdev,
10457 pci_select_bars(pdev, IORESOURCE_MEM));
10458
10459 pci_disable_pcie_error_reporting(pdev);
10460 pci_disable_device(pdev);
10461}
10462
10463/**
10464 * i40e_pci_error_detected - warning that something funky happened in PCI land
10465 * @pdev: PCI device information struct
10466 *
10467 * Called to warn that something happened and the error handling steps
10468 * are in progress. Allows the driver to quiesce things, be ready for
10469 * remediation.
10470 **/
10471static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10472 enum pci_channel_state error)
10473{
10474 struct i40e_pf *pf = pci_get_drvdata(pdev);
10475
10476 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10477
10478 /* shutdown all operations */
9007bccd
SN		 10479 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10480 rtnl_lock();
10481 i40e_prep_for_reset(pf);
10482 rtnl_unlock();
10483 }
41c445ff
JB		 10484
10485 /* Request a slot reset */
10486 return PCI_ERS_RESULT_NEED_RESET;
10487}
10488
10489/**
10490 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10491 * @pdev: PCI device information struct
10492 *
10493 * Called to find if the driver can work with the device now that
10494 * the pci slot has been reset. If a basic connection seems good
10495 * (registers are readable and have sane content) then return a
10496 * happy little PCI_ERS_RESULT_xxx.
10497 **/
10498static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10499{
10500 struct i40e_pf *pf = pci_get_drvdata(pdev);
10501 pci_ers_result_t result;
10502 int err;
10503 u32 reg;
10504
10505 dev_info(&pdev->dev, "%s\n", __func__);
10506 if (pci_enable_device_mem(pdev)) {
10507 dev_info(&pdev->dev,
10508 "Cannot re-enable PCI device after reset.\n");
10509 result = PCI_ERS_RESULT_DISCONNECT;
10510 } else {
10511 pci_set_master(pdev);
10512 pci_restore_state(pdev);
10513 pci_save_state(pdev);
10514 pci_wake_from_d3(pdev, false);
10515
10516 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10517 if (reg == 0)
10518 result = PCI_ERS_RESULT_RECOVERED;
10519 else
10520 result = PCI_ERS_RESULT_DISCONNECT;
10521 }
10522
10523 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10524 if (err) {
10525 dev_info(&pdev->dev,
10526 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10527 err);
10528 /* non-fatal, continue */
10529 }
10530
10531 return result;
10532}
10533
10534/**
10535 * i40e_pci_error_resume - restart operations after PCI error recovery
10536 * @pdev: PCI device information struct
10537 *
10538 * Called to allow the driver to bring things back up after PCI error
10539 * and/or reset recovery has finished.
10540 **/
10541static void i40e_pci_error_resume(struct pci_dev *pdev)
10542{
10543 struct i40e_pf *pf = pci_get_drvdata(pdev);
10544
10545 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10546 if (test_bit(__I40E_SUSPENDED, &pf->state))
10547 return;
10548
10549 rtnl_lock();
41c445ff 10550 i40e_handle_reset_warning(pf);
4c4935a9 10551 rtnl_unlock();
9007bccd
SN		 10552}
10553
10554/**
10555 * i40e_shutdown - PCI callback for shutting down
10556 * @pdev: PCI device information struct
10557 **/
10558static void i40e_shutdown(struct pci_dev *pdev)
10559{
10560 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10561 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10562
10563 set_bit(__I40E_SUSPENDED, &pf->state);
10564 set_bit(__I40E_DOWN, &pf->state);
10565 rtnl_lock();
10566 i40e_prep_for_reset(pf);
10567 rtnl_unlock();
10568
8e2773ae
SN		 10569 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10570 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10571
02b42498
CS		 10572 del_timer_sync(&pf->service_timer);
10573 cancel_work_sync(&pf->service_task);
10574 i40e_fdir_teardown(pf);
10575
10576 rtnl_lock();
10577 i40e_prep_for_reset(pf);
10578 rtnl_unlock();
10579
10580 wr32(hw, I40E_PFPM_APM,
10581 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10582 wr32(hw, I40E_PFPM_WUFC,
10583 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10584
e147758d
SN		 10585 i40e_clear_interrupt_scheme(pf);
10586
9007bccd 10587 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10588 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10589 pci_set_power_state(pdev, PCI_D3hot);
10590 }
10591}
10592
10593#ifdef CONFIG_PM
10594/**
10595 * i40e_suspend - PCI callback for moving to D3
10596 * @pdev: PCI device information struct
10597 **/
10598static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10599{
10600 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10601 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10602
10603 set_bit(__I40E_SUSPENDED, &pf->state);
10604 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 10605
9007bccd
SN		 10606 rtnl_lock();
10607 i40e_prep_for_reset(pf);
10608 rtnl_unlock();
10609
8e2773ae
SN		 10610 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10611 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10612
10613 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10614 pci_set_power_state(pdev, PCI_D3hot);
10615
10616 return 0;
41c445ff
JB		 10617}
10618
9007bccd
SN		 10619/**
10620 * i40e_resume - PCI callback for waking up from D3
10621 * @pdev: PCI device information struct
10622 **/
10623static int i40e_resume(struct pci_dev *pdev)
10624{
10625 struct i40e_pf *pf = pci_get_drvdata(pdev);
10626 u32 err;
10627
10628 pci_set_power_state(pdev, PCI_D0);
10629 pci_restore_state(pdev);
10630 /* pci_restore_state() clears dev->state_saves, so
10631 * call pci_save_state() again to restore it.
10632 */
10633 pci_save_state(pdev);
10634
10635 err = pci_enable_device_mem(pdev);
10636 if (err) {
10637 dev_err(&pdev->dev,
10638 "%s: Cannot enable PCI device from suspend\n",
10639 __func__);
10640 return err;
10641 }
10642 pci_set_master(pdev);
10643
10644 /* no wakeup events while running */
10645 pci_wake_from_d3(pdev, false);
10646
10647 /* handling the reset will rebuild the device state */
10648 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10649 clear_bit(__I40E_DOWN, &pf->state);
10650 rtnl_lock();
10651 i40e_reset_and_rebuild(pf, false);
10652 rtnl_unlock();
10653 }
10654
10655 return 0;
10656}
10657
10658#endif
41c445ff
JB		 10659static const struct pci_error_handlers i40e_err_handler = {
10660 .error_detected = i40e_pci_error_detected,
10661 .slot_reset = i40e_pci_error_slot_reset,
10662 .resume = i40e_pci_error_resume,
10663};
10664
10665static struct pci_driver i40e_driver = {
10666 .name = i40e_driver_name,
10667 .id_table = i40e_pci_tbl,
10668 .probe = i40e_probe,
10669 .remove = i40e_remove,
9007bccd
SN		 10670#ifdef CONFIG_PM
10671 .suspend = i40e_suspend,
10672 .resume = i40e_resume,
10673#endif
10674 .shutdown = i40e_shutdown,
41c445ff
JB		 10675 .err_handler = &i40e_err_handler,
10676 .sriov_configure = i40e_pci_sriov_configure,
10677};
10678
10679/**
10680 * i40e_init_module - Driver registration routine
10681 *
10682 * i40e_init_module is the first routine called when the driver is
10683 * loaded. All it does is register with the PCI subsystem.
10684 **/
10685static int __init i40e_init_module(void)
10686{
10687 pr_info("%s: %s - version %s\n", i40e_driver_name,
10688 i40e_driver_string, i40e_driver_version_str);
10689 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10690
41c445ff
JB		 10691 i40e_dbg_init();
10692 return pci_register_driver(&i40e_driver);
10693}
10694module_init(i40e_init_module);
10695
10696/**
10697 * i40e_exit_module - Driver exit cleanup routine
10698 *
10699 * i40e_exit_module is called just before the driver is removed
10700 * from memory.
10701 **/
10702static void __exit i40e_exit_module(void)
10703{
10704 pci_unregister_driver(&i40e_driver);
10705 i40e_dbg_exit();
10706}
10707module_exit(i40e_exit_module);
Linux kernel - Deliverables
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