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i40e: APIs to Add/remove port mirroring rules
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
b499ffb0
SV		 27#include <linux/etherdevice.h>
28#include <linux/of_net.h>
29#include <linux/pci.h>
30
31#ifdef CONFIG_SPARC
32#include <asm/idprom.h>
33#include <asm/prom.h>
34#endif
35
41c445ff
JB		 36/* Local includes */
37#include "i40e.h"
4eb3f768 38#include "i40e_diag.h"
6a899024 39#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 40#include <net/vxlan.h>
41#endif
6a899024
SA		 42#if IS_ENABLED(CONFIG_GENEVE)
43#include <net/geneve.h>
44#endif
41c445ff
JB		 45
46const char i40e_driver_name[] = "i40e";
47static const char i40e_driver_string[] =
48 "Intel(R) Ethernet Connection XL710 Network Driver";
49
50#define DRV_KERN "-k"
51
e8e724db 52#define DRV_VERSION_MAJOR 1
1c2df9e5 53#define DRV_VERSION_MINOR 4
82f399c9 54#define DRV_VERSION_BUILD 11
41c445ff
JB		 55#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
56 __stringify(DRV_VERSION_MINOR) "." \
57 __stringify(DRV_VERSION_BUILD) DRV_KERN
58const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 59static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 60
61/* a bit of forward declarations */
62static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
63static void i40e_handle_reset_warning(struct i40e_pf *pf);
64static int i40e_add_vsi(struct i40e_vsi *vsi);
65static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 66static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 67static int i40e_setup_misc_vector(struct i40e_pf *pf);
68static void i40e_determine_queue_usage(struct i40e_pf *pf);
69static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 70static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
71 u16 rss_table_size, u16 rss_size);
cbf61325 72static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 73static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 74
75/* i40e_pci_tbl - PCI Device ID Table
76 *
77 * Last entry must be all 0s
78 *
79 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
80 * Class, Class Mask, private data (not used) }
81 */
9baa3c34 82static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e 84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
ab60085e
SN		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 91 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 92 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
35dae51d
ASJ		 93 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
94 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
87e6c1d7
ASJ		 95 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
96 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
97 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 98 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
99 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 100 /* required last entry */
101 {0, }
102};
103MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
104
105#define I40E_MAX_VF_COUNT 128
106static int debug = -1;
107module_param(debug, int, 0);
108MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
109
110MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
111MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
2803b16c
JB		 115static struct workqueue_struct *i40e_wq;
116
41c445ff
JB		 117/**
118 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
119 * @hw: pointer to the HW structure
120 * @mem: ptr to mem struct to fill out
121 * @size: size of memory requested
122 * @alignment: what to align the allocation to
123 **/
124int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
125 u64 size, u32 alignment)
126{
127 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
128
129 mem->size = ALIGN(size, alignment);
130 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
131 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 132 if (!mem->va)
133 return -ENOMEM;
41c445ff 134
93bc73b8 135 return 0;
41c445ff
JB		 136}
137
138/**
139 * i40e_free_dma_mem_d - OS specific memory free for shared code
140 * @hw: pointer to the HW structure
141 * @mem: ptr to mem struct to free
142 **/
143int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
144{
145 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
146
147 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
148 mem->va = NULL;
149 mem->pa = 0;
150 mem->size = 0;
151
152 return 0;
153}
154
155/**
156 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
157 * @hw: pointer to the HW structure
158 * @mem: ptr to mem struct to fill out
159 * @size: size of memory requested
160 **/
161int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
162 u32 size)
163{
164 mem->size = size;
165 mem->va = kzalloc(size, GFP_KERNEL);
166
93bc73b8
JB		 167 if (!mem->va)
168 return -ENOMEM;
41c445ff 169
93bc73b8 170 return 0;
41c445ff
JB		 171}
172
173/**
174 * i40e_free_virt_mem_d - OS specific memory free for shared code
175 * @hw: pointer to the HW structure
176 * @mem: ptr to mem struct to free
177 **/
178int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
179{
180 /* it's ok to kfree a NULL pointer */
181 kfree(mem->va);
182 mem->va = NULL;
183 mem->size = 0;
184
185 return 0;
186}
187
188/**
189 * i40e_get_lump - find a lump of free generic resource
190 * @pf: board private structure
191 * @pile: the pile of resource to search
192 * @needed: the number of items needed
193 * @id: an owner id to stick on the items assigned
194 *
195 * Returns the base item index of the lump, or negative for error
196 *
197 * The search_hint trick and lack of advanced fit-finding only work
198 * because we're highly likely to have all the same size lump requests.
199 * Linear search time and any fragmentation should be minimal.
200 **/
201static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
202 u16 needed, u16 id)
203{
204 int ret = -ENOMEM;
ddf434ac 205 int i, j;
41c445ff
JB		 206
207 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
208 dev_info(&pf->pdev->dev,
209 "param err: pile=%p needed=%d id=0x%04x\n",
210 pile, needed, id);
211 return -EINVAL;
212 }
213
214 /* start the linear search with an imperfect hint */
215 i = pile->search_hint;
ddf434ac 216 while (i < pile->num_entries) {
41c445ff
JB		 217 /* skip already allocated entries */
218 if (pile->list[i] & I40E_PILE_VALID_BIT) {
219 i++;
220 continue;
221 }
222
223 /* do we have enough in this lump? */
224 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
225 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
226 break;
227 }
228
229 if (j == needed) {
230 /* there was enough, so assign it to the requestor */
231 for (j = 0; j < needed; j++)
232 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
233 ret = i;
234 pile->search_hint = i + j;
ddf434ac 235 break;
41c445ff 236 }
6995b36c
JB		 237
238 /* not enough, so skip over it and continue looking */
239 i += j;
41c445ff
JB		 240 }
241
242 return ret;
243}
244
245/**
246 * i40e_put_lump - return a lump of generic resource
247 * @pile: the pile of resource to search
248 * @index: the base item index
249 * @id: the owner id of the items assigned
250 *
251 * Returns the count of items in the lump
252 **/
253static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
254{
255 int valid_id = (id | I40E_PILE_VALID_BIT);
256 int count = 0;
257 int i;
258
259 if (!pile || index >= pile->num_entries)
260 return -EINVAL;
261
262 for (i = index;
263 i < pile->num_entries && pile->list[i] == valid_id;
264 i++) {
265 pile->list[i] = 0;
266 count++;
267 }
268
269 if (count && index < pile->search_hint)
270 pile->search_hint = index;
271
272 return count;
273}
274
fdf0e0bf
ASJ		 275/**
276 * i40e_find_vsi_from_id - searches for the vsi with the given id
277 * @pf - the pf structure to search for the vsi
278 * @id - id of the vsi it is searching for
279 **/
280struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
281{
282 int i;
283
284 for (i = 0; i < pf->num_alloc_vsi; i++)
285 if (pf->vsi[i] && (pf->vsi[i]->id == id))
286 return pf->vsi[i];
287
288 return NULL;
289}
290
41c445ff
JB		 291/**
292 * i40e_service_event_schedule - Schedule the service task to wake up
293 * @pf: board private structure
294 *
295 * If not already scheduled, this puts the task into the work queue
296 **/
297static void i40e_service_event_schedule(struct i40e_pf *pf)
298{
299 if (!test_bit(__I40E_DOWN, &pf->state) &&
300 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
301 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
2803b16c 302 queue_work(i40e_wq, &pf->service_task);
41c445ff
JB		 303}
304
305/**
306 * i40e_tx_timeout - Respond to a Tx Hang
307 * @netdev: network interface device structure
308 *
309 * If any port has noticed a Tx timeout, it is likely that the whole
310 * device is munged, not just the one netdev port, so go for the full
311 * reset.
312 **/
38e00438
VD		 313#ifdef I40E_FCOE
314void i40e_tx_timeout(struct net_device *netdev)
315#else
41c445ff 316static void i40e_tx_timeout(struct net_device *netdev)
38e00438 317#endif
41c445ff
JB		 318{
319 struct i40e_netdev_priv *np = netdev_priv(netdev);
320 struct i40e_vsi *vsi = np->vsi;
321 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 322 struct i40e_ring *tx_ring = NULL;
323 unsigned int i, hung_queue = 0;
324 u32 head, val;
41c445ff
JB		 325
326 pf->tx_timeout_count++;
327
b03a8c1f
KP		 328 /* find the stopped queue the same way the stack does */
329 for (i = 0; i < netdev->num_tx_queues; i++) {
330 struct netdev_queue *q;
331 unsigned long trans_start;
332
333 q = netdev_get_tx_queue(netdev, i);
334 trans_start = q->trans_start ? : netdev->trans_start;
335 if (netif_xmit_stopped(q) &&
336 time_after(jiffies,
337 (trans_start + netdev->watchdog_timeo))) {
338 hung_queue = i;
339 break;
340 }
341 }
342
343 if (i == netdev->num_tx_queues) {
344 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
345 } else {
346 /* now that we have an index, find the tx_ring struct */
347 for (i = 0; i < vsi->num_queue_pairs; i++) {
348 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
349 if (hung_queue ==
350 vsi->tx_rings[i]->queue_index) {
351 tx_ring = vsi->tx_rings[i];
352 break;
353 }
354 }
355 }
356 }
357
41c445ff 358 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 359 pf->tx_timeout_recovery_level = 1; /* reset after some time */
360 else if (time_before(jiffies,
361 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
362 return; /* don't do any new action before the next timeout */
363
364 if (tx_ring) {
365 head = i40e_get_head(tx_ring);
366 /* Read interrupt register */
367 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
368 val = rd32(&pf->hw,
369 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
370 tx_ring->vsi->base_vector - 1));
371 else
372 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
373
374 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
375 vsi->seid, hung_queue, tx_ring->next_to_clean,
376 head, tx_ring->next_to_use,
377 readl(tx_ring->tail), val);
378 }
379
41c445ff 380 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 381 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
382 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 383
384 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 385 case 1:
386 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
387 break;
388 case 2:
389 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
390 break;
391 case 3:
392 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
393 break;
394 default:
395 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 396 break;
397 }
b03a8c1f 398
41c445ff
JB		 399 i40e_service_event_schedule(pf);
400 pf->tx_timeout_recovery_level++;
401}
402
403/**
404 * i40e_release_rx_desc - Store the new tail and head values
405 * @rx_ring: ring to bump
406 * @val: new head index
407 **/
408static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
409{
410 rx_ring->next_to_use = val;
411
412 /* Force memory writes to complete before letting h/w
413 * know there are new descriptors to fetch. (Only
414 * applicable for weak-ordered memory model archs,
415 * such as IA-64).
416 */
417 wmb();
418 writel(val, rx_ring->tail);
419}
420
421/**
422 * i40e_get_vsi_stats_struct - Get System Network Statistics
423 * @vsi: the VSI we care about
424 *
425 * Returns the address of the device statistics structure.
426 * The statistics are actually updated from the service task.
427 **/
428struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
429{
430 return &vsi->net_stats;
431}
432
433/**
434 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
435 * @netdev: network interface device structure
436 *
437 * Returns the address of the device statistics structure.
438 * The statistics are actually updated from the service task.
439 **/
38e00438
VD		 440#ifdef I40E_FCOE
441struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
442 struct net_device *netdev,
443 struct rtnl_link_stats64 *stats)
444#else
41c445ff
JB		 445static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
446 struct net_device *netdev,
980e9b11 447 struct rtnl_link_stats64 *stats)
38e00438 448#endif
41c445ff
JB		 449{
450 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 451 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 452 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 453 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
454 int i;
455
bc7d338f
ASJ		 456 if (test_bit(__I40E_DOWN, &vsi->state))
457 return stats;
458
3c325ced
JB		 459 if (!vsi->tx_rings)
460 return stats;
461
980e9b11
AD		 462 rcu_read_lock();
463 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 464 u64 bytes, packets;
465 unsigned int start;
466
467 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
468 if (!tx_ring)
469 continue;
470
471 do {
57a7744e 472 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 473 packets = tx_ring->stats.packets;
474 bytes = tx_ring->stats.bytes;
57a7744e 475 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 476
477 stats->tx_packets += packets;
478 stats->tx_bytes += bytes;
479 rx_ring = &tx_ring[1];
480
481 do {
57a7744e 482 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 483 packets = rx_ring->stats.packets;
484 bytes = rx_ring->stats.bytes;
57a7744e 485 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 486
980e9b11
AD		 487 stats->rx_packets += packets;
488 stats->rx_bytes += bytes;
489 }
490 rcu_read_unlock();
491
a5282f44 492 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 493 stats->multicast = vsi_stats->multicast;
494 stats->tx_errors = vsi_stats->tx_errors;
495 stats->tx_dropped = vsi_stats->tx_dropped;
496 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 497 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 498 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
499 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 500
980e9b11 501 return stats;
41c445ff
JB		 502}
503
504/**
505 * i40e_vsi_reset_stats - Resets all stats of the given vsi
506 * @vsi: the VSI to have its stats reset
507 **/
508void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
509{
510 struct rtnl_link_stats64 *ns;
511 int i;
512
513 if (!vsi)
514 return;
515
516 ns = i40e_get_vsi_stats_struct(vsi);
517 memset(ns, 0, sizeof(*ns));
518 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
519 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
520 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 521 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 522 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 523 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 524 sizeof(vsi->rx_rings[i]->stats));
6995b36c 525 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 526 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 527 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 528 sizeof(vsi->tx_rings[i]->stats));
529 memset(&vsi->tx_rings[i]->tx_stats, 0,
530 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 531 }
8e9dca53 532 }
41c445ff
JB		 533 vsi->stat_offsets_loaded = false;
534}
535
536/**
b40c82e6 537 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 538 * @pf: the PF to be reset
539 **/
540void i40e_pf_reset_stats(struct i40e_pf *pf)
541{
e91fdf76
SN		 542 int i;
543
41c445ff
JB		 544 memset(&pf->stats, 0, sizeof(pf->stats));
545 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
546 pf->stat_offsets_loaded = false;
e91fdf76
SN		 547
548 for (i = 0; i < I40E_MAX_VEB; i++) {
549 if (pf->veb[i]) {
550 memset(&pf->veb[i]->stats, 0,
551 sizeof(pf->veb[i]->stats));
552 memset(&pf->veb[i]->stats_offsets, 0,
553 sizeof(pf->veb[i]->stats_offsets));
554 pf->veb[i]->stat_offsets_loaded = false;
555 }
556 }
41c445ff
JB		 557}
558
559/**
560 * i40e_stat_update48 - read and update a 48 bit stat from the chip
561 * @hw: ptr to the hardware info
562 * @hireg: the high 32 bit reg to read
563 * @loreg: the low 32 bit reg to read
564 * @offset_loaded: has the initial offset been loaded yet
565 * @offset: ptr to current offset value
566 * @stat: ptr to the stat
567 *
568 * Since the device stats are not reset at PFReset, they likely will not
569 * be zeroed when the driver starts. We'll save the first values read
570 * and use them as offsets to be subtracted from the raw values in order
571 * to report stats that count from zero. In the process, we also manage
572 * the potential roll-over.
573 **/
574static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
575 bool offset_loaded, u64 *offset, u64 *stat)
576{
577 u64 new_data;
578
ab60085e 579 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 580 new_data = rd32(hw, loreg);
581 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
582 } else {
583 new_data = rd64(hw, loreg);
584 }
585 if (!offset_loaded)
586 *offset = new_data;
587 if (likely(new_data >= *offset))
588 *stat = new_data - *offset;
589 else
41a1d04b 590 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 591 *stat &= 0xFFFFFFFFFFFFULL;
592}
593
594/**
595 * i40e_stat_update32 - read and update a 32 bit stat from the chip
596 * @hw: ptr to the hardware info
597 * @reg: the hw reg to read
598 * @offset_loaded: has the initial offset been loaded yet
599 * @offset: ptr to current offset value
600 * @stat: ptr to the stat
601 **/
602static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
603 bool offset_loaded, u64 *offset, u64 *stat)
604{
605 u32 new_data;
606
607 new_data = rd32(hw, reg);
608 if (!offset_loaded)
609 *offset = new_data;
610 if (likely(new_data >= *offset))
611 *stat = (u32)(new_data - *offset);
612 else
41a1d04b 613 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 614}
615
616/**
617 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
618 * @vsi: the VSI to be updated
619 **/
620void i40e_update_eth_stats(struct i40e_vsi *vsi)
621{
622 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
623 struct i40e_pf *pf = vsi->back;
624 struct i40e_hw *hw = &pf->hw;
625 struct i40e_eth_stats *oes;
626 struct i40e_eth_stats *es; /* device's eth stats */
627
628 es = &vsi->eth_stats;
629 oes = &vsi->eth_stats_offsets;
630
631 /* Gather up the stats that the hw collects */
632 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
633 vsi->stat_offsets_loaded,
634 &oes->tx_errors, &es->tx_errors);
635 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
636 vsi->stat_offsets_loaded,
637 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 638 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
639 vsi->stat_offsets_loaded,
640 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
641 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 644
645 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
646 I40E_GLV_GORCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->rx_bytes, &es->rx_bytes);
649 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
650 I40E_GLV_UPRCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->rx_unicast, &es->rx_unicast);
653 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
654 I40E_GLV_MPRCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->rx_multicast, &es->rx_multicast);
657 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
658 I40E_GLV_BPRCL(stat_idx),
659 vsi->stat_offsets_loaded,
660 &oes->rx_broadcast, &es->rx_broadcast);
661
662 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
663 I40E_GLV_GOTCL(stat_idx),
664 vsi->stat_offsets_loaded,
665 &oes->tx_bytes, &es->tx_bytes);
666 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
667 I40E_GLV_UPTCL(stat_idx),
668 vsi->stat_offsets_loaded,
669 &oes->tx_unicast, &es->tx_unicast);
670 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
671 I40E_GLV_MPTCL(stat_idx),
672 vsi->stat_offsets_loaded,
673 &oes->tx_multicast, &es->tx_multicast);
674 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
675 I40E_GLV_BPTCL(stat_idx),
676 vsi->stat_offsets_loaded,
677 &oes->tx_broadcast, &es->tx_broadcast);
678 vsi->stat_offsets_loaded = true;
679}
680
681/**
682 * i40e_update_veb_stats - Update Switch component statistics
683 * @veb: the VEB being updated
684 **/
685static void i40e_update_veb_stats(struct i40e_veb *veb)
686{
687 struct i40e_pf *pf = veb->pf;
688 struct i40e_hw *hw = &pf->hw;
689 struct i40e_eth_stats *oes;
690 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 691 struct i40e_veb_tc_stats *veb_oes;
692 struct i40e_veb_tc_stats *veb_es;
693 int i, idx = 0;
41c445ff
JB		 694
695 idx = veb->stats_idx;
696 es = &veb->stats;
697 oes = &veb->stats_offsets;
fe860afb
NP		 698 veb_es = &veb->tc_stats;
699 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 700
701 /* Gather up the stats that the hw collects */
702 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
703 veb->stat_offsets_loaded,
704 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 705 if (hw->revision_id > 0)
706 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
707 veb->stat_offsets_loaded,
708 &oes->rx_unknown_protocol,
709 &es->rx_unknown_protocol);
41c445ff
JB		 710 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
711 veb->stat_offsets_loaded,
712 &oes->rx_bytes, &es->rx_bytes);
713 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
714 veb->stat_offsets_loaded,
715 &oes->rx_unicast, &es->rx_unicast);
716 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
717 veb->stat_offsets_loaded,
718 &oes->rx_multicast, &es->rx_multicast);
719 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
720 veb->stat_offsets_loaded,
721 &oes->rx_broadcast, &es->rx_broadcast);
722
723 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
724 veb->stat_offsets_loaded,
725 &oes->tx_bytes, &es->tx_bytes);
726 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
727 veb->stat_offsets_loaded,
728 &oes->tx_unicast, &es->tx_unicast);
729 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
730 veb->stat_offsets_loaded,
731 &oes->tx_multicast, &es->tx_multicast);
732 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
733 veb->stat_offsets_loaded,
734 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 735 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
736 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
737 I40E_GLVEBTC_RPCL(i, idx),
738 veb->stat_offsets_loaded,
739 &veb_oes->tc_rx_packets[i],
740 &veb_es->tc_rx_packets[i]);
741 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
742 I40E_GLVEBTC_RBCL(i, idx),
743 veb->stat_offsets_loaded,
744 &veb_oes->tc_rx_bytes[i],
745 &veb_es->tc_rx_bytes[i]);
746 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
747 I40E_GLVEBTC_TPCL(i, idx),
748 veb->stat_offsets_loaded,
749 &veb_oes->tc_tx_packets[i],
750 &veb_es->tc_tx_packets[i]);
751 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
752 I40E_GLVEBTC_TBCL(i, idx),
753 veb->stat_offsets_loaded,
754 &veb_oes->tc_tx_bytes[i],
755 &veb_es->tc_tx_bytes[i]);
756 }
41c445ff
JB		 757 veb->stat_offsets_loaded = true;
758}
759
38e00438
VD		 760#ifdef I40E_FCOE
761/**
762 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
763 * @vsi: the VSI that is capable of doing FCoE
764 **/
765static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
766{
767 struct i40e_pf *pf = vsi->back;
768 struct i40e_hw *hw = &pf->hw;
769 struct i40e_fcoe_stats *ofs;
770 struct i40e_fcoe_stats *fs; /* device's eth stats */
771 int idx;
772
773 if (vsi->type != I40E_VSI_FCOE)
774 return;
775
776 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
777 fs = &vsi->fcoe_stats;
778 ofs = &vsi->fcoe_stats_offsets;
779
780 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
781 vsi->fcoe_stat_offsets_loaded,
782 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
783 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
784 vsi->fcoe_stat_offsets_loaded,
785 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
786 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
787 vsi->fcoe_stat_offsets_loaded,
788 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
789 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
790 vsi->fcoe_stat_offsets_loaded,
791 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
792 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
793 vsi->fcoe_stat_offsets_loaded,
794 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
795 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
796 vsi->fcoe_stat_offsets_loaded,
797 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
798 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
799 vsi->fcoe_stat_offsets_loaded,
800 &ofs->fcoe_last_error, &fs->fcoe_last_error);
801 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
802 vsi->fcoe_stat_offsets_loaded,
803 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
804
805 vsi->fcoe_stat_offsets_loaded = true;
806}
807
808#endif
41c445ff 809/**
7812fddc 810 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 811 * @vsi: the VSI to be updated
812 *
813 * There are a few instances where we store the same stat in a
814 * couple of different structs. This is partly because we have
815 * the netdev stats that need to be filled out, which is slightly
816 * different from the "eth_stats" defined by the chip and used in
7812fddc 817 * VF communications. We sort it out here.
41c445ff 818 **/
7812fddc 819static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 820{
821 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 822 struct rtnl_link_stats64 *ons;
823 struct rtnl_link_stats64 *ns; /* netdev stats */
824 struct i40e_eth_stats *oes;
825 struct i40e_eth_stats *es; /* device's eth stats */
826 u32 tx_restart, tx_busy;
bf00b376 827 struct i40e_ring *p;
41c445ff 828 u32 rx_page, rx_buf;
bf00b376
AA		 829 u64 bytes, packets;
830 unsigned int start;
2fc3d715 831 u64 tx_linearize;
164c9f54 832 u64 tx_force_wb;
41c445ff
JB		 833 u64 rx_p, rx_b;
834 u64 tx_p, tx_b;
41c445ff
JB		 835 u16 q;
836
837 if (test_bit(__I40E_DOWN, &vsi->state) ||
838 test_bit(__I40E_CONFIG_BUSY, &pf->state))
839 return;
840
841 ns = i40e_get_vsi_stats_struct(vsi);
842 ons = &vsi->net_stats_offsets;
843 es = &vsi->eth_stats;
844 oes = &vsi->eth_stats_offsets;
845
846 /* Gather up the netdev and vsi stats that the driver collects
847 * on the fly during packet processing
848 */
849 rx_b = rx_p = 0;
850 tx_b = tx_p = 0;
164c9f54 851 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
41c445ff
JB		 852 rx_page = 0;
853 rx_buf = 0;
980e9b11 854 rcu_read_lock();
41c445ff 855 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 856 /* locate Tx ring */
857 p = ACCESS_ONCE(vsi->tx_rings[q]);
858
859 do {
57a7744e 860 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 861 packets = p->stats.packets;
862 bytes = p->stats.bytes;
57a7744e 863 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 864 tx_b += bytes;
865 tx_p += packets;
866 tx_restart += p->tx_stats.restart_queue;
867 tx_busy += p->tx_stats.tx_busy;
2fc3d715 868 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 869 tx_force_wb += p->tx_stats.tx_force_wb;
41c445ff 870
980e9b11
AD		 871 /* Rx queue is part of the same block as Tx queue */
872 p = &p[1];
873 do {
57a7744e 874 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 875 packets = p->stats.packets;
876 bytes = p->stats.bytes;
57a7744e 877 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 878 rx_b += bytes;
879 rx_p += packets;
420136cc
MW		 880 rx_buf += p->rx_stats.alloc_buff_failed;
881 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 882 }
980e9b11 883 rcu_read_unlock();
41c445ff
JB		 884 vsi->tx_restart = tx_restart;
885 vsi->tx_busy = tx_busy;
2fc3d715 886 vsi->tx_linearize = tx_linearize;
164c9f54 887 vsi->tx_force_wb = tx_force_wb;
41c445ff
JB		 888 vsi->rx_page_failed = rx_page;
889 vsi->rx_buf_failed = rx_buf;
890
891 ns->rx_packets = rx_p;
892 ns->rx_bytes = rx_b;
893 ns->tx_packets = tx_p;
894 ns->tx_bytes = tx_b;
895
41c445ff 896 /* update netdev stats from eth stats */
7812fddc 897 i40e_update_eth_stats(vsi);
41c445ff
JB		 898 ons->tx_errors = oes->tx_errors;
899 ns->tx_errors = es->tx_errors;
900 ons->multicast = oes->rx_multicast;
901 ns->multicast = es->rx_multicast;
41a9e55c
SN		 902 ons->rx_dropped = oes->rx_discards;
903 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 904 ons->tx_dropped = oes->tx_discards;
905 ns->tx_dropped = es->tx_discards;
906
7812fddc 907 /* pull in a couple PF stats if this is the main vsi */
41c445ff 908 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 909 ns->rx_crc_errors = pf->stats.crc_errors;
910 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
911 ns->rx_length_errors = pf->stats.rx_length_errors;
912 }
913}
41c445ff 914
7812fddc 915/**
b40c82e6 916 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 917 * @pf: the PF to be updated
918 **/
919static void i40e_update_pf_stats(struct i40e_pf *pf)
920{
921 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
922 struct i40e_hw_port_stats *nsd = &pf->stats;
923 struct i40e_hw *hw = &pf->hw;
924 u32 val;
925 int i;
41c445ff 926
7812fddc
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
928 I40E_GLPRT_GORCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
931 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
932 I40E_GLPRT_GOTCL(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
935 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
936 pf->stat_offsets_loaded,
937 &osd->eth.rx_discards,
938 &nsd->eth.rx_discards);
532d283d
SN		 939 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
940 I40E_GLPRT_UPRCL(hw->port),
941 pf->stat_offsets_loaded,
942 &osd->eth.rx_unicast,
943 &nsd->eth.rx_unicast);
7812fddc
SN		 944 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
945 I40E_GLPRT_MPRCL(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->eth.rx_multicast,
948 &nsd->eth.rx_multicast);
532d283d
SN		 949 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
950 I40E_GLPRT_BPRCL(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->eth.rx_broadcast,
953 &nsd->eth.rx_broadcast);
954 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
955 I40E_GLPRT_UPTCL(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->eth.tx_unicast,
958 &nsd->eth.tx_unicast);
959 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
960 I40E_GLPRT_MPTCL(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->eth.tx_multicast,
963 &nsd->eth.tx_multicast);
964 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
965 I40E_GLPRT_BPTCL(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->eth.tx_broadcast,
968 &nsd->eth.tx_broadcast);
41c445ff 969
7812fddc
SN		 970 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->tx_dropped_link_down,
973 &nsd->tx_dropped_link_down);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->crc_errors, &nsd->crc_errors);
41c445ff 978
7812fddc
SN		 979 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
980 pf->stat_offsets_loaded,
981 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 982
7812fddc
SN		 983 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->mac_local_faults,
986 &nsd->mac_local_faults);
987 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->mac_remote_faults,
990 &nsd->mac_remote_faults);
41c445ff 991
7812fddc
SN		 992 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->rx_length_errors,
995 &nsd->rx_length_errors);
41c445ff 996
7812fddc
SN		 997 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
998 pf->stat_offsets_loaded,
999 &osd->link_xon_rx, &nsd->link_xon_rx);
1000 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1001 pf->stat_offsets_loaded,
1002 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 1003 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1004 pf->stat_offsets_loaded,
1005 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 1006 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1007 pf->stat_offsets_loaded,
1008 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1009
7812fddc 1010 for (i = 0; i < 8; i++) {
95db239f
NP		 1011 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1012 pf->stat_offsets_loaded,
1013 &osd->priority_xoff_rx[i],
1014 &nsd->priority_xoff_rx[i]);
7812fddc 1015 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1016 pf->stat_offsets_loaded,
7812fddc
SN		 1017 &osd->priority_xon_rx[i],
1018 &nsd->priority_xon_rx[i]);
1019 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1020 pf->stat_offsets_loaded,
7812fddc
SN		 1021 &osd->priority_xon_tx[i],
1022 &nsd->priority_xon_tx[i]);
1023 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1024 pf->stat_offsets_loaded,
7812fddc
SN		 1025 &osd->priority_xoff_tx[i],
1026 &nsd->priority_xoff_tx[i]);
1027 i40e_stat_update32(hw,
1028 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1029 pf->stat_offsets_loaded,
7812fddc
SN		 1030 &osd->priority_xon_2_xoff[i],
1031 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1032 }
1033
7812fddc
SN		 1034 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1035 I40E_GLPRT_PRC64L(hw->port),
1036 pf->stat_offsets_loaded,
1037 &osd->rx_size_64, &nsd->rx_size_64);
1038 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1039 I40E_GLPRT_PRC127L(hw->port),
1040 pf->stat_offsets_loaded,
1041 &osd->rx_size_127, &nsd->rx_size_127);
1042 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1043 I40E_GLPRT_PRC255L(hw->port),
1044 pf->stat_offsets_loaded,
1045 &osd->rx_size_255, &nsd->rx_size_255);
1046 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1047 I40E_GLPRT_PRC511L(hw->port),
1048 pf->stat_offsets_loaded,
1049 &osd->rx_size_511, &nsd->rx_size_511);
1050 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1051 I40E_GLPRT_PRC1023L(hw->port),
1052 pf->stat_offsets_loaded,
1053 &osd->rx_size_1023, &nsd->rx_size_1023);
1054 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1055 I40E_GLPRT_PRC1522L(hw->port),
1056 pf->stat_offsets_loaded,
1057 &osd->rx_size_1522, &nsd->rx_size_1522);
1058 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1059 I40E_GLPRT_PRC9522L(hw->port),
1060 pf->stat_offsets_loaded,
1061 &osd->rx_size_big, &nsd->rx_size_big);
1062
1063 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1064 I40E_GLPRT_PTC64L(hw->port),
1065 pf->stat_offsets_loaded,
1066 &osd->tx_size_64, &nsd->tx_size_64);
1067 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1068 I40E_GLPRT_PTC127L(hw->port),
1069 pf->stat_offsets_loaded,
1070 &osd->tx_size_127, &nsd->tx_size_127);
1071 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1072 I40E_GLPRT_PTC255L(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->tx_size_255, &nsd->tx_size_255);
1075 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1076 I40E_GLPRT_PTC511L(hw->port),
1077 pf->stat_offsets_loaded,
1078 &osd->tx_size_511, &nsd->tx_size_511);
1079 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1080 I40E_GLPRT_PTC1023L(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->tx_size_1023, &nsd->tx_size_1023);
1083 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1084 I40E_GLPRT_PTC1522L(hw->port),
1085 pf->stat_offsets_loaded,
1086 &osd->tx_size_1522, &nsd->tx_size_1522);
1087 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1088 I40E_GLPRT_PTC9522L(hw->port),
1089 pf->stat_offsets_loaded,
1090 &osd->tx_size_big, &nsd->tx_size_big);
1091
1092 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1093 pf->stat_offsets_loaded,
1094 &osd->rx_undersize, &nsd->rx_undersize);
1095 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1096 pf->stat_offsets_loaded,
1097 &osd->rx_fragments, &nsd->rx_fragments);
1098 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1099 pf->stat_offsets_loaded,
1100 &osd->rx_oversize, &nsd->rx_oversize);
1101 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1102 pf->stat_offsets_loaded,
1103 &osd->rx_jabber, &nsd->rx_jabber);
1104
433c47de 1105 /* FDIR stats */
0bf4b1b0
ASJ		 1106 i40e_stat_update32(hw,
1107 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1108 pf->stat_offsets_loaded,
1109 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1110 i40e_stat_update32(hw,
1111 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1112 pf->stat_offsets_loaded,
1113 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1114 i40e_stat_update32(hw,
1115 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1116 pf->stat_offsets_loaded,
1117 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1118
7812fddc
SN		 1119 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1120 nsd->tx_lpi_status =
1121 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1122 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1123 nsd->rx_lpi_status =
1124 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1125 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1126 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1127 pf->stat_offsets_loaded,
1128 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1129 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1130 pf->stat_offsets_loaded,
1131 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1132
d0389e51
ASJ		 1133 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1134 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1135 nsd->fd_sb_status = true;
1136 else
1137 nsd->fd_sb_status = false;
1138
1139 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1140 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1141 nsd->fd_atr_status = true;
1142 else
1143 nsd->fd_atr_status = false;
1144
41c445ff
JB		 1145 pf->stat_offsets_loaded = true;
1146}
1147
7812fddc
SN		 1148/**
1149 * i40e_update_stats - Update the various statistics counters.
1150 * @vsi: the VSI to be updated
1151 *
1152 * Update the various stats for this VSI and its related entities.
1153 **/
1154void i40e_update_stats(struct i40e_vsi *vsi)
1155{
1156 struct i40e_pf *pf = vsi->back;
1157
1158 if (vsi == pf->vsi[pf->lan_vsi])
1159 i40e_update_pf_stats(pf);
1160
1161 i40e_update_vsi_stats(vsi);
38e00438
VD		 1162#ifdef I40E_FCOE
1163 i40e_update_fcoe_stats(vsi);
1164#endif
7812fddc
SN		 1165}
1166
41c445ff
JB		 1167/**
1168 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1169 * @vsi: the VSI to be searched
1170 * @macaddr: the MAC address
1171 * @vlan: the vlan
b40c82e6 1172 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1173 * @is_netdev: make sure its a netdev filter, else doesn't matter
1174 *
1175 * Returns ptr to the filter object or NULL
1176 **/
1177static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1178 u8 *macaddr, s16 vlan,
1179 bool is_vf, bool is_netdev)
1180{
1181 struct i40e_mac_filter *f;
1182
1183 if (!vsi || !macaddr)
1184 return NULL;
1185
1186 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1187 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1188 (vlan == f->vlan) &&
1189 (!is_vf || f->is_vf) &&
1190 (!is_netdev || f->is_netdev))
1191 return f;
1192 }
1193 return NULL;
1194}
1195
1196/**
1197 * i40e_find_mac - Find a mac addr in the macvlan filters list
1198 * @vsi: the VSI to be searched
1199 * @macaddr: the MAC address we are searching for
b40c82e6 1200 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1201 * @is_netdev: make sure its a netdev filter, else doesn't matter
1202 *
1203 * Returns the first filter with the provided MAC address or NULL if
1204 * MAC address was not found
1205 **/
1206struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1207 bool is_vf, bool is_netdev)
1208{
1209 struct i40e_mac_filter *f;
1210
1211 if (!vsi || !macaddr)
1212 return NULL;
1213
1214 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1215 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1216 (!is_vf || f->is_vf) &&
1217 (!is_netdev || f->is_netdev))
1218 return f;
1219 }
1220 return NULL;
1221}
1222
1223/**
1224 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1225 * @vsi: the VSI to be searched
1226 *
1227 * Returns true if VSI is in vlan mode or false otherwise
1228 **/
1229bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1230{
1231 struct i40e_mac_filter *f;
1232
1233 /* Only -1 for all the filters denotes not in vlan mode
1234 * so we have to go through all the list in order to make sure
1235 */
1236 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1237 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1238 return true;
1239 }
1240
1241 return false;
1242}
1243
1244/**
1245 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1246 * @vsi: the VSI to be searched
1247 * @macaddr: the mac address to be filtered
b40c82e6 1248 * @is_vf: true if it is a VF
41c445ff
JB		 1249 * @is_netdev: true if it is a netdev
1250 *
1251 * Goes through all the macvlan filters and adds a
1252 * macvlan filter for each unique vlan that already exists
1253 *
1254 * Returns first filter found on success, else NULL
1255 **/
1256struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1257 bool is_vf, bool is_netdev)
1258{
1259 struct i40e_mac_filter *f;
1260
1261 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1262 if (vsi->info.pvid)
1263 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1264 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1265 is_vf, is_netdev)) {
1266 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1267 is_vf, is_netdev))
41c445ff
JB		 1268 return NULL;
1269 }
1270 }
1271
1272 return list_first_entry_or_null(&vsi->mac_filter_list,
1273 struct i40e_mac_filter, list);
1274}
1275
b36e9ab5
MW		 1276/**
1277 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1278 * @vsi: the VSI to be searched
1279 * @macaddr: the mac address to be removed
1280 * @is_vf: true if it is a VF
1281 * @is_netdev: true if it is a netdev
1282 *
1283 * Removes a given MAC address from a VSI, regardless of VLAN
1284 *
1285 * Returns 0 for success, or error
1286 **/
1287int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1288 bool is_vf, bool is_netdev)
1289{
1290 struct i40e_mac_filter *f = NULL;
1291 int changed = 0;
1292
1293 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1294 "Missing mac_filter_list_lock\n");
1295 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1296 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1297 (is_vf == f->is_vf) &&
1298 (is_netdev == f->is_netdev)) {
1299 f->counter--;
1300 f->changed = true;
1301 changed = 1;
1302 }
1303 }
1304 if (changed) {
1305 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1306 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1307 return 0;
1308 }
1309 return -ENOENT;
1310}
1311
8c27d42e
GR		 1312/**
1313 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1314 * @vsi: the PF Main VSI - inappropriate for any other VSI
1315 * @macaddr: the MAC address
30650cc5
SN		 1316 *
1317 * Some older firmware configurations set up a default promiscuous VLAN
1318 * filter that needs to be removed.
8c27d42e 1319 **/
30650cc5 1320static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1321{
1322 struct i40e_aqc_remove_macvlan_element_data element;
1323 struct i40e_pf *pf = vsi->back;
f1c7e72e 1324 i40e_status ret;
8c27d42e
GR		 1325
1326 /* Only appropriate for the PF main VSI */
1327 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1328 return -EINVAL;
8c27d42e 1329
30650cc5 1330 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1331 ether_addr_copy(element.mac_addr, macaddr);
1332 element.vlan_tag = 0;
1333 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1334 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1335 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1336 if (ret)
30650cc5
SN		 1337 return -ENOENT;
1338
1339 return 0;
8c27d42e
GR		 1340}
1341
41c445ff
JB		 1342/**
1343 * i40e_add_filter - Add a mac/vlan filter to the VSI
1344 * @vsi: the VSI to be searched
1345 * @macaddr: the MAC address
1346 * @vlan: the vlan
b40c82e6 1347 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1348 * @is_netdev: make sure its a netdev filter, else doesn't matter
1349 *
1350 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1351 *
1352 * NOTE: This function is expected to be called with mac_filter_list_lock
1353 * being held.
41c445ff
JB		 1354 **/
1355struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1356 u8 *macaddr, s16 vlan,
1357 bool is_vf, bool is_netdev)
1358{
1359 struct i40e_mac_filter *f;
1360
1361 if (!vsi || !macaddr)
1362 return NULL;
1363
1364 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1365 if (!f) {
1366 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1367 if (!f)
1368 goto add_filter_out;
1369
9a173901 1370 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1371 f->vlan = vlan;
1372 f->changed = true;
1373
1374 INIT_LIST_HEAD(&f->list);
04d5a21d 1375 list_add_tail(&f->list, &vsi->mac_filter_list);
41c445ff
JB		 1376 }
1377
1378 /* increment counter and add a new flag if needed */
1379 if (is_vf) {
1380 if (!f->is_vf) {
1381 f->is_vf = true;
1382 f->counter++;
1383 }
1384 } else if (is_netdev) {
1385 if (!f->is_netdev) {
1386 f->is_netdev = true;
1387 f->counter++;
1388 }
1389 } else {
1390 f->counter++;
1391 }
1392
1393 /* changed tells sync_filters_subtask to
1394 * push the filter down to the firmware
1395 */
1396 if (f->changed) {
1397 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1398 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1399 }
1400
1401add_filter_out:
1402 return f;
1403}
1404
1405/**
1406 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1407 * @vsi: the VSI to be searched
1408 * @macaddr: the MAC address
1409 * @vlan: the vlan
b40c82e6 1410 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1411 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1412 *
1413 * NOTE: This function is expected to be called with mac_filter_list_lock
1414 * being held.
41c445ff
JB		 1415 **/
1416void i40e_del_filter(struct i40e_vsi *vsi,
1417 u8 *macaddr, s16 vlan,
1418 bool is_vf, bool is_netdev)
1419{
1420 struct i40e_mac_filter *f;
1421
1422 if (!vsi || !macaddr)
1423 return;
1424
1425 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1426 if (!f || f->counter == 0)
1427 return;
1428
1429 if (is_vf) {
1430 if (f->is_vf) {
1431 f->is_vf = false;
1432 f->counter--;
1433 }
1434 } else if (is_netdev) {
1435 if (f->is_netdev) {
1436 f->is_netdev = false;
1437 f->counter--;
1438 }
1439 } else {
b40c82e6 1440 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1441 int min_f = 0;
6995b36c 1442
41c445ff
JB		 1443 min_f += (f->is_vf ? 1 : 0);
1444 min_f += (f->is_netdev ? 1 : 0);
1445
1446 if (f->counter > min_f)
1447 f->counter--;
1448 }
1449
1450 /* counter == 0 tells sync_filters_subtask to
1451 * remove the filter from the firmware's list
1452 */
1453 if (f->counter == 0) {
1454 f->changed = true;
1455 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1456 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1457 }
1458}
1459
1460/**
1461 * i40e_set_mac - NDO callback to set mac address
1462 * @netdev: network interface device structure
1463 * @p: pointer to an address structure
1464 *
1465 * Returns 0 on success, negative on failure
1466 **/
38e00438
VD		 1467#ifdef I40E_FCOE
1468int i40e_set_mac(struct net_device *netdev, void *p)
1469#else
41c445ff 1470static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1471#endif
41c445ff
JB		 1472{
1473 struct i40e_netdev_priv *np = netdev_priv(netdev);
1474 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1475 struct i40e_pf *pf = vsi->back;
1476 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1477 struct sockaddr *addr = p;
1478 struct i40e_mac_filter *f;
1479
1480 if (!is_valid_ether_addr(addr->sa_data))
1481 return -EADDRNOTAVAIL;
1482
30650cc5
SN		 1483 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1484 netdev_info(netdev, "already using mac address %pM\n",
1485 addr->sa_data);
1486 return 0;
1487 }
41c445ff 1488
80f6428f
ASJ		 1489 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1490 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1491 return -EADDRNOTAVAIL;
1492
30650cc5
SN		 1493 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1494 netdev_info(netdev, "returning to hw mac address %pM\n",
1495 hw->mac.addr);
1496 else
1497 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1498
41c445ff
JB		 1499 if (vsi->type == I40E_VSI_MAIN) {
1500 i40e_status ret;
6995b36c 1501
41c445ff 1502 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1503 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1504 addr->sa_data, NULL);
1505 if (ret) {
1506 netdev_info(netdev,
1507 "Addr change for Main VSI failed: %d\n",
1508 ret);
1509 return -EADDRNOTAVAIL;
1510 }
41c445ff
JB		 1511 }
1512
30650cc5
SN		 1513 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1514 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1515
30650cc5
SN		 1516 memset(&element, 0, sizeof(element));
1517 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1518 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1519 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1520 } else {
21659035 1521 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1522 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1523 false, false);
21659035 1524 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1525 }
41c445ff 1526
30650cc5
SN		 1527 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1528 struct i40e_aqc_add_macvlan_element_data element;
1529
1530 memset(&element, 0, sizeof(element));
1531 ether_addr_copy(element.mac_addr, hw->mac.addr);
1532 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1533 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1534 } else {
21659035 1535 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1536 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1537 false, false);
1538 if (f)
1539 f->is_laa = true;
21659035 1540 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1541 }
1542
30650cc5 1543 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b 1544
c53934c6
JB		 1545 /* schedule our worker thread which will take care of
1546 * applying the new filter changes
1547 */
1548 i40e_service_event_schedule(vsi->back);
1549 return 0;
41c445ff
JB		 1550}
1551
1552/**
1553 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1554 * @vsi: the VSI being setup
1555 * @ctxt: VSI context structure
1556 * @enabled_tc: Enabled TCs bitmap
1557 * @is_add: True if called before Add VSI
1558 *
1559 * Setup VSI queue mapping for enabled traffic classes.
1560 **/
38e00438
VD		 1561#ifdef I40E_FCOE
1562void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1563 struct i40e_vsi_context *ctxt,
1564 u8 enabled_tc,
1565 bool is_add)
1566#else
41c445ff
JB		 1567static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1568 struct i40e_vsi_context *ctxt,
1569 u8 enabled_tc,
1570 bool is_add)
38e00438 1571#endif
41c445ff
JB		 1572{
1573 struct i40e_pf *pf = vsi->back;
1574 u16 sections = 0;
1575 u8 netdev_tc = 0;
1576 u16 numtc = 0;
1577 u16 qcount;
1578 u8 offset;
1579 u16 qmap;
1580 int i;
4e3b35b0 1581 u16 num_tc_qps = 0;
41c445ff
JB		 1582
1583 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1584 offset = 0;
1585
1586 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1587 /* Find numtc from enabled TC bitmap */
1588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1589 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1590 numtc++;
1591 }
1592 if (!numtc) {
1593 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1594 numtc = 1;
1595 }
1596 } else {
1597 /* At least TC0 is enabled in case of non-DCB case */
1598 numtc = 1;
1599 }
1600
1601 vsi->tc_config.numtc = numtc;
1602 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1603 /* Number of queues per enabled TC */
7f9ff476
AS		 1604 /* In MFP case we can have a much lower count of MSIx
1605 * vectors available and so we need to lower the used
1606 * q count.
1607 */
26cdc443
ASJ		 1608 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1609 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1610 else
1611 qcount = vsi->alloc_queue_pairs;
7f9ff476 1612 num_tc_qps = qcount / numtc;
e25d00b8 1613 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1614
1615 /* Setup queue offset/count for all TCs for given VSI */
1616 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1617 /* See if the given TC is enabled for the given VSI */
75f5cea9 1618 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1619 /* TC is enabled */
41c445ff
JB		 1620 int pow, num_qps;
1621
41c445ff
JB		 1622 switch (vsi->type) {
1623 case I40E_VSI_MAIN:
acd65448
HZ		 1624 qcount = min_t(int, pf->alloc_rss_size,
1625 num_tc_qps);
41c445ff 1626 break;
38e00438
VD		 1627#ifdef I40E_FCOE
1628 case I40E_VSI_FCOE:
1629 qcount = num_tc_qps;
1630 break;
1631#endif
41c445ff
JB		 1632 case I40E_VSI_FDIR:
1633 case I40E_VSI_SRIOV:
1634 case I40E_VSI_VMDQ2:
1635 default:
4e3b35b0 1636 qcount = num_tc_qps;
41c445ff
JB		 1637 WARN_ON(i != 0);
1638 break;
1639 }
4e3b35b0
NP		 1640 vsi->tc_config.tc_info[i].qoffset = offset;
1641 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1642
1e200e4a 1643 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1644 num_qps = qcount;
41c445ff 1645 pow = 0;
41a1d04b 1646 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1647 pow++;
1648 num_qps >>= 1;
1649 }
1650
1651 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1652 qmap =
1653 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1654 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1655
4e3b35b0 1656 offset += qcount;
41c445ff
JB		 1657 } else {
1658 /* TC is not enabled so set the offset to
1659 * default queue and allocate one queue
1660 * for the given TC.
1661 */
1662 vsi->tc_config.tc_info[i].qoffset = 0;
1663 vsi->tc_config.tc_info[i].qcount = 1;
1664 vsi->tc_config.tc_info[i].netdev_tc = 0;
1665
1666 qmap = 0;
1667 }
1668 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1669 }
1670
1671 /* Set actual Tx/Rx queue pairs */
1672 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1673 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1674 if (vsi->req_queue_pairs > 0)
1675 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1676 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1677 vsi->num_queue_pairs = pf->num_lan_msix;
1678 }
41c445ff
JB		 1679
1680 /* Scheduler section valid can only be set for ADD VSI */
1681 if (is_add) {
1682 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1683
1684 ctxt->info.up_enable_bits = enabled_tc;
1685 }
1686 if (vsi->type == I40E_VSI_SRIOV) {
1687 ctxt->info.mapping_flags |=
1688 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1689 for (i = 0; i < vsi->num_queue_pairs; i++)
1690 ctxt->info.queue_mapping[i] =
1691 cpu_to_le16(vsi->base_queue + i);
1692 } else {
1693 ctxt->info.mapping_flags |=
1694 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1695 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1696 }
1697 ctxt->info.valid_sections |= cpu_to_le16(sections);
1698}
1699
1700/**
1701 * i40e_set_rx_mode - NDO callback to set the netdev filters
1702 * @netdev: network interface device structure
1703 **/
38e00438
VD		 1704#ifdef I40E_FCOE
1705void i40e_set_rx_mode(struct net_device *netdev)
1706#else
41c445ff 1707static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1708#endif
41c445ff
JB		 1709{
1710 struct i40e_netdev_priv *np = netdev_priv(netdev);
1711 struct i40e_mac_filter *f, *ftmp;
1712 struct i40e_vsi *vsi = np->vsi;
1713 struct netdev_hw_addr *uca;
1714 struct netdev_hw_addr *mca;
1715 struct netdev_hw_addr *ha;
1716
21659035
KP		 1717 spin_lock_bh(&vsi->mac_filter_list_lock);
1718
41c445ff
JB		 1719 /* add addr if not already in the filter list */
1720 netdev_for_each_uc_addr(uca, netdev) {
1721 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1722 if (i40e_is_vsi_in_vlan(vsi))
1723 i40e_put_mac_in_vlan(vsi, uca->addr,
1724 false, true);
1725 else
1726 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1727 false, true);
1728 }
1729 }
1730
1731 netdev_for_each_mc_addr(mca, netdev) {
1732 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1733 if (i40e_is_vsi_in_vlan(vsi))
1734 i40e_put_mac_in_vlan(vsi, mca->addr,
1735 false, true);
1736 else
1737 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1738 false, true);
1739 }
1740 }
1741
1742 /* remove filter if not in netdev list */
1743 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1744
1745 if (!f->is_netdev)
1746 continue;
1747
2f41f335
SN		 1748 netdev_for_each_mc_addr(mca, netdev)
1749 if (ether_addr_equal(mca->addr, f->macaddr))
1750 goto bottom_of_search_loop;
41c445ff 1751
2f41f335
SN		 1752 netdev_for_each_uc_addr(uca, netdev)
1753 if (ether_addr_equal(uca->addr, f->macaddr))
1754 goto bottom_of_search_loop;
1755
1756 for_each_dev_addr(netdev, ha)
1757 if (ether_addr_equal(ha->addr, f->macaddr))
1758 goto bottom_of_search_loop;
1759
1760 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1761 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1762
1763bottom_of_search_loop:
1764 continue;
41c445ff 1765 }
21659035 1766 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1767
1768 /* check for other flag changes */
1769 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1770 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1771 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1772 }
c53934c6
JB		 1773
1774 /* schedule our worker thread which will take care of
1775 * applying the new filter changes
1776 */
1777 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1778}
1779
21659035
KP		 1780/**
1781 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1782 * @src: source MAC filter entry to be clones
1783 *
1784 * Returns the pointer to newly cloned MAC filter entry or NULL
1785 * in case of error
1786 **/
1787static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1788 struct i40e_mac_filter *src)
1789{
1790 struct i40e_mac_filter *f;
1791
1792 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1793 if (!f)
1794 return NULL;
1795 *f = *src;
1796
1797 INIT_LIST_HEAD(&f->list);
1798
1799 return f;
1800}
1801
1802/**
1803 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1804 * @vsi: pointer to vsi struct
1805 * @from: Pointer to list which contains MAC filter entries - changes to
1806 * those entries needs to be undone.
1807 *
1808 * MAC filter entries from list were slated to be removed from device.
1809 **/
1810static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1811 struct list_head *from)
1812{
1813 struct i40e_mac_filter *f, *ftmp;
1814
1815 list_for_each_entry_safe(f, ftmp, from, list) {
1816 f->changed = true;
1817 /* Move the element back into MAC filter list*/
1818 list_move_tail(&f->list, &vsi->mac_filter_list);
1819 }
1820}
1821
1822/**
1823 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1824 * @vsi: pointer to vsi struct
1825 *
1826 * MAC filter entries from list were slated to be added from device.
1827 **/
1828static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1829{
1830 struct i40e_mac_filter *f, *ftmp;
1831
1832 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1833 if (!f->changed && f->counter)
1834 f->changed = true;
1835 }
1836}
1837
1838/**
1839 * i40e_cleanup_add_list - Deletes the element from add list and release
1840 * memory
1841 * @add_list: Pointer to list which contains MAC filter entries
1842 **/
1843static void i40e_cleanup_add_list(struct list_head *add_list)
1844{
1845 struct i40e_mac_filter *f, *ftmp;
1846
1847 list_for_each_entry_safe(f, ftmp, add_list, list) {
1848 list_del(&f->list);
1849 kfree(f);
1850 }
1851}
1852
41c445ff
JB		 1853/**
1854 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1855 * @vsi: ptr to the VSI
1856 *
1857 * Push any outstanding VSI filter changes through the AdminQ.
1858 *
1859 * Returns 0 or error value
1860 **/
17652c63 1861int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1862{
21659035
KP		 1863 struct list_head tmp_del_list, tmp_add_list;
1864 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1865 bool promisc_forced_on = false;
1866 bool add_happened = false;
1867 int filter_list_len = 0;
1868 u32 changed_flags = 0;
ea02e90b 1869 i40e_status aq_ret = 0;
21659035 1870 bool err_cond = false;
ea02e90b 1871 int retval = 0;
41c445ff
JB		 1872 struct i40e_pf *pf;
1873 int num_add = 0;
1874 int num_del = 0;
f1c7e72e 1875 int aq_err = 0;
41c445ff
JB		 1876 u16 cmd_flags;
1877
1878 /* empty array typed pointers, kcalloc later */
1879 struct i40e_aqc_add_macvlan_element_data *add_list;
1880 struct i40e_aqc_remove_macvlan_element_data *del_list;
1881
1882 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1883 usleep_range(1000, 2000);
1884 pf = vsi->back;
1885
1886 if (vsi->netdev) {
1887 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1888 vsi->current_netdev_flags = vsi->netdev->flags;
1889 }
1890
21659035
KP		 1891 INIT_LIST_HEAD(&tmp_del_list);
1892 INIT_LIST_HEAD(&tmp_add_list);
1893
41c445ff
JB		 1894 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1895 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1896
21659035 1897 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1898 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1899 if (!f->changed)
1900 continue;
1901
1902 if (f->counter != 0)
1903 continue;
1904 f->changed = false;
21659035
KP		 1905
1906 /* Move the element into temporary del_list */
1907 list_move_tail(&f->list, &tmp_del_list);
1908 }
1909
1910 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1911 if (!f->changed)
1912 continue;
1913
1914 if (f->counter == 0)
1915 continue;
1916 f->changed = false;
1917
1918 /* Clone MAC filter entry and add into temporary list */
1919 fclone = i40e_mac_filter_entry_clone(f);
1920 if (!fclone) {
1921 err_cond = true;
1922 break;
1923 }
1924 list_add_tail(&fclone->list, &tmp_add_list);
1925 }
1926
1927 /* if failed to clone MAC filter entry - undo */
1928 if (err_cond) {
1929 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1930 i40e_undo_add_filter_entries(vsi);
1931 }
1932 spin_unlock_bh(&vsi->mac_filter_list_lock);
1933
ea02e90b 1934 if (err_cond) {
21659035 1935 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1936 retval = -ENOMEM;
1937 goto out;
1938 }
21659035
KP		 1939 }
1940
1941 /* Now process 'del_list' outside the lock */
1942 if (!list_empty(&tmp_del_list)) {
f1199998
SN		 1943 int del_list_size;
1944
21659035
KP		 1945 filter_list_len = pf->hw.aq.asq_buf_size /
1946 sizeof(struct i40e_aqc_remove_macvlan_element_data);
f1199998
SN		 1947 del_list_size = filter_list_len *
1948 sizeof(struct i40e_aqc_remove_macvlan_element_data);
38c3cec7 1949 del_list = kzalloc(del_list_size, GFP_ATOMIC);
21659035
KP		 1950 if (!del_list) {
1951 i40e_cleanup_add_list(&tmp_add_list);
1952
1953 /* Undo VSI's MAC filter entry element updates */
1954 spin_lock_bh(&vsi->mac_filter_list_lock);
1955 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1956 i40e_undo_add_filter_entries(vsi);
1957 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1958 retval = -ENOMEM;
1959 goto out;
21659035
KP		 1960 }
1961
1962 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1963 cmd_flags = 0;
1964
1965 /* add to delete list */
9a173901 1966 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1967 del_list[num_del].vlan_tag =
1968 cpu_to_le16((u16)(f->vlan ==
1969 I40E_VLAN_ANY ? 0 : f->vlan));
1970
41c445ff
JB		 1971 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1972 del_list[num_del].flags = cmd_flags;
1973 num_del++;
1974
41c445ff
JB		 1975 /* flush a full buffer */
1976 if (num_del == filter_list_len) {
ea02e90b
MW		 1977 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1978 vsi->seid,
1979 del_list,
1980 num_del,
1981 NULL);
f1c7e72e 1982 aq_err = pf->hw.aq.asq_last_status;
41c445ff 1983 num_del = 0;
f1199998 1984 memset(del_list, 0, del_list_size);
41c445ff 1985
ea02e90b
MW		 1986 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1987 retval = -EIO;
21659035
KP		 1988 dev_err(&pf->pdev->dev,
1989 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
ea02e90b 1990 i40e_stat_str(&pf->hw, aq_ret),
21659035 1991 i40e_aq_str(&pf->hw, aq_err));
ea02e90b 1992 }
41c445ff 1993 }
21659035
KP		 1994 /* Release memory for MAC filter entries which were
1995 * synced up with HW.
1996 */
1997 list_del(&f->list);
1998 kfree(f);
41c445ff 1999 }
21659035 2000
41c445ff 2001 if (num_del) {
ea02e90b
MW		 2002 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
2003 del_list, num_del,
2004 NULL);
f1c7e72e 2005 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2006 num_del = 0;
2007
ea02e90b 2008 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 2009 dev_info(&pf->pdev->dev,
f1c7e72e 2010 "ignoring delete macvlan error, err %s aq_err %s\n",
ea02e90b 2011 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2012 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2013 }
2014
2015 kfree(del_list);
2016 del_list = NULL;
21659035
KP		 2017 }
2018
2019 if (!list_empty(&tmp_add_list)) {
f1199998 2020 int add_list_size;
41c445ff
JB		 2021
2022 /* do all the adds now */
2023 filter_list_len = pf->hw.aq.asq_buf_size /
2024 sizeof(struct i40e_aqc_add_macvlan_element_data),
f1199998
SN		 2025 add_list_size = filter_list_len *
2026 sizeof(struct i40e_aqc_add_macvlan_element_data);
38c3cec7 2027 add_list = kzalloc(add_list_size, GFP_ATOMIC);
21659035
KP		 2028 if (!add_list) {
2029 /* Purge element from temporary lists */
2030 i40e_cleanup_add_list(&tmp_add_list);
2031
2032 /* Undo add filter entries from VSI MAC filter list */
2033 spin_lock_bh(&vsi->mac_filter_list_lock);
2034 i40e_undo_add_filter_entries(vsi);
2035 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2036 retval = -ENOMEM;
2037 goto out;
21659035 2038 }
41c445ff 2039
21659035 2040 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2041
41c445ff
JB		 2042 add_happened = true;
2043 cmd_flags = 0;
2044
2045 /* add to add array */
9a173901 2046 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2047 add_list[num_add].vlan_tag =
2048 cpu_to_le16(
2049 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2050 add_list[num_add].queue_number = 0;
2051
2052 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2053 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2054 num_add++;
2055
2056 /* flush a full buffer */
2057 if (num_add == filter_list_len) {
ea02e90b
MW		 2058 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2059 add_list, num_add,
2060 NULL);
f1c7e72e 2061 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2062 num_add = 0;
2063
ea02e90b 2064 if (aq_ret)
41c445ff 2065 break;
f1199998 2066 memset(add_list, 0, add_list_size);
41c445ff 2067 }
21659035
KP		 2068 /* Entries from tmp_add_list were cloned from MAC
2069 * filter list, hence clean those cloned entries
2070 */
2071 list_del(&f->list);
2072 kfree(f);
41c445ff 2073 }
21659035 2074
41c445ff 2075 if (num_add) {
ea02e90b
MW		 2076 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2077 add_list, num_add, NULL);
f1c7e72e 2078 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2079 num_add = 0;
2080 }
2081 kfree(add_list);
2082 add_list = NULL;
2083
ea02e90b
MW		 2084 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2085 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2086 dev_info(&pf->pdev->dev,
f1c7e72e 2087 "add filter failed, err %s aq_err %s\n",
ea02e90b 2088 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2089 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2090 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2091 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2092 &vsi->state)) {
2093 promisc_forced_on = true;
2094 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2095 &vsi->state);
2096 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2097 }
2098 }
2099 }
2100
2101 /* check for changes in promiscuous modes */
2102 if (changed_flags & IFF_ALLMULTI) {
2103 bool cur_multipromisc;
6995b36c 2104
41c445ff 2105 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2106 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2107 vsi->seid,
2108 cur_multipromisc,
2109 NULL);
2110 if (aq_ret) {
2111 retval = i40e_aq_rc_to_posix(aq_ret,
2112 pf->hw.aq.asq_last_status);
41c445ff 2113 dev_info(&pf->pdev->dev,
f1c7e72e 2114 "set multi promisc failed, err %s aq_err %s\n",
ea02e90b 2115 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2116 i40e_aq_str(&pf->hw,
2117 pf->hw.aq.asq_last_status));
ea02e90b 2118 }
41c445ff
JB		 2119 }
2120 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2121 bool cur_promisc;
6995b36c 2122
41c445ff
JB		 2123 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2124 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2125 &vsi->state));
92faef85
ASJ		 2126 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
2127 /* set defport ON for Main VSI instead of true promisc
2128 * this way we will get all unicast/multicast and VLAN
2129 * promisc behavior but will not get VF or VMDq traffic
2130 * replicated on the Main VSI.
2131 */
2132 if (pf->cur_promisc != cur_promisc) {
2133 pf->cur_promisc = cur_promisc;
0e4425ed 2134 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2135 }
2136 } else {
ea02e90b 2137 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
92faef85 2138 &vsi->back->hw,
f1c7e72e
SN		 2139 vsi->seid,
2140 cur_promisc, NULL);
ea02e90b
MW		 2141 if (aq_ret) {
2142 retval =
2143 i40e_aq_rc_to_posix(aq_ret,
2144 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2145 dev_info(&pf->pdev->dev,
2146 "set unicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2147 aq_ret, pf->hw.aq.asq_last_status);
2148 }
2149 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
92faef85
ASJ		 2150 &vsi->back->hw,
2151 vsi->seid,
2152 cur_promisc, NULL);
ea02e90b
MW		 2153 if (aq_ret) {
2154 retval =
2155 i40e_aq_rc_to_posix(aq_ret,
2156 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2157 dev_info(&pf->pdev->dev,
2158 "set multicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2159 aq_ret, pf->hw.aq.asq_last_status);
2160 }
92faef85 2161 }
ea02e90b
MW		 2162 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2163 vsi->seid,
2164 cur_promisc, NULL);
2165 if (aq_ret) {
2166 retval = i40e_aq_rc_to_posix(aq_ret,
2167 pf->hw.aq.asq_last_status);
1a10370a 2168 dev_info(&pf->pdev->dev,
f1c7e72e 2169 "set brdcast promisc failed, err %s, aq_err %s\n",
ea02e90b 2170 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2171 i40e_aq_str(&pf->hw,
2172 pf->hw.aq.asq_last_status));
ea02e90b 2173 }
41c445ff 2174 }
ea02e90b 2175out:
41c445ff 2176 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2177 return retval;
41c445ff
JB		 2178}
2179
2180/**
2181 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2182 * @pf: board private structure
2183 **/
2184static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2185{
2186 int v;
2187
2188 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2189 return;
2190 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2191
505682cd 2192 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2193 if (pf->vsi[v] &&
17652c63
JB		 2194 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2195 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2196
2197 if (ret) {
2198 /* come back and try again later */
2199 pf->flags |= I40E_FLAG_FILTER_SYNC;
2200 break;
2201 }
2202 }
41c445ff
JB		 2203 }
2204}
2205
2206/**
2207 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2208 * @netdev: network interface device structure
2209 * @new_mtu: new value for maximum frame size
2210 *
2211 * Returns 0 on success, negative on failure
2212 **/
2213static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2214{
2215 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2216 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2217 struct i40e_vsi *vsi = np->vsi;
2218
2219 /* MTU < 68 is an error and causes problems on some kernels */
2220 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2221 return -EINVAL;
2222
2223 netdev_info(netdev, "changing MTU from %d to %d\n",
2224 netdev->mtu, new_mtu);
2225 netdev->mtu = new_mtu;
2226 if (netif_running(netdev))
2227 i40e_vsi_reinit_locked(vsi);
2228
2229 return 0;
2230}
2231
beb0dff1
JK		 2232/**
2233 * i40e_ioctl - Access the hwtstamp interface
2234 * @netdev: network interface device structure
2235 * @ifr: interface request data
2236 * @cmd: ioctl command
2237 **/
2238int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2239{
2240 struct i40e_netdev_priv *np = netdev_priv(netdev);
2241 struct i40e_pf *pf = np->vsi->back;
2242
2243 switch (cmd) {
2244 case SIOCGHWTSTAMP:
2245 return i40e_ptp_get_ts_config(pf, ifr);
2246 case SIOCSHWTSTAMP:
2247 return i40e_ptp_set_ts_config(pf, ifr);
2248 default:
2249 return -EOPNOTSUPP;
2250 }
2251}
2252
41c445ff
JB		 2253/**
2254 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2255 * @vsi: the vsi being adjusted
2256 **/
2257void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2258{
2259 struct i40e_vsi_context ctxt;
2260 i40e_status ret;
2261
2262 if ((vsi->info.valid_sections &
2263 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2264 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2265 return; /* already enabled */
2266
2267 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2268 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2269 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2270
2271 ctxt.seid = vsi->seid;
1a2f6248 2272 ctxt.info = vsi->info;
41c445ff
JB		 2273 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2274 if (ret) {
2275 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2276 "update vlan stripping failed, err %s aq_err %s\n",
2277 i40e_stat_str(&vsi->back->hw, ret),
2278 i40e_aq_str(&vsi->back->hw,
2279 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2280 }
2281}
2282
2283/**
2284 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2285 * @vsi: the vsi being adjusted
2286 **/
2287void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2288{
2289 struct i40e_vsi_context ctxt;
2290 i40e_status ret;
2291
2292 if ((vsi->info.valid_sections &
2293 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2294 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2295 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2296 return; /* already disabled */
2297
2298 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2299 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2300 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2301
2302 ctxt.seid = vsi->seid;
1a2f6248 2303 ctxt.info = vsi->info;
41c445ff
JB		 2304 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2305 if (ret) {
2306 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2307 "update vlan stripping failed, err %s aq_err %s\n",
2308 i40e_stat_str(&vsi->back->hw, ret),
2309 i40e_aq_str(&vsi->back->hw,
2310 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2311 }
2312}
2313
2314/**
2315 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2316 * @netdev: network interface to be adjusted
2317 * @features: netdev features to test if VLAN offload is enabled or not
2318 **/
2319static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2320{
2321 struct i40e_netdev_priv *np = netdev_priv(netdev);
2322 struct i40e_vsi *vsi = np->vsi;
2323
2324 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2325 i40e_vlan_stripping_enable(vsi);
2326 else
2327 i40e_vlan_stripping_disable(vsi);
2328}
2329
2330/**
2331 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2332 * @vsi: the vsi being configured
2333 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2334 **/
2335int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2336{
2337 struct i40e_mac_filter *f, *add_f;
2338 bool is_netdev, is_vf;
41c445ff
JB		 2339
2340 is_vf = (vsi->type == I40E_VSI_SRIOV);
2341 is_netdev = !!(vsi->netdev);
2342
21659035
KP		 2343 /* Locked once because all functions invoked below iterates list*/
2344 spin_lock_bh(&vsi->mac_filter_list_lock);
2345
41c445ff
JB		 2346 if (is_netdev) {
2347 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2348 is_vf, is_netdev);
2349 if (!add_f) {
2350 dev_info(&vsi->back->pdev->dev,
2351 "Could not add vlan filter %d for %pM\n",
2352 vid, vsi->netdev->dev_addr);
21659035 2353 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2354 return -ENOMEM;
2355 }
2356 }
2357
2358 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2359 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2360 if (!add_f) {
2361 dev_info(&vsi->back->pdev->dev,
2362 "Could not add vlan filter %d for %pM\n",
2363 vid, f->macaddr);
21659035 2364 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2365 return -ENOMEM;
2366 }
2367 }
2368
41c445ff
JB		 2369 /* Now if we add a vlan tag, make sure to check if it is the first
2370 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2371 * with 0, so we now accept untagged and specified tagged traffic
2372 * (and not any taged and untagged)
2373 */
2374 if (vid > 0) {
2375 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2376 I40E_VLAN_ANY,
2377 is_vf, is_netdev)) {
2378 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2379 I40E_VLAN_ANY, is_vf, is_netdev);
2380 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2381 is_vf, is_netdev);
2382 if (!add_f) {
2383 dev_info(&vsi->back->pdev->dev,
2384 "Could not add filter 0 for %pM\n",
2385 vsi->netdev->dev_addr);
21659035 2386 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2387 return -ENOMEM;
2388 }
2389 }
8d82a7c5 2390 }
41c445ff 2391
8d82a7c5
GR		 2392 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2393 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2394 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2395 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2396 is_vf, is_netdev))
2397 continue;
2398 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2399 is_vf, is_netdev);
2400 add_f = i40e_add_filter(vsi, f->macaddr,
2401 0, is_vf, is_netdev);
2402 if (!add_f) {
2403 dev_info(&vsi->back->pdev->dev,
2404 "Could not add filter 0 for %pM\n",
2405 f->macaddr);
2406 spin_unlock_bh(&vsi->mac_filter_list_lock);
2407 return -ENOMEM;
41c445ff
JB		 2408 }
2409 }
41c445ff
JB		 2410 }
2411
21659035
KP		 2412 spin_unlock_bh(&vsi->mac_filter_list_lock);
2413
0e4425ed
JB		 2414 /* schedule our worker thread which will take care of
2415 * applying the new filter changes
2416 */
2417 i40e_service_event_schedule(vsi->back);
2418 return 0;
41c445ff
JB		 2419}
2420
2421/**
2422 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2423 * @vsi: the vsi being configured
2424 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2425 *
2426 * Return: 0 on success or negative otherwise
41c445ff
JB		 2427 **/
2428int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2429{
2430 struct net_device *netdev = vsi->netdev;
2431 struct i40e_mac_filter *f, *add_f;
2432 bool is_vf, is_netdev;
2433 int filter_count = 0;
41c445ff
JB		 2434
2435 is_vf = (vsi->type == I40E_VSI_SRIOV);
2436 is_netdev = !!(netdev);
2437
21659035
KP		 2438 /* Locked once because all functions invoked below iterates list */
2439 spin_lock_bh(&vsi->mac_filter_list_lock);
2440
41c445ff
JB		 2441 if (is_netdev)
2442 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2443
2444 list_for_each_entry(f, &vsi->mac_filter_list, list)
2445 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2446
41c445ff
JB		 2447 /* go through all the filters for this VSI and if there is only
2448 * vid == 0 it means there are no other filters, so vid 0 must
2449 * be replaced with -1. This signifies that we should from now
2450 * on accept any traffic (with any tag present, or untagged)
2451 */
2452 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2453 if (is_netdev) {
2454 if (f->vlan &&
2455 ether_addr_equal(netdev->dev_addr, f->macaddr))
2456 filter_count++;
2457 }
2458
2459 if (f->vlan)
2460 filter_count++;
2461 }
2462
2463 if (!filter_count && is_netdev) {
2464 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2465 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2466 is_vf, is_netdev);
2467 if (!f) {
2468 dev_info(&vsi->back->pdev->dev,
2469 "Could not add filter %d for %pM\n",
2470 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2471 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2472 return -ENOMEM;
2473 }
2474 }
2475
2476 if (!filter_count) {
2477 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2478 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2479 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2480 is_vf, is_netdev);
41c445ff
JB		 2481 if (!add_f) {
2482 dev_info(&vsi->back->pdev->dev,
2483 "Could not add filter %d for %pM\n",
2484 I40E_VLAN_ANY, f->macaddr);
21659035 2485 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2486 return -ENOMEM;
2487 }
2488 }
2489 }
2490
21659035
KP		 2491 spin_unlock_bh(&vsi->mac_filter_list_lock);
2492
0e4425ed
JB		 2493 /* schedule our worker thread which will take care of
2494 * applying the new filter changes
2495 */
2496 i40e_service_event_schedule(vsi->back);
2497 return 0;
41c445ff
JB		 2498}
2499
2500/**
2501 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2502 * @netdev: network interface to be adjusted
2503 * @vid: vlan id to be added
078b5876
JB		 2504 *
2505 * net_device_ops implementation for adding vlan ids
41c445ff 2506 **/
38e00438
VD		 2507#ifdef I40E_FCOE
2508int i40e_vlan_rx_add_vid(struct net_device *netdev,
2509 __always_unused __be16 proto, u16 vid)
2510#else
41c445ff
JB		 2511static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2512 __always_unused __be16 proto, u16 vid)
38e00438 2513#endif
41c445ff
JB		 2514{
2515 struct i40e_netdev_priv *np = netdev_priv(netdev);
2516 struct i40e_vsi *vsi = np->vsi;
078b5876 2517 int ret = 0;
41c445ff
JB		 2518
2519 if (vid > 4095)
078b5876
JB		 2520 return -EINVAL;
2521
2522 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2523
6982d429
ASJ		 2524 /* If the network stack called us with vid = 0 then
2525 * it is asking to receive priority tagged packets with
2526 * vlan id 0. Our HW receives them by default when configured
2527 * to receive untagged packets so there is no need to add an
2528 * extra filter for vlan 0 tagged packets.
41c445ff 2529 */
6982d429
ASJ		 2530 if (vid)
2531 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2532
078b5876
JB		 2533 if (!ret && (vid < VLAN_N_VID))
2534 set_bit(vid, vsi->active_vlans);
41c445ff 2535
078b5876 2536 return ret;
41c445ff
JB		 2537}
2538
2539/**
2540 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2541 * @netdev: network interface to be adjusted
2542 * @vid: vlan id to be removed
078b5876 2543 *
fdfd943e 2544 * net_device_ops implementation for removing vlan ids
41c445ff 2545 **/
38e00438
VD		 2546#ifdef I40E_FCOE
2547int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2548 __always_unused __be16 proto, u16 vid)
2549#else
41c445ff
JB		 2550static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2551 __always_unused __be16 proto, u16 vid)
38e00438 2552#endif
41c445ff
JB		 2553{
2554 struct i40e_netdev_priv *np = netdev_priv(netdev);
2555 struct i40e_vsi *vsi = np->vsi;
2556
078b5876
JB		 2557 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2558
41c445ff
JB		 2559 /* return code is ignored as there is nothing a user
2560 * can do about failure to remove and a log message was
078b5876 2561 * already printed from the other function
41c445ff
JB		 2562 */
2563 i40e_vsi_kill_vlan(vsi, vid);
2564
2565 clear_bit(vid, vsi->active_vlans);
078b5876 2566
41c445ff
JB		 2567 return 0;
2568}
2569
2570/**
2571 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2572 * @vsi: the vsi being brought back up
2573 **/
2574static void i40e_restore_vlan(struct i40e_vsi *vsi)
2575{
2576 u16 vid;
2577
2578 if (!vsi->netdev)
2579 return;
2580
2581 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2582
2583 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2584 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2585 vid);
2586}
2587
2588/**
2589 * i40e_vsi_add_pvid - Add pvid for the VSI
2590 * @vsi: the vsi being adjusted
2591 * @vid: the vlan id to set as a PVID
2592 **/
dcae29be 2593int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2594{
2595 struct i40e_vsi_context ctxt;
f1c7e72e 2596 i40e_status ret;
41c445ff
JB		 2597
2598 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2599 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2600 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2601 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2602 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2603
2604 ctxt.seid = vsi->seid;
1a2f6248 2605 ctxt.info = vsi->info;
f1c7e72e
SN		 2606 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2607 if (ret) {
41c445ff 2608 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2609 "add pvid failed, err %s aq_err %s\n",
2610 i40e_stat_str(&vsi->back->hw, ret),
2611 i40e_aq_str(&vsi->back->hw,
2612 vsi->back->hw.aq.asq_last_status));
dcae29be 2613 return -ENOENT;
41c445ff
JB		 2614 }
2615
dcae29be 2616 return 0;
41c445ff
JB		 2617}
2618
2619/**
2620 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2621 * @vsi: the vsi being adjusted
2622 *
2623 * Just use the vlan_rx_register() service to put it back to normal
2624 **/
2625void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2626{
6c12fcbf
GR		 2627 i40e_vlan_stripping_disable(vsi);
2628
41c445ff 2629 vsi->info.pvid = 0;
41c445ff
JB		 2630}
2631
2632/**
2633 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2634 * @vsi: ptr to the VSI
2635 *
2636 * If this function returns with an error, then it's possible one or
2637 * more of the rings is populated (while the rest are not). It is the
2638 * callers duty to clean those orphaned rings.
2639 *
2640 * Return 0 on success, negative on failure
2641 **/
2642static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2643{
2644 int i, err = 0;
2645
2646 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2647 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2648
2649 return err;
2650}
2651
2652/**
2653 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2654 * @vsi: ptr to the VSI
2655 *
2656 * Free VSI's transmit software resources
2657 **/
2658static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2659{
2660 int i;
2661
8e9dca53
GR		 2662 if (!vsi->tx_rings)
2663 return;
2664
41c445ff 2665 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2666 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2667 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2668}
2669
2670/**
2671 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2672 * @vsi: ptr to the VSI
2673 *
2674 * If this function returns with an error, then it's possible one or
2675 * more of the rings is populated (while the rest are not). It is the
2676 * callers duty to clean those orphaned rings.
2677 *
2678 * Return 0 on success, negative on failure
2679 **/
2680static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2681{
2682 int i, err = 0;
2683
2684 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2685 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2686#ifdef I40E_FCOE
2687 i40e_fcoe_setup_ddp_resources(vsi);
2688#endif
41c445ff
JB		 2689 return err;
2690}
2691
2692/**
2693 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2694 * @vsi: ptr to the VSI
2695 *
2696 * Free all receive software resources
2697 **/
2698static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2699{
2700 int i;
2701
8e9dca53
GR		 2702 if (!vsi->rx_rings)
2703 return;
2704
41c445ff 2705 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2706 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2707 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2708#ifdef I40E_FCOE
2709 i40e_fcoe_free_ddp_resources(vsi);
2710#endif
41c445ff
JB		 2711}
2712
3ffa037d
NP		 2713/**
2714 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2715 * @ring: The Tx ring to configure
2716 *
2717 * This enables/disables XPS for a given Tx descriptor ring
2718 * based on the TCs enabled for the VSI that ring belongs to.
2719 **/
2720static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2721{
2722 struct i40e_vsi *vsi = ring->vsi;
2723 cpumask_var_t mask;
2724
9a660eea
JB		 2725 if (!ring->q_vector || !ring->netdev)
2726 return;
2727
2728 /* Single TC mode enable XPS */
2729 if (vsi->tc_config.numtc <= 1) {
2730 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2731 netif_set_xps_queue(ring->netdev,
2732 &ring->q_vector->affinity_mask,
2733 ring->queue_index);
9a660eea
JB		 2734 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2735 /* Disable XPS to allow selection based on TC */
2736 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2737 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2738 free_cpumask_var(mask);
3ffa037d 2739 }
0e4425ed
JB		 2740
2741 /* schedule our worker thread which will take care of
2742 * applying the new filter changes
2743 */
2744 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2745}
2746
41c445ff
JB		 2747/**
2748 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2749 * @ring: The Tx ring to configure
2750 *
2751 * Configure the Tx descriptor ring in the HMC context.
2752 **/
2753static int i40e_configure_tx_ring(struct i40e_ring *ring)
2754{
2755 struct i40e_vsi *vsi = ring->vsi;
2756 u16 pf_q = vsi->base_queue + ring->queue_index;
2757 struct i40e_hw *hw = &vsi->back->hw;
2758 struct i40e_hmc_obj_txq tx_ctx;
2759 i40e_status err = 0;
2760 u32 qtx_ctl = 0;
2761
2762 /* some ATR related tx ring init */
60ea5f83 2763 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2764 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2765 ring->atr_count = 0;
2766 } else {
2767 ring->atr_sample_rate = 0;
2768 }
2769
3ffa037d
NP		 2770 /* configure XPS */
2771 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2772
2773 /* clear the context structure first */
2774 memset(&tx_ctx, 0, sizeof(tx_ctx));
2775
2776 tx_ctx.new_context = 1;
2777 tx_ctx.base = (ring->dma / 128);
2778 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2779 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2780 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2781#ifdef I40E_FCOE
2782 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2783#endif
beb0dff1 2784 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2785 /* FDIR VSI tx ring can still use RS bit and writebacks */
2786 if (vsi->type != I40E_VSI_FDIR)
2787 tx_ctx.head_wb_ena = 1;
2788 tx_ctx.head_wb_addr = ring->dma +
2789 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2790
2791 /* As part of VSI creation/update, FW allocates certain
2792 * Tx arbitration queue sets for each TC enabled for
2793 * the VSI. The FW returns the handles to these queue
2794 * sets as part of the response buffer to Add VSI,
2795 * Update VSI, etc. AQ commands. It is expected that
2796 * these queue set handles be associated with the Tx
2797 * queues by the driver as part of the TX queue context
2798 * initialization. This has to be done regardless of
2799 * DCB as by default everything is mapped to TC0.
2800 */
2801 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2802 tx_ctx.rdylist_act = 0;
2803
2804 /* clear the context in the HMC */
2805 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2806 if (err) {
2807 dev_info(&vsi->back->pdev->dev,
2808 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2809 ring->queue_index, pf_q, err);
2810 return -ENOMEM;
2811 }
2812
2813 /* set the context in the HMC */
2814 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2815 if (err) {
2816 dev_info(&vsi->back->pdev->dev,
2817 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2818 ring->queue_index, pf_q, err);
2819 return -ENOMEM;
2820 }
2821
2822 /* Now associate this queue with this PCI function */
7a28d885 2823 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2824 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2825 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2826 I40E_QTX_CTL_VFVM_INDX_MASK;
2827 } else {
9d8bf547 2828 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2829 }
2830
13fd9774
SN		 2831 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2832 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2833 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2834 i40e_flush(hw);
2835
41c445ff
JB		 2836 /* cache tail off for easier writes later */
2837 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2838
2839 return 0;
2840}
2841
2842/**
2843 * i40e_configure_rx_ring - Configure a receive ring context
2844 * @ring: The Rx ring to configure
2845 *
2846 * Configure the Rx descriptor ring in the HMC context.
2847 **/
2848static int i40e_configure_rx_ring(struct i40e_ring *ring)
2849{
2850 struct i40e_vsi *vsi = ring->vsi;
2851 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2852 u16 pf_q = vsi->base_queue + ring->queue_index;
2853 struct i40e_hw *hw = &vsi->back->hw;
2854 struct i40e_hmc_obj_rxq rx_ctx;
2855 i40e_status err = 0;
2856
2857 ring->state = 0;
2858
2859 /* clear the context structure first */
2860 memset(&rx_ctx, 0, sizeof(rx_ctx));
2861
2862 ring->rx_buf_len = vsi->rx_buf_len;
2863 ring->rx_hdr_len = vsi->rx_hdr_len;
2864
2865 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2866 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2867
2868 rx_ctx.base = (ring->dma / 128);
2869 rx_ctx.qlen = ring->count;
2870
2871 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2872 set_ring_16byte_desc_enabled(ring);
2873 rx_ctx.dsize = 0;
2874 } else {
2875 rx_ctx.dsize = 1;
2876 }
2877
2878 rx_ctx.dtype = vsi->dtype;
2879 if (vsi->dtype) {
2880 set_ring_ps_enabled(ring);
2881 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2882 I40E_RX_SPLIT_IP |
2883 I40E_RX_SPLIT_TCP_UDP |
2884 I40E_RX_SPLIT_SCTP;
2885 } else {
2886 rx_ctx.hsplit_0 = 0;
2887 }
2888
2889 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2890 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2891 if (hw->revision_id == 0)
2892 rx_ctx.lrxqthresh = 0;
2893 else
2894 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2895 rx_ctx.crcstrip = 1;
2896 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2897 /* this controls whether VLAN is stripped from inner headers */
2898 rx_ctx.showiv = 0;
38e00438
VD		 2899#ifdef I40E_FCOE
2900 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2901#endif
acb3676b
CS		 2902 /* set the prefena field to 1 because the manual says to */
2903 rx_ctx.prefena = 1;
41c445ff
JB		 2904
2905 /* clear the context in the HMC */
2906 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2907 if (err) {
2908 dev_info(&vsi->back->pdev->dev,
2909 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2910 ring->queue_index, pf_q, err);
2911 return -ENOMEM;
2912 }
2913
2914 /* set the context in the HMC */
2915 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2916 if (err) {
2917 dev_info(&vsi->back->pdev->dev,
2918 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2919 ring->queue_index, pf_q, err);
2920 return -ENOMEM;
2921 }
2922
2923 /* cache tail for quicker writes, and clear the reg before use */
2924 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2925 writel(0, ring->tail);
2926
a132af24
MW		 2927 if (ring_is_ps_enabled(ring)) {
2928 i40e_alloc_rx_headers(ring);
2929 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2930 } else {
2931 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2932 }
41c445ff
JB		 2933
2934 return 0;
2935}
2936
2937/**
2938 * i40e_vsi_configure_tx - Configure the VSI for Tx
2939 * @vsi: VSI structure describing this set of rings and resources
2940 *
2941 * Configure the Tx VSI for operation.
2942 **/
2943static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2944{
2945 int err = 0;
2946 u16 i;
2947
9f65e15b
AD		 2948 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2949 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2950
2951 return err;
2952}
2953
2954/**
2955 * i40e_vsi_configure_rx - Configure the VSI for Rx
2956 * @vsi: the VSI being configured
2957 *
2958 * Configure the Rx VSI for operation.
2959 **/
2960static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2961{
2962 int err = 0;
2963 u16 i;
2964
2965 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2966 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2967 + ETH_FCS_LEN + VLAN_HLEN;
2968 else
2969 vsi->max_frame = I40E_RXBUFFER_2048;
2970
2971 /* figure out correct receive buffer length */
2972 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2973 I40E_FLAG_RX_PS_ENABLED)) {
2974 case I40E_FLAG_RX_1BUF_ENABLED:
2975 vsi->rx_hdr_len = 0;
2976 vsi->rx_buf_len = vsi->max_frame;
2977 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2978 break;
2979 case I40E_FLAG_RX_PS_ENABLED:
2980 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2981 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2982 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2983 break;
2984 default:
2985 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2986 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2987 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2988 break;
2989 }
2990
38e00438
VD		 2991#ifdef I40E_FCOE
2992 /* setup rx buffer for FCoE */
2993 if ((vsi->type == I40E_VSI_FCOE) &&
2994 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2995 vsi->rx_hdr_len = 0;
2996 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2997 vsi->max_frame = I40E_RXBUFFER_3072;
2998 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2999 }
3000
3001#endif /* I40E_FCOE */
41c445ff
JB		 3002 /* round up for the chip's needs */
3003 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 3004 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 3005 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 3006 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 3007
3008 /* set up individual rings */
3009 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 3010 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3011
3012 return err;
3013}
3014
3015/**
3016 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
3017 * @vsi: ptr to the VSI
3018 **/
3019static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
3020{
e7046ee1 3021 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 3022 u16 qoffset, qcount;
3023 int i, n;
3024
cd238a3e
PN		 3025 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3026 /* Reset the TC information */
3027 for (i = 0; i < vsi->num_queue_pairs; i++) {
3028 rx_ring = vsi->rx_rings[i];
3029 tx_ring = vsi->tx_rings[i];
3030 rx_ring->dcb_tc = 0;
3031 tx_ring->dcb_tc = 0;
3032 }
3033 }
41c445ff
JB		 3034
3035 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3036 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3037 continue;
3038
3039 qoffset = vsi->tc_config.tc_info[n].qoffset;
3040 qcount = vsi->tc_config.tc_info[n].qcount;
3041 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3042 rx_ring = vsi->rx_rings[i];
3043 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3044 rx_ring->dcb_tc = n;
3045 tx_ring->dcb_tc = n;
3046 }
3047 }
3048}
3049
3050/**
3051 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3052 * @vsi: ptr to the VSI
3053 **/
3054static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3055{
3056 if (vsi->netdev)
3057 i40e_set_rx_mode(vsi->netdev);
3058}
3059
17a73f6b
JG		 3060/**
3061 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3062 * @vsi: Pointer to the targeted VSI
3063 *
3064 * This function replays the hlist on the hw where all the SB Flow Director
3065 * filters were saved.
3066 **/
3067static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3068{
3069 struct i40e_fdir_filter *filter;
3070 struct i40e_pf *pf = vsi->back;
3071 struct hlist_node *node;
3072
55a5e60b
ASJ		 3073 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3074 return;
3075
17a73f6b
JG		 3076 hlist_for_each_entry_safe(filter, node,
3077 &pf->fdir_filter_list, fdir_node) {
3078 i40e_add_del_fdir(vsi, filter, true);
3079 }
3080}
3081
41c445ff
JB		 3082/**
3083 * i40e_vsi_configure - Set up the VSI for action
3084 * @vsi: the VSI being configured
3085 **/
3086static int i40e_vsi_configure(struct i40e_vsi *vsi)
3087{
3088 int err;
3089
3090 i40e_set_vsi_rx_mode(vsi);
3091 i40e_restore_vlan(vsi);
3092 i40e_vsi_config_dcb_rings(vsi);
3093 err = i40e_vsi_configure_tx(vsi);
3094 if (!err)
3095 err = i40e_vsi_configure_rx(vsi);
3096
3097 return err;
3098}
3099
3100/**
3101 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3102 * @vsi: the VSI being configured
3103 **/
3104static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3105{
3106 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3107 struct i40e_hw *hw = &pf->hw;
3108 u16 vector;
3109 int i, q;
41c445ff
JB		 3110 u32 qp;
3111
3112 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3113 * and PFINT_LNKLSTn registers, e.g.:
3114 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3115 */
3116 qp = vsi->base_queue;
3117 vector = vsi->base_vector;
493fb300 3118 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3119 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3120
ee2319cf 3121 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3122 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3123 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3124 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3125 q_vector->rx.itr);
3126 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3127 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3128 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3129 q_vector->tx.itr);
ac26fc13
JB		 3130 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3131 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3132
3133 /* Linked list for the queuepairs assigned to this vector */
3134 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3135 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3136 u32 val;
3137
41c445ff
JB		 3138 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3139 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3140 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3141 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3142 (I40E_QUEUE_TYPE_TX
3143 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3144
3145 wr32(hw, I40E_QINT_RQCTL(qp), val);
3146
3147 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3148 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3149 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3150 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3151 (I40E_QUEUE_TYPE_RX
3152 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3153
3154 /* Terminate the linked list */
3155 if (q == (q_vector->num_ringpairs - 1))
3156 val |= (I40E_QUEUE_END_OF_LIST
3157 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3158
3159 wr32(hw, I40E_QINT_TQCTL(qp), val);
3160 qp++;
3161 }
3162 }
3163
3164 i40e_flush(hw);
3165}
3166
3167/**
3168 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3169 * @hw: ptr to the hardware info
3170 **/
ab437b5a 3171static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3172{
ab437b5a 3173 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3174 u32 val;
3175
3176 /* clear things first */
3177 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3178 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3179
3180 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3181 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3182 I40E_PFINT_ICR0_ENA_GRST_MASK |
3183 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3184 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3185 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3186 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3187 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3188
0d8e1439
ASJ		 3189 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3190 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3191
ab437b5a
JK		 3192 if (pf->flags & I40E_FLAG_PTP)
3193 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3194
41c445ff
JB		 3195 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3196
3197 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3198 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3199 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3200
3201 /* OTHER_ITR_IDX = 0 */
3202 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3203}
3204
3205/**
3206 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3207 * @vsi: the VSI being configured
3208 **/
3209static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3210{
493fb300 3211 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3212 struct i40e_pf *pf = vsi->back;
3213 struct i40e_hw *hw = &pf->hw;
3214 u32 val;
3215
3216 /* set the ITR configuration */
ee2319cf 3217 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3218 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3219 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3220 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3221 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3222 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3223 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3224
ab437b5a 3225 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3226
3227 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3228 wr32(hw, I40E_PFINT_LNKLST0, 0);
3229
f29eaa3d 3230 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3231 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3232 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3233 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3234
3235 wr32(hw, I40E_QINT_RQCTL(0), val);
3236
3237 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3238 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3239 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3240
3241 wr32(hw, I40E_QINT_TQCTL(0), val);
3242 i40e_flush(hw);
3243}
3244
2ef28cfb
MW		 3245/**
3246 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3247 * @pf: board private structure
3248 **/
3249void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3250{
3251 struct i40e_hw *hw = &pf->hw;
3252
3253 wr32(hw, I40E_PFINT_DYN_CTL0,
3254 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3255 i40e_flush(hw);
3256}
3257
41c445ff
JB		 3258/**
3259 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3260 * @pf: board private structure
3261 **/
116a57d4 3262void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3263{
3264 struct i40e_hw *hw = &pf->hw;
3265 u32 val;
3266
3267 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3268 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3269 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3270
3271 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3272 i40e_flush(hw);
3273}
3274
5c2cebda
CW		 3275/**
3276 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3277 * @vsi: pointer to a vsi
03147773 3278 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3279 **/
3280void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3281{
3282 struct i40e_pf *pf = vsi->back;
3283 struct i40e_hw *hw = &pf->hw;
3284 u32 val;
3285
3286 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3287 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3288 i40e_flush(hw);
3289}
3290
41c445ff
JB		 3291/**
3292 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3293 * @irq: interrupt number
3294 * @data: pointer to a q_vector
3295 **/
3296static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3297{
3298 struct i40e_q_vector *q_vector = data;
3299
cd0b6fa6 3300 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3301 return IRQ_HANDLED;
3302
5d3465a1 3303 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3304
3305 return IRQ_HANDLED;
3306}
3307
41c445ff
JB		 3308/**
3309 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3310 * @vsi: the VSI being configured
3311 * @basename: name for the vector
3312 *
3313 * Allocates MSI-X vectors and requests interrupts from the kernel.
3314 **/
3315static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3316{
3317 int q_vectors = vsi->num_q_vectors;
3318 struct i40e_pf *pf = vsi->back;
3319 int base = vsi->base_vector;
3320 int rx_int_idx = 0;
3321 int tx_int_idx = 0;
3322 int vector, err;
3323
3324 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3325 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3326
cd0b6fa6 3327 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3328 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3329 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3330 tx_int_idx++;
cd0b6fa6 3331 } else if (q_vector->rx.ring) {
41c445ff
JB		 3332 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3333 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3334 } else if (q_vector->tx.ring) {
41c445ff
JB		 3335 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3336 "%s-%s-%d", basename, "tx", tx_int_idx++);
3337 } else {
3338 /* skip this unused q_vector */
3339 continue;
3340 }
3341 err = request_irq(pf->msix_entries[base + vector].vector,
3342 vsi->irq_handler,
3343 0,
3344 q_vector->name,
3345 q_vector);
3346 if (err) {
3347 dev_info(&pf->pdev->dev,
fb43201f 3348 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3349 goto free_queue_irqs;
3350 }
3351 /* assign the mask for this irq */
3352 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3353 &q_vector->affinity_mask);
3354 }
3355
63741846 3356 vsi->irqs_ready = true;
41c445ff
JB		 3357 return 0;
3358
3359free_queue_irqs:
3360 while (vector) {
3361 vector--;
3362 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3363 NULL);
3364 free_irq(pf->msix_entries[base + vector].vector,
3365 &(vsi->q_vectors[vector]));
3366 }
3367 return err;
3368}
3369
3370/**
3371 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3372 * @vsi: the VSI being un-configured
3373 **/
3374static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3375{
3376 struct i40e_pf *pf = vsi->back;
3377 struct i40e_hw *hw = &pf->hw;
3378 int base = vsi->base_vector;
3379 int i;
3380
3381 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3382 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3383 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3384 }
3385
3386 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3387 for (i = vsi->base_vector;
3388 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3389 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3390
3391 i40e_flush(hw);
3392 for (i = 0; i < vsi->num_q_vectors; i++)
3393 synchronize_irq(pf->msix_entries[i + base].vector);
3394 } else {
3395 /* Legacy and MSI mode - this stops all interrupt handling */
3396 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3397 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3398 i40e_flush(hw);
3399 synchronize_irq(pf->pdev->irq);
3400 }
3401}
3402
3403/**
3404 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3405 * @vsi: the VSI being configured
3406 **/
3407static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3408{
3409 struct i40e_pf *pf = vsi->back;
3410 int i;
3411
3412 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3413 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3414 i40e_irq_dynamic_enable(vsi, i);
3415 } else {
3416 i40e_irq_dynamic_enable_icr0(pf);
3417 }
3418
1022cb6c 3419 i40e_flush(&pf->hw);
41c445ff
JB		 3420 return 0;
3421}
3422
3423/**
3424 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3425 * @pf: board private structure
3426 **/
3427static void i40e_stop_misc_vector(struct i40e_pf *pf)
3428{
3429 /* Disable ICR 0 */
3430 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3431 i40e_flush(&pf->hw);
3432}
3433
3434/**
3435 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3436 * @irq: interrupt number
3437 * @data: pointer to a q_vector
3438 *
3439 * This is the handler used for all MSI/Legacy interrupts, and deals
3440 * with both queue and non-queue interrupts. This is also used in
3441 * MSIX mode to handle the non-queue interrupts.
3442 **/
3443static irqreturn_t i40e_intr(int irq, void *data)
3444{
3445 struct i40e_pf *pf = (struct i40e_pf *)data;
3446 struct i40e_hw *hw = &pf->hw;
5e823066 3447 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3448 u32 icr0, icr0_remaining;
3449 u32 val, ena_mask;
3450
3451 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3452 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3453
116a57d4
SN		 3454 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3455 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3456 goto enable_intr;
41c445ff 3457
cd92e72f
SN		 3458 /* if interrupt but no bits showing, must be SWINT */
3459 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3460 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3461 pf->sw_int_count++;
3462
0d8e1439
ASJ		 3463 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3464 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3465 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3466 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3467 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3468 }
3469
41c445ff
JB		 3470 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3471 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3472 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3473 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3474
3475 /* temporarily disable queue cause for NAPI processing */
3476 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3477
41c445ff
JB		 3478 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3479 wr32(hw, I40E_QINT_RQCTL(0), qval);
3480
3481 qval = rd32(hw, I40E_QINT_TQCTL(0));
3482 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3483 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3484
3485 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3486 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3487 }
3488
3489 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3490 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3491 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3492 }
3493
3494 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3495 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3496 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3497 }
3498
3499 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3500 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3501 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3502 }
3503
3504 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3505 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3506 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3507 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3508 val = rd32(hw, I40E_GLGEN_RSTAT);
3509 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3510 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3511 if (val == I40E_RESET_CORER) {
41c445ff 3512 pf->corer_count++;
4eb3f768 3513 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3514 pf->globr_count++;
4eb3f768 3515 } else if (val == I40E_RESET_EMPR) {
41c445ff 3516 pf->empr_count++;
9df42d1a 3517 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3518 }
41c445ff
JB		 3519 }
3520
9c010ee0
ASJ		 3521 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3522 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3523 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3524 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3525 rd32(hw, I40E_PFHMC_ERRORINFO),
3526 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3527 }
3528
beb0dff1
JK		 3529 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3530 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3531
3532 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3533 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3534 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3535 }
beb0dff1
JK		 3536 }
3537
41c445ff
JB		 3538 /* If a critical error is pending we have no choice but to reset the
3539 * device.
3540 * Report and mask out any remaining unexpected interrupts.
3541 */
3542 icr0_remaining = icr0 & ena_mask;
3543 if (icr0_remaining) {
3544 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3545 icr0_remaining);
9c010ee0 3546 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3547 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3548 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3549 dev_info(&pf->pdev->dev, "device will be reset\n");
3550 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3551 i40e_service_event_schedule(pf);
41c445ff
JB		 3552 }
3553 ena_mask &= ~icr0_remaining;
3554 }
5e823066 3555 ret = IRQ_HANDLED;
41c445ff 3556
5e823066 3557enable_intr:
41c445ff
JB		 3558 /* re-enable interrupt causes */
3559 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3560 if (!test_bit(__I40E_DOWN, &pf->state)) {
3561 i40e_service_event_schedule(pf);
3562 i40e_irq_dynamic_enable_icr0(pf);
3563 }
3564
5e823066 3565 return ret;
41c445ff
JB		 3566}
3567
cbf61325
ASJ		 3568/**
3569 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3570 * @tx_ring: tx ring to clean
3571 * @budget: how many cleans we're allowed
3572 *
3573 * Returns true if there's any budget left (e.g. the clean is finished)
3574 **/
3575static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3576{
3577 struct i40e_vsi *vsi = tx_ring->vsi;
3578 u16 i = tx_ring->next_to_clean;
3579 struct i40e_tx_buffer *tx_buf;
3580 struct i40e_tx_desc *tx_desc;
3581
3582 tx_buf = &tx_ring->tx_bi[i];
3583 tx_desc = I40E_TX_DESC(tx_ring, i);
3584 i -= tx_ring->count;
3585
3586 do {
3587 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3588
3589 /* if next_to_watch is not set then there is no work pending */
3590 if (!eop_desc)
3591 break;
3592
3593 /* prevent any other reads prior to eop_desc */
3594 read_barrier_depends();
3595
3596 /* if the descriptor isn't done, no work yet to do */
3597 if (!(eop_desc->cmd_type_offset_bsz &
3598 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3599 break;
3600
3601 /* clear next_to_watch to prevent false hangs */
3602 tx_buf->next_to_watch = NULL;
3603
49d7d933
ASJ		 3604 tx_desc->buffer_addr = 0;
3605 tx_desc->cmd_type_offset_bsz = 0;
3606 /* move past filter desc */
3607 tx_buf++;
3608 tx_desc++;
3609 i++;
3610 if (unlikely(!i)) {
3611 i -= tx_ring->count;
3612 tx_buf = tx_ring->tx_bi;
3613 tx_desc = I40E_TX_DESC(tx_ring, 0);
3614 }
cbf61325
ASJ		 3615 /* unmap skb header data */
3616 dma_unmap_single(tx_ring->dev,
3617 dma_unmap_addr(tx_buf, dma),
3618 dma_unmap_len(tx_buf, len),
3619 DMA_TO_DEVICE);
49d7d933
ASJ		 3620 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3621 kfree(tx_buf->raw_buf);
cbf61325 3622
49d7d933
ASJ		 3623 tx_buf->raw_buf = NULL;
3624 tx_buf->tx_flags = 0;
3625 tx_buf->next_to_watch = NULL;
cbf61325 3626 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3627 tx_desc->buffer_addr = 0;
3628 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3629
49d7d933 3630 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3631 tx_buf++;
3632 tx_desc++;
3633 i++;
3634 if (unlikely(!i)) {
3635 i -= tx_ring->count;
3636 tx_buf = tx_ring->tx_bi;
3637 tx_desc = I40E_TX_DESC(tx_ring, 0);
3638 }
3639
3640 /* update budget accounting */
3641 budget--;
3642 } while (likely(budget));
3643
3644 i += tx_ring->count;
3645 tx_ring->next_to_clean = i;
3646
6995b36c 3647 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3648 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3649
cbf61325
ASJ		 3650 return budget > 0;
3651}
3652
3653/**
3654 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3655 * @irq: interrupt number
3656 * @data: pointer to a q_vector
3657 **/
3658static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3659{
3660 struct i40e_q_vector *q_vector = data;
3661 struct i40e_vsi *vsi;
3662
3663 if (!q_vector->tx.ring)
3664 return IRQ_HANDLED;
3665
3666 vsi = q_vector->tx.ring->vsi;
3667 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3668
3669 return IRQ_HANDLED;
3670}
3671
41c445ff 3672/**
cd0b6fa6 3673 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3674 * @vsi: the VSI being configured
3675 * @v_idx: vector index
cd0b6fa6 3676 * @qp_idx: queue pair index
41c445ff 3677 **/
26cdc443 3678static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3679{
493fb300 3680 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3681 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3682 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3683
3684 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3685 tx_ring->next = q_vector->tx.ring;
3686 q_vector->tx.ring = tx_ring;
41c445ff 3687 q_vector->tx.count++;
cd0b6fa6
AD		 3688
3689 rx_ring->q_vector = q_vector;
3690 rx_ring->next = q_vector->rx.ring;
3691 q_vector->rx.ring = rx_ring;
3692 q_vector->rx.count++;
41c445ff
JB		 3693}
3694
3695/**
3696 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3697 * @vsi: the VSI being configured
3698 *
3699 * This function maps descriptor rings to the queue-specific vectors
3700 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3701 * one vector per queue pair, but on a constrained vector budget, we
3702 * group the queue pairs as "efficiently" as possible.
3703 **/
3704static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3705{
3706 int qp_remaining = vsi->num_queue_pairs;
3707 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3708 int num_ringpairs;
41c445ff
JB		 3709 int v_start = 0;
3710 int qp_idx = 0;
3711
3712 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3713 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3714 * It is also important to go through all the vectors available to be
3715 * sure that if we don't use all the vectors, that the remaining vectors
3716 * are cleared. This is especially important when decreasing the
3717 * number of queues in use.
41c445ff 3718 */
70114ec4 3719 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3720 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3721
3722 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3723
3724 q_vector->num_ringpairs = num_ringpairs;
3725
3726 q_vector->rx.count = 0;
3727 q_vector->tx.count = 0;
3728 q_vector->rx.ring = NULL;
3729 q_vector->tx.ring = NULL;
3730
3731 while (num_ringpairs--) {
26cdc443 3732 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3733 qp_idx++;
3734 qp_remaining--;
41c445ff
JB		 3735 }
3736 }
3737}
3738
3739/**
3740 * i40e_vsi_request_irq - Request IRQ from the OS
3741 * @vsi: the VSI being configured
3742 * @basename: name for the vector
3743 **/
3744static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3745{
3746 struct i40e_pf *pf = vsi->back;
3747 int err;
3748
3749 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3750 err = i40e_vsi_request_irq_msix(vsi, basename);
3751 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3752 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3753 pf->int_name, pf);
41c445ff
JB		 3754 else
3755 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3756 pf->int_name, pf);
41c445ff
JB		 3757
3758 if (err)
3759 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3760
3761 return err;
3762}
3763
3764#ifdef CONFIG_NET_POLL_CONTROLLER
3765/**
d89d967f 3766 * i40e_netpoll - A Polling 'interrupt' handler
41c445ff
JB		 3767 * @netdev: network interface device structure
3768 *
3769 * This is used by netconsole to send skbs without having to re-enable
3770 * interrupts. It's not called while the normal interrupt routine is executing.
3771 **/
38e00438
VD		 3772#ifdef I40E_FCOE
3773void i40e_netpoll(struct net_device *netdev)
3774#else
41c445ff 3775static void i40e_netpoll(struct net_device *netdev)
38e00438 3776#endif
41c445ff
JB		 3777{
3778 struct i40e_netdev_priv *np = netdev_priv(netdev);
3779 struct i40e_vsi *vsi = np->vsi;
3780 struct i40e_pf *pf = vsi->back;
3781 int i;
3782
3783 /* if interface is down do nothing */
3784 if (test_bit(__I40E_DOWN, &vsi->state))
3785 return;
3786
41c445ff
JB		 3787 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3788 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3789 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3790 } else {
3791 i40e_intr(pf->pdev->irq, netdev);
3792 }
41c445ff
JB		 3793}
3794#endif
3795
23527308
NP		 3796/**
3797 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3798 * @pf: the PF being configured
3799 * @pf_q: the PF queue
3800 * @enable: enable or disable state of the queue
3801 *
3802 * This routine will wait for the given Tx queue of the PF to reach the
3803 * enabled or disabled state.
3804 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3805 * multiple retries; else will return 0 in case of success.
3806 **/
3807static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3808{
3809 int i;
3810 u32 tx_reg;
3811
3812 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3813 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3814 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3815 break;
3816
f98a2006 3817 usleep_range(10, 20);
23527308
NP		 3818 }
3819 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3820 return -ETIMEDOUT;
3821
3822 return 0;
3823}
3824
41c445ff
JB		 3825/**
3826 * i40e_vsi_control_tx - Start or stop a VSI's rings
3827 * @vsi: the VSI being configured
3828 * @enable: start or stop the rings
3829 **/
3830static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3831{
3832 struct i40e_pf *pf = vsi->back;
3833 struct i40e_hw *hw = &pf->hw;
23527308 3834 int i, j, pf_q, ret = 0;
41c445ff
JB		 3835 u32 tx_reg;
3836
3837 pf_q = vsi->base_queue;
3838 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3839
3840 /* warn the TX unit of coming changes */
3841 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3842 if (!enable)
f98a2006 3843 usleep_range(10, 20);
351499ab 3844
6c5ef620 3845 for (j = 0; j < 50; j++) {
41c445ff 3846 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3847 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3848 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3849 break;
3850 usleep_range(1000, 2000);
3851 }
fda972f6 3852 /* Skip if the queue is already in the requested state */
7c122007 3853 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3854 continue;
41c445ff
JB		 3855
3856 /* turn on/off the queue */
c5c9eb9e
SN		 3857 if (enable) {
3858 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3859 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3860 } else {
41c445ff 3861 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3862 }
41c445ff
JB		 3863
3864 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3865 /* No waiting for the Tx queue to disable */
3866 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3867 continue;
41c445ff
JB		 3868
3869 /* wait for the change to finish */
23527308
NP		 3870 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3871 if (ret) {
3872 dev_info(&pf->pdev->dev,
fb43201f
SN		 3873 "VSI seid %d Tx ring %d %sable timeout\n",
3874 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3875 break;
41c445ff
JB		 3876 }
3877 }
3878
7134f9ce
JB		 3879 if (hw->revision_id == 0)
3880 mdelay(50);
23527308
NP		 3881 return ret;
3882}
3883
3884/**
3885 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3886 * @pf: the PF being configured
3887 * @pf_q: the PF queue
3888 * @enable: enable or disable state of the queue
3889 *
3890 * This routine will wait for the given Rx queue of the PF to reach the
3891 * enabled or disabled state.
3892 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3893 * multiple retries; else will return 0 in case of success.
3894 **/
3895static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3896{
3897 int i;
3898 u32 rx_reg;
3899
3900 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3901 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3902 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3903 break;
3904
f98a2006 3905 usleep_range(10, 20);
23527308
NP		 3906 }
3907 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3908 return -ETIMEDOUT;
7134f9ce 3909
41c445ff
JB		 3910 return 0;
3911}
3912
3913/**
3914 * i40e_vsi_control_rx - Start or stop a VSI's rings
3915 * @vsi: the VSI being configured
3916 * @enable: start or stop the rings
3917 **/
3918static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3919{
3920 struct i40e_pf *pf = vsi->back;
3921 struct i40e_hw *hw = &pf->hw;
23527308 3922 int i, j, pf_q, ret = 0;
41c445ff
JB		 3923 u32 rx_reg;
3924
3925 pf_q = vsi->base_queue;
3926 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3927 for (j = 0; j < 50; j++) {
41c445ff 3928 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3929 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3930 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3931 break;
3932 usleep_range(1000, 2000);
3933 }
41c445ff 3934
7c122007
CS		 3935 /* Skip if the queue is already in the requested state */
3936 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3937 continue;
41c445ff
JB		 3938
3939 /* turn on/off the queue */
3940 if (enable)
6c5ef620 3941 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3942 else
6c5ef620 3943 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3944 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3945
3946 /* wait for the change to finish */
23527308
NP		 3947 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3948 if (ret) {
3949 dev_info(&pf->pdev->dev,
fb43201f
SN		 3950 "VSI seid %d Rx ring %d %sable timeout\n",
3951 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3952 break;
41c445ff
JB		 3953 }
3954 }
3955
23527308 3956 return ret;
41c445ff
JB		 3957}
3958
3959/**
3960 * i40e_vsi_control_rings - Start or stop a VSI's rings
3961 * @vsi: the VSI being configured
3962 * @enable: start or stop the rings
3963 **/
fc18eaa0 3964int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3965{
3b867b28 3966 int ret = 0;
41c445ff
JB		 3967
3968 /* do rx first for enable and last for disable */
3969 if (request) {
3970 ret = i40e_vsi_control_rx(vsi, request);
3971 if (ret)
3972 return ret;
3973 ret = i40e_vsi_control_tx(vsi, request);
3974 } else {
3b867b28
ASJ		 3975 /* Ignore return value, we need to shutdown whatever we can */
3976 i40e_vsi_control_tx(vsi, request);
3977 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3978 }
3979
3980 return ret;
3981}
3982
3983/**
3984 * i40e_vsi_free_irq - Free the irq association with the OS
3985 * @vsi: the VSI being configured
3986 **/
3987static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3988{
3989 struct i40e_pf *pf = vsi->back;
3990 struct i40e_hw *hw = &pf->hw;
3991 int base = vsi->base_vector;
3992 u32 val, qp;
3993 int i;
3994
3995 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3996 if (!vsi->q_vectors)
3997 return;
3998
63741846
SN		 3999 if (!vsi->irqs_ready)
4000 return;
4001
4002 vsi->irqs_ready = false;
41c445ff
JB		 4003 for (i = 0; i < vsi->num_q_vectors; i++) {
4004 u16 vector = i + base;
4005
4006 /* free only the irqs that were actually requested */
78681b1f
SN		 4007 if (!vsi->q_vectors[i] ||
4008 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 4009 continue;
4010
4011 /* clear the affinity_mask in the IRQ descriptor */
4012 irq_set_affinity_hint(pf->msix_entries[vector].vector,
4013 NULL);
4014 free_irq(pf->msix_entries[vector].vector,
493fb300 4015 vsi->q_vectors[i]);
41c445ff
JB		 4016
4017 /* Tear down the interrupt queue link list
4018 *
4019 * We know that they come in pairs and always
4020 * the Rx first, then the Tx. To clear the
4021 * link list, stick the EOL value into the
4022 * next_q field of the registers.
4023 */
4024 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
4025 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4026 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4027 val |= I40E_QUEUE_END_OF_LIST
4028 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4029 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4030
4031 while (qp != I40E_QUEUE_END_OF_LIST) {
4032 u32 next;
4033
4034 val = rd32(hw, I40E_QINT_RQCTL(qp));
4035
4036 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4037 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4038 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4039 I40E_QINT_RQCTL_INTEVENT_MASK);
4040
4041 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4042 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4043
4044 wr32(hw, I40E_QINT_RQCTL(qp), val);
4045
4046 val = rd32(hw, I40E_QINT_TQCTL(qp));
4047
4048 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4049 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4050
4051 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4052 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4053 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4054 I40E_QINT_TQCTL_INTEVENT_MASK);
4055
4056 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4057 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4058
4059 wr32(hw, I40E_QINT_TQCTL(qp), val);
4060 qp = next;
4061 }
4062 }
4063 } else {
4064 free_irq(pf->pdev->irq, pf);
4065
4066 val = rd32(hw, I40E_PFINT_LNKLST0);
4067 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4068 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4069 val |= I40E_QUEUE_END_OF_LIST
4070 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4071 wr32(hw, I40E_PFINT_LNKLST0, val);
4072
4073 val = rd32(hw, I40E_QINT_RQCTL(qp));
4074 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4075 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4076 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4077 I40E_QINT_RQCTL_INTEVENT_MASK);
4078
4079 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4080 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4081
4082 wr32(hw, I40E_QINT_RQCTL(qp), val);
4083
4084 val = rd32(hw, I40E_QINT_TQCTL(qp));
4085
4086 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4087 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4088 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4089 I40E_QINT_TQCTL_INTEVENT_MASK);
4090
4091 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4092 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4093
4094 wr32(hw, I40E_QINT_TQCTL(qp), val);
4095 }
4096}
4097
493fb300
AD		 4098/**
4099 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4100 * @vsi: the VSI being configured
4101 * @v_idx: Index of vector to be freed
4102 *
4103 * This function frees the memory allocated to the q_vector. In addition if
4104 * NAPI is enabled it will delete any references to the NAPI struct prior
4105 * to freeing the q_vector.
4106 **/
4107static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4108{
4109 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4110 struct i40e_ring *ring;
493fb300
AD		 4111
4112 if (!q_vector)
4113 return;
4114
4115 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4116 i40e_for_each_ring(ring, q_vector->tx)
4117 ring->q_vector = NULL;
4118
4119 i40e_for_each_ring(ring, q_vector->rx)
4120 ring->q_vector = NULL;
493fb300
AD		 4121
4122 /* only VSI w/ an associated netdev is set up w/ NAPI */
4123 if (vsi->netdev)
4124 netif_napi_del(&q_vector->napi);
4125
4126 vsi->q_vectors[v_idx] = NULL;
4127
4128 kfree_rcu(q_vector, rcu);
4129}
4130
41c445ff
JB		 4131/**
4132 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4133 * @vsi: the VSI being un-configured
4134 *
4135 * This frees the memory allocated to the q_vectors and
4136 * deletes references to the NAPI struct.
4137 **/
4138static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4139{
4140 int v_idx;
4141
493fb300
AD		 4142 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4143 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4144}
4145
4146/**
4147 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4148 * @pf: board private structure
4149 **/
4150static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4151{
4152 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4153 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4154 pci_disable_msix(pf->pdev);
4155 kfree(pf->msix_entries);
4156 pf->msix_entries = NULL;
3b444399
SN		 4157 kfree(pf->irq_pile);
4158 pf->irq_pile = NULL;
41c445ff
JB		 4159 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4160 pci_disable_msi(pf->pdev);
4161 }
4162 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4163}
4164
4165/**
4166 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4167 * @pf: board private structure
4168 *
4169 * We go through and clear interrupt specific resources and reset the structure
4170 * to pre-load conditions
4171 **/
4172static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4173{
4174 int i;
4175
e147758d
SN		 4176 i40e_stop_misc_vector(pf);
4177 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4178 synchronize_irq(pf->msix_entries[0].vector);
4179 free_irq(pf->msix_entries[0].vector, pf);
4180 }
4181
41c445ff 4182 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4183 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4184 if (pf->vsi[i])
4185 i40e_vsi_free_q_vectors(pf->vsi[i]);
4186 i40e_reset_interrupt_capability(pf);
4187}
4188
4189/**
4190 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4191 * @vsi: the VSI being configured
4192 **/
4193static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4194{
4195 int q_idx;
4196
4197 if (!vsi->netdev)
4198 return;
4199
4200 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4201 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4202}
4203
4204/**
4205 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4206 * @vsi: the VSI being configured
4207 **/
4208static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4209{
4210 int q_idx;
4211
4212 if (!vsi->netdev)
4213 return;
4214
4215 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4216 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4217}
4218
90ef8d47
SN		 4219/**
4220 * i40e_vsi_close - Shut down a VSI
4221 * @vsi: the vsi to be quelled
4222 **/
4223static void i40e_vsi_close(struct i40e_vsi *vsi)
4224{
4225 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4226 i40e_down(vsi);
4227 i40e_vsi_free_irq(vsi);
4228 i40e_vsi_free_tx_resources(vsi);
4229 i40e_vsi_free_rx_resources(vsi);
92faef85 4230 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4231}
4232
41c445ff
JB		 4233/**
4234 * i40e_quiesce_vsi - Pause a given VSI
4235 * @vsi: the VSI being paused
4236 **/
4237static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4238{
4239 if (test_bit(__I40E_DOWN, &vsi->state))
4240 return;
4241
d341b7a5
NP		 4242 /* No need to disable FCoE VSI when Tx suspended */
4243 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4244 vsi->type == I40E_VSI_FCOE) {
4245 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4246 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4247 return;
4248 }
4249
41c445ff 4250 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4251 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4252 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4253 else
90ef8d47 4254 i40e_vsi_close(vsi);
41c445ff
JB		 4255}
4256
4257/**
4258 * i40e_unquiesce_vsi - Resume a given VSI
4259 * @vsi: the VSI being resumed
4260 **/
4261static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4262{
4263 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4264 return;
4265
4266 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4267 if (vsi->netdev && netif_running(vsi->netdev))
4268 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4269 else
8276f757 4270 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4271}
4272
4273/**
4274 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4275 * @pf: the PF
4276 **/
4277static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4278{
4279 int v;
4280
505682cd 4281 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4282 if (pf->vsi[v])
4283 i40e_quiesce_vsi(pf->vsi[v]);
4284 }
4285}
4286
4287/**
4288 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4289 * @pf: the PF
4290 **/
4291static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4292{
4293 int v;
4294
505682cd 4295 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4296 if (pf->vsi[v])
4297 i40e_unquiesce_vsi(pf->vsi[v]);
4298 }
4299}
4300
69129dc3
NP		 4301#ifdef CONFIG_I40E_DCB
4302/**
4303 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4304 * @vsi: the VSI being configured
4305 *
4306 * This function waits for the given VSI's Tx queues to be disabled.
4307 **/
4308static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4309{
4310 struct i40e_pf *pf = vsi->back;
4311 int i, pf_q, ret;
4312
4313 pf_q = vsi->base_queue;
4314 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4315 /* Check and wait for the disable status of the queue */
4316 ret = i40e_pf_txq_wait(pf, pf_q, false);
4317 if (ret) {
4318 dev_info(&pf->pdev->dev,
fb43201f
SN		 4319 "VSI seid %d Tx ring %d disable timeout\n",
4320 vsi->seid, pf_q);
69129dc3
NP		 4321 return ret;
4322 }
4323 }
4324
4325 return 0;
4326}
4327
4328/**
4329 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4330 * @pf: the PF
4331 *
4332 * This function waits for the Tx queues to be in disabled state for all the
4333 * VSIs that are managed by this PF.
4334 **/
4335static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4336{
4337 int v, ret = 0;
4338
4339 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4340 /* No need to wait for FCoE VSI queues */
4341 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4342 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4343 if (ret)
4344 break;
4345 }
4346 }
4347
4348 return ret;
4349}
4350
4351#endif
b03a8c1f
KP		 4352
4353/**
4354 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4355 * @q_idx: TX queue number
4356 * @vsi: Pointer to VSI struct
4357 *
4358 * This function checks specified queue for given VSI. Detects hung condition.
4359 * Sets hung bit since it is two step process. Before next run of service task
4360 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4361 * hung condition remain unchanged and during subsequent run, this function
4362 * issues SW interrupt to recover from hung condition.
4363 **/
4364static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4365{
4366 struct i40e_ring *tx_ring = NULL;
4367 struct i40e_pf *pf;
4368 u32 head, val, tx_pending;
4369 int i;
4370
4371 pf = vsi->back;
4372
4373 /* now that we have an index, find the tx_ring struct */
4374 for (i = 0; i < vsi->num_queue_pairs; i++) {
4375 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4376 if (q_idx == vsi->tx_rings[i]->queue_index) {
4377 tx_ring = vsi->tx_rings[i];
4378 break;
4379 }
4380 }
4381 }
4382
4383 if (!tx_ring)
4384 return;
4385
4386 /* Read interrupt register */
4387 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4388 val = rd32(&pf->hw,
4389 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4390 tx_ring->vsi->base_vector - 1));
4391 else
4392 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4393
9c6c1259
KP		 4394 /* Bail out if interrupts are disabled because napi_poll
4395 * execution in-progress or will get scheduled soon.
4396 * napi_poll cleans TX and RX queues and updates 'next_to_clean'.
4397 */
4398 if (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))
4399 return;
4400
b03a8c1f
KP		 4401 head = i40e_get_head(tx_ring);
4402
4403 tx_pending = i40e_get_tx_pending(tx_ring);
4404
9c6c1259
KP		 4405 /* HW is done executing descriptors, updated HEAD write back,
4406 * but SW hasn't processed those descriptors. If interrupt is
4407 * not generated from this point ON, it could result into
4408 * dev_watchdog detecting timeout on those netdev_queue,
4409 * hence proactively trigger SW interrupt.
b03a8c1f 4410 */
9c6c1259
KP		 4411 if (tx_pending) {
4412 /* NAPI Poll didn't run and clear since it was set */
4413 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4414 &tx_ring->q_vector->hung_detected)) {
4415 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4416 vsi->seid, q_idx, tx_pending,
4417 tx_ring->next_to_clean, head,
4418 tx_ring->next_to_use,
4419 readl(tx_ring->tail));
4420 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4421 vsi->seid, q_idx, val);
4422 i40e_force_wb(vsi, tx_ring->q_vector);
4423 } else {
4424 /* First Chance - detected possible hung */
4425 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4426 &tx_ring->q_vector->hung_detected);
4427 }
4428 }
b03a8c1f
KP		 4429}
4430
4431/**
4432 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4433 * @pf: pointer to PF struct
4434 *
4435 * LAN VSI has netdev and netdev has TX queues. This function is to check
4436 * each of those TX queues if they are hung, trigger recovery by issuing
4437 * SW interrupt.
4438 **/
4439static void i40e_detect_recover_hung(struct i40e_pf *pf)
4440{
4441 struct net_device *netdev;
4442 struct i40e_vsi *vsi;
4443 int i;
4444
4445 /* Only for LAN VSI */
4446 vsi = pf->vsi[pf->lan_vsi];
4447
4448 if (!vsi)
4449 return;
4450
4451 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4452 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4453 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4454 return;
4455
4456 /* Make sure type is MAIN VSI */
4457 if (vsi->type != I40E_VSI_MAIN)
4458 return;
4459
4460 netdev = vsi->netdev;
4461 if (!netdev)
4462 return;
4463
4464 /* Bail out if netif_carrier is not OK */
4465 if (!netif_carrier_ok(netdev))
4466 return;
4467
4468 /* Go thru' TX queues for netdev */
4469 for (i = 0; i < netdev->num_tx_queues; i++) {
4470 struct netdev_queue *q;
4471
4472 q = netdev_get_tx_queue(netdev, i);
4473 if (q)
4474 i40e_detect_recover_hung_queue(i, vsi);
4475 }
4476}
4477
63d7e5a4
NP		 4478/**
4479 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4480 * @pf: pointer to PF
63d7e5a4
NP		 4481 *
4482 * Get TC map for ISCSI PF type that will include iSCSI TC
4483 * and LAN TC.
4484 **/
4485static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4486{
4487 struct i40e_dcb_app_priority_table app;
4488 struct i40e_hw *hw = &pf->hw;
4489 u8 enabled_tc = 1; /* TC0 is always enabled */
4490 u8 tc, i;
4491 /* Get the iSCSI APP TLV */
4492 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4493
4494 for (i = 0; i < dcbcfg->numapps; i++) {
4495 app = dcbcfg->app[i];
4496 if (app.selector == I40E_APP_SEL_TCPIP &&
4497 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4498 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4499 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4500 break;
4501 }
4502 }
4503
4504 return enabled_tc;
4505}
4506
41c445ff
JB		 4507/**
4508 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4509 * @dcbcfg: the corresponding DCBx configuration structure
4510 *
4511 * Return the number of TCs from given DCBx configuration
4512 **/
4513static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4514{
078b5876
JB		 4515 u8 num_tc = 0;
4516 int i;
41c445ff
JB		 4517
4518 /* Scan the ETS Config Priority Table to find
4519 * traffic class enabled for a given priority
4520 * and use the traffic class index to get the
4521 * number of traffic classes enabled
4522 */
4523 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4524 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4525 num_tc = dcbcfg->etscfg.prioritytable[i];
4526 }
4527
4528 /* Traffic class index starts from zero so
4529 * increment to return the actual count
4530 */
078b5876 4531 return num_tc + 1;
41c445ff
JB		 4532}
4533
4534/**
4535 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4536 * @dcbcfg: the corresponding DCBx configuration structure
4537 *
4538 * Query the current DCB configuration and return the number of
4539 * traffic classes enabled from the given DCBX config
4540 **/
4541static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4542{
4543 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4544 u8 enabled_tc = 1;
4545 u8 i;
4546
4547 for (i = 0; i < num_tc; i++)
41a1d04b 4548 enabled_tc |= BIT(i);
41c445ff
JB		 4549
4550 return enabled_tc;
4551}
4552
4553/**
4554 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4555 * @pf: PF being queried
4556 *
4557 * Return number of traffic classes enabled for the given PF
4558 **/
4559static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4560{
4561 struct i40e_hw *hw = &pf->hw;
4562 u8 i, enabled_tc;
4563 u8 num_tc = 0;
4564 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4565
4566 /* If DCB is not enabled then always in single TC */
4567 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4568 return 1;
4569
63d7e5a4
NP		 4570 /* SFP mode will be enabled for all TCs on port */
4571 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4572 return i40e_dcb_get_num_tc(dcbcfg);
4573
41c445ff 4574 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4575 if (pf->hw.func_caps.iscsi)
4576 enabled_tc = i40e_get_iscsi_tc_map(pf);
4577 else
fc51de96 4578 return 1; /* Only TC0 */
41c445ff 4579
63d7e5a4
NP		 4580 /* At least have TC0 */
4581 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4582 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4583 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4584 num_tc++;
4585 }
4586 return num_tc;
41c445ff
JB		 4587}
4588
4589/**
4590 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4591 * @pf: PF being queried
4592 *
4593 * Return a bitmap for first enabled traffic class for this PF.
4594 **/
4595static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4596{
4597 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4598 u8 i = 0;
4599
4600 if (!enabled_tc)
4601 return 0x1; /* TC0 */
4602
4603 /* Find the first enabled TC */
4604 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4605 if (enabled_tc & BIT(i))
41c445ff
JB		 4606 break;
4607 }
4608
41a1d04b 4609 return BIT(i);
41c445ff
JB		 4610}
4611
4612/**
4613 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4614 * @pf: PF being queried
4615 *
4616 * Return a bitmap for enabled traffic classes for this PF.
4617 **/
4618static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4619{
4620 /* If DCB is not enabled for this PF then just return default TC */
4621 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4622 return i40e_pf_get_default_tc(pf);
4623
41c445ff 4624 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4625 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4626 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4627
fc51de96 4628 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4629 if (pf->hw.func_caps.iscsi)
4630 return i40e_get_iscsi_tc_map(pf);
4631 else
fc51de96 4632 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4633}
4634
4635/**
4636 * i40e_vsi_get_bw_info - Query VSI BW Information
4637 * @vsi: the VSI being queried
4638 *
4639 * Returns 0 on success, negative value on failure
4640 **/
4641static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4642{
4643 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4644 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4645 struct i40e_pf *pf = vsi->back;
4646 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4647 i40e_status ret;
41c445ff 4648 u32 tc_bw_max;
41c445ff
JB		 4649 int i;
4650
4651 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4652 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4653 if (ret) {
41c445ff 4654 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4655 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4656 i40e_stat_str(&pf->hw, ret),
4657 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4658 return -EINVAL;
41c445ff
JB		 4659 }
4660
4661 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4662 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4663 NULL);
4664 if (ret) {
41c445ff 4665 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4666 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4667 i40e_stat_str(&pf->hw, ret),
4668 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4669 return -EINVAL;
41c445ff
JB		 4670 }
4671
4672 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4673 dev_info(&pf->pdev->dev,
4674 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4675 bw_config.tc_valid_bits,
4676 bw_ets_config.tc_valid_bits);
4677 /* Still continuing */
4678 }
4679
4680 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4681 vsi->bw_max_quanta = bw_config.max_bw;
4682 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4683 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4684 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4685 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4686 vsi->bw_ets_limit_credits[i] =
4687 le16_to_cpu(bw_ets_config.credits[i]);
4688 /* 3 bits out of 4 for each TC */
4689 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4690 }
078b5876 4691
dcae29be 4692 return 0;
41c445ff
JB		 4693}
4694
4695/**
4696 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4697 * @vsi: the VSI being configured
4698 * @enabled_tc: TC bitmap
4699 * @bw_credits: BW shared credits per TC
4700 *
4701 * Returns 0 on success, negative value on failure
4702 **/
dcae29be 4703static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4704 u8 *bw_share)
4705{
4706 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4707 i40e_status ret;
dcae29be 4708 int i;
41c445ff
JB		 4709
4710 bw_data.tc_valid_bits = enabled_tc;
4711 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4712 bw_data.tc_bw_credits[i] = bw_share[i];
4713
f1c7e72e
SN		 4714 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4715 NULL);
4716 if (ret) {
41c445ff 4717 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4718 "AQ command Config VSI BW allocation per TC failed = %d\n",
4719 vsi->back->hw.aq.asq_last_status);
dcae29be 4720 return -EINVAL;
41c445ff
JB		 4721 }
4722
4723 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4724 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4725
dcae29be 4726 return 0;
41c445ff
JB		 4727}
4728
4729/**
4730 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4731 * @vsi: the VSI being configured
4732 * @enabled_tc: TC map to be enabled
4733 *
4734 **/
4735static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4736{
4737 struct net_device *netdev = vsi->netdev;
4738 struct i40e_pf *pf = vsi->back;
4739 struct i40e_hw *hw = &pf->hw;
4740 u8 netdev_tc = 0;
4741 int i;
4742 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4743
4744 if (!netdev)
4745 return;
4746
4747 if (!enabled_tc) {
4748 netdev_reset_tc(netdev);
4749 return;
4750 }
4751
4752 /* Set up actual enabled TCs on the VSI */
4753 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4754 return;
4755
4756 /* set per TC queues for the VSI */
4757 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4758 /* Only set TC queues for enabled tcs
4759 *
4760 * e.g. For a VSI that has TC0 and TC3 enabled the
4761 * enabled_tc bitmap would be 0x00001001; the driver
4762 * will set the numtc for netdev as 2 that will be
4763 * referenced by the netdev layer as TC 0 and 1.
4764 */
75f5cea9 4765 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4766 netdev_set_tc_queue(netdev,
4767 vsi->tc_config.tc_info[i].netdev_tc,
4768 vsi->tc_config.tc_info[i].qcount,
4769 vsi->tc_config.tc_info[i].qoffset);
4770 }
4771
4772 /* Assign UP2TC map for the VSI */
4773 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4774 /* Get the actual TC# for the UP */
4775 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4776 /* Get the mapped netdev TC# for the UP */
4777 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4778 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4779 }
4780}
4781
4782/**
4783 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4784 * @vsi: the VSI being configured
4785 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4786 **/
4787static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4788 struct i40e_vsi_context *ctxt)
4789{
4790 /* copy just the sections touched not the entire info
4791 * since not all sections are valid as returned by
4792 * update vsi params
4793 */
4794 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4795 memcpy(&vsi->info.queue_mapping,
4796 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4797 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4798 sizeof(vsi->info.tc_mapping));
4799}
4800
4801/**
4802 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4803 * @vsi: VSI to be configured
4804 * @enabled_tc: TC bitmap
4805 *
4806 * This configures a particular VSI for TCs that are mapped to the
4807 * given TC bitmap. It uses default bandwidth share for TCs across
4808 * VSIs to configure TC for a particular VSI.
4809 *
4810 * NOTE:
4811 * It is expected that the VSI queues have been quisced before calling
4812 * this function.
4813 **/
4814static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4815{
4816 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4817 struct i40e_vsi_context ctxt;
4818 int ret = 0;
4819 int i;
4820
4821 /* Check if enabled_tc is same as existing or new TCs */
4822 if (vsi->tc_config.enabled_tc == enabled_tc)
4823 return ret;
4824
4825 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4826 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4827 if (enabled_tc & BIT(i))
41c445ff
JB		 4828 bw_share[i] = 1;
4829 }
4830
4831 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4832 if (ret) {
4833 dev_info(&vsi->back->pdev->dev,
4834 "Failed configuring TC map %d for VSI %d\n",
4835 enabled_tc, vsi->seid);
4836 goto out;
4837 }
4838
4839 /* Update Queue Pairs Mapping for currently enabled UPs */
4840 ctxt.seid = vsi->seid;
4841 ctxt.pf_num = vsi->back->hw.pf_id;
4842 ctxt.vf_num = 0;
4843 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4844 ctxt.info = vsi->info;
41c445ff
JB		 4845 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4846
4847 /* Update the VSI after updating the VSI queue-mapping information */
4848 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4849 if (ret) {
4850 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4851 "Update vsi tc config failed, err %s aq_err %s\n",
4852 i40e_stat_str(&vsi->back->hw, ret),
4853 i40e_aq_str(&vsi->back->hw,
4854 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4855 goto out;
4856 }
4857 /* update the local VSI info with updated queue map */
4858 i40e_vsi_update_queue_map(vsi, &ctxt);
4859 vsi->info.valid_sections = 0;
4860
4861 /* Update current VSI BW information */
4862 ret = i40e_vsi_get_bw_info(vsi);
4863 if (ret) {
4864 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4865 "Failed updating vsi bw info, err %s aq_err %s\n",
4866 i40e_stat_str(&vsi->back->hw, ret),
4867 i40e_aq_str(&vsi->back->hw,
4868 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4869 goto out;
4870 }
4871
4872 /* Update the netdev TC setup */
4873 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4874out:
4875 return ret;
4876}
4877
4e3b35b0
NP		 4878/**
4879 * i40e_veb_config_tc - Configure TCs for given VEB
4880 * @veb: given VEB
4881 * @enabled_tc: TC bitmap
4882 *
4883 * Configures given TC bitmap for VEB (switching) element
4884 **/
4885int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4886{
4887 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4888 struct i40e_pf *pf = veb->pf;
4889 int ret = 0;
4890 int i;
4891
4892 /* No TCs or already enabled TCs just return */
4893 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4894 return ret;
4895
4896 bw_data.tc_valid_bits = enabled_tc;
4897 /* bw_data.absolute_credits is not set (relative) */
4898
4899 /* Enable ETS TCs with equal BW Share for now */
4900 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4901 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4902 bw_data.tc_bw_share_credits[i] = 1;
4903 }
4904
4905 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4906 &bw_data, NULL);
4907 if (ret) {
4908 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4909 "VEB bw config failed, err %s aq_err %s\n",
4910 i40e_stat_str(&pf->hw, ret),
4911 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4912 goto out;
4913 }
4914
4915 /* Update the BW information */
4916 ret = i40e_veb_get_bw_info(veb);
4917 if (ret) {
4918 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4919 "Failed getting veb bw config, err %s aq_err %s\n",
4920 i40e_stat_str(&pf->hw, ret),
4921 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4922 }
4923
4924out:
4925 return ret;
4926}
4927
4928#ifdef CONFIG_I40E_DCB
4929/**
4930 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4931 * @pf: PF struct
4932 *
4933 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4934 * the caller would've quiesce all the VSIs before calling
4935 * this function
4936 **/
4937static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4938{
4939 u8 tc_map = 0;
4940 int ret;
4941 u8 v;
4942
4943 /* Enable the TCs available on PF to all VEBs */
4944 tc_map = i40e_pf_get_tc_map(pf);
4945 for (v = 0; v < I40E_MAX_VEB; v++) {
4946 if (!pf->veb[v])
4947 continue;
4948 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4949 if (ret) {
4950 dev_info(&pf->pdev->dev,
4951 "Failed configuring TC for VEB seid=%d\n",
4952 pf->veb[v]->seid);
4953 /* Will try to configure as many components */
4954 }
4955 }
4956
4957 /* Update each VSI */
505682cd 4958 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4959 if (!pf->vsi[v])
4960 continue;
4961
4962 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4963#ifdef I40E_FCOE
4964 * - For FCoE VSI only enable the TC configured
4965 * as per the APP TLV
4966#endif
4e3b35b0
NP		 4967 * - For all others keep them at TC0 for now
4968 */
4969 if (v == pf->lan_vsi)
4970 tc_map = i40e_pf_get_tc_map(pf);
4971 else
4972 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4973#ifdef I40E_FCOE
4974 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4975 tc_map = i40e_get_fcoe_tc_map(pf);
4976#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4977
4978 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4979 if (ret) {
4980 dev_info(&pf->pdev->dev,
4981 "Failed configuring TC for VSI seid=%d\n",
4982 pf->vsi[v]->seid);
4983 /* Will try to configure as many components */
4984 } else {
0672a091
NP		 4985 /* Re-configure VSI vectors based on updated TC map */
4986 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4987 if (pf->vsi[v]->netdev)
4988 i40e_dcbnl_set_all(pf->vsi[v]);
4989 }
4990 }
4991}
4992
2fd75f31
NP		 4993/**
4994 * i40e_resume_port_tx - Resume port Tx
4995 * @pf: PF struct
4996 *
4997 * Resume a port's Tx and issue a PF reset in case of failure to
4998 * resume.
4999 **/
5000static int i40e_resume_port_tx(struct i40e_pf *pf)
5001{
5002 struct i40e_hw *hw = &pf->hw;
5003 int ret;
5004
5005 ret = i40e_aq_resume_port_tx(hw, NULL);
5006 if (ret) {
5007 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5008 "Resume Port Tx failed, err %s aq_err %s\n",
5009 i40e_stat_str(&pf->hw, ret),
5010 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 5011 /* Schedule PF reset to recover */
5012 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5013 i40e_service_event_schedule(pf);
5014 }
5015
5016 return ret;
5017}
5018
4e3b35b0
NP		 5019/**
5020 * i40e_init_pf_dcb - Initialize DCB configuration
5021 * @pf: PF being configured
5022 *
5023 * Query the current DCB configuration and cache it
5024 * in the hardware structure
5025 **/
5026static int i40e_init_pf_dcb(struct i40e_pf *pf)
5027{
5028 struct i40e_hw *hw = &pf->hw;
5029 int err = 0;
5030
025b4a54
ASJ		 5031 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
5032 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
5033 (pf->hw.aq.fw_maj_ver < 4))
5034 goto out;
5035
4e3b35b0
NP		 5036 /* Get the initial DCB configuration */
5037 err = i40e_init_dcb(hw);
5038 if (!err) {
5039 /* Device/Function is not DCBX capable */
5040 if ((!hw->func_caps.dcb) ||
5041 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5042 dev_info(&pf->pdev->dev,
5043 "DCBX offload is not supported or is disabled for this PF.\n");
5044
5045 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5046 goto out;
5047
5048 } else {
5049 /* When status is not DISABLED then DCBX in FW */
5050 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5051 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5052
5053 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5054 /* Enable DCB tagging only when more than one TC */
5055 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5056 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5057 dev_dbg(&pf->pdev->dev,
5058 "DCBX offload is supported for this PF.\n");
4e3b35b0 5059 }
014269ff 5060 } else {
aebfc816 5061 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5062 "Query for DCB configuration failed, err %s aq_err %s\n",
5063 i40e_stat_str(&pf->hw, err),
5064 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5065 }
5066
5067out:
5068 return err;
5069}
5070#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5071#define SPEED_SIZE 14
5072#define FC_SIZE 8
5073/**
5074 * i40e_print_link_message - print link up or down
5075 * @vsi: the VSI for which link needs a message
5076 */
c156f856 5077void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5078{
a9165490
SN		 5079 char *speed = "Unknown";
5080 char *fc = "Unknown";
cf05ed08 5081
c156f856
MJ		 5082 if (vsi->current_isup == isup)
5083 return;
5084 vsi->current_isup = isup;
cf05ed08
JB		 5085 if (!isup) {
5086 netdev_info(vsi->netdev, "NIC Link is Down\n");
5087 return;
5088 }
5089
148c2d80
GR		 5090 /* Warn user if link speed on NPAR enabled partition is not at
5091 * least 10GB
5092 */
5093 if (vsi->back->hw.func_caps.npar_enable &&
5094 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5095 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5096 netdev_warn(vsi->netdev,
5097 "The partition detected link speed that is less than 10Gbps\n");
5098
cf05ed08
JB		 5099 switch (vsi->back->hw.phy.link_info.link_speed) {
5100 case I40E_LINK_SPEED_40GB:
a9165490 5101 speed = "40 G";
cf05ed08 5102 break;
ae24b409 5103 case I40E_LINK_SPEED_20GB:
a9165490 5104 speed = "20 G";
ae24b409 5105 break;
cf05ed08 5106 case I40E_LINK_SPEED_10GB:
a9165490 5107 speed = "10 G";
cf05ed08
JB		 5108 break;
5109 case I40E_LINK_SPEED_1GB:
a9165490 5110 speed = "1000 M";
cf05ed08 5111 break;
5960d33f 5112 case I40E_LINK_SPEED_100MB:
a9165490 5113 speed = "100 M";
5960d33f 5114 break;
cf05ed08
JB		 5115 default:
5116 break;
5117 }
5118
5119 switch (vsi->back->hw.fc.current_mode) {
5120 case I40E_FC_FULL:
a9165490 5121 fc = "RX/TX";
cf05ed08
JB		 5122 break;
5123 case I40E_FC_TX_PAUSE:
a9165490 5124 fc = "TX";
cf05ed08
JB		 5125 break;
5126 case I40E_FC_RX_PAUSE:
a9165490 5127 fc = "RX";
cf05ed08
JB		 5128 break;
5129 default:
a9165490 5130 fc = "None";
cf05ed08
JB		 5131 break;
5132 }
5133
a9165490 5134 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5135 speed, fc);
5136}
4e3b35b0 5137
41c445ff
JB		 5138/**
5139 * i40e_up_complete - Finish the last steps of bringing up a connection
5140 * @vsi: the VSI being configured
5141 **/
5142static int i40e_up_complete(struct i40e_vsi *vsi)
5143{
5144 struct i40e_pf *pf = vsi->back;
5145 int err;
5146
5147 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5148 i40e_vsi_configure_msix(vsi);
5149 else
5150 i40e_configure_msi_and_legacy(vsi);
5151
5152 /* start rings */
5153 err = i40e_vsi_control_rings(vsi, true);
5154 if (err)
5155 return err;
5156
5157 clear_bit(__I40E_DOWN, &vsi->state);
5158 i40e_napi_enable_all(vsi);
5159 i40e_vsi_enable_irq(vsi);
5160
5161 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5162 (vsi->netdev)) {
cf05ed08 5163 i40e_print_link_message(vsi, true);
41c445ff
JB		 5164 netif_tx_start_all_queues(vsi->netdev);
5165 netif_carrier_on(vsi->netdev);
6d779b41 5166 } else if (vsi->netdev) {
cf05ed08 5167 i40e_print_link_message(vsi, false);
7b592f61
CW		 5168 /* need to check for qualified module here*/
5169 if ((pf->hw.phy.link_info.link_info &
5170 I40E_AQ_MEDIA_AVAILABLE) &&
5171 (!(pf->hw.phy.link_info.an_info &
5172 I40E_AQ_QUALIFIED_MODULE)))
5173 netdev_err(vsi->netdev,
5174 "the driver failed to link because an unqualified module was detected.");
41c445ff 5175 }
ca64fa4e
ASJ		 5176
5177 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5178 if (vsi->type == I40E_VSI_FDIR) {
5179 /* reset fd counters */
5180 pf->fd_add_err = pf->fd_atr_cnt = 0;
5181 if (pf->fd_tcp_rule > 0) {
5182 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5183 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5184 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5185 pf->fd_tcp_rule = 0;
5186 }
ca64fa4e 5187 i40e_fdir_filter_restore(vsi);
1e1be8f6 5188 }
41c445ff
JB		 5189 i40e_service_event_schedule(pf);
5190
5191 return 0;
5192}
5193
5194/**
5195 * i40e_vsi_reinit_locked - Reset the VSI
5196 * @vsi: the VSI being configured
5197 *
5198 * Rebuild the ring structs after some configuration
5199 * has changed, e.g. MTU size.
5200 **/
5201static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5202{
5203 struct i40e_pf *pf = vsi->back;
5204
5205 WARN_ON(in_interrupt());
5206 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5207 usleep_range(1000, 2000);
5208 i40e_down(vsi);
5209
5210 /* Give a VF some time to respond to the reset. The
5211 * two second wait is based upon the watchdog cycle in
5212 * the VF driver.
5213 */
5214 if (vsi->type == I40E_VSI_SRIOV)
5215 msleep(2000);
5216 i40e_up(vsi);
5217 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5218}
5219
5220/**
5221 * i40e_up - Bring the connection back up after being down
5222 * @vsi: the VSI being configured
5223 **/
5224int i40e_up(struct i40e_vsi *vsi)
5225{
5226 int err;
5227
5228 err = i40e_vsi_configure(vsi);
5229 if (!err)
5230 err = i40e_up_complete(vsi);
5231
5232 return err;
5233}
5234
5235/**
5236 * i40e_down - Shutdown the connection processing
5237 * @vsi: the VSI being stopped
5238 **/
5239void i40e_down(struct i40e_vsi *vsi)
5240{
5241 int i;
5242
5243 /* It is assumed that the caller of this function
5244 * sets the vsi->state __I40E_DOWN bit.
5245 */
5246 if (vsi->netdev) {
5247 netif_carrier_off(vsi->netdev);
5248 netif_tx_disable(vsi->netdev);
5249 }
5250 i40e_vsi_disable_irq(vsi);
5251 i40e_vsi_control_rings(vsi, false);
5252 i40e_napi_disable_all(vsi);
5253
5254 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5255 i40e_clean_tx_ring(vsi->tx_rings[i]);
5256 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5257 }
5258}
5259
5260/**
5261 * i40e_setup_tc - configure multiple traffic classes
5262 * @netdev: net device to configure
5263 * @tc: number of traffic classes to enable
5264 **/
5265static int i40e_setup_tc(struct net_device *netdev, u8 tc)
5266{
5267 struct i40e_netdev_priv *np = netdev_priv(netdev);
5268 struct i40e_vsi *vsi = np->vsi;
5269 struct i40e_pf *pf = vsi->back;
5270 u8 enabled_tc = 0;
5271 int ret = -EINVAL;
5272 int i;
5273
5274 /* Check if DCB enabled to continue */
5275 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5276 netdev_info(netdev, "DCB is not enabled for adapter\n");
5277 goto exit;
5278 }
5279
5280 /* Check if MFP enabled */
5281 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5282 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5283 goto exit;
5284 }
5285
5286 /* Check whether tc count is within enabled limit */
5287 if (tc > i40e_pf_get_num_tc(pf)) {
5288 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5289 goto exit;
5290 }
5291
5292 /* Generate TC map for number of tc requested */
5293 for (i = 0; i < tc; i++)
75f5cea9 5294 enabled_tc |= BIT(i);
41c445ff
JB		 5295
5296 /* Requesting same TC configuration as already enabled */
5297 if (enabled_tc == vsi->tc_config.enabled_tc)
5298 return 0;
5299
5300 /* Quiesce VSI queues */
5301 i40e_quiesce_vsi(vsi);
5302
5303 /* Configure VSI for enabled TCs */
5304 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5305 if (ret) {
5306 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5307 vsi->seid);
5308 goto exit;
5309 }
5310
5311 /* Unquiesce VSI */
5312 i40e_unquiesce_vsi(vsi);
5313
5314exit:
5315 return ret;
5316}
5317
e4c6734e 5318#ifdef I40E_FCOE
16e5cc64
JF		 5319int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5320 struct tc_to_netdev *tc)
e4c6734e 5321#else
16e5cc64
JF		 5322static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5323 struct tc_to_netdev *tc)
e4c6734e
JF		 5324#endif
5325{
16e5cc64 5326 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
e4c6734e 5327 return -EINVAL;
16e5cc64 5328 return i40e_setup_tc(netdev, tc->tc);
e4c6734e
JF		 5329}
5330
41c445ff
JB		 5331/**
5332 * i40e_open - Called when a network interface is made active
5333 * @netdev: network interface device structure
5334 *
5335 * The open entry point is called when a network interface is made
5336 * active by the system (IFF_UP). At this point all resources needed
5337 * for transmit and receive operations are allocated, the interrupt
5338 * handler is registered with the OS, the netdev watchdog subtask is
5339 * enabled, and the stack is notified that the interface is ready.
5340 *
5341 * Returns 0 on success, negative value on failure
5342 **/
38e00438 5343int i40e_open(struct net_device *netdev)
41c445ff
JB		 5344{
5345 struct i40e_netdev_priv *np = netdev_priv(netdev);
5346 struct i40e_vsi *vsi = np->vsi;
5347 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5348 int err;
5349
4eb3f768
SN		 5350 /* disallow open during test or if eeprom is broken */
5351 if (test_bit(__I40E_TESTING, &pf->state) ||
5352 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5353 return -EBUSY;
5354
5355 netif_carrier_off(netdev);
5356
6c167f58
EK		 5357 err = i40e_vsi_open(vsi);
5358 if (err)
5359 return err;
5360
059dab69
JB		 5361 /* configure global TSO hardware offload settings */
5362 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5363 TCP_FLAG_FIN) >> 16);
5364 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5365 TCP_FLAG_FIN |
5366 TCP_FLAG_CWR) >> 16);
5367 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5368
6633d381 5369#ifdef CONFIG_I40E_VXLAN
6c167f58
EK		 5370 vxlan_get_rx_port(netdev);
5371#endif
cd866606
SA		 5372#ifdef CONFIG_I40E_GENEVE
5373 geneve_get_rx_port(netdev);
5374#endif
6c167f58
EK		 5375
5376 return 0;
5377}
5378
5379/**
5380 * i40e_vsi_open -
5381 * @vsi: the VSI to open
5382 *
5383 * Finish initialization of the VSI.
5384 *
5385 * Returns 0 on success, negative value on failure
5386 **/
5387int i40e_vsi_open(struct i40e_vsi *vsi)
5388{
5389 struct i40e_pf *pf = vsi->back;
b294ac70 5390 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5391 int err;
5392
41c445ff
JB		 5393 /* allocate descriptors */
5394 err = i40e_vsi_setup_tx_resources(vsi);
5395 if (err)
5396 goto err_setup_tx;
5397 err = i40e_vsi_setup_rx_resources(vsi);
5398 if (err)
5399 goto err_setup_rx;
5400
5401 err = i40e_vsi_configure(vsi);
5402 if (err)
5403 goto err_setup_rx;
5404
c22e3c6c
SN		 5405 if (vsi->netdev) {
5406 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5407 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5408 err = i40e_vsi_request_irq(vsi, int_name);
5409 if (err)
5410 goto err_setup_rx;
41c445ff 5411
c22e3c6c
SN		 5412 /* Notify the stack of the actual queue counts. */
5413 err = netif_set_real_num_tx_queues(vsi->netdev,
5414 vsi->num_queue_pairs);
5415 if (err)
5416 goto err_set_queues;
25946ddb 5417
c22e3c6c
SN		 5418 err = netif_set_real_num_rx_queues(vsi->netdev,
5419 vsi->num_queue_pairs);
5420 if (err)
5421 goto err_set_queues;
8a9eb7d3
SN		 5422
5423 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5424 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5425 dev_driver_string(&pf->pdev->dev),
5426 dev_name(&pf->pdev->dev));
8a9eb7d3 5427 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5428
c22e3c6c 5429 } else {
ce9ccb17 5430 err = -EINVAL;
6c167f58
EK		 5431 goto err_setup_rx;
5432 }
25946ddb 5433
41c445ff
JB		 5434 err = i40e_up_complete(vsi);
5435 if (err)
5436 goto err_up_complete;
5437
41c445ff
JB		 5438 return 0;
5439
5440err_up_complete:
5441 i40e_down(vsi);
25946ddb 5442err_set_queues:
41c445ff
JB		 5443 i40e_vsi_free_irq(vsi);
5444err_setup_rx:
5445 i40e_vsi_free_rx_resources(vsi);
5446err_setup_tx:
5447 i40e_vsi_free_tx_resources(vsi);
5448 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5449 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5450
5451 return err;
5452}
5453
17a73f6b
JG		 5454/**
5455 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5456 * @pf: Pointer to PF
17a73f6b
JG		 5457 *
5458 * This function destroys the hlist where all the Flow Director
5459 * filters were saved.
5460 **/
5461static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5462{
5463 struct i40e_fdir_filter *filter;
5464 struct hlist_node *node2;
5465
5466 hlist_for_each_entry_safe(filter, node2,
5467 &pf->fdir_filter_list, fdir_node) {
5468 hlist_del(&filter->fdir_node);
5469 kfree(filter);
5470 }
5471 pf->fdir_pf_active_filters = 0;
5472}
5473
41c445ff
JB		 5474/**
5475 * i40e_close - Disables a network interface
5476 * @netdev: network interface device structure
5477 *
5478 * The close entry point is called when an interface is de-activated
5479 * by the OS. The hardware is still under the driver's control, but
5480 * this netdev interface is disabled.
5481 *
5482 * Returns 0, this is not allowed to fail
5483 **/
38e00438
VD		 5484#ifdef I40E_FCOE
5485int i40e_close(struct net_device *netdev)
5486#else
41c445ff 5487static int i40e_close(struct net_device *netdev)
38e00438 5488#endif
41c445ff
JB		 5489{
5490 struct i40e_netdev_priv *np = netdev_priv(netdev);
5491 struct i40e_vsi *vsi = np->vsi;
5492
90ef8d47 5493 i40e_vsi_close(vsi);
41c445ff
JB		 5494
5495 return 0;
5496}
5497
5498/**
5499 * i40e_do_reset - Start a PF or Core Reset sequence
5500 * @pf: board private structure
5501 * @reset_flags: which reset is requested
5502 *
5503 * The essential difference in resets is that the PF Reset
5504 * doesn't clear the packet buffers, doesn't reset the PE
5505 * firmware, and doesn't bother the other PFs on the chip.
5506 **/
5507void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5508{
5509 u32 val;
5510
5511 WARN_ON(in_interrupt());
5512
263fc48f
MW		 5513 if (i40e_check_asq_alive(&pf->hw))
5514 i40e_vc_notify_reset(pf);
5515
41c445ff 5516 /* do the biggest reset indicated */
41a1d04b 5517 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5518
5519 /* Request a Global Reset
5520 *
5521 * This will start the chip's countdown to the actual full
5522 * chip reset event, and a warning interrupt to be sent
5523 * to all PFs, including the requestor. Our handler
5524 * for the warning interrupt will deal with the shutdown
5525 * and recovery of the switch setup.
5526 */
69bfb110 5527 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5528 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5529 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5530 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5531
41a1d04b 5532 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5533
5534 /* Request a Core Reset
5535 *
5536 * Same as Global Reset, except does *not* include the MAC/PHY
5537 */
69bfb110 5538 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5539 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5540 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5541 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5542 i40e_flush(&pf->hw);
5543
41a1d04b 5544 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5545
5546 /* Request a PF Reset
5547 *
5548 * Resets only the PF-specific registers
5549 *
5550 * This goes directly to the tear-down and rebuild of
5551 * the switch, since we need to do all the recovery as
5552 * for the Core Reset.
5553 */
69bfb110 5554 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5555 i40e_handle_reset_warning(pf);
5556
41a1d04b 5557 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5558 int v;
5559
5560 /* Find the VSI(s) that requested a re-init */
5561 dev_info(&pf->pdev->dev,
5562 "VSI reinit requested\n");
505682cd 5563 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5564 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5565
41c445ff
JB		 5566 if (vsi != NULL &&
5567 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5568 i40e_vsi_reinit_locked(pf->vsi[v]);
5569 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5570 }
5571 }
41a1d04b 5572 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5573 int v;
5574
5575 /* Find the VSI(s) that needs to be brought down */
5576 dev_info(&pf->pdev->dev, "VSI down requested\n");
5577 for (v = 0; v < pf->num_alloc_vsi; v++) {
5578 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5579
b5d06f05
NP		 5580 if (vsi != NULL &&
5581 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5582 set_bit(__I40E_DOWN, &vsi->state);
5583 i40e_down(vsi);
5584 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5585 }
5586 }
41c445ff
JB		 5587 } else {
5588 dev_info(&pf->pdev->dev,
5589 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5590 }
5591}
5592
4e3b35b0
NP		 5593#ifdef CONFIG_I40E_DCB
5594/**
5595 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5596 * @pf: board private structure
5597 * @old_cfg: current DCB config
5598 * @new_cfg: new DCB config
5599 **/
5600bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5601 struct i40e_dcbx_config *old_cfg,
5602 struct i40e_dcbx_config *new_cfg)
5603{
5604 bool need_reconfig = false;
5605
5606 /* Check if ETS configuration has changed */
5607 if (memcmp(&new_cfg->etscfg,
5608 &old_cfg->etscfg,
5609 sizeof(new_cfg->etscfg))) {
5610 /* If Priority Table has changed reconfig is needed */
5611 if (memcmp(&new_cfg->etscfg.prioritytable,
5612 &old_cfg->etscfg.prioritytable,
5613 sizeof(new_cfg->etscfg.prioritytable))) {
5614 need_reconfig = true;
69bfb110 5615 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5616 }
5617
5618 if (memcmp(&new_cfg->etscfg.tcbwtable,
5619 &old_cfg->etscfg.tcbwtable,
5620 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5621 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5622
5623 if (memcmp(&new_cfg->etscfg.tsatable,
5624 &old_cfg->etscfg.tsatable,
5625 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5626 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5627 }
5628
5629 /* Check if PFC configuration has changed */
5630 if (memcmp(&new_cfg->pfc,
5631 &old_cfg->pfc,
5632 sizeof(new_cfg->pfc))) {
5633 need_reconfig = true;
69bfb110 5634 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5635 }
5636
5637 /* Check if APP Table has changed */
5638 if (memcmp(&new_cfg->app,
5639 &old_cfg->app,
3d9667a9 5640 sizeof(new_cfg->app))) {
4e3b35b0 5641 need_reconfig = true;
69bfb110 5642 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5643 }
4e3b35b0 5644
fb43201f 5645 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5646 return need_reconfig;
5647}
5648
5649/**
5650 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5651 * @pf: board private structure
5652 * @e: event info posted on ARQ
5653 **/
5654static int i40e_handle_lldp_event(struct i40e_pf *pf,
5655 struct i40e_arq_event_info *e)
5656{
5657 struct i40e_aqc_lldp_get_mib *mib =
5658 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5659 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5660 struct i40e_dcbx_config tmp_dcbx_cfg;
5661 bool need_reconfig = false;
5662 int ret = 0;
5663 u8 type;
5664
4d9b6043
NP		 5665 /* Not DCB capable or capability disabled */
5666 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5667 return ret;
5668
4e3b35b0
NP		 5669 /* Ignore if event is not for Nearest Bridge */
5670 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5671 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5672 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5673 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5674 return ret;
5675
5676 /* Check MIB Type and return if event for Remote MIB update */
5677 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5678 dev_dbg(&pf->pdev->dev,
fb43201f 5679 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5680 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5681 /* Update the remote cached instance and return */
5682 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5683 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5684 &hw->remote_dcbx_config);
5685 goto exit;
5686 }
5687
9fa61dd2 5688 /* Store the old configuration */
1a2f6248 5689 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5690
750fcbcf
NP		 5691 /* Reset the old DCBx configuration data */
5692 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5693 /* Get updated DCBX data from firmware */
5694 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5695 if (ret) {
f1c7e72e
SN		 5696 dev_info(&pf->pdev->dev,
5697 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5698 i40e_stat_str(&pf->hw, ret),
5699 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5700 goto exit;
5701 }
5702
5703 /* No change detected in DCBX configs */
750fcbcf
NP		 5704 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5705 sizeof(tmp_dcbx_cfg))) {
69bfb110 5706 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5707 goto exit;
5708 }
5709
750fcbcf
NP		 5710 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5711 &hw->local_dcbx_config);
4e3b35b0 5712
750fcbcf 5713 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5714
5715 if (!need_reconfig)
5716 goto exit;
5717
4d9b6043 5718 /* Enable DCB tagging only when more than one TC */
750fcbcf 5719 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5720 pf->flags |= I40E_FLAG_DCB_ENABLED;
5721 else
5722 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5723
69129dc3 5724 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5725 /* Reconfiguration needed quiesce all VSIs */
5726 i40e_pf_quiesce_all_vsi(pf);
5727
5728 /* Changes in configuration update VEB/VSI */
5729 i40e_dcb_reconfigure(pf);
5730
2fd75f31
NP		 5731 ret = i40e_resume_port_tx(pf);
5732
69129dc3 5733 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5734 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5735 if (ret)
5736 goto exit;
5737
5738 /* Wait for the PF's Tx queues to be disabled */
5739 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5740 if (ret) {
5741 /* Schedule PF reset to recover */
5742 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5743 i40e_service_event_schedule(pf);
5744 } else {
2fd75f31 5745 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5746 }
5747
4e3b35b0
NP		 5748exit:
5749 return ret;
5750}
5751#endif /* CONFIG_I40E_DCB */
5752
23326186
ASJ		 5753/**
5754 * i40e_do_reset_safe - Protected reset path for userland calls.
5755 * @pf: board private structure
5756 * @reset_flags: which reset is requested
5757 *
5758 **/
5759void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5760{
5761 rtnl_lock();
5762 i40e_do_reset(pf, reset_flags);
5763 rtnl_unlock();
5764}
5765
41c445ff
JB		 5766/**
5767 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5768 * @pf: board private structure
5769 * @e: event info posted on ARQ
5770 *
5771 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5772 * and VF queues
5773 **/
5774static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5775 struct i40e_arq_event_info *e)
5776{
5777 struct i40e_aqc_lan_overflow *data =
5778 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5779 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5780 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5781 struct i40e_hw *hw = &pf->hw;
5782 struct i40e_vf *vf;
5783 u16 vf_id;
5784
69bfb110
JB		 5785 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5786 queue, qtx_ctl);
41c445ff
JB		 5787
5788 /* Queue belongs to VF, find the VF and issue VF reset */
5789 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5790 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5791 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5792 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5793 vf_id -= hw->func_caps.vf_base_id;
5794 vf = &pf->vf[vf_id];
5795 i40e_vc_notify_vf_reset(vf);
5796 /* Allow VF to process pending reset notification */
5797 msleep(20);
5798 i40e_reset_vf(vf, false);
5799 }
5800}
5801
5802/**
5803 * i40e_service_event_complete - Finish up the service event
5804 * @pf: board private structure
5805 **/
5806static void i40e_service_event_complete(struct i40e_pf *pf)
5807{
b875f99b 5808 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5809
5810 /* flush memory to make sure state is correct before next watchog */
4e857c58 5811 smp_mb__before_atomic();
41c445ff
JB		 5812 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5813}
5814
55a5e60b 5815/**
12957388
ASJ		 5816 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5817 * @pf: board private structure
5818 **/
04294e38 5819u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5820{
04294e38 5821 u32 val, fcnt_prog;
12957388
ASJ		 5822
5823 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5824 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5825 return fcnt_prog;
5826}
5827
5828/**
04294e38 5829 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5830 * @pf: board private structure
5831 **/
04294e38 5832u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5833{
04294e38
ASJ		 5834 u32 val, fcnt_prog;
5835
55a5e60b
ASJ		 5836 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5837 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5838 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5839 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5840 return fcnt_prog;
5841}
1e1be8f6 5842
04294e38
ASJ		 5843/**
5844 * i40e_get_global_fd_count - Get total FD filters programmed on device
5845 * @pf: board private structure
5846 **/
5847u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5848{
5849 u32 val, fcnt_prog;
5850
5851 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5852 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5853 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5854 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5855 return fcnt_prog;
5856}
5857
55a5e60b
ASJ		 5858/**
5859 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5860 * @pf: board private structure
5861 **/
5862void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5863{
3487b6c3 5864 struct i40e_fdir_filter *filter;
55a5e60b 5865 u32 fcnt_prog, fcnt_avail;
3487b6c3 5866 struct hlist_node *node;
55a5e60b 5867
1e1be8f6
ASJ		 5868 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5869 return;
5870
55a5e60b
ASJ		 5871 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5872 * to re-enable
5873 */
04294e38 5874 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5875 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5876 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5877 (pf->fd_add_err == 0) ||
5878 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5879 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5880 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5881 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5882 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5883 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5884 }
5885 }
5886 /* Wait for some more space to be available to turn on ATR */
5887 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5888 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5889 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5890 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5891 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5892 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5893 }
5894 }
3487b6c3
CW		 5895
5896 /* if hw had a problem adding a filter, delete it */
5897 if (pf->fd_inv > 0) {
5898 hlist_for_each_entry_safe(filter, node,
5899 &pf->fdir_filter_list, fdir_node) {
5900 if (filter->fd_id == pf->fd_inv) {
5901 hlist_del(&filter->fdir_node);
5902 kfree(filter);
5903 pf->fdir_pf_active_filters--;
5904 }
5905 }
5906 }
55a5e60b
ASJ		 5907}
5908
1e1be8f6 5909#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5910#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5911/**
5912 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5913 * @pf: board private structure
5914 **/
5915static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5916{
04294e38 5917 unsigned long min_flush_time;
1e1be8f6 5918 int flush_wait_retry = 50;
04294e38
ASJ		 5919 bool disable_atr = false;
5920 int fd_room;
1e1be8f6
ASJ		 5921 int reg;
5922
1790ed0c
AA		 5923 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5924 return;
5925
a5fdaf34
JB		 5926 if (!time_after(jiffies, pf->fd_flush_timestamp +
5927 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5928 return;
04294e38 5929
a5fdaf34
JB		 5930 /* If the flush is happening too quick and we have mostly SB rules we
5931 * should not re-enable ATR for some time.
5932 */
5933 min_flush_time = pf->fd_flush_timestamp +
5934 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5935 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5936
5937 if (!(time_after(jiffies, min_flush_time)) &&
5938 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5939 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5940 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5941 disable_atr = true;
5942 }
5943
5944 pf->fd_flush_timestamp = jiffies;
5945 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5946 /* flush all filters */
5947 wr32(&pf->hw, I40E_PFQF_CTL_1,
5948 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5949 i40e_flush(&pf->hw);
5950 pf->fd_flush_cnt++;
5951 pf->fd_add_err = 0;
5952 do {
5953 /* Check FD flush status every 5-6msec */
5954 usleep_range(5000, 6000);
5955 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5956 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5957 break;
5958 } while (flush_wait_retry--);
5959 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5960 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5961 } else {
5962 /* replay sideband filters */
5963 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5964 if (!disable_atr)
5965 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5966 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5967 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5968 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5969 }
a5fdaf34 5970
1e1be8f6
ASJ		 5971}
5972
5973/**
5974 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5975 * @pf: board private structure
5976 **/
04294e38 5977u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5978{
5979 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5980}
5981
5982/* We can see up to 256 filter programming desc in transit if the filters are
5983 * being applied really fast; before we see the first
5984 * filter miss error on Rx queue 0. Accumulating enough error messages before
5985 * reacting will make sure we don't cause flush too often.
5986 */
5987#define I40E_MAX_FD_PROGRAM_ERROR 256
5988
41c445ff
JB		 5989/**
5990 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5991 * @pf: board private structure
5992 **/
5993static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5994{
41c445ff 5995
41c445ff
JB		 5996 /* if interface is down do nothing */
5997 if (test_bit(__I40E_DOWN, &pf->state))
5998 return;
1e1be8f6 5999
1790ed0c
AA		 6000 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
6001 return;
6002
04294e38 6003 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 6004 i40e_fdir_flush_and_replay(pf);
6005
55a5e60b
ASJ		 6006 i40e_fdir_check_and_reenable(pf);
6007
41c445ff
JB		 6008}
6009
6010/**
6011 * i40e_vsi_link_event - notify VSI of a link event
6012 * @vsi: vsi to be notified
6013 * @link_up: link up or down
6014 **/
6015static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
6016{
32b5b811 6017 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 6018 return;
6019
6020 switch (vsi->type) {
6021 case I40E_VSI_MAIN:
38e00438
VD		 6022#ifdef I40E_FCOE
6023 case I40E_VSI_FCOE:
6024#endif
41c445ff
JB		 6025 if (!vsi->netdev || !vsi->netdev_registered)
6026 break;
6027
6028 if (link_up) {
6029 netif_carrier_on(vsi->netdev);
6030 netif_tx_wake_all_queues(vsi->netdev);
6031 } else {
6032 netif_carrier_off(vsi->netdev);
6033 netif_tx_stop_all_queues(vsi->netdev);
6034 }
6035 break;
6036
6037 case I40E_VSI_SRIOV:
41c445ff
JB		 6038 case I40E_VSI_VMDQ2:
6039 case I40E_VSI_CTRL:
6040 case I40E_VSI_MIRROR:
6041 default:
6042 /* there is no notification for other VSIs */
6043 break;
6044 }
6045}
6046
6047/**
6048 * i40e_veb_link_event - notify elements on the veb of a link event
6049 * @veb: veb to be notified
6050 * @link_up: link up or down
6051 **/
6052static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6053{
6054 struct i40e_pf *pf;
6055 int i;
6056
6057 if (!veb || !veb->pf)
6058 return;
6059 pf = veb->pf;
6060
6061 /* depth first... */
6062 for (i = 0; i < I40E_MAX_VEB; i++)
6063 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6064 i40e_veb_link_event(pf->veb[i], link_up);
6065
6066 /* ... now the local VSIs */
505682cd 6067 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6068 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6069 i40e_vsi_link_event(pf->vsi[i], link_up);
6070}
6071
6072/**
6073 * i40e_link_event - Update netif_carrier status
6074 * @pf: board private structure
6075 **/
6076static void i40e_link_event(struct i40e_pf *pf)
6077{
320684cd 6078 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6079 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6080 i40e_status status;
6081 bool new_link, old_link;
41c445ff 6082
1f9610e4
CS		 6083 /* save off old link status information */
6084 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6085
1e701e09
JB		 6086 /* set this to force the get_link_status call to refresh state */
6087 pf->hw.phy.get_link_info = true;
6088
41c445ff 6089 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6090
6091 status = i40e_get_link_status(&pf->hw, &new_link);
6092 if (status) {
6093 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6094 status);
6095 return;
6096 }
6097
fef59ddf
CS		 6098 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6099 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6100
1e701e09 6101 if (new_link == old_link &&
fef59ddf 6102 new_link_speed == old_link_speed &&
320684cd
MW		 6103 (test_bit(__I40E_DOWN, &vsi->state) ||
6104 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6105 return;
320684cd
MW		 6106
6107 if (!test_bit(__I40E_DOWN, &vsi->state))
6108 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6109
6110 /* Notify the base of the switch tree connected to
6111 * the link. Floating VEBs are not notified.
6112 */
6113 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6114 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6115 else
320684cd 6116 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6117
6118 if (pf->vf)
6119 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6120
6121 if (pf->flags & I40E_FLAG_PTP)
6122 i40e_ptp_set_increment(pf);
41c445ff
JB		 6123}
6124
41c445ff 6125/**
21536717 6126 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6127 * @pf: board private structure
6128 **/
6129static void i40e_watchdog_subtask(struct i40e_pf *pf)
6130{
6131 int i;
6132
6133 /* if interface is down do nothing */
6134 if (test_bit(__I40E_DOWN, &pf->state) ||
6135 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6136 return;
6137
21536717
SN		 6138 /* make sure we don't do these things too often */
6139 if (time_before(jiffies, (pf->service_timer_previous +
6140 pf->service_timer_period)))
6141 return;
6142 pf->service_timer_previous = jiffies;
6143
9ac77266
SN		 6144 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6145 i40e_link_event(pf);
21536717 6146
41c445ff
JB		 6147 /* Update the stats for active netdevs so the network stack
6148 * can look at updated numbers whenever it cares to
6149 */
505682cd 6150 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6151 if (pf->vsi[i] && pf->vsi[i]->netdev)
6152 i40e_update_stats(pf->vsi[i]);
6153
d1a8d275
ASJ		 6154 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6155 /* Update the stats for the active switching components */
6156 for (i = 0; i < I40E_MAX_VEB; i++)
6157 if (pf->veb[i])
6158 i40e_update_veb_stats(pf->veb[i]);
6159 }
beb0dff1
JK		 6160
6161 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6162}
6163
6164/**
6165 * i40e_reset_subtask - Set up for resetting the device and driver
6166 * @pf: board private structure
6167 **/
6168static void i40e_reset_subtask(struct i40e_pf *pf)
6169{
6170 u32 reset_flags = 0;
6171
23326186 6172 rtnl_lock();
41c445ff 6173 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6174 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6175 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6176 }
6177 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6178 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6179 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6180 }
6181 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6182 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6183 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6184 }
6185 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6186 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6187 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6188 }
b5d06f05 6189 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6190 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6191 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6192 }
41c445ff
JB		 6193
6194 /* If there's a recovery already waiting, it takes
6195 * precedence before starting a new reset sequence.
6196 */
6197 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6198 i40e_handle_reset_warning(pf);
23326186 6199 goto unlock;
41c445ff
JB		 6200 }
6201
6202 /* If we're already down or resetting, just bail */
6203 if (reset_flags &&
6204 !test_bit(__I40E_DOWN, &pf->state) &&
6205 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6206 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6207
6208unlock:
6209 rtnl_unlock();
41c445ff
JB		 6210}
6211
6212/**
6213 * i40e_handle_link_event - Handle link event
6214 * @pf: board private structure
6215 * @e: event info posted on ARQ
6216 **/
6217static void i40e_handle_link_event(struct i40e_pf *pf,
6218 struct i40e_arq_event_info *e)
6219{
41c445ff
JB		 6220 struct i40e_aqc_get_link_status *status =
6221 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6222
1e701e09
JB		 6223 /* Do a new status request to re-enable LSE reporting
6224 * and load new status information into the hw struct
6225 * This completely ignores any state information
6226 * in the ARQ event info, instead choosing to always
6227 * issue the AQ update link status command.
6228 */
6229 i40e_link_event(pf);
6230
7b592f61
CW		 6231 /* check for unqualified module, if link is down */
6232 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6233 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6234 (!(status->link_info & I40E_AQ_LINK_UP)))
6235 dev_err(&pf->pdev->dev,
6236 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6237}
6238
6239/**
6240 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6241 * @pf: board private structure
6242 **/
6243static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6244{
6245 struct i40e_arq_event_info event;
6246 struct i40e_hw *hw = &pf->hw;
6247 u16 pending, i = 0;
6248 i40e_status ret;
6249 u16 opcode;
86df242b 6250 u32 oldval;
41c445ff
JB		 6251 u32 val;
6252
a316f651
ASJ		 6253 /* Do not run clean AQ when PF reset fails */
6254 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6255 return;
6256
86df242b
SN		 6257 /* check for error indications */
6258 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6259 oldval = val;
6260 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6261 if (hw->debug_mask & I40E_DEBUG_AQ)
6262 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6263 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6264 }
6265 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6266 if (hw->debug_mask & I40E_DEBUG_AQ)
6267 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b 6268 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
1d0a4ada 6269 pf->arq_overflows++;
86df242b
SN		 6270 }
6271 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6272 if (hw->debug_mask & I40E_DEBUG_AQ)
6273 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6274 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6275 }
6276 if (oldval != val)
6277 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6278
6279 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6280 oldval = val;
6281 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6282 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6283 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6284 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6285 }
6286 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6287 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6288 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6289 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6290 }
6291 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6292 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6293 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6294 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6295 }
6296 if (oldval != val)
6297 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6298
1001dc37
MW		 6299 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6300 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6301 if (!event.msg_buf)
6302 return;
6303
6304 do {
6305 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6306 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6307 break;
56497978 6308 else if (ret) {
41c445ff
JB		 6309 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6310 break;
6311 }
6312
6313 opcode = le16_to_cpu(event.desc.opcode);
6314 switch (opcode) {
6315
6316 case i40e_aqc_opc_get_link_status:
6317 i40e_handle_link_event(pf, &event);
6318 break;
6319 case i40e_aqc_opc_send_msg_to_pf:
6320 ret = i40e_vc_process_vf_msg(pf,
6321 le16_to_cpu(event.desc.retval),
6322 le32_to_cpu(event.desc.cookie_high),
6323 le32_to_cpu(event.desc.cookie_low),
6324 event.msg_buf,
1001dc37 6325 event.msg_len);
41c445ff
JB		 6326 break;
6327 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6328 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6329#ifdef CONFIG_I40E_DCB
6330 rtnl_lock();
6331 ret = i40e_handle_lldp_event(pf, &event);
6332 rtnl_unlock();
6333#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6334 break;
6335 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6336 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6337 i40e_handle_lan_overflow_event(pf, &event);
6338 break;
0467bc91
SN		 6339 case i40e_aqc_opc_send_msg_to_peer:
6340 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6341 break;
91a0f930
SN		 6342 case i40e_aqc_opc_nvm_erase:
6343 case i40e_aqc_opc_nvm_update:
00ada50d 6344 case i40e_aqc_opc_oem_post_update:
91a0f930
SN		 6345 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6346 break;
41c445ff
JB		 6347 default:
6348 dev_info(&pf->pdev->dev,
0467bc91
SN		 6349 "ARQ Error: Unknown event 0x%04x received\n",
6350 opcode);
41c445ff
JB		 6351 break;
6352 }
6353 } while (pending && (i++ < pf->adminq_work_limit));
6354
6355 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6356 /* re-enable Admin queue interrupt cause */
6357 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6358 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6359 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6360 i40e_flush(hw);
6361
6362 kfree(event.msg_buf);
6363}
6364
4eb3f768
SN		 6365/**
6366 * i40e_verify_eeprom - make sure eeprom is good to use
6367 * @pf: board private structure
6368 **/
6369static void i40e_verify_eeprom(struct i40e_pf *pf)
6370{
6371 int err;
6372
6373 err = i40e_diag_eeprom_test(&pf->hw);
6374 if (err) {
6375 /* retry in case of garbage read */
6376 err = i40e_diag_eeprom_test(&pf->hw);
6377 if (err) {
6378 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6379 err);
6380 set_bit(__I40E_BAD_EEPROM, &pf->state);
6381 }
6382 }
6383
6384 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6385 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6386 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6387 }
6388}
6389
386a0afa
AA		 6390/**
6391 * i40e_enable_pf_switch_lb
b40c82e6 6392 * @pf: pointer to the PF structure
386a0afa
AA		 6393 *
6394 * enable switch loop back or die - no point in a return value
6395 **/
6396static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6397{
6398 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6399 struct i40e_vsi_context ctxt;
f1c7e72e 6400 int ret;
386a0afa
AA		 6401
6402 ctxt.seid = pf->main_vsi_seid;
6403 ctxt.pf_num = pf->hw.pf_id;
6404 ctxt.vf_num = 0;
f1c7e72e
SN		 6405 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6406 if (ret) {
386a0afa 6407 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6408 "couldn't get PF vsi config, err %s aq_err %s\n",
6409 i40e_stat_str(&pf->hw, ret),
6410 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6411 return;
6412 }
6413 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6414 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6415 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6416
f1c7e72e
SN		 6417 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6418 if (ret) {
386a0afa 6419 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6420 "update vsi switch failed, err %s aq_err %s\n",
6421 i40e_stat_str(&pf->hw, ret),
6422 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6423 }
6424}
6425
6426/**
6427 * i40e_disable_pf_switch_lb
b40c82e6 6428 * @pf: pointer to the PF structure
386a0afa
AA		 6429 *
6430 * disable switch loop back or die - no point in a return value
6431 **/
6432static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6433{
6434 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6435 struct i40e_vsi_context ctxt;
f1c7e72e 6436 int ret;
386a0afa
AA		 6437
6438 ctxt.seid = pf->main_vsi_seid;
6439 ctxt.pf_num = pf->hw.pf_id;
6440 ctxt.vf_num = 0;
f1c7e72e
SN		 6441 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6442 if (ret) {
386a0afa 6443 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6444 "couldn't get PF vsi config, err %s aq_err %s\n",
6445 i40e_stat_str(&pf->hw, ret),
6446 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6447 return;
6448 }
6449 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6450 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6451 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6452
f1c7e72e
SN		 6453 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6454 if (ret) {
386a0afa 6455 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6456 "update vsi switch failed, err %s aq_err %s\n",
6457 i40e_stat_str(&pf->hw, ret),
6458 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6459 }
6460}
6461
51616018
NP		 6462/**
6463 * i40e_config_bridge_mode - Configure the HW bridge mode
6464 * @veb: pointer to the bridge instance
6465 *
6466 * Configure the loop back mode for the LAN VSI that is downlink to the
6467 * specified HW bridge instance. It is expected this function is called
6468 * when a new HW bridge is instantiated.
6469 **/
6470static void i40e_config_bridge_mode(struct i40e_veb *veb)
6471{
6472 struct i40e_pf *pf = veb->pf;
6473
6dec1017
SN		 6474 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6475 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6476 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6477 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6478 i40e_disable_pf_switch_lb(pf);
6479 else
6480 i40e_enable_pf_switch_lb(pf);
6481}
6482
41c445ff
JB		 6483/**
6484 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6485 * @veb: pointer to the VEB instance
6486 *
6487 * This is a recursive function that first builds the attached VSIs then
6488 * recurses in to build the next layer of VEB. We track the connections
6489 * through our own index numbers because the seid's from the HW could
6490 * change across the reset.
6491 **/
6492static int i40e_reconstitute_veb(struct i40e_veb *veb)
6493{
6494 struct i40e_vsi *ctl_vsi = NULL;
6495 struct i40e_pf *pf = veb->pf;
6496 int v, veb_idx;
6497 int ret;
6498
6499 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6500 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6501 if (pf->vsi[v] &&
6502 pf->vsi[v]->veb_idx == veb->idx &&
6503 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6504 ctl_vsi = pf->vsi[v];
6505 break;
6506 }
6507 }
6508 if (!ctl_vsi) {
6509 dev_info(&pf->pdev->dev,
6510 "missing owner VSI for veb_idx %d\n", veb->idx);
6511 ret = -ENOENT;
6512 goto end_reconstitute;
6513 }
6514 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6515 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6516 ret = i40e_add_vsi(ctl_vsi);
6517 if (ret) {
6518 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6519 "rebuild of veb_idx %d owner VSI failed: %d\n",
6520 veb->idx, ret);
41c445ff
JB		 6521 goto end_reconstitute;
6522 }
6523 i40e_vsi_reset_stats(ctl_vsi);
6524
6525 /* create the VEB in the switch and move the VSI onto the VEB */
6526 ret = i40e_add_veb(veb, ctl_vsi);
6527 if (ret)
6528 goto end_reconstitute;
6529
fc60861e
ASJ		 6530 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6531 veb->bridge_mode = BRIDGE_MODE_VEB;
6532 else
6533 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6534 i40e_config_bridge_mode(veb);
b64ba084 6535
41c445ff 6536 /* create the remaining VSIs attached to this VEB */
505682cd 6537 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6538 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6539 continue;
6540
6541 if (pf->vsi[v]->veb_idx == veb->idx) {
6542 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6543
41c445ff
JB		 6544 vsi->uplink_seid = veb->seid;
6545 ret = i40e_add_vsi(vsi);
6546 if (ret) {
6547 dev_info(&pf->pdev->dev,
6548 "rebuild of vsi_idx %d failed: %d\n",
6549 v, ret);
6550 goto end_reconstitute;
6551 }
6552 i40e_vsi_reset_stats(vsi);
6553 }
6554 }
6555
6556 /* create any VEBs attached to this VEB - RECURSION */
6557 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6558 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6559 pf->veb[veb_idx]->uplink_seid = veb->seid;
6560 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6561 if (ret)
6562 break;
6563 }
6564 }
6565
6566end_reconstitute:
6567 return ret;
6568}
6569
6570/**
6571 * i40e_get_capabilities - get info about the HW
6572 * @pf: the PF struct
6573 **/
6574static int i40e_get_capabilities(struct i40e_pf *pf)
6575{
6576 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6577 u16 data_size;
6578 int buf_len;
6579 int err;
6580
6581 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6582 do {
6583 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6584 if (!cap_buf)
6585 return -ENOMEM;
6586
6587 /* this loads the data into the hw struct for us */
6588 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6589 &data_size,
6590 i40e_aqc_opc_list_func_capabilities,
6591 NULL);
6592 /* data loaded, buffer no longer needed */
6593 kfree(cap_buf);
6594
6595 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6596 /* retry with a larger buffer */
6597 buf_len = data_size;
6598 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6599 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6600 "capability discovery failed, err %s aq_err %s\n",
6601 i40e_stat_str(&pf->hw, err),
6602 i40e_aq_str(&pf->hw,
6603 pf->hw.aq.asq_last_status));
41c445ff
JB		 6604 return -ENODEV;
6605 }
6606 } while (err);
6607
6608 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6609 dev_info(&pf->pdev->dev,
6610 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6611 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6612 pf->hw.func_caps.num_msix_vectors,
6613 pf->hw.func_caps.num_msix_vectors_vf,
6614 pf->hw.func_caps.fd_filters_guaranteed,
6615 pf->hw.func_caps.fd_filters_best_effort,
6616 pf->hw.func_caps.num_tx_qp,
6617 pf->hw.func_caps.num_vsis);
6618
7134f9ce
JB		 6619#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6620 + pf->hw.func_caps.num_vfs)
6621 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6622 dev_info(&pf->pdev->dev,
6623 "got num_vsis %d, setting num_vsis to %d\n",
6624 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6625 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6626 }
6627
41c445ff
JB		 6628 return 0;
6629}
6630
cbf61325
ASJ		 6631static int i40e_vsi_clear(struct i40e_vsi *vsi);
6632
41c445ff 6633/**
cbf61325 6634 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6635 * @pf: board private structure
6636 **/
cbf61325 6637static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6638{
6639 struct i40e_vsi *vsi;
8a9eb7d3 6640 int i;
41c445ff 6641
407e063c
JB		 6642 /* quick workaround for an NVM issue that leaves a critical register
6643 * uninitialized
6644 */
6645 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6646 static const u32 hkey[] = {
6647 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6648 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6649 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6650 0x95b3a76d};
6651
6652 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6653 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6654 }
6655
cbf61325 6656 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6657 return;
6658
cbf61325 6659 /* find existing VSI and see if it needs configuring */
41c445ff 6660 vsi = NULL;
505682cd 6661 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6662 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6663 vsi = pf->vsi[i];
cbf61325
ASJ		 6664 break;
6665 }
6666 }
6667
6668 /* create a new VSI if none exists */
41c445ff 6669 if (!vsi) {
cbf61325
ASJ		 6670 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6671 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6672 if (!vsi) {
6673 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6674 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6675 return;
41c445ff 6676 }
cbf61325 6677 }
41c445ff 6678
8a9eb7d3 6679 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6680}
6681
6682/**
6683 * i40e_fdir_teardown - release the Flow Director resources
6684 * @pf: board private structure
6685 **/
6686static void i40e_fdir_teardown(struct i40e_pf *pf)
6687{
6688 int i;
6689
17a73f6b 6690 i40e_fdir_filter_exit(pf);
505682cd 6691 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6692 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6693 i40e_vsi_release(pf->vsi[i]);
6694 break;
6695 }
6696 }
6697}
6698
6699/**
f650a38b 6700 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6701 * @pf: board private structure
6702 *
b40c82e6 6703 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6704 **/
23cfbe07 6705static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6706{
41c445ff 6707 struct i40e_hw *hw = &pf->hw;
60442dea 6708 i40e_status ret = 0;
41c445ff
JB		 6709 u32 v;
6710
6711 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6712 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6713 return;
41c445ff 6714
69bfb110 6715 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6716
41c445ff
JB		 6717 /* quiesce the VSIs and their queues that are not already DOWN */
6718 i40e_pf_quiesce_all_vsi(pf);
6719
505682cd 6720 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6721 if (pf->vsi[v])
6722 pf->vsi[v]->seid = 0;
6723 }
6724
6725 i40e_shutdown_adminq(&pf->hw);
6726
f650a38b 6727 /* call shutdown HMC */
60442dea
SN		 6728 if (hw->hmc.hmc_obj) {
6729 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6730 if (ret)
60442dea
SN		 6731 dev_warn(&pf->pdev->dev,
6732 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6733 }
f650a38b
ASJ		 6734}
6735
44033fac
JB		 6736/**
6737 * i40e_send_version - update firmware with driver version
6738 * @pf: PF struct
6739 */
6740static void i40e_send_version(struct i40e_pf *pf)
6741{
6742 struct i40e_driver_version dv;
6743
6744 dv.major_version = DRV_VERSION_MAJOR;
6745 dv.minor_version = DRV_VERSION_MINOR;
6746 dv.build_version = DRV_VERSION_BUILD;
6747 dv.subbuild_version = 0;
35a7d804 6748 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6749 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6750}
6751
f650a38b 6752/**
4dda12e6 6753 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6754 * @pf: board private structure
bc7d338f 6755 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6756 **/
bc7d338f 6757static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6758{
f650a38b 6759 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6760 u8 set_fc_aq_fail = 0;
f650a38b 6761 i40e_status ret;
4f2f017c 6762 u32 val;
f650a38b
ASJ		 6763 u32 v;
6764
41c445ff
JB		 6765 /* Now we wait for GRST to settle out.
6766 * We don't have to delete the VEBs or VSIs from the hw switch
6767 * because the reset will make them disappear.
6768 */
6769 ret = i40e_pf_reset(hw);
b5565400 6770 if (ret) {
41c445ff 6771 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6772 set_bit(__I40E_RESET_FAILED, &pf->state);
6773 goto clear_recovery;
b5565400 6774 }
41c445ff
JB		 6775 pf->pfr_count++;
6776
6777 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6778 goto clear_recovery;
69bfb110 6779 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6780
6781 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6782 ret = i40e_init_adminq(&pf->hw);
6783 if (ret) {
f1c7e72e
SN		 6784 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6785 i40e_stat_str(&pf->hw, ret),
6786 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6787 goto clear_recovery;
41c445ff
JB		 6788 }
6789
4eb3f768 6790 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6791 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6792 i40e_verify_eeprom(pf);
4eb3f768 6793
e78ac4bf 6794 i40e_clear_pxe_mode(hw);
41c445ff 6795 ret = i40e_get_capabilities(pf);
f1c7e72e 6796 if (ret)
41c445ff 6797 goto end_core_reset;
41c445ff 6798
41c445ff
JB		 6799 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6800 hw->func_caps.num_rx_qp,
6801 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6802 if (ret) {
6803 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6804 goto end_core_reset;
6805 }
6806 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6807 if (ret) {
6808 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6809 goto end_core_reset;
6810 }
6811
4e3b35b0
NP		 6812#ifdef CONFIG_I40E_DCB
6813 ret = i40e_init_pf_dcb(pf);
6814 if (ret) {
aebfc816
SN		 6815 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6816 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6817 /* Continue without DCB enabled */
4e3b35b0
NP		 6818 }
6819#endif /* CONFIG_I40E_DCB */
38e00438 6820#ifdef I40E_FCOE
21364bcf 6821 i40e_init_pf_fcoe(pf);
4e3b35b0 6822
38e00438 6823#endif
41c445ff 6824 /* do basic switch setup */
bc7d338f 6825 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6826 if (ret)
6827 goto end_core_reset;
6828
7e2453fe
JB		 6829 /* driver is only interested in link up/down and module qualification
6830 * reports from firmware
6831 */
6832 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6833 I40E_AQ_EVENT_LINK_UPDOWN |
6834 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6835 if (ret)
f1c7e72e
SN		 6836 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6837 i40e_stat_str(&pf->hw, ret),
6838 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6839
cafa2ee6
ASJ		 6840 /* make sure our flow control settings are restored */
6841 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6842 if (ret)
8279e495
NP		 6843 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6844 i40e_stat_str(&pf->hw, ret),
6845 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6846
41c445ff
JB		 6847 /* Rebuild the VSIs and VEBs that existed before reset.
6848 * They are still in our local switch element arrays, so only
6849 * need to rebuild the switch model in the HW.
6850 *
6851 * If there were VEBs but the reconstitution failed, we'll try
6852 * try to recover minimal use by getting the basic PF VSI working.
6853 */
6854 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6855 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6856 /* find the one VEB connected to the MAC, and find orphans */
6857 for (v = 0; v < I40E_MAX_VEB; v++) {
6858 if (!pf->veb[v])
6859 continue;
6860
6861 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6862 pf->veb[v]->uplink_seid == 0) {
6863 ret = i40e_reconstitute_veb(pf->veb[v]);
6864
6865 if (!ret)
6866 continue;
6867
6868 /* If Main VEB failed, we're in deep doodoo,
6869 * so give up rebuilding the switch and set up
6870 * for minimal rebuild of PF VSI.
6871 * If orphan failed, we'll report the error
6872 * but try to keep going.
6873 */
6874 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6875 dev_info(&pf->pdev->dev,
6876 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6877 ret);
6878 pf->vsi[pf->lan_vsi]->uplink_seid
6879 = pf->mac_seid;
6880 break;
6881 } else if (pf->veb[v]->uplink_seid == 0) {
6882 dev_info(&pf->pdev->dev,
6883 "rebuild of orphan VEB failed: %d\n",
6884 ret);
6885 }
6886 }
6887 }
6888 }
6889
6890 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6891 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6892 /* no VEB, so rebuild only the Main VSI */
6893 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6894 if (ret) {
6895 dev_info(&pf->pdev->dev,
6896 "rebuild of Main VSI failed: %d\n", ret);
6897 goto end_core_reset;
6898 }
6899 }
6900
4f2f017c
ASJ		 6901 /* Reconfigure hardware for allowing smaller MSS in the case
6902 * of TSO, so that we avoid the MDD being fired and causing
6903 * a reset in the case of small MSS+TSO.
6904 */
6905#define I40E_REG_MSS 0x000E64DC
6906#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6907#define I40E_64BYTE_MSS 0x400000
6908 val = rd32(hw, I40E_REG_MSS);
6909 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6910 val &= ~I40E_REG_MSS_MIN_MASK;
6911 val |= I40E_64BYTE_MSS;
6912 wr32(hw, I40E_REG_MSS, val);
6913 }
6914
8eed76fa 6915 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 6916 msleep(75);
6917 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6918 if (ret)
f1c7e72e
SN		 6919 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6920 i40e_stat_str(&pf->hw, ret),
6921 i40e_aq_str(&pf->hw,
6922 pf->hw.aq.asq_last_status));
cafa2ee6 6923 }
41c445ff
JB		 6924 /* reinit the misc interrupt */
6925 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6926 ret = i40e_setup_misc_vector(pf);
6927
e7358f54
ASJ		 6928 /* Add a filter to drop all Flow control frames from any VSI from being
6929 * transmitted. By doing so we stop a malicious VF from sending out
6930 * PAUSE or PFC frames and potentially controlling traffic for other
6931 * PF/VF VSIs.
6932 * The FW can still send Flow control frames if enabled.
6933 */
6934 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6935 pf->main_vsi_seid);
6936
41c445ff
JB		 6937 /* restart the VSIs that were rebuilt and running before the reset */
6938 i40e_pf_unquiesce_all_vsi(pf);
6939
69f64b2b
MW		 6940 if (pf->num_alloc_vfs) {
6941 for (v = 0; v < pf->num_alloc_vfs; v++)
6942 i40e_reset_vf(&pf->vf[v], true);
6943 }
6944
41c445ff 6945 /* tell the firmware that we're starting */
44033fac 6946 i40e_send_version(pf);
41c445ff
JB		 6947
6948end_core_reset:
a316f651
ASJ		 6949 clear_bit(__I40E_RESET_FAILED, &pf->state);
6950clear_recovery:
41c445ff
JB		 6951 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6952}
6953
f650a38b 6954/**
b40c82e6 6955 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6956 * @pf: board private structure
6957 *
6958 * Close up the VFs and other things in prep for a Core Reset,
6959 * then get ready to rebuild the world.
6960 **/
6961static void i40e_handle_reset_warning(struct i40e_pf *pf)
6962{
23cfbe07
SN		 6963 i40e_prep_for_reset(pf);
6964 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6965}
6966
41c445ff
JB		 6967/**
6968 * i40e_handle_mdd_event
b40c82e6 6969 * @pf: pointer to the PF structure
41c445ff
JB		 6970 *
6971 * Called from the MDD irq handler to identify possibly malicious vfs
6972 **/
6973static void i40e_handle_mdd_event(struct i40e_pf *pf)
6974{
6975 struct i40e_hw *hw = &pf->hw;
6976 bool mdd_detected = false;
df430b12 6977 bool pf_mdd_detected = false;
41c445ff
JB		 6978 struct i40e_vf *vf;
6979 u32 reg;
6980 int i;
6981
6982 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6983 return;
6984
6985 /* find what triggered the MDD event */
6986 reg = rd32(hw, I40E_GL_MDET_TX);
6987 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6988 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6989 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6990 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6991 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6992 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6993 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6994 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6995 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6996 pf->hw.func_caps.base_queue;
faf32978 6997 if (netif_msg_tx_err(pf))
b40c82e6 6998 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6999 event, queue, pf_num, vf_num);
41c445ff
JB		 7000 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
7001 mdd_detected = true;
7002 }
7003 reg = rd32(hw, I40E_GL_MDET_RX);
7004 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 7005 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
7006 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 7007 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 7008 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 7009 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
7010 I40E_GL_MDET_RX_QUEUE_SHIFT) -
7011 pf->hw.func_caps.base_queue;
faf32978
JB		 7012 if (netif_msg_rx_err(pf))
7013 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
7014 event, queue, func);
41c445ff
JB		 7015 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
7016 mdd_detected = true;
7017 }
7018
df430b12
NP		 7019 if (mdd_detected) {
7020 reg = rd32(hw, I40E_PF_MDET_TX);
7021 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
7022 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 7023 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 7024 pf_mdd_detected = true;
7025 }
7026 reg = rd32(hw, I40E_PF_MDET_RX);
7027 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
7028 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 7029 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 7030 pf_mdd_detected = true;
7031 }
7032 /* Queue belongs to the PF, initiate a reset */
7033 if (pf_mdd_detected) {
7034 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7035 i40e_service_event_schedule(pf);
7036 }
7037 }
7038
41c445ff
JB		 7039 /* see if one of the VFs needs its hand slapped */
7040 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7041 vf = &(pf->vf[i]);
7042 reg = rd32(hw, I40E_VP_MDET_TX(i));
7043 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7044 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7045 vf->num_mdd_events++;
faf32978
JB		 7046 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7047 i);
41c445ff
JB		 7048 }
7049
7050 reg = rd32(hw, I40E_VP_MDET_RX(i));
7051 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7052 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7053 vf->num_mdd_events++;
faf32978
JB		 7054 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7055 i);
41c445ff
JB		 7056 }
7057
7058 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7059 dev_info(&pf->pdev->dev,
7060 "Too many MDD events on VF %d, disabled\n", i);
7061 dev_info(&pf->pdev->dev,
7062 "Use PF Control I/F to re-enable the VF\n");
7063 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7064 }
7065 }
7066
7067 /* re-enable mdd interrupt cause */
7068 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7069 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7070 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7071 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7072 i40e_flush(hw);
7073}
7074
a1c9a9d9 7075/**
6a899024 7076 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7077 * @pf: board private structure
7078 **/
6a899024 7079static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7080{
6a899024 7081#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9
JK		 7082 struct i40e_hw *hw = &pf->hw;
7083 i40e_status ret;
a1c9a9d9
JK		 7084 __be16 port;
7085 int i;
7086
6a899024 7087 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7088 return;
7089
6a899024 7090 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7091
7092 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7093 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7094 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7095 port = pf->udp_ports[i].index;
c22c06c8
SN		 7096 if (port)
7097 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7098 pf->udp_ports[i].type,
c22c06c8
SN		 7099 NULL, NULL);
7100 else
7101 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7102
7103 if (ret) {
c22c06c8 7104 dev_info(&pf->pdev->dev,
f1c7e72e 7105 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 7106 port ? "add" : "delete",
f1c7e72e
SN		 7107 ntohs(port), i,
7108 i40e_stat_str(&pf->hw, ret),
7109 i40e_aq_str(&pf->hw,
7110 pf->hw.aq.asq_last_status));
6a899024 7111 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7112 }
7113 }
7114 }
6a899024 7115#endif
a1c9a9d9
JK		 7116}
7117
41c445ff
JB		 7118/**
7119 * i40e_service_task - Run the driver's async subtasks
7120 * @work: pointer to work_struct containing our data
7121 **/
7122static void i40e_service_task(struct work_struct *work)
7123{
7124 struct i40e_pf *pf = container_of(work,
7125 struct i40e_pf,
7126 service_task);
7127 unsigned long start_time = jiffies;
7128
e57a2fea
SN		 7129 /* don't bother with service tasks if a reset is in progress */
7130 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7131 i40e_service_event_complete(pf);
7132 return;
7133 }
7134
b03a8c1f 7135 i40e_detect_recover_hung(pf);
41c445ff
JB		 7136 i40e_reset_subtask(pf);
7137 i40e_handle_mdd_event(pf);
7138 i40e_vc_process_vflr_event(pf);
7139 i40e_watchdog_subtask(pf);
7140 i40e_fdir_reinit_subtask(pf);
41c445ff 7141 i40e_sync_filters_subtask(pf);
6a899024 7142 i40e_sync_udp_filters_subtask(pf);
41c445ff
JB		 7143 i40e_clean_adminq_subtask(pf);
7144
7145 i40e_service_event_complete(pf);
7146
7147 /* If the tasks have taken longer than one timer cycle or there
7148 * is more work to be done, reschedule the service task now
7149 * rather than wait for the timer to tick again.
7150 */
7151 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7152 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7153 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7154 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7155 i40e_service_event_schedule(pf);
7156}
7157
7158/**
7159 * i40e_service_timer - timer callback
7160 * @data: pointer to PF struct
7161 **/
7162static void i40e_service_timer(unsigned long data)
7163{
7164 struct i40e_pf *pf = (struct i40e_pf *)data;
7165
7166 mod_timer(&pf->service_timer,
7167 round_jiffies(jiffies + pf->service_timer_period));
7168 i40e_service_event_schedule(pf);
7169}
7170
7171/**
7172 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7173 * @vsi: the VSI being configured
7174 **/
7175static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7176{
7177 struct i40e_pf *pf = vsi->back;
7178
7179 switch (vsi->type) {
7180 case I40E_VSI_MAIN:
7181 vsi->alloc_queue_pairs = pf->num_lan_qps;
7182 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7183 I40E_REQ_DESCRIPTOR_MULTIPLE);
7184 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7185 vsi->num_q_vectors = pf->num_lan_msix;
7186 else
7187 vsi->num_q_vectors = 1;
7188
7189 break;
7190
7191 case I40E_VSI_FDIR:
7192 vsi->alloc_queue_pairs = 1;
7193 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7194 I40E_REQ_DESCRIPTOR_MULTIPLE);
7195 vsi->num_q_vectors = 1;
7196 break;
7197
7198 case I40E_VSI_VMDQ2:
7199 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7200 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7201 I40E_REQ_DESCRIPTOR_MULTIPLE);
7202 vsi->num_q_vectors = pf->num_vmdq_msix;
7203 break;
7204
7205 case I40E_VSI_SRIOV:
7206 vsi->alloc_queue_pairs = pf->num_vf_qps;
7207 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7208 I40E_REQ_DESCRIPTOR_MULTIPLE);
7209 break;
7210
38e00438
VD		 7211#ifdef I40E_FCOE
7212 case I40E_VSI_FCOE:
7213 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7214 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7215 I40E_REQ_DESCRIPTOR_MULTIPLE);
7216 vsi->num_q_vectors = pf->num_fcoe_msix;
7217 break;
7218
7219#endif /* I40E_FCOE */
41c445ff
JB		 7220 default:
7221 WARN_ON(1);
7222 return -ENODATA;
7223 }
7224
7225 return 0;
7226}
7227
f650a38b
ASJ		 7228/**
7229 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7230 * @type: VSI pointer
bc7d338f 7231 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7232 *
7233 * On error: returns error code (negative)
7234 * On success: returns 0
7235 **/
bc7d338f 7236static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7237{
7238 int size;
7239 int ret = 0;
7240
ac6c5e3d 7241 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7242 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7243 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7244 if (!vsi->tx_rings)
7245 return -ENOMEM;
f650a38b
ASJ		 7246 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7247
bc7d338f
ASJ		 7248 if (alloc_qvectors) {
7249 /* allocate memory for q_vector pointers */
f57e4fbd 7250 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7251 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7252 if (!vsi->q_vectors) {
7253 ret = -ENOMEM;
7254 goto err_vectors;
7255 }
f650a38b
ASJ		 7256 }
7257 return ret;
7258
7259err_vectors:
7260 kfree(vsi->tx_rings);
7261 return ret;
7262}
7263
41c445ff
JB		 7264/**
7265 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7266 * @pf: board private structure
7267 * @type: type of VSI
7268 *
7269 * On error: returns error code (negative)
7270 * On success: returns vsi index in PF (positive)
7271 **/
7272static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7273{
7274 int ret = -ENODEV;
7275 struct i40e_vsi *vsi;
7276 int vsi_idx;
7277 int i;
7278
7279 /* Need to protect the allocation of the VSIs at the PF level */
7280 mutex_lock(&pf->switch_mutex);
7281
7282 /* VSI list may be fragmented if VSI creation/destruction has
7283 * been happening. We can afford to do a quick scan to look
7284 * for any free VSIs in the list.
7285 *
7286 * find next empty vsi slot, looping back around if necessary
7287 */
7288 i = pf->next_vsi;
505682cd 7289 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7290 i++;
505682cd 7291 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7292 i = 0;
7293 while (i < pf->next_vsi && pf->vsi[i])
7294 i++;
7295 }
7296
505682cd 7297 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7298 vsi_idx = i; /* Found one! */
7299 } else {
7300 ret = -ENODEV;
493fb300 7301 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7302 }
7303 pf->next_vsi = ++i;
7304
7305 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7306 if (!vsi) {
7307 ret = -ENOMEM;
493fb300 7308 goto unlock_pf;
41c445ff
JB		 7309 }
7310 vsi->type = type;
7311 vsi->back = pf;
7312 set_bit(__I40E_DOWN, &vsi->state);
7313 vsi->flags = 0;
7314 vsi->idx = vsi_idx;
7315 vsi->rx_itr_setting = pf->rx_itr_default;
7316 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7317 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7318 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7319 pf->rss_table_size : 64;
41c445ff
JB		 7320 vsi->netdev_registered = false;
7321 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7322 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7323 vsi->irqs_ready = false;
41c445ff 7324
9f65e15b
AD		 7325 ret = i40e_set_num_rings_in_vsi(vsi);
7326 if (ret)
7327 goto err_rings;
7328
bc7d338f 7329 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7330 if (ret)
9f65e15b 7331 goto err_rings;
493fb300 7332
41c445ff
JB		 7333 /* Setup default MSIX irq handler for VSI */
7334 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7335
21659035
KP		 7336 /* Initialize VSI lock */
7337 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7338 pf->vsi[vsi_idx] = vsi;
7339 ret = vsi_idx;
493fb300
AD		 7340 goto unlock_pf;
7341
9f65e15b 7342err_rings:
493fb300
AD		 7343 pf->next_vsi = i - 1;
7344 kfree(vsi);
7345unlock_pf:
41c445ff
JB		 7346 mutex_unlock(&pf->switch_mutex);
7347 return ret;
7348}
7349
f650a38b
ASJ		 7350/**
7351 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7352 * @type: VSI pointer
bc7d338f 7353 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7354 *
7355 * On error: returns error code (negative)
7356 * On success: returns 0
7357 **/
bc7d338f 7358static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7359{
7360 /* free the ring and vector containers */
bc7d338f
ASJ		 7361 if (free_qvectors) {
7362 kfree(vsi->q_vectors);
7363 vsi->q_vectors = NULL;
7364 }
f650a38b
ASJ		 7365 kfree(vsi->tx_rings);
7366 vsi->tx_rings = NULL;
7367 vsi->rx_rings = NULL;
7368}
7369
28c5869f
HZ		 7370/**
7371 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7372 * and lookup table
7373 * @vsi: Pointer to VSI structure
7374 */
7375static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7376{
7377 if (!vsi)
7378 return;
7379
7380 kfree(vsi->rss_hkey_user);
7381 vsi->rss_hkey_user = NULL;
7382
7383 kfree(vsi->rss_lut_user);
7384 vsi->rss_lut_user = NULL;
7385}
7386
41c445ff
JB		 7387/**
7388 * i40e_vsi_clear - Deallocate the VSI provided
7389 * @vsi: the VSI being un-configured
7390 **/
7391static int i40e_vsi_clear(struct i40e_vsi *vsi)
7392{
7393 struct i40e_pf *pf;
7394
7395 if (!vsi)
7396 return 0;
7397
7398 if (!vsi->back)
7399 goto free_vsi;
7400 pf = vsi->back;
7401
7402 mutex_lock(&pf->switch_mutex);
7403 if (!pf->vsi[vsi->idx]) {
7404 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7405 vsi->idx, vsi->idx, vsi, vsi->type);
7406 goto unlock_vsi;
7407 }
7408
7409 if (pf->vsi[vsi->idx] != vsi) {
7410 dev_err(&pf->pdev->dev,
7411 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7412 pf->vsi[vsi->idx]->idx,
7413 pf->vsi[vsi->idx],
7414 pf->vsi[vsi->idx]->type,
7415 vsi->idx, vsi, vsi->type);
7416 goto unlock_vsi;
7417 }
7418
b40c82e6 7419 /* updates the PF for this cleared vsi */
41c445ff
JB		 7420 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7421 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7422
bc7d338f 7423 i40e_vsi_free_arrays(vsi, true);
28c5869f 7424 i40e_clear_rss_config_user(vsi);
493fb300 7425
41c445ff
JB		 7426 pf->vsi[vsi->idx] = NULL;
7427 if (vsi->idx < pf->next_vsi)
7428 pf->next_vsi = vsi->idx;
7429
7430unlock_vsi:
7431 mutex_unlock(&pf->switch_mutex);
7432free_vsi:
7433 kfree(vsi);
7434
7435 return 0;
7436}
7437
9f65e15b
AD		 7438/**
7439 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7440 * @vsi: the VSI being cleaned
7441 **/
be1d5eea 7442static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7443{
7444 int i;
7445
8e9dca53 7446 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7447 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7448 kfree_rcu(vsi->tx_rings[i], rcu);
7449 vsi->tx_rings[i] = NULL;
7450 vsi->rx_rings[i] = NULL;
7451 }
be1d5eea 7452 }
9f65e15b
AD		 7453}
7454
41c445ff
JB		 7455/**
7456 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7457 * @vsi: the VSI being configured
7458 **/
7459static int i40e_alloc_rings(struct i40e_vsi *vsi)
7460{
e7046ee1 7461 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7462 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7463 int i;
7464
41c445ff 7465 /* Set basic values in the rings to be used later during open() */
d7397644 7466 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7467 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7468 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7469 if (!tx_ring)
7470 goto err_out;
41c445ff
JB		 7471
7472 tx_ring->queue_index = i;
7473 tx_ring->reg_idx = vsi->base_queue + i;
7474 tx_ring->ring_active = false;
7475 tx_ring->vsi = vsi;
7476 tx_ring->netdev = vsi->netdev;
7477 tx_ring->dev = &pf->pdev->dev;
7478 tx_ring->count = vsi->num_desc;
7479 tx_ring->size = 0;
7480 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7481 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7482 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7483 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7484 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7485 vsi->tx_rings[i] = tx_ring;
41c445ff 7486
9f65e15b 7487 rx_ring = &tx_ring[1];
41c445ff
JB		 7488 rx_ring->queue_index = i;
7489 rx_ring->reg_idx = vsi->base_queue + i;
7490 rx_ring->ring_active = false;
7491 rx_ring->vsi = vsi;
7492 rx_ring->netdev = vsi->netdev;
7493 rx_ring->dev = &pf->pdev->dev;
7494 rx_ring->count = vsi->num_desc;
7495 rx_ring->size = 0;
7496 rx_ring->dcb_tc = 0;
7497 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7498 set_ring_16byte_desc_enabled(rx_ring);
7499 else
7500 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7501 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7502 }
7503
7504 return 0;
9f65e15b
AD		 7505
7506err_out:
7507 i40e_vsi_clear_rings(vsi);
7508 return -ENOMEM;
41c445ff
JB		 7509}
7510
7511/**
7512 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7513 * @pf: board private structure
7514 * @vectors: the number of MSI-X vectors to request
7515 *
7516 * Returns the number of vectors reserved, or error
7517 **/
7518static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7519{
7b37f376
AG		 7520 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7521 I40E_MIN_MSIX, vectors);
7522 if (vectors < 0) {
41c445ff 7523 dev_info(&pf->pdev->dev,
7b37f376 7524 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7525 vectors = 0;
7526 }
7527
7528 return vectors;
7529}
7530
7531/**
7532 * i40e_init_msix - Setup the MSIX capability
7533 * @pf: board private structure
7534 *
7535 * Work with the OS to set up the MSIX vectors needed.
7536 *
3b444399 7537 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7538 **/
7539static int i40e_init_msix(struct i40e_pf *pf)
7540{
41c445ff 7541 struct i40e_hw *hw = &pf->hw;
1e200e4a 7542 int vectors_left;
41c445ff 7543 int v_budget, i;
3b444399 7544 int v_actual;
41c445ff
JB		 7545
7546 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7547 return -ENODEV;
7548
7549 /* The number of vectors we'll request will be comprised of:
7550 * - Add 1 for "other" cause for Admin Queue events, etc.
7551 * - The number of LAN queue pairs
f8ff1464
ASJ		 7552 * - Queues being used for RSS.
7553 * We don't need as many as max_rss_size vectors.
7554 * use rss_size instead in the calculation since that
7555 * is governed by number of cpus in the system.
7556 * - assumes symmetric Tx/Rx pairing
41c445ff 7557 * - The number of VMDq pairs
38e00438
VD		 7558#ifdef I40E_FCOE
7559 * - The number of FCOE qps.
7560#endif
41c445ff
JB		 7561 * Once we count this up, try the request.
7562 *
7563 * If we can't get what we want, we'll simplify to nearly nothing
7564 * and try again. If that still fails, we punt.
7565 */
1e200e4a
SN		 7566 vectors_left = hw->func_caps.num_msix_vectors;
7567 v_budget = 0;
7568
7569 /* reserve one vector for miscellaneous handler */
7570 if (vectors_left) {
7571 v_budget++;
7572 vectors_left--;
7573 }
7574
7575 /* reserve vectors for the main PF traffic queues */
7576 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7577 vectors_left -= pf->num_lan_msix;
7578 v_budget += pf->num_lan_msix;
7579
7580 /* reserve one vector for sideband flow director */
7581 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7582 if (vectors_left) {
7583 v_budget++;
7584 vectors_left--;
7585 } else {
7586 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7587 }
7588 }
83840e4b 7589
38e00438 7590#ifdef I40E_FCOE
1e200e4a 7591 /* can we reserve enough for FCoE? */
38e00438 7592 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7593 if (!vectors_left)
7594 pf->num_fcoe_msix = 0;
7595 else if (vectors_left >= pf->num_fcoe_qps)
7596 pf->num_fcoe_msix = pf->num_fcoe_qps;
7597 else
7598 pf->num_fcoe_msix = 1;
38e00438 7599 v_budget += pf->num_fcoe_msix;
1e200e4a 7600 vectors_left -= pf->num_fcoe_msix;
38e00438 7601 }
1e200e4a 7602
38e00438 7603#endif
1e200e4a
SN		 7604 /* any vectors left over go for VMDq support */
7605 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7606 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7607 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7608
7609 /* if we're short on vectors for what's desired, we limit
7610 * the queues per vmdq. If this is still more than are
7611 * available, the user will need to change the number of
7612 * queues/vectors used by the PF later with the ethtool
7613 * channels command
7614 */
7615 if (vmdq_vecs < vmdq_vecs_wanted)
7616 pf->num_vmdq_qps = 1;
7617 pf->num_vmdq_msix = pf->num_vmdq_qps;
7618
7619 v_budget += vmdq_vecs;
7620 vectors_left -= vmdq_vecs;
7621 }
41c445ff
JB		 7622
7623 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7624 GFP_KERNEL);
7625 if (!pf->msix_entries)
7626 return -ENOMEM;
7627
7628 for (i = 0; i < v_budget; i++)
7629 pf->msix_entries[i].entry = i;
3b444399 7630 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7631
3b444399 7632 if (v_actual != v_budget) {
a34977ba
ASJ		 7633 /* If we have limited resources, we will start with no vectors
7634 * for the special features and then allocate vectors to some
7635 * of these features based on the policy and at the end disable
7636 * the features that did not get any vectors.
7637 */
38e00438
VD		 7638#ifdef I40E_FCOE
7639 pf->num_fcoe_qps = 0;
7640 pf->num_fcoe_msix = 0;
7641#endif
a34977ba
ASJ		 7642 pf->num_vmdq_msix = 0;
7643 }
7644
3b444399 7645 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7646 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7647 kfree(pf->msix_entries);
7648 pf->msix_entries = NULL;
7649 return -ENODEV;
7650
3b444399 7651 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7652 /* Adjust for minimal MSIX use */
41c445ff
JB		 7653 pf->num_vmdq_vsis = 0;
7654 pf->num_vmdq_qps = 0;
41c445ff
JB		 7655 pf->num_lan_qps = 1;
7656 pf->num_lan_msix = 1;
7657
3b444399
SN		 7658 } else if (v_actual != v_budget) {
7659 int vec;
7660
a34977ba 7661 /* reserve the misc vector */
3b444399 7662 vec = v_actual - 1;
a34977ba 7663
41c445ff
JB		 7664 /* Scale vector usage down */
7665 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7666 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7667 pf->num_vmdq_qps = 1;
7668 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7669
7670 /* partition out the remaining vectors */
7671 switch (vec) {
7672 case 2:
41c445ff
JB		 7673 pf->num_lan_msix = 1;
7674 break;
7675 case 3:
38e00438
VD		 7676#ifdef I40E_FCOE
7677 /* give one vector to FCoE */
7678 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7679 pf->num_lan_msix = 1;
7680 pf->num_fcoe_msix = 1;
7681 }
7682#else
41c445ff 7683 pf->num_lan_msix = 2;
38e00438 7684#endif
41c445ff
JB		 7685 break;
7686 default:
38e00438
VD		 7687#ifdef I40E_FCOE
7688 /* give one vector to FCoE */
7689 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7690 pf->num_fcoe_msix = 1;
7691 vec--;
7692 }
7693#endif
1e200e4a
SN		 7694 /* give the rest to the PF */
7695 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7696 break;
7697 }
7698 }
7699
a34977ba
ASJ		 7700 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7701 (pf->num_vmdq_msix == 0)) {
7702 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7703 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7704 }
38e00438
VD		 7705#ifdef I40E_FCOE
7706
7707 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7708 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7709 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7710 }
7711#endif
3b444399 7712 return v_actual;
41c445ff
JB		 7713}
7714
493fb300 7715/**
90e04070 7716 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7717 * @vsi: the VSI being configured
7718 * @v_idx: index of the vector in the vsi struct
7719 *
7720 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7721 **/
90e04070 7722static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7723{
7724 struct i40e_q_vector *q_vector;
7725
7726 /* allocate q_vector */
7727 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7728 if (!q_vector)
7729 return -ENOMEM;
7730
7731 q_vector->vsi = vsi;
7732 q_vector->v_idx = v_idx;
7733 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7734 if (vsi->netdev)
7735 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7736 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7737
cd0b6fa6
AD		 7738 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7739 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7740
493fb300
AD		 7741 /* tie q_vector and vsi together */
7742 vsi->q_vectors[v_idx] = q_vector;
7743
7744 return 0;
7745}
7746
41c445ff 7747/**
90e04070 7748 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7749 * @vsi: the VSI being configured
7750 *
7751 * We allocate one q_vector per queue interrupt. If allocation fails we
7752 * return -ENOMEM.
7753 **/
90e04070 7754static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7755{
7756 struct i40e_pf *pf = vsi->back;
7757 int v_idx, num_q_vectors;
493fb300 7758 int err;
41c445ff
JB		 7759
7760 /* if not MSIX, give the one vector only to the LAN VSI */
7761 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7762 num_q_vectors = vsi->num_q_vectors;
7763 else if (vsi == pf->vsi[pf->lan_vsi])
7764 num_q_vectors = 1;
7765 else
7766 return -EINVAL;
7767
41c445ff 7768 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7769 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7770 if (err)
7771 goto err_out;
41c445ff
JB		 7772 }
7773
7774 return 0;
493fb300
AD		 7775
7776err_out:
7777 while (v_idx--)
7778 i40e_free_q_vector(vsi, v_idx);
7779
7780 return err;
41c445ff
JB		 7781}
7782
7783/**
7784 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7785 * @pf: board private structure to initialize
7786 **/
c1147280 7787static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7788{
3b444399
SN		 7789 int vectors = 0;
7790 ssize_t size;
41c445ff
JB		 7791
7792 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7793 vectors = i40e_init_msix(pf);
7794 if (vectors < 0) {
60ea5f83 7795 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7796#ifdef I40E_FCOE
7797 I40E_FLAG_FCOE_ENABLED |
7798#endif
60ea5f83 7799 I40E_FLAG_RSS_ENABLED |
4d9b6043 7800 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7801 I40E_FLAG_SRIOV_ENABLED |
7802 I40E_FLAG_FD_SB_ENABLED |
7803 I40E_FLAG_FD_ATR_ENABLED |
7804 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7805
7806 /* rework the queue expectations without MSIX */
7807 i40e_determine_queue_usage(pf);
7808 }
7809 }
7810
7811 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7812 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7813 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7814 vectors = pci_enable_msi(pf->pdev);
7815 if (vectors < 0) {
7816 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7817 vectors);
41c445ff
JB		 7818 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7819 }
3b444399 7820 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7821 }
7822
958a3e3b 7823 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7824 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7825
3b444399
SN		 7826 /* set up vector assignment tracking */
7827 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7828 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7829 if (!pf->irq_pile) {
7830 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7831 return -ENOMEM;
7832 }
3b444399
SN		 7833 pf->irq_pile->num_entries = vectors;
7834 pf->irq_pile->search_hint = 0;
7835
c1147280 7836 /* track first vector for misc interrupts, ignore return */
3b444399 7837 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7838
7839 return 0;
41c445ff
JB		 7840}
7841
7842/**
7843 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7844 * @pf: board private structure
7845 *
7846 * This sets up the handler for MSIX 0, which is used to manage the
7847 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7848 * when in MSI or Legacy interrupt mode.
7849 **/
7850static int i40e_setup_misc_vector(struct i40e_pf *pf)
7851{
7852 struct i40e_hw *hw = &pf->hw;
7853 int err = 0;
7854
7855 /* Only request the irq if this is the first time through, and
7856 * not when we're rebuilding after a Reset
7857 */
7858 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7859 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7860 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7861 if (err) {
7862 dev_info(&pf->pdev->dev,
77fa28be 7863 "request_irq for %s failed: %d\n",
b294ac70 7864 pf->int_name, err);
41c445ff
JB		 7865 return -EFAULT;
7866 }
7867 }
7868
ab437b5a 7869 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7870
7871 /* associate no queues to the misc vector */
7872 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7873 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7874
7875 i40e_flush(hw);
7876
7877 i40e_irq_dynamic_enable_icr0(pf);
7878
7879 return err;
7880}
7881
7882/**
e25d00b8
ASJ		 7883 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7884 * @vsi: vsi structure
7885 * @seed: RSS hash seed
7886 **/
e69ff813
HZ		 7887static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7888 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7889{
7890 struct i40e_aqc_get_set_rss_key_data rss_key;
7891 struct i40e_pf *pf = vsi->back;
7892 struct i40e_hw *hw = &pf->hw;
7893 bool pf_lut = false;
7894 u8 *rss_lut;
7895 int ret, i;
7896
7897 memset(&rss_key, 0, sizeof(rss_key));
7898 memcpy(&rss_key, seed, sizeof(rss_key));
7899
7900 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7901 if (!rss_lut)
7902 return -ENOMEM;
7903
7904 /* Populate the LUT with max no. of queues in round robin fashion */
7905 for (i = 0; i < vsi->rss_table_size; i++)
7906 rss_lut[i] = i % vsi->rss_size;
7907
7908 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7909 if (ret) {
7910 dev_info(&pf->pdev->dev,
7911 "Cannot set RSS key, err %s aq_err %s\n",
7912 i40e_stat_str(&pf->hw, ret),
7913 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7914 goto config_rss_aq_out;
e25d00b8
ASJ		 7915 }
7916
7917 if (vsi->type == I40E_VSI_MAIN)
7918 pf_lut = true;
7919
7920 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7921 vsi->rss_table_size);
7922 if (ret)
7923 dev_info(&pf->pdev->dev,
7924 "Cannot set RSS lut, err %s aq_err %s\n",
7925 i40e_stat_str(&pf->hw, ret),
7926 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7927
126b63d9
AS		 7928config_rss_aq_out:
7929 kfree(rss_lut);
e25d00b8
ASJ		 7930 return ret;
7931}
7932
7933/**
7934 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7935 * @vsi: VSI structure
7936 **/
7937static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7938{
7939 u8 seed[I40E_HKEY_ARRAY_SIZE];
7940 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7941 u8 *lut;
7942 int ret;
7943
7944 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7945 return 0;
7946
7947 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7948 if (!lut)
7949 return -ENOMEM;
e25d00b8 7950
e69ff813 7951 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7952 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7953 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7954 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7955 kfree(lut);
e25d00b8 7956
e69ff813 7957 return ret;
e25d00b8
ASJ		 7958}
7959
95a73780
ASJ		 7960/**
7961 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
7962 * @vsi: Pointer to vsi structure
7963 * @seed: Buffter to store the hash keys
7964 * @lut: Buffer to store the lookup table entries
7965 * @lut_size: Size of buffer to store the lookup table entries
7966 *
7967 * Return 0 on success, negative on failure
7968 */
7969static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7970 u8 *lut, u16 lut_size)
7971{
7972 struct i40e_pf *pf = vsi->back;
7973 struct i40e_hw *hw = &pf->hw;
7974 int ret = 0;
7975
7976 if (seed) {
7977 ret = i40e_aq_get_rss_key(hw, vsi->id,
7978 (struct i40e_aqc_get_set_rss_key_data *)seed);
7979 if (ret) {
7980 dev_info(&pf->pdev->dev,
7981 "Cannot get RSS key, err %s aq_err %s\n",
7982 i40e_stat_str(&pf->hw, ret),
7983 i40e_aq_str(&pf->hw,
7984 pf->hw.aq.asq_last_status));
7985 return ret;
7986 }
7987 }
7988
7989 if (lut) {
7990 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
7991
7992 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
7993 if (ret) {
7994 dev_info(&pf->pdev->dev,
7995 "Cannot get RSS lut, err %s aq_err %s\n",
7996 i40e_stat_str(&pf->hw, ret),
7997 i40e_aq_str(&pf->hw,
7998 pf->hw.aq.asq_last_status));
7999 return ret;
8000 }
8001 }
8002
8003 return ret;
8004}
8005
e25d00b8 8006/**
043dd650 8007 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 8008 * @vsi: Pointer to vsi structure
e25d00b8 8009 * @seed: RSS hash seed
e69ff813
HZ		 8010 * @lut: Lookup table
8011 * @lut_size: Lookup table size
8012 *
8013 * Returns 0 on success, negative on failure
41c445ff 8014 **/
e69ff813
HZ		 8015static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
8016 const u8 *lut, u16 lut_size)
41c445ff 8017{
e69ff813 8018 struct i40e_pf *pf = vsi->back;
4617e8c0 8019 struct i40e_hw *hw = &pf->hw;
e69ff813 8020 u8 i;
41c445ff 8021
e25d00b8 8022 /* Fill out hash function seed */
e69ff813
HZ		 8023 if (seed) {
8024 u32 *seed_dw = (u32 *)seed;
8025
8026 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8027 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
8028 }
8029
8030 if (lut) {
8031 u32 *lut_dw = (u32 *)lut;
8032
8033 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8034 return -EINVAL;
8035
8036 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8037 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
e25d00b8
ASJ		 8038 }
8039 i40e_flush(hw);
8040
8041 return 0;
8042}
8043
043dd650
HZ		 8044/**
8045 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
8046 * @vsi: Pointer to VSI structure
8047 * @seed: Buffer to store the keys
8048 * @lut: Buffer to store the lookup table entries
8049 * @lut_size: Size of buffer to store the lookup table entries
8050 *
8051 * Returns 0 on success, negative on failure
8052 */
8053static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
8054 u8 *lut, u16 lut_size)
8055{
8056 struct i40e_pf *pf = vsi->back;
8057 struct i40e_hw *hw = &pf->hw;
8058 u16 i;
8059
8060 if (seed) {
8061 u32 *seed_dw = (u32 *)seed;
8062
8063 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8064 seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
8065 }
8066 if (lut) {
8067 u32 *lut_dw = (u32 *)lut;
8068
8069 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8070 return -EINVAL;
8071 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8072 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
8073 }
8074
8075 return 0;
8076}
8077
8078/**
8079 * i40e_config_rss - Configure RSS keys and lut
8080 * @vsi: Pointer to VSI structure
8081 * @seed: RSS hash seed
8082 * @lut: Lookup table
8083 * @lut_size: Lookup table size
8084 *
8085 * Returns 0 on success, negative on failure
8086 */
8087int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8088{
8089 struct i40e_pf *pf = vsi->back;
8090
8091 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8092 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8093 else
8094 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8095}
8096
8097/**
8098 * i40e_get_rss - Get RSS keys and lut
8099 * @vsi: Pointer to VSI structure
8100 * @seed: Buffer to store the keys
8101 * @lut: Buffer to store the lookup table entries
8102 * lut_size: Size of buffer to store the lookup table entries
8103 *
8104 * Returns 0 on success, negative on failure
8105 */
8106int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8107{
95a73780
ASJ		 8108 struct i40e_pf *pf = vsi->back;
8109
8110 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8111 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
8112 else
8113 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
043dd650
HZ		 8114}
8115
e69ff813
HZ		 8116/**
8117 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8118 * @pf: Pointer to board private structure
8119 * @lut: Lookup table
8120 * @rss_table_size: Lookup table size
8121 * @rss_size: Range of queue number for hashing
8122 */
8123static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8124 u16 rss_table_size, u16 rss_size)
8125{
8126 u16 i;
8127
8128 for (i = 0; i < rss_table_size; i++)
8129 lut[i] = i % rss_size;
8130}
8131
e25d00b8 8132/**
043dd650 8133 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8134 * @pf: board private structure
8135 **/
043dd650 8136static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8137{
8138 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8139 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8140 u8 *lut;
e25d00b8
ASJ		 8141 struct i40e_hw *hw = &pf->hw;
8142 u32 reg_val;
8143 u64 hena;
e69ff813 8144 int ret;
e25d00b8 8145
41c445ff
JB		 8146 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
8147 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
8148 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8149 hena |= i40e_pf_get_default_rss_hena(pf);
8150
41c445ff
JB		 8151 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
8152 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
8153
e25d00b8 8154 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 8155 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8156 reg_val = (pf->rss_table_size == 512) ?
8157 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8158 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 8159 wr32(hw, I40E_PFQF_CTL_0, reg_val);
8160
28c5869f
HZ		 8161 /* Determine the RSS size of the VSI */
8162 if (!vsi->rss_size)
acd65448
HZ		 8163 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8164 vsi->num_queue_pairs);
28c5869f 8165
e69ff813
HZ		 8166 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8167 if (!lut)
8168 return -ENOMEM;
8169
28c5869f
HZ		 8170 /* Use user configured lut if there is one, otherwise use default */
8171 if (vsi->rss_lut_user)
8172 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8173 else
8174 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8175
28c5869f
HZ		 8176 /* Use user configured hash key if there is one, otherwise
8177 * use default.
8178 */
8179 if (vsi->rss_hkey_user)
8180 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8181 else
8182 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8183 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8184 kfree(lut);
8185
8186 return ret;
41c445ff
JB		 8187}
8188
f8ff1464
ASJ		 8189/**
8190 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8191 * @pf: board private structure
8192 * @queue_count: the requested queue count for rss.
8193 *
8194 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8195 * count which may be different from the requested queue count.
8196 **/
8197int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8198{
9a3bd2f1
ASJ		 8199 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8200 int new_rss_size;
8201
f8ff1464
ASJ		 8202 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8203 return 0;
8204
9a3bd2f1 8205 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8206
9a3bd2f1
ASJ		 8207 if (queue_count != vsi->num_queue_pairs) {
8208 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8209 i40e_prep_for_reset(pf);
8210
acd65448 8211 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8212
8213 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8214
8215 /* Discard the user configured hash keys and lut, if less
8216 * queues are enabled.
8217 */
8218 if (queue_count < vsi->rss_size) {
8219 i40e_clear_rss_config_user(vsi);
8220 dev_dbg(&pf->pdev->dev,
8221 "discard user configured hash keys and lut\n");
8222 }
8223
8224 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8225 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8226 vsi->num_queue_pairs);
28c5869f 8227
043dd650 8228 i40e_pf_config_rss(pf);
f8ff1464 8229 }
e36b0b11
HZ		 8230 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8231 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8232 return pf->alloc_rss_size;
f8ff1464
ASJ		 8233}
8234
f4492db1
GR		 8235/**
8236 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8237 * @pf: board private structure
8238 **/
8239i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8240{
8241 i40e_status status;
8242 bool min_valid, max_valid;
8243 u32 max_bw, min_bw;
8244
8245 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8246 &min_valid, &max_valid);
8247
8248 if (!status) {
8249 if (min_valid)
8250 pf->npar_min_bw = min_bw;
8251 if (max_valid)
8252 pf->npar_max_bw = max_bw;
8253 }
8254
8255 return status;
8256}
8257
8258/**
8259 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8260 * @pf: board private structure
8261 **/
8262i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8263{
8264 struct i40e_aqc_configure_partition_bw_data bw_data;
8265 i40e_status status;
8266
b40c82e6 8267 /* Set the valid bit for this PF */
41a1d04b 8268 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8269 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8270 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8271
8272 /* Set the new bandwidths */
8273 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8274
8275 return status;
8276}
8277
8278/**
8279 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8280 * @pf: board private structure
8281 **/
8282i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8283{
8284 /* Commit temporary BW setting to permanent NVM image */
8285 enum i40e_admin_queue_err last_aq_status;
8286 i40e_status ret;
8287 u16 nvm_word;
8288
8289 if (pf->hw.partition_id != 1) {
8290 dev_info(&pf->pdev->dev,
8291 "Commit BW only works on partition 1! This is partition %d",
8292 pf->hw.partition_id);
8293 ret = I40E_NOT_SUPPORTED;
8294 goto bw_commit_out;
8295 }
8296
8297 /* Acquire NVM for read access */
8298 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8299 last_aq_status = pf->hw.aq.asq_last_status;
8300 if (ret) {
8301 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8302 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8303 i40e_stat_str(&pf->hw, ret),
8304 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8305 goto bw_commit_out;
8306 }
8307
8308 /* Read word 0x10 of NVM - SW compatibility word 1 */
8309 ret = i40e_aq_read_nvm(&pf->hw,
8310 I40E_SR_NVM_CONTROL_WORD,
8311 0x10, sizeof(nvm_word), &nvm_word,
8312 false, NULL);
8313 /* Save off last admin queue command status before releasing
8314 * the NVM
8315 */
8316 last_aq_status = pf->hw.aq.asq_last_status;
8317 i40e_release_nvm(&pf->hw);
8318 if (ret) {
f1c7e72e
SN		 8319 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8320 i40e_stat_str(&pf->hw, ret),
8321 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8322 goto bw_commit_out;
8323 }
8324
8325 /* Wait a bit for NVM release to complete */
8326 msleep(50);
8327
8328 /* Acquire NVM for write access */
8329 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8330 last_aq_status = pf->hw.aq.asq_last_status;
8331 if (ret) {
8332 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8333 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8334 i40e_stat_str(&pf->hw, ret),
8335 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8336 goto bw_commit_out;
8337 }
8338 /* Write it back out unchanged to initiate update NVM,
8339 * which will force a write of the shadow (alt) RAM to
8340 * the NVM - thus storing the bandwidth values permanently.
8341 */
8342 ret = i40e_aq_update_nvm(&pf->hw,
8343 I40E_SR_NVM_CONTROL_WORD,
8344 0x10, sizeof(nvm_word),
8345 &nvm_word, true, NULL);
8346 /* Save off last admin queue command status before releasing
8347 * the NVM
8348 */
8349 last_aq_status = pf->hw.aq.asq_last_status;
8350 i40e_release_nvm(&pf->hw);
8351 if (ret)
8352 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8353 "BW settings NOT SAVED, err %s aq_err %s\n",
8354 i40e_stat_str(&pf->hw, ret),
8355 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8356bw_commit_out:
8357
8358 return ret;
8359}
8360
41c445ff
JB		 8361/**
8362 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8363 * @pf: board private structure to initialize
8364 *
8365 * i40e_sw_init initializes the Adapter private data structure.
8366 * Fields are initialized based on PCI device information and
8367 * OS network device settings (MTU size).
8368 **/
8369static int i40e_sw_init(struct i40e_pf *pf)
8370{
8371 int err = 0;
8372 int size;
8373
8374 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8375 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 8376 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 8377 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8378 if (I40E_DEBUG_USER & debug)
8379 pf->hw.debug_mask = debug;
8380 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8381 I40E_DEFAULT_MSG_ENABLE);
8382 }
8383
8384 /* Set default capability flags */
8385 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8386 I40E_FLAG_MSI_ENABLED |
9ac77266 8387 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 8388 I40E_FLAG_MSIX_ENABLED;
8389
8390 if (iommu_present(&pci_bus_type))
8391 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8392 else
8393 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8394
ca99eb99
MW		 8395 /* Set default ITR */
8396 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8397 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8398
7134f9ce
JB		 8399 /* Depending on PF configurations, it is possible that the RSS
8400 * maximum might end up larger than the available queues
8401 */
41a1d04b 8402 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8403 pf->alloc_rss_size = 1;
5db4cb59 8404 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8405 pf->rss_size_max = min_t(int, pf->rss_size_max,
8406 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8407 if (pf->hw.func_caps.rss) {
8408 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8409 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8410 num_online_cpus());
41c445ff
JB		 8411 }
8412
2050bc65 8413 /* MFP mode enabled */
c78b953e 8414 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8415 pf->flags |= I40E_FLAG_MFP_ENABLED;
8416 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8417 if (i40e_get_npar_bw_setting(pf))
8418 dev_warn(&pf->pdev->dev,
8419 "Could not get NPAR bw settings\n");
8420 else
8421 dev_info(&pf->pdev->dev,
8422 "Min BW = %8.8x, Max BW = %8.8x\n",
8423 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8424 }
8425
cbf61325
ASJ		 8426 /* FW/NVM is not yet fixed in this regard */
8427 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8428 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8429 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8430 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8431 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8432 pf->hw.num_partitions > 1)
cbf61325 8433 dev_info(&pf->pdev->dev,
0b67584f 8434 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8435 else
8436 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8437 pf->fdir_pf_filter_count =
8438 pf->hw.func_caps.fd_filters_guaranteed;
8439 pf->hw.fdir_shared_filter_count =
8440 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8441 }
8442
8eed76fa
ASJ		 8443 if (((pf->hw.mac.type == I40E_MAC_X710) ||
8444 (pf->hw.mac.type == I40E_MAC_XL710)) &&
8445 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
8446 (pf->hw.aq.fw_maj_ver < 4)))
8447 pf->flags |= I40E_FLAG_RESTART_AUTONEG;
8448
41c445ff 8449 if (pf->hw.func_caps.vmdq) {
41c445ff 8450 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8451 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8452 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8453 }
8454
38e00438 8455#ifdef I40E_FCOE
21364bcf 8456 i40e_init_pf_fcoe(pf);
38e00438
VD		 8457
8458#endif /* I40E_FCOE */
41c445ff 8459#ifdef CONFIG_PCI_IOV
ba252f13 8460 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8461 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8462 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8463 pf->num_req_vfs = min_t(int,
8464 pf->hw.func_caps.num_vfs,
8465 I40E_MAX_VF_COUNT);
8466 }
8467#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8468 if (pf->hw.mac.type == I40E_MAC_X722) {
8469 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8470 I40E_FLAG_128_QP_RSS_CAPABLE |
8471 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8472 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8473 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024 8474 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
f8db54cc 8475 I40E_FLAG_100M_SGMII_CAPABLE |
6a899024 8476 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
d502ce01 8477 }
41c445ff
JB		 8478 pf->eeprom_version = 0xDEAD;
8479 pf->lan_veb = I40E_NO_VEB;
8480 pf->lan_vsi = I40E_NO_VSI;
8481
d1a8d275
ASJ		 8482 /* By default FW has this off for performance reasons */
8483 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8484
41c445ff
JB		 8485 /* set up queue assignment tracking */
8486 size = sizeof(struct i40e_lump_tracking)
8487 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8488 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8489 if (!pf->qp_pile) {
8490 err = -ENOMEM;
8491 goto sw_init_done;
8492 }
8493 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8494 pf->qp_pile->search_hint = 0;
8495
327fe04b
ASJ		 8496 pf->tx_timeout_recovery_level = 1;
8497
41c445ff
JB		 8498 mutex_init(&pf->switch_mutex);
8499
c668a12c
GR		 8500 /* If NPAR is enabled nudge the Tx scheduler */
8501 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8502 i40e_set_npar_bw_setting(pf);
8503
41c445ff
JB		 8504sw_init_done:
8505 return err;
8506}
8507
7c3c288b
ASJ		 8508/**
8509 * i40e_set_ntuple - set the ntuple feature flag and take action
8510 * @pf: board private structure to initialize
8511 * @features: the feature set that the stack is suggesting
8512 *
8513 * returns a bool to indicate if reset needs to happen
8514 **/
8515bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8516{
8517 bool need_reset = false;
8518
8519 /* Check if Flow Director n-tuple support was enabled or disabled. If
8520 * the state changed, we need to reset.
8521 */
8522 if (features & NETIF_F_NTUPLE) {
8523 /* Enable filters and mark for reset */
8524 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8525 need_reset = true;
8526 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8527 } else {
8528 /* turn off filters, mark for reset and clear SW filter list */
8529 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8530 need_reset = true;
8531 i40e_fdir_filter_exit(pf);
8532 }
8533 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8534 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8535 /* reset fd counters */
8536 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8537 pf->fdir_pf_active_filters = 0;
8538 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8539 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8540 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8541 /* if ATR was auto disabled it can be re-enabled. */
8542 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8543 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8544 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8545 }
8546 return need_reset;
8547}
8548
41c445ff
JB		 8549/**
8550 * i40e_set_features - set the netdev feature flags
8551 * @netdev: ptr to the netdev being adjusted
8552 * @features: the feature set that the stack is suggesting
8553 **/
8554static int i40e_set_features(struct net_device *netdev,
8555 netdev_features_t features)
8556{
8557 struct i40e_netdev_priv *np = netdev_priv(netdev);
8558 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8559 struct i40e_pf *pf = vsi->back;
8560 bool need_reset;
41c445ff
JB		 8561
8562 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8563 i40e_vlan_stripping_enable(vsi);
8564 else
8565 i40e_vlan_stripping_disable(vsi);
8566
7c3c288b
ASJ		 8567 need_reset = i40e_set_ntuple(pf, features);
8568
8569 if (need_reset)
41a1d04b 8570 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8571
41c445ff
JB		 8572 return 0;
8573}
8574
6a899024 8575#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9 8576/**
6a899024 8577 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8578 * @pf: board private structure
8579 * @port: The UDP port to look up
8580 *
8581 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8582 **/
6a899024 8583static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8584{
8585 u8 i;
8586
8587 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8588 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8589 return i;
8590 }
8591
8592 return i;
8593}
8594
6a899024 8595#endif
5cae7615
ED		 8596
8597#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8598/**
8599 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8600 * @netdev: This physical port's netdev
8601 * @sa_family: Socket Family that VXLAN is notifying us about
8602 * @port: New UDP port number that VXLAN started listening to
8603 **/
8604static void i40e_add_vxlan_port(struct net_device *netdev,
8605 sa_family_t sa_family, __be16 port)
8606{
8607 struct i40e_netdev_priv *np = netdev_priv(netdev);
8608 struct i40e_vsi *vsi = np->vsi;
8609 struct i40e_pf *pf = vsi->back;
8610 u8 next_idx;
8611 u8 idx;
8612
8613 if (sa_family == AF_INET6)
8614 return;
8615
6a899024 8616 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8617
8618 /* Check if port already exists */
8619 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8620 netdev_info(netdev, "vxlan port %d already offloaded\n",
8621 ntohs(port));
a1c9a9d9
JK		 8622 return;
8623 }
8624
8625 /* Now check if there is space to add the new port */
6a899024 8626 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8627
8628 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8629 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8630 ntohs(port));
8631 return;
8632 }
8633
8634 /* New port: add it and mark its index in the bitmap */
6a899024
SA		 8635 pf->udp_ports[next_idx].index = port;
8636 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8637 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8638 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 8639}
8640
8641/**
8642 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8643 * @netdev: This physical port's netdev
8644 * @sa_family: Socket Family that VXLAN is notifying us about
8645 * @port: UDP port number that VXLAN stopped listening to
8646 **/
8647static void i40e_del_vxlan_port(struct net_device *netdev,
8648 sa_family_t sa_family, __be16 port)
8649{
8650 struct i40e_netdev_priv *np = netdev_priv(netdev);
8651 struct i40e_vsi *vsi = np->vsi;
8652 struct i40e_pf *pf = vsi->back;
8653 u8 idx;
8654
8655 if (sa_family == AF_INET6)
8656 return;
8657
6a899024 8658 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8659
8660 /* Check if port already exists */
8661 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8662 /* if port exists, set it to 0 (mark for deletion)
8663 * and make it pending
8664 */
6a899024
SA		 8665 pf->udp_ports[idx].index = 0;
8666 pf->pending_udp_bitmap |= BIT_ULL(idx);
8667 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9 8668 } else {
c22c06c8 8669 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8670 ntohs(port));
8671 }
6a899024 8672}
5cae7615 8673#endif
6a899024 8674
5cae7615 8675#if IS_ENABLED(CONFIG_GENEVE)
6a899024
SA		 8676/**
8677 * i40e_add_geneve_port - Get notifications about GENEVE ports that come up
8678 * @netdev: This physical port's netdev
8679 * @sa_family: Socket Family that GENEVE is notifying us about
8680 * @port: New UDP port number that GENEVE started listening to
8681 **/
8682static void i40e_add_geneve_port(struct net_device *netdev,
8683 sa_family_t sa_family, __be16 port)
8684{
6a899024
SA		 8685 struct i40e_netdev_priv *np = netdev_priv(netdev);
8686 struct i40e_vsi *vsi = np->vsi;
8687 struct i40e_pf *pf = vsi->back;
8688 u8 next_idx;
8689 u8 idx;
8690
8691 if (sa_family == AF_INET6)
8692 return;
8693
8694 idx = i40e_get_udp_port_idx(pf, port);
8695
8696 /* Check if port already exists */
8697 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8698 netdev_info(netdev, "udp port %d already offloaded\n",
8699 ntohs(port));
8700 return;
8701 }
8702
8703 /* Now check if there is space to add the new port */
8704 next_idx = i40e_get_udp_port_idx(pf, 0);
8705
8706 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8707 netdev_info(netdev, "maximum number of UDP ports reached, not adding port %d\n",
8708 ntohs(port));
8709 return;
8710 }
8711
8712 /* New port: add it and mark its index in the bitmap */
8713 pf->udp_ports[next_idx].index = port;
8714 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8715 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8716 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8717
8718 dev_info(&pf->pdev->dev, "adding geneve port %d\n", ntohs(port));
a1c9a9d9
JK		 8719}
8720
6a899024
SA		 8721/**
8722 * i40e_del_geneve_port - Get notifications about GENEVE ports that go away
8723 * @netdev: This physical port's netdev
8724 * @sa_family: Socket Family that GENEVE is notifying us about
8725 * @port: UDP port number that GENEVE stopped listening to
8726 **/
8727static void i40e_del_geneve_port(struct net_device *netdev,
8728 sa_family_t sa_family, __be16 port)
8729{
6a899024
SA		 8730 struct i40e_netdev_priv *np = netdev_priv(netdev);
8731 struct i40e_vsi *vsi = np->vsi;
8732 struct i40e_pf *pf = vsi->back;
8733 u8 idx;
8734
8735 if (sa_family == AF_INET6)
8736 return;
8737
8738 idx = i40e_get_udp_port_idx(pf, port);
8739
8740 /* Check if port already exists */
8741 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8742 /* if port exists, set it to 0 (mark for deletion)
8743 * and make it pending
8744 */
8745 pf->udp_ports[idx].index = 0;
8746 pf->pending_udp_bitmap |= BIT_ULL(idx);
8747 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8748
8749 dev_info(&pf->pdev->dev, "deleting geneve port %d\n",
8750 ntohs(port));
8751 } else {
8752 netdev_warn(netdev, "geneve port %d was not found, not deleting\n",
8753 ntohs(port));
8754 }
6a899024 8755}
5cae7615 8756#endif
6a899024 8757
1f224ad2 8758static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8759 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8760{
8761 struct i40e_netdev_priv *np = netdev_priv(netdev);
8762 struct i40e_pf *pf = np->vsi->back;
8763 struct i40e_hw *hw = &pf->hw;
8764
8765 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8766 return -EOPNOTSUPP;
8767
8768 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8769 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8770
8771 return 0;
8772}
8773
2f90ade6
JB		 8774/**
8775 * i40e_ndo_fdb_add - add an entry to the hardware database
8776 * @ndm: the input from the stack
8777 * @tb: pointer to array of nladdr (unused)
8778 * @dev: the net device pointer
8779 * @addr: the MAC address entry being added
8780 * @flags: instructions from stack about fdb operation
8781 */
4ba0dea5
GR		 8782static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8783 struct net_device *dev,
f6f6424b 8784 const unsigned char *addr, u16 vid,
4ba0dea5 8785 u16 flags)
4ba0dea5
GR		 8786{
8787 struct i40e_netdev_priv *np = netdev_priv(dev);
8788 struct i40e_pf *pf = np->vsi->back;
8789 int err = 0;
8790
8791 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8792 return -EOPNOTSUPP;
8793
65891fea
OG		 8794 if (vid) {
8795 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8796 return -EINVAL;
8797 }
8798
4ba0dea5
GR		 8799 /* Hardware does not support aging addresses so if a
8800 * ndm_state is given only allow permanent addresses
8801 */
8802 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8803 netdev_info(dev, "FDB only supports static addresses\n");
8804 return -EINVAL;
8805 }
8806
8807 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8808 err = dev_uc_add_excl(dev, addr);
8809 else if (is_multicast_ether_addr(addr))
8810 err = dev_mc_add_excl(dev, addr);
8811 else
8812 err = -EINVAL;
8813
8814 /* Only return duplicate errors if NLM_F_EXCL is set */
8815 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8816 err = 0;
8817
8818 return err;
8819}
8820
51616018
NP		 8821/**
8822 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8823 * @dev: the netdev being configured
8824 * @nlh: RTNL message
8825 *
8826 * Inserts a new hardware bridge if not already created and
8827 * enables the bridging mode requested (VEB or VEPA). If the
8828 * hardware bridge has already been inserted and the request
8829 * is to change the mode then that requires a PF reset to
8830 * allow rebuild of the components with required hardware
8831 * bridge mode enabled.
8832 **/
8833static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8834 struct nlmsghdr *nlh,
8835 u16 flags)
51616018
NP		 8836{
8837 struct i40e_netdev_priv *np = netdev_priv(dev);
8838 struct i40e_vsi *vsi = np->vsi;
8839 struct i40e_pf *pf = vsi->back;
8840 struct i40e_veb *veb = NULL;
8841 struct nlattr *attr, *br_spec;
8842 int i, rem;
8843
8844 /* Only for PF VSI for now */
8845 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8846 return -EOPNOTSUPP;
8847
8848 /* Find the HW bridge for PF VSI */
8849 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8850 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8851 veb = pf->veb[i];
8852 }
8853
8854 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8855
8856 nla_for_each_nested(attr, br_spec, rem) {
8857 __u16 mode;
8858
8859 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8860 continue;
8861
8862 mode = nla_get_u16(attr);
8863 if ((mode != BRIDGE_MODE_VEPA) &&
8864 (mode != BRIDGE_MODE_VEB))
8865 return -EINVAL;
8866
8867 /* Insert a new HW bridge */
8868 if (!veb) {
8869 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8870 vsi->tc_config.enabled_tc);
8871 if (veb) {
8872 veb->bridge_mode = mode;
8873 i40e_config_bridge_mode(veb);
8874 } else {
8875 /* No Bridge HW offload available */
8876 return -ENOENT;
8877 }
8878 break;
8879 } else if (mode != veb->bridge_mode) {
8880 /* Existing HW bridge but different mode needs reset */
8881 veb->bridge_mode = mode;
fc60861e
ASJ		 8882 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8883 if (mode == BRIDGE_MODE_VEB)
8884 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8885 else
8886 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8887 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8888 break;
8889 }
8890 }
8891
8892 return 0;
8893}
8894
8895/**
8896 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8897 * @skb: skb buff
8898 * @pid: process id
8899 * @seq: RTNL message seq #
8900 * @dev: the netdev being configured
8901 * @filter_mask: unused
d4b2f9fe 8902 * @nlflags: netlink flags passed in
51616018
NP		 8903 *
8904 * Return the mode in which the hardware bridge is operating in
8905 * i.e VEB or VEPA.
8906 **/
51616018
NP		 8907static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8908 struct net_device *dev,
9f4ffc44
CW		 8909 u32 __always_unused filter_mask,
8910 int nlflags)
51616018
NP		 8911{
8912 struct i40e_netdev_priv *np = netdev_priv(dev);
8913 struct i40e_vsi *vsi = np->vsi;
8914 struct i40e_pf *pf = vsi->back;
8915 struct i40e_veb *veb = NULL;
8916 int i;
8917
8918 /* Only for PF VSI for now */
8919 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8920 return -EOPNOTSUPP;
8921
8922 /* Find the HW bridge for the PF VSI */
8923 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8924 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8925 veb = pf->veb[i];
8926 }
8927
8928 if (!veb)
8929 return 0;
8930
46c264da 8931 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8932 nlflags, 0, 0, filter_mask, NULL);
51616018 8933}
51616018 8934
6a899024
SA		 8935/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
8936 * inner mac plus all inner ethertypes.
8937 */
8938#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 8939/**
8940 * i40e_features_check - Validate encapsulated packet conforms to limits
8941 * @skb: skb buff
2bc11c63 8942 * @dev: This physical port's netdev
f44a75e2
JS		 8943 * @features: Offload features that the stack believes apply
8944 **/
8945static netdev_features_t i40e_features_check(struct sk_buff *skb,
8946 struct net_device *dev,
8947 netdev_features_t features)
8948{
8949 if (skb->encapsulation &&
6a899024 8950 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 8951 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 8952 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 8953
8954 return features;
8955}
8956
37a2973a 8957static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8958 .ndo_open = i40e_open,
8959 .ndo_stop = i40e_close,
8960 .ndo_start_xmit = i40e_lan_xmit_frame,
8961 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8962 .ndo_set_rx_mode = i40e_set_rx_mode,
8963 .ndo_validate_addr = eth_validate_addr,
8964 .ndo_set_mac_address = i40e_set_mac,
8965 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8966 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8967 .ndo_tx_timeout = i40e_tx_timeout,
8968 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8969 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8970#ifdef CONFIG_NET_POLL_CONTROLLER
8971 .ndo_poll_controller = i40e_netpoll,
8972#endif
e4c6734e 8973 .ndo_setup_tc = __i40e_setup_tc,
38e00438
VD		 8974#ifdef I40E_FCOE
8975 .ndo_fcoe_enable = i40e_fcoe_enable,
8976 .ndo_fcoe_disable = i40e_fcoe_disable,
8977#endif
41c445ff
JB		 8978 .ndo_set_features = i40e_set_features,
8979 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8980 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8981 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8982 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8983 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8984 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
6a899024 8985#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8986 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8987 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6a899024
SA		 8988#endif
8989#if IS_ENABLED(CONFIG_GENEVE)
8990 .ndo_add_geneve_port = i40e_add_geneve_port,
8991 .ndo_del_geneve_port = i40e_del_geneve_port,
a1c9a9d9 8992#endif
1f224ad2 8993 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8994 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8995 .ndo_features_check = i40e_features_check,
51616018
NP		 8996 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8997 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8998};
8999
9000/**
9001 * i40e_config_netdev - Setup the netdev flags
9002 * @vsi: the VSI being configured
9003 *
9004 * Returns 0 on success, negative value on failure
9005 **/
9006static int i40e_config_netdev(struct i40e_vsi *vsi)
9007{
1a10370a 9008 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 9009 struct i40e_pf *pf = vsi->back;
9010 struct i40e_hw *hw = &pf->hw;
9011 struct i40e_netdev_priv *np;
9012 struct net_device *netdev;
9013 u8 mac_addr[ETH_ALEN];
9014 int etherdev_size;
9015
9016 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 9017 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 9018 if (!netdev)
9019 return -ENOMEM;
9020
9021 vsi->netdev = netdev;
9022 np = netdev_priv(netdev);
9023 np->vsi = vsi;
9024
5afdaaa0
JB		 9025 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
9026 NETIF_F_GSO_UDP_TUNNEL |
9027 NETIF_F_GSO_GRE |
9028 NETIF_F_TSO |
9029 0;
41c445ff
JB		 9030
9031 netdev->features = NETIF_F_SG |
9032 NETIF_F_IP_CSUM |
53692b1d 9033 NETIF_F_SCTP_CRC |
41c445ff
JB		 9034 NETIF_F_HIGHDMA |
9035 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 9036 NETIF_F_GSO_GRE |
41c445ff
JB		 9037 NETIF_F_HW_VLAN_CTAG_TX |
9038 NETIF_F_HW_VLAN_CTAG_RX |
9039 NETIF_F_HW_VLAN_CTAG_FILTER |
9040 NETIF_F_IPV6_CSUM |
9041 NETIF_F_TSO |
059dab69 9042 NETIF_F_TSO_ECN |
41c445ff
JB		 9043 NETIF_F_TSO6 |
9044 NETIF_F_RXCSUM |
9045 NETIF_F_RXHASH |
9046 0;
9047
2e86a0b6
ASJ		 9048 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
9049 netdev->features |= NETIF_F_NTUPLE;
9050
41c445ff
JB		 9051 /* copy netdev features into list of user selectable features */
9052 netdev->hw_features |= netdev->features;
9053
9054 if (vsi->type == I40E_VSI_MAIN) {
9055 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 9056 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 9057 /* The following steps are necessary to prevent reception
9058 * of tagged packets - some older NVM configurations load a
9059 * default a MAC-VLAN filter that accepts any tagged packet
9060 * which must be replaced by a normal filter.
8c27d42e 9061 */
21659035
KP		 9062 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
9063 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 9064 i40e_add_filter(vsi, mac_addr,
9065 I40E_VLAN_ANY, false, true);
21659035
KP		 9066 spin_unlock_bh(&vsi->mac_filter_list_lock);
9067 }
41c445ff
JB		 9068 } else {
9069 /* relate the VSI_VMDQ name to the VSI_MAIN name */
9070 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
9071 pf->vsi[pf->lan_vsi]->netdev->name);
9072 random_ether_addr(mac_addr);
21659035
KP		 9073
9074 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 9075 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 9076 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9077 }
21659035
KP		 9078
9079 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 9080 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 9081 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9082
9a173901
GR		 9083 ether_addr_copy(netdev->dev_addr, mac_addr);
9084 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 9085 /* vlan gets same features (except vlan offload)
9086 * after any tweaks for specific VSI types
9087 */
9088 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
9089 NETIF_F_HW_VLAN_CTAG_RX |
9090 NETIF_F_HW_VLAN_CTAG_FILTER);
9091 netdev->priv_flags |= IFF_UNICAST_FLT;
9092 netdev->priv_flags |= IFF_SUPP_NOFCS;
9093 /* Setup netdev TC information */
9094 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9095
9096 netdev->netdev_ops = &i40e_netdev_ops;
9097 netdev->watchdog_timeo = 5 * HZ;
9098 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9099#ifdef I40E_FCOE
9100 i40e_fcoe_config_netdev(netdev, vsi);
9101#endif
41c445ff
JB		 9102
9103 return 0;
9104}
9105
9106/**
9107 * i40e_vsi_delete - Delete a VSI from the switch
9108 * @vsi: the VSI being removed
9109 *
9110 * Returns 0 on success, negative value on failure
9111 **/
9112static void i40e_vsi_delete(struct i40e_vsi *vsi)
9113{
9114 /* remove default VSI is not allowed */
9115 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9116 return;
9117
41c445ff 9118 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9119}
9120
51616018
NP		 9121/**
9122 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9123 * @vsi: the VSI being queried
9124 *
9125 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9126 **/
9127int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9128{
9129 struct i40e_veb *veb;
9130 struct i40e_pf *pf = vsi->back;
9131
9132 /* Uplink is not a bridge so default to VEB */
9133 if (vsi->veb_idx == I40E_NO_VEB)
9134 return 1;
9135
9136 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9137 if (!veb) {
9138 dev_info(&pf->pdev->dev,
9139 "There is no veb associated with the bridge\n");
9140 return -ENOENT;
9141 }
9142
51616018 9143 /* Uplink is a bridge in VEPA mode */
09603eaa 9144 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9145 return 0;
09603eaa
AA		 9146 } else {
9147 /* Uplink is a bridge in VEB mode */
9148 return 1;
9149 }
51616018 9150
09603eaa
AA		 9151 /* VEPA is now default bridge, so return 0 */
9152 return 0;
51616018
NP		 9153}
9154
41c445ff
JB		 9155/**
9156 * i40e_add_vsi - Add a VSI to the switch
9157 * @vsi: the VSI being configured
9158 *
9159 * This initializes a VSI context depending on the VSI type to be added and
9160 * passes it down to the add_vsi aq command.
9161 **/
9162static int i40e_add_vsi(struct i40e_vsi *vsi)
9163{
9164 int ret = -ENODEV;
21659035
KP		 9165 u8 laa_macaddr[ETH_ALEN];
9166 bool found_laa_mac_filter = false;
41c445ff
JB		 9167 struct i40e_pf *pf = vsi->back;
9168 struct i40e_hw *hw = &pf->hw;
9169 struct i40e_vsi_context ctxt;
21659035
KP		 9170 struct i40e_mac_filter *f, *ftmp;
9171
41c445ff
JB		 9172 u8 enabled_tc = 0x1; /* TC0 enabled */
9173 int f_count = 0;
9174
9175 memset(&ctxt, 0, sizeof(ctxt));
9176 switch (vsi->type) {
9177 case I40E_VSI_MAIN:
9178 /* The PF's main VSI is already setup as part of the
9179 * device initialization, so we'll not bother with
9180 * the add_vsi call, but we will retrieve the current
9181 * VSI context.
9182 */
9183 ctxt.seid = pf->main_vsi_seid;
9184 ctxt.pf_num = pf->hw.pf_id;
9185 ctxt.vf_num = 0;
9186 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9187 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9188 if (ret) {
9189 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9190 "couldn't get PF vsi config, err %s aq_err %s\n",
9191 i40e_stat_str(&pf->hw, ret),
9192 i40e_aq_str(&pf->hw,
9193 pf->hw.aq.asq_last_status));
41c445ff
JB		 9194 return -ENOENT;
9195 }
1a2f6248 9196 vsi->info = ctxt.info;
41c445ff
JB		 9197 vsi->info.valid_sections = 0;
9198
9199 vsi->seid = ctxt.seid;
9200 vsi->id = ctxt.vsi_number;
9201
9202 enabled_tc = i40e_pf_get_tc_map(pf);
9203
9204 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9205 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9206 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9207 memset(&ctxt, 0, sizeof(ctxt));
9208 ctxt.seid = pf->main_vsi_seid;
9209 ctxt.pf_num = pf->hw.pf_id;
9210 ctxt.vf_num = 0;
9211 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9212 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9213 if (ret) {
9214 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9215 "update vsi failed, err %s aq_err %s\n",
9216 i40e_stat_str(&pf->hw, ret),
9217 i40e_aq_str(&pf->hw,
9218 pf->hw.aq.asq_last_status));
41c445ff
JB		 9219 ret = -ENOENT;
9220 goto err;
9221 }
9222 /* update the local VSI info queue map */
9223 i40e_vsi_update_queue_map(vsi, &ctxt);
9224 vsi->info.valid_sections = 0;
9225 } else {
9226 /* Default/Main VSI is only enabled for TC0
9227 * reconfigure it to enable all TCs that are
9228 * available on the port in SFP mode.
63d7e5a4
NP		 9229 * For MFP case the iSCSI PF would use this
9230 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9231 */
9232 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9233 if (ret) {
9234 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9235 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9236 enabled_tc,
9237 i40e_stat_str(&pf->hw, ret),
9238 i40e_aq_str(&pf->hw,
9239 pf->hw.aq.asq_last_status));
41c445ff
JB		 9240 ret = -ENOENT;
9241 }
9242 }
9243 break;
9244
9245 case I40E_VSI_FDIR:
cbf61325
ASJ		 9246 ctxt.pf_num = hw->pf_id;
9247 ctxt.vf_num = 0;
9248 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9249 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9250 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9251 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9252 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9253 ctxt.info.valid_sections |=
fc60861e 9254 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9255 ctxt.info.switch_id =
fc60861e 9256 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9257 }
41c445ff 9258 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9259 break;
9260
9261 case I40E_VSI_VMDQ2:
9262 ctxt.pf_num = hw->pf_id;
9263 ctxt.vf_num = 0;
9264 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9265 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9266 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9267
41c445ff
JB		 9268 /* This VSI is connected to VEB so the switch_id
9269 * should be set to zero by default.
9270 */
51616018
NP		 9271 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9272 ctxt.info.valid_sections |=
9273 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9274 ctxt.info.switch_id =
9275 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9276 }
41c445ff
JB		 9277
9278 /* Setup the VSI tx/rx queue map for TC0 only for now */
9279 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9280 break;
9281
9282 case I40E_VSI_SRIOV:
9283 ctxt.pf_num = hw->pf_id;
9284 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9285 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9286 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9287 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9288
41c445ff
JB		 9289 /* This VSI is connected to VEB so the switch_id
9290 * should be set to zero by default.
9291 */
51616018
NP		 9292 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9293 ctxt.info.valid_sections |=
9294 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9295 ctxt.info.switch_id =
9296 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9297 }
41c445ff
JB		 9298
9299 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9300 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9301 if (pf->vf[vsi->vf_id].spoofchk) {
9302 ctxt.info.valid_sections |=
9303 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9304 ctxt.info.sec_flags |=
9305 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9306 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9307 }
41c445ff
JB		 9308 /* Setup the VSI tx/rx queue map for TC0 only for now */
9309 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9310 break;
9311
38e00438
VD		 9312#ifdef I40E_FCOE
9313 case I40E_VSI_FCOE:
9314 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9315 if (ret) {
9316 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9317 return ret;
9318 }
9319 break;
9320
9321#endif /* I40E_FCOE */
41c445ff
JB		 9322 default:
9323 return -ENODEV;
9324 }
9325
9326 if (vsi->type != I40E_VSI_MAIN) {
9327 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9328 if (ret) {
9329 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9330 "add vsi failed, err %s aq_err %s\n",
9331 i40e_stat_str(&pf->hw, ret),
9332 i40e_aq_str(&pf->hw,
9333 pf->hw.aq.asq_last_status));
41c445ff
JB		 9334 ret = -ENOENT;
9335 goto err;
9336 }
1a2f6248 9337 vsi->info = ctxt.info;
41c445ff
JB		 9338 vsi->info.valid_sections = 0;
9339 vsi->seid = ctxt.seid;
9340 vsi->id = ctxt.vsi_number;
9341 }
9342
21659035 9343 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9344 /* If macvlan filters already exist, force them to get loaded */
9345 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9346 f->changed = true;
9347 f_count++;
6252c7e4 9348
21659035 9349 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9350 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9351 ether_addr_copy(laa_macaddr, f->macaddr);
9352 found_laa_mac_filter = true;
9353 }
9354 }
9355 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9356
21659035
KP		 9357 if (found_laa_mac_filter) {
9358 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9359
21659035
KP		 9360 memset(&element, 0, sizeof(element));
9361 ether_addr_copy(element.mac_addr, laa_macaddr);
9362 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9363 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9364 &element, 1, NULL);
9365 if (ret) {
9366 /* some older FW has a different default */
9367 element.flags |=
9368 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9369 i40e_aq_remove_macvlan(hw, vsi->seid,
9370 &element, 1, NULL);
6252c7e4 9371 }
21659035
KP		 9372
9373 i40e_aq_mac_address_write(hw,
9374 I40E_AQC_WRITE_TYPE_LAA_WOL,
9375 laa_macaddr, NULL);
41c445ff 9376 }
21659035 9377
41c445ff
JB		 9378 if (f_count) {
9379 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9380 pf->flags |= I40E_FLAG_FILTER_SYNC;
9381 }
9382
9383 /* Update VSI BW information */
9384 ret = i40e_vsi_get_bw_info(vsi);
9385 if (ret) {
9386 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9387 "couldn't get vsi bw info, err %s aq_err %s\n",
9388 i40e_stat_str(&pf->hw, ret),
9389 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9390 /* VSI is already added so not tearing that up */
9391 ret = 0;
9392 }
9393
9394err:
9395 return ret;
9396}
9397
9398/**
9399 * i40e_vsi_release - Delete a VSI and free its resources
9400 * @vsi: the VSI being removed
9401 *
9402 * Returns 0 on success or < 0 on error
9403 **/
9404int i40e_vsi_release(struct i40e_vsi *vsi)
9405{
9406 struct i40e_mac_filter *f, *ftmp;
9407 struct i40e_veb *veb = NULL;
9408 struct i40e_pf *pf;
9409 u16 uplink_seid;
9410 int i, n;
9411
9412 pf = vsi->back;
9413
9414 /* release of a VEB-owner or last VSI is not allowed */
9415 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9416 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9417 vsi->seid, vsi->uplink_seid);
9418 return -ENODEV;
9419 }
9420 if (vsi == pf->vsi[pf->lan_vsi] &&
9421 !test_bit(__I40E_DOWN, &pf->state)) {
9422 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9423 return -ENODEV;
9424 }
9425
9426 uplink_seid = vsi->uplink_seid;
9427 if (vsi->type != I40E_VSI_SRIOV) {
9428 if (vsi->netdev_registered) {
9429 vsi->netdev_registered = false;
9430 if (vsi->netdev) {
9431 /* results in a call to i40e_close() */
9432 unregister_netdev(vsi->netdev);
41c445ff
JB		 9433 }
9434 } else {
90ef8d47 9435 i40e_vsi_close(vsi);
41c445ff
JB		 9436 }
9437 i40e_vsi_disable_irq(vsi);
9438 }
9439
21659035 9440 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9441 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9442 i40e_del_filter(vsi, f->macaddr, f->vlan,
9443 f->is_vf, f->is_netdev);
21659035
KP		 9444 spin_unlock_bh(&vsi->mac_filter_list_lock);
9445
17652c63 9446 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9447
9448 i40e_vsi_delete(vsi);
9449 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9450 if (vsi->netdev) {
9451 free_netdev(vsi->netdev);
9452 vsi->netdev = NULL;
9453 }
41c445ff
JB		 9454 i40e_vsi_clear_rings(vsi);
9455 i40e_vsi_clear(vsi);
9456
9457 /* If this was the last thing on the VEB, except for the
9458 * controlling VSI, remove the VEB, which puts the controlling
9459 * VSI onto the next level down in the switch.
9460 *
9461 * Well, okay, there's one more exception here: don't remove
9462 * the orphan VEBs yet. We'll wait for an explicit remove request
9463 * from up the network stack.
9464 */
505682cd 9465 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9466 if (pf->vsi[i] &&
9467 pf->vsi[i]->uplink_seid == uplink_seid &&
9468 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9469 n++; /* count the VSIs */
9470 }
9471 }
9472 for (i = 0; i < I40E_MAX_VEB; i++) {
9473 if (!pf->veb[i])
9474 continue;
9475 if (pf->veb[i]->uplink_seid == uplink_seid)
9476 n++; /* count the VEBs */
9477 if (pf->veb[i]->seid == uplink_seid)
9478 veb = pf->veb[i];
9479 }
9480 if (n == 0 && veb && veb->uplink_seid != 0)
9481 i40e_veb_release(veb);
9482
9483 return 0;
9484}
9485
9486/**
9487 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9488 * @vsi: ptr to the VSI
9489 *
9490 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9491 * corresponding SW VSI structure and initializes num_queue_pairs for the
9492 * newly allocated VSI.
9493 *
9494 * Returns 0 on success or negative on failure
9495 **/
9496static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9497{
9498 int ret = -ENOENT;
9499 struct i40e_pf *pf = vsi->back;
9500
493fb300 9501 if (vsi->q_vectors[0]) {
41c445ff
JB		 9502 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9503 vsi->seid);
9504 return -EEXIST;
9505 }
9506
9507 if (vsi->base_vector) {
f29eaa3d 9508 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9509 vsi->seid, vsi->base_vector);
9510 return -EEXIST;
9511 }
9512
90e04070 9513 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9514 if (ret) {
9515 dev_info(&pf->pdev->dev,
9516 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9517 vsi->num_q_vectors, vsi->seid, ret);
9518 vsi->num_q_vectors = 0;
9519 goto vector_setup_out;
9520 }
9521
26cdc443
ASJ		 9522 /* In Legacy mode, we do not have to get any other vector since we
9523 * piggyback on the misc/ICR0 for queue interrupts.
9524 */
9525 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9526 return ret;
958a3e3b
SN		 9527 if (vsi->num_q_vectors)
9528 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9529 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9530 if (vsi->base_vector < 0) {
9531 dev_info(&pf->pdev->dev,
049a2be8
SN		 9532 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9533 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9534 i40e_vsi_free_q_vectors(vsi);
9535 ret = -ENOENT;
9536 goto vector_setup_out;
9537 }
9538
9539vector_setup_out:
9540 return ret;
9541}
9542
bc7d338f
ASJ		 9543/**
9544 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9545 * @vsi: pointer to the vsi.
9546 *
9547 * This re-allocates a vsi's queue resources.
9548 *
9549 * Returns pointer to the successfully allocated and configured VSI sw struct
9550 * on success, otherwise returns NULL on failure.
9551 **/
9552static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9553{
9554 struct i40e_pf *pf = vsi->back;
9555 u8 enabled_tc;
9556 int ret;
9557
9558 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9559 i40e_vsi_clear_rings(vsi);
9560
9561 i40e_vsi_free_arrays(vsi, false);
9562 i40e_set_num_rings_in_vsi(vsi);
9563 ret = i40e_vsi_alloc_arrays(vsi, false);
9564 if (ret)
9565 goto err_vsi;
9566
9567 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9568 if (ret < 0) {
049a2be8 9569 dev_info(&pf->pdev->dev,
f1c7e72e 9570 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9571 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9572 goto err_vsi;
9573 }
9574 vsi->base_queue = ret;
9575
9576 /* Update the FW view of the VSI. Force a reset of TC and queue
9577 * layout configurations.
9578 */
9579 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9580 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9581 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9582 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9583
9584 /* assign it some queues */
9585 ret = i40e_alloc_rings(vsi);
9586 if (ret)
9587 goto err_rings;
9588
9589 /* map all of the rings to the q_vectors */
9590 i40e_vsi_map_rings_to_vectors(vsi);
9591 return vsi;
9592
9593err_rings:
9594 i40e_vsi_free_q_vectors(vsi);
9595 if (vsi->netdev_registered) {
9596 vsi->netdev_registered = false;
9597 unregister_netdev(vsi->netdev);
9598 free_netdev(vsi->netdev);
9599 vsi->netdev = NULL;
9600 }
9601 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9602err_vsi:
9603 i40e_vsi_clear(vsi);
9604 return NULL;
9605}
9606
b499ffb0
SV		 9607/**
9608 * i40e_macaddr_init - explicitly write the mac address filters.
9609 *
9610 * @vsi: pointer to the vsi.
9611 * @macaddr: the MAC address
9612 *
9613 * This is needed when the macaddr has been obtained by other
9614 * means than the default, e.g., from Open Firmware or IDPROM.
9615 * Returns 0 on success, negative on failure
9616 **/
9617static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr)
9618{
9619 int ret;
9620 struct i40e_aqc_add_macvlan_element_data element;
9621
9622 ret = i40e_aq_mac_address_write(&vsi->back->hw,
9623 I40E_AQC_WRITE_TYPE_LAA_WOL,
9624 macaddr, NULL);
9625 if (ret) {
9626 dev_info(&vsi->back->pdev->dev,
9627 "Addr change for VSI failed: %d\n", ret);
9628 return -EADDRNOTAVAIL;
9629 }
9630
9631 memset(&element, 0, sizeof(element));
9632 ether_addr_copy(element.mac_addr, macaddr);
9633 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
9634 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL);
9635 if (ret) {
9636 dev_info(&vsi->back->pdev->dev,
9637 "add filter failed err %s aq_err %s\n",
9638 i40e_stat_str(&vsi->back->hw, ret),
9639 i40e_aq_str(&vsi->back->hw,
9640 vsi->back->hw.aq.asq_last_status));
9641 }
9642 return ret;
9643}
9644
41c445ff
JB		 9645/**
9646 * i40e_vsi_setup - Set up a VSI by a given type
9647 * @pf: board private structure
9648 * @type: VSI type
9649 * @uplink_seid: the switch element to link to
9650 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9651 *
9652 * This allocates the sw VSI structure and its queue resources, then add a VSI
9653 * to the identified VEB.
9654 *
9655 * Returns pointer to the successfully allocated and configure VSI sw struct on
9656 * success, otherwise returns NULL on failure.
9657 **/
9658struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9659 u16 uplink_seid, u32 param1)
9660{
9661 struct i40e_vsi *vsi = NULL;
9662 struct i40e_veb *veb = NULL;
9663 int ret, i;
9664 int v_idx;
9665
9666 /* The requested uplink_seid must be either
9667 * - the PF's port seid
9668 * no VEB is needed because this is the PF
9669 * or this is a Flow Director special case VSI
9670 * - seid of an existing VEB
9671 * - seid of a VSI that owns an existing VEB
9672 * - seid of a VSI that doesn't own a VEB
9673 * a new VEB is created and the VSI becomes the owner
9674 * - seid of the PF VSI, which is what creates the first VEB
9675 * this is a special case of the previous
9676 *
9677 * Find which uplink_seid we were given and create a new VEB if needed
9678 */
9679 for (i = 0; i < I40E_MAX_VEB; i++) {
9680 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9681 veb = pf->veb[i];
9682 break;
9683 }
9684 }
9685
9686 if (!veb && uplink_seid != pf->mac_seid) {
9687
505682cd 9688 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9689 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9690 vsi = pf->vsi[i];
9691 break;
9692 }
9693 }
9694 if (!vsi) {
9695 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9696 uplink_seid);
9697 return NULL;
9698 }
9699
9700 if (vsi->uplink_seid == pf->mac_seid)
9701 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9702 vsi->tc_config.enabled_tc);
9703 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9704 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9705 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9706 if (veb) {
9707 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9708 dev_info(&vsi->back->pdev->dev,
fb43201f 9709 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9710 return NULL;
9711 }
fa11cb3d
ASJ		 9712 /* We come up by default in VEPA mode if SRIOV is not
9713 * already enabled, in which case we can't force VEPA
9714 * mode.
9715 */
9716 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9717 veb->bridge_mode = BRIDGE_MODE_VEPA;
9718 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9719 }
51616018 9720 i40e_config_bridge_mode(veb);
79c21a82 9721 }
41c445ff
JB		 9722 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9723 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9724 veb = pf->veb[i];
9725 }
9726 if (!veb) {
9727 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9728 return NULL;
9729 }
9730
9731 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9732 uplink_seid = veb->seid;
9733 }
9734
9735 /* get vsi sw struct */
9736 v_idx = i40e_vsi_mem_alloc(pf, type);
9737 if (v_idx < 0)
9738 goto err_alloc;
9739 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9740 if (!vsi)
9741 goto err_alloc;
41c445ff
JB		 9742 vsi->type = type;
9743 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9744
9745 if (type == I40E_VSI_MAIN)
9746 pf->lan_vsi = v_idx;
9747 else if (type == I40E_VSI_SRIOV)
9748 vsi->vf_id = param1;
9749 /* assign it some queues */
cbf61325
ASJ		 9750 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9751 vsi->idx);
41c445ff 9752 if (ret < 0) {
049a2be8
SN		 9753 dev_info(&pf->pdev->dev,
9754 "failed to get tracking for %d queues for VSI %d err=%d\n",
9755 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9756 goto err_vsi;
9757 }
9758 vsi->base_queue = ret;
9759
9760 /* get a VSI from the hardware */
9761 vsi->uplink_seid = uplink_seid;
9762 ret = i40e_add_vsi(vsi);
9763 if (ret)
9764 goto err_vsi;
9765
9766 switch (vsi->type) {
9767 /* setup the netdev if needed */
9768 case I40E_VSI_MAIN:
b499ffb0
SV		 9769 /* Apply relevant filters if a platform-specific mac
9770 * address was selected.
9771 */
9772 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
9773 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr);
9774 if (ret) {
9775 dev_warn(&pf->pdev->dev,
9776 "could not set up macaddr; err %d\n",
9777 ret);
9778 }
9779 }
41c445ff 9780 case I40E_VSI_VMDQ2:
38e00438 9781 case I40E_VSI_FCOE:
41c445ff
JB		 9782 ret = i40e_config_netdev(vsi);
9783 if (ret)
9784 goto err_netdev;
9785 ret = register_netdev(vsi->netdev);
9786 if (ret)
9787 goto err_netdev;
9788 vsi->netdev_registered = true;
9789 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9790#ifdef CONFIG_I40E_DCB
9791 /* Setup DCB netlink interface */
9792 i40e_dcbnl_setup(vsi);
9793#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9794 /* fall through */
9795
9796 case I40E_VSI_FDIR:
9797 /* set up vectors and rings if needed */
9798 ret = i40e_vsi_setup_vectors(vsi);
9799 if (ret)
9800 goto err_msix;
9801
9802 ret = i40e_alloc_rings(vsi);
9803 if (ret)
9804 goto err_rings;
9805
9806 /* map all of the rings to the q_vectors */
9807 i40e_vsi_map_rings_to_vectors(vsi);
9808
9809 i40e_vsi_reset_stats(vsi);
9810 break;
9811
9812 default:
9813 /* no netdev or rings for the other VSI types */
9814 break;
9815 }
9816
e25d00b8
ASJ		 9817 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9818 (vsi->type == I40E_VSI_VMDQ2)) {
9819 ret = i40e_vsi_config_rss(vsi);
9820 }
41c445ff
JB		 9821 return vsi;
9822
9823err_rings:
9824 i40e_vsi_free_q_vectors(vsi);
9825err_msix:
9826 if (vsi->netdev_registered) {
9827 vsi->netdev_registered = false;
9828 unregister_netdev(vsi->netdev);
9829 free_netdev(vsi->netdev);
9830 vsi->netdev = NULL;
9831 }
9832err_netdev:
9833 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9834err_vsi:
9835 i40e_vsi_clear(vsi);
9836err_alloc:
9837 return NULL;
9838}
9839
9840/**
9841 * i40e_veb_get_bw_info - Query VEB BW information
9842 * @veb: the veb to query
9843 *
9844 * Query the Tx scheduler BW configuration data for given VEB
9845 **/
9846static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9847{
9848 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9849 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9850 struct i40e_pf *pf = veb->pf;
9851 struct i40e_hw *hw = &pf->hw;
9852 u32 tc_bw_max;
9853 int ret = 0;
9854 int i;
9855
9856 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9857 &bw_data, NULL);
9858 if (ret) {
9859 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9860 "query veb bw config failed, err %s aq_err %s\n",
9861 i40e_stat_str(&pf->hw, ret),
9862 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9863 goto out;
9864 }
9865
9866 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9867 &ets_data, NULL);
9868 if (ret) {
9869 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9870 "query veb bw ets config failed, err %s aq_err %s\n",
9871 i40e_stat_str(&pf->hw, ret),
9872 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9873 goto out;
9874 }
9875
9876 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9877 veb->bw_max_quanta = ets_data.tc_bw_max;
9878 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9879 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9880 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9881 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9882 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9883 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9884 veb->bw_tc_limit_credits[i] =
9885 le16_to_cpu(bw_data.tc_bw_limits[i]);
9886 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9887 }
9888
9889out:
9890 return ret;
9891}
9892
9893/**
9894 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9895 * @pf: board private structure
9896 *
9897 * On error: returns error code (negative)
9898 * On success: returns vsi index in PF (positive)
9899 **/
9900static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9901{
9902 int ret = -ENOENT;
9903 struct i40e_veb *veb;
9904 int i;
9905
9906 /* Need to protect the allocation of switch elements at the PF level */
9907 mutex_lock(&pf->switch_mutex);
9908
9909 /* VEB list may be fragmented if VEB creation/destruction has
9910 * been happening. We can afford to do a quick scan to look
9911 * for any free slots in the list.
9912 *
9913 * find next empty veb slot, looping back around if necessary
9914 */
9915 i = 0;
9916 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9917 i++;
9918 if (i >= I40E_MAX_VEB) {
9919 ret = -ENOMEM;
9920 goto err_alloc_veb; /* out of VEB slots! */
9921 }
9922
9923 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9924 if (!veb) {
9925 ret = -ENOMEM;
9926 goto err_alloc_veb;
9927 }
9928 veb->pf = pf;
9929 veb->idx = i;
9930 veb->enabled_tc = 1;
9931
9932 pf->veb[i] = veb;
9933 ret = i;
9934err_alloc_veb:
9935 mutex_unlock(&pf->switch_mutex);
9936 return ret;
9937}
9938
9939/**
9940 * i40e_switch_branch_release - Delete a branch of the switch tree
9941 * @branch: where to start deleting
9942 *
9943 * This uses recursion to find the tips of the branch to be
9944 * removed, deleting until we get back to and can delete this VEB.
9945 **/
9946static void i40e_switch_branch_release(struct i40e_veb *branch)
9947{
9948 struct i40e_pf *pf = branch->pf;
9949 u16 branch_seid = branch->seid;
9950 u16 veb_idx = branch->idx;
9951 int i;
9952
9953 /* release any VEBs on this VEB - RECURSION */
9954 for (i = 0; i < I40E_MAX_VEB; i++) {
9955 if (!pf->veb[i])
9956 continue;
9957 if (pf->veb[i]->uplink_seid == branch->seid)
9958 i40e_switch_branch_release(pf->veb[i]);
9959 }
9960
9961 /* Release the VSIs on this VEB, but not the owner VSI.
9962 *
9963 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9964 * the VEB itself, so don't use (*branch) after this loop.
9965 */
505682cd 9966 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9967 if (!pf->vsi[i])
9968 continue;
9969 if (pf->vsi[i]->uplink_seid == branch_seid &&
9970 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9971 i40e_vsi_release(pf->vsi[i]);
9972 }
9973 }
9974
9975 /* There's one corner case where the VEB might not have been
9976 * removed, so double check it here and remove it if needed.
9977 * This case happens if the veb was created from the debugfs
9978 * commands and no VSIs were added to it.
9979 */
9980 if (pf->veb[veb_idx])
9981 i40e_veb_release(pf->veb[veb_idx]);
9982}
9983
9984/**
9985 * i40e_veb_clear - remove veb struct
9986 * @veb: the veb to remove
9987 **/
9988static void i40e_veb_clear(struct i40e_veb *veb)
9989{
9990 if (!veb)
9991 return;
9992
9993 if (veb->pf) {
9994 struct i40e_pf *pf = veb->pf;
9995
9996 mutex_lock(&pf->switch_mutex);
9997 if (pf->veb[veb->idx] == veb)
9998 pf->veb[veb->idx] = NULL;
9999 mutex_unlock(&pf->switch_mutex);
10000 }
10001
10002 kfree(veb);
10003}
10004
10005/**
10006 * i40e_veb_release - Delete a VEB and free its resources
10007 * @veb: the VEB being removed
10008 **/
10009void i40e_veb_release(struct i40e_veb *veb)
10010{
10011 struct i40e_vsi *vsi = NULL;
10012 struct i40e_pf *pf;
10013 int i, n = 0;
10014
10015 pf = veb->pf;
10016
10017 /* find the remaining VSI and check for extras */
505682cd 10018 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10019 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
10020 n++;
10021 vsi = pf->vsi[i];
10022 }
10023 }
10024 if (n != 1) {
10025 dev_info(&pf->pdev->dev,
10026 "can't remove VEB %d with %d VSIs left\n",
10027 veb->seid, n);
10028 return;
10029 }
10030
10031 /* move the remaining VSI to uplink veb */
10032 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
10033 if (veb->uplink_seid) {
10034 vsi->uplink_seid = veb->uplink_seid;
10035 if (veb->uplink_seid == pf->mac_seid)
10036 vsi->veb_idx = I40E_NO_VEB;
10037 else
10038 vsi->veb_idx = veb->veb_idx;
10039 } else {
10040 /* floating VEB */
10041 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10042 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
10043 }
10044
10045 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
10046 i40e_veb_clear(veb);
41c445ff
JB		 10047}
10048
10049/**
10050 * i40e_add_veb - create the VEB in the switch
10051 * @veb: the VEB to be instantiated
10052 * @vsi: the controlling VSI
10053 **/
10054static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
10055{
f1c7e72e 10056 struct i40e_pf *pf = veb->pf;
92faef85 10057 bool is_default = veb->pf->cur_promisc;
e1c51b95 10058 bool is_cloud = false;
41c445ff
JB		 10059 int ret;
10060
10061 /* get a VEB from the hardware */
f1c7e72e 10062 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 10063 veb->enabled_tc, is_default,
10064 is_cloud, &veb->seid, NULL);
41c445ff 10065 if (ret) {
f1c7e72e
SN		 10066 dev_info(&pf->pdev->dev,
10067 "couldn't add VEB, err %s aq_err %s\n",
10068 i40e_stat_str(&pf->hw, ret),
10069 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10070 return -EPERM;
10071 }
10072
10073 /* get statistics counter */
f1c7e72e 10074 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 10075 &veb->stats_idx, NULL, NULL, NULL);
10076 if (ret) {
f1c7e72e
SN		 10077 dev_info(&pf->pdev->dev,
10078 "couldn't get VEB statistics idx, err %s aq_err %s\n",
10079 i40e_stat_str(&pf->hw, ret),
10080 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10081 return -EPERM;
10082 }
10083 ret = i40e_veb_get_bw_info(veb);
10084 if (ret) {
f1c7e72e
SN		 10085 dev_info(&pf->pdev->dev,
10086 "couldn't get VEB bw info, err %s aq_err %s\n",
10087 i40e_stat_str(&pf->hw, ret),
10088 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10089 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 10090 return -ENOENT;
10091 }
10092
10093 vsi->uplink_seid = veb->seid;
10094 vsi->veb_idx = veb->idx;
10095 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
10096
10097 return 0;
10098}
10099
10100/**
10101 * i40e_veb_setup - Set up a VEB
10102 * @pf: board private structure
10103 * @flags: VEB setup flags
10104 * @uplink_seid: the switch element to link to
10105 * @vsi_seid: the initial VSI seid
10106 * @enabled_tc: Enabled TC bit-map
10107 *
10108 * This allocates the sw VEB structure and links it into the switch
10109 * It is possible and legal for this to be a duplicate of an already
10110 * existing VEB. It is also possible for both uplink and vsi seids
10111 * to be zero, in order to create a floating VEB.
10112 *
10113 * Returns pointer to the successfully allocated VEB sw struct on
10114 * success, otherwise returns NULL on failure.
10115 **/
10116struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
10117 u16 uplink_seid, u16 vsi_seid,
10118 u8 enabled_tc)
10119{
10120 struct i40e_veb *veb, *uplink_veb = NULL;
10121 int vsi_idx, veb_idx;
10122 int ret;
10123
10124 /* if one seid is 0, the other must be 0 to create a floating relay */
10125 if ((uplink_seid == 0 || vsi_seid == 0) &&
10126 (uplink_seid + vsi_seid != 0)) {
10127 dev_info(&pf->pdev->dev,
10128 "one, not both seid's are 0: uplink=%d vsi=%d\n",
10129 uplink_seid, vsi_seid);
10130 return NULL;
10131 }
10132
10133 /* make sure there is such a vsi and uplink */
505682cd 10134 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10135 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10136 break;
505682cd 10137 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10138 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10139 vsi_seid);
10140 return NULL;
10141 }
10142
10143 if (uplink_seid && uplink_seid != pf->mac_seid) {
10144 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10145 if (pf->veb[veb_idx] &&
10146 pf->veb[veb_idx]->seid == uplink_seid) {
10147 uplink_veb = pf->veb[veb_idx];
10148 break;
10149 }
10150 }
10151 if (!uplink_veb) {
10152 dev_info(&pf->pdev->dev,
10153 "uplink seid %d not found\n", uplink_seid);
10154 return NULL;
10155 }
10156 }
10157
10158 /* get veb sw struct */
10159 veb_idx = i40e_veb_mem_alloc(pf);
10160 if (veb_idx < 0)
10161 goto err_alloc;
10162 veb = pf->veb[veb_idx];
10163 veb->flags = flags;
10164 veb->uplink_seid = uplink_seid;
10165 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10166 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10167
10168 /* create the VEB in the switch */
10169 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10170 if (ret)
10171 goto err_veb;
1bb8b935
SN		 10172 if (vsi_idx == pf->lan_vsi)
10173 pf->lan_veb = veb->idx;
41c445ff
JB		 10174
10175 return veb;
10176
10177err_veb:
10178 i40e_veb_clear(veb);
10179err_alloc:
10180 return NULL;
10181}
10182
10183/**
b40c82e6 10184 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10185 * @pf: board private structure
10186 * @ele: element we are building info from
10187 * @num_reported: total number of elements
10188 * @printconfig: should we print the contents
10189 *
10190 * helper function to assist in extracting a few useful SEID values.
10191 **/
10192static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10193 struct i40e_aqc_switch_config_element_resp *ele,
10194 u16 num_reported, bool printconfig)
10195{
10196 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10197 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10198 u8 element_type = ele->element_type;
10199 u16 seid = le16_to_cpu(ele->seid);
10200
10201 if (printconfig)
10202 dev_info(&pf->pdev->dev,
10203 "type=%d seid=%d uplink=%d downlink=%d\n",
10204 element_type, seid, uplink_seid, downlink_seid);
10205
10206 switch (element_type) {
10207 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10208 pf->mac_seid = seid;
10209 break;
10210 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10211 /* Main VEB? */
10212 if (uplink_seid != pf->mac_seid)
10213 break;
10214 if (pf->lan_veb == I40E_NO_VEB) {
10215 int v;
10216
10217 /* find existing or else empty VEB */
10218 for (v = 0; v < I40E_MAX_VEB; v++) {
10219 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10220 pf->lan_veb = v;
10221 break;
10222 }
10223 }
10224 if (pf->lan_veb == I40E_NO_VEB) {
10225 v = i40e_veb_mem_alloc(pf);
10226 if (v < 0)
10227 break;
10228 pf->lan_veb = v;
10229 }
10230 }
10231
10232 pf->veb[pf->lan_veb]->seid = seid;
10233 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10234 pf->veb[pf->lan_veb]->pf = pf;
10235 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10236 break;
10237 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10238 if (num_reported != 1)
10239 break;
10240 /* This is immediately after a reset so we can assume this is
10241 * the PF's VSI
10242 */
10243 pf->mac_seid = uplink_seid;
10244 pf->pf_seid = downlink_seid;
10245 pf->main_vsi_seid = seid;
10246 if (printconfig)
10247 dev_info(&pf->pdev->dev,
10248 "pf_seid=%d main_vsi_seid=%d\n",
10249 pf->pf_seid, pf->main_vsi_seid);
10250 break;
10251 case I40E_SWITCH_ELEMENT_TYPE_PF:
10252 case I40E_SWITCH_ELEMENT_TYPE_VF:
10253 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10254 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10255 case I40E_SWITCH_ELEMENT_TYPE_PE:
10256 case I40E_SWITCH_ELEMENT_TYPE_PA:
10257 /* ignore these for now */
10258 break;
10259 default:
10260 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10261 element_type, seid);
10262 break;
10263 }
10264}
10265
10266/**
10267 * i40e_fetch_switch_configuration - Get switch config from firmware
10268 * @pf: board private structure
10269 * @printconfig: should we print the contents
10270 *
10271 * Get the current switch configuration from the device and
10272 * extract a few useful SEID values.
10273 **/
10274int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10275{
10276 struct i40e_aqc_get_switch_config_resp *sw_config;
10277 u16 next_seid = 0;
10278 int ret = 0;
10279 u8 *aq_buf;
10280 int i;
10281
10282 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10283 if (!aq_buf)
10284 return -ENOMEM;
10285
10286 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10287 do {
10288 u16 num_reported, num_total;
10289
10290 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10291 I40E_AQ_LARGE_BUF,
10292 &next_seid, NULL);
10293 if (ret) {
10294 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10295 "get switch config failed err %s aq_err %s\n",
10296 i40e_stat_str(&pf->hw, ret),
10297 i40e_aq_str(&pf->hw,
10298 pf->hw.aq.asq_last_status));
41c445ff
JB		 10299 kfree(aq_buf);
10300 return -ENOENT;
10301 }
10302
10303 num_reported = le16_to_cpu(sw_config->header.num_reported);
10304 num_total = le16_to_cpu(sw_config->header.num_total);
10305
10306 if (printconfig)
10307 dev_info(&pf->pdev->dev,
10308 "header: %d reported %d total\n",
10309 num_reported, num_total);
10310
41c445ff
JB		 10311 for (i = 0; i < num_reported; i++) {
10312 struct i40e_aqc_switch_config_element_resp *ele =
10313 &sw_config->element[i];
10314
10315 i40e_setup_pf_switch_element(pf, ele, num_reported,
10316 printconfig);
10317 }
10318 } while (next_seid != 0);
10319
10320 kfree(aq_buf);
10321 return ret;
10322}
10323
10324/**
10325 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10326 * @pf: board private structure
bc7d338f 10327 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10328 *
10329 * Returns 0 on success, negative value on failure
10330 **/
bc7d338f 10331static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10332{
10333 int ret;
10334
10335 /* find out what's out there already */
10336 ret = i40e_fetch_switch_configuration(pf, false);
10337 if (ret) {
10338 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10339 "couldn't fetch switch config, err %s aq_err %s\n",
10340 i40e_stat_str(&pf->hw, ret),
10341 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10342 return ret;
10343 }
10344 i40e_pf_reset_stats(pf);
10345
41c445ff 10346 /* first time setup */
bc7d338f 10347 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10348 struct i40e_vsi *vsi = NULL;
10349 u16 uplink_seid;
10350
10351 /* Set up the PF VSI associated with the PF's main VSI
10352 * that is already in the HW switch
10353 */
10354 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10355 uplink_seid = pf->veb[pf->lan_veb]->seid;
10356 else
10357 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10358 if (pf->lan_vsi == I40E_NO_VSI)
10359 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10360 else if (reinit)
10361 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10362 if (!vsi) {
10363 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10364 i40e_fdir_teardown(pf);
10365 return -EAGAIN;
10366 }
41c445ff
JB		 10367 } else {
10368 /* force a reset of TC and queue layout configurations */
10369 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10370
41c445ff
JB		 10371 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10372 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10373 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10374 }
10375 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10376
cbf61325
ASJ		 10377 i40e_fdir_sb_setup(pf);
10378
41c445ff
JB		 10379 /* Setup static PF queue filter control settings */
10380 ret = i40e_setup_pf_filter_control(pf);
10381 if (ret) {
10382 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10383 ret);
10384 /* Failure here should not stop continuing other steps */
10385 }
10386
10387 /* enable RSS in the HW, even for only one queue, as the stack can use
10388 * the hash
10389 */
10390 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10391 i40e_pf_config_rss(pf);
41c445ff
JB		 10392
10393 /* fill in link information and enable LSE reporting */
0a862b43 10394 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10395 i40e_link_event(pf);
10396
d52c20b7 10397 /* Initialize user-specific link properties */
41c445ff
JB		 10398 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10399 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10400
beb0dff1
JK		 10401 i40e_ptp_init(pf);
10402
41c445ff
JB		 10403 return ret;
10404}
10405
41c445ff
JB		 10406/**
10407 * i40e_determine_queue_usage - Work out queue distribution
10408 * @pf: board private structure
10409 **/
10410static void i40e_determine_queue_usage(struct i40e_pf *pf)
10411{
41c445ff
JB		 10412 int queues_left;
10413
10414 pf->num_lan_qps = 0;
38e00438
VD		 10415#ifdef I40E_FCOE
10416 pf->num_fcoe_qps = 0;
10417#endif
41c445ff
JB		 10418
10419 /* Find the max queues to be put into basic use. We'll always be
10420 * using TC0, whether or not DCB is running, and TC0 will get the
10421 * big RSS set.
10422 */
10423 queues_left = pf->hw.func_caps.num_tx_qp;
10424
cbf61325 10425 if ((queues_left == 1) ||
9aa7e935 10426 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10427 /* one qp for PF, no queues for anything else */
10428 queues_left = 0;
acd65448 10429 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10430
10431 /* make sure all the fancies are disabled */
60ea5f83 10432 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10433#ifdef I40E_FCOE
10434 I40E_FLAG_FCOE_ENABLED |
10435#endif
60ea5f83
JB		 10436 I40E_FLAG_FD_SB_ENABLED |
10437 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10438 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10439 I40E_FLAG_SRIOV_ENABLED |
10440 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10441 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10442 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10443 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10444 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10445 /* one qp for PF */
acd65448 10446 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10447 queues_left -= pf->num_lan_qps;
10448
10449 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10450#ifdef I40E_FCOE
10451 I40E_FLAG_FCOE_ENABLED |
10452#endif
9aa7e935
FZ		 10453 I40E_FLAG_FD_SB_ENABLED |
10454 I40E_FLAG_FD_ATR_ENABLED |
10455 I40E_FLAG_DCB_ENABLED |
10456 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10457 } else {
cbf61325 10458 /* Not enough queues for all TCs */
4d9b6043 10459 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10460 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10461 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10462 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10463 }
9a3bd2f1
ASJ		 10464 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10465 num_online_cpus());
10466 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10467 pf->hw.func_caps.num_tx_qp);
10468
cbf61325
ASJ		 10469 queues_left -= pf->num_lan_qps;
10470 }
10471
38e00438
VD		 10472#ifdef I40E_FCOE
10473 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10474 if (I40E_DEFAULT_FCOE <= queues_left) {
10475 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10476 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10477 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10478 } else {
10479 pf->num_fcoe_qps = 0;
10480 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10481 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10482 }
10483
10484 queues_left -= pf->num_fcoe_qps;
10485 }
10486
10487#endif
cbf61325
ASJ		 10488 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10489 if (queues_left > 1) {
10490 queues_left -= 1; /* save 1 queue for FD */
10491 } else {
10492 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10493 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10494 }
41c445ff
JB		 10495 }
10496
10497 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10498 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10499 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10500 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10501 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10502 }
10503
10504 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10505 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10506 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10507 (queues_left / pf->num_vmdq_qps));
10508 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10509 }
10510
f8ff1464 10511 pf->queues_left = queues_left;
8279e495
NP		 10512 dev_dbg(&pf->pdev->dev,
10513 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10514 pf->hw.func_caps.num_tx_qp,
10515 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10516 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10517 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10518 queues_left);
38e00438 10519#ifdef I40E_FCOE
8279e495 10520 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10521#endif
41c445ff
JB		 10522}
10523
10524/**
10525 * i40e_setup_pf_filter_control - Setup PF static filter control
10526 * @pf: PF to be setup
10527 *
b40c82e6 10528 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10529 * settings. If PE/FCoE are enabled then it will also set the per PF
10530 * based filter sizes required for them. It also enables Flow director,
10531 * ethertype and macvlan type filter settings for the pf.
10532 *
10533 * Returns 0 on success, negative on failure
10534 **/
10535static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10536{
10537 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10538
10539 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10540
10541 /* Flow Director is enabled */
60ea5f83 10542 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10543 settings->enable_fdir = true;
10544
10545 /* Ethtype and MACVLAN filters enabled for PF */
10546 settings->enable_ethtype = true;
10547 settings->enable_macvlan = true;
10548
10549 if (i40e_set_filter_control(&pf->hw, settings))
10550 return -ENOENT;
10551
10552 return 0;
10553}
10554
0c22b3dd 10555#define INFO_STRING_LEN 255
7fd89545 10556#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10557static void i40e_print_features(struct i40e_pf *pf)
10558{
10559 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10560 char *buf;
10561 int i;
0c22b3dd 10562
3b195843
JP		 10563 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10564 if (!buf)
0c22b3dd 10565 return;
0c22b3dd 10566
3b195843 10567 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10568#ifdef CONFIG_PCI_IOV
3b195843 10569 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10570#endif
3b195843 10571 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d RX: %s",
7fd89545
SN		 10572 pf->hw.func_caps.num_vsis,
10573 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10574 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10575
10576 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10577 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10578 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10579 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10580 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10581 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10582 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10583 }
4d9b6043 10584 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10585 i += snprintf(&buf[i], REMAIN(i), " DCB");
ce6fcb3f 10586#if IS_ENABLED(CONFIG_VXLAN)
3b195843 10587 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024
SA		 10588#endif
10589#if IS_ENABLED(CONFIG_GENEVE)
10590 i += snprintf(&buf[i], REMAIN(i), " Geneve");
ce6fcb3f 10591#endif
0c22b3dd 10592 if (pf->flags & I40E_FLAG_PTP)
3b195843 10593 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10594#ifdef I40E_FCOE
10595 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10596 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10597#endif
6dec1017 10598 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10599 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10600 else
3b195843 10601 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10602
3b195843
JP		 10603 dev_info(&pf->pdev->dev, "%s\n", buf);
10604 kfree(buf);
7fd89545 10605 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10606}
10607
b499ffb0
SV		 10608/**
10609 * i40e_get_platform_mac_addr - get platform-specific MAC address
10610 *
10611 * @pdev: PCI device information struct
10612 * @pf: board private structure
10613 *
10614 * Look up the MAC address in Open Firmware on systems that support it,
10615 * and use IDPROM on SPARC if no OF address is found. On return, the
10616 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value
10617 * has been selected.
10618 **/
10619static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
10620{
10621 struct device_node *dp = pci_device_to_OF_node(pdev);
10622 const unsigned char *addr;
10623 u8 *mac_addr = pf->hw.mac.addr;
10624
10625 pf->flags &= ~I40E_FLAG_PF_MAC;
10626 addr = of_get_mac_address(dp);
10627 if (addr) {
10628 ether_addr_copy(mac_addr, addr);
10629 pf->flags |= I40E_FLAG_PF_MAC;
10630#ifdef CONFIG_SPARC
10631 } else {
10632 ether_addr_copy(mac_addr, idprom->id_ethaddr);
10633 pf->flags |= I40E_FLAG_PF_MAC;
10634#endif /* CONFIG_SPARC */
10635 }
10636}
10637
41c445ff
JB		 10638/**
10639 * i40e_probe - Device initialization routine
10640 * @pdev: PCI device information struct
10641 * @ent: entry in i40e_pci_tbl
10642 *
b40c82e6
JK		 10643 * i40e_probe initializes a PF identified by a pci_dev structure.
10644 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10645 * and a hardware reset occur.
10646 *
10647 * Returns 0 on success, negative on failure
10648 **/
10649static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10650{
e827845c 10651 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10652 struct i40e_pf *pf;
10653 struct i40e_hw *hw;
93cd765b 10654 static u16 pfs_found;
1d5109d1 10655 u16 wol_nvm_bits;
d4dfb81a 10656 u16 link_status;
6f66a484 10657 int err;
4f2f017c 10658 u32 val;
8a9eb7d3 10659 u32 i;
58fc3267 10660 u8 set_fc_aq_fail;
41c445ff
JB		 10661
10662 err = pci_enable_device_mem(pdev);
10663 if (err)
10664 return err;
10665
10666 /* set up for high or low dma */
6494294f 10667 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10668 if (err) {
e3e3bfdd
JS		 10669 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10670 if (err) {
10671 dev_err(&pdev->dev,
10672 "DMA configuration failed: 0x%x\n", err);
10673 goto err_dma;
10674 }
41c445ff
JB		 10675 }
10676
10677 /* set up pci connections */
10678 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10679 IORESOURCE_MEM), i40e_driver_name);
10680 if (err) {
10681 dev_info(&pdev->dev,
10682 "pci_request_selected_regions failed %d\n", err);
10683 goto err_pci_reg;
10684 }
10685
10686 pci_enable_pcie_error_reporting(pdev);
10687 pci_set_master(pdev);
10688
10689 /* Now that we have a PCI connection, we need to do the
10690 * low level device setup. This is primarily setting up
10691 * the Admin Queue structures and then querying for the
10692 * device's current profile information.
10693 */
10694 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10695 if (!pf) {
10696 err = -ENOMEM;
10697 goto err_pf_alloc;
10698 }
10699 pf->next_vsi = 0;
10700 pf->pdev = pdev;
10701 set_bit(__I40E_DOWN, &pf->state);
10702
10703 hw = &pf->hw;
10704 hw->back = pf;
232f4706 10705
2ac8b675
SN		 10706 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10707 I40E_MAX_CSR_SPACE);
232f4706 10708
2ac8b675 10709 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10710 if (!hw->hw_addr) {
10711 err = -EIO;
10712 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10713 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10714 pf->ioremap_len, err);
41c445ff
JB		 10715 goto err_ioremap;
10716 }
10717 hw->vendor_id = pdev->vendor;
10718 hw->device_id = pdev->device;
10719 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10720 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10721 hw->subsystem_device_id = pdev->subsystem_device;
10722 hw->bus.device = PCI_SLOT(pdev->devfn);
10723 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10724 pf->instance = pfs_found;
41c445ff 10725
5b5faa43
SN		 10726 if (debug != -1) {
10727 pf->msg_enable = pf->hw.debug_mask;
10728 pf->msg_enable = debug;
10729 }
10730
7134f9ce
JB		 10731 /* do a special CORER for clearing PXE mode once at init */
10732 if (hw->revision_id == 0 &&
10733 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10734 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10735 i40e_flush(hw);
10736 msleep(200);
10737 pf->corer_count++;
10738
10739 i40e_clear_pxe_mode(hw);
10740 }
10741
41c445ff 10742 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10743 i40e_clear_hw(hw);
41c445ff
JB		 10744 err = i40e_pf_reset(hw);
10745 if (err) {
10746 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10747 goto err_pf_reset;
10748 }
10749 pf->pfr_count++;
10750
10751 hw->aq.num_arq_entries = I40E_AQ_LEN;
10752 hw->aq.num_asq_entries = I40E_AQ_LEN;
10753 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10754 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10755 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10756
b294ac70 10757 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10758 "%s-%s:misc",
10759 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10760
10761 err = i40e_init_shared_code(hw);
10762 if (err) {
b2a75c58
ASJ		 10763 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10764 err);
41c445ff
JB		 10765 goto err_pf_reset;
10766 }
10767
d52c20b7
JB		 10768 /* set up a default setting for link flow control */
10769 pf->hw.fc.requested_mode = I40E_FC_NONE;
10770
8ddb3326
JB		 10771 /* set up the locks for the AQ, do this only once in probe
10772 * and destroy them only once in remove
10773 */
10774 mutex_init(&hw->aq.asq_mutex);
10775 mutex_init(&hw->aq.arq_mutex);
10776
41c445ff 10777 err = i40e_init_adminq(hw);
2b2426a7
CW		 10778 if (err) {
10779 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10780 dev_info(&pdev->dev,
10781 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10782 else
10783 dev_info(&pdev->dev,
10784 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10785
10786 goto err_pf_reset;
10787 }
f0b44440 10788
6dec1017
SN		 10789 /* provide nvm, fw, api versions */
10790 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10791 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10792 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10793 i40e_nvm_version_str(hw));
f0b44440 10794
7aa67613
CS		 10795 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10796 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10797 dev_info(&pdev->dev,
7aa67613
CS		 10798 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10799 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10800 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10801 dev_info(&pdev->dev,
7aa67613 10802 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10803
4eb3f768
SN		 10804 i40e_verify_eeprom(pf);
10805
2c5fe33b
JB		 10806 /* Rev 0 hardware was never productized */
10807 if (hw->revision_id < 1)
10808 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10809
6ff4ef86 10810 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10811 err = i40e_get_capabilities(pf);
10812 if (err)
10813 goto err_adminq_setup;
10814
10815 err = i40e_sw_init(pf);
10816 if (err) {
10817 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10818 goto err_sw_init;
10819 }
10820
10821 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10822 hw->func_caps.num_rx_qp,
10823 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10824 if (err) {
10825 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10826 goto err_init_lan_hmc;
10827 }
10828
10829 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10830 if (err) {
10831 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10832 err = -ENOENT;
10833 goto err_configure_lan_hmc;
10834 }
10835
b686ece5
NP		 10836 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10837 * Ignore error return codes because if it was already disabled via
10838 * hardware settings this will fail
10839 */
10840 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10841 (pf->hw.aq.fw_maj_ver < 4)) {
10842 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10843 i40e_aq_stop_lldp(hw, true, NULL);
10844 }
10845
41c445ff 10846 i40e_get_mac_addr(hw, hw->mac.addr);
b499ffb0
SV		 10847 /* allow a platform config to override the HW addr */
10848 i40e_get_platform_mac_addr(pdev, pf);
f62b5060 10849 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10850 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10851 err = -EIO;
10852 goto err_mac_addr;
10853 }
10854 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10855 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10856 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10857 if (is_valid_ether_addr(hw->mac.port_addr))
10858 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10859#ifdef I40E_FCOE
10860 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10861 if (err)
10862 dev_info(&pdev->dev,
10863 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10864 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10865 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10866 hw->mac.san_addr);
10867 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10868 }
10869 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10870#endif /* I40E_FCOE */
41c445ff
JB		 10871
10872 pci_set_drvdata(pdev, pf);
10873 pci_save_state(pdev);
4e3b35b0
NP		 10874#ifdef CONFIG_I40E_DCB
10875 err = i40e_init_pf_dcb(pf);
10876 if (err) {
aebfc816 10877 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10878 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10879 /* Continue without DCB enabled */
4e3b35b0
NP		 10880 }
10881#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10882
10883 /* set up periodic task facility */
10884 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10885 pf->service_timer_period = HZ;
10886
10887 INIT_WORK(&pf->service_task, i40e_service_task);
10888 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10889 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10890
1d5109d1
SN		 10891 /* NVM bit on means WoL disabled for the port */
10892 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10893 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10894 pf->wol_en = false;
10895 else
10896 pf->wol_en = true;
8e2773ae
SN		 10897 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10898
41c445ff
JB		 10899 /* set up the main switch operations */
10900 i40e_determine_queue_usage(pf);
c1147280
JB		 10901 err = i40e_init_interrupt_scheme(pf);
10902 if (err)
10903 goto err_switch_setup;
41c445ff 10904
505682cd
MW		 10905 /* The number of VSIs reported by the FW is the minimum guaranteed
10906 * to us; HW supports far more and we share the remaining pool with
10907 * the other PFs. We allocate space for more than the guarantee with
10908 * the understanding that we might not get them all later.
41c445ff 10909 */
505682cd
MW		 10910 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10911 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10912 else
10913 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10914
10915 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
d17038d6
JB		 10916 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
10917 GFP_KERNEL);
ed87ac09
WY		 10918 if (!pf->vsi) {
10919 err = -ENOMEM;
41c445ff 10920 goto err_switch_setup;
ed87ac09 10921 }
41c445ff 10922
fa11cb3d
ASJ		 10923#ifdef CONFIG_PCI_IOV
10924 /* prep for VF support */
10925 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10926 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10927 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10928 if (pci_num_vf(pdev))
10929 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10930 }
10931#endif
bc7d338f 10932 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10933 if (err) {
10934 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10935 goto err_vsis;
10936 }
58fc3267
HZ		 10937
10938 /* Make sure flow control is set according to current settings */
10939 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10940 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10941 dev_dbg(&pf->pdev->dev,
10942 "Set fc with err %s aq_err %s on get_phy_cap\n",
10943 i40e_stat_str(hw, err),
10944 i40e_aq_str(hw, hw->aq.asq_last_status));
10945 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10946 dev_dbg(&pf->pdev->dev,
10947 "Set fc with err %s aq_err %s on set_phy_config\n",
10948 i40e_stat_str(hw, err),
10949 i40e_aq_str(hw, hw->aq.asq_last_status));
10950 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10951 dev_dbg(&pf->pdev->dev,
10952 "Set fc with err %s aq_err %s on get_link_info\n",
10953 i40e_stat_str(hw, err),
10954 i40e_aq_str(hw, hw->aq.asq_last_status));
10955
8a9eb7d3 10956 /* if FDIR VSI was set up, start it now */
505682cd 10957 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10958 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10959 i40e_vsi_open(pf->vsi[i]);
10960 break;
10961 }
10962 }
41c445ff 10963
7e2453fe
JB		 10964 /* driver is only interested in link up/down and module qualification
10965 * reports from firmware
10966 */
10967 err = i40e_aq_set_phy_int_mask(&pf->hw,
10968 I40E_AQ_EVENT_LINK_UPDOWN |
10969 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10970 if (err)
f1c7e72e
SN		 10971 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10972 i40e_stat_str(&pf->hw, err),
10973 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10974
4f2f017c
ASJ		 10975 /* Reconfigure hardware for allowing smaller MSS in the case
10976 * of TSO, so that we avoid the MDD being fired and causing
10977 * a reset in the case of small MSS+TSO.
10978 */
10979 val = rd32(hw, I40E_REG_MSS);
10980 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10981 val &= ~I40E_REG_MSS_MIN_MASK;
10982 val |= I40E_64BYTE_MSS;
10983 wr32(hw, I40E_REG_MSS, val);
10984 }
10985
8eed76fa 10986 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 10987 msleep(75);
10988 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10989 if (err)
f1c7e72e
SN		 10990 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10991 i40e_stat_str(&pf->hw, err),
10992 i40e_aq_str(&pf->hw,
10993 pf->hw.aq.asq_last_status));
cafa2ee6 10994 }
41c445ff
JB		 10995 /* The main driver is (mostly) up and happy. We need to set this state
10996 * before setting up the misc vector or we get a race and the vector
10997 * ends up disabled forever.
10998 */
10999 clear_bit(__I40E_DOWN, &pf->state);
11000
11001 /* In case of MSIX we are going to setup the misc vector right here
11002 * to handle admin queue events etc. In case of legacy and MSI
11003 * the misc functionality and queue processing is combined in
11004 * the same vector and that gets setup at open.
11005 */
11006 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
11007 err = i40e_setup_misc_vector(pf);
11008 if (err) {
11009 dev_info(&pdev->dev,
11010 "setup of misc vector failed: %d\n", err);
11011 goto err_vsis;
11012 }
11013 }
11014
df805f62 11015#ifdef CONFIG_PCI_IOV
41c445ff
JB		 11016 /* prep for VF support */
11017 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 11018 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11019 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 11020 /* disable link interrupts for VFs */
11021 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
11022 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
11023 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
11024 i40e_flush(hw);
4aeec010
MW		 11025
11026 if (pci_num_vf(pdev)) {
11027 dev_info(&pdev->dev,
11028 "Active VFs found, allocating resources.\n");
11029 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
11030 if (err)
11031 dev_info(&pdev->dev,
11032 "Error %d allocating resources for existing VFs\n",
11033 err);
11034 }
41c445ff 11035 }
df805f62 11036#endif /* CONFIG_PCI_IOV */
41c445ff 11037
93cd765b
ASJ		 11038 pfs_found++;
11039
41c445ff
JB		 11040 i40e_dbg_pf_init(pf);
11041
11042 /* tell the firmware that we're starting */
44033fac 11043 i40e_send_version(pf);
41c445ff
JB		 11044
11045 /* since everything's happy, start the service_task timer */
11046 mod_timer(&pf->service_timer,
11047 round_jiffies(jiffies + pf->service_timer_period));
11048
38e00438
VD		 11049#ifdef I40E_FCOE
11050 /* create FCoE interface */
11051 i40e_fcoe_vsi_setup(pf);
11052
11053#endif
3fced535
ASJ		 11054#define PCI_SPEED_SIZE 8
11055#define PCI_WIDTH_SIZE 8
11056 /* Devices on the IOSF bus do not have this information
11057 * and will report PCI Gen 1 x 1 by default so don't bother
11058 * checking them.
11059 */
11060 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
11061 char speed[PCI_SPEED_SIZE] = "Unknown";
11062 char width[PCI_WIDTH_SIZE] = "Unknown";
11063
11064 /* Get the negotiated link width and speed from PCI config
11065 * space
11066 */
11067 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
11068 &link_status);
11069
11070 i40e_set_pci_config_data(hw, link_status);
11071
11072 switch (hw->bus.speed) {
11073 case i40e_bus_speed_8000:
11074 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
11075 case i40e_bus_speed_5000:
11076 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
11077 case i40e_bus_speed_2500:
11078 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
11079 default:
11080 break;
11081 }
11082 switch (hw->bus.width) {
11083 case i40e_bus_width_pcie_x8:
11084 strncpy(width, "8", PCI_WIDTH_SIZE); break;
11085 case i40e_bus_width_pcie_x4:
11086 strncpy(width, "4", PCI_WIDTH_SIZE); break;
11087 case i40e_bus_width_pcie_x2:
11088 strncpy(width, "2", PCI_WIDTH_SIZE); break;
11089 case i40e_bus_width_pcie_x1:
11090 strncpy(width, "1", PCI_WIDTH_SIZE); break;
11091 default:
11092 break;
11093 }
11094
11095 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
11096 speed, width);
11097
11098 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
11099 hw->bus.speed < i40e_bus_speed_8000) {
11100 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
11101 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
11102 }
d4dfb81a
CS		 11103 }
11104
e827845c
CS		 11105 /* get the requested speeds from the fw */
11106 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
11107 if (err)
8279e495
NP		 11108 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
11109 i40e_stat_str(&pf->hw, err),
11110 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 11111 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
11112
fc72dbce
CS		 11113 /* get the supported phy types from the fw */
11114 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
11115 if (err)
11116 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
11117 i40e_stat_str(&pf->hw, err),
11118 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11119 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
11120
e7358f54
ASJ		 11121 /* Add a filter to drop all Flow control frames from any VSI from being
11122 * transmitted. By doing so we stop a malicious VF from sending out
11123 * PAUSE or PFC frames and potentially controlling traffic for other
11124 * PF/VF VSIs.
11125 * The FW can still send Flow control frames if enabled.
11126 */
11127 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11128 pf->main_vsi_seid);
11129
0c22b3dd
JB		 11130 /* print a string summarizing features */
11131 i40e_print_features(pf);
11132
41c445ff
JB		 11133 return 0;
11134
11135 /* Unwind what we've done if something failed in the setup */
11136err_vsis:
11137 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 11138 i40e_clear_interrupt_scheme(pf);
11139 kfree(pf->vsi);
04b03013
SN		 11140err_switch_setup:
11141 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 11142 del_timer_sync(&pf->service_timer);
11143err_mac_addr:
11144err_configure_lan_hmc:
11145 (void)i40e_shutdown_lan_hmc(hw);
11146err_init_lan_hmc:
11147 kfree(pf->qp_pile);
41c445ff
JB		 11148err_sw_init:
11149err_adminq_setup:
11150 (void)i40e_shutdown_adminq(hw);
11151err_pf_reset:
11152 iounmap(hw->hw_addr);
11153err_ioremap:
11154 kfree(pf);
11155err_pf_alloc:
11156 pci_disable_pcie_error_reporting(pdev);
11157 pci_release_selected_regions(pdev,
11158 pci_select_bars(pdev, IORESOURCE_MEM));
11159err_pci_reg:
11160err_dma:
11161 pci_disable_device(pdev);
11162 return err;
11163}
11164
11165/**
11166 * i40e_remove - Device removal routine
11167 * @pdev: PCI device information struct
11168 *
11169 * i40e_remove is called by the PCI subsystem to alert the driver
11170 * that is should release a PCI device. This could be caused by a
11171 * Hot-Plug event, or because the driver is going to be removed from
11172 * memory.
11173 **/
11174static void i40e_remove(struct pci_dev *pdev)
11175{
11176 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11177 struct i40e_hw *hw = &pf->hw;
41c445ff 11178 i40e_status ret_code;
41c445ff
JB		 11179 int i;
11180
11181 i40e_dbg_pf_exit(pf);
11182
beb0dff1
JK		 11183 i40e_ptp_stop(pf);
11184
bcab2db9
CW		 11185 /* Disable RSS in hw */
11186 wr32(hw, I40E_PFQF_HENA(0), 0);
11187 wr32(hw, I40E_PFQF_HENA(1), 0);
11188
41c445ff
JB		 11189 /* no more scheduling of any task */
11190 set_bit(__I40E_DOWN, &pf->state);
11191 del_timer_sync(&pf->service_timer);
11192 cancel_work_sync(&pf->service_task);
11193
eb2d80bc
MW		 11194 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11195 i40e_free_vfs(pf);
11196 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11197 }
11198
41c445ff
JB		 11199 i40e_fdir_teardown(pf);
11200
11201 /* If there is a switch structure or any orphans, remove them.
11202 * This will leave only the PF's VSI remaining.
11203 */
11204 for (i = 0; i < I40E_MAX_VEB; i++) {
11205 if (!pf->veb[i])
11206 continue;
11207
11208 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11209 pf->veb[i]->uplink_seid == 0)
11210 i40e_switch_branch_release(pf->veb[i]);
11211 }
11212
11213 /* Now we can shutdown the PF's VSI, just before we kill
11214 * adminq and hmc.
11215 */
11216 if (pf->vsi[pf->lan_vsi])
11217 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11218
41c445ff 11219 /* shutdown and destroy the HMC */
60442dea
SN		 11220 if (pf->hw.hmc.hmc_obj) {
11221 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
11222 if (ret_code)
11223 dev_warn(&pdev->dev,
11224 "Failed to destroy the HMC resources: %d\n",
11225 ret_code);
11226 }
41c445ff
JB		 11227
11228 /* shutdown the adminq */
41c445ff
JB		 11229 ret_code = i40e_shutdown_adminq(&pf->hw);
11230 if (ret_code)
11231 dev_warn(&pdev->dev,
11232 "Failed to destroy the Admin Queue resources: %d\n",
11233 ret_code);
11234
8ddb3326
JB		 11235 /* destroy the locks only once, here */
11236 mutex_destroy(&hw->aq.arq_mutex);
11237 mutex_destroy(&hw->aq.asq_mutex);
11238
41c445ff
JB		 11239 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11240 i40e_clear_interrupt_scheme(pf);
505682cd 11241 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11242 if (pf->vsi[i]) {
11243 i40e_vsi_clear_rings(pf->vsi[i]);
11244 i40e_vsi_clear(pf->vsi[i]);
11245 pf->vsi[i] = NULL;
11246 }
11247 }
11248
11249 for (i = 0; i < I40E_MAX_VEB; i++) {
11250 kfree(pf->veb[i]);
11251 pf->veb[i] = NULL;
11252 }
11253
11254 kfree(pf->qp_pile);
41c445ff
JB		 11255 kfree(pf->vsi);
11256
41c445ff
JB		 11257 iounmap(pf->hw.hw_addr);
11258 kfree(pf);
11259 pci_release_selected_regions(pdev,
11260 pci_select_bars(pdev, IORESOURCE_MEM));
11261
11262 pci_disable_pcie_error_reporting(pdev);
11263 pci_disable_device(pdev);
11264}
11265
11266/**
11267 * i40e_pci_error_detected - warning that something funky happened in PCI land
11268 * @pdev: PCI device information struct
11269 *
11270 * Called to warn that something happened and the error handling steps
11271 * are in progress. Allows the driver to quiesce things, be ready for
11272 * remediation.
11273 **/
11274static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11275 enum pci_channel_state error)
11276{
11277 struct i40e_pf *pf = pci_get_drvdata(pdev);
11278
11279 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11280
11281 /* shutdown all operations */
9007bccd
SN		 11282 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11283 rtnl_lock();
11284 i40e_prep_for_reset(pf);
11285 rtnl_unlock();
11286 }
41c445ff
JB		 11287
11288 /* Request a slot reset */
11289 return PCI_ERS_RESULT_NEED_RESET;
11290}
11291
11292/**
11293 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11294 * @pdev: PCI device information struct
11295 *
11296 * Called to find if the driver can work with the device now that
11297 * the pci slot has been reset. If a basic connection seems good
11298 * (registers are readable and have sane content) then return a
11299 * happy little PCI_ERS_RESULT_xxx.
11300 **/
11301static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11302{
11303 struct i40e_pf *pf = pci_get_drvdata(pdev);
11304 pci_ers_result_t result;
11305 int err;
11306 u32 reg;
11307
fb43201f 11308 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11309 if (pci_enable_device_mem(pdev)) {
11310 dev_info(&pdev->dev,
11311 "Cannot re-enable PCI device after reset.\n");
11312 result = PCI_ERS_RESULT_DISCONNECT;
11313 } else {
11314 pci_set_master(pdev);
11315 pci_restore_state(pdev);
11316 pci_save_state(pdev);
11317 pci_wake_from_d3(pdev, false);
11318
11319 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11320 if (reg == 0)
11321 result = PCI_ERS_RESULT_RECOVERED;
11322 else
11323 result = PCI_ERS_RESULT_DISCONNECT;
11324 }
11325
11326 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11327 if (err) {
11328 dev_info(&pdev->dev,
11329 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11330 err);
11331 /* non-fatal, continue */
11332 }
11333
11334 return result;
11335}
11336
11337/**
11338 * i40e_pci_error_resume - restart operations after PCI error recovery
11339 * @pdev: PCI device information struct
11340 *
11341 * Called to allow the driver to bring things back up after PCI error
11342 * and/or reset recovery has finished.
11343 **/
11344static void i40e_pci_error_resume(struct pci_dev *pdev)
11345{
11346 struct i40e_pf *pf = pci_get_drvdata(pdev);
11347
fb43201f 11348 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11349 if (test_bit(__I40E_SUSPENDED, &pf->state))
11350 return;
11351
11352 rtnl_lock();
41c445ff 11353 i40e_handle_reset_warning(pf);
4c4935a9 11354 rtnl_unlock();
9007bccd
SN		 11355}
11356
11357/**
11358 * i40e_shutdown - PCI callback for shutting down
11359 * @pdev: PCI device information struct
11360 **/
11361static void i40e_shutdown(struct pci_dev *pdev)
11362{
11363 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11364 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11365
11366 set_bit(__I40E_SUSPENDED, &pf->state);
11367 set_bit(__I40E_DOWN, &pf->state);
11368 rtnl_lock();
11369 i40e_prep_for_reset(pf);
11370 rtnl_unlock();
11371
8e2773ae
SN		 11372 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11373 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11374
02b42498
CS		 11375 del_timer_sync(&pf->service_timer);
11376 cancel_work_sync(&pf->service_task);
11377 i40e_fdir_teardown(pf);
11378
11379 rtnl_lock();
11380 i40e_prep_for_reset(pf);
11381 rtnl_unlock();
11382
11383 wr32(hw, I40E_PFPM_APM,
11384 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11385 wr32(hw, I40E_PFPM_WUFC,
11386 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11387
e147758d
SN		 11388 i40e_clear_interrupt_scheme(pf);
11389
9007bccd 11390 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11391 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11392 pci_set_power_state(pdev, PCI_D3hot);
11393 }
11394}
11395
11396#ifdef CONFIG_PM
11397/**
11398 * i40e_suspend - PCI callback for moving to D3
11399 * @pdev: PCI device information struct
11400 **/
11401static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11402{
11403 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11404 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11405
11406 set_bit(__I40E_SUSPENDED, &pf->state);
11407 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11408
9007bccd
SN		 11409 rtnl_lock();
11410 i40e_prep_for_reset(pf);
11411 rtnl_unlock();
11412
8e2773ae
SN		 11413 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11414 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11415
11416 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11417 pci_set_power_state(pdev, PCI_D3hot);
11418
11419 return 0;
41c445ff
JB		 11420}
11421
9007bccd
SN		 11422/**
11423 * i40e_resume - PCI callback for waking up from D3
11424 * @pdev: PCI device information struct
11425 **/
11426static int i40e_resume(struct pci_dev *pdev)
11427{
11428 struct i40e_pf *pf = pci_get_drvdata(pdev);
11429 u32 err;
11430
11431 pci_set_power_state(pdev, PCI_D0);
11432 pci_restore_state(pdev);
11433 /* pci_restore_state() clears dev->state_saves, so
11434 * call pci_save_state() again to restore it.
11435 */
11436 pci_save_state(pdev);
11437
11438 err = pci_enable_device_mem(pdev);
11439 if (err) {
fb43201f 11440 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11441 return err;
11442 }
11443 pci_set_master(pdev);
11444
11445 /* no wakeup events while running */
11446 pci_wake_from_d3(pdev, false);
11447
11448 /* handling the reset will rebuild the device state */
11449 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11450 clear_bit(__I40E_DOWN, &pf->state);
11451 rtnl_lock();
11452 i40e_reset_and_rebuild(pf, false);
11453 rtnl_unlock();
11454 }
11455
11456 return 0;
11457}
11458
11459#endif
41c445ff
JB		 11460static const struct pci_error_handlers i40e_err_handler = {
11461 .error_detected = i40e_pci_error_detected,
11462 .slot_reset = i40e_pci_error_slot_reset,
11463 .resume = i40e_pci_error_resume,
11464};
11465
11466static struct pci_driver i40e_driver = {
11467 .name = i40e_driver_name,
11468 .id_table = i40e_pci_tbl,
11469 .probe = i40e_probe,
11470 .remove = i40e_remove,
9007bccd
SN		 11471#ifdef CONFIG_PM
11472 .suspend = i40e_suspend,
11473 .resume = i40e_resume,
11474#endif
11475 .shutdown = i40e_shutdown,
41c445ff
JB		 11476 .err_handler = &i40e_err_handler,
11477 .sriov_configure = i40e_pci_sriov_configure,
11478};
11479
11480/**
11481 * i40e_init_module - Driver registration routine
11482 *
11483 * i40e_init_module is the first routine called when the driver is
11484 * loaded. All it does is register with the PCI subsystem.
11485 **/
11486static int __init i40e_init_module(void)
11487{
11488 pr_info("%s: %s - version %s\n", i40e_driver_name,
11489 i40e_driver_string, i40e_driver_version_str);
11490 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11491
2803b16c
JB		 11492 /* we will see if single thread per module is enough for now,
11493 * it can't be any worse than using the system workqueue which
11494 * was already single threaded
11495 */
11496 i40e_wq = create_singlethread_workqueue(i40e_driver_name);
11497 if (!i40e_wq) {
11498 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
11499 return -ENOMEM;
11500 }
11501
41c445ff
JB		 11502 i40e_dbg_init();
11503 return pci_register_driver(&i40e_driver);
11504}
11505module_init(i40e_init_module);
11506
11507/**
11508 * i40e_exit_module - Driver exit cleanup routine
11509 *
11510 * i40e_exit_module is called just before the driver is removed
11511 * from memory.
11512 **/
11513static void __exit i40e_exit_module(void)
11514{
11515 pci_unregister_driver(&i40e_driver);
2803b16c 11516 destroy_workqueue(i40e_wq);
41c445ff
JB		 11517 i40e_dbg_exit();
11518}
11519module_exit(i40e_exit_module);
Linux kernel - Deliverables
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