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i40e: trivial: formatting and checkpatch fixes
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
a1c9a9d9
JK		 29#ifdef CONFIG_I40E_VXLAN
30#include <net/vxlan.h>
31#endif
41c445ff
JB		 32
33const char i40e_driver_name[] = "i40e";
34static const char i40e_driver_string[] =
35 "Intel(R) Ethernet Connection XL710 Network Driver";
36
37#define DRV_KERN "-k"
38
39#define DRV_VERSION_MAJOR 0
40#define DRV_VERSION_MINOR 3
7f61d1f7 41#define DRV_VERSION_BUILD 25
41c445ff
JB		 42#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
43 __stringify(DRV_VERSION_MINOR) "." \
44 __stringify(DRV_VERSION_BUILD) DRV_KERN
45const char i40e_driver_version_str[] = DRV_VERSION;
46static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
47
48/* a bit of forward declarations */
49static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
50static void i40e_handle_reset_warning(struct i40e_pf *pf);
51static int i40e_add_vsi(struct i40e_vsi *vsi);
52static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 53static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 54static int i40e_setup_misc_vector(struct i40e_pf *pf);
55static void i40e_determine_queue_usage(struct i40e_pf *pf);
56static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
57
58/* i40e_pci_tbl - PCI Device ID Table
59 *
60 * Last entry must be all 0s
61 *
62 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
63 * Class, Class Mask, private data (not used) }
64 */
65static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
66 {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
67 {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
68 {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
69 {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
70 {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
71 {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
72 {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
73 {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
74 {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
75 {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
76 /* required last entry */
77 {0, }
78};
79MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
80
81#define I40E_MAX_VF_COUNT 128
82static int debug = -1;
83module_param(debug, int, 0);
84MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
85
86MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
87MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
88MODULE_LICENSE("GPL");
89MODULE_VERSION(DRV_VERSION);
90
91/**
92 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
93 * @hw: pointer to the HW structure
94 * @mem: ptr to mem struct to fill out
95 * @size: size of memory requested
96 * @alignment: what to align the allocation to
97 **/
98int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
99 u64 size, u32 alignment)
100{
101 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
102
103 mem->size = ALIGN(size, alignment);
104 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
105 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 106 if (!mem->va)
107 return -ENOMEM;
41c445ff 108
93bc73b8 109 return 0;
41c445ff
JB		 110}
111
112/**
113 * i40e_free_dma_mem_d - OS specific memory free for shared code
114 * @hw: pointer to the HW structure
115 * @mem: ptr to mem struct to free
116 **/
117int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
118{
119 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
120
121 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
122 mem->va = NULL;
123 mem->pa = 0;
124 mem->size = 0;
125
126 return 0;
127}
128
129/**
130 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
131 * @hw: pointer to the HW structure
132 * @mem: ptr to mem struct to fill out
133 * @size: size of memory requested
134 **/
135int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
136 u32 size)
137{
138 mem->size = size;
139 mem->va = kzalloc(size, GFP_KERNEL);
140
93bc73b8
JB		 141 if (!mem->va)
142 return -ENOMEM;
41c445ff 143
93bc73b8 144 return 0;
41c445ff
JB		 145}
146
147/**
148 * i40e_free_virt_mem_d - OS specific memory free for shared code
149 * @hw: pointer to the HW structure
150 * @mem: ptr to mem struct to free
151 **/
152int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
153{
154 /* it's ok to kfree a NULL pointer */
155 kfree(mem->va);
156 mem->va = NULL;
157 mem->size = 0;
158
159 return 0;
160}
161
162/**
163 * i40e_get_lump - find a lump of free generic resource
164 * @pf: board private structure
165 * @pile: the pile of resource to search
166 * @needed: the number of items needed
167 * @id: an owner id to stick on the items assigned
168 *
169 * Returns the base item index of the lump, or negative for error
170 *
171 * The search_hint trick and lack of advanced fit-finding only work
172 * because we're highly likely to have all the same size lump requests.
173 * Linear search time and any fragmentation should be minimal.
174 **/
175static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
176 u16 needed, u16 id)
177{
178 int ret = -ENOMEM;
ddf434ac 179 int i, j;
41c445ff
JB		 180
181 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
182 dev_info(&pf->pdev->dev,
183 "param err: pile=%p needed=%d id=0x%04x\n",
184 pile, needed, id);
185 return -EINVAL;
186 }
187
188 /* start the linear search with an imperfect hint */
189 i = pile->search_hint;
ddf434ac 190 while (i < pile->num_entries) {
41c445ff
JB		 191 /* skip already allocated entries */
192 if (pile->list[i] & I40E_PILE_VALID_BIT) {
193 i++;
194 continue;
195 }
196
197 /* do we have enough in this lump? */
198 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
199 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
200 break;
201 }
202
203 if (j == needed) {
204 /* there was enough, so assign it to the requestor */
205 for (j = 0; j < needed; j++)
206 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
207 ret = i;
208 pile->search_hint = i + j;
ddf434ac 209 break;
41c445ff
JB		 210 } else {
211 /* not enough, so skip over it and continue looking */
212 i += j;
213 }
214 }
215
216 return ret;
217}
218
219/**
220 * i40e_put_lump - return a lump of generic resource
221 * @pile: the pile of resource to search
222 * @index: the base item index
223 * @id: the owner id of the items assigned
224 *
225 * Returns the count of items in the lump
226 **/
227static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
228{
229 int valid_id = (id | I40E_PILE_VALID_BIT);
230 int count = 0;
231 int i;
232
233 if (!pile || index >= pile->num_entries)
234 return -EINVAL;
235
236 for (i = index;
237 i < pile->num_entries && pile->list[i] == valid_id;
238 i++) {
239 pile->list[i] = 0;
240 count++;
241 }
242
243 if (count && index < pile->search_hint)
244 pile->search_hint = index;
245
246 return count;
247}
248
249/**
250 * i40e_service_event_schedule - Schedule the service task to wake up
251 * @pf: board private structure
252 *
253 * If not already scheduled, this puts the task into the work queue
254 **/
255static void i40e_service_event_schedule(struct i40e_pf *pf)
256{
257 if (!test_bit(__I40E_DOWN, &pf->state) &&
258 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
259 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
260 schedule_work(&pf->service_task);
261}
262
263/**
264 * i40e_tx_timeout - Respond to a Tx Hang
265 * @netdev: network interface device structure
266 *
267 * If any port has noticed a Tx timeout, it is likely that the whole
268 * device is munged, not just the one netdev port, so go for the full
269 * reset.
270 **/
271static void i40e_tx_timeout(struct net_device *netdev)
272{
273 struct i40e_netdev_priv *np = netdev_priv(netdev);
274 struct i40e_vsi *vsi = np->vsi;
275 struct i40e_pf *pf = vsi->back;
276
277 pf->tx_timeout_count++;
278
279 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
280 pf->tx_timeout_recovery_level = 0;
281 pf->tx_timeout_last_recovery = jiffies;
282 netdev_info(netdev, "tx_timeout recovery level %d\n",
283 pf->tx_timeout_recovery_level);
284
285 switch (pf->tx_timeout_recovery_level) {
286 case 0:
287 /* disable and re-enable queues for the VSI */
288 if (in_interrupt()) {
289 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
290 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
291 } else {
292 i40e_vsi_reinit_locked(vsi);
293 }
294 break;
295 case 1:
296 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
297 break;
298 case 2:
299 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
300 break;
301 case 3:
302 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
303 break;
304 default:
305 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
306 i40e_down(vsi);
307 break;
308 }
309 i40e_service_event_schedule(pf);
310 pf->tx_timeout_recovery_level++;
311}
312
313/**
314 * i40e_release_rx_desc - Store the new tail and head values
315 * @rx_ring: ring to bump
316 * @val: new head index
317 **/
318static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
319{
320 rx_ring->next_to_use = val;
321
322 /* Force memory writes to complete before letting h/w
323 * know there are new descriptors to fetch. (Only
324 * applicable for weak-ordered memory model archs,
325 * such as IA-64).
326 */
327 wmb();
328 writel(val, rx_ring->tail);
329}
330
331/**
332 * i40e_get_vsi_stats_struct - Get System Network Statistics
333 * @vsi: the VSI we care about
334 *
335 * Returns the address of the device statistics structure.
336 * The statistics are actually updated from the service task.
337 **/
338struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
339{
340 return &vsi->net_stats;
341}
342
343/**
344 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
345 * @netdev: network interface device structure
346 *
347 * Returns the address of the device statistics structure.
348 * The statistics are actually updated from the service task.
349 **/
350static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
351 struct net_device *netdev,
980e9b11 352 struct rtnl_link_stats64 *stats)
41c445ff
JB		 353{
354 struct i40e_netdev_priv *np = netdev_priv(netdev);
355 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 356 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
357 int i;
358
143c9054 359
bc7d338f
ASJ		 360 if (test_bit(__I40E_DOWN, &vsi->state))
361 return stats;
362
3c325ced
JB		 363 if (!vsi->tx_rings)
364 return stats;
365
980e9b11
AD		 366 rcu_read_lock();
367 for (i = 0; i < vsi->num_queue_pairs; i++) {
368 struct i40e_ring *tx_ring, *rx_ring;
369 u64 bytes, packets;
370 unsigned int start;
371
372 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
373 if (!tx_ring)
374 continue;
375
376 do {
377 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
378 packets = tx_ring->stats.packets;
379 bytes = tx_ring->stats.bytes;
380 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
381
382 stats->tx_packets += packets;
383 stats->tx_bytes += bytes;
384 rx_ring = &tx_ring[1];
385
386 do {
387 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
388 packets = rx_ring->stats.packets;
389 bytes = rx_ring->stats.bytes;
390 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 391
980e9b11
AD		 392 stats->rx_packets += packets;
393 stats->rx_bytes += bytes;
394 }
395 rcu_read_unlock();
396
397 /* following stats updated by ixgbe_watchdog_task() */
398 stats->multicast = vsi_stats->multicast;
399 stats->tx_errors = vsi_stats->tx_errors;
400 stats->tx_dropped = vsi_stats->tx_dropped;
401 stats->rx_errors = vsi_stats->rx_errors;
402 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
403 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 404
980e9b11 405 return stats;
41c445ff
JB		 406}
407
408/**
409 * i40e_vsi_reset_stats - Resets all stats of the given vsi
410 * @vsi: the VSI to have its stats reset
411 **/
412void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
413{
414 struct rtnl_link_stats64 *ns;
415 int i;
416
417 if (!vsi)
418 return;
419
420 ns = i40e_get_vsi_stats_struct(vsi);
421 memset(ns, 0, sizeof(*ns));
422 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
423 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
424 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 425 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 426 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 427 memset(&vsi->rx_rings[i]->stats, 0 ,
428 sizeof(vsi->rx_rings[i]->stats));
429 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
430 sizeof(vsi->rx_rings[i]->rx_stats));
431 memset(&vsi->tx_rings[i]->stats, 0 ,
432 sizeof(vsi->tx_rings[i]->stats));
433 memset(&vsi->tx_rings[i]->tx_stats, 0,
434 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 435 }
8e9dca53 436 }
41c445ff
JB		 437 vsi->stat_offsets_loaded = false;
438}
439
440/**
441 * i40e_pf_reset_stats - Reset all of the stats for the given pf
442 * @pf: the PF to be reset
443 **/
444void i40e_pf_reset_stats(struct i40e_pf *pf)
445{
446 memset(&pf->stats, 0, sizeof(pf->stats));
447 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
448 pf->stat_offsets_loaded = false;
449}
450
451/**
452 * i40e_stat_update48 - read and update a 48 bit stat from the chip
453 * @hw: ptr to the hardware info
454 * @hireg: the high 32 bit reg to read
455 * @loreg: the low 32 bit reg to read
456 * @offset_loaded: has the initial offset been loaded yet
457 * @offset: ptr to current offset value
458 * @stat: ptr to the stat
459 *
460 * Since the device stats are not reset at PFReset, they likely will not
461 * be zeroed when the driver starts. We'll save the first values read
462 * and use them as offsets to be subtracted from the raw values in order
463 * to report stats that count from zero. In the process, we also manage
464 * the potential roll-over.
465 **/
466static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
467 bool offset_loaded, u64 *offset, u64 *stat)
468{
469 u64 new_data;
470
471 if (hw->device_id == I40E_QEMU_DEVICE_ID) {
472 new_data = rd32(hw, loreg);
473 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
474 } else {
475 new_data = rd64(hw, loreg);
476 }
477 if (!offset_loaded)
478 *offset = new_data;
479 if (likely(new_data >= *offset))
480 *stat = new_data - *offset;
481 else
482 *stat = (new_data + ((u64)1 << 48)) - *offset;
483 *stat &= 0xFFFFFFFFFFFFULL;
484}
485
486/**
487 * i40e_stat_update32 - read and update a 32 bit stat from the chip
488 * @hw: ptr to the hardware info
489 * @reg: the hw reg to read
490 * @offset_loaded: has the initial offset been loaded yet
491 * @offset: ptr to current offset value
492 * @stat: ptr to the stat
493 **/
494static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
495 bool offset_loaded, u64 *offset, u64 *stat)
496{
497 u32 new_data;
498
499 new_data = rd32(hw, reg);
500 if (!offset_loaded)
501 *offset = new_data;
502 if (likely(new_data >= *offset))
503 *stat = (u32)(new_data - *offset);
504 else
505 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
506}
507
508/**
509 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
510 * @vsi: the VSI to be updated
511 **/
512void i40e_update_eth_stats(struct i40e_vsi *vsi)
513{
514 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
515 struct i40e_pf *pf = vsi->back;
516 struct i40e_hw *hw = &pf->hw;
517 struct i40e_eth_stats *oes;
518 struct i40e_eth_stats *es; /* device's eth stats */
519
520 es = &vsi->eth_stats;
521 oes = &vsi->eth_stats_offsets;
522
523 /* Gather up the stats that the hw collects */
524 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
525 vsi->stat_offsets_loaded,
526 &oes->tx_errors, &es->tx_errors);
527 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->rx_discards, &es->rx_discards);
530
531 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
532 I40E_GLV_GORCL(stat_idx),
533 vsi->stat_offsets_loaded,
534 &oes->rx_bytes, &es->rx_bytes);
535 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
536 I40E_GLV_UPRCL(stat_idx),
537 vsi->stat_offsets_loaded,
538 &oes->rx_unicast, &es->rx_unicast);
539 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
540 I40E_GLV_MPRCL(stat_idx),
541 vsi->stat_offsets_loaded,
542 &oes->rx_multicast, &es->rx_multicast);
543 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
544 I40E_GLV_BPRCL(stat_idx),
545 vsi->stat_offsets_loaded,
546 &oes->rx_broadcast, &es->rx_broadcast);
547
548 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
549 I40E_GLV_GOTCL(stat_idx),
550 vsi->stat_offsets_loaded,
551 &oes->tx_bytes, &es->tx_bytes);
552 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
553 I40E_GLV_UPTCL(stat_idx),
554 vsi->stat_offsets_loaded,
555 &oes->tx_unicast, &es->tx_unicast);
556 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
557 I40E_GLV_MPTCL(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_multicast, &es->tx_multicast);
560 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
561 I40E_GLV_BPTCL(stat_idx),
562 vsi->stat_offsets_loaded,
563 &oes->tx_broadcast, &es->tx_broadcast);
564 vsi->stat_offsets_loaded = true;
565}
566
567/**
568 * i40e_update_veb_stats - Update Switch component statistics
569 * @veb: the VEB being updated
570 **/
571static void i40e_update_veb_stats(struct i40e_veb *veb)
572{
573 struct i40e_pf *pf = veb->pf;
574 struct i40e_hw *hw = &pf->hw;
575 struct i40e_eth_stats *oes;
576 struct i40e_eth_stats *es; /* device's eth stats */
577 int idx = 0;
578
579 idx = veb->stats_idx;
580 es = &veb->stats;
581 oes = &veb->stats_offsets;
582
583 /* Gather up the stats that the hw collects */
584 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
585 veb->stat_offsets_loaded,
586 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 587 if (hw->revision_id > 0)
588 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
589 veb->stat_offsets_loaded,
590 &oes->rx_unknown_protocol,
591 &es->rx_unknown_protocol);
41c445ff
JB		 592 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
593 veb->stat_offsets_loaded,
594 &oes->rx_bytes, &es->rx_bytes);
595 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_unicast, &es->rx_unicast);
598 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_multicast, &es->rx_multicast);
601 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_broadcast, &es->rx_broadcast);
604
605 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
606 veb->stat_offsets_loaded,
607 &oes->tx_bytes, &es->tx_bytes);
608 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_unicast, &es->tx_unicast);
611 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_multicast, &es->tx_multicast);
614 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_broadcast, &es->tx_broadcast);
617 veb->stat_offsets_loaded = true;
618}
619
620/**
621 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
622 * @pf: the corresponding PF
623 *
624 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
625 **/
626static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
627{
628 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
629 struct i40e_hw_port_stats *nsd = &pf->stats;
630 struct i40e_hw *hw = &pf->hw;
631 u64 xoff = 0;
632 u16 i, v;
633
634 if ((hw->fc.current_mode != I40E_FC_FULL) &&
635 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
636 return;
637
638 xoff = nsd->link_xoff_rx;
639 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
640 pf->stat_offsets_loaded,
641 &osd->link_xoff_rx, &nsd->link_xoff_rx);
642
643 /* No new LFC xoff rx */
644 if (!(nsd->link_xoff_rx - xoff))
645 return;
646
647 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
648 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
649 struct i40e_vsi *vsi = pf->vsi[v];
650
651 if (!vsi)
652 continue;
653
654 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 655 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 656 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
657 }
658 }
659}
660
661/**
662 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
663 * @pf: the corresponding PF
664 *
665 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
666 **/
667static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
668{
669 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
670 struct i40e_hw_port_stats *nsd = &pf->stats;
671 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
672 struct i40e_dcbx_config *dcb_cfg;
673 struct i40e_hw *hw = &pf->hw;
674 u16 i, v;
675 u8 tc;
676
677 dcb_cfg = &hw->local_dcbx_config;
678
679 /* See if DCB enabled with PFC TC */
680 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
681 !(dcb_cfg->pfc.pfcenable)) {
682 i40e_update_link_xoff_rx(pf);
683 return;
684 }
685
686 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
687 u64 prio_xoff = nsd->priority_xoff_rx[i];
688 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
689 pf->stat_offsets_loaded,
690 &osd->priority_xoff_rx[i],
691 &nsd->priority_xoff_rx[i]);
692
693 /* No new PFC xoff rx */
694 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
695 continue;
696 /* Get the TC for given priority */
697 tc = dcb_cfg->etscfg.prioritytable[i];
698 xoff[tc] = true;
699 }
700
701 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
702 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
703 struct i40e_vsi *vsi = pf->vsi[v];
704
705 if (!vsi)
706 continue;
707
708 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 709 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 710
711 tc = ring->dcb_tc;
712 if (xoff[tc])
713 clear_bit(__I40E_HANG_CHECK_ARMED,
714 &ring->state);
715 }
716 }
717}
718
719/**
720 * i40e_update_stats - Update the board statistics counters.
721 * @vsi: the VSI to be updated
722 *
723 * There are a few instances where we store the same stat in a
724 * couple of different structs. This is partly because we have
725 * the netdev stats that need to be filled out, which is slightly
726 * different from the "eth_stats" defined by the chip and used in
727 * VF communications. We sort it all out here in a central place.
728 **/
729void i40e_update_stats(struct i40e_vsi *vsi)
730{
731 struct i40e_pf *pf = vsi->back;
732 struct i40e_hw *hw = &pf->hw;
733 struct rtnl_link_stats64 *ons;
734 struct rtnl_link_stats64 *ns; /* netdev stats */
735 struct i40e_eth_stats *oes;
736 struct i40e_eth_stats *es; /* device's eth stats */
737 u32 tx_restart, tx_busy;
738 u32 rx_page, rx_buf;
739 u64 rx_p, rx_b;
740 u64 tx_p, tx_b;
741 int i;
742 u16 q;
743
744 if (test_bit(__I40E_DOWN, &vsi->state) ||
745 test_bit(__I40E_CONFIG_BUSY, &pf->state))
746 return;
747
748 ns = i40e_get_vsi_stats_struct(vsi);
749 ons = &vsi->net_stats_offsets;
750 es = &vsi->eth_stats;
751 oes = &vsi->eth_stats_offsets;
752
753 /* Gather up the netdev and vsi stats that the driver collects
754 * on the fly during packet processing
755 */
756 rx_b = rx_p = 0;
757 tx_b = tx_p = 0;
758 tx_restart = tx_busy = 0;
759 rx_page = 0;
760 rx_buf = 0;
980e9b11 761 rcu_read_lock();
41c445ff
JB		 762 for (q = 0; q < vsi->num_queue_pairs; q++) {
763 struct i40e_ring *p;
980e9b11
AD		 764 u64 bytes, packets;
765 unsigned int start;
766
767 /* locate Tx ring */
768 p = ACCESS_ONCE(vsi->tx_rings[q]);
769
770 do {
771 start = u64_stats_fetch_begin_bh(&p->syncp);
772 packets = p->stats.packets;
773 bytes = p->stats.bytes;
774 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
775 tx_b += bytes;
776 tx_p += packets;
777 tx_restart += p->tx_stats.restart_queue;
778 tx_busy += p->tx_stats.tx_busy;
41c445ff 779
980e9b11
AD		 780 /* Rx queue is part of the same block as Tx queue */
781 p = &p[1];
782 do {
783 start = u64_stats_fetch_begin_bh(&p->syncp);
784 packets = p->stats.packets;
785 bytes = p->stats.bytes;
786 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
787 rx_b += bytes;
788 rx_p += packets;
420136cc
MW		 789 rx_buf += p->rx_stats.alloc_buff_failed;
790 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 791 }
980e9b11 792 rcu_read_unlock();
41c445ff
JB		 793 vsi->tx_restart = tx_restart;
794 vsi->tx_busy = tx_busy;
795 vsi->rx_page_failed = rx_page;
796 vsi->rx_buf_failed = rx_buf;
797
798 ns->rx_packets = rx_p;
799 ns->rx_bytes = rx_b;
800 ns->tx_packets = tx_p;
801 ns->tx_bytes = tx_b;
802
803 i40e_update_eth_stats(vsi);
804 /* update netdev stats from eth stats */
805 ons->rx_errors = oes->rx_errors;
806 ns->rx_errors = es->rx_errors;
807 ons->tx_errors = oes->tx_errors;
808 ns->tx_errors = es->tx_errors;
809 ons->multicast = oes->rx_multicast;
810 ns->multicast = es->rx_multicast;
811 ons->tx_dropped = oes->tx_discards;
812 ns->tx_dropped = es->tx_discards;
813
814 /* Get the port data only if this is the main PF VSI */
815 if (vsi == pf->vsi[pf->lan_vsi]) {
816 struct i40e_hw_port_stats *nsd = &pf->stats;
817 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
818
819 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
820 I40E_GLPRT_GORCL(hw->port),
821 pf->stat_offsets_loaded,
822 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
823 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
824 I40E_GLPRT_GOTCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
827 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
828 pf->stat_offsets_loaded,
829 &osd->eth.rx_discards,
830 &nsd->eth.rx_discards);
831 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.tx_discards,
834 &nsd->eth.tx_discards);
835 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
836 I40E_GLPRT_MPRCL(hw->port),
837 pf->stat_offsets_loaded,
838 &osd->eth.rx_multicast,
839 &nsd->eth.rx_multicast);
840
841 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
842 pf->stat_offsets_loaded,
843 &osd->tx_dropped_link_down,
844 &nsd->tx_dropped_link_down);
845
846 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
847 pf->stat_offsets_loaded,
848 &osd->crc_errors, &nsd->crc_errors);
849 ns->rx_crc_errors = nsd->crc_errors;
850
851 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
852 pf->stat_offsets_loaded,
853 &osd->illegal_bytes, &nsd->illegal_bytes);
854 ns->rx_errors = nsd->crc_errors
855 + nsd->illegal_bytes;
856
857 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
858 pf->stat_offsets_loaded,
859 &osd->mac_local_faults,
860 &nsd->mac_local_faults);
861 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_remote_faults,
864 &nsd->mac_remote_faults);
865
866 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
867 pf->stat_offsets_loaded,
868 &osd->rx_length_errors,
869 &nsd->rx_length_errors);
870 ns->rx_length_errors = nsd->rx_length_errors;
871
872 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->link_xon_rx, &nsd->link_xon_rx);
875 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
876 pf->stat_offsets_loaded,
877 &osd->link_xon_tx, &nsd->link_xon_tx);
878 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
879 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xoff_tx, &nsd->link_xoff_tx);
882
883 for (i = 0; i < 8; i++) {
884 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
885 pf->stat_offsets_loaded,
886 &osd->priority_xon_rx[i],
887 &nsd->priority_xon_rx[i]);
888 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_tx[i],
891 &nsd->priority_xon_tx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xoff_tx[i],
895 &nsd->priority_xoff_tx[i]);
896 i40e_stat_update32(hw,
897 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
898 pf->stat_offsets_loaded,
899 &osd->priority_xon_2_xoff[i],
900 &nsd->priority_xon_2_xoff[i]);
901 }
902
903 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
904 I40E_GLPRT_PRC64L(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->rx_size_64, &nsd->rx_size_64);
907 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
908 I40E_GLPRT_PRC127L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_127, &nsd->rx_size_127);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
912 I40E_GLPRT_PRC255L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_255, &nsd->rx_size_255);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
916 I40E_GLPRT_PRC511L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_511, &nsd->rx_size_511);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
920 I40E_GLPRT_PRC1023L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_1023, &nsd->rx_size_1023);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
924 I40E_GLPRT_PRC1522L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1522, &nsd->rx_size_1522);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
928 I40E_GLPRT_PRC9522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_big, &nsd->rx_size_big);
931
932 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
933 I40E_GLPRT_PTC64L(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->tx_size_64, &nsd->tx_size_64);
936 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
937 I40E_GLPRT_PTC127L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_127, &nsd->tx_size_127);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
941 I40E_GLPRT_PTC255L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_255, &nsd->tx_size_255);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
945 I40E_GLPRT_PTC511L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_511, &nsd->tx_size_511);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
949 I40E_GLPRT_PTC1023L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_1023, &nsd->tx_size_1023);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
953 I40E_GLPRT_PTC1522L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1522, &nsd->tx_size_1522);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
957 I40E_GLPRT_PTC9522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_big, &nsd->tx_size_big);
960
961 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->rx_undersize, &nsd->rx_undersize);
964 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->rx_fragments, &nsd->rx_fragments);
967 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->rx_oversize, &nsd->rx_oversize);
970 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_jabber, &nsd->rx_jabber);
973 }
974
975 pf->stat_offsets_loaded = true;
976}
977
978/**
979 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
980 * @vsi: the VSI to be searched
981 * @macaddr: the MAC address
982 * @vlan: the vlan
983 * @is_vf: make sure its a vf filter, else doesn't matter
984 * @is_netdev: make sure its a netdev filter, else doesn't matter
985 *
986 * Returns ptr to the filter object or NULL
987 **/
988static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
989 u8 *macaddr, s16 vlan,
990 bool is_vf, bool is_netdev)
991{
992 struct i40e_mac_filter *f;
993
994 if (!vsi || !macaddr)
995 return NULL;
996
997 list_for_each_entry(f, &vsi->mac_filter_list, list) {
998 if ((ether_addr_equal(macaddr, f->macaddr)) &&
999 (vlan == f->vlan) &&
1000 (!is_vf || f->is_vf) &&
1001 (!is_netdev || f->is_netdev))
1002 return f;
1003 }
1004 return NULL;
1005}
1006
1007/**
1008 * i40e_find_mac - Find a mac addr in the macvlan filters list
1009 * @vsi: the VSI to be searched
1010 * @macaddr: the MAC address we are searching for
1011 * @is_vf: make sure its a vf filter, else doesn't matter
1012 * @is_netdev: make sure its a netdev filter, else doesn't matter
1013 *
1014 * Returns the first filter with the provided MAC address or NULL if
1015 * MAC address was not found
1016 **/
1017struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1018 bool is_vf, bool is_netdev)
1019{
1020 struct i40e_mac_filter *f;
1021
1022 if (!vsi || !macaddr)
1023 return NULL;
1024
1025 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1026 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1027 (!is_vf || f->is_vf) &&
1028 (!is_netdev || f->is_netdev))
1029 return f;
1030 }
1031 return NULL;
1032}
1033
1034/**
1035 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1036 * @vsi: the VSI to be searched
1037 *
1038 * Returns true if VSI is in vlan mode or false otherwise
1039 **/
1040bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1041{
1042 struct i40e_mac_filter *f;
1043
1044 /* Only -1 for all the filters denotes not in vlan mode
1045 * so we have to go through all the list in order to make sure
1046 */
1047 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1048 if (f->vlan >= 0)
1049 return true;
1050 }
1051
1052 return false;
1053}
1054
1055/**
1056 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1057 * @vsi: the VSI to be searched
1058 * @macaddr: the mac address to be filtered
1059 * @is_vf: true if it is a vf
1060 * @is_netdev: true if it is a netdev
1061 *
1062 * Goes through all the macvlan filters and adds a
1063 * macvlan filter for each unique vlan that already exists
1064 *
1065 * Returns first filter found on success, else NULL
1066 **/
1067struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1068 bool is_vf, bool is_netdev)
1069{
1070 struct i40e_mac_filter *f;
1071
1072 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1073 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1074 is_vf, is_netdev)) {
1075 if (!i40e_add_filter(vsi, macaddr, f->vlan,
1076 is_vf, is_netdev))
1077 return NULL;
1078 }
1079 }
1080
1081 return list_first_entry_or_null(&vsi->mac_filter_list,
1082 struct i40e_mac_filter, list);
1083}
1084
1085/**
1086 * i40e_add_filter - Add a mac/vlan filter to the VSI
1087 * @vsi: the VSI to be searched
1088 * @macaddr: the MAC address
1089 * @vlan: the vlan
1090 * @is_vf: make sure its a vf filter, else doesn't matter
1091 * @is_netdev: make sure its a netdev filter, else doesn't matter
1092 *
1093 * Returns ptr to the filter object or NULL when no memory available.
1094 **/
1095struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1096 u8 *macaddr, s16 vlan,
1097 bool is_vf, bool is_netdev)
1098{
1099 struct i40e_mac_filter *f;
1100
1101 if (!vsi || !macaddr)
1102 return NULL;
1103
1104 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1105 if (!f) {
1106 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1107 if (!f)
1108 goto add_filter_out;
1109
1110 memcpy(f->macaddr, macaddr, ETH_ALEN);
1111 f->vlan = vlan;
1112 f->changed = true;
1113
1114 INIT_LIST_HEAD(&f->list);
1115 list_add(&f->list, &vsi->mac_filter_list);
1116 }
1117
1118 /* increment counter and add a new flag if needed */
1119 if (is_vf) {
1120 if (!f->is_vf) {
1121 f->is_vf = true;
1122 f->counter++;
1123 }
1124 } else if (is_netdev) {
1125 if (!f->is_netdev) {
1126 f->is_netdev = true;
1127 f->counter++;
1128 }
1129 } else {
1130 f->counter++;
1131 }
1132
1133 /* changed tells sync_filters_subtask to
1134 * push the filter down to the firmware
1135 */
1136 if (f->changed) {
1137 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1138 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1139 }
1140
1141add_filter_out:
1142 return f;
1143}
1144
1145/**
1146 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1147 * @vsi: the VSI to be searched
1148 * @macaddr: the MAC address
1149 * @vlan: the vlan
1150 * @is_vf: make sure it's a vf filter, else doesn't matter
1151 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1152 **/
1153void i40e_del_filter(struct i40e_vsi *vsi,
1154 u8 *macaddr, s16 vlan,
1155 bool is_vf, bool is_netdev)
1156{
1157 struct i40e_mac_filter *f;
1158
1159 if (!vsi || !macaddr)
1160 return;
1161
1162 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1163 if (!f || f->counter == 0)
1164 return;
1165
1166 if (is_vf) {
1167 if (f->is_vf) {
1168 f->is_vf = false;
1169 f->counter--;
1170 }
1171 } else if (is_netdev) {
1172 if (f->is_netdev) {
1173 f->is_netdev = false;
1174 f->counter--;
1175 }
1176 } else {
1177 /* make sure we don't remove a filter in use by vf or netdev */
1178 int min_f = 0;
1179 min_f += (f->is_vf ? 1 : 0);
1180 min_f += (f->is_netdev ? 1 : 0);
1181
1182 if (f->counter > min_f)
1183 f->counter--;
1184 }
1185
1186 /* counter == 0 tells sync_filters_subtask to
1187 * remove the filter from the firmware's list
1188 */
1189 if (f->counter == 0) {
1190 f->changed = true;
1191 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1192 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1193 }
1194}
1195
1196/**
1197 * i40e_set_mac - NDO callback to set mac address
1198 * @netdev: network interface device structure
1199 * @p: pointer to an address structure
1200 *
1201 * Returns 0 on success, negative on failure
1202 **/
1203static int i40e_set_mac(struct net_device *netdev, void *p)
1204{
1205 struct i40e_netdev_priv *np = netdev_priv(netdev);
1206 struct i40e_vsi *vsi = np->vsi;
1207 struct sockaddr *addr = p;
1208 struct i40e_mac_filter *f;
1209
1210 if (!is_valid_ether_addr(addr->sa_data))
1211 return -EADDRNOTAVAIL;
1212
1213 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1214
1215 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1216 return 0;
1217
80f6428f
ASJ		 1218 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1219 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1220 return -EADDRNOTAVAIL;
1221
41c445ff
JB		 1222 if (vsi->type == I40E_VSI_MAIN) {
1223 i40e_status ret;
1224 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1225 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1226 addr->sa_data, NULL);
1227 if (ret) {
1228 netdev_info(netdev,
1229 "Addr change for Main VSI failed: %d\n",
1230 ret);
1231 return -EADDRNOTAVAIL;
1232 }
1233
1234 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1235 }
1236
1237 /* In order to be sure to not drop any packets, add the new address
1238 * then delete the old one.
1239 */
1240 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1241 if (!f)
1242 return -ENOMEM;
1243
1244 i40e_sync_vsi_filters(vsi);
1245 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1246 i40e_sync_vsi_filters(vsi);
1247
1248 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1249
1250 return 0;
1251}
1252
1253/**
1254 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1255 * @vsi: the VSI being setup
1256 * @ctxt: VSI context structure
1257 * @enabled_tc: Enabled TCs bitmap
1258 * @is_add: True if called before Add VSI
1259 *
1260 * Setup VSI queue mapping for enabled traffic classes.
1261 **/
1262static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1263 struct i40e_vsi_context *ctxt,
1264 u8 enabled_tc,
1265 bool is_add)
1266{
1267 struct i40e_pf *pf = vsi->back;
1268 u16 sections = 0;
1269 u8 netdev_tc = 0;
1270 u16 numtc = 0;
1271 u16 qcount;
1272 u8 offset;
1273 u16 qmap;
1274 int i;
1275
1276 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1277 offset = 0;
1278
1279 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1280 /* Find numtc from enabled TC bitmap */
1281 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1282 if (enabled_tc & (1 << i)) /* TC is enabled */
1283 numtc++;
1284 }
1285 if (!numtc) {
1286 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1287 numtc = 1;
1288 }
1289 } else {
1290 /* At least TC0 is enabled in case of non-DCB case */
1291 numtc = 1;
1292 }
1293
1294 vsi->tc_config.numtc = numtc;
1295 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1296
1297 /* Setup queue offset/count for all TCs for given VSI */
1298 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1299 /* See if the given TC is enabled for the given VSI */
1300 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1301 int pow, num_qps;
1302
1303 vsi->tc_config.tc_info[i].qoffset = offset;
1304 switch (vsi->type) {
1305 case I40E_VSI_MAIN:
1306 if (i == 0)
1307 qcount = pf->rss_size;
1308 else
1309 qcount = pf->num_tc_qps;
1310 vsi->tc_config.tc_info[i].qcount = qcount;
1311 break;
1312 case I40E_VSI_FDIR:
1313 case I40E_VSI_SRIOV:
1314 case I40E_VSI_VMDQ2:
1315 default:
1316 qcount = vsi->alloc_queue_pairs;
1317 vsi->tc_config.tc_info[i].qcount = qcount;
1318 WARN_ON(i != 0);
1319 break;
1320 }
1321
1322 /* find the power-of-2 of the number of queue pairs */
1323 num_qps = vsi->tc_config.tc_info[i].qcount;
1324 pow = 0;
1325 while (num_qps &&
1326 ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
1327 pow++;
1328 num_qps >>= 1;
1329 }
1330
1331 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1332 qmap =
1333 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1334 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1335
1336 offset += vsi->tc_config.tc_info[i].qcount;
1337 } else {
1338 /* TC is not enabled so set the offset to
1339 * default queue and allocate one queue
1340 * for the given TC.
1341 */
1342 vsi->tc_config.tc_info[i].qoffset = 0;
1343 vsi->tc_config.tc_info[i].qcount = 1;
1344 vsi->tc_config.tc_info[i].netdev_tc = 0;
1345
1346 qmap = 0;
1347 }
1348 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1349 }
1350
1351 /* Set actual Tx/Rx queue pairs */
1352 vsi->num_queue_pairs = offset;
1353
1354 /* Scheduler section valid can only be set for ADD VSI */
1355 if (is_add) {
1356 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1357
1358 ctxt->info.up_enable_bits = enabled_tc;
1359 }
1360 if (vsi->type == I40E_VSI_SRIOV) {
1361 ctxt->info.mapping_flags |=
1362 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1363 for (i = 0; i < vsi->num_queue_pairs; i++)
1364 ctxt->info.queue_mapping[i] =
1365 cpu_to_le16(vsi->base_queue + i);
1366 } else {
1367 ctxt->info.mapping_flags |=
1368 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1369 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1370 }
1371 ctxt->info.valid_sections |= cpu_to_le16(sections);
1372}
1373
1374/**
1375 * i40e_set_rx_mode - NDO callback to set the netdev filters
1376 * @netdev: network interface device structure
1377 **/
1378static void i40e_set_rx_mode(struct net_device *netdev)
1379{
1380 struct i40e_netdev_priv *np = netdev_priv(netdev);
1381 struct i40e_mac_filter *f, *ftmp;
1382 struct i40e_vsi *vsi = np->vsi;
1383 struct netdev_hw_addr *uca;
1384 struct netdev_hw_addr *mca;
1385 struct netdev_hw_addr *ha;
1386
1387 /* add addr if not already in the filter list */
1388 netdev_for_each_uc_addr(uca, netdev) {
1389 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1390 if (i40e_is_vsi_in_vlan(vsi))
1391 i40e_put_mac_in_vlan(vsi, uca->addr,
1392 false, true);
1393 else
1394 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1395 false, true);
1396 }
1397 }
1398
1399 netdev_for_each_mc_addr(mca, netdev) {
1400 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1401 if (i40e_is_vsi_in_vlan(vsi))
1402 i40e_put_mac_in_vlan(vsi, mca->addr,
1403 false, true);
1404 else
1405 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1406 false, true);
1407 }
1408 }
1409
1410 /* remove filter if not in netdev list */
1411 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1412 bool found = false;
1413
1414 if (!f->is_netdev)
1415 continue;
1416
1417 if (is_multicast_ether_addr(f->macaddr)) {
1418 netdev_for_each_mc_addr(mca, netdev) {
1419 if (ether_addr_equal(mca->addr, f->macaddr)) {
1420 found = true;
1421 break;
1422 }
1423 }
1424 } else {
1425 netdev_for_each_uc_addr(uca, netdev) {
1426 if (ether_addr_equal(uca->addr, f->macaddr)) {
1427 found = true;
1428 break;
1429 }
1430 }
1431
1432 for_each_dev_addr(netdev, ha) {
1433 if (ether_addr_equal(ha->addr, f->macaddr)) {
1434 found = true;
1435 break;
1436 }
1437 }
1438 }
1439 if (!found)
1440 i40e_del_filter(
1441 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1442 }
1443
1444 /* check for other flag changes */
1445 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1446 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1447 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1448 }
1449}
1450
1451/**
1452 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1453 * @vsi: ptr to the VSI
1454 *
1455 * Push any outstanding VSI filter changes through the AdminQ.
1456 *
1457 * Returns 0 or error value
1458 **/
1459int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1460{
1461 struct i40e_mac_filter *f, *ftmp;
1462 bool promisc_forced_on = false;
1463 bool add_happened = false;
1464 int filter_list_len = 0;
1465 u32 changed_flags = 0;
dcae29be 1466 i40e_status aq_ret = 0;
41c445ff
JB		 1467 struct i40e_pf *pf;
1468 int num_add = 0;
1469 int num_del = 0;
1470 u16 cmd_flags;
1471
1472 /* empty array typed pointers, kcalloc later */
1473 struct i40e_aqc_add_macvlan_element_data *add_list;
1474 struct i40e_aqc_remove_macvlan_element_data *del_list;
1475
1476 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1477 usleep_range(1000, 2000);
1478 pf = vsi->back;
1479
1480 if (vsi->netdev) {
1481 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1482 vsi->current_netdev_flags = vsi->netdev->flags;
1483 }
1484
1485 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1486 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1487
1488 filter_list_len = pf->hw.aq.asq_buf_size /
1489 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1490 del_list = kcalloc(filter_list_len,
1491 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1492 GFP_KERNEL);
1493 if (!del_list)
1494 return -ENOMEM;
1495
1496 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1497 if (!f->changed)
1498 continue;
1499
1500 if (f->counter != 0)
1501 continue;
1502 f->changed = false;
1503 cmd_flags = 0;
1504
1505 /* add to delete list */
1506 memcpy(del_list[num_del].mac_addr,
1507 f->macaddr, ETH_ALEN);
1508 del_list[num_del].vlan_tag =
1509 cpu_to_le16((u16)(f->vlan ==
1510 I40E_VLAN_ANY ? 0 : f->vlan));
1511
41c445ff
JB		 1512 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1513 del_list[num_del].flags = cmd_flags;
1514 num_del++;
1515
1516 /* unlink from filter list */
1517 list_del(&f->list);
1518 kfree(f);
1519
1520 /* flush a full buffer */
1521 if (num_del == filter_list_len) {
dcae29be 1522 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1523 vsi->seid, del_list, num_del,
1524 NULL);
1525 num_del = 0;
1526 memset(del_list, 0, sizeof(*del_list));
1527
dcae29be 1528 if (aq_ret)
41c445ff
JB		 1529 dev_info(&pf->pdev->dev,
1530 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1531 aq_ret,
41c445ff
JB		 1532 pf->hw.aq.asq_last_status);
1533 }
1534 }
1535 if (num_del) {
dcae29be 1536 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1537 del_list, num_del, NULL);
1538 num_del = 0;
1539
dcae29be 1540 if (aq_ret)
41c445ff
JB		 1541 dev_info(&pf->pdev->dev,
1542 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1543 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1544 }
1545
1546 kfree(del_list);
1547 del_list = NULL;
1548
1549 /* do all the adds now */
1550 filter_list_len = pf->hw.aq.asq_buf_size /
1551 sizeof(struct i40e_aqc_add_macvlan_element_data),
1552 add_list = kcalloc(filter_list_len,
1553 sizeof(struct i40e_aqc_add_macvlan_element_data),
1554 GFP_KERNEL);
1555 if (!add_list)
1556 return -ENOMEM;
1557
1558 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1559 if (!f->changed)
1560 continue;
1561
1562 if (f->counter == 0)
1563 continue;
1564 f->changed = false;
1565 add_happened = true;
1566 cmd_flags = 0;
1567
1568 /* add to add array */
1569 memcpy(add_list[num_add].mac_addr,
1570 f->macaddr, ETH_ALEN);
1571 add_list[num_add].vlan_tag =
1572 cpu_to_le16(
1573 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1574 add_list[num_add].queue_number = 0;
1575
1576 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1577 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1578 num_add++;
1579
1580 /* flush a full buffer */
1581 if (num_add == filter_list_len) {
dcae29be
JB		 1582 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1583 add_list, num_add,
1584 NULL);
41c445ff
JB		 1585 num_add = 0;
1586
dcae29be 1587 if (aq_ret)
41c445ff
JB		 1588 break;
1589 memset(add_list, 0, sizeof(*add_list));
1590 }
1591 }
1592 if (num_add) {
dcae29be
JB		 1593 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1594 add_list, num_add, NULL);
41c445ff
JB		 1595 num_add = 0;
1596 }
1597 kfree(add_list);
1598 add_list = NULL;
1599
dcae29be 1600 if (add_happened && (!aq_ret)) {
41c445ff 1601 /* do nothing */;
dcae29be 1602 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1603 dev_info(&pf->pdev->dev,
1604 "add filter failed, err %d, aq_err %d\n",
dcae29be 1605 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1606 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1607 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1608 &vsi->state)) {
1609 promisc_forced_on = true;
1610 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1611 &vsi->state);
1612 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1613 }
1614 }
1615 }
1616
1617 /* check for changes in promiscuous modes */
1618 if (changed_flags & IFF_ALLMULTI) {
1619 bool cur_multipromisc;
1620 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1621 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1622 vsi->seid,
1623 cur_multipromisc,
1624 NULL);
1625 if (aq_ret)
41c445ff
JB		 1626 dev_info(&pf->pdev->dev,
1627 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1628 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1629 }
1630 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1631 bool cur_promisc;
1632 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1633 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1634 &vsi->state));
dcae29be
JB		 1635 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1636 vsi->seid,
1637 cur_promisc, NULL);
1638 if (aq_ret)
41c445ff
JB		 1639 dev_info(&pf->pdev->dev,
1640 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1641 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1642 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1643 vsi->seid,
1644 cur_promisc, NULL);
1645 if (aq_ret)
1646 dev_info(&pf->pdev->dev,
1647 "set brdcast promisc failed, err %d, aq_err %d\n",
1648 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1649 }
1650
1651 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1652 return 0;
1653}
1654
1655/**
1656 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1657 * @pf: board private structure
1658 **/
1659static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1660{
1661 int v;
1662
1663 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1664 return;
1665 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1666
1667 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1668 if (pf->vsi[v] &&
1669 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1670 i40e_sync_vsi_filters(pf->vsi[v]);
1671 }
1672}
1673
1674/**
1675 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1676 * @netdev: network interface device structure
1677 * @new_mtu: new value for maximum frame size
1678 *
1679 * Returns 0 on success, negative on failure
1680 **/
1681static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1682{
1683 struct i40e_netdev_priv *np = netdev_priv(netdev);
1684 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1685 struct i40e_vsi *vsi = np->vsi;
1686
1687 /* MTU < 68 is an error and causes problems on some kernels */
1688 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1689 return -EINVAL;
1690
1691 netdev_info(netdev, "changing MTU from %d to %d\n",
1692 netdev->mtu, new_mtu);
1693 netdev->mtu = new_mtu;
1694 if (netif_running(netdev))
1695 i40e_vsi_reinit_locked(vsi);
1696
1697 return 0;
1698}
1699
1700/**
1701 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1702 * @vsi: the vsi being adjusted
1703 **/
1704void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1705{
1706 struct i40e_vsi_context ctxt;
1707 i40e_status ret;
1708
1709 if ((vsi->info.valid_sections &
1710 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1711 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1712 return; /* already enabled */
1713
1714 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1715 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1716 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1717
1718 ctxt.seid = vsi->seid;
1719 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1720 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1721 if (ret) {
1722 dev_info(&vsi->back->pdev->dev,
1723 "%s: update vsi failed, aq_err=%d\n",
1724 __func__, vsi->back->hw.aq.asq_last_status);
1725 }
1726}
1727
1728/**
1729 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1730 * @vsi: the vsi being adjusted
1731 **/
1732void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1733{
1734 struct i40e_vsi_context ctxt;
1735 i40e_status ret;
1736
1737 if ((vsi->info.valid_sections &
1738 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1739 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1740 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1741 return; /* already disabled */
1742
1743 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1744 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1745 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1746
1747 ctxt.seid = vsi->seid;
1748 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1749 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1750 if (ret) {
1751 dev_info(&vsi->back->pdev->dev,
1752 "%s: update vsi failed, aq_err=%d\n",
1753 __func__, vsi->back->hw.aq.asq_last_status);
1754 }
1755}
1756
1757/**
1758 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1759 * @netdev: network interface to be adjusted
1760 * @features: netdev features to test if VLAN offload is enabled or not
1761 **/
1762static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1763{
1764 struct i40e_netdev_priv *np = netdev_priv(netdev);
1765 struct i40e_vsi *vsi = np->vsi;
1766
1767 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1768 i40e_vlan_stripping_enable(vsi);
1769 else
1770 i40e_vlan_stripping_disable(vsi);
1771}
1772
1773/**
1774 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1775 * @vsi: the vsi being configured
1776 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1777 **/
1778int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1779{
1780 struct i40e_mac_filter *f, *add_f;
1781 bool is_netdev, is_vf;
41c445ff
JB		 1782
1783 is_vf = (vsi->type == I40E_VSI_SRIOV);
1784 is_netdev = !!(vsi->netdev);
1785
1786 if (is_netdev) {
1787 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1788 is_vf, is_netdev);
1789 if (!add_f) {
1790 dev_info(&vsi->back->pdev->dev,
1791 "Could not add vlan filter %d for %pM\n",
1792 vid, vsi->netdev->dev_addr);
1793 return -ENOMEM;
1794 }
1795 }
1796
1797 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1798 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1799 if (!add_f) {
1800 dev_info(&vsi->back->pdev->dev,
1801 "Could not add vlan filter %d for %pM\n",
1802 vid, f->macaddr);
1803 return -ENOMEM;
1804 }
1805 }
1806
41c445ff
JB		 1807 /* Now if we add a vlan tag, make sure to check if it is the first
1808 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1809 * with 0, so we now accept untagged and specified tagged traffic
1810 * (and not any taged and untagged)
1811 */
1812 if (vid > 0) {
1813 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1814 I40E_VLAN_ANY,
1815 is_vf, is_netdev)) {
1816 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1817 I40E_VLAN_ANY, is_vf, is_netdev);
1818 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1819 is_vf, is_netdev);
1820 if (!add_f) {
1821 dev_info(&vsi->back->pdev->dev,
1822 "Could not add filter 0 for %pM\n",
1823 vsi->netdev->dev_addr);
1824 return -ENOMEM;
1825 }
1826 }
1827
1828 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1829 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1830 is_vf, is_netdev)) {
1831 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1832 is_vf, is_netdev);
1833 add_f = i40e_add_filter(vsi, f->macaddr,
1834 0, is_vf, is_netdev);
1835 if (!add_f) {
1836 dev_info(&vsi->back->pdev->dev,
1837 "Could not add filter 0 for %pM\n",
1838 f->macaddr);
1839 return -ENOMEM;
1840 }
1841 }
1842 }
41c445ff
JB		 1843 }
1844
80f6428f
ASJ		 1845 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1846 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1847 return 0;
1848
1849 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1850}
1851
1852/**
1853 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1854 * @vsi: the vsi being configured
1855 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1856 *
1857 * Return: 0 on success or negative otherwise
41c445ff
JB		 1858 **/
1859int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1860{
1861 struct net_device *netdev = vsi->netdev;
1862 struct i40e_mac_filter *f, *add_f;
1863 bool is_vf, is_netdev;
1864 int filter_count = 0;
41c445ff
JB		 1865
1866 is_vf = (vsi->type == I40E_VSI_SRIOV);
1867 is_netdev = !!(netdev);
1868
1869 if (is_netdev)
1870 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1871
1872 list_for_each_entry(f, &vsi->mac_filter_list, list)
1873 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1874
41c445ff
JB		 1875 /* go through all the filters for this VSI and if there is only
1876 * vid == 0 it means there are no other filters, so vid 0 must
1877 * be replaced with -1. This signifies that we should from now
1878 * on accept any traffic (with any tag present, or untagged)
1879 */
1880 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1881 if (is_netdev) {
1882 if (f->vlan &&
1883 ether_addr_equal(netdev->dev_addr, f->macaddr))
1884 filter_count++;
1885 }
1886
1887 if (f->vlan)
1888 filter_count++;
1889 }
1890
1891 if (!filter_count && is_netdev) {
1892 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1893 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1894 is_vf, is_netdev);
1895 if (!f) {
1896 dev_info(&vsi->back->pdev->dev,
1897 "Could not add filter %d for %pM\n",
1898 I40E_VLAN_ANY, netdev->dev_addr);
1899 return -ENOMEM;
1900 }
1901 }
1902
1903 if (!filter_count) {
1904 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1905 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1906 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1907 is_vf, is_netdev);
1908 if (!add_f) {
1909 dev_info(&vsi->back->pdev->dev,
1910 "Could not add filter %d for %pM\n",
1911 I40E_VLAN_ANY, f->macaddr);
1912 return -ENOMEM;
1913 }
1914 }
1915 }
1916
80f6428f
ASJ		 1917 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1918 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1919 return 0;
1920
41c445ff
JB		 1921 return i40e_sync_vsi_filters(vsi);
1922}
1923
1924/**
1925 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1926 * @netdev: network interface to be adjusted
1927 * @vid: vlan id to be added
078b5876
JB		 1928 *
1929 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1930 **/
1931static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1932 __always_unused __be16 proto, u16 vid)
1933{
1934 struct i40e_netdev_priv *np = netdev_priv(netdev);
1935 struct i40e_vsi *vsi = np->vsi;
078b5876 1936 int ret = 0;
41c445ff
JB		 1937
1938 if (vid > 4095)
078b5876
JB		 1939 return -EINVAL;
1940
1941 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1942
41c445ff
JB		 1943 /* If the network stack called us with vid = 0, we should
1944 * indicate to i40e_vsi_add_vlan() that we want to receive
1945 * any traffic (i.e. with any vlan tag, or untagged)
1946 */
1947 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1948
078b5876
JB		 1949 if (!ret && (vid < VLAN_N_VID))
1950 set_bit(vid, vsi->active_vlans);
41c445ff 1951
078b5876 1952 return ret;
41c445ff
JB		 1953}
1954
1955/**
1956 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1957 * @netdev: network interface to be adjusted
1958 * @vid: vlan id to be removed
078b5876
JB		 1959 *
1960 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1961 **/
1962static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1963 __always_unused __be16 proto, u16 vid)
1964{
1965 struct i40e_netdev_priv *np = netdev_priv(netdev);
1966 struct i40e_vsi *vsi = np->vsi;
1967
078b5876
JB		 1968 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1969
41c445ff
JB		 1970 /* return code is ignored as there is nothing a user
1971 * can do about failure to remove and a log message was
078b5876 1972 * already printed from the other function
41c445ff
JB		 1973 */
1974 i40e_vsi_kill_vlan(vsi, vid);
1975
1976 clear_bit(vid, vsi->active_vlans);
078b5876 1977
41c445ff
JB		 1978 return 0;
1979}
1980
1981/**
1982 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
1983 * @vsi: the vsi being brought back up
1984 **/
1985static void i40e_restore_vlan(struct i40e_vsi *vsi)
1986{
1987 u16 vid;
1988
1989 if (!vsi->netdev)
1990 return;
1991
1992 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
1993
1994 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
1995 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
1996 vid);
1997}
1998
1999/**
2000 * i40e_vsi_add_pvid - Add pvid for the VSI
2001 * @vsi: the vsi being adjusted
2002 * @vid: the vlan id to set as a PVID
2003 **/
dcae29be 2004int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2005{
2006 struct i40e_vsi_context ctxt;
dcae29be 2007 i40e_status aq_ret;
41c445ff
JB		 2008
2009 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2010 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2011 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2012 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2013 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2014
2015 ctxt.seid = vsi->seid;
2016 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2017 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2018 if (aq_ret) {
41c445ff
JB		 2019 dev_info(&vsi->back->pdev->dev,
2020 "%s: update vsi failed, aq_err=%d\n",
2021 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2022 return -ENOENT;
41c445ff
JB		 2023 }
2024
dcae29be 2025 return 0;
41c445ff
JB		 2026}
2027
2028/**
2029 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2030 * @vsi: the vsi being adjusted
2031 *
2032 * Just use the vlan_rx_register() service to put it back to normal
2033 **/
2034void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2035{
6c12fcbf
GR		 2036 i40e_vlan_stripping_disable(vsi);
2037
41c445ff 2038 vsi->info.pvid = 0;
41c445ff
JB		 2039}
2040
2041/**
2042 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2043 * @vsi: ptr to the VSI
2044 *
2045 * If this function returns with an error, then it's possible one or
2046 * more of the rings is populated (while the rest are not). It is the
2047 * callers duty to clean those orphaned rings.
2048 *
2049 * Return 0 on success, negative on failure
2050 **/
2051static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2052{
2053 int i, err = 0;
2054
2055 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2056 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2057
2058 return err;
2059}
2060
2061/**
2062 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2063 * @vsi: ptr to the VSI
2064 *
2065 * Free VSI's transmit software resources
2066 **/
2067static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2068{
2069 int i;
2070
8e9dca53
GR		 2071 if (!vsi->tx_rings)
2072 return;
2073
41c445ff 2074 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2075 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2076 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2077}
2078
2079/**
2080 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2081 * @vsi: ptr to the VSI
2082 *
2083 * If this function returns with an error, then it's possible one or
2084 * more of the rings is populated (while the rest are not). It is the
2085 * callers duty to clean those orphaned rings.
2086 *
2087 * Return 0 on success, negative on failure
2088 **/
2089static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2090{
2091 int i, err = 0;
2092
2093 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2094 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2095 return err;
2096}
2097
2098/**
2099 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2100 * @vsi: ptr to the VSI
2101 *
2102 * Free all receive software resources
2103 **/
2104static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2105{
2106 int i;
2107
8e9dca53
GR		 2108 if (!vsi->rx_rings)
2109 return;
2110
41c445ff 2111 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2112 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2113 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2114}
2115
2116/**
2117 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2118 * @ring: The Tx ring to configure
2119 *
2120 * Configure the Tx descriptor ring in the HMC context.
2121 **/
2122static int i40e_configure_tx_ring(struct i40e_ring *ring)
2123{
2124 struct i40e_vsi *vsi = ring->vsi;
2125 u16 pf_q = vsi->base_queue + ring->queue_index;
2126 struct i40e_hw *hw = &vsi->back->hw;
2127 struct i40e_hmc_obj_txq tx_ctx;
2128 i40e_status err = 0;
2129 u32 qtx_ctl = 0;
2130
2131 /* some ATR related tx ring init */
2132 if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
2133 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2134 ring->atr_count = 0;
2135 } else {
2136 ring->atr_sample_rate = 0;
2137 }
2138
2139 /* initialize XPS */
2140 if (ring->q_vector && ring->netdev &&
2141 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2142 netif_set_xps_queue(ring->netdev,
2143 &ring->q_vector->affinity_mask,
2144 ring->queue_index);
2145
2146 /* clear the context structure first */
2147 memset(&tx_ctx, 0, sizeof(tx_ctx));
2148
2149 tx_ctx.new_context = 1;
2150 tx_ctx.base = (ring->dma / 128);
2151 tx_ctx.qlen = ring->count;
2152 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
2153 I40E_FLAG_FDIR_ATR_ENABLED));
2154
2155 /* As part of VSI creation/update, FW allocates certain
2156 * Tx arbitration queue sets for each TC enabled for
2157 * the VSI. The FW returns the handles to these queue
2158 * sets as part of the response buffer to Add VSI,
2159 * Update VSI, etc. AQ commands. It is expected that
2160 * these queue set handles be associated with the Tx
2161 * queues by the driver as part of the TX queue context
2162 * initialization. This has to be done regardless of
2163 * DCB as by default everything is mapped to TC0.
2164 */
2165 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2166 tx_ctx.rdylist_act = 0;
2167
2168 /* clear the context in the HMC */
2169 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2170 if (err) {
2171 dev_info(&vsi->back->pdev->dev,
2172 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2173 ring->queue_index, pf_q, err);
2174 return -ENOMEM;
2175 }
2176
2177 /* set the context in the HMC */
2178 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2179 if (err) {
2180 dev_info(&vsi->back->pdev->dev,
2181 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2182 ring->queue_index, pf_q, err);
2183 return -ENOMEM;
2184 }
2185
2186 /* Now associate this queue with this PCI function */
2187 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2188 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2189 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2190 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2191 i40e_flush(hw);
2192
2193 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2194
2195 /* cache tail off for easier writes later */
2196 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2197
2198 return 0;
2199}
2200
2201/**
2202 * i40e_configure_rx_ring - Configure a receive ring context
2203 * @ring: The Rx ring to configure
2204 *
2205 * Configure the Rx descriptor ring in the HMC context.
2206 **/
2207static int i40e_configure_rx_ring(struct i40e_ring *ring)
2208{
2209 struct i40e_vsi *vsi = ring->vsi;
2210 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2211 u16 pf_q = vsi->base_queue + ring->queue_index;
2212 struct i40e_hw *hw = &vsi->back->hw;
2213 struct i40e_hmc_obj_rxq rx_ctx;
2214 i40e_status err = 0;
2215
2216 ring->state = 0;
2217
2218 /* clear the context structure first */
2219 memset(&rx_ctx, 0, sizeof(rx_ctx));
2220
2221 ring->rx_buf_len = vsi->rx_buf_len;
2222 ring->rx_hdr_len = vsi->rx_hdr_len;
2223
2224 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2225 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2226
2227 rx_ctx.base = (ring->dma / 128);
2228 rx_ctx.qlen = ring->count;
2229
2230 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2231 set_ring_16byte_desc_enabled(ring);
2232 rx_ctx.dsize = 0;
2233 } else {
2234 rx_ctx.dsize = 1;
2235 }
2236
2237 rx_ctx.dtype = vsi->dtype;
2238 if (vsi->dtype) {
2239 set_ring_ps_enabled(ring);
2240 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2241 I40E_RX_SPLIT_IP |
2242 I40E_RX_SPLIT_TCP_UDP |
2243 I40E_RX_SPLIT_SCTP;
2244 } else {
2245 rx_ctx.hsplit_0 = 0;
2246 }
2247
2248 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2249 (chain_len * ring->rx_buf_len));
2250 rx_ctx.tphrdesc_ena = 1;
2251 rx_ctx.tphwdesc_ena = 1;
2252 rx_ctx.tphdata_ena = 1;
2253 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2254 if (hw->revision_id == 0)
2255 rx_ctx.lrxqthresh = 0;
2256 else
2257 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2258 rx_ctx.crcstrip = 1;
2259 rx_ctx.l2tsel = 1;
2260 rx_ctx.showiv = 1;
2261
2262 /* clear the context in the HMC */
2263 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2264 if (err) {
2265 dev_info(&vsi->back->pdev->dev,
2266 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2267 ring->queue_index, pf_q, err);
2268 return -ENOMEM;
2269 }
2270
2271 /* set the context in the HMC */
2272 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2273 if (err) {
2274 dev_info(&vsi->back->pdev->dev,
2275 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2276 ring->queue_index, pf_q, err);
2277 return -ENOMEM;
2278 }
2279
2280 /* cache tail for quicker writes, and clear the reg before use */
2281 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2282 writel(0, ring->tail);
2283
2284 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2285
2286 return 0;
2287}
2288
2289/**
2290 * i40e_vsi_configure_tx - Configure the VSI for Tx
2291 * @vsi: VSI structure describing this set of rings and resources
2292 *
2293 * Configure the Tx VSI for operation.
2294 **/
2295static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2296{
2297 int err = 0;
2298 u16 i;
2299
9f65e15b
AD		 2300 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2301 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2302
2303 return err;
2304}
2305
2306/**
2307 * i40e_vsi_configure_rx - Configure the VSI for Rx
2308 * @vsi: the VSI being configured
2309 *
2310 * Configure the Rx VSI for operation.
2311 **/
2312static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2313{
2314 int err = 0;
2315 u16 i;
2316
2317 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2318 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2319 + ETH_FCS_LEN + VLAN_HLEN;
2320 else
2321 vsi->max_frame = I40E_RXBUFFER_2048;
2322
2323 /* figure out correct receive buffer length */
2324 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2325 I40E_FLAG_RX_PS_ENABLED)) {
2326 case I40E_FLAG_RX_1BUF_ENABLED:
2327 vsi->rx_hdr_len = 0;
2328 vsi->rx_buf_len = vsi->max_frame;
2329 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2330 break;
2331 case I40E_FLAG_RX_PS_ENABLED:
2332 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2333 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2334 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2335 break;
2336 default:
2337 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2338 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2339 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2340 break;
2341 }
2342
2343 /* round up for the chip's needs */
2344 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2345 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2346 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2347 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2348
2349 /* set up individual rings */
2350 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2351 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2352
2353 return err;
2354}
2355
2356/**
2357 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2358 * @vsi: ptr to the VSI
2359 **/
2360static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2361{
2362 u16 qoffset, qcount;
2363 int i, n;
2364
2365 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2366 return;
2367
2368 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2369 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2370 continue;
2371
2372 qoffset = vsi->tc_config.tc_info[n].qoffset;
2373 qcount = vsi->tc_config.tc_info[n].qcount;
2374 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2375 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2376 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2377 rx_ring->dcb_tc = n;
2378 tx_ring->dcb_tc = n;
2379 }
2380 }
2381}
2382
2383/**
2384 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2385 * @vsi: ptr to the VSI
2386 **/
2387static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2388{
2389 if (vsi->netdev)
2390 i40e_set_rx_mode(vsi->netdev);
2391}
2392
2393/**
2394 * i40e_vsi_configure - Set up the VSI for action
2395 * @vsi: the VSI being configured
2396 **/
2397static int i40e_vsi_configure(struct i40e_vsi *vsi)
2398{
2399 int err;
2400
2401 i40e_set_vsi_rx_mode(vsi);
2402 i40e_restore_vlan(vsi);
2403 i40e_vsi_config_dcb_rings(vsi);
2404 err = i40e_vsi_configure_tx(vsi);
2405 if (!err)
2406 err = i40e_vsi_configure_rx(vsi);
2407
2408 return err;
2409}
2410
2411/**
2412 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2413 * @vsi: the VSI being configured
2414 **/
2415static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2416{
2417 struct i40e_pf *pf = vsi->back;
2418 struct i40e_q_vector *q_vector;
2419 struct i40e_hw *hw = &pf->hw;
2420 u16 vector;
2421 int i, q;
2422 u32 val;
2423 u32 qp;
2424
2425 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2426 * and PFINT_LNKLSTn registers, e.g.:
2427 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2428 */
2429 qp = vsi->base_queue;
2430 vector = vsi->base_vector;
493fb300
AD		 2431 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2432 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2433 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2434 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2435 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2436 q_vector->rx.itr);
2437 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2438 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2439 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2440 q_vector->tx.itr);
2441
2442 /* Linked list for the queuepairs assigned to this vector */
2443 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2444 for (q = 0; q < q_vector->num_ringpairs; q++) {
2445 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2446 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2447 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2448 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2449 (I40E_QUEUE_TYPE_TX
2450 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2451
2452 wr32(hw, I40E_QINT_RQCTL(qp), val);
2453
2454 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2455 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2456 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2457 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2458 (I40E_QUEUE_TYPE_RX
2459 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2460
2461 /* Terminate the linked list */
2462 if (q == (q_vector->num_ringpairs - 1))
2463 val |= (I40E_QUEUE_END_OF_LIST
2464 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2465
2466 wr32(hw, I40E_QINT_TQCTL(qp), val);
2467 qp++;
2468 }
2469 }
2470
2471 i40e_flush(hw);
2472}
2473
2474/**
2475 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2476 * @hw: ptr to the hardware info
2477 **/
2478static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2479{
2480 u32 val;
2481
2482 /* clear things first */
2483 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2484 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2485
2486 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2487 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2488 I40E_PFINT_ICR0_ENA_GRST_MASK |
2489 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2490 I40E_PFINT_ICR0_ENA_GPIO_MASK |
2491 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2492 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2493 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2494 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2495
2496 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2497
2498 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2499 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2500 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2501
2502 /* OTHER_ITR_IDX = 0 */
2503 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2504}
2505
2506/**
2507 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2508 * @vsi: the VSI being configured
2509 **/
2510static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2511{
493fb300 2512 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2513 struct i40e_pf *pf = vsi->back;
2514 struct i40e_hw *hw = &pf->hw;
2515 u32 val;
2516
2517 /* set the ITR configuration */
2518 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2519 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2520 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2521 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2522 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2523 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2524
2525 i40e_enable_misc_int_causes(hw);
2526
2527 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2528 wr32(hw, I40E_PFINT_LNKLST0, 0);
2529
2530 /* Associate the queue pair to the vector and enable the q int */
2531 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2532 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2533 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2534
2535 wr32(hw, I40E_QINT_RQCTL(0), val);
2536
2537 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2538 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2539 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2540
2541 wr32(hw, I40E_QINT_TQCTL(0), val);
2542 i40e_flush(hw);
2543}
2544
2ef28cfb
MW		 2545/**
2546 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2547 * @pf: board private structure
2548 **/
2549void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2550{
2551 struct i40e_hw *hw = &pf->hw;
2552
2553 wr32(hw, I40E_PFINT_DYN_CTL0,
2554 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2555 i40e_flush(hw);
2556}
2557
41c445ff
JB		 2558/**
2559 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2560 * @pf: board private structure
2561 **/
116a57d4 2562void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2563{
2564 struct i40e_hw *hw = &pf->hw;
2565 u32 val;
2566
2567 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2568 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2569 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2570
2571 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2572 i40e_flush(hw);
2573}
2574
2575/**
2576 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2577 * @vsi: pointer to a vsi
2578 * @vector: enable a particular Hw Interrupt vector
2579 **/
2580void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2581{
2582 struct i40e_pf *pf = vsi->back;
2583 struct i40e_hw *hw = &pf->hw;
2584 u32 val;
2585
2586 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2587 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2588 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2589 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2590 /* skip the flush */
41c445ff
JB		 2591}
2592
2593/**
2594 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2595 * @irq: interrupt number
2596 * @data: pointer to a q_vector
2597 **/
2598static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2599{
2600 struct i40e_q_vector *q_vector = data;
2601
cd0b6fa6 2602 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2603 return IRQ_HANDLED;
2604
2605 napi_schedule(&q_vector->napi);
2606
2607 return IRQ_HANDLED;
2608}
2609
2610/**
2611 * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
2612 * @irq: interrupt number
2613 * @data: pointer to a q_vector
2614 **/
2615static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
2616{
2617 struct i40e_q_vector *q_vector = data;
2618
cd0b6fa6 2619 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2620 return IRQ_HANDLED;
2621
2622 pr_info("fdir ring cleaning needed\n");
2623
2624 return IRQ_HANDLED;
2625}
2626
2627/**
2628 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2629 * @vsi: the VSI being configured
2630 * @basename: name for the vector
2631 *
2632 * Allocates MSI-X vectors and requests interrupts from the kernel.
2633 **/
2634static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2635{
2636 int q_vectors = vsi->num_q_vectors;
2637 struct i40e_pf *pf = vsi->back;
2638 int base = vsi->base_vector;
2639 int rx_int_idx = 0;
2640 int tx_int_idx = 0;
2641 int vector, err;
2642
2643 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2644 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2645
cd0b6fa6 2646 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2647 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2648 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2649 tx_int_idx++;
cd0b6fa6 2650 } else if (q_vector->rx.ring) {
41c445ff
JB		 2651 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2652 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2653 } else if (q_vector->tx.ring) {
41c445ff
JB		 2654 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2655 "%s-%s-%d", basename, "tx", tx_int_idx++);
2656 } else {
2657 /* skip this unused q_vector */
2658 continue;
2659 }
2660 err = request_irq(pf->msix_entries[base + vector].vector,
2661 vsi->irq_handler,
2662 0,
2663 q_vector->name,
2664 q_vector);
2665 if (err) {
2666 dev_info(&pf->pdev->dev,
2667 "%s: request_irq failed, error: %d\n",
2668 __func__, err);
2669 goto free_queue_irqs;
2670 }
2671 /* assign the mask for this irq */
2672 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2673 &q_vector->affinity_mask);
2674 }
2675
2676 return 0;
2677
2678free_queue_irqs:
2679 while (vector) {
2680 vector--;
2681 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2682 NULL);
2683 free_irq(pf->msix_entries[base + vector].vector,
2684 &(vsi->q_vectors[vector]));
2685 }
2686 return err;
2687}
2688
2689/**
2690 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2691 * @vsi: the VSI being un-configured
2692 **/
2693static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2694{
2695 struct i40e_pf *pf = vsi->back;
2696 struct i40e_hw *hw = &pf->hw;
2697 int base = vsi->base_vector;
2698 int i;
2699
2700 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2701 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2702 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2703 }
2704
2705 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2706 for (i = vsi->base_vector;
2707 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2708 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2709
2710 i40e_flush(hw);
2711 for (i = 0; i < vsi->num_q_vectors; i++)
2712 synchronize_irq(pf->msix_entries[i + base].vector);
2713 } else {
2714 /* Legacy and MSI mode - this stops all interrupt handling */
2715 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2716 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2717 i40e_flush(hw);
2718 synchronize_irq(pf->pdev->irq);
2719 }
2720}
2721
2722/**
2723 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2724 * @vsi: the VSI being configured
2725 **/
2726static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2727{
2728 struct i40e_pf *pf = vsi->back;
2729 int i;
2730
2731 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2732 for (i = vsi->base_vector;
2733 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2734 i40e_irq_dynamic_enable(vsi, i);
2735 } else {
2736 i40e_irq_dynamic_enable_icr0(pf);
2737 }
2738
1022cb6c 2739 i40e_flush(&pf->hw);
41c445ff
JB		 2740 return 0;
2741}
2742
2743/**
2744 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2745 * @pf: board private structure
2746 **/
2747static void i40e_stop_misc_vector(struct i40e_pf *pf)
2748{
2749 /* Disable ICR 0 */
2750 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2751 i40e_flush(&pf->hw);
2752}
2753
2754/**
2755 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2756 * @irq: interrupt number
2757 * @data: pointer to a q_vector
2758 *
2759 * This is the handler used for all MSI/Legacy interrupts, and deals
2760 * with both queue and non-queue interrupts. This is also used in
2761 * MSIX mode to handle the non-queue interrupts.
2762 **/
2763static irqreturn_t i40e_intr(int irq, void *data)
2764{
2765 struct i40e_pf *pf = (struct i40e_pf *)data;
2766 struct i40e_hw *hw = &pf->hw;
5e823066 2767 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2768 u32 icr0, icr0_remaining;
2769 u32 val, ena_mask;
2770
2771 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2772 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2773
116a57d4
SN		 2774 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2775 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2776 goto enable_intr;
41c445ff 2777
cd92e72f
SN		 2778 /* if interrupt but no bits showing, must be SWINT */
2779 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2780 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2781 pf->sw_int_count++;
2782
41c445ff
JB		 2783 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2784 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2785
2786 /* temporarily disable queue cause for NAPI processing */
2787 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2788 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2789 wr32(hw, I40E_QINT_RQCTL(0), qval);
2790
2791 qval = rd32(hw, I40E_QINT_TQCTL(0));
2792 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2793 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2794
2795 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2796 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2797 }
2798
2799 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2800 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2801 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2802 }
2803
2804 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2805 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2806 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2807 }
2808
2809 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2810 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2811 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2812 }
2813
2814 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2815 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2816 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2817 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2818 val = rd32(hw, I40E_GLGEN_RSTAT);
2819 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2820 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2821 if (val == I40E_RESET_CORER)
41c445ff 2822 pf->corer_count++;
d52cf0a9 2823 else if (val == I40E_RESET_GLOBR)
41c445ff 2824 pf->globr_count++;
d52cf0a9 2825 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2826 pf->empr_count++;
2827 }
2828
9c010ee0
ASJ		 2829 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2830 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2831 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2832 }
2833
41c445ff
JB		 2834 /* If a critical error is pending we have no choice but to reset the
2835 * device.
2836 * Report and mask out any remaining unexpected interrupts.
2837 */
2838 icr0_remaining = icr0 & ena_mask;
2839 if (icr0_remaining) {
2840 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2841 icr0_remaining);
9c010ee0 2842 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2843 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2844 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2845 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2846 dev_info(&pf->pdev->dev, "device will be reset\n");
2847 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2848 i40e_service_event_schedule(pf);
41c445ff
JB		 2849 }
2850 ena_mask &= ~icr0_remaining;
2851 }
5e823066 2852 ret = IRQ_HANDLED;
41c445ff 2853
5e823066 2854enable_intr:
41c445ff
JB		 2855 /* re-enable interrupt causes */
2856 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2857 if (!test_bit(__I40E_DOWN, &pf->state)) {
2858 i40e_service_event_schedule(pf);
2859 i40e_irq_dynamic_enable_icr0(pf);
2860 }
2861
5e823066 2862 return ret;
41c445ff
JB		 2863}
2864
2865/**
cd0b6fa6 2866 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2867 * @vsi: the VSI being configured
2868 * @v_idx: vector index
cd0b6fa6 2869 * @qp_idx: queue pair index
41c445ff 2870 **/
cd0b6fa6 2871static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2872{
493fb300 2873 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2874 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2875 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2876
2877 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2878 tx_ring->next = q_vector->tx.ring;
2879 q_vector->tx.ring = tx_ring;
41c445ff 2880 q_vector->tx.count++;
cd0b6fa6
AD		 2881
2882 rx_ring->q_vector = q_vector;
2883 rx_ring->next = q_vector->rx.ring;
2884 q_vector->rx.ring = rx_ring;
2885 q_vector->rx.count++;
41c445ff
JB		 2886}
2887
2888/**
2889 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
2890 * @vsi: the VSI being configured
2891 *
2892 * This function maps descriptor rings to the queue-specific vectors
2893 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2894 * one vector per queue pair, but on a constrained vector budget, we
2895 * group the queue pairs as "efficiently" as possible.
2896 **/
2897static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
2898{
2899 int qp_remaining = vsi->num_queue_pairs;
2900 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 2901 int num_ringpairs;
41c445ff
JB		 2902 int v_start = 0;
2903 int qp_idx = 0;
2904
2905 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2906 * group them so there are multiple queues per vector.
2907 */
2908 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 2909 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
2910
2911 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
2912
2913 q_vector->num_ringpairs = num_ringpairs;
2914
2915 q_vector->rx.count = 0;
2916 q_vector->tx.count = 0;
2917 q_vector->rx.ring = NULL;
2918 q_vector->tx.ring = NULL;
2919
2920 while (num_ringpairs--) {
2921 map_vector_to_qp(vsi, v_start, qp_idx);
2922 qp_idx++;
2923 qp_remaining--;
41c445ff
JB		 2924 }
2925 }
2926}
2927
2928/**
2929 * i40e_vsi_request_irq - Request IRQ from the OS
2930 * @vsi: the VSI being configured
2931 * @basename: name for the vector
2932 **/
2933static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
2934{
2935 struct i40e_pf *pf = vsi->back;
2936 int err;
2937
2938 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
2939 err = i40e_vsi_request_irq_msix(vsi, basename);
2940 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
2941 err = request_irq(pf->pdev->irq, i40e_intr, 0,
2942 pf->misc_int_name, pf);
2943 else
2944 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
2945 pf->misc_int_name, pf);
2946
2947 if (err)
2948 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
2949
2950 return err;
2951}
2952
2953#ifdef CONFIG_NET_POLL_CONTROLLER
2954/**
2955 * i40e_netpoll - A Polling 'interrupt'handler
2956 * @netdev: network interface device structure
2957 *
2958 * This is used by netconsole to send skbs without having to re-enable
2959 * interrupts. It's not called while the normal interrupt routine is executing.
2960 **/
2961static void i40e_netpoll(struct net_device *netdev)
2962{
2963 struct i40e_netdev_priv *np = netdev_priv(netdev);
2964 struct i40e_vsi *vsi = np->vsi;
2965 struct i40e_pf *pf = vsi->back;
2966 int i;
2967
2968 /* if interface is down do nothing */
2969 if (test_bit(__I40E_DOWN, &vsi->state))
2970 return;
2971
2972 pf->flags |= I40E_FLAG_IN_NETPOLL;
2973 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2974 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 2975 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 2976 } else {
2977 i40e_intr(pf->pdev->irq, netdev);
2978 }
2979 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
2980}
2981#endif
2982
2983/**
2984 * i40e_vsi_control_tx - Start or stop a VSI's rings
2985 * @vsi: the VSI being configured
2986 * @enable: start or stop the rings
2987 **/
2988static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
2989{
2990 struct i40e_pf *pf = vsi->back;
2991 struct i40e_hw *hw = &pf->hw;
2992 int i, j, pf_q;
2993 u32 tx_reg;
2994
2995 pf_q = vsi->base_queue;
2996 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
2997 j = 1000;
2998 do {
2999 usleep_range(1000, 2000);
3000 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3001 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
3002 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
3003
fda972f6
MW		 3004 /* Skip if the queue is already in the requested state */
3005 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3006 continue;
3007 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3008 continue;
41c445ff
JB		 3009
3010 /* turn on/off the queue */
3011 if (enable)
3012 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
3013 I40E_QTX_ENA_QENA_STAT_MASK;
3014 else
3015 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3016
3017 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3018
3019 /* wait for the change to finish */
3020 for (j = 0; j < 10; j++) {
3021 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3022 if (enable) {
3023 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3024 break;
3025 } else {
3026 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3027 break;
3028 }
3029
3030 udelay(10);
3031 }
3032 if (j >= 10) {
3033 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3034 pf_q, (enable ? "en" : "dis"));
3035 return -ETIMEDOUT;
3036 }
3037 }
3038
7134f9ce
JB		 3039 if (hw->revision_id == 0)
3040 mdelay(50);
3041
41c445ff
JB		 3042 return 0;
3043}
3044
3045/**
3046 * i40e_vsi_control_rx - Start or stop a VSI's rings
3047 * @vsi: the VSI being configured
3048 * @enable: start or stop the rings
3049 **/
3050static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3051{
3052 struct i40e_pf *pf = vsi->back;
3053 struct i40e_hw *hw = &pf->hw;
3054 int i, j, pf_q;
3055 u32 rx_reg;
3056
3057 pf_q = vsi->base_queue;
3058 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3059 j = 1000;
3060 do {
3061 usleep_range(1000, 2000);
3062 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3063 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3064 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3065
3066 if (enable) {
3067 /* is STAT set ? */
3068 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3069 continue;
3070 } else {
3071 /* is !STAT set ? */
3072 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3073 continue;
3074 }
3075
3076 /* turn on/off the queue */
3077 if (enable)
3078 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3079 I40E_QRX_ENA_QENA_STAT_MASK;
3080 else
3081 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3082 I40E_QRX_ENA_QENA_STAT_MASK);
3083 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3084
3085 /* wait for the change to finish */
3086 for (j = 0; j < 10; j++) {
3087 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3088
3089 if (enable) {
3090 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3091 break;
3092 } else {
3093 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3094 break;
3095 }
3096
3097 udelay(10);
3098 }
3099 if (j >= 10) {
3100 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3101 pf_q, (enable ? "en" : "dis"));
3102 return -ETIMEDOUT;
3103 }
3104 }
3105
3106 return 0;
3107}
3108
3109/**
3110 * i40e_vsi_control_rings - Start or stop a VSI's rings
3111 * @vsi: the VSI being configured
3112 * @enable: start or stop the rings
3113 **/
fc18eaa0 3114int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff
JB		 3115{
3116 int ret;
3117
3118 /* do rx first for enable and last for disable */
3119 if (request) {
3120 ret = i40e_vsi_control_rx(vsi, request);
3121 if (ret)
3122 return ret;
3123 ret = i40e_vsi_control_tx(vsi, request);
3124 } else {
3125 ret = i40e_vsi_control_tx(vsi, request);
3126 if (ret)
3127 return ret;
3128 ret = i40e_vsi_control_rx(vsi, request);
3129 }
3130
3131 return ret;
3132}
3133
3134/**
3135 * i40e_vsi_free_irq - Free the irq association with the OS
3136 * @vsi: the VSI being configured
3137 **/
3138static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3139{
3140 struct i40e_pf *pf = vsi->back;
3141 struct i40e_hw *hw = &pf->hw;
3142 int base = vsi->base_vector;
3143 u32 val, qp;
3144 int i;
3145
3146 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3147 if (!vsi->q_vectors)
3148 return;
3149
3150 for (i = 0; i < vsi->num_q_vectors; i++) {
3151 u16 vector = i + base;
3152
3153 /* free only the irqs that were actually requested */
78681b1f
SN		 3154 if (!vsi->q_vectors[i] ||
3155 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3156 continue;
3157
3158 /* clear the affinity_mask in the IRQ descriptor */
3159 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3160 NULL);
3161 free_irq(pf->msix_entries[vector].vector,
493fb300 3162 vsi->q_vectors[i]);
41c445ff
JB		 3163
3164 /* Tear down the interrupt queue link list
3165 *
3166 * We know that they come in pairs and always
3167 * the Rx first, then the Tx. To clear the
3168 * link list, stick the EOL value into the
3169 * next_q field of the registers.
3170 */
3171 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3172 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3173 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3174 val |= I40E_QUEUE_END_OF_LIST
3175 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3176 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3177
3178 while (qp != I40E_QUEUE_END_OF_LIST) {
3179 u32 next;
3180
3181 val = rd32(hw, I40E_QINT_RQCTL(qp));
3182
3183 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3184 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3185 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3186 I40E_QINT_RQCTL_INTEVENT_MASK);
3187
3188 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3189 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3190
3191 wr32(hw, I40E_QINT_RQCTL(qp), val);
3192
3193 val = rd32(hw, I40E_QINT_TQCTL(qp));
3194
3195 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3196 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3197
3198 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3199 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3200 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3201 I40E_QINT_TQCTL_INTEVENT_MASK);
3202
3203 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3204 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3205
3206 wr32(hw, I40E_QINT_TQCTL(qp), val);
3207 qp = next;
3208 }
3209 }
3210 } else {
3211 free_irq(pf->pdev->irq, pf);
3212
3213 val = rd32(hw, I40E_PFINT_LNKLST0);
3214 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3215 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3216 val |= I40E_QUEUE_END_OF_LIST
3217 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3218 wr32(hw, I40E_PFINT_LNKLST0, val);
3219
3220 val = rd32(hw, I40E_QINT_RQCTL(qp));
3221 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3222 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3223 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3224 I40E_QINT_RQCTL_INTEVENT_MASK);
3225
3226 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3227 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3228
3229 wr32(hw, I40E_QINT_RQCTL(qp), val);
3230
3231 val = rd32(hw, I40E_QINT_TQCTL(qp));
3232
3233 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3234 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3235 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3236 I40E_QINT_TQCTL_INTEVENT_MASK);
3237
3238 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3239 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3240
3241 wr32(hw, I40E_QINT_TQCTL(qp), val);
3242 }
3243}
3244
493fb300
AD		 3245/**
3246 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3247 * @vsi: the VSI being configured
3248 * @v_idx: Index of vector to be freed
3249 *
3250 * This function frees the memory allocated to the q_vector. In addition if
3251 * NAPI is enabled it will delete any references to the NAPI struct prior
3252 * to freeing the q_vector.
3253 **/
3254static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3255{
3256 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3257 struct i40e_ring *ring;
493fb300
AD		 3258
3259 if (!q_vector)
3260 return;
3261
3262 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3263 i40e_for_each_ring(ring, q_vector->tx)
3264 ring->q_vector = NULL;
3265
3266 i40e_for_each_ring(ring, q_vector->rx)
3267 ring->q_vector = NULL;
493fb300
AD		 3268
3269 /* only VSI w/ an associated netdev is set up w/ NAPI */
3270 if (vsi->netdev)
3271 netif_napi_del(&q_vector->napi);
3272
3273 vsi->q_vectors[v_idx] = NULL;
3274
3275 kfree_rcu(q_vector, rcu);
3276}
3277
41c445ff
JB		 3278/**
3279 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3280 * @vsi: the VSI being un-configured
3281 *
3282 * This frees the memory allocated to the q_vectors and
3283 * deletes references to the NAPI struct.
3284 **/
3285static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3286{
3287 int v_idx;
3288
493fb300
AD		 3289 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3290 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3291}
3292
3293/**
3294 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3295 * @pf: board private structure
3296 **/
3297static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3298{
3299 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3300 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3301 pci_disable_msix(pf->pdev);
3302 kfree(pf->msix_entries);
3303 pf->msix_entries = NULL;
3304 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3305 pci_disable_msi(pf->pdev);
3306 }
3307 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3308}
3309
3310/**
3311 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3312 * @pf: board private structure
3313 *
3314 * We go through and clear interrupt specific resources and reset the structure
3315 * to pre-load conditions
3316 **/
3317static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3318{
3319 int i;
3320
3321 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3322 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3323 if (pf->vsi[i])
3324 i40e_vsi_free_q_vectors(pf->vsi[i]);
3325 i40e_reset_interrupt_capability(pf);
3326}
3327
3328/**
3329 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3330 * @vsi: the VSI being configured
3331 **/
3332static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3333{
3334 int q_idx;
3335
3336 if (!vsi->netdev)
3337 return;
3338
3339 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3340 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3341}
3342
3343/**
3344 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3345 * @vsi: the VSI being configured
3346 **/
3347static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3348{
3349 int q_idx;
3350
3351 if (!vsi->netdev)
3352 return;
3353
3354 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3355 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3356}
3357
3358/**
3359 * i40e_quiesce_vsi - Pause a given VSI
3360 * @vsi: the VSI being paused
3361 **/
3362static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3363{
3364 if (test_bit(__I40E_DOWN, &vsi->state))
3365 return;
3366
3367 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3368 if (vsi->netdev && netif_running(vsi->netdev)) {
3369 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3370 } else {
3371 set_bit(__I40E_DOWN, &vsi->state);
3372 i40e_down(vsi);
3373 }
3374}
3375
3376/**
3377 * i40e_unquiesce_vsi - Resume a given VSI
3378 * @vsi: the VSI being resumed
3379 **/
3380static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3381{
3382 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3383 return;
3384
3385 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3386 if (vsi->netdev && netif_running(vsi->netdev))
3387 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3388 else
3389 i40e_up(vsi); /* this clears the DOWN bit */
3390}
3391
3392/**
3393 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3394 * @pf: the PF
3395 **/
3396static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3397{
3398 int v;
3399
3400 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3401 if (pf->vsi[v])
3402 i40e_quiesce_vsi(pf->vsi[v]);
3403 }
3404}
3405
3406/**
3407 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3408 * @pf: the PF
3409 **/
3410static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3411{
3412 int v;
3413
3414 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3415 if (pf->vsi[v])
3416 i40e_unquiesce_vsi(pf->vsi[v]);
3417 }
3418}
3419
3420/**
3421 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3422 * @dcbcfg: the corresponding DCBx configuration structure
3423 *
3424 * Return the number of TCs from given DCBx configuration
3425 **/
3426static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3427{
078b5876
JB		 3428 u8 num_tc = 0;
3429 int i;
41c445ff
JB		 3430
3431 /* Scan the ETS Config Priority Table to find
3432 * traffic class enabled for a given priority
3433 * and use the traffic class index to get the
3434 * number of traffic classes enabled
3435 */
3436 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3437 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3438 num_tc = dcbcfg->etscfg.prioritytable[i];
3439 }
3440
3441 /* Traffic class index starts from zero so
3442 * increment to return the actual count
3443 */
078b5876 3444 return num_tc + 1;
41c445ff
JB		 3445}
3446
3447/**
3448 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3449 * @dcbcfg: the corresponding DCBx configuration structure
3450 *
3451 * Query the current DCB configuration and return the number of
3452 * traffic classes enabled from the given DCBX config
3453 **/
3454static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3455{
3456 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3457 u8 enabled_tc = 1;
3458 u8 i;
3459
3460 for (i = 0; i < num_tc; i++)
3461 enabled_tc |= 1 << i;
3462
3463 return enabled_tc;
3464}
3465
3466/**
3467 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3468 * @pf: PF being queried
3469 *
3470 * Return number of traffic classes enabled for the given PF
3471 **/
3472static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3473{
3474 struct i40e_hw *hw = &pf->hw;
3475 u8 i, enabled_tc;
3476 u8 num_tc = 0;
3477 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3478
3479 /* If DCB is not enabled then always in single TC */
3480 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3481 return 1;
3482
3483 /* MFP mode return count of enabled TCs for this PF */
3484 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3485 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3486 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3487 if (enabled_tc & (1 << i))
3488 num_tc++;
3489 }
3490 return num_tc;
3491 }
3492
3493 /* SFP mode will be enabled for all TCs on port */
3494 return i40e_dcb_get_num_tc(dcbcfg);
3495}
3496
3497/**
3498 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3499 * @pf: PF being queried
3500 *
3501 * Return a bitmap for first enabled traffic class for this PF.
3502 **/
3503static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3504{
3505 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3506 u8 i = 0;
3507
3508 if (!enabled_tc)
3509 return 0x1; /* TC0 */
3510
3511 /* Find the first enabled TC */
3512 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3513 if (enabled_tc & (1 << i))
3514 break;
3515 }
3516
3517 return 1 << i;
3518}
3519
3520/**
3521 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3522 * @pf: PF being queried
3523 *
3524 * Return a bitmap for enabled traffic classes for this PF.
3525 **/
3526static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3527{
3528 /* If DCB is not enabled for this PF then just return default TC */
3529 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3530 return i40e_pf_get_default_tc(pf);
3531
3532 /* MFP mode will have enabled TCs set by FW */
3533 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3534 return pf->hw.func_caps.enabled_tcmap;
3535
3536 /* SFP mode we want PF to be enabled for all TCs */
3537 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3538}
3539
3540/**
3541 * i40e_vsi_get_bw_info - Query VSI BW Information
3542 * @vsi: the VSI being queried
3543 *
3544 * Returns 0 on success, negative value on failure
3545 **/
3546static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3547{
3548 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3549 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3550 struct i40e_pf *pf = vsi->back;
3551 struct i40e_hw *hw = &pf->hw;
dcae29be 3552 i40e_status aq_ret;
41c445ff 3553 u32 tc_bw_max;
41c445ff
JB		 3554 int i;
3555
3556 /* Get the VSI level BW configuration */
dcae29be
JB		 3557 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3558 if (aq_ret) {
41c445ff
JB		 3559 dev_info(&pf->pdev->dev,
3560 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3561 aq_ret, pf->hw.aq.asq_last_status);
3562 return -EINVAL;
41c445ff
JB		 3563 }
3564
3565 /* Get the VSI level BW configuration per TC */
dcae29be
JB		 3566 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
3567 NULL);
3568 if (aq_ret) {
41c445ff
JB		 3569 dev_info(&pf->pdev->dev,
3570 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3571 aq_ret, pf->hw.aq.asq_last_status);
3572 return -EINVAL;
41c445ff
JB		 3573 }
3574
3575 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3576 dev_info(&pf->pdev->dev,
3577 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3578 bw_config.tc_valid_bits,
3579 bw_ets_config.tc_valid_bits);
3580 /* Still continuing */
3581 }
3582
3583 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3584 vsi->bw_max_quanta = bw_config.max_bw;
3585 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3586 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3587 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3588 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3589 vsi->bw_ets_limit_credits[i] =
3590 le16_to_cpu(bw_ets_config.credits[i]);
3591 /* 3 bits out of 4 for each TC */
3592 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3593 }
078b5876 3594
dcae29be 3595 return 0;
41c445ff
JB		 3596}
3597
3598/**
3599 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3600 * @vsi: the VSI being configured
3601 * @enabled_tc: TC bitmap
3602 * @bw_credits: BW shared credits per TC
3603 *
3604 * Returns 0 on success, negative value on failure
3605 **/
dcae29be 3606static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3607 u8 *bw_share)
3608{
3609 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3610 i40e_status aq_ret;
3611 int i;
41c445ff
JB		 3612
3613 bw_data.tc_valid_bits = enabled_tc;
3614 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3615 bw_data.tc_bw_credits[i] = bw_share[i];
3616
dcae29be
JB		 3617 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3618 NULL);
3619 if (aq_ret) {
41c445ff
JB		 3620 dev_info(&vsi->back->pdev->dev,
3621 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3622 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3623 return -EINVAL;
41c445ff
JB		 3624 }
3625
3626 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3627 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3628
dcae29be 3629 return 0;
41c445ff
JB		 3630}
3631
3632/**
3633 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3634 * @vsi: the VSI being configured
3635 * @enabled_tc: TC map to be enabled
3636 *
3637 **/
3638static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3639{
3640 struct net_device *netdev = vsi->netdev;
3641 struct i40e_pf *pf = vsi->back;
3642 struct i40e_hw *hw = &pf->hw;
3643 u8 netdev_tc = 0;
3644 int i;
3645 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3646
3647 if (!netdev)
3648 return;
3649
3650 if (!enabled_tc) {
3651 netdev_reset_tc(netdev);
3652 return;
3653 }
3654
3655 /* Set up actual enabled TCs on the VSI */
3656 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3657 return;
3658
3659 /* set per TC queues for the VSI */
3660 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3661 /* Only set TC queues for enabled tcs
3662 *
3663 * e.g. For a VSI that has TC0 and TC3 enabled the
3664 * enabled_tc bitmap would be 0x00001001; the driver
3665 * will set the numtc for netdev as 2 that will be
3666 * referenced by the netdev layer as TC 0 and 1.
3667 */
3668 if (vsi->tc_config.enabled_tc & (1 << i))
3669 netdev_set_tc_queue(netdev,
3670 vsi->tc_config.tc_info[i].netdev_tc,
3671 vsi->tc_config.tc_info[i].qcount,
3672 vsi->tc_config.tc_info[i].qoffset);
3673 }
3674
3675 /* Assign UP2TC map for the VSI */
3676 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3677 /* Get the actual TC# for the UP */
3678 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3679 /* Get the mapped netdev TC# for the UP */
3680 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3681 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3682 }
3683}
3684
3685/**
3686 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3687 * @vsi: the VSI being configured
3688 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3689 **/
3690static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3691 struct i40e_vsi_context *ctxt)
3692{
3693 /* copy just the sections touched not the entire info
3694 * since not all sections are valid as returned by
3695 * update vsi params
3696 */
3697 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3698 memcpy(&vsi->info.queue_mapping,
3699 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3700 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3701 sizeof(vsi->info.tc_mapping));
3702}
3703
3704/**
3705 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3706 * @vsi: VSI to be configured
3707 * @enabled_tc: TC bitmap
3708 *
3709 * This configures a particular VSI for TCs that are mapped to the
3710 * given TC bitmap. It uses default bandwidth share for TCs across
3711 * VSIs to configure TC for a particular VSI.
3712 *
3713 * NOTE:
3714 * It is expected that the VSI queues have been quisced before calling
3715 * this function.
3716 **/
3717static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3718{
3719 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3720 struct i40e_vsi_context ctxt;
3721 int ret = 0;
3722 int i;
3723
3724 /* Check if enabled_tc is same as existing or new TCs */
3725 if (vsi->tc_config.enabled_tc == enabled_tc)
3726 return ret;
3727
3728 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3729 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3730 if (enabled_tc & (1 << i))
3731 bw_share[i] = 1;
3732 }
3733
3734 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3735 if (ret) {
3736 dev_info(&vsi->back->pdev->dev,
3737 "Failed configuring TC map %d for VSI %d\n",
3738 enabled_tc, vsi->seid);
3739 goto out;
3740 }
3741
3742 /* Update Queue Pairs Mapping for currently enabled UPs */
3743 ctxt.seid = vsi->seid;
3744 ctxt.pf_num = vsi->back->hw.pf_id;
3745 ctxt.vf_num = 0;
3746 ctxt.uplink_seid = vsi->uplink_seid;
3747 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3748 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3749
3750 /* Update the VSI after updating the VSI queue-mapping information */
3751 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3752 if (ret) {
3753 dev_info(&vsi->back->pdev->dev,
3754 "update vsi failed, aq_err=%d\n",
3755 vsi->back->hw.aq.asq_last_status);
3756 goto out;
3757 }
3758 /* update the local VSI info with updated queue map */
3759 i40e_vsi_update_queue_map(vsi, &ctxt);
3760 vsi->info.valid_sections = 0;
3761
3762 /* Update current VSI BW information */
3763 ret = i40e_vsi_get_bw_info(vsi);
3764 if (ret) {
3765 dev_info(&vsi->back->pdev->dev,
3766 "Failed updating vsi bw info, aq_err=%d\n",
3767 vsi->back->hw.aq.asq_last_status);
3768 goto out;
3769 }
3770
3771 /* Update the netdev TC setup */
3772 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3773out:
3774 return ret;
3775}
3776
3777/**
3778 * i40e_up_complete - Finish the last steps of bringing up a connection
3779 * @vsi: the VSI being configured
3780 **/
3781static int i40e_up_complete(struct i40e_vsi *vsi)
3782{
3783 struct i40e_pf *pf = vsi->back;
3784 int err;
3785
3786 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3787 i40e_vsi_configure_msix(vsi);
3788 else
3789 i40e_configure_msi_and_legacy(vsi);
3790
3791 /* start rings */
3792 err = i40e_vsi_control_rings(vsi, true);
3793 if (err)
3794 return err;
3795
3796 clear_bit(__I40E_DOWN, &vsi->state);
3797 i40e_napi_enable_all(vsi);
3798 i40e_vsi_enable_irq(vsi);
3799
3800 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
3801 (vsi->netdev)) {
6d779b41 3802 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 3803 netif_tx_start_all_queues(vsi->netdev);
3804 netif_carrier_on(vsi->netdev);
6d779b41
AS		 3805 } else if (vsi->netdev) {
3806 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 3807 }
3808 i40e_service_event_schedule(pf);
3809
3810 return 0;
3811}
3812
3813/**
3814 * i40e_vsi_reinit_locked - Reset the VSI
3815 * @vsi: the VSI being configured
3816 *
3817 * Rebuild the ring structs after some configuration
3818 * has changed, e.g. MTU size.
3819 **/
3820static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
3821{
3822 struct i40e_pf *pf = vsi->back;
3823
3824 WARN_ON(in_interrupt());
3825 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
3826 usleep_range(1000, 2000);
3827 i40e_down(vsi);
3828
3829 /* Give a VF some time to respond to the reset. The
3830 * two second wait is based upon the watchdog cycle in
3831 * the VF driver.
3832 */
3833 if (vsi->type == I40E_VSI_SRIOV)
3834 msleep(2000);
3835 i40e_up(vsi);
3836 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
3837}
3838
3839/**
3840 * i40e_up - Bring the connection back up after being down
3841 * @vsi: the VSI being configured
3842 **/
3843int i40e_up(struct i40e_vsi *vsi)
3844{
3845 int err;
3846
3847 err = i40e_vsi_configure(vsi);
3848 if (!err)
3849 err = i40e_up_complete(vsi);
3850
3851 return err;
3852}
3853
3854/**
3855 * i40e_down - Shutdown the connection processing
3856 * @vsi: the VSI being stopped
3857 **/
3858void i40e_down(struct i40e_vsi *vsi)
3859{
3860 int i;
3861
3862 /* It is assumed that the caller of this function
3863 * sets the vsi->state __I40E_DOWN bit.
3864 */
3865 if (vsi->netdev) {
3866 netif_carrier_off(vsi->netdev);
3867 netif_tx_disable(vsi->netdev);
3868 }
3869 i40e_vsi_disable_irq(vsi);
3870 i40e_vsi_control_rings(vsi, false);
3871 i40e_napi_disable_all(vsi);
3872
3873 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3874 i40e_clean_tx_ring(vsi->tx_rings[i]);
3875 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3876 }
3877}
3878
3879/**
3880 * i40e_setup_tc - configure multiple traffic classes
3881 * @netdev: net device to configure
3882 * @tc: number of traffic classes to enable
3883 **/
3884static int i40e_setup_tc(struct net_device *netdev, u8 tc)
3885{
3886 struct i40e_netdev_priv *np = netdev_priv(netdev);
3887 struct i40e_vsi *vsi = np->vsi;
3888 struct i40e_pf *pf = vsi->back;
3889 u8 enabled_tc = 0;
3890 int ret = -EINVAL;
3891 int i;
3892
3893 /* Check if DCB enabled to continue */
3894 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
3895 netdev_info(netdev, "DCB is not enabled for adapter\n");
3896 goto exit;
3897 }
3898
3899 /* Check if MFP enabled */
3900 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3901 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
3902 goto exit;
3903 }
3904
3905 /* Check whether tc count is within enabled limit */
3906 if (tc > i40e_pf_get_num_tc(pf)) {
3907 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
3908 goto exit;
3909 }
3910
3911 /* Generate TC map for number of tc requested */
3912 for (i = 0; i < tc; i++)
3913 enabled_tc |= (1 << i);
3914
3915 /* Requesting same TC configuration as already enabled */
3916 if (enabled_tc == vsi->tc_config.enabled_tc)
3917 return 0;
3918
3919 /* Quiesce VSI queues */
3920 i40e_quiesce_vsi(vsi);
3921
3922 /* Configure VSI for enabled TCs */
3923 ret = i40e_vsi_config_tc(vsi, enabled_tc);
3924 if (ret) {
3925 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
3926 vsi->seid);
3927 goto exit;
3928 }
3929
3930 /* Unquiesce VSI */
3931 i40e_unquiesce_vsi(vsi);
3932
3933exit:
3934 return ret;
3935}
3936
3937/**
3938 * i40e_open - Called when a network interface is made active
3939 * @netdev: network interface device structure
3940 *
3941 * The open entry point is called when a network interface is made
3942 * active by the system (IFF_UP). At this point all resources needed
3943 * for transmit and receive operations are allocated, the interrupt
3944 * handler is registered with the OS, the netdev watchdog subtask is
3945 * enabled, and the stack is notified that the interface is ready.
3946 *
3947 * Returns 0 on success, negative value on failure
3948 **/
3949static int i40e_open(struct net_device *netdev)
3950{
3951 struct i40e_netdev_priv *np = netdev_priv(netdev);
3952 struct i40e_vsi *vsi = np->vsi;
3953 struct i40e_pf *pf = vsi->back;
3954 char int_name[IFNAMSIZ];
3955 int err;
3956
3957 /* disallow open during test */
3958 if (test_bit(__I40E_TESTING, &pf->state))
3959 return -EBUSY;
3960
3961 netif_carrier_off(netdev);
3962
3963 /* allocate descriptors */
3964 err = i40e_vsi_setup_tx_resources(vsi);
3965 if (err)
3966 goto err_setup_tx;
3967 err = i40e_vsi_setup_rx_resources(vsi);
3968 if (err)
3969 goto err_setup_rx;
3970
3971 err = i40e_vsi_configure(vsi);
3972 if (err)
3973 goto err_setup_rx;
3974
3975 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
3976 dev_driver_string(&pf->pdev->dev), netdev->name);
3977 err = i40e_vsi_request_irq(vsi, int_name);
3978 if (err)
3979 goto err_setup_rx;
3980
25946ddb 3981 /* Notify the stack of the actual queue counts. */
d7397644 3982 err = netif_set_real_num_tx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3983 if (err)
3984 goto err_set_queues;
3985
d7397644 3986 err = netif_set_real_num_rx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3987 if (err)
3988 goto err_set_queues;
3989
41c445ff
JB		 3990 err = i40e_up_complete(vsi);
3991 if (err)
3992 goto err_up_complete;
3993
a1c9a9d9
JK		 3994#ifdef CONFIG_I40E_VXLAN
3995 vxlan_get_rx_port(netdev);
3996#endif
41c445ff
JB		 3997
3998 return 0;
3999
4000err_up_complete:
4001 i40e_down(vsi);
25946ddb 4002err_set_queues:
41c445ff
JB		 4003 i40e_vsi_free_irq(vsi);
4004err_setup_rx:
4005 i40e_vsi_free_rx_resources(vsi);
4006err_setup_tx:
4007 i40e_vsi_free_tx_resources(vsi);
4008 if (vsi == pf->vsi[pf->lan_vsi])
4009 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4010
4011 return err;
4012}
4013
4014/**
4015 * i40e_close - Disables a network interface
4016 * @netdev: network interface device structure
4017 *
4018 * The close entry point is called when an interface is de-activated
4019 * by the OS. The hardware is still under the driver's control, but
4020 * this netdev interface is disabled.
4021 *
4022 * Returns 0, this is not allowed to fail
4023 **/
4024static int i40e_close(struct net_device *netdev)
4025{
4026 struct i40e_netdev_priv *np = netdev_priv(netdev);
4027 struct i40e_vsi *vsi = np->vsi;
4028
4029 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4030 return 0;
4031
4032 i40e_down(vsi);
4033 i40e_vsi_free_irq(vsi);
4034
4035 i40e_vsi_free_tx_resources(vsi);
4036 i40e_vsi_free_rx_resources(vsi);
4037
4038 return 0;
4039}
4040
4041/**
4042 * i40e_do_reset - Start a PF or Core Reset sequence
4043 * @pf: board private structure
4044 * @reset_flags: which reset is requested
4045 *
4046 * The essential difference in resets is that the PF Reset
4047 * doesn't clear the packet buffers, doesn't reset the PE
4048 * firmware, and doesn't bother the other PFs on the chip.
4049 **/
4050void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4051{
4052 u32 val;
4053
4054 WARN_ON(in_interrupt());
4055
4056 /* do the biggest reset indicated */
4057 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4058
4059 /* Request a Global Reset
4060 *
4061 * This will start the chip's countdown to the actual full
4062 * chip reset event, and a warning interrupt to be sent
4063 * to all PFs, including the requestor. Our handler
4064 * for the warning interrupt will deal with the shutdown
4065 * and recovery of the switch setup.
4066 */
4067 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4068 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4069 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4070 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4071
4072 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4073
4074 /* Request a Core Reset
4075 *
4076 * Same as Global Reset, except does *not* include the MAC/PHY
4077 */
4078 dev_info(&pf->pdev->dev, "CoreR requested\n");
4079 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4080 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4081 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4082 i40e_flush(&pf->hw);
4083
7823fe34
SN		 4084 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4085
4086 /* Request a Firmware Reset
4087 *
4088 * Same as Global reset, plus restarting the
4089 * embedded firmware engine.
4090 */
4091 /* enable EMP Reset */
4092 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4093 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4094 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4095
4096 /* force the reset */
4097 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4098 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4099 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4100 i40e_flush(&pf->hw);
4101
41c445ff
JB		 4102 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4103
4104 /* Request a PF Reset
4105 *
4106 * Resets only the PF-specific registers
4107 *
4108 * This goes directly to the tear-down and rebuild of
4109 * the switch, since we need to do all the recovery as
4110 * for the Core Reset.
4111 */
4112 dev_info(&pf->pdev->dev, "PFR requested\n");
4113 i40e_handle_reset_warning(pf);
4114
4115 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4116 int v;
4117
4118 /* Find the VSI(s) that requested a re-init */
4119 dev_info(&pf->pdev->dev,
4120 "VSI reinit requested\n");
4121 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4122 struct i40e_vsi *vsi = pf->vsi[v];
4123 if (vsi != NULL &&
4124 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4125 i40e_vsi_reinit_locked(pf->vsi[v]);
4126 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4127 }
4128 }
4129
4130 /* no further action needed, so return now */
4131 return;
4132 } else {
4133 dev_info(&pf->pdev->dev,
4134 "bad reset request 0x%08x\n", reset_flags);
4135 return;
4136 }
4137}
4138
23326186
ASJ		 4139/**
4140 * i40e_do_reset_safe - Protected reset path for userland calls.
4141 * @pf: board private structure
4142 * @reset_flags: which reset is requested
4143 *
4144 **/
4145void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4146{
4147 rtnl_lock();
4148 i40e_do_reset(pf, reset_flags);
4149 rtnl_unlock();
4150}
4151
41c445ff
JB		 4152/**
4153 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4154 * @pf: board private structure
4155 * @e: event info posted on ARQ
4156 *
4157 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4158 * and VF queues
4159 **/
4160static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4161 struct i40e_arq_event_info *e)
4162{
4163 struct i40e_aqc_lan_overflow *data =
4164 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4165 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4166 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4167 struct i40e_hw *hw = &pf->hw;
4168 struct i40e_vf *vf;
4169 u16 vf_id;
4170
4171 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4172 __func__, queue, qtx_ctl);
4173
4174 /* Queue belongs to VF, find the VF and issue VF reset */
4175 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4176 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4177 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4178 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4179 vf_id -= hw->func_caps.vf_base_id;
4180 vf = &pf->vf[vf_id];
4181 i40e_vc_notify_vf_reset(vf);
4182 /* Allow VF to process pending reset notification */
4183 msleep(20);
4184 i40e_reset_vf(vf, false);
4185 }
4186}
4187
4188/**
4189 * i40e_service_event_complete - Finish up the service event
4190 * @pf: board private structure
4191 **/
4192static void i40e_service_event_complete(struct i40e_pf *pf)
4193{
4194 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4195
4196 /* flush memory to make sure state is correct before next watchog */
4197 smp_mb__before_clear_bit();
4198 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4199}
4200
4201/**
4202 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4203 * @pf: board private structure
4204 **/
4205static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4206{
4207 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4208 return;
4209
4210 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4211
4212 /* if interface is down do nothing */
4213 if (test_bit(__I40E_DOWN, &pf->state))
4214 return;
4215}
4216
4217/**
4218 * i40e_vsi_link_event - notify VSI of a link event
4219 * @vsi: vsi to be notified
4220 * @link_up: link up or down
4221 **/
4222static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4223{
4224 if (!vsi)
4225 return;
4226
4227 switch (vsi->type) {
4228 case I40E_VSI_MAIN:
4229 if (!vsi->netdev || !vsi->netdev_registered)
4230 break;
4231
4232 if (link_up) {
4233 netif_carrier_on(vsi->netdev);
4234 netif_tx_wake_all_queues(vsi->netdev);
4235 } else {
4236 netif_carrier_off(vsi->netdev);
4237 netif_tx_stop_all_queues(vsi->netdev);
4238 }
4239 break;
4240
4241 case I40E_VSI_SRIOV:
4242 break;
4243
4244 case I40E_VSI_VMDQ2:
4245 case I40E_VSI_CTRL:
4246 case I40E_VSI_MIRROR:
4247 default:
4248 /* there is no notification for other VSIs */
4249 break;
4250 }
4251}
4252
4253/**
4254 * i40e_veb_link_event - notify elements on the veb of a link event
4255 * @veb: veb to be notified
4256 * @link_up: link up or down
4257 **/
4258static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4259{
4260 struct i40e_pf *pf;
4261 int i;
4262
4263 if (!veb || !veb->pf)
4264 return;
4265 pf = veb->pf;
4266
4267 /* depth first... */
4268 for (i = 0; i < I40E_MAX_VEB; i++)
4269 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4270 i40e_veb_link_event(pf->veb[i], link_up);
4271
4272 /* ... now the local VSIs */
4273 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4274 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4275 i40e_vsi_link_event(pf->vsi[i], link_up);
4276}
4277
4278/**
4279 * i40e_link_event - Update netif_carrier status
4280 * @pf: board private structure
4281 **/
4282static void i40e_link_event(struct i40e_pf *pf)
4283{
4284 bool new_link, old_link;
4285
4286 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4287 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4288
4289 if (new_link == old_link)
4290 return;
4291
6d779b41
AS		 4292 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4293 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4294 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4295
4296 /* Notify the base of the switch tree connected to
4297 * the link. Floating VEBs are not notified.
4298 */
4299 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4300 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4301 else
4302 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4303
4304 if (pf->vf)
4305 i40e_vc_notify_link_state(pf);
4306}
4307
4308/**
4309 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4310 * @pf: board private structure
4311 *
4312 * Set the per-queue flags to request a check for stuck queues in the irq
4313 * clean functions, then force interrupts to be sure the irq clean is called.
4314 **/
4315static void i40e_check_hang_subtask(struct i40e_pf *pf)
4316{
4317 int i, v;
4318
4319 /* If we're down or resetting, just bail */
4320 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4321 return;
4322
4323 /* for each VSI/netdev
4324 * for each Tx queue
4325 * set the check flag
4326 * for each q_vector
4327 * force an interrupt
4328 */
4329 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4330 struct i40e_vsi *vsi = pf->vsi[v];
4331 int armed = 0;
4332
4333 if (!pf->vsi[v] ||
4334 test_bit(__I40E_DOWN, &vsi->state) ||
4335 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4336 continue;
4337
4338 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4339 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4340 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4341 &vsi->tx_rings[i]->state))
41c445ff
JB		 4342 armed++;
4343 }
4344
4345 if (armed) {
4346 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4347 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4348 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4349 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4350 } else {
4351 u16 vec = vsi->base_vector - 1;
4352 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4353 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4354 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4355 wr32(&vsi->back->hw,
4356 I40E_PFINT_DYN_CTLN(vec), val);
4357 }
4358 i40e_flush(&vsi->back->hw);
4359 }
4360 }
4361}
4362
4363/**
4364 * i40e_watchdog_subtask - Check and bring link up
4365 * @pf: board private structure
4366 **/
4367static void i40e_watchdog_subtask(struct i40e_pf *pf)
4368{
4369 int i;
4370
4371 /* if interface is down do nothing */
4372 if (test_bit(__I40E_DOWN, &pf->state) ||
4373 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4374 return;
4375
4376 /* Update the stats for active netdevs so the network stack
4377 * can look at updated numbers whenever it cares to
4378 */
4379 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4380 if (pf->vsi[i] && pf->vsi[i]->netdev)
4381 i40e_update_stats(pf->vsi[i]);
4382
4383 /* Update the stats for the active switching components */
4384 for (i = 0; i < I40E_MAX_VEB; i++)
4385 if (pf->veb[i])
4386 i40e_update_veb_stats(pf->veb[i]);
4387}
4388
4389/**
4390 * i40e_reset_subtask - Set up for resetting the device and driver
4391 * @pf: board private structure
4392 **/
4393static void i40e_reset_subtask(struct i40e_pf *pf)
4394{
4395 u32 reset_flags = 0;
4396
23326186 4397 rtnl_lock();
41c445ff
JB		 4398 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4399 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4400 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4401 }
4402 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4403 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4404 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4405 }
4406 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4407 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4408 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4409 }
4410 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4411 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4412 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4413 }
4414
4415 /* If there's a recovery already waiting, it takes
4416 * precedence before starting a new reset sequence.
4417 */
4418 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4419 i40e_handle_reset_warning(pf);
23326186 4420 goto unlock;
41c445ff
JB		 4421 }
4422
4423 /* If we're already down or resetting, just bail */
4424 if (reset_flags &&
4425 !test_bit(__I40E_DOWN, &pf->state) &&
4426 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4427 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4428
4429unlock:
4430 rtnl_unlock();
41c445ff
JB		 4431}
4432
4433/**
4434 * i40e_handle_link_event - Handle link event
4435 * @pf: board private structure
4436 * @e: event info posted on ARQ
4437 **/
4438static void i40e_handle_link_event(struct i40e_pf *pf,
4439 struct i40e_arq_event_info *e)
4440{
4441 struct i40e_hw *hw = &pf->hw;
4442 struct i40e_aqc_get_link_status *status =
4443 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4444 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4445
4446 /* save off old link status information */
4447 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4448 sizeof(pf->hw.phy.link_info_old));
4449
4450 /* update link status */
4451 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4452 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4453 hw_link_info->link_info = status->link_info;
4454 hw_link_info->an_info = status->an_info;
4455 hw_link_info->ext_info = status->ext_info;
4456 hw_link_info->lse_enable =
4457 le16_to_cpu(status->command_flags) &
4458 I40E_AQ_LSE_ENABLE;
4459
4460 /* process the event */
4461 i40e_link_event(pf);
4462
4463 /* Do a new status request to re-enable LSE reporting
4464 * and load new status information into the hw struct,
4465 * then see if the status changed while processing the
4466 * initial event.
4467 */
4468 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4469 i40e_link_event(pf);
4470}
4471
4472/**
4473 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4474 * @pf: board private structure
4475 **/
4476static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4477{
4478 struct i40e_arq_event_info event;
4479 struct i40e_hw *hw = &pf->hw;
4480 u16 pending, i = 0;
4481 i40e_status ret;
4482 u16 opcode;
4483 u32 val;
4484
4485 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4486 return;
4487
3197ce22 4488 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 4489 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4490 if (!event.msg_buf)
4491 return;
4492
4493 do {
2f019123 4494 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 4495 ret = i40e_clean_arq_element(hw, &event, &pending);
4496 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4497 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4498 break;
4499 } else if (ret) {
4500 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4501 break;
4502 }
4503
4504 opcode = le16_to_cpu(event.desc.opcode);
4505 switch (opcode) {
4506
4507 case i40e_aqc_opc_get_link_status:
4508 i40e_handle_link_event(pf, &event);
4509 break;
4510 case i40e_aqc_opc_send_msg_to_pf:
4511 ret = i40e_vc_process_vf_msg(pf,
4512 le16_to_cpu(event.desc.retval),
4513 le32_to_cpu(event.desc.cookie_high),
4514 le32_to_cpu(event.desc.cookie_low),
4515 event.msg_buf,
4516 event.msg_size);
4517 break;
4518 case i40e_aqc_opc_lldp_update_mib:
4519 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4520 break;
4521 case i40e_aqc_opc_event_lan_overflow:
4522 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4523 i40e_handle_lan_overflow_event(pf, &event);
4524 break;
0467bc91
SN		 4525 case i40e_aqc_opc_send_msg_to_peer:
4526 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
4527 break;
41c445ff
JB		 4528 default:
4529 dev_info(&pf->pdev->dev,
0467bc91
SN		 4530 "ARQ Error: Unknown event 0x%04x received\n",
4531 opcode);
41c445ff
JB		 4532 break;
4533 }
4534 } while (pending && (i++ < pf->adminq_work_limit));
4535
4536 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4537 /* re-enable Admin queue interrupt cause */
4538 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4539 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4540 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4541 i40e_flush(hw);
4542
4543 kfree(event.msg_buf);
4544}
4545
4546/**
4547 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4548 * @veb: pointer to the VEB instance
4549 *
4550 * This is a recursive function that first builds the attached VSIs then
4551 * recurses in to build the next layer of VEB. We track the connections
4552 * through our own index numbers because the seid's from the HW could
4553 * change across the reset.
4554 **/
4555static int i40e_reconstitute_veb(struct i40e_veb *veb)
4556{
4557 struct i40e_vsi *ctl_vsi = NULL;
4558 struct i40e_pf *pf = veb->pf;
4559 int v, veb_idx;
4560 int ret;
4561
4562 /* build VSI that owns this VEB, temporarily attached to base VEB */
4563 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4564 if (pf->vsi[v] &&
4565 pf->vsi[v]->veb_idx == veb->idx &&
4566 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4567 ctl_vsi = pf->vsi[v];
4568 break;
4569 }
4570 }
4571 if (!ctl_vsi) {
4572 dev_info(&pf->pdev->dev,
4573 "missing owner VSI for veb_idx %d\n", veb->idx);
4574 ret = -ENOENT;
4575 goto end_reconstitute;
4576 }
4577 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4578 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4579 ret = i40e_add_vsi(ctl_vsi);
4580 if (ret) {
4581 dev_info(&pf->pdev->dev,
4582 "rebuild of owner VSI failed: %d\n", ret);
4583 goto end_reconstitute;
4584 }
4585 i40e_vsi_reset_stats(ctl_vsi);
4586
4587 /* create the VEB in the switch and move the VSI onto the VEB */
4588 ret = i40e_add_veb(veb, ctl_vsi);
4589 if (ret)
4590 goto end_reconstitute;
4591
4592 /* create the remaining VSIs attached to this VEB */
4593 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4594 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4595 continue;
4596
4597 if (pf->vsi[v]->veb_idx == veb->idx) {
4598 struct i40e_vsi *vsi = pf->vsi[v];
4599 vsi->uplink_seid = veb->seid;
4600 ret = i40e_add_vsi(vsi);
4601 if (ret) {
4602 dev_info(&pf->pdev->dev,
4603 "rebuild of vsi_idx %d failed: %d\n",
4604 v, ret);
4605 goto end_reconstitute;
4606 }
4607 i40e_vsi_reset_stats(vsi);
4608 }
4609 }
4610
4611 /* create any VEBs attached to this VEB - RECURSION */
4612 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
4613 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
4614 pf->veb[veb_idx]->uplink_seid = veb->seid;
4615 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
4616 if (ret)
4617 break;
4618 }
4619 }
4620
4621end_reconstitute:
4622 return ret;
4623}
4624
4625/**
4626 * i40e_get_capabilities - get info about the HW
4627 * @pf: the PF struct
4628 **/
4629static int i40e_get_capabilities(struct i40e_pf *pf)
4630{
4631 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
4632 u16 data_size;
4633 int buf_len;
4634 int err;
4635
4636 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
4637 do {
4638 cap_buf = kzalloc(buf_len, GFP_KERNEL);
4639 if (!cap_buf)
4640 return -ENOMEM;
4641
4642 /* this loads the data into the hw struct for us */
4643 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
4644 &data_size,
4645 i40e_aqc_opc_list_func_capabilities,
4646 NULL);
4647 /* data loaded, buffer no longer needed */
4648 kfree(cap_buf);
4649
4650 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
4651 /* retry with a larger buffer */
4652 buf_len = data_size;
4653 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
4654 dev_info(&pf->pdev->dev,
4655 "capability discovery failed: aq=%d\n",
4656 pf->hw.aq.asq_last_status);
4657 return -ENODEV;
4658 }
4659 } while (err);
4660
7134f9ce
JB		 4661 if (pf->hw.revision_id == 0 && pf->hw.func_caps.npar_enable) {
4662 pf->hw.func_caps.num_msix_vectors += 1;
4663 pf->hw.func_caps.num_tx_qp =
4664 min_t(int, pf->hw.func_caps.num_tx_qp,
4665 I40E_MAX_NPAR_QPS);
4666 }
4667
41c445ff
JB		 4668 if (pf->hw.debug_mask & I40E_DEBUG_USER)
4669 dev_info(&pf->pdev->dev,
4670 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
4671 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
4672 pf->hw.func_caps.num_msix_vectors,
4673 pf->hw.func_caps.num_msix_vectors_vf,
4674 pf->hw.func_caps.fd_filters_guaranteed,
4675 pf->hw.func_caps.fd_filters_best_effort,
4676 pf->hw.func_caps.num_tx_qp,
4677 pf->hw.func_caps.num_vsis);
4678
7134f9ce
JB		 4679#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
4680 + pf->hw.func_caps.num_vfs)
4681 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
4682 dev_info(&pf->pdev->dev,
4683 "got num_vsis %d, setting num_vsis to %d\n",
4684 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
4685 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
4686 }
4687
41c445ff
JB		 4688 return 0;
4689}
4690
4691/**
4692 * i40e_fdir_setup - initialize the Flow Director resources
4693 * @pf: board private structure
4694 **/
4695static void i40e_fdir_setup(struct i40e_pf *pf)
4696{
4697 struct i40e_vsi *vsi;
4698 bool new_vsi = false;
4699 int err, i;
4700
958a3e3b
SN		 4701 if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED |
4702 I40E_FLAG_FDIR_ATR_ENABLED)))
41c445ff
JB		 4703 return;
4704
4705 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
4706
4707 /* find existing or make new FDIR VSI */
4708 vsi = NULL;
4709 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4710 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
4711 vsi = pf->vsi[i];
4712 if (!vsi) {
4713 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
4714 if (!vsi) {
4715 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
4716 pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
4717 return;
4718 }
4719 new_vsi = true;
4720 }
4721 WARN_ON(vsi->base_queue != I40E_FDIR_RING);
4722 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
4723
4724 err = i40e_vsi_setup_tx_resources(vsi);
4725 if (!err)
4726 err = i40e_vsi_setup_rx_resources(vsi);
4727 if (!err)
4728 err = i40e_vsi_configure(vsi);
4729 if (!err && new_vsi) {
4730 char int_name[IFNAMSIZ + 9];
4731 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4732 dev_driver_string(&pf->pdev->dev));
4733 err = i40e_vsi_request_irq(vsi, int_name);
4734 }
4735 if (!err)
4736 err = i40e_up_complete(vsi);
4737
4738 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4739}
4740
4741/**
4742 * i40e_fdir_teardown - release the Flow Director resources
4743 * @pf: board private structure
4744 **/
4745static void i40e_fdir_teardown(struct i40e_pf *pf)
4746{
4747 int i;
4748
4749 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
4750 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
4751 i40e_vsi_release(pf->vsi[i]);
4752 break;
4753 }
4754 }
4755}
4756
4757/**
f650a38b 4758 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 4759 * @pf: board private structure
4760 *
f650a38b
ASJ		 4761 * Close up the VFs and other things in prep for pf Reset.
4762 **/
4763static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 4764{
41c445ff
JB		 4765 struct i40e_hw *hw = &pf->hw;
4766 i40e_status ret;
4767 u32 v;
4768
4769 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
4770 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 4771 return 0;
41c445ff
JB		 4772
4773 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
4774
37f0be6d
ASJ		 4775 if (i40e_check_asq_alive(hw))
4776 i40e_vc_notify_reset(pf);
41c445ff
JB		 4777
4778 /* quiesce the VSIs and their queues that are not already DOWN */
4779 i40e_pf_quiesce_all_vsi(pf);
4780
4781 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4782 if (pf->vsi[v])
4783 pf->vsi[v]->seid = 0;
4784 }
4785
4786 i40e_shutdown_adminq(&pf->hw);
4787
f650a38b
ASJ		 4788 /* call shutdown HMC */
4789 ret = i40e_shutdown_lan_hmc(hw);
4790 if (ret) {
4791 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
4792 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4793 }
4794 return ret;
4795}
4796
4797/**
4798 * i40e_reset_and_rebuild - reset and rebuid using a saved config
4799 * @pf: board private structure
bc7d338f 4800 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 4801 **/
bc7d338f 4802static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 4803{
4804 struct i40e_driver_version dv;
4805 struct i40e_hw *hw = &pf->hw;
4806 i40e_status ret;
4807 u32 v;
4808
41c445ff
JB		 4809 /* Now we wait for GRST to settle out.
4810 * We don't have to delete the VEBs or VSIs from the hw switch
4811 * because the reset will make them disappear.
4812 */
4813 ret = i40e_pf_reset(hw);
4814 if (ret)
4815 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
4816 pf->pfr_count++;
4817
4818 if (test_bit(__I40E_DOWN, &pf->state))
4819 goto end_core_reset;
4820 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
4821
4822 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
4823 ret = i40e_init_adminq(&pf->hw);
4824 if (ret) {
4825 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
4826 goto end_core_reset;
4827 }
4828
4829 ret = i40e_get_capabilities(pf);
4830 if (ret) {
4831 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
4832 ret);
4833 goto end_core_reset;
4834 }
4835
41c445ff
JB		 4836 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
4837 hw->func_caps.num_rx_qp,
4838 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
4839 if (ret) {
4840 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
4841 goto end_core_reset;
4842 }
4843 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
4844 if (ret) {
4845 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
4846 goto end_core_reset;
4847 }
4848
4849 /* do basic switch setup */
bc7d338f 4850 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 4851 if (ret)
4852 goto end_core_reset;
4853
4854 /* Rebuild the VSIs and VEBs that existed before reset.
4855 * They are still in our local switch element arrays, so only
4856 * need to rebuild the switch model in the HW.
4857 *
4858 * If there were VEBs but the reconstitution failed, we'll try
4859 * try to recover minimal use by getting the basic PF VSI working.
4860 */
4861 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
4862 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
4863 /* find the one VEB connected to the MAC, and find orphans */
4864 for (v = 0; v < I40E_MAX_VEB; v++) {
4865 if (!pf->veb[v])
4866 continue;
4867
4868 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
4869 pf->veb[v]->uplink_seid == 0) {
4870 ret = i40e_reconstitute_veb(pf->veb[v]);
4871
4872 if (!ret)
4873 continue;
4874
4875 /* If Main VEB failed, we're in deep doodoo,
4876 * so give up rebuilding the switch and set up
4877 * for minimal rebuild of PF VSI.
4878 * If orphan failed, we'll report the error
4879 * but try to keep going.
4880 */
4881 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
4882 dev_info(&pf->pdev->dev,
4883 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
4884 ret);
4885 pf->vsi[pf->lan_vsi]->uplink_seid
4886 = pf->mac_seid;
4887 break;
4888 } else if (pf->veb[v]->uplink_seid == 0) {
4889 dev_info(&pf->pdev->dev,
4890 "rebuild of orphan VEB failed: %d\n",
4891 ret);
4892 }
4893 }
4894 }
4895 }
4896
4897 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
4898 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
4899 /* no VEB, so rebuild only the Main VSI */
4900 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
4901 if (ret) {
4902 dev_info(&pf->pdev->dev,
4903 "rebuild of Main VSI failed: %d\n", ret);
4904 goto end_core_reset;
4905 }
4906 }
4907
4908 /* reinit the misc interrupt */
4909 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4910 ret = i40e_setup_misc_vector(pf);
4911
4912 /* restart the VSIs that were rebuilt and running before the reset */
4913 i40e_pf_unquiesce_all_vsi(pf);
4914
4915 /* tell the firmware that we're starting */
4916 dv.major_version = DRV_VERSION_MAJOR;
4917 dv.minor_version = DRV_VERSION_MINOR;
4918 dv.build_version = DRV_VERSION_BUILD;
4919 dv.subbuild_version = 0;
4920 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
4921
4922 dev_info(&pf->pdev->dev, "PF reset done\n");
4923
4924end_core_reset:
4925 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4926}
4927
f650a38b
ASJ		 4928/**
4929 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
4930 * @pf: board private structure
4931 *
4932 * Close up the VFs and other things in prep for a Core Reset,
4933 * then get ready to rebuild the world.
4934 **/
4935static void i40e_handle_reset_warning(struct i40e_pf *pf)
4936{
4937 i40e_status ret;
4938
4939 ret = i40e_prep_for_reset(pf);
4940 if (!ret)
bc7d338f 4941 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 4942}
4943
41c445ff
JB		 4944/**
4945 * i40e_handle_mdd_event
4946 * @pf: pointer to the pf structure
4947 *
4948 * Called from the MDD irq handler to identify possibly malicious vfs
4949 **/
4950static void i40e_handle_mdd_event(struct i40e_pf *pf)
4951{
4952 struct i40e_hw *hw = &pf->hw;
4953 bool mdd_detected = false;
4954 struct i40e_vf *vf;
4955 u32 reg;
4956 int i;
4957
4958 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
4959 return;
4960
4961 /* find what triggered the MDD event */
4962 reg = rd32(hw, I40E_GL_MDET_TX);
4963 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4964 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
4965 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
4966 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
4967 >> I40E_GL_MDET_TX_EVENT_SHIFT;
4968 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
4969 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
4970 dev_info(&pf->pdev->dev,
4971 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
4972 event, queue, func);
4973 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
4974 mdd_detected = true;
4975 }
4976 reg = rd32(hw, I40E_GL_MDET_RX);
4977 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4978 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
4979 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
4980 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
4981 >> I40E_GL_MDET_RX_EVENT_SHIFT;
4982 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
4983 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
4984 dev_info(&pf->pdev->dev,
4985 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
4986 event, queue, func);
4987 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
4988 mdd_detected = true;
4989 }
4990
4991 /* see if one of the VFs needs its hand slapped */
4992 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
4993 vf = &(pf->vf[i]);
4994 reg = rd32(hw, I40E_VP_MDET_TX(i));
4995 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
4996 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
4997 vf->num_mdd_events++;
4998 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
4999 }
5000
5001 reg = rd32(hw, I40E_VP_MDET_RX(i));
5002 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5003 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5004 vf->num_mdd_events++;
5005 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5006 }
5007
5008 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5009 dev_info(&pf->pdev->dev,
5010 "Too many MDD events on VF %d, disabled\n", i);
5011 dev_info(&pf->pdev->dev,
5012 "Use PF Control I/F to re-enable the VF\n");
5013 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5014 }
5015 }
5016
5017 /* re-enable mdd interrupt cause */
5018 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5019 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5020 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5021 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5022 i40e_flush(hw);
5023}
5024
a1c9a9d9
JK		 5025#ifdef CONFIG_I40E_VXLAN
5026/**
5027 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5028 * @pf: board private structure
5029 **/
5030static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5031{
5032 const int vxlan_hdr_qwords = 4;
5033 struct i40e_hw *hw = &pf->hw;
5034 i40e_status ret;
5035 u8 filter_index;
5036 __be16 port;
5037 int i;
5038
5039 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5040 return;
5041
5042 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5043
5044 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5045 if (pf->pending_vxlan_bitmap & (1 << i)) {
5046 pf->pending_vxlan_bitmap &= ~(1 << i);
5047 port = pf->vxlan_ports[i];
5048 ret = port ?
5049 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5050 vxlan_hdr_qwords,
5051 I40E_AQC_TUNNEL_TYPE_VXLAN,
5052 &filter_index, NULL)
5053 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5054
5055 if (ret) {
5056 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5057 port ? "adding" : "deleting",
5058 ntohs(port), port ? i : i);
5059
5060 pf->vxlan_ports[i] = 0;
5061 } else {
5062 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5063 port ? "Added" : "Deleted",
5064 ntohs(port), port ? i : filter_index);
5065 }
5066 }
5067 }
5068}
5069
5070#endif
41c445ff
JB		 5071/**
5072 * i40e_service_task - Run the driver's async subtasks
5073 * @work: pointer to work_struct containing our data
5074 **/
5075static void i40e_service_task(struct work_struct *work)
5076{
5077 struct i40e_pf *pf = container_of(work,
5078 struct i40e_pf,
5079 service_task);
5080 unsigned long start_time = jiffies;
5081
5082 i40e_reset_subtask(pf);
5083 i40e_handle_mdd_event(pf);
5084 i40e_vc_process_vflr_event(pf);
5085 i40e_watchdog_subtask(pf);
5086 i40e_fdir_reinit_subtask(pf);
5087 i40e_check_hang_subtask(pf);
5088 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5089#ifdef CONFIG_I40E_VXLAN
5090 i40e_sync_vxlan_filters_subtask(pf);
5091#endif
41c445ff
JB		 5092 i40e_clean_adminq_subtask(pf);
5093
5094 i40e_service_event_complete(pf);
5095
5096 /* If the tasks have taken longer than one timer cycle or there
5097 * is more work to be done, reschedule the service task now
5098 * rather than wait for the timer to tick again.
5099 */
5100 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5101 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5102 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5103 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5104 i40e_service_event_schedule(pf);
5105}
5106
5107/**
5108 * i40e_service_timer - timer callback
5109 * @data: pointer to PF struct
5110 **/
5111static void i40e_service_timer(unsigned long data)
5112{
5113 struct i40e_pf *pf = (struct i40e_pf *)data;
5114
5115 mod_timer(&pf->service_timer,
5116 round_jiffies(jiffies + pf->service_timer_period));
5117 i40e_service_event_schedule(pf);
5118}
5119
5120/**
5121 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5122 * @vsi: the VSI being configured
5123 **/
5124static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5125{
5126 struct i40e_pf *pf = vsi->back;
5127
5128 switch (vsi->type) {
5129 case I40E_VSI_MAIN:
5130 vsi->alloc_queue_pairs = pf->num_lan_qps;
5131 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5132 I40E_REQ_DESCRIPTOR_MULTIPLE);
5133 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5134 vsi->num_q_vectors = pf->num_lan_msix;
5135 else
5136 vsi->num_q_vectors = 1;
5137
5138 break;
5139
5140 case I40E_VSI_FDIR:
5141 vsi->alloc_queue_pairs = 1;
5142 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5143 I40E_REQ_DESCRIPTOR_MULTIPLE);
5144 vsi->num_q_vectors = 1;
5145 break;
5146
5147 case I40E_VSI_VMDQ2:
5148 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5149 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5150 I40E_REQ_DESCRIPTOR_MULTIPLE);
5151 vsi->num_q_vectors = pf->num_vmdq_msix;
5152 break;
5153
5154 case I40E_VSI_SRIOV:
5155 vsi->alloc_queue_pairs = pf->num_vf_qps;
5156 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5157 I40E_REQ_DESCRIPTOR_MULTIPLE);
5158 break;
5159
5160 default:
5161 WARN_ON(1);
5162 return -ENODATA;
5163 }
5164
5165 return 0;
5166}
5167
f650a38b
ASJ		 5168/**
5169 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5170 * @type: VSI pointer
bc7d338f 5171 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5172 *
5173 * On error: returns error code (negative)
5174 * On success: returns 0
5175 **/
bc7d338f 5176static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5177{
5178 int size;
5179 int ret = 0;
5180
ac6c5e3d 5181 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5182 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5183 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5184 if (!vsi->tx_rings)
5185 return -ENOMEM;
f650a38b
ASJ		 5186 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5187
bc7d338f
ASJ		 5188 if (alloc_qvectors) {
5189 /* allocate memory for q_vector pointers */
5190 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5191 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5192 if (!vsi->q_vectors) {
5193 ret = -ENOMEM;
5194 goto err_vectors;
5195 }
f650a38b
ASJ		 5196 }
5197 return ret;
5198
5199err_vectors:
5200 kfree(vsi->tx_rings);
5201 return ret;
5202}
5203
41c445ff
JB		 5204/**
5205 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5206 * @pf: board private structure
5207 * @type: type of VSI
5208 *
5209 * On error: returns error code (negative)
5210 * On success: returns vsi index in PF (positive)
5211 **/
5212static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5213{
5214 int ret = -ENODEV;
5215 struct i40e_vsi *vsi;
5216 int vsi_idx;
5217 int i;
5218
5219 /* Need to protect the allocation of the VSIs at the PF level */
5220 mutex_lock(&pf->switch_mutex);
5221
5222 /* VSI list may be fragmented if VSI creation/destruction has
5223 * been happening. We can afford to do a quick scan to look
5224 * for any free VSIs in the list.
5225 *
5226 * find next empty vsi slot, looping back around if necessary
5227 */
5228 i = pf->next_vsi;
5229 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5230 i++;
5231 if (i >= pf->hw.func_caps.num_vsis) {
5232 i = 0;
5233 while (i < pf->next_vsi && pf->vsi[i])
5234 i++;
5235 }
5236
5237 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5238 vsi_idx = i; /* Found one! */
5239 } else {
5240 ret = -ENODEV;
493fb300 5241 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5242 }
5243 pf->next_vsi = ++i;
5244
5245 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5246 if (!vsi) {
5247 ret = -ENOMEM;
493fb300 5248 goto unlock_pf;
41c445ff
JB		 5249 }
5250 vsi->type = type;
5251 vsi->back = pf;
5252 set_bit(__I40E_DOWN, &vsi->state);
5253 vsi->flags = 0;
5254 vsi->idx = vsi_idx;
5255 vsi->rx_itr_setting = pf->rx_itr_default;
5256 vsi->tx_itr_setting = pf->tx_itr_default;
5257 vsi->netdev_registered = false;
5258 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5259 INIT_LIST_HEAD(&vsi->mac_filter_list);
5260
9f65e15b
AD		 5261 ret = i40e_set_num_rings_in_vsi(vsi);
5262 if (ret)
5263 goto err_rings;
5264
bc7d338f 5265 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5266 if (ret)
9f65e15b 5267 goto err_rings;
493fb300 5268
41c445ff
JB		 5269 /* Setup default MSIX irq handler for VSI */
5270 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5271
5272 pf->vsi[vsi_idx] = vsi;
5273 ret = vsi_idx;
493fb300
AD		 5274 goto unlock_pf;
5275
9f65e15b 5276err_rings:
493fb300
AD		 5277 pf->next_vsi = i - 1;
5278 kfree(vsi);
5279unlock_pf:
41c445ff
JB		 5280 mutex_unlock(&pf->switch_mutex);
5281 return ret;
5282}
5283
f650a38b
ASJ		 5284/**
5285 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5286 * @type: VSI pointer
bc7d338f 5287 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5288 *
5289 * On error: returns error code (negative)
5290 * On success: returns 0
5291 **/
bc7d338f 5292static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5293{
5294 /* free the ring and vector containers */
bc7d338f
ASJ		 5295 if (free_qvectors) {
5296 kfree(vsi->q_vectors);
5297 vsi->q_vectors = NULL;
5298 }
f650a38b
ASJ		 5299 kfree(vsi->tx_rings);
5300 vsi->tx_rings = NULL;
5301 vsi->rx_rings = NULL;
5302}
5303
41c445ff
JB		 5304/**
5305 * i40e_vsi_clear - Deallocate the VSI provided
5306 * @vsi: the VSI being un-configured
5307 **/
5308static int i40e_vsi_clear(struct i40e_vsi *vsi)
5309{
5310 struct i40e_pf *pf;
5311
5312 if (!vsi)
5313 return 0;
5314
5315 if (!vsi->back)
5316 goto free_vsi;
5317 pf = vsi->back;
5318
5319 mutex_lock(&pf->switch_mutex);
5320 if (!pf->vsi[vsi->idx]) {
5321 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5322 vsi->idx, vsi->idx, vsi, vsi->type);
5323 goto unlock_vsi;
5324 }
5325
5326 if (pf->vsi[vsi->idx] != vsi) {
5327 dev_err(&pf->pdev->dev,
5328 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5329 pf->vsi[vsi->idx]->idx,
5330 pf->vsi[vsi->idx],
5331 pf->vsi[vsi->idx]->type,
5332 vsi->idx, vsi, vsi->type);
5333 goto unlock_vsi;
5334 }
5335
5336 /* updates the pf for this cleared vsi */
5337 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5338 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5339
bc7d338f 5340 i40e_vsi_free_arrays(vsi, true);
493fb300 5341
41c445ff
JB		 5342 pf->vsi[vsi->idx] = NULL;
5343 if (vsi->idx < pf->next_vsi)
5344 pf->next_vsi = vsi->idx;
5345
5346unlock_vsi:
5347 mutex_unlock(&pf->switch_mutex);
5348free_vsi:
5349 kfree(vsi);
5350
5351 return 0;
5352}
5353
9f65e15b
AD		 5354/**
5355 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5356 * @vsi: the VSI being cleaned
5357 **/
be1d5eea 5358static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5359{
5360 int i;
5361
8e9dca53 5362 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5363 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5364 kfree_rcu(vsi->tx_rings[i], rcu);
5365 vsi->tx_rings[i] = NULL;
5366 vsi->rx_rings[i] = NULL;
5367 }
be1d5eea 5368 }
9f65e15b
AD		 5369}
5370
41c445ff
JB		 5371/**
5372 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5373 * @vsi: the VSI being configured
5374 **/
5375static int i40e_alloc_rings(struct i40e_vsi *vsi)
5376{
5377 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5378 int i;
5379
41c445ff 5380 /* Set basic values in the rings to be used later during open() */
d7397644 5381 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5382 struct i40e_ring *tx_ring;
5383 struct i40e_ring *rx_ring;
5384
ac6c5e3d 5385 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5386 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5387 if (!tx_ring)
5388 goto err_out;
41c445ff
JB		 5389
5390 tx_ring->queue_index = i;
5391 tx_ring->reg_idx = vsi->base_queue + i;
5392 tx_ring->ring_active = false;
5393 tx_ring->vsi = vsi;
5394 tx_ring->netdev = vsi->netdev;
5395 tx_ring->dev = &pf->pdev->dev;
5396 tx_ring->count = vsi->num_desc;
5397 tx_ring->size = 0;
5398 tx_ring->dcb_tc = 0;
9f65e15b 5399 vsi->tx_rings[i] = tx_ring;
41c445ff 5400
9f65e15b 5401 rx_ring = &tx_ring[1];
41c445ff
JB		 5402 rx_ring->queue_index = i;
5403 rx_ring->reg_idx = vsi->base_queue + i;
5404 rx_ring->ring_active = false;
5405 rx_ring->vsi = vsi;
5406 rx_ring->netdev = vsi->netdev;
5407 rx_ring->dev = &pf->pdev->dev;
5408 rx_ring->count = vsi->num_desc;
5409 rx_ring->size = 0;
5410 rx_ring->dcb_tc = 0;
5411 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5412 set_ring_16byte_desc_enabled(rx_ring);
5413 else
5414 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5415 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5416 }
5417
5418 return 0;
9f65e15b
AD		 5419
5420err_out:
5421 i40e_vsi_clear_rings(vsi);
5422 return -ENOMEM;
41c445ff
JB		 5423}
5424
5425/**
5426 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5427 * @pf: board private structure
5428 * @vectors: the number of MSI-X vectors to request
5429 *
5430 * Returns the number of vectors reserved, or error
5431 **/
5432static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5433{
5434 int err = 0;
5435
5436 pf->num_msix_entries = 0;
5437 while (vectors >= I40E_MIN_MSIX) {
5438 err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
5439 if (err == 0) {
5440 /* good to go */
5441 pf->num_msix_entries = vectors;
5442 break;
5443 } else if (err < 0) {
5444 /* total failure */
5445 dev_info(&pf->pdev->dev,
5446 "MSI-X vector reservation failed: %d\n", err);
5447 vectors = 0;
5448 break;
5449 } else {
5450 /* err > 0 is the hint for retry */
5451 dev_info(&pf->pdev->dev,
5452 "MSI-X vectors wanted %d, retrying with %d\n",
5453 vectors, err);
5454 vectors = err;
5455 }
5456 }
5457
5458 if (vectors > 0 && vectors < I40E_MIN_MSIX) {
5459 dev_info(&pf->pdev->dev,
5460 "Couldn't get enough vectors, only %d available\n",
5461 vectors);
5462 vectors = 0;
5463 }
5464
5465 return vectors;
5466}
5467
5468/**
5469 * i40e_init_msix - Setup the MSIX capability
5470 * @pf: board private structure
5471 *
5472 * Work with the OS to set up the MSIX vectors needed.
5473 *
5474 * Returns 0 on success, negative on failure
5475 **/
5476static int i40e_init_msix(struct i40e_pf *pf)
5477{
5478 i40e_status err = 0;
5479 struct i40e_hw *hw = &pf->hw;
5480 int v_budget, i;
5481 int vec;
5482
5483 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5484 return -ENODEV;
5485
5486 /* The number of vectors we'll request will be comprised of:
5487 * - Add 1 for "other" cause for Admin Queue events, etc.
5488 * - The number of LAN queue pairs
f8ff1464
ASJ		 5489 * - Queues being used for RSS.
5490 * We don't need as many as max_rss_size vectors.
5491 * use rss_size instead in the calculation since that
5492 * is governed by number of cpus in the system.
5493 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5494 * - The number of VMDq pairs
5495 * Once we count this up, try the request.
5496 *
5497 * If we can't get what we want, we'll simplify to nearly nothing
5498 * and try again. If that still fails, we punt.
5499 */
f8ff1464 5500 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5501 pf->num_vmdq_msix = pf->num_vmdq_qps;
5502 v_budget = 1 + pf->num_lan_msix;
5503 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
5504 if (pf->flags & I40E_FLAG_FDIR_ENABLED)
5505 v_budget++;
5506
5507 /* Scale down if necessary, and the rings will share vectors */
5508 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5509
5510 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5511 GFP_KERNEL);
5512 if (!pf->msix_entries)
5513 return -ENOMEM;
5514
5515 for (i = 0; i < v_budget; i++)
5516 pf->msix_entries[i].entry = i;
5517 vec = i40e_reserve_msix_vectors(pf, v_budget);
5518 if (vec < I40E_MIN_MSIX) {
5519 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5520 kfree(pf->msix_entries);
5521 pf->msix_entries = NULL;
5522 return -ENODEV;
5523
5524 } else if (vec == I40E_MIN_MSIX) {
5525 /* Adjust for minimal MSIX use */
5526 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5527 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5528 pf->num_vmdq_vsis = 0;
5529 pf->num_vmdq_qps = 0;
5530 pf->num_vmdq_msix = 0;
5531 pf->num_lan_qps = 1;
5532 pf->num_lan_msix = 1;
5533
5534 } else if (vec != v_budget) {
5535 /* Scale vector usage down */
5536 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5537 vec--; /* reserve the misc vector */
5538
5539 /* partition out the remaining vectors */
5540 switch (vec) {
5541 case 2:
5542 pf->num_vmdq_vsis = 1;
5543 pf->num_lan_msix = 1;
5544 break;
5545 case 3:
5546 pf->num_vmdq_vsis = 1;
5547 pf->num_lan_msix = 2;
5548 break;
5549 default:
5550 pf->num_lan_msix = min_t(int, (vec / 2),
5551 pf->num_lan_qps);
5552 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5553 I40E_DEFAULT_NUM_VMDQ_VSI);
5554 break;
5555 }
5556 }
5557
5558 return err;
5559}
5560
493fb300
AD		 5561/**
5562 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5563 * @vsi: the VSI being configured
5564 * @v_idx: index of the vector in the vsi struct
5565 *
5566 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5567 **/
5568static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5569{
5570 struct i40e_q_vector *q_vector;
5571
5572 /* allocate q_vector */
5573 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5574 if (!q_vector)
5575 return -ENOMEM;
5576
5577 q_vector->vsi = vsi;
5578 q_vector->v_idx = v_idx;
5579 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5580 if (vsi->netdev)
5581 netif_napi_add(vsi->netdev, &q_vector->napi,
5582 i40e_napi_poll, vsi->work_limit);
5583
cd0b6fa6
AD		 5584 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5585 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5586
493fb300
AD		 5587 /* tie q_vector and vsi together */
5588 vsi->q_vectors[v_idx] = q_vector;
5589
5590 return 0;
5591}
5592
41c445ff
JB		 5593/**
5594 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5595 * @vsi: the VSI being configured
5596 *
5597 * We allocate one q_vector per queue interrupt. If allocation fails we
5598 * return -ENOMEM.
5599 **/
5600static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
5601{
5602 struct i40e_pf *pf = vsi->back;
5603 int v_idx, num_q_vectors;
493fb300 5604 int err;
41c445ff
JB		 5605
5606 /* if not MSIX, give the one vector only to the LAN VSI */
5607 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5608 num_q_vectors = vsi->num_q_vectors;
5609 else if (vsi == pf->vsi[pf->lan_vsi])
5610 num_q_vectors = 1;
5611 else
5612 return -EINVAL;
5613
41c445ff 5614 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 5615 err = i40e_alloc_q_vector(vsi, v_idx);
5616 if (err)
5617 goto err_out;
41c445ff
JB		 5618 }
5619
5620 return 0;
493fb300
AD		 5621
5622err_out:
5623 while (v_idx--)
5624 i40e_free_q_vector(vsi, v_idx);
5625
5626 return err;
41c445ff
JB		 5627}
5628
5629/**
5630 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
5631 * @pf: board private structure to initialize
5632 **/
5633static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
5634{
5635 int err = 0;
5636
5637 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
5638 err = i40e_init_msix(pf);
5639 if (err) {
958a3e3b
SN		 5640 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
5641 I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 5642 I40E_FLAG_DCB_ENABLED |
5643 I40E_FLAG_SRIOV_ENABLED |
5644 I40E_FLAG_FDIR_ENABLED |
5645 I40E_FLAG_FDIR_ATR_ENABLED |
5646 I40E_FLAG_VMDQ_ENABLED);
5647
5648 /* rework the queue expectations without MSIX */
5649 i40e_determine_queue_usage(pf);
5650 }
5651 }
5652
5653 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
5654 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 5655 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 5656 err = pci_enable_msi(pf->pdev);
5657 if (err) {
958a3e3b 5658 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 5659 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
5660 }
5661 }
5662
958a3e3b
SN		 5663 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
5664 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
5665
41c445ff
JB		 5666 /* track first vector for misc interrupts */
5667 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
5668}
5669
5670/**
5671 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
5672 * @pf: board private structure
5673 *
5674 * This sets up the handler for MSIX 0, which is used to manage the
5675 * non-queue interrupts, e.g. AdminQ and errors. This is not used
5676 * when in MSI or Legacy interrupt mode.
5677 **/
5678static int i40e_setup_misc_vector(struct i40e_pf *pf)
5679{
5680 struct i40e_hw *hw = &pf->hw;
5681 int err = 0;
5682
5683 /* Only request the irq if this is the first time through, and
5684 * not when we're rebuilding after a Reset
5685 */
5686 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5687 err = request_irq(pf->msix_entries[0].vector,
5688 i40e_intr, 0, pf->misc_int_name, pf);
5689 if (err) {
5690 dev_info(&pf->pdev->dev,
5691 "request_irq for msix_misc failed: %d\n", err);
5692 return -EFAULT;
5693 }
5694 }
5695
5696 i40e_enable_misc_int_causes(hw);
5697
5698 /* associate no queues to the misc vector */
5699 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
5700 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
5701
5702 i40e_flush(hw);
5703
5704 i40e_irq_dynamic_enable_icr0(pf);
5705
5706 return err;
5707}
5708
5709/**
5710 * i40e_config_rss - Prepare for RSS if used
5711 * @pf: board private structure
5712 **/
5713static int i40e_config_rss(struct i40e_pf *pf)
5714{
41c445ff
JB		 5715 /* Set of random keys generated using kernel random number generator */
5716 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
5717 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
5718 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
5719 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 5720 struct i40e_hw *hw = &pf->hw;
5721 u32 lut = 0;
5722 int i, j;
5723 u64 hena;
41c445ff
JB		 5724
5725 /* Fill out hash function seed */
5726 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5727 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
5728
5729 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
5730 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
5731 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 5732 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 5733 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
5734 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
5735
5736 /* Populate the LUT with max no. of queues in round robin fashion */
5737 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
5738
5739 /* The assumption is that lan qp count will be the highest
5740 * qp count for any PF VSI that needs RSS.
5741 * If multiple VSIs need RSS support, all the qp counts
5742 * for those VSIs should be a power of 2 for RSS to work.
5743 * If LAN VSI is the only consumer for RSS then this requirement
5744 * is not necessary.
5745 */
5746 if (j == pf->rss_size)
5747 j = 0;
5748 /* lut = 4-byte sliding window of 4 lut entries */
5749 lut = (lut << 8) | (j &
5750 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
5751 /* On i = 3, we have 4 entries in lut; write to the register */
5752 if ((i & 3) == 3)
5753 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
5754 }
5755 i40e_flush(hw);
5756
5757 return 0;
5758}
5759
f8ff1464
ASJ		 5760/**
5761 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
5762 * @pf: board private structure
5763 * @queue_count: the requested queue count for rss.
5764 *
5765 * returns 0 if rss is not enabled, if enabled returns the final rss queue
5766 * count which may be different from the requested queue count.
5767 **/
5768int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
5769{
5770 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
5771 return 0;
5772
5773 queue_count = min_t(int, queue_count, pf->rss_size_max);
5774 queue_count = rounddown_pow_of_two(queue_count);
5775
5776 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 5777 i40e_prep_for_reset(pf);
5778
f8ff1464
ASJ		 5779 pf->rss_size = queue_count;
5780
5781 i40e_reset_and_rebuild(pf, true);
5782 i40e_config_rss(pf);
5783 }
5784 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
5785 return pf->rss_size;
5786}
5787
41c445ff
JB		 5788/**
5789 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
5790 * @pf: board private structure to initialize
5791 *
5792 * i40e_sw_init initializes the Adapter private data structure.
5793 * Fields are initialized based on PCI device information and
5794 * OS network device settings (MTU size).
5795 **/
5796static int i40e_sw_init(struct i40e_pf *pf)
5797{
5798 int err = 0;
5799 int size;
5800
5801 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
5802 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 5803 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 5804 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
5805 if (I40E_DEBUG_USER & debug)
5806 pf->hw.debug_mask = debug;
5807 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
5808 I40E_DEFAULT_MSG_ENABLE);
5809 }
5810
5811 /* Set default capability flags */
5812 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
5813 I40E_FLAG_MSI_ENABLED |
5814 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 5815 I40E_FLAG_RX_1BUF_ENABLED;
5816
7134f9ce
JB		 5817 /* Depending on PF configurations, it is possible that the RSS
5818 * maximum might end up larger than the available queues
5819 */
41c445ff 5820 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 5821 pf->rss_size_max = min_t(int, pf->rss_size_max,
5822 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 5823 if (pf->hw.func_caps.rss) {
5824 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 5825 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 5826 } else {
5827 pf->rss_size = 1;
5828 }
5829
5830 if (pf->hw.func_caps.dcb)
5831 pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
5832 else
5833 pf->num_tc_qps = 0;
5834
5835 if (pf->hw.func_caps.fd) {
5836 /* FW/NVM is not yet fixed in this regard */
5837 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
5838 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
5839 pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
5840 dev_info(&pf->pdev->dev,
5841 "Flow Director ATR mode Enabled\n");
5842 pf->flags |= I40E_FLAG_FDIR_ENABLED;
5843 dev_info(&pf->pdev->dev,
5844 "Flow Director Side Band mode Enabled\n");
5845 pf->fdir_pf_filter_count =
5846 pf->hw.func_caps.fd_filters_guaranteed;
5847 }
5848 } else {
5849 pf->fdir_pf_filter_count = 0;
5850 }
5851
5852 if (pf->hw.func_caps.vmdq) {
5853 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
5854 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
5855 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
5856 }
5857
5858 /* MFP mode enabled */
5859 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
5860 pf->flags |= I40E_FLAG_MFP_ENABLED;
5861 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
5862 }
5863
5864#ifdef CONFIG_PCI_IOV
5865 if (pf->hw.func_caps.num_vfs) {
5866 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
5867 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
5868 pf->num_req_vfs = min_t(int,
5869 pf->hw.func_caps.num_vfs,
5870 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 5871 dev_info(&pf->pdev->dev,
5872 "Number of VFs being requested for PF[%d] = %d\n",
5873 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 5874 }
5875#endif /* CONFIG_PCI_IOV */
5876 pf->eeprom_version = 0xDEAD;
5877 pf->lan_veb = I40E_NO_VEB;
5878 pf->lan_vsi = I40E_NO_VSI;
5879
5880 /* set up queue assignment tracking */
5881 size = sizeof(struct i40e_lump_tracking)
5882 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
5883 pf->qp_pile = kzalloc(size, GFP_KERNEL);
5884 if (!pf->qp_pile) {
5885 err = -ENOMEM;
5886 goto sw_init_done;
5887 }
5888 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
5889 pf->qp_pile->search_hint = 0;
5890
5891 /* set up vector assignment tracking */
5892 size = sizeof(struct i40e_lump_tracking)
5893 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
5894 pf->irq_pile = kzalloc(size, GFP_KERNEL);
5895 if (!pf->irq_pile) {
5896 kfree(pf->qp_pile);
5897 err = -ENOMEM;
5898 goto sw_init_done;
5899 }
5900 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
5901 pf->irq_pile->search_hint = 0;
5902
5903 mutex_init(&pf->switch_mutex);
5904
5905sw_init_done:
5906 return err;
5907}
5908
5909/**
5910 * i40e_set_features - set the netdev feature flags
5911 * @netdev: ptr to the netdev being adjusted
5912 * @features: the feature set that the stack is suggesting
5913 **/
5914static int i40e_set_features(struct net_device *netdev,
5915 netdev_features_t features)
5916{
5917 struct i40e_netdev_priv *np = netdev_priv(netdev);
5918 struct i40e_vsi *vsi = np->vsi;
5919
5920 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5921 i40e_vlan_stripping_enable(vsi);
5922 else
5923 i40e_vlan_stripping_disable(vsi);
5924
5925 return 0;
5926}
5927
a1c9a9d9
JK		 5928#ifdef CONFIG_I40E_VXLAN
5929/**
5930 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
5931 * @pf: board private structure
5932 * @port: The UDP port to look up
5933 *
5934 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
5935 **/
5936static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
5937{
5938 u8 i;
5939
5940 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5941 if (pf->vxlan_ports[i] == port)
5942 return i;
5943 }
5944
5945 return i;
5946}
5947
5948/**
5949 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
5950 * @netdev: This physical port's netdev
5951 * @sa_family: Socket Family that VXLAN is notifying us about
5952 * @port: New UDP port number that VXLAN started listening to
5953 **/
5954static void i40e_add_vxlan_port(struct net_device *netdev,
5955 sa_family_t sa_family, __be16 port)
5956{
5957 struct i40e_netdev_priv *np = netdev_priv(netdev);
5958 struct i40e_vsi *vsi = np->vsi;
5959 struct i40e_pf *pf = vsi->back;
5960 u8 next_idx;
5961 u8 idx;
5962
5963 if (sa_family == AF_INET6)
5964 return;
5965
5966 idx = i40e_get_vxlan_port_idx(pf, port);
5967
5968 /* Check if port already exists */
5969 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5970 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
5971 return;
5972 }
5973
5974 /* Now check if there is space to add the new port */
5975 next_idx = i40e_get_vxlan_port_idx(pf, 0);
5976
5977 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5978 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
5979 ntohs(port));
5980 return;
5981 }
5982
5983 /* New port: add it and mark its index in the bitmap */
5984 pf->vxlan_ports[next_idx] = port;
5985 pf->pending_vxlan_bitmap |= (1 << next_idx);
5986
5987 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
5988}
5989
5990/**
5991 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
5992 * @netdev: This physical port's netdev
5993 * @sa_family: Socket Family that VXLAN is notifying us about
5994 * @port: UDP port number that VXLAN stopped listening to
5995 **/
5996static void i40e_del_vxlan_port(struct net_device *netdev,
5997 sa_family_t sa_family, __be16 port)
5998{
5999 struct i40e_netdev_priv *np = netdev_priv(netdev);
6000 struct i40e_vsi *vsi = np->vsi;
6001 struct i40e_pf *pf = vsi->back;
6002 u8 idx;
6003
6004 if (sa_family == AF_INET6)
6005 return;
6006
6007 idx = i40e_get_vxlan_port_idx(pf, port);
6008
6009 /* Check if port already exists */
6010 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6011 /* if port exists, set it to 0 (mark for deletion)
6012 * and make it pending
6013 */
6014 pf->vxlan_ports[idx] = 0;
6015
6016 pf->pending_vxlan_bitmap |= (1 << idx);
6017
6018 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6019 } else {
6020 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6021 ntohs(port));
6022 }
6023}
6024
6025#endif
41c445ff
JB		 6026static const struct net_device_ops i40e_netdev_ops = {
6027 .ndo_open = i40e_open,
6028 .ndo_stop = i40e_close,
6029 .ndo_start_xmit = i40e_lan_xmit_frame,
6030 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6031 .ndo_set_rx_mode = i40e_set_rx_mode,
6032 .ndo_validate_addr = eth_validate_addr,
6033 .ndo_set_mac_address = i40e_set_mac,
6034 .ndo_change_mtu = i40e_change_mtu,
6035 .ndo_tx_timeout = i40e_tx_timeout,
6036 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6037 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6038#ifdef CONFIG_NET_POLL_CONTROLLER
6039 .ndo_poll_controller = i40e_netpoll,
6040#endif
6041 .ndo_setup_tc = i40e_setup_tc,
6042 .ndo_set_features = i40e_set_features,
6043 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6044 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6045 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6046 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6047#ifdef CONFIG_I40E_VXLAN
6048 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6049 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6050#endif
41c445ff
JB		 6051};
6052
6053/**
6054 * i40e_config_netdev - Setup the netdev flags
6055 * @vsi: the VSI being configured
6056 *
6057 * Returns 0 on success, negative value on failure
6058 **/
6059static int i40e_config_netdev(struct i40e_vsi *vsi)
6060{
1a10370a 6061 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6062 struct i40e_pf *pf = vsi->back;
6063 struct i40e_hw *hw = &pf->hw;
6064 struct i40e_netdev_priv *np;
6065 struct net_device *netdev;
6066 u8 mac_addr[ETH_ALEN];
6067 int etherdev_size;
6068
6069 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6070 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6071 if (!netdev)
6072 return -ENOMEM;
6073
6074 vsi->netdev = netdev;
6075 np = netdev_priv(netdev);
6076 np->vsi = vsi;
6077
6078 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6079 NETIF_F_GSO_UDP_TUNNEL |
6080 NETIF_F_TSO |
6081 NETIF_F_SG;
6082
6083 netdev->features = NETIF_F_SG |
6084 NETIF_F_IP_CSUM |
6085 NETIF_F_SCTP_CSUM |
6086 NETIF_F_HIGHDMA |
6087 NETIF_F_GSO_UDP_TUNNEL |
6088 NETIF_F_HW_VLAN_CTAG_TX |
6089 NETIF_F_HW_VLAN_CTAG_RX |
6090 NETIF_F_HW_VLAN_CTAG_FILTER |
6091 NETIF_F_IPV6_CSUM |
6092 NETIF_F_TSO |
6093 NETIF_F_TSO6 |
6094 NETIF_F_RXCSUM |
6095 NETIF_F_RXHASH |
6096 0;
6097
6098 /* copy netdev features into list of user selectable features */
6099 netdev->hw_features |= netdev->features;
6100
6101 if (vsi->type == I40E_VSI_MAIN) {
6102 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6103 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6104 } else {
6105 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6106 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6107 pf->vsi[pf->lan_vsi]->netdev->name);
6108 random_ether_addr(mac_addr);
6109 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6110 }
1a10370a 6111 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6112
6113 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6114 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6115 /* vlan gets same features (except vlan offload)
6116 * after any tweaks for specific VSI types
6117 */
6118 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6119 NETIF_F_HW_VLAN_CTAG_RX |
6120 NETIF_F_HW_VLAN_CTAG_FILTER);
6121 netdev->priv_flags |= IFF_UNICAST_FLT;
6122 netdev->priv_flags |= IFF_SUPP_NOFCS;
6123 /* Setup netdev TC information */
6124 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6125
6126 netdev->netdev_ops = &i40e_netdev_ops;
6127 netdev->watchdog_timeo = 5 * HZ;
6128 i40e_set_ethtool_ops(netdev);
6129
6130 return 0;
6131}
6132
6133/**
6134 * i40e_vsi_delete - Delete a VSI from the switch
6135 * @vsi: the VSI being removed
6136 *
6137 * Returns 0 on success, negative value on failure
6138 **/
6139static void i40e_vsi_delete(struct i40e_vsi *vsi)
6140{
6141 /* remove default VSI is not allowed */
6142 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6143 return;
6144
6145 /* there is no HW VSI for FDIR */
6146 if (vsi->type == I40E_VSI_FDIR)
6147 return;
6148
6149 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6150 return;
6151}
6152
6153/**
6154 * i40e_add_vsi - Add a VSI to the switch
6155 * @vsi: the VSI being configured
6156 *
6157 * This initializes a VSI context depending on the VSI type to be added and
6158 * passes it down to the add_vsi aq command.
6159 **/
6160static int i40e_add_vsi(struct i40e_vsi *vsi)
6161{
6162 int ret = -ENODEV;
6163 struct i40e_mac_filter *f, *ftmp;
6164 struct i40e_pf *pf = vsi->back;
6165 struct i40e_hw *hw = &pf->hw;
6166 struct i40e_vsi_context ctxt;
6167 u8 enabled_tc = 0x1; /* TC0 enabled */
6168 int f_count = 0;
6169
6170 memset(&ctxt, 0, sizeof(ctxt));
6171 switch (vsi->type) {
6172 case I40E_VSI_MAIN:
6173 /* The PF's main VSI is already setup as part of the
6174 * device initialization, so we'll not bother with
6175 * the add_vsi call, but we will retrieve the current
6176 * VSI context.
6177 */
6178 ctxt.seid = pf->main_vsi_seid;
6179 ctxt.pf_num = pf->hw.pf_id;
6180 ctxt.vf_num = 0;
6181 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6182 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6183 if (ret) {
6184 dev_info(&pf->pdev->dev,
6185 "couldn't get pf vsi config, err %d, aq_err %d\n",
6186 ret, pf->hw.aq.asq_last_status);
6187 return -ENOENT;
6188 }
6189 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6190 vsi->info.valid_sections = 0;
6191
6192 vsi->seid = ctxt.seid;
6193 vsi->id = ctxt.vsi_number;
6194
6195 enabled_tc = i40e_pf_get_tc_map(pf);
6196
6197 /* MFP mode setup queue map and update VSI */
6198 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6199 memset(&ctxt, 0, sizeof(ctxt));
6200 ctxt.seid = pf->main_vsi_seid;
6201 ctxt.pf_num = pf->hw.pf_id;
6202 ctxt.vf_num = 0;
6203 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6204 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6205 if (ret) {
6206 dev_info(&pf->pdev->dev,
6207 "update vsi failed, aq_err=%d\n",
6208 pf->hw.aq.asq_last_status);
6209 ret = -ENOENT;
6210 goto err;
6211 }
6212 /* update the local VSI info queue map */
6213 i40e_vsi_update_queue_map(vsi, &ctxt);
6214 vsi->info.valid_sections = 0;
6215 } else {
6216 /* Default/Main VSI is only enabled for TC0
6217 * reconfigure it to enable all TCs that are
6218 * available on the port in SFP mode.
6219 */
6220 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6221 if (ret) {
6222 dev_info(&pf->pdev->dev,
6223 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6224 enabled_tc, ret,
6225 pf->hw.aq.asq_last_status);
6226 ret = -ENOENT;
6227 }
6228 }
6229 break;
6230
6231 case I40E_VSI_FDIR:
6232 /* no queue mapping or actual HW VSI needed */
6233 vsi->info.valid_sections = 0;
6234 vsi->seid = 0;
6235 vsi->id = 0;
6236 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6237 return 0;
6238 break;
6239
6240 case I40E_VSI_VMDQ2:
6241 ctxt.pf_num = hw->pf_id;
6242 ctxt.vf_num = 0;
6243 ctxt.uplink_seid = vsi->uplink_seid;
6244 ctxt.connection_type = 0x1; /* regular data port */
6245 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6246
6247 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6248
6249 /* This VSI is connected to VEB so the switch_id
6250 * should be set to zero by default.
6251 */
6252 ctxt.info.switch_id = 0;
6253 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6254 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6255
6256 /* Setup the VSI tx/rx queue map for TC0 only for now */
6257 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6258 break;
6259
6260 case I40E_VSI_SRIOV:
6261 ctxt.pf_num = hw->pf_id;
6262 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6263 ctxt.uplink_seid = vsi->uplink_seid;
6264 ctxt.connection_type = 0x1; /* regular data port */
6265 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6266
6267 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6268
6269 /* This VSI is connected to VEB so the switch_id
6270 * should be set to zero by default.
6271 */
6272 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6273
6274 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6275 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6276 /* Setup the VSI tx/rx queue map for TC0 only for now */
6277 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6278 break;
6279
6280 default:
6281 return -ENODEV;
6282 }
6283
6284 if (vsi->type != I40E_VSI_MAIN) {
6285 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6286 if (ret) {
6287 dev_info(&vsi->back->pdev->dev,
6288 "add vsi failed, aq_err=%d\n",
6289 vsi->back->hw.aq.asq_last_status);
6290 ret = -ENOENT;
6291 goto err;
6292 }
6293 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6294 vsi->info.valid_sections = 0;
6295 vsi->seid = ctxt.seid;
6296 vsi->id = ctxt.vsi_number;
6297 }
6298
6299 /* If macvlan filters already exist, force them to get loaded */
6300 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6301 f->changed = true;
6302 f_count++;
6303 }
6304 if (f_count) {
6305 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6306 pf->flags |= I40E_FLAG_FILTER_SYNC;
6307 }
6308
6309 /* Update VSI BW information */
6310 ret = i40e_vsi_get_bw_info(vsi);
6311 if (ret) {
6312 dev_info(&pf->pdev->dev,
6313 "couldn't get vsi bw info, err %d, aq_err %d\n",
6314 ret, pf->hw.aq.asq_last_status);
6315 /* VSI is already added so not tearing that up */
6316 ret = 0;
6317 }
6318
6319err:
6320 return ret;
6321}
6322
6323/**
6324 * i40e_vsi_release - Delete a VSI and free its resources
6325 * @vsi: the VSI being removed
6326 *
6327 * Returns 0 on success or < 0 on error
6328 **/
6329int i40e_vsi_release(struct i40e_vsi *vsi)
6330{
6331 struct i40e_mac_filter *f, *ftmp;
6332 struct i40e_veb *veb = NULL;
6333 struct i40e_pf *pf;
6334 u16 uplink_seid;
6335 int i, n;
6336
6337 pf = vsi->back;
6338
6339 /* release of a VEB-owner or last VSI is not allowed */
6340 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6341 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6342 vsi->seid, vsi->uplink_seid);
6343 return -ENODEV;
6344 }
6345 if (vsi == pf->vsi[pf->lan_vsi] &&
6346 !test_bit(__I40E_DOWN, &pf->state)) {
6347 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6348 return -ENODEV;
6349 }
6350
6351 uplink_seid = vsi->uplink_seid;
6352 if (vsi->type != I40E_VSI_SRIOV) {
6353 if (vsi->netdev_registered) {
6354 vsi->netdev_registered = false;
6355 if (vsi->netdev) {
6356 /* results in a call to i40e_close() */
6357 unregister_netdev(vsi->netdev);
6358 free_netdev(vsi->netdev);
6359 vsi->netdev = NULL;
6360 }
6361 } else {
6362 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6363 i40e_down(vsi);
6364 i40e_vsi_free_irq(vsi);
6365 i40e_vsi_free_tx_resources(vsi);
6366 i40e_vsi_free_rx_resources(vsi);
6367 }
6368 i40e_vsi_disable_irq(vsi);
6369 }
6370
6371 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6372 i40e_del_filter(vsi, f->macaddr, f->vlan,
6373 f->is_vf, f->is_netdev);
6374 i40e_sync_vsi_filters(vsi);
6375
6376 i40e_vsi_delete(vsi);
6377 i40e_vsi_free_q_vectors(vsi);
6378 i40e_vsi_clear_rings(vsi);
6379 i40e_vsi_clear(vsi);
6380
6381 /* If this was the last thing on the VEB, except for the
6382 * controlling VSI, remove the VEB, which puts the controlling
6383 * VSI onto the next level down in the switch.
6384 *
6385 * Well, okay, there's one more exception here: don't remove
6386 * the orphan VEBs yet. We'll wait for an explicit remove request
6387 * from up the network stack.
6388 */
6389 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6390 if (pf->vsi[i] &&
6391 pf->vsi[i]->uplink_seid == uplink_seid &&
6392 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6393 n++; /* count the VSIs */
6394 }
6395 }
6396 for (i = 0; i < I40E_MAX_VEB; i++) {
6397 if (!pf->veb[i])
6398 continue;
6399 if (pf->veb[i]->uplink_seid == uplink_seid)
6400 n++; /* count the VEBs */
6401 if (pf->veb[i]->seid == uplink_seid)
6402 veb = pf->veb[i];
6403 }
6404 if (n == 0 && veb && veb->uplink_seid != 0)
6405 i40e_veb_release(veb);
6406
6407 return 0;
6408}
6409
6410/**
6411 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6412 * @vsi: ptr to the VSI
6413 *
6414 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6415 * corresponding SW VSI structure and initializes num_queue_pairs for the
6416 * newly allocated VSI.
6417 *
6418 * Returns 0 on success or negative on failure
6419 **/
6420static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6421{
6422 int ret = -ENOENT;
6423 struct i40e_pf *pf = vsi->back;
6424
493fb300 6425 if (vsi->q_vectors[0]) {
41c445ff
JB		 6426 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6427 vsi->seid);
6428 return -EEXIST;
6429 }
6430
6431 if (vsi->base_vector) {
6432 dev_info(&pf->pdev->dev,
6433 "VSI %d has non-zero base vector %d\n",
6434 vsi->seid, vsi->base_vector);
6435 return -EEXIST;
6436 }
6437
6438 ret = i40e_alloc_q_vectors(vsi);
6439 if (ret) {
6440 dev_info(&pf->pdev->dev,
6441 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6442 vsi->num_q_vectors, vsi->seid, ret);
6443 vsi->num_q_vectors = 0;
6444 goto vector_setup_out;
6445 }
6446
958a3e3b
SN		 6447 if (vsi->num_q_vectors)
6448 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6449 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6450 if (vsi->base_vector < 0) {
6451 dev_info(&pf->pdev->dev,
6452 "failed to get q tracking for VSI %d, err=%d\n",
6453 vsi->seid, vsi->base_vector);
6454 i40e_vsi_free_q_vectors(vsi);
6455 ret = -ENOENT;
6456 goto vector_setup_out;
6457 }
6458
6459vector_setup_out:
6460 return ret;
6461}
6462
bc7d338f
ASJ		 6463/**
6464 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6465 * @vsi: pointer to the vsi.
6466 *
6467 * This re-allocates a vsi's queue resources.
6468 *
6469 * Returns pointer to the successfully allocated and configured VSI sw struct
6470 * on success, otherwise returns NULL on failure.
6471 **/
6472static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6473{
6474 struct i40e_pf *pf = vsi->back;
6475 u8 enabled_tc;
6476 int ret;
6477
6478 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6479 i40e_vsi_clear_rings(vsi);
6480
6481 i40e_vsi_free_arrays(vsi, false);
6482 i40e_set_num_rings_in_vsi(vsi);
6483 ret = i40e_vsi_alloc_arrays(vsi, false);
6484 if (ret)
6485 goto err_vsi;
6486
6487 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6488 if (ret < 0) {
6489 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6490 vsi->seid, ret);
6491 goto err_vsi;
6492 }
6493 vsi->base_queue = ret;
6494
6495 /* Update the FW view of the VSI. Force a reset of TC and queue
6496 * layout configurations.
6497 */
6498 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6499 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6500 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6501 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6502
6503 /* assign it some queues */
6504 ret = i40e_alloc_rings(vsi);
6505 if (ret)
6506 goto err_rings;
6507
6508 /* map all of the rings to the q_vectors */
6509 i40e_vsi_map_rings_to_vectors(vsi);
6510 return vsi;
6511
6512err_rings:
6513 i40e_vsi_free_q_vectors(vsi);
6514 if (vsi->netdev_registered) {
6515 vsi->netdev_registered = false;
6516 unregister_netdev(vsi->netdev);
6517 free_netdev(vsi->netdev);
6518 vsi->netdev = NULL;
6519 }
6520 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6521err_vsi:
6522 i40e_vsi_clear(vsi);
6523 return NULL;
6524}
6525
41c445ff
JB		 6526/**
6527 * i40e_vsi_setup - Set up a VSI by a given type
6528 * @pf: board private structure
6529 * @type: VSI type
6530 * @uplink_seid: the switch element to link to
6531 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6532 *
6533 * This allocates the sw VSI structure and its queue resources, then add a VSI
6534 * to the identified VEB.
6535 *
6536 * Returns pointer to the successfully allocated and configure VSI sw struct on
6537 * success, otherwise returns NULL on failure.
6538 **/
6539struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6540 u16 uplink_seid, u32 param1)
6541{
6542 struct i40e_vsi *vsi = NULL;
6543 struct i40e_veb *veb = NULL;
6544 int ret, i;
6545 int v_idx;
6546
6547 /* The requested uplink_seid must be either
6548 * - the PF's port seid
6549 * no VEB is needed because this is the PF
6550 * or this is a Flow Director special case VSI
6551 * - seid of an existing VEB
6552 * - seid of a VSI that owns an existing VEB
6553 * - seid of a VSI that doesn't own a VEB
6554 * a new VEB is created and the VSI becomes the owner
6555 * - seid of the PF VSI, which is what creates the first VEB
6556 * this is a special case of the previous
6557 *
6558 * Find which uplink_seid we were given and create a new VEB if needed
6559 */
6560 for (i = 0; i < I40E_MAX_VEB; i++) {
6561 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6562 veb = pf->veb[i];
6563 break;
6564 }
6565 }
6566
6567 if (!veb && uplink_seid != pf->mac_seid) {
6568
6569 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6570 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6571 vsi = pf->vsi[i];
6572 break;
6573 }
6574 }
6575 if (!vsi) {
6576 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6577 uplink_seid);
6578 return NULL;
6579 }
6580
6581 if (vsi->uplink_seid == pf->mac_seid)
6582 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6583 vsi->tc_config.enabled_tc);
6584 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6585 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6586 vsi->tc_config.enabled_tc);
6587
6588 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6589 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6590 veb = pf->veb[i];
6591 }
6592 if (!veb) {
6593 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6594 return NULL;
6595 }
6596
6597 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6598 uplink_seid = veb->seid;
6599 }
6600
6601 /* get vsi sw struct */
6602 v_idx = i40e_vsi_mem_alloc(pf, type);
6603 if (v_idx < 0)
6604 goto err_alloc;
6605 vsi = pf->vsi[v_idx];
6606 vsi->type = type;
6607 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
6608
6609 if (type == I40E_VSI_MAIN)
6610 pf->lan_vsi = v_idx;
6611 else if (type == I40E_VSI_SRIOV)
6612 vsi->vf_id = param1;
6613 /* assign it some queues */
6614 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6615 if (ret < 0) {
6616 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6617 vsi->seid, ret);
6618 goto err_vsi;
6619 }
6620 vsi->base_queue = ret;
6621
6622 /* get a VSI from the hardware */
6623 vsi->uplink_seid = uplink_seid;
6624 ret = i40e_add_vsi(vsi);
6625 if (ret)
6626 goto err_vsi;
6627
6628 switch (vsi->type) {
6629 /* setup the netdev if needed */
6630 case I40E_VSI_MAIN:
6631 case I40E_VSI_VMDQ2:
6632 ret = i40e_config_netdev(vsi);
6633 if (ret)
6634 goto err_netdev;
6635 ret = register_netdev(vsi->netdev);
6636 if (ret)
6637 goto err_netdev;
6638 vsi->netdev_registered = true;
6639 netif_carrier_off(vsi->netdev);
6640 /* fall through */
6641
6642 case I40E_VSI_FDIR:
6643 /* set up vectors and rings if needed */
6644 ret = i40e_vsi_setup_vectors(vsi);
6645 if (ret)
6646 goto err_msix;
6647
6648 ret = i40e_alloc_rings(vsi);
6649 if (ret)
6650 goto err_rings;
6651
6652 /* map all of the rings to the q_vectors */
6653 i40e_vsi_map_rings_to_vectors(vsi);
6654
6655 i40e_vsi_reset_stats(vsi);
6656 break;
6657
6658 default:
6659 /* no netdev or rings for the other VSI types */
6660 break;
6661 }
6662
6663 return vsi;
6664
6665err_rings:
6666 i40e_vsi_free_q_vectors(vsi);
6667err_msix:
6668 if (vsi->netdev_registered) {
6669 vsi->netdev_registered = false;
6670 unregister_netdev(vsi->netdev);
6671 free_netdev(vsi->netdev);
6672 vsi->netdev = NULL;
6673 }
6674err_netdev:
6675 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6676err_vsi:
6677 i40e_vsi_clear(vsi);
6678err_alloc:
6679 return NULL;
6680}
6681
6682/**
6683 * i40e_veb_get_bw_info - Query VEB BW information
6684 * @veb: the veb to query
6685 *
6686 * Query the Tx scheduler BW configuration data for given VEB
6687 **/
6688static int i40e_veb_get_bw_info(struct i40e_veb *veb)
6689{
6690 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
6691 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
6692 struct i40e_pf *pf = veb->pf;
6693 struct i40e_hw *hw = &pf->hw;
6694 u32 tc_bw_max;
6695 int ret = 0;
6696 int i;
6697
6698 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
6699 &bw_data, NULL);
6700 if (ret) {
6701 dev_info(&pf->pdev->dev,
6702 "query veb bw config failed, aq_err=%d\n",
6703 hw->aq.asq_last_status);
6704 goto out;
6705 }
6706
6707 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
6708 &ets_data, NULL);
6709 if (ret) {
6710 dev_info(&pf->pdev->dev,
6711 "query veb bw ets config failed, aq_err=%d\n",
6712 hw->aq.asq_last_status);
6713 goto out;
6714 }
6715
6716 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
6717 veb->bw_max_quanta = ets_data.tc_bw_max;
6718 veb->is_abs_credits = bw_data.absolute_credits_enable;
6719 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
6720 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
6721 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6722 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
6723 veb->bw_tc_limit_credits[i] =
6724 le16_to_cpu(bw_data.tc_bw_limits[i]);
6725 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
6726 }
6727
6728out:
6729 return ret;
6730}
6731
6732/**
6733 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
6734 * @pf: board private structure
6735 *
6736 * On error: returns error code (negative)
6737 * On success: returns vsi index in PF (positive)
6738 **/
6739static int i40e_veb_mem_alloc(struct i40e_pf *pf)
6740{
6741 int ret = -ENOENT;
6742 struct i40e_veb *veb;
6743 int i;
6744
6745 /* Need to protect the allocation of switch elements at the PF level */
6746 mutex_lock(&pf->switch_mutex);
6747
6748 /* VEB list may be fragmented if VEB creation/destruction has
6749 * been happening. We can afford to do a quick scan to look
6750 * for any free slots in the list.
6751 *
6752 * find next empty veb slot, looping back around if necessary
6753 */
6754 i = 0;
6755 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
6756 i++;
6757 if (i >= I40E_MAX_VEB) {
6758 ret = -ENOMEM;
6759 goto err_alloc_veb; /* out of VEB slots! */
6760 }
6761
6762 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
6763 if (!veb) {
6764 ret = -ENOMEM;
6765 goto err_alloc_veb;
6766 }
6767 veb->pf = pf;
6768 veb->idx = i;
6769 veb->enabled_tc = 1;
6770
6771 pf->veb[i] = veb;
6772 ret = i;
6773err_alloc_veb:
6774 mutex_unlock(&pf->switch_mutex);
6775 return ret;
6776}
6777
6778/**
6779 * i40e_switch_branch_release - Delete a branch of the switch tree
6780 * @branch: where to start deleting
6781 *
6782 * This uses recursion to find the tips of the branch to be
6783 * removed, deleting until we get back to and can delete this VEB.
6784 **/
6785static void i40e_switch_branch_release(struct i40e_veb *branch)
6786{
6787 struct i40e_pf *pf = branch->pf;
6788 u16 branch_seid = branch->seid;
6789 u16 veb_idx = branch->idx;
6790 int i;
6791
6792 /* release any VEBs on this VEB - RECURSION */
6793 for (i = 0; i < I40E_MAX_VEB; i++) {
6794 if (!pf->veb[i])
6795 continue;
6796 if (pf->veb[i]->uplink_seid == branch->seid)
6797 i40e_switch_branch_release(pf->veb[i]);
6798 }
6799
6800 /* Release the VSIs on this VEB, but not the owner VSI.
6801 *
6802 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
6803 * the VEB itself, so don't use (*branch) after this loop.
6804 */
6805 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6806 if (!pf->vsi[i])
6807 continue;
6808 if (pf->vsi[i]->uplink_seid == branch_seid &&
6809 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6810 i40e_vsi_release(pf->vsi[i]);
6811 }
6812 }
6813
6814 /* There's one corner case where the VEB might not have been
6815 * removed, so double check it here and remove it if needed.
6816 * This case happens if the veb was created from the debugfs
6817 * commands and no VSIs were added to it.
6818 */
6819 if (pf->veb[veb_idx])
6820 i40e_veb_release(pf->veb[veb_idx]);
6821}
6822
6823/**
6824 * i40e_veb_clear - remove veb struct
6825 * @veb: the veb to remove
6826 **/
6827static void i40e_veb_clear(struct i40e_veb *veb)
6828{
6829 if (!veb)
6830 return;
6831
6832 if (veb->pf) {
6833 struct i40e_pf *pf = veb->pf;
6834
6835 mutex_lock(&pf->switch_mutex);
6836 if (pf->veb[veb->idx] == veb)
6837 pf->veb[veb->idx] = NULL;
6838 mutex_unlock(&pf->switch_mutex);
6839 }
6840
6841 kfree(veb);
6842}
6843
6844/**
6845 * i40e_veb_release - Delete a VEB and free its resources
6846 * @veb: the VEB being removed
6847 **/
6848void i40e_veb_release(struct i40e_veb *veb)
6849{
6850 struct i40e_vsi *vsi = NULL;
6851 struct i40e_pf *pf;
6852 int i, n = 0;
6853
6854 pf = veb->pf;
6855
6856 /* find the remaining VSI and check for extras */
6857 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6858 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
6859 n++;
6860 vsi = pf->vsi[i];
6861 }
6862 }
6863 if (n != 1) {
6864 dev_info(&pf->pdev->dev,
6865 "can't remove VEB %d with %d VSIs left\n",
6866 veb->seid, n);
6867 return;
6868 }
6869
6870 /* move the remaining VSI to uplink veb */
6871 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
6872 if (veb->uplink_seid) {
6873 vsi->uplink_seid = veb->uplink_seid;
6874 if (veb->uplink_seid == pf->mac_seid)
6875 vsi->veb_idx = I40E_NO_VEB;
6876 else
6877 vsi->veb_idx = veb->veb_idx;
6878 } else {
6879 /* floating VEB */
6880 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6881 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
6882 }
6883
6884 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
6885 i40e_veb_clear(veb);
6886
6887 return;
6888}
6889
6890/**
6891 * i40e_add_veb - create the VEB in the switch
6892 * @veb: the VEB to be instantiated
6893 * @vsi: the controlling VSI
6894 **/
6895static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
6896{
56747264 6897 bool is_default = false;
e1c51b95 6898 bool is_cloud = false;
41c445ff
JB		 6899 int ret;
6900
6901 /* get a VEB from the hardware */
6902 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 6903 veb->enabled_tc, is_default,
6904 is_cloud, &veb->seid, NULL);
41c445ff
JB		 6905 if (ret) {
6906 dev_info(&veb->pf->pdev->dev,
6907 "couldn't add VEB, err %d, aq_err %d\n",
6908 ret, veb->pf->hw.aq.asq_last_status);
6909 return -EPERM;
6910 }
6911
6912 /* get statistics counter */
6913 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
6914 &veb->stats_idx, NULL, NULL, NULL);
6915 if (ret) {
6916 dev_info(&veb->pf->pdev->dev,
6917 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
6918 ret, veb->pf->hw.aq.asq_last_status);
6919 return -EPERM;
6920 }
6921 ret = i40e_veb_get_bw_info(veb);
6922 if (ret) {
6923 dev_info(&veb->pf->pdev->dev,
6924 "couldn't get VEB bw info, err %d, aq_err %d\n",
6925 ret, veb->pf->hw.aq.asq_last_status);
6926 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
6927 return -ENOENT;
6928 }
6929
6930 vsi->uplink_seid = veb->seid;
6931 vsi->veb_idx = veb->idx;
6932 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6933
6934 return 0;
6935}
6936
6937/**
6938 * i40e_veb_setup - Set up a VEB
6939 * @pf: board private structure
6940 * @flags: VEB setup flags
6941 * @uplink_seid: the switch element to link to
6942 * @vsi_seid: the initial VSI seid
6943 * @enabled_tc: Enabled TC bit-map
6944 *
6945 * This allocates the sw VEB structure and links it into the switch
6946 * It is possible and legal for this to be a duplicate of an already
6947 * existing VEB. It is also possible for both uplink and vsi seids
6948 * to be zero, in order to create a floating VEB.
6949 *
6950 * Returns pointer to the successfully allocated VEB sw struct on
6951 * success, otherwise returns NULL on failure.
6952 **/
6953struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
6954 u16 uplink_seid, u16 vsi_seid,
6955 u8 enabled_tc)
6956{
6957 struct i40e_veb *veb, *uplink_veb = NULL;
6958 int vsi_idx, veb_idx;
6959 int ret;
6960
6961 /* if one seid is 0, the other must be 0 to create a floating relay */
6962 if ((uplink_seid == 0 || vsi_seid == 0) &&
6963 (uplink_seid + vsi_seid != 0)) {
6964 dev_info(&pf->pdev->dev,
6965 "one, not both seid's are 0: uplink=%d vsi=%d\n",
6966 uplink_seid, vsi_seid);
6967 return NULL;
6968 }
6969
6970 /* make sure there is such a vsi and uplink */
6971 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
6972 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
6973 break;
6974 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
6975 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
6976 vsi_seid);
6977 return NULL;
6978 }
6979
6980 if (uplink_seid && uplink_seid != pf->mac_seid) {
6981 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6982 if (pf->veb[veb_idx] &&
6983 pf->veb[veb_idx]->seid == uplink_seid) {
6984 uplink_veb = pf->veb[veb_idx];
6985 break;
6986 }
6987 }
6988 if (!uplink_veb) {
6989 dev_info(&pf->pdev->dev,
6990 "uplink seid %d not found\n", uplink_seid);
6991 return NULL;
6992 }
6993 }
6994
6995 /* get veb sw struct */
6996 veb_idx = i40e_veb_mem_alloc(pf);
6997 if (veb_idx < 0)
6998 goto err_alloc;
6999 veb = pf->veb[veb_idx];
7000 veb->flags = flags;
7001 veb->uplink_seid = uplink_seid;
7002 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7003 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7004
7005 /* create the VEB in the switch */
7006 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7007 if (ret)
7008 goto err_veb;
7009
7010 return veb;
7011
7012err_veb:
7013 i40e_veb_clear(veb);
7014err_alloc:
7015 return NULL;
7016}
7017
7018/**
7019 * i40e_setup_pf_switch_element - set pf vars based on switch type
7020 * @pf: board private structure
7021 * @ele: element we are building info from
7022 * @num_reported: total number of elements
7023 * @printconfig: should we print the contents
7024 *
7025 * helper function to assist in extracting a few useful SEID values.
7026 **/
7027static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7028 struct i40e_aqc_switch_config_element_resp *ele,
7029 u16 num_reported, bool printconfig)
7030{
7031 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7032 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7033 u8 element_type = ele->element_type;
7034 u16 seid = le16_to_cpu(ele->seid);
7035
7036 if (printconfig)
7037 dev_info(&pf->pdev->dev,
7038 "type=%d seid=%d uplink=%d downlink=%d\n",
7039 element_type, seid, uplink_seid, downlink_seid);
7040
7041 switch (element_type) {
7042 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7043 pf->mac_seid = seid;
7044 break;
7045 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7046 /* Main VEB? */
7047 if (uplink_seid != pf->mac_seid)
7048 break;
7049 if (pf->lan_veb == I40E_NO_VEB) {
7050 int v;
7051
7052 /* find existing or else empty VEB */
7053 for (v = 0; v < I40E_MAX_VEB; v++) {
7054 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7055 pf->lan_veb = v;
7056 break;
7057 }
7058 }
7059 if (pf->lan_veb == I40E_NO_VEB) {
7060 v = i40e_veb_mem_alloc(pf);
7061 if (v < 0)
7062 break;
7063 pf->lan_veb = v;
7064 }
7065 }
7066
7067 pf->veb[pf->lan_veb]->seid = seid;
7068 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7069 pf->veb[pf->lan_veb]->pf = pf;
7070 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7071 break;
7072 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7073 if (num_reported != 1)
7074 break;
7075 /* This is immediately after a reset so we can assume this is
7076 * the PF's VSI
7077 */
7078 pf->mac_seid = uplink_seid;
7079 pf->pf_seid = downlink_seid;
7080 pf->main_vsi_seid = seid;
7081 if (printconfig)
7082 dev_info(&pf->pdev->dev,
7083 "pf_seid=%d main_vsi_seid=%d\n",
7084 pf->pf_seid, pf->main_vsi_seid);
7085 break;
7086 case I40E_SWITCH_ELEMENT_TYPE_PF:
7087 case I40E_SWITCH_ELEMENT_TYPE_VF:
7088 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7089 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7090 case I40E_SWITCH_ELEMENT_TYPE_PE:
7091 case I40E_SWITCH_ELEMENT_TYPE_PA:
7092 /* ignore these for now */
7093 break;
7094 default:
7095 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7096 element_type, seid);
7097 break;
7098 }
7099}
7100
7101/**
7102 * i40e_fetch_switch_configuration - Get switch config from firmware
7103 * @pf: board private structure
7104 * @printconfig: should we print the contents
7105 *
7106 * Get the current switch configuration from the device and
7107 * extract a few useful SEID values.
7108 **/
7109int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7110{
7111 struct i40e_aqc_get_switch_config_resp *sw_config;
7112 u16 next_seid = 0;
7113 int ret = 0;
7114 u8 *aq_buf;
7115 int i;
7116
7117 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7118 if (!aq_buf)
7119 return -ENOMEM;
7120
7121 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7122 do {
7123 u16 num_reported, num_total;
7124
7125 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7126 I40E_AQ_LARGE_BUF,
7127 &next_seid, NULL);
7128 if (ret) {
7129 dev_info(&pf->pdev->dev,
7130 "get switch config failed %d aq_err=%x\n",
7131 ret, pf->hw.aq.asq_last_status);
7132 kfree(aq_buf);
7133 return -ENOENT;
7134 }
7135
7136 num_reported = le16_to_cpu(sw_config->header.num_reported);
7137 num_total = le16_to_cpu(sw_config->header.num_total);
7138
7139 if (printconfig)
7140 dev_info(&pf->pdev->dev,
7141 "header: %d reported %d total\n",
7142 num_reported, num_total);
7143
7144 if (num_reported) {
7145 int sz = sizeof(*sw_config) * num_reported;
7146
7147 kfree(pf->sw_config);
7148 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7149 if (pf->sw_config)
7150 memcpy(pf->sw_config, sw_config, sz);
7151 }
7152
7153 for (i = 0; i < num_reported; i++) {
7154 struct i40e_aqc_switch_config_element_resp *ele =
7155 &sw_config->element[i];
7156
7157 i40e_setup_pf_switch_element(pf, ele, num_reported,
7158 printconfig);
7159 }
7160 } while (next_seid != 0);
7161
7162 kfree(aq_buf);
7163 return ret;
7164}
7165
7166/**
7167 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7168 * @pf: board private structure
bc7d338f 7169 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7170 *
7171 * Returns 0 on success, negative value on failure
7172 **/
bc7d338f 7173static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7174{
895106a5 7175 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7176 int ret;
7177
7178 /* find out what's out there already */
7179 ret = i40e_fetch_switch_configuration(pf, false);
7180 if (ret) {
7181 dev_info(&pf->pdev->dev,
7182 "couldn't fetch switch config, err %d, aq_err %d\n",
7183 ret, pf->hw.aq.asq_last_status);
7184 return ret;
7185 }
7186 i40e_pf_reset_stats(pf);
7187
7188 /* fdir VSI must happen first to be sure it gets queue 0, but only
7189 * if there is enough room for the fdir VSI
7190 */
7191 if (pf->num_lan_qps > 1)
7192 i40e_fdir_setup(pf);
7193
7194 /* first time setup */
bc7d338f 7195 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7196 struct i40e_vsi *vsi = NULL;
7197 u16 uplink_seid;
7198
7199 /* Set up the PF VSI associated with the PF's main VSI
7200 * that is already in the HW switch
7201 */
7202 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7203 uplink_seid = pf->veb[pf->lan_veb]->seid;
7204 else
7205 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7206 if (pf->lan_vsi == I40E_NO_VSI)
7207 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7208 else if (reinit)
7209 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7210 if (!vsi) {
7211 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7212 i40e_fdir_teardown(pf);
7213 return -EAGAIN;
7214 }
41c445ff
JB		 7215 } else {
7216 /* force a reset of TC and queue layout configurations */
7217 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7218 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7219 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7220 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7221 }
7222 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7223
7224 /* Setup static PF queue filter control settings */
7225 ret = i40e_setup_pf_filter_control(pf);
7226 if (ret) {
7227 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7228 ret);
7229 /* Failure here should not stop continuing other steps */
7230 }
7231
7232 /* enable RSS in the HW, even for only one queue, as the stack can use
7233 * the hash
7234 */
7235 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7236 i40e_config_rss(pf);
7237
7238 /* fill in link information and enable LSE reporting */
7239 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7240 i40e_link_event(pf);
7241
d52c20b7 7242 /* Initialize user-specific link properties */
41c445ff
JB		 7243 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7244 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7245 /* requested_mode is set in probe or by ethtool */
7246 if (!pf->fc_autoneg_status)
7247 goto no_autoneg;
7248
7249 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7250 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7251 pf->hw.fc.current_mode = I40E_FC_FULL;
7252 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7253 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7254 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7255 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7256 else
d52c20b7
JB		 7257 pf->hw.fc.current_mode = I40E_FC_NONE;
7258
7259 /* sync the flow control settings with the auto-neg values */
7260 switch (pf->hw.fc.current_mode) {
7261 case I40E_FC_FULL:
7262 txfc = 1;
7263 rxfc = 1;
7264 break;
7265 case I40E_FC_TX_PAUSE:
7266 txfc = 1;
7267 rxfc = 0;
7268 break;
7269 case I40E_FC_RX_PAUSE:
7270 txfc = 0;
7271 rxfc = 1;
7272 break;
7273 case I40E_FC_NONE:
7274 case I40E_FC_DEFAULT:
7275 txfc = 0;
7276 rxfc = 0;
7277 break;
7278 case I40E_FC_PFC:
7279 /* TBD */
7280 break;
7281 /* no default case, we have to handle all possibilities here */
7282 }
7283
7284 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7285
7286 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7287 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7288 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7289
7290 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7291
d52c20b7
JB		 7292 goto fc_complete;
7293
7294no_autoneg:
7295 /* disable L2 flow control, user can turn it on if they wish */
7296 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7297 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7298 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7299
7300fc_complete:
41c445ff
JB		 7301 return ret;
7302}
7303
7304/**
7305 * i40e_set_rss_size - helper to set rss_size
7306 * @pf: board private structure
7307 * @queues_left: how many queues
7308 */
7309static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
7310{
7311 int num_tc0;
7312
7313 num_tc0 = min_t(int, queues_left, pf->rss_size_max);
bf051a3b 7314 num_tc0 = min_t(int, num_tc0, num_online_cpus());
41c445ff
JB		 7315 num_tc0 = rounddown_pow_of_two(num_tc0);
7316
7317 return num_tc0;
7318}
7319
7320/**
7321 * i40e_determine_queue_usage - Work out queue distribution
7322 * @pf: board private structure
7323 **/
7324static void i40e_determine_queue_usage(struct i40e_pf *pf)
7325{
7326 int accum_tc_size;
7327 int queues_left;
7328
7329 pf->num_lan_qps = 0;
7330 pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
7331 accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
7332
7333 /* Find the max queues to be put into basic use. We'll always be
7334 * using TC0, whether or not DCB is running, and TC0 will get the
7335 * big RSS set.
7336 */
7337 queues_left = pf->hw.func_caps.num_tx_qp;
7338
9f52987b 7339 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
41c445ff
JB		 7340 !(pf->flags & (I40E_FLAG_RSS_ENABLED |
7341 I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
7342 (queues_left == 1)) {
7343
7344 /* one qp for PF, no queues for anything else */
7345 queues_left = 0;
7346 pf->rss_size = pf->num_lan_qps = 1;
7347
7348 /* make sure all the fancies are disabled */
7349 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 7350 I40E_FLAG_FDIR_ENABLED |
7351 I40E_FLAG_FDIR_ATR_ENABLED |
7352 I40E_FLAG_DCB_ENABLED |
7353 I40E_FLAG_SRIOV_ENABLED |
7354 I40E_FLAG_VMDQ_ENABLED);
7355
7356 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7357 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7358 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7359
7360 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7361
7362 queues_left -= pf->rss_size;
f8ff1464 7363 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7364
7365 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7366 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7367 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7368
7369 /* save num_tc_qps queues for TCs 1 thru 7 and the rest
7370 * are set up for RSS in TC0
7371 */
7372 queues_left -= accum_tc_size;
7373
7374 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7375
7376 queues_left -= pf->rss_size;
7377 if (queues_left < 0) {
7378 dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
7379 return;
7380 }
7381
f8ff1464 7382 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7383
7384 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7385 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7386 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7387
7388 queues_left -= 1; /* save 1 queue for FD */
7389
7390 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7391
7392 queues_left -= pf->rss_size;
7393 if (queues_left < 0) {
7394 dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
7395 return;
7396 }
7397
f8ff1464 7398 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7399
7400 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7401 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7402 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7403
7404 /* save 1 queue for TCs 1 thru 7,
7405 * 1 queue for flow director,
7406 * and the rest are set up for RSS in TC0
7407 */
7408 queues_left -= 1;
7409 queues_left -= accum_tc_size;
7410
7411 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7412 queues_left -= pf->rss_size;
7413 if (queues_left < 0) {
7414 dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
7415 return;
7416 }
7417
f8ff1464 7418 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7419
7420 } else {
7421 dev_info(&pf->pdev->dev,
7422 "Invalid configuration, flags=0x%08llx\n", pf->flags);
7423 return;
7424 }
7425
7426 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7427 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
7428 pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
7429 pf->num_vf_qps));
7430 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7431 }
7432
7433 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7434 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7435 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7436 (queues_left / pf->num_vmdq_qps));
7437 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7438 }
7439
f8ff1464 7440 pf->queues_left = queues_left;
41c445ff
JB		 7441 return;
7442}
7443
7444/**
7445 * i40e_setup_pf_filter_control - Setup PF static filter control
7446 * @pf: PF to be setup
7447 *
7448 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7449 * settings. If PE/FCoE are enabled then it will also set the per PF
7450 * based filter sizes required for them. It also enables Flow director,
7451 * ethertype and macvlan type filter settings for the pf.
7452 *
7453 * Returns 0 on success, negative on failure
7454 **/
7455static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7456{
7457 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7458
7459 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7460
7461 /* Flow Director is enabled */
7462 if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
7463 settings->enable_fdir = true;
7464
7465 /* Ethtype and MACVLAN filters enabled for PF */
7466 settings->enable_ethtype = true;
7467 settings->enable_macvlan = true;
7468
7469 if (i40e_set_filter_control(&pf->hw, settings))
7470 return -ENOENT;
7471
7472 return 0;
7473}
7474
7475/**
7476 * i40e_probe - Device initialization routine
7477 * @pdev: PCI device information struct
7478 * @ent: entry in i40e_pci_tbl
7479 *
7480 * i40e_probe initializes a pf identified by a pci_dev structure.
7481 * The OS initialization, configuring of the pf private structure,
7482 * and a hardware reset occur.
7483 *
7484 * Returns 0 on success, negative on failure
7485 **/
7486static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7487{
7488 struct i40e_driver_version dv;
7489 struct i40e_pf *pf;
7490 struct i40e_hw *hw;
93cd765b 7491 static u16 pfs_found;
d4dfb81a 7492 u16 link_status;
41c445ff
JB		 7493 int err = 0;
7494 u32 len;
7495
7496 err = pci_enable_device_mem(pdev);
7497 if (err)
7498 return err;
7499
7500 /* set up for high or low dma */
7501 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7502 /* coherent mask for the same size will always succeed if
7503 * dma_set_mask does
7504 */
7505 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7506 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7507 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7508 } else {
7509 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7510 err = -EIO;
7511 goto err_dma;
7512 }
7513
7514 /* set up pci connections */
7515 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7516 IORESOURCE_MEM), i40e_driver_name);
7517 if (err) {
7518 dev_info(&pdev->dev,
7519 "pci_request_selected_regions failed %d\n", err);
7520 goto err_pci_reg;
7521 }
7522
7523 pci_enable_pcie_error_reporting(pdev);
7524 pci_set_master(pdev);
7525
7526 /* Now that we have a PCI connection, we need to do the
7527 * low level device setup. This is primarily setting up
7528 * the Admin Queue structures and then querying for the
7529 * device's current profile information.
7530 */
7531 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7532 if (!pf) {
7533 err = -ENOMEM;
7534 goto err_pf_alloc;
7535 }
7536 pf->next_vsi = 0;
7537 pf->pdev = pdev;
7538 set_bit(__I40E_DOWN, &pf->state);
7539
7540 hw = &pf->hw;
7541 hw->back = pf;
7542 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7543 pci_resource_len(pdev, 0));
7544 if (!hw->hw_addr) {
7545 err = -EIO;
7546 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7547 (unsigned int)pci_resource_start(pdev, 0),
7548 (unsigned int)pci_resource_len(pdev, 0), err);
7549 goto err_ioremap;
7550 }
7551 hw->vendor_id = pdev->vendor;
7552 hw->device_id = pdev->device;
7553 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7554 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7555 hw->subsystem_device_id = pdev->subsystem_device;
7556 hw->bus.device = PCI_SLOT(pdev->devfn);
7557 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7558 pf->instance = pfs_found;
41c445ff 7559
7134f9ce
JB		 7560 /* do a special CORER for clearing PXE mode once at init */
7561 if (hw->revision_id == 0 &&
7562 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7563 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7564 i40e_flush(hw);
7565 msleep(200);
7566 pf->corer_count++;
7567
7568 i40e_clear_pxe_mode(hw);
7569 }
7570
41c445ff
JB		 7571 /* Reset here to make sure all is clean and to define PF 'n' */
7572 err = i40e_pf_reset(hw);
7573 if (err) {
7574 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7575 goto err_pf_reset;
7576 }
7577 pf->pfr_count++;
7578
7579 hw->aq.num_arq_entries = I40E_AQ_LEN;
7580 hw->aq.num_asq_entries = I40E_AQ_LEN;
7581 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7582 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7583 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7584 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7585 "%s-pf%d:misc",
7586 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7587
7588 err = i40e_init_shared_code(hw);
7589 if (err) {
7590 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7591 goto err_pf_reset;
7592 }
7593
d52c20b7
JB		 7594 /* set up a default setting for link flow control */
7595 pf->hw.fc.requested_mode = I40E_FC_NONE;
7596
41c445ff
JB		 7597 err = i40e_init_adminq(hw);
7598 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7599 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7600 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7601 dev_info(&pdev->dev,
7602 "warning: NVM version not supported, supported version: %02x.%02x\n",
7603 I40E_CURRENT_NVM_VERSION_HI,
7604 I40E_CURRENT_NVM_VERSION_LO);
7605 }
41c445ff
JB		 7606 if (err) {
7607 dev_info(&pdev->dev,
7608 "init_adminq failed: %d expecting API %02x.%02x\n",
7609 err,
7610 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7611 goto err_pf_reset;
7612 }
7613
7614 err = i40e_get_capabilities(pf);
7615 if (err)
7616 goto err_adminq_setup;
7617
7618 err = i40e_sw_init(pf);
7619 if (err) {
7620 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7621 goto err_sw_init;
7622 }
7623
7624 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7625 hw->func_caps.num_rx_qp,
7626 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7627 if (err) {
7628 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7629 goto err_init_lan_hmc;
7630 }
7631
7632 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7633 if (err) {
7634 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7635 err = -ENOENT;
7636 goto err_configure_lan_hmc;
7637 }
7638
7639 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 7640 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 7641 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7642 err = -EIO;
7643 goto err_mac_addr;
7644 }
7645 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7646 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7647
7648 pci_set_drvdata(pdev, pf);
7649 pci_save_state(pdev);
7650
7651 /* set up periodic task facility */
7652 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7653 pf->service_timer_period = HZ;
7654
7655 INIT_WORK(&pf->service_task, i40e_service_task);
7656 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
7657 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
7658 pf->link_check_timeout = jiffies;
7659
8e2773ae
SN		 7660 /* WoL defaults to disabled */
7661 pf->wol_en = false;
7662 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
7663
41c445ff
JB		 7664 /* set up the main switch operations */
7665 i40e_determine_queue_usage(pf);
7666 i40e_init_interrupt_scheme(pf);
7667
7668 /* Set up the *vsi struct based on the number of VSIs in the HW,
7669 * and set up our local tracking of the MAIN PF vsi.
7670 */
7671 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
7672 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 7673 if (!pf->vsi) {
7674 err = -ENOMEM;
41c445ff 7675 goto err_switch_setup;
ed87ac09 7676 }
41c445ff 7677
bc7d338f 7678 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 7679 if (err) {
7680 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
7681 goto err_vsis;
7682 }
7683
7684 /* The main driver is (mostly) up and happy. We need to set this state
7685 * before setting up the misc vector or we get a race and the vector
7686 * ends up disabled forever.
7687 */
7688 clear_bit(__I40E_DOWN, &pf->state);
7689
7690 /* In case of MSIX we are going to setup the misc vector right here
7691 * to handle admin queue events etc. In case of legacy and MSI
7692 * the misc functionality and queue processing is combined in
7693 * the same vector and that gets setup at open.
7694 */
7695 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7696 err = i40e_setup_misc_vector(pf);
7697 if (err) {
7698 dev_info(&pdev->dev,
7699 "setup of misc vector failed: %d\n", err);
7700 goto err_vsis;
7701 }
7702 }
7703
7704 /* prep for VF support */
7705 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7706 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
7707 u32 val;
7708
7709 /* disable link interrupts for VFs */
7710 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
7711 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
7712 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
7713 i40e_flush(hw);
7714 }
7715
93cd765b
ASJ		 7716 pfs_found++;
7717
41c445ff
JB		 7718 i40e_dbg_pf_init(pf);
7719
7720 /* tell the firmware that we're starting */
7721 dv.major_version = DRV_VERSION_MAJOR;
7722 dv.minor_version = DRV_VERSION_MINOR;
7723 dv.build_version = DRV_VERSION_BUILD;
7724 dv.subbuild_version = 0;
7725 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
7726
7727 /* since everything's happy, start the service_task timer */
7728 mod_timer(&pf->service_timer,
7729 round_jiffies(jiffies + pf->service_timer_period));
7730
d4dfb81a
CS		 7731 /* Get the negotiated link width and speed from PCI config space */
7732 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
7733
7734 i40e_set_pci_config_data(hw, link_status);
7735
7736 dev_info(&pdev->dev, "PCI Express: %s %s\n",
7737 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
7738 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
7739 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
7740 "Unknown"),
7741 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
7742 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
7743 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
7744 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
7745 "Unknown"));
7746
7747 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
7748 hw->bus.speed < i40e_bus_speed_8000) {
7749 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
7750 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
7751 }
7752
41c445ff
JB		 7753 return 0;
7754
7755 /* Unwind what we've done if something failed in the setup */
7756err_vsis:
7757 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 7758 i40e_clear_interrupt_scheme(pf);
7759 kfree(pf->vsi);
04b03013
SN		 7760err_switch_setup:
7761 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 7762 del_timer_sync(&pf->service_timer);
7763err_mac_addr:
7764err_configure_lan_hmc:
7765 (void)i40e_shutdown_lan_hmc(hw);
7766err_init_lan_hmc:
7767 kfree(pf->qp_pile);
7768 kfree(pf->irq_pile);
7769err_sw_init:
7770err_adminq_setup:
7771 (void)i40e_shutdown_adminq(hw);
7772err_pf_reset:
7773 iounmap(hw->hw_addr);
7774err_ioremap:
7775 kfree(pf);
7776err_pf_alloc:
7777 pci_disable_pcie_error_reporting(pdev);
7778 pci_release_selected_regions(pdev,
7779 pci_select_bars(pdev, IORESOURCE_MEM));
7780err_pci_reg:
7781err_dma:
7782 pci_disable_device(pdev);
7783 return err;
7784}
7785
7786/**
7787 * i40e_remove - Device removal routine
7788 * @pdev: PCI device information struct
7789 *
7790 * i40e_remove is called by the PCI subsystem to alert the driver
7791 * that is should release a PCI device. This could be caused by a
7792 * Hot-Plug event, or because the driver is going to be removed from
7793 * memory.
7794 **/
7795static void i40e_remove(struct pci_dev *pdev)
7796{
7797 struct i40e_pf *pf = pci_get_drvdata(pdev);
7798 i40e_status ret_code;
7799 u32 reg;
7800 int i;
7801
7802 i40e_dbg_pf_exit(pf);
7803
7804 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7805 i40e_free_vfs(pf);
7806 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
7807 }
7808
7809 /* no more scheduling of any task */
7810 set_bit(__I40E_DOWN, &pf->state);
7811 del_timer_sync(&pf->service_timer);
7812 cancel_work_sync(&pf->service_task);
7813
7814 i40e_fdir_teardown(pf);
7815
7816 /* If there is a switch structure or any orphans, remove them.
7817 * This will leave only the PF's VSI remaining.
7818 */
7819 for (i = 0; i < I40E_MAX_VEB; i++) {
7820 if (!pf->veb[i])
7821 continue;
7822
7823 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
7824 pf->veb[i]->uplink_seid == 0)
7825 i40e_switch_branch_release(pf->veb[i]);
7826 }
7827
7828 /* Now we can shutdown the PF's VSI, just before we kill
7829 * adminq and hmc.
7830 */
7831 if (pf->vsi[pf->lan_vsi])
7832 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
7833
7834 i40e_stop_misc_vector(pf);
7835 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7836 synchronize_irq(pf->msix_entries[0].vector);
7837 free_irq(pf->msix_entries[0].vector, pf);
7838 }
7839
7840 /* shutdown and destroy the HMC */
7841 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
7842 if (ret_code)
7843 dev_warn(&pdev->dev,
7844 "Failed to destroy the HMC resources: %d\n", ret_code);
7845
7846 /* shutdown the adminq */
41c445ff
JB		 7847 ret_code = i40e_shutdown_adminq(&pf->hw);
7848 if (ret_code)
7849 dev_warn(&pdev->dev,
7850 "Failed to destroy the Admin Queue resources: %d\n",
7851 ret_code);
7852
7853 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
7854 i40e_clear_interrupt_scheme(pf);
7855 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7856 if (pf->vsi[i]) {
7857 i40e_vsi_clear_rings(pf->vsi[i]);
7858 i40e_vsi_clear(pf->vsi[i]);
7859 pf->vsi[i] = NULL;
7860 }
7861 }
7862
7863 for (i = 0; i < I40E_MAX_VEB; i++) {
7864 kfree(pf->veb[i]);
7865 pf->veb[i] = NULL;
7866 }
7867
7868 kfree(pf->qp_pile);
7869 kfree(pf->irq_pile);
7870 kfree(pf->sw_config);
7871 kfree(pf->vsi);
7872
7873 /* force a PF reset to clean anything leftover */
7874 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
7875 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7876 i40e_flush(&pf->hw);
7877
7878 iounmap(pf->hw.hw_addr);
7879 kfree(pf);
7880 pci_release_selected_regions(pdev,
7881 pci_select_bars(pdev, IORESOURCE_MEM));
7882
7883 pci_disable_pcie_error_reporting(pdev);
7884 pci_disable_device(pdev);
7885}
7886
7887/**
7888 * i40e_pci_error_detected - warning that something funky happened in PCI land
7889 * @pdev: PCI device information struct
7890 *
7891 * Called to warn that something happened and the error handling steps
7892 * are in progress. Allows the driver to quiesce things, be ready for
7893 * remediation.
7894 **/
7895static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
7896 enum pci_channel_state error)
7897{
7898 struct i40e_pf *pf = pci_get_drvdata(pdev);
7899
7900 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
7901
7902 /* shutdown all operations */
9007bccd
SN		 7903 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
7904 rtnl_lock();
7905 i40e_prep_for_reset(pf);
7906 rtnl_unlock();
7907 }
41c445ff
JB		 7908
7909 /* Request a slot reset */
7910 return PCI_ERS_RESULT_NEED_RESET;
7911}
7912
7913/**
7914 * i40e_pci_error_slot_reset - a PCI slot reset just happened
7915 * @pdev: PCI device information struct
7916 *
7917 * Called to find if the driver can work with the device now that
7918 * the pci slot has been reset. If a basic connection seems good
7919 * (registers are readable and have sane content) then return a
7920 * happy little PCI_ERS_RESULT_xxx.
7921 **/
7922static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
7923{
7924 struct i40e_pf *pf = pci_get_drvdata(pdev);
7925 pci_ers_result_t result;
7926 int err;
7927 u32 reg;
7928
7929 dev_info(&pdev->dev, "%s\n", __func__);
7930 if (pci_enable_device_mem(pdev)) {
7931 dev_info(&pdev->dev,
7932 "Cannot re-enable PCI device after reset.\n");
7933 result = PCI_ERS_RESULT_DISCONNECT;
7934 } else {
7935 pci_set_master(pdev);
7936 pci_restore_state(pdev);
7937 pci_save_state(pdev);
7938 pci_wake_from_d3(pdev, false);
7939
7940 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7941 if (reg == 0)
7942 result = PCI_ERS_RESULT_RECOVERED;
7943 else
7944 result = PCI_ERS_RESULT_DISCONNECT;
7945 }
7946
7947 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7948 if (err) {
7949 dev_info(&pdev->dev,
7950 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7951 err);
7952 /* non-fatal, continue */
7953 }
7954
7955 return result;
7956}
7957
7958/**
7959 * i40e_pci_error_resume - restart operations after PCI error recovery
7960 * @pdev: PCI device information struct
7961 *
7962 * Called to allow the driver to bring things back up after PCI error
7963 * and/or reset recovery has finished.
7964 **/
7965static void i40e_pci_error_resume(struct pci_dev *pdev)
7966{
7967 struct i40e_pf *pf = pci_get_drvdata(pdev);
7968
7969 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 7970 if (test_bit(__I40E_SUSPENDED, &pf->state))
7971 return;
7972
7973 rtnl_lock();
41c445ff 7974 i40e_handle_reset_warning(pf);
9007bccd
SN		 7975 rtnl_lock();
7976}
7977
7978/**
7979 * i40e_shutdown - PCI callback for shutting down
7980 * @pdev: PCI device information struct
7981 **/
7982static void i40e_shutdown(struct pci_dev *pdev)
7983{
7984 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 7985 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 7986
7987 set_bit(__I40E_SUSPENDED, &pf->state);
7988 set_bit(__I40E_DOWN, &pf->state);
7989 rtnl_lock();
7990 i40e_prep_for_reset(pf);
7991 rtnl_unlock();
7992
8e2773ae
SN		 7993 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
7994 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
7995
9007bccd 7996 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 7997 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 7998 pci_set_power_state(pdev, PCI_D3hot);
7999 }
8000}
8001
8002#ifdef CONFIG_PM
8003/**
8004 * i40e_suspend - PCI callback for moving to D3
8005 * @pdev: PCI device information struct
8006 **/
8007static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8008{
8009 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8010 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8011
8012 set_bit(__I40E_SUSPENDED, &pf->state);
8013 set_bit(__I40E_DOWN, &pf->state);
8014 rtnl_lock();
8015 i40e_prep_for_reset(pf);
8016 rtnl_unlock();
8017
8e2773ae
SN		 8018 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8019 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8020
8021 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8022 pci_set_power_state(pdev, PCI_D3hot);
8023
8024 return 0;
41c445ff
JB		 8025}
8026
9007bccd
SN		 8027/**
8028 * i40e_resume - PCI callback for waking up from D3
8029 * @pdev: PCI device information struct
8030 **/
8031static int i40e_resume(struct pci_dev *pdev)
8032{
8033 struct i40e_pf *pf = pci_get_drvdata(pdev);
8034 u32 err;
8035
8036 pci_set_power_state(pdev, PCI_D0);
8037 pci_restore_state(pdev);
8038 /* pci_restore_state() clears dev->state_saves, so
8039 * call pci_save_state() again to restore it.
8040 */
8041 pci_save_state(pdev);
8042
8043 err = pci_enable_device_mem(pdev);
8044 if (err) {
8045 dev_err(&pdev->dev,
8046 "%s: Cannot enable PCI device from suspend\n",
8047 __func__);
8048 return err;
8049 }
8050 pci_set_master(pdev);
8051
8052 /* no wakeup events while running */
8053 pci_wake_from_d3(pdev, false);
8054
8055 /* handling the reset will rebuild the device state */
8056 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8057 clear_bit(__I40E_DOWN, &pf->state);
8058 rtnl_lock();
8059 i40e_reset_and_rebuild(pf, false);
8060 rtnl_unlock();
8061 }
8062
8063 return 0;
8064}
8065
8066#endif
41c445ff
JB		 8067static const struct pci_error_handlers i40e_err_handler = {
8068 .error_detected = i40e_pci_error_detected,
8069 .slot_reset = i40e_pci_error_slot_reset,
8070 .resume = i40e_pci_error_resume,
8071};
8072
8073static struct pci_driver i40e_driver = {
8074 .name = i40e_driver_name,
8075 .id_table = i40e_pci_tbl,
8076 .probe = i40e_probe,
8077 .remove = i40e_remove,
9007bccd
SN		 8078#ifdef CONFIG_PM
8079 .suspend = i40e_suspend,
8080 .resume = i40e_resume,
8081#endif
8082 .shutdown = i40e_shutdown,
41c445ff
JB		 8083 .err_handler = &i40e_err_handler,
8084 .sriov_configure = i40e_pci_sriov_configure,
8085};
8086
8087/**
8088 * i40e_init_module - Driver registration routine
8089 *
8090 * i40e_init_module is the first routine called when the driver is
8091 * loaded. All it does is register with the PCI subsystem.
8092 **/
8093static int __init i40e_init_module(void)
8094{
8095 pr_info("%s: %s - version %s\n", i40e_driver_name,
8096 i40e_driver_string, i40e_driver_version_str);
8097 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8098 i40e_dbg_init();
8099 return pci_register_driver(&i40e_driver);
8100}
8101module_init(i40e_init_module);
8102
8103/**
8104 * i40e_exit_module - Driver exit cleanup routine
8105 *
8106 * i40e_exit_module is called just before the driver is removed
8107 * from memory.
8108 **/
8109static void __exit i40e_exit_module(void)
8110{
8111 pci_unregister_driver(&i40e_driver);
8112 i40e_dbg_exit();
8113}
8114module_exit(i40e_exit_module);
Linux kernel - Deliverables
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