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i40e: Leave debug_mask cleared at init
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
2818ccd9 4 * Copyright(c) 2013 - 2016 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
b499ffb0
SV		 27#include <linux/etherdevice.h>
28#include <linux/of_net.h>
29#include <linux/pci.h>
30
41c445ff
JB		 31/* Local includes */
32#include "i40e.h"
4eb3f768 33#include "i40e_diag.h"
6a899024 34#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 35#include <net/vxlan.h>
36#endif
6a899024
SA		 37#if IS_ENABLED(CONFIG_GENEVE)
38#include <net/geneve.h>
39#endif
41c445ff
JB		 40
41const char i40e_driver_name[] = "i40e";
42static const char i40e_driver_string[] =
43 "Intel(R) Ethernet Connection XL710 Network Driver";
44
45#define DRV_KERN "-k"
46
e8e724db 47#define DRV_VERSION_MAJOR 1
50f26a50 48#define DRV_VERSION_MINOR 5
066439ce 49#define DRV_VERSION_BUILD 2
41c445ff
JB		 50#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
51 __stringify(DRV_VERSION_MINOR) "." \
52 __stringify(DRV_VERSION_BUILD) DRV_KERN
53const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 54static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 55
56/* a bit of forward declarations */
57static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
58static void i40e_handle_reset_warning(struct i40e_pf *pf);
59static int i40e_add_vsi(struct i40e_vsi *vsi);
60static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 61static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 62static int i40e_setup_misc_vector(struct i40e_pf *pf);
63static void i40e_determine_queue_usage(struct i40e_pf *pf);
64static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 65static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
66 u16 rss_table_size, u16 rss_size);
cbf61325 67static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 68static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 69
70/* i40e_pci_tbl - PCI Device ID Table
71 *
72 * Last entry must be all 0s
73 *
74 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
75 * Class, Class Mask, private data (not used) }
76 */
9baa3c34 77static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
ab60085e
SN		 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
35dae51d
ASJ		 88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
87e6c1d7
ASJ		 90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
91 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
92 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
d6bf58c2 93 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},
48a3b512
SN		 94 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
95 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 96 /* required last entry */
97 {0, }
98};
99MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
100
101#define I40E_MAX_VF_COUNT 128
102static int debug = -1;
103module_param(debug, int, 0);
104MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
105
106MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
107MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
108MODULE_LICENSE("GPL");
109MODULE_VERSION(DRV_VERSION);
110
2803b16c
JB		 111static struct workqueue_struct *i40e_wq;
112
41c445ff
JB		 113/**
114 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to fill out
117 * @size: size of memory requested
118 * @alignment: what to align the allocation to
119 **/
120int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
121 u64 size, u32 alignment)
122{
123 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
124
125 mem->size = ALIGN(size, alignment);
126 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
127 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 128 if (!mem->va)
129 return -ENOMEM;
41c445ff 130
93bc73b8 131 return 0;
41c445ff
JB		 132}
133
134/**
135 * i40e_free_dma_mem_d - OS specific memory free for shared code
136 * @hw: pointer to the HW structure
137 * @mem: ptr to mem struct to free
138 **/
139int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
140{
141 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
142
143 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
144 mem->va = NULL;
145 mem->pa = 0;
146 mem->size = 0;
147
148 return 0;
149}
150
151/**
152 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
153 * @hw: pointer to the HW structure
154 * @mem: ptr to mem struct to fill out
155 * @size: size of memory requested
156 **/
157int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
158 u32 size)
159{
160 mem->size = size;
161 mem->va = kzalloc(size, GFP_KERNEL);
162
93bc73b8
JB		 163 if (!mem->va)
164 return -ENOMEM;
41c445ff 165
93bc73b8 166 return 0;
41c445ff
JB		 167}
168
169/**
170 * i40e_free_virt_mem_d - OS specific memory free for shared code
171 * @hw: pointer to the HW structure
172 * @mem: ptr to mem struct to free
173 **/
174int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
175{
176 /* it's ok to kfree a NULL pointer */
177 kfree(mem->va);
178 mem->va = NULL;
179 mem->size = 0;
180
181 return 0;
182}
183
184/**
185 * i40e_get_lump - find a lump of free generic resource
186 * @pf: board private structure
187 * @pile: the pile of resource to search
188 * @needed: the number of items needed
189 * @id: an owner id to stick on the items assigned
190 *
191 * Returns the base item index of the lump, or negative for error
192 *
193 * The search_hint trick and lack of advanced fit-finding only work
194 * because we're highly likely to have all the same size lump requests.
195 * Linear search time and any fragmentation should be minimal.
196 **/
197static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
198 u16 needed, u16 id)
199{
200 int ret = -ENOMEM;
ddf434ac 201 int i, j;
41c445ff
JB		 202
203 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
204 dev_info(&pf->pdev->dev,
205 "param err: pile=%p needed=%d id=0x%04x\n",
206 pile, needed, id);
207 return -EINVAL;
208 }
209
210 /* start the linear search with an imperfect hint */
211 i = pile->search_hint;
ddf434ac 212 while (i < pile->num_entries) {
41c445ff
JB		 213 /* skip already allocated entries */
214 if (pile->list[i] & I40E_PILE_VALID_BIT) {
215 i++;
216 continue;
217 }
218
219 /* do we have enough in this lump? */
220 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
221 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
222 break;
223 }
224
225 if (j == needed) {
226 /* there was enough, so assign it to the requestor */
227 for (j = 0; j < needed; j++)
228 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
229 ret = i;
230 pile->search_hint = i + j;
ddf434ac 231 break;
41c445ff 232 }
6995b36c
JB		 233
234 /* not enough, so skip over it and continue looking */
235 i += j;
41c445ff
JB		 236 }
237
238 return ret;
239}
240
241/**
242 * i40e_put_lump - return a lump of generic resource
243 * @pile: the pile of resource to search
244 * @index: the base item index
245 * @id: the owner id of the items assigned
246 *
247 * Returns the count of items in the lump
248 **/
249static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
250{
251 int valid_id = (id | I40E_PILE_VALID_BIT);
252 int count = 0;
253 int i;
254
255 if (!pile || index >= pile->num_entries)
256 return -EINVAL;
257
258 for (i = index;
259 i < pile->num_entries && pile->list[i] == valid_id;
260 i++) {
261 pile->list[i] = 0;
262 count++;
263 }
264
265 if (count && index < pile->search_hint)
266 pile->search_hint = index;
267
268 return count;
269}
270
fdf0e0bf
ASJ		 271/**
272 * i40e_find_vsi_from_id - searches for the vsi with the given id
273 * @pf - the pf structure to search for the vsi
274 * @id - id of the vsi it is searching for
275 **/
276struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
277{
278 int i;
279
280 for (i = 0; i < pf->num_alloc_vsi; i++)
281 if (pf->vsi[i] && (pf->vsi[i]->id == id))
282 return pf->vsi[i];
283
284 return NULL;
285}
286
41c445ff
JB		 287/**
288 * i40e_service_event_schedule - Schedule the service task to wake up
289 * @pf: board private structure
290 *
291 * If not already scheduled, this puts the task into the work queue
292 **/
e3219ce6 293void i40e_service_event_schedule(struct i40e_pf *pf)
41c445ff
JB		 294{
295 if (!test_bit(__I40E_DOWN, &pf->state) &&
296 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
297 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
2803b16c 298 queue_work(i40e_wq, &pf->service_task);
41c445ff
JB		 299}
300
301/**
302 * i40e_tx_timeout - Respond to a Tx Hang
303 * @netdev: network interface device structure
304 *
305 * If any port has noticed a Tx timeout, it is likely that the whole
306 * device is munged, not just the one netdev port, so go for the full
307 * reset.
308 **/
38e00438
VD		 309#ifdef I40E_FCOE
310void i40e_tx_timeout(struct net_device *netdev)
311#else
41c445ff 312static void i40e_tx_timeout(struct net_device *netdev)
38e00438 313#endif
41c445ff
JB		 314{
315 struct i40e_netdev_priv *np = netdev_priv(netdev);
316 struct i40e_vsi *vsi = np->vsi;
317 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 318 struct i40e_ring *tx_ring = NULL;
319 unsigned int i, hung_queue = 0;
320 u32 head, val;
41c445ff
JB		 321
322 pf->tx_timeout_count++;
323
b03a8c1f
KP		 324 /* find the stopped queue the same way the stack does */
325 for (i = 0; i < netdev->num_tx_queues; i++) {
326 struct netdev_queue *q;
327 unsigned long trans_start;
328
329 q = netdev_get_tx_queue(netdev, i);
330 trans_start = q->trans_start ? : netdev->trans_start;
331 if (netif_xmit_stopped(q) &&
332 time_after(jiffies,
333 (trans_start + netdev->watchdog_timeo))) {
334 hung_queue = i;
335 break;
336 }
337 }
338
339 if (i == netdev->num_tx_queues) {
340 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
341 } else {
342 /* now that we have an index, find the tx_ring struct */
343 for (i = 0; i < vsi->num_queue_pairs; i++) {
344 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
345 if (hung_queue ==
346 vsi->tx_rings[i]->queue_index) {
347 tx_ring = vsi->tx_rings[i];
348 break;
349 }
350 }
351 }
352 }
353
41c445ff 354 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 355 pf->tx_timeout_recovery_level = 1; /* reset after some time */
356 else if (time_before(jiffies,
357 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
358 return; /* don't do any new action before the next timeout */
359
360 if (tx_ring) {
361 head = i40e_get_head(tx_ring);
362 /* Read interrupt register */
363 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
364 val = rd32(&pf->hw,
365 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
366 tx_ring->vsi->base_vector - 1));
367 else
368 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
369
370 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
371 vsi->seid, hung_queue, tx_ring->next_to_clean,
372 head, tx_ring->next_to_use,
373 readl(tx_ring->tail), val);
374 }
375
41c445ff 376 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 377 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
378 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 379
380 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 381 case 1:
382 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
383 break;
384 case 2:
385 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
386 break;
387 case 3:
388 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
389 break;
390 default:
391 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 392 break;
393 }
b03a8c1f 394
41c445ff
JB		 395 i40e_service_event_schedule(pf);
396 pf->tx_timeout_recovery_level++;
397}
398
399/**
400 * i40e_release_rx_desc - Store the new tail and head values
401 * @rx_ring: ring to bump
402 * @val: new head index
403 **/
404static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
405{
406 rx_ring->next_to_use = val;
407
408 /* Force memory writes to complete before letting h/w
409 * know there are new descriptors to fetch. (Only
410 * applicable for weak-ordered memory model archs,
411 * such as IA-64).
412 */
413 wmb();
414 writel(val, rx_ring->tail);
415}
416
417/**
418 * i40e_get_vsi_stats_struct - Get System Network Statistics
419 * @vsi: the VSI we care about
420 *
421 * Returns the address of the device statistics structure.
422 * The statistics are actually updated from the service task.
423 **/
424struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
425{
426 return &vsi->net_stats;
427}
428
429/**
430 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
431 * @netdev: network interface device structure
432 *
433 * Returns the address of the device statistics structure.
434 * The statistics are actually updated from the service task.
435 **/
38e00438
VD		 436#ifdef I40E_FCOE
437struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
438 struct net_device *netdev,
439 struct rtnl_link_stats64 *stats)
440#else
41c445ff
JB		 441static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
442 struct net_device *netdev,
980e9b11 443 struct rtnl_link_stats64 *stats)
38e00438 444#endif
41c445ff
JB		 445{
446 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 447 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 448 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 449 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
450 int i;
451
bc7d338f
ASJ		 452 if (test_bit(__I40E_DOWN, &vsi->state))
453 return stats;
454
3c325ced
JB		 455 if (!vsi->tx_rings)
456 return stats;
457
980e9b11
AD		 458 rcu_read_lock();
459 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 460 u64 bytes, packets;
461 unsigned int start;
462
463 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
464 if (!tx_ring)
465 continue;
466
467 do {
57a7744e 468 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 469 packets = tx_ring->stats.packets;
470 bytes = tx_ring->stats.bytes;
57a7744e 471 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 472
473 stats->tx_packets += packets;
474 stats->tx_bytes += bytes;
475 rx_ring = &tx_ring[1];
476
477 do {
57a7744e 478 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 479 packets = rx_ring->stats.packets;
480 bytes = rx_ring->stats.bytes;
57a7744e 481 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 482
980e9b11
AD		 483 stats->rx_packets += packets;
484 stats->rx_bytes += bytes;
485 }
486 rcu_read_unlock();
487
a5282f44 488 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 489 stats->multicast = vsi_stats->multicast;
490 stats->tx_errors = vsi_stats->tx_errors;
491 stats->tx_dropped = vsi_stats->tx_dropped;
492 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 493 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 494 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
495 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 496
980e9b11 497 return stats;
41c445ff
JB		 498}
499
500/**
501 * i40e_vsi_reset_stats - Resets all stats of the given vsi
502 * @vsi: the VSI to have its stats reset
503 **/
504void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
505{
506 struct rtnl_link_stats64 *ns;
507 int i;
508
509 if (!vsi)
510 return;
511
512 ns = i40e_get_vsi_stats_struct(vsi);
513 memset(ns, 0, sizeof(*ns));
514 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
515 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
516 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 517 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 518 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 519 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 520 sizeof(vsi->rx_rings[i]->stats));
6995b36c 521 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 522 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 523 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 524 sizeof(vsi->tx_rings[i]->stats));
525 memset(&vsi->tx_rings[i]->tx_stats, 0,
526 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 527 }
8e9dca53 528 }
41c445ff
JB		 529 vsi->stat_offsets_loaded = false;
530}
531
532/**
b40c82e6 533 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 534 * @pf: the PF to be reset
535 **/
536void i40e_pf_reset_stats(struct i40e_pf *pf)
537{
e91fdf76
SN		 538 int i;
539
41c445ff
JB		 540 memset(&pf->stats, 0, sizeof(pf->stats));
541 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
542 pf->stat_offsets_loaded = false;
e91fdf76
SN		 543
544 for (i = 0; i < I40E_MAX_VEB; i++) {
545 if (pf->veb[i]) {
546 memset(&pf->veb[i]->stats, 0,
547 sizeof(pf->veb[i]->stats));
548 memset(&pf->veb[i]->stats_offsets, 0,
549 sizeof(pf->veb[i]->stats_offsets));
550 pf->veb[i]->stat_offsets_loaded = false;
551 }
552 }
41c445ff
JB		 553}
554
555/**
556 * i40e_stat_update48 - read and update a 48 bit stat from the chip
557 * @hw: ptr to the hardware info
558 * @hireg: the high 32 bit reg to read
559 * @loreg: the low 32 bit reg to read
560 * @offset_loaded: has the initial offset been loaded yet
561 * @offset: ptr to current offset value
562 * @stat: ptr to the stat
563 *
564 * Since the device stats are not reset at PFReset, they likely will not
565 * be zeroed when the driver starts. We'll save the first values read
566 * and use them as offsets to be subtracted from the raw values in order
567 * to report stats that count from zero. In the process, we also manage
568 * the potential roll-over.
569 **/
570static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
571 bool offset_loaded, u64 *offset, u64 *stat)
572{
573 u64 new_data;
574
ab60085e 575 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 576 new_data = rd32(hw, loreg);
577 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
578 } else {
579 new_data = rd64(hw, loreg);
580 }
581 if (!offset_loaded)
582 *offset = new_data;
583 if (likely(new_data >= *offset))
584 *stat = new_data - *offset;
585 else
41a1d04b 586 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 587 *stat &= 0xFFFFFFFFFFFFULL;
588}
589
590/**
591 * i40e_stat_update32 - read and update a 32 bit stat from the chip
592 * @hw: ptr to the hardware info
593 * @reg: the hw reg to read
594 * @offset_loaded: has the initial offset been loaded yet
595 * @offset: ptr to current offset value
596 * @stat: ptr to the stat
597 **/
598static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
599 bool offset_loaded, u64 *offset, u64 *stat)
600{
601 u32 new_data;
602
603 new_data = rd32(hw, reg);
604 if (!offset_loaded)
605 *offset = new_data;
606 if (likely(new_data >= *offset))
607 *stat = (u32)(new_data - *offset);
608 else
41a1d04b 609 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 610}
611
612/**
613 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
614 * @vsi: the VSI to be updated
615 **/
616void i40e_update_eth_stats(struct i40e_vsi *vsi)
617{
618 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
619 struct i40e_pf *pf = vsi->back;
620 struct i40e_hw *hw = &pf->hw;
621 struct i40e_eth_stats *oes;
622 struct i40e_eth_stats *es; /* device's eth stats */
623
624 es = &vsi->eth_stats;
625 oes = &vsi->eth_stats_offsets;
626
627 /* Gather up the stats that the hw collects */
628 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
629 vsi->stat_offsets_loaded,
630 &oes->tx_errors, &es->tx_errors);
631 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
632 vsi->stat_offsets_loaded,
633 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 634 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
635 vsi->stat_offsets_loaded,
636 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
637 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 640
641 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
642 I40E_GLV_GORCL(stat_idx),
643 vsi->stat_offsets_loaded,
644 &oes->rx_bytes, &es->rx_bytes);
645 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
646 I40E_GLV_UPRCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->rx_unicast, &es->rx_unicast);
649 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
650 I40E_GLV_MPRCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->rx_multicast, &es->rx_multicast);
653 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
654 I40E_GLV_BPRCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->rx_broadcast, &es->rx_broadcast);
657
658 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
659 I40E_GLV_GOTCL(stat_idx),
660 vsi->stat_offsets_loaded,
661 &oes->tx_bytes, &es->tx_bytes);
662 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
663 I40E_GLV_UPTCL(stat_idx),
664 vsi->stat_offsets_loaded,
665 &oes->tx_unicast, &es->tx_unicast);
666 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
667 I40E_GLV_MPTCL(stat_idx),
668 vsi->stat_offsets_loaded,
669 &oes->tx_multicast, &es->tx_multicast);
670 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
671 I40E_GLV_BPTCL(stat_idx),
672 vsi->stat_offsets_loaded,
673 &oes->tx_broadcast, &es->tx_broadcast);
674 vsi->stat_offsets_loaded = true;
675}
676
677/**
678 * i40e_update_veb_stats - Update Switch component statistics
679 * @veb: the VEB being updated
680 **/
681static void i40e_update_veb_stats(struct i40e_veb *veb)
682{
683 struct i40e_pf *pf = veb->pf;
684 struct i40e_hw *hw = &pf->hw;
685 struct i40e_eth_stats *oes;
686 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 687 struct i40e_veb_tc_stats *veb_oes;
688 struct i40e_veb_tc_stats *veb_es;
689 int i, idx = 0;
41c445ff
JB		 690
691 idx = veb->stats_idx;
692 es = &veb->stats;
693 oes = &veb->stats_offsets;
fe860afb
NP		 694 veb_es = &veb->tc_stats;
695 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 696
697 /* Gather up the stats that the hw collects */
698 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
699 veb->stat_offsets_loaded,
700 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 701 if (hw->revision_id > 0)
702 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
703 veb->stat_offsets_loaded,
704 &oes->rx_unknown_protocol,
705 &es->rx_unknown_protocol);
41c445ff
JB		 706 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->rx_bytes, &es->rx_bytes);
709 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
710 veb->stat_offsets_loaded,
711 &oes->rx_unicast, &es->rx_unicast);
712 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
713 veb->stat_offsets_loaded,
714 &oes->rx_multicast, &es->rx_multicast);
715 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
716 veb->stat_offsets_loaded,
717 &oes->rx_broadcast, &es->rx_broadcast);
718
719 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
720 veb->stat_offsets_loaded,
721 &oes->tx_bytes, &es->tx_bytes);
722 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
723 veb->stat_offsets_loaded,
724 &oes->tx_unicast, &es->tx_unicast);
725 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
726 veb->stat_offsets_loaded,
727 &oes->tx_multicast, &es->tx_multicast);
728 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
729 veb->stat_offsets_loaded,
730 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 731 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
732 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
733 I40E_GLVEBTC_RPCL(i, idx),
734 veb->stat_offsets_loaded,
735 &veb_oes->tc_rx_packets[i],
736 &veb_es->tc_rx_packets[i]);
737 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
738 I40E_GLVEBTC_RBCL(i, idx),
739 veb->stat_offsets_loaded,
740 &veb_oes->tc_rx_bytes[i],
741 &veb_es->tc_rx_bytes[i]);
742 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
743 I40E_GLVEBTC_TPCL(i, idx),
744 veb->stat_offsets_loaded,
745 &veb_oes->tc_tx_packets[i],
746 &veb_es->tc_tx_packets[i]);
747 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
748 I40E_GLVEBTC_TBCL(i, idx),
749 veb->stat_offsets_loaded,
750 &veb_oes->tc_tx_bytes[i],
751 &veb_es->tc_tx_bytes[i]);
752 }
41c445ff
JB		 753 veb->stat_offsets_loaded = true;
754}
755
38e00438
VD		 756#ifdef I40E_FCOE
757/**
758 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
759 * @vsi: the VSI that is capable of doing FCoE
760 **/
761static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
762{
763 struct i40e_pf *pf = vsi->back;
764 struct i40e_hw *hw = &pf->hw;
765 struct i40e_fcoe_stats *ofs;
766 struct i40e_fcoe_stats *fs; /* device's eth stats */
767 int idx;
768
769 if (vsi->type != I40E_VSI_FCOE)
770 return;
771
4147e2c5 772 idx = hw->pf_id + I40E_FCOE_PF_STAT_OFFSET;
38e00438
VD		 773 fs = &vsi->fcoe_stats;
774 ofs = &vsi->fcoe_stats_offsets;
775
776 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
777 vsi->fcoe_stat_offsets_loaded,
778 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
779 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
780 vsi->fcoe_stat_offsets_loaded,
781 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
782 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
783 vsi->fcoe_stat_offsets_loaded,
784 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
785 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
786 vsi->fcoe_stat_offsets_loaded,
787 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
788 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
789 vsi->fcoe_stat_offsets_loaded,
790 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
791 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
792 vsi->fcoe_stat_offsets_loaded,
793 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
794 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
795 vsi->fcoe_stat_offsets_loaded,
796 &ofs->fcoe_last_error, &fs->fcoe_last_error);
797 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
798 vsi->fcoe_stat_offsets_loaded,
799 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
800
801 vsi->fcoe_stat_offsets_loaded = true;
802}
803
804#endif
41c445ff 805/**
7812fddc 806 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 807 * @vsi: the VSI to be updated
808 *
809 * There are a few instances where we store the same stat in a
810 * couple of different structs. This is partly because we have
811 * the netdev stats that need to be filled out, which is slightly
812 * different from the "eth_stats" defined by the chip and used in
7812fddc 813 * VF communications. We sort it out here.
41c445ff 814 **/
7812fddc 815static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 816{
817 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 818 struct rtnl_link_stats64 *ons;
819 struct rtnl_link_stats64 *ns; /* netdev stats */
820 struct i40e_eth_stats *oes;
821 struct i40e_eth_stats *es; /* device's eth stats */
822 u32 tx_restart, tx_busy;
dd353109 823 u64 tx_lost_interrupt;
bf00b376 824 struct i40e_ring *p;
41c445ff 825 u32 rx_page, rx_buf;
bf00b376
AA		 826 u64 bytes, packets;
827 unsigned int start;
2fc3d715 828 u64 tx_linearize;
164c9f54 829 u64 tx_force_wb;
41c445ff
JB		 830 u64 rx_p, rx_b;
831 u64 tx_p, tx_b;
41c445ff
JB		 832 u16 q;
833
834 if (test_bit(__I40E_DOWN, &vsi->state) ||
835 test_bit(__I40E_CONFIG_BUSY, &pf->state))
836 return;
837
838 ns = i40e_get_vsi_stats_struct(vsi);
839 ons = &vsi->net_stats_offsets;
840 es = &vsi->eth_stats;
841 oes = &vsi->eth_stats_offsets;
842
843 /* Gather up the netdev and vsi stats that the driver collects
844 * on the fly during packet processing
845 */
846 rx_b = rx_p = 0;
847 tx_b = tx_p = 0;
164c9f54 848 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
dd353109 849 tx_lost_interrupt = 0;
41c445ff
JB		 850 rx_page = 0;
851 rx_buf = 0;
980e9b11 852 rcu_read_lock();
41c445ff 853 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 854 /* locate Tx ring */
855 p = ACCESS_ONCE(vsi->tx_rings[q]);
856
857 do {
57a7744e 858 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 859 packets = p->stats.packets;
860 bytes = p->stats.bytes;
57a7744e 861 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 862 tx_b += bytes;
863 tx_p += packets;
864 tx_restart += p->tx_stats.restart_queue;
865 tx_busy += p->tx_stats.tx_busy;
2fc3d715 866 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 867 tx_force_wb += p->tx_stats.tx_force_wb;
dd353109 868 tx_lost_interrupt += p->tx_stats.tx_lost_interrupt;
41c445ff 869
980e9b11
AD		 870 /* Rx queue is part of the same block as Tx queue */
871 p = &p[1];
872 do {
57a7744e 873 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 874 packets = p->stats.packets;
875 bytes = p->stats.bytes;
57a7744e 876 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 877 rx_b += bytes;
878 rx_p += packets;
420136cc
MW		 879 rx_buf += p->rx_stats.alloc_buff_failed;
880 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 881 }
980e9b11 882 rcu_read_unlock();
41c445ff
JB		 883 vsi->tx_restart = tx_restart;
884 vsi->tx_busy = tx_busy;
2fc3d715 885 vsi->tx_linearize = tx_linearize;
164c9f54 886 vsi->tx_force_wb = tx_force_wb;
dd353109 887 vsi->tx_lost_interrupt = tx_lost_interrupt;
41c445ff
JB		 888 vsi->rx_page_failed = rx_page;
889 vsi->rx_buf_failed = rx_buf;
890
891 ns->rx_packets = rx_p;
892 ns->rx_bytes = rx_b;
893 ns->tx_packets = tx_p;
894 ns->tx_bytes = tx_b;
895
41c445ff 896 /* update netdev stats from eth stats */
7812fddc 897 i40e_update_eth_stats(vsi);
41c445ff
JB		 898 ons->tx_errors = oes->tx_errors;
899 ns->tx_errors = es->tx_errors;
900 ons->multicast = oes->rx_multicast;
901 ns->multicast = es->rx_multicast;
41a9e55c
SN		 902 ons->rx_dropped = oes->rx_discards;
903 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 904 ons->tx_dropped = oes->tx_discards;
905 ns->tx_dropped = es->tx_discards;
906
7812fddc 907 /* pull in a couple PF stats if this is the main vsi */
41c445ff 908 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 909 ns->rx_crc_errors = pf->stats.crc_errors;
910 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
911 ns->rx_length_errors = pf->stats.rx_length_errors;
912 }
913}
41c445ff 914
7812fddc 915/**
b40c82e6 916 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 917 * @pf: the PF to be updated
918 **/
919static void i40e_update_pf_stats(struct i40e_pf *pf)
920{
921 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
922 struct i40e_hw_port_stats *nsd = &pf->stats;
923 struct i40e_hw *hw = &pf->hw;
924 u32 val;
925 int i;
41c445ff 926
7812fddc
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
928 I40E_GLPRT_GORCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
931 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
932 I40E_GLPRT_GOTCL(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
935 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
936 pf->stat_offsets_loaded,
937 &osd->eth.rx_discards,
938 &nsd->eth.rx_discards);
532d283d
SN		 939 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
940 I40E_GLPRT_UPRCL(hw->port),
941 pf->stat_offsets_loaded,
942 &osd->eth.rx_unicast,
943 &nsd->eth.rx_unicast);
7812fddc
SN		 944 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
945 I40E_GLPRT_MPRCL(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->eth.rx_multicast,
948 &nsd->eth.rx_multicast);
532d283d
SN		 949 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
950 I40E_GLPRT_BPRCL(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->eth.rx_broadcast,
953 &nsd->eth.rx_broadcast);
954 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
955 I40E_GLPRT_UPTCL(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->eth.tx_unicast,
958 &nsd->eth.tx_unicast);
959 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
960 I40E_GLPRT_MPTCL(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->eth.tx_multicast,
963 &nsd->eth.tx_multicast);
964 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
965 I40E_GLPRT_BPTCL(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->eth.tx_broadcast,
968 &nsd->eth.tx_broadcast);
41c445ff 969
7812fddc
SN		 970 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->tx_dropped_link_down,
973 &nsd->tx_dropped_link_down);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->crc_errors, &nsd->crc_errors);
41c445ff 978
7812fddc
SN		 979 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
980 pf->stat_offsets_loaded,
981 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 982
7812fddc
SN		 983 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->mac_local_faults,
986 &nsd->mac_local_faults);
987 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->mac_remote_faults,
990 &nsd->mac_remote_faults);
41c445ff 991
7812fddc
SN		 992 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->rx_length_errors,
995 &nsd->rx_length_errors);
41c445ff 996
7812fddc
SN		 997 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
998 pf->stat_offsets_loaded,
999 &osd->link_xon_rx, &nsd->link_xon_rx);
1000 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1001 pf->stat_offsets_loaded,
1002 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 1003 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1004 pf->stat_offsets_loaded,
1005 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 1006 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1007 pf->stat_offsets_loaded,
1008 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1009
7812fddc 1010 for (i = 0; i < 8; i++) {
95db239f
NP		 1011 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1012 pf->stat_offsets_loaded,
1013 &osd->priority_xoff_rx[i],
1014 &nsd->priority_xoff_rx[i]);
7812fddc 1015 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1016 pf->stat_offsets_loaded,
7812fddc
SN		 1017 &osd->priority_xon_rx[i],
1018 &nsd->priority_xon_rx[i]);
1019 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1020 pf->stat_offsets_loaded,
7812fddc
SN		 1021 &osd->priority_xon_tx[i],
1022 &nsd->priority_xon_tx[i]);
1023 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1024 pf->stat_offsets_loaded,
7812fddc
SN		 1025 &osd->priority_xoff_tx[i],
1026 &nsd->priority_xoff_tx[i]);
1027 i40e_stat_update32(hw,
1028 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1029 pf->stat_offsets_loaded,
7812fddc
SN		 1030 &osd->priority_xon_2_xoff[i],
1031 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1032 }
1033
7812fddc
SN		 1034 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1035 I40E_GLPRT_PRC64L(hw->port),
1036 pf->stat_offsets_loaded,
1037 &osd->rx_size_64, &nsd->rx_size_64);
1038 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1039 I40E_GLPRT_PRC127L(hw->port),
1040 pf->stat_offsets_loaded,
1041 &osd->rx_size_127, &nsd->rx_size_127);
1042 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1043 I40E_GLPRT_PRC255L(hw->port),
1044 pf->stat_offsets_loaded,
1045 &osd->rx_size_255, &nsd->rx_size_255);
1046 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1047 I40E_GLPRT_PRC511L(hw->port),
1048 pf->stat_offsets_loaded,
1049 &osd->rx_size_511, &nsd->rx_size_511);
1050 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1051 I40E_GLPRT_PRC1023L(hw->port),
1052 pf->stat_offsets_loaded,
1053 &osd->rx_size_1023, &nsd->rx_size_1023);
1054 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1055 I40E_GLPRT_PRC1522L(hw->port),
1056 pf->stat_offsets_loaded,
1057 &osd->rx_size_1522, &nsd->rx_size_1522);
1058 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1059 I40E_GLPRT_PRC9522L(hw->port),
1060 pf->stat_offsets_loaded,
1061 &osd->rx_size_big, &nsd->rx_size_big);
1062
1063 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1064 I40E_GLPRT_PTC64L(hw->port),
1065 pf->stat_offsets_loaded,
1066 &osd->tx_size_64, &nsd->tx_size_64);
1067 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1068 I40E_GLPRT_PTC127L(hw->port),
1069 pf->stat_offsets_loaded,
1070 &osd->tx_size_127, &nsd->tx_size_127);
1071 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1072 I40E_GLPRT_PTC255L(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->tx_size_255, &nsd->tx_size_255);
1075 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1076 I40E_GLPRT_PTC511L(hw->port),
1077 pf->stat_offsets_loaded,
1078 &osd->tx_size_511, &nsd->tx_size_511);
1079 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1080 I40E_GLPRT_PTC1023L(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->tx_size_1023, &nsd->tx_size_1023);
1083 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1084 I40E_GLPRT_PTC1522L(hw->port),
1085 pf->stat_offsets_loaded,
1086 &osd->tx_size_1522, &nsd->tx_size_1522);
1087 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1088 I40E_GLPRT_PTC9522L(hw->port),
1089 pf->stat_offsets_loaded,
1090 &osd->tx_size_big, &nsd->tx_size_big);
1091
1092 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1093 pf->stat_offsets_loaded,
1094 &osd->rx_undersize, &nsd->rx_undersize);
1095 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1096 pf->stat_offsets_loaded,
1097 &osd->rx_fragments, &nsd->rx_fragments);
1098 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1099 pf->stat_offsets_loaded,
1100 &osd->rx_oversize, &nsd->rx_oversize);
1101 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1102 pf->stat_offsets_loaded,
1103 &osd->rx_jabber, &nsd->rx_jabber);
1104
433c47de 1105 /* FDIR stats */
0bf4b1b0
ASJ		 1106 i40e_stat_update32(hw,
1107 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1108 pf->stat_offsets_loaded,
1109 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1110 i40e_stat_update32(hw,
1111 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1112 pf->stat_offsets_loaded,
1113 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1114 i40e_stat_update32(hw,
1115 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1116 pf->stat_offsets_loaded,
1117 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1118
7812fddc
SN		 1119 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1120 nsd->tx_lpi_status =
1121 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1122 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1123 nsd->rx_lpi_status =
1124 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1125 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1126 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1127 pf->stat_offsets_loaded,
1128 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1129 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1130 pf->stat_offsets_loaded,
1131 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1132
d0389e51
ASJ		 1133 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1134 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1135 nsd->fd_sb_status = true;
1136 else
1137 nsd->fd_sb_status = false;
1138
1139 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1140 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1141 nsd->fd_atr_status = true;
1142 else
1143 nsd->fd_atr_status = false;
1144
41c445ff
JB		 1145 pf->stat_offsets_loaded = true;
1146}
1147
7812fddc
SN		 1148/**
1149 * i40e_update_stats - Update the various statistics counters.
1150 * @vsi: the VSI to be updated
1151 *
1152 * Update the various stats for this VSI and its related entities.
1153 **/
1154void i40e_update_stats(struct i40e_vsi *vsi)
1155{
1156 struct i40e_pf *pf = vsi->back;
1157
1158 if (vsi == pf->vsi[pf->lan_vsi])
1159 i40e_update_pf_stats(pf);
1160
1161 i40e_update_vsi_stats(vsi);
38e00438
VD		 1162#ifdef I40E_FCOE
1163 i40e_update_fcoe_stats(vsi);
1164#endif
7812fddc
SN		 1165}
1166
41c445ff
JB		 1167/**
1168 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1169 * @vsi: the VSI to be searched
1170 * @macaddr: the MAC address
1171 * @vlan: the vlan
b40c82e6 1172 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1173 * @is_netdev: make sure its a netdev filter, else doesn't matter
1174 *
1175 * Returns ptr to the filter object or NULL
1176 **/
1177static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1178 u8 *macaddr, s16 vlan,
1179 bool is_vf, bool is_netdev)
1180{
1181 struct i40e_mac_filter *f;
1182
1183 if (!vsi || !macaddr)
1184 return NULL;
1185
1186 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1187 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1188 (vlan == f->vlan) &&
1189 (!is_vf || f->is_vf) &&
1190 (!is_netdev || f->is_netdev))
1191 return f;
1192 }
1193 return NULL;
1194}
1195
1196/**
1197 * i40e_find_mac - Find a mac addr in the macvlan filters list
1198 * @vsi: the VSI to be searched
1199 * @macaddr: the MAC address we are searching for
b40c82e6 1200 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1201 * @is_netdev: make sure its a netdev filter, else doesn't matter
1202 *
1203 * Returns the first filter with the provided MAC address or NULL if
1204 * MAC address was not found
1205 **/
1206struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1207 bool is_vf, bool is_netdev)
1208{
1209 struct i40e_mac_filter *f;
1210
1211 if (!vsi || !macaddr)
1212 return NULL;
1213
1214 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1215 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1216 (!is_vf || f->is_vf) &&
1217 (!is_netdev || f->is_netdev))
1218 return f;
1219 }
1220 return NULL;
1221}
1222
1223/**
1224 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1225 * @vsi: the VSI to be searched
1226 *
1227 * Returns true if VSI is in vlan mode or false otherwise
1228 **/
1229bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1230{
1231 struct i40e_mac_filter *f;
1232
1233 /* Only -1 for all the filters denotes not in vlan mode
1234 * so we have to go through all the list in order to make sure
1235 */
1236 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1237 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1238 return true;
1239 }
1240
1241 return false;
1242}
1243
1244/**
1245 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1246 * @vsi: the VSI to be searched
1247 * @macaddr: the mac address to be filtered
b40c82e6 1248 * @is_vf: true if it is a VF
41c445ff
JB		 1249 * @is_netdev: true if it is a netdev
1250 *
1251 * Goes through all the macvlan filters and adds a
1252 * macvlan filter for each unique vlan that already exists
1253 *
1254 * Returns first filter found on success, else NULL
1255 **/
1256struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1257 bool is_vf, bool is_netdev)
1258{
1259 struct i40e_mac_filter *f;
1260
1261 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1262 if (vsi->info.pvid)
1263 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1264 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1265 is_vf, is_netdev)) {
1266 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1267 is_vf, is_netdev))
41c445ff
JB		 1268 return NULL;
1269 }
1270 }
1271
1272 return list_first_entry_or_null(&vsi->mac_filter_list,
1273 struct i40e_mac_filter, list);
1274}
1275
b36e9ab5
MW		 1276/**
1277 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1278 * @vsi: the VSI to be searched
1279 * @macaddr: the mac address to be removed
1280 * @is_vf: true if it is a VF
1281 * @is_netdev: true if it is a netdev
1282 *
1283 * Removes a given MAC address from a VSI, regardless of VLAN
1284 *
1285 * Returns 0 for success, or error
1286 **/
1287int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1288 bool is_vf, bool is_netdev)
1289{
1290 struct i40e_mac_filter *f = NULL;
1291 int changed = 0;
1292
1293 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1294 "Missing mac_filter_list_lock\n");
1295 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1296 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1297 (is_vf == f->is_vf) &&
1298 (is_netdev == f->is_netdev)) {
1299 f->counter--;
1300 f->changed = true;
1301 changed = 1;
1302 }
1303 }
1304 if (changed) {
1305 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1306 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1307 return 0;
1308 }
1309 return -ENOENT;
1310}
1311
8c27d42e
GR		 1312/**
1313 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1314 * @vsi: the PF Main VSI - inappropriate for any other VSI
1315 * @macaddr: the MAC address
30650cc5
SN		 1316 *
1317 * Some older firmware configurations set up a default promiscuous VLAN
1318 * filter that needs to be removed.
8c27d42e 1319 **/
30650cc5 1320static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1321{
1322 struct i40e_aqc_remove_macvlan_element_data element;
1323 struct i40e_pf *pf = vsi->back;
f1c7e72e 1324 i40e_status ret;
8c27d42e
GR		 1325
1326 /* Only appropriate for the PF main VSI */
1327 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1328 return -EINVAL;
8c27d42e 1329
30650cc5 1330 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1331 ether_addr_copy(element.mac_addr, macaddr);
1332 element.vlan_tag = 0;
1333 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1334 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1335 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1336 if (ret)
30650cc5
SN		 1337 return -ENOENT;
1338
1339 return 0;
8c27d42e
GR		 1340}
1341
41c445ff
JB		 1342/**
1343 * i40e_add_filter - Add a mac/vlan filter to the VSI
1344 * @vsi: the VSI to be searched
1345 * @macaddr: the MAC address
1346 * @vlan: the vlan
b40c82e6 1347 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1348 * @is_netdev: make sure its a netdev filter, else doesn't matter
1349 *
1350 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1351 *
1352 * NOTE: This function is expected to be called with mac_filter_list_lock
1353 * being held.
41c445ff
JB		 1354 **/
1355struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1356 u8 *macaddr, s16 vlan,
1357 bool is_vf, bool is_netdev)
1358{
1359 struct i40e_mac_filter *f;
1360
1361 if (!vsi || !macaddr)
1362 return NULL;
1363
1364 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1365 if (!f) {
1366 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1367 if (!f)
1368 goto add_filter_out;
1369
9a173901 1370 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1371 f->vlan = vlan;
1372 f->changed = true;
1373
1374 INIT_LIST_HEAD(&f->list);
04d5a21d 1375 list_add_tail(&f->list, &vsi->mac_filter_list);
41c445ff
JB		 1376 }
1377
1378 /* increment counter and add a new flag if needed */
1379 if (is_vf) {
1380 if (!f->is_vf) {
1381 f->is_vf = true;
1382 f->counter++;
1383 }
1384 } else if (is_netdev) {
1385 if (!f->is_netdev) {
1386 f->is_netdev = true;
1387 f->counter++;
1388 }
1389 } else {
1390 f->counter++;
1391 }
1392
1393 /* changed tells sync_filters_subtask to
1394 * push the filter down to the firmware
1395 */
1396 if (f->changed) {
1397 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1398 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1399 }
1400
1401add_filter_out:
1402 return f;
1403}
1404
1405/**
1406 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1407 * @vsi: the VSI to be searched
1408 * @macaddr: the MAC address
1409 * @vlan: the vlan
b40c82e6 1410 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1411 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1412 *
1413 * NOTE: This function is expected to be called with mac_filter_list_lock
1414 * being held.
41c445ff
JB		 1415 **/
1416void i40e_del_filter(struct i40e_vsi *vsi,
1417 u8 *macaddr, s16 vlan,
1418 bool is_vf, bool is_netdev)
1419{
1420 struct i40e_mac_filter *f;
1421
1422 if (!vsi || !macaddr)
1423 return;
1424
1425 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1426 if (!f || f->counter == 0)
1427 return;
1428
1429 if (is_vf) {
1430 if (f->is_vf) {
1431 f->is_vf = false;
1432 f->counter--;
1433 }
1434 } else if (is_netdev) {
1435 if (f->is_netdev) {
1436 f->is_netdev = false;
1437 f->counter--;
1438 }
1439 } else {
b40c82e6 1440 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1441 int min_f = 0;
6995b36c 1442
41c445ff
JB		 1443 min_f += (f->is_vf ? 1 : 0);
1444 min_f += (f->is_netdev ? 1 : 0);
1445
1446 if (f->counter > min_f)
1447 f->counter--;
1448 }
1449
1450 /* counter == 0 tells sync_filters_subtask to
1451 * remove the filter from the firmware's list
1452 */
1453 if (f->counter == 0) {
1454 f->changed = true;
1455 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1456 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1457 }
1458}
1459
1460/**
1461 * i40e_set_mac - NDO callback to set mac address
1462 * @netdev: network interface device structure
1463 * @p: pointer to an address structure
1464 *
1465 * Returns 0 on success, negative on failure
1466 **/
38e00438
VD		 1467#ifdef I40E_FCOE
1468int i40e_set_mac(struct net_device *netdev, void *p)
1469#else
41c445ff 1470static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1471#endif
41c445ff
JB		 1472{
1473 struct i40e_netdev_priv *np = netdev_priv(netdev);
1474 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1475 struct i40e_pf *pf = vsi->back;
1476 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1477 struct sockaddr *addr = p;
1478 struct i40e_mac_filter *f;
1479
1480 if (!is_valid_ether_addr(addr->sa_data))
1481 return -EADDRNOTAVAIL;
1482
30650cc5
SN		 1483 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1484 netdev_info(netdev, "already using mac address %pM\n",
1485 addr->sa_data);
1486 return 0;
1487 }
41c445ff 1488
80f6428f
ASJ		 1489 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1490 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1491 return -EADDRNOTAVAIL;
1492
30650cc5
SN		 1493 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1494 netdev_info(netdev, "returning to hw mac address %pM\n",
1495 hw->mac.addr);
1496 else
1497 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1498
41c445ff
JB		 1499 if (vsi->type == I40E_VSI_MAIN) {
1500 i40e_status ret;
6995b36c 1501
41c445ff 1502 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1503 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1504 addr->sa_data, NULL);
1505 if (ret) {
1506 netdev_info(netdev,
1507 "Addr change for Main VSI failed: %d\n",
1508 ret);
1509 return -EADDRNOTAVAIL;
1510 }
41c445ff
JB		 1511 }
1512
30650cc5
SN		 1513 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1514 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1515
30650cc5
SN		 1516 memset(&element, 0, sizeof(element));
1517 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1518 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1519 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1520 } else {
21659035 1521 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1522 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1523 false, false);
21659035 1524 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1525 }
41c445ff 1526
30650cc5
SN		 1527 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1528 struct i40e_aqc_add_macvlan_element_data element;
1529
1530 memset(&element, 0, sizeof(element));
1531 ether_addr_copy(element.mac_addr, hw->mac.addr);
1532 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1533 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1534 } else {
21659035 1535 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1536 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1537 false, false);
1538 if (f)
1539 f->is_laa = true;
21659035 1540 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1541 }
1542
30650cc5 1543 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b 1544
c53934c6
JB		 1545 /* schedule our worker thread which will take care of
1546 * applying the new filter changes
1547 */
1548 i40e_service_event_schedule(vsi->back);
1549 return 0;
41c445ff
JB		 1550}
1551
1552/**
1553 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1554 * @vsi: the VSI being setup
1555 * @ctxt: VSI context structure
1556 * @enabled_tc: Enabled TCs bitmap
1557 * @is_add: True if called before Add VSI
1558 *
1559 * Setup VSI queue mapping for enabled traffic classes.
1560 **/
38e00438
VD		 1561#ifdef I40E_FCOE
1562void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1563 struct i40e_vsi_context *ctxt,
1564 u8 enabled_tc,
1565 bool is_add)
1566#else
41c445ff
JB		 1567static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1568 struct i40e_vsi_context *ctxt,
1569 u8 enabled_tc,
1570 bool is_add)
38e00438 1571#endif
41c445ff
JB		 1572{
1573 struct i40e_pf *pf = vsi->back;
1574 u16 sections = 0;
1575 u8 netdev_tc = 0;
1576 u16 numtc = 0;
1577 u16 qcount;
1578 u8 offset;
1579 u16 qmap;
1580 int i;
4e3b35b0 1581 u16 num_tc_qps = 0;
41c445ff
JB		 1582
1583 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1584 offset = 0;
1585
1586 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1587 /* Find numtc from enabled TC bitmap */
1588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1589 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1590 numtc++;
1591 }
1592 if (!numtc) {
1593 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1594 numtc = 1;
1595 }
1596 } else {
1597 /* At least TC0 is enabled in case of non-DCB case */
1598 numtc = 1;
1599 }
1600
1601 vsi->tc_config.numtc = numtc;
1602 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1603 /* Number of queues per enabled TC */
7f9ff476
AS		 1604 /* In MFP case we can have a much lower count of MSIx
1605 * vectors available and so we need to lower the used
1606 * q count.
1607 */
26cdc443
ASJ		 1608 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1609 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1610 else
1611 qcount = vsi->alloc_queue_pairs;
7f9ff476 1612 num_tc_qps = qcount / numtc;
e25d00b8 1613 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1614
1615 /* Setup queue offset/count for all TCs for given VSI */
1616 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1617 /* See if the given TC is enabled for the given VSI */
75f5cea9 1618 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1619 /* TC is enabled */
41c445ff
JB		 1620 int pow, num_qps;
1621
41c445ff
JB		 1622 switch (vsi->type) {
1623 case I40E_VSI_MAIN:
acd65448
HZ		 1624 qcount = min_t(int, pf->alloc_rss_size,
1625 num_tc_qps);
41c445ff 1626 break;
38e00438
VD		 1627#ifdef I40E_FCOE
1628 case I40E_VSI_FCOE:
1629 qcount = num_tc_qps;
1630 break;
1631#endif
41c445ff
JB		 1632 case I40E_VSI_FDIR:
1633 case I40E_VSI_SRIOV:
1634 case I40E_VSI_VMDQ2:
1635 default:
4e3b35b0 1636 qcount = num_tc_qps;
41c445ff
JB		 1637 WARN_ON(i != 0);
1638 break;
1639 }
4e3b35b0
NP		 1640 vsi->tc_config.tc_info[i].qoffset = offset;
1641 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1642
1e200e4a 1643 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1644 num_qps = qcount;
41c445ff 1645 pow = 0;
41a1d04b 1646 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1647 pow++;
1648 num_qps >>= 1;
1649 }
1650
1651 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1652 qmap =
1653 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1654 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1655
4e3b35b0 1656 offset += qcount;
41c445ff
JB		 1657 } else {
1658 /* TC is not enabled so set the offset to
1659 * default queue and allocate one queue
1660 * for the given TC.
1661 */
1662 vsi->tc_config.tc_info[i].qoffset = 0;
1663 vsi->tc_config.tc_info[i].qcount = 1;
1664 vsi->tc_config.tc_info[i].netdev_tc = 0;
1665
1666 qmap = 0;
1667 }
1668 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1669 }
1670
1671 /* Set actual Tx/Rx queue pairs */
1672 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1673 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1674 if (vsi->req_queue_pairs > 0)
1675 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1676 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1677 vsi->num_queue_pairs = pf->num_lan_msix;
1678 }
41c445ff
JB		 1679
1680 /* Scheduler section valid can only be set for ADD VSI */
1681 if (is_add) {
1682 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1683
1684 ctxt->info.up_enable_bits = enabled_tc;
1685 }
1686 if (vsi->type == I40E_VSI_SRIOV) {
1687 ctxt->info.mapping_flags |=
1688 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1689 for (i = 0; i < vsi->num_queue_pairs; i++)
1690 ctxt->info.queue_mapping[i] =
1691 cpu_to_le16(vsi->base_queue + i);
1692 } else {
1693 ctxt->info.mapping_flags |=
1694 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1695 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1696 }
1697 ctxt->info.valid_sections |= cpu_to_le16(sections);
1698}
1699
1700/**
1701 * i40e_set_rx_mode - NDO callback to set the netdev filters
1702 * @netdev: network interface device structure
1703 **/
38e00438
VD		 1704#ifdef I40E_FCOE
1705void i40e_set_rx_mode(struct net_device *netdev)
1706#else
41c445ff 1707static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1708#endif
41c445ff
JB		 1709{
1710 struct i40e_netdev_priv *np = netdev_priv(netdev);
1711 struct i40e_mac_filter *f, *ftmp;
1712 struct i40e_vsi *vsi = np->vsi;
1713 struct netdev_hw_addr *uca;
1714 struct netdev_hw_addr *mca;
1715 struct netdev_hw_addr *ha;
1716
21659035
KP		 1717 spin_lock_bh(&vsi->mac_filter_list_lock);
1718
41c445ff
JB		 1719 /* add addr if not already in the filter list */
1720 netdev_for_each_uc_addr(uca, netdev) {
1721 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1722 if (i40e_is_vsi_in_vlan(vsi))
1723 i40e_put_mac_in_vlan(vsi, uca->addr,
1724 false, true);
1725 else
1726 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1727 false, true);
1728 }
1729 }
1730
1731 netdev_for_each_mc_addr(mca, netdev) {
1732 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1733 if (i40e_is_vsi_in_vlan(vsi))
1734 i40e_put_mac_in_vlan(vsi, mca->addr,
1735 false, true);
1736 else
1737 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1738 false, true);
1739 }
1740 }
1741
1742 /* remove filter if not in netdev list */
1743 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1744
1745 if (!f->is_netdev)
1746 continue;
1747
2f41f335
SN		 1748 netdev_for_each_mc_addr(mca, netdev)
1749 if (ether_addr_equal(mca->addr, f->macaddr))
1750 goto bottom_of_search_loop;
41c445ff 1751
2f41f335
SN		 1752 netdev_for_each_uc_addr(uca, netdev)
1753 if (ether_addr_equal(uca->addr, f->macaddr))
1754 goto bottom_of_search_loop;
1755
1756 for_each_dev_addr(netdev, ha)
1757 if (ether_addr_equal(ha->addr, f->macaddr))
1758 goto bottom_of_search_loop;
1759
1760 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1761 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1762
1763bottom_of_search_loop:
1764 continue;
41c445ff 1765 }
21659035 1766 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1767
1768 /* check for other flag changes */
1769 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1770 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1771 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1772 }
c53934c6
JB		 1773
1774 /* schedule our worker thread which will take care of
1775 * applying the new filter changes
1776 */
1777 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1778}
1779
21659035
KP		 1780/**
1781 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1782 * @src: source MAC filter entry to be clones
1783 *
1784 * Returns the pointer to newly cloned MAC filter entry or NULL
1785 * in case of error
1786 **/
1787static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1788 struct i40e_mac_filter *src)
1789{
1790 struct i40e_mac_filter *f;
1791
1792 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1793 if (!f)
1794 return NULL;
1795 *f = *src;
1796
1797 INIT_LIST_HEAD(&f->list);
1798
1799 return f;
1800}
1801
1802/**
1803 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1804 * @vsi: pointer to vsi struct
1805 * @from: Pointer to list which contains MAC filter entries - changes to
1806 * those entries needs to be undone.
1807 *
1808 * MAC filter entries from list were slated to be removed from device.
1809 **/
1810static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1811 struct list_head *from)
1812{
1813 struct i40e_mac_filter *f, *ftmp;
1814
1815 list_for_each_entry_safe(f, ftmp, from, list) {
1816 f->changed = true;
1817 /* Move the element back into MAC filter list*/
1818 list_move_tail(&f->list, &vsi->mac_filter_list);
1819 }
1820}
1821
1822/**
1823 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1824 * @vsi: pointer to vsi struct
1825 *
1826 * MAC filter entries from list were slated to be added from device.
1827 **/
1828static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1829{
1830 struct i40e_mac_filter *f, *ftmp;
1831
1832 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1833 if (!f->changed && f->counter)
1834 f->changed = true;
1835 }
1836}
1837
1838/**
1839 * i40e_cleanup_add_list - Deletes the element from add list and release
1840 * memory
1841 * @add_list: Pointer to list which contains MAC filter entries
1842 **/
1843static void i40e_cleanup_add_list(struct list_head *add_list)
1844{
1845 struct i40e_mac_filter *f, *ftmp;
1846
1847 list_for_each_entry_safe(f, ftmp, add_list, list) {
1848 list_del(&f->list);
1849 kfree(f);
1850 }
1851}
1852
41c445ff
JB		 1853/**
1854 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1855 * @vsi: ptr to the VSI
1856 *
1857 * Push any outstanding VSI filter changes through the AdminQ.
1858 *
1859 * Returns 0 or error value
1860 **/
17652c63 1861int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1862{
21659035
KP		 1863 struct list_head tmp_del_list, tmp_add_list;
1864 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1865 bool promisc_forced_on = false;
1866 bool add_happened = false;
1867 int filter_list_len = 0;
1868 u32 changed_flags = 0;
ea02e90b 1869 i40e_status aq_ret = 0;
21659035 1870 bool err_cond = false;
ea02e90b 1871 int retval = 0;
41c445ff
JB		 1872 struct i40e_pf *pf;
1873 int num_add = 0;
1874 int num_del = 0;
f1c7e72e 1875 int aq_err = 0;
41c445ff
JB		 1876 u16 cmd_flags;
1877
1878 /* empty array typed pointers, kcalloc later */
1879 struct i40e_aqc_add_macvlan_element_data *add_list;
1880 struct i40e_aqc_remove_macvlan_element_data *del_list;
1881
1882 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1883 usleep_range(1000, 2000);
1884 pf = vsi->back;
1885
1886 if (vsi->netdev) {
1887 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1888 vsi->current_netdev_flags = vsi->netdev->flags;
1889 }
1890
21659035
KP		 1891 INIT_LIST_HEAD(&tmp_del_list);
1892 INIT_LIST_HEAD(&tmp_add_list);
1893
41c445ff
JB		 1894 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1895 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1896
21659035 1897 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1898 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1899 if (!f->changed)
1900 continue;
1901
1902 if (f->counter != 0)
1903 continue;
1904 f->changed = false;
21659035
KP		 1905
1906 /* Move the element into temporary del_list */
1907 list_move_tail(&f->list, &tmp_del_list);
1908 }
1909
1910 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1911 if (!f->changed)
1912 continue;
1913
1914 if (f->counter == 0)
1915 continue;
1916 f->changed = false;
1917
1918 /* Clone MAC filter entry and add into temporary list */
1919 fclone = i40e_mac_filter_entry_clone(f);
1920 if (!fclone) {
1921 err_cond = true;
1922 break;
1923 }
1924 list_add_tail(&fclone->list, &tmp_add_list);
1925 }
1926
1927 /* if failed to clone MAC filter entry - undo */
1928 if (err_cond) {
1929 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1930 i40e_undo_add_filter_entries(vsi);
1931 }
1932 spin_unlock_bh(&vsi->mac_filter_list_lock);
1933
ea02e90b 1934 if (err_cond) {
21659035 1935 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1936 retval = -ENOMEM;
1937 goto out;
1938 }
21659035
KP		 1939 }
1940
1941 /* Now process 'del_list' outside the lock */
1942 if (!list_empty(&tmp_del_list)) {
f1199998
SN		 1943 int del_list_size;
1944
21659035
KP		 1945 filter_list_len = pf->hw.aq.asq_buf_size /
1946 sizeof(struct i40e_aqc_remove_macvlan_element_data);
f1199998
SN		 1947 del_list_size = filter_list_len *
1948 sizeof(struct i40e_aqc_remove_macvlan_element_data);
38c3cec7 1949 del_list = kzalloc(del_list_size, GFP_ATOMIC);
21659035
KP		 1950 if (!del_list) {
1951 i40e_cleanup_add_list(&tmp_add_list);
1952
1953 /* Undo VSI's MAC filter entry element updates */
1954 spin_lock_bh(&vsi->mac_filter_list_lock);
1955 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1956 i40e_undo_add_filter_entries(vsi);
1957 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1958 retval = -ENOMEM;
1959 goto out;
21659035
KP		 1960 }
1961
1962 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1963 cmd_flags = 0;
1964
1965 /* add to delete list */
9a173901 1966 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1967 del_list[num_del].vlan_tag =
1968 cpu_to_le16((u16)(f->vlan ==
1969 I40E_VLAN_ANY ? 0 : f->vlan));
1970
41c445ff
JB		 1971 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1972 del_list[num_del].flags = cmd_flags;
1973 num_del++;
1974
41c445ff
JB		 1975 /* flush a full buffer */
1976 if (num_del == filter_list_len) {
ea02e90b
MW		 1977 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1978 vsi->seid,
1979 del_list,
1980 num_del,
1981 NULL);
f1c7e72e 1982 aq_err = pf->hw.aq.asq_last_status;
41c445ff 1983 num_del = 0;
f1199998 1984 memset(del_list, 0, del_list_size);
41c445ff 1985
ea02e90b
MW		 1986 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1987 retval = -EIO;
21659035
KP		 1988 dev_err(&pf->pdev->dev,
1989 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
ea02e90b 1990 i40e_stat_str(&pf->hw, aq_ret),
21659035 1991 i40e_aq_str(&pf->hw, aq_err));
ea02e90b 1992 }
41c445ff 1993 }
21659035
KP		 1994 /* Release memory for MAC filter entries which were
1995 * synced up with HW.
1996 */
1997 list_del(&f->list);
1998 kfree(f);
41c445ff 1999 }
21659035 2000
41c445ff 2001 if (num_del) {
ea02e90b
MW		 2002 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
2003 del_list, num_del,
2004 NULL);
f1c7e72e 2005 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2006 num_del = 0;
2007
ea02e90b 2008 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 2009 dev_info(&pf->pdev->dev,
f1c7e72e 2010 "ignoring delete macvlan error, err %s aq_err %s\n",
ea02e90b 2011 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2012 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2013 }
2014
2015 kfree(del_list);
2016 del_list = NULL;
21659035
KP		 2017 }
2018
2019 if (!list_empty(&tmp_add_list)) {
f1199998 2020 int add_list_size;
41c445ff
JB		 2021
2022 /* do all the adds now */
2023 filter_list_len = pf->hw.aq.asq_buf_size /
2024 sizeof(struct i40e_aqc_add_macvlan_element_data),
f1199998
SN		 2025 add_list_size = filter_list_len *
2026 sizeof(struct i40e_aqc_add_macvlan_element_data);
38c3cec7 2027 add_list = kzalloc(add_list_size, GFP_ATOMIC);
21659035
KP		 2028 if (!add_list) {
2029 /* Purge element from temporary lists */
2030 i40e_cleanup_add_list(&tmp_add_list);
2031
2032 /* Undo add filter entries from VSI MAC filter list */
2033 spin_lock_bh(&vsi->mac_filter_list_lock);
2034 i40e_undo_add_filter_entries(vsi);
2035 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2036 retval = -ENOMEM;
2037 goto out;
21659035 2038 }
41c445ff 2039
21659035 2040 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2041
41c445ff
JB		 2042 add_happened = true;
2043 cmd_flags = 0;
2044
2045 /* add to add array */
9a173901 2046 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2047 add_list[num_add].vlan_tag =
2048 cpu_to_le16(
2049 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2050 add_list[num_add].queue_number = 0;
2051
2052 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2053 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2054 num_add++;
2055
2056 /* flush a full buffer */
2057 if (num_add == filter_list_len) {
ea02e90b
MW		 2058 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2059 add_list, num_add,
2060 NULL);
f1c7e72e 2061 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2062 num_add = 0;
2063
ea02e90b 2064 if (aq_ret)
41c445ff 2065 break;
f1199998 2066 memset(add_list, 0, add_list_size);
41c445ff 2067 }
21659035
KP		 2068 /* Entries from tmp_add_list were cloned from MAC
2069 * filter list, hence clean those cloned entries
2070 */
2071 list_del(&f->list);
2072 kfree(f);
41c445ff 2073 }
21659035 2074
41c445ff 2075 if (num_add) {
ea02e90b
MW		 2076 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2077 add_list, num_add, NULL);
f1c7e72e 2078 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2079 num_add = 0;
2080 }
2081 kfree(add_list);
2082 add_list = NULL;
2083
ea02e90b
MW		 2084 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2085 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2086 dev_info(&pf->pdev->dev,
f1c7e72e 2087 "add filter failed, err %s aq_err %s\n",
ea02e90b 2088 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2089 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2090 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2091 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2092 &vsi->state)) {
2093 promisc_forced_on = true;
2094 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2095 &vsi->state);
2096 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2097 }
2098 }
2099 }
2100
2101 /* check for changes in promiscuous modes */
2102 if (changed_flags & IFF_ALLMULTI) {
2103 bool cur_multipromisc;
6995b36c 2104
41c445ff 2105 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2106 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2107 vsi->seid,
2108 cur_multipromisc,
2109 NULL);
2110 if (aq_ret) {
2111 retval = i40e_aq_rc_to_posix(aq_ret,
2112 pf->hw.aq.asq_last_status);
41c445ff 2113 dev_info(&pf->pdev->dev,
f1c7e72e 2114 "set multi promisc failed, err %s aq_err %s\n",
ea02e90b 2115 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2116 i40e_aq_str(&pf->hw,
2117 pf->hw.aq.asq_last_status));
ea02e90b 2118 }
41c445ff
JB		 2119 }
2120 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2121 bool cur_promisc;
6995b36c 2122
41c445ff
JB		 2123 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2124 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2125 &vsi->state));
6784ed5a
ASJ		 2126 if ((vsi->type == I40E_VSI_MAIN) &&
2127 (pf->lan_veb != I40E_NO_VEB) &&
2128 !(pf->flags & I40E_FLAG_MFP_ENABLED)) {
92faef85
ASJ		 2129 /* set defport ON for Main VSI instead of true promisc
2130 * this way we will get all unicast/multicast and VLAN
2131 * promisc behavior but will not get VF or VMDq traffic
2132 * replicated on the Main VSI.
2133 */
2134 if (pf->cur_promisc != cur_promisc) {
2135 pf->cur_promisc = cur_promisc;
0e4425ed 2136 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2137 }
2138 } else {
ea02e90b 2139 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
92faef85 2140 &vsi->back->hw,
f1c7e72e
SN		 2141 vsi->seid,
2142 cur_promisc, NULL);
ea02e90b
MW		 2143 if (aq_ret) {
2144 retval =
2145 i40e_aq_rc_to_posix(aq_ret,
2146 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2147 dev_info(&pf->pdev->dev,
2148 "set unicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2149 aq_ret, pf->hw.aq.asq_last_status);
2150 }
2151 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
92faef85
ASJ		 2152 &vsi->back->hw,
2153 vsi->seid,
2154 cur_promisc, NULL);
ea02e90b
MW		 2155 if (aq_ret) {
2156 retval =
2157 i40e_aq_rc_to_posix(aq_ret,
2158 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2159 dev_info(&pf->pdev->dev,
2160 "set multicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2161 aq_ret, pf->hw.aq.asq_last_status);
2162 }
92faef85 2163 }
ea02e90b
MW		 2164 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2165 vsi->seid,
2166 cur_promisc, NULL);
2167 if (aq_ret) {
2168 retval = i40e_aq_rc_to_posix(aq_ret,
2169 pf->hw.aq.asq_last_status);
1a10370a 2170 dev_info(&pf->pdev->dev,
f1c7e72e 2171 "set brdcast promisc failed, err %s, aq_err %s\n",
ea02e90b 2172 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2173 i40e_aq_str(&pf->hw,
2174 pf->hw.aq.asq_last_status));
ea02e90b 2175 }
41c445ff 2176 }
ea02e90b 2177out:
2818ccd9
JB		 2178 /* if something went wrong then set the changed flag so we try again */
2179 if (retval)
2180 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2181
41c445ff 2182 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2183 return retval;
41c445ff
JB		 2184}
2185
2186/**
2187 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2188 * @pf: board private structure
2189 **/
2190static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2191{
2192 int v;
2193
2194 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2195 return;
2196 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2197
505682cd 2198 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2199 if (pf->vsi[v] &&
17652c63
JB		 2200 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2201 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2202
2203 if (ret) {
2204 /* come back and try again later */
2205 pf->flags |= I40E_FLAG_FILTER_SYNC;
2206 break;
2207 }
2208 }
41c445ff
JB		 2209 }
2210}
2211
2212/**
2213 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2214 * @netdev: network interface device structure
2215 * @new_mtu: new value for maximum frame size
2216 *
2217 * Returns 0 on success, negative on failure
2218 **/
2219static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2220{
2221 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2222 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2223 struct i40e_vsi *vsi = np->vsi;
2224
2225 /* MTU < 68 is an error and causes problems on some kernels */
2226 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2227 return -EINVAL;
2228
2229 netdev_info(netdev, "changing MTU from %d to %d\n",
2230 netdev->mtu, new_mtu);
2231 netdev->mtu = new_mtu;
2232 if (netif_running(netdev))
2233 i40e_vsi_reinit_locked(vsi);
e3219ce6 2234 i40e_notify_client_of_l2_param_changes(vsi);
41c445ff
JB		 2235 return 0;
2236}
2237
beb0dff1
JK		 2238/**
2239 * i40e_ioctl - Access the hwtstamp interface
2240 * @netdev: network interface device structure
2241 * @ifr: interface request data
2242 * @cmd: ioctl command
2243 **/
2244int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2245{
2246 struct i40e_netdev_priv *np = netdev_priv(netdev);
2247 struct i40e_pf *pf = np->vsi->back;
2248
2249 switch (cmd) {
2250 case SIOCGHWTSTAMP:
2251 return i40e_ptp_get_ts_config(pf, ifr);
2252 case SIOCSHWTSTAMP:
2253 return i40e_ptp_set_ts_config(pf, ifr);
2254 default:
2255 return -EOPNOTSUPP;
2256 }
2257}
2258
41c445ff
JB		 2259/**
2260 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2261 * @vsi: the vsi being adjusted
2262 **/
2263void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2264{
2265 struct i40e_vsi_context ctxt;
2266 i40e_status ret;
2267
2268 if ((vsi->info.valid_sections &
2269 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2270 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2271 return; /* already enabled */
2272
2273 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2274 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2275 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2276
2277 ctxt.seid = vsi->seid;
1a2f6248 2278 ctxt.info = vsi->info;
41c445ff
JB		 2279 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2280 if (ret) {
2281 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2282 "update vlan stripping failed, err %s aq_err %s\n",
2283 i40e_stat_str(&vsi->back->hw, ret),
2284 i40e_aq_str(&vsi->back->hw,
2285 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2286 }
2287}
2288
2289/**
2290 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2291 * @vsi: the vsi being adjusted
2292 **/
2293void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2294{
2295 struct i40e_vsi_context ctxt;
2296 i40e_status ret;
2297
2298 if ((vsi->info.valid_sections &
2299 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2300 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2301 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2302 return; /* already disabled */
2303
2304 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2305 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2306 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2307
2308 ctxt.seid = vsi->seid;
1a2f6248 2309 ctxt.info = vsi->info;
41c445ff
JB		 2310 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2311 if (ret) {
2312 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2313 "update vlan stripping failed, err %s aq_err %s\n",
2314 i40e_stat_str(&vsi->back->hw, ret),
2315 i40e_aq_str(&vsi->back->hw,
2316 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2317 }
2318}
2319
2320/**
2321 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2322 * @netdev: network interface to be adjusted
2323 * @features: netdev features to test if VLAN offload is enabled or not
2324 **/
2325static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2326{
2327 struct i40e_netdev_priv *np = netdev_priv(netdev);
2328 struct i40e_vsi *vsi = np->vsi;
2329
2330 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2331 i40e_vlan_stripping_enable(vsi);
2332 else
2333 i40e_vlan_stripping_disable(vsi);
2334}
2335
2336/**
2337 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2338 * @vsi: the vsi being configured
2339 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2340 **/
2341int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2342{
2343 struct i40e_mac_filter *f, *add_f;
2344 bool is_netdev, is_vf;
41c445ff
JB		 2345
2346 is_vf = (vsi->type == I40E_VSI_SRIOV);
2347 is_netdev = !!(vsi->netdev);
2348
21659035
KP		 2349 /* Locked once because all functions invoked below iterates list*/
2350 spin_lock_bh(&vsi->mac_filter_list_lock);
2351
41c445ff
JB		 2352 if (is_netdev) {
2353 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2354 is_vf, is_netdev);
2355 if (!add_f) {
2356 dev_info(&vsi->back->pdev->dev,
2357 "Could not add vlan filter %d for %pM\n",
2358 vid, vsi->netdev->dev_addr);
21659035 2359 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2360 return -ENOMEM;
2361 }
2362 }
2363
2364 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2365 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2366 if (!add_f) {
2367 dev_info(&vsi->back->pdev->dev,
2368 "Could not add vlan filter %d for %pM\n",
2369 vid, f->macaddr);
21659035 2370 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2371 return -ENOMEM;
2372 }
2373 }
2374
41c445ff
JB		 2375 /* Now if we add a vlan tag, make sure to check if it is the first
2376 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2377 * with 0, so we now accept untagged and specified tagged traffic
2378 * (and not any taged and untagged)
2379 */
2380 if (vid > 0) {
2381 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2382 I40E_VLAN_ANY,
2383 is_vf, is_netdev)) {
2384 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2385 I40E_VLAN_ANY, is_vf, is_netdev);
2386 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2387 is_vf, is_netdev);
2388 if (!add_f) {
2389 dev_info(&vsi->back->pdev->dev,
2390 "Could not add filter 0 for %pM\n",
2391 vsi->netdev->dev_addr);
21659035 2392 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2393 return -ENOMEM;
2394 }
2395 }
8d82a7c5 2396 }
41c445ff 2397
8d82a7c5
GR		 2398 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2399 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2400 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2401 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2402 is_vf, is_netdev))
2403 continue;
2404 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2405 is_vf, is_netdev);
2406 add_f = i40e_add_filter(vsi, f->macaddr,
2407 0, is_vf, is_netdev);
2408 if (!add_f) {
2409 dev_info(&vsi->back->pdev->dev,
2410 "Could not add filter 0 for %pM\n",
2411 f->macaddr);
2412 spin_unlock_bh(&vsi->mac_filter_list_lock);
2413 return -ENOMEM;
41c445ff
JB		 2414 }
2415 }
41c445ff
JB		 2416 }
2417
21659035
KP		 2418 spin_unlock_bh(&vsi->mac_filter_list_lock);
2419
0e4425ed
JB		 2420 /* schedule our worker thread which will take care of
2421 * applying the new filter changes
2422 */
2423 i40e_service_event_schedule(vsi->back);
2424 return 0;
41c445ff
JB		 2425}
2426
2427/**
2428 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2429 * @vsi: the vsi being configured
2430 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2431 *
2432 * Return: 0 on success or negative otherwise
41c445ff
JB		 2433 **/
2434int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2435{
2436 struct net_device *netdev = vsi->netdev;
2437 struct i40e_mac_filter *f, *add_f;
2438 bool is_vf, is_netdev;
2439 int filter_count = 0;
41c445ff
JB		 2440
2441 is_vf = (vsi->type == I40E_VSI_SRIOV);
2442 is_netdev = !!(netdev);
2443
21659035
KP		 2444 /* Locked once because all functions invoked below iterates list */
2445 spin_lock_bh(&vsi->mac_filter_list_lock);
2446
41c445ff
JB		 2447 if (is_netdev)
2448 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2449
2450 list_for_each_entry(f, &vsi->mac_filter_list, list)
2451 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2452
41c445ff
JB		 2453 /* go through all the filters for this VSI and if there is only
2454 * vid == 0 it means there are no other filters, so vid 0 must
2455 * be replaced with -1. This signifies that we should from now
2456 * on accept any traffic (with any tag present, or untagged)
2457 */
2458 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2459 if (is_netdev) {
2460 if (f->vlan &&
2461 ether_addr_equal(netdev->dev_addr, f->macaddr))
2462 filter_count++;
2463 }
2464
2465 if (f->vlan)
2466 filter_count++;
2467 }
2468
2469 if (!filter_count && is_netdev) {
2470 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2471 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2472 is_vf, is_netdev);
2473 if (!f) {
2474 dev_info(&vsi->back->pdev->dev,
2475 "Could not add filter %d for %pM\n",
2476 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2477 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2478 return -ENOMEM;
2479 }
2480 }
2481
2482 if (!filter_count) {
2483 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2484 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2485 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2486 is_vf, is_netdev);
41c445ff
JB		 2487 if (!add_f) {
2488 dev_info(&vsi->back->pdev->dev,
2489 "Could not add filter %d for %pM\n",
2490 I40E_VLAN_ANY, f->macaddr);
21659035 2491 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2492 return -ENOMEM;
2493 }
2494 }
2495 }
2496
21659035
KP		 2497 spin_unlock_bh(&vsi->mac_filter_list_lock);
2498
0e4425ed
JB		 2499 /* schedule our worker thread which will take care of
2500 * applying the new filter changes
2501 */
2502 i40e_service_event_schedule(vsi->back);
2503 return 0;
41c445ff
JB		 2504}
2505
2506/**
2507 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2508 * @netdev: network interface to be adjusted
2509 * @vid: vlan id to be added
078b5876
JB		 2510 *
2511 * net_device_ops implementation for adding vlan ids
41c445ff 2512 **/
38e00438
VD		 2513#ifdef I40E_FCOE
2514int i40e_vlan_rx_add_vid(struct net_device *netdev,
2515 __always_unused __be16 proto, u16 vid)
2516#else
41c445ff
JB		 2517static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2518 __always_unused __be16 proto, u16 vid)
38e00438 2519#endif
41c445ff
JB		 2520{
2521 struct i40e_netdev_priv *np = netdev_priv(netdev);
2522 struct i40e_vsi *vsi = np->vsi;
078b5876 2523 int ret = 0;
41c445ff
JB		 2524
2525 if (vid > 4095)
078b5876
JB		 2526 return -EINVAL;
2527
2528 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2529
6982d429
ASJ		 2530 /* If the network stack called us with vid = 0 then
2531 * it is asking to receive priority tagged packets with
2532 * vlan id 0. Our HW receives them by default when configured
2533 * to receive untagged packets so there is no need to add an
2534 * extra filter for vlan 0 tagged packets.
41c445ff 2535 */
6982d429
ASJ		 2536 if (vid)
2537 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2538
078b5876
JB		 2539 if (!ret && (vid < VLAN_N_VID))
2540 set_bit(vid, vsi->active_vlans);
41c445ff 2541
078b5876 2542 return ret;
41c445ff
JB		 2543}
2544
2545/**
2546 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2547 * @netdev: network interface to be adjusted
2548 * @vid: vlan id to be removed
078b5876 2549 *
fdfd943e 2550 * net_device_ops implementation for removing vlan ids
41c445ff 2551 **/
38e00438
VD		 2552#ifdef I40E_FCOE
2553int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2554 __always_unused __be16 proto, u16 vid)
2555#else
41c445ff
JB		 2556static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2557 __always_unused __be16 proto, u16 vid)
38e00438 2558#endif
41c445ff
JB		 2559{
2560 struct i40e_netdev_priv *np = netdev_priv(netdev);
2561 struct i40e_vsi *vsi = np->vsi;
2562
078b5876
JB		 2563 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2564
41c445ff
JB		 2565 /* return code is ignored as there is nothing a user
2566 * can do about failure to remove and a log message was
078b5876 2567 * already printed from the other function
41c445ff
JB		 2568 */
2569 i40e_vsi_kill_vlan(vsi, vid);
2570
2571 clear_bit(vid, vsi->active_vlans);
078b5876 2572
41c445ff
JB		 2573 return 0;
2574}
2575
2576/**
2577 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2578 * @vsi: the vsi being brought back up
2579 **/
2580static void i40e_restore_vlan(struct i40e_vsi *vsi)
2581{
2582 u16 vid;
2583
2584 if (!vsi->netdev)
2585 return;
2586
2587 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2588
2589 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2590 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2591 vid);
2592}
2593
2594/**
2595 * i40e_vsi_add_pvid - Add pvid for the VSI
2596 * @vsi: the vsi being adjusted
2597 * @vid: the vlan id to set as a PVID
2598 **/
dcae29be 2599int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2600{
2601 struct i40e_vsi_context ctxt;
f1c7e72e 2602 i40e_status ret;
41c445ff
JB		 2603
2604 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2605 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2606 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2607 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2608 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2609
2610 ctxt.seid = vsi->seid;
1a2f6248 2611 ctxt.info = vsi->info;
f1c7e72e
SN		 2612 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2613 if (ret) {
41c445ff 2614 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2615 "add pvid failed, err %s aq_err %s\n",
2616 i40e_stat_str(&vsi->back->hw, ret),
2617 i40e_aq_str(&vsi->back->hw,
2618 vsi->back->hw.aq.asq_last_status));
dcae29be 2619 return -ENOENT;
41c445ff
JB		 2620 }
2621
dcae29be 2622 return 0;
41c445ff
JB		 2623}
2624
2625/**
2626 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2627 * @vsi: the vsi being adjusted
2628 *
2629 * Just use the vlan_rx_register() service to put it back to normal
2630 **/
2631void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2632{
6c12fcbf
GR		 2633 i40e_vlan_stripping_disable(vsi);
2634
41c445ff 2635 vsi->info.pvid = 0;
41c445ff
JB		 2636}
2637
2638/**
2639 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2640 * @vsi: ptr to the VSI
2641 *
2642 * If this function returns with an error, then it's possible one or
2643 * more of the rings is populated (while the rest are not). It is the
2644 * callers duty to clean those orphaned rings.
2645 *
2646 * Return 0 on success, negative on failure
2647 **/
2648static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2649{
2650 int i, err = 0;
2651
2652 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2653 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2654
2655 return err;
2656}
2657
2658/**
2659 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2660 * @vsi: ptr to the VSI
2661 *
2662 * Free VSI's transmit software resources
2663 **/
2664static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2665{
2666 int i;
2667
8e9dca53
GR		 2668 if (!vsi->tx_rings)
2669 return;
2670
41c445ff 2671 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2672 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2673 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2674}
2675
2676/**
2677 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2678 * @vsi: ptr to the VSI
2679 *
2680 * If this function returns with an error, then it's possible one or
2681 * more of the rings is populated (while the rest are not). It is the
2682 * callers duty to clean those orphaned rings.
2683 *
2684 * Return 0 on success, negative on failure
2685 **/
2686static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2687{
2688 int i, err = 0;
2689
2690 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2691 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2692#ifdef I40E_FCOE
2693 i40e_fcoe_setup_ddp_resources(vsi);
2694#endif
41c445ff
JB		 2695 return err;
2696}
2697
2698/**
2699 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2700 * @vsi: ptr to the VSI
2701 *
2702 * Free all receive software resources
2703 **/
2704static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2705{
2706 int i;
2707
8e9dca53
GR		 2708 if (!vsi->rx_rings)
2709 return;
2710
41c445ff 2711 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2712 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2713 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2714#ifdef I40E_FCOE
2715 i40e_fcoe_free_ddp_resources(vsi);
2716#endif
41c445ff
JB		 2717}
2718
3ffa037d
NP		 2719/**
2720 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2721 * @ring: The Tx ring to configure
2722 *
2723 * This enables/disables XPS for a given Tx descriptor ring
2724 * based on the TCs enabled for the VSI that ring belongs to.
2725 **/
2726static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2727{
2728 struct i40e_vsi *vsi = ring->vsi;
2729 cpumask_var_t mask;
2730
9a660eea
JB		 2731 if (!ring->q_vector || !ring->netdev)
2732 return;
2733
2734 /* Single TC mode enable XPS */
2735 if (vsi->tc_config.numtc <= 1) {
2736 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2737 netif_set_xps_queue(ring->netdev,
2738 &ring->q_vector->affinity_mask,
2739 ring->queue_index);
9a660eea
JB		 2740 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2741 /* Disable XPS to allow selection based on TC */
2742 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2743 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2744 free_cpumask_var(mask);
3ffa037d 2745 }
0e4425ed
JB		 2746
2747 /* schedule our worker thread which will take care of
2748 * applying the new filter changes
2749 */
2750 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2751}
2752
41c445ff
JB		 2753/**
2754 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2755 * @ring: The Tx ring to configure
2756 *
2757 * Configure the Tx descriptor ring in the HMC context.
2758 **/
2759static int i40e_configure_tx_ring(struct i40e_ring *ring)
2760{
2761 struct i40e_vsi *vsi = ring->vsi;
2762 u16 pf_q = vsi->base_queue + ring->queue_index;
2763 struct i40e_hw *hw = &vsi->back->hw;
2764 struct i40e_hmc_obj_txq tx_ctx;
2765 i40e_status err = 0;
2766 u32 qtx_ctl = 0;
2767
2768 /* some ATR related tx ring init */
60ea5f83 2769 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2770 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2771 ring->atr_count = 0;
2772 } else {
2773 ring->atr_sample_rate = 0;
2774 }
2775
3ffa037d
NP		 2776 /* configure XPS */
2777 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2778
2779 /* clear the context structure first */
2780 memset(&tx_ctx, 0, sizeof(tx_ctx));
2781
2782 tx_ctx.new_context = 1;
2783 tx_ctx.base = (ring->dma / 128);
2784 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2785 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2786 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2787#ifdef I40E_FCOE
2788 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2789#endif
beb0dff1 2790 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2791 /* FDIR VSI tx ring can still use RS bit and writebacks */
2792 if (vsi->type != I40E_VSI_FDIR)
2793 tx_ctx.head_wb_ena = 1;
2794 tx_ctx.head_wb_addr = ring->dma +
2795 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2796
2797 /* As part of VSI creation/update, FW allocates certain
2798 * Tx arbitration queue sets for each TC enabled for
2799 * the VSI. The FW returns the handles to these queue
2800 * sets as part of the response buffer to Add VSI,
2801 * Update VSI, etc. AQ commands. It is expected that
2802 * these queue set handles be associated with the Tx
2803 * queues by the driver as part of the TX queue context
2804 * initialization. This has to be done regardless of
2805 * DCB as by default everything is mapped to TC0.
2806 */
2807 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2808 tx_ctx.rdylist_act = 0;
2809
2810 /* clear the context in the HMC */
2811 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2812 if (err) {
2813 dev_info(&vsi->back->pdev->dev,
2814 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2815 ring->queue_index, pf_q, err);
2816 return -ENOMEM;
2817 }
2818
2819 /* set the context in the HMC */
2820 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2821 if (err) {
2822 dev_info(&vsi->back->pdev->dev,
2823 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2824 ring->queue_index, pf_q, err);
2825 return -ENOMEM;
2826 }
2827
2828 /* Now associate this queue with this PCI function */
7a28d885 2829 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2830 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2831 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2832 I40E_QTX_CTL_VFVM_INDX_MASK;
2833 } else {
9d8bf547 2834 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2835 }
2836
13fd9774
SN		 2837 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2838 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2839 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2840 i40e_flush(hw);
2841
41c445ff
JB		 2842 /* cache tail off for easier writes later */
2843 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2844
2845 return 0;
2846}
2847
2848/**
2849 * i40e_configure_rx_ring - Configure a receive ring context
2850 * @ring: The Rx ring to configure
2851 *
2852 * Configure the Rx descriptor ring in the HMC context.
2853 **/
2854static int i40e_configure_rx_ring(struct i40e_ring *ring)
2855{
2856 struct i40e_vsi *vsi = ring->vsi;
2857 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2858 u16 pf_q = vsi->base_queue + ring->queue_index;
2859 struct i40e_hw *hw = &vsi->back->hw;
2860 struct i40e_hmc_obj_rxq rx_ctx;
2861 i40e_status err = 0;
2862
2863 ring->state = 0;
2864
2865 /* clear the context structure first */
2866 memset(&rx_ctx, 0, sizeof(rx_ctx));
2867
2868 ring->rx_buf_len = vsi->rx_buf_len;
2869 ring->rx_hdr_len = vsi->rx_hdr_len;
2870
2871 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2872 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2873
2874 rx_ctx.base = (ring->dma / 128);
2875 rx_ctx.qlen = ring->count;
2876
2877 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2878 set_ring_16byte_desc_enabled(ring);
2879 rx_ctx.dsize = 0;
2880 } else {
2881 rx_ctx.dsize = 1;
2882 }
2883
2884 rx_ctx.dtype = vsi->dtype;
2885 if (vsi->dtype) {
2886 set_ring_ps_enabled(ring);
2887 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2888 I40E_RX_SPLIT_IP |
2889 I40E_RX_SPLIT_TCP_UDP |
2890 I40E_RX_SPLIT_SCTP;
2891 } else {
2892 rx_ctx.hsplit_0 = 0;
2893 }
2894
2895 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2896 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2897 if (hw->revision_id == 0)
2898 rx_ctx.lrxqthresh = 0;
2899 else
2900 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2901 rx_ctx.crcstrip = 1;
2902 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2903 /* this controls whether VLAN is stripped from inner headers */
2904 rx_ctx.showiv = 0;
38e00438
VD		 2905#ifdef I40E_FCOE
2906 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2907#endif
acb3676b
CS		 2908 /* set the prefena field to 1 because the manual says to */
2909 rx_ctx.prefena = 1;
41c445ff
JB		 2910
2911 /* clear the context in the HMC */
2912 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2913 if (err) {
2914 dev_info(&vsi->back->pdev->dev,
2915 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2916 ring->queue_index, pf_q, err);
2917 return -ENOMEM;
2918 }
2919
2920 /* set the context in the HMC */
2921 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2922 if (err) {
2923 dev_info(&vsi->back->pdev->dev,
2924 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2925 ring->queue_index, pf_q, err);
2926 return -ENOMEM;
2927 }
2928
2929 /* cache tail for quicker writes, and clear the reg before use */
2930 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2931 writel(0, ring->tail);
2932
a132af24
MW		 2933 if (ring_is_ps_enabled(ring)) {
2934 i40e_alloc_rx_headers(ring);
2935 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2936 } else {
2937 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2938 }
41c445ff
JB		 2939
2940 return 0;
2941}
2942
2943/**
2944 * i40e_vsi_configure_tx - Configure the VSI for Tx
2945 * @vsi: VSI structure describing this set of rings and resources
2946 *
2947 * Configure the Tx VSI for operation.
2948 **/
2949static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2950{
2951 int err = 0;
2952 u16 i;
2953
9f65e15b
AD		 2954 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2955 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2956
2957 return err;
2958}
2959
2960/**
2961 * i40e_vsi_configure_rx - Configure the VSI for Rx
2962 * @vsi: the VSI being configured
2963 *
2964 * Configure the Rx VSI for operation.
2965 **/
2966static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2967{
2968 int err = 0;
2969 u16 i;
2970
2971 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2972 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2973 + ETH_FCS_LEN + VLAN_HLEN;
2974 else
2975 vsi->max_frame = I40E_RXBUFFER_2048;
2976
2977 /* figure out correct receive buffer length */
2978 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2979 I40E_FLAG_RX_PS_ENABLED)) {
2980 case I40E_FLAG_RX_1BUF_ENABLED:
2981 vsi->rx_hdr_len = 0;
2982 vsi->rx_buf_len = vsi->max_frame;
2983 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2984 break;
2985 case I40E_FLAG_RX_PS_ENABLED:
2986 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2987 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2988 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2989 break;
2990 default:
2991 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2992 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2993 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2994 break;
2995 }
2996
38e00438
VD		 2997#ifdef I40E_FCOE
2998 /* setup rx buffer for FCoE */
2999 if ((vsi->type == I40E_VSI_FCOE) &&
3000 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
3001 vsi->rx_hdr_len = 0;
3002 vsi->rx_buf_len = I40E_RXBUFFER_3072;
3003 vsi->max_frame = I40E_RXBUFFER_3072;
3004 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
3005 }
3006
3007#endif /* I40E_FCOE */
41c445ff
JB		 3008 /* round up for the chip's needs */
3009 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 3010 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 3011 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 3012 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 3013
3014 /* set up individual rings */
3015 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 3016 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3017
3018 return err;
3019}
3020
3021/**
3022 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
3023 * @vsi: ptr to the VSI
3024 **/
3025static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
3026{
e7046ee1 3027 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 3028 u16 qoffset, qcount;
3029 int i, n;
3030
cd238a3e
PN		 3031 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3032 /* Reset the TC information */
3033 for (i = 0; i < vsi->num_queue_pairs; i++) {
3034 rx_ring = vsi->rx_rings[i];
3035 tx_ring = vsi->tx_rings[i];
3036 rx_ring->dcb_tc = 0;
3037 tx_ring->dcb_tc = 0;
3038 }
3039 }
41c445ff
JB		 3040
3041 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3042 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3043 continue;
3044
3045 qoffset = vsi->tc_config.tc_info[n].qoffset;
3046 qcount = vsi->tc_config.tc_info[n].qcount;
3047 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3048 rx_ring = vsi->rx_rings[i];
3049 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3050 rx_ring->dcb_tc = n;
3051 tx_ring->dcb_tc = n;
3052 }
3053 }
3054}
3055
3056/**
3057 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3058 * @vsi: ptr to the VSI
3059 **/
3060static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3061{
3062 if (vsi->netdev)
3063 i40e_set_rx_mode(vsi->netdev);
3064}
3065
17a73f6b
JG		 3066/**
3067 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3068 * @vsi: Pointer to the targeted VSI
3069 *
3070 * This function replays the hlist on the hw where all the SB Flow Director
3071 * filters were saved.
3072 **/
3073static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3074{
3075 struct i40e_fdir_filter *filter;
3076 struct i40e_pf *pf = vsi->back;
3077 struct hlist_node *node;
3078
55a5e60b
ASJ		 3079 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3080 return;
3081
17a73f6b
JG		 3082 hlist_for_each_entry_safe(filter, node,
3083 &pf->fdir_filter_list, fdir_node) {
3084 i40e_add_del_fdir(vsi, filter, true);
3085 }
3086}
3087
41c445ff
JB		 3088/**
3089 * i40e_vsi_configure - Set up the VSI for action
3090 * @vsi: the VSI being configured
3091 **/
3092static int i40e_vsi_configure(struct i40e_vsi *vsi)
3093{
3094 int err;
3095
3096 i40e_set_vsi_rx_mode(vsi);
3097 i40e_restore_vlan(vsi);
3098 i40e_vsi_config_dcb_rings(vsi);
3099 err = i40e_vsi_configure_tx(vsi);
3100 if (!err)
3101 err = i40e_vsi_configure_rx(vsi);
3102
3103 return err;
3104}
3105
3106/**
3107 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3108 * @vsi: the VSI being configured
3109 **/
3110static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3111{
3112 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3113 struct i40e_hw *hw = &pf->hw;
3114 u16 vector;
3115 int i, q;
41c445ff
JB		 3116 u32 qp;
3117
3118 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3119 * and PFINT_LNKLSTn registers, e.g.:
3120 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3121 */
3122 qp = vsi->base_queue;
3123 vector = vsi->base_vector;
493fb300 3124 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3125 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3126
ee2319cf 3127 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3128 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting);
41c445ff
JB		 3129 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3130 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3131 q_vector->rx.itr);
a75e8005 3132 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting);
41c445ff
JB		 3133 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3134 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3135 q_vector->tx.itr);
ac26fc13
JB		 3136 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3137 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3138
3139 /* Linked list for the queuepairs assigned to this vector */
3140 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3141 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3142 u32 val;
3143
41c445ff
JB		 3144 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3145 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3146 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3147 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3148 (I40E_QUEUE_TYPE_TX
3149 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3150
3151 wr32(hw, I40E_QINT_RQCTL(qp), val);
3152
3153 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3154 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3155 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3156 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3157 (I40E_QUEUE_TYPE_RX
3158 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3159
3160 /* Terminate the linked list */
3161 if (q == (q_vector->num_ringpairs - 1))
3162 val |= (I40E_QUEUE_END_OF_LIST
3163 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3164
3165 wr32(hw, I40E_QINT_TQCTL(qp), val);
3166 qp++;
3167 }
3168 }
3169
3170 i40e_flush(hw);
3171}
3172
3173/**
3174 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3175 * @hw: ptr to the hardware info
3176 **/
ab437b5a 3177static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3178{
ab437b5a 3179 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3180 u32 val;
3181
3182 /* clear things first */
3183 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3184 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3185
3186 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3187 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3188 I40E_PFINT_ICR0_ENA_GRST_MASK |
3189 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3190 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3191 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3192 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3193 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3194
0d8e1439
ASJ		 3195 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3196 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3197
ab437b5a
JK		 3198 if (pf->flags & I40E_FLAG_PTP)
3199 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3200
41c445ff
JB		 3201 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3202
3203 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3204 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3205 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3206
3207 /* OTHER_ITR_IDX = 0 */
3208 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3209}
3210
3211/**
3212 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3213 * @vsi: the VSI being configured
3214 **/
3215static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3216{
493fb300 3217 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3218 struct i40e_pf *pf = vsi->back;
3219 struct i40e_hw *hw = &pf->hw;
3220 u32 val;
3221
3222 /* set the ITR configuration */
ee2319cf 3223 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3224 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting);
41c445ff
JB		 3225 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3226 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
a75e8005 3227 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting);
41c445ff
JB		 3228 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3229 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3230
ab437b5a 3231 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3232
3233 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3234 wr32(hw, I40E_PFINT_LNKLST0, 0);
3235
f29eaa3d 3236 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3237 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3238 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3239 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3240
3241 wr32(hw, I40E_QINT_RQCTL(0), val);
3242
3243 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3244 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3245 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3246
3247 wr32(hw, I40E_QINT_TQCTL(0), val);
3248 i40e_flush(hw);
3249}
3250
2ef28cfb
MW		 3251/**
3252 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3253 * @pf: board private structure
3254 **/
3255void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3256{
3257 struct i40e_hw *hw = &pf->hw;
3258
3259 wr32(hw, I40E_PFINT_DYN_CTL0,
3260 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3261 i40e_flush(hw);
3262}
3263
41c445ff
JB		 3264/**
3265 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3266 * @pf: board private structure
40d72a50 3267 * @clearpba: true when all pending interrupt events should be cleared
41c445ff 3268 **/
40d72a50 3269void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba)
41c445ff
JB		 3270{
3271 struct i40e_hw *hw = &pf->hw;
3272 u32 val;
3273
3274 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
40d72a50 3275 (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) |
41c445ff
JB		 3276 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3277
3278 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3279 i40e_flush(hw);
3280}
3281
41c445ff
JB		 3282/**
3283 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3284 * @irq: interrupt number
3285 * @data: pointer to a q_vector
3286 **/
3287static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3288{
3289 struct i40e_q_vector *q_vector = data;
3290
cd0b6fa6 3291 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3292 return IRQ_HANDLED;
3293
5d3465a1 3294 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3295
3296 return IRQ_HANDLED;
3297}
3298
41c445ff
JB		 3299/**
3300 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3301 * @vsi: the VSI being configured
3302 * @basename: name for the vector
3303 *
3304 * Allocates MSI-X vectors and requests interrupts from the kernel.
3305 **/
3306static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3307{
3308 int q_vectors = vsi->num_q_vectors;
3309 struct i40e_pf *pf = vsi->back;
3310 int base = vsi->base_vector;
3311 int rx_int_idx = 0;
3312 int tx_int_idx = 0;
3313 int vector, err;
3314
3315 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3316 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3317
cd0b6fa6 3318 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3319 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3320 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3321 tx_int_idx++;
cd0b6fa6 3322 } else if (q_vector->rx.ring) {
41c445ff
JB		 3323 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3324 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3325 } else if (q_vector->tx.ring) {
41c445ff
JB		 3326 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3327 "%s-%s-%d", basename, "tx", tx_int_idx++);
3328 } else {
3329 /* skip this unused q_vector */
3330 continue;
3331 }
3332 err = request_irq(pf->msix_entries[base + vector].vector,
3333 vsi->irq_handler,
3334 0,
3335 q_vector->name,
3336 q_vector);
3337 if (err) {
3338 dev_info(&pf->pdev->dev,
fb43201f 3339 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3340 goto free_queue_irqs;
3341 }
3342 /* assign the mask for this irq */
3343 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3344 &q_vector->affinity_mask);
3345 }
3346
63741846 3347 vsi->irqs_ready = true;
41c445ff
JB		 3348 return 0;
3349
3350free_queue_irqs:
3351 while (vector) {
3352 vector--;
3353 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3354 NULL);
3355 free_irq(pf->msix_entries[base + vector].vector,
3356 &(vsi->q_vectors[vector]));
3357 }
3358 return err;
3359}
3360
3361/**
3362 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3363 * @vsi: the VSI being un-configured
3364 **/
3365static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3366{
3367 struct i40e_pf *pf = vsi->back;
3368 struct i40e_hw *hw = &pf->hw;
3369 int base = vsi->base_vector;
3370 int i;
3371
3372 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3373 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3374 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3375 }
3376
3377 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3378 for (i = vsi->base_vector;
3379 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3380 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3381
3382 i40e_flush(hw);
3383 for (i = 0; i < vsi->num_q_vectors; i++)
3384 synchronize_irq(pf->msix_entries[i + base].vector);
3385 } else {
3386 /* Legacy and MSI mode - this stops all interrupt handling */
3387 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3388 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3389 i40e_flush(hw);
3390 synchronize_irq(pf->pdev->irq);
3391 }
3392}
3393
3394/**
3395 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3396 * @vsi: the VSI being configured
3397 **/
3398static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3399{
3400 struct i40e_pf *pf = vsi->back;
3401 int i;
3402
3403 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3404 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3405 i40e_irq_dynamic_enable(vsi, i);
3406 } else {
40d72a50 3407 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 3408 }
3409
1022cb6c 3410 i40e_flush(&pf->hw);
41c445ff
JB		 3411 return 0;
3412}
3413
3414/**
3415 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3416 * @pf: board private structure
3417 **/
3418static void i40e_stop_misc_vector(struct i40e_pf *pf)
3419{
3420 /* Disable ICR 0 */
3421 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3422 i40e_flush(&pf->hw);
3423}
3424
3425/**
3426 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3427 * @irq: interrupt number
3428 * @data: pointer to a q_vector
3429 *
3430 * This is the handler used for all MSI/Legacy interrupts, and deals
3431 * with both queue and non-queue interrupts. This is also used in
3432 * MSIX mode to handle the non-queue interrupts.
3433 **/
3434static irqreturn_t i40e_intr(int irq, void *data)
3435{
3436 struct i40e_pf *pf = (struct i40e_pf *)data;
3437 struct i40e_hw *hw = &pf->hw;
5e823066 3438 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3439 u32 icr0, icr0_remaining;
3440 u32 val, ena_mask;
3441
3442 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3443 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3444
116a57d4
SN		 3445 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3446 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3447 goto enable_intr;
41c445ff 3448
cd92e72f
SN		 3449 /* if interrupt but no bits showing, must be SWINT */
3450 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3451 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3452 pf->sw_int_count++;
3453
0d8e1439
ASJ		 3454 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3455 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3456 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3457 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3458 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3459 }
3460
41c445ff
JB		 3461 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3462 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3463 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3464 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff 3465
a16ae2d5
ASJ		 3466 /* We do not have a way to disarm Queue causes while leaving
3467 * interrupt enabled for all other causes, ideally
3468 * interrupt should be disabled while we are in NAPI but
3469 * this is not a performance path and napi_schedule()
3470 * can deal with rescheduling.
3471 */
41c445ff 3472 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3473 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3474 }
3475
3476 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3477 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3478 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6e93d0c9 3479 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n");
41c445ff
JB		 3480 }
3481
3482 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3483 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3484 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3485 }
3486
3487 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3488 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3489 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3490 }
3491
3492 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3493 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3494 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3495 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3496 val = rd32(hw, I40E_GLGEN_RSTAT);
3497 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3498 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3499 if (val == I40E_RESET_CORER) {
41c445ff 3500 pf->corer_count++;
4eb3f768 3501 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3502 pf->globr_count++;
4eb3f768 3503 } else if (val == I40E_RESET_EMPR) {
41c445ff 3504 pf->empr_count++;
9df42d1a 3505 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3506 }
41c445ff
JB		 3507 }
3508
9c010ee0
ASJ		 3509 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3510 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3511 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3512 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3513 rd32(hw, I40E_PFHMC_ERRORINFO),
3514 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3515 }
3516
beb0dff1
JK		 3517 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3518 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3519
3520 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3521 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3522 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3523 }
beb0dff1
JK		 3524 }
3525
41c445ff
JB		 3526 /* If a critical error is pending we have no choice but to reset the
3527 * device.
3528 * Report and mask out any remaining unexpected interrupts.
3529 */
3530 icr0_remaining = icr0 & ena_mask;
3531 if (icr0_remaining) {
3532 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3533 icr0_remaining);
9c010ee0 3534 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3535 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3536 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3537 dev_info(&pf->pdev->dev, "device will be reset\n");
3538 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3539 i40e_service_event_schedule(pf);
41c445ff
JB		 3540 }
3541 ena_mask &= ~icr0_remaining;
3542 }
5e823066 3543 ret = IRQ_HANDLED;
41c445ff 3544
5e823066 3545enable_intr:
41c445ff
JB		 3546 /* re-enable interrupt causes */
3547 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3548 if (!test_bit(__I40E_DOWN, &pf->state)) {
3549 i40e_service_event_schedule(pf);
40d72a50 3550 i40e_irq_dynamic_enable_icr0(pf, false);
41c445ff
JB		 3551 }
3552
5e823066 3553 return ret;
41c445ff
JB		 3554}
3555
cbf61325
ASJ		 3556/**
3557 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3558 * @tx_ring: tx ring to clean
3559 * @budget: how many cleans we're allowed
3560 *
3561 * Returns true if there's any budget left (e.g. the clean is finished)
3562 **/
3563static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3564{
3565 struct i40e_vsi *vsi = tx_ring->vsi;
3566 u16 i = tx_ring->next_to_clean;
3567 struct i40e_tx_buffer *tx_buf;
3568 struct i40e_tx_desc *tx_desc;
3569
3570 tx_buf = &tx_ring->tx_bi[i];
3571 tx_desc = I40E_TX_DESC(tx_ring, i);
3572 i -= tx_ring->count;
3573
3574 do {
3575 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3576
3577 /* if next_to_watch is not set then there is no work pending */
3578 if (!eop_desc)
3579 break;
3580
3581 /* prevent any other reads prior to eop_desc */
3582 read_barrier_depends();
3583
3584 /* if the descriptor isn't done, no work yet to do */
3585 if (!(eop_desc->cmd_type_offset_bsz &
3586 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3587 break;
3588
3589 /* clear next_to_watch to prevent false hangs */
3590 tx_buf->next_to_watch = NULL;
3591
49d7d933
ASJ		 3592 tx_desc->buffer_addr = 0;
3593 tx_desc->cmd_type_offset_bsz = 0;
3594 /* move past filter desc */
3595 tx_buf++;
3596 tx_desc++;
3597 i++;
3598 if (unlikely(!i)) {
3599 i -= tx_ring->count;
3600 tx_buf = tx_ring->tx_bi;
3601 tx_desc = I40E_TX_DESC(tx_ring, 0);
3602 }
cbf61325
ASJ		 3603 /* unmap skb header data */
3604 dma_unmap_single(tx_ring->dev,
3605 dma_unmap_addr(tx_buf, dma),
3606 dma_unmap_len(tx_buf, len),
3607 DMA_TO_DEVICE);
49d7d933
ASJ		 3608 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3609 kfree(tx_buf->raw_buf);
cbf61325 3610
49d7d933
ASJ		 3611 tx_buf->raw_buf = NULL;
3612 tx_buf->tx_flags = 0;
3613 tx_buf->next_to_watch = NULL;
cbf61325 3614 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3615 tx_desc->buffer_addr = 0;
3616 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3617
49d7d933 3618 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3619 tx_buf++;
3620 tx_desc++;
3621 i++;
3622 if (unlikely(!i)) {
3623 i -= tx_ring->count;
3624 tx_buf = tx_ring->tx_bi;
3625 tx_desc = I40E_TX_DESC(tx_ring, 0);
3626 }
3627
3628 /* update budget accounting */
3629 budget--;
3630 } while (likely(budget));
3631
3632 i += tx_ring->count;
3633 tx_ring->next_to_clean = i;
3634
6995b36c 3635 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3636 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3637
cbf61325
ASJ		 3638 return budget > 0;
3639}
3640
3641/**
3642 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3643 * @irq: interrupt number
3644 * @data: pointer to a q_vector
3645 **/
3646static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3647{
3648 struct i40e_q_vector *q_vector = data;
3649 struct i40e_vsi *vsi;
3650
3651 if (!q_vector->tx.ring)
3652 return IRQ_HANDLED;
3653
3654 vsi = q_vector->tx.ring->vsi;
3655 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3656
3657 return IRQ_HANDLED;
3658}
3659
41c445ff 3660/**
cd0b6fa6 3661 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3662 * @vsi: the VSI being configured
3663 * @v_idx: vector index
cd0b6fa6 3664 * @qp_idx: queue pair index
41c445ff 3665 **/
26cdc443 3666static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3667{
493fb300 3668 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3669 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3670 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3671
3672 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3673 tx_ring->next = q_vector->tx.ring;
3674 q_vector->tx.ring = tx_ring;
41c445ff 3675 q_vector->tx.count++;
cd0b6fa6
AD		 3676
3677 rx_ring->q_vector = q_vector;
3678 rx_ring->next = q_vector->rx.ring;
3679 q_vector->rx.ring = rx_ring;
3680 q_vector->rx.count++;
41c445ff
JB		 3681}
3682
3683/**
3684 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3685 * @vsi: the VSI being configured
3686 *
3687 * This function maps descriptor rings to the queue-specific vectors
3688 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3689 * one vector per queue pair, but on a constrained vector budget, we
3690 * group the queue pairs as "efficiently" as possible.
3691 **/
3692static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3693{
3694 int qp_remaining = vsi->num_queue_pairs;
3695 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3696 int num_ringpairs;
41c445ff
JB		 3697 int v_start = 0;
3698 int qp_idx = 0;
3699
3700 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3701 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3702 * It is also important to go through all the vectors available to be
3703 * sure that if we don't use all the vectors, that the remaining vectors
3704 * are cleared. This is especially important when decreasing the
3705 * number of queues in use.
41c445ff 3706 */
70114ec4 3707 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3708 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3709
3710 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3711
3712 q_vector->num_ringpairs = num_ringpairs;
3713
3714 q_vector->rx.count = 0;
3715 q_vector->tx.count = 0;
3716 q_vector->rx.ring = NULL;
3717 q_vector->tx.ring = NULL;
3718
3719 while (num_ringpairs--) {
26cdc443 3720 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3721 qp_idx++;
3722 qp_remaining--;
41c445ff
JB		 3723 }
3724 }
3725}
3726
3727/**
3728 * i40e_vsi_request_irq - Request IRQ from the OS
3729 * @vsi: the VSI being configured
3730 * @basename: name for the vector
3731 **/
3732static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3733{
3734 struct i40e_pf *pf = vsi->back;
3735 int err;
3736
3737 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3738 err = i40e_vsi_request_irq_msix(vsi, basename);
3739 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3740 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3741 pf->int_name, pf);
41c445ff
JB		 3742 else
3743 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3744 pf->int_name, pf);
41c445ff
JB		 3745
3746 if (err)
3747 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3748
3749 return err;
3750}
3751
3752#ifdef CONFIG_NET_POLL_CONTROLLER
3753/**
d89d967f 3754 * i40e_netpoll - A Polling 'interrupt' handler
41c445ff
JB		 3755 * @netdev: network interface device structure
3756 *
3757 * This is used by netconsole to send skbs without having to re-enable
3758 * interrupts. It's not called while the normal interrupt routine is executing.
3759 **/
38e00438
VD		 3760#ifdef I40E_FCOE
3761void i40e_netpoll(struct net_device *netdev)
3762#else
41c445ff 3763static void i40e_netpoll(struct net_device *netdev)
38e00438 3764#endif
41c445ff
JB		 3765{
3766 struct i40e_netdev_priv *np = netdev_priv(netdev);
3767 struct i40e_vsi *vsi = np->vsi;
3768 struct i40e_pf *pf = vsi->back;
3769 int i;
3770
3771 /* if interface is down do nothing */
3772 if (test_bit(__I40E_DOWN, &vsi->state))
3773 return;
3774
41c445ff
JB		 3775 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3776 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3777 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3778 } else {
3779 i40e_intr(pf->pdev->irq, netdev);
3780 }
41c445ff
JB		 3781}
3782#endif
3783
23527308
NP		 3784/**
3785 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3786 * @pf: the PF being configured
3787 * @pf_q: the PF queue
3788 * @enable: enable or disable state of the queue
3789 *
3790 * This routine will wait for the given Tx queue of the PF to reach the
3791 * enabled or disabled state.
3792 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3793 * multiple retries; else will return 0 in case of success.
3794 **/
3795static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3796{
3797 int i;
3798 u32 tx_reg;
3799
3800 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3801 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3802 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3803 break;
3804
f98a2006 3805 usleep_range(10, 20);
23527308
NP		 3806 }
3807 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3808 return -ETIMEDOUT;
3809
3810 return 0;
3811}
3812
41c445ff
JB		 3813/**
3814 * i40e_vsi_control_tx - Start or stop a VSI's rings
3815 * @vsi: the VSI being configured
3816 * @enable: start or stop the rings
3817 **/
3818static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3819{
3820 struct i40e_pf *pf = vsi->back;
3821 struct i40e_hw *hw = &pf->hw;
23527308 3822 int i, j, pf_q, ret = 0;
41c445ff
JB		 3823 u32 tx_reg;
3824
3825 pf_q = vsi->base_queue;
3826 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3827
3828 /* warn the TX unit of coming changes */
3829 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3830 if (!enable)
f98a2006 3831 usleep_range(10, 20);
351499ab 3832
6c5ef620 3833 for (j = 0; j < 50; j++) {
41c445ff 3834 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3835 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3836 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3837 break;
3838 usleep_range(1000, 2000);
3839 }
fda972f6 3840 /* Skip if the queue is already in the requested state */
7c122007 3841 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3842 continue;
41c445ff
JB		 3843
3844 /* turn on/off the queue */
c5c9eb9e
SN		 3845 if (enable) {
3846 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3847 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3848 } else {
41c445ff 3849 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3850 }
41c445ff
JB		 3851
3852 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3853 /* No waiting for the Tx queue to disable */
3854 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3855 continue;
41c445ff
JB		 3856
3857 /* wait for the change to finish */
23527308
NP		 3858 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3859 if (ret) {
3860 dev_info(&pf->pdev->dev,
fb43201f
SN		 3861 "VSI seid %d Tx ring %d %sable timeout\n",
3862 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3863 break;
41c445ff
JB		 3864 }
3865 }
3866
7134f9ce
JB		 3867 if (hw->revision_id == 0)
3868 mdelay(50);
23527308
NP		 3869 return ret;
3870}
3871
3872/**
3873 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3874 * @pf: the PF being configured
3875 * @pf_q: the PF queue
3876 * @enable: enable or disable state of the queue
3877 *
3878 * This routine will wait for the given Rx queue of the PF to reach the
3879 * enabled or disabled state.
3880 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3881 * multiple retries; else will return 0 in case of success.
3882 **/
3883static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3884{
3885 int i;
3886 u32 rx_reg;
3887
3888 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3889 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3890 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3891 break;
3892
f98a2006 3893 usleep_range(10, 20);
23527308
NP		 3894 }
3895 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3896 return -ETIMEDOUT;
7134f9ce 3897
41c445ff
JB		 3898 return 0;
3899}
3900
3901/**
3902 * i40e_vsi_control_rx - Start or stop a VSI's rings
3903 * @vsi: the VSI being configured
3904 * @enable: start or stop the rings
3905 **/
3906static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3907{
3908 struct i40e_pf *pf = vsi->back;
3909 struct i40e_hw *hw = &pf->hw;
23527308 3910 int i, j, pf_q, ret = 0;
41c445ff
JB		 3911 u32 rx_reg;
3912
3913 pf_q = vsi->base_queue;
3914 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3915 for (j = 0; j < 50; j++) {
41c445ff 3916 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3917 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3918 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3919 break;
3920 usleep_range(1000, 2000);
3921 }
41c445ff 3922
7c122007
CS		 3923 /* Skip if the queue is already in the requested state */
3924 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3925 continue;
41c445ff
JB		 3926
3927 /* turn on/off the queue */
3928 if (enable)
6c5ef620 3929 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3930 else
6c5ef620 3931 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3932 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3fe06f41
NP		 3933 /* No waiting for the Tx queue to disable */
3934 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3935 continue;
41c445ff
JB		 3936
3937 /* wait for the change to finish */
23527308
NP		 3938 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3939 if (ret) {
3940 dev_info(&pf->pdev->dev,
fb43201f
SN		 3941 "VSI seid %d Rx ring %d %sable timeout\n",
3942 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3943 break;
41c445ff
JB		 3944 }
3945 }
3946
23527308 3947 return ret;
41c445ff
JB		 3948}
3949
3950/**
3951 * i40e_vsi_control_rings - Start or stop a VSI's rings
3952 * @vsi: the VSI being configured
3953 * @enable: start or stop the rings
3954 **/
fc18eaa0 3955int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3956{
3b867b28 3957 int ret = 0;
41c445ff
JB		 3958
3959 /* do rx first for enable and last for disable */
3960 if (request) {
3961 ret = i40e_vsi_control_rx(vsi, request);
3962 if (ret)
3963 return ret;
3964 ret = i40e_vsi_control_tx(vsi, request);
3965 } else {
3b867b28
ASJ		 3966 /* Ignore return value, we need to shutdown whatever we can */
3967 i40e_vsi_control_tx(vsi, request);
3968 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3969 }
3970
3971 return ret;
3972}
3973
3974/**
3975 * i40e_vsi_free_irq - Free the irq association with the OS
3976 * @vsi: the VSI being configured
3977 **/
3978static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3979{
3980 struct i40e_pf *pf = vsi->back;
3981 struct i40e_hw *hw = &pf->hw;
3982 int base = vsi->base_vector;
3983 u32 val, qp;
3984 int i;
3985
3986 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3987 if (!vsi->q_vectors)
3988 return;
3989
63741846
SN		 3990 if (!vsi->irqs_ready)
3991 return;
3992
3993 vsi->irqs_ready = false;
41c445ff
JB		 3994 for (i = 0; i < vsi->num_q_vectors; i++) {
3995 u16 vector = i + base;
3996
3997 /* free only the irqs that were actually requested */
78681b1f
SN		 3998 if (!vsi->q_vectors[i] ||
3999 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 4000 continue;
4001
4002 /* clear the affinity_mask in the IRQ descriptor */
4003 irq_set_affinity_hint(pf->msix_entries[vector].vector,
4004 NULL);
4005 free_irq(pf->msix_entries[vector].vector,
493fb300 4006 vsi->q_vectors[i]);
41c445ff
JB		 4007
4008 /* Tear down the interrupt queue link list
4009 *
4010 * We know that they come in pairs and always
4011 * the Rx first, then the Tx. To clear the
4012 * link list, stick the EOL value into the
4013 * next_q field of the registers.
4014 */
4015 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
4016 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4017 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4018 val |= I40E_QUEUE_END_OF_LIST
4019 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4020 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4021
4022 while (qp != I40E_QUEUE_END_OF_LIST) {
4023 u32 next;
4024
4025 val = rd32(hw, I40E_QINT_RQCTL(qp));
4026
4027 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4028 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4029 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4030 I40E_QINT_RQCTL_INTEVENT_MASK);
4031
4032 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4033 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4034
4035 wr32(hw, I40E_QINT_RQCTL(qp), val);
4036
4037 val = rd32(hw, I40E_QINT_TQCTL(qp));
4038
4039 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4040 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4041
4042 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4043 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4044 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4045 I40E_QINT_TQCTL_INTEVENT_MASK);
4046
4047 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4048 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4049
4050 wr32(hw, I40E_QINT_TQCTL(qp), val);
4051 qp = next;
4052 }
4053 }
4054 } else {
4055 free_irq(pf->pdev->irq, pf);
4056
4057 val = rd32(hw, I40E_PFINT_LNKLST0);
4058 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4059 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4060 val |= I40E_QUEUE_END_OF_LIST
4061 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4062 wr32(hw, I40E_PFINT_LNKLST0, val);
4063
4064 val = rd32(hw, I40E_QINT_RQCTL(qp));
4065 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4066 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4067 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4068 I40E_QINT_RQCTL_INTEVENT_MASK);
4069
4070 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4071 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4072
4073 wr32(hw, I40E_QINT_RQCTL(qp), val);
4074
4075 val = rd32(hw, I40E_QINT_TQCTL(qp));
4076
4077 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4078 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4079 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4080 I40E_QINT_TQCTL_INTEVENT_MASK);
4081
4082 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4083 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4084
4085 wr32(hw, I40E_QINT_TQCTL(qp), val);
4086 }
4087}
4088
493fb300
AD		 4089/**
4090 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4091 * @vsi: the VSI being configured
4092 * @v_idx: Index of vector to be freed
4093 *
4094 * This function frees the memory allocated to the q_vector. In addition if
4095 * NAPI is enabled it will delete any references to the NAPI struct prior
4096 * to freeing the q_vector.
4097 **/
4098static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4099{
4100 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4101 struct i40e_ring *ring;
493fb300
AD		 4102
4103 if (!q_vector)
4104 return;
4105
4106 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4107 i40e_for_each_ring(ring, q_vector->tx)
4108 ring->q_vector = NULL;
4109
4110 i40e_for_each_ring(ring, q_vector->rx)
4111 ring->q_vector = NULL;
493fb300
AD		 4112
4113 /* only VSI w/ an associated netdev is set up w/ NAPI */
4114 if (vsi->netdev)
4115 netif_napi_del(&q_vector->napi);
4116
4117 vsi->q_vectors[v_idx] = NULL;
4118
4119 kfree_rcu(q_vector, rcu);
4120}
4121
41c445ff
JB		 4122/**
4123 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4124 * @vsi: the VSI being un-configured
4125 *
4126 * This frees the memory allocated to the q_vectors and
4127 * deletes references to the NAPI struct.
4128 **/
4129static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4130{
4131 int v_idx;
4132
493fb300
AD		 4133 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4134 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4135}
4136
4137/**
4138 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4139 * @pf: board private structure
4140 **/
4141static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4142{
4143 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4144 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4145 pci_disable_msix(pf->pdev);
4146 kfree(pf->msix_entries);
4147 pf->msix_entries = NULL;
3b444399
SN		 4148 kfree(pf->irq_pile);
4149 pf->irq_pile = NULL;
41c445ff
JB		 4150 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4151 pci_disable_msi(pf->pdev);
4152 }
4153 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4154}
4155
4156/**
4157 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4158 * @pf: board private structure
4159 *
4160 * We go through and clear interrupt specific resources and reset the structure
4161 * to pre-load conditions
4162 **/
4163static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4164{
4165 int i;
4166
e147758d 4167 i40e_stop_misc_vector(pf);
69278398 4168 if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) {
e147758d
SN		 4169 synchronize_irq(pf->msix_entries[0].vector);
4170 free_irq(pf->msix_entries[0].vector, pf);
4171 }
4172
e3219ce6
ASJ		 4173 i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector,
4174 I40E_IWARP_IRQ_PILE_ID);
4175
41c445ff 4176 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4177 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4178 if (pf->vsi[i])
4179 i40e_vsi_free_q_vectors(pf->vsi[i]);
4180 i40e_reset_interrupt_capability(pf);
4181}
4182
4183/**
4184 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4185 * @vsi: the VSI being configured
4186 **/
4187static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4188{
4189 int q_idx;
4190
4191 if (!vsi->netdev)
4192 return;
4193
4194 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4195 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4196}
4197
4198/**
4199 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4200 * @vsi: the VSI being configured
4201 **/
4202static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4203{
4204 int q_idx;
4205
4206 if (!vsi->netdev)
4207 return;
4208
4209 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4210 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4211}
4212
90ef8d47
SN		 4213/**
4214 * i40e_vsi_close - Shut down a VSI
4215 * @vsi: the vsi to be quelled
4216 **/
4217static void i40e_vsi_close(struct i40e_vsi *vsi)
4218{
e3219ce6
ASJ		 4219 bool reset = false;
4220
90ef8d47
SN		 4221 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4222 i40e_down(vsi);
4223 i40e_vsi_free_irq(vsi);
4224 i40e_vsi_free_tx_resources(vsi);
4225 i40e_vsi_free_rx_resources(vsi);
92faef85 4226 vsi->current_netdev_flags = 0;
e3219ce6
ASJ		 4227 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4228 reset = true;
4229 i40e_notify_client_of_netdev_close(vsi, reset);
90ef8d47
SN		 4230}
4231
41c445ff
JB		 4232/**
4233 * i40e_quiesce_vsi - Pause a given VSI
4234 * @vsi: the VSI being paused
4235 **/
4236static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4237{
4238 if (test_bit(__I40E_DOWN, &vsi->state))
4239 return;
4240
d341b7a5
NP		 4241 /* No need to disable FCoE VSI when Tx suspended */
4242 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4243 vsi->type == I40E_VSI_FCOE) {
4244 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4245 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4246 return;
4247 }
4248
41c445ff 4249 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4250 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4251 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4252 else
90ef8d47 4253 i40e_vsi_close(vsi);
41c445ff
JB		 4254}
4255
4256/**
4257 * i40e_unquiesce_vsi - Resume a given VSI
4258 * @vsi: the VSI being resumed
4259 **/
4260static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4261{
4262 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4263 return;
4264
4265 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4266 if (vsi->netdev && netif_running(vsi->netdev))
4267 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4268 else
8276f757 4269 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4270}
4271
4272/**
4273 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4274 * @pf: the PF
4275 **/
4276static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4277{
4278 int v;
4279
505682cd 4280 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4281 if (pf->vsi[v])
4282 i40e_quiesce_vsi(pf->vsi[v]);
4283 }
4284}
4285
4286/**
4287 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4288 * @pf: the PF
4289 **/
4290static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4291{
4292 int v;
4293
505682cd 4294 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4295 if (pf->vsi[v])
4296 i40e_unquiesce_vsi(pf->vsi[v]);
4297 }
4298}
4299
69129dc3
NP		 4300#ifdef CONFIG_I40E_DCB
4301/**
3fe06f41 4302 * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled
69129dc3
NP		 4303 * @vsi: the VSI being configured
4304 *
3fe06f41 4305 * This function waits for the given VSI's queues to be disabled.
69129dc3 4306 **/
3fe06f41 4307static int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi)
69129dc3
NP		 4308{
4309 struct i40e_pf *pf = vsi->back;
4310 int i, pf_q, ret;
4311
4312 pf_q = vsi->base_queue;
4313 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4314 /* Check and wait for the disable status of the queue */
4315 ret = i40e_pf_txq_wait(pf, pf_q, false);
4316 if (ret) {
4317 dev_info(&pf->pdev->dev,
fb43201f
SN		 4318 "VSI seid %d Tx ring %d disable timeout\n",
4319 vsi->seid, pf_q);
69129dc3
NP		 4320 return ret;
4321 }
4322 }
4323
3fe06f41
NP		 4324 pf_q = vsi->base_queue;
4325 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4326 /* Check and wait for the disable status of the queue */
4327 ret = i40e_pf_rxq_wait(pf, pf_q, false);
4328 if (ret) {
4329 dev_info(&pf->pdev->dev,
4330 "VSI seid %d Rx ring %d disable timeout\n",
4331 vsi->seid, pf_q);
4332 return ret;
4333 }
4334 }
4335
69129dc3
NP		 4336 return 0;
4337}
4338
4339/**
3fe06f41 4340 * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled
69129dc3
NP		 4341 * @pf: the PF
4342 *
3fe06f41 4343 * This function waits for the queues to be in disabled state for all the
69129dc3
NP		 4344 * VSIs that are managed by this PF.
4345 **/
3fe06f41 4346static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf)
69129dc3
NP		 4347{
4348 int v, ret = 0;
4349
4350 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4351 /* No need to wait for FCoE VSI queues */
4352 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
3fe06f41 4353 ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]);
69129dc3
NP		 4354 if (ret)
4355 break;
4356 }
4357 }
4358
4359 return ret;
4360}
4361
4362#endif
b03a8c1f
KP		 4363
4364/**
4365 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4366 * @q_idx: TX queue number
4367 * @vsi: Pointer to VSI struct
4368 *
4369 * This function checks specified queue for given VSI. Detects hung condition.
4370 * Sets hung bit since it is two step process. Before next run of service task
4371 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4372 * hung condition remain unchanged and during subsequent run, this function
4373 * issues SW interrupt to recover from hung condition.
4374 **/
4375static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4376{
4377 struct i40e_ring *tx_ring = NULL;
4378 struct i40e_pf *pf;
dd353109 4379 u32 head, val, tx_pending_hw;
b03a8c1f
KP		 4380 int i;
4381
4382 pf = vsi->back;
4383
4384 /* now that we have an index, find the tx_ring struct */
4385 for (i = 0; i < vsi->num_queue_pairs; i++) {
4386 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4387 if (q_idx == vsi->tx_rings[i]->queue_index) {
4388 tx_ring = vsi->tx_rings[i];
4389 break;
4390 }
4391 }
4392 }
4393
4394 if (!tx_ring)
4395 return;
4396
4397 /* Read interrupt register */
4398 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4399 val = rd32(&pf->hw,
4400 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4401 tx_ring->vsi->base_vector - 1));
4402 else
4403 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4404
4405 head = i40e_get_head(tx_ring);
4406
dd353109 4407 tx_pending_hw = i40e_get_tx_pending(tx_ring, false);
b03a8c1f 4408
9c6c1259
KP		 4409 /* HW is done executing descriptors, updated HEAD write back,
4410 * but SW hasn't processed those descriptors. If interrupt is
4411 * not generated from this point ON, it could result into
4412 * dev_watchdog detecting timeout on those netdev_queue,
4413 * hence proactively trigger SW interrupt.
b03a8c1f 4414 */
dd353109 4415 if (tx_pending_hw && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
9c6c1259
KP		 4416 /* NAPI Poll didn't run and clear since it was set */
4417 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4418 &tx_ring->q_vector->hung_detected)) {
dd353109
ASJ		 4419 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending_hw: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4420 vsi->seid, q_idx, tx_pending_hw,
9c6c1259
KP		 4421 tx_ring->next_to_clean, head,
4422 tx_ring->next_to_use,
4423 readl(tx_ring->tail));
4424 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4425 vsi->seid, q_idx, val);
4426 i40e_force_wb(vsi, tx_ring->q_vector);
4427 } else {
4428 /* First Chance - detected possible hung */
4429 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4430 &tx_ring->q_vector->hung_detected);
4431 }
4432 }
dd353109
ASJ		 4433
4434 /* This is the case where we have interrupts missing,
4435 * so the tx_pending in HW will most likely be 0, but we
4436 * will have tx_pending in SW since the WB happened but the
4437 * interrupt got lost.
4438 */
4439 if ((!tx_pending_hw) && i40e_get_tx_pending(tx_ring, true) &&
4440 (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
4441 if (napi_reschedule(&tx_ring->q_vector->napi))
4442 tx_ring->tx_stats.tx_lost_interrupt++;
4443 }
b03a8c1f
KP		 4444}
4445
4446/**
4447 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4448 * @pf: pointer to PF struct
4449 *
4450 * LAN VSI has netdev and netdev has TX queues. This function is to check
4451 * each of those TX queues if they are hung, trigger recovery by issuing
4452 * SW interrupt.
4453 **/
4454static void i40e_detect_recover_hung(struct i40e_pf *pf)
4455{
4456 struct net_device *netdev;
4457 struct i40e_vsi *vsi;
4458 int i;
4459
4460 /* Only for LAN VSI */
4461 vsi = pf->vsi[pf->lan_vsi];
4462
4463 if (!vsi)
4464 return;
4465
4466 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4467 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4468 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4469 return;
4470
4471 /* Make sure type is MAIN VSI */
4472 if (vsi->type != I40E_VSI_MAIN)
4473 return;
4474
4475 netdev = vsi->netdev;
4476 if (!netdev)
4477 return;
4478
4479 /* Bail out if netif_carrier is not OK */
4480 if (!netif_carrier_ok(netdev))
4481 return;
4482
4483 /* Go thru' TX queues for netdev */
4484 for (i = 0; i < netdev->num_tx_queues; i++) {
4485 struct netdev_queue *q;
4486
4487 q = netdev_get_tx_queue(netdev, i);
4488 if (q)
4489 i40e_detect_recover_hung_queue(i, vsi);
4490 }
4491}
4492
63d7e5a4
NP		 4493/**
4494 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4495 * @pf: pointer to PF
63d7e5a4
NP		 4496 *
4497 * Get TC map for ISCSI PF type that will include iSCSI TC
4498 * and LAN TC.
4499 **/
4500static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4501{
4502 struct i40e_dcb_app_priority_table app;
4503 struct i40e_hw *hw = &pf->hw;
4504 u8 enabled_tc = 1; /* TC0 is always enabled */
4505 u8 tc, i;
4506 /* Get the iSCSI APP TLV */
4507 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4508
4509 for (i = 0; i < dcbcfg->numapps; i++) {
4510 app = dcbcfg->app[i];
4511 if (app.selector == I40E_APP_SEL_TCPIP &&
4512 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4513 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4514 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4515 break;
4516 }
4517 }
4518
4519 return enabled_tc;
4520}
4521
41c445ff
JB		 4522/**
4523 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4524 * @dcbcfg: the corresponding DCBx configuration structure
4525 *
4526 * Return the number of TCs from given DCBx configuration
4527 **/
4528static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4529{
078b5876
JB		 4530 u8 num_tc = 0;
4531 int i;
41c445ff
JB		 4532
4533 /* Scan the ETS Config Priority Table to find
4534 * traffic class enabled for a given priority
4535 * and use the traffic class index to get the
4536 * number of traffic classes enabled
4537 */
4538 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4539 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4540 num_tc = dcbcfg->etscfg.prioritytable[i];
4541 }
4542
4543 /* Traffic class index starts from zero so
4544 * increment to return the actual count
4545 */
078b5876 4546 return num_tc + 1;
41c445ff
JB		 4547}
4548
4549/**
4550 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4551 * @dcbcfg: the corresponding DCBx configuration structure
4552 *
4553 * Query the current DCB configuration and return the number of
4554 * traffic classes enabled from the given DCBX config
4555 **/
4556static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4557{
4558 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4559 u8 enabled_tc = 1;
4560 u8 i;
4561
4562 for (i = 0; i < num_tc; i++)
41a1d04b 4563 enabled_tc |= BIT(i);
41c445ff
JB		 4564
4565 return enabled_tc;
4566}
4567
4568/**
4569 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4570 * @pf: PF being queried
4571 *
4572 * Return number of traffic classes enabled for the given PF
4573 **/
4574static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4575{
4576 struct i40e_hw *hw = &pf->hw;
4577 u8 i, enabled_tc;
4578 u8 num_tc = 0;
4579 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4580
4581 /* If DCB is not enabled then always in single TC */
4582 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4583 return 1;
4584
63d7e5a4
NP		 4585 /* SFP mode will be enabled for all TCs on port */
4586 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4587 return i40e_dcb_get_num_tc(dcbcfg);
4588
41c445ff 4589 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4590 if (pf->hw.func_caps.iscsi)
4591 enabled_tc = i40e_get_iscsi_tc_map(pf);
4592 else
fc51de96 4593 return 1; /* Only TC0 */
41c445ff 4594
63d7e5a4
NP		 4595 /* At least have TC0 */
4596 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4597 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4598 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4599 num_tc++;
4600 }
4601 return num_tc;
41c445ff
JB		 4602}
4603
4604/**
4605 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4606 * @pf: PF being queried
4607 *
4608 * Return a bitmap for first enabled traffic class for this PF.
4609 **/
4610static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4611{
4612 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4613 u8 i = 0;
4614
4615 if (!enabled_tc)
4616 return 0x1; /* TC0 */
4617
4618 /* Find the first enabled TC */
4619 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4620 if (enabled_tc & BIT(i))
41c445ff
JB		 4621 break;
4622 }
4623
41a1d04b 4624 return BIT(i);
41c445ff
JB		 4625}
4626
4627/**
4628 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4629 * @pf: PF being queried
4630 *
4631 * Return a bitmap for enabled traffic classes for this PF.
4632 **/
4633static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4634{
4635 /* If DCB is not enabled for this PF then just return default TC */
4636 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4637 return i40e_pf_get_default_tc(pf);
4638
41c445ff 4639 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4640 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4641 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4642
fc51de96 4643 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4644 if (pf->hw.func_caps.iscsi)
4645 return i40e_get_iscsi_tc_map(pf);
4646 else
fc51de96 4647 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4648}
4649
4650/**
4651 * i40e_vsi_get_bw_info - Query VSI BW Information
4652 * @vsi: the VSI being queried
4653 *
4654 * Returns 0 on success, negative value on failure
4655 **/
4656static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4657{
4658 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4659 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4660 struct i40e_pf *pf = vsi->back;
4661 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4662 i40e_status ret;
41c445ff 4663 u32 tc_bw_max;
41c445ff
JB		 4664 int i;
4665
4666 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4667 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4668 if (ret) {
41c445ff 4669 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4670 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4671 i40e_stat_str(&pf->hw, ret),
4672 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4673 return -EINVAL;
41c445ff
JB		 4674 }
4675
4676 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4677 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4678 NULL);
4679 if (ret) {
41c445ff 4680 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4681 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4682 i40e_stat_str(&pf->hw, ret),
4683 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4684 return -EINVAL;
41c445ff
JB		 4685 }
4686
4687 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4688 dev_info(&pf->pdev->dev,
4689 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4690 bw_config.tc_valid_bits,
4691 bw_ets_config.tc_valid_bits);
4692 /* Still continuing */
4693 }
4694
4695 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4696 vsi->bw_max_quanta = bw_config.max_bw;
4697 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4698 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4699 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4700 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4701 vsi->bw_ets_limit_credits[i] =
4702 le16_to_cpu(bw_ets_config.credits[i]);
4703 /* 3 bits out of 4 for each TC */
4704 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4705 }
078b5876 4706
dcae29be 4707 return 0;
41c445ff
JB		 4708}
4709
4710/**
4711 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4712 * @vsi: the VSI being configured
4713 * @enabled_tc: TC bitmap
4714 * @bw_credits: BW shared credits per TC
4715 *
4716 * Returns 0 on success, negative value on failure
4717 **/
dcae29be 4718static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4719 u8 *bw_share)
4720{
4721 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4722 i40e_status ret;
dcae29be 4723 int i;
41c445ff
JB		 4724
4725 bw_data.tc_valid_bits = enabled_tc;
4726 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4727 bw_data.tc_bw_credits[i] = bw_share[i];
4728
f1c7e72e
SN		 4729 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4730 NULL);
4731 if (ret) {
41c445ff 4732 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4733 "AQ command Config VSI BW allocation per TC failed = %d\n",
4734 vsi->back->hw.aq.asq_last_status);
dcae29be 4735 return -EINVAL;
41c445ff
JB		 4736 }
4737
4738 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4739 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4740
dcae29be 4741 return 0;
41c445ff
JB		 4742}
4743
4744/**
4745 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4746 * @vsi: the VSI being configured
4747 * @enabled_tc: TC map to be enabled
4748 *
4749 **/
4750static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4751{
4752 struct net_device *netdev = vsi->netdev;
4753 struct i40e_pf *pf = vsi->back;
4754 struct i40e_hw *hw = &pf->hw;
4755 u8 netdev_tc = 0;
4756 int i;
4757 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4758
4759 if (!netdev)
4760 return;
4761
4762 if (!enabled_tc) {
4763 netdev_reset_tc(netdev);
4764 return;
4765 }
4766
4767 /* Set up actual enabled TCs on the VSI */
4768 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4769 return;
4770
4771 /* set per TC queues for the VSI */
4772 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4773 /* Only set TC queues for enabled tcs
4774 *
4775 * e.g. For a VSI that has TC0 and TC3 enabled the
4776 * enabled_tc bitmap would be 0x00001001; the driver
4777 * will set the numtc for netdev as 2 that will be
4778 * referenced by the netdev layer as TC 0 and 1.
4779 */
75f5cea9 4780 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4781 netdev_set_tc_queue(netdev,
4782 vsi->tc_config.tc_info[i].netdev_tc,
4783 vsi->tc_config.tc_info[i].qcount,
4784 vsi->tc_config.tc_info[i].qoffset);
4785 }
4786
4787 /* Assign UP2TC map for the VSI */
4788 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4789 /* Get the actual TC# for the UP */
4790 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4791 /* Get the mapped netdev TC# for the UP */
4792 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4793 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4794 }
4795}
4796
4797/**
4798 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4799 * @vsi: the VSI being configured
4800 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4801 **/
4802static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4803 struct i40e_vsi_context *ctxt)
4804{
4805 /* copy just the sections touched not the entire info
4806 * since not all sections are valid as returned by
4807 * update vsi params
4808 */
4809 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4810 memcpy(&vsi->info.queue_mapping,
4811 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4812 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4813 sizeof(vsi->info.tc_mapping));
4814}
4815
4816/**
4817 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4818 * @vsi: VSI to be configured
4819 * @enabled_tc: TC bitmap
4820 *
4821 * This configures a particular VSI for TCs that are mapped to the
4822 * given TC bitmap. It uses default bandwidth share for TCs across
4823 * VSIs to configure TC for a particular VSI.
4824 *
4825 * NOTE:
4826 * It is expected that the VSI queues have been quisced before calling
4827 * this function.
4828 **/
4829static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4830{
4831 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4832 struct i40e_vsi_context ctxt;
4833 int ret = 0;
4834 int i;
4835
4836 /* Check if enabled_tc is same as existing or new TCs */
4837 if (vsi->tc_config.enabled_tc == enabled_tc)
4838 return ret;
4839
4840 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4841 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4842 if (enabled_tc & BIT(i))
41c445ff
JB		 4843 bw_share[i] = 1;
4844 }
4845
4846 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4847 if (ret) {
4848 dev_info(&vsi->back->pdev->dev,
4849 "Failed configuring TC map %d for VSI %d\n",
4850 enabled_tc, vsi->seid);
4851 goto out;
4852 }
4853
4854 /* Update Queue Pairs Mapping for currently enabled UPs */
4855 ctxt.seid = vsi->seid;
4856 ctxt.pf_num = vsi->back->hw.pf_id;
4857 ctxt.vf_num = 0;
4858 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4859 ctxt.info = vsi->info;
41c445ff
JB		 4860 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4861
e3219ce6
ASJ		 4862 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
4863 ctxt.info.valid_sections |=
4864 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
4865 ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
4866 }
4867
41c445ff
JB		 4868 /* Update the VSI after updating the VSI queue-mapping information */
4869 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4870 if (ret) {
4871 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4872 "Update vsi tc config failed, err %s aq_err %s\n",
4873 i40e_stat_str(&vsi->back->hw, ret),
4874 i40e_aq_str(&vsi->back->hw,
4875 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4876 goto out;
4877 }
4878 /* update the local VSI info with updated queue map */
4879 i40e_vsi_update_queue_map(vsi, &ctxt);
4880 vsi->info.valid_sections = 0;
4881
4882 /* Update current VSI BW information */
4883 ret = i40e_vsi_get_bw_info(vsi);
4884 if (ret) {
4885 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4886 "Failed updating vsi bw info, err %s aq_err %s\n",
4887 i40e_stat_str(&vsi->back->hw, ret),
4888 i40e_aq_str(&vsi->back->hw,
4889 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4890 goto out;
4891 }
4892
4893 /* Update the netdev TC setup */
4894 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4895out:
4896 return ret;
4897}
4898
4e3b35b0
NP		 4899/**
4900 * i40e_veb_config_tc - Configure TCs for given VEB
4901 * @veb: given VEB
4902 * @enabled_tc: TC bitmap
4903 *
4904 * Configures given TC bitmap for VEB (switching) element
4905 **/
4906int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4907{
4908 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4909 struct i40e_pf *pf = veb->pf;
4910 int ret = 0;
4911 int i;
4912
4913 /* No TCs or already enabled TCs just return */
4914 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4915 return ret;
4916
4917 bw_data.tc_valid_bits = enabled_tc;
4918 /* bw_data.absolute_credits is not set (relative) */
4919
4920 /* Enable ETS TCs with equal BW Share for now */
4921 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4922 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4923 bw_data.tc_bw_share_credits[i] = 1;
4924 }
4925
4926 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4927 &bw_data, NULL);
4928 if (ret) {
4929 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4930 "VEB bw config failed, err %s aq_err %s\n",
4931 i40e_stat_str(&pf->hw, ret),
4932 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4933 goto out;
4934 }
4935
4936 /* Update the BW information */
4937 ret = i40e_veb_get_bw_info(veb);
4938 if (ret) {
4939 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4940 "Failed getting veb bw config, err %s aq_err %s\n",
4941 i40e_stat_str(&pf->hw, ret),
4942 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4943 }
4944
4945out:
4946 return ret;
4947}
4948
4949#ifdef CONFIG_I40E_DCB
4950/**
4951 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4952 * @pf: PF struct
4953 *
4954 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4955 * the caller would've quiesce all the VSIs before calling
4956 * this function
4957 **/
4958static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4959{
4960 u8 tc_map = 0;
4961 int ret;
4962 u8 v;
4963
4964 /* Enable the TCs available on PF to all VEBs */
4965 tc_map = i40e_pf_get_tc_map(pf);
4966 for (v = 0; v < I40E_MAX_VEB; v++) {
4967 if (!pf->veb[v])
4968 continue;
4969 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4970 if (ret) {
4971 dev_info(&pf->pdev->dev,
4972 "Failed configuring TC for VEB seid=%d\n",
4973 pf->veb[v]->seid);
4974 /* Will try to configure as many components */
4975 }
4976 }
4977
4978 /* Update each VSI */
505682cd 4979 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4980 if (!pf->vsi[v])
4981 continue;
4982
4983 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4984#ifdef I40E_FCOE
4985 * - For FCoE VSI only enable the TC configured
4986 * as per the APP TLV
4987#endif
4e3b35b0
NP		 4988 * - For all others keep them at TC0 for now
4989 */
4990 if (v == pf->lan_vsi)
4991 tc_map = i40e_pf_get_tc_map(pf);
4992 else
4993 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4994#ifdef I40E_FCOE
4995 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4996 tc_map = i40e_get_fcoe_tc_map(pf);
4997#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4998
4999 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
5000 if (ret) {
5001 dev_info(&pf->pdev->dev,
5002 "Failed configuring TC for VSI seid=%d\n",
5003 pf->vsi[v]->seid);
5004 /* Will try to configure as many components */
5005 } else {
0672a091
NP		 5006 /* Re-configure VSI vectors based on updated TC map */
5007 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 5008 if (pf->vsi[v]->netdev)
5009 i40e_dcbnl_set_all(pf->vsi[v]);
5010 }
e3219ce6 5011 i40e_notify_client_of_l2_param_changes(pf->vsi[v]);
4e3b35b0
NP		 5012 }
5013}
5014
2fd75f31
NP		 5015/**
5016 * i40e_resume_port_tx - Resume port Tx
5017 * @pf: PF struct
5018 *
5019 * Resume a port's Tx and issue a PF reset in case of failure to
5020 * resume.
5021 **/
5022static int i40e_resume_port_tx(struct i40e_pf *pf)
5023{
5024 struct i40e_hw *hw = &pf->hw;
5025 int ret;
5026
5027 ret = i40e_aq_resume_port_tx(hw, NULL);
5028 if (ret) {
5029 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5030 "Resume Port Tx failed, err %s aq_err %s\n",
5031 i40e_stat_str(&pf->hw, ret),
5032 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 5033 /* Schedule PF reset to recover */
5034 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5035 i40e_service_event_schedule(pf);
5036 }
5037
5038 return ret;
5039}
5040
4e3b35b0
NP		 5041/**
5042 * i40e_init_pf_dcb - Initialize DCB configuration
5043 * @pf: PF being configured
5044 *
5045 * Query the current DCB configuration and cache it
5046 * in the hardware structure
5047 **/
5048static int i40e_init_pf_dcb(struct i40e_pf *pf)
5049{
5050 struct i40e_hw *hw = &pf->hw;
5051 int err = 0;
5052
025b4a54 5053 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
f1bbad33 5054 if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT)
025b4a54
ASJ		 5055 goto out;
5056
4e3b35b0
NP		 5057 /* Get the initial DCB configuration */
5058 err = i40e_init_dcb(hw);
5059 if (!err) {
5060 /* Device/Function is not DCBX capable */
5061 if ((!hw->func_caps.dcb) ||
5062 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5063 dev_info(&pf->pdev->dev,
5064 "DCBX offload is not supported or is disabled for this PF.\n");
5065
5066 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5067 goto out;
5068
5069 } else {
5070 /* When status is not DISABLED then DCBX in FW */
5071 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5072 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5073
5074 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5075 /* Enable DCB tagging only when more than one TC */
5076 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5077 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5078 dev_dbg(&pf->pdev->dev,
5079 "DCBX offload is supported for this PF.\n");
4e3b35b0 5080 }
014269ff 5081 } else {
aebfc816 5082 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5083 "Query for DCB configuration failed, err %s aq_err %s\n",
5084 i40e_stat_str(&pf->hw, err),
5085 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5086 }
5087
5088out:
5089 return err;
5090}
5091#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5092#define SPEED_SIZE 14
5093#define FC_SIZE 8
5094/**
5095 * i40e_print_link_message - print link up or down
5096 * @vsi: the VSI for which link needs a message
5097 */
c156f856 5098void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5099{
a9165490
SN		 5100 char *speed = "Unknown";
5101 char *fc = "Unknown";
cf05ed08 5102
c156f856
MJ		 5103 if (vsi->current_isup == isup)
5104 return;
5105 vsi->current_isup = isup;
cf05ed08
JB		 5106 if (!isup) {
5107 netdev_info(vsi->netdev, "NIC Link is Down\n");
5108 return;
5109 }
5110
148c2d80
GR		 5111 /* Warn user if link speed on NPAR enabled partition is not at
5112 * least 10GB
5113 */
5114 if (vsi->back->hw.func_caps.npar_enable &&
5115 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5116 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5117 netdev_warn(vsi->netdev,
5118 "The partition detected link speed that is less than 10Gbps\n");
5119
cf05ed08
JB		 5120 switch (vsi->back->hw.phy.link_info.link_speed) {
5121 case I40E_LINK_SPEED_40GB:
a9165490 5122 speed = "40 G";
cf05ed08 5123 break;
ae24b409 5124 case I40E_LINK_SPEED_20GB:
a9165490 5125 speed = "20 G";
ae24b409 5126 break;
cf05ed08 5127 case I40E_LINK_SPEED_10GB:
a9165490 5128 speed = "10 G";
cf05ed08
JB		 5129 break;
5130 case I40E_LINK_SPEED_1GB:
a9165490 5131 speed = "1000 M";
cf05ed08 5132 break;
5960d33f 5133 case I40E_LINK_SPEED_100MB:
a9165490 5134 speed = "100 M";
5960d33f 5135 break;
cf05ed08
JB		 5136 default:
5137 break;
5138 }
5139
5140 switch (vsi->back->hw.fc.current_mode) {
5141 case I40E_FC_FULL:
a9165490 5142 fc = "RX/TX";
cf05ed08
JB		 5143 break;
5144 case I40E_FC_TX_PAUSE:
a9165490 5145 fc = "TX";
cf05ed08
JB		 5146 break;
5147 case I40E_FC_RX_PAUSE:
a9165490 5148 fc = "RX";
cf05ed08
JB		 5149 break;
5150 default:
a9165490 5151 fc = "None";
cf05ed08
JB		 5152 break;
5153 }
5154
a9165490 5155 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5156 speed, fc);
5157}
4e3b35b0 5158
41c445ff
JB		 5159/**
5160 * i40e_up_complete - Finish the last steps of bringing up a connection
5161 * @vsi: the VSI being configured
5162 **/
5163static int i40e_up_complete(struct i40e_vsi *vsi)
5164{
5165 struct i40e_pf *pf = vsi->back;
5166 int err;
5167
5168 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5169 i40e_vsi_configure_msix(vsi);
5170 else
5171 i40e_configure_msi_and_legacy(vsi);
5172
5173 /* start rings */
5174 err = i40e_vsi_control_rings(vsi, true);
5175 if (err)
5176 return err;
5177
5178 clear_bit(__I40E_DOWN, &vsi->state);
5179 i40e_napi_enable_all(vsi);
5180 i40e_vsi_enable_irq(vsi);
5181
5182 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5183 (vsi->netdev)) {
cf05ed08 5184 i40e_print_link_message(vsi, true);
41c445ff
JB		 5185 netif_tx_start_all_queues(vsi->netdev);
5186 netif_carrier_on(vsi->netdev);
6d779b41 5187 } else if (vsi->netdev) {
cf05ed08 5188 i40e_print_link_message(vsi, false);
7b592f61
CW		 5189 /* need to check for qualified module here*/
5190 if ((pf->hw.phy.link_info.link_info &
5191 I40E_AQ_MEDIA_AVAILABLE) &&
5192 (!(pf->hw.phy.link_info.an_info &
5193 I40E_AQ_QUALIFIED_MODULE)))
5194 netdev_err(vsi->netdev,
5195 "the driver failed to link because an unqualified module was detected.");
41c445ff 5196 }
ca64fa4e
ASJ		 5197
5198 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5199 if (vsi->type == I40E_VSI_FDIR) {
5200 /* reset fd counters */
5201 pf->fd_add_err = pf->fd_atr_cnt = 0;
5202 if (pf->fd_tcp_rule > 0) {
5203 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5204 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5205 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5206 pf->fd_tcp_rule = 0;
5207 }
ca64fa4e 5208 i40e_fdir_filter_restore(vsi);
1e1be8f6 5209 }
e3219ce6
ASJ		 5210
5211 /* On the next run of the service_task, notify any clients of the new
5212 * opened netdev
5213 */
5214 pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED;
41c445ff
JB		 5215 i40e_service_event_schedule(pf);
5216
5217 return 0;
5218}
5219
5220/**
5221 * i40e_vsi_reinit_locked - Reset the VSI
5222 * @vsi: the VSI being configured
5223 *
5224 * Rebuild the ring structs after some configuration
5225 * has changed, e.g. MTU size.
5226 **/
5227static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5228{
5229 struct i40e_pf *pf = vsi->back;
5230
5231 WARN_ON(in_interrupt());
5232 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5233 usleep_range(1000, 2000);
5234 i40e_down(vsi);
5235
5236 /* Give a VF some time to respond to the reset. The
5237 * two second wait is based upon the watchdog cycle in
5238 * the VF driver.
5239 */
5240 if (vsi->type == I40E_VSI_SRIOV)
5241 msleep(2000);
5242 i40e_up(vsi);
5243 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5244}
5245
5246/**
5247 * i40e_up - Bring the connection back up after being down
5248 * @vsi: the VSI being configured
5249 **/
5250int i40e_up(struct i40e_vsi *vsi)
5251{
5252 int err;
5253
5254 err = i40e_vsi_configure(vsi);
5255 if (!err)
5256 err = i40e_up_complete(vsi);
5257
5258 return err;
5259}
5260
5261/**
5262 * i40e_down - Shutdown the connection processing
5263 * @vsi: the VSI being stopped
5264 **/
5265void i40e_down(struct i40e_vsi *vsi)
5266{
5267 int i;
5268
5269 /* It is assumed that the caller of this function
5270 * sets the vsi->state __I40E_DOWN bit.
5271 */
5272 if (vsi->netdev) {
5273 netif_carrier_off(vsi->netdev);
5274 netif_tx_disable(vsi->netdev);
5275 }
5276 i40e_vsi_disable_irq(vsi);
5277 i40e_vsi_control_rings(vsi, false);
5278 i40e_napi_disable_all(vsi);
5279
5280 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5281 i40e_clean_tx_ring(vsi->tx_rings[i]);
5282 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5283 }
5284}
5285
5286/**
5287 * i40e_setup_tc - configure multiple traffic classes
5288 * @netdev: net device to configure
5289 * @tc: number of traffic classes to enable
5290 **/
5291static int i40e_setup_tc(struct net_device *netdev, u8 tc)
5292{
5293 struct i40e_netdev_priv *np = netdev_priv(netdev);
5294 struct i40e_vsi *vsi = np->vsi;
5295 struct i40e_pf *pf = vsi->back;
5296 u8 enabled_tc = 0;
5297 int ret = -EINVAL;
5298 int i;
5299
5300 /* Check if DCB enabled to continue */
5301 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5302 netdev_info(netdev, "DCB is not enabled for adapter\n");
5303 goto exit;
5304 }
5305
5306 /* Check if MFP enabled */
5307 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5308 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5309 goto exit;
5310 }
5311
5312 /* Check whether tc count is within enabled limit */
5313 if (tc > i40e_pf_get_num_tc(pf)) {
5314 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5315 goto exit;
5316 }
5317
5318 /* Generate TC map for number of tc requested */
5319 for (i = 0; i < tc; i++)
75f5cea9 5320 enabled_tc |= BIT(i);
41c445ff
JB		 5321
5322 /* Requesting same TC configuration as already enabled */
5323 if (enabled_tc == vsi->tc_config.enabled_tc)
5324 return 0;
5325
5326 /* Quiesce VSI queues */
5327 i40e_quiesce_vsi(vsi);
5328
5329 /* Configure VSI for enabled TCs */
5330 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5331 if (ret) {
5332 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5333 vsi->seid);
5334 goto exit;
5335 }
5336
5337 /* Unquiesce VSI */
5338 i40e_unquiesce_vsi(vsi);
5339
5340exit:
5341 return ret;
5342}
5343
e4c6734e 5344#ifdef I40E_FCOE
16e5cc64
JF		 5345int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5346 struct tc_to_netdev *tc)
e4c6734e 5347#else
16e5cc64
JF		 5348static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5349 struct tc_to_netdev *tc)
e4c6734e
JF		 5350#endif
5351{
16e5cc64 5352 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
e4c6734e 5353 return -EINVAL;
16e5cc64 5354 return i40e_setup_tc(netdev, tc->tc);
e4c6734e
JF		 5355}
5356
41c445ff
JB		 5357/**
5358 * i40e_open - Called when a network interface is made active
5359 * @netdev: network interface device structure
5360 *
5361 * The open entry point is called when a network interface is made
5362 * active by the system (IFF_UP). At this point all resources needed
5363 * for transmit and receive operations are allocated, the interrupt
5364 * handler is registered with the OS, the netdev watchdog subtask is
5365 * enabled, and the stack is notified that the interface is ready.
5366 *
5367 * Returns 0 on success, negative value on failure
5368 **/
38e00438 5369int i40e_open(struct net_device *netdev)
41c445ff
JB		 5370{
5371 struct i40e_netdev_priv *np = netdev_priv(netdev);
5372 struct i40e_vsi *vsi = np->vsi;
5373 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5374 int err;
5375
4eb3f768
SN		 5376 /* disallow open during test or if eeprom is broken */
5377 if (test_bit(__I40E_TESTING, &pf->state) ||
5378 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5379 return -EBUSY;
5380
5381 netif_carrier_off(netdev);
5382
6c167f58
EK		 5383 err = i40e_vsi_open(vsi);
5384 if (err)
5385 return err;
5386
059dab69
JB		 5387 /* configure global TSO hardware offload settings */
5388 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5389 TCP_FLAG_FIN) >> 16);
5390 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5391 TCP_FLAG_FIN |
5392 TCP_FLAG_CWR) >> 16);
5393 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5394
6633d381 5395#ifdef CONFIG_I40E_VXLAN
6c167f58
EK		 5396 vxlan_get_rx_port(netdev);
5397#endif
cd866606 5398#ifdef CONFIG_I40E_GENEVE
a340c789
AS		 5399 if (pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE)
5400 geneve_get_rx_port(netdev);
cd866606 5401#endif
6c167f58 5402
e3219ce6
ASJ		 5403 i40e_notify_client_of_netdev_open(vsi);
5404
6c167f58
EK		 5405 return 0;
5406}
5407
5408/**
5409 * i40e_vsi_open -
5410 * @vsi: the VSI to open
5411 *
5412 * Finish initialization of the VSI.
5413 *
5414 * Returns 0 on success, negative value on failure
5415 **/
5416int i40e_vsi_open(struct i40e_vsi *vsi)
5417{
5418 struct i40e_pf *pf = vsi->back;
b294ac70 5419 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5420 int err;
5421
41c445ff
JB		 5422 /* allocate descriptors */
5423 err = i40e_vsi_setup_tx_resources(vsi);
5424 if (err)
5425 goto err_setup_tx;
5426 err = i40e_vsi_setup_rx_resources(vsi);
5427 if (err)
5428 goto err_setup_rx;
5429
5430 err = i40e_vsi_configure(vsi);
5431 if (err)
5432 goto err_setup_rx;
5433
c22e3c6c
SN		 5434 if (vsi->netdev) {
5435 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5436 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5437 err = i40e_vsi_request_irq(vsi, int_name);
5438 if (err)
5439 goto err_setup_rx;
41c445ff 5440
c22e3c6c
SN		 5441 /* Notify the stack of the actual queue counts. */
5442 err = netif_set_real_num_tx_queues(vsi->netdev,
5443 vsi->num_queue_pairs);
5444 if (err)
5445 goto err_set_queues;
25946ddb 5446
c22e3c6c
SN		 5447 err = netif_set_real_num_rx_queues(vsi->netdev,
5448 vsi->num_queue_pairs);
5449 if (err)
5450 goto err_set_queues;
8a9eb7d3
SN		 5451
5452 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5453 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5454 dev_driver_string(&pf->pdev->dev),
5455 dev_name(&pf->pdev->dev));
8a9eb7d3 5456 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5457
c22e3c6c 5458 } else {
ce9ccb17 5459 err = -EINVAL;
6c167f58
EK		 5460 goto err_setup_rx;
5461 }
25946ddb 5462
41c445ff
JB		 5463 err = i40e_up_complete(vsi);
5464 if (err)
5465 goto err_up_complete;
5466
41c445ff
JB		 5467 return 0;
5468
5469err_up_complete:
5470 i40e_down(vsi);
25946ddb 5471err_set_queues:
41c445ff
JB		 5472 i40e_vsi_free_irq(vsi);
5473err_setup_rx:
5474 i40e_vsi_free_rx_resources(vsi);
5475err_setup_tx:
5476 i40e_vsi_free_tx_resources(vsi);
5477 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5478 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5479
5480 return err;
5481}
5482
17a73f6b
JG		 5483/**
5484 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5485 * @pf: Pointer to PF
17a73f6b
JG		 5486 *
5487 * This function destroys the hlist where all the Flow Director
5488 * filters were saved.
5489 **/
5490static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5491{
5492 struct i40e_fdir_filter *filter;
5493 struct hlist_node *node2;
5494
5495 hlist_for_each_entry_safe(filter, node2,
5496 &pf->fdir_filter_list, fdir_node) {
5497 hlist_del(&filter->fdir_node);
5498 kfree(filter);
5499 }
5500 pf->fdir_pf_active_filters = 0;
5501}
5502
41c445ff
JB		 5503/**
5504 * i40e_close - Disables a network interface
5505 * @netdev: network interface device structure
5506 *
5507 * The close entry point is called when an interface is de-activated
5508 * by the OS. The hardware is still under the driver's control, but
5509 * this netdev interface is disabled.
5510 *
5511 * Returns 0, this is not allowed to fail
5512 **/
38e00438 5513int i40e_close(struct net_device *netdev)
41c445ff
JB		 5514{
5515 struct i40e_netdev_priv *np = netdev_priv(netdev);
5516 struct i40e_vsi *vsi = np->vsi;
5517
90ef8d47 5518 i40e_vsi_close(vsi);
41c445ff
JB		 5519
5520 return 0;
5521}
5522
5523/**
5524 * i40e_do_reset - Start a PF or Core Reset sequence
5525 * @pf: board private structure
5526 * @reset_flags: which reset is requested
5527 *
5528 * The essential difference in resets is that the PF Reset
5529 * doesn't clear the packet buffers, doesn't reset the PE
5530 * firmware, and doesn't bother the other PFs on the chip.
5531 **/
5532void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5533{
5534 u32 val;
5535
5536 WARN_ON(in_interrupt());
5537
263fc48f 5538
41c445ff 5539 /* do the biggest reset indicated */
41a1d04b 5540 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5541
5542 /* Request a Global Reset
5543 *
5544 * This will start the chip's countdown to the actual full
5545 * chip reset event, and a warning interrupt to be sent
5546 * to all PFs, including the requestor. Our handler
5547 * for the warning interrupt will deal with the shutdown
5548 * and recovery of the switch setup.
5549 */
69bfb110 5550 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5551 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5552 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5553 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5554
41a1d04b 5555 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5556
5557 /* Request a Core Reset
5558 *
5559 * Same as Global Reset, except does *not* include the MAC/PHY
5560 */
69bfb110 5561 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5562 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5563 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5564 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5565 i40e_flush(&pf->hw);
5566
41a1d04b 5567 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5568
5569 /* Request a PF Reset
5570 *
5571 * Resets only the PF-specific registers
5572 *
5573 * This goes directly to the tear-down and rebuild of
5574 * the switch, since we need to do all the recovery as
5575 * for the Core Reset.
5576 */
69bfb110 5577 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5578 i40e_handle_reset_warning(pf);
5579
41a1d04b 5580 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5581 int v;
5582
5583 /* Find the VSI(s) that requested a re-init */
5584 dev_info(&pf->pdev->dev,
5585 "VSI reinit requested\n");
505682cd 5586 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5587 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5588
41c445ff
JB		 5589 if (vsi != NULL &&
5590 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5591 i40e_vsi_reinit_locked(pf->vsi[v]);
5592 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5593 }
5594 }
41a1d04b 5595 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5596 int v;
5597
5598 /* Find the VSI(s) that needs to be brought down */
5599 dev_info(&pf->pdev->dev, "VSI down requested\n");
5600 for (v = 0; v < pf->num_alloc_vsi; v++) {
5601 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5602
b5d06f05
NP		 5603 if (vsi != NULL &&
5604 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5605 set_bit(__I40E_DOWN, &vsi->state);
5606 i40e_down(vsi);
5607 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5608 }
5609 }
41c445ff
JB		 5610 } else {
5611 dev_info(&pf->pdev->dev,
5612 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5613 }
5614}
5615
4e3b35b0
NP		 5616#ifdef CONFIG_I40E_DCB
5617/**
5618 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5619 * @pf: board private structure
5620 * @old_cfg: current DCB config
5621 * @new_cfg: new DCB config
5622 **/
5623bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5624 struct i40e_dcbx_config *old_cfg,
5625 struct i40e_dcbx_config *new_cfg)
5626{
5627 bool need_reconfig = false;
5628
5629 /* Check if ETS configuration has changed */
5630 if (memcmp(&new_cfg->etscfg,
5631 &old_cfg->etscfg,
5632 sizeof(new_cfg->etscfg))) {
5633 /* If Priority Table has changed reconfig is needed */
5634 if (memcmp(&new_cfg->etscfg.prioritytable,
5635 &old_cfg->etscfg.prioritytable,
5636 sizeof(new_cfg->etscfg.prioritytable))) {
5637 need_reconfig = true;
69bfb110 5638 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5639 }
5640
5641 if (memcmp(&new_cfg->etscfg.tcbwtable,
5642 &old_cfg->etscfg.tcbwtable,
5643 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5644 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5645
5646 if (memcmp(&new_cfg->etscfg.tsatable,
5647 &old_cfg->etscfg.tsatable,
5648 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5649 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5650 }
5651
5652 /* Check if PFC configuration has changed */
5653 if (memcmp(&new_cfg->pfc,
5654 &old_cfg->pfc,
5655 sizeof(new_cfg->pfc))) {
5656 need_reconfig = true;
69bfb110 5657 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5658 }
5659
5660 /* Check if APP Table has changed */
5661 if (memcmp(&new_cfg->app,
5662 &old_cfg->app,
3d9667a9 5663 sizeof(new_cfg->app))) {
4e3b35b0 5664 need_reconfig = true;
69bfb110 5665 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5666 }
4e3b35b0 5667
fb43201f 5668 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5669 return need_reconfig;
5670}
5671
5672/**
5673 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5674 * @pf: board private structure
5675 * @e: event info posted on ARQ
5676 **/
5677static int i40e_handle_lldp_event(struct i40e_pf *pf,
5678 struct i40e_arq_event_info *e)
5679{
5680 struct i40e_aqc_lldp_get_mib *mib =
5681 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5682 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5683 struct i40e_dcbx_config tmp_dcbx_cfg;
5684 bool need_reconfig = false;
5685 int ret = 0;
5686 u8 type;
5687
4d9b6043
NP		 5688 /* Not DCB capable or capability disabled */
5689 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5690 return ret;
5691
4e3b35b0
NP		 5692 /* Ignore if event is not for Nearest Bridge */
5693 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5694 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5695 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5696 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5697 return ret;
5698
5699 /* Check MIB Type and return if event for Remote MIB update */
5700 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5701 dev_dbg(&pf->pdev->dev,
fb43201f 5702 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5703 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5704 /* Update the remote cached instance and return */
5705 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5706 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5707 &hw->remote_dcbx_config);
5708 goto exit;
5709 }
5710
9fa61dd2 5711 /* Store the old configuration */
1a2f6248 5712 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5713
750fcbcf
NP		 5714 /* Reset the old DCBx configuration data */
5715 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5716 /* Get updated DCBX data from firmware */
5717 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5718 if (ret) {
f1c7e72e
SN		 5719 dev_info(&pf->pdev->dev,
5720 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5721 i40e_stat_str(&pf->hw, ret),
5722 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5723 goto exit;
5724 }
5725
5726 /* No change detected in DCBX configs */
750fcbcf
NP		 5727 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5728 sizeof(tmp_dcbx_cfg))) {
69bfb110 5729 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5730 goto exit;
5731 }
5732
750fcbcf
NP		 5733 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5734 &hw->local_dcbx_config);
4e3b35b0 5735
750fcbcf 5736 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5737
5738 if (!need_reconfig)
5739 goto exit;
5740
4d9b6043 5741 /* Enable DCB tagging only when more than one TC */
750fcbcf 5742 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5743 pf->flags |= I40E_FLAG_DCB_ENABLED;
5744 else
5745 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5746
69129dc3 5747 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5748 /* Reconfiguration needed quiesce all VSIs */
5749 i40e_pf_quiesce_all_vsi(pf);
5750
5751 /* Changes in configuration update VEB/VSI */
5752 i40e_dcb_reconfigure(pf);
5753
2fd75f31
NP		 5754 ret = i40e_resume_port_tx(pf);
5755
69129dc3 5756 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5757 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5758 if (ret)
5759 goto exit;
5760
3fe06f41
NP		 5761 /* Wait for the PF's queues to be disabled */
5762 ret = i40e_pf_wait_queues_disabled(pf);
11e47708
PN		 5763 if (ret) {
5764 /* Schedule PF reset to recover */
5765 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5766 i40e_service_event_schedule(pf);
5767 } else {
2fd75f31 5768 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5769 }
5770
4e3b35b0
NP		 5771exit:
5772 return ret;
5773}
5774#endif /* CONFIG_I40E_DCB */
5775
23326186
ASJ		 5776/**
5777 * i40e_do_reset_safe - Protected reset path for userland calls.
5778 * @pf: board private structure
5779 * @reset_flags: which reset is requested
5780 *
5781 **/
5782void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5783{
5784 rtnl_lock();
5785 i40e_do_reset(pf, reset_flags);
5786 rtnl_unlock();
5787}
5788
41c445ff
JB		 5789/**
5790 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5791 * @pf: board private structure
5792 * @e: event info posted on ARQ
5793 *
5794 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5795 * and VF queues
5796 **/
5797static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5798 struct i40e_arq_event_info *e)
5799{
5800 struct i40e_aqc_lan_overflow *data =
5801 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5802 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5803 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5804 struct i40e_hw *hw = &pf->hw;
5805 struct i40e_vf *vf;
5806 u16 vf_id;
5807
69bfb110
JB		 5808 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5809 queue, qtx_ctl);
41c445ff
JB		 5810
5811 /* Queue belongs to VF, find the VF and issue VF reset */
5812 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5813 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5814 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5815 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5816 vf_id -= hw->func_caps.vf_base_id;
5817 vf = &pf->vf[vf_id];
5818 i40e_vc_notify_vf_reset(vf);
5819 /* Allow VF to process pending reset notification */
5820 msleep(20);
5821 i40e_reset_vf(vf, false);
5822 }
5823}
5824
5825/**
5826 * i40e_service_event_complete - Finish up the service event
5827 * @pf: board private structure
5828 **/
5829static void i40e_service_event_complete(struct i40e_pf *pf)
5830{
b875f99b 5831 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5832
5833 /* flush memory to make sure state is correct before next watchog */
4e857c58 5834 smp_mb__before_atomic();
41c445ff
JB		 5835 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5836}
5837
55a5e60b 5838/**
12957388
ASJ		 5839 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5840 * @pf: board private structure
5841 **/
04294e38 5842u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5843{
04294e38 5844 u32 val, fcnt_prog;
12957388
ASJ		 5845
5846 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5847 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5848 return fcnt_prog;
5849}
5850
5851/**
04294e38 5852 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5853 * @pf: board private structure
5854 **/
04294e38 5855u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5856{
04294e38
ASJ		 5857 u32 val, fcnt_prog;
5858
55a5e60b
ASJ		 5859 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5860 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5861 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5862 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5863 return fcnt_prog;
5864}
1e1be8f6 5865
04294e38
ASJ		 5866/**
5867 * i40e_get_global_fd_count - Get total FD filters programmed on device
5868 * @pf: board private structure
5869 **/
5870u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5871{
5872 u32 val, fcnt_prog;
5873
5874 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5875 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5876 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5877 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5878 return fcnt_prog;
5879}
5880
55a5e60b
ASJ		 5881/**
5882 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5883 * @pf: board private structure
5884 **/
5885void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5886{
3487b6c3 5887 struct i40e_fdir_filter *filter;
55a5e60b 5888 u32 fcnt_prog, fcnt_avail;
3487b6c3 5889 struct hlist_node *node;
55a5e60b 5890
1e1be8f6
ASJ		 5891 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5892 return;
5893
55a5e60b
ASJ		 5894 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5895 * to re-enable
5896 */
04294e38 5897 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5898 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5899 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5900 (pf->fd_add_err == 0) ||
5901 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5902 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5903 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5904 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5905 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5906 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5907 }
5908 }
5909 /* Wait for some more space to be available to turn on ATR */
5910 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5911 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5912 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5913 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5914 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5915 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5916 }
5917 }
3487b6c3
CW		 5918
5919 /* if hw had a problem adding a filter, delete it */
5920 if (pf->fd_inv > 0) {
5921 hlist_for_each_entry_safe(filter, node,
5922 &pf->fdir_filter_list, fdir_node) {
5923 if (filter->fd_id == pf->fd_inv) {
5924 hlist_del(&filter->fdir_node);
5925 kfree(filter);
5926 pf->fdir_pf_active_filters--;
5927 }
5928 }
5929 }
55a5e60b
ASJ		 5930}
5931
1e1be8f6 5932#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5933#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5934/**
5935 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5936 * @pf: board private structure
5937 **/
5938static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5939{
04294e38 5940 unsigned long min_flush_time;
1e1be8f6 5941 int flush_wait_retry = 50;
04294e38
ASJ		 5942 bool disable_atr = false;
5943 int fd_room;
1e1be8f6
ASJ		 5944 int reg;
5945
1790ed0c
AA		 5946 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5947 return;
5948
a5fdaf34
JB		 5949 if (!time_after(jiffies, pf->fd_flush_timestamp +
5950 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5951 return;
04294e38 5952
a5fdaf34
JB		 5953 /* If the flush is happening too quick and we have mostly SB rules we
5954 * should not re-enable ATR for some time.
5955 */
5956 min_flush_time = pf->fd_flush_timestamp +
5957 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5958 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5959
5960 if (!(time_after(jiffies, min_flush_time)) &&
5961 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5962 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5963 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5964 disable_atr = true;
5965 }
5966
5967 pf->fd_flush_timestamp = jiffies;
5968 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5969 /* flush all filters */
5970 wr32(&pf->hw, I40E_PFQF_CTL_1,
5971 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5972 i40e_flush(&pf->hw);
5973 pf->fd_flush_cnt++;
5974 pf->fd_add_err = 0;
5975 do {
5976 /* Check FD flush status every 5-6msec */
5977 usleep_range(5000, 6000);
5978 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5979 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5980 break;
5981 } while (flush_wait_retry--);
5982 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5983 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5984 } else {
5985 /* replay sideband filters */
5986 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5987 if (!disable_atr)
5988 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5989 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5990 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5991 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5992 }
a5fdaf34 5993
1e1be8f6
ASJ		 5994}
5995
5996/**
5997 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5998 * @pf: board private structure
5999 **/
04294e38 6000u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 6001{
6002 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
6003}
6004
6005/* We can see up to 256 filter programming desc in transit if the filters are
6006 * being applied really fast; before we see the first
6007 * filter miss error on Rx queue 0. Accumulating enough error messages before
6008 * reacting will make sure we don't cause flush too often.
6009 */
6010#define I40E_MAX_FD_PROGRAM_ERROR 256
6011
41c445ff
JB		 6012/**
6013 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
6014 * @pf: board private structure
6015 **/
6016static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
6017{
41c445ff 6018
41c445ff
JB		 6019 /* if interface is down do nothing */
6020 if (test_bit(__I40E_DOWN, &pf->state))
6021 return;
1e1be8f6 6022
1790ed0c
AA		 6023 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
6024 return;
6025
04294e38 6026 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 6027 i40e_fdir_flush_and_replay(pf);
6028
55a5e60b
ASJ		 6029 i40e_fdir_check_and_reenable(pf);
6030
41c445ff
JB		 6031}
6032
6033/**
6034 * i40e_vsi_link_event - notify VSI of a link event
6035 * @vsi: vsi to be notified
6036 * @link_up: link up or down
6037 **/
6038static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
6039{
32b5b811 6040 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 6041 return;
6042
6043 switch (vsi->type) {
6044 case I40E_VSI_MAIN:
38e00438
VD		 6045#ifdef I40E_FCOE
6046 case I40E_VSI_FCOE:
6047#endif
41c445ff
JB		 6048 if (!vsi->netdev || !vsi->netdev_registered)
6049 break;
6050
6051 if (link_up) {
6052 netif_carrier_on(vsi->netdev);
6053 netif_tx_wake_all_queues(vsi->netdev);
6054 } else {
6055 netif_carrier_off(vsi->netdev);
6056 netif_tx_stop_all_queues(vsi->netdev);
6057 }
6058 break;
6059
6060 case I40E_VSI_SRIOV:
41c445ff
JB		 6061 case I40E_VSI_VMDQ2:
6062 case I40E_VSI_CTRL:
e3219ce6 6063 case I40E_VSI_IWARP:
41c445ff
JB		 6064 case I40E_VSI_MIRROR:
6065 default:
6066 /* there is no notification for other VSIs */
6067 break;
6068 }
6069}
6070
6071/**
6072 * i40e_veb_link_event - notify elements on the veb of a link event
6073 * @veb: veb to be notified
6074 * @link_up: link up or down
6075 **/
6076static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6077{
6078 struct i40e_pf *pf;
6079 int i;
6080
6081 if (!veb || !veb->pf)
6082 return;
6083 pf = veb->pf;
6084
6085 /* depth first... */
6086 for (i = 0; i < I40E_MAX_VEB; i++)
6087 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6088 i40e_veb_link_event(pf->veb[i], link_up);
6089
6090 /* ... now the local VSIs */
505682cd 6091 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6092 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6093 i40e_vsi_link_event(pf->vsi[i], link_up);
6094}
6095
6096/**
6097 * i40e_link_event - Update netif_carrier status
6098 * @pf: board private structure
6099 **/
6100static void i40e_link_event(struct i40e_pf *pf)
6101{
320684cd 6102 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6103 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6104 i40e_status status;
6105 bool new_link, old_link;
41c445ff 6106
1f9610e4
CS		 6107 /* save off old link status information */
6108 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6109
1e701e09
JB		 6110 /* set this to force the get_link_status call to refresh state */
6111 pf->hw.phy.get_link_info = true;
6112
41c445ff 6113 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6114
6115 status = i40e_get_link_status(&pf->hw, &new_link);
6116 if (status) {
6117 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6118 status);
6119 return;
6120 }
6121
fef59ddf
CS		 6122 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6123 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6124
1e701e09 6125 if (new_link == old_link &&
fef59ddf 6126 new_link_speed == old_link_speed &&
320684cd
MW		 6127 (test_bit(__I40E_DOWN, &vsi->state) ||
6128 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6129 return;
320684cd
MW		 6130
6131 if (!test_bit(__I40E_DOWN, &vsi->state))
6132 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6133
6134 /* Notify the base of the switch tree connected to
6135 * the link. Floating VEBs are not notified.
6136 */
6137 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6138 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6139 else
320684cd 6140 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6141
6142 if (pf->vf)
6143 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6144
6145 if (pf->flags & I40E_FLAG_PTP)
6146 i40e_ptp_set_increment(pf);
41c445ff
JB		 6147}
6148
41c445ff 6149/**
21536717 6150 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6151 * @pf: board private structure
6152 **/
6153static void i40e_watchdog_subtask(struct i40e_pf *pf)
6154{
6155 int i;
6156
6157 /* if interface is down do nothing */
6158 if (test_bit(__I40E_DOWN, &pf->state) ||
6159 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6160 return;
6161
21536717
SN		 6162 /* make sure we don't do these things too often */
6163 if (time_before(jiffies, (pf->service_timer_previous +
6164 pf->service_timer_period)))
6165 return;
6166 pf->service_timer_previous = jiffies;
6167
9ac77266
SN		 6168 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6169 i40e_link_event(pf);
21536717 6170
41c445ff
JB		 6171 /* Update the stats for active netdevs so the network stack
6172 * can look at updated numbers whenever it cares to
6173 */
505682cd 6174 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6175 if (pf->vsi[i] && pf->vsi[i]->netdev)
6176 i40e_update_stats(pf->vsi[i]);
6177
d1a8d275
ASJ		 6178 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6179 /* Update the stats for the active switching components */
6180 for (i = 0; i < I40E_MAX_VEB; i++)
6181 if (pf->veb[i])
6182 i40e_update_veb_stats(pf->veb[i]);
6183 }
beb0dff1
JK		 6184
6185 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6186}
6187
6188/**
6189 * i40e_reset_subtask - Set up for resetting the device and driver
6190 * @pf: board private structure
6191 **/
6192static void i40e_reset_subtask(struct i40e_pf *pf)
6193{
6194 u32 reset_flags = 0;
6195
23326186 6196 rtnl_lock();
41c445ff 6197 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6198 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6199 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6200 }
6201 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6202 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6203 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6204 }
6205 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6206 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6207 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6208 }
6209 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6210 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6211 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6212 }
b5d06f05 6213 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6214 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6215 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6216 }
41c445ff
JB		 6217
6218 /* If there's a recovery already waiting, it takes
6219 * precedence before starting a new reset sequence.
6220 */
6221 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6222 i40e_handle_reset_warning(pf);
23326186 6223 goto unlock;
41c445ff
JB		 6224 }
6225
6226 /* If we're already down or resetting, just bail */
6227 if (reset_flags &&
6228 !test_bit(__I40E_DOWN, &pf->state) &&
6229 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6230 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6231
6232unlock:
6233 rtnl_unlock();
41c445ff
JB		 6234}
6235
6236/**
6237 * i40e_handle_link_event - Handle link event
6238 * @pf: board private structure
6239 * @e: event info posted on ARQ
6240 **/
6241static void i40e_handle_link_event(struct i40e_pf *pf,
6242 struct i40e_arq_event_info *e)
6243{
41c445ff
JB		 6244 struct i40e_aqc_get_link_status *status =
6245 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6246
1e701e09
JB		 6247 /* Do a new status request to re-enable LSE reporting
6248 * and load new status information into the hw struct
6249 * This completely ignores any state information
6250 * in the ARQ event info, instead choosing to always
6251 * issue the AQ update link status command.
6252 */
6253 i40e_link_event(pf);
6254
7b592f61
CW		 6255 /* check for unqualified module, if link is down */
6256 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6257 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6258 (!(status->link_info & I40E_AQ_LINK_UP)))
6259 dev_err(&pf->pdev->dev,
6260 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6261}
6262
6263/**
6264 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6265 * @pf: board private structure
6266 **/
6267static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6268{
6269 struct i40e_arq_event_info event;
6270 struct i40e_hw *hw = &pf->hw;
6271 u16 pending, i = 0;
6272 i40e_status ret;
6273 u16 opcode;
86df242b 6274 u32 oldval;
41c445ff
JB		 6275 u32 val;
6276
a316f651
ASJ		 6277 /* Do not run clean AQ when PF reset fails */
6278 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6279 return;
6280
86df242b
SN		 6281 /* check for error indications */
6282 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6283 oldval = val;
6284 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6285 if (hw->debug_mask & I40E_DEBUG_AQ)
6286 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6287 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6288 }
6289 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6290 if (hw->debug_mask & I40E_DEBUG_AQ)
6291 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b 6292 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
1d0a4ada 6293 pf->arq_overflows++;
86df242b
SN		 6294 }
6295 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6296 if (hw->debug_mask & I40E_DEBUG_AQ)
6297 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6298 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6299 }
6300 if (oldval != val)
6301 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6302
6303 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6304 oldval = val;
6305 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6306 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6307 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6308 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6309 }
6310 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6311 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6312 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6313 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6314 }
6315 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6316 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6317 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6318 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6319 }
6320 if (oldval != val)
6321 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6322
1001dc37
MW		 6323 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6324 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6325 if (!event.msg_buf)
6326 return;
6327
6328 do {
6329 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6330 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6331 break;
56497978 6332 else if (ret) {
41c445ff
JB		 6333 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6334 break;
6335 }
6336
6337 opcode = le16_to_cpu(event.desc.opcode);
6338 switch (opcode) {
6339
6340 case i40e_aqc_opc_get_link_status:
6341 i40e_handle_link_event(pf, &event);
6342 break;
6343 case i40e_aqc_opc_send_msg_to_pf:
6344 ret = i40e_vc_process_vf_msg(pf,
6345 le16_to_cpu(event.desc.retval),
6346 le32_to_cpu(event.desc.cookie_high),
6347 le32_to_cpu(event.desc.cookie_low),
6348 event.msg_buf,
1001dc37 6349 event.msg_len);
41c445ff
JB		 6350 break;
6351 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6352 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6353#ifdef CONFIG_I40E_DCB
6354 rtnl_lock();
6355 ret = i40e_handle_lldp_event(pf, &event);
6356 rtnl_unlock();
6357#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6358 break;
6359 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6360 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6361 i40e_handle_lan_overflow_event(pf, &event);
6362 break;
0467bc91
SN		 6363 case i40e_aqc_opc_send_msg_to_peer:
6364 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6365 break;
91a0f930
SN		 6366 case i40e_aqc_opc_nvm_erase:
6367 case i40e_aqc_opc_nvm_update:
00ada50d 6368 case i40e_aqc_opc_oem_post_update:
6e93d0c9
SN		 6369 i40e_debug(&pf->hw, I40E_DEBUG_NVM,
6370 "ARQ NVM operation 0x%04x completed\n",
6371 opcode);
91a0f930 6372 break;
41c445ff
JB		 6373 default:
6374 dev_info(&pf->pdev->dev,
56e5ca68 6375 "ARQ: Unknown event 0x%04x ignored\n",
0467bc91 6376 opcode);
41c445ff
JB		 6377 break;
6378 }
6379 } while (pending && (i++ < pf->adminq_work_limit));
6380
6381 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6382 /* re-enable Admin queue interrupt cause */
6383 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6384 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6385 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6386 i40e_flush(hw);
6387
6388 kfree(event.msg_buf);
6389}
6390
4eb3f768
SN		 6391/**
6392 * i40e_verify_eeprom - make sure eeprom is good to use
6393 * @pf: board private structure
6394 **/
6395static void i40e_verify_eeprom(struct i40e_pf *pf)
6396{
6397 int err;
6398
6399 err = i40e_diag_eeprom_test(&pf->hw);
6400 if (err) {
6401 /* retry in case of garbage read */
6402 err = i40e_diag_eeprom_test(&pf->hw);
6403 if (err) {
6404 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6405 err);
6406 set_bit(__I40E_BAD_EEPROM, &pf->state);
6407 }
6408 }
6409
6410 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6411 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6412 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6413 }
6414}
6415
386a0afa
AA		 6416/**
6417 * i40e_enable_pf_switch_lb
b40c82e6 6418 * @pf: pointer to the PF structure
386a0afa
AA		 6419 *
6420 * enable switch loop back or die - no point in a return value
6421 **/
6422static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6423{
6424 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6425 struct i40e_vsi_context ctxt;
f1c7e72e 6426 int ret;
386a0afa
AA		 6427
6428 ctxt.seid = pf->main_vsi_seid;
6429 ctxt.pf_num = pf->hw.pf_id;
6430 ctxt.vf_num = 0;
f1c7e72e
SN		 6431 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6432 if (ret) {
386a0afa 6433 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6434 "couldn't get PF vsi config, err %s aq_err %s\n",
6435 i40e_stat_str(&pf->hw, ret),
6436 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6437 return;
6438 }
6439 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6440 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6441 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6442
f1c7e72e
SN		 6443 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6444 if (ret) {
386a0afa 6445 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6446 "update vsi switch failed, err %s aq_err %s\n",
6447 i40e_stat_str(&pf->hw, ret),
6448 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6449 }
6450}
6451
6452/**
6453 * i40e_disable_pf_switch_lb
b40c82e6 6454 * @pf: pointer to the PF structure
386a0afa
AA		 6455 *
6456 * disable switch loop back or die - no point in a return value
6457 **/
6458static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6459{
6460 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6461 struct i40e_vsi_context ctxt;
f1c7e72e 6462 int ret;
386a0afa
AA		 6463
6464 ctxt.seid = pf->main_vsi_seid;
6465 ctxt.pf_num = pf->hw.pf_id;
6466 ctxt.vf_num = 0;
f1c7e72e
SN		 6467 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6468 if (ret) {
386a0afa 6469 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6470 "couldn't get PF vsi config, err %s aq_err %s\n",
6471 i40e_stat_str(&pf->hw, ret),
6472 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6473 return;
6474 }
6475 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6476 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6477 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6478
f1c7e72e
SN		 6479 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6480 if (ret) {
386a0afa 6481 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6482 "update vsi switch failed, err %s aq_err %s\n",
6483 i40e_stat_str(&pf->hw, ret),
6484 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6485 }
6486}
6487
51616018
NP		 6488/**
6489 * i40e_config_bridge_mode - Configure the HW bridge mode
6490 * @veb: pointer to the bridge instance
6491 *
6492 * Configure the loop back mode for the LAN VSI that is downlink to the
6493 * specified HW bridge instance. It is expected this function is called
6494 * when a new HW bridge is instantiated.
6495 **/
6496static void i40e_config_bridge_mode(struct i40e_veb *veb)
6497{
6498 struct i40e_pf *pf = veb->pf;
6499
6dec1017
SN		 6500 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6501 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6502 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6503 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6504 i40e_disable_pf_switch_lb(pf);
6505 else
6506 i40e_enable_pf_switch_lb(pf);
6507}
6508
41c445ff
JB		 6509/**
6510 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6511 * @veb: pointer to the VEB instance
6512 *
6513 * This is a recursive function that first builds the attached VSIs then
6514 * recurses in to build the next layer of VEB. We track the connections
6515 * through our own index numbers because the seid's from the HW could
6516 * change across the reset.
6517 **/
6518static int i40e_reconstitute_veb(struct i40e_veb *veb)
6519{
6520 struct i40e_vsi *ctl_vsi = NULL;
6521 struct i40e_pf *pf = veb->pf;
6522 int v, veb_idx;
6523 int ret;
6524
6525 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6526 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6527 if (pf->vsi[v] &&
6528 pf->vsi[v]->veb_idx == veb->idx &&
6529 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6530 ctl_vsi = pf->vsi[v];
6531 break;
6532 }
6533 }
6534 if (!ctl_vsi) {
6535 dev_info(&pf->pdev->dev,
6536 "missing owner VSI for veb_idx %d\n", veb->idx);
6537 ret = -ENOENT;
6538 goto end_reconstitute;
6539 }
6540 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6541 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6542 ret = i40e_add_vsi(ctl_vsi);
6543 if (ret) {
6544 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6545 "rebuild of veb_idx %d owner VSI failed: %d\n",
6546 veb->idx, ret);
41c445ff
JB		 6547 goto end_reconstitute;
6548 }
6549 i40e_vsi_reset_stats(ctl_vsi);
6550
6551 /* create the VEB in the switch and move the VSI onto the VEB */
6552 ret = i40e_add_veb(veb, ctl_vsi);
6553 if (ret)
6554 goto end_reconstitute;
6555
fc60861e
ASJ		 6556 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6557 veb->bridge_mode = BRIDGE_MODE_VEB;
6558 else
6559 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6560 i40e_config_bridge_mode(veb);
b64ba084 6561
41c445ff 6562 /* create the remaining VSIs attached to this VEB */
505682cd 6563 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6564 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6565 continue;
6566
6567 if (pf->vsi[v]->veb_idx == veb->idx) {
6568 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6569
41c445ff
JB		 6570 vsi->uplink_seid = veb->seid;
6571 ret = i40e_add_vsi(vsi);
6572 if (ret) {
6573 dev_info(&pf->pdev->dev,
6574 "rebuild of vsi_idx %d failed: %d\n",
6575 v, ret);
6576 goto end_reconstitute;
6577 }
6578 i40e_vsi_reset_stats(vsi);
6579 }
6580 }
6581
6582 /* create any VEBs attached to this VEB - RECURSION */
6583 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6584 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6585 pf->veb[veb_idx]->uplink_seid = veb->seid;
6586 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6587 if (ret)
6588 break;
6589 }
6590 }
6591
6592end_reconstitute:
6593 return ret;
6594}
6595
6596/**
6597 * i40e_get_capabilities - get info about the HW
6598 * @pf: the PF struct
6599 **/
6600static int i40e_get_capabilities(struct i40e_pf *pf)
6601{
6602 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6603 u16 data_size;
6604 int buf_len;
6605 int err;
6606
6607 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6608 do {
6609 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6610 if (!cap_buf)
6611 return -ENOMEM;
6612
6613 /* this loads the data into the hw struct for us */
6614 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6615 &data_size,
6616 i40e_aqc_opc_list_func_capabilities,
6617 NULL);
6618 /* data loaded, buffer no longer needed */
6619 kfree(cap_buf);
6620
6621 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6622 /* retry with a larger buffer */
6623 buf_len = data_size;
6624 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6625 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6626 "capability discovery failed, err %s aq_err %s\n",
6627 i40e_stat_str(&pf->hw, err),
6628 i40e_aq_str(&pf->hw,
6629 pf->hw.aq.asq_last_status));
41c445ff
JB		 6630 return -ENODEV;
6631 }
6632 } while (err);
6633
6634 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6635 dev_info(&pf->pdev->dev,
6636 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6637 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6638 pf->hw.func_caps.num_msix_vectors,
6639 pf->hw.func_caps.num_msix_vectors_vf,
6640 pf->hw.func_caps.fd_filters_guaranteed,
6641 pf->hw.func_caps.fd_filters_best_effort,
6642 pf->hw.func_caps.num_tx_qp,
6643 pf->hw.func_caps.num_vsis);
6644
7134f9ce
JB		 6645#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6646 + pf->hw.func_caps.num_vfs)
6647 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6648 dev_info(&pf->pdev->dev,
6649 "got num_vsis %d, setting num_vsis to %d\n",
6650 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6651 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6652 }
6653
41c445ff
JB		 6654 return 0;
6655}
6656
cbf61325
ASJ		 6657static int i40e_vsi_clear(struct i40e_vsi *vsi);
6658
41c445ff 6659/**
cbf61325 6660 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6661 * @pf: board private structure
6662 **/
cbf61325 6663static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6664{
6665 struct i40e_vsi *vsi;
8a9eb7d3 6666 int i;
41c445ff 6667
407e063c
JB		 6668 /* quick workaround for an NVM issue that leaves a critical register
6669 * uninitialized
6670 */
6671 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6672 static const u32 hkey[] = {
6673 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6674 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6675 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6676 0x95b3a76d};
6677
6678 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6679 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6680 }
6681
cbf61325 6682 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6683 return;
6684
cbf61325 6685 /* find existing VSI and see if it needs configuring */
41c445ff 6686 vsi = NULL;
505682cd 6687 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6688 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6689 vsi = pf->vsi[i];
cbf61325
ASJ		 6690 break;
6691 }
6692 }
6693
6694 /* create a new VSI if none exists */
41c445ff 6695 if (!vsi) {
cbf61325
ASJ		 6696 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6697 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6698 if (!vsi) {
6699 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6700 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6701 return;
41c445ff 6702 }
cbf61325 6703 }
41c445ff 6704
8a9eb7d3 6705 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6706}
6707
6708/**
6709 * i40e_fdir_teardown - release the Flow Director resources
6710 * @pf: board private structure
6711 **/
6712static void i40e_fdir_teardown(struct i40e_pf *pf)
6713{
6714 int i;
6715
17a73f6b 6716 i40e_fdir_filter_exit(pf);
505682cd 6717 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6718 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6719 i40e_vsi_release(pf->vsi[i]);
6720 break;
6721 }
6722 }
6723}
6724
6725/**
f650a38b 6726 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6727 * @pf: board private structure
6728 *
b40c82e6 6729 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6730 **/
23cfbe07 6731static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6732{
41c445ff 6733 struct i40e_hw *hw = &pf->hw;
60442dea 6734 i40e_status ret = 0;
41c445ff
JB		 6735 u32 v;
6736
6737 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6738 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6739 return;
d3ce5734
MW		 6740 if (i40e_check_asq_alive(&pf->hw))
6741 i40e_vc_notify_reset(pf);
41c445ff 6742
69bfb110 6743 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6744
41c445ff
JB		 6745 /* quiesce the VSIs and their queues that are not already DOWN */
6746 i40e_pf_quiesce_all_vsi(pf);
6747
505682cd 6748 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6749 if (pf->vsi[v])
6750 pf->vsi[v]->seid = 0;
6751 }
6752
6753 i40e_shutdown_adminq(&pf->hw);
6754
f650a38b 6755 /* call shutdown HMC */
60442dea
SN		 6756 if (hw->hmc.hmc_obj) {
6757 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6758 if (ret)
60442dea
SN		 6759 dev_warn(&pf->pdev->dev,
6760 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6761 }
f650a38b
ASJ		 6762}
6763
44033fac
JB		 6764/**
6765 * i40e_send_version - update firmware with driver version
6766 * @pf: PF struct
6767 */
6768static void i40e_send_version(struct i40e_pf *pf)
6769{
6770 struct i40e_driver_version dv;
6771
6772 dv.major_version = DRV_VERSION_MAJOR;
6773 dv.minor_version = DRV_VERSION_MINOR;
6774 dv.build_version = DRV_VERSION_BUILD;
6775 dv.subbuild_version = 0;
35a7d804 6776 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6777 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6778}
6779
f650a38b 6780/**
4dda12e6 6781 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6782 * @pf: board private structure
bc7d338f 6783 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6784 **/
bc7d338f 6785static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6786{
f650a38b 6787 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6788 u8 set_fc_aq_fail = 0;
f650a38b 6789 i40e_status ret;
4f2f017c 6790 u32 val;
f650a38b
ASJ		 6791 u32 v;
6792
41c445ff
JB		 6793 /* Now we wait for GRST to settle out.
6794 * We don't have to delete the VEBs or VSIs from the hw switch
6795 * because the reset will make them disappear.
6796 */
6797 ret = i40e_pf_reset(hw);
b5565400 6798 if (ret) {
41c445ff 6799 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6800 set_bit(__I40E_RESET_FAILED, &pf->state);
6801 goto clear_recovery;
b5565400 6802 }
41c445ff
JB		 6803 pf->pfr_count++;
6804
6805 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6806 goto clear_recovery;
69bfb110 6807 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6808
6809 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6810 ret = i40e_init_adminq(&pf->hw);
6811 if (ret) {
f1c7e72e
SN		 6812 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6813 i40e_stat_str(&pf->hw, ret),
6814 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6815 goto clear_recovery;
41c445ff
JB		 6816 }
6817
4eb3f768 6818 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6819 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6820 i40e_verify_eeprom(pf);
4eb3f768 6821
e78ac4bf 6822 i40e_clear_pxe_mode(hw);
41c445ff 6823 ret = i40e_get_capabilities(pf);
f1c7e72e 6824 if (ret)
41c445ff 6825 goto end_core_reset;
41c445ff 6826
41c445ff
JB		 6827 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6828 hw->func_caps.num_rx_qp,
6829 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6830 if (ret) {
6831 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6832 goto end_core_reset;
6833 }
6834 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6835 if (ret) {
6836 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6837 goto end_core_reset;
6838 }
6839
4e3b35b0
NP		 6840#ifdef CONFIG_I40E_DCB
6841 ret = i40e_init_pf_dcb(pf);
6842 if (ret) {
aebfc816
SN		 6843 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6844 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6845 /* Continue without DCB enabled */
4e3b35b0
NP		 6846 }
6847#endif /* CONFIG_I40E_DCB */
38e00438 6848#ifdef I40E_FCOE
21364bcf 6849 i40e_init_pf_fcoe(pf);
4e3b35b0 6850
38e00438 6851#endif
41c445ff 6852 /* do basic switch setup */
bc7d338f 6853 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6854 if (ret)
6855 goto end_core_reset;
6856
2f0aff41
SN		 6857 /* The driver only wants link up/down and module qualification
6858 * reports from firmware. Note the negative logic.
7e2453fe
JB		 6859 */
6860 ret = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 6861 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 6862 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 6863 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 6864 if (ret)
f1c7e72e
SN		 6865 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6866 i40e_stat_str(&pf->hw, ret),
6867 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6868
cafa2ee6
ASJ		 6869 /* make sure our flow control settings are restored */
6870 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6871 if (ret)
8279e495
NP		 6872 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6873 i40e_stat_str(&pf->hw, ret),
6874 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6875
41c445ff
JB		 6876 /* Rebuild the VSIs and VEBs that existed before reset.
6877 * They are still in our local switch element arrays, so only
6878 * need to rebuild the switch model in the HW.
6879 *
6880 * If there were VEBs but the reconstitution failed, we'll try
6881 * try to recover minimal use by getting the basic PF VSI working.
6882 */
6883 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6884 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6885 /* find the one VEB connected to the MAC, and find orphans */
6886 for (v = 0; v < I40E_MAX_VEB; v++) {
6887 if (!pf->veb[v])
6888 continue;
6889
6890 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6891 pf->veb[v]->uplink_seid == 0) {
6892 ret = i40e_reconstitute_veb(pf->veb[v]);
6893
6894 if (!ret)
6895 continue;
6896
6897 /* If Main VEB failed, we're in deep doodoo,
6898 * so give up rebuilding the switch and set up
6899 * for minimal rebuild of PF VSI.
6900 * If orphan failed, we'll report the error
6901 * but try to keep going.
6902 */
6903 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6904 dev_info(&pf->pdev->dev,
6905 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6906 ret);
6907 pf->vsi[pf->lan_vsi]->uplink_seid
6908 = pf->mac_seid;
6909 break;
6910 } else if (pf->veb[v]->uplink_seid == 0) {
6911 dev_info(&pf->pdev->dev,
6912 "rebuild of orphan VEB failed: %d\n",
6913 ret);
6914 }
6915 }
6916 }
6917 }
6918
6919 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6920 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6921 /* no VEB, so rebuild only the Main VSI */
6922 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6923 if (ret) {
6924 dev_info(&pf->pdev->dev,
6925 "rebuild of Main VSI failed: %d\n", ret);
6926 goto end_core_reset;
6927 }
6928 }
6929
4f2f017c
ASJ		 6930 /* Reconfigure hardware for allowing smaller MSS in the case
6931 * of TSO, so that we avoid the MDD being fired and causing
6932 * a reset in the case of small MSS+TSO.
6933 */
6934#define I40E_REG_MSS 0x000E64DC
6935#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6936#define I40E_64BYTE_MSS 0x400000
6937 val = rd32(hw, I40E_REG_MSS);
6938 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6939 val &= ~I40E_REG_MSS_MIN_MASK;
6940 val |= I40E_64BYTE_MSS;
6941 wr32(hw, I40E_REG_MSS, val);
6942 }
6943
8eed76fa 6944 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 6945 msleep(75);
6946 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6947 if (ret)
f1c7e72e
SN		 6948 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6949 i40e_stat_str(&pf->hw, ret),
6950 i40e_aq_str(&pf->hw,
6951 pf->hw.aq.asq_last_status));
cafa2ee6 6952 }
41c445ff
JB		 6953 /* reinit the misc interrupt */
6954 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6955 ret = i40e_setup_misc_vector(pf);
6956
e7358f54
ASJ		 6957 /* Add a filter to drop all Flow control frames from any VSI from being
6958 * transmitted. By doing so we stop a malicious VF from sending out
6959 * PAUSE or PFC frames and potentially controlling traffic for other
6960 * PF/VF VSIs.
6961 * The FW can still send Flow control frames if enabled.
6962 */
6963 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6964 pf->main_vsi_seid);
6965
41c445ff
JB		 6966 /* restart the VSIs that were rebuilt and running before the reset */
6967 i40e_pf_unquiesce_all_vsi(pf);
6968
69f64b2b
MW		 6969 if (pf->num_alloc_vfs) {
6970 for (v = 0; v < pf->num_alloc_vfs; v++)
6971 i40e_reset_vf(&pf->vf[v], true);
6972 }
6973
41c445ff 6974 /* tell the firmware that we're starting */
44033fac 6975 i40e_send_version(pf);
41c445ff
JB		 6976
6977end_core_reset:
a316f651
ASJ		 6978 clear_bit(__I40E_RESET_FAILED, &pf->state);
6979clear_recovery:
41c445ff
JB		 6980 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6981}
6982
f650a38b 6983/**
b40c82e6 6984 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6985 * @pf: board private structure
6986 *
6987 * Close up the VFs and other things in prep for a Core Reset,
6988 * then get ready to rebuild the world.
6989 **/
6990static void i40e_handle_reset_warning(struct i40e_pf *pf)
6991{
23cfbe07
SN		 6992 i40e_prep_for_reset(pf);
6993 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6994}
6995
41c445ff
JB		 6996/**
6997 * i40e_handle_mdd_event
b40c82e6 6998 * @pf: pointer to the PF structure
41c445ff
JB		 6999 *
7000 * Called from the MDD irq handler to identify possibly malicious vfs
7001 **/
7002static void i40e_handle_mdd_event(struct i40e_pf *pf)
7003{
7004 struct i40e_hw *hw = &pf->hw;
7005 bool mdd_detected = false;
df430b12 7006 bool pf_mdd_detected = false;
41c445ff
JB		 7007 struct i40e_vf *vf;
7008 u32 reg;
7009 int i;
7010
7011 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
7012 return;
7013
7014 /* find what triggered the MDD event */
7015 reg = rd32(hw, I40E_GL_MDET_TX);
7016 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 7017 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
7018 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 7019 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 7020 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 7021 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 7022 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 7023 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
7024 I40E_GL_MDET_TX_QUEUE_SHIFT) -
7025 pf->hw.func_caps.base_queue;
faf32978 7026 if (netif_msg_tx_err(pf))
b40c82e6 7027 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 7028 event, queue, pf_num, vf_num);
41c445ff
JB		 7029 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
7030 mdd_detected = true;
7031 }
7032 reg = rd32(hw, I40E_GL_MDET_RX);
7033 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 7034 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
7035 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 7036 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 7037 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 7038 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
7039 I40E_GL_MDET_RX_QUEUE_SHIFT) -
7040 pf->hw.func_caps.base_queue;
faf32978
JB		 7041 if (netif_msg_rx_err(pf))
7042 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
7043 event, queue, func);
41c445ff
JB		 7044 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
7045 mdd_detected = true;
7046 }
7047
df430b12
NP		 7048 if (mdd_detected) {
7049 reg = rd32(hw, I40E_PF_MDET_TX);
7050 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
7051 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 7052 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 7053 pf_mdd_detected = true;
7054 }
7055 reg = rd32(hw, I40E_PF_MDET_RX);
7056 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
7057 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 7058 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 7059 pf_mdd_detected = true;
7060 }
7061 /* Queue belongs to the PF, initiate a reset */
7062 if (pf_mdd_detected) {
7063 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7064 i40e_service_event_schedule(pf);
7065 }
7066 }
7067
41c445ff
JB		 7068 /* see if one of the VFs needs its hand slapped */
7069 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7070 vf = &(pf->vf[i]);
7071 reg = rd32(hw, I40E_VP_MDET_TX(i));
7072 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7073 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7074 vf->num_mdd_events++;
faf32978
JB		 7075 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7076 i);
41c445ff
JB		 7077 }
7078
7079 reg = rd32(hw, I40E_VP_MDET_RX(i));
7080 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7081 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7082 vf->num_mdd_events++;
faf32978
JB		 7083 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7084 i);
41c445ff
JB		 7085 }
7086
7087 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7088 dev_info(&pf->pdev->dev,
7089 "Too many MDD events on VF %d, disabled\n", i);
7090 dev_info(&pf->pdev->dev,
7091 "Use PF Control I/F to re-enable the VF\n");
7092 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7093 }
7094 }
7095
7096 /* re-enable mdd interrupt cause */
7097 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7098 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7099 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7100 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7101 i40e_flush(hw);
7102}
7103
a1c9a9d9 7104/**
6a899024 7105 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7106 * @pf: board private structure
7107 **/
6a899024 7108static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7109{
6a899024 7110#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9
JK		 7111 struct i40e_hw *hw = &pf->hw;
7112 i40e_status ret;
a1c9a9d9
JK		 7113 __be16 port;
7114 int i;
7115
6a899024 7116 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7117 return;
7118
6a899024 7119 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7120
7121 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7122 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7123 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7124 port = pf->udp_ports[i].index;
c22c06c8
SN		 7125 if (port)
7126 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7127 pf->udp_ports[i].type,
c22c06c8
SN		 7128 NULL, NULL);
7129 else
7130 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7131
7132 if (ret) {
730a8f87
CW		 7133 dev_dbg(&pf->pdev->dev,
7134 "%s %s port %d, index %d failed, err %s aq_err %s\n",
7135 pf->udp_ports[i].type ? "vxlan" : "geneve",
7136 port ? "add" : "delete",
7137 ntohs(port), i,
7138 i40e_stat_str(&pf->hw, ret),
7139 i40e_aq_str(&pf->hw,
f1c7e72e 7140 pf->hw.aq.asq_last_status));
6a899024 7141 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7142 }
7143 }
7144 }
6a899024 7145#endif
a1c9a9d9
JK		 7146}
7147
41c445ff
JB		 7148/**
7149 * i40e_service_task - Run the driver's async subtasks
7150 * @work: pointer to work_struct containing our data
7151 **/
7152static void i40e_service_task(struct work_struct *work)
7153{
7154 struct i40e_pf *pf = container_of(work,
7155 struct i40e_pf,
7156 service_task);
7157 unsigned long start_time = jiffies;
7158
e57a2fea
SN		 7159 /* don't bother with service tasks if a reset is in progress */
7160 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7161 i40e_service_event_complete(pf);
7162 return;
7163 }
7164
b03a8c1f 7165 i40e_detect_recover_hung(pf);
2818ccd9 7166 i40e_sync_filters_subtask(pf);
41c445ff
JB		 7167 i40e_reset_subtask(pf);
7168 i40e_handle_mdd_event(pf);
7169 i40e_vc_process_vflr_event(pf);
7170 i40e_watchdog_subtask(pf);
7171 i40e_fdir_reinit_subtask(pf);
e3219ce6 7172 i40e_client_subtask(pf);
41c445ff 7173 i40e_sync_filters_subtask(pf);
6a899024 7174 i40e_sync_udp_filters_subtask(pf);
41c445ff
JB		 7175 i40e_clean_adminq_subtask(pf);
7176
7177 i40e_service_event_complete(pf);
7178
7179 /* If the tasks have taken longer than one timer cycle or there
7180 * is more work to be done, reschedule the service task now
7181 * rather than wait for the timer to tick again.
7182 */
7183 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7184 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7185 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7186 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7187 i40e_service_event_schedule(pf);
7188}
7189
7190/**
7191 * i40e_service_timer - timer callback
7192 * @data: pointer to PF struct
7193 **/
7194static void i40e_service_timer(unsigned long data)
7195{
7196 struct i40e_pf *pf = (struct i40e_pf *)data;
7197
7198 mod_timer(&pf->service_timer,
7199 round_jiffies(jiffies + pf->service_timer_period));
7200 i40e_service_event_schedule(pf);
7201}
7202
7203/**
7204 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7205 * @vsi: the VSI being configured
7206 **/
7207static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7208{
7209 struct i40e_pf *pf = vsi->back;
7210
7211 switch (vsi->type) {
7212 case I40E_VSI_MAIN:
7213 vsi->alloc_queue_pairs = pf->num_lan_qps;
7214 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7215 I40E_REQ_DESCRIPTOR_MULTIPLE);
7216 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7217 vsi->num_q_vectors = pf->num_lan_msix;
7218 else
7219 vsi->num_q_vectors = 1;
7220
7221 break;
7222
7223 case I40E_VSI_FDIR:
7224 vsi->alloc_queue_pairs = 1;
7225 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7226 I40E_REQ_DESCRIPTOR_MULTIPLE);
7227 vsi->num_q_vectors = 1;
7228 break;
7229
7230 case I40E_VSI_VMDQ2:
7231 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7232 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7233 I40E_REQ_DESCRIPTOR_MULTIPLE);
7234 vsi->num_q_vectors = pf->num_vmdq_msix;
7235 break;
7236
7237 case I40E_VSI_SRIOV:
7238 vsi->alloc_queue_pairs = pf->num_vf_qps;
7239 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7240 I40E_REQ_DESCRIPTOR_MULTIPLE);
7241 break;
7242
38e00438
VD		 7243#ifdef I40E_FCOE
7244 case I40E_VSI_FCOE:
7245 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7246 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7247 I40E_REQ_DESCRIPTOR_MULTIPLE);
7248 vsi->num_q_vectors = pf->num_fcoe_msix;
7249 break;
7250
7251#endif /* I40E_FCOE */
41c445ff
JB		 7252 default:
7253 WARN_ON(1);
7254 return -ENODATA;
7255 }
7256
7257 return 0;
7258}
7259
f650a38b
ASJ		 7260/**
7261 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7262 * @type: VSI pointer
bc7d338f 7263 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7264 *
7265 * On error: returns error code (negative)
7266 * On success: returns 0
7267 **/
bc7d338f 7268static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7269{
7270 int size;
7271 int ret = 0;
7272
ac6c5e3d 7273 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7274 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7275 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7276 if (!vsi->tx_rings)
7277 return -ENOMEM;
f650a38b
ASJ		 7278 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7279
bc7d338f
ASJ		 7280 if (alloc_qvectors) {
7281 /* allocate memory for q_vector pointers */
f57e4fbd 7282 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7283 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7284 if (!vsi->q_vectors) {
7285 ret = -ENOMEM;
7286 goto err_vectors;
7287 }
f650a38b
ASJ		 7288 }
7289 return ret;
7290
7291err_vectors:
7292 kfree(vsi->tx_rings);
7293 return ret;
7294}
7295
41c445ff
JB		 7296/**
7297 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7298 * @pf: board private structure
7299 * @type: type of VSI
7300 *
7301 * On error: returns error code (negative)
7302 * On success: returns vsi index in PF (positive)
7303 **/
7304static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7305{
7306 int ret = -ENODEV;
7307 struct i40e_vsi *vsi;
7308 int vsi_idx;
7309 int i;
7310
7311 /* Need to protect the allocation of the VSIs at the PF level */
7312 mutex_lock(&pf->switch_mutex);
7313
7314 /* VSI list may be fragmented if VSI creation/destruction has
7315 * been happening. We can afford to do a quick scan to look
7316 * for any free VSIs in the list.
7317 *
7318 * find next empty vsi slot, looping back around if necessary
7319 */
7320 i = pf->next_vsi;
505682cd 7321 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7322 i++;
505682cd 7323 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7324 i = 0;
7325 while (i < pf->next_vsi && pf->vsi[i])
7326 i++;
7327 }
7328
505682cd 7329 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7330 vsi_idx = i; /* Found one! */
7331 } else {
7332 ret = -ENODEV;
493fb300 7333 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7334 }
7335 pf->next_vsi = ++i;
7336
7337 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7338 if (!vsi) {
7339 ret = -ENOMEM;
493fb300 7340 goto unlock_pf;
41c445ff
JB		 7341 }
7342 vsi->type = type;
7343 vsi->back = pf;
7344 set_bit(__I40E_DOWN, &vsi->state);
7345 vsi->flags = 0;
7346 vsi->idx = vsi_idx;
ac26fc13 7347 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7348 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7349 pf->rss_table_size : 64;
41c445ff
JB		 7350 vsi->netdev_registered = false;
7351 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7352 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7353 vsi->irqs_ready = false;
41c445ff 7354
9f65e15b
AD		 7355 ret = i40e_set_num_rings_in_vsi(vsi);
7356 if (ret)
7357 goto err_rings;
7358
bc7d338f 7359 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7360 if (ret)
9f65e15b 7361 goto err_rings;
493fb300 7362
41c445ff
JB		 7363 /* Setup default MSIX irq handler for VSI */
7364 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7365
21659035
KP		 7366 /* Initialize VSI lock */
7367 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7368 pf->vsi[vsi_idx] = vsi;
7369 ret = vsi_idx;
493fb300
AD		 7370 goto unlock_pf;
7371
9f65e15b 7372err_rings:
493fb300
AD		 7373 pf->next_vsi = i - 1;
7374 kfree(vsi);
7375unlock_pf:
41c445ff
JB		 7376 mutex_unlock(&pf->switch_mutex);
7377 return ret;
7378}
7379
f650a38b
ASJ		 7380/**
7381 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7382 * @type: VSI pointer
bc7d338f 7383 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7384 *
7385 * On error: returns error code (negative)
7386 * On success: returns 0
7387 **/
bc7d338f 7388static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7389{
7390 /* free the ring and vector containers */
bc7d338f
ASJ		 7391 if (free_qvectors) {
7392 kfree(vsi->q_vectors);
7393 vsi->q_vectors = NULL;
7394 }
f650a38b
ASJ		 7395 kfree(vsi->tx_rings);
7396 vsi->tx_rings = NULL;
7397 vsi->rx_rings = NULL;
7398}
7399
28c5869f
HZ		 7400/**
7401 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7402 * and lookup table
7403 * @vsi: Pointer to VSI structure
7404 */
7405static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7406{
7407 if (!vsi)
7408 return;
7409
7410 kfree(vsi->rss_hkey_user);
7411 vsi->rss_hkey_user = NULL;
7412
7413 kfree(vsi->rss_lut_user);
7414 vsi->rss_lut_user = NULL;
7415}
7416
41c445ff
JB		 7417/**
7418 * i40e_vsi_clear - Deallocate the VSI provided
7419 * @vsi: the VSI being un-configured
7420 **/
7421static int i40e_vsi_clear(struct i40e_vsi *vsi)
7422{
7423 struct i40e_pf *pf;
7424
7425 if (!vsi)
7426 return 0;
7427
7428 if (!vsi->back)
7429 goto free_vsi;
7430 pf = vsi->back;
7431
7432 mutex_lock(&pf->switch_mutex);
7433 if (!pf->vsi[vsi->idx]) {
7434 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7435 vsi->idx, vsi->idx, vsi, vsi->type);
7436 goto unlock_vsi;
7437 }
7438
7439 if (pf->vsi[vsi->idx] != vsi) {
7440 dev_err(&pf->pdev->dev,
7441 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7442 pf->vsi[vsi->idx]->idx,
7443 pf->vsi[vsi->idx],
7444 pf->vsi[vsi->idx]->type,
7445 vsi->idx, vsi, vsi->type);
7446 goto unlock_vsi;
7447 }
7448
b40c82e6 7449 /* updates the PF for this cleared vsi */
41c445ff
JB		 7450 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7451 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7452
bc7d338f 7453 i40e_vsi_free_arrays(vsi, true);
28c5869f 7454 i40e_clear_rss_config_user(vsi);
493fb300 7455
41c445ff
JB		 7456 pf->vsi[vsi->idx] = NULL;
7457 if (vsi->idx < pf->next_vsi)
7458 pf->next_vsi = vsi->idx;
7459
7460unlock_vsi:
7461 mutex_unlock(&pf->switch_mutex);
7462free_vsi:
7463 kfree(vsi);
7464
7465 return 0;
7466}
7467
9f65e15b
AD		 7468/**
7469 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7470 * @vsi: the VSI being cleaned
7471 **/
be1d5eea 7472static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7473{
7474 int i;
7475
8e9dca53 7476 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7477 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7478 kfree_rcu(vsi->tx_rings[i], rcu);
7479 vsi->tx_rings[i] = NULL;
7480 vsi->rx_rings[i] = NULL;
7481 }
be1d5eea 7482 }
9f65e15b
AD		 7483}
7484
41c445ff
JB		 7485/**
7486 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7487 * @vsi: the VSI being configured
7488 **/
7489static int i40e_alloc_rings(struct i40e_vsi *vsi)
7490{
e7046ee1 7491 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7492 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7493 int i;
7494
41c445ff 7495 /* Set basic values in the rings to be used later during open() */
d7397644 7496 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7497 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7498 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7499 if (!tx_ring)
7500 goto err_out;
41c445ff
JB		 7501
7502 tx_ring->queue_index = i;
7503 tx_ring->reg_idx = vsi->base_queue + i;
7504 tx_ring->ring_active = false;
7505 tx_ring->vsi = vsi;
7506 tx_ring->netdev = vsi->netdev;
7507 tx_ring->dev = &pf->pdev->dev;
7508 tx_ring->count = vsi->num_desc;
7509 tx_ring->size = 0;
7510 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7511 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7512 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
a75e8005 7513 tx_ring->tx_itr_setting = pf->tx_itr_default;
9f65e15b 7514 vsi->tx_rings[i] = tx_ring;
41c445ff 7515
9f65e15b 7516 rx_ring = &tx_ring[1];
41c445ff
JB		 7517 rx_ring->queue_index = i;
7518 rx_ring->reg_idx = vsi->base_queue + i;
7519 rx_ring->ring_active = false;
7520 rx_ring->vsi = vsi;
7521 rx_ring->netdev = vsi->netdev;
7522 rx_ring->dev = &pf->pdev->dev;
7523 rx_ring->count = vsi->num_desc;
7524 rx_ring->size = 0;
7525 rx_ring->dcb_tc = 0;
7526 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7527 set_ring_16byte_desc_enabled(rx_ring);
7528 else
7529 clear_ring_16byte_desc_enabled(rx_ring);
a75e8005 7530 rx_ring->rx_itr_setting = pf->rx_itr_default;
9f65e15b 7531 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7532 }
7533
7534 return 0;
9f65e15b
AD		 7535
7536err_out:
7537 i40e_vsi_clear_rings(vsi);
7538 return -ENOMEM;
41c445ff
JB		 7539}
7540
7541/**
7542 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7543 * @pf: board private structure
7544 * @vectors: the number of MSI-X vectors to request
7545 *
7546 * Returns the number of vectors reserved, or error
7547 **/
7548static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7549{
7b37f376
AG		 7550 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7551 I40E_MIN_MSIX, vectors);
7552 if (vectors < 0) {
41c445ff 7553 dev_info(&pf->pdev->dev,
7b37f376 7554 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7555 vectors = 0;
7556 }
7557
7558 return vectors;
7559}
7560
7561/**
7562 * i40e_init_msix - Setup the MSIX capability
7563 * @pf: board private structure
7564 *
7565 * Work with the OS to set up the MSIX vectors needed.
7566 *
3b444399 7567 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7568 **/
7569static int i40e_init_msix(struct i40e_pf *pf)
7570{
41c445ff 7571 struct i40e_hw *hw = &pf->hw;
1e200e4a 7572 int vectors_left;
41c445ff 7573 int v_budget, i;
3b444399 7574 int v_actual;
e3219ce6 7575 int iwarp_requested = 0;
41c445ff
JB		 7576
7577 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7578 return -ENODEV;
7579
7580 /* The number of vectors we'll request will be comprised of:
7581 * - Add 1 for "other" cause for Admin Queue events, etc.
7582 * - The number of LAN queue pairs
f8ff1464
ASJ		 7583 * - Queues being used for RSS.
7584 * We don't need as many as max_rss_size vectors.
7585 * use rss_size instead in the calculation since that
7586 * is governed by number of cpus in the system.
7587 * - assumes symmetric Tx/Rx pairing
41c445ff 7588 * - The number of VMDq pairs
e3219ce6 7589 * - The CPU count within the NUMA node if iWARP is enabled
38e00438
VD		 7590#ifdef I40E_FCOE
7591 * - The number of FCOE qps.
7592#endif
41c445ff
JB		 7593 * Once we count this up, try the request.
7594 *
7595 * If we can't get what we want, we'll simplify to nearly nothing
7596 * and try again. If that still fails, we punt.
7597 */
1e200e4a
SN		 7598 vectors_left = hw->func_caps.num_msix_vectors;
7599 v_budget = 0;
7600
7601 /* reserve one vector for miscellaneous handler */
7602 if (vectors_left) {
7603 v_budget++;
7604 vectors_left--;
7605 }
7606
7607 /* reserve vectors for the main PF traffic queues */
7608 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7609 vectors_left -= pf->num_lan_msix;
7610 v_budget += pf->num_lan_msix;
7611
7612 /* reserve one vector for sideband flow director */
7613 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7614 if (vectors_left) {
7615 v_budget++;
7616 vectors_left--;
7617 } else {
7618 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7619 }
7620 }
83840e4b 7621
38e00438 7622#ifdef I40E_FCOE
1e200e4a 7623 /* can we reserve enough for FCoE? */
38e00438 7624 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7625 if (!vectors_left)
7626 pf->num_fcoe_msix = 0;
7627 else if (vectors_left >= pf->num_fcoe_qps)
7628 pf->num_fcoe_msix = pf->num_fcoe_qps;
7629 else
7630 pf->num_fcoe_msix = 1;
38e00438 7631 v_budget += pf->num_fcoe_msix;
1e200e4a 7632 vectors_left -= pf->num_fcoe_msix;
38e00438 7633 }
1e200e4a 7634
38e00438 7635#endif
e3219ce6
ASJ		 7636 /* can we reserve enough for iWARP? */
7637 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7638 if (!vectors_left)
7639 pf->num_iwarp_msix = 0;
7640 else if (vectors_left < pf->num_iwarp_msix)
7641 pf->num_iwarp_msix = 1;
7642 v_budget += pf->num_iwarp_msix;
7643 vectors_left -= pf->num_iwarp_msix;
7644 }
7645
1e200e4a
SN		 7646 /* any vectors left over go for VMDq support */
7647 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7648 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7649 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7650
7651 /* if we're short on vectors for what's desired, we limit
7652 * the queues per vmdq. If this is still more than are
7653 * available, the user will need to change the number of
7654 * queues/vectors used by the PF later with the ethtool
7655 * channels command
7656 */
7657 if (vmdq_vecs < vmdq_vecs_wanted)
7658 pf->num_vmdq_qps = 1;
7659 pf->num_vmdq_msix = pf->num_vmdq_qps;
7660
7661 v_budget += vmdq_vecs;
7662 vectors_left -= vmdq_vecs;
7663 }
41c445ff
JB		 7664
7665 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7666 GFP_KERNEL);
7667 if (!pf->msix_entries)
7668 return -ENOMEM;
7669
7670 for (i = 0; i < v_budget; i++)
7671 pf->msix_entries[i].entry = i;
3b444399 7672 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7673
3b444399 7674 if (v_actual != v_budget) {
a34977ba
ASJ		 7675 /* If we have limited resources, we will start with no vectors
7676 * for the special features and then allocate vectors to some
7677 * of these features based on the policy and at the end disable
7678 * the features that did not get any vectors.
7679 */
e3219ce6
ASJ		 7680 iwarp_requested = pf->num_iwarp_msix;
7681 pf->num_iwarp_msix = 0;
38e00438
VD		 7682#ifdef I40E_FCOE
7683 pf->num_fcoe_qps = 0;
7684 pf->num_fcoe_msix = 0;
7685#endif
a34977ba
ASJ		 7686 pf->num_vmdq_msix = 0;
7687 }
7688
3b444399 7689 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7690 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7691 kfree(pf->msix_entries);
7692 pf->msix_entries = NULL;
7693 return -ENODEV;
7694
3b444399 7695 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7696 /* Adjust for minimal MSIX use */
41c445ff
JB		 7697 pf->num_vmdq_vsis = 0;
7698 pf->num_vmdq_qps = 0;
41c445ff
JB		 7699 pf->num_lan_qps = 1;
7700 pf->num_lan_msix = 1;
7701
3b444399
SN		 7702 } else if (v_actual != v_budget) {
7703 int vec;
7704
a34977ba 7705 /* reserve the misc vector */
3b444399 7706 vec = v_actual - 1;
a34977ba 7707
41c445ff
JB		 7708 /* Scale vector usage down */
7709 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7710 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7711 pf->num_vmdq_qps = 1;
7712 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7713
7714 /* partition out the remaining vectors */
7715 switch (vec) {
7716 case 2:
41c445ff
JB		 7717 pf->num_lan_msix = 1;
7718 break;
7719 case 3:
e3219ce6
ASJ		 7720 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7721 pf->num_lan_msix = 1;
7722 pf->num_iwarp_msix = 1;
7723 } else {
7724 pf->num_lan_msix = 2;
7725 }
38e00438
VD		 7726#ifdef I40E_FCOE
7727 /* give one vector to FCoE */
7728 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7729 pf->num_lan_msix = 1;
7730 pf->num_fcoe_msix = 1;
7731 }
38e00438 7732#endif
41c445ff
JB		 7733 break;
7734 default:
e3219ce6
ASJ		 7735 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7736 pf->num_iwarp_msix = min_t(int, (vec / 3),
7737 iwarp_requested);
7738 pf->num_vmdq_vsis = min_t(int, (vec / 3),
7739 I40E_DEFAULT_NUM_VMDQ_VSI);
7740 } else {
7741 pf->num_vmdq_vsis = min_t(int, (vec / 2),
7742 I40E_DEFAULT_NUM_VMDQ_VSI);
7743 }
7744 pf->num_lan_msix = min_t(int,
7745 (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)),
7746 pf->num_lan_msix);
38e00438
VD		 7747#ifdef I40E_FCOE
7748 /* give one vector to FCoE */
7749 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7750 pf->num_fcoe_msix = 1;
7751 vec--;
7752 }
7753#endif
41c445ff
JB		 7754 break;
7755 }
7756 }
7757
a34977ba
ASJ		 7758 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7759 (pf->num_vmdq_msix == 0)) {
7760 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7761 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7762 }
e3219ce6
ASJ		 7763
7764 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
7765 (pf->num_iwarp_msix == 0)) {
7766 dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n");
7767 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
7768 }
38e00438
VD		 7769#ifdef I40E_FCOE
7770
7771 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7772 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7773 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7774 }
7775#endif
3b444399 7776 return v_actual;
41c445ff
JB		 7777}
7778
493fb300 7779/**
90e04070 7780 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7781 * @vsi: the VSI being configured
7782 * @v_idx: index of the vector in the vsi struct
7783 *
7784 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7785 **/
90e04070 7786static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7787{
7788 struct i40e_q_vector *q_vector;
7789
7790 /* allocate q_vector */
7791 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7792 if (!q_vector)
7793 return -ENOMEM;
7794
7795 q_vector->vsi = vsi;
7796 q_vector->v_idx = v_idx;
7797 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7798 if (vsi->netdev)
7799 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7800 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7801
cd0b6fa6
AD		 7802 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7803 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7804
493fb300
AD		 7805 /* tie q_vector and vsi together */
7806 vsi->q_vectors[v_idx] = q_vector;
7807
7808 return 0;
7809}
7810
41c445ff 7811/**
90e04070 7812 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7813 * @vsi: the VSI being configured
7814 *
7815 * We allocate one q_vector per queue interrupt. If allocation fails we
7816 * return -ENOMEM.
7817 **/
90e04070 7818static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7819{
7820 struct i40e_pf *pf = vsi->back;
7821 int v_idx, num_q_vectors;
493fb300 7822 int err;
41c445ff
JB		 7823
7824 /* if not MSIX, give the one vector only to the LAN VSI */
7825 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7826 num_q_vectors = vsi->num_q_vectors;
7827 else if (vsi == pf->vsi[pf->lan_vsi])
7828 num_q_vectors = 1;
7829 else
7830 return -EINVAL;
7831
41c445ff 7832 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7833 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7834 if (err)
7835 goto err_out;
41c445ff
JB		 7836 }
7837
7838 return 0;
493fb300
AD		 7839
7840err_out:
7841 while (v_idx--)
7842 i40e_free_q_vector(vsi, v_idx);
7843
7844 return err;
41c445ff
JB		 7845}
7846
7847/**
7848 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7849 * @pf: board private structure to initialize
7850 **/
c1147280 7851static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7852{
3b444399
SN		 7853 int vectors = 0;
7854 ssize_t size;
41c445ff
JB		 7855
7856 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7857 vectors = i40e_init_msix(pf);
7858 if (vectors < 0) {
60ea5f83 7859 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
e3219ce6 7860 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 7861#ifdef I40E_FCOE
7862 I40E_FLAG_FCOE_ENABLED |
7863#endif
60ea5f83 7864 I40E_FLAG_RSS_ENABLED |
4d9b6043 7865 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7866 I40E_FLAG_SRIOV_ENABLED |
7867 I40E_FLAG_FD_SB_ENABLED |
7868 I40E_FLAG_FD_ATR_ENABLED |
7869 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7870
7871 /* rework the queue expectations without MSIX */
7872 i40e_determine_queue_usage(pf);
7873 }
7874 }
7875
7876 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7877 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7878 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7879 vectors = pci_enable_msi(pf->pdev);
7880 if (vectors < 0) {
7881 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7882 vectors);
41c445ff
JB		 7883 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7884 }
3b444399 7885 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7886 }
7887
958a3e3b 7888 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7889 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7890
3b444399
SN		 7891 /* set up vector assignment tracking */
7892 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7893 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7894 if (!pf->irq_pile) {
7895 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7896 return -ENOMEM;
7897 }
3b444399
SN		 7898 pf->irq_pile->num_entries = vectors;
7899 pf->irq_pile->search_hint = 0;
7900
c1147280 7901 /* track first vector for misc interrupts, ignore return */
3b444399 7902 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7903
7904 return 0;
41c445ff
JB		 7905}
7906
7907/**
7908 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7909 * @pf: board private structure
7910 *
7911 * This sets up the handler for MSIX 0, which is used to manage the
7912 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7913 * when in MSI or Legacy interrupt mode.
7914 **/
7915static int i40e_setup_misc_vector(struct i40e_pf *pf)
7916{
7917 struct i40e_hw *hw = &pf->hw;
7918 int err = 0;
7919
7920 /* Only request the irq if this is the first time through, and
7921 * not when we're rebuilding after a Reset
7922 */
7923 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7924 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7925 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7926 if (err) {
7927 dev_info(&pf->pdev->dev,
77fa28be 7928 "request_irq for %s failed: %d\n",
b294ac70 7929 pf->int_name, err);
41c445ff
JB		 7930 return -EFAULT;
7931 }
7932 }
7933
ab437b5a 7934 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7935
7936 /* associate no queues to the misc vector */
7937 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7938 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7939
7940 i40e_flush(hw);
7941
40d72a50 7942 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 7943
7944 return err;
7945}
7946
7947/**
e25d00b8
ASJ		 7948 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7949 * @vsi: vsi structure
7950 * @seed: RSS hash seed
7951 **/
e69ff813
HZ		 7952static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7953 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7954{
7955 struct i40e_aqc_get_set_rss_key_data rss_key;
7956 struct i40e_pf *pf = vsi->back;
7957 struct i40e_hw *hw = &pf->hw;
7958 bool pf_lut = false;
7959 u8 *rss_lut;
7960 int ret, i;
7961
7962 memset(&rss_key, 0, sizeof(rss_key));
7963 memcpy(&rss_key, seed, sizeof(rss_key));
7964
7965 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7966 if (!rss_lut)
7967 return -ENOMEM;
7968
7969 /* Populate the LUT with max no. of queues in round robin fashion */
7970 for (i = 0; i < vsi->rss_table_size; i++)
7971 rss_lut[i] = i % vsi->rss_size;
7972
7973 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7974 if (ret) {
7975 dev_info(&pf->pdev->dev,
7976 "Cannot set RSS key, err %s aq_err %s\n",
7977 i40e_stat_str(&pf->hw, ret),
7978 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7979 goto config_rss_aq_out;
e25d00b8
ASJ		 7980 }
7981
7982 if (vsi->type == I40E_VSI_MAIN)
7983 pf_lut = true;
7984
7985 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7986 vsi->rss_table_size);
7987 if (ret)
7988 dev_info(&pf->pdev->dev,
7989 "Cannot set RSS lut, err %s aq_err %s\n",
7990 i40e_stat_str(&pf->hw, ret),
7991 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7992
126b63d9
AS		 7993config_rss_aq_out:
7994 kfree(rss_lut);
e25d00b8
ASJ		 7995 return ret;
7996}
7997
7998/**
7999 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
8000 * @vsi: VSI structure
8001 **/
8002static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
8003{
8004 u8 seed[I40E_HKEY_ARRAY_SIZE];
8005 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 8006 u8 *lut;
8007 int ret;
8008
8009 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
8010 return 0;
8011
8012 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8013 if (!lut)
8014 return -ENOMEM;
e25d00b8 8015
e69ff813 8016 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 8017 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 8018 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 8019 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
8020 kfree(lut);
e25d00b8 8021
e69ff813 8022 return ret;
e25d00b8
ASJ		 8023}
8024
95a73780
ASJ		 8025/**
8026 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
8027 * @vsi: Pointer to vsi structure
8028 * @seed: Buffter to store the hash keys
8029 * @lut: Buffer to store the lookup table entries
8030 * @lut_size: Size of buffer to store the lookup table entries
8031 *
8032 * Return 0 on success, negative on failure
8033 */
8034static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
8035 u8 *lut, u16 lut_size)
8036{
8037 struct i40e_pf *pf = vsi->back;
8038 struct i40e_hw *hw = &pf->hw;
8039 int ret = 0;
8040
8041 if (seed) {
8042 ret = i40e_aq_get_rss_key(hw, vsi->id,
8043 (struct i40e_aqc_get_set_rss_key_data *)seed);
8044 if (ret) {
8045 dev_info(&pf->pdev->dev,
8046 "Cannot get RSS key, err %s aq_err %s\n",
8047 i40e_stat_str(&pf->hw, ret),
8048 i40e_aq_str(&pf->hw,
8049 pf->hw.aq.asq_last_status));
8050 return ret;
8051 }
8052 }
8053
8054 if (lut) {
8055 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
8056
8057 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
8058 if (ret) {
8059 dev_info(&pf->pdev->dev,
8060 "Cannot get RSS lut, err %s aq_err %s\n",
8061 i40e_stat_str(&pf->hw, ret),
8062 i40e_aq_str(&pf->hw,
8063 pf->hw.aq.asq_last_status));
8064 return ret;
8065 }
8066 }
8067
8068 return ret;
8069}
8070
e25d00b8 8071/**
043dd650 8072 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 8073 * @vsi: Pointer to vsi structure
e25d00b8 8074 * @seed: RSS hash seed
e69ff813
HZ		 8075 * @lut: Lookup table
8076 * @lut_size: Lookup table size
8077 *
8078 * Returns 0 on success, negative on failure
41c445ff 8079 **/
e69ff813
HZ		 8080static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
8081 const u8 *lut, u16 lut_size)
41c445ff 8082{
e69ff813 8083 struct i40e_pf *pf = vsi->back;
4617e8c0 8084 struct i40e_hw *hw = &pf->hw;
e69ff813 8085 u8 i;
41c445ff 8086
e25d00b8 8087 /* Fill out hash function seed */
e69ff813
HZ		 8088 if (seed) {
8089 u32 *seed_dw = (u32 *)seed;
8090
8091 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
272cdaf2 8092 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
e69ff813
HZ		 8093 }
8094
8095 if (lut) {
8096 u32 *lut_dw = (u32 *)lut;
8097
8098 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8099 return -EINVAL;
8100
8101 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8102 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
e25d00b8
ASJ		 8103 }
8104 i40e_flush(hw);
8105
8106 return 0;
8107}
8108
043dd650
HZ		 8109/**
8110 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
8111 * @vsi: Pointer to VSI structure
8112 * @seed: Buffer to store the keys
8113 * @lut: Buffer to store the lookup table entries
8114 * @lut_size: Size of buffer to store the lookup table entries
8115 *
8116 * Returns 0 on success, negative on failure
8117 */
8118static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
8119 u8 *lut, u16 lut_size)
8120{
8121 struct i40e_pf *pf = vsi->back;
8122 struct i40e_hw *hw = &pf->hw;
8123 u16 i;
8124
8125 if (seed) {
8126 u32 *seed_dw = (u32 *)seed;
8127
8128 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
272cdaf2 8129 seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
043dd650
HZ		 8130 }
8131 if (lut) {
8132 u32 *lut_dw = (u32 *)lut;
8133
8134 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8135 return -EINVAL;
8136 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8137 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
8138 }
8139
8140 return 0;
8141}
8142
8143/**
8144 * i40e_config_rss - Configure RSS keys and lut
8145 * @vsi: Pointer to VSI structure
8146 * @seed: RSS hash seed
8147 * @lut: Lookup table
8148 * @lut_size: Lookup table size
8149 *
8150 * Returns 0 on success, negative on failure
8151 */
8152int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8153{
8154 struct i40e_pf *pf = vsi->back;
8155
8156 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8157 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8158 else
8159 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8160}
8161
8162/**
8163 * i40e_get_rss - Get RSS keys and lut
8164 * @vsi: Pointer to VSI structure
8165 * @seed: Buffer to store the keys
8166 * @lut: Buffer to store the lookup table entries
8167 * lut_size: Size of buffer to store the lookup table entries
8168 *
8169 * Returns 0 on success, negative on failure
8170 */
8171int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8172{
95a73780
ASJ		 8173 struct i40e_pf *pf = vsi->back;
8174
8175 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8176 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
8177 else
8178 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
043dd650
HZ		 8179}
8180
e69ff813
HZ		 8181/**
8182 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8183 * @pf: Pointer to board private structure
8184 * @lut: Lookup table
8185 * @rss_table_size: Lookup table size
8186 * @rss_size: Range of queue number for hashing
8187 */
8188static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8189 u16 rss_table_size, u16 rss_size)
8190{
8191 u16 i;
8192
8193 for (i = 0; i < rss_table_size; i++)
8194 lut[i] = i % rss_size;
8195}
8196
e25d00b8 8197/**
043dd650 8198 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8199 * @pf: board private structure
8200 **/
043dd650 8201static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8202{
8203 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8204 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8205 u8 *lut;
e25d00b8
ASJ		 8206 struct i40e_hw *hw = &pf->hw;
8207 u32 reg_val;
8208 u64 hena;
e69ff813 8209 int ret;
e25d00b8 8210
41c445ff 8211 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
272cdaf2
SN		 8212 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
8213 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8214 hena |= i40e_pf_get_default_rss_hena(pf);
8215
272cdaf2
SN		 8216 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
8217 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
41c445ff 8218
e25d00b8 8219 /* Determine the RSS table size based on the hardware capabilities */
272cdaf2 8220 reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8221 reg_val = (pf->rss_table_size == 512) ?
8222 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8223 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
272cdaf2 8224 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
e157ea30 8225
28c5869f
HZ		 8226 /* Determine the RSS size of the VSI */
8227 if (!vsi->rss_size)
acd65448
HZ		 8228 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8229 vsi->num_queue_pairs);
28c5869f 8230
e69ff813
HZ		 8231 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8232 if (!lut)
8233 return -ENOMEM;
8234
28c5869f
HZ		 8235 /* Use user configured lut if there is one, otherwise use default */
8236 if (vsi->rss_lut_user)
8237 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8238 else
8239 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8240
28c5869f
HZ		 8241 /* Use user configured hash key if there is one, otherwise
8242 * use default.
8243 */
8244 if (vsi->rss_hkey_user)
8245 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8246 else
8247 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8248 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8249 kfree(lut);
8250
8251 return ret;
41c445ff
JB		 8252}
8253
f8ff1464
ASJ		 8254/**
8255 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8256 * @pf: board private structure
8257 * @queue_count: the requested queue count for rss.
8258 *
8259 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8260 * count which may be different from the requested queue count.
8261 **/
8262int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8263{
9a3bd2f1
ASJ		 8264 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8265 int new_rss_size;
8266
f8ff1464
ASJ		 8267 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8268 return 0;
8269
9a3bd2f1 8270 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8271
9a3bd2f1
ASJ		 8272 if (queue_count != vsi->num_queue_pairs) {
8273 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8274 i40e_prep_for_reset(pf);
8275
acd65448 8276 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8277
8278 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8279
8280 /* Discard the user configured hash keys and lut, if less
8281 * queues are enabled.
8282 */
8283 if (queue_count < vsi->rss_size) {
8284 i40e_clear_rss_config_user(vsi);
8285 dev_dbg(&pf->pdev->dev,
8286 "discard user configured hash keys and lut\n");
8287 }
8288
8289 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8290 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8291 vsi->num_queue_pairs);
28c5869f 8292
043dd650 8293 i40e_pf_config_rss(pf);
f8ff1464 8294 }
e36b0b11
HZ		 8295 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8296 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8297 return pf->alloc_rss_size;
f8ff1464
ASJ		 8298}
8299
f4492db1
GR		 8300/**
8301 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8302 * @pf: board private structure
8303 **/
8304i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8305{
8306 i40e_status status;
8307 bool min_valid, max_valid;
8308 u32 max_bw, min_bw;
8309
8310 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8311 &min_valid, &max_valid);
8312
8313 if (!status) {
8314 if (min_valid)
8315 pf->npar_min_bw = min_bw;
8316 if (max_valid)
8317 pf->npar_max_bw = max_bw;
8318 }
8319
8320 return status;
8321}
8322
8323/**
8324 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8325 * @pf: board private structure
8326 **/
8327i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8328{
8329 struct i40e_aqc_configure_partition_bw_data bw_data;
8330 i40e_status status;
8331
b40c82e6 8332 /* Set the valid bit for this PF */
41a1d04b 8333 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8334 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8335 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8336
8337 /* Set the new bandwidths */
8338 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8339
8340 return status;
8341}
8342
8343/**
8344 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8345 * @pf: board private structure
8346 **/
8347i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8348{
8349 /* Commit temporary BW setting to permanent NVM image */
8350 enum i40e_admin_queue_err last_aq_status;
8351 i40e_status ret;
8352 u16 nvm_word;
8353
8354 if (pf->hw.partition_id != 1) {
8355 dev_info(&pf->pdev->dev,
8356 "Commit BW only works on partition 1! This is partition %d",
8357 pf->hw.partition_id);
8358 ret = I40E_NOT_SUPPORTED;
8359 goto bw_commit_out;
8360 }
8361
8362 /* Acquire NVM for read access */
8363 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8364 last_aq_status = pf->hw.aq.asq_last_status;
8365 if (ret) {
8366 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8367 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8368 i40e_stat_str(&pf->hw, ret),
8369 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8370 goto bw_commit_out;
8371 }
8372
8373 /* Read word 0x10 of NVM - SW compatibility word 1 */
8374 ret = i40e_aq_read_nvm(&pf->hw,
8375 I40E_SR_NVM_CONTROL_WORD,
8376 0x10, sizeof(nvm_word), &nvm_word,
8377 false, NULL);
8378 /* Save off last admin queue command status before releasing
8379 * the NVM
8380 */
8381 last_aq_status = pf->hw.aq.asq_last_status;
8382 i40e_release_nvm(&pf->hw);
8383 if (ret) {
f1c7e72e
SN		 8384 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8385 i40e_stat_str(&pf->hw, ret),
8386 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8387 goto bw_commit_out;
8388 }
8389
8390 /* Wait a bit for NVM release to complete */
8391 msleep(50);
8392
8393 /* Acquire NVM for write access */
8394 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8395 last_aq_status = pf->hw.aq.asq_last_status;
8396 if (ret) {
8397 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8398 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8399 i40e_stat_str(&pf->hw, ret),
8400 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8401 goto bw_commit_out;
8402 }
8403 /* Write it back out unchanged to initiate update NVM,
8404 * which will force a write of the shadow (alt) RAM to
8405 * the NVM - thus storing the bandwidth values permanently.
8406 */
8407 ret = i40e_aq_update_nvm(&pf->hw,
8408 I40E_SR_NVM_CONTROL_WORD,
8409 0x10, sizeof(nvm_word),
8410 &nvm_word, true, NULL);
8411 /* Save off last admin queue command status before releasing
8412 * the NVM
8413 */
8414 last_aq_status = pf->hw.aq.asq_last_status;
8415 i40e_release_nvm(&pf->hw);
8416 if (ret)
8417 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8418 "BW settings NOT SAVED, err %s aq_err %s\n",
8419 i40e_stat_str(&pf->hw, ret),
8420 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8421bw_commit_out:
8422
8423 return ret;
8424}
8425
41c445ff
JB		 8426/**
8427 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8428 * @pf: board private structure to initialize
8429 *
8430 * i40e_sw_init initializes the Adapter private data structure.
8431 * Fields are initialized based on PCI device information and
8432 * OS network device settings (MTU size).
8433 **/
8434static int i40e_sw_init(struct i40e_pf *pf)
8435{
8436 int err = 0;
8437 int size;
8438
8439 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8440 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
8441 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8442 if (I40E_DEBUG_USER & debug)
8443 pf->hw.debug_mask = debug;
8444 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8445 I40E_DEFAULT_MSG_ENABLE);
8446 }
8447
8448 /* Set default capability flags */
8449 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8450 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 8451 I40E_FLAG_MSIX_ENABLED;
8452
8453 if (iommu_present(&pci_bus_type))
8454 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8455 else
8456 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8457
ca99eb99
MW		 8458 /* Set default ITR */
8459 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8460 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8461
7134f9ce
JB		 8462 /* Depending on PF configurations, it is possible that the RSS
8463 * maximum might end up larger than the available queues
8464 */
41a1d04b 8465 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8466 pf->alloc_rss_size = 1;
5db4cb59 8467 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8468 pf->rss_size_max = min_t(int, pf->rss_size_max,
8469 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8470 if (pf->hw.func_caps.rss) {
8471 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8472 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8473 num_online_cpus());
41c445ff
JB		 8474 }
8475
2050bc65 8476 /* MFP mode enabled */
c78b953e 8477 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8478 pf->flags |= I40E_FLAG_MFP_ENABLED;
8479 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8480 if (i40e_get_npar_bw_setting(pf))
8481 dev_warn(&pf->pdev->dev,
8482 "Could not get NPAR bw settings\n");
8483 else
8484 dev_info(&pf->pdev->dev,
8485 "Min BW = %8.8x, Max BW = %8.8x\n",
8486 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8487 }
8488
cbf61325
ASJ		 8489 /* FW/NVM is not yet fixed in this regard */
8490 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8491 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8492 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8493 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8494 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8495 pf->hw.num_partitions > 1)
cbf61325 8496 dev_info(&pf->pdev->dev,
0b67584f 8497 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8498 else
8499 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8500 pf->fdir_pf_filter_count =
8501 pf->hw.func_caps.fd_filters_guaranteed;
8502 pf->hw.fdir_shared_filter_count =
8503 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8504 }
8505
f1bbad33 8506 if (i40e_is_mac_710(&pf->hw) &&
8eed76fa 8507 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
f1bbad33 8508 (pf->hw.aq.fw_maj_ver < 4))) {
8eed76fa 8509 pf->flags |= I40E_FLAG_RESTART_AUTONEG;
f1bbad33
NP		 8510 /* No DCB support for FW < v4.33 */
8511 pf->flags |= I40E_FLAG_NO_DCB_SUPPORT;
8512 }
8513
8514 /* Disable FW LLDP if FW < v4.3 */
8515 if (i40e_is_mac_710(&pf->hw) &&
8516 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
8517 (pf->hw.aq.fw_maj_ver < 4)))
8518 pf->flags |= I40E_FLAG_STOP_FW_LLDP;
8519
8520 /* Use the FW Set LLDP MIB API if FW > v4.40 */
8521 if (i40e_is_mac_710(&pf->hw) &&
8522 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
8523 (pf->hw.aq.fw_maj_ver >= 5)))
8524 pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB;
8eed76fa 8525
41c445ff 8526 if (pf->hw.func_caps.vmdq) {
41c445ff 8527 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8528 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8529 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8530 }
8531
e3219ce6
ASJ		 8532 if (pf->hw.func_caps.iwarp) {
8533 pf->flags |= I40E_FLAG_IWARP_ENABLED;
8534 /* IWARP needs one extra vector for CQP just like MISC.*/
8535 pf->num_iwarp_msix = (int)num_online_cpus() + 1;
8536 }
8537
38e00438 8538#ifdef I40E_FCOE
21364bcf 8539 i40e_init_pf_fcoe(pf);
38e00438
VD		 8540
8541#endif /* I40E_FCOE */
41c445ff 8542#ifdef CONFIG_PCI_IOV
ba252f13 8543 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8544 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8545 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8546 pf->num_req_vfs = min_t(int,
8547 pf->hw.func_caps.num_vfs,
8548 I40E_MAX_VF_COUNT);
8549 }
8550#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8551 if (pf->hw.mac.type == I40E_MAC_X722) {
8552 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8553 I40E_FLAG_128_QP_RSS_CAPABLE |
8554 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8555 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8556 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024 8557 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
f8db54cc 8558 I40E_FLAG_100M_SGMII_CAPABLE |
f1bbad33 8559 I40E_FLAG_USE_SET_LLDP_MIB |
6a899024 8560 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
a340c789
AS		 8561 } else if ((pf->hw.aq.api_maj_ver > 1) ||
8562 ((pf->hw.aq.api_maj_ver == 1) &&
8563 (pf->hw.aq.api_min_ver > 4))) {
8564 /* Supported in FW API version higher than 1.4 */
8565 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
72b74869
ASJ		 8566 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
8567 } else {
8568 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
d502ce01 8569 }
a340c789 8570
41c445ff
JB		 8571 pf->eeprom_version = 0xDEAD;
8572 pf->lan_veb = I40E_NO_VEB;
8573 pf->lan_vsi = I40E_NO_VSI;
8574
d1a8d275
ASJ		 8575 /* By default FW has this off for performance reasons */
8576 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8577
41c445ff
JB		 8578 /* set up queue assignment tracking */
8579 size = sizeof(struct i40e_lump_tracking)
8580 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8581 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8582 if (!pf->qp_pile) {
8583 err = -ENOMEM;
8584 goto sw_init_done;
8585 }
8586 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8587 pf->qp_pile->search_hint = 0;
8588
327fe04b
ASJ		 8589 pf->tx_timeout_recovery_level = 1;
8590
41c445ff
JB		 8591 mutex_init(&pf->switch_mutex);
8592
c668a12c
GR		 8593 /* If NPAR is enabled nudge the Tx scheduler */
8594 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8595 i40e_set_npar_bw_setting(pf);
8596
41c445ff
JB		 8597sw_init_done:
8598 return err;
8599}
8600
7c3c288b
ASJ		 8601/**
8602 * i40e_set_ntuple - set the ntuple feature flag and take action
8603 * @pf: board private structure to initialize
8604 * @features: the feature set that the stack is suggesting
8605 *
8606 * returns a bool to indicate if reset needs to happen
8607 **/
8608bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8609{
8610 bool need_reset = false;
8611
8612 /* Check if Flow Director n-tuple support was enabled or disabled. If
8613 * the state changed, we need to reset.
8614 */
8615 if (features & NETIF_F_NTUPLE) {
8616 /* Enable filters and mark for reset */
8617 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8618 need_reset = true;
8619 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8620 } else {
8621 /* turn off filters, mark for reset and clear SW filter list */
8622 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8623 need_reset = true;
8624 i40e_fdir_filter_exit(pf);
8625 }
8626 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8627 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8628 /* reset fd counters */
8629 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8630 pf->fdir_pf_active_filters = 0;
8631 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8632 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8633 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8634 /* if ATR was auto disabled it can be re-enabled. */
8635 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8636 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8637 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8638 }
8639 return need_reset;
8640}
8641
41c445ff
JB		 8642/**
8643 * i40e_set_features - set the netdev feature flags
8644 * @netdev: ptr to the netdev being adjusted
8645 * @features: the feature set that the stack is suggesting
8646 **/
8647static int i40e_set_features(struct net_device *netdev,
8648 netdev_features_t features)
8649{
8650 struct i40e_netdev_priv *np = netdev_priv(netdev);
8651 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8652 struct i40e_pf *pf = vsi->back;
8653 bool need_reset;
41c445ff
JB		 8654
8655 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8656 i40e_vlan_stripping_enable(vsi);
8657 else
8658 i40e_vlan_stripping_disable(vsi);
8659
7c3c288b
ASJ		 8660 need_reset = i40e_set_ntuple(pf, features);
8661
8662 if (need_reset)
41a1d04b 8663 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8664
41c445ff
JB		 8665 return 0;
8666}
8667
6a899024 8668#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9 8669/**
6a899024 8670 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8671 * @pf: board private structure
8672 * @port: The UDP port to look up
8673 *
8674 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8675 **/
6a899024 8676static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8677{
8678 u8 i;
8679
8680 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8681 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8682 return i;
8683 }
8684
8685 return i;
8686}
8687
6a899024 8688#endif
5cae7615
ED		 8689
8690#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8691/**
8692 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8693 * @netdev: This physical port's netdev
8694 * @sa_family: Socket Family that VXLAN is notifying us about
8695 * @port: New UDP port number that VXLAN started listening to
8696 **/
8697static void i40e_add_vxlan_port(struct net_device *netdev,
8698 sa_family_t sa_family, __be16 port)
8699{
8700 struct i40e_netdev_priv *np = netdev_priv(netdev);
8701 struct i40e_vsi *vsi = np->vsi;
8702 struct i40e_pf *pf = vsi->back;
8703 u8 next_idx;
8704 u8 idx;
8705
6a899024 8706 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8707
8708 /* Check if port already exists */
8709 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8710 netdev_info(netdev, "vxlan port %d already offloaded\n",
8711 ntohs(port));
a1c9a9d9
JK		 8712 return;
8713 }
8714
8715 /* Now check if there is space to add the new port */
6a899024 8716 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8717
8718 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8719 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8720 ntohs(port));
8721 return;
8722 }
8723
8724 /* New port: add it and mark its index in the bitmap */
6a899024
SA		 8725 pf->udp_ports[next_idx].index = port;
8726 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8727 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8728 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 8729}
8730
8731/**
8732 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8733 * @netdev: This physical port's netdev
8734 * @sa_family: Socket Family that VXLAN is notifying us about
8735 * @port: UDP port number that VXLAN stopped listening to
8736 **/
8737static void i40e_del_vxlan_port(struct net_device *netdev,
8738 sa_family_t sa_family, __be16 port)
8739{
8740 struct i40e_netdev_priv *np = netdev_priv(netdev);
8741 struct i40e_vsi *vsi = np->vsi;
8742 struct i40e_pf *pf = vsi->back;
8743 u8 idx;
8744
6a899024 8745 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8746
8747 /* Check if port already exists */
8748 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8749 /* if port exists, set it to 0 (mark for deletion)
8750 * and make it pending
8751 */
6a899024
SA		 8752 pf->udp_ports[idx].index = 0;
8753 pf->pending_udp_bitmap |= BIT_ULL(idx);
8754 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9 8755 } else {
c22c06c8 8756 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8757 ntohs(port));
8758 }
6a899024 8759}
5cae7615 8760#endif
6a899024 8761
5cae7615 8762#if IS_ENABLED(CONFIG_GENEVE)
6a899024
SA		 8763/**
8764 * i40e_add_geneve_port - Get notifications about GENEVE ports that come up
8765 * @netdev: This physical port's netdev
8766 * @sa_family: Socket Family that GENEVE is notifying us about
8767 * @port: New UDP port number that GENEVE started listening to
8768 **/
8769static void i40e_add_geneve_port(struct net_device *netdev,
8770 sa_family_t sa_family, __be16 port)
8771{
6a899024
SA		 8772 struct i40e_netdev_priv *np = netdev_priv(netdev);
8773 struct i40e_vsi *vsi = np->vsi;
8774 struct i40e_pf *pf = vsi->back;
8775 u8 next_idx;
8776 u8 idx;
8777
a340c789
AS		 8778 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8779 return;
8780
6a899024
SA		 8781 idx = i40e_get_udp_port_idx(pf, port);
8782
8783 /* Check if port already exists */
8784 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8785 netdev_info(netdev, "udp port %d already offloaded\n",
8786 ntohs(port));
8787 return;
8788 }
8789
8790 /* Now check if there is space to add the new port */
8791 next_idx = i40e_get_udp_port_idx(pf, 0);
8792
8793 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8794 netdev_info(netdev, "maximum number of UDP ports reached, not adding port %d\n",
8795 ntohs(port));
8796 return;
8797 }
8798
8799 /* New port: add it and mark its index in the bitmap */
8800 pf->udp_ports[next_idx].index = port;
8801 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8802 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8803 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8804
8805 dev_info(&pf->pdev->dev, "adding geneve port %d\n", ntohs(port));
a1c9a9d9
JK		 8806}
8807
6a899024
SA		 8808/**
8809 * i40e_del_geneve_port - Get notifications about GENEVE ports that go away
8810 * @netdev: This physical port's netdev
8811 * @sa_family: Socket Family that GENEVE is notifying us about
8812 * @port: UDP port number that GENEVE stopped listening to
8813 **/
8814static void i40e_del_geneve_port(struct net_device *netdev,
8815 sa_family_t sa_family, __be16 port)
8816{
6a899024
SA		 8817 struct i40e_netdev_priv *np = netdev_priv(netdev);
8818 struct i40e_vsi *vsi = np->vsi;
8819 struct i40e_pf *pf = vsi->back;
8820 u8 idx;
8821
a340c789
AS		 8822 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8823 return;
8824
6a899024
SA		 8825 idx = i40e_get_udp_port_idx(pf, port);
8826
8827 /* Check if port already exists */
8828 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8829 /* if port exists, set it to 0 (mark for deletion)
8830 * and make it pending
8831 */
8832 pf->udp_ports[idx].index = 0;
8833 pf->pending_udp_bitmap |= BIT_ULL(idx);
8834 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8835
8836 dev_info(&pf->pdev->dev, "deleting geneve port %d\n",
8837 ntohs(port));
8838 } else {
8839 netdev_warn(netdev, "geneve port %d was not found, not deleting\n",
8840 ntohs(port));
8841 }
6a899024 8842}
5cae7615 8843#endif
6a899024 8844
1f224ad2 8845static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8846 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8847{
8848 struct i40e_netdev_priv *np = netdev_priv(netdev);
8849 struct i40e_pf *pf = np->vsi->back;
8850 struct i40e_hw *hw = &pf->hw;
8851
8852 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8853 return -EOPNOTSUPP;
8854
8855 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8856 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8857
8858 return 0;
8859}
8860
2f90ade6
JB		 8861/**
8862 * i40e_ndo_fdb_add - add an entry to the hardware database
8863 * @ndm: the input from the stack
8864 * @tb: pointer to array of nladdr (unused)
8865 * @dev: the net device pointer
8866 * @addr: the MAC address entry being added
8867 * @flags: instructions from stack about fdb operation
8868 */
4ba0dea5
GR		 8869static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8870 struct net_device *dev,
f6f6424b 8871 const unsigned char *addr, u16 vid,
4ba0dea5 8872 u16 flags)
4ba0dea5
GR		 8873{
8874 struct i40e_netdev_priv *np = netdev_priv(dev);
8875 struct i40e_pf *pf = np->vsi->back;
8876 int err = 0;
8877
8878 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8879 return -EOPNOTSUPP;
8880
65891fea
OG		 8881 if (vid) {
8882 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8883 return -EINVAL;
8884 }
8885
4ba0dea5
GR		 8886 /* Hardware does not support aging addresses so if a
8887 * ndm_state is given only allow permanent addresses
8888 */
8889 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8890 netdev_info(dev, "FDB only supports static addresses\n");
8891 return -EINVAL;
8892 }
8893
8894 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8895 err = dev_uc_add_excl(dev, addr);
8896 else if (is_multicast_ether_addr(addr))
8897 err = dev_mc_add_excl(dev, addr);
8898 else
8899 err = -EINVAL;
8900
8901 /* Only return duplicate errors if NLM_F_EXCL is set */
8902 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8903 err = 0;
8904
8905 return err;
8906}
8907
51616018
NP		 8908/**
8909 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8910 * @dev: the netdev being configured
8911 * @nlh: RTNL message
8912 *
8913 * Inserts a new hardware bridge if not already created and
8914 * enables the bridging mode requested (VEB or VEPA). If the
8915 * hardware bridge has already been inserted and the request
8916 * is to change the mode then that requires a PF reset to
8917 * allow rebuild of the components with required hardware
8918 * bridge mode enabled.
8919 **/
8920static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8921 struct nlmsghdr *nlh,
8922 u16 flags)
51616018
NP		 8923{
8924 struct i40e_netdev_priv *np = netdev_priv(dev);
8925 struct i40e_vsi *vsi = np->vsi;
8926 struct i40e_pf *pf = vsi->back;
8927 struct i40e_veb *veb = NULL;
8928 struct nlattr *attr, *br_spec;
8929 int i, rem;
8930
8931 /* Only for PF VSI for now */
8932 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8933 return -EOPNOTSUPP;
8934
8935 /* Find the HW bridge for PF VSI */
8936 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8937 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8938 veb = pf->veb[i];
8939 }
8940
8941 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8942
8943 nla_for_each_nested(attr, br_spec, rem) {
8944 __u16 mode;
8945
8946 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8947 continue;
8948
8949 mode = nla_get_u16(attr);
8950 if ((mode != BRIDGE_MODE_VEPA) &&
8951 (mode != BRIDGE_MODE_VEB))
8952 return -EINVAL;
8953
8954 /* Insert a new HW bridge */
8955 if (!veb) {
8956 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8957 vsi->tc_config.enabled_tc);
8958 if (veb) {
8959 veb->bridge_mode = mode;
8960 i40e_config_bridge_mode(veb);
8961 } else {
8962 /* No Bridge HW offload available */
8963 return -ENOENT;
8964 }
8965 break;
8966 } else if (mode != veb->bridge_mode) {
8967 /* Existing HW bridge but different mode needs reset */
8968 veb->bridge_mode = mode;
fc60861e
ASJ		 8969 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8970 if (mode == BRIDGE_MODE_VEB)
8971 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8972 else
8973 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8974 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8975 break;
8976 }
8977 }
8978
8979 return 0;
8980}
8981
8982/**
8983 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8984 * @skb: skb buff
8985 * @pid: process id
8986 * @seq: RTNL message seq #
8987 * @dev: the netdev being configured
8988 * @filter_mask: unused
d4b2f9fe 8989 * @nlflags: netlink flags passed in
51616018
NP		 8990 *
8991 * Return the mode in which the hardware bridge is operating in
8992 * i.e VEB or VEPA.
8993 **/
51616018
NP		 8994static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8995 struct net_device *dev,
9f4ffc44
CW		 8996 u32 __always_unused filter_mask,
8997 int nlflags)
51616018
NP		 8998{
8999 struct i40e_netdev_priv *np = netdev_priv(dev);
9000 struct i40e_vsi *vsi = np->vsi;
9001 struct i40e_pf *pf = vsi->back;
9002 struct i40e_veb *veb = NULL;
9003 int i;
9004
9005 /* Only for PF VSI for now */
9006 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
9007 return -EOPNOTSUPP;
9008
9009 /* Find the HW bridge for the PF VSI */
9010 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9011 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9012 veb = pf->veb[i];
9013 }
9014
9015 if (!veb)
9016 return 0;
9017
46c264da 9018 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 9019 nlflags, 0, 0, filter_mask, NULL);
51616018 9020}
51616018 9021
6a899024
SA		 9022/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
9023 * inner mac plus all inner ethertypes.
9024 */
9025#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 9026/**
9027 * i40e_features_check - Validate encapsulated packet conforms to limits
9028 * @skb: skb buff
2bc11c63 9029 * @dev: This physical port's netdev
f44a75e2
JS		 9030 * @features: Offload features that the stack believes apply
9031 **/
9032static netdev_features_t i40e_features_check(struct sk_buff *skb,
9033 struct net_device *dev,
9034 netdev_features_t features)
9035{
9036 if (skb->encapsulation &&
6a899024 9037 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 9038 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 9039 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 9040
9041 return features;
9042}
9043
37a2973a 9044static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 9045 .ndo_open = i40e_open,
9046 .ndo_stop = i40e_close,
9047 .ndo_start_xmit = i40e_lan_xmit_frame,
9048 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
9049 .ndo_set_rx_mode = i40e_set_rx_mode,
9050 .ndo_validate_addr = eth_validate_addr,
9051 .ndo_set_mac_address = i40e_set_mac,
9052 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 9053 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 9054 .ndo_tx_timeout = i40e_tx_timeout,
9055 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
9056 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
9057#ifdef CONFIG_NET_POLL_CONTROLLER
9058 .ndo_poll_controller = i40e_netpoll,
9059#endif
e4c6734e 9060 .ndo_setup_tc = __i40e_setup_tc,
38e00438
VD		 9061#ifdef I40E_FCOE
9062 .ndo_fcoe_enable = i40e_fcoe_enable,
9063 .ndo_fcoe_disable = i40e_fcoe_disable,
9064#endif
41c445ff
JB		 9065 .ndo_set_features = i40e_set_features,
9066 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
9067 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 9068 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 9069 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 9070 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 9071 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
6a899024 9072#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 9073 .ndo_add_vxlan_port = i40e_add_vxlan_port,
9074 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6a899024
SA		 9075#endif
9076#if IS_ENABLED(CONFIG_GENEVE)
9077 .ndo_add_geneve_port = i40e_add_geneve_port,
9078 .ndo_del_geneve_port = i40e_del_geneve_port,
a1c9a9d9 9079#endif
1f224ad2 9080 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 9081 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 9082 .ndo_features_check = i40e_features_check,
51616018
NP		 9083 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
9084 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 9085};
9086
9087/**
9088 * i40e_config_netdev - Setup the netdev flags
9089 * @vsi: the VSI being configured
9090 *
9091 * Returns 0 on success, negative value on failure
9092 **/
9093static int i40e_config_netdev(struct i40e_vsi *vsi)
9094{
1a10370a 9095 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 9096 struct i40e_pf *pf = vsi->back;
9097 struct i40e_hw *hw = &pf->hw;
9098 struct i40e_netdev_priv *np;
9099 struct net_device *netdev;
9100 u8 mac_addr[ETH_ALEN];
9101 int etherdev_size;
9102
9103 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 9104 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 9105 if (!netdev)
9106 return -ENOMEM;
9107
9108 vsi->netdev = netdev;
9109 np = netdev_priv(netdev);
9110 np->vsi = vsi;
9111
bc5d252b
AD		 9112 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
9113 NETIF_F_IPV6_CSUM |
9114 NETIF_F_TSO |
9115 NETIF_F_TSO6 |
9116 NETIF_F_TSO_ECN |
9117 NETIF_F_GSO_GRE |
9118 NETIF_F_GSO_UDP_TUNNEL |
9119 NETIF_F_GSO_UDP_TUNNEL_CSUM |
5afdaaa0 9120 0;
41c445ff
JB		 9121
9122 netdev->features = NETIF_F_SG |
9123 NETIF_F_IP_CSUM |
53692b1d 9124 NETIF_F_SCTP_CRC |
41c445ff
JB		 9125 NETIF_F_HIGHDMA |
9126 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 9127 NETIF_F_GSO_GRE |
41c445ff
JB		 9128 NETIF_F_HW_VLAN_CTAG_TX |
9129 NETIF_F_HW_VLAN_CTAG_RX |
9130 NETIF_F_HW_VLAN_CTAG_FILTER |
9131 NETIF_F_IPV6_CSUM |
9132 NETIF_F_TSO |
059dab69 9133 NETIF_F_TSO_ECN |
41c445ff
JB		 9134 NETIF_F_TSO6 |
9135 NETIF_F_RXCSUM |
9136 NETIF_F_RXHASH |
9137 0;
9138
2e86a0b6
ASJ		 9139 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
9140 netdev->features |= NETIF_F_NTUPLE;
bc5d252b
AD		 9141 if (pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
9142 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2e86a0b6 9143
41c445ff
JB		 9144 /* copy netdev features into list of user selectable features */
9145 netdev->hw_features |= netdev->features;
9146
9147 if (vsi->type == I40E_VSI_MAIN) {
9148 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 9149 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 9150 /* The following steps are necessary to prevent reception
9151 * of tagged packets - some older NVM configurations load a
9152 * default a MAC-VLAN filter that accepts any tagged packet
9153 * which must be replaced by a normal filter.
8c27d42e 9154 */
21659035
KP		 9155 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
9156 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 9157 i40e_add_filter(vsi, mac_addr,
9158 I40E_VLAN_ANY, false, true);
21659035
KP		 9159 spin_unlock_bh(&vsi->mac_filter_list_lock);
9160 }
3845ccea
ASJ		 9161 } else if ((pf->hw.aq.api_maj_ver > 1) ||
9162 ((pf->hw.aq.api_maj_ver == 1) &&
9163 (pf->hw.aq.api_min_ver > 4))) {
9164 /* Supported in FW API version higher than 1.4 */
9165 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
9166 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
41c445ff
JB		 9167 } else {
9168 /* relate the VSI_VMDQ name to the VSI_MAIN name */
9169 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
9170 pf->vsi[pf->lan_vsi]->netdev->name);
9171 random_ether_addr(mac_addr);
21659035
KP		 9172
9173 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 9174 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 9175 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9176 }
21659035
KP		 9177
9178 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 9179 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 9180 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9181
9a173901
GR		 9182 ether_addr_copy(netdev->dev_addr, mac_addr);
9183 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 9184 /* vlan gets same features (except vlan offload)
9185 * after any tweaks for specific VSI types
9186 */
9187 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
9188 NETIF_F_HW_VLAN_CTAG_RX |
9189 NETIF_F_HW_VLAN_CTAG_FILTER);
9190 netdev->priv_flags |= IFF_UNICAST_FLT;
9191 netdev->priv_flags |= IFF_SUPP_NOFCS;
9192 /* Setup netdev TC information */
9193 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9194
9195 netdev->netdev_ops = &i40e_netdev_ops;
9196 netdev->watchdog_timeo = 5 * HZ;
9197 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9198#ifdef I40E_FCOE
9199 i40e_fcoe_config_netdev(netdev, vsi);
9200#endif
41c445ff
JB		 9201
9202 return 0;
9203}
9204
9205/**
9206 * i40e_vsi_delete - Delete a VSI from the switch
9207 * @vsi: the VSI being removed
9208 *
9209 * Returns 0 on success, negative value on failure
9210 **/
9211static void i40e_vsi_delete(struct i40e_vsi *vsi)
9212{
9213 /* remove default VSI is not allowed */
9214 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9215 return;
9216
41c445ff 9217 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9218}
9219
51616018
NP		 9220/**
9221 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9222 * @vsi: the VSI being queried
9223 *
9224 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9225 **/
9226int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9227{
9228 struct i40e_veb *veb;
9229 struct i40e_pf *pf = vsi->back;
9230
9231 /* Uplink is not a bridge so default to VEB */
9232 if (vsi->veb_idx == I40E_NO_VEB)
9233 return 1;
9234
9235 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9236 if (!veb) {
9237 dev_info(&pf->pdev->dev,
9238 "There is no veb associated with the bridge\n");
9239 return -ENOENT;
9240 }
9241
51616018 9242 /* Uplink is a bridge in VEPA mode */
09603eaa 9243 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9244 return 0;
09603eaa
AA		 9245 } else {
9246 /* Uplink is a bridge in VEB mode */
9247 return 1;
9248 }
51616018 9249
09603eaa
AA		 9250 /* VEPA is now default bridge, so return 0 */
9251 return 0;
51616018
NP		 9252}
9253
41c445ff
JB		 9254/**
9255 * i40e_add_vsi - Add a VSI to the switch
9256 * @vsi: the VSI being configured
9257 *
9258 * This initializes a VSI context depending on the VSI type to be added and
9259 * passes it down to the add_vsi aq command.
9260 **/
9261static int i40e_add_vsi(struct i40e_vsi *vsi)
9262{
9263 int ret = -ENODEV;
21659035
KP		 9264 u8 laa_macaddr[ETH_ALEN];
9265 bool found_laa_mac_filter = false;
41c445ff
JB		 9266 struct i40e_pf *pf = vsi->back;
9267 struct i40e_hw *hw = &pf->hw;
9268 struct i40e_vsi_context ctxt;
21659035
KP		 9269 struct i40e_mac_filter *f, *ftmp;
9270
41c445ff
JB		 9271 u8 enabled_tc = 0x1; /* TC0 enabled */
9272 int f_count = 0;
9273
9274 memset(&ctxt, 0, sizeof(ctxt));
9275 switch (vsi->type) {
9276 case I40E_VSI_MAIN:
9277 /* The PF's main VSI is already setup as part of the
9278 * device initialization, so we'll not bother with
9279 * the add_vsi call, but we will retrieve the current
9280 * VSI context.
9281 */
9282 ctxt.seid = pf->main_vsi_seid;
9283 ctxt.pf_num = pf->hw.pf_id;
9284 ctxt.vf_num = 0;
9285 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9286 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9287 if (ret) {
9288 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9289 "couldn't get PF vsi config, err %s aq_err %s\n",
9290 i40e_stat_str(&pf->hw, ret),
9291 i40e_aq_str(&pf->hw,
9292 pf->hw.aq.asq_last_status));
41c445ff
JB		 9293 return -ENOENT;
9294 }
1a2f6248 9295 vsi->info = ctxt.info;
41c445ff
JB		 9296 vsi->info.valid_sections = 0;
9297
9298 vsi->seid = ctxt.seid;
9299 vsi->id = ctxt.vsi_number;
9300
9301 enabled_tc = i40e_pf_get_tc_map(pf);
9302
9303 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9304 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9305 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9306 memset(&ctxt, 0, sizeof(ctxt));
9307 ctxt.seid = pf->main_vsi_seid;
9308 ctxt.pf_num = pf->hw.pf_id;
9309 ctxt.vf_num = 0;
9310 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9311 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9312 if (ret) {
9313 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9314 "update vsi failed, err %s aq_err %s\n",
9315 i40e_stat_str(&pf->hw, ret),
9316 i40e_aq_str(&pf->hw,
9317 pf->hw.aq.asq_last_status));
41c445ff
JB		 9318 ret = -ENOENT;
9319 goto err;
9320 }
9321 /* update the local VSI info queue map */
9322 i40e_vsi_update_queue_map(vsi, &ctxt);
9323 vsi->info.valid_sections = 0;
9324 } else {
9325 /* Default/Main VSI is only enabled for TC0
9326 * reconfigure it to enable all TCs that are
9327 * available on the port in SFP mode.
63d7e5a4
NP		 9328 * For MFP case the iSCSI PF would use this
9329 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9330 */
9331 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9332 if (ret) {
9333 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9334 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9335 enabled_tc,
9336 i40e_stat_str(&pf->hw, ret),
9337 i40e_aq_str(&pf->hw,
9338 pf->hw.aq.asq_last_status));
41c445ff
JB		 9339 ret = -ENOENT;
9340 }
9341 }
9342 break;
9343
9344 case I40E_VSI_FDIR:
cbf61325
ASJ		 9345 ctxt.pf_num = hw->pf_id;
9346 ctxt.vf_num = 0;
9347 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9348 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9349 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9350 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9351 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9352 ctxt.info.valid_sections |=
fc60861e 9353 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9354 ctxt.info.switch_id =
fc60861e 9355 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9356 }
41c445ff 9357 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9358 break;
9359
9360 case I40E_VSI_VMDQ2:
9361 ctxt.pf_num = hw->pf_id;
9362 ctxt.vf_num = 0;
9363 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9364 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9365 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9366
41c445ff
JB		 9367 /* This VSI is connected to VEB so the switch_id
9368 * should be set to zero by default.
9369 */
51616018
NP		 9370 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9371 ctxt.info.valid_sections |=
9372 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9373 ctxt.info.switch_id =
9374 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9375 }
41c445ff
JB		 9376
9377 /* Setup the VSI tx/rx queue map for TC0 only for now */
9378 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9379 break;
9380
9381 case I40E_VSI_SRIOV:
9382 ctxt.pf_num = hw->pf_id;
9383 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9384 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9385 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9386 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9387
41c445ff
JB		 9388 /* This VSI is connected to VEB so the switch_id
9389 * should be set to zero by default.
9390 */
51616018
NP		 9391 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9392 ctxt.info.valid_sections |=
9393 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9394 ctxt.info.switch_id =
9395 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9396 }
41c445ff 9397
e3219ce6
ASJ		 9398 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
9399 ctxt.info.valid_sections |=
9400 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
9401 ctxt.info.queueing_opt_flags |=
9402 I40E_AQ_VSI_QUE_OPT_TCP_ENA;
9403 }
9404
41c445ff
JB		 9405 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9406 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9407 if (pf->vf[vsi->vf_id].spoofchk) {
9408 ctxt.info.valid_sections |=
9409 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9410 ctxt.info.sec_flags |=
9411 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9412 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9413 }
41c445ff
JB		 9414 /* Setup the VSI tx/rx queue map for TC0 only for now */
9415 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9416 break;
9417
38e00438
VD		 9418#ifdef I40E_FCOE
9419 case I40E_VSI_FCOE:
9420 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9421 if (ret) {
9422 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9423 return ret;
9424 }
9425 break;
9426
9427#endif /* I40E_FCOE */
e3219ce6
ASJ		 9428 case I40E_VSI_IWARP:
9429 /* send down message to iWARP */
9430 break;
9431
41c445ff
JB		 9432 default:
9433 return -ENODEV;
9434 }
9435
9436 if (vsi->type != I40E_VSI_MAIN) {
9437 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9438 if (ret) {
9439 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9440 "add vsi failed, err %s aq_err %s\n",
9441 i40e_stat_str(&pf->hw, ret),
9442 i40e_aq_str(&pf->hw,
9443 pf->hw.aq.asq_last_status));
41c445ff
JB		 9444 ret = -ENOENT;
9445 goto err;
9446 }
1a2f6248 9447 vsi->info = ctxt.info;
41c445ff
JB		 9448 vsi->info.valid_sections = 0;
9449 vsi->seid = ctxt.seid;
9450 vsi->id = ctxt.vsi_number;
9451 }
9452
21659035 9453 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9454 /* If macvlan filters already exist, force them to get loaded */
9455 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9456 f->changed = true;
9457 f_count++;
6252c7e4 9458
21659035 9459 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9460 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9461 ether_addr_copy(laa_macaddr, f->macaddr);
9462 found_laa_mac_filter = true;
9463 }
9464 }
9465 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9466
21659035
KP		 9467 if (found_laa_mac_filter) {
9468 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9469
21659035
KP		 9470 memset(&element, 0, sizeof(element));
9471 ether_addr_copy(element.mac_addr, laa_macaddr);
9472 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9473 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9474 &element, 1, NULL);
9475 if (ret) {
9476 /* some older FW has a different default */
9477 element.flags |=
9478 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9479 i40e_aq_remove_macvlan(hw, vsi->seid,
9480 &element, 1, NULL);
6252c7e4 9481 }
21659035
KP		 9482
9483 i40e_aq_mac_address_write(hw,
9484 I40E_AQC_WRITE_TYPE_LAA_WOL,
9485 laa_macaddr, NULL);
41c445ff 9486 }
21659035 9487
41c445ff
JB		 9488 if (f_count) {
9489 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9490 pf->flags |= I40E_FLAG_FILTER_SYNC;
9491 }
9492
9493 /* Update VSI BW information */
9494 ret = i40e_vsi_get_bw_info(vsi);
9495 if (ret) {
9496 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9497 "couldn't get vsi bw info, err %s aq_err %s\n",
9498 i40e_stat_str(&pf->hw, ret),
9499 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9500 /* VSI is already added so not tearing that up */
9501 ret = 0;
9502 }
9503
9504err:
9505 return ret;
9506}
9507
9508/**
9509 * i40e_vsi_release - Delete a VSI and free its resources
9510 * @vsi: the VSI being removed
9511 *
9512 * Returns 0 on success or < 0 on error
9513 **/
9514int i40e_vsi_release(struct i40e_vsi *vsi)
9515{
9516 struct i40e_mac_filter *f, *ftmp;
9517 struct i40e_veb *veb = NULL;
9518 struct i40e_pf *pf;
9519 u16 uplink_seid;
9520 int i, n;
9521
9522 pf = vsi->back;
9523
9524 /* release of a VEB-owner or last VSI is not allowed */
9525 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9526 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9527 vsi->seid, vsi->uplink_seid);
9528 return -ENODEV;
9529 }
9530 if (vsi == pf->vsi[pf->lan_vsi] &&
9531 !test_bit(__I40E_DOWN, &pf->state)) {
9532 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9533 return -ENODEV;
9534 }
9535
9536 uplink_seid = vsi->uplink_seid;
9537 if (vsi->type != I40E_VSI_SRIOV) {
9538 if (vsi->netdev_registered) {
9539 vsi->netdev_registered = false;
9540 if (vsi->netdev) {
9541 /* results in a call to i40e_close() */
9542 unregister_netdev(vsi->netdev);
41c445ff
JB		 9543 }
9544 } else {
90ef8d47 9545 i40e_vsi_close(vsi);
41c445ff
JB		 9546 }
9547 i40e_vsi_disable_irq(vsi);
9548 }
9549
21659035 9550 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9551 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9552 i40e_del_filter(vsi, f->macaddr, f->vlan,
9553 f->is_vf, f->is_netdev);
21659035
KP		 9554 spin_unlock_bh(&vsi->mac_filter_list_lock);
9555
17652c63 9556 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9557
9558 i40e_vsi_delete(vsi);
9559 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9560 if (vsi->netdev) {
9561 free_netdev(vsi->netdev);
9562 vsi->netdev = NULL;
9563 }
41c445ff
JB		 9564 i40e_vsi_clear_rings(vsi);
9565 i40e_vsi_clear(vsi);
9566
9567 /* If this was the last thing on the VEB, except for the
9568 * controlling VSI, remove the VEB, which puts the controlling
9569 * VSI onto the next level down in the switch.
9570 *
9571 * Well, okay, there's one more exception here: don't remove
9572 * the orphan VEBs yet. We'll wait for an explicit remove request
9573 * from up the network stack.
9574 */
505682cd 9575 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9576 if (pf->vsi[i] &&
9577 pf->vsi[i]->uplink_seid == uplink_seid &&
9578 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9579 n++; /* count the VSIs */
9580 }
9581 }
9582 for (i = 0; i < I40E_MAX_VEB; i++) {
9583 if (!pf->veb[i])
9584 continue;
9585 if (pf->veb[i]->uplink_seid == uplink_seid)
9586 n++; /* count the VEBs */
9587 if (pf->veb[i]->seid == uplink_seid)
9588 veb = pf->veb[i];
9589 }
9590 if (n == 0 && veb && veb->uplink_seid != 0)
9591 i40e_veb_release(veb);
9592
9593 return 0;
9594}
9595
9596/**
9597 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9598 * @vsi: ptr to the VSI
9599 *
9600 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9601 * corresponding SW VSI structure and initializes num_queue_pairs for the
9602 * newly allocated VSI.
9603 *
9604 * Returns 0 on success or negative on failure
9605 **/
9606static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9607{
9608 int ret = -ENOENT;
9609 struct i40e_pf *pf = vsi->back;
9610
493fb300 9611 if (vsi->q_vectors[0]) {
41c445ff
JB		 9612 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9613 vsi->seid);
9614 return -EEXIST;
9615 }
9616
9617 if (vsi->base_vector) {
f29eaa3d 9618 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9619 vsi->seid, vsi->base_vector);
9620 return -EEXIST;
9621 }
9622
90e04070 9623 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9624 if (ret) {
9625 dev_info(&pf->pdev->dev,
9626 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9627 vsi->num_q_vectors, vsi->seid, ret);
9628 vsi->num_q_vectors = 0;
9629 goto vector_setup_out;
9630 }
9631
26cdc443
ASJ		 9632 /* In Legacy mode, we do not have to get any other vector since we
9633 * piggyback on the misc/ICR0 for queue interrupts.
9634 */
9635 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9636 return ret;
958a3e3b
SN		 9637 if (vsi->num_q_vectors)
9638 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9639 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9640 if (vsi->base_vector < 0) {
9641 dev_info(&pf->pdev->dev,
049a2be8
SN		 9642 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9643 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9644 i40e_vsi_free_q_vectors(vsi);
9645 ret = -ENOENT;
9646 goto vector_setup_out;
9647 }
9648
9649vector_setup_out:
9650 return ret;
9651}
9652
bc7d338f
ASJ		 9653/**
9654 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9655 * @vsi: pointer to the vsi.
9656 *
9657 * This re-allocates a vsi's queue resources.
9658 *
9659 * Returns pointer to the successfully allocated and configured VSI sw struct
9660 * on success, otherwise returns NULL on failure.
9661 **/
9662static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9663{
f534039d 9664 struct i40e_pf *pf;
bc7d338f
ASJ		 9665 u8 enabled_tc;
9666 int ret;
9667
f534039d
JU		 9668 if (!vsi)
9669 return NULL;
9670
9671 pf = vsi->back;
9672
bc7d338f
ASJ		 9673 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9674 i40e_vsi_clear_rings(vsi);
9675
9676 i40e_vsi_free_arrays(vsi, false);
9677 i40e_set_num_rings_in_vsi(vsi);
9678 ret = i40e_vsi_alloc_arrays(vsi, false);
9679 if (ret)
9680 goto err_vsi;
9681
9682 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9683 if (ret < 0) {
049a2be8 9684 dev_info(&pf->pdev->dev,
f1c7e72e 9685 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9686 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9687 goto err_vsi;
9688 }
9689 vsi->base_queue = ret;
9690
9691 /* Update the FW view of the VSI. Force a reset of TC and queue
9692 * layout configurations.
9693 */
9694 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9695 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9696 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9697 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9698
9699 /* assign it some queues */
9700 ret = i40e_alloc_rings(vsi);
9701 if (ret)
9702 goto err_rings;
9703
9704 /* map all of the rings to the q_vectors */
9705 i40e_vsi_map_rings_to_vectors(vsi);
9706 return vsi;
9707
9708err_rings:
9709 i40e_vsi_free_q_vectors(vsi);
9710 if (vsi->netdev_registered) {
9711 vsi->netdev_registered = false;
9712 unregister_netdev(vsi->netdev);
9713 free_netdev(vsi->netdev);
9714 vsi->netdev = NULL;
9715 }
9716 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9717err_vsi:
9718 i40e_vsi_clear(vsi);
9719 return NULL;
9720}
9721
b499ffb0
SV		 9722/**
9723 * i40e_macaddr_init - explicitly write the mac address filters.
9724 *
9725 * @vsi: pointer to the vsi.
9726 * @macaddr: the MAC address
9727 *
9728 * This is needed when the macaddr has been obtained by other
9729 * means than the default, e.g., from Open Firmware or IDPROM.
9730 * Returns 0 on success, negative on failure
9731 **/
9732static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr)
9733{
9734 int ret;
9735 struct i40e_aqc_add_macvlan_element_data element;
9736
9737 ret = i40e_aq_mac_address_write(&vsi->back->hw,
9738 I40E_AQC_WRITE_TYPE_LAA_WOL,
9739 macaddr, NULL);
9740 if (ret) {
9741 dev_info(&vsi->back->pdev->dev,
9742 "Addr change for VSI failed: %d\n", ret);
9743 return -EADDRNOTAVAIL;
9744 }
9745
9746 memset(&element, 0, sizeof(element));
9747 ether_addr_copy(element.mac_addr, macaddr);
9748 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
9749 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL);
9750 if (ret) {
9751 dev_info(&vsi->back->pdev->dev,
9752 "add filter failed err %s aq_err %s\n",
9753 i40e_stat_str(&vsi->back->hw, ret),
9754 i40e_aq_str(&vsi->back->hw,
9755 vsi->back->hw.aq.asq_last_status));
9756 }
9757 return ret;
9758}
9759
41c445ff
JB		 9760/**
9761 * i40e_vsi_setup - Set up a VSI by a given type
9762 * @pf: board private structure
9763 * @type: VSI type
9764 * @uplink_seid: the switch element to link to
9765 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9766 *
9767 * This allocates the sw VSI structure and its queue resources, then add a VSI
9768 * to the identified VEB.
9769 *
9770 * Returns pointer to the successfully allocated and configure VSI sw struct on
9771 * success, otherwise returns NULL on failure.
9772 **/
9773struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9774 u16 uplink_seid, u32 param1)
9775{
9776 struct i40e_vsi *vsi = NULL;
9777 struct i40e_veb *veb = NULL;
9778 int ret, i;
9779 int v_idx;
9780
9781 /* The requested uplink_seid must be either
9782 * - the PF's port seid
9783 * no VEB is needed because this is the PF
9784 * or this is a Flow Director special case VSI
9785 * - seid of an existing VEB
9786 * - seid of a VSI that owns an existing VEB
9787 * - seid of a VSI that doesn't own a VEB
9788 * a new VEB is created and the VSI becomes the owner
9789 * - seid of the PF VSI, which is what creates the first VEB
9790 * this is a special case of the previous
9791 *
9792 * Find which uplink_seid we were given and create a new VEB if needed
9793 */
9794 for (i = 0; i < I40E_MAX_VEB; i++) {
9795 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9796 veb = pf->veb[i];
9797 break;
9798 }
9799 }
9800
9801 if (!veb && uplink_seid != pf->mac_seid) {
9802
505682cd 9803 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9804 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9805 vsi = pf->vsi[i];
9806 break;
9807 }
9808 }
9809 if (!vsi) {
9810 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9811 uplink_seid);
9812 return NULL;
9813 }
9814
9815 if (vsi->uplink_seid == pf->mac_seid)
9816 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9817 vsi->tc_config.enabled_tc);
9818 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9819 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9820 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9821 if (veb) {
9822 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9823 dev_info(&vsi->back->pdev->dev,
fb43201f 9824 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9825 return NULL;
9826 }
fa11cb3d
ASJ		 9827 /* We come up by default in VEPA mode if SRIOV is not
9828 * already enabled, in which case we can't force VEPA
9829 * mode.
9830 */
9831 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9832 veb->bridge_mode = BRIDGE_MODE_VEPA;
9833 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9834 }
51616018 9835 i40e_config_bridge_mode(veb);
79c21a82 9836 }
41c445ff
JB		 9837 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9838 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9839 veb = pf->veb[i];
9840 }
9841 if (!veb) {
9842 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9843 return NULL;
9844 }
9845
9846 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9847 uplink_seid = veb->seid;
9848 }
9849
9850 /* get vsi sw struct */
9851 v_idx = i40e_vsi_mem_alloc(pf, type);
9852 if (v_idx < 0)
9853 goto err_alloc;
9854 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9855 if (!vsi)
9856 goto err_alloc;
41c445ff
JB		 9857 vsi->type = type;
9858 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9859
9860 if (type == I40E_VSI_MAIN)
9861 pf->lan_vsi = v_idx;
9862 else if (type == I40E_VSI_SRIOV)
9863 vsi->vf_id = param1;
9864 /* assign it some queues */
cbf61325
ASJ		 9865 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9866 vsi->idx);
41c445ff 9867 if (ret < 0) {
049a2be8
SN		 9868 dev_info(&pf->pdev->dev,
9869 "failed to get tracking for %d queues for VSI %d err=%d\n",
9870 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9871 goto err_vsi;
9872 }
9873 vsi->base_queue = ret;
9874
9875 /* get a VSI from the hardware */
9876 vsi->uplink_seid = uplink_seid;
9877 ret = i40e_add_vsi(vsi);
9878 if (ret)
9879 goto err_vsi;
9880
9881 switch (vsi->type) {
9882 /* setup the netdev if needed */
9883 case I40E_VSI_MAIN:
b499ffb0
SV		 9884 /* Apply relevant filters if a platform-specific mac
9885 * address was selected.
9886 */
9887 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
9888 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr);
9889 if (ret) {
9890 dev_warn(&pf->pdev->dev,
9891 "could not set up macaddr; err %d\n",
9892 ret);
9893 }
9894 }
41c445ff 9895 case I40E_VSI_VMDQ2:
38e00438 9896 case I40E_VSI_FCOE:
41c445ff
JB		 9897 ret = i40e_config_netdev(vsi);
9898 if (ret)
9899 goto err_netdev;
9900 ret = register_netdev(vsi->netdev);
9901 if (ret)
9902 goto err_netdev;
9903 vsi->netdev_registered = true;
9904 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9905#ifdef CONFIG_I40E_DCB
9906 /* Setup DCB netlink interface */
9907 i40e_dcbnl_setup(vsi);
9908#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9909 /* fall through */
9910
9911 case I40E_VSI_FDIR:
9912 /* set up vectors and rings if needed */
9913 ret = i40e_vsi_setup_vectors(vsi);
9914 if (ret)
9915 goto err_msix;
9916
9917 ret = i40e_alloc_rings(vsi);
9918 if (ret)
9919 goto err_rings;
9920
9921 /* map all of the rings to the q_vectors */
9922 i40e_vsi_map_rings_to_vectors(vsi);
9923
9924 i40e_vsi_reset_stats(vsi);
9925 break;
9926
9927 default:
9928 /* no netdev or rings for the other VSI types */
9929 break;
9930 }
9931
e25d00b8
ASJ		 9932 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9933 (vsi->type == I40E_VSI_VMDQ2)) {
9934 ret = i40e_vsi_config_rss(vsi);
9935 }
41c445ff
JB		 9936 return vsi;
9937
9938err_rings:
9939 i40e_vsi_free_q_vectors(vsi);
9940err_msix:
9941 if (vsi->netdev_registered) {
9942 vsi->netdev_registered = false;
9943 unregister_netdev(vsi->netdev);
9944 free_netdev(vsi->netdev);
9945 vsi->netdev = NULL;
9946 }
9947err_netdev:
9948 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9949err_vsi:
9950 i40e_vsi_clear(vsi);
9951err_alloc:
9952 return NULL;
9953}
9954
9955/**
9956 * i40e_veb_get_bw_info - Query VEB BW information
9957 * @veb: the veb to query
9958 *
9959 * Query the Tx scheduler BW configuration data for given VEB
9960 **/
9961static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9962{
9963 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9964 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9965 struct i40e_pf *pf = veb->pf;
9966 struct i40e_hw *hw = &pf->hw;
9967 u32 tc_bw_max;
9968 int ret = 0;
9969 int i;
9970
9971 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9972 &bw_data, NULL);
9973 if (ret) {
9974 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9975 "query veb bw config failed, err %s aq_err %s\n",
9976 i40e_stat_str(&pf->hw, ret),
9977 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9978 goto out;
9979 }
9980
9981 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9982 &ets_data, NULL);
9983 if (ret) {
9984 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9985 "query veb bw ets config failed, err %s aq_err %s\n",
9986 i40e_stat_str(&pf->hw, ret),
9987 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9988 goto out;
9989 }
9990
9991 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9992 veb->bw_max_quanta = ets_data.tc_bw_max;
9993 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9994 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9995 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9996 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9997 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9998 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9999 veb->bw_tc_limit_credits[i] =
10000 le16_to_cpu(bw_data.tc_bw_limits[i]);
10001 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
10002 }
10003
10004out:
10005 return ret;
10006}
10007
10008/**
10009 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
10010 * @pf: board private structure
10011 *
10012 * On error: returns error code (negative)
10013 * On success: returns vsi index in PF (positive)
10014 **/
10015static int i40e_veb_mem_alloc(struct i40e_pf *pf)
10016{
10017 int ret = -ENOENT;
10018 struct i40e_veb *veb;
10019 int i;
10020
10021 /* Need to protect the allocation of switch elements at the PF level */
10022 mutex_lock(&pf->switch_mutex);
10023
10024 /* VEB list may be fragmented if VEB creation/destruction has
10025 * been happening. We can afford to do a quick scan to look
10026 * for any free slots in the list.
10027 *
10028 * find next empty veb slot, looping back around if necessary
10029 */
10030 i = 0;
10031 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
10032 i++;
10033 if (i >= I40E_MAX_VEB) {
10034 ret = -ENOMEM;
10035 goto err_alloc_veb; /* out of VEB slots! */
10036 }
10037
10038 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
10039 if (!veb) {
10040 ret = -ENOMEM;
10041 goto err_alloc_veb;
10042 }
10043 veb->pf = pf;
10044 veb->idx = i;
10045 veb->enabled_tc = 1;
10046
10047 pf->veb[i] = veb;
10048 ret = i;
10049err_alloc_veb:
10050 mutex_unlock(&pf->switch_mutex);
10051 return ret;
10052}
10053
10054/**
10055 * i40e_switch_branch_release - Delete a branch of the switch tree
10056 * @branch: where to start deleting
10057 *
10058 * This uses recursion to find the tips of the branch to be
10059 * removed, deleting until we get back to and can delete this VEB.
10060 **/
10061static void i40e_switch_branch_release(struct i40e_veb *branch)
10062{
10063 struct i40e_pf *pf = branch->pf;
10064 u16 branch_seid = branch->seid;
10065 u16 veb_idx = branch->idx;
10066 int i;
10067
10068 /* release any VEBs on this VEB - RECURSION */
10069 for (i = 0; i < I40E_MAX_VEB; i++) {
10070 if (!pf->veb[i])
10071 continue;
10072 if (pf->veb[i]->uplink_seid == branch->seid)
10073 i40e_switch_branch_release(pf->veb[i]);
10074 }
10075
10076 /* Release the VSIs on this VEB, but not the owner VSI.
10077 *
10078 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
10079 * the VEB itself, so don't use (*branch) after this loop.
10080 */
505682cd 10081 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10082 if (!pf->vsi[i])
10083 continue;
10084 if (pf->vsi[i]->uplink_seid == branch_seid &&
10085 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
10086 i40e_vsi_release(pf->vsi[i]);
10087 }
10088 }
10089
10090 /* There's one corner case where the VEB might not have been
10091 * removed, so double check it here and remove it if needed.
10092 * This case happens if the veb was created from the debugfs
10093 * commands and no VSIs were added to it.
10094 */
10095 if (pf->veb[veb_idx])
10096 i40e_veb_release(pf->veb[veb_idx]);
10097}
10098
10099/**
10100 * i40e_veb_clear - remove veb struct
10101 * @veb: the veb to remove
10102 **/
10103static void i40e_veb_clear(struct i40e_veb *veb)
10104{
10105 if (!veb)
10106 return;
10107
10108 if (veb->pf) {
10109 struct i40e_pf *pf = veb->pf;
10110
10111 mutex_lock(&pf->switch_mutex);
10112 if (pf->veb[veb->idx] == veb)
10113 pf->veb[veb->idx] = NULL;
10114 mutex_unlock(&pf->switch_mutex);
10115 }
10116
10117 kfree(veb);
10118}
10119
10120/**
10121 * i40e_veb_release - Delete a VEB and free its resources
10122 * @veb: the VEB being removed
10123 **/
10124void i40e_veb_release(struct i40e_veb *veb)
10125{
10126 struct i40e_vsi *vsi = NULL;
10127 struct i40e_pf *pf;
10128 int i, n = 0;
10129
10130 pf = veb->pf;
10131
10132 /* find the remaining VSI and check for extras */
505682cd 10133 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10134 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
10135 n++;
10136 vsi = pf->vsi[i];
10137 }
10138 }
10139 if (n != 1) {
10140 dev_info(&pf->pdev->dev,
10141 "can't remove VEB %d with %d VSIs left\n",
10142 veb->seid, n);
10143 return;
10144 }
10145
10146 /* move the remaining VSI to uplink veb */
10147 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
10148 if (veb->uplink_seid) {
10149 vsi->uplink_seid = veb->uplink_seid;
10150 if (veb->uplink_seid == pf->mac_seid)
10151 vsi->veb_idx = I40E_NO_VEB;
10152 else
10153 vsi->veb_idx = veb->veb_idx;
10154 } else {
10155 /* floating VEB */
10156 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10157 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
10158 }
10159
10160 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
10161 i40e_veb_clear(veb);
41c445ff
JB		 10162}
10163
10164/**
10165 * i40e_add_veb - create the VEB in the switch
10166 * @veb: the VEB to be instantiated
10167 * @vsi: the controlling VSI
10168 **/
10169static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
10170{
f1c7e72e 10171 struct i40e_pf *pf = veb->pf;
92faef85 10172 bool is_default = veb->pf->cur_promisc;
66fc360a 10173 bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED);
41c445ff
JB		 10174 int ret;
10175
10176 /* get a VEB from the hardware */
f1c7e72e 10177 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95 10178 veb->enabled_tc, is_default,
66fc360a 10179 &veb->seid, enable_stats, NULL);
41c445ff 10180 if (ret) {
f1c7e72e
SN		 10181 dev_info(&pf->pdev->dev,
10182 "couldn't add VEB, err %s aq_err %s\n",
10183 i40e_stat_str(&pf->hw, ret),
10184 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10185 return -EPERM;
10186 }
10187
10188 /* get statistics counter */
f1c7e72e 10189 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 10190 &veb->stats_idx, NULL, NULL, NULL);
10191 if (ret) {
f1c7e72e
SN		 10192 dev_info(&pf->pdev->dev,
10193 "couldn't get VEB statistics idx, err %s aq_err %s\n",
10194 i40e_stat_str(&pf->hw, ret),
10195 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10196 return -EPERM;
10197 }
10198 ret = i40e_veb_get_bw_info(veb);
10199 if (ret) {
f1c7e72e
SN		 10200 dev_info(&pf->pdev->dev,
10201 "couldn't get VEB bw info, err %s aq_err %s\n",
10202 i40e_stat_str(&pf->hw, ret),
10203 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10204 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 10205 return -ENOENT;
10206 }
10207
10208 vsi->uplink_seid = veb->seid;
10209 vsi->veb_idx = veb->idx;
10210 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
10211
10212 return 0;
10213}
10214
10215/**
10216 * i40e_veb_setup - Set up a VEB
10217 * @pf: board private structure
10218 * @flags: VEB setup flags
10219 * @uplink_seid: the switch element to link to
10220 * @vsi_seid: the initial VSI seid
10221 * @enabled_tc: Enabled TC bit-map
10222 *
10223 * This allocates the sw VEB structure and links it into the switch
10224 * It is possible and legal for this to be a duplicate of an already
10225 * existing VEB. It is also possible for both uplink and vsi seids
10226 * to be zero, in order to create a floating VEB.
10227 *
10228 * Returns pointer to the successfully allocated VEB sw struct on
10229 * success, otherwise returns NULL on failure.
10230 **/
10231struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
10232 u16 uplink_seid, u16 vsi_seid,
10233 u8 enabled_tc)
10234{
10235 struct i40e_veb *veb, *uplink_veb = NULL;
10236 int vsi_idx, veb_idx;
10237 int ret;
10238
10239 /* if one seid is 0, the other must be 0 to create a floating relay */
10240 if ((uplink_seid == 0 || vsi_seid == 0) &&
10241 (uplink_seid + vsi_seid != 0)) {
10242 dev_info(&pf->pdev->dev,
10243 "one, not both seid's are 0: uplink=%d vsi=%d\n",
10244 uplink_seid, vsi_seid);
10245 return NULL;
10246 }
10247
10248 /* make sure there is such a vsi and uplink */
505682cd 10249 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10250 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10251 break;
505682cd 10252 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10253 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10254 vsi_seid);
10255 return NULL;
10256 }
10257
10258 if (uplink_seid && uplink_seid != pf->mac_seid) {
10259 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10260 if (pf->veb[veb_idx] &&
10261 pf->veb[veb_idx]->seid == uplink_seid) {
10262 uplink_veb = pf->veb[veb_idx];
10263 break;
10264 }
10265 }
10266 if (!uplink_veb) {
10267 dev_info(&pf->pdev->dev,
10268 "uplink seid %d not found\n", uplink_seid);
10269 return NULL;
10270 }
10271 }
10272
10273 /* get veb sw struct */
10274 veb_idx = i40e_veb_mem_alloc(pf);
10275 if (veb_idx < 0)
10276 goto err_alloc;
10277 veb = pf->veb[veb_idx];
10278 veb->flags = flags;
10279 veb->uplink_seid = uplink_seid;
10280 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10281 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10282
10283 /* create the VEB in the switch */
10284 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10285 if (ret)
10286 goto err_veb;
1bb8b935
SN		 10287 if (vsi_idx == pf->lan_vsi)
10288 pf->lan_veb = veb->idx;
41c445ff
JB		 10289
10290 return veb;
10291
10292err_veb:
10293 i40e_veb_clear(veb);
10294err_alloc:
10295 return NULL;
10296}
10297
10298/**
b40c82e6 10299 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10300 * @pf: board private structure
10301 * @ele: element we are building info from
10302 * @num_reported: total number of elements
10303 * @printconfig: should we print the contents
10304 *
10305 * helper function to assist in extracting a few useful SEID values.
10306 **/
10307static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10308 struct i40e_aqc_switch_config_element_resp *ele,
10309 u16 num_reported, bool printconfig)
10310{
10311 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10312 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10313 u8 element_type = ele->element_type;
10314 u16 seid = le16_to_cpu(ele->seid);
10315
10316 if (printconfig)
10317 dev_info(&pf->pdev->dev,
10318 "type=%d seid=%d uplink=%d downlink=%d\n",
10319 element_type, seid, uplink_seid, downlink_seid);
10320
10321 switch (element_type) {
10322 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10323 pf->mac_seid = seid;
10324 break;
10325 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10326 /* Main VEB? */
10327 if (uplink_seid != pf->mac_seid)
10328 break;
10329 if (pf->lan_veb == I40E_NO_VEB) {
10330 int v;
10331
10332 /* find existing or else empty VEB */
10333 for (v = 0; v < I40E_MAX_VEB; v++) {
10334 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10335 pf->lan_veb = v;
10336 break;
10337 }
10338 }
10339 if (pf->lan_veb == I40E_NO_VEB) {
10340 v = i40e_veb_mem_alloc(pf);
10341 if (v < 0)
10342 break;
10343 pf->lan_veb = v;
10344 }
10345 }
10346
10347 pf->veb[pf->lan_veb]->seid = seid;
10348 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10349 pf->veb[pf->lan_veb]->pf = pf;
10350 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10351 break;
10352 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10353 if (num_reported != 1)
10354 break;
10355 /* This is immediately after a reset so we can assume this is
10356 * the PF's VSI
10357 */
10358 pf->mac_seid = uplink_seid;
10359 pf->pf_seid = downlink_seid;
10360 pf->main_vsi_seid = seid;
10361 if (printconfig)
10362 dev_info(&pf->pdev->dev,
10363 "pf_seid=%d main_vsi_seid=%d\n",
10364 pf->pf_seid, pf->main_vsi_seid);
10365 break;
10366 case I40E_SWITCH_ELEMENT_TYPE_PF:
10367 case I40E_SWITCH_ELEMENT_TYPE_VF:
10368 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10369 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10370 case I40E_SWITCH_ELEMENT_TYPE_PE:
10371 case I40E_SWITCH_ELEMENT_TYPE_PA:
10372 /* ignore these for now */
10373 break;
10374 default:
10375 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10376 element_type, seid);
10377 break;
10378 }
10379}
10380
10381/**
10382 * i40e_fetch_switch_configuration - Get switch config from firmware
10383 * @pf: board private structure
10384 * @printconfig: should we print the contents
10385 *
10386 * Get the current switch configuration from the device and
10387 * extract a few useful SEID values.
10388 **/
10389int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10390{
10391 struct i40e_aqc_get_switch_config_resp *sw_config;
10392 u16 next_seid = 0;
10393 int ret = 0;
10394 u8 *aq_buf;
10395 int i;
10396
10397 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10398 if (!aq_buf)
10399 return -ENOMEM;
10400
10401 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10402 do {
10403 u16 num_reported, num_total;
10404
10405 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10406 I40E_AQ_LARGE_BUF,
10407 &next_seid, NULL);
10408 if (ret) {
10409 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10410 "get switch config failed err %s aq_err %s\n",
10411 i40e_stat_str(&pf->hw, ret),
10412 i40e_aq_str(&pf->hw,
10413 pf->hw.aq.asq_last_status));
41c445ff
JB		 10414 kfree(aq_buf);
10415 return -ENOENT;
10416 }
10417
10418 num_reported = le16_to_cpu(sw_config->header.num_reported);
10419 num_total = le16_to_cpu(sw_config->header.num_total);
10420
10421 if (printconfig)
10422 dev_info(&pf->pdev->dev,
10423 "header: %d reported %d total\n",
10424 num_reported, num_total);
10425
41c445ff
JB		 10426 for (i = 0; i < num_reported; i++) {
10427 struct i40e_aqc_switch_config_element_resp *ele =
10428 &sw_config->element[i];
10429
10430 i40e_setup_pf_switch_element(pf, ele, num_reported,
10431 printconfig);
10432 }
10433 } while (next_seid != 0);
10434
10435 kfree(aq_buf);
10436 return ret;
10437}
10438
10439/**
10440 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10441 * @pf: board private structure
bc7d338f 10442 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10443 *
10444 * Returns 0 on success, negative value on failure
10445 **/
bc7d338f 10446static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10447{
10448 int ret;
10449
10450 /* find out what's out there already */
10451 ret = i40e_fetch_switch_configuration(pf, false);
10452 if (ret) {
10453 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10454 "couldn't fetch switch config, err %s aq_err %s\n",
10455 i40e_stat_str(&pf->hw, ret),
10456 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10457 return ret;
10458 }
10459 i40e_pf_reset_stats(pf);
10460
41c445ff 10461 /* first time setup */
bc7d338f 10462 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10463 struct i40e_vsi *vsi = NULL;
10464 u16 uplink_seid;
10465
10466 /* Set up the PF VSI associated with the PF's main VSI
10467 * that is already in the HW switch
10468 */
10469 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10470 uplink_seid = pf->veb[pf->lan_veb]->seid;
10471 else
10472 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10473 if (pf->lan_vsi == I40E_NO_VSI)
10474 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10475 else if (reinit)
10476 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10477 if (!vsi) {
10478 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10479 i40e_fdir_teardown(pf);
10480 return -EAGAIN;
10481 }
41c445ff
JB		 10482 } else {
10483 /* force a reset of TC and queue layout configurations */
10484 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10485
41c445ff
JB		 10486 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10487 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10488 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10489 }
10490 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10491
cbf61325
ASJ		 10492 i40e_fdir_sb_setup(pf);
10493
41c445ff
JB		 10494 /* Setup static PF queue filter control settings */
10495 ret = i40e_setup_pf_filter_control(pf);
10496 if (ret) {
10497 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10498 ret);
10499 /* Failure here should not stop continuing other steps */
10500 }
10501
10502 /* enable RSS in the HW, even for only one queue, as the stack can use
10503 * the hash
10504 */
10505 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10506 i40e_pf_config_rss(pf);
41c445ff
JB		 10507
10508 /* fill in link information and enable LSE reporting */
0a862b43 10509 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10510 i40e_link_event(pf);
10511
d52c20b7 10512 /* Initialize user-specific link properties */
41c445ff
JB		 10513 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10514 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10515
beb0dff1
JK		 10516 i40e_ptp_init(pf);
10517
41c445ff
JB		 10518 return ret;
10519}
10520
41c445ff
JB		 10521/**
10522 * i40e_determine_queue_usage - Work out queue distribution
10523 * @pf: board private structure
10524 **/
10525static void i40e_determine_queue_usage(struct i40e_pf *pf)
10526{
41c445ff
JB		 10527 int queues_left;
10528
10529 pf->num_lan_qps = 0;
38e00438
VD		 10530#ifdef I40E_FCOE
10531 pf->num_fcoe_qps = 0;
10532#endif
41c445ff
JB		 10533
10534 /* Find the max queues to be put into basic use. We'll always be
10535 * using TC0, whether or not DCB is running, and TC0 will get the
10536 * big RSS set.
10537 */
10538 queues_left = pf->hw.func_caps.num_tx_qp;
10539
cbf61325 10540 if ((queues_left == 1) ||
9aa7e935 10541 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10542 /* one qp for PF, no queues for anything else */
10543 queues_left = 0;
acd65448 10544 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10545
10546 /* make sure all the fancies are disabled */
60ea5f83 10547 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10548 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10549#ifdef I40E_FCOE
10550 I40E_FLAG_FCOE_ENABLED |
10551#endif
60ea5f83
JB		 10552 I40E_FLAG_FD_SB_ENABLED |
10553 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10554 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10555 I40E_FLAG_SRIOV_ENABLED |
10556 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10557 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10558 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10559 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10560 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10561 /* one qp for PF */
acd65448 10562 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10563 queues_left -= pf->num_lan_qps;
10564
10565 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10566 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10567#ifdef I40E_FCOE
10568 I40E_FLAG_FCOE_ENABLED |
10569#endif
9aa7e935
FZ		 10570 I40E_FLAG_FD_SB_ENABLED |
10571 I40E_FLAG_FD_ATR_ENABLED |
10572 I40E_FLAG_DCB_ENABLED |
10573 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10574 } else {
cbf61325 10575 /* Not enough queues for all TCs */
4d9b6043 10576 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10577 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10578 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10579 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10580 }
9a3bd2f1
ASJ		 10581 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10582 num_online_cpus());
10583 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10584 pf->hw.func_caps.num_tx_qp);
10585
cbf61325
ASJ		 10586 queues_left -= pf->num_lan_qps;
10587 }
10588
38e00438
VD		 10589#ifdef I40E_FCOE
10590 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10591 if (I40E_DEFAULT_FCOE <= queues_left) {
10592 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10593 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10594 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10595 } else {
10596 pf->num_fcoe_qps = 0;
10597 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10598 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10599 }
10600
10601 queues_left -= pf->num_fcoe_qps;
10602 }
10603
10604#endif
cbf61325
ASJ		 10605 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10606 if (queues_left > 1) {
10607 queues_left -= 1; /* save 1 queue for FD */
10608 } else {
10609 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10610 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10611 }
41c445ff
JB		 10612 }
10613
10614 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10615 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10616 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10617 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10618 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10619 }
10620
10621 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10622 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10623 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10624 (queues_left / pf->num_vmdq_qps));
10625 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10626 }
10627
f8ff1464 10628 pf->queues_left = queues_left;
8279e495
NP		 10629 dev_dbg(&pf->pdev->dev,
10630 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10631 pf->hw.func_caps.num_tx_qp,
10632 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10633 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10634 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10635 queues_left);
38e00438 10636#ifdef I40E_FCOE
8279e495 10637 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10638#endif
41c445ff
JB		 10639}
10640
10641/**
10642 * i40e_setup_pf_filter_control - Setup PF static filter control
10643 * @pf: PF to be setup
10644 *
b40c82e6 10645 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10646 * settings. If PE/FCoE are enabled then it will also set the per PF
10647 * based filter sizes required for them. It also enables Flow director,
10648 * ethertype and macvlan type filter settings for the pf.
10649 *
10650 * Returns 0 on success, negative on failure
10651 **/
10652static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10653{
10654 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10655
10656 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10657
10658 /* Flow Director is enabled */
60ea5f83 10659 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10660 settings->enable_fdir = true;
10661
10662 /* Ethtype and MACVLAN filters enabled for PF */
10663 settings->enable_ethtype = true;
10664 settings->enable_macvlan = true;
10665
10666 if (i40e_set_filter_control(&pf->hw, settings))
10667 return -ENOENT;
10668
10669 return 0;
10670}
10671
0c22b3dd 10672#define INFO_STRING_LEN 255
7fd89545 10673#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10674static void i40e_print_features(struct i40e_pf *pf)
10675{
10676 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10677 char *buf;
10678 int i;
0c22b3dd 10679
3b195843
JP		 10680 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10681 if (!buf)
0c22b3dd 10682 return;
0c22b3dd 10683
3b195843 10684 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10685#ifdef CONFIG_PCI_IOV
3b195843 10686 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10687#endif
3b195843 10688 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d RX: %s",
7fd89545
SN		 10689 pf->hw.func_caps.num_vsis,
10690 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10691 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10692
10693 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10694 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10695 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10696 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10697 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10698 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10699 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10700 }
4d9b6043 10701 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10702 i += snprintf(&buf[i], REMAIN(i), " DCB");
ce6fcb3f 10703#if IS_ENABLED(CONFIG_VXLAN)
3b195843 10704 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024
SA		 10705#endif
10706#if IS_ENABLED(CONFIG_GENEVE)
10707 i += snprintf(&buf[i], REMAIN(i), " Geneve");
ce6fcb3f 10708#endif
0c22b3dd 10709 if (pf->flags & I40E_FLAG_PTP)
3b195843 10710 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10711#ifdef I40E_FCOE
10712 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10713 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10714#endif
6dec1017 10715 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10716 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10717 else
3b195843 10718 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10719
3b195843
JP		 10720 dev_info(&pf->pdev->dev, "%s\n", buf);
10721 kfree(buf);
7fd89545 10722 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10723}
10724
b499ffb0
SV		 10725/**
10726 * i40e_get_platform_mac_addr - get platform-specific MAC address
10727 *
10728 * @pdev: PCI device information struct
10729 * @pf: board private structure
10730 *
10731 * Look up the MAC address in Open Firmware on systems that support it,
10732 * and use IDPROM on SPARC if no OF address is found. On return, the
10733 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value
10734 * has been selected.
10735 **/
10736static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
10737{
b499ffb0 10738 pf->flags &= ~I40E_FLAG_PF_MAC;
ba94272d 10739 if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr))
b499ffb0 10740 pf->flags |= I40E_FLAG_PF_MAC;
b499ffb0
SV		 10741}
10742
41c445ff
JB		 10743/**
10744 * i40e_probe - Device initialization routine
10745 * @pdev: PCI device information struct
10746 * @ent: entry in i40e_pci_tbl
10747 *
b40c82e6
JK		 10748 * i40e_probe initializes a PF identified by a pci_dev structure.
10749 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10750 * and a hardware reset occur.
10751 *
10752 * Returns 0 on success, negative on failure
10753 **/
10754static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10755{
e827845c 10756 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10757 struct i40e_pf *pf;
10758 struct i40e_hw *hw;
93cd765b 10759 static u16 pfs_found;
1d5109d1 10760 u16 wol_nvm_bits;
d4dfb81a 10761 u16 link_status;
6f66a484 10762 int err;
4f2f017c 10763 u32 val;
8a9eb7d3 10764 u32 i;
58fc3267 10765 u8 set_fc_aq_fail;
41c445ff
JB		 10766
10767 err = pci_enable_device_mem(pdev);
10768 if (err)
10769 return err;
10770
10771 /* set up for high or low dma */
6494294f 10772 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10773 if (err) {
e3e3bfdd
JS		 10774 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10775 if (err) {
10776 dev_err(&pdev->dev,
10777 "DMA configuration failed: 0x%x\n", err);
10778 goto err_dma;
10779 }
41c445ff
JB		 10780 }
10781
10782 /* set up pci connections */
10783 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10784 IORESOURCE_MEM), i40e_driver_name);
10785 if (err) {
10786 dev_info(&pdev->dev,
10787 "pci_request_selected_regions failed %d\n", err);
10788 goto err_pci_reg;
10789 }
10790
10791 pci_enable_pcie_error_reporting(pdev);
10792 pci_set_master(pdev);
10793
10794 /* Now that we have a PCI connection, we need to do the
10795 * low level device setup. This is primarily setting up
10796 * the Admin Queue structures and then querying for the
10797 * device's current profile information.
10798 */
10799 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10800 if (!pf) {
10801 err = -ENOMEM;
10802 goto err_pf_alloc;
10803 }
10804 pf->next_vsi = 0;
10805 pf->pdev = pdev;
10806 set_bit(__I40E_DOWN, &pf->state);
10807
10808 hw = &pf->hw;
10809 hw->back = pf;
232f4706 10810
2ac8b675
SN		 10811 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10812 I40E_MAX_CSR_SPACE);
232f4706 10813
2ac8b675 10814 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10815 if (!hw->hw_addr) {
10816 err = -EIO;
10817 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10818 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10819 pf->ioremap_len, err);
41c445ff
JB		 10820 goto err_ioremap;
10821 }
10822 hw->vendor_id = pdev->vendor;
10823 hw->device_id = pdev->device;
10824 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10825 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10826 hw->subsystem_device_id = pdev->subsystem_device;
10827 hw->bus.device = PCI_SLOT(pdev->devfn);
10828 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10829 pf->instance = pfs_found;
41c445ff 10830
de03d2b0
SN		 10831 /* set up the locks for the AQ, do this only once in probe
10832 * and destroy them only once in remove
10833 */
10834 mutex_init(&hw->aq.asq_mutex);
10835 mutex_init(&hw->aq.arq_mutex);
10836
5b5faa43
SN		 10837 if (debug != -1) {
10838 pf->msg_enable = pf->hw.debug_mask;
10839 pf->msg_enable = debug;
10840 }
10841
7134f9ce
JB		 10842 /* do a special CORER for clearing PXE mode once at init */
10843 if (hw->revision_id == 0 &&
10844 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10845 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10846 i40e_flush(hw);
10847 msleep(200);
10848 pf->corer_count++;
10849
10850 i40e_clear_pxe_mode(hw);
10851 }
10852
41c445ff 10853 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10854 i40e_clear_hw(hw);
41c445ff
JB		 10855 err = i40e_pf_reset(hw);
10856 if (err) {
10857 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10858 goto err_pf_reset;
10859 }
10860 pf->pfr_count++;
10861
10862 hw->aq.num_arq_entries = I40E_AQ_LEN;
10863 hw->aq.num_asq_entries = I40E_AQ_LEN;
10864 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10865 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10866 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10867
b294ac70 10868 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10869 "%s-%s:misc",
10870 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10871
10872 err = i40e_init_shared_code(hw);
10873 if (err) {
b2a75c58
ASJ		 10874 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10875 err);
41c445ff
JB		 10876 goto err_pf_reset;
10877 }
10878
d52c20b7
JB		 10879 /* set up a default setting for link flow control */
10880 pf->hw.fc.requested_mode = I40E_FC_NONE;
10881
41c445ff 10882 err = i40e_init_adminq(hw);
2b2426a7
CW		 10883 if (err) {
10884 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10885 dev_info(&pdev->dev,
10886 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10887 else
10888 dev_info(&pdev->dev,
10889 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10890
10891 goto err_pf_reset;
10892 }
f0b44440 10893
6dec1017
SN		 10894 /* provide nvm, fw, api versions */
10895 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10896 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10897 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10898 i40e_nvm_version_str(hw));
f0b44440 10899
7aa67613
CS		 10900 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10901 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10902 dev_info(&pdev->dev,
7aa67613
CS		 10903 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10904 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10905 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10906 dev_info(&pdev->dev,
7aa67613 10907 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10908
4eb3f768
SN		 10909 i40e_verify_eeprom(pf);
10910
2c5fe33b
JB		 10911 /* Rev 0 hardware was never productized */
10912 if (hw->revision_id < 1)
10913 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10914
6ff4ef86 10915 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10916 err = i40e_get_capabilities(pf);
10917 if (err)
10918 goto err_adminq_setup;
10919
10920 err = i40e_sw_init(pf);
10921 if (err) {
10922 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10923 goto err_sw_init;
10924 }
10925
10926 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10927 hw->func_caps.num_rx_qp,
10928 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10929 if (err) {
10930 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10931 goto err_init_lan_hmc;
10932 }
10933
10934 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10935 if (err) {
10936 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10937 err = -ENOENT;
10938 goto err_configure_lan_hmc;
10939 }
10940
b686ece5
NP		 10941 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10942 * Ignore error return codes because if it was already disabled via
10943 * hardware settings this will fail
10944 */
f1bbad33 10945 if (pf->flags & I40E_FLAG_STOP_FW_LLDP) {
b686ece5
NP		 10946 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10947 i40e_aq_stop_lldp(hw, true, NULL);
10948 }
10949
41c445ff 10950 i40e_get_mac_addr(hw, hw->mac.addr);
b499ffb0
SV		 10951 /* allow a platform config to override the HW addr */
10952 i40e_get_platform_mac_addr(pdev, pf);
f62b5060 10953 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10954 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10955 err = -EIO;
10956 goto err_mac_addr;
10957 }
10958 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10959 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10960 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10961 if (is_valid_ether_addr(hw->mac.port_addr))
10962 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10963#ifdef I40E_FCOE
10964 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10965 if (err)
10966 dev_info(&pdev->dev,
10967 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10968 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10969 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10970 hw->mac.san_addr);
10971 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10972 }
10973 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10974#endif /* I40E_FCOE */
41c445ff
JB		 10975
10976 pci_set_drvdata(pdev, pf);
10977 pci_save_state(pdev);
4e3b35b0
NP		 10978#ifdef CONFIG_I40E_DCB
10979 err = i40e_init_pf_dcb(pf);
10980 if (err) {
aebfc816 10981 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10982 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10983 /* Continue without DCB enabled */
4e3b35b0
NP		 10984 }
10985#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10986
10987 /* set up periodic task facility */
10988 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10989 pf->service_timer_period = HZ;
10990
10991 INIT_WORK(&pf->service_task, i40e_service_task);
10992 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10993 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10994
1d5109d1
SN		 10995 /* NVM bit on means WoL disabled for the port */
10996 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10997 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10998 pf->wol_en = false;
10999 else
11000 pf->wol_en = true;
8e2773ae
SN		 11001 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
11002
41c445ff
JB		 11003 /* set up the main switch operations */
11004 i40e_determine_queue_usage(pf);
c1147280
JB		 11005 err = i40e_init_interrupt_scheme(pf);
11006 if (err)
11007 goto err_switch_setup;
41c445ff 11008
505682cd
MW		 11009 /* The number of VSIs reported by the FW is the minimum guaranteed
11010 * to us; HW supports far more and we share the remaining pool with
11011 * the other PFs. We allocate space for more than the guarantee with
11012 * the understanding that we might not get them all later.
41c445ff 11013 */
505682cd
MW		 11014 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
11015 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
11016 else
11017 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
11018
11019 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
d17038d6
JB		 11020 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
11021 GFP_KERNEL);
ed87ac09
WY		 11022 if (!pf->vsi) {
11023 err = -ENOMEM;
41c445ff 11024 goto err_switch_setup;
ed87ac09 11025 }
41c445ff 11026
fa11cb3d
ASJ		 11027#ifdef CONFIG_PCI_IOV
11028 /* prep for VF support */
11029 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
11030 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11031 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
11032 if (pci_num_vf(pdev))
11033 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
11034 }
11035#endif
bc7d338f 11036 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 11037 if (err) {
11038 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
11039 goto err_vsis;
11040 }
58fc3267
HZ		 11041
11042 /* Make sure flow control is set according to current settings */
11043 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
11044 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
11045 dev_dbg(&pf->pdev->dev,
11046 "Set fc with err %s aq_err %s on get_phy_cap\n",
11047 i40e_stat_str(hw, err),
11048 i40e_aq_str(hw, hw->aq.asq_last_status));
11049 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
11050 dev_dbg(&pf->pdev->dev,
11051 "Set fc with err %s aq_err %s on set_phy_config\n",
11052 i40e_stat_str(hw, err),
11053 i40e_aq_str(hw, hw->aq.asq_last_status));
11054 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
11055 dev_dbg(&pf->pdev->dev,
11056 "Set fc with err %s aq_err %s on get_link_info\n",
11057 i40e_stat_str(hw, err),
11058 i40e_aq_str(hw, hw->aq.asq_last_status));
11059
8a9eb7d3 11060 /* if FDIR VSI was set up, start it now */
505682cd 11061 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 11062 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
11063 i40e_vsi_open(pf->vsi[i]);
11064 break;
11065 }
11066 }
41c445ff 11067
2f0aff41
SN		 11068 /* The driver only wants link up/down and module qualification
11069 * reports from firmware. Note the negative logic.
7e2453fe
JB		 11070 */
11071 err = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 11072 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 11073 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 11074 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 11075 if (err)
f1c7e72e
SN		 11076 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
11077 i40e_stat_str(&pf->hw, err),
11078 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 11079
4f2f017c
ASJ		 11080 /* Reconfigure hardware for allowing smaller MSS in the case
11081 * of TSO, so that we avoid the MDD being fired and causing
11082 * a reset in the case of small MSS+TSO.
11083 */
11084 val = rd32(hw, I40E_REG_MSS);
11085 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
11086 val &= ~I40E_REG_MSS_MIN_MASK;
11087 val |= I40E_64BYTE_MSS;
11088 wr32(hw, I40E_REG_MSS, val);
11089 }
11090
8eed76fa 11091 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 11092 msleep(75);
11093 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
11094 if (err)
f1c7e72e
SN		 11095 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
11096 i40e_stat_str(&pf->hw, err),
11097 i40e_aq_str(&pf->hw,
11098 pf->hw.aq.asq_last_status));
cafa2ee6 11099 }
41c445ff
JB		 11100 /* The main driver is (mostly) up and happy. We need to set this state
11101 * before setting up the misc vector or we get a race and the vector
11102 * ends up disabled forever.
11103 */
11104 clear_bit(__I40E_DOWN, &pf->state);
11105
11106 /* In case of MSIX we are going to setup the misc vector right here
11107 * to handle admin queue events etc. In case of legacy and MSI
11108 * the misc functionality and queue processing is combined in
11109 * the same vector and that gets setup at open.
11110 */
11111 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
11112 err = i40e_setup_misc_vector(pf);
11113 if (err) {
11114 dev_info(&pdev->dev,
11115 "setup of misc vector failed: %d\n", err);
11116 goto err_vsis;
11117 }
11118 }
11119
df805f62 11120#ifdef CONFIG_PCI_IOV
41c445ff
JB		 11121 /* prep for VF support */
11122 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 11123 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11124 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 11125 /* disable link interrupts for VFs */
11126 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
11127 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
11128 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
11129 i40e_flush(hw);
4aeec010
MW		 11130
11131 if (pci_num_vf(pdev)) {
11132 dev_info(&pdev->dev,
11133 "Active VFs found, allocating resources.\n");
11134 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
11135 if (err)
11136 dev_info(&pdev->dev,
11137 "Error %d allocating resources for existing VFs\n",
11138 err);
11139 }
41c445ff 11140 }
df805f62 11141#endif /* CONFIG_PCI_IOV */
41c445ff 11142
e3219ce6
ASJ		 11143 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
11144 pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile,
11145 pf->num_iwarp_msix,
11146 I40E_IWARP_IRQ_PILE_ID);
11147 if (pf->iwarp_base_vector < 0) {
11148 dev_info(&pdev->dev,
11149 "failed to get tracking for %d vectors for IWARP err=%d\n",
11150 pf->num_iwarp_msix, pf->iwarp_base_vector);
11151 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
11152 }
11153 }
93cd765b 11154
41c445ff
JB		 11155 i40e_dbg_pf_init(pf);
11156
11157 /* tell the firmware that we're starting */
44033fac 11158 i40e_send_version(pf);
41c445ff
JB		 11159
11160 /* since everything's happy, start the service_task timer */
11161 mod_timer(&pf->service_timer,
11162 round_jiffies(jiffies + pf->service_timer_period));
11163
e3219ce6
ASJ		 11164 /* add this PF to client device list and launch a client service task */
11165 err = i40e_lan_add_device(pf);
11166 if (err)
11167 dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n",
11168 err);
11169
38e00438
VD		 11170#ifdef I40E_FCOE
11171 /* create FCoE interface */
11172 i40e_fcoe_vsi_setup(pf);
11173
11174#endif
3fced535
ASJ		 11175#define PCI_SPEED_SIZE 8
11176#define PCI_WIDTH_SIZE 8
11177 /* Devices on the IOSF bus do not have this information
11178 * and will report PCI Gen 1 x 1 by default so don't bother
11179 * checking them.
11180 */
11181 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
11182 char speed[PCI_SPEED_SIZE] = "Unknown";
11183 char width[PCI_WIDTH_SIZE] = "Unknown";
11184
11185 /* Get the negotiated link width and speed from PCI config
11186 * space
11187 */
11188 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
11189 &link_status);
11190
11191 i40e_set_pci_config_data(hw, link_status);
11192
11193 switch (hw->bus.speed) {
11194 case i40e_bus_speed_8000:
11195 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
11196 case i40e_bus_speed_5000:
11197 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
11198 case i40e_bus_speed_2500:
11199 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
11200 default:
11201 break;
11202 }
11203 switch (hw->bus.width) {
11204 case i40e_bus_width_pcie_x8:
11205 strncpy(width, "8", PCI_WIDTH_SIZE); break;
11206 case i40e_bus_width_pcie_x4:
11207 strncpy(width, "4", PCI_WIDTH_SIZE); break;
11208 case i40e_bus_width_pcie_x2:
11209 strncpy(width, "2", PCI_WIDTH_SIZE); break;
11210 case i40e_bus_width_pcie_x1:
11211 strncpy(width, "1", PCI_WIDTH_SIZE); break;
11212 default:
11213 break;
11214 }
11215
11216 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
11217 speed, width);
11218
11219 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
11220 hw->bus.speed < i40e_bus_speed_8000) {
11221 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
11222 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
11223 }
d4dfb81a
CS		 11224 }
11225
e827845c
CS		 11226 /* get the requested speeds from the fw */
11227 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
11228 if (err)
8279e495
NP		 11229 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
11230 i40e_stat_str(&pf->hw, err),
11231 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 11232 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
11233
fc72dbce
CS		 11234 /* get the supported phy types from the fw */
11235 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
11236 if (err)
11237 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
11238 i40e_stat_str(&pf->hw, err),
11239 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11240 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
11241
e7358f54
ASJ		 11242 /* Add a filter to drop all Flow control frames from any VSI from being
11243 * transmitted. By doing so we stop a malicious VF from sending out
11244 * PAUSE or PFC frames and potentially controlling traffic for other
11245 * PF/VF VSIs.
11246 * The FW can still send Flow control frames if enabled.
11247 */
11248 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11249 pf->main_vsi_seid);
11250
31b606d0
CW		 11251 if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
11252 (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
11253 pf->flags |= I40E_FLAG_HAVE_10GBASET_PHY;
11254
0c22b3dd
JB		 11255 /* print a string summarizing features */
11256 i40e_print_features(pf);
11257
41c445ff
JB		 11258 return 0;
11259
11260 /* Unwind what we've done if something failed in the setup */
11261err_vsis:
11262 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 11263 i40e_clear_interrupt_scheme(pf);
11264 kfree(pf->vsi);
04b03013
SN		 11265err_switch_setup:
11266 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 11267 del_timer_sync(&pf->service_timer);
11268err_mac_addr:
11269err_configure_lan_hmc:
11270 (void)i40e_shutdown_lan_hmc(hw);
11271err_init_lan_hmc:
11272 kfree(pf->qp_pile);
41c445ff
JB		 11273err_sw_init:
11274err_adminq_setup:
41c445ff
JB		 11275err_pf_reset:
11276 iounmap(hw->hw_addr);
11277err_ioremap:
11278 kfree(pf);
11279err_pf_alloc:
11280 pci_disable_pcie_error_reporting(pdev);
11281 pci_release_selected_regions(pdev,
11282 pci_select_bars(pdev, IORESOURCE_MEM));
11283err_pci_reg:
11284err_dma:
11285 pci_disable_device(pdev);
11286 return err;
11287}
11288
11289/**
11290 * i40e_remove - Device removal routine
11291 * @pdev: PCI device information struct
11292 *
11293 * i40e_remove is called by the PCI subsystem to alert the driver
11294 * that is should release a PCI device. This could be caused by a
11295 * Hot-Plug event, or because the driver is going to be removed from
11296 * memory.
11297 **/
11298static void i40e_remove(struct pci_dev *pdev)
11299{
11300 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11301 struct i40e_hw *hw = &pf->hw;
41c445ff 11302 i40e_status ret_code;
41c445ff
JB		 11303 int i;
11304
11305 i40e_dbg_pf_exit(pf);
11306
beb0dff1
JK		 11307 i40e_ptp_stop(pf);
11308
bcab2db9 11309 /* Disable RSS in hw */
272cdaf2
SN		 11310 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
11311 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
bcab2db9 11312
41c445ff 11313 /* no more scheduling of any task */
a4618ec8 11314 set_bit(__I40E_SUSPENDED, &pf->state);
41c445ff 11315 set_bit(__I40E_DOWN, &pf->state);
c99abb4c
SN		 11316 if (pf->service_timer.data)
11317 del_timer_sync(&pf->service_timer);
11318 if (pf->service_task.func)
11319 cancel_work_sync(&pf->service_task);
41c445ff 11320
eb2d80bc
MW		 11321 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11322 i40e_free_vfs(pf);
11323 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11324 }
11325
41c445ff
JB		 11326 i40e_fdir_teardown(pf);
11327
11328 /* If there is a switch structure or any orphans, remove them.
11329 * This will leave only the PF's VSI remaining.
11330 */
11331 for (i = 0; i < I40E_MAX_VEB; i++) {
11332 if (!pf->veb[i])
11333 continue;
11334
11335 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11336 pf->veb[i]->uplink_seid == 0)
11337 i40e_switch_branch_release(pf->veb[i]);
11338 }
11339
11340 /* Now we can shutdown the PF's VSI, just before we kill
11341 * adminq and hmc.
11342 */
11343 if (pf->vsi[pf->lan_vsi])
11344 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11345
e3219ce6
ASJ		 11346 /* remove attached clients */
11347 ret_code = i40e_lan_del_device(pf);
11348 if (ret_code) {
11349 dev_warn(&pdev->dev, "Failed to delete client device: %d\n",
11350 ret_code);
11351 }
11352
41c445ff 11353 /* shutdown and destroy the HMC */
f734dfff
JB		 11354 if (hw->hmc.hmc_obj) {
11355 ret_code = i40e_shutdown_lan_hmc(hw);
60442dea
SN		 11356 if (ret_code)
11357 dev_warn(&pdev->dev,
11358 "Failed to destroy the HMC resources: %d\n",
11359 ret_code);
11360 }
41c445ff
JB		 11361
11362 /* shutdown the adminq */
f734dfff 11363 ret_code = i40e_shutdown_adminq(hw);
41c445ff
JB		 11364 if (ret_code)
11365 dev_warn(&pdev->dev,
11366 "Failed to destroy the Admin Queue resources: %d\n",
11367 ret_code);
11368
8ddb3326
JB		 11369 /* destroy the locks only once, here */
11370 mutex_destroy(&hw->aq.arq_mutex);
11371 mutex_destroy(&hw->aq.asq_mutex);
11372
41c445ff
JB		 11373 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11374 i40e_clear_interrupt_scheme(pf);
505682cd 11375 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11376 if (pf->vsi[i]) {
11377 i40e_vsi_clear_rings(pf->vsi[i]);
11378 i40e_vsi_clear(pf->vsi[i]);
11379 pf->vsi[i] = NULL;
11380 }
11381 }
11382
11383 for (i = 0; i < I40E_MAX_VEB; i++) {
11384 kfree(pf->veb[i]);
11385 pf->veb[i] = NULL;
11386 }
11387
11388 kfree(pf->qp_pile);
41c445ff
JB		 11389 kfree(pf->vsi);
11390
f734dfff 11391 iounmap(hw->hw_addr);
41c445ff
JB		 11392 kfree(pf);
11393 pci_release_selected_regions(pdev,
11394 pci_select_bars(pdev, IORESOURCE_MEM));
11395
11396 pci_disable_pcie_error_reporting(pdev);
11397 pci_disable_device(pdev);
11398}
11399
11400/**
11401 * i40e_pci_error_detected - warning that something funky happened in PCI land
11402 * @pdev: PCI device information struct
11403 *
11404 * Called to warn that something happened and the error handling steps
11405 * are in progress. Allows the driver to quiesce things, be ready for
11406 * remediation.
11407 **/
11408static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11409 enum pci_channel_state error)
11410{
11411 struct i40e_pf *pf = pci_get_drvdata(pdev);
11412
11413 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11414
11415 /* shutdown all operations */
9007bccd
SN		 11416 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11417 rtnl_lock();
11418 i40e_prep_for_reset(pf);
11419 rtnl_unlock();
11420 }
41c445ff
JB		 11421
11422 /* Request a slot reset */
11423 return PCI_ERS_RESULT_NEED_RESET;
11424}
11425
11426/**
11427 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11428 * @pdev: PCI device information struct
11429 *
11430 * Called to find if the driver can work with the device now that
11431 * the pci slot has been reset. If a basic connection seems good
11432 * (registers are readable and have sane content) then return a
11433 * happy little PCI_ERS_RESULT_xxx.
11434 **/
11435static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11436{
11437 struct i40e_pf *pf = pci_get_drvdata(pdev);
11438 pci_ers_result_t result;
11439 int err;
11440 u32 reg;
11441
fb43201f 11442 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11443 if (pci_enable_device_mem(pdev)) {
11444 dev_info(&pdev->dev,
11445 "Cannot re-enable PCI device after reset.\n");
11446 result = PCI_ERS_RESULT_DISCONNECT;
11447 } else {
11448 pci_set_master(pdev);
11449 pci_restore_state(pdev);
11450 pci_save_state(pdev);
11451 pci_wake_from_d3(pdev, false);
11452
11453 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11454 if (reg == 0)
11455 result = PCI_ERS_RESULT_RECOVERED;
11456 else
11457 result = PCI_ERS_RESULT_DISCONNECT;
11458 }
11459
11460 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11461 if (err) {
11462 dev_info(&pdev->dev,
11463 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11464 err);
11465 /* non-fatal, continue */
11466 }
11467
11468 return result;
11469}
11470
11471/**
11472 * i40e_pci_error_resume - restart operations after PCI error recovery
11473 * @pdev: PCI device information struct
11474 *
11475 * Called to allow the driver to bring things back up after PCI error
11476 * and/or reset recovery has finished.
11477 **/
11478static void i40e_pci_error_resume(struct pci_dev *pdev)
11479{
11480 struct i40e_pf *pf = pci_get_drvdata(pdev);
11481
fb43201f 11482 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11483 if (test_bit(__I40E_SUSPENDED, &pf->state))
11484 return;
11485
11486 rtnl_lock();
41c445ff 11487 i40e_handle_reset_warning(pf);
4c4935a9 11488 rtnl_unlock();
9007bccd
SN		 11489}
11490
11491/**
11492 * i40e_shutdown - PCI callback for shutting down
11493 * @pdev: PCI device information struct
11494 **/
11495static void i40e_shutdown(struct pci_dev *pdev)
11496{
11497 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11498 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11499
11500 set_bit(__I40E_SUSPENDED, &pf->state);
11501 set_bit(__I40E_DOWN, &pf->state);
11502 rtnl_lock();
11503 i40e_prep_for_reset(pf);
11504 rtnl_unlock();
11505
8e2773ae
SN		 11506 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11507 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11508
02b42498
CS		 11509 del_timer_sync(&pf->service_timer);
11510 cancel_work_sync(&pf->service_task);
11511 i40e_fdir_teardown(pf);
11512
11513 rtnl_lock();
11514 i40e_prep_for_reset(pf);
11515 rtnl_unlock();
11516
11517 wr32(hw, I40E_PFPM_APM,
11518 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11519 wr32(hw, I40E_PFPM_WUFC,
11520 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11521
e147758d
SN		 11522 i40e_clear_interrupt_scheme(pf);
11523
9007bccd 11524 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11525 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11526 pci_set_power_state(pdev, PCI_D3hot);
11527 }
11528}
11529
11530#ifdef CONFIG_PM
11531/**
11532 * i40e_suspend - PCI callback for moving to D3
11533 * @pdev: PCI device information struct
11534 **/
11535static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11536{
11537 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11538 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11539
11540 set_bit(__I40E_SUSPENDED, &pf->state);
11541 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11542
9007bccd
SN		 11543 rtnl_lock();
11544 i40e_prep_for_reset(pf);
11545 rtnl_unlock();
11546
8e2773ae
SN		 11547 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11548 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11549
11550 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11551 pci_set_power_state(pdev, PCI_D3hot);
11552
11553 return 0;
41c445ff
JB		 11554}
11555
9007bccd
SN		 11556/**
11557 * i40e_resume - PCI callback for waking up from D3
11558 * @pdev: PCI device information struct
11559 **/
11560static int i40e_resume(struct pci_dev *pdev)
11561{
11562 struct i40e_pf *pf = pci_get_drvdata(pdev);
11563 u32 err;
11564
11565 pci_set_power_state(pdev, PCI_D0);
11566 pci_restore_state(pdev);
11567 /* pci_restore_state() clears dev->state_saves, so
11568 * call pci_save_state() again to restore it.
11569 */
11570 pci_save_state(pdev);
11571
11572 err = pci_enable_device_mem(pdev);
11573 if (err) {
fb43201f 11574 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11575 return err;
11576 }
11577 pci_set_master(pdev);
11578
11579 /* no wakeup events while running */
11580 pci_wake_from_d3(pdev, false);
11581
11582 /* handling the reset will rebuild the device state */
11583 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11584 clear_bit(__I40E_DOWN, &pf->state);
11585 rtnl_lock();
11586 i40e_reset_and_rebuild(pf, false);
11587 rtnl_unlock();
11588 }
11589
11590 return 0;
11591}
11592
11593#endif
41c445ff
JB		 11594static const struct pci_error_handlers i40e_err_handler = {
11595 .error_detected = i40e_pci_error_detected,
11596 .slot_reset = i40e_pci_error_slot_reset,
11597 .resume = i40e_pci_error_resume,
11598};
11599
11600static struct pci_driver i40e_driver = {
11601 .name = i40e_driver_name,
11602 .id_table = i40e_pci_tbl,
11603 .probe = i40e_probe,
11604 .remove = i40e_remove,
9007bccd
SN		 11605#ifdef CONFIG_PM
11606 .suspend = i40e_suspend,
11607 .resume = i40e_resume,
11608#endif
11609 .shutdown = i40e_shutdown,
41c445ff
JB		 11610 .err_handler = &i40e_err_handler,
11611 .sriov_configure = i40e_pci_sriov_configure,
11612};
11613
11614/**
11615 * i40e_init_module - Driver registration routine
11616 *
11617 * i40e_init_module is the first routine called when the driver is
11618 * loaded. All it does is register with the PCI subsystem.
11619 **/
11620static int __init i40e_init_module(void)
11621{
11622 pr_info("%s: %s - version %s\n", i40e_driver_name,
11623 i40e_driver_string, i40e_driver_version_str);
11624 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11625
2803b16c
JB		 11626 /* we will see if single thread per module is enough for now,
11627 * it can't be any worse than using the system workqueue which
11628 * was already single threaded
11629 */
11630 i40e_wq = create_singlethread_workqueue(i40e_driver_name);
11631 if (!i40e_wq) {
11632 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
11633 return -ENOMEM;
11634 }
11635
41c445ff
JB		 11636 i40e_dbg_init();
11637 return pci_register_driver(&i40e_driver);
11638}
11639module_init(i40e_init_module);
11640
11641/**
11642 * i40e_exit_module - Driver exit cleanup routine
11643 *
11644 * i40e_exit_module is called just before the driver is removed
11645 * from memory.
11646 **/
11647static void __exit i40e_exit_module(void)
11648{
11649 pci_unregister_driver(&i40e_driver);
2803b16c 11650 destroy_workqueue(i40e_wq);
41c445ff
JB		 11651 i40e_dbg_exit();
11652}
11653module_exit(i40e_exit_module);
Linux kernel - Deliverables
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