projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'for-linus-v4.8' of git://github.com/martinbrandenburg/linux
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
2818ccd9 4 * Copyright(c) 2013 - 2016 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
b499ffb0
SV		 27#include <linux/etherdevice.h>
28#include <linux/of_net.h>
29#include <linux/pci.h>
30
41c445ff
JB		 31/* Local includes */
32#include "i40e.h"
4eb3f768 33#include "i40e_diag.h"
06a5f7f1 34#include <net/udp_tunnel.h>
41c445ff
JB		 35
36const char i40e_driver_name[] = "i40e";
37static const char i40e_driver_string[] =
38 "Intel(R) Ethernet Connection XL710 Network Driver";
39
40#define DRV_KERN "-k"
41
e8e724db 42#define DRV_VERSION_MAJOR 1
07061958 43#define DRV_VERSION_MINOR 6
ae33256c 44#define DRV_VERSION_BUILD 11
41c445ff
JB		 45#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
46 __stringify(DRV_VERSION_MINOR) "." \
47 __stringify(DRV_VERSION_BUILD) DRV_KERN
48const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 49static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 50
51/* a bit of forward declarations */
52static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
53static void i40e_handle_reset_warning(struct i40e_pf *pf);
54static int i40e_add_vsi(struct i40e_vsi *vsi);
55static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 56static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 57static int i40e_setup_misc_vector(struct i40e_pf *pf);
58static void i40e_determine_queue_usage(struct i40e_pf *pf);
59static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 60static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
61 u16 rss_table_size, u16 rss_size);
cbf61325 62static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 63static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 64
65/* i40e_pci_tbl - PCI Device ID Table
66 *
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
9baa3c34 72static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
ab60085e
SN		 75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
35dae51d
ASJ		 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
87e6c1d7
ASJ		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
d6bf58c2 88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},
48a3b512
SN		 89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 91 /* required last entry */
92 {0, }
93};
94MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
95
96#define I40E_MAX_VF_COUNT 128
97static int debug = -1;
98module_param(debug, int, 0);
99MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
100
101MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
102MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
103MODULE_LICENSE("GPL");
104MODULE_VERSION(DRV_VERSION);
105
2803b16c
JB		 106static struct workqueue_struct *i40e_wq;
107
41c445ff
JB		 108/**
109 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
110 * @hw: pointer to the HW structure
111 * @mem: ptr to mem struct to fill out
112 * @size: size of memory requested
113 * @alignment: what to align the allocation to
114 **/
115int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
116 u64 size, u32 alignment)
117{
118 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
119
120 mem->size = ALIGN(size, alignment);
121 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
122 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 123 if (!mem->va)
124 return -ENOMEM;
41c445ff 125
93bc73b8 126 return 0;
41c445ff
JB		 127}
128
129/**
130 * i40e_free_dma_mem_d - OS specific memory free for shared code
131 * @hw: pointer to the HW structure
132 * @mem: ptr to mem struct to free
133 **/
134int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
135{
136 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
137
138 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
139 mem->va = NULL;
140 mem->pa = 0;
141 mem->size = 0;
142
143 return 0;
144}
145
146/**
147 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
148 * @hw: pointer to the HW structure
149 * @mem: ptr to mem struct to fill out
150 * @size: size of memory requested
151 **/
152int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
153 u32 size)
154{
155 mem->size = size;
156 mem->va = kzalloc(size, GFP_KERNEL);
157
93bc73b8
JB		 158 if (!mem->va)
159 return -ENOMEM;
41c445ff 160
93bc73b8 161 return 0;
41c445ff
JB		 162}
163
164/**
165 * i40e_free_virt_mem_d - OS specific memory free for shared code
166 * @hw: pointer to the HW structure
167 * @mem: ptr to mem struct to free
168 **/
169int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
170{
171 /* it's ok to kfree a NULL pointer */
172 kfree(mem->va);
173 mem->va = NULL;
174 mem->size = 0;
175
176 return 0;
177}
178
179/**
180 * i40e_get_lump - find a lump of free generic resource
181 * @pf: board private structure
182 * @pile: the pile of resource to search
183 * @needed: the number of items needed
184 * @id: an owner id to stick on the items assigned
185 *
186 * Returns the base item index of the lump, or negative for error
187 *
188 * The search_hint trick and lack of advanced fit-finding only work
189 * because we're highly likely to have all the same size lump requests.
190 * Linear search time and any fragmentation should be minimal.
191 **/
192static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
193 u16 needed, u16 id)
194{
195 int ret = -ENOMEM;
ddf434ac 196 int i, j;
41c445ff
JB		 197
198 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
199 dev_info(&pf->pdev->dev,
200 "param err: pile=%p needed=%d id=0x%04x\n",
201 pile, needed, id);
202 return -EINVAL;
203 }
204
205 /* start the linear search with an imperfect hint */
206 i = pile->search_hint;
ddf434ac 207 while (i < pile->num_entries) {
41c445ff
JB		 208 /* skip already allocated entries */
209 if (pile->list[i] & I40E_PILE_VALID_BIT) {
210 i++;
211 continue;
212 }
213
214 /* do we have enough in this lump? */
215 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
216 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
217 break;
218 }
219
220 if (j == needed) {
221 /* there was enough, so assign it to the requestor */
222 for (j = 0; j < needed; j++)
223 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
224 ret = i;
225 pile->search_hint = i + j;
ddf434ac 226 break;
41c445ff 227 }
6995b36c
JB		 228
229 /* not enough, so skip over it and continue looking */
230 i += j;
41c445ff
JB		 231 }
232
233 return ret;
234}
235
236/**
237 * i40e_put_lump - return a lump of generic resource
238 * @pile: the pile of resource to search
239 * @index: the base item index
240 * @id: the owner id of the items assigned
241 *
242 * Returns the count of items in the lump
243 **/
244static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
245{
246 int valid_id = (id | I40E_PILE_VALID_BIT);
247 int count = 0;
248 int i;
249
250 if (!pile || index >= pile->num_entries)
251 return -EINVAL;
252
253 for (i = index;
254 i < pile->num_entries && pile->list[i] == valid_id;
255 i++) {
256 pile->list[i] = 0;
257 count++;
258 }
259
260 if (count && index < pile->search_hint)
261 pile->search_hint = index;
262
263 return count;
264}
265
fdf0e0bf
ASJ		 266/**
267 * i40e_find_vsi_from_id - searches for the vsi with the given id
268 * @pf - the pf structure to search for the vsi
269 * @id - id of the vsi it is searching for
270 **/
271struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
272{
273 int i;
274
275 for (i = 0; i < pf->num_alloc_vsi; i++)
276 if (pf->vsi[i] && (pf->vsi[i]->id == id))
277 return pf->vsi[i];
278
279 return NULL;
280}
281
41c445ff
JB		 282/**
283 * i40e_service_event_schedule - Schedule the service task to wake up
284 * @pf: board private structure
285 *
286 * If not already scheduled, this puts the task into the work queue
287 **/
e3219ce6 288void i40e_service_event_schedule(struct i40e_pf *pf)
41c445ff
JB		 289{
290 if (!test_bit(__I40E_DOWN, &pf->state) &&
291 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
292 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
2803b16c 293 queue_work(i40e_wq, &pf->service_task);
41c445ff
JB		 294}
295
296/**
297 * i40e_tx_timeout - Respond to a Tx Hang
298 * @netdev: network interface device structure
299 *
300 * If any port has noticed a Tx timeout, it is likely that the whole
301 * device is munged, not just the one netdev port, so go for the full
302 * reset.
303 **/
38e00438
VD		 304#ifdef I40E_FCOE
305void i40e_tx_timeout(struct net_device *netdev)
306#else
41c445ff 307static void i40e_tx_timeout(struct net_device *netdev)
38e00438 308#endif
41c445ff
JB		 309{
310 struct i40e_netdev_priv *np = netdev_priv(netdev);
311 struct i40e_vsi *vsi = np->vsi;
312 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 313 struct i40e_ring *tx_ring = NULL;
314 unsigned int i, hung_queue = 0;
315 u32 head, val;
41c445ff
JB		 316
317 pf->tx_timeout_count++;
318
b03a8c1f
KP		 319 /* find the stopped queue the same way the stack does */
320 for (i = 0; i < netdev->num_tx_queues; i++) {
321 struct netdev_queue *q;
322 unsigned long trans_start;
323
324 q = netdev_get_tx_queue(netdev, i);
9b36627a 325 trans_start = q->trans_start;
b03a8c1f
KP		 326 if (netif_xmit_stopped(q) &&
327 time_after(jiffies,
328 (trans_start + netdev->watchdog_timeo))) {
329 hung_queue = i;
330 break;
331 }
332 }
333
334 if (i == netdev->num_tx_queues) {
335 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
336 } else {
337 /* now that we have an index, find the tx_ring struct */
338 for (i = 0; i < vsi->num_queue_pairs; i++) {
339 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
340 if (hung_queue ==
341 vsi->tx_rings[i]->queue_index) {
342 tx_ring = vsi->tx_rings[i];
343 break;
344 }
345 }
346 }
347 }
348
41c445ff 349 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 350 pf->tx_timeout_recovery_level = 1; /* reset after some time */
351 else if (time_before(jiffies,
352 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
353 return; /* don't do any new action before the next timeout */
354
355 if (tx_ring) {
356 head = i40e_get_head(tx_ring);
357 /* Read interrupt register */
358 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
359 val = rd32(&pf->hw,
360 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
361 tx_ring->vsi->base_vector - 1));
362 else
363 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
364
365 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
366 vsi->seid, hung_queue, tx_ring->next_to_clean,
367 head, tx_ring->next_to_use,
368 readl(tx_ring->tail), val);
369 }
370
41c445ff 371 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 372 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
373 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 374
375 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 376 case 1:
377 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
378 break;
379 case 2:
380 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
381 break;
382 case 3:
383 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
384 break;
385 default:
386 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 387 break;
388 }
b03a8c1f 389
41c445ff
JB		 390 i40e_service_event_schedule(pf);
391 pf->tx_timeout_recovery_level++;
392}
393
41c445ff
JB		 394/**
395 * i40e_get_vsi_stats_struct - Get System Network Statistics
396 * @vsi: the VSI we care about
397 *
398 * Returns the address of the device statistics structure.
399 * The statistics are actually updated from the service task.
400 **/
401struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
402{
403 return &vsi->net_stats;
404}
405
406/**
407 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
408 * @netdev: network interface device structure
409 *
410 * Returns the address of the device statistics structure.
411 * The statistics are actually updated from the service task.
412 **/
38e00438
VD		 413#ifdef I40E_FCOE
414struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
415 struct net_device *netdev,
416 struct rtnl_link_stats64 *stats)
417#else
41c445ff
JB		 418static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
419 struct net_device *netdev,
980e9b11 420 struct rtnl_link_stats64 *stats)
38e00438 421#endif
41c445ff
JB		 422{
423 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 424 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 425 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 426 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
427 int i;
428
bc7d338f
ASJ		 429 if (test_bit(__I40E_DOWN, &vsi->state))
430 return stats;
431
3c325ced
JB		 432 if (!vsi->tx_rings)
433 return stats;
434
980e9b11
AD		 435 rcu_read_lock();
436 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 437 u64 bytes, packets;
438 unsigned int start;
439
440 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
441 if (!tx_ring)
442 continue;
443
444 do {
57a7744e 445 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 446 packets = tx_ring->stats.packets;
447 bytes = tx_ring->stats.bytes;
57a7744e 448 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 449
450 stats->tx_packets += packets;
451 stats->tx_bytes += bytes;
452 rx_ring = &tx_ring[1];
453
454 do {
57a7744e 455 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 456 packets = rx_ring->stats.packets;
457 bytes = rx_ring->stats.bytes;
57a7744e 458 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 459
980e9b11
AD		 460 stats->rx_packets += packets;
461 stats->rx_bytes += bytes;
462 }
463 rcu_read_unlock();
464
a5282f44 465 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 466 stats->multicast = vsi_stats->multicast;
467 stats->tx_errors = vsi_stats->tx_errors;
468 stats->tx_dropped = vsi_stats->tx_dropped;
469 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 470 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 471 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
472 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 473
980e9b11 474 return stats;
41c445ff
JB		 475}
476
477/**
478 * i40e_vsi_reset_stats - Resets all stats of the given vsi
479 * @vsi: the VSI to have its stats reset
480 **/
481void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
482{
483 struct rtnl_link_stats64 *ns;
484 int i;
485
486 if (!vsi)
487 return;
488
489 ns = i40e_get_vsi_stats_struct(vsi);
490 memset(ns, 0, sizeof(*ns));
491 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
492 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
493 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 494 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 495 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 496 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 497 sizeof(vsi->rx_rings[i]->stats));
6995b36c 498 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 499 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 500 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 501 sizeof(vsi->tx_rings[i]->stats));
502 memset(&vsi->tx_rings[i]->tx_stats, 0,
503 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 504 }
8e9dca53 505 }
41c445ff
JB		 506 vsi->stat_offsets_loaded = false;
507}
508
509/**
b40c82e6 510 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 511 * @pf: the PF to be reset
512 **/
513void i40e_pf_reset_stats(struct i40e_pf *pf)
514{
e91fdf76
SN		 515 int i;
516
41c445ff
JB		 517 memset(&pf->stats, 0, sizeof(pf->stats));
518 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
519 pf->stat_offsets_loaded = false;
e91fdf76
SN		 520
521 for (i = 0; i < I40E_MAX_VEB; i++) {
522 if (pf->veb[i]) {
523 memset(&pf->veb[i]->stats, 0,
524 sizeof(pf->veb[i]->stats));
525 memset(&pf->veb[i]->stats_offsets, 0,
526 sizeof(pf->veb[i]->stats_offsets));
527 pf->veb[i]->stat_offsets_loaded = false;
528 }
529 }
41c445ff
JB		 530}
531
532/**
533 * i40e_stat_update48 - read and update a 48 bit stat from the chip
534 * @hw: ptr to the hardware info
535 * @hireg: the high 32 bit reg to read
536 * @loreg: the low 32 bit reg to read
537 * @offset_loaded: has the initial offset been loaded yet
538 * @offset: ptr to current offset value
539 * @stat: ptr to the stat
540 *
541 * Since the device stats are not reset at PFReset, they likely will not
542 * be zeroed when the driver starts. We'll save the first values read
543 * and use them as offsets to be subtracted from the raw values in order
544 * to report stats that count from zero. In the process, we also manage
545 * the potential roll-over.
546 **/
547static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
548 bool offset_loaded, u64 *offset, u64 *stat)
549{
550 u64 new_data;
551
ab60085e 552 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 553 new_data = rd32(hw, loreg);
554 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
555 } else {
556 new_data = rd64(hw, loreg);
557 }
558 if (!offset_loaded)
559 *offset = new_data;
560 if (likely(new_data >= *offset))
561 *stat = new_data - *offset;
562 else
41a1d04b 563 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 564 *stat &= 0xFFFFFFFFFFFFULL;
565}
566
567/**
568 * i40e_stat_update32 - read and update a 32 bit stat from the chip
569 * @hw: ptr to the hardware info
570 * @reg: the hw reg to read
571 * @offset_loaded: has the initial offset been loaded yet
572 * @offset: ptr to current offset value
573 * @stat: ptr to the stat
574 **/
575static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
576 bool offset_loaded, u64 *offset, u64 *stat)
577{
578 u32 new_data;
579
580 new_data = rd32(hw, reg);
581 if (!offset_loaded)
582 *offset = new_data;
583 if (likely(new_data >= *offset))
584 *stat = (u32)(new_data - *offset);
585 else
41a1d04b 586 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 587}
588
589/**
590 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
591 * @vsi: the VSI to be updated
592 **/
593void i40e_update_eth_stats(struct i40e_vsi *vsi)
594{
595 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
596 struct i40e_pf *pf = vsi->back;
597 struct i40e_hw *hw = &pf->hw;
598 struct i40e_eth_stats *oes;
599 struct i40e_eth_stats *es; /* device's eth stats */
600
601 es = &vsi->eth_stats;
602 oes = &vsi->eth_stats_offsets;
603
604 /* Gather up the stats that the hw collects */
605 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
606 vsi->stat_offsets_loaded,
607 &oes->tx_errors, &es->tx_errors);
608 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
609 vsi->stat_offsets_loaded,
610 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 611 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
612 vsi->stat_offsets_loaded,
613 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
614 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
615 vsi->stat_offsets_loaded,
616 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 617
618 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
619 I40E_GLV_GORCL(stat_idx),
620 vsi->stat_offsets_loaded,
621 &oes->rx_bytes, &es->rx_bytes);
622 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
623 I40E_GLV_UPRCL(stat_idx),
624 vsi->stat_offsets_loaded,
625 &oes->rx_unicast, &es->rx_unicast);
626 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
627 I40E_GLV_MPRCL(stat_idx),
628 vsi->stat_offsets_loaded,
629 &oes->rx_multicast, &es->rx_multicast);
630 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
631 I40E_GLV_BPRCL(stat_idx),
632 vsi->stat_offsets_loaded,
633 &oes->rx_broadcast, &es->rx_broadcast);
634
635 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
636 I40E_GLV_GOTCL(stat_idx),
637 vsi->stat_offsets_loaded,
638 &oes->tx_bytes, &es->tx_bytes);
639 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
640 I40E_GLV_UPTCL(stat_idx),
641 vsi->stat_offsets_loaded,
642 &oes->tx_unicast, &es->tx_unicast);
643 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
644 I40E_GLV_MPTCL(stat_idx),
645 vsi->stat_offsets_loaded,
646 &oes->tx_multicast, &es->tx_multicast);
647 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
648 I40E_GLV_BPTCL(stat_idx),
649 vsi->stat_offsets_loaded,
650 &oes->tx_broadcast, &es->tx_broadcast);
651 vsi->stat_offsets_loaded = true;
652}
653
654/**
655 * i40e_update_veb_stats - Update Switch component statistics
656 * @veb: the VEB being updated
657 **/
658static void i40e_update_veb_stats(struct i40e_veb *veb)
659{
660 struct i40e_pf *pf = veb->pf;
661 struct i40e_hw *hw = &pf->hw;
662 struct i40e_eth_stats *oes;
663 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 664 struct i40e_veb_tc_stats *veb_oes;
665 struct i40e_veb_tc_stats *veb_es;
666 int i, idx = 0;
41c445ff
JB		 667
668 idx = veb->stats_idx;
669 es = &veb->stats;
670 oes = &veb->stats_offsets;
fe860afb
NP		 671 veb_es = &veb->tc_stats;
672 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 673
674 /* Gather up the stats that the hw collects */
675 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
676 veb->stat_offsets_loaded,
677 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 678 if (hw->revision_id > 0)
679 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
680 veb->stat_offsets_loaded,
681 &oes->rx_unknown_protocol,
682 &es->rx_unknown_protocol);
41c445ff
JB		 683 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
684 veb->stat_offsets_loaded,
685 &oes->rx_bytes, &es->rx_bytes);
686 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
687 veb->stat_offsets_loaded,
688 &oes->rx_unicast, &es->rx_unicast);
689 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
690 veb->stat_offsets_loaded,
691 &oes->rx_multicast, &es->rx_multicast);
692 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
693 veb->stat_offsets_loaded,
694 &oes->rx_broadcast, &es->rx_broadcast);
695
696 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
697 veb->stat_offsets_loaded,
698 &oes->tx_bytes, &es->tx_bytes);
699 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
700 veb->stat_offsets_loaded,
701 &oes->tx_unicast, &es->tx_unicast);
702 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
703 veb->stat_offsets_loaded,
704 &oes->tx_multicast, &es->tx_multicast);
705 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
706 veb->stat_offsets_loaded,
707 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 708 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
709 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
710 I40E_GLVEBTC_RPCL(i, idx),
711 veb->stat_offsets_loaded,
712 &veb_oes->tc_rx_packets[i],
713 &veb_es->tc_rx_packets[i]);
714 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
715 I40E_GLVEBTC_RBCL(i, idx),
716 veb->stat_offsets_loaded,
717 &veb_oes->tc_rx_bytes[i],
718 &veb_es->tc_rx_bytes[i]);
719 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
720 I40E_GLVEBTC_TPCL(i, idx),
721 veb->stat_offsets_loaded,
722 &veb_oes->tc_tx_packets[i],
723 &veb_es->tc_tx_packets[i]);
724 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
725 I40E_GLVEBTC_TBCL(i, idx),
726 veb->stat_offsets_loaded,
727 &veb_oes->tc_tx_bytes[i],
728 &veb_es->tc_tx_bytes[i]);
729 }
41c445ff
JB		 730 veb->stat_offsets_loaded = true;
731}
732
38e00438
VD		 733#ifdef I40E_FCOE
734/**
735 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
736 * @vsi: the VSI that is capable of doing FCoE
737 **/
738static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
739{
740 struct i40e_pf *pf = vsi->back;
741 struct i40e_hw *hw = &pf->hw;
742 struct i40e_fcoe_stats *ofs;
743 struct i40e_fcoe_stats *fs; /* device's eth stats */
744 int idx;
745
746 if (vsi->type != I40E_VSI_FCOE)
747 return;
748
4147e2c5 749 idx = hw->pf_id + I40E_FCOE_PF_STAT_OFFSET;
38e00438
VD		 750 fs = &vsi->fcoe_stats;
751 ofs = &vsi->fcoe_stats_offsets;
752
753 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
754 vsi->fcoe_stat_offsets_loaded,
755 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
756 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
757 vsi->fcoe_stat_offsets_loaded,
758 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
759 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
760 vsi->fcoe_stat_offsets_loaded,
761 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
762 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
763 vsi->fcoe_stat_offsets_loaded,
764 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
765 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
766 vsi->fcoe_stat_offsets_loaded,
767 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
768 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
769 vsi->fcoe_stat_offsets_loaded,
770 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
771 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
772 vsi->fcoe_stat_offsets_loaded,
773 &ofs->fcoe_last_error, &fs->fcoe_last_error);
774 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
775 vsi->fcoe_stat_offsets_loaded,
776 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
777
778 vsi->fcoe_stat_offsets_loaded = true;
779}
780
781#endif
41c445ff 782/**
7812fddc 783 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 784 * @vsi: the VSI to be updated
785 *
786 * There are a few instances where we store the same stat in a
787 * couple of different structs. This is partly because we have
788 * the netdev stats that need to be filled out, which is slightly
789 * different from the "eth_stats" defined by the chip and used in
7812fddc 790 * VF communications. We sort it out here.
41c445ff 791 **/
7812fddc 792static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 793{
794 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 795 struct rtnl_link_stats64 *ons;
796 struct rtnl_link_stats64 *ns; /* netdev stats */
797 struct i40e_eth_stats *oes;
798 struct i40e_eth_stats *es; /* device's eth stats */
799 u32 tx_restart, tx_busy;
dd353109 800 u64 tx_lost_interrupt;
bf00b376 801 struct i40e_ring *p;
41c445ff 802 u32 rx_page, rx_buf;
bf00b376
AA		 803 u64 bytes, packets;
804 unsigned int start;
2fc3d715 805 u64 tx_linearize;
164c9f54 806 u64 tx_force_wb;
41c445ff
JB		 807 u64 rx_p, rx_b;
808 u64 tx_p, tx_b;
41c445ff
JB		 809 u16 q;
810
811 if (test_bit(__I40E_DOWN, &vsi->state) ||
812 test_bit(__I40E_CONFIG_BUSY, &pf->state))
813 return;
814
815 ns = i40e_get_vsi_stats_struct(vsi);
816 ons = &vsi->net_stats_offsets;
817 es = &vsi->eth_stats;
818 oes = &vsi->eth_stats_offsets;
819
820 /* Gather up the netdev and vsi stats that the driver collects
821 * on the fly during packet processing
822 */
823 rx_b = rx_p = 0;
824 tx_b = tx_p = 0;
164c9f54 825 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
dd353109 826 tx_lost_interrupt = 0;
41c445ff
JB		 827 rx_page = 0;
828 rx_buf = 0;
980e9b11 829 rcu_read_lock();
41c445ff 830 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 831 /* locate Tx ring */
832 p = ACCESS_ONCE(vsi->tx_rings[q]);
833
834 do {
57a7744e 835 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 836 packets = p->stats.packets;
837 bytes = p->stats.bytes;
57a7744e 838 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 839 tx_b += bytes;
840 tx_p += packets;
841 tx_restart += p->tx_stats.restart_queue;
842 tx_busy += p->tx_stats.tx_busy;
2fc3d715 843 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 844 tx_force_wb += p->tx_stats.tx_force_wb;
dd353109 845 tx_lost_interrupt += p->tx_stats.tx_lost_interrupt;
41c445ff 846
980e9b11
AD		 847 /* Rx queue is part of the same block as Tx queue */
848 p = &p[1];
849 do {
57a7744e 850 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 851 packets = p->stats.packets;
852 bytes = p->stats.bytes;
57a7744e 853 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 854 rx_b += bytes;
855 rx_p += packets;
420136cc
MW		 856 rx_buf += p->rx_stats.alloc_buff_failed;
857 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 858 }
980e9b11 859 rcu_read_unlock();
41c445ff
JB		 860 vsi->tx_restart = tx_restart;
861 vsi->tx_busy = tx_busy;
2fc3d715 862 vsi->tx_linearize = tx_linearize;
164c9f54 863 vsi->tx_force_wb = tx_force_wb;
dd353109 864 vsi->tx_lost_interrupt = tx_lost_interrupt;
41c445ff
JB		 865 vsi->rx_page_failed = rx_page;
866 vsi->rx_buf_failed = rx_buf;
867
868 ns->rx_packets = rx_p;
869 ns->rx_bytes = rx_b;
870 ns->tx_packets = tx_p;
871 ns->tx_bytes = tx_b;
872
41c445ff 873 /* update netdev stats from eth stats */
7812fddc 874 i40e_update_eth_stats(vsi);
41c445ff
JB		 875 ons->tx_errors = oes->tx_errors;
876 ns->tx_errors = es->tx_errors;
877 ons->multicast = oes->rx_multicast;
878 ns->multicast = es->rx_multicast;
41a9e55c
SN		 879 ons->rx_dropped = oes->rx_discards;
880 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 881 ons->tx_dropped = oes->tx_discards;
882 ns->tx_dropped = es->tx_discards;
883
7812fddc 884 /* pull in a couple PF stats if this is the main vsi */
41c445ff 885 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 886 ns->rx_crc_errors = pf->stats.crc_errors;
887 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
888 ns->rx_length_errors = pf->stats.rx_length_errors;
889 }
890}
41c445ff 891
7812fddc 892/**
b40c82e6 893 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 894 * @pf: the PF to be updated
895 **/
896static void i40e_update_pf_stats(struct i40e_pf *pf)
897{
898 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
899 struct i40e_hw_port_stats *nsd = &pf->stats;
900 struct i40e_hw *hw = &pf->hw;
901 u32 val;
902 int i;
41c445ff 903
7812fddc
SN		 904 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
905 I40E_GLPRT_GORCL(hw->port),
906 pf->stat_offsets_loaded,
907 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
908 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
909 I40E_GLPRT_GOTCL(hw->port),
910 pf->stat_offsets_loaded,
911 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
912 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->eth.rx_discards,
915 &nsd->eth.rx_discards);
532d283d
SN		 916 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
917 I40E_GLPRT_UPRCL(hw->port),
918 pf->stat_offsets_loaded,
919 &osd->eth.rx_unicast,
920 &nsd->eth.rx_unicast);
7812fddc
SN		 921 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
922 I40E_GLPRT_MPRCL(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->eth.rx_multicast,
925 &nsd->eth.rx_multicast);
532d283d
SN		 926 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
927 I40E_GLPRT_BPRCL(hw->port),
928 pf->stat_offsets_loaded,
929 &osd->eth.rx_broadcast,
930 &nsd->eth.rx_broadcast);
931 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
932 I40E_GLPRT_UPTCL(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->eth.tx_unicast,
935 &nsd->eth.tx_unicast);
936 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
937 I40E_GLPRT_MPTCL(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->eth.tx_multicast,
940 &nsd->eth.tx_multicast);
941 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
942 I40E_GLPRT_BPTCL(hw->port),
943 pf->stat_offsets_loaded,
944 &osd->eth.tx_broadcast,
945 &nsd->eth.tx_broadcast);
41c445ff 946
7812fddc
SN		 947 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
948 pf->stat_offsets_loaded,
949 &osd->tx_dropped_link_down,
950 &nsd->tx_dropped_link_down);
41c445ff 951
7812fddc
SN		 952 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
953 pf->stat_offsets_loaded,
954 &osd->crc_errors, &nsd->crc_errors);
41c445ff 955
7812fddc
SN		 956 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
957 pf->stat_offsets_loaded,
958 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 959
7812fddc
SN		 960 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->mac_local_faults,
963 &nsd->mac_local_faults);
964 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->mac_remote_faults,
967 &nsd->mac_remote_faults);
41c445ff 968
7812fddc
SN		 969 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
970 pf->stat_offsets_loaded,
971 &osd->rx_length_errors,
972 &nsd->rx_length_errors);
41c445ff 973
7812fddc
SN		 974 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->link_xon_rx, &nsd->link_xon_rx);
977 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 980 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 983 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 986
7812fddc 987 for (i = 0; i < 8; i++) {
95db239f
NP		 988 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
989 pf->stat_offsets_loaded,
990 &osd->priority_xoff_rx[i],
991 &nsd->priority_xoff_rx[i]);
7812fddc 992 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 993 pf->stat_offsets_loaded,
7812fddc
SN		 994 &osd->priority_xon_rx[i],
995 &nsd->priority_xon_rx[i]);
996 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 997 pf->stat_offsets_loaded,
7812fddc
SN		 998 &osd->priority_xon_tx[i],
999 &nsd->priority_xon_tx[i]);
1000 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1001 pf->stat_offsets_loaded,
7812fddc
SN		 1002 &osd->priority_xoff_tx[i],
1003 &nsd->priority_xoff_tx[i]);
1004 i40e_stat_update32(hw,
1005 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xon_2_xoff[i],
1008 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1009 }
1010
7812fddc
SN		 1011 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1012 I40E_GLPRT_PRC64L(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->rx_size_64, &nsd->rx_size_64);
1015 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1016 I40E_GLPRT_PRC127L(hw->port),
1017 pf->stat_offsets_loaded,
1018 &osd->rx_size_127, &nsd->rx_size_127);
1019 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1020 I40E_GLPRT_PRC255L(hw->port),
1021 pf->stat_offsets_loaded,
1022 &osd->rx_size_255, &nsd->rx_size_255);
1023 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1024 I40E_GLPRT_PRC511L(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->rx_size_511, &nsd->rx_size_511);
1027 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1028 I40E_GLPRT_PRC1023L(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->rx_size_1023, &nsd->rx_size_1023);
1031 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1032 I40E_GLPRT_PRC1522L(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->rx_size_1522, &nsd->rx_size_1522);
1035 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1036 I40E_GLPRT_PRC9522L(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->rx_size_big, &nsd->rx_size_big);
1039
1040 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1041 I40E_GLPRT_PTC64L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->tx_size_64, &nsd->tx_size_64);
1044 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1045 I40E_GLPRT_PTC127L(hw->port),
1046 pf->stat_offsets_loaded,
1047 &osd->tx_size_127, &nsd->tx_size_127);
1048 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1049 I40E_GLPRT_PTC255L(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->tx_size_255, &nsd->tx_size_255);
1052 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1053 I40E_GLPRT_PTC511L(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->tx_size_511, &nsd->tx_size_511);
1056 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1057 I40E_GLPRT_PTC1023L(hw->port),
1058 pf->stat_offsets_loaded,
1059 &osd->tx_size_1023, &nsd->tx_size_1023);
1060 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1061 I40E_GLPRT_PTC1522L(hw->port),
1062 pf->stat_offsets_loaded,
1063 &osd->tx_size_1522, &nsd->tx_size_1522);
1064 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1065 I40E_GLPRT_PTC9522L(hw->port),
1066 pf->stat_offsets_loaded,
1067 &osd->tx_size_big, &nsd->tx_size_big);
1068
1069 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1070 pf->stat_offsets_loaded,
1071 &osd->rx_undersize, &nsd->rx_undersize);
1072 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->rx_fragments, &nsd->rx_fragments);
1075 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1076 pf->stat_offsets_loaded,
1077 &osd->rx_oversize, &nsd->rx_oversize);
1078 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_jabber, &nsd->rx_jabber);
1081
433c47de 1082 /* FDIR stats */
0bf4b1b0
ASJ		 1083 i40e_stat_update32(hw,
1084 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1085 pf->stat_offsets_loaded,
1086 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1087 i40e_stat_update32(hw,
1088 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1089 pf->stat_offsets_loaded,
1090 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1091 i40e_stat_update32(hw,
1092 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1093 pf->stat_offsets_loaded,
1094 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1095
7812fddc
SN		 1096 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1097 nsd->tx_lpi_status =
1098 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1099 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1100 nsd->rx_lpi_status =
1101 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1102 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1103 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1104 pf->stat_offsets_loaded,
1105 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1106 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1107 pf->stat_offsets_loaded,
1108 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1109
d0389e51
ASJ		 1110 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1111 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1112 nsd->fd_sb_status = true;
1113 else
1114 nsd->fd_sb_status = false;
1115
1116 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1117 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1118 nsd->fd_atr_status = true;
1119 else
1120 nsd->fd_atr_status = false;
1121
41c445ff
JB		 1122 pf->stat_offsets_loaded = true;
1123}
1124
7812fddc
SN		 1125/**
1126 * i40e_update_stats - Update the various statistics counters.
1127 * @vsi: the VSI to be updated
1128 *
1129 * Update the various stats for this VSI and its related entities.
1130 **/
1131void i40e_update_stats(struct i40e_vsi *vsi)
1132{
1133 struct i40e_pf *pf = vsi->back;
1134
1135 if (vsi == pf->vsi[pf->lan_vsi])
1136 i40e_update_pf_stats(pf);
1137
1138 i40e_update_vsi_stats(vsi);
38e00438
VD		 1139#ifdef I40E_FCOE
1140 i40e_update_fcoe_stats(vsi);
1141#endif
7812fddc
SN		 1142}
1143
41c445ff
JB		 1144/**
1145 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1146 * @vsi: the VSI to be searched
1147 * @macaddr: the MAC address
1148 * @vlan: the vlan
b40c82e6 1149 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1150 * @is_netdev: make sure its a netdev filter, else doesn't matter
1151 *
1152 * Returns ptr to the filter object or NULL
1153 **/
1154static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1155 u8 *macaddr, s16 vlan,
1156 bool is_vf, bool is_netdev)
1157{
1158 struct i40e_mac_filter *f;
1159
1160 if (!vsi || !macaddr)
1161 return NULL;
1162
1163 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1164 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1165 (vlan == f->vlan) &&
1166 (!is_vf || f->is_vf) &&
1167 (!is_netdev || f->is_netdev))
1168 return f;
1169 }
1170 return NULL;
1171}
1172
1173/**
1174 * i40e_find_mac - Find a mac addr in the macvlan filters list
1175 * @vsi: the VSI to be searched
1176 * @macaddr: the MAC address we are searching for
b40c82e6 1177 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1178 * @is_netdev: make sure its a netdev filter, else doesn't matter
1179 *
1180 * Returns the first filter with the provided MAC address or NULL if
1181 * MAC address was not found
1182 **/
1183struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1184 bool is_vf, bool is_netdev)
1185{
1186 struct i40e_mac_filter *f;
1187
1188 if (!vsi || !macaddr)
1189 return NULL;
1190
1191 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1192 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1193 (!is_vf || f->is_vf) &&
1194 (!is_netdev || f->is_netdev))
1195 return f;
1196 }
1197 return NULL;
1198}
1199
1200/**
1201 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1202 * @vsi: the VSI to be searched
1203 *
1204 * Returns true if VSI is in vlan mode or false otherwise
1205 **/
1206bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1207{
1208 struct i40e_mac_filter *f;
1209
1210 /* Only -1 for all the filters denotes not in vlan mode
1211 * so we have to go through all the list in order to make sure
1212 */
1213 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1214 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1215 return true;
1216 }
1217
1218 return false;
1219}
1220
1221/**
1222 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1223 * @vsi: the VSI to be searched
1224 * @macaddr: the mac address to be filtered
b40c82e6 1225 * @is_vf: true if it is a VF
41c445ff
JB		 1226 * @is_netdev: true if it is a netdev
1227 *
1228 * Goes through all the macvlan filters and adds a
1229 * macvlan filter for each unique vlan that already exists
1230 *
1231 * Returns first filter found on success, else NULL
1232 **/
1233struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1234 bool is_vf, bool is_netdev)
1235{
1236 struct i40e_mac_filter *f;
1237
1238 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1239 if (vsi->info.pvid)
1240 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1241 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1242 is_vf, is_netdev)) {
1243 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1244 is_vf, is_netdev))
41c445ff
JB		 1245 return NULL;
1246 }
1247 }
1248
1249 return list_first_entry_or_null(&vsi->mac_filter_list,
1250 struct i40e_mac_filter, list);
1251}
1252
b36e9ab5
MW		 1253/**
1254 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1255 * @vsi: the VSI to be searched
1256 * @macaddr: the mac address to be removed
1257 * @is_vf: true if it is a VF
1258 * @is_netdev: true if it is a netdev
1259 *
1260 * Removes a given MAC address from a VSI, regardless of VLAN
1261 *
1262 * Returns 0 for success, or error
1263 **/
1264int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1265 bool is_vf, bool is_netdev)
1266{
1267 struct i40e_mac_filter *f = NULL;
1268 int changed = 0;
1269
1270 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1271 "Missing mac_filter_list_lock\n");
1272 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1273 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1274 (is_vf == f->is_vf) &&
1275 (is_netdev == f->is_netdev)) {
1276 f->counter--;
b36e9ab5 1277 changed = 1;
c3c7ea27
MW		 1278 if (f->counter == 0)
1279 f->state = I40E_FILTER_REMOVE;
b36e9ab5
MW		 1280 }
1281 }
1282 if (changed) {
1283 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1284 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1285 return 0;
1286 }
1287 return -ENOENT;
1288}
1289
8c27d42e
GR		 1290/**
1291 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1292 * @vsi: the PF Main VSI - inappropriate for any other VSI
1293 * @macaddr: the MAC address
30650cc5 1294 *
c3c7ea27
MW		 1295 * Remove whatever filter the firmware set up so the driver can manage
1296 * its own filtering intelligently.
8c27d42e 1297 **/
c3c7ea27 1298static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1299{
1300 struct i40e_aqc_remove_macvlan_element_data element;
1301 struct i40e_pf *pf = vsi->back;
8c27d42e
GR		 1302
1303 /* Only appropriate for the PF main VSI */
1304 if (vsi->type != I40E_VSI_MAIN)
c3c7ea27 1305 return;
8c27d42e 1306
30650cc5 1307 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1308 ether_addr_copy(element.mac_addr, macaddr);
1309 element.vlan_tag = 0;
c3c7ea27
MW		 1310 /* Ignore error returns, some firmware does it this way... */
1311 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1312 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
30650cc5 1313
c3c7ea27
MW		 1314 memset(&element, 0, sizeof(element));
1315 ether_addr_copy(element.mac_addr, macaddr);
1316 element.vlan_tag = 0;
1317 /* ...and some firmware does it this way. */
1318 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1319 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
1320 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
8c27d42e
GR		 1321}
1322
41c445ff
JB		 1323/**
1324 * i40e_add_filter - Add a mac/vlan filter to the VSI
1325 * @vsi: the VSI to be searched
1326 * @macaddr: the MAC address
1327 * @vlan: the vlan
b40c82e6 1328 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1329 * @is_netdev: make sure its a netdev filter, else doesn't matter
1330 *
1331 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1332 *
1333 * NOTE: This function is expected to be called with mac_filter_list_lock
1334 * being held.
41c445ff
JB		 1335 **/
1336struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1337 u8 *macaddr, s16 vlan,
1338 bool is_vf, bool is_netdev)
1339{
1340 struct i40e_mac_filter *f;
c3c7ea27 1341 int changed = false;
41c445ff
JB		 1342
1343 if (!vsi || !macaddr)
1344 return NULL;
1345
f6bd0962
KP		 1346 /* Do not allow broadcast filter to be added since broadcast filter
1347 * is added as part of add VSI for any newly created VSI except
1348 * FDIR VSI
1349 */
1350 if (is_broadcast_ether_addr(macaddr))
1351 return NULL;
1352
41c445ff
JB		 1353 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1354 if (!f) {
1355 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1356 if (!f)
1357 goto add_filter_out;
1358
9a173901 1359 ether_addr_copy(f->macaddr, macaddr);
41c445ff 1360 f->vlan = vlan;
c3c7ea27
MW		 1361 /* If we're in overflow promisc mode, set the state directly
1362 * to failed, so we don't bother to try sending the filter
1363 * to the hardware.
1364 */
1365 if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state))
1366 f->state = I40E_FILTER_FAILED;
1367 else
1368 f->state = I40E_FILTER_NEW;
1369 changed = true;
41c445ff 1370 INIT_LIST_HEAD(&f->list);
04d5a21d 1371 list_add_tail(&f->list, &vsi->mac_filter_list);
41c445ff
JB		 1372 }
1373
1374 /* increment counter and add a new flag if needed */
1375 if (is_vf) {
1376 if (!f->is_vf) {
1377 f->is_vf = true;
1378 f->counter++;
1379 }
1380 } else if (is_netdev) {
1381 if (!f->is_netdev) {
1382 f->is_netdev = true;
1383 f->counter++;
1384 }
1385 } else {
1386 f->counter++;
1387 }
1388
c3c7ea27 1389 if (changed) {
41c445ff
JB		 1390 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1391 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1392 }
1393
1394add_filter_out:
1395 return f;
1396}
1397
1398/**
1399 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1400 * @vsi: the VSI to be searched
1401 * @macaddr: the MAC address
1402 * @vlan: the vlan
b40c82e6 1403 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1404 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1405 *
1406 * NOTE: This function is expected to be called with mac_filter_list_lock
1407 * being held.
c3c7ea27
MW		 1408 * ANOTHER NOTE: This function MUST be called from within the context of
1409 * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe()
1410 * instead of list_for_each_entry().
41c445ff
JB		 1411 **/
1412void i40e_del_filter(struct i40e_vsi *vsi,
1413 u8 *macaddr, s16 vlan,
1414 bool is_vf, bool is_netdev)
1415{
1416 struct i40e_mac_filter *f;
1417
1418 if (!vsi || !macaddr)
1419 return;
1420
1421 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1422 if (!f || f->counter == 0)
1423 return;
1424
1425 if (is_vf) {
1426 if (f->is_vf) {
1427 f->is_vf = false;
1428 f->counter--;
1429 }
1430 } else if (is_netdev) {
1431 if (f->is_netdev) {
1432 f->is_netdev = false;
1433 f->counter--;
1434 }
1435 } else {
b40c82e6 1436 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1437 int min_f = 0;
6995b36c 1438
41c445ff
JB		 1439 min_f += (f->is_vf ? 1 : 0);
1440 min_f += (f->is_netdev ? 1 : 0);
1441
1442 if (f->counter > min_f)
1443 f->counter--;
1444 }
1445
1446 /* counter == 0 tells sync_filters_subtask to
1447 * remove the filter from the firmware's list
1448 */
1449 if (f->counter == 0) {
c3c7ea27
MW		 1450 if ((f->state == I40E_FILTER_FAILED) ||
1451 (f->state == I40E_FILTER_NEW)) {
1452 /* this one never got added by the FW. Just remove it,
1453 * no need to sync anything.
1454 */
1455 list_del(&f->list);
1456 kfree(f);
1457 } else {
1458 f->state = I40E_FILTER_REMOVE;
1459 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1460 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1461 }
41c445ff
JB		 1462 }
1463}
1464
1465/**
1466 * i40e_set_mac - NDO callback to set mac address
1467 * @netdev: network interface device structure
1468 * @p: pointer to an address structure
1469 *
1470 * Returns 0 on success, negative on failure
1471 **/
38e00438
VD		 1472#ifdef I40E_FCOE
1473int i40e_set_mac(struct net_device *netdev, void *p)
1474#else
41c445ff 1475static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1476#endif
41c445ff
JB		 1477{
1478 struct i40e_netdev_priv *np = netdev_priv(netdev);
1479 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1480 struct i40e_pf *pf = vsi->back;
1481 struct i40e_hw *hw = &pf->hw;
41c445ff 1482 struct sockaddr *addr = p;
41c445ff
JB		 1483
1484 if (!is_valid_ether_addr(addr->sa_data))
1485 return -EADDRNOTAVAIL;
1486
30650cc5
SN		 1487 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1488 netdev_info(netdev, "already using mac address %pM\n",
1489 addr->sa_data);
1490 return 0;
1491 }
41c445ff 1492
80f6428f
ASJ		 1493 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1494 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1495 return -EADDRNOTAVAIL;
1496
30650cc5
SN		 1497 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1498 netdev_info(netdev, "returning to hw mac address %pM\n",
1499 hw->mac.addr);
1500 else
1501 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1502
c3c7ea27
MW		 1503 spin_lock_bh(&vsi->mac_filter_list_lock);
1504 i40e_del_mac_all_vlan(vsi, netdev->dev_addr, false, true);
1505 i40e_put_mac_in_vlan(vsi, addr->sa_data, false, true);
1506 spin_unlock_bh(&vsi->mac_filter_list_lock);
1507 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1508 if (vsi->type == I40E_VSI_MAIN) {
1509 i40e_status ret;
6995b36c 1510
41c445ff 1511 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1512 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff 1513 addr->sa_data, NULL);
c3c7ea27
MW		 1514 if (ret)
1515 netdev_info(netdev, "Ignoring error from firmware on LAA update, status %s, AQ ret %s\n",
1516 i40e_stat_str(hw, ret),
1517 i40e_aq_str(hw, hw->aq.asq_last_status));
30650cc5
SN		 1518 }
1519
c53934c6
JB		 1520 /* schedule our worker thread which will take care of
1521 * applying the new filter changes
1522 */
1523 i40e_service_event_schedule(vsi->back);
1524 return 0;
41c445ff
JB		 1525}
1526
1527/**
1528 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1529 * @vsi: the VSI being setup
1530 * @ctxt: VSI context structure
1531 * @enabled_tc: Enabled TCs bitmap
1532 * @is_add: True if called before Add VSI
1533 *
1534 * Setup VSI queue mapping for enabled traffic classes.
1535 **/
38e00438
VD		 1536#ifdef I40E_FCOE
1537void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1538 struct i40e_vsi_context *ctxt,
1539 u8 enabled_tc,
1540 bool is_add)
1541#else
41c445ff
JB		 1542static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1543 struct i40e_vsi_context *ctxt,
1544 u8 enabled_tc,
1545 bool is_add)
38e00438 1546#endif
41c445ff
JB		 1547{
1548 struct i40e_pf *pf = vsi->back;
1549 u16 sections = 0;
1550 u8 netdev_tc = 0;
1551 u16 numtc = 0;
1552 u16 qcount;
1553 u8 offset;
1554 u16 qmap;
1555 int i;
4e3b35b0 1556 u16 num_tc_qps = 0;
41c445ff
JB		 1557
1558 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1559 offset = 0;
1560
1561 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1562 /* Find numtc from enabled TC bitmap */
1563 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1564 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1565 numtc++;
1566 }
1567 if (!numtc) {
1568 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1569 numtc = 1;
1570 }
1571 } else {
1572 /* At least TC0 is enabled in case of non-DCB case */
1573 numtc = 1;
1574 }
1575
1576 vsi->tc_config.numtc = numtc;
1577 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1578 /* Number of queues per enabled TC */
7d64402f
CS		 1579 qcount = vsi->alloc_queue_pairs;
1580
7f9ff476 1581 num_tc_qps = qcount / numtc;
e25d00b8 1582 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1583
1584 /* Setup queue offset/count for all TCs for given VSI */
1585 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1586 /* See if the given TC is enabled for the given VSI */
75f5cea9 1587 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1588 /* TC is enabled */
41c445ff
JB		 1589 int pow, num_qps;
1590
41c445ff
JB		 1591 switch (vsi->type) {
1592 case I40E_VSI_MAIN:
acd65448
HZ		 1593 qcount = min_t(int, pf->alloc_rss_size,
1594 num_tc_qps);
41c445ff 1595 break;
38e00438
VD		 1596#ifdef I40E_FCOE
1597 case I40E_VSI_FCOE:
1598 qcount = num_tc_qps;
1599 break;
1600#endif
41c445ff
JB		 1601 case I40E_VSI_FDIR:
1602 case I40E_VSI_SRIOV:
1603 case I40E_VSI_VMDQ2:
1604 default:
4e3b35b0 1605 qcount = num_tc_qps;
41c445ff
JB		 1606 WARN_ON(i != 0);
1607 break;
1608 }
4e3b35b0
NP		 1609 vsi->tc_config.tc_info[i].qoffset = offset;
1610 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1611
1e200e4a 1612 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1613 num_qps = qcount;
41c445ff 1614 pow = 0;
41a1d04b 1615 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1616 pow++;
1617 num_qps >>= 1;
1618 }
1619
1620 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1621 qmap =
1622 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1623 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1624
4e3b35b0 1625 offset += qcount;
41c445ff
JB		 1626 } else {
1627 /* TC is not enabled so set the offset to
1628 * default queue and allocate one queue
1629 * for the given TC.
1630 */
1631 vsi->tc_config.tc_info[i].qoffset = 0;
1632 vsi->tc_config.tc_info[i].qcount = 1;
1633 vsi->tc_config.tc_info[i].netdev_tc = 0;
1634
1635 qmap = 0;
1636 }
1637 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1638 }
1639
1640 /* Set actual Tx/Rx queue pairs */
1641 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1642 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1643 if (vsi->req_queue_pairs > 0)
1644 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1645 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1646 vsi->num_queue_pairs = pf->num_lan_msix;
1647 }
41c445ff
JB		 1648
1649 /* Scheduler section valid can only be set for ADD VSI */
1650 if (is_add) {
1651 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1652
1653 ctxt->info.up_enable_bits = enabled_tc;
1654 }
1655 if (vsi->type == I40E_VSI_SRIOV) {
1656 ctxt->info.mapping_flags |=
1657 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1658 for (i = 0; i < vsi->num_queue_pairs; i++)
1659 ctxt->info.queue_mapping[i] =
1660 cpu_to_le16(vsi->base_queue + i);
1661 } else {
1662 ctxt->info.mapping_flags |=
1663 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1664 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1665 }
1666 ctxt->info.valid_sections |= cpu_to_le16(sections);
1667}
1668
1669/**
1670 * i40e_set_rx_mode - NDO callback to set the netdev filters
1671 * @netdev: network interface device structure
1672 **/
38e00438
VD		 1673#ifdef I40E_FCOE
1674void i40e_set_rx_mode(struct net_device *netdev)
1675#else
41c445ff 1676static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1677#endif
41c445ff
JB		 1678{
1679 struct i40e_netdev_priv *np = netdev_priv(netdev);
1680 struct i40e_mac_filter *f, *ftmp;
1681 struct i40e_vsi *vsi = np->vsi;
1682 struct netdev_hw_addr *uca;
1683 struct netdev_hw_addr *mca;
1684 struct netdev_hw_addr *ha;
1685
21659035
KP		 1686 spin_lock_bh(&vsi->mac_filter_list_lock);
1687
41c445ff
JB		 1688 /* add addr if not already in the filter list */
1689 netdev_for_each_uc_addr(uca, netdev) {
1690 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1691 if (i40e_is_vsi_in_vlan(vsi))
1692 i40e_put_mac_in_vlan(vsi, uca->addr,
1693 false, true);
1694 else
1695 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1696 false, true);
1697 }
1698 }
1699
1700 netdev_for_each_mc_addr(mca, netdev) {
1701 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1702 if (i40e_is_vsi_in_vlan(vsi))
1703 i40e_put_mac_in_vlan(vsi, mca->addr,
1704 false, true);
1705 else
1706 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1707 false, true);
1708 }
1709 }
1710
1711 /* remove filter if not in netdev list */
1712 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1713
1714 if (!f->is_netdev)
1715 continue;
1716
2f41f335
SN		 1717 netdev_for_each_mc_addr(mca, netdev)
1718 if (ether_addr_equal(mca->addr, f->macaddr))
1719 goto bottom_of_search_loop;
41c445ff 1720
2f41f335
SN		 1721 netdev_for_each_uc_addr(uca, netdev)
1722 if (ether_addr_equal(uca->addr, f->macaddr))
1723 goto bottom_of_search_loop;
1724
1725 for_each_dev_addr(netdev, ha)
1726 if (ether_addr_equal(ha->addr, f->macaddr))
1727 goto bottom_of_search_loop;
1728
1729 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1730 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1731
1732bottom_of_search_loop:
1733 continue;
41c445ff 1734 }
21659035 1735 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1736
1737 /* check for other flag changes */
1738 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1739 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1740 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1741 }
c53934c6
JB		 1742
1743 /* schedule our worker thread which will take care of
1744 * applying the new filter changes
1745 */
1746 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1747}
1748
21659035
KP		 1749/**
1750 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1751 * @vsi: pointer to vsi struct
1752 * @from: Pointer to list which contains MAC filter entries - changes to
1753 * those entries needs to be undone.
1754 *
1755 * MAC filter entries from list were slated to be removed from device.
1756 **/
1757static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1758 struct list_head *from)
1759{
1760 struct i40e_mac_filter *f, *ftmp;
1761
1762 list_for_each_entry_safe(f, ftmp, from, list) {
21659035
KP		 1763 /* Move the element back into MAC filter list*/
1764 list_move_tail(&f->list, &vsi->mac_filter_list);
1765 }
1766}
1767
1768/**
c3c7ea27
MW		 1769 * i40e_update_filter_state - Update filter state based on return data
1770 * from firmware
1771 * @count: Number of filters added
1772 * @add_list: return data from fw
1773 * @head: pointer to first filter in current batch
1774 * @aq_err: status from fw
21659035 1775 *
c3c7ea27
MW		 1776 * MAC filter entries from list were slated to be added to device. Returns
1777 * number of successful filters. Note that 0 does NOT mean success!
21659035 1778 **/
c3c7ea27
MW		 1779static int
1780i40e_update_filter_state(int count,
1781 struct i40e_aqc_add_macvlan_element_data *add_list,
1782 struct i40e_mac_filter *add_head, int aq_err)
21659035 1783{
c3c7ea27
MW		 1784 int retval = 0;
1785 int i;
21659035 1786
21659035 1787
c3c7ea27
MW		 1788 if (!aq_err) {
1789 retval = count;
1790 /* Everything's good, mark all filters active. */
1791 for (i = 0; i < count ; i++) {
1792 add_head->state = I40E_FILTER_ACTIVE;
1793 add_head = list_next_entry(add_head, list);
1794 }
1795 } else if (aq_err == I40E_AQ_RC_ENOSPC) {
1796 /* Device ran out of filter space. Check the return value
1797 * for each filter to see which ones are active.
1798 */
1799 for (i = 0; i < count ; i++) {
1800 if (add_list[i].match_method ==
1801 I40E_AQC_MM_ERR_NO_RES) {
1802 add_head->state = I40E_FILTER_FAILED;
1803 } else {
1804 add_head->state = I40E_FILTER_ACTIVE;
1805 retval++;
1806 }
1807 add_head = list_next_entry(add_head, list);
1808 }
1809 } else {
1810 /* Some other horrible thing happened, fail all filters */
1811 retval = 0;
1812 for (i = 0; i < count ; i++) {
1813 add_head->state = I40E_FILTER_FAILED;
1814 add_head = list_next_entry(add_head, list);
1815 }
21659035 1816 }
c3c7ea27 1817 return retval;
21659035
KP		 1818}
1819
41c445ff
JB		 1820/**
1821 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1822 * @vsi: ptr to the VSI
1823 *
1824 * Push any outstanding VSI filter changes through the AdminQ.
1825 *
1826 * Returns 0 or error value
1827 **/
17652c63 1828int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1829{
c3c7ea27
MW		 1830 struct i40e_mac_filter *f, *ftmp, *add_head = NULL;
1831 struct list_head tmp_add_list, tmp_del_list;
3e25a8f3 1832 struct i40e_hw *hw = &vsi->back->hw;
c3c7ea27 1833 bool promisc_changed = false;
2d1de828 1834 char vsi_name[16] = "PF";
41c445ff
JB		 1835 int filter_list_len = 0;
1836 u32 changed_flags = 0;
ea02e90b 1837 i40e_status aq_ret = 0;
ea02e90b 1838 int retval = 0;
41c445ff
JB		 1839 struct i40e_pf *pf;
1840 int num_add = 0;
1841 int num_del = 0;
f1c7e72e 1842 int aq_err = 0;
41c445ff 1843 u16 cmd_flags;
c3c7ea27
MW		 1844 int list_size;
1845 int fcnt;
41c445ff
JB		 1846
1847 /* empty array typed pointers, kcalloc later */
1848 struct i40e_aqc_add_macvlan_element_data *add_list;
1849 struct i40e_aqc_remove_macvlan_element_data *del_list;
1850
1851 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1852 usleep_range(1000, 2000);
1853 pf = vsi->back;
1854
1855 if (vsi->netdev) {
1856 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1857 vsi->current_netdev_flags = vsi->netdev->flags;
1858 }
1859
21659035 1860 INIT_LIST_HEAD(&tmp_add_list);
c3c7ea27 1861 INIT_LIST_HEAD(&tmp_del_list);
21659035 1862
2d1de828
SN		 1863 if (vsi->type == I40E_VSI_SRIOV)
1864 snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id);
1865 else if (vsi->type != I40E_VSI_MAIN)
1866 snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid);
1867
41c445ff
JB		 1868 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1869 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1870
21659035 1871 spin_lock_bh(&vsi->mac_filter_list_lock);
c3c7ea27 1872 /* Create a list of filters to delete. */
41c445ff 1873 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
c3c7ea27
MW		 1874 if (f->state == I40E_FILTER_REMOVE) {
1875 WARN_ON(f->counter != 0);
1876 /* Move the element into temporary del_list */
1877 list_move_tail(&f->list, &tmp_del_list);
1878 vsi->active_filters--;
1879 }
1880 if (f->state == I40E_FILTER_NEW) {
1881 WARN_ON(f->counter == 0);
1882 /* Move the element into temporary add_list */
1883 list_move_tail(&f->list, &tmp_add_list);
21659035 1884 }
21659035
KP		 1885 }
1886 spin_unlock_bh(&vsi->mac_filter_list_lock);
21659035
KP		 1887 }
1888
1889 /* Now process 'del_list' outside the lock */
1890 if (!list_empty(&tmp_del_list)) {
3e25a8f3 1891 filter_list_len = hw->aq.asq_buf_size /
21659035 1892 sizeof(struct i40e_aqc_remove_macvlan_element_data);
c3c7ea27 1893 list_size = filter_list_len *
f1199998 1894 sizeof(struct i40e_aqc_remove_macvlan_element_data);
c3c7ea27 1895 del_list = kzalloc(list_size, GFP_ATOMIC);
21659035 1896 if (!del_list) {
21659035
KP		 1897 /* Undo VSI's MAC filter entry element updates */
1898 spin_lock_bh(&vsi->mac_filter_list_lock);
1899 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
21659035 1900 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1901 retval = -ENOMEM;
1902 goto out;
21659035
KP		 1903 }
1904
1905 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1906 cmd_flags = 0;
1907
1908 /* add to delete list */
9a173901 1909 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
c3c7ea27
MW		 1910 if (f->vlan == I40E_VLAN_ANY) {
1911 del_list[num_del].vlan_tag = 0;
1912 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
1913 } else {
1914 del_list[num_del].vlan_tag =
1915 cpu_to_le16((u16)(f->vlan));
1916 }
41c445ff 1917
41c445ff
JB		 1918 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1919 del_list[num_del].flags = cmd_flags;
1920 num_del++;
1921
41c445ff
JB		 1922 /* flush a full buffer */
1923 if (num_del == filter_list_len) {
c3c7ea27
MW		 1924 aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid,
1925 del_list,
1926 num_del, NULL);
3e25a8f3 1927 aq_err = hw->aq.asq_last_status;
41c445ff 1928 num_del = 0;
c3c7ea27 1929 memset(del_list, 0, list_size);
41c445ff 1930
c3c7ea27
MW		 1931 /* Explicitly ignore and do not report when
1932 * firmware returns ENOENT.
1933 */
1934 if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) {
ea02e90b 1935 retval = -EIO;
c3c7ea27
MW		 1936 dev_info(&pf->pdev->dev,
1937 "ignoring delete macvlan error on %s, err %s, aq_err %s\n",
2d1de828 1938 vsi_name,
3e25a8f3
MW		 1939 i40e_stat_str(hw, aq_ret),
1940 i40e_aq_str(hw, aq_err));
ea02e90b 1941 }
41c445ff 1942 }
21659035
KP		 1943 /* Release memory for MAC filter entries which were
1944 * synced up with HW.
1945 */
1946 list_del(&f->list);
1947 kfree(f);
41c445ff 1948 }
21659035 1949
41c445ff 1950 if (num_del) {
3e25a8f3
MW		 1951 aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, del_list,
1952 num_del, NULL);
1953 aq_err = hw->aq.asq_last_status;
41c445ff
JB		 1954 num_del = 0;
1955
c3c7ea27
MW		 1956 /* Explicitly ignore and do not report when firmware
1957 * returns ENOENT.
1958 */
1959 if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) {
1960 retval = -EIO;
41c445ff 1961 dev_info(&pf->pdev->dev,
2d1de828
SN		 1962 "ignoring delete macvlan error on %s, err %s aq_err %s\n",
1963 vsi_name,
3e25a8f3
MW		 1964 i40e_stat_str(hw, aq_ret),
1965 i40e_aq_str(hw, aq_err));
c3c7ea27 1966 }
41c445ff
JB		 1967 }
1968
1969 kfree(del_list);
1970 del_list = NULL;
21659035
KP		 1971 }
1972
1973 if (!list_empty(&tmp_add_list)) {
c3c7ea27 1974 /* Do all the adds now. */
3e25a8f3 1975 filter_list_len = hw->aq.asq_buf_size /
f1199998 1976 sizeof(struct i40e_aqc_add_macvlan_element_data);
c3c7ea27
MW		 1977 list_size = filter_list_len *
1978 sizeof(struct i40e_aqc_add_macvlan_element_data);
1979 add_list = kzalloc(list_size, GFP_ATOMIC);
21659035 1980 if (!add_list) {
ea02e90b
MW		 1981 retval = -ENOMEM;
1982 goto out;
21659035 1983 }
c3c7ea27
MW		 1984 num_add = 0;
1985 list_for_each_entry(f, &tmp_add_list, list) {
1986 if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1987 &vsi->state)) {
1988 f->state = I40E_FILTER_FAILED;
1989 continue;
1990 }
41c445ff 1991 /* add to add array */
c3c7ea27
MW		 1992 if (num_add == 0)
1993 add_head = f;
1994 cmd_flags = 0;
9a173901 1995 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
c3c7ea27
MW		 1996 if (f->vlan == I40E_VLAN_ANY) {
1997 add_list[num_add].vlan_tag = 0;
1998 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
1999 } else {
2000 add_list[num_add].vlan_tag =
2001 cpu_to_le16((u16)(f->vlan));
2002 }
41c445ff 2003 add_list[num_add].queue_number = 0;
41c445ff 2004 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2005 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2006 num_add++;
2007
2008 /* flush a full buffer */
2009 if (num_add == filter_list_len) {
3e25a8f3 2010 aq_ret = i40e_aq_add_macvlan(hw, vsi->seid,
ea02e90b
MW		 2011 add_list, num_add,
2012 NULL);
3e25a8f3 2013 aq_err = hw->aq.asq_last_status;
c3c7ea27
MW		 2014 fcnt = i40e_update_filter_state(num_add,
2015 add_list,
2016 add_head,
2017 aq_ret);
2018 vsi->active_filters += fcnt;
2019
2020 if (fcnt != num_add) {
2021 promisc_changed = true;
2022 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2023 &vsi->state);
2024 vsi->promisc_threshold =
2025 (vsi->active_filters * 3) / 4;
2026 dev_warn(&pf->pdev->dev,
2027 "Error %s adding RX filters on %s, promiscuous mode forced on\n",
2028 i40e_aq_str(hw, aq_err),
2029 vsi_name);
2030 }
2031 memset(add_list, 0, list_size);
41c445ff 2032 num_add = 0;
41c445ff
JB		 2033 }
2034 }
2035 if (num_add) {
3e25a8f3 2036 aq_ret = i40e_aq_add_macvlan(hw, vsi->seid,
ea02e90b 2037 add_list, num_add, NULL);
3e25a8f3 2038 aq_err = hw->aq.asq_last_status;
c3c7ea27
MW		 2039 fcnt = i40e_update_filter_state(num_add, add_list,
2040 add_head, aq_ret);
2041 vsi->active_filters += fcnt;
2042 if (fcnt != num_add) {
2043 promisc_changed = true;
2044 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2045 &vsi->state);
2046 vsi->promisc_threshold =
2047 (vsi->active_filters * 3) / 4;
2048 dev_warn(&pf->pdev->dev,
2049 "Error %s adding RX filters on %s, promiscuous mode forced on\n",
2050 i40e_aq_str(hw, aq_err), vsi_name);
2051 }
41c445ff 2052 }
c3c7ea27
MW		 2053 /* Now move all of the filters from the temp add list back to
2054 * the VSI's list.
2055 */
2056 spin_lock_bh(&vsi->mac_filter_list_lock);
2057 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
2058 list_move_tail(&f->list, &vsi->mac_filter_list);
2059 }
2060 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2061 kfree(add_list);
2062 add_list = NULL;
c3c7ea27 2063 }
41c445ff 2064
c3c7ea27
MW		 2065 /* Check to see if we can drop out of overflow promiscuous mode. */
2066 if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state) &&
2067 (vsi->active_filters < vsi->promisc_threshold)) {
2068 int failed_count = 0;
2069 /* See if we have any failed filters. We can't drop out of
2070 * promiscuous until these have all been deleted.
2071 */
2072 spin_lock_bh(&vsi->mac_filter_list_lock);
2073 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2074 if (f->state == I40E_FILTER_FAILED)
2075 failed_count++;
2076 }
2077 spin_unlock_bh(&vsi->mac_filter_list_lock);
2078 if (!failed_count) {
41c445ff 2079 dev_info(&pf->pdev->dev,
c3c7ea27
MW		 2080 "filter logjam cleared on %s, leaving overflow promiscuous mode\n",
2081 vsi_name);
2082 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state);
2083 promisc_changed = true;
2084 vsi->promisc_threshold = 0;
41c445ff
JB		 2085 }
2086 }
2087
a856b5cb
ASJ		 2088 /* if the VF is not trusted do not do promisc */
2089 if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) {
2090 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state);
2091 goto out;
2092 }
2093
41c445ff
JB		 2094 /* check for changes in promiscuous modes */
2095 if (changed_flags & IFF_ALLMULTI) {
2096 bool cur_multipromisc;
6995b36c 2097
41c445ff 2098 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2099 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2100 vsi->seid,
2101 cur_multipromisc,
2102 NULL);
2103 if (aq_ret) {
2104 retval = i40e_aq_rc_to_posix(aq_ret,
3e25a8f3 2105 hw->aq.asq_last_status);
41c445ff 2106 dev_info(&pf->pdev->dev,
2d1de828
SN		 2107 "set multi promisc failed on %s, err %s aq_err %s\n",
2108 vsi_name,
3e25a8f3
MW		 2109 i40e_stat_str(hw, aq_ret),
2110 i40e_aq_str(hw, hw->aq.asq_last_status));
ea02e90b 2111 }
41c445ff 2112 }
c3c7ea27
MW		 2113 if ((changed_flags & IFF_PROMISC) ||
2114 (promisc_changed &&
2115 test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state))) {
41c445ff 2116 bool cur_promisc;
6995b36c 2117
41c445ff
JB		 2118 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2119 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2120 &vsi->state));
6784ed5a
ASJ		 2121 if ((vsi->type == I40E_VSI_MAIN) &&
2122 (pf->lan_veb != I40E_NO_VEB) &&
2123 !(pf->flags & I40E_FLAG_MFP_ENABLED)) {
92faef85
ASJ		 2124 /* set defport ON for Main VSI instead of true promisc
2125 * this way we will get all unicast/multicast and VLAN
2126 * promisc behavior but will not get VF or VMDq traffic
2127 * replicated on the Main VSI.
2128 */
2129 if (pf->cur_promisc != cur_promisc) {
2130 pf->cur_promisc = cur_promisc;
5bc16031
MW		 2131 if (cur_promisc)
2132 aq_ret =
2133 i40e_aq_set_default_vsi(hw,
2134 vsi->seid,
2135 NULL);
2136 else
2137 aq_ret =
2138 i40e_aq_clear_default_vsi(hw,
2139 vsi->seid,
2140 NULL);
2141 if (aq_ret) {
2142 retval = i40e_aq_rc_to_posix(aq_ret,
2143 hw->aq.asq_last_status);
2144 dev_info(&pf->pdev->dev,
2d1de828
SN		 2145 "Set default VSI failed on %s, err %s, aq_err %s\n",
2146 vsi_name,
5bc16031
MW		 2147 i40e_stat_str(hw, aq_ret),
2148 i40e_aq_str(hw,
2149 hw->aq.asq_last_status));
2150 }
92faef85
ASJ		 2151 }
2152 } else {
ea02e90b 2153 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
3e25a8f3 2154 hw,
f1c7e72e 2155 vsi->seid,
b5569892
ASJ		 2156 cur_promisc, NULL,
2157 true);
ea02e90b
MW		 2158 if (aq_ret) {
2159 retval =
2160 i40e_aq_rc_to_posix(aq_ret,
3e25a8f3 2161 hw->aq.asq_last_status);
92faef85 2162 dev_info(&pf->pdev->dev,
2d1de828
SN		 2163 "set unicast promisc failed on %s, err %s, aq_err %s\n",
2164 vsi_name,
3e25a8f3
MW		 2165 i40e_stat_str(hw, aq_ret),
2166 i40e_aq_str(hw,
2167 hw->aq.asq_last_status));
ea02e90b
MW		 2168 }
2169 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
3e25a8f3 2170 hw,
92faef85
ASJ		 2171 vsi->seid,
2172 cur_promisc, NULL);
ea02e90b
MW		 2173 if (aq_ret) {
2174 retval =
2175 i40e_aq_rc_to_posix(aq_ret,
3e25a8f3 2176 hw->aq.asq_last_status);
92faef85 2177 dev_info(&pf->pdev->dev,
2d1de828
SN		 2178 "set multicast promisc failed on %s, err %s, aq_err %s\n",
2179 vsi_name,
3e25a8f3
MW		 2180 i40e_stat_str(hw, aq_ret),
2181 i40e_aq_str(hw,
2182 hw->aq.asq_last_status));
ea02e90b 2183 }
92faef85 2184 }
ea02e90b
MW		 2185 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2186 vsi->seid,
2187 cur_promisc, NULL);
2188 if (aq_ret) {
2189 retval = i40e_aq_rc_to_posix(aq_ret,
2190 pf->hw.aq.asq_last_status);
1a10370a 2191 dev_info(&pf->pdev->dev,
f1c7e72e 2192 "set brdcast promisc failed, err %s, aq_err %s\n",
3e25a8f3
MW		 2193 i40e_stat_str(hw, aq_ret),
2194 i40e_aq_str(hw,
2195 hw->aq.asq_last_status));
ea02e90b 2196 }
41c445ff 2197 }
ea02e90b 2198out:
2818ccd9
JB		 2199 /* if something went wrong then set the changed flag so we try again */
2200 if (retval)
2201 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2202
41c445ff 2203 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2204 return retval;
41c445ff
JB		 2205}
2206
2207/**
2208 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2209 * @pf: board private structure
2210 **/
2211static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2212{
2213 int v;
2214
2215 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2216 return;
2217 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2218
505682cd 2219 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2220 if (pf->vsi[v] &&
17652c63
JB		 2221 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2222 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2223
2224 if (ret) {
2225 /* come back and try again later */
2226 pf->flags |= I40E_FLAG_FILTER_SYNC;
2227 break;
2228 }
2229 }
41c445ff
JB		 2230 }
2231}
2232
2233/**
2234 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2235 * @netdev: network interface device structure
2236 * @new_mtu: new value for maximum frame size
2237 *
2238 * Returns 0 on success, negative on failure
2239 **/
2240static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2241{
2242 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2243 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2244 struct i40e_vsi *vsi = np->vsi;
2245
2246 /* MTU < 68 is an error and causes problems on some kernels */
2247 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2248 return -EINVAL;
2249
2250 netdev_info(netdev, "changing MTU from %d to %d\n",
2251 netdev->mtu, new_mtu);
2252 netdev->mtu = new_mtu;
2253 if (netif_running(netdev))
2254 i40e_vsi_reinit_locked(vsi);
e3219ce6 2255 i40e_notify_client_of_l2_param_changes(vsi);
41c445ff
JB		 2256 return 0;
2257}
2258
beb0dff1
JK		 2259/**
2260 * i40e_ioctl - Access the hwtstamp interface
2261 * @netdev: network interface device structure
2262 * @ifr: interface request data
2263 * @cmd: ioctl command
2264 **/
2265int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2266{
2267 struct i40e_netdev_priv *np = netdev_priv(netdev);
2268 struct i40e_pf *pf = np->vsi->back;
2269
2270 switch (cmd) {
2271 case SIOCGHWTSTAMP:
2272 return i40e_ptp_get_ts_config(pf, ifr);
2273 case SIOCSHWTSTAMP:
2274 return i40e_ptp_set_ts_config(pf, ifr);
2275 default:
2276 return -EOPNOTSUPP;
2277 }
2278}
2279
41c445ff
JB		 2280/**
2281 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2282 * @vsi: the vsi being adjusted
2283 **/
2284void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2285{
2286 struct i40e_vsi_context ctxt;
2287 i40e_status ret;
2288
2289 if ((vsi->info.valid_sections &
2290 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2291 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2292 return; /* already enabled */
2293
2294 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2295 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2296 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2297
2298 ctxt.seid = vsi->seid;
1a2f6248 2299 ctxt.info = vsi->info;
41c445ff
JB		 2300 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2301 if (ret) {
2302 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2303 "update vlan stripping failed, err %s aq_err %s\n",
2304 i40e_stat_str(&vsi->back->hw, ret),
2305 i40e_aq_str(&vsi->back->hw,
2306 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2307 }
2308}
2309
2310/**
2311 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2312 * @vsi: the vsi being adjusted
2313 **/
2314void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2315{
2316 struct i40e_vsi_context ctxt;
2317 i40e_status ret;
2318
2319 if ((vsi->info.valid_sections &
2320 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2321 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2322 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2323 return; /* already disabled */
2324
2325 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2326 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2327 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2328
2329 ctxt.seid = vsi->seid;
1a2f6248 2330 ctxt.info = vsi->info;
41c445ff
JB		 2331 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2332 if (ret) {
2333 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2334 "update vlan stripping failed, err %s aq_err %s\n",
2335 i40e_stat_str(&vsi->back->hw, ret),
2336 i40e_aq_str(&vsi->back->hw,
2337 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2338 }
2339}
2340
2341/**
2342 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2343 * @netdev: network interface to be adjusted
2344 * @features: netdev features to test if VLAN offload is enabled or not
2345 **/
2346static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2347{
2348 struct i40e_netdev_priv *np = netdev_priv(netdev);
2349 struct i40e_vsi *vsi = np->vsi;
2350
2351 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2352 i40e_vlan_stripping_enable(vsi);
2353 else
2354 i40e_vlan_stripping_disable(vsi);
2355}
2356
2357/**
2358 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2359 * @vsi: the vsi being configured
2360 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2361 **/
2362int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2363{
c3c7ea27 2364 struct i40e_mac_filter *f, *ftmp, *add_f;
41c445ff 2365 bool is_netdev, is_vf;
41c445ff
JB		 2366
2367 is_vf = (vsi->type == I40E_VSI_SRIOV);
2368 is_netdev = !!(vsi->netdev);
2369
21659035
KP		 2370 /* Locked once because all functions invoked below iterates list*/
2371 spin_lock_bh(&vsi->mac_filter_list_lock);
2372
41c445ff
JB		 2373 if (is_netdev) {
2374 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2375 is_vf, is_netdev);
2376 if (!add_f) {
2377 dev_info(&vsi->back->pdev->dev,
2378 "Could not add vlan filter %d for %pM\n",
2379 vid, vsi->netdev->dev_addr);
21659035 2380 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2381 return -ENOMEM;
2382 }
2383 }
2384
c3c7ea27 2385 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 2386 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2387 if (!add_f) {
2388 dev_info(&vsi->back->pdev->dev,
2389 "Could not add vlan filter %d for %pM\n",
2390 vid, f->macaddr);
21659035 2391 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2392 return -ENOMEM;
2393 }
2394 }
2395
41c445ff
JB		 2396 /* Now if we add a vlan tag, make sure to check if it is the first
2397 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2398 * with 0, so we now accept untagged and specified tagged traffic
c3c7ea27 2399 * (and not all tags along with untagged)
41c445ff
JB		 2400 */
2401 if (vid > 0) {
2402 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2403 I40E_VLAN_ANY,
2404 is_vf, is_netdev)) {
2405 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2406 I40E_VLAN_ANY, is_vf, is_netdev);
2407 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2408 is_vf, is_netdev);
2409 if (!add_f) {
2410 dev_info(&vsi->back->pdev->dev,
2411 "Could not add filter 0 for %pM\n",
2412 vsi->netdev->dev_addr);
21659035 2413 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2414 return -ENOMEM;
2415 }
2416 }
8d82a7c5 2417 }
41c445ff 2418
8d82a7c5
GR		 2419 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2420 if (vid > 0 && !vsi->info.pvid) {
c3c7ea27 2421 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
21659035
KP		 2422 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2423 is_vf, is_netdev))
2424 continue;
2425 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2426 is_vf, is_netdev);
2427 add_f = i40e_add_filter(vsi, f->macaddr,
2428 0, is_vf, is_netdev);
2429 if (!add_f) {
2430 dev_info(&vsi->back->pdev->dev,
2431 "Could not add filter 0 for %pM\n",
2432 f->macaddr);
2433 spin_unlock_bh(&vsi->mac_filter_list_lock);
2434 return -ENOMEM;
41c445ff
JB		 2435 }
2436 }
41c445ff
JB		 2437 }
2438
21659035
KP		 2439 spin_unlock_bh(&vsi->mac_filter_list_lock);
2440
0e4425ed
JB		 2441 /* schedule our worker thread which will take care of
2442 * applying the new filter changes
2443 */
2444 i40e_service_event_schedule(vsi->back);
2445 return 0;
41c445ff
JB		 2446}
2447
2448/**
2449 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2450 * @vsi: the vsi being configured
2451 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2452 *
2453 * Return: 0 on success or negative otherwise
41c445ff
JB		 2454 **/
2455int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2456{
2457 struct net_device *netdev = vsi->netdev;
c3c7ea27 2458 struct i40e_mac_filter *f, *ftmp, *add_f;
41c445ff
JB		 2459 bool is_vf, is_netdev;
2460 int filter_count = 0;
41c445ff
JB		 2461
2462 is_vf = (vsi->type == I40E_VSI_SRIOV);
2463 is_netdev = !!(netdev);
2464
21659035
KP		 2465 /* Locked once because all functions invoked below iterates list */
2466 spin_lock_bh(&vsi->mac_filter_list_lock);
2467
41c445ff
JB		 2468 if (is_netdev)
2469 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2470
c3c7ea27 2471 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
41c445ff
JB		 2472 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2473
41c445ff
JB		 2474 /* go through all the filters for this VSI and if there is only
2475 * vid == 0 it means there are no other filters, so vid 0 must
2476 * be replaced with -1. This signifies that we should from now
2477 * on accept any traffic (with any tag present, or untagged)
2478 */
2479 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2480 if (is_netdev) {
2481 if (f->vlan &&
2482 ether_addr_equal(netdev->dev_addr, f->macaddr))
2483 filter_count++;
2484 }
2485
2486 if (f->vlan)
2487 filter_count++;
2488 }
2489
2490 if (!filter_count && is_netdev) {
2491 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2492 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2493 is_vf, is_netdev);
2494 if (!f) {
2495 dev_info(&vsi->back->pdev->dev,
2496 "Could not add filter %d for %pM\n",
2497 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2498 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2499 return -ENOMEM;
2500 }
2501 }
2502
2503 if (!filter_count) {
c3c7ea27 2504 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 2505 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2506 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2507 is_vf, is_netdev);
41c445ff
JB		 2508 if (!add_f) {
2509 dev_info(&vsi->back->pdev->dev,
2510 "Could not add filter %d for %pM\n",
2511 I40E_VLAN_ANY, f->macaddr);
21659035 2512 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2513 return -ENOMEM;
2514 }
2515 }
2516 }
2517
21659035
KP		 2518 spin_unlock_bh(&vsi->mac_filter_list_lock);
2519
0e4425ed
JB		 2520 /* schedule our worker thread which will take care of
2521 * applying the new filter changes
2522 */
2523 i40e_service_event_schedule(vsi->back);
2524 return 0;
41c445ff
JB		 2525}
2526
2527/**
2528 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2529 * @netdev: network interface to be adjusted
2530 * @vid: vlan id to be added
078b5876
JB		 2531 *
2532 * net_device_ops implementation for adding vlan ids
41c445ff 2533 **/
38e00438
VD		 2534#ifdef I40E_FCOE
2535int i40e_vlan_rx_add_vid(struct net_device *netdev,
2536 __always_unused __be16 proto, u16 vid)
2537#else
41c445ff
JB		 2538static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2539 __always_unused __be16 proto, u16 vid)
38e00438 2540#endif
41c445ff
JB		 2541{
2542 struct i40e_netdev_priv *np = netdev_priv(netdev);
2543 struct i40e_vsi *vsi = np->vsi;
078b5876 2544 int ret = 0;
41c445ff
JB		 2545
2546 if (vid > 4095)
078b5876
JB		 2547 return -EINVAL;
2548
6982d429
ASJ		 2549 /* If the network stack called us with vid = 0 then
2550 * it is asking to receive priority tagged packets with
2551 * vlan id 0. Our HW receives them by default when configured
2552 * to receive untagged packets so there is no need to add an
2553 * extra filter for vlan 0 tagged packets.
41c445ff 2554 */
6982d429
ASJ		 2555 if (vid)
2556 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2557
078b5876
JB		 2558 if (!ret && (vid < VLAN_N_VID))
2559 set_bit(vid, vsi->active_vlans);
41c445ff 2560
078b5876 2561 return ret;
41c445ff
JB		 2562}
2563
2564/**
2565 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2566 * @netdev: network interface to be adjusted
2567 * @vid: vlan id to be removed
078b5876 2568 *
fdfd943e 2569 * net_device_ops implementation for removing vlan ids
41c445ff 2570 **/
38e00438
VD		 2571#ifdef I40E_FCOE
2572int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2573 __always_unused __be16 proto, u16 vid)
2574#else
41c445ff
JB		 2575static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2576 __always_unused __be16 proto, u16 vid)
38e00438 2577#endif
41c445ff
JB		 2578{
2579 struct i40e_netdev_priv *np = netdev_priv(netdev);
2580 struct i40e_vsi *vsi = np->vsi;
2581
41c445ff
JB		 2582 /* return code is ignored as there is nothing a user
2583 * can do about failure to remove and a log message was
078b5876 2584 * already printed from the other function
41c445ff
JB		 2585 */
2586 i40e_vsi_kill_vlan(vsi, vid);
2587
2588 clear_bit(vid, vsi->active_vlans);
078b5876 2589
41c445ff
JB		 2590 return 0;
2591}
2592
b1b15df5
TD		 2593/**
2594 * i40e_macaddr_init - explicitly write the mac address filters
2595 *
2596 * @vsi: pointer to the vsi
2597 * @macaddr: the MAC address
2598 *
2599 * This is needed when the macaddr has been obtained by other
2600 * means than the default, e.g., from Open Firmware or IDPROM.
2601 * Returns 0 on success, negative on failure
2602 **/
2603static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr)
2604{
2605 int ret;
2606 struct i40e_aqc_add_macvlan_element_data element;
2607
2608 ret = i40e_aq_mac_address_write(&vsi->back->hw,
2609 I40E_AQC_WRITE_TYPE_LAA_WOL,
2610 macaddr, NULL);
2611 if (ret) {
2612 dev_info(&vsi->back->pdev->dev,
2613 "Addr change for VSI failed: %d\n", ret);
2614 return -EADDRNOTAVAIL;
2615 }
2616
2617 memset(&element, 0, sizeof(element));
2618 ether_addr_copy(element.mac_addr, macaddr);
2619 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
2620 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL);
2621 if (ret) {
2622 dev_info(&vsi->back->pdev->dev,
2623 "add filter failed err %s aq_err %s\n",
2624 i40e_stat_str(&vsi->back->hw, ret),
2625 i40e_aq_str(&vsi->back->hw,
2626 vsi->back->hw.aq.asq_last_status));
2627 }
2628 return ret;
2629}
2630
41c445ff
JB		 2631/**
2632 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2633 * @vsi: the vsi being brought back up
2634 **/
2635static void i40e_restore_vlan(struct i40e_vsi *vsi)
2636{
2637 u16 vid;
2638
2639 if (!vsi->netdev)
2640 return;
2641
2642 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2643
2644 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2645 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2646 vid);
2647}
2648
2649/**
2650 * i40e_vsi_add_pvid - Add pvid for the VSI
2651 * @vsi: the vsi being adjusted
2652 * @vid: the vlan id to set as a PVID
2653 **/
dcae29be 2654int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2655{
2656 struct i40e_vsi_context ctxt;
f1c7e72e 2657 i40e_status ret;
41c445ff
JB		 2658
2659 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2660 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2661 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2662 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2663 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2664
2665 ctxt.seid = vsi->seid;
1a2f6248 2666 ctxt.info = vsi->info;
f1c7e72e
SN		 2667 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2668 if (ret) {
41c445ff 2669 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2670 "add pvid failed, err %s aq_err %s\n",
2671 i40e_stat_str(&vsi->back->hw, ret),
2672 i40e_aq_str(&vsi->back->hw,
2673 vsi->back->hw.aq.asq_last_status));
dcae29be 2674 return -ENOENT;
41c445ff
JB		 2675 }
2676
dcae29be 2677 return 0;
41c445ff
JB		 2678}
2679
2680/**
2681 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2682 * @vsi: the vsi being adjusted
2683 *
2684 * Just use the vlan_rx_register() service to put it back to normal
2685 **/
2686void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2687{
6c12fcbf
GR		 2688 i40e_vlan_stripping_disable(vsi);
2689
41c445ff 2690 vsi->info.pvid = 0;
41c445ff
JB		 2691}
2692
2693/**
2694 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2695 * @vsi: ptr to the VSI
2696 *
2697 * If this function returns with an error, then it's possible one or
2698 * more of the rings is populated (while the rest are not). It is the
2699 * callers duty to clean those orphaned rings.
2700 *
2701 * Return 0 on success, negative on failure
2702 **/
2703static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2704{
2705 int i, err = 0;
2706
2707 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2708 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2709
2710 return err;
2711}
2712
2713/**
2714 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2715 * @vsi: ptr to the VSI
2716 *
2717 * Free VSI's transmit software resources
2718 **/
2719static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2720{
2721 int i;
2722
8e9dca53
GR		 2723 if (!vsi->tx_rings)
2724 return;
2725
41c445ff 2726 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2727 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2728 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2729}
2730
2731/**
2732 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2733 * @vsi: ptr to the VSI
2734 *
2735 * If this function returns with an error, then it's possible one or
2736 * more of the rings is populated (while the rest are not). It is the
2737 * callers duty to clean those orphaned rings.
2738 *
2739 * Return 0 on success, negative on failure
2740 **/
2741static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2742{
2743 int i, err = 0;
2744
2745 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2746 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2747#ifdef I40E_FCOE
2748 i40e_fcoe_setup_ddp_resources(vsi);
2749#endif
41c445ff
JB		 2750 return err;
2751}
2752
2753/**
2754 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2755 * @vsi: ptr to the VSI
2756 *
2757 * Free all receive software resources
2758 **/
2759static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2760{
2761 int i;
2762
8e9dca53
GR		 2763 if (!vsi->rx_rings)
2764 return;
2765
41c445ff 2766 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2767 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2768 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2769#ifdef I40E_FCOE
2770 i40e_fcoe_free_ddp_resources(vsi);
2771#endif
41c445ff
JB		 2772}
2773
3ffa037d
NP		 2774/**
2775 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2776 * @ring: The Tx ring to configure
2777 *
2778 * This enables/disables XPS for a given Tx descriptor ring
2779 * based on the TCs enabled for the VSI that ring belongs to.
2780 **/
2781static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2782{
2783 struct i40e_vsi *vsi = ring->vsi;
2784 cpumask_var_t mask;
2785
9a660eea
JB		 2786 if (!ring->q_vector || !ring->netdev)
2787 return;
2788
2789 /* Single TC mode enable XPS */
2790 if (vsi->tc_config.numtc <= 1) {
2791 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2792 netif_set_xps_queue(ring->netdev,
2793 &ring->q_vector->affinity_mask,
2794 ring->queue_index);
9a660eea
JB		 2795 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2796 /* Disable XPS to allow selection based on TC */
2797 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2798 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2799 free_cpumask_var(mask);
3ffa037d 2800 }
0e4425ed
JB		 2801
2802 /* schedule our worker thread which will take care of
2803 * applying the new filter changes
2804 */
2805 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2806}
2807
41c445ff
JB		 2808/**
2809 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2810 * @ring: The Tx ring to configure
2811 *
2812 * Configure the Tx descriptor ring in the HMC context.
2813 **/
2814static int i40e_configure_tx_ring(struct i40e_ring *ring)
2815{
2816 struct i40e_vsi *vsi = ring->vsi;
2817 u16 pf_q = vsi->base_queue + ring->queue_index;
2818 struct i40e_hw *hw = &vsi->back->hw;
2819 struct i40e_hmc_obj_txq tx_ctx;
2820 i40e_status err = 0;
2821 u32 qtx_ctl = 0;
2822
2823 /* some ATR related tx ring init */
60ea5f83 2824 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2825 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2826 ring->atr_count = 0;
2827 } else {
2828 ring->atr_sample_rate = 0;
2829 }
2830
3ffa037d
NP		 2831 /* configure XPS */
2832 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2833
2834 /* clear the context structure first */
2835 memset(&tx_ctx, 0, sizeof(tx_ctx));
2836
2837 tx_ctx.new_context = 1;
2838 tx_ctx.base = (ring->dma / 128);
2839 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2840 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2841 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2842#ifdef I40E_FCOE
2843 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2844#endif
beb0dff1 2845 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2846 /* FDIR VSI tx ring can still use RS bit and writebacks */
2847 if (vsi->type != I40E_VSI_FDIR)
2848 tx_ctx.head_wb_ena = 1;
2849 tx_ctx.head_wb_addr = ring->dma +
2850 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2851
2852 /* As part of VSI creation/update, FW allocates certain
2853 * Tx arbitration queue sets for each TC enabled for
2854 * the VSI. The FW returns the handles to these queue
2855 * sets as part of the response buffer to Add VSI,
2856 * Update VSI, etc. AQ commands. It is expected that
2857 * these queue set handles be associated with the Tx
2858 * queues by the driver as part of the TX queue context
2859 * initialization. This has to be done regardless of
2860 * DCB as by default everything is mapped to TC0.
2861 */
2862 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2863 tx_ctx.rdylist_act = 0;
2864
2865 /* clear the context in the HMC */
2866 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2867 if (err) {
2868 dev_info(&vsi->back->pdev->dev,
2869 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2870 ring->queue_index, pf_q, err);
2871 return -ENOMEM;
2872 }
2873
2874 /* set the context in the HMC */
2875 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2876 if (err) {
2877 dev_info(&vsi->back->pdev->dev,
2878 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2879 ring->queue_index, pf_q, err);
2880 return -ENOMEM;
2881 }
2882
2883 /* Now associate this queue with this PCI function */
7a28d885 2884 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2885 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2886 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2887 I40E_QTX_CTL_VFVM_INDX_MASK;
2888 } else {
9d8bf547 2889 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2890 }
2891
13fd9774
SN		 2892 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2893 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2894 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2895 i40e_flush(hw);
2896
41c445ff
JB		 2897 /* cache tail off for easier writes later */
2898 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2899
2900 return 0;
2901}
2902
2903/**
2904 * i40e_configure_rx_ring - Configure a receive ring context
2905 * @ring: The Rx ring to configure
2906 *
2907 * Configure the Rx descriptor ring in the HMC context.
2908 **/
2909static int i40e_configure_rx_ring(struct i40e_ring *ring)
2910{
2911 struct i40e_vsi *vsi = ring->vsi;
2912 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2913 u16 pf_q = vsi->base_queue + ring->queue_index;
2914 struct i40e_hw *hw = &vsi->back->hw;
2915 struct i40e_hmc_obj_rxq rx_ctx;
2916 i40e_status err = 0;
2917
2918 ring->state = 0;
2919
2920 /* clear the context structure first */
2921 memset(&rx_ctx, 0, sizeof(rx_ctx));
2922
2923 ring->rx_buf_len = vsi->rx_buf_len;
41c445ff
JB		 2924
2925 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
41c445ff
JB		 2926
2927 rx_ctx.base = (ring->dma / 128);
2928 rx_ctx.qlen = ring->count;
2929
bec60fc4
JB		 2930 /* use 32 byte descriptors */
2931 rx_ctx.dsize = 1;
41c445ff 2932
bec60fc4
JB		 2933 /* descriptor type is always zero
2934 * rx_ctx.dtype = 0;
2935 */
b32bfa17 2936 rx_ctx.hsplit_0 = 0;
41c445ff 2937
b32bfa17 2938 rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len);
7134f9ce
JB		 2939 if (hw->revision_id == 0)
2940 rx_ctx.lrxqthresh = 0;
2941 else
2942 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2943 rx_ctx.crcstrip = 1;
2944 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2945 /* this controls whether VLAN is stripped from inner headers */
2946 rx_ctx.showiv = 0;
38e00438
VD		 2947#ifdef I40E_FCOE
2948 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2949#endif
acb3676b
CS		 2950 /* set the prefena field to 1 because the manual says to */
2951 rx_ctx.prefena = 1;
41c445ff
JB		 2952
2953 /* clear the context in the HMC */
2954 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2955 if (err) {
2956 dev_info(&vsi->back->pdev->dev,
2957 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2958 ring->queue_index, pf_q, err);
2959 return -ENOMEM;
2960 }
2961
2962 /* set the context in the HMC */
2963 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2964 if (err) {
2965 dev_info(&vsi->back->pdev->dev,
2966 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2967 ring->queue_index, pf_q, err);
2968 return -ENOMEM;
2969 }
2970
2971 /* cache tail for quicker writes, and clear the reg before use */
2972 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2973 writel(0, ring->tail);
2974
1a557afc 2975 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
41c445ff
JB		 2976
2977 return 0;
2978}
2979
2980/**
2981 * i40e_vsi_configure_tx - Configure the VSI for Tx
2982 * @vsi: VSI structure describing this set of rings and resources
2983 *
2984 * Configure the Tx VSI for operation.
2985 **/
2986static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2987{
2988 int err = 0;
2989 u16 i;
2990
9f65e15b
AD		 2991 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2992 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2993
2994 return err;
2995}
2996
2997/**
2998 * i40e_vsi_configure_rx - Configure the VSI for Rx
2999 * @vsi: the VSI being configured
3000 *
3001 * Configure the Rx VSI for operation.
3002 **/
3003static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
3004{
3005 int err = 0;
3006 u16 i;
3007
3008 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
3009 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
3010 + ETH_FCS_LEN + VLAN_HLEN;
3011 else
3012 vsi->max_frame = I40E_RXBUFFER_2048;
3013
1a557afc 3014 vsi->rx_buf_len = I40E_RXBUFFER_2048;
41c445ff 3015
38e00438
VD		 3016#ifdef I40E_FCOE
3017 /* setup rx buffer for FCoE */
3018 if ((vsi->type == I40E_VSI_FCOE) &&
3019 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
38e00438
VD		 3020 vsi->rx_buf_len = I40E_RXBUFFER_3072;
3021 vsi->max_frame = I40E_RXBUFFER_3072;
38e00438
VD		 3022 }
3023
3024#endif /* I40E_FCOE */
41c445ff 3025 /* round up for the chip's needs */
41c445ff 3026 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 3027 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 3028
3029 /* set up individual rings */
3030 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 3031 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3032
3033 return err;
3034}
3035
3036/**
3037 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
3038 * @vsi: ptr to the VSI
3039 **/
3040static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
3041{
e7046ee1 3042 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 3043 u16 qoffset, qcount;
3044 int i, n;
3045
cd238a3e
PN		 3046 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3047 /* Reset the TC information */
3048 for (i = 0; i < vsi->num_queue_pairs; i++) {
3049 rx_ring = vsi->rx_rings[i];
3050 tx_ring = vsi->tx_rings[i];
3051 rx_ring->dcb_tc = 0;
3052 tx_ring->dcb_tc = 0;
3053 }
3054 }
41c445ff
JB		 3055
3056 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3057 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3058 continue;
3059
3060 qoffset = vsi->tc_config.tc_info[n].qoffset;
3061 qcount = vsi->tc_config.tc_info[n].qcount;
3062 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3063 rx_ring = vsi->rx_rings[i];
3064 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3065 rx_ring->dcb_tc = n;
3066 tx_ring->dcb_tc = n;
3067 }
3068 }
3069}
3070
3071/**
3072 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3073 * @vsi: ptr to the VSI
3074 **/
3075static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3076{
b1b15df5
TD		 3077 struct i40e_pf *pf = vsi->back;
3078 int err;
3079
41c445ff
JB		 3080 if (vsi->netdev)
3081 i40e_set_rx_mode(vsi->netdev);
b1b15df5
TD		 3082
3083 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
3084 err = i40e_macaddr_init(vsi, pf->hw.mac.addr);
3085 if (err) {
3086 dev_warn(&pf->pdev->dev,
3087 "could not set up macaddr; err %d\n", err);
3088 }
3089 }
41c445ff
JB		 3090}
3091
17a73f6b
JG		 3092/**
3093 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3094 * @vsi: Pointer to the targeted VSI
3095 *
3096 * This function replays the hlist on the hw where all the SB Flow Director
3097 * filters were saved.
3098 **/
3099static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3100{
3101 struct i40e_fdir_filter *filter;
3102 struct i40e_pf *pf = vsi->back;
3103 struct hlist_node *node;
3104
55a5e60b
ASJ		 3105 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3106 return;
3107
17a73f6b
JG		 3108 hlist_for_each_entry_safe(filter, node,
3109 &pf->fdir_filter_list, fdir_node) {
3110 i40e_add_del_fdir(vsi, filter, true);
3111 }
3112}
3113
41c445ff
JB		 3114/**
3115 * i40e_vsi_configure - Set up the VSI for action
3116 * @vsi: the VSI being configured
3117 **/
3118static int i40e_vsi_configure(struct i40e_vsi *vsi)
3119{
3120 int err;
3121
3122 i40e_set_vsi_rx_mode(vsi);
3123 i40e_restore_vlan(vsi);
3124 i40e_vsi_config_dcb_rings(vsi);
3125 err = i40e_vsi_configure_tx(vsi);
3126 if (!err)
3127 err = i40e_vsi_configure_rx(vsi);
3128
3129 return err;
3130}
3131
3132/**
3133 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3134 * @vsi: the VSI being configured
3135 **/
3136static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3137{
3138 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3139 struct i40e_hw *hw = &pf->hw;
3140 u16 vector;
3141 int i, q;
41c445ff
JB		 3142 u32 qp;
3143
3144 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3145 * and PFINT_LNKLSTn registers, e.g.:
3146 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3147 */
3148 qp = vsi->base_queue;
3149 vector = vsi->base_vector;
493fb300 3150 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3151 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3152
ee2319cf 3153 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3154 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting);
41c445ff
JB		 3155 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3156 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3157 q_vector->rx.itr);
a75e8005 3158 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting);
41c445ff
JB		 3159 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3160 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3161 q_vector->tx.itr);
ac26fc13
JB		 3162 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3163 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3164
3165 /* Linked list for the queuepairs assigned to this vector */
3166 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3167 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3168 u32 val;
3169
41c445ff
JB		 3170 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3171 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3172 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3173 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3174 (I40E_QUEUE_TYPE_TX
3175 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3176
3177 wr32(hw, I40E_QINT_RQCTL(qp), val);
3178
3179 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3180 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3181 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3182 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3183 (I40E_QUEUE_TYPE_RX
3184 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3185
3186 /* Terminate the linked list */
3187 if (q == (q_vector->num_ringpairs - 1))
3188 val |= (I40E_QUEUE_END_OF_LIST
3189 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3190
3191 wr32(hw, I40E_QINT_TQCTL(qp), val);
3192 qp++;
3193 }
3194 }
3195
3196 i40e_flush(hw);
3197}
3198
3199/**
3200 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3201 * @hw: ptr to the hardware info
3202 **/
ab437b5a 3203static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3204{
ab437b5a 3205 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3206 u32 val;
3207
3208 /* clear things first */
3209 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3210 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3211
3212 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3213 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3214 I40E_PFINT_ICR0_ENA_GRST_MASK |
3215 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3216 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3217 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3218 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3219 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3220
0d8e1439
ASJ		 3221 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3222 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3223
ab437b5a
JK		 3224 if (pf->flags & I40E_FLAG_PTP)
3225 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3226
41c445ff
JB		 3227 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3228
3229 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3230 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3231 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3232
3233 /* OTHER_ITR_IDX = 0 */
3234 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3235}
3236
3237/**
3238 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3239 * @vsi: the VSI being configured
3240 **/
3241static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3242{
493fb300 3243 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3244 struct i40e_pf *pf = vsi->back;
3245 struct i40e_hw *hw = &pf->hw;
3246 u32 val;
3247
3248 /* set the ITR configuration */
ee2319cf 3249 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3250 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting);
41c445ff
JB		 3251 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3252 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
a75e8005 3253 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting);
41c445ff
JB		 3254 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3255 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3256
ab437b5a 3257 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3258
3259 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3260 wr32(hw, I40E_PFINT_LNKLST0, 0);
3261
f29eaa3d 3262 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3263 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3264 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3265 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3266
3267 wr32(hw, I40E_QINT_RQCTL(0), val);
3268
3269 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3270 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3271 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3272
3273 wr32(hw, I40E_QINT_TQCTL(0), val);
3274 i40e_flush(hw);
3275}
3276
2ef28cfb
MW		 3277/**
3278 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3279 * @pf: board private structure
3280 **/
3281void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3282{
3283 struct i40e_hw *hw = &pf->hw;
3284
3285 wr32(hw, I40E_PFINT_DYN_CTL0,
3286 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3287 i40e_flush(hw);
3288}
3289
41c445ff
JB		 3290/**
3291 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3292 * @pf: board private structure
40d72a50 3293 * @clearpba: true when all pending interrupt events should be cleared
41c445ff 3294 **/
40d72a50 3295void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba)
41c445ff
JB		 3296{
3297 struct i40e_hw *hw = &pf->hw;
3298 u32 val;
3299
3300 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
40d72a50 3301 (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) |
41c445ff
JB		 3302 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3303
3304 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3305 i40e_flush(hw);
3306}
3307
41c445ff
JB		 3308/**
3309 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3310 * @irq: interrupt number
3311 * @data: pointer to a q_vector
3312 **/
3313static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3314{
3315 struct i40e_q_vector *q_vector = data;
3316
cd0b6fa6 3317 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3318 return IRQ_HANDLED;
3319
5d3465a1 3320 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3321
3322 return IRQ_HANDLED;
3323}
3324
41c445ff
JB		 3325/**
3326 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3327 * @vsi: the VSI being configured
3328 * @basename: name for the vector
3329 *
3330 * Allocates MSI-X vectors and requests interrupts from the kernel.
3331 **/
3332static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3333{
3334 int q_vectors = vsi->num_q_vectors;
3335 struct i40e_pf *pf = vsi->back;
3336 int base = vsi->base_vector;
3337 int rx_int_idx = 0;
3338 int tx_int_idx = 0;
3339 int vector, err;
3340
3341 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3342 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3343
cd0b6fa6 3344 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3345 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3346 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3347 tx_int_idx++;
cd0b6fa6 3348 } else if (q_vector->rx.ring) {
41c445ff
JB		 3349 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3350 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3351 } else if (q_vector->tx.ring) {
41c445ff
JB		 3352 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3353 "%s-%s-%d", basename, "tx", tx_int_idx++);
3354 } else {
3355 /* skip this unused q_vector */
3356 continue;
3357 }
3358 err = request_irq(pf->msix_entries[base + vector].vector,
3359 vsi->irq_handler,
3360 0,
3361 q_vector->name,
3362 q_vector);
3363 if (err) {
3364 dev_info(&pf->pdev->dev,
fb43201f 3365 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3366 goto free_queue_irqs;
3367 }
3368 /* assign the mask for this irq */
3369 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3370 &q_vector->affinity_mask);
3371 }
3372
63741846 3373 vsi->irqs_ready = true;
41c445ff
JB		 3374 return 0;
3375
3376free_queue_irqs:
3377 while (vector) {
3378 vector--;
3379 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3380 NULL);
3381 free_irq(pf->msix_entries[base + vector].vector,
3382 &(vsi->q_vectors[vector]));
3383 }
3384 return err;
3385}
3386
3387/**
3388 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3389 * @vsi: the VSI being un-configured
3390 **/
3391static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3392{
3393 struct i40e_pf *pf = vsi->back;
3394 struct i40e_hw *hw = &pf->hw;
3395 int base = vsi->base_vector;
3396 int i;
3397
3398 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3399 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3400 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3401 }
3402
3403 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3404 for (i = vsi->base_vector;
3405 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3406 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3407
3408 i40e_flush(hw);
3409 for (i = 0; i < vsi->num_q_vectors; i++)
3410 synchronize_irq(pf->msix_entries[i + base].vector);
3411 } else {
3412 /* Legacy and MSI mode - this stops all interrupt handling */
3413 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3414 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3415 i40e_flush(hw);
3416 synchronize_irq(pf->pdev->irq);
3417 }
3418}
3419
3420/**
3421 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3422 * @vsi: the VSI being configured
3423 **/
3424static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3425{
3426 struct i40e_pf *pf = vsi->back;
3427 int i;
3428
3429 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3430 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3431 i40e_irq_dynamic_enable(vsi, i);
3432 } else {
40d72a50 3433 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 3434 }
3435
1022cb6c 3436 i40e_flush(&pf->hw);
41c445ff
JB		 3437 return 0;
3438}
3439
3440/**
3441 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3442 * @pf: board private structure
3443 **/
3444static void i40e_stop_misc_vector(struct i40e_pf *pf)
3445{
3446 /* Disable ICR 0 */
3447 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3448 i40e_flush(&pf->hw);
3449}
3450
3451/**
3452 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3453 * @irq: interrupt number
3454 * @data: pointer to a q_vector
3455 *
3456 * This is the handler used for all MSI/Legacy interrupts, and deals
3457 * with both queue and non-queue interrupts. This is also used in
3458 * MSIX mode to handle the non-queue interrupts.
3459 **/
3460static irqreturn_t i40e_intr(int irq, void *data)
3461{
3462 struct i40e_pf *pf = (struct i40e_pf *)data;
3463 struct i40e_hw *hw = &pf->hw;
5e823066 3464 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3465 u32 icr0, icr0_remaining;
3466 u32 val, ena_mask;
3467
3468 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3469 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3470
116a57d4
SN		 3471 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3472 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3473 goto enable_intr;
41c445ff 3474
cd92e72f
SN		 3475 /* if interrupt but no bits showing, must be SWINT */
3476 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3477 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3478 pf->sw_int_count++;
3479
0d8e1439
ASJ		 3480 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3481 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3482 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3483 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3484 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3485 }
3486
41c445ff
JB		 3487 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3488 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3489 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3490 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff 3491
a16ae2d5
ASJ		 3492 /* We do not have a way to disarm Queue causes while leaving
3493 * interrupt enabled for all other causes, ideally
3494 * interrupt should be disabled while we are in NAPI but
3495 * this is not a performance path and napi_schedule()
3496 * can deal with rescheduling.
3497 */
41c445ff 3498 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3499 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3500 }
3501
3502 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3503 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3504 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6e93d0c9 3505 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n");
41c445ff
JB		 3506 }
3507
3508 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3509 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3510 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3511 }
3512
3513 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3514 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3515 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3516 }
3517
3518 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3519 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3520 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3521 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3522 val = rd32(hw, I40E_GLGEN_RSTAT);
3523 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3524 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3525 if (val == I40E_RESET_CORER) {
41c445ff 3526 pf->corer_count++;
4eb3f768 3527 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3528 pf->globr_count++;
4eb3f768 3529 } else if (val == I40E_RESET_EMPR) {
41c445ff 3530 pf->empr_count++;
9df42d1a 3531 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3532 }
41c445ff
JB		 3533 }
3534
9c010ee0
ASJ		 3535 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3536 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3537 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3538 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3539 rd32(hw, I40E_PFHMC_ERRORINFO),
3540 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3541 }
3542
beb0dff1
JK		 3543 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3544 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3545
3546 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3547 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3548 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3549 }
beb0dff1
JK		 3550 }
3551
41c445ff
JB		 3552 /* If a critical error is pending we have no choice but to reset the
3553 * device.
3554 * Report and mask out any remaining unexpected interrupts.
3555 */
3556 icr0_remaining = icr0 & ena_mask;
3557 if (icr0_remaining) {
3558 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3559 icr0_remaining);
9c010ee0 3560 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3561 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3562 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3563 dev_info(&pf->pdev->dev, "device will be reset\n");
3564 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3565 i40e_service_event_schedule(pf);
41c445ff
JB		 3566 }
3567 ena_mask &= ~icr0_remaining;
3568 }
5e823066 3569 ret = IRQ_HANDLED;
41c445ff 3570
5e823066 3571enable_intr:
41c445ff
JB		 3572 /* re-enable interrupt causes */
3573 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3574 if (!test_bit(__I40E_DOWN, &pf->state)) {
3575 i40e_service_event_schedule(pf);
40d72a50 3576 i40e_irq_dynamic_enable_icr0(pf, false);
41c445ff
JB		 3577 }
3578
5e823066 3579 return ret;
41c445ff
JB		 3580}
3581
cbf61325
ASJ		 3582/**
3583 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3584 * @tx_ring: tx ring to clean
3585 * @budget: how many cleans we're allowed
3586 *
3587 * Returns true if there's any budget left (e.g. the clean is finished)
3588 **/
3589static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3590{
3591 struct i40e_vsi *vsi = tx_ring->vsi;
3592 u16 i = tx_ring->next_to_clean;
3593 struct i40e_tx_buffer *tx_buf;
3594 struct i40e_tx_desc *tx_desc;
3595
3596 tx_buf = &tx_ring->tx_bi[i];
3597 tx_desc = I40E_TX_DESC(tx_ring, i);
3598 i -= tx_ring->count;
3599
3600 do {
3601 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3602
3603 /* if next_to_watch is not set then there is no work pending */
3604 if (!eop_desc)
3605 break;
3606
3607 /* prevent any other reads prior to eop_desc */
3608 read_barrier_depends();
3609
3610 /* if the descriptor isn't done, no work yet to do */
3611 if (!(eop_desc->cmd_type_offset_bsz &
3612 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3613 break;
3614
3615 /* clear next_to_watch to prevent false hangs */
3616 tx_buf->next_to_watch = NULL;
3617
49d7d933
ASJ		 3618 tx_desc->buffer_addr = 0;
3619 tx_desc->cmd_type_offset_bsz = 0;
3620 /* move past filter desc */
3621 tx_buf++;
3622 tx_desc++;
3623 i++;
3624 if (unlikely(!i)) {
3625 i -= tx_ring->count;
3626 tx_buf = tx_ring->tx_bi;
3627 tx_desc = I40E_TX_DESC(tx_ring, 0);
3628 }
cbf61325
ASJ		 3629 /* unmap skb header data */
3630 dma_unmap_single(tx_ring->dev,
3631 dma_unmap_addr(tx_buf, dma),
3632 dma_unmap_len(tx_buf, len),
3633 DMA_TO_DEVICE);
49d7d933
ASJ		 3634 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3635 kfree(tx_buf->raw_buf);
cbf61325 3636
49d7d933
ASJ		 3637 tx_buf->raw_buf = NULL;
3638 tx_buf->tx_flags = 0;
3639 tx_buf->next_to_watch = NULL;
cbf61325 3640 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3641 tx_desc->buffer_addr = 0;
3642 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3643
49d7d933 3644 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3645 tx_buf++;
3646 tx_desc++;
3647 i++;
3648 if (unlikely(!i)) {
3649 i -= tx_ring->count;
3650 tx_buf = tx_ring->tx_bi;
3651 tx_desc = I40E_TX_DESC(tx_ring, 0);
3652 }
3653
3654 /* update budget accounting */
3655 budget--;
3656 } while (likely(budget));
3657
3658 i += tx_ring->count;
3659 tx_ring->next_to_clean = i;
3660
6995b36c 3661 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3662 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3663
cbf61325
ASJ		 3664 return budget > 0;
3665}
3666
3667/**
3668 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3669 * @irq: interrupt number
3670 * @data: pointer to a q_vector
3671 **/
3672static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3673{
3674 struct i40e_q_vector *q_vector = data;
3675 struct i40e_vsi *vsi;
3676
3677 if (!q_vector->tx.ring)
3678 return IRQ_HANDLED;
3679
3680 vsi = q_vector->tx.ring->vsi;
3681 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3682
3683 return IRQ_HANDLED;
3684}
3685
41c445ff 3686/**
cd0b6fa6 3687 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3688 * @vsi: the VSI being configured
3689 * @v_idx: vector index
cd0b6fa6 3690 * @qp_idx: queue pair index
41c445ff 3691 **/
26cdc443 3692static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3693{
493fb300 3694 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3695 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3696 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3697
3698 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3699 tx_ring->next = q_vector->tx.ring;
3700 q_vector->tx.ring = tx_ring;
41c445ff 3701 q_vector->tx.count++;
cd0b6fa6
AD		 3702
3703 rx_ring->q_vector = q_vector;
3704 rx_ring->next = q_vector->rx.ring;
3705 q_vector->rx.ring = rx_ring;
3706 q_vector->rx.count++;
41c445ff
JB		 3707}
3708
3709/**
3710 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3711 * @vsi: the VSI being configured
3712 *
3713 * This function maps descriptor rings to the queue-specific vectors
3714 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3715 * one vector per queue pair, but on a constrained vector budget, we
3716 * group the queue pairs as "efficiently" as possible.
3717 **/
3718static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3719{
3720 int qp_remaining = vsi->num_queue_pairs;
3721 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3722 int num_ringpairs;
41c445ff
JB		 3723 int v_start = 0;
3724 int qp_idx = 0;
3725
3726 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3727 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3728 * It is also important to go through all the vectors available to be
3729 * sure that if we don't use all the vectors, that the remaining vectors
3730 * are cleared. This is especially important when decreasing the
3731 * number of queues in use.
41c445ff 3732 */
70114ec4 3733 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3734 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3735
3736 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3737
3738 q_vector->num_ringpairs = num_ringpairs;
3739
3740 q_vector->rx.count = 0;
3741 q_vector->tx.count = 0;
3742 q_vector->rx.ring = NULL;
3743 q_vector->tx.ring = NULL;
3744
3745 while (num_ringpairs--) {
26cdc443 3746 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3747 qp_idx++;
3748 qp_remaining--;
41c445ff
JB		 3749 }
3750 }
3751}
3752
3753/**
3754 * i40e_vsi_request_irq - Request IRQ from the OS
3755 * @vsi: the VSI being configured
3756 * @basename: name for the vector
3757 **/
3758static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3759{
3760 struct i40e_pf *pf = vsi->back;
3761 int err;
3762
3763 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3764 err = i40e_vsi_request_irq_msix(vsi, basename);
3765 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3766 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3767 pf->int_name, pf);
41c445ff
JB		 3768 else
3769 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3770 pf->int_name, pf);
41c445ff
JB		 3771
3772 if (err)
3773 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3774
3775 return err;
3776}
3777
3778#ifdef CONFIG_NET_POLL_CONTROLLER
3779/**
d89d967f 3780 * i40e_netpoll - A Polling 'interrupt' handler
41c445ff
JB		 3781 * @netdev: network interface device structure
3782 *
3783 * This is used by netconsole to send skbs without having to re-enable
3784 * interrupts. It's not called while the normal interrupt routine is executing.
3785 **/
38e00438
VD		 3786#ifdef I40E_FCOE
3787void i40e_netpoll(struct net_device *netdev)
3788#else
41c445ff 3789static void i40e_netpoll(struct net_device *netdev)
38e00438 3790#endif
41c445ff
JB		 3791{
3792 struct i40e_netdev_priv *np = netdev_priv(netdev);
3793 struct i40e_vsi *vsi = np->vsi;
3794 struct i40e_pf *pf = vsi->back;
3795 int i;
3796
3797 /* if interface is down do nothing */
3798 if (test_bit(__I40E_DOWN, &vsi->state))
3799 return;
3800
41c445ff
JB		 3801 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3802 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3803 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3804 } else {
3805 i40e_intr(pf->pdev->irq, netdev);
3806 }
41c445ff
JB		 3807}
3808#endif
3809
23527308
NP		 3810/**
3811 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3812 * @pf: the PF being configured
3813 * @pf_q: the PF queue
3814 * @enable: enable or disable state of the queue
3815 *
3816 * This routine will wait for the given Tx queue of the PF to reach the
3817 * enabled or disabled state.
3818 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3819 * multiple retries; else will return 0 in case of success.
3820 **/
3821static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3822{
3823 int i;
3824 u32 tx_reg;
3825
3826 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3827 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3828 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3829 break;
3830
f98a2006 3831 usleep_range(10, 20);
23527308
NP		 3832 }
3833 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3834 return -ETIMEDOUT;
3835
3836 return 0;
3837}
3838
41c445ff
JB		 3839/**
3840 * i40e_vsi_control_tx - Start or stop a VSI's rings
3841 * @vsi: the VSI being configured
3842 * @enable: start or stop the rings
3843 **/
3844static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3845{
3846 struct i40e_pf *pf = vsi->back;
3847 struct i40e_hw *hw = &pf->hw;
23527308 3848 int i, j, pf_q, ret = 0;
41c445ff
JB		 3849 u32 tx_reg;
3850
3851 pf_q = vsi->base_queue;
3852 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3853
3854 /* warn the TX unit of coming changes */
3855 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3856 if (!enable)
f98a2006 3857 usleep_range(10, 20);
351499ab 3858
6c5ef620 3859 for (j = 0; j < 50; j++) {
41c445ff 3860 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3861 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3862 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3863 break;
3864 usleep_range(1000, 2000);
3865 }
fda972f6 3866 /* Skip if the queue is already in the requested state */
7c122007 3867 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3868 continue;
41c445ff
JB		 3869
3870 /* turn on/off the queue */
c5c9eb9e
SN		 3871 if (enable) {
3872 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3873 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3874 } else {
41c445ff 3875 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3876 }
41c445ff
JB		 3877
3878 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3879 /* No waiting for the Tx queue to disable */
3880 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3881 continue;
41c445ff
JB		 3882
3883 /* wait for the change to finish */
23527308
NP		 3884 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3885 if (ret) {
3886 dev_info(&pf->pdev->dev,
fb43201f
SN		 3887 "VSI seid %d Tx ring %d %sable timeout\n",
3888 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3889 break;
41c445ff
JB		 3890 }
3891 }
3892
7134f9ce
JB		 3893 if (hw->revision_id == 0)
3894 mdelay(50);
23527308
NP		 3895 return ret;
3896}
3897
3898/**
3899 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3900 * @pf: the PF being configured
3901 * @pf_q: the PF queue
3902 * @enable: enable or disable state of the queue
3903 *
3904 * This routine will wait for the given Rx queue of the PF to reach the
3905 * enabled or disabled state.
3906 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3907 * multiple retries; else will return 0 in case of success.
3908 **/
3909static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3910{
3911 int i;
3912 u32 rx_reg;
3913
3914 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3915 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3916 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3917 break;
3918
f98a2006 3919 usleep_range(10, 20);
23527308
NP		 3920 }
3921 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3922 return -ETIMEDOUT;
7134f9ce 3923
41c445ff
JB		 3924 return 0;
3925}
3926
3927/**
3928 * i40e_vsi_control_rx - Start or stop a VSI's rings
3929 * @vsi: the VSI being configured
3930 * @enable: start or stop the rings
3931 **/
3932static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3933{
3934 struct i40e_pf *pf = vsi->back;
3935 struct i40e_hw *hw = &pf->hw;
23527308 3936 int i, j, pf_q, ret = 0;
41c445ff
JB		 3937 u32 rx_reg;
3938
3939 pf_q = vsi->base_queue;
3940 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3941 for (j = 0; j < 50; j++) {
41c445ff 3942 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3943 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3944 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3945 break;
3946 usleep_range(1000, 2000);
3947 }
41c445ff 3948
7c122007
CS		 3949 /* Skip if the queue is already in the requested state */
3950 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3951 continue;
41c445ff
JB		 3952
3953 /* turn on/off the queue */
3954 if (enable)
6c5ef620 3955 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3956 else
6c5ef620 3957 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3958 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3fe06f41
NP		 3959 /* No waiting for the Tx queue to disable */
3960 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3961 continue;
41c445ff
JB		 3962
3963 /* wait for the change to finish */
23527308
NP		 3964 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3965 if (ret) {
3966 dev_info(&pf->pdev->dev,
fb43201f
SN		 3967 "VSI seid %d Rx ring %d %sable timeout\n",
3968 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3969 break;
41c445ff
JB		 3970 }
3971 }
3972
23527308 3973 return ret;
41c445ff
JB		 3974}
3975
3976/**
3977 * i40e_vsi_control_rings - Start or stop a VSI's rings
3978 * @vsi: the VSI being configured
3979 * @enable: start or stop the rings
3980 **/
fc18eaa0 3981int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3982{
3b867b28 3983 int ret = 0;
41c445ff
JB		 3984
3985 /* do rx first for enable and last for disable */
3986 if (request) {
3987 ret = i40e_vsi_control_rx(vsi, request);
3988 if (ret)
3989 return ret;
3990 ret = i40e_vsi_control_tx(vsi, request);
3991 } else {
3b867b28
ASJ		 3992 /* Ignore return value, we need to shutdown whatever we can */
3993 i40e_vsi_control_tx(vsi, request);
3994 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3995 }
3996
3997 return ret;
3998}
3999
4000/**
4001 * i40e_vsi_free_irq - Free the irq association with the OS
4002 * @vsi: the VSI being configured
4003 **/
4004static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
4005{
4006 struct i40e_pf *pf = vsi->back;
4007 struct i40e_hw *hw = &pf->hw;
4008 int base = vsi->base_vector;
4009 u32 val, qp;
4010 int i;
4011
4012 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4013 if (!vsi->q_vectors)
4014 return;
4015
63741846
SN		 4016 if (!vsi->irqs_ready)
4017 return;
4018
4019 vsi->irqs_ready = false;
41c445ff
JB		 4020 for (i = 0; i < vsi->num_q_vectors; i++) {
4021 u16 vector = i + base;
4022
4023 /* free only the irqs that were actually requested */
78681b1f
SN		 4024 if (!vsi->q_vectors[i] ||
4025 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 4026 continue;
4027
4028 /* clear the affinity_mask in the IRQ descriptor */
4029 irq_set_affinity_hint(pf->msix_entries[vector].vector,
4030 NULL);
b33d3b73 4031 synchronize_irq(pf->msix_entries[vector].vector);
41c445ff 4032 free_irq(pf->msix_entries[vector].vector,
493fb300 4033 vsi->q_vectors[i]);
41c445ff
JB		 4034
4035 /* Tear down the interrupt queue link list
4036 *
4037 * We know that they come in pairs and always
4038 * the Rx first, then the Tx. To clear the
4039 * link list, stick the EOL value into the
4040 * next_q field of the registers.
4041 */
4042 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
4043 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4044 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4045 val |= I40E_QUEUE_END_OF_LIST
4046 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4047 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4048
4049 while (qp != I40E_QUEUE_END_OF_LIST) {
4050 u32 next;
4051
4052 val = rd32(hw, I40E_QINT_RQCTL(qp));
4053
4054 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4055 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4056 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4057 I40E_QINT_RQCTL_INTEVENT_MASK);
4058
4059 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4060 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4061
4062 wr32(hw, I40E_QINT_RQCTL(qp), val);
4063
4064 val = rd32(hw, I40E_QINT_TQCTL(qp));
4065
4066 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4067 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4068
4069 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4070 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4071 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4072 I40E_QINT_TQCTL_INTEVENT_MASK);
4073
4074 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4075 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4076
4077 wr32(hw, I40E_QINT_TQCTL(qp), val);
4078 qp = next;
4079 }
4080 }
4081 } else {
4082 free_irq(pf->pdev->irq, pf);
4083
4084 val = rd32(hw, I40E_PFINT_LNKLST0);
4085 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4086 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4087 val |= I40E_QUEUE_END_OF_LIST
4088 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4089 wr32(hw, I40E_PFINT_LNKLST0, val);
4090
4091 val = rd32(hw, I40E_QINT_RQCTL(qp));
4092 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4093 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4094 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4095 I40E_QINT_RQCTL_INTEVENT_MASK);
4096
4097 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4098 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4099
4100 wr32(hw, I40E_QINT_RQCTL(qp), val);
4101
4102 val = rd32(hw, I40E_QINT_TQCTL(qp));
4103
4104 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4105 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4106 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4107 I40E_QINT_TQCTL_INTEVENT_MASK);
4108
4109 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4110 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4111
4112 wr32(hw, I40E_QINT_TQCTL(qp), val);
4113 }
4114}
4115
493fb300
AD		 4116/**
4117 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4118 * @vsi: the VSI being configured
4119 * @v_idx: Index of vector to be freed
4120 *
4121 * This function frees the memory allocated to the q_vector. In addition if
4122 * NAPI is enabled it will delete any references to the NAPI struct prior
4123 * to freeing the q_vector.
4124 **/
4125static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4126{
4127 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4128 struct i40e_ring *ring;
493fb300
AD		 4129
4130 if (!q_vector)
4131 return;
4132
4133 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4134 i40e_for_each_ring(ring, q_vector->tx)
4135 ring->q_vector = NULL;
4136
4137 i40e_for_each_ring(ring, q_vector->rx)
4138 ring->q_vector = NULL;
493fb300
AD		 4139
4140 /* only VSI w/ an associated netdev is set up w/ NAPI */
4141 if (vsi->netdev)
4142 netif_napi_del(&q_vector->napi);
4143
4144 vsi->q_vectors[v_idx] = NULL;
4145
4146 kfree_rcu(q_vector, rcu);
4147}
4148
41c445ff
JB		 4149/**
4150 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4151 * @vsi: the VSI being un-configured
4152 *
4153 * This frees the memory allocated to the q_vectors and
4154 * deletes references to the NAPI struct.
4155 **/
4156static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4157{
4158 int v_idx;
4159
493fb300
AD		 4160 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4161 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4162}
4163
4164/**
4165 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4166 * @pf: board private structure
4167 **/
4168static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4169{
4170 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4171 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4172 pci_disable_msix(pf->pdev);
4173 kfree(pf->msix_entries);
4174 pf->msix_entries = NULL;
3b444399
SN		 4175 kfree(pf->irq_pile);
4176 pf->irq_pile = NULL;
41c445ff
JB		 4177 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4178 pci_disable_msi(pf->pdev);
4179 }
4180 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4181}
4182
4183/**
4184 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4185 * @pf: board private structure
4186 *
4187 * We go through and clear interrupt specific resources and reset the structure
4188 * to pre-load conditions
4189 **/
4190static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4191{
4192 int i;
4193
e147758d 4194 i40e_stop_misc_vector(pf);
69278398 4195 if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) {
e147758d
SN		 4196 synchronize_irq(pf->msix_entries[0].vector);
4197 free_irq(pf->msix_entries[0].vector, pf);
4198 }
4199
e3219ce6
ASJ		 4200 i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector,
4201 I40E_IWARP_IRQ_PILE_ID);
4202
41c445ff 4203 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4204 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4205 if (pf->vsi[i])
4206 i40e_vsi_free_q_vectors(pf->vsi[i]);
4207 i40e_reset_interrupt_capability(pf);
4208}
4209
4210/**
4211 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4212 * @vsi: the VSI being configured
4213 **/
4214static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4215{
4216 int q_idx;
4217
4218 if (!vsi->netdev)
4219 return;
4220
4221 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4222 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4223}
4224
4225/**
4226 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4227 * @vsi: the VSI being configured
4228 **/
4229static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4230{
4231 int q_idx;
4232
4233 if (!vsi->netdev)
4234 return;
4235
4236 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4237 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4238}
4239
90ef8d47
SN		 4240/**
4241 * i40e_vsi_close - Shut down a VSI
4242 * @vsi: the vsi to be quelled
4243 **/
4244static void i40e_vsi_close(struct i40e_vsi *vsi)
4245{
e3219ce6
ASJ		 4246 bool reset = false;
4247
90ef8d47
SN		 4248 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4249 i40e_down(vsi);
4250 i40e_vsi_free_irq(vsi);
4251 i40e_vsi_free_tx_resources(vsi);
4252 i40e_vsi_free_rx_resources(vsi);
92faef85 4253 vsi->current_netdev_flags = 0;
e3219ce6
ASJ		 4254 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4255 reset = true;
4256 i40e_notify_client_of_netdev_close(vsi, reset);
90ef8d47
SN		 4257}
4258
41c445ff
JB		 4259/**
4260 * i40e_quiesce_vsi - Pause a given VSI
4261 * @vsi: the VSI being paused
4262 **/
4263static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4264{
4265 if (test_bit(__I40E_DOWN, &vsi->state))
4266 return;
4267
d341b7a5
NP		 4268 /* No need to disable FCoE VSI when Tx suspended */
4269 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4270 vsi->type == I40E_VSI_FCOE) {
4271 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4272 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4273 return;
4274 }
4275
41c445ff 4276 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4277 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4278 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4279 else
90ef8d47 4280 i40e_vsi_close(vsi);
41c445ff
JB		 4281}
4282
4283/**
4284 * i40e_unquiesce_vsi - Resume a given VSI
4285 * @vsi: the VSI being resumed
4286 **/
4287static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4288{
4289 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4290 return;
4291
4292 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4293 if (vsi->netdev && netif_running(vsi->netdev))
4294 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4295 else
8276f757 4296 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4297}
4298
4299/**
4300 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4301 * @pf: the PF
4302 **/
4303static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4304{
4305 int v;
4306
505682cd 4307 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4308 if (pf->vsi[v])
4309 i40e_quiesce_vsi(pf->vsi[v]);
4310 }
4311}
4312
4313/**
4314 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4315 * @pf: the PF
4316 **/
4317static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4318{
4319 int v;
4320
505682cd 4321 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4322 if (pf->vsi[v])
4323 i40e_unquiesce_vsi(pf->vsi[v]);
4324 }
4325}
4326
69129dc3
NP		 4327#ifdef CONFIG_I40E_DCB
4328/**
3fe06f41 4329 * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled
69129dc3
NP		 4330 * @vsi: the VSI being configured
4331 *
3fe06f41 4332 * This function waits for the given VSI's queues to be disabled.
69129dc3 4333 **/
3fe06f41 4334static int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi)
69129dc3
NP		 4335{
4336 struct i40e_pf *pf = vsi->back;
4337 int i, pf_q, ret;
4338
4339 pf_q = vsi->base_queue;
4340 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4341 /* Check and wait for the disable status of the queue */
4342 ret = i40e_pf_txq_wait(pf, pf_q, false);
4343 if (ret) {
4344 dev_info(&pf->pdev->dev,
fb43201f
SN		 4345 "VSI seid %d Tx ring %d disable timeout\n",
4346 vsi->seid, pf_q);
69129dc3
NP		 4347 return ret;
4348 }
4349 }
4350
3fe06f41
NP		 4351 pf_q = vsi->base_queue;
4352 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4353 /* Check and wait for the disable status of the queue */
4354 ret = i40e_pf_rxq_wait(pf, pf_q, false);
4355 if (ret) {
4356 dev_info(&pf->pdev->dev,
4357 "VSI seid %d Rx ring %d disable timeout\n",
4358 vsi->seid, pf_q);
4359 return ret;
4360 }
4361 }
4362
69129dc3
NP		 4363 return 0;
4364}
4365
4366/**
3fe06f41 4367 * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled
69129dc3
NP		 4368 * @pf: the PF
4369 *
3fe06f41 4370 * This function waits for the queues to be in disabled state for all the
69129dc3
NP		 4371 * VSIs that are managed by this PF.
4372 **/
3fe06f41 4373static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf)
69129dc3
NP		 4374{
4375 int v, ret = 0;
4376
4377 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4378 /* No need to wait for FCoE VSI queues */
4379 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
3fe06f41 4380 ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]);
69129dc3
NP		 4381 if (ret)
4382 break;
4383 }
4384 }
4385
4386 return ret;
4387}
4388
4389#endif
b03a8c1f
KP		 4390
4391/**
4392 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4393 * @q_idx: TX queue number
4394 * @vsi: Pointer to VSI struct
4395 *
4396 * This function checks specified queue for given VSI. Detects hung condition.
4397 * Sets hung bit since it is two step process. Before next run of service task
4398 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4399 * hung condition remain unchanged and during subsequent run, this function
4400 * issues SW interrupt to recover from hung condition.
4401 **/
4402static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4403{
4404 struct i40e_ring *tx_ring = NULL;
4405 struct i40e_pf *pf;
dd353109 4406 u32 head, val, tx_pending_hw;
b03a8c1f
KP		 4407 int i;
4408
4409 pf = vsi->back;
4410
4411 /* now that we have an index, find the tx_ring struct */
4412 for (i = 0; i < vsi->num_queue_pairs; i++) {
4413 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4414 if (q_idx == vsi->tx_rings[i]->queue_index) {
4415 tx_ring = vsi->tx_rings[i];
4416 break;
4417 }
4418 }
4419 }
4420
4421 if (!tx_ring)
4422 return;
4423
4424 /* Read interrupt register */
4425 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4426 val = rd32(&pf->hw,
4427 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4428 tx_ring->vsi->base_vector - 1));
4429 else
4430 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4431
4432 head = i40e_get_head(tx_ring);
4433
dd353109 4434 tx_pending_hw = i40e_get_tx_pending(tx_ring, false);
b03a8c1f 4435
9c6c1259
KP		 4436 /* HW is done executing descriptors, updated HEAD write back,
4437 * but SW hasn't processed those descriptors. If interrupt is
4438 * not generated from this point ON, it could result into
4439 * dev_watchdog detecting timeout on those netdev_queue,
4440 * hence proactively trigger SW interrupt.
b03a8c1f 4441 */
dd353109 4442 if (tx_pending_hw && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
9c6c1259
KP		 4443 /* NAPI Poll didn't run and clear since it was set */
4444 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4445 &tx_ring->q_vector->hung_detected)) {
dd353109
ASJ		 4446 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending_hw: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4447 vsi->seid, q_idx, tx_pending_hw,
9c6c1259
KP		 4448 tx_ring->next_to_clean, head,
4449 tx_ring->next_to_use,
4450 readl(tx_ring->tail));
4451 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4452 vsi->seid, q_idx, val);
4453 i40e_force_wb(vsi, tx_ring->q_vector);
4454 } else {
4455 /* First Chance - detected possible hung */
4456 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4457 &tx_ring->q_vector->hung_detected);
4458 }
4459 }
dd353109
ASJ		 4460
4461 /* This is the case where we have interrupts missing,
4462 * so the tx_pending in HW will most likely be 0, but we
4463 * will have tx_pending in SW since the WB happened but the
4464 * interrupt got lost.
4465 */
4466 if ((!tx_pending_hw) && i40e_get_tx_pending(tx_ring, true) &&
4467 (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
4468 if (napi_reschedule(&tx_ring->q_vector->napi))
4469 tx_ring->tx_stats.tx_lost_interrupt++;
4470 }
b03a8c1f
KP		 4471}
4472
4473/**
4474 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4475 * @pf: pointer to PF struct
4476 *
4477 * LAN VSI has netdev and netdev has TX queues. This function is to check
4478 * each of those TX queues if they are hung, trigger recovery by issuing
4479 * SW interrupt.
4480 **/
4481static void i40e_detect_recover_hung(struct i40e_pf *pf)
4482{
4483 struct net_device *netdev;
4484 struct i40e_vsi *vsi;
4485 int i;
4486
4487 /* Only for LAN VSI */
4488 vsi = pf->vsi[pf->lan_vsi];
4489
4490 if (!vsi)
4491 return;
4492
4493 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4494 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4495 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4496 return;
4497
4498 /* Make sure type is MAIN VSI */
4499 if (vsi->type != I40E_VSI_MAIN)
4500 return;
4501
4502 netdev = vsi->netdev;
4503 if (!netdev)
4504 return;
4505
4506 /* Bail out if netif_carrier is not OK */
4507 if (!netif_carrier_ok(netdev))
4508 return;
4509
4510 /* Go thru' TX queues for netdev */
4511 for (i = 0; i < netdev->num_tx_queues; i++) {
4512 struct netdev_queue *q;
4513
4514 q = netdev_get_tx_queue(netdev, i);
4515 if (q)
4516 i40e_detect_recover_hung_queue(i, vsi);
4517 }
4518}
4519
63d7e5a4
NP		 4520/**
4521 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4522 * @pf: pointer to PF
63d7e5a4
NP		 4523 *
4524 * Get TC map for ISCSI PF type that will include iSCSI TC
4525 * and LAN TC.
4526 **/
4527static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4528{
4529 struct i40e_dcb_app_priority_table app;
4530 struct i40e_hw *hw = &pf->hw;
4531 u8 enabled_tc = 1; /* TC0 is always enabled */
4532 u8 tc, i;
4533 /* Get the iSCSI APP TLV */
4534 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4535
4536 for (i = 0; i < dcbcfg->numapps; i++) {
4537 app = dcbcfg->app[i];
4538 if (app.selector == I40E_APP_SEL_TCPIP &&
4539 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4540 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4541 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4542 break;
4543 }
4544 }
4545
4546 return enabled_tc;
4547}
4548
41c445ff
JB		 4549/**
4550 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4551 * @dcbcfg: the corresponding DCBx configuration structure
4552 *
4553 * Return the number of TCs from given DCBx configuration
4554 **/
4555static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4556{
078b5876
JB		 4557 u8 num_tc = 0;
4558 int i;
41c445ff
JB		 4559
4560 /* Scan the ETS Config Priority Table to find
4561 * traffic class enabled for a given priority
4562 * and use the traffic class index to get the
4563 * number of traffic classes enabled
4564 */
4565 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4566 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4567 num_tc = dcbcfg->etscfg.prioritytable[i];
4568 }
4569
4570 /* Traffic class index starts from zero so
4571 * increment to return the actual count
4572 */
078b5876 4573 return num_tc + 1;
41c445ff
JB		 4574}
4575
4576/**
4577 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4578 * @dcbcfg: the corresponding DCBx configuration structure
4579 *
4580 * Query the current DCB configuration and return the number of
4581 * traffic classes enabled from the given DCBX config
4582 **/
4583static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4584{
4585 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4586 u8 enabled_tc = 1;
4587 u8 i;
4588
4589 for (i = 0; i < num_tc; i++)
41a1d04b 4590 enabled_tc |= BIT(i);
41c445ff
JB		 4591
4592 return enabled_tc;
4593}
4594
4595/**
4596 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4597 * @pf: PF being queried
4598 *
4599 * Return number of traffic classes enabled for the given PF
4600 **/
4601static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4602{
4603 struct i40e_hw *hw = &pf->hw;
4604 u8 i, enabled_tc;
4605 u8 num_tc = 0;
4606 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4607
4608 /* If DCB is not enabled then always in single TC */
4609 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4610 return 1;
4611
63d7e5a4
NP		 4612 /* SFP mode will be enabled for all TCs on port */
4613 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4614 return i40e_dcb_get_num_tc(dcbcfg);
4615
41c445ff 4616 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4617 if (pf->hw.func_caps.iscsi)
4618 enabled_tc = i40e_get_iscsi_tc_map(pf);
4619 else
fc51de96 4620 return 1; /* Only TC0 */
41c445ff 4621
63d7e5a4
NP		 4622 /* At least have TC0 */
4623 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4624 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4625 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4626 num_tc++;
4627 }
4628 return num_tc;
41c445ff
JB		 4629}
4630
4631/**
4632 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4633 * @pf: PF being queried
4634 *
4635 * Return a bitmap for first enabled traffic class for this PF.
4636 **/
4637static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4638{
4639 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4640 u8 i = 0;
4641
4642 if (!enabled_tc)
4643 return 0x1; /* TC0 */
4644
4645 /* Find the first enabled TC */
4646 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4647 if (enabled_tc & BIT(i))
41c445ff
JB		 4648 break;
4649 }
4650
41a1d04b 4651 return BIT(i);
41c445ff
JB		 4652}
4653
4654/**
4655 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4656 * @pf: PF being queried
4657 *
4658 * Return a bitmap for enabled traffic classes for this PF.
4659 **/
4660static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4661{
4662 /* If DCB is not enabled for this PF then just return default TC */
4663 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4664 return i40e_pf_get_default_tc(pf);
4665
41c445ff 4666 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4667 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4668 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4669
fc51de96 4670 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4671 if (pf->hw.func_caps.iscsi)
4672 return i40e_get_iscsi_tc_map(pf);
4673 else
fc51de96 4674 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4675}
4676
4677/**
4678 * i40e_vsi_get_bw_info - Query VSI BW Information
4679 * @vsi: the VSI being queried
4680 *
4681 * Returns 0 on success, negative value on failure
4682 **/
4683static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4684{
4685 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4686 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4687 struct i40e_pf *pf = vsi->back;
4688 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4689 i40e_status ret;
41c445ff 4690 u32 tc_bw_max;
41c445ff
JB		 4691 int i;
4692
4693 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4694 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4695 if (ret) {
41c445ff 4696 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4697 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4698 i40e_stat_str(&pf->hw, ret),
4699 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4700 return -EINVAL;
41c445ff
JB		 4701 }
4702
4703 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4704 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4705 NULL);
4706 if (ret) {
41c445ff 4707 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4708 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4709 i40e_stat_str(&pf->hw, ret),
4710 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4711 return -EINVAL;
41c445ff
JB		 4712 }
4713
4714 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4715 dev_info(&pf->pdev->dev,
4716 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4717 bw_config.tc_valid_bits,
4718 bw_ets_config.tc_valid_bits);
4719 /* Still continuing */
4720 }
4721
4722 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4723 vsi->bw_max_quanta = bw_config.max_bw;
4724 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4725 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4726 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4727 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4728 vsi->bw_ets_limit_credits[i] =
4729 le16_to_cpu(bw_ets_config.credits[i]);
4730 /* 3 bits out of 4 for each TC */
4731 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4732 }
078b5876 4733
dcae29be 4734 return 0;
41c445ff
JB		 4735}
4736
4737/**
4738 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4739 * @vsi: the VSI being configured
4740 * @enabled_tc: TC bitmap
4741 * @bw_credits: BW shared credits per TC
4742 *
4743 * Returns 0 on success, negative value on failure
4744 **/
dcae29be 4745static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4746 u8 *bw_share)
4747{
4748 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4749 i40e_status ret;
dcae29be 4750 int i;
41c445ff
JB		 4751
4752 bw_data.tc_valid_bits = enabled_tc;
4753 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4754 bw_data.tc_bw_credits[i] = bw_share[i];
4755
f1c7e72e
SN		 4756 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4757 NULL);
4758 if (ret) {
41c445ff 4759 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4760 "AQ command Config VSI BW allocation per TC failed = %d\n",
4761 vsi->back->hw.aq.asq_last_status);
dcae29be 4762 return -EINVAL;
41c445ff
JB		 4763 }
4764
4765 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4766 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4767
dcae29be 4768 return 0;
41c445ff
JB		 4769}
4770
4771/**
4772 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4773 * @vsi: the VSI being configured
4774 * @enabled_tc: TC map to be enabled
4775 *
4776 **/
4777static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4778{
4779 struct net_device *netdev = vsi->netdev;
4780 struct i40e_pf *pf = vsi->back;
4781 struct i40e_hw *hw = &pf->hw;
4782 u8 netdev_tc = 0;
4783 int i;
4784 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4785
4786 if (!netdev)
4787 return;
4788
4789 if (!enabled_tc) {
4790 netdev_reset_tc(netdev);
4791 return;
4792 }
4793
4794 /* Set up actual enabled TCs on the VSI */
4795 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4796 return;
4797
4798 /* set per TC queues for the VSI */
4799 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4800 /* Only set TC queues for enabled tcs
4801 *
4802 * e.g. For a VSI that has TC0 and TC3 enabled the
4803 * enabled_tc bitmap would be 0x00001001; the driver
4804 * will set the numtc for netdev as 2 that will be
4805 * referenced by the netdev layer as TC 0 and 1.
4806 */
75f5cea9 4807 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4808 netdev_set_tc_queue(netdev,
4809 vsi->tc_config.tc_info[i].netdev_tc,
4810 vsi->tc_config.tc_info[i].qcount,
4811 vsi->tc_config.tc_info[i].qoffset);
4812 }
4813
4814 /* Assign UP2TC map for the VSI */
4815 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4816 /* Get the actual TC# for the UP */
4817 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4818 /* Get the mapped netdev TC# for the UP */
4819 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4820 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4821 }
4822}
4823
4824/**
4825 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4826 * @vsi: the VSI being configured
4827 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4828 **/
4829static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4830 struct i40e_vsi_context *ctxt)
4831{
4832 /* copy just the sections touched not the entire info
4833 * since not all sections are valid as returned by
4834 * update vsi params
4835 */
4836 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4837 memcpy(&vsi->info.queue_mapping,
4838 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4839 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4840 sizeof(vsi->info.tc_mapping));
4841}
4842
4843/**
4844 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4845 * @vsi: VSI to be configured
4846 * @enabled_tc: TC bitmap
4847 *
4848 * This configures a particular VSI for TCs that are mapped to the
4849 * given TC bitmap. It uses default bandwidth share for TCs across
4850 * VSIs to configure TC for a particular VSI.
4851 *
4852 * NOTE:
4853 * It is expected that the VSI queues have been quisced before calling
4854 * this function.
4855 **/
4856static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4857{
4858 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4859 struct i40e_vsi_context ctxt;
4860 int ret = 0;
4861 int i;
4862
4863 /* Check if enabled_tc is same as existing or new TCs */
4864 if (vsi->tc_config.enabled_tc == enabled_tc)
4865 return ret;
4866
4867 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4868 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4869 if (enabled_tc & BIT(i))
41c445ff
JB		 4870 bw_share[i] = 1;
4871 }
4872
4873 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4874 if (ret) {
4875 dev_info(&vsi->back->pdev->dev,
4876 "Failed configuring TC map %d for VSI %d\n",
4877 enabled_tc, vsi->seid);
4878 goto out;
4879 }
4880
4881 /* Update Queue Pairs Mapping for currently enabled UPs */
4882 ctxt.seid = vsi->seid;
4883 ctxt.pf_num = vsi->back->hw.pf_id;
4884 ctxt.vf_num = 0;
4885 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4886 ctxt.info = vsi->info;
41c445ff
JB		 4887 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4888
e3219ce6
ASJ		 4889 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
4890 ctxt.info.valid_sections |=
4891 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
4892 ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
4893 }
4894
41c445ff
JB		 4895 /* Update the VSI after updating the VSI queue-mapping information */
4896 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4897 if (ret) {
4898 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4899 "Update vsi tc config failed, err %s aq_err %s\n",
4900 i40e_stat_str(&vsi->back->hw, ret),
4901 i40e_aq_str(&vsi->back->hw,
4902 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4903 goto out;
4904 }
4905 /* update the local VSI info with updated queue map */
4906 i40e_vsi_update_queue_map(vsi, &ctxt);
4907 vsi->info.valid_sections = 0;
4908
4909 /* Update current VSI BW information */
4910 ret = i40e_vsi_get_bw_info(vsi);
4911 if (ret) {
4912 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4913 "Failed updating vsi bw info, err %s aq_err %s\n",
4914 i40e_stat_str(&vsi->back->hw, ret),
4915 i40e_aq_str(&vsi->back->hw,
4916 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4917 goto out;
4918 }
4919
4920 /* Update the netdev TC setup */
4921 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4922out:
4923 return ret;
4924}
4925
4e3b35b0
NP		 4926/**
4927 * i40e_veb_config_tc - Configure TCs for given VEB
4928 * @veb: given VEB
4929 * @enabled_tc: TC bitmap
4930 *
4931 * Configures given TC bitmap for VEB (switching) element
4932 **/
4933int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4934{
4935 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4936 struct i40e_pf *pf = veb->pf;
4937 int ret = 0;
4938 int i;
4939
4940 /* No TCs or already enabled TCs just return */
4941 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4942 return ret;
4943
4944 bw_data.tc_valid_bits = enabled_tc;
4945 /* bw_data.absolute_credits is not set (relative) */
4946
4947 /* Enable ETS TCs with equal BW Share for now */
4948 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4949 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4950 bw_data.tc_bw_share_credits[i] = 1;
4951 }
4952
4953 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4954 &bw_data, NULL);
4955 if (ret) {
4956 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4957 "VEB bw config failed, err %s aq_err %s\n",
4958 i40e_stat_str(&pf->hw, ret),
4959 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4960 goto out;
4961 }
4962
4963 /* Update the BW information */
4964 ret = i40e_veb_get_bw_info(veb);
4965 if (ret) {
4966 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4967 "Failed getting veb bw config, err %s aq_err %s\n",
4968 i40e_stat_str(&pf->hw, ret),
4969 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4970 }
4971
4972out:
4973 return ret;
4974}
4975
4976#ifdef CONFIG_I40E_DCB
4977/**
4978 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4979 * @pf: PF struct
4980 *
4981 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4982 * the caller would've quiesce all the VSIs before calling
4983 * this function
4984 **/
4985static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4986{
4987 u8 tc_map = 0;
4988 int ret;
4989 u8 v;
4990
4991 /* Enable the TCs available on PF to all VEBs */
4992 tc_map = i40e_pf_get_tc_map(pf);
4993 for (v = 0; v < I40E_MAX_VEB; v++) {
4994 if (!pf->veb[v])
4995 continue;
4996 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4997 if (ret) {
4998 dev_info(&pf->pdev->dev,
4999 "Failed configuring TC for VEB seid=%d\n",
5000 pf->veb[v]->seid);
5001 /* Will try to configure as many components */
5002 }
5003 }
5004
5005 /* Update each VSI */
505682cd 5006 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 5007 if (!pf->vsi[v])
5008 continue;
5009
5010 /* - Enable all TCs for the LAN VSI
38e00438
VD		 5011#ifdef I40E_FCOE
5012 * - For FCoE VSI only enable the TC configured
5013 * as per the APP TLV
5014#endif
4e3b35b0
NP		 5015 * - For all others keep them at TC0 for now
5016 */
5017 if (v == pf->lan_vsi)
5018 tc_map = i40e_pf_get_tc_map(pf);
5019 else
5020 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 5021#ifdef I40E_FCOE
5022 if (pf->vsi[v]->type == I40E_VSI_FCOE)
5023 tc_map = i40e_get_fcoe_tc_map(pf);
5024#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 5025
5026 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
5027 if (ret) {
5028 dev_info(&pf->pdev->dev,
5029 "Failed configuring TC for VSI seid=%d\n",
5030 pf->vsi[v]->seid);
5031 /* Will try to configure as many components */
5032 } else {
0672a091
NP		 5033 /* Re-configure VSI vectors based on updated TC map */
5034 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 5035 if (pf->vsi[v]->netdev)
5036 i40e_dcbnl_set_all(pf->vsi[v]);
5037 }
5038 }
5039}
5040
2fd75f31
NP		 5041/**
5042 * i40e_resume_port_tx - Resume port Tx
5043 * @pf: PF struct
5044 *
5045 * Resume a port's Tx and issue a PF reset in case of failure to
5046 * resume.
5047 **/
5048static int i40e_resume_port_tx(struct i40e_pf *pf)
5049{
5050 struct i40e_hw *hw = &pf->hw;
5051 int ret;
5052
5053 ret = i40e_aq_resume_port_tx(hw, NULL);
5054 if (ret) {
5055 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5056 "Resume Port Tx failed, err %s aq_err %s\n",
5057 i40e_stat_str(&pf->hw, ret),
5058 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 5059 /* Schedule PF reset to recover */
5060 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5061 i40e_service_event_schedule(pf);
5062 }
5063
5064 return ret;
5065}
5066
4e3b35b0
NP		 5067/**
5068 * i40e_init_pf_dcb - Initialize DCB configuration
5069 * @pf: PF being configured
5070 *
5071 * Query the current DCB configuration and cache it
5072 * in the hardware structure
5073 **/
5074static int i40e_init_pf_dcb(struct i40e_pf *pf)
5075{
5076 struct i40e_hw *hw = &pf->hw;
5077 int err = 0;
5078
025b4a54 5079 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
f1bbad33 5080 if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT)
025b4a54
ASJ		 5081 goto out;
5082
4e3b35b0
NP		 5083 /* Get the initial DCB configuration */
5084 err = i40e_init_dcb(hw);
5085 if (!err) {
5086 /* Device/Function is not DCBX capable */
5087 if ((!hw->func_caps.dcb) ||
5088 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5089 dev_info(&pf->pdev->dev,
5090 "DCBX offload is not supported or is disabled for this PF.\n");
5091
5092 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5093 goto out;
5094
5095 } else {
5096 /* When status is not DISABLED then DCBX in FW */
5097 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5098 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5099
5100 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5101 /* Enable DCB tagging only when more than one TC */
5102 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5103 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5104 dev_dbg(&pf->pdev->dev,
5105 "DCBX offload is supported for this PF.\n");
4e3b35b0 5106 }
014269ff 5107 } else {
aebfc816 5108 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5109 "Query for DCB configuration failed, err %s aq_err %s\n",
5110 i40e_stat_str(&pf->hw, err),
5111 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5112 }
5113
5114out:
5115 return err;
5116}
5117#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5118#define SPEED_SIZE 14
5119#define FC_SIZE 8
5120/**
5121 * i40e_print_link_message - print link up or down
5122 * @vsi: the VSI for which link needs a message
5123 */
c156f856 5124void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5125{
a9165490
SN		 5126 char *speed = "Unknown";
5127 char *fc = "Unknown";
cf05ed08 5128
c156f856
MJ		 5129 if (vsi->current_isup == isup)
5130 return;
5131 vsi->current_isup = isup;
cf05ed08
JB		 5132 if (!isup) {
5133 netdev_info(vsi->netdev, "NIC Link is Down\n");
5134 return;
5135 }
5136
148c2d80
GR		 5137 /* Warn user if link speed on NPAR enabled partition is not at
5138 * least 10GB
5139 */
5140 if (vsi->back->hw.func_caps.npar_enable &&
5141 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5142 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5143 netdev_warn(vsi->netdev,
5144 "The partition detected link speed that is less than 10Gbps\n");
5145
cf05ed08
JB		 5146 switch (vsi->back->hw.phy.link_info.link_speed) {
5147 case I40E_LINK_SPEED_40GB:
a9165490 5148 speed = "40 G";
cf05ed08 5149 break;
ae24b409 5150 case I40E_LINK_SPEED_20GB:
a9165490 5151 speed = "20 G";
ae24b409 5152 break;
cf05ed08 5153 case I40E_LINK_SPEED_10GB:
a9165490 5154 speed = "10 G";
cf05ed08
JB		 5155 break;
5156 case I40E_LINK_SPEED_1GB:
a9165490 5157 speed = "1000 M";
cf05ed08 5158 break;
5960d33f 5159 case I40E_LINK_SPEED_100MB:
a9165490 5160 speed = "100 M";
5960d33f 5161 break;
cf05ed08
JB		 5162 default:
5163 break;
5164 }
5165
5166 switch (vsi->back->hw.fc.current_mode) {
5167 case I40E_FC_FULL:
a9165490 5168 fc = "RX/TX";
cf05ed08
JB		 5169 break;
5170 case I40E_FC_TX_PAUSE:
a9165490 5171 fc = "TX";
cf05ed08
JB		 5172 break;
5173 case I40E_FC_RX_PAUSE:
a9165490 5174 fc = "RX";
cf05ed08
JB		 5175 break;
5176 default:
a9165490 5177 fc = "None";
cf05ed08
JB		 5178 break;
5179 }
5180
a9165490 5181 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5182 speed, fc);
5183}
4e3b35b0 5184
41c445ff
JB		 5185/**
5186 * i40e_up_complete - Finish the last steps of bringing up a connection
5187 * @vsi: the VSI being configured
5188 **/
5189static int i40e_up_complete(struct i40e_vsi *vsi)
5190{
5191 struct i40e_pf *pf = vsi->back;
5192 int err;
5193
5194 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5195 i40e_vsi_configure_msix(vsi);
5196 else
5197 i40e_configure_msi_and_legacy(vsi);
5198
5199 /* start rings */
5200 err = i40e_vsi_control_rings(vsi, true);
5201 if (err)
5202 return err;
5203
5204 clear_bit(__I40E_DOWN, &vsi->state);
5205 i40e_napi_enable_all(vsi);
5206 i40e_vsi_enable_irq(vsi);
5207
5208 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5209 (vsi->netdev)) {
cf05ed08 5210 i40e_print_link_message(vsi, true);
41c445ff
JB		 5211 netif_tx_start_all_queues(vsi->netdev);
5212 netif_carrier_on(vsi->netdev);
6d779b41 5213 } else if (vsi->netdev) {
cf05ed08 5214 i40e_print_link_message(vsi, false);
7b592f61
CW		 5215 /* need to check for qualified module here*/
5216 if ((pf->hw.phy.link_info.link_info &
5217 I40E_AQ_MEDIA_AVAILABLE) &&
5218 (!(pf->hw.phy.link_info.an_info &
5219 I40E_AQ_QUALIFIED_MODULE)))
5220 netdev_err(vsi->netdev,
5221 "the driver failed to link because an unqualified module was detected.");
41c445ff 5222 }
ca64fa4e
ASJ		 5223
5224 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5225 if (vsi->type == I40E_VSI_FDIR) {
5226 /* reset fd counters */
5227 pf->fd_add_err = pf->fd_atr_cnt = 0;
5228 if (pf->fd_tcp_rule > 0) {
5229 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5230 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5231 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5232 pf->fd_tcp_rule = 0;
5233 }
ca64fa4e 5234 i40e_fdir_filter_restore(vsi);
1e1be8f6 5235 }
e3219ce6
ASJ		 5236
5237 /* On the next run of the service_task, notify any clients of the new
5238 * opened netdev
5239 */
5240 pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED;
41c445ff
JB		 5241 i40e_service_event_schedule(pf);
5242
5243 return 0;
5244}
5245
5246/**
5247 * i40e_vsi_reinit_locked - Reset the VSI
5248 * @vsi: the VSI being configured
5249 *
5250 * Rebuild the ring structs after some configuration
5251 * has changed, e.g. MTU size.
5252 **/
5253static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5254{
5255 struct i40e_pf *pf = vsi->back;
5256
5257 WARN_ON(in_interrupt());
5258 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5259 usleep_range(1000, 2000);
5260 i40e_down(vsi);
5261
41c445ff
JB		 5262 i40e_up(vsi);
5263 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5264}
5265
5266/**
5267 * i40e_up - Bring the connection back up after being down
5268 * @vsi: the VSI being configured
5269 **/
5270int i40e_up(struct i40e_vsi *vsi)
5271{
5272 int err;
5273
5274 err = i40e_vsi_configure(vsi);
5275 if (!err)
5276 err = i40e_up_complete(vsi);
5277
5278 return err;
5279}
5280
5281/**
5282 * i40e_down - Shutdown the connection processing
5283 * @vsi: the VSI being stopped
5284 **/
5285void i40e_down(struct i40e_vsi *vsi)
5286{
5287 int i;
5288
5289 /* It is assumed that the caller of this function
5290 * sets the vsi->state __I40E_DOWN bit.
5291 */
5292 if (vsi->netdev) {
5293 netif_carrier_off(vsi->netdev);
5294 netif_tx_disable(vsi->netdev);
5295 }
5296 i40e_vsi_disable_irq(vsi);
5297 i40e_vsi_control_rings(vsi, false);
5298 i40e_napi_disable_all(vsi);
5299
5300 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5301 i40e_clean_tx_ring(vsi->tx_rings[i]);
5302 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff 5303 }
f980d445
CS		 5304
5305 i40e_notify_client_of_netdev_close(vsi, false);
5306
41c445ff
JB		 5307}
5308
5309/**
5310 * i40e_setup_tc - configure multiple traffic classes
5311 * @netdev: net device to configure
5312 * @tc: number of traffic classes to enable
5313 **/
5314static int i40e_setup_tc(struct net_device *netdev, u8 tc)
5315{
5316 struct i40e_netdev_priv *np = netdev_priv(netdev);
5317 struct i40e_vsi *vsi = np->vsi;
5318 struct i40e_pf *pf = vsi->back;
5319 u8 enabled_tc = 0;
5320 int ret = -EINVAL;
5321 int i;
5322
5323 /* Check if DCB enabled to continue */
5324 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5325 netdev_info(netdev, "DCB is not enabled for adapter\n");
5326 goto exit;
5327 }
5328
5329 /* Check if MFP enabled */
5330 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5331 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5332 goto exit;
5333 }
5334
5335 /* Check whether tc count is within enabled limit */
5336 if (tc > i40e_pf_get_num_tc(pf)) {
5337 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5338 goto exit;
5339 }
5340
5341 /* Generate TC map for number of tc requested */
5342 for (i = 0; i < tc; i++)
75f5cea9 5343 enabled_tc |= BIT(i);
41c445ff
JB		 5344
5345 /* Requesting same TC configuration as already enabled */
5346 if (enabled_tc == vsi->tc_config.enabled_tc)
5347 return 0;
5348
5349 /* Quiesce VSI queues */
5350 i40e_quiesce_vsi(vsi);
5351
5352 /* Configure VSI for enabled TCs */
5353 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5354 if (ret) {
5355 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5356 vsi->seid);
5357 goto exit;
5358 }
5359
5360 /* Unquiesce VSI */
5361 i40e_unquiesce_vsi(vsi);
5362
5363exit:
5364 return ret;
5365}
5366
e4c6734e 5367#ifdef I40E_FCOE
16e5cc64
JF		 5368int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5369 struct tc_to_netdev *tc)
e4c6734e 5370#else
16e5cc64
JF		 5371static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5372 struct tc_to_netdev *tc)
e4c6734e
JF		 5373#endif
5374{
16e5cc64 5375 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
e4c6734e 5376 return -EINVAL;
16e5cc64 5377 return i40e_setup_tc(netdev, tc->tc);
e4c6734e
JF		 5378}
5379
41c445ff
JB		 5380/**
5381 * i40e_open - Called when a network interface is made active
5382 * @netdev: network interface device structure
5383 *
5384 * The open entry point is called when a network interface is made
5385 * active by the system (IFF_UP). At this point all resources needed
5386 * for transmit and receive operations are allocated, the interrupt
5387 * handler is registered with the OS, the netdev watchdog subtask is
5388 * enabled, and the stack is notified that the interface is ready.
5389 *
5390 * Returns 0 on success, negative value on failure
5391 **/
38e00438 5392int i40e_open(struct net_device *netdev)
41c445ff
JB		 5393{
5394 struct i40e_netdev_priv *np = netdev_priv(netdev);
5395 struct i40e_vsi *vsi = np->vsi;
5396 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5397 int err;
5398
4eb3f768
SN		 5399 /* disallow open during test or if eeprom is broken */
5400 if (test_bit(__I40E_TESTING, &pf->state) ||
5401 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5402 return -EBUSY;
5403
5404 netif_carrier_off(netdev);
5405
6c167f58
EK		 5406 err = i40e_vsi_open(vsi);
5407 if (err)
5408 return err;
5409
059dab69
JB		 5410 /* configure global TSO hardware offload settings */
5411 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5412 TCP_FLAG_FIN) >> 16);
5413 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5414 TCP_FLAG_FIN |
5415 TCP_FLAG_CWR) >> 16);
5416 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5417
06a5f7f1 5418 udp_tunnel_get_rx_info(netdev);
e3219ce6
ASJ		 5419 i40e_notify_client_of_netdev_open(vsi);
5420
6c167f58
EK		 5421 return 0;
5422}
5423
5424/**
5425 * i40e_vsi_open -
5426 * @vsi: the VSI to open
5427 *
5428 * Finish initialization of the VSI.
5429 *
5430 * Returns 0 on success, negative value on failure
5431 **/
5432int i40e_vsi_open(struct i40e_vsi *vsi)
5433{
5434 struct i40e_pf *pf = vsi->back;
b294ac70 5435 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5436 int err;
5437
41c445ff
JB		 5438 /* allocate descriptors */
5439 err = i40e_vsi_setup_tx_resources(vsi);
5440 if (err)
5441 goto err_setup_tx;
5442 err = i40e_vsi_setup_rx_resources(vsi);
5443 if (err)
5444 goto err_setup_rx;
5445
5446 err = i40e_vsi_configure(vsi);
5447 if (err)
5448 goto err_setup_rx;
5449
c22e3c6c
SN		 5450 if (vsi->netdev) {
5451 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5452 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5453 err = i40e_vsi_request_irq(vsi, int_name);
5454 if (err)
5455 goto err_setup_rx;
41c445ff 5456
c22e3c6c
SN		 5457 /* Notify the stack of the actual queue counts. */
5458 err = netif_set_real_num_tx_queues(vsi->netdev,
5459 vsi->num_queue_pairs);
5460 if (err)
5461 goto err_set_queues;
25946ddb 5462
c22e3c6c
SN		 5463 err = netif_set_real_num_rx_queues(vsi->netdev,
5464 vsi->num_queue_pairs);
5465 if (err)
5466 goto err_set_queues;
8a9eb7d3
SN		 5467
5468 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5469 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5470 dev_driver_string(&pf->pdev->dev),
5471 dev_name(&pf->pdev->dev));
8a9eb7d3 5472 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5473
c22e3c6c 5474 } else {
ce9ccb17 5475 err = -EINVAL;
6c167f58
EK		 5476 goto err_setup_rx;
5477 }
25946ddb 5478
41c445ff
JB		 5479 err = i40e_up_complete(vsi);
5480 if (err)
5481 goto err_up_complete;
5482
41c445ff
JB		 5483 return 0;
5484
5485err_up_complete:
5486 i40e_down(vsi);
25946ddb 5487err_set_queues:
41c445ff
JB		 5488 i40e_vsi_free_irq(vsi);
5489err_setup_rx:
5490 i40e_vsi_free_rx_resources(vsi);
5491err_setup_tx:
5492 i40e_vsi_free_tx_resources(vsi);
5493 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5494 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5495
5496 return err;
5497}
5498
17a73f6b
JG		 5499/**
5500 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5501 * @pf: Pointer to PF
17a73f6b
JG		 5502 *
5503 * This function destroys the hlist where all the Flow Director
5504 * filters were saved.
5505 **/
5506static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5507{
5508 struct i40e_fdir_filter *filter;
5509 struct hlist_node *node2;
5510
5511 hlist_for_each_entry_safe(filter, node2,
5512 &pf->fdir_filter_list, fdir_node) {
5513 hlist_del(&filter->fdir_node);
5514 kfree(filter);
5515 }
5516 pf->fdir_pf_active_filters = 0;
5517}
5518
41c445ff
JB		 5519/**
5520 * i40e_close - Disables a network interface
5521 * @netdev: network interface device structure
5522 *
5523 * The close entry point is called when an interface is de-activated
5524 * by the OS. The hardware is still under the driver's control, but
5525 * this netdev interface is disabled.
5526 *
5527 * Returns 0, this is not allowed to fail
5528 **/
38e00438 5529int i40e_close(struct net_device *netdev)
41c445ff
JB		 5530{
5531 struct i40e_netdev_priv *np = netdev_priv(netdev);
5532 struct i40e_vsi *vsi = np->vsi;
5533
90ef8d47 5534 i40e_vsi_close(vsi);
41c445ff
JB		 5535
5536 return 0;
5537}
5538
5539/**
5540 * i40e_do_reset - Start a PF or Core Reset sequence
5541 * @pf: board private structure
5542 * @reset_flags: which reset is requested
5543 *
5544 * The essential difference in resets is that the PF Reset
5545 * doesn't clear the packet buffers, doesn't reset the PE
5546 * firmware, and doesn't bother the other PFs on the chip.
5547 **/
5548void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5549{
5550 u32 val;
5551
5552 WARN_ON(in_interrupt());
5553
263fc48f 5554
41c445ff 5555 /* do the biggest reset indicated */
41a1d04b 5556 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5557
5558 /* Request a Global Reset
5559 *
5560 * This will start the chip's countdown to the actual full
5561 * chip reset event, and a warning interrupt to be sent
5562 * to all PFs, including the requestor. Our handler
5563 * for the warning interrupt will deal with the shutdown
5564 * and recovery of the switch setup.
5565 */
69bfb110 5566 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5567 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5568 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5569 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5570
41a1d04b 5571 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5572
5573 /* Request a Core Reset
5574 *
5575 * Same as Global Reset, except does *not* include the MAC/PHY
5576 */
69bfb110 5577 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5578 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5579 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5580 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5581 i40e_flush(&pf->hw);
5582
41a1d04b 5583 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5584
5585 /* Request a PF Reset
5586 *
5587 * Resets only the PF-specific registers
5588 *
5589 * This goes directly to the tear-down and rebuild of
5590 * the switch, since we need to do all the recovery as
5591 * for the Core Reset.
5592 */
69bfb110 5593 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5594 i40e_handle_reset_warning(pf);
5595
41a1d04b 5596 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5597 int v;
5598
5599 /* Find the VSI(s) that requested a re-init */
5600 dev_info(&pf->pdev->dev,
5601 "VSI reinit requested\n");
505682cd 5602 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5603 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5604
41c445ff
JB		 5605 if (vsi != NULL &&
5606 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5607 i40e_vsi_reinit_locked(pf->vsi[v]);
5608 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5609 }
5610 }
41a1d04b 5611 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5612 int v;
5613
5614 /* Find the VSI(s) that needs to be brought down */
5615 dev_info(&pf->pdev->dev, "VSI down requested\n");
5616 for (v = 0; v < pf->num_alloc_vsi; v++) {
5617 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5618
b5d06f05
NP		 5619 if (vsi != NULL &&
5620 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5621 set_bit(__I40E_DOWN, &vsi->state);
5622 i40e_down(vsi);
5623 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5624 }
5625 }
41c445ff
JB		 5626 } else {
5627 dev_info(&pf->pdev->dev,
5628 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5629 }
5630}
5631
4e3b35b0
NP		 5632#ifdef CONFIG_I40E_DCB
5633/**
5634 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5635 * @pf: board private structure
5636 * @old_cfg: current DCB config
5637 * @new_cfg: new DCB config
5638 **/
5639bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5640 struct i40e_dcbx_config *old_cfg,
5641 struct i40e_dcbx_config *new_cfg)
5642{
5643 bool need_reconfig = false;
5644
5645 /* Check if ETS configuration has changed */
5646 if (memcmp(&new_cfg->etscfg,
5647 &old_cfg->etscfg,
5648 sizeof(new_cfg->etscfg))) {
5649 /* If Priority Table has changed reconfig is needed */
5650 if (memcmp(&new_cfg->etscfg.prioritytable,
5651 &old_cfg->etscfg.prioritytable,
5652 sizeof(new_cfg->etscfg.prioritytable))) {
5653 need_reconfig = true;
69bfb110 5654 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5655 }
5656
5657 if (memcmp(&new_cfg->etscfg.tcbwtable,
5658 &old_cfg->etscfg.tcbwtable,
5659 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5660 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5661
5662 if (memcmp(&new_cfg->etscfg.tsatable,
5663 &old_cfg->etscfg.tsatable,
5664 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5665 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5666 }
5667
5668 /* Check if PFC configuration has changed */
5669 if (memcmp(&new_cfg->pfc,
5670 &old_cfg->pfc,
5671 sizeof(new_cfg->pfc))) {
5672 need_reconfig = true;
69bfb110 5673 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5674 }
5675
5676 /* Check if APP Table has changed */
5677 if (memcmp(&new_cfg->app,
5678 &old_cfg->app,
3d9667a9 5679 sizeof(new_cfg->app))) {
4e3b35b0 5680 need_reconfig = true;
69bfb110 5681 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5682 }
4e3b35b0 5683
fb43201f 5684 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5685 return need_reconfig;
5686}
5687
5688/**
5689 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5690 * @pf: board private structure
5691 * @e: event info posted on ARQ
5692 **/
5693static int i40e_handle_lldp_event(struct i40e_pf *pf,
5694 struct i40e_arq_event_info *e)
5695{
5696 struct i40e_aqc_lldp_get_mib *mib =
5697 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5698 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5699 struct i40e_dcbx_config tmp_dcbx_cfg;
5700 bool need_reconfig = false;
5701 int ret = 0;
5702 u8 type;
5703
4d9b6043
NP		 5704 /* Not DCB capable or capability disabled */
5705 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5706 return ret;
5707
4e3b35b0
NP		 5708 /* Ignore if event is not for Nearest Bridge */
5709 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5710 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5711 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5712 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5713 return ret;
5714
5715 /* Check MIB Type and return if event for Remote MIB update */
5716 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5717 dev_dbg(&pf->pdev->dev,
fb43201f 5718 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5719 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5720 /* Update the remote cached instance and return */
5721 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5722 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5723 &hw->remote_dcbx_config);
5724 goto exit;
5725 }
5726
9fa61dd2 5727 /* Store the old configuration */
1a2f6248 5728 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5729
750fcbcf
NP		 5730 /* Reset the old DCBx configuration data */
5731 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5732 /* Get updated DCBX data from firmware */
5733 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5734 if (ret) {
f1c7e72e
SN		 5735 dev_info(&pf->pdev->dev,
5736 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5737 i40e_stat_str(&pf->hw, ret),
5738 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5739 goto exit;
5740 }
5741
5742 /* No change detected in DCBX configs */
750fcbcf
NP		 5743 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5744 sizeof(tmp_dcbx_cfg))) {
69bfb110 5745 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5746 goto exit;
5747 }
5748
750fcbcf
NP		 5749 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5750 &hw->local_dcbx_config);
4e3b35b0 5751
750fcbcf 5752 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5753
5754 if (!need_reconfig)
5755 goto exit;
5756
4d9b6043 5757 /* Enable DCB tagging only when more than one TC */
750fcbcf 5758 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5759 pf->flags |= I40E_FLAG_DCB_ENABLED;
5760 else
5761 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5762
69129dc3 5763 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5764 /* Reconfiguration needed quiesce all VSIs */
5765 i40e_pf_quiesce_all_vsi(pf);
5766
5767 /* Changes in configuration update VEB/VSI */
5768 i40e_dcb_reconfigure(pf);
5769
2fd75f31
NP		 5770 ret = i40e_resume_port_tx(pf);
5771
69129dc3 5772 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5773 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5774 if (ret)
5775 goto exit;
5776
3fe06f41
NP		 5777 /* Wait for the PF's queues to be disabled */
5778 ret = i40e_pf_wait_queues_disabled(pf);
11e47708
PN		 5779 if (ret) {
5780 /* Schedule PF reset to recover */
5781 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5782 i40e_service_event_schedule(pf);
5783 } else {
2fd75f31 5784 i40e_pf_unquiesce_all_vsi(pf);
85a1aab7
NP		 5785 /* Notify the client for the DCB changes */
5786 i40e_notify_client_of_l2_param_changes(pf->vsi[pf->lan_vsi]);
11e47708
PN		 5787 }
5788
4e3b35b0
NP		 5789exit:
5790 return ret;
5791}
5792#endif /* CONFIG_I40E_DCB */
5793
23326186
ASJ		 5794/**
5795 * i40e_do_reset_safe - Protected reset path for userland calls.
5796 * @pf: board private structure
5797 * @reset_flags: which reset is requested
5798 *
5799 **/
5800void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5801{
5802 rtnl_lock();
5803 i40e_do_reset(pf, reset_flags);
5804 rtnl_unlock();
5805}
5806
41c445ff
JB		 5807/**
5808 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5809 * @pf: board private structure
5810 * @e: event info posted on ARQ
5811 *
5812 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5813 * and VF queues
5814 **/
5815static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5816 struct i40e_arq_event_info *e)
5817{
5818 struct i40e_aqc_lan_overflow *data =
5819 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5820 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5821 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5822 struct i40e_hw *hw = &pf->hw;
5823 struct i40e_vf *vf;
5824 u16 vf_id;
5825
69bfb110
JB		 5826 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5827 queue, qtx_ctl);
41c445ff
JB		 5828
5829 /* Queue belongs to VF, find the VF and issue VF reset */
5830 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5831 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5832 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5833 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5834 vf_id -= hw->func_caps.vf_base_id;
5835 vf = &pf->vf[vf_id];
5836 i40e_vc_notify_vf_reset(vf);
5837 /* Allow VF to process pending reset notification */
5838 msleep(20);
5839 i40e_reset_vf(vf, false);
5840 }
5841}
5842
5843/**
5844 * i40e_service_event_complete - Finish up the service event
5845 * @pf: board private structure
5846 **/
5847static void i40e_service_event_complete(struct i40e_pf *pf)
5848{
b875f99b 5849 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5850
5851 /* flush memory to make sure state is correct before next watchog */
4e857c58 5852 smp_mb__before_atomic();
41c445ff
JB		 5853 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5854}
5855
55a5e60b 5856/**
12957388
ASJ		 5857 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5858 * @pf: board private structure
5859 **/
04294e38 5860u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5861{
04294e38 5862 u32 val, fcnt_prog;
12957388
ASJ		 5863
5864 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5865 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5866 return fcnt_prog;
5867}
5868
5869/**
04294e38 5870 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5871 * @pf: board private structure
5872 **/
04294e38 5873u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5874{
04294e38
ASJ		 5875 u32 val, fcnt_prog;
5876
55a5e60b
ASJ		 5877 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5878 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5879 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5880 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5881 return fcnt_prog;
5882}
1e1be8f6 5883
04294e38
ASJ		 5884/**
5885 * i40e_get_global_fd_count - Get total FD filters programmed on device
5886 * @pf: board private structure
5887 **/
5888u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5889{
5890 u32 val, fcnt_prog;
5891
5892 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5893 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5894 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5895 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5896 return fcnt_prog;
5897}
5898
55a5e60b
ASJ		 5899/**
5900 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5901 * @pf: board private structure
5902 **/
5903void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5904{
3487b6c3 5905 struct i40e_fdir_filter *filter;
55a5e60b 5906 u32 fcnt_prog, fcnt_avail;
3487b6c3 5907 struct hlist_node *node;
55a5e60b 5908
1e1be8f6
ASJ		 5909 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5910 return;
5911
55a5e60b
ASJ		 5912 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5913 * to re-enable
5914 */
04294e38 5915 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5916 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5917 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5918 (pf->fd_add_err == 0) ||
5919 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5920 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5921 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5922 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5923 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5924 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5925 }
5926 }
5927 /* Wait for some more space to be available to turn on ATR */
5928 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5929 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5930 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5931 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5932 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5933 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5934 }
5935 }
3487b6c3
CW		 5936
5937 /* if hw had a problem adding a filter, delete it */
5938 if (pf->fd_inv > 0) {
5939 hlist_for_each_entry_safe(filter, node,
5940 &pf->fdir_filter_list, fdir_node) {
5941 if (filter->fd_id == pf->fd_inv) {
5942 hlist_del(&filter->fdir_node);
5943 kfree(filter);
5944 pf->fdir_pf_active_filters--;
5945 }
5946 }
5947 }
55a5e60b
ASJ		 5948}
5949
1e1be8f6 5950#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5951#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5952/**
5953 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5954 * @pf: board private structure
5955 **/
5956static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5957{
04294e38 5958 unsigned long min_flush_time;
1e1be8f6 5959 int flush_wait_retry = 50;
04294e38
ASJ		 5960 bool disable_atr = false;
5961 int fd_room;
1e1be8f6
ASJ		 5962 int reg;
5963
1790ed0c
AA		 5964 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5965 return;
5966
a5fdaf34
JB		 5967 if (!time_after(jiffies, pf->fd_flush_timestamp +
5968 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5969 return;
04294e38 5970
a5fdaf34
JB		 5971 /* If the flush is happening too quick and we have mostly SB rules we
5972 * should not re-enable ATR for some time.
5973 */
5974 min_flush_time = pf->fd_flush_timestamp +
5975 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5976 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5977
5978 if (!(time_after(jiffies, min_flush_time)) &&
5979 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5980 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5981 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5982 disable_atr = true;
5983 }
5984
5985 pf->fd_flush_timestamp = jiffies;
5986 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5987 /* flush all filters */
5988 wr32(&pf->hw, I40E_PFQF_CTL_1,
5989 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5990 i40e_flush(&pf->hw);
5991 pf->fd_flush_cnt++;
5992 pf->fd_add_err = 0;
5993 do {
5994 /* Check FD flush status every 5-6msec */
5995 usleep_range(5000, 6000);
5996 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5997 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5998 break;
5999 } while (flush_wait_retry--);
6000 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
6001 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
6002 } else {
6003 /* replay sideband filters */
6004 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
6005 if (!disable_atr)
6006 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6007 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
6008 if (I40E_DEBUG_FD & pf->hw.debug_mask)
6009 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6
ASJ		 6010 }
6011}
6012
6013/**
6014 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
6015 * @pf: board private structure
6016 **/
04294e38 6017u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 6018{
6019 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
6020}
6021
6022/* We can see up to 256 filter programming desc in transit if the filters are
6023 * being applied really fast; before we see the first
6024 * filter miss error on Rx queue 0. Accumulating enough error messages before
6025 * reacting will make sure we don't cause flush too often.
6026 */
6027#define I40E_MAX_FD_PROGRAM_ERROR 256
6028
41c445ff
JB		 6029/**
6030 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
6031 * @pf: board private structure
6032 **/
6033static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
6034{
41c445ff 6035
41c445ff
JB		 6036 /* if interface is down do nothing */
6037 if (test_bit(__I40E_DOWN, &pf->state))
6038 return;
1e1be8f6 6039
1790ed0c
AA		 6040 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
6041 return;
6042
04294e38 6043 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 6044 i40e_fdir_flush_and_replay(pf);
6045
55a5e60b
ASJ		 6046 i40e_fdir_check_and_reenable(pf);
6047
41c445ff
JB		 6048}
6049
6050/**
6051 * i40e_vsi_link_event - notify VSI of a link event
6052 * @vsi: vsi to be notified
6053 * @link_up: link up or down
6054 **/
6055static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
6056{
32b5b811 6057 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 6058 return;
6059
6060 switch (vsi->type) {
6061 case I40E_VSI_MAIN:
38e00438
VD		 6062#ifdef I40E_FCOE
6063 case I40E_VSI_FCOE:
6064#endif
41c445ff
JB		 6065 if (!vsi->netdev || !vsi->netdev_registered)
6066 break;
6067
6068 if (link_up) {
6069 netif_carrier_on(vsi->netdev);
6070 netif_tx_wake_all_queues(vsi->netdev);
6071 } else {
6072 netif_carrier_off(vsi->netdev);
6073 netif_tx_stop_all_queues(vsi->netdev);
6074 }
6075 break;
6076
6077 case I40E_VSI_SRIOV:
41c445ff
JB		 6078 case I40E_VSI_VMDQ2:
6079 case I40E_VSI_CTRL:
e3219ce6 6080 case I40E_VSI_IWARP:
41c445ff
JB		 6081 case I40E_VSI_MIRROR:
6082 default:
6083 /* there is no notification for other VSIs */
6084 break;
6085 }
6086}
6087
6088/**
6089 * i40e_veb_link_event - notify elements on the veb of a link event
6090 * @veb: veb to be notified
6091 * @link_up: link up or down
6092 **/
6093static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6094{
6095 struct i40e_pf *pf;
6096 int i;
6097
6098 if (!veb || !veb->pf)
6099 return;
6100 pf = veb->pf;
6101
6102 /* depth first... */
6103 for (i = 0; i < I40E_MAX_VEB; i++)
6104 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6105 i40e_veb_link_event(pf->veb[i], link_up);
6106
6107 /* ... now the local VSIs */
505682cd 6108 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6109 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6110 i40e_vsi_link_event(pf->vsi[i], link_up);
6111}
6112
6113/**
6114 * i40e_link_event - Update netif_carrier status
6115 * @pf: board private structure
6116 **/
6117static void i40e_link_event(struct i40e_pf *pf)
6118{
320684cd 6119 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6120 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6121 i40e_status status;
6122 bool new_link, old_link;
41c445ff 6123
1f9610e4
CS		 6124 /* save off old link status information */
6125 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6126
1e701e09
JB		 6127 /* set this to force the get_link_status call to refresh state */
6128 pf->hw.phy.get_link_info = true;
6129
41c445ff 6130 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6131
6132 status = i40e_get_link_status(&pf->hw, &new_link);
6133 if (status) {
6134 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6135 status);
6136 return;
6137 }
6138
fef59ddf
CS		 6139 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6140 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6141
1e701e09 6142 if (new_link == old_link &&
fef59ddf 6143 new_link_speed == old_link_speed &&
320684cd
MW		 6144 (test_bit(__I40E_DOWN, &vsi->state) ||
6145 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6146 return;
320684cd
MW		 6147
6148 if (!test_bit(__I40E_DOWN, &vsi->state))
6149 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6150
6151 /* Notify the base of the switch tree connected to
6152 * the link. Floating VEBs are not notified.
6153 */
6154 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6155 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6156 else
320684cd 6157 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6158
6159 if (pf->vf)
6160 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6161
6162 if (pf->flags & I40E_FLAG_PTP)
6163 i40e_ptp_set_increment(pf);
41c445ff
JB		 6164}
6165
41c445ff 6166/**
21536717 6167 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6168 * @pf: board private structure
6169 **/
6170static void i40e_watchdog_subtask(struct i40e_pf *pf)
6171{
6172 int i;
6173
6174 /* if interface is down do nothing */
6175 if (test_bit(__I40E_DOWN, &pf->state) ||
6176 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6177 return;
6178
21536717
SN		 6179 /* make sure we don't do these things too often */
6180 if (time_before(jiffies, (pf->service_timer_previous +
6181 pf->service_timer_period)))
6182 return;
6183 pf->service_timer_previous = jiffies;
6184
9ac77266
SN		 6185 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6186 i40e_link_event(pf);
21536717 6187
41c445ff
JB		 6188 /* Update the stats for active netdevs so the network stack
6189 * can look at updated numbers whenever it cares to
6190 */
505682cd 6191 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6192 if (pf->vsi[i] && pf->vsi[i]->netdev)
6193 i40e_update_stats(pf->vsi[i]);
6194
d1a8d275
ASJ		 6195 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6196 /* Update the stats for the active switching components */
6197 for (i = 0; i < I40E_MAX_VEB; i++)
6198 if (pf->veb[i])
6199 i40e_update_veb_stats(pf->veb[i]);
6200 }
beb0dff1
JK		 6201
6202 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6203}
6204
6205/**
6206 * i40e_reset_subtask - Set up for resetting the device and driver
6207 * @pf: board private structure
6208 **/
6209static void i40e_reset_subtask(struct i40e_pf *pf)
6210{
6211 u32 reset_flags = 0;
6212
23326186 6213 rtnl_lock();
41c445ff 6214 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6215 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6216 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6217 }
6218 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6219 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6220 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6221 }
6222 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6223 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6224 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6225 }
6226 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6227 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6228 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6229 }
b5d06f05 6230 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6231 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6232 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6233 }
41c445ff
JB		 6234
6235 /* If there's a recovery already waiting, it takes
6236 * precedence before starting a new reset sequence.
6237 */
6238 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6239 i40e_handle_reset_warning(pf);
23326186 6240 goto unlock;
41c445ff
JB		 6241 }
6242
6243 /* If we're already down or resetting, just bail */
6244 if (reset_flags &&
6245 !test_bit(__I40E_DOWN, &pf->state) &&
6246 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6247 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6248
6249unlock:
6250 rtnl_unlock();
41c445ff
JB		 6251}
6252
6253/**
6254 * i40e_handle_link_event - Handle link event
6255 * @pf: board private structure
6256 * @e: event info posted on ARQ
6257 **/
6258static void i40e_handle_link_event(struct i40e_pf *pf,
6259 struct i40e_arq_event_info *e)
6260{
41c445ff
JB		 6261 struct i40e_aqc_get_link_status *status =
6262 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6263
1e701e09
JB		 6264 /* Do a new status request to re-enable LSE reporting
6265 * and load new status information into the hw struct
6266 * This completely ignores any state information
6267 * in the ARQ event info, instead choosing to always
6268 * issue the AQ update link status command.
6269 */
6270 i40e_link_event(pf);
6271
7b592f61
CW		 6272 /* check for unqualified module, if link is down */
6273 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6274 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6275 (!(status->link_info & I40E_AQ_LINK_UP)))
6276 dev_err(&pf->pdev->dev,
6277 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6278}
6279
6280/**
6281 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6282 * @pf: board private structure
6283 **/
6284static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6285{
6286 struct i40e_arq_event_info event;
6287 struct i40e_hw *hw = &pf->hw;
6288 u16 pending, i = 0;
6289 i40e_status ret;
6290 u16 opcode;
86df242b 6291 u32 oldval;
41c445ff
JB		 6292 u32 val;
6293
a316f651
ASJ		 6294 /* Do not run clean AQ when PF reset fails */
6295 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6296 return;
6297
86df242b
SN		 6298 /* check for error indications */
6299 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6300 oldval = val;
6301 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6302 if (hw->debug_mask & I40E_DEBUG_AQ)
6303 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6304 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6305 }
6306 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6307 if (hw->debug_mask & I40E_DEBUG_AQ)
6308 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b 6309 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
1d0a4ada 6310 pf->arq_overflows++;
86df242b
SN		 6311 }
6312 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6313 if (hw->debug_mask & I40E_DEBUG_AQ)
6314 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6315 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6316 }
6317 if (oldval != val)
6318 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6319
6320 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6321 oldval = val;
6322 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6323 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6324 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6325 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6326 }
6327 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6328 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6329 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6330 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6331 }
6332 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6333 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6334 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6335 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6336 }
6337 if (oldval != val)
6338 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6339
1001dc37
MW		 6340 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6341 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6342 if (!event.msg_buf)
6343 return;
6344
6345 do {
6346 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6347 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6348 break;
56497978 6349 else if (ret) {
41c445ff
JB		 6350 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6351 break;
6352 }
6353
6354 opcode = le16_to_cpu(event.desc.opcode);
6355 switch (opcode) {
6356
6357 case i40e_aqc_opc_get_link_status:
6358 i40e_handle_link_event(pf, &event);
6359 break;
6360 case i40e_aqc_opc_send_msg_to_pf:
6361 ret = i40e_vc_process_vf_msg(pf,
6362 le16_to_cpu(event.desc.retval),
6363 le32_to_cpu(event.desc.cookie_high),
6364 le32_to_cpu(event.desc.cookie_low),
6365 event.msg_buf,
1001dc37 6366 event.msg_len);
41c445ff
JB		 6367 break;
6368 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6369 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6370#ifdef CONFIG_I40E_DCB
6371 rtnl_lock();
6372 ret = i40e_handle_lldp_event(pf, &event);
6373 rtnl_unlock();
6374#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6375 break;
6376 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6377 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6378 i40e_handle_lan_overflow_event(pf, &event);
6379 break;
0467bc91
SN		 6380 case i40e_aqc_opc_send_msg_to_peer:
6381 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6382 break;
91a0f930
SN		 6383 case i40e_aqc_opc_nvm_erase:
6384 case i40e_aqc_opc_nvm_update:
00ada50d 6385 case i40e_aqc_opc_oem_post_update:
6e93d0c9
SN		 6386 i40e_debug(&pf->hw, I40E_DEBUG_NVM,
6387 "ARQ NVM operation 0x%04x completed\n",
6388 opcode);
91a0f930 6389 break;
41c445ff
JB		 6390 default:
6391 dev_info(&pf->pdev->dev,
56e5ca68 6392 "ARQ: Unknown event 0x%04x ignored\n",
0467bc91 6393 opcode);
41c445ff
JB		 6394 break;
6395 }
6396 } while (pending && (i++ < pf->adminq_work_limit));
6397
6398 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6399 /* re-enable Admin queue interrupt cause */
6400 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6401 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6402 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6403 i40e_flush(hw);
6404
6405 kfree(event.msg_buf);
6406}
6407
4eb3f768
SN		 6408/**
6409 * i40e_verify_eeprom - make sure eeprom is good to use
6410 * @pf: board private structure
6411 **/
6412static void i40e_verify_eeprom(struct i40e_pf *pf)
6413{
6414 int err;
6415
6416 err = i40e_diag_eeprom_test(&pf->hw);
6417 if (err) {
6418 /* retry in case of garbage read */
6419 err = i40e_diag_eeprom_test(&pf->hw);
6420 if (err) {
6421 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6422 err);
6423 set_bit(__I40E_BAD_EEPROM, &pf->state);
6424 }
6425 }
6426
6427 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6428 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6429 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6430 }
6431}
6432
386a0afa
AA		 6433/**
6434 * i40e_enable_pf_switch_lb
b40c82e6 6435 * @pf: pointer to the PF structure
386a0afa
AA		 6436 *
6437 * enable switch loop back or die - no point in a return value
6438 **/
6439static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6440{
6441 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6442 struct i40e_vsi_context ctxt;
f1c7e72e 6443 int ret;
386a0afa
AA		 6444
6445 ctxt.seid = pf->main_vsi_seid;
6446 ctxt.pf_num = pf->hw.pf_id;
6447 ctxt.vf_num = 0;
f1c7e72e
SN		 6448 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6449 if (ret) {
386a0afa 6450 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6451 "couldn't get PF vsi config, err %s aq_err %s\n",
6452 i40e_stat_str(&pf->hw, ret),
6453 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6454 return;
6455 }
6456 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6457 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6458 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6459
f1c7e72e
SN		 6460 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6461 if (ret) {
386a0afa 6462 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6463 "update vsi switch failed, err %s aq_err %s\n",
6464 i40e_stat_str(&pf->hw, ret),
6465 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6466 }
6467}
6468
6469/**
6470 * i40e_disable_pf_switch_lb
b40c82e6 6471 * @pf: pointer to the PF structure
386a0afa
AA		 6472 *
6473 * disable switch loop back or die - no point in a return value
6474 **/
6475static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6476{
6477 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6478 struct i40e_vsi_context ctxt;
f1c7e72e 6479 int ret;
386a0afa
AA		 6480
6481 ctxt.seid = pf->main_vsi_seid;
6482 ctxt.pf_num = pf->hw.pf_id;
6483 ctxt.vf_num = 0;
f1c7e72e
SN		 6484 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6485 if (ret) {
386a0afa 6486 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6487 "couldn't get PF vsi config, err %s aq_err %s\n",
6488 i40e_stat_str(&pf->hw, ret),
6489 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6490 return;
6491 }
6492 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6493 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6494 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6495
f1c7e72e
SN		 6496 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6497 if (ret) {
386a0afa 6498 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6499 "update vsi switch failed, err %s aq_err %s\n",
6500 i40e_stat_str(&pf->hw, ret),
6501 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6502 }
6503}
6504
51616018
NP		 6505/**
6506 * i40e_config_bridge_mode - Configure the HW bridge mode
6507 * @veb: pointer to the bridge instance
6508 *
6509 * Configure the loop back mode for the LAN VSI that is downlink to the
6510 * specified HW bridge instance. It is expected this function is called
6511 * when a new HW bridge is instantiated.
6512 **/
6513static void i40e_config_bridge_mode(struct i40e_veb *veb)
6514{
6515 struct i40e_pf *pf = veb->pf;
6516
6dec1017
SN		 6517 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6518 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6519 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6520 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6521 i40e_disable_pf_switch_lb(pf);
6522 else
6523 i40e_enable_pf_switch_lb(pf);
6524}
6525
41c445ff
JB		 6526/**
6527 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6528 * @veb: pointer to the VEB instance
6529 *
6530 * This is a recursive function that first builds the attached VSIs then
6531 * recurses in to build the next layer of VEB. We track the connections
6532 * through our own index numbers because the seid's from the HW could
6533 * change across the reset.
6534 **/
6535static int i40e_reconstitute_veb(struct i40e_veb *veb)
6536{
6537 struct i40e_vsi *ctl_vsi = NULL;
6538 struct i40e_pf *pf = veb->pf;
6539 int v, veb_idx;
6540 int ret;
6541
6542 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6543 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6544 if (pf->vsi[v] &&
6545 pf->vsi[v]->veb_idx == veb->idx &&
6546 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6547 ctl_vsi = pf->vsi[v];
6548 break;
6549 }
6550 }
6551 if (!ctl_vsi) {
6552 dev_info(&pf->pdev->dev,
6553 "missing owner VSI for veb_idx %d\n", veb->idx);
6554 ret = -ENOENT;
6555 goto end_reconstitute;
6556 }
6557 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6558 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6559 ret = i40e_add_vsi(ctl_vsi);
6560 if (ret) {
6561 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6562 "rebuild of veb_idx %d owner VSI failed: %d\n",
6563 veb->idx, ret);
41c445ff
JB		 6564 goto end_reconstitute;
6565 }
6566 i40e_vsi_reset_stats(ctl_vsi);
6567
6568 /* create the VEB in the switch and move the VSI onto the VEB */
6569 ret = i40e_add_veb(veb, ctl_vsi);
6570 if (ret)
6571 goto end_reconstitute;
6572
fc60861e
ASJ		 6573 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6574 veb->bridge_mode = BRIDGE_MODE_VEB;
6575 else
6576 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6577 i40e_config_bridge_mode(veb);
b64ba084 6578
41c445ff 6579 /* create the remaining VSIs attached to this VEB */
505682cd 6580 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6581 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6582 continue;
6583
6584 if (pf->vsi[v]->veb_idx == veb->idx) {
6585 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6586
41c445ff
JB		 6587 vsi->uplink_seid = veb->seid;
6588 ret = i40e_add_vsi(vsi);
6589 if (ret) {
6590 dev_info(&pf->pdev->dev,
6591 "rebuild of vsi_idx %d failed: %d\n",
6592 v, ret);
6593 goto end_reconstitute;
6594 }
6595 i40e_vsi_reset_stats(vsi);
6596 }
6597 }
6598
6599 /* create any VEBs attached to this VEB - RECURSION */
6600 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6601 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6602 pf->veb[veb_idx]->uplink_seid = veb->seid;
6603 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6604 if (ret)
6605 break;
6606 }
6607 }
6608
6609end_reconstitute:
6610 return ret;
6611}
6612
6613/**
6614 * i40e_get_capabilities - get info about the HW
6615 * @pf: the PF struct
6616 **/
6617static int i40e_get_capabilities(struct i40e_pf *pf)
6618{
6619 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6620 u16 data_size;
6621 int buf_len;
6622 int err;
6623
6624 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6625 do {
6626 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6627 if (!cap_buf)
6628 return -ENOMEM;
6629
6630 /* this loads the data into the hw struct for us */
6631 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6632 &data_size,
6633 i40e_aqc_opc_list_func_capabilities,
6634 NULL);
6635 /* data loaded, buffer no longer needed */
6636 kfree(cap_buf);
6637
6638 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6639 /* retry with a larger buffer */
6640 buf_len = data_size;
6641 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6642 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6643 "capability discovery failed, err %s aq_err %s\n",
6644 i40e_stat_str(&pf->hw, err),
6645 i40e_aq_str(&pf->hw,
6646 pf->hw.aq.asq_last_status));
41c445ff
JB		 6647 return -ENODEV;
6648 }
6649 } while (err);
6650
6651 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6652 dev_info(&pf->pdev->dev,
6653 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6654 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6655 pf->hw.func_caps.num_msix_vectors,
6656 pf->hw.func_caps.num_msix_vectors_vf,
6657 pf->hw.func_caps.fd_filters_guaranteed,
6658 pf->hw.func_caps.fd_filters_best_effort,
6659 pf->hw.func_caps.num_tx_qp,
6660 pf->hw.func_caps.num_vsis);
6661
7134f9ce
JB		 6662#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6663 + pf->hw.func_caps.num_vfs)
6664 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6665 dev_info(&pf->pdev->dev,
6666 "got num_vsis %d, setting num_vsis to %d\n",
6667 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6668 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6669 }
6670
41c445ff
JB		 6671 return 0;
6672}
6673
cbf61325
ASJ		 6674static int i40e_vsi_clear(struct i40e_vsi *vsi);
6675
41c445ff 6676/**
cbf61325 6677 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6678 * @pf: board private structure
6679 **/
cbf61325 6680static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6681{
6682 struct i40e_vsi *vsi;
8a9eb7d3 6683 int i;
41c445ff 6684
407e063c
JB		 6685 /* quick workaround for an NVM issue that leaves a critical register
6686 * uninitialized
6687 */
6688 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6689 static const u32 hkey[] = {
6690 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6691 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6692 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6693 0x95b3a76d};
6694
6695 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6696 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6697 }
6698
cbf61325 6699 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6700 return;
6701
cbf61325 6702 /* find existing VSI and see if it needs configuring */
41c445ff 6703 vsi = NULL;
505682cd 6704 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6705 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6706 vsi = pf->vsi[i];
cbf61325
ASJ		 6707 break;
6708 }
6709 }
6710
6711 /* create a new VSI if none exists */
41c445ff 6712 if (!vsi) {
cbf61325
ASJ		 6713 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6714 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6715 if (!vsi) {
6716 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6717 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6718 return;
41c445ff 6719 }
cbf61325 6720 }
41c445ff 6721
8a9eb7d3 6722 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6723}
6724
6725/**
6726 * i40e_fdir_teardown - release the Flow Director resources
6727 * @pf: board private structure
6728 **/
6729static void i40e_fdir_teardown(struct i40e_pf *pf)
6730{
6731 int i;
6732
17a73f6b 6733 i40e_fdir_filter_exit(pf);
505682cd 6734 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6735 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6736 i40e_vsi_release(pf->vsi[i]);
6737 break;
6738 }
6739 }
6740}
6741
6742/**
f650a38b 6743 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6744 * @pf: board private structure
6745 *
b40c82e6 6746 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6747 **/
23cfbe07 6748static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6749{
41c445ff 6750 struct i40e_hw *hw = &pf->hw;
60442dea 6751 i40e_status ret = 0;
41c445ff
JB		 6752 u32 v;
6753
6754 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6755 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6756 return;
d3ce5734
MW		 6757 if (i40e_check_asq_alive(&pf->hw))
6758 i40e_vc_notify_reset(pf);
41c445ff 6759
69bfb110 6760 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6761
41c445ff
JB		 6762 /* quiesce the VSIs and their queues that are not already DOWN */
6763 i40e_pf_quiesce_all_vsi(pf);
6764
505682cd 6765 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6766 if (pf->vsi[v])
6767 pf->vsi[v]->seid = 0;
6768 }
6769
6770 i40e_shutdown_adminq(&pf->hw);
6771
f650a38b 6772 /* call shutdown HMC */
60442dea
SN		 6773 if (hw->hmc.hmc_obj) {
6774 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6775 if (ret)
60442dea
SN		 6776 dev_warn(&pf->pdev->dev,
6777 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6778 }
f650a38b
ASJ		 6779}
6780
44033fac
JB		 6781/**
6782 * i40e_send_version - update firmware with driver version
6783 * @pf: PF struct
6784 */
6785static void i40e_send_version(struct i40e_pf *pf)
6786{
6787 struct i40e_driver_version dv;
6788
6789 dv.major_version = DRV_VERSION_MAJOR;
6790 dv.minor_version = DRV_VERSION_MINOR;
6791 dv.build_version = DRV_VERSION_BUILD;
6792 dv.subbuild_version = 0;
35a7d804 6793 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6794 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6795}
6796
f650a38b 6797/**
4dda12e6 6798 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6799 * @pf: board private structure
bc7d338f 6800 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6801 **/
bc7d338f 6802static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6803{
f650a38b 6804 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6805 u8 set_fc_aq_fail = 0;
f650a38b 6806 i40e_status ret;
4f2f017c 6807 u32 val;
f650a38b
ASJ		 6808 u32 v;
6809
41c445ff
JB		 6810 /* Now we wait for GRST to settle out.
6811 * We don't have to delete the VEBs or VSIs from the hw switch
6812 * because the reset will make them disappear.
6813 */
6814 ret = i40e_pf_reset(hw);
b5565400 6815 if (ret) {
41c445ff 6816 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6817 set_bit(__I40E_RESET_FAILED, &pf->state);
6818 goto clear_recovery;
b5565400 6819 }
41c445ff
JB		 6820 pf->pfr_count++;
6821
6822 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6823 goto clear_recovery;
69bfb110 6824 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6825
6826 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6827 ret = i40e_init_adminq(&pf->hw);
6828 if (ret) {
f1c7e72e
SN		 6829 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6830 i40e_stat_str(&pf->hw, ret),
6831 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6832 goto clear_recovery;
41c445ff
JB		 6833 }
6834
4eb3f768 6835 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6836 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6837 i40e_verify_eeprom(pf);
4eb3f768 6838
e78ac4bf 6839 i40e_clear_pxe_mode(hw);
41c445ff 6840 ret = i40e_get_capabilities(pf);
f1c7e72e 6841 if (ret)
41c445ff 6842 goto end_core_reset;
41c445ff 6843
41c445ff
JB		 6844 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6845 hw->func_caps.num_rx_qp,
6846 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6847 if (ret) {
6848 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6849 goto end_core_reset;
6850 }
6851 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6852 if (ret) {
6853 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6854 goto end_core_reset;
6855 }
6856
4e3b35b0
NP		 6857#ifdef CONFIG_I40E_DCB
6858 ret = i40e_init_pf_dcb(pf);
6859 if (ret) {
aebfc816
SN		 6860 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6861 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6862 /* Continue without DCB enabled */
4e3b35b0
NP		 6863 }
6864#endif /* CONFIG_I40E_DCB */
38e00438 6865#ifdef I40E_FCOE
21364bcf 6866 i40e_init_pf_fcoe(pf);
4e3b35b0 6867
38e00438 6868#endif
41c445ff 6869 /* do basic switch setup */
bc7d338f 6870 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6871 if (ret)
6872 goto end_core_reset;
6873
2f0aff41
SN		 6874 /* The driver only wants link up/down and module qualification
6875 * reports from firmware. Note the negative logic.
7e2453fe
JB		 6876 */
6877 ret = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 6878 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 6879 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 6880 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 6881 if (ret)
f1c7e72e
SN		 6882 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6883 i40e_stat_str(&pf->hw, ret),
6884 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6885
cafa2ee6
ASJ		 6886 /* make sure our flow control settings are restored */
6887 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6888 if (ret)
8279e495
NP		 6889 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6890 i40e_stat_str(&pf->hw, ret),
6891 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6892
41c445ff
JB		 6893 /* Rebuild the VSIs and VEBs that existed before reset.
6894 * They are still in our local switch element arrays, so only
6895 * need to rebuild the switch model in the HW.
6896 *
6897 * If there were VEBs but the reconstitution failed, we'll try
6898 * try to recover minimal use by getting the basic PF VSI working.
6899 */
6900 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6901 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6902 /* find the one VEB connected to the MAC, and find orphans */
6903 for (v = 0; v < I40E_MAX_VEB; v++) {
6904 if (!pf->veb[v])
6905 continue;
6906
6907 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6908 pf->veb[v]->uplink_seid == 0) {
6909 ret = i40e_reconstitute_veb(pf->veb[v]);
6910
6911 if (!ret)
6912 continue;
6913
6914 /* If Main VEB failed, we're in deep doodoo,
6915 * so give up rebuilding the switch and set up
6916 * for minimal rebuild of PF VSI.
6917 * If orphan failed, we'll report the error
6918 * but try to keep going.
6919 */
6920 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6921 dev_info(&pf->pdev->dev,
6922 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6923 ret);
6924 pf->vsi[pf->lan_vsi]->uplink_seid
6925 = pf->mac_seid;
6926 break;
6927 } else if (pf->veb[v]->uplink_seid == 0) {
6928 dev_info(&pf->pdev->dev,
6929 "rebuild of orphan VEB failed: %d\n",
6930 ret);
6931 }
6932 }
6933 }
6934 }
6935
6936 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6937 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6938 /* no VEB, so rebuild only the Main VSI */
6939 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6940 if (ret) {
6941 dev_info(&pf->pdev->dev,
6942 "rebuild of Main VSI failed: %d\n", ret);
6943 goto end_core_reset;
6944 }
6945 }
6946
4f2f017c
ASJ		 6947 /* Reconfigure hardware for allowing smaller MSS in the case
6948 * of TSO, so that we avoid the MDD being fired and causing
6949 * a reset in the case of small MSS+TSO.
6950 */
6951#define I40E_REG_MSS 0x000E64DC
6952#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6953#define I40E_64BYTE_MSS 0x400000
6954 val = rd32(hw, I40E_REG_MSS);
6955 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6956 val &= ~I40E_REG_MSS_MIN_MASK;
6957 val |= I40E_64BYTE_MSS;
6958 wr32(hw, I40E_REG_MSS, val);
6959 }
6960
8eed76fa 6961 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 6962 msleep(75);
6963 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6964 if (ret)
f1c7e72e
SN		 6965 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6966 i40e_stat_str(&pf->hw, ret),
6967 i40e_aq_str(&pf->hw,
6968 pf->hw.aq.asq_last_status));
cafa2ee6 6969 }
41c445ff
JB		 6970 /* reinit the misc interrupt */
6971 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6972 ret = i40e_setup_misc_vector(pf);
6973
e7358f54
ASJ		 6974 /* Add a filter to drop all Flow control frames from any VSI from being
6975 * transmitted. By doing so we stop a malicious VF from sending out
6976 * PAUSE or PFC frames and potentially controlling traffic for other
6977 * PF/VF VSIs.
6978 * The FW can still send Flow control frames if enabled.
6979 */
6980 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6981 pf->main_vsi_seid);
6982
41c445ff
JB		 6983 /* restart the VSIs that were rebuilt and running before the reset */
6984 i40e_pf_unquiesce_all_vsi(pf);
6985
69f64b2b
MW		 6986 if (pf->num_alloc_vfs) {
6987 for (v = 0; v < pf->num_alloc_vfs; v++)
6988 i40e_reset_vf(&pf->vf[v], true);
6989 }
6990
41c445ff 6991 /* tell the firmware that we're starting */
44033fac 6992 i40e_send_version(pf);
41c445ff
JB		 6993
6994end_core_reset:
a316f651
ASJ		 6995 clear_bit(__I40E_RESET_FAILED, &pf->state);
6996clear_recovery:
41c445ff
JB		 6997 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6998}
6999
f650a38b 7000/**
b40c82e6 7001 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 7002 * @pf: board private structure
7003 *
7004 * Close up the VFs and other things in prep for a Core Reset,
7005 * then get ready to rebuild the world.
7006 **/
7007static void i40e_handle_reset_warning(struct i40e_pf *pf)
7008{
23cfbe07
SN		 7009 i40e_prep_for_reset(pf);
7010 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 7011}
7012
41c445ff
JB		 7013/**
7014 * i40e_handle_mdd_event
b40c82e6 7015 * @pf: pointer to the PF structure
41c445ff
JB		 7016 *
7017 * Called from the MDD irq handler to identify possibly malicious vfs
7018 **/
7019static void i40e_handle_mdd_event(struct i40e_pf *pf)
7020{
7021 struct i40e_hw *hw = &pf->hw;
7022 bool mdd_detected = false;
df430b12 7023 bool pf_mdd_detected = false;
41c445ff
JB		 7024 struct i40e_vf *vf;
7025 u32 reg;
7026 int i;
7027
7028 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
7029 return;
7030
7031 /* find what triggered the MDD event */
7032 reg = rd32(hw, I40E_GL_MDET_TX);
7033 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 7034 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
7035 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 7036 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 7037 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 7038 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 7039 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 7040 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
7041 I40E_GL_MDET_TX_QUEUE_SHIFT) -
7042 pf->hw.func_caps.base_queue;
faf32978 7043 if (netif_msg_tx_err(pf))
b40c82e6 7044 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 7045 event, queue, pf_num, vf_num);
41c445ff
JB		 7046 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
7047 mdd_detected = true;
7048 }
7049 reg = rd32(hw, I40E_GL_MDET_RX);
7050 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 7051 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
7052 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 7053 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 7054 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 7055 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
7056 I40E_GL_MDET_RX_QUEUE_SHIFT) -
7057 pf->hw.func_caps.base_queue;
faf32978
JB		 7058 if (netif_msg_rx_err(pf))
7059 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
7060 event, queue, func);
41c445ff
JB		 7061 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
7062 mdd_detected = true;
7063 }
7064
df430b12
NP		 7065 if (mdd_detected) {
7066 reg = rd32(hw, I40E_PF_MDET_TX);
7067 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
7068 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 7069 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 7070 pf_mdd_detected = true;
7071 }
7072 reg = rd32(hw, I40E_PF_MDET_RX);
7073 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
7074 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 7075 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 7076 pf_mdd_detected = true;
7077 }
7078 /* Queue belongs to the PF, initiate a reset */
7079 if (pf_mdd_detected) {
7080 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7081 i40e_service_event_schedule(pf);
7082 }
7083 }
7084
41c445ff
JB		 7085 /* see if one of the VFs needs its hand slapped */
7086 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7087 vf = &(pf->vf[i]);
7088 reg = rd32(hw, I40E_VP_MDET_TX(i));
7089 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7090 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7091 vf->num_mdd_events++;
faf32978
JB		 7092 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7093 i);
41c445ff
JB		 7094 }
7095
7096 reg = rd32(hw, I40E_VP_MDET_RX(i));
7097 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7098 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7099 vf->num_mdd_events++;
faf32978
JB		 7100 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7101 i);
41c445ff
JB		 7102 }
7103
7104 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7105 dev_info(&pf->pdev->dev,
7106 "Too many MDD events on VF %d, disabled\n", i);
7107 dev_info(&pf->pdev->dev,
7108 "Use PF Control I/F to re-enable the VF\n");
7109 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7110 }
7111 }
7112
7113 /* re-enable mdd interrupt cause */
7114 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7115 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7116 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7117 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7118 i40e_flush(hw);
7119}
7120
a1c9a9d9 7121/**
6a899024 7122 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7123 * @pf: board private structure
7124 **/
6a899024 7125static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7126{
a1c9a9d9
JK		 7127 struct i40e_hw *hw = &pf->hw;
7128 i40e_status ret;
a1c9a9d9
JK		 7129 __be16 port;
7130 int i;
7131
6a899024 7132 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7133 return;
7134
6a899024 7135 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7136
7137 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7138 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7139 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7140 port = pf->udp_ports[i].index;
c22c06c8
SN		 7141 if (port)
7142 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7143 pf->udp_ports[i].type,
c22c06c8
SN		 7144 NULL, NULL);
7145 else
7146 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7147
7148 if (ret) {
730a8f87
CW		 7149 dev_dbg(&pf->pdev->dev,
7150 "%s %s port %d, index %d failed, err %s aq_err %s\n",
7151 pf->udp_ports[i].type ? "vxlan" : "geneve",
7152 port ? "add" : "delete",
7153 ntohs(port), i,
7154 i40e_stat_str(&pf->hw, ret),
7155 i40e_aq_str(&pf->hw,
f1c7e72e 7156 pf->hw.aq.asq_last_status));
6a899024 7157 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7158 }
7159 }
7160 }
7161}
7162
41c445ff
JB		 7163/**
7164 * i40e_service_task - Run the driver's async subtasks
7165 * @work: pointer to work_struct containing our data
7166 **/
7167static void i40e_service_task(struct work_struct *work)
7168{
7169 struct i40e_pf *pf = container_of(work,
7170 struct i40e_pf,
7171 service_task);
7172 unsigned long start_time = jiffies;
7173
e57a2fea
SN		 7174 /* don't bother with service tasks if a reset is in progress */
7175 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7176 i40e_service_event_complete(pf);
7177 return;
7178 }
7179
b03a8c1f 7180 i40e_detect_recover_hung(pf);
2818ccd9 7181 i40e_sync_filters_subtask(pf);
41c445ff
JB		 7182 i40e_reset_subtask(pf);
7183 i40e_handle_mdd_event(pf);
7184 i40e_vc_process_vflr_event(pf);
7185 i40e_watchdog_subtask(pf);
7186 i40e_fdir_reinit_subtask(pf);
e3219ce6 7187 i40e_client_subtask(pf);
41c445ff 7188 i40e_sync_filters_subtask(pf);
6a899024 7189 i40e_sync_udp_filters_subtask(pf);
41c445ff
JB		 7190 i40e_clean_adminq_subtask(pf);
7191
7192 i40e_service_event_complete(pf);
7193
7194 /* If the tasks have taken longer than one timer cycle or there
7195 * is more work to be done, reschedule the service task now
7196 * rather than wait for the timer to tick again.
7197 */
7198 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7199 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7200 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7201 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7202 i40e_service_event_schedule(pf);
7203}
7204
7205/**
7206 * i40e_service_timer - timer callback
7207 * @data: pointer to PF struct
7208 **/
7209static void i40e_service_timer(unsigned long data)
7210{
7211 struct i40e_pf *pf = (struct i40e_pf *)data;
7212
7213 mod_timer(&pf->service_timer,
7214 round_jiffies(jiffies + pf->service_timer_period));
7215 i40e_service_event_schedule(pf);
7216}
7217
7218/**
7219 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7220 * @vsi: the VSI being configured
7221 **/
7222static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7223{
7224 struct i40e_pf *pf = vsi->back;
7225
7226 switch (vsi->type) {
7227 case I40E_VSI_MAIN:
7228 vsi->alloc_queue_pairs = pf->num_lan_qps;
7229 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7230 I40E_REQ_DESCRIPTOR_MULTIPLE);
7231 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7232 vsi->num_q_vectors = pf->num_lan_msix;
7233 else
7234 vsi->num_q_vectors = 1;
7235
7236 break;
7237
7238 case I40E_VSI_FDIR:
7239 vsi->alloc_queue_pairs = 1;
7240 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7241 I40E_REQ_DESCRIPTOR_MULTIPLE);
a70e407f 7242 vsi->num_q_vectors = pf->num_fdsb_msix;
41c445ff
JB		 7243 break;
7244
7245 case I40E_VSI_VMDQ2:
7246 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7247 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7248 I40E_REQ_DESCRIPTOR_MULTIPLE);
7249 vsi->num_q_vectors = pf->num_vmdq_msix;
7250 break;
7251
7252 case I40E_VSI_SRIOV:
7253 vsi->alloc_queue_pairs = pf->num_vf_qps;
7254 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7255 I40E_REQ_DESCRIPTOR_MULTIPLE);
7256 break;
7257
38e00438
VD		 7258#ifdef I40E_FCOE
7259 case I40E_VSI_FCOE:
7260 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7261 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7262 I40E_REQ_DESCRIPTOR_MULTIPLE);
7263 vsi->num_q_vectors = pf->num_fcoe_msix;
7264 break;
7265
7266#endif /* I40E_FCOE */
41c445ff
JB		 7267 default:
7268 WARN_ON(1);
7269 return -ENODATA;
7270 }
7271
7272 return 0;
7273}
7274
f650a38b
ASJ		 7275/**
7276 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7277 * @type: VSI pointer
bc7d338f 7278 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7279 *
7280 * On error: returns error code (negative)
7281 * On success: returns 0
7282 **/
bc7d338f 7283static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7284{
7285 int size;
7286 int ret = 0;
7287
ac6c5e3d 7288 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7289 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7290 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7291 if (!vsi->tx_rings)
7292 return -ENOMEM;
f650a38b
ASJ		 7293 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7294
bc7d338f
ASJ		 7295 if (alloc_qvectors) {
7296 /* allocate memory for q_vector pointers */
f57e4fbd 7297 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7298 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7299 if (!vsi->q_vectors) {
7300 ret = -ENOMEM;
7301 goto err_vectors;
7302 }
f650a38b
ASJ		 7303 }
7304 return ret;
7305
7306err_vectors:
7307 kfree(vsi->tx_rings);
7308 return ret;
7309}
7310
41c445ff
JB		 7311/**
7312 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7313 * @pf: board private structure
7314 * @type: type of VSI
7315 *
7316 * On error: returns error code (negative)
7317 * On success: returns vsi index in PF (positive)
7318 **/
7319static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7320{
7321 int ret = -ENODEV;
7322 struct i40e_vsi *vsi;
7323 int vsi_idx;
7324 int i;
7325
7326 /* Need to protect the allocation of the VSIs at the PF level */
7327 mutex_lock(&pf->switch_mutex);
7328
7329 /* VSI list may be fragmented if VSI creation/destruction has
7330 * been happening. We can afford to do a quick scan to look
7331 * for any free VSIs in the list.
7332 *
7333 * find next empty vsi slot, looping back around if necessary
7334 */
7335 i = pf->next_vsi;
505682cd 7336 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7337 i++;
505682cd 7338 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7339 i = 0;
7340 while (i < pf->next_vsi && pf->vsi[i])
7341 i++;
7342 }
7343
505682cd 7344 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7345 vsi_idx = i; /* Found one! */
7346 } else {
7347 ret = -ENODEV;
493fb300 7348 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7349 }
7350 pf->next_vsi = ++i;
7351
7352 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7353 if (!vsi) {
7354 ret = -ENOMEM;
493fb300 7355 goto unlock_pf;
41c445ff
JB		 7356 }
7357 vsi->type = type;
7358 vsi->back = pf;
7359 set_bit(__I40E_DOWN, &vsi->state);
7360 vsi->flags = 0;
7361 vsi->idx = vsi_idx;
ac26fc13 7362 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7363 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7364 pf->rss_table_size : 64;
41c445ff
JB		 7365 vsi->netdev_registered = false;
7366 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7367 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7368 vsi->irqs_ready = false;
41c445ff 7369
9f65e15b
AD		 7370 ret = i40e_set_num_rings_in_vsi(vsi);
7371 if (ret)
7372 goto err_rings;
7373
bc7d338f 7374 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7375 if (ret)
9f65e15b 7376 goto err_rings;
493fb300 7377
41c445ff
JB		 7378 /* Setup default MSIX irq handler for VSI */
7379 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7380
21659035
KP		 7381 /* Initialize VSI lock */
7382 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7383 pf->vsi[vsi_idx] = vsi;
7384 ret = vsi_idx;
493fb300
AD		 7385 goto unlock_pf;
7386
9f65e15b 7387err_rings:
493fb300
AD		 7388 pf->next_vsi = i - 1;
7389 kfree(vsi);
7390unlock_pf:
41c445ff
JB		 7391 mutex_unlock(&pf->switch_mutex);
7392 return ret;
7393}
7394
f650a38b
ASJ		 7395/**
7396 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7397 * @type: VSI pointer
bc7d338f 7398 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7399 *
7400 * On error: returns error code (negative)
7401 * On success: returns 0
7402 **/
bc7d338f 7403static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7404{
7405 /* free the ring and vector containers */
bc7d338f
ASJ		 7406 if (free_qvectors) {
7407 kfree(vsi->q_vectors);
7408 vsi->q_vectors = NULL;
7409 }
f650a38b
ASJ		 7410 kfree(vsi->tx_rings);
7411 vsi->tx_rings = NULL;
7412 vsi->rx_rings = NULL;
7413}
7414
28c5869f
HZ		 7415/**
7416 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7417 * and lookup table
7418 * @vsi: Pointer to VSI structure
7419 */
7420static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7421{
7422 if (!vsi)
7423 return;
7424
7425 kfree(vsi->rss_hkey_user);
7426 vsi->rss_hkey_user = NULL;
7427
7428 kfree(vsi->rss_lut_user);
7429 vsi->rss_lut_user = NULL;
7430}
7431
41c445ff
JB		 7432/**
7433 * i40e_vsi_clear - Deallocate the VSI provided
7434 * @vsi: the VSI being un-configured
7435 **/
7436static int i40e_vsi_clear(struct i40e_vsi *vsi)
7437{
7438 struct i40e_pf *pf;
7439
7440 if (!vsi)
7441 return 0;
7442
7443 if (!vsi->back)
7444 goto free_vsi;
7445 pf = vsi->back;
7446
7447 mutex_lock(&pf->switch_mutex);
7448 if (!pf->vsi[vsi->idx]) {
7449 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7450 vsi->idx, vsi->idx, vsi, vsi->type);
7451 goto unlock_vsi;
7452 }
7453
7454 if (pf->vsi[vsi->idx] != vsi) {
7455 dev_err(&pf->pdev->dev,
7456 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7457 pf->vsi[vsi->idx]->idx,
7458 pf->vsi[vsi->idx],
7459 pf->vsi[vsi->idx]->type,
7460 vsi->idx, vsi, vsi->type);
7461 goto unlock_vsi;
7462 }
7463
b40c82e6 7464 /* updates the PF for this cleared vsi */
41c445ff
JB		 7465 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7466 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7467
bc7d338f 7468 i40e_vsi_free_arrays(vsi, true);
28c5869f 7469 i40e_clear_rss_config_user(vsi);
493fb300 7470
41c445ff
JB		 7471 pf->vsi[vsi->idx] = NULL;
7472 if (vsi->idx < pf->next_vsi)
7473 pf->next_vsi = vsi->idx;
7474
7475unlock_vsi:
7476 mutex_unlock(&pf->switch_mutex);
7477free_vsi:
7478 kfree(vsi);
7479
7480 return 0;
7481}
7482
9f65e15b
AD		 7483/**
7484 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7485 * @vsi: the VSI being cleaned
7486 **/
be1d5eea 7487static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7488{
7489 int i;
7490
8e9dca53 7491 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7492 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7493 kfree_rcu(vsi->tx_rings[i], rcu);
7494 vsi->tx_rings[i] = NULL;
7495 vsi->rx_rings[i] = NULL;
7496 }
be1d5eea 7497 }
9f65e15b
AD		 7498}
7499
41c445ff
JB		 7500/**
7501 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7502 * @vsi: the VSI being configured
7503 **/
7504static int i40e_alloc_rings(struct i40e_vsi *vsi)
7505{
e7046ee1 7506 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7507 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7508 int i;
7509
41c445ff 7510 /* Set basic values in the rings to be used later during open() */
d7397644 7511 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7512 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7513 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7514 if (!tx_ring)
7515 goto err_out;
41c445ff
JB		 7516
7517 tx_ring->queue_index = i;
7518 tx_ring->reg_idx = vsi->base_queue + i;
7519 tx_ring->ring_active = false;
7520 tx_ring->vsi = vsi;
7521 tx_ring->netdev = vsi->netdev;
7522 tx_ring->dev = &pf->pdev->dev;
7523 tx_ring->count = vsi->num_desc;
7524 tx_ring->size = 0;
7525 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7526 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7527 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
a75e8005 7528 tx_ring->tx_itr_setting = pf->tx_itr_default;
9f65e15b 7529 vsi->tx_rings[i] = tx_ring;
41c445ff 7530
9f65e15b 7531 rx_ring = &tx_ring[1];
41c445ff
JB		 7532 rx_ring->queue_index = i;
7533 rx_ring->reg_idx = vsi->base_queue + i;
7534 rx_ring->ring_active = false;
7535 rx_ring->vsi = vsi;
7536 rx_ring->netdev = vsi->netdev;
7537 rx_ring->dev = &pf->pdev->dev;
7538 rx_ring->count = vsi->num_desc;
7539 rx_ring->size = 0;
7540 rx_ring->dcb_tc = 0;
a75e8005 7541 rx_ring->rx_itr_setting = pf->rx_itr_default;
9f65e15b 7542 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7543 }
7544
7545 return 0;
9f65e15b
AD		 7546
7547err_out:
7548 i40e_vsi_clear_rings(vsi);
7549 return -ENOMEM;
41c445ff
JB		 7550}
7551
7552/**
7553 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7554 * @pf: board private structure
7555 * @vectors: the number of MSI-X vectors to request
7556 *
7557 * Returns the number of vectors reserved, or error
7558 **/
7559static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7560{
7b37f376
AG		 7561 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7562 I40E_MIN_MSIX, vectors);
7563 if (vectors < 0) {
41c445ff 7564 dev_info(&pf->pdev->dev,
7b37f376 7565 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7566 vectors = 0;
7567 }
7568
7569 return vectors;
7570}
7571
7572/**
7573 * i40e_init_msix - Setup the MSIX capability
7574 * @pf: board private structure
7575 *
7576 * Work with the OS to set up the MSIX vectors needed.
7577 *
3b444399 7578 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7579 **/
7580static int i40e_init_msix(struct i40e_pf *pf)
7581{
41c445ff 7582 struct i40e_hw *hw = &pf->hw;
1e200e4a 7583 int vectors_left;
41c445ff 7584 int v_budget, i;
3b444399 7585 int v_actual;
e3219ce6 7586 int iwarp_requested = 0;
41c445ff
JB		 7587
7588 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7589 return -ENODEV;
7590
7591 /* The number of vectors we'll request will be comprised of:
7592 * - Add 1 for "other" cause for Admin Queue events, etc.
7593 * - The number of LAN queue pairs
f8ff1464
ASJ		 7594 * - Queues being used for RSS.
7595 * We don't need as many as max_rss_size vectors.
7596 * use rss_size instead in the calculation since that
7597 * is governed by number of cpus in the system.
7598 * - assumes symmetric Tx/Rx pairing
41c445ff 7599 * - The number of VMDq pairs
e3219ce6 7600 * - The CPU count within the NUMA node if iWARP is enabled
38e00438
VD		 7601#ifdef I40E_FCOE
7602 * - The number of FCOE qps.
7603#endif
41c445ff
JB		 7604 * Once we count this up, try the request.
7605 *
7606 * If we can't get what we want, we'll simplify to nearly nothing
7607 * and try again. If that still fails, we punt.
7608 */
1e200e4a
SN		 7609 vectors_left = hw->func_caps.num_msix_vectors;
7610 v_budget = 0;
7611
7612 /* reserve one vector for miscellaneous handler */
7613 if (vectors_left) {
7614 v_budget++;
7615 vectors_left--;
7616 }
7617
7618 /* reserve vectors for the main PF traffic queues */
7619 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7620 vectors_left -= pf->num_lan_msix;
7621 v_budget += pf->num_lan_msix;
7622
7623 /* reserve one vector for sideband flow director */
7624 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7625 if (vectors_left) {
a70e407f 7626 pf->num_fdsb_msix = 1;
1e200e4a
SN		 7627 v_budget++;
7628 vectors_left--;
7629 } else {
a70e407f 7630 pf->num_fdsb_msix = 0;
1e200e4a
SN		 7631 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7632 }
7633 }
83840e4b 7634
38e00438 7635#ifdef I40E_FCOE
1e200e4a 7636 /* can we reserve enough for FCoE? */
38e00438 7637 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7638 if (!vectors_left)
7639 pf->num_fcoe_msix = 0;
7640 else if (vectors_left >= pf->num_fcoe_qps)
7641 pf->num_fcoe_msix = pf->num_fcoe_qps;
7642 else
7643 pf->num_fcoe_msix = 1;
38e00438 7644 v_budget += pf->num_fcoe_msix;
1e200e4a 7645 vectors_left -= pf->num_fcoe_msix;
38e00438 7646 }
1e200e4a 7647
38e00438 7648#endif
e3219ce6
ASJ		 7649 /* can we reserve enough for iWARP? */
7650 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7651 if (!vectors_left)
7652 pf->num_iwarp_msix = 0;
7653 else if (vectors_left < pf->num_iwarp_msix)
7654 pf->num_iwarp_msix = 1;
7655 v_budget += pf->num_iwarp_msix;
7656 vectors_left -= pf->num_iwarp_msix;
7657 }
7658
1e200e4a
SN		 7659 /* any vectors left over go for VMDq support */
7660 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7661 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7662 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7663
7664 /* if we're short on vectors for what's desired, we limit
7665 * the queues per vmdq. If this is still more than are
7666 * available, the user will need to change the number of
7667 * queues/vectors used by the PF later with the ethtool
7668 * channels command
7669 */
7670 if (vmdq_vecs < vmdq_vecs_wanted)
7671 pf->num_vmdq_qps = 1;
7672 pf->num_vmdq_msix = pf->num_vmdq_qps;
7673
7674 v_budget += vmdq_vecs;
7675 vectors_left -= vmdq_vecs;
7676 }
41c445ff
JB		 7677
7678 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7679 GFP_KERNEL);
7680 if (!pf->msix_entries)
7681 return -ENOMEM;
7682
7683 for (i = 0; i < v_budget; i++)
7684 pf->msix_entries[i].entry = i;
3b444399 7685 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7686
3b444399 7687 if (v_actual != v_budget) {
a34977ba
ASJ		 7688 /* If we have limited resources, we will start with no vectors
7689 * for the special features and then allocate vectors to some
7690 * of these features based on the policy and at the end disable
7691 * the features that did not get any vectors.
7692 */
e3219ce6
ASJ		 7693 iwarp_requested = pf->num_iwarp_msix;
7694 pf->num_iwarp_msix = 0;
38e00438
VD		 7695#ifdef I40E_FCOE
7696 pf->num_fcoe_qps = 0;
7697 pf->num_fcoe_msix = 0;
7698#endif
a34977ba
ASJ		 7699 pf->num_vmdq_msix = 0;
7700 }
7701
3b444399 7702 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7703 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7704 kfree(pf->msix_entries);
7705 pf->msix_entries = NULL;
7706 return -ENODEV;
7707
3b444399 7708 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7709 /* Adjust for minimal MSIX use */
41c445ff
JB		 7710 pf->num_vmdq_vsis = 0;
7711 pf->num_vmdq_qps = 0;
41c445ff
JB		 7712 pf->num_lan_qps = 1;
7713 pf->num_lan_msix = 1;
7714
3b444399
SN		 7715 } else if (v_actual != v_budget) {
7716 int vec;
7717
a34977ba 7718 /* reserve the misc vector */
3b444399 7719 vec = v_actual - 1;
a34977ba 7720
41c445ff
JB		 7721 /* Scale vector usage down */
7722 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7723 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7724 pf->num_vmdq_qps = 1;
7725 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7726
7727 /* partition out the remaining vectors */
7728 switch (vec) {
7729 case 2:
41c445ff
JB		 7730 pf->num_lan_msix = 1;
7731 break;
7732 case 3:
e3219ce6
ASJ		 7733 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7734 pf->num_lan_msix = 1;
7735 pf->num_iwarp_msix = 1;
7736 } else {
7737 pf->num_lan_msix = 2;
7738 }
38e00438
VD		 7739#ifdef I40E_FCOE
7740 /* give one vector to FCoE */
7741 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7742 pf->num_lan_msix = 1;
7743 pf->num_fcoe_msix = 1;
7744 }
38e00438 7745#endif
41c445ff
JB		 7746 break;
7747 default:
e3219ce6
ASJ		 7748 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7749 pf->num_iwarp_msix = min_t(int, (vec / 3),
7750 iwarp_requested);
7751 pf->num_vmdq_vsis = min_t(int, (vec / 3),
7752 I40E_DEFAULT_NUM_VMDQ_VSI);
7753 } else {
7754 pf->num_vmdq_vsis = min_t(int, (vec / 2),
7755 I40E_DEFAULT_NUM_VMDQ_VSI);
7756 }
7757 pf->num_lan_msix = min_t(int,
7758 (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)),
7759 pf->num_lan_msix);
38e00438
VD		 7760#ifdef I40E_FCOE
7761 /* give one vector to FCoE */
7762 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7763 pf->num_fcoe_msix = 1;
7764 vec--;
7765 }
7766#endif
41c445ff
JB		 7767 break;
7768 }
7769 }
7770
a34977ba
ASJ		 7771 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7772 (pf->num_vmdq_msix == 0)) {
7773 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7774 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7775 }
e3219ce6
ASJ		 7776
7777 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
7778 (pf->num_iwarp_msix == 0)) {
7779 dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n");
7780 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
7781 }
38e00438
VD		 7782#ifdef I40E_FCOE
7783
7784 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7785 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7786 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7787 }
7788#endif
3b444399 7789 return v_actual;
41c445ff
JB		 7790}
7791
493fb300 7792/**
90e04070 7793 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7794 * @vsi: the VSI being configured
7795 * @v_idx: index of the vector in the vsi struct
7f6c5539 7796 * @cpu: cpu to be used on affinity_mask
493fb300
AD		 7797 *
7798 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7799 **/
7f6c5539 7800static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx, int cpu)
493fb300
AD		 7801{
7802 struct i40e_q_vector *q_vector;
7803
7804 /* allocate q_vector */
7805 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7806 if (!q_vector)
7807 return -ENOMEM;
7808
7809 q_vector->vsi = vsi;
7810 q_vector->v_idx = v_idx;
7f6c5539
GP		 7811 cpumask_set_cpu(cpu, &q_vector->affinity_mask);
7812
493fb300
AD		 7813 if (vsi->netdev)
7814 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7815 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7816
cd0b6fa6
AD		 7817 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7818 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7819
493fb300
AD		 7820 /* tie q_vector and vsi together */
7821 vsi->q_vectors[v_idx] = q_vector;
7822
7823 return 0;
7824}
7825
41c445ff 7826/**
90e04070 7827 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7828 * @vsi: the VSI being configured
7829 *
7830 * We allocate one q_vector per queue interrupt. If allocation fails we
7831 * return -ENOMEM.
7832 **/
90e04070 7833static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7834{
7835 struct i40e_pf *pf = vsi->back;
7f6c5539 7836 int err, v_idx, num_q_vectors, current_cpu;
41c445ff
JB		 7837
7838 /* if not MSIX, give the one vector only to the LAN VSI */
7839 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7840 num_q_vectors = vsi->num_q_vectors;
7841 else if (vsi == pf->vsi[pf->lan_vsi])
7842 num_q_vectors = 1;
7843 else
7844 return -EINVAL;
7845
7f6c5539
GP		 7846 current_cpu = cpumask_first(cpu_online_mask);
7847
41c445ff 7848 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
7f6c5539 7849 err = i40e_vsi_alloc_q_vector(vsi, v_idx, current_cpu);
493fb300
AD		 7850 if (err)
7851 goto err_out;
7f6c5539
GP		 7852 current_cpu = cpumask_next(current_cpu, cpu_online_mask);
7853 if (unlikely(current_cpu >= nr_cpu_ids))
7854 current_cpu = cpumask_first(cpu_online_mask);
41c445ff
JB		 7855 }
7856
7857 return 0;
493fb300
AD		 7858
7859err_out:
7860 while (v_idx--)
7861 i40e_free_q_vector(vsi, v_idx);
7862
7863 return err;
41c445ff
JB		 7864}
7865
7866/**
7867 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7868 * @pf: board private structure to initialize
7869 **/
c1147280 7870static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7871{
3b444399
SN		 7872 int vectors = 0;
7873 ssize_t size;
41c445ff
JB		 7874
7875 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7876 vectors = i40e_init_msix(pf);
7877 if (vectors < 0) {
60ea5f83 7878 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
e3219ce6 7879 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 7880#ifdef I40E_FCOE
7881 I40E_FLAG_FCOE_ENABLED |
7882#endif
60ea5f83 7883 I40E_FLAG_RSS_ENABLED |
4d9b6043 7884 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7885 I40E_FLAG_SRIOV_ENABLED |
7886 I40E_FLAG_FD_SB_ENABLED |
7887 I40E_FLAG_FD_ATR_ENABLED |
7888 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7889
7890 /* rework the queue expectations without MSIX */
7891 i40e_determine_queue_usage(pf);
7892 }
7893 }
7894
7895 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7896 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7897 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7898 vectors = pci_enable_msi(pf->pdev);
7899 if (vectors < 0) {
7900 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7901 vectors);
41c445ff
JB		 7902 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7903 }
3b444399 7904 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7905 }
7906
958a3e3b 7907 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7908 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7909
3b444399
SN		 7910 /* set up vector assignment tracking */
7911 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7912 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7913 if (!pf->irq_pile) {
7914 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7915 return -ENOMEM;
7916 }
3b444399
SN		 7917 pf->irq_pile->num_entries = vectors;
7918 pf->irq_pile->search_hint = 0;
7919
c1147280 7920 /* track first vector for misc interrupts, ignore return */
3b444399 7921 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7922
7923 return 0;
41c445ff
JB		 7924}
7925
7926/**
7927 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7928 * @pf: board private structure
7929 *
7930 * This sets up the handler for MSIX 0, which is used to manage the
7931 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7932 * when in MSI or Legacy interrupt mode.
7933 **/
7934static int i40e_setup_misc_vector(struct i40e_pf *pf)
7935{
7936 struct i40e_hw *hw = &pf->hw;
7937 int err = 0;
7938
7939 /* Only request the irq if this is the first time through, and
7940 * not when we're rebuilding after a Reset
7941 */
7942 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7943 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7944 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7945 if (err) {
7946 dev_info(&pf->pdev->dev,
77fa28be 7947 "request_irq for %s failed: %d\n",
b294ac70 7948 pf->int_name, err);
41c445ff
JB		 7949 return -EFAULT;
7950 }
7951 }
7952
ab437b5a 7953 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7954
7955 /* associate no queues to the misc vector */
7956 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7957 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7958
7959 i40e_flush(hw);
7960
40d72a50 7961 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 7962
7963 return err;
7964}
7965
7966/**
e25d00b8
ASJ		 7967 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7968 * @vsi: vsi structure
7969 * @seed: RSS hash seed
7970 **/
e69ff813
HZ		 7971static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7972 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7973{
7974 struct i40e_aqc_get_set_rss_key_data rss_key;
7975 struct i40e_pf *pf = vsi->back;
7976 struct i40e_hw *hw = &pf->hw;
7977 bool pf_lut = false;
7978 u8 *rss_lut;
7979 int ret, i;
7980
e25d00b8
ASJ		 7981 memcpy(&rss_key, seed, sizeof(rss_key));
7982
7983 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7984 if (!rss_lut)
7985 return -ENOMEM;
7986
7987 /* Populate the LUT with max no. of queues in round robin fashion */
7988 for (i = 0; i < vsi->rss_table_size; i++)
7989 rss_lut[i] = i % vsi->rss_size;
7990
7991 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7992 if (ret) {
7993 dev_info(&pf->pdev->dev,
7994 "Cannot set RSS key, err %s aq_err %s\n",
7995 i40e_stat_str(&pf->hw, ret),
7996 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7997 goto config_rss_aq_out;
e25d00b8
ASJ		 7998 }
7999
8000 if (vsi->type == I40E_VSI_MAIN)
8001 pf_lut = true;
8002
8003 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
8004 vsi->rss_table_size);
8005 if (ret)
8006 dev_info(&pf->pdev->dev,
8007 "Cannot set RSS lut, err %s aq_err %s\n",
8008 i40e_stat_str(&pf->hw, ret),
8009 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
8010
126b63d9
AS		 8011config_rss_aq_out:
8012 kfree(rss_lut);
e25d00b8
ASJ		 8013 return ret;
8014}
8015
8016/**
8017 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
8018 * @vsi: VSI structure
8019 **/
8020static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
8021{
8022 u8 seed[I40E_HKEY_ARRAY_SIZE];
8023 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 8024 u8 *lut;
8025 int ret;
8026
8027 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
8028 return 0;
8029
8030 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8031 if (!lut)
8032 return -ENOMEM;
e25d00b8 8033
e69ff813 8034 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 8035 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 8036 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 8037 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
8038 kfree(lut);
e25d00b8 8039
e69ff813 8040 return ret;
e25d00b8
ASJ		 8041}
8042
95a73780
ASJ		 8043/**
8044 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
8045 * @vsi: Pointer to vsi structure
8046 * @seed: Buffter to store the hash keys
8047 * @lut: Buffer to store the lookup table entries
8048 * @lut_size: Size of buffer to store the lookup table entries
8049 *
8050 * Return 0 on success, negative on failure
8051 */
8052static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
8053 u8 *lut, u16 lut_size)
8054{
8055 struct i40e_pf *pf = vsi->back;
8056 struct i40e_hw *hw = &pf->hw;
8057 int ret = 0;
8058
8059 if (seed) {
8060 ret = i40e_aq_get_rss_key(hw, vsi->id,
8061 (struct i40e_aqc_get_set_rss_key_data *)seed);
8062 if (ret) {
8063 dev_info(&pf->pdev->dev,
8064 "Cannot get RSS key, err %s aq_err %s\n",
8065 i40e_stat_str(&pf->hw, ret),
8066 i40e_aq_str(&pf->hw,
8067 pf->hw.aq.asq_last_status));
8068 return ret;
8069 }
8070 }
8071
8072 if (lut) {
8073 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
8074
8075 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
8076 if (ret) {
8077 dev_info(&pf->pdev->dev,
8078 "Cannot get RSS lut, err %s aq_err %s\n",
8079 i40e_stat_str(&pf->hw, ret),
8080 i40e_aq_str(&pf->hw,
8081 pf->hw.aq.asq_last_status));
8082 return ret;
8083 }
8084 }
8085
8086 return ret;
8087}
8088
e25d00b8 8089/**
043dd650 8090 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 8091 * @vsi: Pointer to vsi structure
e25d00b8 8092 * @seed: RSS hash seed
e69ff813
HZ		 8093 * @lut: Lookup table
8094 * @lut_size: Lookup table size
8095 *
8096 * Returns 0 on success, negative on failure
41c445ff 8097 **/
e69ff813
HZ		 8098static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
8099 const u8 *lut, u16 lut_size)
41c445ff 8100{
e69ff813 8101 struct i40e_pf *pf = vsi->back;
4617e8c0 8102 struct i40e_hw *hw = &pf->hw;
c4e1868c 8103 u16 vf_id = vsi->vf_id;
e69ff813 8104 u8 i;
41c445ff 8105
e25d00b8 8106 /* Fill out hash function seed */
e69ff813
HZ		 8107 if (seed) {
8108 u32 *seed_dw = (u32 *)seed;
8109
c4e1868c
MW		 8110 if (vsi->type == I40E_VSI_MAIN) {
8111 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8112 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i),
8113 seed_dw[i]);
8114 } else if (vsi->type == I40E_VSI_SRIOV) {
8115 for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++)
8116 i40e_write_rx_ctl(hw,
8117 I40E_VFQF_HKEY1(i, vf_id),
8118 seed_dw[i]);
8119 } else {
8120 dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n");
8121 }
e69ff813
HZ		 8122 }
8123
8124 if (lut) {
8125 u32 *lut_dw = (u32 *)lut;
8126
c4e1868c
MW		 8127 if (vsi->type == I40E_VSI_MAIN) {
8128 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8129 return -EINVAL;
8130 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8131 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
8132 } else if (vsi->type == I40E_VSI_SRIOV) {
8133 if (lut_size != I40E_VF_HLUT_ARRAY_SIZE)
8134 return -EINVAL;
8135 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++)
8136 i40e_write_rx_ctl(hw,
8137 I40E_VFQF_HLUT1(i, vf_id),
8138 lut_dw[i]);
8139 } else {
8140 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n");
8141 }
e25d00b8
ASJ		 8142 }
8143 i40e_flush(hw);
8144
8145 return 0;
8146}
8147
043dd650
HZ		 8148/**
8149 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
8150 * @vsi: Pointer to VSI structure
8151 * @seed: Buffer to store the keys
8152 * @lut: Buffer to store the lookup table entries
8153 * @lut_size: Size of buffer to store the lookup table entries
8154 *
8155 * Returns 0 on success, negative on failure
8156 */
8157static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
8158 u8 *lut, u16 lut_size)
8159{
8160 struct i40e_pf *pf = vsi->back;
8161 struct i40e_hw *hw = &pf->hw;
8162 u16 i;
8163
8164 if (seed) {
8165 u32 *seed_dw = (u32 *)seed;
8166
8167 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
272cdaf2 8168 seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
043dd650
HZ		 8169 }
8170 if (lut) {
8171 u32 *lut_dw = (u32 *)lut;
8172
8173 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8174 return -EINVAL;
8175 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8176 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
8177 }
8178
8179 return 0;
8180}
8181
8182/**
8183 * i40e_config_rss - Configure RSS keys and lut
8184 * @vsi: Pointer to VSI structure
8185 * @seed: RSS hash seed
8186 * @lut: Lookup table
8187 * @lut_size: Lookup table size
8188 *
8189 * Returns 0 on success, negative on failure
8190 */
8191int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8192{
8193 struct i40e_pf *pf = vsi->back;
8194
8195 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8196 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8197 else
8198 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8199}
8200
8201/**
8202 * i40e_get_rss - Get RSS keys and lut
8203 * @vsi: Pointer to VSI structure
8204 * @seed: Buffer to store the keys
8205 * @lut: Buffer to store the lookup table entries
8206 * lut_size: Size of buffer to store the lookup table entries
8207 *
8208 * Returns 0 on success, negative on failure
8209 */
8210int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8211{
95a73780
ASJ		 8212 struct i40e_pf *pf = vsi->back;
8213
8214 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8215 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
8216 else
8217 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
043dd650
HZ		 8218}
8219
e69ff813
HZ		 8220/**
8221 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8222 * @pf: Pointer to board private structure
8223 * @lut: Lookup table
8224 * @rss_table_size: Lookup table size
8225 * @rss_size: Range of queue number for hashing
8226 */
8227static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8228 u16 rss_table_size, u16 rss_size)
8229{
8230 u16 i;
8231
8232 for (i = 0; i < rss_table_size; i++)
8233 lut[i] = i % rss_size;
8234}
8235
e25d00b8 8236/**
043dd650 8237 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8238 * @pf: board private structure
8239 **/
043dd650 8240static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8241{
8242 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8243 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8244 u8 *lut;
e25d00b8
ASJ		 8245 struct i40e_hw *hw = &pf->hw;
8246 u32 reg_val;
8247 u64 hena;
e69ff813 8248 int ret;
e25d00b8 8249
41c445ff 8250 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
272cdaf2
SN		 8251 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
8252 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8253 hena |= i40e_pf_get_default_rss_hena(pf);
8254
272cdaf2
SN		 8255 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
8256 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
41c445ff 8257
e25d00b8 8258 /* Determine the RSS table size based on the hardware capabilities */
272cdaf2 8259 reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8260 reg_val = (pf->rss_table_size == 512) ?
8261 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8262 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
272cdaf2 8263 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
e157ea30 8264
28c5869f
HZ		 8265 /* Determine the RSS size of the VSI */
8266 if (!vsi->rss_size)
acd65448
HZ		 8267 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8268 vsi->num_queue_pairs);
28c5869f 8269
e69ff813
HZ		 8270 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8271 if (!lut)
8272 return -ENOMEM;
8273
28c5869f
HZ		 8274 /* Use user configured lut if there is one, otherwise use default */
8275 if (vsi->rss_lut_user)
8276 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8277 else
8278 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8279
28c5869f
HZ		 8280 /* Use user configured hash key if there is one, otherwise
8281 * use default.
8282 */
8283 if (vsi->rss_hkey_user)
8284 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8285 else
8286 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8287 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8288 kfree(lut);
8289
8290 return ret;
41c445ff
JB		 8291}
8292
f8ff1464
ASJ		 8293/**
8294 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8295 * @pf: board private structure
8296 * @queue_count: the requested queue count for rss.
8297 *
8298 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8299 * count which may be different from the requested queue count.
8300 **/
8301int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8302{
9a3bd2f1
ASJ		 8303 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8304 int new_rss_size;
8305
f8ff1464
ASJ		 8306 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8307 return 0;
8308
9a3bd2f1 8309 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8310
9a3bd2f1
ASJ		 8311 if (queue_count != vsi->num_queue_pairs) {
8312 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8313 i40e_prep_for_reset(pf);
8314
acd65448 8315 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8316
8317 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8318
8319 /* Discard the user configured hash keys and lut, if less
8320 * queues are enabled.
8321 */
8322 if (queue_count < vsi->rss_size) {
8323 i40e_clear_rss_config_user(vsi);
8324 dev_dbg(&pf->pdev->dev,
8325 "discard user configured hash keys and lut\n");
8326 }
8327
8328 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8329 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8330 vsi->num_queue_pairs);
28c5869f 8331
043dd650 8332 i40e_pf_config_rss(pf);
f8ff1464 8333 }
e36b0b11
HZ		 8334 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8335 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8336 return pf->alloc_rss_size;
f8ff1464
ASJ		 8337}
8338
f4492db1
GR		 8339/**
8340 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8341 * @pf: board private structure
8342 **/
8343i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8344{
8345 i40e_status status;
8346 bool min_valid, max_valid;
8347 u32 max_bw, min_bw;
8348
8349 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8350 &min_valid, &max_valid);
8351
8352 if (!status) {
8353 if (min_valid)
8354 pf->npar_min_bw = min_bw;
8355 if (max_valid)
8356 pf->npar_max_bw = max_bw;
8357 }
8358
8359 return status;
8360}
8361
8362/**
8363 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8364 * @pf: board private structure
8365 **/
8366i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8367{
8368 struct i40e_aqc_configure_partition_bw_data bw_data;
8369 i40e_status status;
8370
b40c82e6 8371 /* Set the valid bit for this PF */
41a1d04b 8372 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8373 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8374 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8375
8376 /* Set the new bandwidths */
8377 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8378
8379 return status;
8380}
8381
8382/**
8383 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8384 * @pf: board private structure
8385 **/
8386i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8387{
8388 /* Commit temporary BW setting to permanent NVM image */
8389 enum i40e_admin_queue_err last_aq_status;
8390 i40e_status ret;
8391 u16 nvm_word;
8392
8393 if (pf->hw.partition_id != 1) {
8394 dev_info(&pf->pdev->dev,
8395 "Commit BW only works on partition 1! This is partition %d",
8396 pf->hw.partition_id);
8397 ret = I40E_NOT_SUPPORTED;
8398 goto bw_commit_out;
8399 }
8400
8401 /* Acquire NVM for read access */
8402 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8403 last_aq_status = pf->hw.aq.asq_last_status;
8404 if (ret) {
8405 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8406 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8407 i40e_stat_str(&pf->hw, ret),
8408 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8409 goto bw_commit_out;
8410 }
8411
8412 /* Read word 0x10 of NVM - SW compatibility word 1 */
8413 ret = i40e_aq_read_nvm(&pf->hw,
8414 I40E_SR_NVM_CONTROL_WORD,
8415 0x10, sizeof(nvm_word), &nvm_word,
8416 false, NULL);
8417 /* Save off last admin queue command status before releasing
8418 * the NVM
8419 */
8420 last_aq_status = pf->hw.aq.asq_last_status;
8421 i40e_release_nvm(&pf->hw);
8422 if (ret) {
f1c7e72e
SN		 8423 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8424 i40e_stat_str(&pf->hw, ret),
8425 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8426 goto bw_commit_out;
8427 }
8428
8429 /* Wait a bit for NVM release to complete */
8430 msleep(50);
8431
8432 /* Acquire NVM for write access */
8433 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8434 last_aq_status = pf->hw.aq.asq_last_status;
8435 if (ret) {
8436 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8437 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8438 i40e_stat_str(&pf->hw, ret),
8439 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8440 goto bw_commit_out;
8441 }
8442 /* Write it back out unchanged to initiate update NVM,
8443 * which will force a write of the shadow (alt) RAM to
8444 * the NVM - thus storing the bandwidth values permanently.
8445 */
8446 ret = i40e_aq_update_nvm(&pf->hw,
8447 I40E_SR_NVM_CONTROL_WORD,
8448 0x10, sizeof(nvm_word),
8449 &nvm_word, true, NULL);
8450 /* Save off last admin queue command status before releasing
8451 * the NVM
8452 */
8453 last_aq_status = pf->hw.aq.asq_last_status;
8454 i40e_release_nvm(&pf->hw);
8455 if (ret)
8456 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8457 "BW settings NOT SAVED, err %s aq_err %s\n",
8458 i40e_stat_str(&pf->hw, ret),
8459 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8460bw_commit_out:
8461
8462 return ret;
8463}
8464
41c445ff
JB		 8465/**
8466 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8467 * @pf: board private structure to initialize
8468 *
8469 * i40e_sw_init initializes the Adapter private data structure.
8470 * Fields are initialized based on PCI device information and
8471 * OS network device settings (MTU size).
8472 **/
8473static int i40e_sw_init(struct i40e_pf *pf)
8474{
8475 int err = 0;
8476 int size;
8477
8478 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8479 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
8480 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8481 if (I40E_DEBUG_USER & debug)
8482 pf->hw.debug_mask = debug;
8483 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8484 I40E_DEFAULT_MSG_ENABLE);
8485 }
8486
8487 /* Set default capability flags */
8488 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8489 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 8490 I40E_FLAG_MSIX_ENABLED;
8491
ca99eb99
MW		 8492 /* Set default ITR */
8493 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8494 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8495
7134f9ce
JB		 8496 /* Depending on PF configurations, it is possible that the RSS
8497 * maximum might end up larger than the available queues
8498 */
41a1d04b 8499 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8500 pf->alloc_rss_size = 1;
5db4cb59 8501 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8502 pf->rss_size_max = min_t(int, pf->rss_size_max,
8503 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8504 if (pf->hw.func_caps.rss) {
8505 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8506 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8507 num_online_cpus());
41c445ff
JB		 8508 }
8509
2050bc65 8510 /* MFP mode enabled */
c78b953e 8511 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8512 pf->flags |= I40E_FLAG_MFP_ENABLED;
8513 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8514 if (i40e_get_npar_bw_setting(pf))
8515 dev_warn(&pf->pdev->dev,
8516 "Could not get NPAR bw settings\n");
8517 else
8518 dev_info(&pf->pdev->dev,
8519 "Min BW = %8.8x, Max BW = %8.8x\n",
8520 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8521 }
8522
cbf61325
ASJ		 8523 /* FW/NVM is not yet fixed in this regard */
8524 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8525 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8526 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8527 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8528 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8529 pf->hw.num_partitions > 1)
cbf61325 8530 dev_info(&pf->pdev->dev,
0b67584f 8531 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8532 else
8533 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8534 pf->fdir_pf_filter_count =
8535 pf->hw.func_caps.fd_filters_guaranteed;
8536 pf->hw.fdir_shared_filter_count =
8537 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8538 }
8539
f1bbad33 8540 if (i40e_is_mac_710(&pf->hw) &&
8eed76fa 8541 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
f1bbad33 8542 (pf->hw.aq.fw_maj_ver < 4))) {
8eed76fa 8543 pf->flags |= I40E_FLAG_RESTART_AUTONEG;
f1bbad33
NP		 8544 /* No DCB support for FW < v4.33 */
8545 pf->flags |= I40E_FLAG_NO_DCB_SUPPORT;
8546 }
8547
8548 /* Disable FW LLDP if FW < v4.3 */
8549 if (i40e_is_mac_710(&pf->hw) &&
8550 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
8551 (pf->hw.aq.fw_maj_ver < 4)))
8552 pf->flags |= I40E_FLAG_STOP_FW_LLDP;
8553
8554 /* Use the FW Set LLDP MIB API if FW > v4.40 */
8555 if (i40e_is_mac_710(&pf->hw) &&
8556 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
8557 (pf->hw.aq.fw_maj_ver >= 5)))
8558 pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB;
8eed76fa 8559
41c445ff 8560 if (pf->hw.func_caps.vmdq) {
41c445ff 8561 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8562 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8563 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8564 }
8565
e3219ce6
ASJ		 8566 if (pf->hw.func_caps.iwarp) {
8567 pf->flags |= I40E_FLAG_IWARP_ENABLED;
8568 /* IWARP needs one extra vector for CQP just like MISC.*/
8569 pf->num_iwarp_msix = (int)num_online_cpus() + 1;
8570 }
8571
38e00438 8572#ifdef I40E_FCOE
21364bcf 8573 i40e_init_pf_fcoe(pf);
38e00438
VD		 8574
8575#endif /* I40E_FCOE */
41c445ff 8576#ifdef CONFIG_PCI_IOV
ba252f13 8577 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8578 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8579 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8580 pf->num_req_vfs = min_t(int,
8581 pf->hw.func_caps.num_vfs,
8582 I40E_MAX_VF_COUNT);
8583 }
8584#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8585 if (pf->hw.mac.type == I40E_MAC_X722) {
8586 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8587 I40E_FLAG_128_QP_RSS_CAPABLE |
8588 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8589 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8590 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024 8591 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
8e2cc0e6 8592 I40E_FLAG_NO_PCI_LINK_CHECK |
f8db54cc 8593 I40E_FLAG_100M_SGMII_CAPABLE |
f1bbad33 8594 I40E_FLAG_USE_SET_LLDP_MIB |
6a899024 8595 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
a340c789
AS		 8596 } else if ((pf->hw.aq.api_maj_ver > 1) ||
8597 ((pf->hw.aq.api_maj_ver == 1) &&
8598 (pf->hw.aq.api_min_ver > 4))) {
8599 /* Supported in FW API version higher than 1.4 */
8600 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
72b74869
ASJ		 8601 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
8602 } else {
8603 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
d502ce01 8604 }
a340c789 8605
41c445ff
JB		 8606 pf->eeprom_version = 0xDEAD;
8607 pf->lan_veb = I40E_NO_VEB;
8608 pf->lan_vsi = I40E_NO_VSI;
8609
d1a8d275
ASJ		 8610 /* By default FW has this off for performance reasons */
8611 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8612
41c445ff
JB		 8613 /* set up queue assignment tracking */
8614 size = sizeof(struct i40e_lump_tracking)
8615 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8616 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8617 if (!pf->qp_pile) {
8618 err = -ENOMEM;
8619 goto sw_init_done;
8620 }
8621 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8622 pf->qp_pile->search_hint = 0;
8623
327fe04b
ASJ		 8624 pf->tx_timeout_recovery_level = 1;
8625
41c445ff
JB		 8626 mutex_init(&pf->switch_mutex);
8627
c668a12c
GR		 8628 /* If NPAR is enabled nudge the Tx scheduler */
8629 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8630 i40e_set_npar_bw_setting(pf);
8631
41c445ff
JB		 8632sw_init_done:
8633 return err;
8634}
8635
7c3c288b
ASJ		 8636/**
8637 * i40e_set_ntuple - set the ntuple feature flag and take action
8638 * @pf: board private structure to initialize
8639 * @features: the feature set that the stack is suggesting
8640 *
8641 * returns a bool to indicate if reset needs to happen
8642 **/
8643bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8644{
8645 bool need_reset = false;
8646
8647 /* Check if Flow Director n-tuple support was enabled or disabled. If
8648 * the state changed, we need to reset.
8649 */
8650 if (features & NETIF_F_NTUPLE) {
8651 /* Enable filters and mark for reset */
8652 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8653 need_reset = true;
a70e407f
TD		 8654 /* enable FD_SB only if there is MSI-X vector */
8655 if (pf->num_fdsb_msix > 0)
8656 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7c3c288b
ASJ		 8657 } else {
8658 /* turn off filters, mark for reset and clear SW filter list */
8659 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8660 need_reset = true;
8661 i40e_fdir_filter_exit(pf);
8662 }
8663 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8664 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8665 /* reset fd counters */
8666 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8667 pf->fdir_pf_active_filters = 0;
8668 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8669 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8670 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8671 /* if ATR was auto disabled it can be re-enabled. */
8672 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8673 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8674 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8675 }
8676 return need_reset;
8677}
8678
41c445ff
JB		 8679/**
8680 * i40e_set_features - set the netdev feature flags
8681 * @netdev: ptr to the netdev being adjusted
8682 * @features: the feature set that the stack is suggesting
8683 **/
8684static int i40e_set_features(struct net_device *netdev,
8685 netdev_features_t features)
8686{
8687 struct i40e_netdev_priv *np = netdev_priv(netdev);
8688 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8689 struct i40e_pf *pf = vsi->back;
8690 bool need_reset;
41c445ff
JB		 8691
8692 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8693 i40e_vlan_stripping_enable(vsi);
8694 else
8695 i40e_vlan_stripping_disable(vsi);
8696
7c3c288b
ASJ		 8697 need_reset = i40e_set_ntuple(pf, features);
8698
8699 if (need_reset)
41a1d04b 8700 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8701
41c445ff
JB		 8702 return 0;
8703}
8704
a1c9a9d9 8705/**
6a899024 8706 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8707 * @pf: board private structure
8708 * @port: The UDP port to look up
8709 *
8710 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8711 **/
6a899024 8712static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8713{
8714 u8 i;
8715
8716 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8717 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8718 return i;
8719 }
8720
8721 return i;
8722}
8723
8724/**
06a5f7f1 8725 * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up
a1c9a9d9 8726 * @netdev: This physical port's netdev
06a5f7f1 8727 * @ti: Tunnel endpoint information
a1c9a9d9 8728 **/
06a5f7f1
AD		 8729static void i40e_udp_tunnel_add(struct net_device *netdev,
8730 struct udp_tunnel_info *ti)
a1c9a9d9
JK		 8731{
8732 struct i40e_netdev_priv *np = netdev_priv(netdev);
8733 struct i40e_vsi *vsi = np->vsi;
8734 struct i40e_pf *pf = vsi->back;
06a5f7f1 8735 __be16 port = ti->port;
a1c9a9d9
JK		 8736 u8 next_idx;
8737 u8 idx;
8738
6a899024 8739 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8740
8741 /* Check if port already exists */
8742 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
06a5f7f1 8743 netdev_info(netdev, "port %d already offloaded\n",
c22c06c8 8744 ntohs(port));
a1c9a9d9
JK		 8745 return;
8746 }
8747
8748 /* Now check if there is space to add the new port */
6a899024 8749 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8750
8751 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
06a5f7f1 8752 netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n",
6a899024
SA		 8753 ntohs(port));
8754 return;
8755 }
8756
06a5f7f1
AD		 8757 switch (ti->type) {
8758 case UDP_TUNNEL_TYPE_VXLAN:
8759 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8760 break;
8761 case UDP_TUNNEL_TYPE_GENEVE:
8762 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8763 return;
8764 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8765 break;
8766 default:
6a899024
SA		 8767 return;
8768 }
8769
8770 /* New port: add it and mark its index in the bitmap */
8771 pf->udp_ports[next_idx].index = port;
6a899024
SA		 8772 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8773 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 8774}
8775
6a899024 8776/**
06a5f7f1 8777 * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away
6a899024 8778 * @netdev: This physical port's netdev
06a5f7f1 8779 * @ti: Tunnel endpoint information
6a899024 8780 **/
06a5f7f1
AD		 8781static void i40e_udp_tunnel_del(struct net_device *netdev,
8782 struct udp_tunnel_info *ti)
6a899024 8783{
6a899024
SA		 8784 struct i40e_netdev_priv *np = netdev_priv(netdev);
8785 struct i40e_vsi *vsi = np->vsi;
8786 struct i40e_pf *pf = vsi->back;
06a5f7f1 8787 __be16 port = ti->port;
6a899024
SA		 8788 u8 idx;
8789
6a899024
SA		 8790 idx = i40e_get_udp_port_idx(pf, port);
8791
8792 /* Check if port already exists */
06a5f7f1
AD		 8793 if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS)
8794 goto not_found;
6a899024 8795
06a5f7f1
AD		 8796 switch (ti->type) {
8797 case UDP_TUNNEL_TYPE_VXLAN:
8798 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN)
8799 goto not_found;
8800 break;
8801 case UDP_TUNNEL_TYPE_GENEVE:
8802 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE)
8803 goto not_found;
8804 break;
8805 default:
8806 goto not_found;
6a899024 8807 }
06a5f7f1
AD		 8808
8809 /* if port exists, set it to 0 (mark for deletion)
8810 * and make it pending
8811 */
8812 pf->udp_ports[idx].index = 0;
8813 pf->pending_udp_bitmap |= BIT_ULL(idx);
8814 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8815
8816 return;
8817not_found:
8818 netdev_warn(netdev, "UDP port %d was not found, not deleting\n",
8819 ntohs(port));
6a899024
SA		 8820}
8821
1f224ad2 8822static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8823 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8824{
8825 struct i40e_netdev_priv *np = netdev_priv(netdev);
8826 struct i40e_pf *pf = np->vsi->back;
8827 struct i40e_hw *hw = &pf->hw;
8828
8829 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8830 return -EOPNOTSUPP;
8831
8832 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8833 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8834
8835 return 0;
8836}
8837
2f90ade6
JB		 8838/**
8839 * i40e_ndo_fdb_add - add an entry to the hardware database
8840 * @ndm: the input from the stack
8841 * @tb: pointer to array of nladdr (unused)
8842 * @dev: the net device pointer
8843 * @addr: the MAC address entry being added
8844 * @flags: instructions from stack about fdb operation
8845 */
4ba0dea5
GR		 8846static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8847 struct net_device *dev,
f6f6424b 8848 const unsigned char *addr, u16 vid,
4ba0dea5 8849 u16 flags)
4ba0dea5
GR		 8850{
8851 struct i40e_netdev_priv *np = netdev_priv(dev);
8852 struct i40e_pf *pf = np->vsi->back;
8853 int err = 0;
8854
8855 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8856 return -EOPNOTSUPP;
8857
65891fea
OG		 8858 if (vid) {
8859 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8860 return -EINVAL;
8861 }
8862
4ba0dea5
GR		 8863 /* Hardware does not support aging addresses so if a
8864 * ndm_state is given only allow permanent addresses
8865 */
8866 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8867 netdev_info(dev, "FDB only supports static addresses\n");
8868 return -EINVAL;
8869 }
8870
8871 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8872 err = dev_uc_add_excl(dev, addr);
8873 else if (is_multicast_ether_addr(addr))
8874 err = dev_mc_add_excl(dev, addr);
8875 else
8876 err = -EINVAL;
8877
8878 /* Only return duplicate errors if NLM_F_EXCL is set */
8879 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8880 err = 0;
8881
8882 return err;
8883}
8884
51616018
NP		 8885/**
8886 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8887 * @dev: the netdev being configured
8888 * @nlh: RTNL message
8889 *
8890 * Inserts a new hardware bridge if not already created and
8891 * enables the bridging mode requested (VEB or VEPA). If the
8892 * hardware bridge has already been inserted and the request
8893 * is to change the mode then that requires a PF reset to
8894 * allow rebuild of the components with required hardware
8895 * bridge mode enabled.
8896 **/
8897static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8898 struct nlmsghdr *nlh,
8899 u16 flags)
51616018
NP		 8900{
8901 struct i40e_netdev_priv *np = netdev_priv(dev);
8902 struct i40e_vsi *vsi = np->vsi;
8903 struct i40e_pf *pf = vsi->back;
8904 struct i40e_veb *veb = NULL;
8905 struct nlattr *attr, *br_spec;
8906 int i, rem;
8907
8908 /* Only for PF VSI for now */
8909 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8910 return -EOPNOTSUPP;
8911
8912 /* Find the HW bridge for PF VSI */
8913 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8914 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8915 veb = pf->veb[i];
8916 }
8917
8918 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8919
8920 nla_for_each_nested(attr, br_spec, rem) {
8921 __u16 mode;
8922
8923 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8924 continue;
8925
8926 mode = nla_get_u16(attr);
8927 if ((mode != BRIDGE_MODE_VEPA) &&
8928 (mode != BRIDGE_MODE_VEB))
8929 return -EINVAL;
8930
8931 /* Insert a new HW bridge */
8932 if (!veb) {
8933 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8934 vsi->tc_config.enabled_tc);
8935 if (veb) {
8936 veb->bridge_mode = mode;
8937 i40e_config_bridge_mode(veb);
8938 } else {
8939 /* No Bridge HW offload available */
8940 return -ENOENT;
8941 }
8942 break;
8943 } else if (mode != veb->bridge_mode) {
8944 /* Existing HW bridge but different mode needs reset */
8945 veb->bridge_mode = mode;
fc60861e
ASJ		 8946 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8947 if (mode == BRIDGE_MODE_VEB)
8948 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8949 else
8950 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8951 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8952 break;
8953 }
8954 }
8955
8956 return 0;
8957}
8958
8959/**
8960 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8961 * @skb: skb buff
8962 * @pid: process id
8963 * @seq: RTNL message seq #
8964 * @dev: the netdev being configured
8965 * @filter_mask: unused
d4b2f9fe 8966 * @nlflags: netlink flags passed in
51616018
NP		 8967 *
8968 * Return the mode in which the hardware bridge is operating in
8969 * i.e VEB or VEPA.
8970 **/
51616018
NP		 8971static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8972 struct net_device *dev,
9f4ffc44
CW		 8973 u32 __always_unused filter_mask,
8974 int nlflags)
51616018
NP		 8975{
8976 struct i40e_netdev_priv *np = netdev_priv(dev);
8977 struct i40e_vsi *vsi = np->vsi;
8978 struct i40e_pf *pf = vsi->back;
8979 struct i40e_veb *veb = NULL;
8980 int i;
8981
8982 /* Only for PF VSI for now */
8983 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8984 return -EOPNOTSUPP;
8985
8986 /* Find the HW bridge for the PF VSI */
8987 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8988 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8989 veb = pf->veb[i];
8990 }
8991
8992 if (!veb)
8993 return 0;
8994
46c264da 8995 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8996 nlflags, 0, 0, filter_mask, NULL);
51616018 8997}
51616018 8998
6a899024
SA		 8999/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
9000 * inner mac plus all inner ethertypes.
9001 */
9002#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 9003/**
9004 * i40e_features_check - Validate encapsulated packet conforms to limits
9005 * @skb: skb buff
2bc11c63 9006 * @dev: This physical port's netdev
f44a75e2
JS		 9007 * @features: Offload features that the stack believes apply
9008 **/
9009static netdev_features_t i40e_features_check(struct sk_buff *skb,
9010 struct net_device *dev,
9011 netdev_features_t features)
9012{
9013 if (skb->encapsulation &&
6a899024 9014 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 9015 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 9016 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 9017
9018 return features;
9019}
9020
37a2973a 9021static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 9022 .ndo_open = i40e_open,
9023 .ndo_stop = i40e_close,
9024 .ndo_start_xmit = i40e_lan_xmit_frame,
9025 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
9026 .ndo_set_rx_mode = i40e_set_rx_mode,
9027 .ndo_validate_addr = eth_validate_addr,
9028 .ndo_set_mac_address = i40e_set_mac,
9029 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 9030 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 9031 .ndo_tx_timeout = i40e_tx_timeout,
9032 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
9033 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
9034#ifdef CONFIG_NET_POLL_CONTROLLER
9035 .ndo_poll_controller = i40e_netpoll,
9036#endif
e4c6734e 9037 .ndo_setup_tc = __i40e_setup_tc,
38e00438
VD		 9038#ifdef I40E_FCOE
9039 .ndo_fcoe_enable = i40e_fcoe_enable,
9040 .ndo_fcoe_disable = i40e_fcoe_disable,
9041#endif
41c445ff
JB		 9042 .ndo_set_features = i40e_set_features,
9043 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
9044 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 9045 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 9046 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 9047 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 9048 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
c3bbbd20 9049 .ndo_set_vf_trust = i40e_ndo_set_vf_trust,
06a5f7f1
AD		 9050 .ndo_udp_tunnel_add = i40e_udp_tunnel_add,
9051 .ndo_udp_tunnel_del = i40e_udp_tunnel_del,
1f224ad2 9052 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 9053 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 9054 .ndo_features_check = i40e_features_check,
51616018
NP		 9055 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
9056 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 9057};
9058
9059/**
9060 * i40e_config_netdev - Setup the netdev flags
9061 * @vsi: the VSI being configured
9062 *
9063 * Returns 0 on success, negative value on failure
9064 **/
9065static int i40e_config_netdev(struct i40e_vsi *vsi)
9066{
9067 struct i40e_pf *pf = vsi->back;
9068 struct i40e_hw *hw = &pf->hw;
9069 struct i40e_netdev_priv *np;
9070 struct net_device *netdev;
9071 u8 mac_addr[ETH_ALEN];
9072 int etherdev_size;
9073
9074 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 9075 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 9076 if (!netdev)
9077 return -ENOMEM;
9078
9079 vsi->netdev = netdev;
9080 np = netdev_priv(netdev);
9081 np->vsi = vsi;
9082
b0fe3306
AD		 9083 netdev->hw_enc_features |= NETIF_F_SG |
9084 NETIF_F_IP_CSUM |
9085 NETIF_F_IPV6_CSUM |
9086 NETIF_F_HIGHDMA |
9087 NETIF_F_SOFT_FEATURES |
9088 NETIF_F_TSO |
9089 NETIF_F_TSO_ECN |
9090 NETIF_F_TSO6 |
9091 NETIF_F_GSO_GRE |
1c7b4a23 9092 NETIF_F_GSO_GRE_CSUM |
7e13318d 9093 NETIF_F_GSO_IPXIP4 |
bf2d1df3 9094 NETIF_F_GSO_IPXIP6 |
b0fe3306
AD		 9095 NETIF_F_GSO_UDP_TUNNEL |
9096 NETIF_F_GSO_UDP_TUNNEL_CSUM |
1c7b4a23 9097 NETIF_F_GSO_PARTIAL |
b0fe3306
AD		 9098 NETIF_F_SCTP_CRC |
9099 NETIF_F_RXHASH |
9100 NETIF_F_RXCSUM |
5afdaaa0 9101 0;
41c445ff 9102
b0fe3306 9103 if (!(pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE))
1c7b4a23
AD		 9104 netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
9105
9106 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
b0fe3306
AD		 9107
9108 /* record features VLANs can make use of */
1c7b4a23
AD		 9109 netdev->vlan_features |= netdev->hw_enc_features |
9110 NETIF_F_TSO_MANGLEID;
41c445ff 9111
2e86a0b6 9112 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
b0fe3306
AD		 9113 netdev->hw_features |= NETIF_F_NTUPLE;
9114
9115 netdev->hw_features |= netdev->hw_enc_features |
9116 NETIF_F_HW_VLAN_CTAG_TX |
9117 NETIF_F_HW_VLAN_CTAG_RX;
2e86a0b6 9118
b0fe3306 9119 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
1c7b4a23 9120 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
41c445ff
JB		 9121
9122 if (vsi->type == I40E_VSI_MAIN) {
9123 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 9124 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 9125 /* The following steps are necessary to prevent reception
9126 * of tagged packets - some older NVM configurations load a
9127 * default a MAC-VLAN filter that accepts any tagged packet
9128 * which must be replaced by a normal filter.
8c27d42e 9129 */
c3c7ea27
MW		 9130 i40e_rm_default_mac_filter(vsi, mac_addr);
9131 spin_lock_bh(&vsi->mac_filter_list_lock);
9132 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, true);
9133 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9134 } else {
9135 /* relate the VSI_VMDQ name to the VSI_MAIN name */
9136 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
9137 pf->vsi[pf->lan_vsi]->netdev->name);
9138 random_ether_addr(mac_addr);
21659035
KP		 9139
9140 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 9141 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 9142 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9143 }
21659035 9144
9a173901
GR		 9145 ether_addr_copy(netdev->dev_addr, mac_addr);
9146 ether_addr_copy(netdev->perm_addr, mac_addr);
b0fe3306 9147
41c445ff
JB		 9148 netdev->priv_flags |= IFF_UNICAST_FLT;
9149 netdev->priv_flags |= IFF_SUPP_NOFCS;
9150 /* Setup netdev TC information */
9151 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9152
9153 netdev->netdev_ops = &i40e_netdev_ops;
9154 netdev->watchdog_timeo = 5 * HZ;
9155 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9156#ifdef I40E_FCOE
9157 i40e_fcoe_config_netdev(netdev, vsi);
9158#endif
41c445ff
JB		 9159
9160 return 0;
9161}
9162
9163/**
9164 * i40e_vsi_delete - Delete a VSI from the switch
9165 * @vsi: the VSI being removed
9166 *
9167 * Returns 0 on success, negative value on failure
9168 **/
9169static void i40e_vsi_delete(struct i40e_vsi *vsi)
9170{
9171 /* remove default VSI is not allowed */
9172 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9173 return;
9174
41c445ff 9175 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9176}
9177
51616018
NP		 9178/**
9179 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9180 * @vsi: the VSI being queried
9181 *
9182 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9183 **/
9184int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9185{
9186 struct i40e_veb *veb;
9187 struct i40e_pf *pf = vsi->back;
9188
9189 /* Uplink is not a bridge so default to VEB */
9190 if (vsi->veb_idx == I40E_NO_VEB)
9191 return 1;
9192
9193 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9194 if (!veb) {
9195 dev_info(&pf->pdev->dev,
9196 "There is no veb associated with the bridge\n");
9197 return -ENOENT;
9198 }
9199
51616018 9200 /* Uplink is a bridge in VEPA mode */
09603eaa 9201 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9202 return 0;
09603eaa
AA		 9203 } else {
9204 /* Uplink is a bridge in VEB mode */
9205 return 1;
9206 }
51616018 9207
09603eaa
AA		 9208 /* VEPA is now default bridge, so return 0 */
9209 return 0;
51616018
NP		 9210}
9211
41c445ff
JB		 9212/**
9213 * i40e_add_vsi - Add a VSI to the switch
9214 * @vsi: the VSI being configured
9215 *
9216 * This initializes a VSI context depending on the VSI type to be added and
9217 * passes it down to the add_vsi aq command.
9218 **/
9219static int i40e_add_vsi(struct i40e_vsi *vsi)
9220{
9221 int ret = -ENODEV;
f6bd0962 9222 i40e_status aq_ret = 0;
41c445ff
JB		 9223 struct i40e_pf *pf = vsi->back;
9224 struct i40e_hw *hw = &pf->hw;
9225 struct i40e_vsi_context ctxt;
21659035
KP		 9226 struct i40e_mac_filter *f, *ftmp;
9227
41c445ff
JB		 9228 u8 enabled_tc = 0x1; /* TC0 enabled */
9229 int f_count = 0;
9230
9231 memset(&ctxt, 0, sizeof(ctxt));
9232 switch (vsi->type) {
9233 case I40E_VSI_MAIN:
9234 /* The PF's main VSI is already setup as part of the
9235 * device initialization, so we'll not bother with
9236 * the add_vsi call, but we will retrieve the current
9237 * VSI context.
9238 */
9239 ctxt.seid = pf->main_vsi_seid;
9240 ctxt.pf_num = pf->hw.pf_id;
9241 ctxt.vf_num = 0;
9242 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9243 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9244 if (ret) {
9245 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9246 "couldn't get PF vsi config, err %s aq_err %s\n",
9247 i40e_stat_str(&pf->hw, ret),
9248 i40e_aq_str(&pf->hw,
9249 pf->hw.aq.asq_last_status));
41c445ff
JB		 9250 return -ENOENT;
9251 }
1a2f6248 9252 vsi->info = ctxt.info;
41c445ff
JB		 9253 vsi->info.valid_sections = 0;
9254
9255 vsi->seid = ctxt.seid;
9256 vsi->id = ctxt.vsi_number;
9257
9258 enabled_tc = i40e_pf_get_tc_map(pf);
9259
9260 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9261 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9262 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9263 memset(&ctxt, 0, sizeof(ctxt));
9264 ctxt.seid = pf->main_vsi_seid;
9265 ctxt.pf_num = pf->hw.pf_id;
9266 ctxt.vf_num = 0;
9267 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9268 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9269 if (ret) {
9270 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9271 "update vsi failed, err %s aq_err %s\n",
9272 i40e_stat_str(&pf->hw, ret),
9273 i40e_aq_str(&pf->hw,
9274 pf->hw.aq.asq_last_status));
41c445ff
JB		 9275 ret = -ENOENT;
9276 goto err;
9277 }
9278 /* update the local VSI info queue map */
9279 i40e_vsi_update_queue_map(vsi, &ctxt);
9280 vsi->info.valid_sections = 0;
9281 } else {
9282 /* Default/Main VSI is only enabled for TC0
9283 * reconfigure it to enable all TCs that are
9284 * available on the port in SFP mode.
63d7e5a4
NP		 9285 * For MFP case the iSCSI PF would use this
9286 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9287 */
9288 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9289 if (ret) {
9290 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9291 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9292 enabled_tc,
9293 i40e_stat_str(&pf->hw, ret),
9294 i40e_aq_str(&pf->hw,
9295 pf->hw.aq.asq_last_status));
41c445ff
JB		 9296 ret = -ENOENT;
9297 }
9298 }
9299 break;
9300
9301 case I40E_VSI_FDIR:
cbf61325
ASJ		 9302 ctxt.pf_num = hw->pf_id;
9303 ctxt.vf_num = 0;
9304 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9305 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9306 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9307 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9308 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9309 ctxt.info.valid_sections |=
fc60861e 9310 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9311 ctxt.info.switch_id =
fc60861e 9312 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9313 }
41c445ff 9314 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9315 break;
9316
9317 case I40E_VSI_VMDQ2:
9318 ctxt.pf_num = hw->pf_id;
9319 ctxt.vf_num = 0;
9320 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9321 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9322 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9323
41c445ff
JB		 9324 /* This VSI is connected to VEB so the switch_id
9325 * should be set to zero by default.
9326 */
51616018
NP		 9327 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9328 ctxt.info.valid_sections |=
9329 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9330 ctxt.info.switch_id =
9331 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9332 }
41c445ff
JB		 9333
9334 /* Setup the VSI tx/rx queue map for TC0 only for now */
9335 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9336 break;
9337
9338 case I40E_VSI_SRIOV:
9339 ctxt.pf_num = hw->pf_id;
9340 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9341 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9342 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9343 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9344
41c445ff
JB		 9345 /* This VSI is connected to VEB so the switch_id
9346 * should be set to zero by default.
9347 */
51616018
NP		 9348 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9349 ctxt.info.valid_sections |=
9350 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9351 ctxt.info.switch_id =
9352 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9353 }
41c445ff 9354
e3219ce6
ASJ		 9355 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
9356 ctxt.info.valid_sections |=
9357 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
9358 ctxt.info.queueing_opt_flags |=
4b28cdba
AS		 9359 (I40E_AQ_VSI_QUE_OPT_TCP_ENA |
9360 I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI);
e3219ce6
ASJ		 9361 }
9362
41c445ff
JB		 9363 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9364 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9365 if (pf->vf[vsi->vf_id].spoofchk) {
9366 ctxt.info.valid_sections |=
9367 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9368 ctxt.info.sec_flags |=
9369 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9370 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9371 }
41c445ff
JB		 9372 /* Setup the VSI tx/rx queue map for TC0 only for now */
9373 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9374 break;
9375
38e00438
VD		 9376#ifdef I40E_FCOE
9377 case I40E_VSI_FCOE:
9378 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9379 if (ret) {
9380 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9381 return ret;
9382 }
9383 break;
9384
9385#endif /* I40E_FCOE */
e3219ce6
ASJ		 9386 case I40E_VSI_IWARP:
9387 /* send down message to iWARP */
9388 break;
9389
41c445ff
JB		 9390 default:
9391 return -ENODEV;
9392 }
9393
9394 if (vsi->type != I40E_VSI_MAIN) {
9395 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9396 if (ret) {
9397 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9398 "add vsi failed, err %s aq_err %s\n",
9399 i40e_stat_str(&pf->hw, ret),
9400 i40e_aq_str(&pf->hw,
9401 pf->hw.aq.asq_last_status));
41c445ff
JB		 9402 ret = -ENOENT;
9403 goto err;
9404 }
1a2f6248 9405 vsi->info = ctxt.info;
41c445ff
JB		 9406 vsi->info.valid_sections = 0;
9407 vsi->seid = ctxt.seid;
9408 vsi->id = ctxt.vsi_number;
9409 }
f6bd0962
KP		 9410 /* Except FDIR VSI, for all othet VSI set the broadcast filter */
9411 if (vsi->type != I40E_VSI_FDIR) {
9412 aq_ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
9413 if (aq_ret) {
9414 ret = i40e_aq_rc_to_posix(aq_ret,
9415 hw->aq.asq_last_status);
9416 dev_info(&pf->pdev->dev,
9417 "set brdcast promisc failed, err %s, aq_err %s\n",
9418 i40e_stat_str(hw, aq_ret),
9419 i40e_aq_str(hw, hw->aq.asq_last_status));
9420 }
9421 }
41c445ff 9422
c3c7ea27
MW		 9423 vsi->active_filters = 0;
9424 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state);
21659035 9425 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9426 /* If macvlan filters already exist, force them to get loaded */
9427 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
c3c7ea27 9428 f->state = I40E_FILTER_NEW;
41c445ff 9429 f_count++;
21659035
KP		 9430 }
9431 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9432
41c445ff
JB		 9433 if (f_count) {
9434 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9435 pf->flags |= I40E_FLAG_FILTER_SYNC;
9436 }
9437
9438 /* Update VSI BW information */
9439 ret = i40e_vsi_get_bw_info(vsi);
9440 if (ret) {
9441 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9442 "couldn't get vsi bw info, err %s aq_err %s\n",
9443 i40e_stat_str(&pf->hw, ret),
9444 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9445 /* VSI is already added so not tearing that up */
9446 ret = 0;
9447 }
9448
9449err:
9450 return ret;
9451}
9452
9453/**
9454 * i40e_vsi_release - Delete a VSI and free its resources
9455 * @vsi: the VSI being removed
9456 *
9457 * Returns 0 on success or < 0 on error
9458 **/
9459int i40e_vsi_release(struct i40e_vsi *vsi)
9460{
9461 struct i40e_mac_filter *f, *ftmp;
9462 struct i40e_veb *veb = NULL;
9463 struct i40e_pf *pf;
9464 u16 uplink_seid;
9465 int i, n;
9466
9467 pf = vsi->back;
9468
9469 /* release of a VEB-owner or last VSI is not allowed */
9470 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9471 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9472 vsi->seid, vsi->uplink_seid);
9473 return -ENODEV;
9474 }
9475 if (vsi == pf->vsi[pf->lan_vsi] &&
9476 !test_bit(__I40E_DOWN, &pf->state)) {
9477 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9478 return -ENODEV;
9479 }
9480
9481 uplink_seid = vsi->uplink_seid;
9482 if (vsi->type != I40E_VSI_SRIOV) {
9483 if (vsi->netdev_registered) {
9484 vsi->netdev_registered = false;
9485 if (vsi->netdev) {
9486 /* results in a call to i40e_close() */
9487 unregister_netdev(vsi->netdev);
41c445ff
JB		 9488 }
9489 } else {
90ef8d47 9490 i40e_vsi_close(vsi);
41c445ff
JB		 9491 }
9492 i40e_vsi_disable_irq(vsi);
9493 }
9494
21659035 9495 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9496 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9497 i40e_del_filter(vsi, f->macaddr, f->vlan,
9498 f->is_vf, f->is_netdev);
21659035
KP		 9499 spin_unlock_bh(&vsi->mac_filter_list_lock);
9500
17652c63 9501 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9502
9503 i40e_vsi_delete(vsi);
9504 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9505 if (vsi->netdev) {
9506 free_netdev(vsi->netdev);
9507 vsi->netdev = NULL;
9508 }
41c445ff
JB		 9509 i40e_vsi_clear_rings(vsi);
9510 i40e_vsi_clear(vsi);
9511
9512 /* If this was the last thing on the VEB, except for the
9513 * controlling VSI, remove the VEB, which puts the controlling
9514 * VSI onto the next level down in the switch.
9515 *
9516 * Well, okay, there's one more exception here: don't remove
9517 * the orphan VEBs yet. We'll wait for an explicit remove request
9518 * from up the network stack.
9519 */
505682cd 9520 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9521 if (pf->vsi[i] &&
9522 pf->vsi[i]->uplink_seid == uplink_seid &&
9523 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9524 n++; /* count the VSIs */
9525 }
9526 }
9527 for (i = 0; i < I40E_MAX_VEB; i++) {
9528 if (!pf->veb[i])
9529 continue;
9530 if (pf->veb[i]->uplink_seid == uplink_seid)
9531 n++; /* count the VEBs */
9532 if (pf->veb[i]->seid == uplink_seid)
9533 veb = pf->veb[i];
9534 }
9535 if (n == 0 && veb && veb->uplink_seid != 0)
9536 i40e_veb_release(veb);
9537
9538 return 0;
9539}
9540
9541/**
9542 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9543 * @vsi: ptr to the VSI
9544 *
9545 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9546 * corresponding SW VSI structure and initializes num_queue_pairs for the
9547 * newly allocated VSI.
9548 *
9549 * Returns 0 on success or negative on failure
9550 **/
9551static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9552{
9553 int ret = -ENOENT;
9554 struct i40e_pf *pf = vsi->back;
9555
493fb300 9556 if (vsi->q_vectors[0]) {
41c445ff
JB		 9557 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9558 vsi->seid);
9559 return -EEXIST;
9560 }
9561
9562 if (vsi->base_vector) {
f29eaa3d 9563 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9564 vsi->seid, vsi->base_vector);
9565 return -EEXIST;
9566 }
9567
90e04070 9568 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9569 if (ret) {
9570 dev_info(&pf->pdev->dev,
9571 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9572 vsi->num_q_vectors, vsi->seid, ret);
9573 vsi->num_q_vectors = 0;
9574 goto vector_setup_out;
9575 }
9576
26cdc443
ASJ		 9577 /* In Legacy mode, we do not have to get any other vector since we
9578 * piggyback on the misc/ICR0 for queue interrupts.
9579 */
9580 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9581 return ret;
958a3e3b
SN		 9582 if (vsi->num_q_vectors)
9583 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9584 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9585 if (vsi->base_vector < 0) {
9586 dev_info(&pf->pdev->dev,
049a2be8
SN		 9587 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9588 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9589 i40e_vsi_free_q_vectors(vsi);
9590 ret = -ENOENT;
9591 goto vector_setup_out;
9592 }
9593
9594vector_setup_out:
9595 return ret;
9596}
9597
bc7d338f
ASJ		 9598/**
9599 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9600 * @vsi: pointer to the vsi.
9601 *
9602 * This re-allocates a vsi's queue resources.
9603 *
9604 * Returns pointer to the successfully allocated and configured VSI sw struct
9605 * on success, otherwise returns NULL on failure.
9606 **/
9607static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9608{
f534039d 9609 struct i40e_pf *pf;
bc7d338f
ASJ		 9610 u8 enabled_tc;
9611 int ret;
9612
f534039d
JU		 9613 if (!vsi)
9614 return NULL;
9615
9616 pf = vsi->back;
9617
bc7d338f
ASJ		 9618 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9619 i40e_vsi_clear_rings(vsi);
9620
9621 i40e_vsi_free_arrays(vsi, false);
9622 i40e_set_num_rings_in_vsi(vsi);
9623 ret = i40e_vsi_alloc_arrays(vsi, false);
9624 if (ret)
9625 goto err_vsi;
9626
9627 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9628 if (ret < 0) {
049a2be8 9629 dev_info(&pf->pdev->dev,
f1c7e72e 9630 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9631 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9632 goto err_vsi;
9633 }
9634 vsi->base_queue = ret;
9635
9636 /* Update the FW view of the VSI. Force a reset of TC and queue
9637 * layout configurations.
9638 */
9639 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9640 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9641 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9642 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
c3c7ea27
MW		 9643 if (vsi->type == I40E_VSI_MAIN)
9644 i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr);
bc7d338f
ASJ		 9645
9646 /* assign it some queues */
9647 ret = i40e_alloc_rings(vsi);
9648 if (ret)
9649 goto err_rings;
9650
9651 /* map all of the rings to the q_vectors */
9652 i40e_vsi_map_rings_to_vectors(vsi);
9653 return vsi;
9654
9655err_rings:
9656 i40e_vsi_free_q_vectors(vsi);
9657 if (vsi->netdev_registered) {
9658 vsi->netdev_registered = false;
9659 unregister_netdev(vsi->netdev);
9660 free_netdev(vsi->netdev);
9661 vsi->netdev = NULL;
9662 }
9663 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9664err_vsi:
9665 i40e_vsi_clear(vsi);
9666 return NULL;
9667}
9668
41c445ff
JB		 9669/**
9670 * i40e_vsi_setup - Set up a VSI by a given type
9671 * @pf: board private structure
9672 * @type: VSI type
9673 * @uplink_seid: the switch element to link to
9674 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9675 *
9676 * This allocates the sw VSI structure and its queue resources, then add a VSI
9677 * to the identified VEB.
9678 *
9679 * Returns pointer to the successfully allocated and configure VSI sw struct on
9680 * success, otherwise returns NULL on failure.
9681 **/
9682struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9683 u16 uplink_seid, u32 param1)
9684{
9685 struct i40e_vsi *vsi = NULL;
9686 struct i40e_veb *veb = NULL;
9687 int ret, i;
9688 int v_idx;
9689
9690 /* The requested uplink_seid must be either
9691 * - the PF's port seid
9692 * no VEB is needed because this is the PF
9693 * or this is a Flow Director special case VSI
9694 * - seid of an existing VEB
9695 * - seid of a VSI that owns an existing VEB
9696 * - seid of a VSI that doesn't own a VEB
9697 * a new VEB is created and the VSI becomes the owner
9698 * - seid of the PF VSI, which is what creates the first VEB
9699 * this is a special case of the previous
9700 *
9701 * Find which uplink_seid we were given and create a new VEB if needed
9702 */
9703 for (i = 0; i < I40E_MAX_VEB; i++) {
9704 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9705 veb = pf->veb[i];
9706 break;
9707 }
9708 }
9709
9710 if (!veb && uplink_seid != pf->mac_seid) {
9711
505682cd 9712 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9713 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9714 vsi = pf->vsi[i];
9715 break;
9716 }
9717 }
9718 if (!vsi) {
9719 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9720 uplink_seid);
9721 return NULL;
9722 }
9723
9724 if (vsi->uplink_seid == pf->mac_seid)
9725 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9726 vsi->tc_config.enabled_tc);
9727 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9728 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9729 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9730 if (veb) {
9731 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9732 dev_info(&vsi->back->pdev->dev,
fb43201f 9733 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9734 return NULL;
9735 }
fa11cb3d
ASJ		 9736 /* We come up by default in VEPA mode if SRIOV is not
9737 * already enabled, in which case we can't force VEPA
9738 * mode.
9739 */
9740 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9741 veb->bridge_mode = BRIDGE_MODE_VEPA;
9742 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9743 }
51616018 9744 i40e_config_bridge_mode(veb);
79c21a82 9745 }
41c445ff
JB		 9746 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9747 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9748 veb = pf->veb[i];
9749 }
9750 if (!veb) {
9751 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9752 return NULL;
9753 }
9754
9755 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9756 uplink_seid = veb->seid;
9757 }
9758
9759 /* get vsi sw struct */
9760 v_idx = i40e_vsi_mem_alloc(pf, type);
9761 if (v_idx < 0)
9762 goto err_alloc;
9763 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9764 if (!vsi)
9765 goto err_alloc;
41c445ff
JB		 9766 vsi->type = type;
9767 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9768
9769 if (type == I40E_VSI_MAIN)
9770 pf->lan_vsi = v_idx;
9771 else if (type == I40E_VSI_SRIOV)
9772 vsi->vf_id = param1;
9773 /* assign it some queues */
cbf61325
ASJ		 9774 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9775 vsi->idx);
41c445ff 9776 if (ret < 0) {
049a2be8
SN		 9777 dev_info(&pf->pdev->dev,
9778 "failed to get tracking for %d queues for VSI %d err=%d\n",
9779 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9780 goto err_vsi;
9781 }
9782 vsi->base_queue = ret;
9783
9784 /* get a VSI from the hardware */
9785 vsi->uplink_seid = uplink_seid;
9786 ret = i40e_add_vsi(vsi);
9787 if (ret)
9788 goto err_vsi;
9789
9790 switch (vsi->type) {
9791 /* setup the netdev if needed */
9792 case I40E_VSI_MAIN:
b499ffb0
SV		 9793 /* Apply relevant filters if a platform-specific mac
9794 * address was selected.
9795 */
9796 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
9797 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr);
9798 if (ret) {
9799 dev_warn(&pf->pdev->dev,
9800 "could not set up macaddr; err %d\n",
9801 ret);
9802 }
9803 }
41c445ff 9804 case I40E_VSI_VMDQ2:
38e00438 9805 case I40E_VSI_FCOE:
41c445ff
JB		 9806 ret = i40e_config_netdev(vsi);
9807 if (ret)
9808 goto err_netdev;
9809 ret = register_netdev(vsi->netdev);
9810 if (ret)
9811 goto err_netdev;
9812 vsi->netdev_registered = true;
9813 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9814#ifdef CONFIG_I40E_DCB
9815 /* Setup DCB netlink interface */
9816 i40e_dcbnl_setup(vsi);
9817#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9818 /* fall through */
9819
9820 case I40E_VSI_FDIR:
9821 /* set up vectors and rings if needed */
9822 ret = i40e_vsi_setup_vectors(vsi);
9823 if (ret)
9824 goto err_msix;
9825
9826 ret = i40e_alloc_rings(vsi);
9827 if (ret)
9828 goto err_rings;
9829
9830 /* map all of the rings to the q_vectors */
9831 i40e_vsi_map_rings_to_vectors(vsi);
9832
9833 i40e_vsi_reset_stats(vsi);
9834 break;
9835
9836 default:
9837 /* no netdev or rings for the other VSI types */
9838 break;
9839 }
9840
e25d00b8
ASJ		 9841 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9842 (vsi->type == I40E_VSI_VMDQ2)) {
9843 ret = i40e_vsi_config_rss(vsi);
9844 }
41c445ff
JB		 9845 return vsi;
9846
9847err_rings:
9848 i40e_vsi_free_q_vectors(vsi);
9849err_msix:
9850 if (vsi->netdev_registered) {
9851 vsi->netdev_registered = false;
9852 unregister_netdev(vsi->netdev);
9853 free_netdev(vsi->netdev);
9854 vsi->netdev = NULL;
9855 }
9856err_netdev:
9857 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9858err_vsi:
9859 i40e_vsi_clear(vsi);
9860err_alloc:
9861 return NULL;
9862}
9863
9864/**
9865 * i40e_veb_get_bw_info - Query VEB BW information
9866 * @veb: the veb to query
9867 *
9868 * Query the Tx scheduler BW configuration data for given VEB
9869 **/
9870static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9871{
9872 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9873 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9874 struct i40e_pf *pf = veb->pf;
9875 struct i40e_hw *hw = &pf->hw;
9876 u32 tc_bw_max;
9877 int ret = 0;
9878 int i;
9879
9880 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9881 &bw_data, NULL);
9882 if (ret) {
9883 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9884 "query veb bw config failed, err %s aq_err %s\n",
9885 i40e_stat_str(&pf->hw, ret),
9886 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9887 goto out;
9888 }
9889
9890 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9891 &ets_data, NULL);
9892 if (ret) {
9893 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9894 "query veb bw ets config failed, err %s aq_err %s\n",
9895 i40e_stat_str(&pf->hw, ret),
9896 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9897 goto out;
9898 }
9899
9900 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9901 veb->bw_max_quanta = ets_data.tc_bw_max;
9902 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9903 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9904 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9905 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9906 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9907 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9908 veb->bw_tc_limit_credits[i] =
9909 le16_to_cpu(bw_data.tc_bw_limits[i]);
9910 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9911 }
9912
9913out:
9914 return ret;
9915}
9916
9917/**
9918 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9919 * @pf: board private structure
9920 *
9921 * On error: returns error code (negative)
9922 * On success: returns vsi index in PF (positive)
9923 **/
9924static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9925{
9926 int ret = -ENOENT;
9927 struct i40e_veb *veb;
9928 int i;
9929
9930 /* Need to protect the allocation of switch elements at the PF level */
9931 mutex_lock(&pf->switch_mutex);
9932
9933 /* VEB list may be fragmented if VEB creation/destruction has
9934 * been happening. We can afford to do a quick scan to look
9935 * for any free slots in the list.
9936 *
9937 * find next empty veb slot, looping back around if necessary
9938 */
9939 i = 0;
9940 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9941 i++;
9942 if (i >= I40E_MAX_VEB) {
9943 ret = -ENOMEM;
9944 goto err_alloc_veb; /* out of VEB slots! */
9945 }
9946
9947 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9948 if (!veb) {
9949 ret = -ENOMEM;
9950 goto err_alloc_veb;
9951 }
9952 veb->pf = pf;
9953 veb->idx = i;
9954 veb->enabled_tc = 1;
9955
9956 pf->veb[i] = veb;
9957 ret = i;
9958err_alloc_veb:
9959 mutex_unlock(&pf->switch_mutex);
9960 return ret;
9961}
9962
9963/**
9964 * i40e_switch_branch_release - Delete a branch of the switch tree
9965 * @branch: where to start deleting
9966 *
9967 * This uses recursion to find the tips of the branch to be
9968 * removed, deleting until we get back to and can delete this VEB.
9969 **/
9970static void i40e_switch_branch_release(struct i40e_veb *branch)
9971{
9972 struct i40e_pf *pf = branch->pf;
9973 u16 branch_seid = branch->seid;
9974 u16 veb_idx = branch->idx;
9975 int i;
9976
9977 /* release any VEBs on this VEB - RECURSION */
9978 for (i = 0; i < I40E_MAX_VEB; i++) {
9979 if (!pf->veb[i])
9980 continue;
9981 if (pf->veb[i]->uplink_seid == branch->seid)
9982 i40e_switch_branch_release(pf->veb[i]);
9983 }
9984
9985 /* Release the VSIs on this VEB, but not the owner VSI.
9986 *
9987 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9988 * the VEB itself, so don't use (*branch) after this loop.
9989 */
505682cd 9990 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9991 if (!pf->vsi[i])
9992 continue;
9993 if (pf->vsi[i]->uplink_seid == branch_seid &&
9994 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9995 i40e_vsi_release(pf->vsi[i]);
9996 }
9997 }
9998
9999 /* There's one corner case where the VEB might not have been
10000 * removed, so double check it here and remove it if needed.
10001 * This case happens if the veb was created from the debugfs
10002 * commands and no VSIs were added to it.
10003 */
10004 if (pf->veb[veb_idx])
10005 i40e_veb_release(pf->veb[veb_idx]);
10006}
10007
10008/**
10009 * i40e_veb_clear - remove veb struct
10010 * @veb: the veb to remove
10011 **/
10012static void i40e_veb_clear(struct i40e_veb *veb)
10013{
10014 if (!veb)
10015 return;
10016
10017 if (veb->pf) {
10018 struct i40e_pf *pf = veb->pf;
10019
10020 mutex_lock(&pf->switch_mutex);
10021 if (pf->veb[veb->idx] == veb)
10022 pf->veb[veb->idx] = NULL;
10023 mutex_unlock(&pf->switch_mutex);
10024 }
10025
10026 kfree(veb);
10027}
10028
10029/**
10030 * i40e_veb_release - Delete a VEB and free its resources
10031 * @veb: the VEB being removed
10032 **/
10033void i40e_veb_release(struct i40e_veb *veb)
10034{
10035 struct i40e_vsi *vsi = NULL;
10036 struct i40e_pf *pf;
10037 int i, n = 0;
10038
10039 pf = veb->pf;
10040
10041 /* find the remaining VSI and check for extras */
505682cd 10042 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10043 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
10044 n++;
10045 vsi = pf->vsi[i];
10046 }
10047 }
10048 if (n != 1) {
10049 dev_info(&pf->pdev->dev,
10050 "can't remove VEB %d with %d VSIs left\n",
10051 veb->seid, n);
10052 return;
10053 }
10054
10055 /* move the remaining VSI to uplink veb */
10056 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
10057 if (veb->uplink_seid) {
10058 vsi->uplink_seid = veb->uplink_seid;
10059 if (veb->uplink_seid == pf->mac_seid)
10060 vsi->veb_idx = I40E_NO_VEB;
10061 else
10062 vsi->veb_idx = veb->veb_idx;
10063 } else {
10064 /* floating VEB */
10065 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10066 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
10067 }
10068
10069 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
10070 i40e_veb_clear(veb);
41c445ff
JB		 10071}
10072
10073/**
10074 * i40e_add_veb - create the VEB in the switch
10075 * @veb: the VEB to be instantiated
10076 * @vsi: the controlling VSI
10077 **/
10078static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
10079{
f1c7e72e 10080 struct i40e_pf *pf = veb->pf;
66fc360a 10081 bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED);
41c445ff
JB		 10082 int ret;
10083
f1c7e72e 10084 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
5bc16031 10085 veb->enabled_tc, false,
66fc360a 10086 &veb->seid, enable_stats, NULL);
5bc16031
MW		 10087
10088 /* get a VEB from the hardware */
41c445ff 10089 if (ret) {
f1c7e72e
SN		 10090 dev_info(&pf->pdev->dev,
10091 "couldn't add VEB, err %s aq_err %s\n",
10092 i40e_stat_str(&pf->hw, ret),
10093 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10094 return -EPERM;
10095 }
10096
10097 /* get statistics counter */
f1c7e72e 10098 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 10099 &veb->stats_idx, NULL, NULL, NULL);
10100 if (ret) {
f1c7e72e
SN		 10101 dev_info(&pf->pdev->dev,
10102 "couldn't get VEB statistics idx, err %s aq_err %s\n",
10103 i40e_stat_str(&pf->hw, ret),
10104 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10105 return -EPERM;
10106 }
10107 ret = i40e_veb_get_bw_info(veb);
10108 if (ret) {
f1c7e72e
SN		 10109 dev_info(&pf->pdev->dev,
10110 "couldn't get VEB bw info, err %s aq_err %s\n",
10111 i40e_stat_str(&pf->hw, ret),
10112 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10113 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 10114 return -ENOENT;
10115 }
10116
10117 vsi->uplink_seid = veb->seid;
10118 vsi->veb_idx = veb->idx;
10119 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
10120
10121 return 0;
10122}
10123
10124/**
10125 * i40e_veb_setup - Set up a VEB
10126 * @pf: board private structure
10127 * @flags: VEB setup flags
10128 * @uplink_seid: the switch element to link to
10129 * @vsi_seid: the initial VSI seid
10130 * @enabled_tc: Enabled TC bit-map
10131 *
10132 * This allocates the sw VEB structure and links it into the switch
10133 * It is possible and legal for this to be a duplicate of an already
10134 * existing VEB. It is also possible for both uplink and vsi seids
10135 * to be zero, in order to create a floating VEB.
10136 *
10137 * Returns pointer to the successfully allocated VEB sw struct on
10138 * success, otherwise returns NULL on failure.
10139 **/
10140struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
10141 u16 uplink_seid, u16 vsi_seid,
10142 u8 enabled_tc)
10143{
10144 struct i40e_veb *veb, *uplink_veb = NULL;
10145 int vsi_idx, veb_idx;
10146 int ret;
10147
10148 /* if one seid is 0, the other must be 0 to create a floating relay */
10149 if ((uplink_seid == 0 || vsi_seid == 0) &&
10150 (uplink_seid + vsi_seid != 0)) {
10151 dev_info(&pf->pdev->dev,
10152 "one, not both seid's are 0: uplink=%d vsi=%d\n",
10153 uplink_seid, vsi_seid);
10154 return NULL;
10155 }
10156
10157 /* make sure there is such a vsi and uplink */
505682cd 10158 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10159 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10160 break;
505682cd 10161 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10162 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10163 vsi_seid);
10164 return NULL;
10165 }
10166
10167 if (uplink_seid && uplink_seid != pf->mac_seid) {
10168 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10169 if (pf->veb[veb_idx] &&
10170 pf->veb[veb_idx]->seid == uplink_seid) {
10171 uplink_veb = pf->veb[veb_idx];
10172 break;
10173 }
10174 }
10175 if (!uplink_veb) {
10176 dev_info(&pf->pdev->dev,
10177 "uplink seid %d not found\n", uplink_seid);
10178 return NULL;
10179 }
10180 }
10181
10182 /* get veb sw struct */
10183 veb_idx = i40e_veb_mem_alloc(pf);
10184 if (veb_idx < 0)
10185 goto err_alloc;
10186 veb = pf->veb[veb_idx];
10187 veb->flags = flags;
10188 veb->uplink_seid = uplink_seid;
10189 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10190 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10191
10192 /* create the VEB in the switch */
10193 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10194 if (ret)
10195 goto err_veb;
1bb8b935
SN		 10196 if (vsi_idx == pf->lan_vsi)
10197 pf->lan_veb = veb->idx;
41c445ff
JB		 10198
10199 return veb;
10200
10201err_veb:
10202 i40e_veb_clear(veb);
10203err_alloc:
10204 return NULL;
10205}
10206
10207/**
b40c82e6 10208 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10209 * @pf: board private structure
10210 * @ele: element we are building info from
10211 * @num_reported: total number of elements
10212 * @printconfig: should we print the contents
10213 *
10214 * helper function to assist in extracting a few useful SEID values.
10215 **/
10216static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10217 struct i40e_aqc_switch_config_element_resp *ele,
10218 u16 num_reported, bool printconfig)
10219{
10220 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10221 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10222 u8 element_type = ele->element_type;
10223 u16 seid = le16_to_cpu(ele->seid);
10224
10225 if (printconfig)
10226 dev_info(&pf->pdev->dev,
10227 "type=%d seid=%d uplink=%d downlink=%d\n",
10228 element_type, seid, uplink_seid, downlink_seid);
10229
10230 switch (element_type) {
10231 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10232 pf->mac_seid = seid;
10233 break;
10234 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10235 /* Main VEB? */
10236 if (uplink_seid != pf->mac_seid)
10237 break;
10238 if (pf->lan_veb == I40E_NO_VEB) {
10239 int v;
10240
10241 /* find existing or else empty VEB */
10242 for (v = 0; v < I40E_MAX_VEB; v++) {
10243 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10244 pf->lan_veb = v;
10245 break;
10246 }
10247 }
10248 if (pf->lan_veb == I40E_NO_VEB) {
10249 v = i40e_veb_mem_alloc(pf);
10250 if (v < 0)
10251 break;
10252 pf->lan_veb = v;
10253 }
10254 }
10255
10256 pf->veb[pf->lan_veb]->seid = seid;
10257 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10258 pf->veb[pf->lan_veb]->pf = pf;
10259 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10260 break;
10261 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10262 if (num_reported != 1)
10263 break;
10264 /* This is immediately after a reset so we can assume this is
10265 * the PF's VSI
10266 */
10267 pf->mac_seid = uplink_seid;
10268 pf->pf_seid = downlink_seid;
10269 pf->main_vsi_seid = seid;
10270 if (printconfig)
10271 dev_info(&pf->pdev->dev,
10272 "pf_seid=%d main_vsi_seid=%d\n",
10273 pf->pf_seid, pf->main_vsi_seid);
10274 break;
10275 case I40E_SWITCH_ELEMENT_TYPE_PF:
10276 case I40E_SWITCH_ELEMENT_TYPE_VF:
10277 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10278 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10279 case I40E_SWITCH_ELEMENT_TYPE_PE:
10280 case I40E_SWITCH_ELEMENT_TYPE_PA:
10281 /* ignore these for now */
10282 break;
10283 default:
10284 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10285 element_type, seid);
10286 break;
10287 }
10288}
10289
10290/**
10291 * i40e_fetch_switch_configuration - Get switch config from firmware
10292 * @pf: board private structure
10293 * @printconfig: should we print the contents
10294 *
10295 * Get the current switch configuration from the device and
10296 * extract a few useful SEID values.
10297 **/
10298int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10299{
10300 struct i40e_aqc_get_switch_config_resp *sw_config;
10301 u16 next_seid = 0;
10302 int ret = 0;
10303 u8 *aq_buf;
10304 int i;
10305
10306 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10307 if (!aq_buf)
10308 return -ENOMEM;
10309
10310 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10311 do {
10312 u16 num_reported, num_total;
10313
10314 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10315 I40E_AQ_LARGE_BUF,
10316 &next_seid, NULL);
10317 if (ret) {
10318 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10319 "get switch config failed err %s aq_err %s\n",
10320 i40e_stat_str(&pf->hw, ret),
10321 i40e_aq_str(&pf->hw,
10322 pf->hw.aq.asq_last_status));
41c445ff
JB		 10323 kfree(aq_buf);
10324 return -ENOENT;
10325 }
10326
10327 num_reported = le16_to_cpu(sw_config->header.num_reported);
10328 num_total = le16_to_cpu(sw_config->header.num_total);
10329
10330 if (printconfig)
10331 dev_info(&pf->pdev->dev,
10332 "header: %d reported %d total\n",
10333 num_reported, num_total);
10334
41c445ff
JB		 10335 for (i = 0; i < num_reported; i++) {
10336 struct i40e_aqc_switch_config_element_resp *ele =
10337 &sw_config->element[i];
10338
10339 i40e_setup_pf_switch_element(pf, ele, num_reported,
10340 printconfig);
10341 }
10342 } while (next_seid != 0);
10343
10344 kfree(aq_buf);
10345 return ret;
10346}
10347
10348/**
10349 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10350 * @pf: board private structure
bc7d338f 10351 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10352 *
10353 * Returns 0 on success, negative value on failure
10354 **/
bc7d338f 10355static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 10356{
b5569892 10357 u16 flags = 0;
41c445ff
JB		 10358 int ret;
10359
10360 /* find out what's out there already */
10361 ret = i40e_fetch_switch_configuration(pf, false);
10362 if (ret) {
10363 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10364 "couldn't fetch switch config, err %s aq_err %s\n",
10365 i40e_stat_str(&pf->hw, ret),
10366 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10367 return ret;
10368 }
10369 i40e_pf_reset_stats(pf);
10370
b5569892
ASJ		 10371 /* set the switch config bit for the whole device to
10372 * support limited promisc or true promisc
10373 * when user requests promisc. The default is limited
10374 * promisc.
10375 */
10376
10377 if ((pf->hw.pf_id == 0) &&
10378 !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT))
10379 flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
10380
10381 if (pf->hw.pf_id == 0) {
10382 u16 valid_flags;
10383
10384 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
10385 ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags,
10386 NULL);
10387 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
10388 dev_info(&pf->pdev->dev,
10389 "couldn't set switch config bits, err %s aq_err %s\n",
10390 i40e_stat_str(&pf->hw, ret),
10391 i40e_aq_str(&pf->hw,
10392 pf->hw.aq.asq_last_status));
10393 /* not a fatal problem, just keep going */
10394 }
10395 }
10396
41c445ff 10397 /* first time setup */
bc7d338f 10398 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10399 struct i40e_vsi *vsi = NULL;
10400 u16 uplink_seid;
10401
10402 /* Set up the PF VSI associated with the PF's main VSI
10403 * that is already in the HW switch
10404 */
10405 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10406 uplink_seid = pf->veb[pf->lan_veb]->seid;
10407 else
10408 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10409 if (pf->lan_vsi == I40E_NO_VSI)
10410 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10411 else if (reinit)
10412 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10413 if (!vsi) {
10414 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10415 i40e_fdir_teardown(pf);
10416 return -EAGAIN;
10417 }
41c445ff
JB		 10418 } else {
10419 /* force a reset of TC and queue layout configurations */
10420 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10421
41c445ff
JB		 10422 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10423 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10424 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10425 }
10426 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10427
cbf61325
ASJ		 10428 i40e_fdir_sb_setup(pf);
10429
41c445ff
JB		 10430 /* Setup static PF queue filter control settings */
10431 ret = i40e_setup_pf_filter_control(pf);
10432 if (ret) {
10433 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10434 ret);
10435 /* Failure here should not stop continuing other steps */
10436 }
10437
10438 /* enable RSS in the HW, even for only one queue, as the stack can use
10439 * the hash
10440 */
10441 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10442 i40e_pf_config_rss(pf);
41c445ff
JB		 10443
10444 /* fill in link information and enable LSE reporting */
0a862b43 10445 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10446 i40e_link_event(pf);
10447
d52c20b7 10448 /* Initialize user-specific link properties */
41c445ff
JB		 10449 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10450 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10451
beb0dff1
JK		 10452 i40e_ptp_init(pf);
10453
41c445ff
JB		 10454 return ret;
10455}
10456
41c445ff
JB		 10457/**
10458 * i40e_determine_queue_usage - Work out queue distribution
10459 * @pf: board private structure
10460 **/
10461static void i40e_determine_queue_usage(struct i40e_pf *pf)
10462{
41c445ff
JB		 10463 int queues_left;
10464
10465 pf->num_lan_qps = 0;
38e00438
VD		 10466#ifdef I40E_FCOE
10467 pf->num_fcoe_qps = 0;
10468#endif
41c445ff
JB		 10469
10470 /* Find the max queues to be put into basic use. We'll always be
10471 * using TC0, whether or not DCB is running, and TC0 will get the
10472 * big RSS set.
10473 */
10474 queues_left = pf->hw.func_caps.num_tx_qp;
10475
cbf61325 10476 if ((queues_left == 1) ||
9aa7e935 10477 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10478 /* one qp for PF, no queues for anything else */
10479 queues_left = 0;
acd65448 10480 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10481
10482 /* make sure all the fancies are disabled */
60ea5f83 10483 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10484 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10485#ifdef I40E_FCOE
10486 I40E_FLAG_FCOE_ENABLED |
10487#endif
60ea5f83
JB		 10488 I40E_FLAG_FD_SB_ENABLED |
10489 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10490 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10491 I40E_FLAG_SRIOV_ENABLED |
10492 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10493 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10494 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10495 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10496 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10497 /* one qp for PF */
acd65448 10498 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10499 queues_left -= pf->num_lan_qps;
10500
10501 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10502 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10503#ifdef I40E_FCOE
10504 I40E_FLAG_FCOE_ENABLED |
10505#endif
9aa7e935
FZ		 10506 I40E_FLAG_FD_SB_ENABLED |
10507 I40E_FLAG_FD_ATR_ENABLED |
10508 I40E_FLAG_DCB_ENABLED |
10509 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10510 } else {
cbf61325 10511 /* Not enough queues for all TCs */
4d9b6043 10512 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10513 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10514 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10515 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10516 }
9a3bd2f1
ASJ		 10517 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10518 num_online_cpus());
10519 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10520 pf->hw.func_caps.num_tx_qp);
10521
cbf61325
ASJ		 10522 queues_left -= pf->num_lan_qps;
10523 }
10524
38e00438
VD		 10525#ifdef I40E_FCOE
10526 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10527 if (I40E_DEFAULT_FCOE <= queues_left) {
10528 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10529 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10530 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10531 } else {
10532 pf->num_fcoe_qps = 0;
10533 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10534 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10535 }
10536
10537 queues_left -= pf->num_fcoe_qps;
10538 }
10539
10540#endif
cbf61325
ASJ		 10541 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10542 if (queues_left > 1) {
10543 queues_left -= 1; /* save 1 queue for FD */
10544 } else {
10545 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10546 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10547 }
41c445ff
JB		 10548 }
10549
10550 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10551 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10552 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10553 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10554 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10555 }
10556
10557 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10558 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10559 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10560 (queues_left / pf->num_vmdq_qps));
10561 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10562 }
10563
f8ff1464 10564 pf->queues_left = queues_left;
8279e495
NP		 10565 dev_dbg(&pf->pdev->dev,
10566 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10567 pf->hw.func_caps.num_tx_qp,
10568 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10569 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10570 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10571 queues_left);
38e00438 10572#ifdef I40E_FCOE
8279e495 10573 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10574#endif
41c445ff
JB		 10575}
10576
10577/**
10578 * i40e_setup_pf_filter_control - Setup PF static filter control
10579 * @pf: PF to be setup
10580 *
b40c82e6 10581 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10582 * settings. If PE/FCoE are enabled then it will also set the per PF
10583 * based filter sizes required for them. It also enables Flow director,
10584 * ethertype and macvlan type filter settings for the pf.
10585 *
10586 * Returns 0 on success, negative on failure
10587 **/
10588static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10589{
10590 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10591
10592 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10593
10594 /* Flow Director is enabled */
60ea5f83 10595 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10596 settings->enable_fdir = true;
10597
10598 /* Ethtype and MACVLAN filters enabled for PF */
10599 settings->enable_ethtype = true;
10600 settings->enable_macvlan = true;
10601
10602 if (i40e_set_filter_control(&pf->hw, settings))
10603 return -ENOENT;
10604
10605 return 0;
10606}
10607
0c22b3dd 10608#define INFO_STRING_LEN 255
7fd89545 10609#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10610static void i40e_print_features(struct i40e_pf *pf)
10611{
10612 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10613 char *buf;
10614 int i;
0c22b3dd 10615
3b195843
JP		 10616 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10617 if (!buf)
0c22b3dd 10618 return;
0c22b3dd 10619
3b195843 10620 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10621#ifdef CONFIG_PCI_IOV
3b195843 10622 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10623#endif
1a557afc 10624 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d",
7fd89545 10625 pf->hw.func_caps.num_vsis,
1a557afc 10626 pf->vsi[pf->lan_vsi]->num_queue_pairs);
0c22b3dd 10627 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10628 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10629 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10630 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10631 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10632 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10633 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10634 }
4d9b6043 10635 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10636 i += snprintf(&buf[i], REMAIN(i), " DCB");
3b195843 10637 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024 10638 i += snprintf(&buf[i], REMAIN(i), " Geneve");
0c22b3dd 10639 if (pf->flags & I40E_FLAG_PTP)
3b195843 10640 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10641#ifdef I40E_FCOE
10642 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10643 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10644#endif
6dec1017 10645 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10646 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10647 else
3b195843 10648 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10649
3b195843
JP		 10650 dev_info(&pf->pdev->dev, "%s\n", buf);
10651 kfree(buf);
7fd89545 10652 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10653}
10654
b499ffb0
SV		 10655/**
10656 * i40e_get_platform_mac_addr - get platform-specific MAC address
10657 *
10658 * @pdev: PCI device information struct
10659 * @pf: board private structure
10660 *
10661 * Look up the MAC address in Open Firmware on systems that support it,
10662 * and use IDPROM on SPARC if no OF address is found. On return, the
10663 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value
10664 * has been selected.
10665 **/
10666static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
10667{
b499ffb0 10668 pf->flags &= ~I40E_FLAG_PF_MAC;
ba94272d 10669 if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr))
b499ffb0 10670 pf->flags |= I40E_FLAG_PF_MAC;
b499ffb0
SV		 10671}
10672
41c445ff
JB		 10673/**
10674 * i40e_probe - Device initialization routine
10675 * @pdev: PCI device information struct
10676 * @ent: entry in i40e_pci_tbl
10677 *
b40c82e6
JK		 10678 * i40e_probe initializes a PF identified by a pci_dev structure.
10679 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10680 * and a hardware reset occur.
10681 *
10682 * Returns 0 on success, negative on failure
10683 **/
10684static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10685{
e827845c 10686 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10687 struct i40e_pf *pf;
10688 struct i40e_hw *hw;
93cd765b 10689 static u16 pfs_found;
1d5109d1 10690 u16 wol_nvm_bits;
d4dfb81a 10691 u16 link_status;
6f66a484 10692 int err;
4f2f017c 10693 u32 val;
8a9eb7d3 10694 u32 i;
58fc3267 10695 u8 set_fc_aq_fail;
41c445ff
JB		 10696
10697 err = pci_enable_device_mem(pdev);
10698 if (err)
10699 return err;
10700
10701 /* set up for high or low dma */
6494294f 10702 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10703 if (err) {
e3e3bfdd
JS		 10704 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10705 if (err) {
10706 dev_err(&pdev->dev,
10707 "DMA configuration failed: 0x%x\n", err);
10708 goto err_dma;
10709 }
41c445ff
JB		 10710 }
10711
10712 /* set up pci connections */
56d766d6 10713 err = pci_request_mem_regions(pdev, i40e_driver_name);
41c445ff
JB		 10714 if (err) {
10715 dev_info(&pdev->dev,
10716 "pci_request_selected_regions failed %d\n", err);
10717 goto err_pci_reg;
10718 }
10719
10720 pci_enable_pcie_error_reporting(pdev);
10721 pci_set_master(pdev);
10722
10723 /* Now that we have a PCI connection, we need to do the
10724 * low level device setup. This is primarily setting up
10725 * the Admin Queue structures and then querying for the
10726 * device's current profile information.
10727 */
10728 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10729 if (!pf) {
10730 err = -ENOMEM;
10731 goto err_pf_alloc;
10732 }
10733 pf->next_vsi = 0;
10734 pf->pdev = pdev;
10735 set_bit(__I40E_DOWN, &pf->state);
10736
10737 hw = &pf->hw;
10738 hw->back = pf;
232f4706 10739
2ac8b675
SN		 10740 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10741 I40E_MAX_CSR_SPACE);
232f4706 10742
2ac8b675 10743 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10744 if (!hw->hw_addr) {
10745 err = -EIO;
10746 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10747 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10748 pf->ioremap_len, err);
41c445ff
JB		 10749 goto err_ioremap;
10750 }
10751 hw->vendor_id = pdev->vendor;
10752 hw->device_id = pdev->device;
10753 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10754 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10755 hw->subsystem_device_id = pdev->subsystem_device;
10756 hw->bus.device = PCI_SLOT(pdev->devfn);
10757 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10758 pf->instance = pfs_found;
41c445ff 10759
de03d2b0
SN		 10760 /* set up the locks for the AQ, do this only once in probe
10761 * and destroy them only once in remove
10762 */
10763 mutex_init(&hw->aq.asq_mutex);
10764 mutex_init(&hw->aq.arq_mutex);
10765
5b5faa43
SN		 10766 if (debug != -1) {
10767 pf->msg_enable = pf->hw.debug_mask;
10768 pf->msg_enable = debug;
10769 }
10770
7134f9ce
JB		 10771 /* do a special CORER for clearing PXE mode once at init */
10772 if (hw->revision_id == 0 &&
10773 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10774 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10775 i40e_flush(hw);
10776 msleep(200);
10777 pf->corer_count++;
10778
10779 i40e_clear_pxe_mode(hw);
10780 }
10781
41c445ff 10782 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10783 i40e_clear_hw(hw);
41c445ff
JB		 10784 err = i40e_pf_reset(hw);
10785 if (err) {
10786 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10787 goto err_pf_reset;
10788 }
10789 pf->pfr_count++;
10790
10791 hw->aq.num_arq_entries = I40E_AQ_LEN;
10792 hw->aq.num_asq_entries = I40E_AQ_LEN;
10793 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10794 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10795 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10796
b294ac70 10797 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10798 "%s-%s:misc",
10799 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10800
10801 err = i40e_init_shared_code(hw);
10802 if (err) {
b2a75c58
ASJ		 10803 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10804 err);
41c445ff
JB		 10805 goto err_pf_reset;
10806 }
10807
d52c20b7
JB		 10808 /* set up a default setting for link flow control */
10809 pf->hw.fc.requested_mode = I40E_FC_NONE;
10810
41c445ff 10811 err = i40e_init_adminq(hw);
2b2426a7
CW		 10812 if (err) {
10813 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10814 dev_info(&pdev->dev,
10815 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10816 else
10817 dev_info(&pdev->dev,
10818 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10819
10820 goto err_pf_reset;
10821 }
f0b44440 10822
6dec1017
SN		 10823 /* provide nvm, fw, api versions */
10824 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10825 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10826 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10827 i40e_nvm_version_str(hw));
f0b44440 10828
7aa67613
CS		 10829 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10830 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10831 dev_info(&pdev->dev,
7aa67613
CS		 10832 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10833 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10834 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10835 dev_info(&pdev->dev,
7aa67613 10836 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10837
4eb3f768
SN		 10838 i40e_verify_eeprom(pf);
10839
2c5fe33b
JB		 10840 /* Rev 0 hardware was never productized */
10841 if (hw->revision_id < 1)
10842 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10843
6ff4ef86 10844 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10845 err = i40e_get_capabilities(pf);
10846 if (err)
10847 goto err_adminq_setup;
10848
10849 err = i40e_sw_init(pf);
10850 if (err) {
10851 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10852 goto err_sw_init;
10853 }
10854
10855 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10856 hw->func_caps.num_rx_qp,
10857 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10858 if (err) {
10859 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10860 goto err_init_lan_hmc;
10861 }
10862
10863 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10864 if (err) {
10865 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10866 err = -ENOENT;
10867 goto err_configure_lan_hmc;
10868 }
10869
b686ece5
NP		 10870 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10871 * Ignore error return codes because if it was already disabled via
10872 * hardware settings this will fail
10873 */
f1bbad33 10874 if (pf->flags & I40E_FLAG_STOP_FW_LLDP) {
b686ece5
NP		 10875 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10876 i40e_aq_stop_lldp(hw, true, NULL);
10877 }
10878
41c445ff 10879 i40e_get_mac_addr(hw, hw->mac.addr);
b499ffb0
SV		 10880 /* allow a platform config to override the HW addr */
10881 i40e_get_platform_mac_addr(pdev, pf);
f62b5060 10882 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10883 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10884 err = -EIO;
10885 goto err_mac_addr;
10886 }
10887 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10888 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10889 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10890 if (is_valid_ether_addr(hw->mac.port_addr))
10891 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10892#ifdef I40E_FCOE
10893 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10894 if (err)
10895 dev_info(&pdev->dev,
10896 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10897 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10898 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10899 hw->mac.san_addr);
10900 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10901 }
10902 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10903#endif /* I40E_FCOE */
41c445ff
JB		 10904
10905 pci_set_drvdata(pdev, pf);
10906 pci_save_state(pdev);
4e3b35b0
NP		 10907#ifdef CONFIG_I40E_DCB
10908 err = i40e_init_pf_dcb(pf);
10909 if (err) {
aebfc816 10910 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10911 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10912 /* Continue without DCB enabled */
4e3b35b0
NP		 10913 }
10914#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10915
10916 /* set up periodic task facility */
10917 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10918 pf->service_timer_period = HZ;
10919
10920 INIT_WORK(&pf->service_task, i40e_service_task);
10921 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10922 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10923
1d5109d1
SN		 10924 /* NVM bit on means WoL disabled for the port */
10925 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10926 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10927 pf->wol_en = false;
10928 else
10929 pf->wol_en = true;
8e2773ae
SN		 10930 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10931
41c445ff
JB		 10932 /* set up the main switch operations */
10933 i40e_determine_queue_usage(pf);
c1147280
JB		 10934 err = i40e_init_interrupt_scheme(pf);
10935 if (err)
10936 goto err_switch_setup;
41c445ff 10937
505682cd
MW		 10938 /* The number of VSIs reported by the FW is the minimum guaranteed
10939 * to us; HW supports far more and we share the remaining pool with
10940 * the other PFs. We allocate space for more than the guarantee with
10941 * the understanding that we might not get them all later.
41c445ff 10942 */
505682cd
MW		 10943 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10944 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10945 else
10946 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10947
10948 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
d17038d6
JB		 10949 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
10950 GFP_KERNEL);
ed87ac09
WY		 10951 if (!pf->vsi) {
10952 err = -ENOMEM;
41c445ff 10953 goto err_switch_setup;
ed87ac09 10954 }
41c445ff 10955
fa11cb3d
ASJ		 10956#ifdef CONFIG_PCI_IOV
10957 /* prep for VF support */
10958 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10959 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10960 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10961 if (pci_num_vf(pdev))
10962 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10963 }
10964#endif
bc7d338f 10965 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10966 if (err) {
10967 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10968 goto err_vsis;
10969 }
58fc3267
HZ		 10970
10971 /* Make sure flow control is set according to current settings */
10972 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10973 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10974 dev_dbg(&pf->pdev->dev,
10975 "Set fc with err %s aq_err %s on get_phy_cap\n",
10976 i40e_stat_str(hw, err),
10977 i40e_aq_str(hw, hw->aq.asq_last_status));
10978 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10979 dev_dbg(&pf->pdev->dev,
10980 "Set fc with err %s aq_err %s on set_phy_config\n",
10981 i40e_stat_str(hw, err),
10982 i40e_aq_str(hw, hw->aq.asq_last_status));
10983 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10984 dev_dbg(&pf->pdev->dev,
10985 "Set fc with err %s aq_err %s on get_link_info\n",
10986 i40e_stat_str(hw, err),
10987 i40e_aq_str(hw, hw->aq.asq_last_status));
10988
8a9eb7d3 10989 /* if FDIR VSI was set up, start it now */
505682cd 10990 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10991 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10992 i40e_vsi_open(pf->vsi[i]);
10993 break;
10994 }
10995 }
41c445ff 10996
2f0aff41
SN		 10997 /* The driver only wants link up/down and module qualification
10998 * reports from firmware. Note the negative logic.
7e2453fe
JB		 10999 */
11000 err = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 11001 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 11002 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 11003 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 11004 if (err)
f1c7e72e
SN		 11005 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
11006 i40e_stat_str(&pf->hw, err),
11007 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 11008
4f2f017c
ASJ		 11009 /* Reconfigure hardware for allowing smaller MSS in the case
11010 * of TSO, so that we avoid the MDD being fired and causing
11011 * a reset in the case of small MSS+TSO.
11012 */
11013 val = rd32(hw, I40E_REG_MSS);
11014 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
11015 val &= ~I40E_REG_MSS_MIN_MASK;
11016 val |= I40E_64BYTE_MSS;
11017 wr32(hw, I40E_REG_MSS, val);
11018 }
11019
8eed76fa 11020 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 11021 msleep(75);
11022 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
11023 if (err)
f1c7e72e
SN		 11024 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
11025 i40e_stat_str(&pf->hw, err),
11026 i40e_aq_str(&pf->hw,
11027 pf->hw.aq.asq_last_status));
cafa2ee6 11028 }
41c445ff
JB		 11029 /* The main driver is (mostly) up and happy. We need to set this state
11030 * before setting up the misc vector or we get a race and the vector
11031 * ends up disabled forever.
11032 */
11033 clear_bit(__I40E_DOWN, &pf->state);
11034
11035 /* In case of MSIX we are going to setup the misc vector right here
11036 * to handle admin queue events etc. In case of legacy and MSI
11037 * the misc functionality and queue processing is combined in
11038 * the same vector and that gets setup at open.
11039 */
11040 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
11041 err = i40e_setup_misc_vector(pf);
11042 if (err) {
11043 dev_info(&pdev->dev,
11044 "setup of misc vector failed: %d\n", err);
11045 goto err_vsis;
11046 }
11047 }
11048
df805f62 11049#ifdef CONFIG_PCI_IOV
41c445ff
JB		 11050 /* prep for VF support */
11051 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 11052 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11053 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 11054 /* disable link interrupts for VFs */
11055 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
11056 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
11057 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
11058 i40e_flush(hw);
4aeec010
MW		 11059
11060 if (pci_num_vf(pdev)) {
11061 dev_info(&pdev->dev,
11062 "Active VFs found, allocating resources.\n");
11063 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
11064 if (err)
11065 dev_info(&pdev->dev,
11066 "Error %d allocating resources for existing VFs\n",
11067 err);
11068 }
41c445ff 11069 }
df805f62 11070#endif /* CONFIG_PCI_IOV */
41c445ff 11071
e3219ce6
ASJ		 11072 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
11073 pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile,
11074 pf->num_iwarp_msix,
11075 I40E_IWARP_IRQ_PILE_ID);
11076 if (pf->iwarp_base_vector < 0) {
11077 dev_info(&pdev->dev,
11078 "failed to get tracking for %d vectors for IWARP err=%d\n",
11079 pf->num_iwarp_msix, pf->iwarp_base_vector);
11080 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
11081 }
11082 }
93cd765b 11083
41c445ff
JB		 11084 i40e_dbg_pf_init(pf);
11085
11086 /* tell the firmware that we're starting */
44033fac 11087 i40e_send_version(pf);
41c445ff
JB		 11088
11089 /* since everything's happy, start the service_task timer */
11090 mod_timer(&pf->service_timer,
11091 round_jiffies(jiffies + pf->service_timer_period));
11092
e3219ce6
ASJ		 11093 /* add this PF to client device list and launch a client service task */
11094 err = i40e_lan_add_device(pf);
11095 if (err)
11096 dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n",
11097 err);
11098
38e00438
VD		 11099#ifdef I40E_FCOE
11100 /* create FCoE interface */
11101 i40e_fcoe_vsi_setup(pf);
11102
11103#endif
3fced535
ASJ		 11104#define PCI_SPEED_SIZE 8
11105#define PCI_WIDTH_SIZE 8
11106 /* Devices on the IOSF bus do not have this information
11107 * and will report PCI Gen 1 x 1 by default so don't bother
11108 * checking them.
11109 */
11110 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
11111 char speed[PCI_SPEED_SIZE] = "Unknown";
11112 char width[PCI_WIDTH_SIZE] = "Unknown";
11113
11114 /* Get the negotiated link width and speed from PCI config
11115 * space
11116 */
11117 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
11118 &link_status);
11119
11120 i40e_set_pci_config_data(hw, link_status);
11121
11122 switch (hw->bus.speed) {
11123 case i40e_bus_speed_8000:
11124 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
11125 case i40e_bus_speed_5000:
11126 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
11127 case i40e_bus_speed_2500:
11128 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
11129 default:
11130 break;
11131 }
11132 switch (hw->bus.width) {
11133 case i40e_bus_width_pcie_x8:
11134 strncpy(width, "8", PCI_WIDTH_SIZE); break;
11135 case i40e_bus_width_pcie_x4:
11136 strncpy(width, "4", PCI_WIDTH_SIZE); break;
11137 case i40e_bus_width_pcie_x2:
11138 strncpy(width, "2", PCI_WIDTH_SIZE); break;
11139 case i40e_bus_width_pcie_x1:
11140 strncpy(width, "1", PCI_WIDTH_SIZE); break;
11141 default:
11142 break;
11143 }
11144
11145 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
11146 speed, width);
11147
11148 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
11149 hw->bus.speed < i40e_bus_speed_8000) {
11150 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
11151 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
11152 }
d4dfb81a
CS		 11153 }
11154
e827845c
CS		 11155 /* get the requested speeds from the fw */
11156 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
11157 if (err)
8279e495
NP		 11158 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
11159 i40e_stat_str(&pf->hw, err),
11160 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 11161 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
11162
fc72dbce
CS		 11163 /* get the supported phy types from the fw */
11164 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
11165 if (err)
11166 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
11167 i40e_stat_str(&pf->hw, err),
11168 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11169 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
11170
e7358f54
ASJ		 11171 /* Add a filter to drop all Flow control frames from any VSI from being
11172 * transmitted. By doing so we stop a malicious VF from sending out
11173 * PAUSE or PFC frames and potentially controlling traffic for other
11174 * PF/VF VSIs.
11175 * The FW can still send Flow control frames if enabled.
11176 */
11177 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11178 pf->main_vsi_seid);
11179
31b606d0
CW		 11180 if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
11181 (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
11182 pf->flags |= I40E_FLAG_HAVE_10GBASET_PHY;
11183
0c22b3dd
JB		 11184 /* print a string summarizing features */
11185 i40e_print_features(pf);
11186
41c445ff
JB		 11187 return 0;
11188
11189 /* Unwind what we've done if something failed in the setup */
11190err_vsis:
11191 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 11192 i40e_clear_interrupt_scheme(pf);
11193 kfree(pf->vsi);
04b03013
SN		 11194err_switch_setup:
11195 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 11196 del_timer_sync(&pf->service_timer);
11197err_mac_addr:
11198err_configure_lan_hmc:
11199 (void)i40e_shutdown_lan_hmc(hw);
11200err_init_lan_hmc:
11201 kfree(pf->qp_pile);
41c445ff
JB		 11202err_sw_init:
11203err_adminq_setup:
41c445ff
JB		 11204err_pf_reset:
11205 iounmap(hw->hw_addr);
11206err_ioremap:
11207 kfree(pf);
11208err_pf_alloc:
11209 pci_disable_pcie_error_reporting(pdev);
56d766d6 11210 pci_release_mem_regions(pdev);
41c445ff
JB		 11211err_pci_reg:
11212err_dma:
11213 pci_disable_device(pdev);
11214 return err;
11215}
11216
11217/**
11218 * i40e_remove - Device removal routine
11219 * @pdev: PCI device information struct
11220 *
11221 * i40e_remove is called by the PCI subsystem to alert the driver
11222 * that is should release a PCI device. This could be caused by a
11223 * Hot-Plug event, or because the driver is going to be removed from
11224 * memory.
11225 **/
11226static void i40e_remove(struct pci_dev *pdev)
11227{
11228 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11229 struct i40e_hw *hw = &pf->hw;
41c445ff 11230 i40e_status ret_code;
41c445ff
JB		 11231 int i;
11232
11233 i40e_dbg_pf_exit(pf);
11234
beb0dff1
JK		 11235 i40e_ptp_stop(pf);
11236
bcab2db9 11237 /* Disable RSS in hw */
272cdaf2
SN		 11238 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
11239 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
bcab2db9 11240
41c445ff 11241 /* no more scheduling of any task */
a4618ec8 11242 set_bit(__I40E_SUSPENDED, &pf->state);
41c445ff 11243 set_bit(__I40E_DOWN, &pf->state);
c99abb4c
SN		 11244 if (pf->service_timer.data)
11245 del_timer_sync(&pf->service_timer);
11246 if (pf->service_task.func)
11247 cancel_work_sync(&pf->service_task);
41c445ff 11248
eb2d80bc
MW		 11249 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11250 i40e_free_vfs(pf);
11251 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11252 }
11253
41c445ff
JB		 11254 i40e_fdir_teardown(pf);
11255
11256 /* If there is a switch structure or any orphans, remove them.
11257 * This will leave only the PF's VSI remaining.
11258 */
11259 for (i = 0; i < I40E_MAX_VEB; i++) {
11260 if (!pf->veb[i])
11261 continue;
11262
11263 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11264 pf->veb[i]->uplink_seid == 0)
11265 i40e_switch_branch_release(pf->veb[i]);
11266 }
11267
11268 /* Now we can shutdown the PF's VSI, just before we kill
11269 * adminq and hmc.
11270 */
11271 if (pf->vsi[pf->lan_vsi])
11272 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11273
e3219ce6
ASJ		 11274 /* remove attached clients */
11275 ret_code = i40e_lan_del_device(pf);
11276 if (ret_code) {
11277 dev_warn(&pdev->dev, "Failed to delete client device: %d\n",
11278 ret_code);
11279 }
11280
41c445ff 11281 /* shutdown and destroy the HMC */
f734dfff
JB		 11282 if (hw->hmc.hmc_obj) {
11283 ret_code = i40e_shutdown_lan_hmc(hw);
60442dea
SN		 11284 if (ret_code)
11285 dev_warn(&pdev->dev,
11286 "Failed to destroy the HMC resources: %d\n",
11287 ret_code);
11288 }
41c445ff
JB		 11289
11290 /* shutdown the adminq */
f734dfff 11291 ret_code = i40e_shutdown_adminq(hw);
41c445ff
JB		 11292 if (ret_code)
11293 dev_warn(&pdev->dev,
11294 "Failed to destroy the Admin Queue resources: %d\n",
11295 ret_code);
11296
8ddb3326
JB		 11297 /* destroy the locks only once, here */
11298 mutex_destroy(&hw->aq.arq_mutex);
11299 mutex_destroy(&hw->aq.asq_mutex);
11300
41c445ff
JB		 11301 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11302 i40e_clear_interrupt_scheme(pf);
505682cd 11303 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11304 if (pf->vsi[i]) {
11305 i40e_vsi_clear_rings(pf->vsi[i]);
11306 i40e_vsi_clear(pf->vsi[i]);
11307 pf->vsi[i] = NULL;
11308 }
11309 }
11310
11311 for (i = 0; i < I40E_MAX_VEB; i++) {
11312 kfree(pf->veb[i]);
11313 pf->veb[i] = NULL;
11314 }
11315
11316 kfree(pf->qp_pile);
41c445ff
JB		 11317 kfree(pf->vsi);
11318
f734dfff 11319 iounmap(hw->hw_addr);
41c445ff 11320 kfree(pf);
56d766d6 11321 pci_release_mem_regions(pdev);
41c445ff
JB		 11322
11323 pci_disable_pcie_error_reporting(pdev);
11324 pci_disable_device(pdev);
11325}
11326
11327/**
11328 * i40e_pci_error_detected - warning that something funky happened in PCI land
11329 * @pdev: PCI device information struct
11330 *
11331 * Called to warn that something happened and the error handling steps
11332 * are in progress. Allows the driver to quiesce things, be ready for
11333 * remediation.
11334 **/
11335static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11336 enum pci_channel_state error)
11337{
11338 struct i40e_pf *pf = pci_get_drvdata(pdev);
11339
11340 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11341
11342 /* shutdown all operations */
9007bccd
SN		 11343 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11344 rtnl_lock();
11345 i40e_prep_for_reset(pf);
11346 rtnl_unlock();
11347 }
41c445ff
JB		 11348
11349 /* Request a slot reset */
11350 return PCI_ERS_RESULT_NEED_RESET;
11351}
11352
11353/**
11354 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11355 * @pdev: PCI device information struct
11356 *
11357 * Called to find if the driver can work with the device now that
11358 * the pci slot has been reset. If a basic connection seems good
11359 * (registers are readable and have sane content) then return a
11360 * happy little PCI_ERS_RESULT_xxx.
11361 **/
11362static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11363{
11364 struct i40e_pf *pf = pci_get_drvdata(pdev);
11365 pci_ers_result_t result;
11366 int err;
11367 u32 reg;
11368
fb43201f 11369 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11370 if (pci_enable_device_mem(pdev)) {
11371 dev_info(&pdev->dev,
11372 "Cannot re-enable PCI device after reset.\n");
11373 result = PCI_ERS_RESULT_DISCONNECT;
11374 } else {
11375 pci_set_master(pdev);
11376 pci_restore_state(pdev);
11377 pci_save_state(pdev);
11378 pci_wake_from_d3(pdev, false);
11379
11380 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11381 if (reg == 0)
11382 result = PCI_ERS_RESULT_RECOVERED;
11383 else
11384 result = PCI_ERS_RESULT_DISCONNECT;
11385 }
11386
11387 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11388 if (err) {
11389 dev_info(&pdev->dev,
11390 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11391 err);
11392 /* non-fatal, continue */
11393 }
11394
11395 return result;
11396}
11397
11398/**
11399 * i40e_pci_error_resume - restart operations after PCI error recovery
11400 * @pdev: PCI device information struct
11401 *
11402 * Called to allow the driver to bring things back up after PCI error
11403 * and/or reset recovery has finished.
11404 **/
11405static void i40e_pci_error_resume(struct pci_dev *pdev)
11406{
11407 struct i40e_pf *pf = pci_get_drvdata(pdev);
11408
fb43201f 11409 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11410 if (test_bit(__I40E_SUSPENDED, &pf->state))
11411 return;
11412
11413 rtnl_lock();
41c445ff 11414 i40e_handle_reset_warning(pf);
4c4935a9 11415 rtnl_unlock();
9007bccd
SN		 11416}
11417
11418/**
11419 * i40e_shutdown - PCI callback for shutting down
11420 * @pdev: PCI device information struct
11421 **/
11422static void i40e_shutdown(struct pci_dev *pdev)
11423{
11424 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11425 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11426
11427 set_bit(__I40E_SUSPENDED, &pf->state);
11428 set_bit(__I40E_DOWN, &pf->state);
11429 rtnl_lock();
11430 i40e_prep_for_reset(pf);
11431 rtnl_unlock();
11432
8e2773ae
SN		 11433 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11434 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11435
02b42498
CS		 11436 del_timer_sync(&pf->service_timer);
11437 cancel_work_sync(&pf->service_task);
11438 i40e_fdir_teardown(pf);
11439
11440 rtnl_lock();
11441 i40e_prep_for_reset(pf);
11442 rtnl_unlock();
11443
11444 wr32(hw, I40E_PFPM_APM,
11445 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11446 wr32(hw, I40E_PFPM_WUFC,
11447 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11448
e147758d
SN		 11449 i40e_clear_interrupt_scheme(pf);
11450
9007bccd 11451 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11452 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11453 pci_set_power_state(pdev, PCI_D3hot);
11454 }
11455}
11456
11457#ifdef CONFIG_PM
11458/**
11459 * i40e_suspend - PCI callback for moving to D3
11460 * @pdev: PCI device information struct
11461 **/
11462static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11463{
11464 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11465 struct i40e_hw *hw = &pf->hw;
059ff69b 11466 int retval = 0;
9007bccd
SN		 11467
11468 set_bit(__I40E_SUSPENDED, &pf->state);
11469 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11470
9007bccd
SN		 11471 rtnl_lock();
11472 i40e_prep_for_reset(pf);
11473 rtnl_unlock();
11474
8e2773ae
SN		 11475 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11476 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11477
b33d3b73
GR		 11478 i40e_stop_misc_vector(pf);
11479
059ff69b
GR		 11480 retval = pci_save_state(pdev);
11481 if (retval)
11482 return retval;
11483
8e2773ae 11484 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11485 pci_set_power_state(pdev, PCI_D3hot);
11486
059ff69b 11487 return retval;
41c445ff
JB		 11488}
11489
9007bccd
SN		 11490/**
11491 * i40e_resume - PCI callback for waking up from D3
11492 * @pdev: PCI device information struct
11493 **/
11494static int i40e_resume(struct pci_dev *pdev)
11495{
11496 struct i40e_pf *pf = pci_get_drvdata(pdev);
11497 u32 err;
11498
11499 pci_set_power_state(pdev, PCI_D0);
11500 pci_restore_state(pdev);
11501 /* pci_restore_state() clears dev->state_saves, so
11502 * call pci_save_state() again to restore it.
11503 */
11504 pci_save_state(pdev);
11505
11506 err = pci_enable_device_mem(pdev);
11507 if (err) {
fb43201f 11508 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11509 return err;
11510 }
11511 pci_set_master(pdev);
11512
11513 /* no wakeup events while running */
11514 pci_wake_from_d3(pdev, false);
11515
11516 /* handling the reset will rebuild the device state */
11517 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11518 clear_bit(__I40E_DOWN, &pf->state);
11519 rtnl_lock();
11520 i40e_reset_and_rebuild(pf, false);
11521 rtnl_unlock();
11522 }
11523
11524 return 0;
11525}
11526
11527#endif
41c445ff
JB		 11528static const struct pci_error_handlers i40e_err_handler = {
11529 .error_detected = i40e_pci_error_detected,
11530 .slot_reset = i40e_pci_error_slot_reset,
11531 .resume = i40e_pci_error_resume,
11532};
11533
11534static struct pci_driver i40e_driver = {
11535 .name = i40e_driver_name,
11536 .id_table = i40e_pci_tbl,
11537 .probe = i40e_probe,
11538 .remove = i40e_remove,
9007bccd
SN		 11539#ifdef CONFIG_PM
11540 .suspend = i40e_suspend,
11541 .resume = i40e_resume,
11542#endif
11543 .shutdown = i40e_shutdown,
41c445ff
JB		 11544 .err_handler = &i40e_err_handler,
11545 .sriov_configure = i40e_pci_sriov_configure,
11546};
11547
11548/**
11549 * i40e_init_module - Driver registration routine
11550 *
11551 * i40e_init_module is the first routine called when the driver is
11552 * loaded. All it does is register with the PCI subsystem.
11553 **/
11554static int __init i40e_init_module(void)
11555{
11556 pr_info("%s: %s - version %s\n", i40e_driver_name,
11557 i40e_driver_string, i40e_driver_version_str);
11558 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11559
2803b16c
JB		 11560 /* we will see if single thread per module is enough for now,
11561 * it can't be any worse than using the system workqueue which
11562 * was already single threaded
11563 */
11564 i40e_wq = create_singlethread_workqueue(i40e_driver_name);
11565 if (!i40e_wq) {
11566 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
11567 return -ENOMEM;
11568 }
11569
41c445ff
JB		 11570 i40e_dbg_init();
11571 return pci_register_driver(&i40e_driver);
11572}
11573module_init(i40e_init_module);
11574
11575/**
11576 * i40e_exit_module - Driver exit cleanup routine
11577 *
11578 * i40e_exit_module is called just before the driver is removed
11579 * from memory.
11580 **/
11581static void __exit i40e_exit_module(void)
11582{
11583 pci_unregister_driver(&i40e_driver);
2803b16c 11584 destroy_workqueue(i40e_wq);
41c445ff
JB		 11585 i40e_dbg_exit();
11586}
11587module_exit(i40e_exit_module);
Linux kernel - Deliverables
This page took 2.629563 seconds and 5 git commands to generate.