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i40e: rename rss_size to alloc_rss_size in i40e_pf
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
1c2df9e5
CS		 41#define DRV_VERSION_MINOR 4
42#define DRV_VERSION_BUILD 2
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 58static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
59 u16 rss_table_size, u16 rss_size);
cbf61325 60static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 61static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 62
63/* i40e_pci_tbl - PCI Device ID Table
64 *
65 * Last entry must be all 0s
66 *
67 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
68 * Class, Class Mask, private data (not used) }
69 */
9baa3c34 70static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 87 /* required last entry */
88 {0, }
89};
90MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
91
92#define I40E_MAX_VF_COUNT 128
93static int debug = -1;
94module_param(debug, int, 0);
95MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
96
97MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
98MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
99MODULE_LICENSE("GPL");
100MODULE_VERSION(DRV_VERSION);
101
102/**
103 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
104 * @hw: pointer to the HW structure
105 * @mem: ptr to mem struct to fill out
106 * @size: size of memory requested
107 * @alignment: what to align the allocation to
108 **/
109int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
110 u64 size, u32 alignment)
111{
112 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
113
114 mem->size = ALIGN(size, alignment);
115 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
116 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 117 if (!mem->va)
118 return -ENOMEM;
41c445ff 119
93bc73b8 120 return 0;
41c445ff
JB		 121}
122
123/**
124 * i40e_free_dma_mem_d - OS specific memory free for shared code
125 * @hw: pointer to the HW structure
126 * @mem: ptr to mem struct to free
127 **/
128int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
129{
130 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
131
132 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
133 mem->va = NULL;
134 mem->pa = 0;
135 mem->size = 0;
136
137 return 0;
138}
139
140/**
141 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
142 * @hw: pointer to the HW structure
143 * @mem: ptr to mem struct to fill out
144 * @size: size of memory requested
145 **/
146int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
147 u32 size)
148{
149 mem->size = size;
150 mem->va = kzalloc(size, GFP_KERNEL);
151
93bc73b8
JB		 152 if (!mem->va)
153 return -ENOMEM;
41c445ff 154
93bc73b8 155 return 0;
41c445ff
JB		 156}
157
158/**
159 * i40e_free_virt_mem_d - OS specific memory free for shared code
160 * @hw: pointer to the HW structure
161 * @mem: ptr to mem struct to free
162 **/
163int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
164{
165 /* it's ok to kfree a NULL pointer */
166 kfree(mem->va);
167 mem->va = NULL;
168 mem->size = 0;
169
170 return 0;
171}
172
173/**
174 * i40e_get_lump - find a lump of free generic resource
175 * @pf: board private structure
176 * @pile: the pile of resource to search
177 * @needed: the number of items needed
178 * @id: an owner id to stick on the items assigned
179 *
180 * Returns the base item index of the lump, or negative for error
181 *
182 * The search_hint trick and lack of advanced fit-finding only work
183 * because we're highly likely to have all the same size lump requests.
184 * Linear search time and any fragmentation should be minimal.
185 **/
186static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
187 u16 needed, u16 id)
188{
189 int ret = -ENOMEM;
ddf434ac 190 int i, j;
41c445ff
JB		 191
192 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
193 dev_info(&pf->pdev->dev,
194 "param err: pile=%p needed=%d id=0x%04x\n",
195 pile, needed, id);
196 return -EINVAL;
197 }
198
199 /* start the linear search with an imperfect hint */
200 i = pile->search_hint;
ddf434ac 201 while (i < pile->num_entries) {
41c445ff
JB		 202 /* skip already allocated entries */
203 if (pile->list[i] & I40E_PILE_VALID_BIT) {
204 i++;
205 continue;
206 }
207
208 /* do we have enough in this lump? */
209 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
210 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
211 break;
212 }
213
214 if (j == needed) {
215 /* there was enough, so assign it to the requestor */
216 for (j = 0; j < needed; j++)
217 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
218 ret = i;
219 pile->search_hint = i + j;
ddf434ac 220 break;
41c445ff 221 }
6995b36c
JB		 222
223 /* not enough, so skip over it and continue looking */
224 i += j;
41c445ff
JB		 225 }
226
227 return ret;
228}
229
230/**
231 * i40e_put_lump - return a lump of generic resource
232 * @pile: the pile of resource to search
233 * @index: the base item index
234 * @id: the owner id of the items assigned
235 *
236 * Returns the count of items in the lump
237 **/
238static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
239{
240 int valid_id = (id | I40E_PILE_VALID_BIT);
241 int count = 0;
242 int i;
243
244 if (!pile || index >= pile->num_entries)
245 return -EINVAL;
246
247 for (i = index;
248 i < pile->num_entries && pile->list[i] == valid_id;
249 i++) {
250 pile->list[i] = 0;
251 count++;
252 }
253
254 if (count && index < pile->search_hint)
255 pile->search_hint = index;
256
257 return count;
258}
259
fdf0e0bf
ASJ		 260/**
261 * i40e_find_vsi_from_id - searches for the vsi with the given id
262 * @pf - the pf structure to search for the vsi
263 * @id - id of the vsi it is searching for
264 **/
265struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
266{
267 int i;
268
269 for (i = 0; i < pf->num_alloc_vsi; i++)
270 if (pf->vsi[i] && (pf->vsi[i]->id == id))
271 return pf->vsi[i];
272
273 return NULL;
274}
275
41c445ff
JB		 276/**
277 * i40e_service_event_schedule - Schedule the service task to wake up
278 * @pf: board private structure
279 *
280 * If not already scheduled, this puts the task into the work queue
281 **/
282static void i40e_service_event_schedule(struct i40e_pf *pf)
283{
284 if (!test_bit(__I40E_DOWN, &pf->state) &&
285 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
286 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
287 schedule_work(&pf->service_task);
288}
289
290/**
291 * i40e_tx_timeout - Respond to a Tx Hang
292 * @netdev: network interface device structure
293 *
294 * If any port has noticed a Tx timeout, it is likely that the whole
295 * device is munged, not just the one netdev port, so go for the full
296 * reset.
297 **/
38e00438
VD		 298#ifdef I40E_FCOE
299void i40e_tx_timeout(struct net_device *netdev)
300#else
41c445ff 301static void i40e_tx_timeout(struct net_device *netdev)
38e00438 302#endif
41c445ff
JB		 303{
304 struct i40e_netdev_priv *np = netdev_priv(netdev);
305 struct i40e_vsi *vsi = np->vsi;
306 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 307 struct i40e_ring *tx_ring = NULL;
308 unsigned int i, hung_queue = 0;
309 u32 head, val;
41c445ff
JB		 310
311 pf->tx_timeout_count++;
312
b03a8c1f
KP		 313 /* find the stopped queue the same way the stack does */
314 for (i = 0; i < netdev->num_tx_queues; i++) {
315 struct netdev_queue *q;
316 unsigned long trans_start;
317
318 q = netdev_get_tx_queue(netdev, i);
319 trans_start = q->trans_start ? : netdev->trans_start;
320 if (netif_xmit_stopped(q) &&
321 time_after(jiffies,
322 (trans_start + netdev->watchdog_timeo))) {
323 hung_queue = i;
324 break;
325 }
326 }
327
328 if (i == netdev->num_tx_queues) {
329 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
330 } else {
331 /* now that we have an index, find the tx_ring struct */
332 for (i = 0; i < vsi->num_queue_pairs; i++) {
333 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
334 if (hung_queue ==
335 vsi->tx_rings[i]->queue_index) {
336 tx_ring = vsi->tx_rings[i];
337 break;
338 }
339 }
340 }
341 }
342
41c445ff 343 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 344 pf->tx_timeout_recovery_level = 1; /* reset after some time */
345 else if (time_before(jiffies,
346 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
347 return; /* don't do any new action before the next timeout */
348
349 if (tx_ring) {
350 head = i40e_get_head(tx_ring);
351 /* Read interrupt register */
352 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
353 val = rd32(&pf->hw,
354 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
355 tx_ring->vsi->base_vector - 1));
356 else
357 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
358
359 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
360 vsi->seid, hung_queue, tx_ring->next_to_clean,
361 head, tx_ring->next_to_use,
362 readl(tx_ring->tail), val);
363 }
364
41c445ff 365 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 366 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
367 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 368
369 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 370 case 1:
371 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
372 break;
373 case 2:
374 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
375 break;
376 case 3:
377 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
378 break;
379 default:
380 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 381 break;
382 }
b03a8c1f 383
41c445ff
JB		 384 i40e_service_event_schedule(pf);
385 pf->tx_timeout_recovery_level++;
386}
387
388/**
389 * i40e_release_rx_desc - Store the new tail and head values
390 * @rx_ring: ring to bump
391 * @val: new head index
392 **/
393static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
394{
395 rx_ring->next_to_use = val;
396
397 /* Force memory writes to complete before letting h/w
398 * know there are new descriptors to fetch. (Only
399 * applicable for weak-ordered memory model archs,
400 * such as IA-64).
401 */
402 wmb();
403 writel(val, rx_ring->tail);
404}
405
406/**
407 * i40e_get_vsi_stats_struct - Get System Network Statistics
408 * @vsi: the VSI we care about
409 *
410 * Returns the address of the device statistics structure.
411 * The statistics are actually updated from the service task.
412 **/
413struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
414{
415 return &vsi->net_stats;
416}
417
418/**
419 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
420 * @netdev: network interface device structure
421 *
422 * Returns the address of the device statistics structure.
423 * The statistics are actually updated from the service task.
424 **/
38e00438
VD		 425#ifdef I40E_FCOE
426struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
427 struct net_device *netdev,
428 struct rtnl_link_stats64 *stats)
429#else
41c445ff
JB		 430static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
431 struct net_device *netdev,
980e9b11 432 struct rtnl_link_stats64 *stats)
38e00438 433#endif
41c445ff
JB		 434{
435 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 436 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 437 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 438 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
439 int i;
440
bc7d338f
ASJ		 441 if (test_bit(__I40E_DOWN, &vsi->state))
442 return stats;
443
3c325ced
JB		 444 if (!vsi->tx_rings)
445 return stats;
446
980e9b11
AD		 447 rcu_read_lock();
448 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 449 u64 bytes, packets;
450 unsigned int start;
451
452 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
453 if (!tx_ring)
454 continue;
455
456 do {
57a7744e 457 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 458 packets = tx_ring->stats.packets;
459 bytes = tx_ring->stats.bytes;
57a7744e 460 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 461
462 stats->tx_packets += packets;
463 stats->tx_bytes += bytes;
464 rx_ring = &tx_ring[1];
465
466 do {
57a7744e 467 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 468 packets = rx_ring->stats.packets;
469 bytes = rx_ring->stats.bytes;
57a7744e 470 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 471
980e9b11
AD		 472 stats->rx_packets += packets;
473 stats->rx_bytes += bytes;
474 }
475 rcu_read_unlock();
476
a5282f44 477 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 478 stats->multicast = vsi_stats->multicast;
479 stats->tx_errors = vsi_stats->tx_errors;
480 stats->tx_dropped = vsi_stats->tx_dropped;
481 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 482 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 483 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
484 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 485
980e9b11 486 return stats;
41c445ff
JB		 487}
488
489/**
490 * i40e_vsi_reset_stats - Resets all stats of the given vsi
491 * @vsi: the VSI to have its stats reset
492 **/
493void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
494{
495 struct rtnl_link_stats64 *ns;
496 int i;
497
498 if (!vsi)
499 return;
500
501 ns = i40e_get_vsi_stats_struct(vsi);
502 memset(ns, 0, sizeof(*ns));
503 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
504 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
505 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 506 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 507 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 508 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 509 sizeof(vsi->rx_rings[i]->stats));
6995b36c 510 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 511 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 512 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 513 sizeof(vsi->tx_rings[i]->stats));
514 memset(&vsi->tx_rings[i]->tx_stats, 0,
515 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 516 }
8e9dca53 517 }
41c445ff
JB		 518 vsi->stat_offsets_loaded = false;
519}
520
521/**
b40c82e6 522 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 523 * @pf: the PF to be reset
524 **/
525void i40e_pf_reset_stats(struct i40e_pf *pf)
526{
e91fdf76
SN		 527 int i;
528
41c445ff
JB		 529 memset(&pf->stats, 0, sizeof(pf->stats));
530 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
531 pf->stat_offsets_loaded = false;
e91fdf76
SN		 532
533 for (i = 0; i < I40E_MAX_VEB; i++) {
534 if (pf->veb[i]) {
535 memset(&pf->veb[i]->stats, 0,
536 sizeof(pf->veb[i]->stats));
537 memset(&pf->veb[i]->stats_offsets, 0,
538 sizeof(pf->veb[i]->stats_offsets));
539 pf->veb[i]->stat_offsets_loaded = false;
540 }
541 }
41c445ff
JB		 542}
543
544/**
545 * i40e_stat_update48 - read and update a 48 bit stat from the chip
546 * @hw: ptr to the hardware info
547 * @hireg: the high 32 bit reg to read
548 * @loreg: the low 32 bit reg to read
549 * @offset_loaded: has the initial offset been loaded yet
550 * @offset: ptr to current offset value
551 * @stat: ptr to the stat
552 *
553 * Since the device stats are not reset at PFReset, they likely will not
554 * be zeroed when the driver starts. We'll save the first values read
555 * and use them as offsets to be subtracted from the raw values in order
556 * to report stats that count from zero. In the process, we also manage
557 * the potential roll-over.
558 **/
559static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
560 bool offset_loaded, u64 *offset, u64 *stat)
561{
562 u64 new_data;
563
ab60085e 564 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 565 new_data = rd32(hw, loreg);
566 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
567 } else {
568 new_data = rd64(hw, loreg);
569 }
570 if (!offset_loaded)
571 *offset = new_data;
572 if (likely(new_data >= *offset))
573 *stat = new_data - *offset;
574 else
41a1d04b 575 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 576 *stat &= 0xFFFFFFFFFFFFULL;
577}
578
579/**
580 * i40e_stat_update32 - read and update a 32 bit stat from the chip
581 * @hw: ptr to the hardware info
582 * @reg: the hw reg to read
583 * @offset_loaded: has the initial offset been loaded yet
584 * @offset: ptr to current offset value
585 * @stat: ptr to the stat
586 **/
587static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
588 bool offset_loaded, u64 *offset, u64 *stat)
589{
590 u32 new_data;
591
592 new_data = rd32(hw, reg);
593 if (!offset_loaded)
594 *offset = new_data;
595 if (likely(new_data >= *offset))
596 *stat = (u32)(new_data - *offset);
597 else
41a1d04b 598 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 599}
600
601/**
602 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
603 * @vsi: the VSI to be updated
604 **/
605void i40e_update_eth_stats(struct i40e_vsi *vsi)
606{
607 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
608 struct i40e_pf *pf = vsi->back;
609 struct i40e_hw *hw = &pf->hw;
610 struct i40e_eth_stats *oes;
611 struct i40e_eth_stats *es; /* device's eth stats */
612
613 es = &vsi->eth_stats;
614 oes = &vsi->eth_stats_offsets;
615
616 /* Gather up the stats that the hw collects */
617 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
618 vsi->stat_offsets_loaded,
619 &oes->tx_errors, &es->tx_errors);
620 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 623 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
624 vsi->stat_offsets_loaded,
625 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
626 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
627 vsi->stat_offsets_loaded,
628 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 629
630 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
631 I40E_GLV_GORCL(stat_idx),
632 vsi->stat_offsets_loaded,
633 &oes->rx_bytes, &es->rx_bytes);
634 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
635 I40E_GLV_UPRCL(stat_idx),
636 vsi->stat_offsets_loaded,
637 &oes->rx_unicast, &es->rx_unicast);
638 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
639 I40E_GLV_MPRCL(stat_idx),
640 vsi->stat_offsets_loaded,
641 &oes->rx_multicast, &es->rx_multicast);
642 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
643 I40E_GLV_BPRCL(stat_idx),
644 vsi->stat_offsets_loaded,
645 &oes->rx_broadcast, &es->rx_broadcast);
646
647 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
648 I40E_GLV_GOTCL(stat_idx),
649 vsi->stat_offsets_loaded,
650 &oes->tx_bytes, &es->tx_bytes);
651 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
652 I40E_GLV_UPTCL(stat_idx),
653 vsi->stat_offsets_loaded,
654 &oes->tx_unicast, &es->tx_unicast);
655 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
656 I40E_GLV_MPTCL(stat_idx),
657 vsi->stat_offsets_loaded,
658 &oes->tx_multicast, &es->tx_multicast);
659 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
660 I40E_GLV_BPTCL(stat_idx),
661 vsi->stat_offsets_loaded,
662 &oes->tx_broadcast, &es->tx_broadcast);
663 vsi->stat_offsets_loaded = true;
664}
665
666/**
667 * i40e_update_veb_stats - Update Switch component statistics
668 * @veb: the VEB being updated
669 **/
670static void i40e_update_veb_stats(struct i40e_veb *veb)
671{
672 struct i40e_pf *pf = veb->pf;
673 struct i40e_hw *hw = &pf->hw;
674 struct i40e_eth_stats *oes;
675 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 676 struct i40e_veb_tc_stats *veb_oes;
677 struct i40e_veb_tc_stats *veb_es;
678 int i, idx = 0;
41c445ff
JB		 679
680 idx = veb->stats_idx;
681 es = &veb->stats;
682 oes = &veb->stats_offsets;
fe860afb
NP		 683 veb_es = &veb->tc_stats;
684 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 685
686 /* Gather up the stats that the hw collects */
687 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
688 veb->stat_offsets_loaded,
689 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 690 if (hw->revision_id > 0)
691 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
692 veb->stat_offsets_loaded,
693 &oes->rx_unknown_protocol,
694 &es->rx_unknown_protocol);
41c445ff
JB		 695 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
696 veb->stat_offsets_loaded,
697 &oes->rx_bytes, &es->rx_bytes);
698 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
699 veb->stat_offsets_loaded,
700 &oes->rx_unicast, &es->rx_unicast);
701 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
702 veb->stat_offsets_loaded,
703 &oes->rx_multicast, &es->rx_multicast);
704 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
705 veb->stat_offsets_loaded,
706 &oes->rx_broadcast, &es->rx_broadcast);
707
708 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
709 veb->stat_offsets_loaded,
710 &oes->tx_bytes, &es->tx_bytes);
711 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
712 veb->stat_offsets_loaded,
713 &oes->tx_unicast, &es->tx_unicast);
714 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
715 veb->stat_offsets_loaded,
716 &oes->tx_multicast, &es->tx_multicast);
717 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
718 veb->stat_offsets_loaded,
719 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 720 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
721 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
722 I40E_GLVEBTC_RPCL(i, idx),
723 veb->stat_offsets_loaded,
724 &veb_oes->tc_rx_packets[i],
725 &veb_es->tc_rx_packets[i]);
726 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
727 I40E_GLVEBTC_RBCL(i, idx),
728 veb->stat_offsets_loaded,
729 &veb_oes->tc_rx_bytes[i],
730 &veb_es->tc_rx_bytes[i]);
731 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
732 I40E_GLVEBTC_TPCL(i, idx),
733 veb->stat_offsets_loaded,
734 &veb_oes->tc_tx_packets[i],
735 &veb_es->tc_tx_packets[i]);
736 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
737 I40E_GLVEBTC_TBCL(i, idx),
738 veb->stat_offsets_loaded,
739 &veb_oes->tc_tx_bytes[i],
740 &veb_es->tc_tx_bytes[i]);
741 }
41c445ff
JB		 742 veb->stat_offsets_loaded = true;
743}
744
38e00438
VD		 745#ifdef I40E_FCOE
746/**
747 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
748 * @vsi: the VSI that is capable of doing FCoE
749 **/
750static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
751{
752 struct i40e_pf *pf = vsi->back;
753 struct i40e_hw *hw = &pf->hw;
754 struct i40e_fcoe_stats *ofs;
755 struct i40e_fcoe_stats *fs; /* device's eth stats */
756 int idx;
757
758 if (vsi->type != I40E_VSI_FCOE)
759 return;
760
761 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
762 fs = &vsi->fcoe_stats;
763 ofs = &vsi->fcoe_stats_offsets;
764
765 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
766 vsi->fcoe_stat_offsets_loaded,
767 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
768 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
769 vsi->fcoe_stat_offsets_loaded,
770 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
771 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
772 vsi->fcoe_stat_offsets_loaded,
773 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
774 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
775 vsi->fcoe_stat_offsets_loaded,
776 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
777 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
778 vsi->fcoe_stat_offsets_loaded,
779 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
780 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
781 vsi->fcoe_stat_offsets_loaded,
782 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
783 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
784 vsi->fcoe_stat_offsets_loaded,
785 &ofs->fcoe_last_error, &fs->fcoe_last_error);
786 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
787 vsi->fcoe_stat_offsets_loaded,
788 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
789
790 vsi->fcoe_stat_offsets_loaded = true;
791}
792
793#endif
41c445ff
JB		 794/**
795 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
796 * @pf: the corresponding PF
797 *
798 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
799 **/
800static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
801{
802 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
803 struct i40e_hw_port_stats *nsd = &pf->stats;
804 struct i40e_hw *hw = &pf->hw;
805 u64 xoff = 0;
41c445ff
JB		 806
807 if ((hw->fc.current_mode != I40E_FC_FULL) &&
808 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
809 return;
810
811 xoff = nsd->link_xoff_rx;
812 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
813 pf->stat_offsets_loaded,
814 &osd->link_xoff_rx, &nsd->link_xoff_rx);
815
816 /* No new LFC xoff rx */
817 if (!(nsd->link_xoff_rx - xoff))
818 return;
819
41c445ff
JB		 820}
821
822/**
823 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
824 * @pf: the corresponding PF
825 *
826 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
827 **/
828static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
829{
830 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
831 struct i40e_hw_port_stats *nsd = &pf->stats;
832 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
833 struct i40e_dcbx_config *dcb_cfg;
834 struct i40e_hw *hw = &pf->hw;
b03a8c1f 835 u16 i;
41c445ff
JB		 836 u8 tc;
837
838 dcb_cfg = &hw->local_dcbx_config;
839
e120814d
NP		 840 /* Collect Link XOFF stats when PFC is disabled */
841 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 842 i40e_update_link_xoff_rx(pf);
843 return;
844 }
845
846 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
847 u64 prio_xoff = nsd->priority_xoff_rx[i];
6995b36c 848
41c445ff
JB		 849 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
850 pf->stat_offsets_loaded,
851 &osd->priority_xoff_rx[i],
852 &nsd->priority_xoff_rx[i]);
853
854 /* No new PFC xoff rx */
855 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
856 continue;
857 /* Get the TC for given priority */
858 tc = dcb_cfg->etscfg.prioritytable[i];
859 xoff[tc] = true;
860 }
41c445ff
JB		 861}
862
863/**
7812fddc 864 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 865 * @vsi: the VSI to be updated
866 *
867 * There are a few instances where we store the same stat in a
868 * couple of different structs. This is partly because we have
869 * the netdev stats that need to be filled out, which is slightly
870 * different from the "eth_stats" defined by the chip and used in
7812fddc 871 * VF communications. We sort it out here.
41c445ff 872 **/
7812fddc 873static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 874{
875 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 876 struct rtnl_link_stats64 *ons;
877 struct rtnl_link_stats64 *ns; /* netdev stats */
878 struct i40e_eth_stats *oes;
879 struct i40e_eth_stats *es; /* device's eth stats */
880 u32 tx_restart, tx_busy;
bf00b376 881 struct i40e_ring *p;
41c445ff 882 u32 rx_page, rx_buf;
bf00b376
AA		 883 u64 bytes, packets;
884 unsigned int start;
2fc3d715 885 u64 tx_linearize;
164c9f54 886 u64 tx_force_wb;
41c445ff
JB		 887 u64 rx_p, rx_b;
888 u64 tx_p, tx_b;
41c445ff
JB		 889 u16 q;
890
891 if (test_bit(__I40E_DOWN, &vsi->state) ||
892 test_bit(__I40E_CONFIG_BUSY, &pf->state))
893 return;
894
895 ns = i40e_get_vsi_stats_struct(vsi);
896 ons = &vsi->net_stats_offsets;
897 es = &vsi->eth_stats;
898 oes = &vsi->eth_stats_offsets;
899
900 /* Gather up the netdev and vsi stats that the driver collects
901 * on the fly during packet processing
902 */
903 rx_b = rx_p = 0;
904 tx_b = tx_p = 0;
164c9f54 905 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
41c445ff
JB		 906 rx_page = 0;
907 rx_buf = 0;
980e9b11 908 rcu_read_lock();
41c445ff 909 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 910 /* locate Tx ring */
911 p = ACCESS_ONCE(vsi->tx_rings[q]);
912
913 do {
57a7744e 914 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 915 packets = p->stats.packets;
916 bytes = p->stats.bytes;
57a7744e 917 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 918 tx_b += bytes;
919 tx_p += packets;
920 tx_restart += p->tx_stats.restart_queue;
921 tx_busy += p->tx_stats.tx_busy;
2fc3d715 922 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 923 tx_force_wb += p->tx_stats.tx_force_wb;
41c445ff 924
980e9b11
AD		 925 /* Rx queue is part of the same block as Tx queue */
926 p = &p[1];
927 do {
57a7744e 928 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 929 packets = p->stats.packets;
930 bytes = p->stats.bytes;
57a7744e 931 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 932 rx_b += bytes;
933 rx_p += packets;
420136cc
MW		 934 rx_buf += p->rx_stats.alloc_buff_failed;
935 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 936 }
980e9b11 937 rcu_read_unlock();
41c445ff
JB		 938 vsi->tx_restart = tx_restart;
939 vsi->tx_busy = tx_busy;
2fc3d715 940 vsi->tx_linearize = tx_linearize;
164c9f54 941 vsi->tx_force_wb = tx_force_wb;
41c445ff
JB		 942 vsi->rx_page_failed = rx_page;
943 vsi->rx_buf_failed = rx_buf;
944
945 ns->rx_packets = rx_p;
946 ns->rx_bytes = rx_b;
947 ns->tx_packets = tx_p;
948 ns->tx_bytes = tx_b;
949
41c445ff 950 /* update netdev stats from eth stats */
7812fddc 951 i40e_update_eth_stats(vsi);
41c445ff
JB		 952 ons->tx_errors = oes->tx_errors;
953 ns->tx_errors = es->tx_errors;
954 ons->multicast = oes->rx_multicast;
955 ns->multicast = es->rx_multicast;
41a9e55c
SN		 956 ons->rx_dropped = oes->rx_discards;
957 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 958 ons->tx_dropped = oes->tx_discards;
959 ns->tx_dropped = es->tx_discards;
960
7812fddc 961 /* pull in a couple PF stats if this is the main vsi */
41c445ff 962 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 963 ns->rx_crc_errors = pf->stats.crc_errors;
964 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
965 ns->rx_length_errors = pf->stats.rx_length_errors;
966 }
967}
41c445ff 968
7812fddc 969/**
b40c82e6 970 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 971 * @pf: the PF to be updated
972 **/
973static void i40e_update_pf_stats(struct i40e_pf *pf)
974{
975 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
976 struct i40e_hw_port_stats *nsd = &pf->stats;
977 struct i40e_hw *hw = &pf->hw;
978 u32 val;
979 int i;
41c445ff 980
7812fddc
SN		 981 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
982 I40E_GLPRT_GORCL(hw->port),
983 pf->stat_offsets_loaded,
984 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
985 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
986 I40E_GLPRT_GOTCL(hw->port),
987 pf->stat_offsets_loaded,
988 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
989 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
990 pf->stat_offsets_loaded,
991 &osd->eth.rx_discards,
992 &nsd->eth.rx_discards);
532d283d
SN		 993 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
994 I40E_GLPRT_UPRCL(hw->port),
995 pf->stat_offsets_loaded,
996 &osd->eth.rx_unicast,
997 &nsd->eth.rx_unicast);
7812fddc
SN		 998 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
999 I40E_GLPRT_MPRCL(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->eth.rx_multicast,
1002 &nsd->eth.rx_multicast);
532d283d
SN		 1003 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
1004 I40E_GLPRT_BPRCL(hw->port),
1005 pf->stat_offsets_loaded,
1006 &osd->eth.rx_broadcast,
1007 &nsd->eth.rx_broadcast);
1008 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
1009 I40E_GLPRT_UPTCL(hw->port),
1010 pf->stat_offsets_loaded,
1011 &osd->eth.tx_unicast,
1012 &nsd->eth.tx_unicast);
1013 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1014 I40E_GLPRT_MPTCL(hw->port),
1015 pf->stat_offsets_loaded,
1016 &osd->eth.tx_multicast,
1017 &nsd->eth.tx_multicast);
1018 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1019 I40E_GLPRT_BPTCL(hw->port),
1020 pf->stat_offsets_loaded,
1021 &osd->eth.tx_broadcast,
1022 &nsd->eth.tx_broadcast);
41c445ff 1023
7812fddc
SN		 1024 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->tx_dropped_link_down,
1027 &nsd->tx_dropped_link_down);
41c445ff 1028
7812fddc
SN		 1029 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->crc_errors, &nsd->crc_errors);
41c445ff 1032
7812fddc
SN		 1033 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 1036
7812fddc
SN		 1037 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->mac_local_faults,
1040 &nsd->mac_local_faults);
1041 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->mac_remote_faults,
1044 &nsd->mac_remote_faults);
41c445ff 1045
7812fddc
SN		 1046 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->rx_length_errors,
1049 &nsd->rx_length_errors);
41c445ff 1050
7812fddc
SN		 1051 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1052 pf->stat_offsets_loaded,
1053 &osd->link_xon_rx, &nsd->link_xon_rx);
1054 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->link_xon_tx, &nsd->link_xon_tx);
1057 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1058 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1061
7812fddc
SN		 1062 for (i = 0; i < 8; i++) {
1063 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1064 pf->stat_offsets_loaded,
7812fddc
SN		 1065 &osd->priority_xon_rx[i],
1066 &nsd->priority_xon_rx[i]);
1067 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1068 pf->stat_offsets_loaded,
7812fddc
SN		 1069 &osd->priority_xon_tx[i],
1070 &nsd->priority_xon_tx[i]);
1071 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1072 pf->stat_offsets_loaded,
7812fddc
SN		 1073 &osd->priority_xoff_tx[i],
1074 &nsd->priority_xoff_tx[i]);
1075 i40e_stat_update32(hw,
1076 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1077 pf->stat_offsets_loaded,
7812fddc
SN		 1078 &osd->priority_xon_2_xoff[i],
1079 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1080 }
1081
7812fddc
SN		 1082 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1083 I40E_GLPRT_PRC64L(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_size_64, &nsd->rx_size_64);
1086 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1087 I40E_GLPRT_PRC127L(hw->port),
1088 pf->stat_offsets_loaded,
1089 &osd->rx_size_127, &nsd->rx_size_127);
1090 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1091 I40E_GLPRT_PRC255L(hw->port),
1092 pf->stat_offsets_loaded,
1093 &osd->rx_size_255, &nsd->rx_size_255);
1094 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1095 I40E_GLPRT_PRC511L(hw->port),
1096 pf->stat_offsets_loaded,
1097 &osd->rx_size_511, &nsd->rx_size_511);
1098 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1099 I40E_GLPRT_PRC1023L(hw->port),
1100 pf->stat_offsets_loaded,
1101 &osd->rx_size_1023, &nsd->rx_size_1023);
1102 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1103 I40E_GLPRT_PRC1522L(hw->port),
1104 pf->stat_offsets_loaded,
1105 &osd->rx_size_1522, &nsd->rx_size_1522);
1106 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1107 I40E_GLPRT_PRC9522L(hw->port),
1108 pf->stat_offsets_loaded,
1109 &osd->rx_size_big, &nsd->rx_size_big);
1110
1111 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1112 I40E_GLPRT_PTC64L(hw->port),
1113 pf->stat_offsets_loaded,
1114 &osd->tx_size_64, &nsd->tx_size_64);
1115 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1116 I40E_GLPRT_PTC127L(hw->port),
1117 pf->stat_offsets_loaded,
1118 &osd->tx_size_127, &nsd->tx_size_127);
1119 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1120 I40E_GLPRT_PTC255L(hw->port),
1121 pf->stat_offsets_loaded,
1122 &osd->tx_size_255, &nsd->tx_size_255);
1123 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1124 I40E_GLPRT_PTC511L(hw->port),
1125 pf->stat_offsets_loaded,
1126 &osd->tx_size_511, &nsd->tx_size_511);
1127 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1128 I40E_GLPRT_PTC1023L(hw->port),
1129 pf->stat_offsets_loaded,
1130 &osd->tx_size_1023, &nsd->tx_size_1023);
1131 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1132 I40E_GLPRT_PTC1522L(hw->port),
1133 pf->stat_offsets_loaded,
1134 &osd->tx_size_1522, &nsd->tx_size_1522);
1135 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1136 I40E_GLPRT_PTC9522L(hw->port),
1137 pf->stat_offsets_loaded,
1138 &osd->tx_size_big, &nsd->tx_size_big);
1139
1140 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1141 pf->stat_offsets_loaded,
1142 &osd->rx_undersize, &nsd->rx_undersize);
1143 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1144 pf->stat_offsets_loaded,
1145 &osd->rx_fragments, &nsd->rx_fragments);
1146 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1147 pf->stat_offsets_loaded,
1148 &osd->rx_oversize, &nsd->rx_oversize);
1149 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1150 pf->stat_offsets_loaded,
1151 &osd->rx_jabber, &nsd->rx_jabber);
1152
433c47de 1153 /* FDIR stats */
0bf4b1b0
ASJ		 1154 i40e_stat_update32(hw,
1155 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1156 pf->stat_offsets_loaded,
1157 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1158 i40e_stat_update32(hw,
1159 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1160 pf->stat_offsets_loaded,
1161 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1162 i40e_stat_update32(hw,
1163 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1164 pf->stat_offsets_loaded,
1165 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1166
7812fddc
SN		 1167 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1168 nsd->tx_lpi_status =
1169 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1170 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1171 nsd->rx_lpi_status =
1172 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1173 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1174 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1175 pf->stat_offsets_loaded,
1176 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1177 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1178 pf->stat_offsets_loaded,
1179 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1180
d0389e51
ASJ		 1181 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1182 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1183 nsd->fd_sb_status = true;
1184 else
1185 nsd->fd_sb_status = false;
1186
1187 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1188 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1189 nsd->fd_atr_status = true;
1190 else
1191 nsd->fd_atr_status = false;
1192
41c445ff
JB		 1193 pf->stat_offsets_loaded = true;
1194}
1195
7812fddc
SN		 1196/**
1197 * i40e_update_stats - Update the various statistics counters.
1198 * @vsi: the VSI to be updated
1199 *
1200 * Update the various stats for this VSI and its related entities.
1201 **/
1202void i40e_update_stats(struct i40e_vsi *vsi)
1203{
1204 struct i40e_pf *pf = vsi->back;
1205
1206 if (vsi == pf->vsi[pf->lan_vsi])
1207 i40e_update_pf_stats(pf);
1208
1209 i40e_update_vsi_stats(vsi);
38e00438
VD		 1210#ifdef I40E_FCOE
1211 i40e_update_fcoe_stats(vsi);
1212#endif
7812fddc
SN		 1213}
1214
41c445ff
JB		 1215/**
1216 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1217 * @vsi: the VSI to be searched
1218 * @macaddr: the MAC address
1219 * @vlan: the vlan
b40c82e6 1220 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1221 * @is_netdev: make sure its a netdev filter, else doesn't matter
1222 *
1223 * Returns ptr to the filter object or NULL
1224 **/
1225static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1226 u8 *macaddr, s16 vlan,
1227 bool is_vf, bool is_netdev)
1228{
1229 struct i40e_mac_filter *f;
1230
1231 if (!vsi || !macaddr)
1232 return NULL;
1233
1234 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1235 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1236 (vlan == f->vlan) &&
1237 (!is_vf || f->is_vf) &&
1238 (!is_netdev || f->is_netdev))
1239 return f;
1240 }
1241 return NULL;
1242}
1243
1244/**
1245 * i40e_find_mac - Find a mac addr in the macvlan filters list
1246 * @vsi: the VSI to be searched
1247 * @macaddr: the MAC address we are searching for
b40c82e6 1248 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1249 * @is_netdev: make sure its a netdev filter, else doesn't matter
1250 *
1251 * Returns the first filter with the provided MAC address or NULL if
1252 * MAC address was not found
1253 **/
1254struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1255 bool is_vf, bool is_netdev)
1256{
1257 struct i40e_mac_filter *f;
1258
1259 if (!vsi || !macaddr)
1260 return NULL;
1261
1262 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1263 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1264 (!is_vf || f->is_vf) &&
1265 (!is_netdev || f->is_netdev))
1266 return f;
1267 }
1268 return NULL;
1269}
1270
1271/**
1272 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1273 * @vsi: the VSI to be searched
1274 *
1275 * Returns true if VSI is in vlan mode or false otherwise
1276 **/
1277bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1278{
1279 struct i40e_mac_filter *f;
1280
1281 /* Only -1 for all the filters denotes not in vlan mode
1282 * so we have to go through all the list in order to make sure
1283 */
1284 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1285 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1286 return true;
1287 }
1288
1289 return false;
1290}
1291
1292/**
1293 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1294 * @vsi: the VSI to be searched
1295 * @macaddr: the mac address to be filtered
b40c82e6 1296 * @is_vf: true if it is a VF
41c445ff
JB		 1297 * @is_netdev: true if it is a netdev
1298 *
1299 * Goes through all the macvlan filters and adds a
1300 * macvlan filter for each unique vlan that already exists
1301 *
1302 * Returns first filter found on success, else NULL
1303 **/
1304struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1305 bool is_vf, bool is_netdev)
1306{
1307 struct i40e_mac_filter *f;
1308
1309 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1310 if (vsi->info.pvid)
1311 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1312 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1313 is_vf, is_netdev)) {
1314 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1315 is_vf, is_netdev))
41c445ff
JB		 1316 return NULL;
1317 }
1318 }
1319
1320 return list_first_entry_or_null(&vsi->mac_filter_list,
1321 struct i40e_mac_filter, list);
1322}
1323
8c27d42e
GR		 1324/**
1325 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1326 * @vsi: the PF Main VSI - inappropriate for any other VSI
1327 * @macaddr: the MAC address
30650cc5
SN		 1328 *
1329 * Some older firmware configurations set up a default promiscuous VLAN
1330 * filter that needs to be removed.
8c27d42e 1331 **/
30650cc5 1332static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1333{
1334 struct i40e_aqc_remove_macvlan_element_data element;
1335 struct i40e_pf *pf = vsi->back;
f1c7e72e 1336 i40e_status ret;
8c27d42e
GR		 1337
1338 /* Only appropriate for the PF main VSI */
1339 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1340 return -EINVAL;
8c27d42e 1341
30650cc5 1342 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1343 ether_addr_copy(element.mac_addr, macaddr);
1344 element.vlan_tag = 0;
1345 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1346 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1347 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1348 if (ret)
30650cc5
SN		 1349 return -ENOENT;
1350
1351 return 0;
8c27d42e
GR		 1352}
1353
41c445ff
JB		 1354/**
1355 * i40e_add_filter - Add a mac/vlan filter to the VSI
1356 * @vsi: the VSI to be searched
1357 * @macaddr: the MAC address
1358 * @vlan: the vlan
b40c82e6 1359 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1360 * @is_netdev: make sure its a netdev filter, else doesn't matter
1361 *
1362 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1363 *
1364 * NOTE: This function is expected to be called with mac_filter_list_lock
1365 * being held.
41c445ff
JB		 1366 **/
1367struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1368 u8 *macaddr, s16 vlan,
1369 bool is_vf, bool is_netdev)
1370{
1371 struct i40e_mac_filter *f;
1372
1373 if (!vsi || !macaddr)
1374 return NULL;
1375
1376 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1377 if (!f) {
1378 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1379 if (!f)
1380 goto add_filter_out;
1381
9a173901 1382 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1383 f->vlan = vlan;
1384 f->changed = true;
1385
1386 INIT_LIST_HEAD(&f->list);
1387 list_add(&f->list, &vsi->mac_filter_list);
1388 }
1389
1390 /* increment counter and add a new flag if needed */
1391 if (is_vf) {
1392 if (!f->is_vf) {
1393 f->is_vf = true;
1394 f->counter++;
1395 }
1396 } else if (is_netdev) {
1397 if (!f->is_netdev) {
1398 f->is_netdev = true;
1399 f->counter++;
1400 }
1401 } else {
1402 f->counter++;
1403 }
1404
1405 /* changed tells sync_filters_subtask to
1406 * push the filter down to the firmware
1407 */
1408 if (f->changed) {
1409 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1410 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1411 }
1412
1413add_filter_out:
1414 return f;
1415}
1416
1417/**
1418 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1419 * @vsi: the VSI to be searched
1420 * @macaddr: the MAC address
1421 * @vlan: the vlan
b40c82e6 1422 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1423 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1424 *
1425 * NOTE: This function is expected to be called with mac_filter_list_lock
1426 * being held.
41c445ff
JB		 1427 **/
1428void i40e_del_filter(struct i40e_vsi *vsi,
1429 u8 *macaddr, s16 vlan,
1430 bool is_vf, bool is_netdev)
1431{
1432 struct i40e_mac_filter *f;
1433
1434 if (!vsi || !macaddr)
1435 return;
1436
1437 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1438 if (!f || f->counter == 0)
1439 return;
1440
1441 if (is_vf) {
1442 if (f->is_vf) {
1443 f->is_vf = false;
1444 f->counter--;
1445 }
1446 } else if (is_netdev) {
1447 if (f->is_netdev) {
1448 f->is_netdev = false;
1449 f->counter--;
1450 }
1451 } else {
b40c82e6 1452 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1453 int min_f = 0;
6995b36c 1454
41c445ff
JB		 1455 min_f += (f->is_vf ? 1 : 0);
1456 min_f += (f->is_netdev ? 1 : 0);
1457
1458 if (f->counter > min_f)
1459 f->counter--;
1460 }
1461
1462 /* counter == 0 tells sync_filters_subtask to
1463 * remove the filter from the firmware's list
1464 */
1465 if (f->counter == 0) {
1466 f->changed = true;
1467 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1468 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1469 }
1470}
1471
1472/**
1473 * i40e_set_mac - NDO callback to set mac address
1474 * @netdev: network interface device structure
1475 * @p: pointer to an address structure
1476 *
1477 * Returns 0 on success, negative on failure
1478 **/
38e00438
VD		 1479#ifdef I40E_FCOE
1480int i40e_set_mac(struct net_device *netdev, void *p)
1481#else
41c445ff 1482static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1483#endif
41c445ff
JB		 1484{
1485 struct i40e_netdev_priv *np = netdev_priv(netdev);
1486 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1487 struct i40e_pf *pf = vsi->back;
1488 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1489 struct sockaddr *addr = p;
1490 struct i40e_mac_filter *f;
1491
1492 if (!is_valid_ether_addr(addr->sa_data))
1493 return -EADDRNOTAVAIL;
1494
30650cc5
SN		 1495 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1496 netdev_info(netdev, "already using mac address %pM\n",
1497 addr->sa_data);
1498 return 0;
1499 }
41c445ff 1500
80f6428f
ASJ		 1501 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1502 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1503 return -EADDRNOTAVAIL;
1504
30650cc5
SN		 1505 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1506 netdev_info(netdev, "returning to hw mac address %pM\n",
1507 hw->mac.addr);
1508 else
1509 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1510
41c445ff
JB		 1511 if (vsi->type == I40E_VSI_MAIN) {
1512 i40e_status ret;
6995b36c 1513
41c445ff 1514 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1515 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1516 addr->sa_data, NULL);
1517 if (ret) {
1518 netdev_info(netdev,
1519 "Addr change for Main VSI failed: %d\n",
1520 ret);
1521 return -EADDRNOTAVAIL;
1522 }
41c445ff
JB		 1523 }
1524
30650cc5
SN		 1525 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1526 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1527
30650cc5
SN		 1528 memset(&element, 0, sizeof(element));
1529 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1530 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1531 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1532 } else {
21659035 1533 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1534 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1535 false, false);
21659035 1536 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1537 }
41c445ff 1538
30650cc5
SN		 1539 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1540 struct i40e_aqc_add_macvlan_element_data element;
1541
1542 memset(&element, 0, sizeof(element));
1543 ether_addr_copy(element.mac_addr, hw->mac.addr);
1544 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1545 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1546 } else {
21659035 1547 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1548 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1549 false, false);
1550 if (f)
1551 f->is_laa = true;
21659035 1552 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1553 }
1554
30e2561b 1555 i40e_sync_vsi_filters(vsi, false);
30650cc5 1556 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1557
1558 return 0;
1559}
1560
1561/**
1562 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1563 * @vsi: the VSI being setup
1564 * @ctxt: VSI context structure
1565 * @enabled_tc: Enabled TCs bitmap
1566 * @is_add: True if called before Add VSI
1567 *
1568 * Setup VSI queue mapping for enabled traffic classes.
1569 **/
38e00438
VD		 1570#ifdef I40E_FCOE
1571void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1572 struct i40e_vsi_context *ctxt,
1573 u8 enabled_tc,
1574 bool is_add)
1575#else
41c445ff
JB		 1576static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1577 struct i40e_vsi_context *ctxt,
1578 u8 enabled_tc,
1579 bool is_add)
38e00438 1580#endif
41c445ff
JB		 1581{
1582 struct i40e_pf *pf = vsi->back;
1583 u16 sections = 0;
1584 u8 netdev_tc = 0;
1585 u16 numtc = 0;
1586 u16 qcount;
1587 u8 offset;
1588 u16 qmap;
1589 int i;
4e3b35b0 1590 u16 num_tc_qps = 0;
41c445ff
JB		 1591
1592 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1593 offset = 0;
1594
1595 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1596 /* Find numtc from enabled TC bitmap */
1597 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1598 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1599 numtc++;
1600 }
1601 if (!numtc) {
1602 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1603 numtc = 1;
1604 }
1605 } else {
1606 /* At least TC0 is enabled in case of non-DCB case */
1607 numtc = 1;
1608 }
1609
1610 vsi->tc_config.numtc = numtc;
1611 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1612 /* Number of queues per enabled TC */
7f9ff476
AS		 1613 /* In MFP case we can have a much lower count of MSIx
1614 * vectors available and so we need to lower the used
1615 * q count.
1616 */
26cdc443
ASJ		 1617 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1618 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1619 else
1620 qcount = vsi->alloc_queue_pairs;
7f9ff476 1621 num_tc_qps = qcount / numtc;
e25d00b8 1622 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1623
1624 /* Setup queue offset/count for all TCs for given VSI */
1625 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1626 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1627 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1628 /* TC is enabled */
41c445ff
JB		 1629 int pow, num_qps;
1630
41c445ff
JB		 1631 switch (vsi->type) {
1632 case I40E_VSI_MAIN:
acd65448
HZ		 1633 qcount = min_t(int, pf->alloc_rss_size,
1634 num_tc_qps);
41c445ff 1635 break;
38e00438
VD		 1636#ifdef I40E_FCOE
1637 case I40E_VSI_FCOE:
1638 qcount = num_tc_qps;
1639 break;
1640#endif
41c445ff
JB		 1641 case I40E_VSI_FDIR:
1642 case I40E_VSI_SRIOV:
1643 case I40E_VSI_VMDQ2:
1644 default:
4e3b35b0 1645 qcount = num_tc_qps;
41c445ff
JB		 1646 WARN_ON(i != 0);
1647 break;
1648 }
4e3b35b0
NP		 1649 vsi->tc_config.tc_info[i].qoffset = offset;
1650 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1651
1e200e4a 1652 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1653 num_qps = qcount;
41c445ff 1654 pow = 0;
41a1d04b 1655 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1656 pow++;
1657 num_qps >>= 1;
1658 }
1659
1660 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1661 qmap =
1662 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1663 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1664
4e3b35b0 1665 offset += qcount;
41c445ff
JB		 1666 } else {
1667 /* TC is not enabled so set the offset to
1668 * default queue and allocate one queue
1669 * for the given TC.
1670 */
1671 vsi->tc_config.tc_info[i].qoffset = 0;
1672 vsi->tc_config.tc_info[i].qcount = 1;
1673 vsi->tc_config.tc_info[i].netdev_tc = 0;
1674
1675 qmap = 0;
1676 }
1677 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1678 }
1679
1680 /* Set actual Tx/Rx queue pairs */
1681 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1682 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1683 if (vsi->req_queue_pairs > 0)
1684 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1685 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1686 vsi->num_queue_pairs = pf->num_lan_msix;
1687 }
41c445ff
JB		 1688
1689 /* Scheduler section valid can only be set for ADD VSI */
1690 if (is_add) {
1691 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1692
1693 ctxt->info.up_enable_bits = enabled_tc;
1694 }
1695 if (vsi->type == I40E_VSI_SRIOV) {
1696 ctxt->info.mapping_flags |=
1697 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1698 for (i = 0; i < vsi->num_queue_pairs; i++)
1699 ctxt->info.queue_mapping[i] =
1700 cpu_to_le16(vsi->base_queue + i);
1701 } else {
1702 ctxt->info.mapping_flags |=
1703 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1704 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1705 }
1706 ctxt->info.valid_sections |= cpu_to_le16(sections);
1707}
1708
1709/**
1710 * i40e_set_rx_mode - NDO callback to set the netdev filters
1711 * @netdev: network interface device structure
1712 **/
38e00438
VD		 1713#ifdef I40E_FCOE
1714void i40e_set_rx_mode(struct net_device *netdev)
1715#else
41c445ff 1716static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1717#endif
41c445ff
JB		 1718{
1719 struct i40e_netdev_priv *np = netdev_priv(netdev);
1720 struct i40e_mac_filter *f, *ftmp;
1721 struct i40e_vsi *vsi = np->vsi;
1722 struct netdev_hw_addr *uca;
1723 struct netdev_hw_addr *mca;
1724 struct netdev_hw_addr *ha;
1725
21659035
KP		 1726 spin_lock_bh(&vsi->mac_filter_list_lock);
1727
41c445ff
JB		 1728 /* add addr if not already in the filter list */
1729 netdev_for_each_uc_addr(uca, netdev) {
1730 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1731 if (i40e_is_vsi_in_vlan(vsi))
1732 i40e_put_mac_in_vlan(vsi, uca->addr,
1733 false, true);
1734 else
1735 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1736 false, true);
1737 }
1738 }
1739
1740 netdev_for_each_mc_addr(mca, netdev) {
1741 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1742 if (i40e_is_vsi_in_vlan(vsi))
1743 i40e_put_mac_in_vlan(vsi, mca->addr,
1744 false, true);
1745 else
1746 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1747 false, true);
1748 }
1749 }
1750
1751 /* remove filter if not in netdev list */
1752 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1753
1754 if (!f->is_netdev)
1755 continue;
1756
2f41f335
SN		 1757 netdev_for_each_mc_addr(mca, netdev)
1758 if (ether_addr_equal(mca->addr, f->macaddr))
1759 goto bottom_of_search_loop;
41c445ff 1760
2f41f335
SN		 1761 netdev_for_each_uc_addr(uca, netdev)
1762 if (ether_addr_equal(uca->addr, f->macaddr))
1763 goto bottom_of_search_loop;
1764
1765 for_each_dev_addr(netdev, ha)
1766 if (ether_addr_equal(ha->addr, f->macaddr))
1767 goto bottom_of_search_loop;
1768
1769 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1770 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1771
1772bottom_of_search_loop:
1773 continue;
41c445ff 1774 }
21659035 1775 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1776
1777 /* check for other flag changes */
1778 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1779 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1780 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1781 }
1782}
1783
21659035
KP		 1784/**
1785 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1786 * @src: source MAC filter entry to be clones
1787 *
1788 * Returns the pointer to newly cloned MAC filter entry or NULL
1789 * in case of error
1790 **/
1791static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1792 struct i40e_mac_filter *src)
1793{
1794 struct i40e_mac_filter *f;
1795
1796 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1797 if (!f)
1798 return NULL;
1799 *f = *src;
1800
1801 INIT_LIST_HEAD(&f->list);
1802
1803 return f;
1804}
1805
1806/**
1807 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1808 * @vsi: pointer to vsi struct
1809 * @from: Pointer to list which contains MAC filter entries - changes to
1810 * those entries needs to be undone.
1811 *
1812 * MAC filter entries from list were slated to be removed from device.
1813 **/
1814static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1815 struct list_head *from)
1816{
1817 struct i40e_mac_filter *f, *ftmp;
1818
1819 list_for_each_entry_safe(f, ftmp, from, list) {
1820 f->changed = true;
1821 /* Move the element back into MAC filter list*/
1822 list_move_tail(&f->list, &vsi->mac_filter_list);
1823 }
1824}
1825
1826/**
1827 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1828 * @vsi: pointer to vsi struct
1829 *
1830 * MAC filter entries from list were slated to be added from device.
1831 **/
1832static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1833{
1834 struct i40e_mac_filter *f, *ftmp;
1835
1836 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1837 if (!f->changed && f->counter)
1838 f->changed = true;
1839 }
1840}
1841
1842/**
1843 * i40e_cleanup_add_list - Deletes the element from add list and release
1844 * memory
1845 * @add_list: Pointer to list which contains MAC filter entries
1846 **/
1847static void i40e_cleanup_add_list(struct list_head *add_list)
1848{
1849 struct i40e_mac_filter *f, *ftmp;
1850
1851 list_for_each_entry_safe(f, ftmp, add_list, list) {
1852 list_del(&f->list);
1853 kfree(f);
1854 }
1855}
1856
41c445ff
JB		 1857/**
1858 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1859 * @vsi: ptr to the VSI
30e2561b 1860 * @grab_rtnl: whether RTNL needs to be grabbed
41c445ff
JB		 1861 *
1862 * Push any outstanding VSI filter changes through the AdminQ.
1863 *
1864 * Returns 0 or error value
1865 **/
30e2561b 1866int i40e_sync_vsi_filters(struct i40e_vsi *vsi, bool grab_rtnl)
41c445ff 1867{
21659035
KP		 1868 struct list_head tmp_del_list, tmp_add_list;
1869 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1870 bool promisc_forced_on = false;
1871 bool add_happened = false;
1872 int filter_list_len = 0;
1873 u32 changed_flags = 0;
21659035 1874 bool err_cond = false;
f1c7e72e 1875 i40e_status ret = 0;
41c445ff
JB		 1876 struct i40e_pf *pf;
1877 int num_add = 0;
1878 int num_del = 0;
f1c7e72e 1879 int aq_err = 0;
41c445ff
JB		 1880 u16 cmd_flags;
1881
1882 /* empty array typed pointers, kcalloc later */
1883 struct i40e_aqc_add_macvlan_element_data *add_list;
1884 struct i40e_aqc_remove_macvlan_element_data *del_list;
1885
1886 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1887 usleep_range(1000, 2000);
1888 pf = vsi->back;
1889
1890 if (vsi->netdev) {
1891 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1892 vsi->current_netdev_flags = vsi->netdev->flags;
1893 }
1894
21659035
KP		 1895 INIT_LIST_HEAD(&tmp_del_list);
1896 INIT_LIST_HEAD(&tmp_add_list);
1897
41c445ff
JB		 1898 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1899 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1900
21659035 1901 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1902 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1903 if (!f->changed)
1904 continue;
1905
1906 if (f->counter != 0)
1907 continue;
1908 f->changed = false;
21659035
KP		 1909
1910 /* Move the element into temporary del_list */
1911 list_move_tail(&f->list, &tmp_del_list);
1912 }
1913
1914 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1915 if (!f->changed)
1916 continue;
1917
1918 if (f->counter == 0)
1919 continue;
1920 f->changed = false;
1921
1922 /* Clone MAC filter entry and add into temporary list */
1923 fclone = i40e_mac_filter_entry_clone(f);
1924 if (!fclone) {
1925 err_cond = true;
1926 break;
1927 }
1928 list_add_tail(&fclone->list, &tmp_add_list);
1929 }
1930
1931 /* if failed to clone MAC filter entry - undo */
1932 if (err_cond) {
1933 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1934 i40e_undo_add_filter_entries(vsi);
1935 }
1936 spin_unlock_bh(&vsi->mac_filter_list_lock);
1937
1938 if (err_cond)
1939 i40e_cleanup_add_list(&tmp_add_list);
1940 }
1941
1942 /* Now process 'del_list' outside the lock */
1943 if (!list_empty(&tmp_del_list)) {
1944 filter_list_len = pf->hw.aq.asq_buf_size /
1945 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1946 del_list = kcalloc(filter_list_len,
1947 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1948 GFP_KERNEL);
1949 if (!del_list) {
1950 i40e_cleanup_add_list(&tmp_add_list);
1951
1952 /* Undo VSI's MAC filter entry element updates */
1953 spin_lock_bh(&vsi->mac_filter_list_lock);
1954 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1955 i40e_undo_add_filter_entries(vsi);
1956 spin_unlock_bh(&vsi->mac_filter_list_lock);
1957 return -ENOMEM;
1958 }
1959
1960 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1961 cmd_flags = 0;
1962
1963 /* add to delete list */
9a173901 1964 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1965 del_list[num_del].vlan_tag =
1966 cpu_to_le16((u16)(f->vlan ==
1967 I40E_VLAN_ANY ? 0 : f->vlan));
1968
41c445ff
JB		 1969 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1970 del_list[num_del].flags = cmd_flags;
1971 num_del++;
1972
41c445ff
JB		 1973 /* flush a full buffer */
1974 if (num_del == filter_list_len) {
f1c7e72e
SN		 1975 ret = i40e_aq_remove_macvlan(&pf->hw,
1976 vsi->seid, del_list, num_del,
1977 NULL);
1978 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1979 num_del = 0;
1980 memset(del_list, 0, sizeof(*del_list));
1981
f1c7e72e 1982 if (ret && aq_err != I40E_AQ_RC_ENOENT)
21659035
KP		 1983 dev_err(&pf->pdev->dev,
1984 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1985 i40e_stat_str(&pf->hw, ret),
1986 i40e_aq_str(&pf->hw, aq_err));
41c445ff 1987 }
21659035
KP		 1988 /* Release memory for MAC filter entries which were
1989 * synced up with HW.
1990 */
1991 list_del(&f->list);
1992 kfree(f);
41c445ff 1993 }
21659035 1994
41c445ff 1995 if (num_del) {
f1c7e72e 1996 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1997 del_list, num_del, NULL);
f1c7e72e 1998 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1999 num_del = 0;
2000
f1c7e72e 2001 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 2002 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2003 "ignoring delete macvlan error, err %s aq_err %s\n",
2004 i40e_stat_str(&pf->hw, ret),
2005 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2006 }
2007
2008 kfree(del_list);
2009 del_list = NULL;
21659035
KP		 2010 }
2011
2012 if (!list_empty(&tmp_add_list)) {
41c445ff
JB		 2013
2014 /* do all the adds now */
2015 filter_list_len = pf->hw.aq.asq_buf_size /
2016 sizeof(struct i40e_aqc_add_macvlan_element_data),
2017 add_list = kcalloc(filter_list_len,
2018 sizeof(struct i40e_aqc_add_macvlan_element_data),
2019 GFP_KERNEL);
21659035
KP		 2020 if (!add_list) {
2021 /* Purge element from temporary lists */
2022 i40e_cleanup_add_list(&tmp_add_list);
2023
2024 /* Undo add filter entries from VSI MAC filter list */
2025 spin_lock_bh(&vsi->mac_filter_list_lock);
2026 i40e_undo_add_filter_entries(vsi);
2027 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 2028 return -ENOMEM;
21659035 2029 }
41c445ff 2030
21659035 2031 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2032
41c445ff
JB		 2033 add_happened = true;
2034 cmd_flags = 0;
2035
2036 /* add to add array */
9a173901 2037 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2038 add_list[num_add].vlan_tag =
2039 cpu_to_le16(
2040 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2041 add_list[num_add].queue_number = 0;
2042
2043 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2044 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2045 num_add++;
2046
2047 /* flush a full buffer */
2048 if (num_add == filter_list_len) {
f1c7e72e
SN		 2049 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2050 add_list, num_add,
2051 NULL);
2052 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2053 num_add = 0;
2054
f1c7e72e 2055 if (ret)
41c445ff
JB		 2056 break;
2057 memset(add_list, 0, sizeof(*add_list));
2058 }
21659035
KP		 2059 /* Entries from tmp_add_list were cloned from MAC
2060 * filter list, hence clean those cloned entries
2061 */
2062 list_del(&f->list);
2063 kfree(f);
41c445ff 2064 }
21659035 2065
41c445ff 2066 if (num_add) {
f1c7e72e
SN		 2067 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2068 add_list, num_add, NULL);
2069 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2070 num_add = 0;
2071 }
2072 kfree(add_list);
2073 add_list = NULL;
2074
f1c7e72e 2075 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 2076 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2077 "add filter failed, err %s aq_err %s\n",
2078 i40e_stat_str(&pf->hw, ret),
2079 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2080 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2081 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2082 &vsi->state)) {
2083 promisc_forced_on = true;
2084 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2085 &vsi->state);
2086 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2087 }
2088 }
2089 }
2090
2091 /* check for changes in promiscuous modes */
2092 if (changed_flags & IFF_ALLMULTI) {
2093 bool cur_multipromisc;
6995b36c 2094
41c445ff 2095 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 2096 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2097 vsi->seid,
2098 cur_multipromisc,
2099 NULL);
2100 if (ret)
41c445ff 2101 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2102 "set multi promisc failed, err %s aq_err %s\n",
2103 i40e_stat_str(&pf->hw, ret),
2104 i40e_aq_str(&pf->hw,
2105 pf->hw.aq.asq_last_status));
41c445ff
JB		 2106 }
2107 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2108 bool cur_promisc;
6995b36c 2109
41c445ff
JB		 2110 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2111 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2112 &vsi->state));
92faef85
ASJ		 2113 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
2114 /* set defport ON for Main VSI instead of true promisc
2115 * this way we will get all unicast/multicast and VLAN
2116 * promisc behavior but will not get VF or VMDq traffic
2117 * replicated on the Main VSI.
2118 */
2119 if (pf->cur_promisc != cur_promisc) {
2120 pf->cur_promisc = cur_promisc;
30e2561b
AS		 2121 if (grab_rtnl)
2122 i40e_do_reset_safe(pf,
2123 BIT(__I40E_PF_RESET_REQUESTED));
2124 else
2125 i40e_do_reset(pf,
92faef85
ASJ		 2126 BIT(__I40E_PF_RESET_REQUESTED));
2127 }
2128 } else {
2129 ret = i40e_aq_set_vsi_unicast_promiscuous(
2130 &vsi->back->hw,
f1c7e72e
SN		 2131 vsi->seid,
2132 cur_promisc, NULL);
92faef85
ASJ		 2133 if (ret)
2134 dev_info(&pf->pdev->dev,
2135 "set unicast promisc failed, err %d, aq_err %d\n",
2136 ret, pf->hw.aq.asq_last_status);
2137 ret = i40e_aq_set_vsi_multicast_promiscuous(
2138 &vsi->back->hw,
2139 vsi->seid,
2140 cur_promisc, NULL);
2141 if (ret)
2142 dev_info(&pf->pdev->dev,
2143 "set multicast promisc failed, err %d, aq_err %d\n",
2144 ret, pf->hw.aq.asq_last_status);
2145 }
f1c7e72e
SN		 2146 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2147 vsi->seid,
2148 cur_promisc, NULL);
2149 if (ret)
1a10370a 2150 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 2151 "set brdcast promisc failed, err %s, aq_err %s\n",
2152 i40e_stat_str(&pf->hw, ret),
2153 i40e_aq_str(&pf->hw,
2154 pf->hw.aq.asq_last_status));
41c445ff
JB		 2155 }
2156
2157 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
2158 return 0;
2159}
2160
2161/**
2162 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2163 * @pf: board private structure
2164 **/
2165static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2166{
2167 int v;
2168
2169 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2170 return;
2171 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2172
505682cd 2173 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 2174 if (pf->vsi[v] &&
2175 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
30e2561b 2176 i40e_sync_vsi_filters(pf->vsi[v], true);
41c445ff
JB		 2177 }
2178}
2179
2180/**
2181 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2182 * @netdev: network interface device structure
2183 * @new_mtu: new value for maximum frame size
2184 *
2185 * Returns 0 on success, negative on failure
2186 **/
2187static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2188{
2189 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2190 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2191 struct i40e_vsi *vsi = np->vsi;
2192
2193 /* MTU < 68 is an error and causes problems on some kernels */
2194 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2195 return -EINVAL;
2196
2197 netdev_info(netdev, "changing MTU from %d to %d\n",
2198 netdev->mtu, new_mtu);
2199 netdev->mtu = new_mtu;
2200 if (netif_running(netdev))
2201 i40e_vsi_reinit_locked(vsi);
2202
2203 return 0;
2204}
2205
beb0dff1
JK		 2206/**
2207 * i40e_ioctl - Access the hwtstamp interface
2208 * @netdev: network interface device structure
2209 * @ifr: interface request data
2210 * @cmd: ioctl command
2211 **/
2212int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2213{
2214 struct i40e_netdev_priv *np = netdev_priv(netdev);
2215 struct i40e_pf *pf = np->vsi->back;
2216
2217 switch (cmd) {
2218 case SIOCGHWTSTAMP:
2219 return i40e_ptp_get_ts_config(pf, ifr);
2220 case SIOCSHWTSTAMP:
2221 return i40e_ptp_set_ts_config(pf, ifr);
2222 default:
2223 return -EOPNOTSUPP;
2224 }
2225}
2226
41c445ff
JB		 2227/**
2228 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2229 * @vsi: the vsi being adjusted
2230 **/
2231void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2232{
2233 struct i40e_vsi_context ctxt;
2234 i40e_status ret;
2235
2236 if ((vsi->info.valid_sections &
2237 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2238 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2239 return; /* already enabled */
2240
2241 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2242 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2243 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2244
2245 ctxt.seid = vsi->seid;
1a2f6248 2246 ctxt.info = vsi->info;
41c445ff
JB		 2247 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2248 if (ret) {
2249 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2250 "update vlan stripping failed, err %s aq_err %s\n",
2251 i40e_stat_str(&vsi->back->hw, ret),
2252 i40e_aq_str(&vsi->back->hw,
2253 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2254 }
2255}
2256
2257/**
2258 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2259 * @vsi: the vsi being adjusted
2260 **/
2261void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2262{
2263 struct i40e_vsi_context ctxt;
2264 i40e_status ret;
2265
2266 if ((vsi->info.valid_sections &
2267 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2268 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2269 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2270 return; /* already disabled */
2271
2272 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2273 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2274 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2275
2276 ctxt.seid = vsi->seid;
1a2f6248 2277 ctxt.info = vsi->info;
41c445ff
JB		 2278 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2279 if (ret) {
2280 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2281 "update vlan stripping failed, err %s aq_err %s\n",
2282 i40e_stat_str(&vsi->back->hw, ret),
2283 i40e_aq_str(&vsi->back->hw,
2284 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2285 }
2286}
2287
2288/**
2289 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2290 * @netdev: network interface to be adjusted
2291 * @features: netdev features to test if VLAN offload is enabled or not
2292 **/
2293static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2294{
2295 struct i40e_netdev_priv *np = netdev_priv(netdev);
2296 struct i40e_vsi *vsi = np->vsi;
2297
2298 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2299 i40e_vlan_stripping_enable(vsi);
2300 else
2301 i40e_vlan_stripping_disable(vsi);
2302}
2303
2304/**
2305 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2306 * @vsi: the vsi being configured
2307 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2308 **/
2309int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2310{
2311 struct i40e_mac_filter *f, *add_f;
2312 bool is_netdev, is_vf;
41c445ff
JB		 2313
2314 is_vf = (vsi->type == I40E_VSI_SRIOV);
2315 is_netdev = !!(vsi->netdev);
2316
21659035
KP		 2317 /* Locked once because all functions invoked below iterates list*/
2318 spin_lock_bh(&vsi->mac_filter_list_lock);
2319
41c445ff
JB		 2320 if (is_netdev) {
2321 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2322 is_vf, is_netdev);
2323 if (!add_f) {
2324 dev_info(&vsi->back->pdev->dev,
2325 "Could not add vlan filter %d for %pM\n",
2326 vid, vsi->netdev->dev_addr);
21659035 2327 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2328 return -ENOMEM;
2329 }
2330 }
2331
2332 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2333 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2334 if (!add_f) {
2335 dev_info(&vsi->back->pdev->dev,
2336 "Could not add vlan filter %d for %pM\n",
2337 vid, f->macaddr);
21659035 2338 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2339 return -ENOMEM;
2340 }
2341 }
2342
41c445ff
JB		 2343 /* Now if we add a vlan tag, make sure to check if it is the first
2344 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2345 * with 0, so we now accept untagged and specified tagged traffic
2346 * (and not any taged and untagged)
2347 */
2348 if (vid > 0) {
2349 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2350 I40E_VLAN_ANY,
2351 is_vf, is_netdev)) {
2352 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2353 I40E_VLAN_ANY, is_vf, is_netdev);
2354 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2355 is_vf, is_netdev);
2356 if (!add_f) {
2357 dev_info(&vsi->back->pdev->dev,
2358 "Could not add filter 0 for %pM\n",
2359 vsi->netdev->dev_addr);
21659035 2360 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2361 return -ENOMEM;
2362 }
2363 }
8d82a7c5 2364 }
41c445ff 2365
8d82a7c5
GR		 2366 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2367 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2368 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2369 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2370 is_vf, is_netdev))
2371 continue;
2372 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2373 is_vf, is_netdev);
2374 add_f = i40e_add_filter(vsi, f->macaddr,
2375 0, is_vf, is_netdev);
2376 if (!add_f) {
2377 dev_info(&vsi->back->pdev->dev,
2378 "Could not add filter 0 for %pM\n",
2379 f->macaddr);
2380 spin_unlock_bh(&vsi->mac_filter_list_lock);
2381 return -ENOMEM;
41c445ff
JB		 2382 }
2383 }
41c445ff
JB		 2384 }
2385
21659035
KP		 2386 /* Make sure to release before sync_vsi_filter because that
2387 * function will lock/unlock as necessary
2388 */
2389 spin_unlock_bh(&vsi->mac_filter_list_lock);
2390
80f6428f
ASJ		 2391 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2392 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2393 return 0;
2394
30e2561b 2395 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2396}
2397
2398/**
2399 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2400 * @vsi: the vsi being configured
2401 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2402 *
2403 * Return: 0 on success or negative otherwise
41c445ff
JB		 2404 **/
2405int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2406{
2407 struct net_device *netdev = vsi->netdev;
2408 struct i40e_mac_filter *f, *add_f;
2409 bool is_vf, is_netdev;
2410 int filter_count = 0;
41c445ff
JB		 2411
2412 is_vf = (vsi->type == I40E_VSI_SRIOV);
2413 is_netdev = !!(netdev);
2414
21659035
KP		 2415 /* Locked once because all functions invoked below iterates list */
2416 spin_lock_bh(&vsi->mac_filter_list_lock);
2417
41c445ff
JB		 2418 if (is_netdev)
2419 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2420
2421 list_for_each_entry(f, &vsi->mac_filter_list, list)
2422 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2423
41c445ff
JB		 2424 /* go through all the filters for this VSI and if there is only
2425 * vid == 0 it means there are no other filters, so vid 0 must
2426 * be replaced with -1. This signifies that we should from now
2427 * on accept any traffic (with any tag present, or untagged)
2428 */
2429 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2430 if (is_netdev) {
2431 if (f->vlan &&
2432 ether_addr_equal(netdev->dev_addr, f->macaddr))
2433 filter_count++;
2434 }
2435
2436 if (f->vlan)
2437 filter_count++;
2438 }
2439
2440 if (!filter_count && is_netdev) {
2441 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2442 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2443 is_vf, is_netdev);
2444 if (!f) {
2445 dev_info(&vsi->back->pdev->dev,
2446 "Could not add filter %d for %pM\n",
2447 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2448 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2449 return -ENOMEM;
2450 }
2451 }
2452
2453 if (!filter_count) {
2454 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2455 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2456 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2457 is_vf, is_netdev);
41c445ff
JB		 2458 if (!add_f) {
2459 dev_info(&vsi->back->pdev->dev,
2460 "Could not add filter %d for %pM\n",
2461 I40E_VLAN_ANY, f->macaddr);
21659035 2462 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2463 return -ENOMEM;
2464 }
2465 }
2466 }
2467
21659035
KP		 2468 /* Make sure to release before sync_vsi_filter because that
2469 * function with lock/unlock as necessary
2470 */
2471 spin_unlock_bh(&vsi->mac_filter_list_lock);
2472
80f6428f
ASJ		 2473 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2474 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2475 return 0;
2476
30e2561b 2477 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2478}
2479
2480/**
2481 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2482 * @netdev: network interface to be adjusted
2483 * @vid: vlan id to be added
078b5876
JB		 2484 *
2485 * net_device_ops implementation for adding vlan ids
41c445ff 2486 **/
38e00438
VD		 2487#ifdef I40E_FCOE
2488int i40e_vlan_rx_add_vid(struct net_device *netdev,
2489 __always_unused __be16 proto, u16 vid)
2490#else
41c445ff
JB		 2491static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2492 __always_unused __be16 proto, u16 vid)
38e00438 2493#endif
41c445ff
JB		 2494{
2495 struct i40e_netdev_priv *np = netdev_priv(netdev);
2496 struct i40e_vsi *vsi = np->vsi;
078b5876 2497 int ret = 0;
41c445ff
JB		 2498
2499 if (vid > 4095)
078b5876
JB		 2500 return -EINVAL;
2501
2502 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2503
6982d429
ASJ		 2504 /* If the network stack called us with vid = 0 then
2505 * it is asking to receive priority tagged packets with
2506 * vlan id 0. Our HW receives them by default when configured
2507 * to receive untagged packets so there is no need to add an
2508 * extra filter for vlan 0 tagged packets.
41c445ff 2509 */
6982d429
ASJ		 2510 if (vid)
2511 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2512
078b5876
JB		 2513 if (!ret && (vid < VLAN_N_VID))
2514 set_bit(vid, vsi->active_vlans);
41c445ff 2515
078b5876 2516 return ret;
41c445ff
JB		 2517}
2518
2519/**
2520 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2521 * @netdev: network interface to be adjusted
2522 * @vid: vlan id to be removed
078b5876 2523 *
fdfd943e 2524 * net_device_ops implementation for removing vlan ids
41c445ff 2525 **/
38e00438
VD		 2526#ifdef I40E_FCOE
2527int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2528 __always_unused __be16 proto, u16 vid)
2529#else
41c445ff
JB		 2530static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2531 __always_unused __be16 proto, u16 vid)
38e00438 2532#endif
41c445ff
JB		 2533{
2534 struct i40e_netdev_priv *np = netdev_priv(netdev);
2535 struct i40e_vsi *vsi = np->vsi;
2536
078b5876
JB		 2537 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2538
41c445ff
JB		 2539 /* return code is ignored as there is nothing a user
2540 * can do about failure to remove and a log message was
078b5876 2541 * already printed from the other function
41c445ff
JB		 2542 */
2543 i40e_vsi_kill_vlan(vsi, vid);
2544
2545 clear_bit(vid, vsi->active_vlans);
078b5876 2546
41c445ff
JB		 2547 return 0;
2548}
2549
2550/**
2551 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2552 * @vsi: the vsi being brought back up
2553 **/
2554static void i40e_restore_vlan(struct i40e_vsi *vsi)
2555{
2556 u16 vid;
2557
2558 if (!vsi->netdev)
2559 return;
2560
2561 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2562
2563 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2564 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2565 vid);
2566}
2567
2568/**
2569 * i40e_vsi_add_pvid - Add pvid for the VSI
2570 * @vsi: the vsi being adjusted
2571 * @vid: the vlan id to set as a PVID
2572 **/
dcae29be 2573int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2574{
2575 struct i40e_vsi_context ctxt;
f1c7e72e 2576 i40e_status ret;
41c445ff
JB		 2577
2578 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2579 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2580 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2581 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2582 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2583
2584 ctxt.seid = vsi->seid;
1a2f6248 2585 ctxt.info = vsi->info;
f1c7e72e
SN		 2586 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2587 if (ret) {
41c445ff 2588 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2589 "add pvid failed, err %s aq_err %s\n",
2590 i40e_stat_str(&vsi->back->hw, ret),
2591 i40e_aq_str(&vsi->back->hw,
2592 vsi->back->hw.aq.asq_last_status));
dcae29be 2593 return -ENOENT;
41c445ff
JB		 2594 }
2595
dcae29be 2596 return 0;
41c445ff
JB		 2597}
2598
2599/**
2600 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2601 * @vsi: the vsi being adjusted
2602 *
2603 * Just use the vlan_rx_register() service to put it back to normal
2604 **/
2605void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2606{
6c12fcbf
GR		 2607 i40e_vlan_stripping_disable(vsi);
2608
41c445ff 2609 vsi->info.pvid = 0;
41c445ff
JB		 2610}
2611
2612/**
2613 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2614 * @vsi: ptr to the VSI
2615 *
2616 * If this function returns with an error, then it's possible one or
2617 * more of the rings is populated (while the rest are not). It is the
2618 * callers duty to clean those orphaned rings.
2619 *
2620 * Return 0 on success, negative on failure
2621 **/
2622static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2623{
2624 int i, err = 0;
2625
2626 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2627 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2628
2629 return err;
2630}
2631
2632/**
2633 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2634 * @vsi: ptr to the VSI
2635 *
2636 * Free VSI's transmit software resources
2637 **/
2638static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2639{
2640 int i;
2641
8e9dca53
GR		 2642 if (!vsi->tx_rings)
2643 return;
2644
41c445ff 2645 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2646 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2647 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2648}
2649
2650/**
2651 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2652 * @vsi: ptr to the VSI
2653 *
2654 * If this function returns with an error, then it's possible one or
2655 * more of the rings is populated (while the rest are not). It is the
2656 * callers duty to clean those orphaned rings.
2657 *
2658 * Return 0 on success, negative on failure
2659 **/
2660static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2661{
2662 int i, err = 0;
2663
2664 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2665 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2666#ifdef I40E_FCOE
2667 i40e_fcoe_setup_ddp_resources(vsi);
2668#endif
41c445ff
JB		 2669 return err;
2670}
2671
2672/**
2673 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2674 * @vsi: ptr to the VSI
2675 *
2676 * Free all receive software resources
2677 **/
2678static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2679{
2680 int i;
2681
8e9dca53
GR		 2682 if (!vsi->rx_rings)
2683 return;
2684
41c445ff 2685 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2686 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2687 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2688#ifdef I40E_FCOE
2689 i40e_fcoe_free_ddp_resources(vsi);
2690#endif
41c445ff
JB		 2691}
2692
3ffa037d
NP		 2693/**
2694 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2695 * @ring: The Tx ring to configure
2696 *
2697 * This enables/disables XPS for a given Tx descriptor ring
2698 * based on the TCs enabled for the VSI that ring belongs to.
2699 **/
2700static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2701{
2702 struct i40e_vsi *vsi = ring->vsi;
2703 cpumask_var_t mask;
2704
9a660eea
JB		 2705 if (!ring->q_vector || !ring->netdev)
2706 return;
2707
2708 /* Single TC mode enable XPS */
2709 if (vsi->tc_config.numtc <= 1) {
2710 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2711 netif_set_xps_queue(ring->netdev,
2712 &ring->q_vector->affinity_mask,
2713 ring->queue_index);
9a660eea
JB		 2714 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2715 /* Disable XPS to allow selection based on TC */
2716 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2717 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2718 free_cpumask_var(mask);
3ffa037d
NP		 2719 }
2720}
2721
41c445ff
JB		 2722/**
2723 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2724 * @ring: The Tx ring to configure
2725 *
2726 * Configure the Tx descriptor ring in the HMC context.
2727 **/
2728static int i40e_configure_tx_ring(struct i40e_ring *ring)
2729{
2730 struct i40e_vsi *vsi = ring->vsi;
2731 u16 pf_q = vsi->base_queue + ring->queue_index;
2732 struct i40e_hw *hw = &vsi->back->hw;
2733 struct i40e_hmc_obj_txq tx_ctx;
2734 i40e_status err = 0;
2735 u32 qtx_ctl = 0;
2736
2737 /* some ATR related tx ring init */
60ea5f83 2738 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2739 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2740 ring->atr_count = 0;
2741 } else {
2742 ring->atr_sample_rate = 0;
2743 }
2744
3ffa037d
NP		 2745 /* configure XPS */
2746 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2747
2748 /* clear the context structure first */
2749 memset(&tx_ctx, 0, sizeof(tx_ctx));
2750
2751 tx_ctx.new_context = 1;
2752 tx_ctx.base = (ring->dma / 128);
2753 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2754 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2755 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2756#ifdef I40E_FCOE
2757 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2758#endif
beb0dff1 2759 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2760 /* FDIR VSI tx ring can still use RS bit and writebacks */
2761 if (vsi->type != I40E_VSI_FDIR)
2762 tx_ctx.head_wb_ena = 1;
2763 tx_ctx.head_wb_addr = ring->dma +
2764 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2765
2766 /* As part of VSI creation/update, FW allocates certain
2767 * Tx arbitration queue sets for each TC enabled for
2768 * the VSI. The FW returns the handles to these queue
2769 * sets as part of the response buffer to Add VSI,
2770 * Update VSI, etc. AQ commands. It is expected that
2771 * these queue set handles be associated with the Tx
2772 * queues by the driver as part of the TX queue context
2773 * initialization. This has to be done regardless of
2774 * DCB as by default everything is mapped to TC0.
2775 */
2776 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2777 tx_ctx.rdylist_act = 0;
2778
2779 /* clear the context in the HMC */
2780 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2781 if (err) {
2782 dev_info(&vsi->back->pdev->dev,
2783 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2784 ring->queue_index, pf_q, err);
2785 return -ENOMEM;
2786 }
2787
2788 /* set the context in the HMC */
2789 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2790 if (err) {
2791 dev_info(&vsi->back->pdev->dev,
2792 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2793 ring->queue_index, pf_q, err);
2794 return -ENOMEM;
2795 }
2796
2797 /* Now associate this queue with this PCI function */
7a28d885 2798 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2799 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2800 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2801 I40E_QTX_CTL_VFVM_INDX_MASK;
2802 } else {
9d8bf547 2803 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2804 }
2805
13fd9774
SN		 2806 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2807 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2808 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2809 i40e_flush(hw);
2810
41c445ff
JB		 2811 /* cache tail off for easier writes later */
2812 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2813
2814 return 0;
2815}
2816
2817/**
2818 * i40e_configure_rx_ring - Configure a receive ring context
2819 * @ring: The Rx ring to configure
2820 *
2821 * Configure the Rx descriptor ring in the HMC context.
2822 **/
2823static int i40e_configure_rx_ring(struct i40e_ring *ring)
2824{
2825 struct i40e_vsi *vsi = ring->vsi;
2826 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2827 u16 pf_q = vsi->base_queue + ring->queue_index;
2828 struct i40e_hw *hw = &vsi->back->hw;
2829 struct i40e_hmc_obj_rxq rx_ctx;
2830 i40e_status err = 0;
2831
2832 ring->state = 0;
2833
2834 /* clear the context structure first */
2835 memset(&rx_ctx, 0, sizeof(rx_ctx));
2836
2837 ring->rx_buf_len = vsi->rx_buf_len;
2838 ring->rx_hdr_len = vsi->rx_hdr_len;
2839
2840 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2841 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2842
2843 rx_ctx.base = (ring->dma / 128);
2844 rx_ctx.qlen = ring->count;
2845
2846 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2847 set_ring_16byte_desc_enabled(ring);
2848 rx_ctx.dsize = 0;
2849 } else {
2850 rx_ctx.dsize = 1;
2851 }
2852
2853 rx_ctx.dtype = vsi->dtype;
2854 if (vsi->dtype) {
2855 set_ring_ps_enabled(ring);
2856 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2857 I40E_RX_SPLIT_IP |
2858 I40E_RX_SPLIT_TCP_UDP |
2859 I40E_RX_SPLIT_SCTP;
2860 } else {
2861 rx_ctx.hsplit_0 = 0;
2862 }
2863
2864 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2865 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2866 if (hw->revision_id == 0)
2867 rx_ctx.lrxqthresh = 0;
2868 else
2869 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2870 rx_ctx.crcstrip = 1;
2871 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2872 /* this controls whether VLAN is stripped from inner headers */
2873 rx_ctx.showiv = 0;
38e00438
VD		 2874#ifdef I40E_FCOE
2875 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2876#endif
acb3676b
CS		 2877 /* set the prefena field to 1 because the manual says to */
2878 rx_ctx.prefena = 1;
41c445ff
JB		 2879
2880 /* clear the context in the HMC */
2881 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2882 if (err) {
2883 dev_info(&vsi->back->pdev->dev,
2884 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2885 ring->queue_index, pf_q, err);
2886 return -ENOMEM;
2887 }
2888
2889 /* set the context in the HMC */
2890 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2891 if (err) {
2892 dev_info(&vsi->back->pdev->dev,
2893 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2894 ring->queue_index, pf_q, err);
2895 return -ENOMEM;
2896 }
2897
2898 /* cache tail for quicker writes, and clear the reg before use */
2899 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2900 writel(0, ring->tail);
2901
a132af24
MW		 2902 if (ring_is_ps_enabled(ring)) {
2903 i40e_alloc_rx_headers(ring);
2904 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2905 } else {
2906 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2907 }
41c445ff
JB		 2908
2909 return 0;
2910}
2911
2912/**
2913 * i40e_vsi_configure_tx - Configure the VSI for Tx
2914 * @vsi: VSI structure describing this set of rings and resources
2915 *
2916 * Configure the Tx VSI for operation.
2917 **/
2918static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2919{
2920 int err = 0;
2921 u16 i;
2922
9f65e15b
AD		 2923 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2924 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2925
2926 return err;
2927}
2928
2929/**
2930 * i40e_vsi_configure_rx - Configure the VSI for Rx
2931 * @vsi: the VSI being configured
2932 *
2933 * Configure the Rx VSI for operation.
2934 **/
2935static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2936{
2937 int err = 0;
2938 u16 i;
2939
2940 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2941 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2942 + ETH_FCS_LEN + VLAN_HLEN;
2943 else
2944 vsi->max_frame = I40E_RXBUFFER_2048;
2945
2946 /* figure out correct receive buffer length */
2947 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2948 I40E_FLAG_RX_PS_ENABLED)) {
2949 case I40E_FLAG_RX_1BUF_ENABLED:
2950 vsi->rx_hdr_len = 0;
2951 vsi->rx_buf_len = vsi->max_frame;
2952 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2953 break;
2954 case I40E_FLAG_RX_PS_ENABLED:
2955 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2956 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2957 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2958 break;
2959 default:
2960 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2961 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2962 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2963 break;
2964 }
2965
38e00438
VD		 2966#ifdef I40E_FCOE
2967 /* setup rx buffer for FCoE */
2968 if ((vsi->type == I40E_VSI_FCOE) &&
2969 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2970 vsi->rx_hdr_len = 0;
2971 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2972 vsi->max_frame = I40E_RXBUFFER_3072;
2973 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2974 }
2975
2976#endif /* I40E_FCOE */
41c445ff
JB		 2977 /* round up for the chip's needs */
2978 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2979 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2980 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2981 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2982
2983 /* set up individual rings */
2984 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2985 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2986
2987 return err;
2988}
2989
2990/**
2991 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2992 * @vsi: ptr to the VSI
2993 **/
2994static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2995{
e7046ee1 2996 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2997 u16 qoffset, qcount;
2998 int i, n;
2999
cd238a3e
PN		 3000 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3001 /* Reset the TC information */
3002 for (i = 0; i < vsi->num_queue_pairs; i++) {
3003 rx_ring = vsi->rx_rings[i];
3004 tx_ring = vsi->tx_rings[i];
3005 rx_ring->dcb_tc = 0;
3006 tx_ring->dcb_tc = 0;
3007 }
3008 }
41c445ff
JB		 3009
3010 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3011 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3012 continue;
3013
3014 qoffset = vsi->tc_config.tc_info[n].qoffset;
3015 qcount = vsi->tc_config.tc_info[n].qcount;
3016 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3017 rx_ring = vsi->rx_rings[i];
3018 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3019 rx_ring->dcb_tc = n;
3020 tx_ring->dcb_tc = n;
3021 }
3022 }
3023}
3024
3025/**
3026 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3027 * @vsi: ptr to the VSI
3028 **/
3029static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3030{
3031 if (vsi->netdev)
3032 i40e_set_rx_mode(vsi->netdev);
3033}
3034
17a73f6b
JG		 3035/**
3036 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3037 * @vsi: Pointer to the targeted VSI
3038 *
3039 * This function replays the hlist on the hw where all the SB Flow Director
3040 * filters were saved.
3041 **/
3042static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3043{
3044 struct i40e_fdir_filter *filter;
3045 struct i40e_pf *pf = vsi->back;
3046 struct hlist_node *node;
3047
55a5e60b
ASJ		 3048 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3049 return;
3050
17a73f6b
JG		 3051 hlist_for_each_entry_safe(filter, node,
3052 &pf->fdir_filter_list, fdir_node) {
3053 i40e_add_del_fdir(vsi, filter, true);
3054 }
3055}
3056
41c445ff
JB		 3057/**
3058 * i40e_vsi_configure - Set up the VSI for action
3059 * @vsi: the VSI being configured
3060 **/
3061static int i40e_vsi_configure(struct i40e_vsi *vsi)
3062{
3063 int err;
3064
3065 i40e_set_vsi_rx_mode(vsi);
3066 i40e_restore_vlan(vsi);
3067 i40e_vsi_config_dcb_rings(vsi);
3068 err = i40e_vsi_configure_tx(vsi);
3069 if (!err)
3070 err = i40e_vsi_configure_rx(vsi);
3071
3072 return err;
3073}
3074
3075/**
3076 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3077 * @vsi: the VSI being configured
3078 **/
3079static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3080{
3081 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3082 struct i40e_hw *hw = &pf->hw;
3083 u16 vector;
3084 int i, q;
41c445ff
JB		 3085 u32 qp;
3086
3087 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3088 * and PFINT_LNKLSTn registers, e.g.:
3089 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3090 */
3091 qp = vsi->base_queue;
3092 vector = vsi->base_vector;
493fb300 3093 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3094 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3095
ee2319cf 3096 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3097 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3098 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3099 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3100 q_vector->rx.itr);
3101 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3102 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3103 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3104 q_vector->tx.itr);
ac26fc13
JB		 3105 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3106 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3107
3108 /* Linked list for the queuepairs assigned to this vector */
3109 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3110 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3111 u32 val;
3112
41c445ff
JB		 3113 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3114 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3115 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3116 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3117 (I40E_QUEUE_TYPE_TX
3118 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3119
3120 wr32(hw, I40E_QINT_RQCTL(qp), val);
3121
3122 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3123 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3124 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3125 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3126 (I40E_QUEUE_TYPE_RX
3127 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3128
3129 /* Terminate the linked list */
3130 if (q == (q_vector->num_ringpairs - 1))
3131 val |= (I40E_QUEUE_END_OF_LIST
3132 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3133
3134 wr32(hw, I40E_QINT_TQCTL(qp), val);
3135 qp++;
3136 }
3137 }
3138
3139 i40e_flush(hw);
3140}
3141
3142/**
3143 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3144 * @hw: ptr to the hardware info
3145 **/
ab437b5a 3146static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3147{
ab437b5a 3148 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3149 u32 val;
3150
3151 /* clear things first */
3152 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3153 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3154
3155 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3156 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3157 I40E_PFINT_ICR0_ENA_GRST_MASK |
3158 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3159 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3160 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3161 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3162 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3163
0d8e1439
ASJ		 3164 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3165 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3166
ab437b5a
JK		 3167 if (pf->flags & I40E_FLAG_PTP)
3168 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3169
41c445ff
JB		 3170 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3171
3172 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3173 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3174 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3175
3176 /* OTHER_ITR_IDX = 0 */
3177 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3178}
3179
3180/**
3181 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3182 * @vsi: the VSI being configured
3183 **/
3184static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3185{
493fb300 3186 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3187 struct i40e_pf *pf = vsi->back;
3188 struct i40e_hw *hw = &pf->hw;
3189 u32 val;
3190
3191 /* set the ITR configuration */
ee2319cf 3192 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3193 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3194 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3195 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3196 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3197 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3198 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3199
ab437b5a 3200 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3201
3202 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3203 wr32(hw, I40E_PFINT_LNKLST0, 0);
3204
f29eaa3d 3205 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3206 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3207 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3208 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3209
3210 wr32(hw, I40E_QINT_RQCTL(0), val);
3211
3212 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3213 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3214 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3215
3216 wr32(hw, I40E_QINT_TQCTL(0), val);
3217 i40e_flush(hw);
3218}
3219
2ef28cfb
MW		 3220/**
3221 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3222 * @pf: board private structure
3223 **/
3224void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3225{
3226 struct i40e_hw *hw = &pf->hw;
3227
3228 wr32(hw, I40E_PFINT_DYN_CTL0,
3229 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3230 i40e_flush(hw);
3231}
3232
41c445ff
JB		 3233/**
3234 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3235 * @pf: board private structure
3236 **/
116a57d4 3237void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3238{
3239 struct i40e_hw *hw = &pf->hw;
3240 u32 val;
3241
3242 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3243 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3244 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3245
3246 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3247 i40e_flush(hw);
3248}
3249
5c2cebda
CW		 3250/**
3251 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3252 * @vsi: pointer to a vsi
03147773 3253 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3254 **/
3255void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3256{
3257 struct i40e_pf *pf = vsi->back;
3258 struct i40e_hw *hw = &pf->hw;
3259 u32 val;
3260
3261 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3262 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3263 i40e_flush(hw);
3264}
3265
41c445ff
JB		 3266/**
3267 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3268 * @irq: interrupt number
3269 * @data: pointer to a q_vector
3270 **/
3271static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3272{
3273 struct i40e_q_vector *q_vector = data;
3274
cd0b6fa6 3275 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3276 return IRQ_HANDLED;
3277
5d3465a1 3278 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3279
3280 return IRQ_HANDLED;
3281}
3282
41c445ff
JB		 3283/**
3284 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3285 * @vsi: the VSI being configured
3286 * @basename: name for the vector
3287 *
3288 * Allocates MSI-X vectors and requests interrupts from the kernel.
3289 **/
3290static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3291{
3292 int q_vectors = vsi->num_q_vectors;
3293 struct i40e_pf *pf = vsi->back;
3294 int base = vsi->base_vector;
3295 int rx_int_idx = 0;
3296 int tx_int_idx = 0;
3297 int vector, err;
3298
3299 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3300 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3301
cd0b6fa6 3302 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3303 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3304 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3305 tx_int_idx++;
cd0b6fa6 3306 } else if (q_vector->rx.ring) {
41c445ff
JB		 3307 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3308 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3309 } else if (q_vector->tx.ring) {
41c445ff
JB		 3310 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3311 "%s-%s-%d", basename, "tx", tx_int_idx++);
3312 } else {
3313 /* skip this unused q_vector */
3314 continue;
3315 }
3316 err = request_irq(pf->msix_entries[base + vector].vector,
3317 vsi->irq_handler,
3318 0,
3319 q_vector->name,
3320 q_vector);
3321 if (err) {
3322 dev_info(&pf->pdev->dev,
fb43201f 3323 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3324 goto free_queue_irqs;
3325 }
3326 /* assign the mask for this irq */
3327 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3328 &q_vector->affinity_mask);
3329 }
3330
63741846 3331 vsi->irqs_ready = true;
41c445ff
JB		 3332 return 0;
3333
3334free_queue_irqs:
3335 while (vector) {
3336 vector--;
3337 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3338 NULL);
3339 free_irq(pf->msix_entries[base + vector].vector,
3340 &(vsi->q_vectors[vector]));
3341 }
3342 return err;
3343}
3344
3345/**
3346 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3347 * @vsi: the VSI being un-configured
3348 **/
3349static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3350{
3351 struct i40e_pf *pf = vsi->back;
3352 struct i40e_hw *hw = &pf->hw;
3353 int base = vsi->base_vector;
3354 int i;
3355
3356 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3357 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3358 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3359 }
3360
3361 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3362 for (i = vsi->base_vector;
3363 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3364 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3365
3366 i40e_flush(hw);
3367 for (i = 0; i < vsi->num_q_vectors; i++)
3368 synchronize_irq(pf->msix_entries[i + base].vector);
3369 } else {
3370 /* Legacy and MSI mode - this stops all interrupt handling */
3371 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3372 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3373 i40e_flush(hw);
3374 synchronize_irq(pf->pdev->irq);
3375 }
3376}
3377
3378/**
3379 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3380 * @vsi: the VSI being configured
3381 **/
3382static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3383{
3384 struct i40e_pf *pf = vsi->back;
3385 int i;
3386
3387 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3388 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3389 i40e_irq_dynamic_enable(vsi, i);
3390 } else {
3391 i40e_irq_dynamic_enable_icr0(pf);
3392 }
3393
1022cb6c 3394 i40e_flush(&pf->hw);
41c445ff
JB		 3395 return 0;
3396}
3397
3398/**
3399 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3400 * @pf: board private structure
3401 **/
3402static void i40e_stop_misc_vector(struct i40e_pf *pf)
3403{
3404 /* Disable ICR 0 */
3405 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3406 i40e_flush(&pf->hw);
3407}
3408
3409/**
3410 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3411 * @irq: interrupt number
3412 * @data: pointer to a q_vector
3413 *
3414 * This is the handler used for all MSI/Legacy interrupts, and deals
3415 * with both queue and non-queue interrupts. This is also used in
3416 * MSIX mode to handle the non-queue interrupts.
3417 **/
3418static irqreturn_t i40e_intr(int irq, void *data)
3419{
3420 struct i40e_pf *pf = (struct i40e_pf *)data;
3421 struct i40e_hw *hw = &pf->hw;
5e823066 3422 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3423 u32 icr0, icr0_remaining;
3424 u32 val, ena_mask;
3425
3426 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3427 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3428
116a57d4
SN		 3429 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3430 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3431 goto enable_intr;
41c445ff 3432
cd92e72f
SN		 3433 /* if interrupt but no bits showing, must be SWINT */
3434 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3435 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3436 pf->sw_int_count++;
3437
0d8e1439
ASJ		 3438 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3439 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3440 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3441 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3442 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3443 }
3444
41c445ff
JB		 3445 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3446 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3447 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3448 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3449
3450 /* temporarily disable queue cause for NAPI processing */
3451 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3452
41c445ff
JB		 3453 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3454 wr32(hw, I40E_QINT_RQCTL(0), qval);
3455
3456 qval = rd32(hw, I40E_QINT_TQCTL(0));
3457 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3458 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3459
3460 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3461 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3462 }
3463
3464 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3465 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3466 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3467 }
3468
3469 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3470 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3471 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3472 }
3473
3474 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3475 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3476 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3477 }
3478
3479 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3480 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3481 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3482 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3483 val = rd32(hw, I40E_GLGEN_RSTAT);
3484 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3485 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3486 if (val == I40E_RESET_CORER) {
41c445ff 3487 pf->corer_count++;
4eb3f768 3488 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3489 pf->globr_count++;
4eb3f768 3490 } else if (val == I40E_RESET_EMPR) {
41c445ff 3491 pf->empr_count++;
9df42d1a 3492 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3493 }
41c445ff
JB		 3494 }
3495
9c010ee0
ASJ		 3496 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3497 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3498 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3499 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3500 rd32(hw, I40E_PFHMC_ERRORINFO),
3501 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3502 }
3503
beb0dff1
JK		 3504 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3505 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3506
3507 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3508 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3509 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3510 }
beb0dff1
JK		 3511 }
3512
41c445ff
JB		 3513 /* If a critical error is pending we have no choice but to reset the
3514 * device.
3515 * Report and mask out any remaining unexpected interrupts.
3516 */
3517 icr0_remaining = icr0 & ena_mask;
3518 if (icr0_remaining) {
3519 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3520 icr0_remaining);
9c010ee0 3521 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3522 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3523 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3524 dev_info(&pf->pdev->dev, "device will be reset\n");
3525 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3526 i40e_service_event_schedule(pf);
41c445ff
JB		 3527 }
3528 ena_mask &= ~icr0_remaining;
3529 }
5e823066 3530 ret = IRQ_HANDLED;
41c445ff 3531
5e823066 3532enable_intr:
41c445ff
JB		 3533 /* re-enable interrupt causes */
3534 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3535 if (!test_bit(__I40E_DOWN, &pf->state)) {
3536 i40e_service_event_schedule(pf);
3537 i40e_irq_dynamic_enable_icr0(pf);
3538 }
3539
5e823066 3540 return ret;
41c445ff
JB		 3541}
3542
cbf61325
ASJ		 3543/**
3544 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3545 * @tx_ring: tx ring to clean
3546 * @budget: how many cleans we're allowed
3547 *
3548 * Returns true if there's any budget left (e.g. the clean is finished)
3549 **/
3550static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3551{
3552 struct i40e_vsi *vsi = tx_ring->vsi;
3553 u16 i = tx_ring->next_to_clean;
3554 struct i40e_tx_buffer *tx_buf;
3555 struct i40e_tx_desc *tx_desc;
3556
3557 tx_buf = &tx_ring->tx_bi[i];
3558 tx_desc = I40E_TX_DESC(tx_ring, i);
3559 i -= tx_ring->count;
3560
3561 do {
3562 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3563
3564 /* if next_to_watch is not set then there is no work pending */
3565 if (!eop_desc)
3566 break;
3567
3568 /* prevent any other reads prior to eop_desc */
3569 read_barrier_depends();
3570
3571 /* if the descriptor isn't done, no work yet to do */
3572 if (!(eop_desc->cmd_type_offset_bsz &
3573 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3574 break;
3575
3576 /* clear next_to_watch to prevent false hangs */
3577 tx_buf->next_to_watch = NULL;
3578
49d7d933
ASJ		 3579 tx_desc->buffer_addr = 0;
3580 tx_desc->cmd_type_offset_bsz = 0;
3581 /* move past filter desc */
3582 tx_buf++;
3583 tx_desc++;
3584 i++;
3585 if (unlikely(!i)) {
3586 i -= tx_ring->count;
3587 tx_buf = tx_ring->tx_bi;
3588 tx_desc = I40E_TX_DESC(tx_ring, 0);
3589 }
cbf61325
ASJ		 3590 /* unmap skb header data */
3591 dma_unmap_single(tx_ring->dev,
3592 dma_unmap_addr(tx_buf, dma),
3593 dma_unmap_len(tx_buf, len),
3594 DMA_TO_DEVICE);
49d7d933
ASJ		 3595 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3596 kfree(tx_buf->raw_buf);
cbf61325 3597
49d7d933
ASJ		 3598 tx_buf->raw_buf = NULL;
3599 tx_buf->tx_flags = 0;
3600 tx_buf->next_to_watch = NULL;
cbf61325 3601 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3602 tx_desc->buffer_addr = 0;
3603 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3604
49d7d933 3605 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3606 tx_buf++;
3607 tx_desc++;
3608 i++;
3609 if (unlikely(!i)) {
3610 i -= tx_ring->count;
3611 tx_buf = tx_ring->tx_bi;
3612 tx_desc = I40E_TX_DESC(tx_ring, 0);
3613 }
3614
3615 /* update budget accounting */
3616 budget--;
3617 } while (likely(budget));
3618
3619 i += tx_ring->count;
3620 tx_ring->next_to_clean = i;
3621
6995b36c 3622 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3623 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3624
cbf61325
ASJ		 3625 return budget > 0;
3626}
3627
3628/**
3629 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3630 * @irq: interrupt number
3631 * @data: pointer to a q_vector
3632 **/
3633static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3634{
3635 struct i40e_q_vector *q_vector = data;
3636 struct i40e_vsi *vsi;
3637
3638 if (!q_vector->tx.ring)
3639 return IRQ_HANDLED;
3640
3641 vsi = q_vector->tx.ring->vsi;
3642 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3643
3644 return IRQ_HANDLED;
3645}
3646
41c445ff 3647/**
cd0b6fa6 3648 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3649 * @vsi: the VSI being configured
3650 * @v_idx: vector index
cd0b6fa6 3651 * @qp_idx: queue pair index
41c445ff 3652 **/
26cdc443 3653static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3654{
493fb300 3655 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3656 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3657 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3658
3659 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3660 tx_ring->next = q_vector->tx.ring;
3661 q_vector->tx.ring = tx_ring;
41c445ff 3662 q_vector->tx.count++;
cd0b6fa6
AD		 3663
3664 rx_ring->q_vector = q_vector;
3665 rx_ring->next = q_vector->rx.ring;
3666 q_vector->rx.ring = rx_ring;
3667 q_vector->rx.count++;
41c445ff
JB		 3668}
3669
3670/**
3671 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3672 * @vsi: the VSI being configured
3673 *
3674 * This function maps descriptor rings to the queue-specific vectors
3675 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3676 * one vector per queue pair, but on a constrained vector budget, we
3677 * group the queue pairs as "efficiently" as possible.
3678 **/
3679static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3680{
3681 int qp_remaining = vsi->num_queue_pairs;
3682 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3683 int num_ringpairs;
41c445ff
JB		 3684 int v_start = 0;
3685 int qp_idx = 0;
3686
3687 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3688 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3689 * It is also important to go through all the vectors available to be
3690 * sure that if we don't use all the vectors, that the remaining vectors
3691 * are cleared. This is especially important when decreasing the
3692 * number of queues in use.
41c445ff 3693 */
70114ec4 3694 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3695 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3696
3697 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3698
3699 q_vector->num_ringpairs = num_ringpairs;
3700
3701 q_vector->rx.count = 0;
3702 q_vector->tx.count = 0;
3703 q_vector->rx.ring = NULL;
3704 q_vector->tx.ring = NULL;
3705
3706 while (num_ringpairs--) {
26cdc443 3707 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3708 qp_idx++;
3709 qp_remaining--;
41c445ff
JB		 3710 }
3711 }
3712}
3713
3714/**
3715 * i40e_vsi_request_irq - Request IRQ from the OS
3716 * @vsi: the VSI being configured
3717 * @basename: name for the vector
3718 **/
3719static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3720{
3721 struct i40e_pf *pf = vsi->back;
3722 int err;
3723
3724 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3725 err = i40e_vsi_request_irq_msix(vsi, basename);
3726 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3727 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3728 pf->int_name, pf);
41c445ff
JB		 3729 else
3730 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3731 pf->int_name, pf);
41c445ff
JB		 3732
3733 if (err)
3734 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3735
3736 return err;
3737}
3738
3739#ifdef CONFIG_NET_POLL_CONTROLLER
3740/**
3741 * i40e_netpoll - A Polling 'interrupt'handler
3742 * @netdev: network interface device structure
3743 *
3744 * This is used by netconsole to send skbs without having to re-enable
3745 * interrupts. It's not called while the normal interrupt routine is executing.
3746 **/
38e00438
VD		 3747#ifdef I40E_FCOE
3748void i40e_netpoll(struct net_device *netdev)
3749#else
41c445ff 3750static void i40e_netpoll(struct net_device *netdev)
38e00438 3751#endif
41c445ff
JB		 3752{
3753 struct i40e_netdev_priv *np = netdev_priv(netdev);
3754 struct i40e_vsi *vsi = np->vsi;
3755 struct i40e_pf *pf = vsi->back;
3756 int i;
3757
3758 /* if interface is down do nothing */
3759 if (test_bit(__I40E_DOWN, &vsi->state))
3760 return;
3761
41c445ff
JB		 3762 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3763 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3764 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3765 } else {
3766 i40e_intr(pf->pdev->irq, netdev);
3767 }
41c445ff
JB		 3768}
3769#endif
3770
23527308
NP		 3771/**
3772 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3773 * @pf: the PF being configured
3774 * @pf_q: the PF queue
3775 * @enable: enable or disable state of the queue
3776 *
3777 * This routine will wait for the given Tx queue of the PF to reach the
3778 * enabled or disabled state.
3779 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3780 * multiple retries; else will return 0 in case of success.
3781 **/
3782static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3783{
3784 int i;
3785 u32 tx_reg;
3786
3787 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3788 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3789 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3790 break;
3791
f98a2006 3792 usleep_range(10, 20);
23527308
NP		 3793 }
3794 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3795 return -ETIMEDOUT;
3796
3797 return 0;
3798}
3799
41c445ff
JB		 3800/**
3801 * i40e_vsi_control_tx - Start or stop a VSI's rings
3802 * @vsi: the VSI being configured
3803 * @enable: start or stop the rings
3804 **/
3805static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3806{
3807 struct i40e_pf *pf = vsi->back;
3808 struct i40e_hw *hw = &pf->hw;
23527308 3809 int i, j, pf_q, ret = 0;
41c445ff
JB		 3810 u32 tx_reg;
3811
3812 pf_q = vsi->base_queue;
3813 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3814
3815 /* warn the TX unit of coming changes */
3816 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3817 if (!enable)
f98a2006 3818 usleep_range(10, 20);
351499ab 3819
6c5ef620 3820 for (j = 0; j < 50; j++) {
41c445ff 3821 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3822 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3823 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3824 break;
3825 usleep_range(1000, 2000);
3826 }
fda972f6 3827 /* Skip if the queue is already in the requested state */
7c122007 3828 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3829 continue;
41c445ff
JB		 3830
3831 /* turn on/off the queue */
c5c9eb9e
SN		 3832 if (enable) {
3833 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3834 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3835 } else {
41c445ff 3836 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3837 }
41c445ff
JB		 3838
3839 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3840 /* No waiting for the Tx queue to disable */
3841 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3842 continue;
41c445ff
JB		 3843
3844 /* wait for the change to finish */
23527308
NP		 3845 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3846 if (ret) {
3847 dev_info(&pf->pdev->dev,
fb43201f
SN		 3848 "VSI seid %d Tx ring %d %sable timeout\n",
3849 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3850 break;
41c445ff
JB		 3851 }
3852 }
3853
7134f9ce
JB		 3854 if (hw->revision_id == 0)
3855 mdelay(50);
23527308
NP		 3856 return ret;
3857}
3858
3859/**
3860 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3861 * @pf: the PF being configured
3862 * @pf_q: the PF queue
3863 * @enable: enable or disable state of the queue
3864 *
3865 * This routine will wait for the given Rx queue of the PF to reach the
3866 * enabled or disabled state.
3867 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3868 * multiple retries; else will return 0 in case of success.
3869 **/
3870static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3871{
3872 int i;
3873 u32 rx_reg;
3874
3875 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3876 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3877 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3878 break;
3879
f98a2006 3880 usleep_range(10, 20);
23527308
NP		 3881 }
3882 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3883 return -ETIMEDOUT;
7134f9ce 3884
41c445ff
JB		 3885 return 0;
3886}
3887
3888/**
3889 * i40e_vsi_control_rx - Start or stop a VSI's rings
3890 * @vsi: the VSI being configured
3891 * @enable: start or stop the rings
3892 **/
3893static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3894{
3895 struct i40e_pf *pf = vsi->back;
3896 struct i40e_hw *hw = &pf->hw;
23527308 3897 int i, j, pf_q, ret = 0;
41c445ff
JB		 3898 u32 rx_reg;
3899
3900 pf_q = vsi->base_queue;
3901 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3902 for (j = 0; j < 50; j++) {
41c445ff 3903 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3904 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3905 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3906 break;
3907 usleep_range(1000, 2000);
3908 }
41c445ff 3909
7c122007
CS		 3910 /* Skip if the queue is already in the requested state */
3911 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3912 continue;
41c445ff
JB		 3913
3914 /* turn on/off the queue */
3915 if (enable)
6c5ef620 3916 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3917 else
6c5ef620 3918 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3919 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3920
3921 /* wait for the change to finish */
23527308
NP		 3922 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3923 if (ret) {
3924 dev_info(&pf->pdev->dev,
fb43201f
SN		 3925 "VSI seid %d Rx ring %d %sable timeout\n",
3926 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3927 break;
41c445ff
JB		 3928 }
3929 }
3930
23527308 3931 return ret;
41c445ff
JB		 3932}
3933
3934/**
3935 * i40e_vsi_control_rings - Start or stop a VSI's rings
3936 * @vsi: the VSI being configured
3937 * @enable: start or stop the rings
3938 **/
fc18eaa0 3939int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3940{
3b867b28 3941 int ret = 0;
41c445ff
JB		 3942
3943 /* do rx first for enable and last for disable */
3944 if (request) {
3945 ret = i40e_vsi_control_rx(vsi, request);
3946 if (ret)
3947 return ret;
3948 ret = i40e_vsi_control_tx(vsi, request);
3949 } else {
3b867b28
ASJ		 3950 /* Ignore return value, we need to shutdown whatever we can */
3951 i40e_vsi_control_tx(vsi, request);
3952 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3953 }
3954
3955 return ret;
3956}
3957
3958/**
3959 * i40e_vsi_free_irq - Free the irq association with the OS
3960 * @vsi: the VSI being configured
3961 **/
3962static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3963{
3964 struct i40e_pf *pf = vsi->back;
3965 struct i40e_hw *hw = &pf->hw;
3966 int base = vsi->base_vector;
3967 u32 val, qp;
3968 int i;
3969
3970 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3971 if (!vsi->q_vectors)
3972 return;
3973
63741846
SN		 3974 if (!vsi->irqs_ready)
3975 return;
3976
3977 vsi->irqs_ready = false;
41c445ff
JB		 3978 for (i = 0; i < vsi->num_q_vectors; i++) {
3979 u16 vector = i + base;
3980
3981 /* free only the irqs that were actually requested */
78681b1f
SN		 3982 if (!vsi->q_vectors[i] ||
3983 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3984 continue;
3985
3986 /* clear the affinity_mask in the IRQ descriptor */
3987 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3988 NULL);
3989 free_irq(pf->msix_entries[vector].vector,
493fb300 3990 vsi->q_vectors[i]);
41c445ff
JB		 3991
3992 /* Tear down the interrupt queue link list
3993 *
3994 * We know that they come in pairs and always
3995 * the Rx first, then the Tx. To clear the
3996 * link list, stick the EOL value into the
3997 * next_q field of the registers.
3998 */
3999 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
4000 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4001 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4002 val |= I40E_QUEUE_END_OF_LIST
4003 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4004 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4005
4006 while (qp != I40E_QUEUE_END_OF_LIST) {
4007 u32 next;
4008
4009 val = rd32(hw, I40E_QINT_RQCTL(qp));
4010
4011 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4012 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4013 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4014 I40E_QINT_RQCTL_INTEVENT_MASK);
4015
4016 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4017 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4018
4019 wr32(hw, I40E_QINT_RQCTL(qp), val);
4020
4021 val = rd32(hw, I40E_QINT_TQCTL(qp));
4022
4023 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4024 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4025
4026 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4027 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4028 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4029 I40E_QINT_TQCTL_INTEVENT_MASK);
4030
4031 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4032 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4033
4034 wr32(hw, I40E_QINT_TQCTL(qp), val);
4035 qp = next;
4036 }
4037 }
4038 } else {
4039 free_irq(pf->pdev->irq, pf);
4040
4041 val = rd32(hw, I40E_PFINT_LNKLST0);
4042 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4043 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4044 val |= I40E_QUEUE_END_OF_LIST
4045 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4046 wr32(hw, I40E_PFINT_LNKLST0, val);
4047
4048 val = rd32(hw, I40E_QINT_RQCTL(qp));
4049 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4050 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4051 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4052 I40E_QINT_RQCTL_INTEVENT_MASK);
4053
4054 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4055 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4056
4057 wr32(hw, I40E_QINT_RQCTL(qp), val);
4058
4059 val = rd32(hw, I40E_QINT_TQCTL(qp));
4060
4061 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4062 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4063 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4064 I40E_QINT_TQCTL_INTEVENT_MASK);
4065
4066 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4067 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4068
4069 wr32(hw, I40E_QINT_TQCTL(qp), val);
4070 }
4071}
4072
493fb300
AD		 4073/**
4074 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4075 * @vsi: the VSI being configured
4076 * @v_idx: Index of vector to be freed
4077 *
4078 * This function frees the memory allocated to the q_vector. In addition if
4079 * NAPI is enabled it will delete any references to the NAPI struct prior
4080 * to freeing the q_vector.
4081 **/
4082static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4083{
4084 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4085 struct i40e_ring *ring;
493fb300
AD		 4086
4087 if (!q_vector)
4088 return;
4089
4090 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4091 i40e_for_each_ring(ring, q_vector->tx)
4092 ring->q_vector = NULL;
4093
4094 i40e_for_each_ring(ring, q_vector->rx)
4095 ring->q_vector = NULL;
493fb300
AD		 4096
4097 /* only VSI w/ an associated netdev is set up w/ NAPI */
4098 if (vsi->netdev)
4099 netif_napi_del(&q_vector->napi);
4100
4101 vsi->q_vectors[v_idx] = NULL;
4102
4103 kfree_rcu(q_vector, rcu);
4104}
4105
41c445ff
JB		 4106/**
4107 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4108 * @vsi: the VSI being un-configured
4109 *
4110 * This frees the memory allocated to the q_vectors and
4111 * deletes references to the NAPI struct.
4112 **/
4113static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4114{
4115 int v_idx;
4116
493fb300
AD		 4117 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4118 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4119}
4120
4121/**
4122 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4123 * @pf: board private structure
4124 **/
4125static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4126{
4127 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4128 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4129 pci_disable_msix(pf->pdev);
4130 kfree(pf->msix_entries);
4131 pf->msix_entries = NULL;
3b444399
SN		 4132 kfree(pf->irq_pile);
4133 pf->irq_pile = NULL;
41c445ff
JB		 4134 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4135 pci_disable_msi(pf->pdev);
4136 }
4137 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4138}
4139
4140/**
4141 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4142 * @pf: board private structure
4143 *
4144 * We go through and clear interrupt specific resources and reset the structure
4145 * to pre-load conditions
4146 **/
4147static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4148{
4149 int i;
4150
e147758d
SN		 4151 i40e_stop_misc_vector(pf);
4152 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4153 synchronize_irq(pf->msix_entries[0].vector);
4154 free_irq(pf->msix_entries[0].vector, pf);
4155 }
4156
41c445ff 4157 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4158 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4159 if (pf->vsi[i])
4160 i40e_vsi_free_q_vectors(pf->vsi[i]);
4161 i40e_reset_interrupt_capability(pf);
4162}
4163
4164/**
4165 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4166 * @vsi: the VSI being configured
4167 **/
4168static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4169{
4170 int q_idx;
4171
4172 if (!vsi->netdev)
4173 return;
4174
4175 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4176 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4177}
4178
4179/**
4180 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4181 * @vsi: the VSI being configured
4182 **/
4183static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4184{
4185 int q_idx;
4186
4187 if (!vsi->netdev)
4188 return;
4189
4190 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4191 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4192}
4193
90ef8d47
SN		 4194/**
4195 * i40e_vsi_close - Shut down a VSI
4196 * @vsi: the vsi to be quelled
4197 **/
4198static void i40e_vsi_close(struct i40e_vsi *vsi)
4199{
4200 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4201 i40e_down(vsi);
4202 i40e_vsi_free_irq(vsi);
4203 i40e_vsi_free_tx_resources(vsi);
4204 i40e_vsi_free_rx_resources(vsi);
92faef85 4205 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4206}
4207
41c445ff
JB		 4208/**
4209 * i40e_quiesce_vsi - Pause a given VSI
4210 * @vsi: the VSI being paused
4211 **/
4212static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4213{
4214 if (test_bit(__I40E_DOWN, &vsi->state))
4215 return;
4216
d341b7a5
NP		 4217 /* No need to disable FCoE VSI when Tx suspended */
4218 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4219 vsi->type == I40E_VSI_FCOE) {
4220 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4221 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4222 return;
4223 }
4224
41c445ff 4225 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4226 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4227 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4228 else
90ef8d47 4229 i40e_vsi_close(vsi);
41c445ff
JB		 4230}
4231
4232/**
4233 * i40e_unquiesce_vsi - Resume a given VSI
4234 * @vsi: the VSI being resumed
4235 **/
4236static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4237{
4238 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4239 return;
4240
4241 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4242 if (vsi->netdev && netif_running(vsi->netdev))
4243 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4244 else
8276f757 4245 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4246}
4247
4248/**
4249 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4250 * @pf: the PF
4251 **/
4252static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4253{
4254 int v;
4255
505682cd 4256 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4257 if (pf->vsi[v])
4258 i40e_quiesce_vsi(pf->vsi[v]);
4259 }
4260}
4261
4262/**
4263 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4264 * @pf: the PF
4265 **/
4266static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4267{
4268 int v;
4269
505682cd 4270 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4271 if (pf->vsi[v])
4272 i40e_unquiesce_vsi(pf->vsi[v]);
4273 }
4274}
4275
69129dc3
NP		 4276#ifdef CONFIG_I40E_DCB
4277/**
4278 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4279 * @vsi: the VSI being configured
4280 *
4281 * This function waits for the given VSI's Tx queues to be disabled.
4282 **/
4283static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4284{
4285 struct i40e_pf *pf = vsi->back;
4286 int i, pf_q, ret;
4287
4288 pf_q = vsi->base_queue;
4289 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4290 /* Check and wait for the disable status of the queue */
4291 ret = i40e_pf_txq_wait(pf, pf_q, false);
4292 if (ret) {
4293 dev_info(&pf->pdev->dev,
fb43201f
SN		 4294 "VSI seid %d Tx ring %d disable timeout\n",
4295 vsi->seid, pf_q);
69129dc3
NP		 4296 return ret;
4297 }
4298 }
4299
4300 return 0;
4301}
4302
4303/**
4304 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4305 * @pf: the PF
4306 *
4307 * This function waits for the Tx queues to be in disabled state for all the
4308 * VSIs that are managed by this PF.
4309 **/
4310static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4311{
4312 int v, ret = 0;
4313
4314 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4315 /* No need to wait for FCoE VSI queues */
4316 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4317 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4318 if (ret)
4319 break;
4320 }
4321 }
4322
4323 return ret;
4324}
4325
4326#endif
b03a8c1f
KP		 4327
4328/**
4329 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4330 * @q_idx: TX queue number
4331 * @vsi: Pointer to VSI struct
4332 *
4333 * This function checks specified queue for given VSI. Detects hung condition.
4334 * Sets hung bit since it is two step process. Before next run of service task
4335 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4336 * hung condition remain unchanged and during subsequent run, this function
4337 * issues SW interrupt to recover from hung condition.
4338 **/
4339static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4340{
4341 struct i40e_ring *tx_ring = NULL;
4342 struct i40e_pf *pf;
4343 u32 head, val, tx_pending;
4344 int i;
4345
4346 pf = vsi->back;
4347
4348 /* now that we have an index, find the tx_ring struct */
4349 for (i = 0; i < vsi->num_queue_pairs; i++) {
4350 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4351 if (q_idx == vsi->tx_rings[i]->queue_index) {
4352 tx_ring = vsi->tx_rings[i];
4353 break;
4354 }
4355 }
4356 }
4357
4358 if (!tx_ring)
4359 return;
4360
4361 /* Read interrupt register */
4362 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4363 val = rd32(&pf->hw,
4364 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4365 tx_ring->vsi->base_vector - 1));
4366 else
4367 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4368
4369 head = i40e_get_head(tx_ring);
4370
4371 tx_pending = i40e_get_tx_pending(tx_ring);
4372
4373 /* Interrupts are disabled and TX pending is non-zero,
4374 * trigger the SW interrupt (don't wait). Worst case
4375 * there will be one extra interrupt which may result
4376 * into not cleaning any queues because queues are cleaned.
4377 */
4378 if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK)))
4379 i40e_force_wb(vsi, tx_ring->q_vector);
4380}
4381
4382/**
4383 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4384 * @pf: pointer to PF struct
4385 *
4386 * LAN VSI has netdev and netdev has TX queues. This function is to check
4387 * each of those TX queues if they are hung, trigger recovery by issuing
4388 * SW interrupt.
4389 **/
4390static void i40e_detect_recover_hung(struct i40e_pf *pf)
4391{
4392 struct net_device *netdev;
4393 struct i40e_vsi *vsi;
4394 int i;
4395
4396 /* Only for LAN VSI */
4397 vsi = pf->vsi[pf->lan_vsi];
4398
4399 if (!vsi)
4400 return;
4401
4402 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4403 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4404 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4405 return;
4406
4407 /* Make sure type is MAIN VSI */
4408 if (vsi->type != I40E_VSI_MAIN)
4409 return;
4410
4411 netdev = vsi->netdev;
4412 if (!netdev)
4413 return;
4414
4415 /* Bail out if netif_carrier is not OK */
4416 if (!netif_carrier_ok(netdev))
4417 return;
4418
4419 /* Go thru' TX queues for netdev */
4420 for (i = 0; i < netdev->num_tx_queues; i++) {
4421 struct netdev_queue *q;
4422
4423 q = netdev_get_tx_queue(netdev, i);
4424 if (q)
4425 i40e_detect_recover_hung_queue(i, vsi);
4426 }
4427}
4428
63d7e5a4
NP		 4429/**
4430 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4431 * @pf: pointer to PF
63d7e5a4
NP		 4432 *
4433 * Get TC map for ISCSI PF type that will include iSCSI TC
4434 * and LAN TC.
4435 **/
4436static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4437{
4438 struct i40e_dcb_app_priority_table app;
4439 struct i40e_hw *hw = &pf->hw;
4440 u8 enabled_tc = 1; /* TC0 is always enabled */
4441 u8 tc, i;
4442 /* Get the iSCSI APP TLV */
4443 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4444
4445 for (i = 0; i < dcbcfg->numapps; i++) {
4446 app = dcbcfg->app[i];
4447 if (app.selector == I40E_APP_SEL_TCPIP &&
4448 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4449 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4450 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4451 break;
4452 }
4453 }
4454
4455 return enabled_tc;
4456}
4457
41c445ff
JB		 4458/**
4459 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4460 * @dcbcfg: the corresponding DCBx configuration structure
4461 *
4462 * Return the number of TCs from given DCBx configuration
4463 **/
4464static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4465{
078b5876
JB		 4466 u8 num_tc = 0;
4467 int i;
41c445ff
JB		 4468
4469 /* Scan the ETS Config Priority Table to find
4470 * traffic class enabled for a given priority
4471 * and use the traffic class index to get the
4472 * number of traffic classes enabled
4473 */
4474 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4475 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4476 num_tc = dcbcfg->etscfg.prioritytable[i];
4477 }
4478
4479 /* Traffic class index starts from zero so
4480 * increment to return the actual count
4481 */
078b5876 4482 return num_tc + 1;
41c445ff
JB		 4483}
4484
4485/**
4486 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4487 * @dcbcfg: the corresponding DCBx configuration structure
4488 *
4489 * Query the current DCB configuration and return the number of
4490 * traffic classes enabled from the given DCBX config
4491 **/
4492static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4493{
4494 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4495 u8 enabled_tc = 1;
4496 u8 i;
4497
4498 for (i = 0; i < num_tc; i++)
41a1d04b 4499 enabled_tc |= BIT(i);
41c445ff
JB		 4500
4501 return enabled_tc;
4502}
4503
4504/**
4505 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4506 * @pf: PF being queried
4507 *
4508 * Return number of traffic classes enabled for the given PF
4509 **/
4510static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4511{
4512 struct i40e_hw *hw = &pf->hw;
4513 u8 i, enabled_tc;
4514 u8 num_tc = 0;
4515 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4516
4517 /* If DCB is not enabled then always in single TC */
4518 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4519 return 1;
4520
63d7e5a4
NP		 4521 /* SFP mode will be enabled for all TCs on port */
4522 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4523 return i40e_dcb_get_num_tc(dcbcfg);
4524
41c445ff 4525 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4526 if (pf->hw.func_caps.iscsi)
4527 enabled_tc = i40e_get_iscsi_tc_map(pf);
4528 else
fc51de96 4529 return 1; /* Only TC0 */
41c445ff 4530
63d7e5a4
NP		 4531 /* At least have TC0 */
4532 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4533 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4534 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4535 num_tc++;
4536 }
4537 return num_tc;
41c445ff
JB		 4538}
4539
4540/**
4541 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4542 * @pf: PF being queried
4543 *
4544 * Return a bitmap for first enabled traffic class for this PF.
4545 **/
4546static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4547{
4548 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4549 u8 i = 0;
4550
4551 if (!enabled_tc)
4552 return 0x1; /* TC0 */
4553
4554 /* Find the first enabled TC */
4555 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4556 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4557 break;
4558 }
4559
41a1d04b 4560 return BIT(i);
41c445ff
JB		 4561}
4562
4563/**
4564 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4565 * @pf: PF being queried
4566 *
4567 * Return a bitmap for enabled traffic classes for this PF.
4568 **/
4569static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4570{
4571 /* If DCB is not enabled for this PF then just return default TC */
4572 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4573 return i40e_pf_get_default_tc(pf);
4574
41c445ff 4575 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4576 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4577 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4578
fc51de96 4579 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4580 if (pf->hw.func_caps.iscsi)
4581 return i40e_get_iscsi_tc_map(pf);
4582 else
fc51de96 4583 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4584}
4585
4586/**
4587 * i40e_vsi_get_bw_info - Query VSI BW Information
4588 * @vsi: the VSI being queried
4589 *
4590 * Returns 0 on success, negative value on failure
4591 **/
4592static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4593{
4594 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4595 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4596 struct i40e_pf *pf = vsi->back;
4597 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4598 i40e_status ret;
41c445ff 4599 u32 tc_bw_max;
41c445ff
JB		 4600 int i;
4601
4602 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4603 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4604 if (ret) {
41c445ff 4605 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4606 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4607 i40e_stat_str(&pf->hw, ret),
4608 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4609 return -EINVAL;
41c445ff
JB		 4610 }
4611
4612 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4613 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4614 NULL);
4615 if (ret) {
41c445ff 4616 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4617 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4618 i40e_stat_str(&pf->hw, ret),
4619 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4620 return -EINVAL;
41c445ff
JB		 4621 }
4622
4623 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4624 dev_info(&pf->pdev->dev,
4625 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4626 bw_config.tc_valid_bits,
4627 bw_ets_config.tc_valid_bits);
4628 /* Still continuing */
4629 }
4630
4631 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4632 vsi->bw_max_quanta = bw_config.max_bw;
4633 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4634 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4635 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4636 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4637 vsi->bw_ets_limit_credits[i] =
4638 le16_to_cpu(bw_ets_config.credits[i]);
4639 /* 3 bits out of 4 for each TC */
4640 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4641 }
078b5876 4642
dcae29be 4643 return 0;
41c445ff
JB		 4644}
4645
4646/**
4647 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4648 * @vsi: the VSI being configured
4649 * @enabled_tc: TC bitmap
4650 * @bw_credits: BW shared credits per TC
4651 *
4652 * Returns 0 on success, negative value on failure
4653 **/
dcae29be 4654static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4655 u8 *bw_share)
4656{
4657 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4658 i40e_status ret;
dcae29be 4659 int i;
41c445ff
JB		 4660
4661 bw_data.tc_valid_bits = enabled_tc;
4662 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4663 bw_data.tc_bw_credits[i] = bw_share[i];
4664
f1c7e72e
SN		 4665 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4666 NULL);
4667 if (ret) {
41c445ff 4668 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4669 "AQ command Config VSI BW allocation per TC failed = %d\n",
4670 vsi->back->hw.aq.asq_last_status);
dcae29be 4671 return -EINVAL;
41c445ff
JB		 4672 }
4673
4674 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4675 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4676
dcae29be 4677 return 0;
41c445ff
JB		 4678}
4679
4680/**
4681 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4682 * @vsi: the VSI being configured
4683 * @enabled_tc: TC map to be enabled
4684 *
4685 **/
4686static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4687{
4688 struct net_device *netdev = vsi->netdev;
4689 struct i40e_pf *pf = vsi->back;
4690 struct i40e_hw *hw = &pf->hw;
4691 u8 netdev_tc = 0;
4692 int i;
4693 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4694
4695 if (!netdev)
4696 return;
4697
4698 if (!enabled_tc) {
4699 netdev_reset_tc(netdev);
4700 return;
4701 }
4702
4703 /* Set up actual enabled TCs on the VSI */
4704 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4705 return;
4706
4707 /* set per TC queues for the VSI */
4708 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4709 /* Only set TC queues for enabled tcs
4710 *
4711 * e.g. For a VSI that has TC0 and TC3 enabled the
4712 * enabled_tc bitmap would be 0x00001001; the driver
4713 * will set the numtc for netdev as 2 that will be
4714 * referenced by the netdev layer as TC 0 and 1.
4715 */
41a1d04b 4716 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4717 netdev_set_tc_queue(netdev,
4718 vsi->tc_config.tc_info[i].netdev_tc,
4719 vsi->tc_config.tc_info[i].qcount,
4720 vsi->tc_config.tc_info[i].qoffset);
4721 }
4722
4723 /* Assign UP2TC map for the VSI */
4724 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4725 /* Get the actual TC# for the UP */
4726 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4727 /* Get the mapped netdev TC# for the UP */
4728 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4729 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4730 }
4731}
4732
4733/**
4734 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4735 * @vsi: the VSI being configured
4736 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4737 **/
4738static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4739 struct i40e_vsi_context *ctxt)
4740{
4741 /* copy just the sections touched not the entire info
4742 * since not all sections are valid as returned by
4743 * update vsi params
4744 */
4745 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4746 memcpy(&vsi->info.queue_mapping,
4747 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4748 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4749 sizeof(vsi->info.tc_mapping));
4750}
4751
4752/**
4753 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4754 * @vsi: VSI to be configured
4755 * @enabled_tc: TC bitmap
4756 *
4757 * This configures a particular VSI for TCs that are mapped to the
4758 * given TC bitmap. It uses default bandwidth share for TCs across
4759 * VSIs to configure TC for a particular VSI.
4760 *
4761 * NOTE:
4762 * It is expected that the VSI queues have been quisced before calling
4763 * this function.
4764 **/
4765static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4766{
4767 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4768 struct i40e_vsi_context ctxt;
4769 int ret = 0;
4770 int i;
4771
4772 /* Check if enabled_tc is same as existing or new TCs */
4773 if (vsi->tc_config.enabled_tc == enabled_tc)
4774 return ret;
4775
4776 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4777 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4778 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4779 bw_share[i] = 1;
4780 }
4781
4782 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4783 if (ret) {
4784 dev_info(&vsi->back->pdev->dev,
4785 "Failed configuring TC map %d for VSI %d\n",
4786 enabled_tc, vsi->seid);
4787 goto out;
4788 }
4789
4790 /* Update Queue Pairs Mapping for currently enabled UPs */
4791 ctxt.seid = vsi->seid;
4792 ctxt.pf_num = vsi->back->hw.pf_id;
4793 ctxt.vf_num = 0;
4794 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4795 ctxt.info = vsi->info;
41c445ff
JB		 4796 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4797
4798 /* Update the VSI after updating the VSI queue-mapping information */
4799 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4800 if (ret) {
4801 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4802 "Update vsi tc config failed, err %s aq_err %s\n",
4803 i40e_stat_str(&vsi->back->hw, ret),
4804 i40e_aq_str(&vsi->back->hw,
4805 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4806 goto out;
4807 }
4808 /* update the local VSI info with updated queue map */
4809 i40e_vsi_update_queue_map(vsi, &ctxt);
4810 vsi->info.valid_sections = 0;
4811
4812 /* Update current VSI BW information */
4813 ret = i40e_vsi_get_bw_info(vsi);
4814 if (ret) {
4815 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4816 "Failed updating vsi bw info, err %s aq_err %s\n",
4817 i40e_stat_str(&vsi->back->hw, ret),
4818 i40e_aq_str(&vsi->back->hw,
4819 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4820 goto out;
4821 }
4822
4823 /* Update the netdev TC setup */
4824 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4825out:
4826 return ret;
4827}
4828
4e3b35b0
NP		 4829/**
4830 * i40e_veb_config_tc - Configure TCs for given VEB
4831 * @veb: given VEB
4832 * @enabled_tc: TC bitmap
4833 *
4834 * Configures given TC bitmap for VEB (switching) element
4835 **/
4836int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4837{
4838 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4839 struct i40e_pf *pf = veb->pf;
4840 int ret = 0;
4841 int i;
4842
4843 /* No TCs or already enabled TCs just return */
4844 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4845 return ret;
4846
4847 bw_data.tc_valid_bits = enabled_tc;
4848 /* bw_data.absolute_credits is not set (relative) */
4849
4850 /* Enable ETS TCs with equal BW Share for now */
4851 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4852 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4853 bw_data.tc_bw_share_credits[i] = 1;
4854 }
4855
4856 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4857 &bw_data, NULL);
4858 if (ret) {
4859 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4860 "VEB bw config failed, err %s aq_err %s\n",
4861 i40e_stat_str(&pf->hw, ret),
4862 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4863 goto out;
4864 }
4865
4866 /* Update the BW information */
4867 ret = i40e_veb_get_bw_info(veb);
4868 if (ret) {
4869 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4870 "Failed getting veb bw config, err %s aq_err %s\n",
4871 i40e_stat_str(&pf->hw, ret),
4872 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4873 }
4874
4875out:
4876 return ret;
4877}
4878
4879#ifdef CONFIG_I40E_DCB
4880/**
4881 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4882 * @pf: PF struct
4883 *
4884 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4885 * the caller would've quiesce all the VSIs before calling
4886 * this function
4887 **/
4888static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4889{
4890 u8 tc_map = 0;
4891 int ret;
4892 u8 v;
4893
4894 /* Enable the TCs available on PF to all VEBs */
4895 tc_map = i40e_pf_get_tc_map(pf);
4896 for (v = 0; v < I40E_MAX_VEB; v++) {
4897 if (!pf->veb[v])
4898 continue;
4899 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4900 if (ret) {
4901 dev_info(&pf->pdev->dev,
4902 "Failed configuring TC for VEB seid=%d\n",
4903 pf->veb[v]->seid);
4904 /* Will try to configure as many components */
4905 }
4906 }
4907
4908 /* Update each VSI */
505682cd 4909 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4910 if (!pf->vsi[v])
4911 continue;
4912
4913 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4914#ifdef I40E_FCOE
4915 * - For FCoE VSI only enable the TC configured
4916 * as per the APP TLV
4917#endif
4e3b35b0
NP		 4918 * - For all others keep them at TC0 for now
4919 */
4920 if (v == pf->lan_vsi)
4921 tc_map = i40e_pf_get_tc_map(pf);
4922 else
4923 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4924#ifdef I40E_FCOE
4925 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4926 tc_map = i40e_get_fcoe_tc_map(pf);
4927#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4928
4929 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4930 if (ret) {
4931 dev_info(&pf->pdev->dev,
4932 "Failed configuring TC for VSI seid=%d\n",
4933 pf->vsi[v]->seid);
4934 /* Will try to configure as many components */
4935 } else {
0672a091
NP		 4936 /* Re-configure VSI vectors based on updated TC map */
4937 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4938 if (pf->vsi[v]->netdev)
4939 i40e_dcbnl_set_all(pf->vsi[v]);
4940 }
4941 }
4942}
4943
2fd75f31
NP		 4944/**
4945 * i40e_resume_port_tx - Resume port Tx
4946 * @pf: PF struct
4947 *
4948 * Resume a port's Tx and issue a PF reset in case of failure to
4949 * resume.
4950 **/
4951static int i40e_resume_port_tx(struct i40e_pf *pf)
4952{
4953 struct i40e_hw *hw = &pf->hw;
4954 int ret;
4955
4956 ret = i40e_aq_resume_port_tx(hw, NULL);
4957 if (ret) {
4958 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4959 "Resume Port Tx failed, err %s aq_err %s\n",
4960 i40e_stat_str(&pf->hw, ret),
4961 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4962 /* Schedule PF reset to recover */
4963 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4964 i40e_service_event_schedule(pf);
4965 }
4966
4967 return ret;
4968}
4969
4e3b35b0
NP		 4970/**
4971 * i40e_init_pf_dcb - Initialize DCB configuration
4972 * @pf: PF being configured
4973 *
4974 * Query the current DCB configuration and cache it
4975 * in the hardware structure
4976 **/
4977static int i40e_init_pf_dcb(struct i40e_pf *pf)
4978{
4979 struct i40e_hw *hw = &pf->hw;
4980 int err = 0;
4981
025b4a54
ASJ		 4982 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4983 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4984 (pf->hw.aq.fw_maj_ver < 4))
4985 goto out;
4986
4e3b35b0
NP		 4987 /* Get the initial DCB configuration */
4988 err = i40e_init_dcb(hw);
4989 if (!err) {
4990 /* Device/Function is not DCBX capable */
4991 if ((!hw->func_caps.dcb) ||
4992 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4993 dev_info(&pf->pdev->dev,
4994 "DCBX offload is not supported or is disabled for this PF.\n");
4995
4996 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4997 goto out;
4998
4999 } else {
5000 /* When status is not DISABLED then DCBX in FW */
5001 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5002 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5003
5004 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5005 /* Enable DCB tagging only when more than one TC */
5006 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5007 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5008 dev_dbg(&pf->pdev->dev,
5009 "DCBX offload is supported for this PF.\n");
4e3b35b0 5010 }
014269ff 5011 } else {
aebfc816 5012 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5013 "Query for DCB configuration failed, err %s aq_err %s\n",
5014 i40e_stat_str(&pf->hw, err),
5015 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5016 }
5017
5018out:
5019 return err;
5020}
5021#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5022#define SPEED_SIZE 14
5023#define FC_SIZE 8
5024/**
5025 * i40e_print_link_message - print link up or down
5026 * @vsi: the VSI for which link needs a message
5027 */
c156f856 5028void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5029{
a9165490
SN		 5030 char *speed = "Unknown";
5031 char *fc = "Unknown";
cf05ed08 5032
c156f856
MJ		 5033 if (vsi->current_isup == isup)
5034 return;
5035 vsi->current_isup = isup;
cf05ed08
JB		 5036 if (!isup) {
5037 netdev_info(vsi->netdev, "NIC Link is Down\n");
5038 return;
5039 }
5040
148c2d80
GR		 5041 /* Warn user if link speed on NPAR enabled partition is not at
5042 * least 10GB
5043 */
5044 if (vsi->back->hw.func_caps.npar_enable &&
5045 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5046 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5047 netdev_warn(vsi->netdev,
5048 "The partition detected link speed that is less than 10Gbps\n");
5049
cf05ed08
JB		 5050 switch (vsi->back->hw.phy.link_info.link_speed) {
5051 case I40E_LINK_SPEED_40GB:
a9165490 5052 speed = "40 G";
cf05ed08 5053 break;
ae24b409 5054 case I40E_LINK_SPEED_20GB:
a9165490 5055 speed = "20 G";
ae24b409 5056 break;
cf05ed08 5057 case I40E_LINK_SPEED_10GB:
a9165490 5058 speed = "10 G";
cf05ed08
JB		 5059 break;
5060 case I40E_LINK_SPEED_1GB:
a9165490 5061 speed = "1000 M";
cf05ed08 5062 break;
5960d33f 5063 case I40E_LINK_SPEED_100MB:
a9165490 5064 speed = "100 M";
5960d33f 5065 break;
cf05ed08
JB		 5066 default:
5067 break;
5068 }
5069
5070 switch (vsi->back->hw.fc.current_mode) {
5071 case I40E_FC_FULL:
a9165490 5072 fc = "RX/TX";
cf05ed08
JB		 5073 break;
5074 case I40E_FC_TX_PAUSE:
a9165490 5075 fc = "TX";
cf05ed08
JB		 5076 break;
5077 case I40E_FC_RX_PAUSE:
a9165490 5078 fc = "RX";
cf05ed08
JB		 5079 break;
5080 default:
a9165490 5081 fc = "None";
cf05ed08
JB		 5082 break;
5083 }
5084
a9165490 5085 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5086 speed, fc);
5087}
4e3b35b0 5088
41c445ff
JB		 5089/**
5090 * i40e_up_complete - Finish the last steps of bringing up a connection
5091 * @vsi: the VSI being configured
5092 **/
5093static int i40e_up_complete(struct i40e_vsi *vsi)
5094{
5095 struct i40e_pf *pf = vsi->back;
5096 int err;
5097
5098 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5099 i40e_vsi_configure_msix(vsi);
5100 else
5101 i40e_configure_msi_and_legacy(vsi);
5102
5103 /* start rings */
5104 err = i40e_vsi_control_rings(vsi, true);
5105 if (err)
5106 return err;
5107
5108 clear_bit(__I40E_DOWN, &vsi->state);
5109 i40e_napi_enable_all(vsi);
5110 i40e_vsi_enable_irq(vsi);
5111
5112 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5113 (vsi->netdev)) {
cf05ed08 5114 i40e_print_link_message(vsi, true);
41c445ff
JB		 5115 netif_tx_start_all_queues(vsi->netdev);
5116 netif_carrier_on(vsi->netdev);
6d779b41 5117 } else if (vsi->netdev) {
cf05ed08 5118 i40e_print_link_message(vsi, false);
7b592f61
CW		 5119 /* need to check for qualified module here*/
5120 if ((pf->hw.phy.link_info.link_info &
5121 I40E_AQ_MEDIA_AVAILABLE) &&
5122 (!(pf->hw.phy.link_info.an_info &
5123 I40E_AQ_QUALIFIED_MODULE)))
5124 netdev_err(vsi->netdev,
5125 "the driver failed to link because an unqualified module was detected.");
41c445ff 5126 }
ca64fa4e
ASJ		 5127
5128 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5129 if (vsi->type == I40E_VSI_FDIR) {
5130 /* reset fd counters */
5131 pf->fd_add_err = pf->fd_atr_cnt = 0;
5132 if (pf->fd_tcp_rule > 0) {
5133 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5134 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5135 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5136 pf->fd_tcp_rule = 0;
5137 }
ca64fa4e 5138 i40e_fdir_filter_restore(vsi);
1e1be8f6 5139 }
41c445ff
JB		 5140 i40e_service_event_schedule(pf);
5141
5142 return 0;
5143}
5144
5145/**
5146 * i40e_vsi_reinit_locked - Reset the VSI
5147 * @vsi: the VSI being configured
5148 *
5149 * Rebuild the ring structs after some configuration
5150 * has changed, e.g. MTU size.
5151 **/
5152static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5153{
5154 struct i40e_pf *pf = vsi->back;
5155
5156 WARN_ON(in_interrupt());
5157 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5158 usleep_range(1000, 2000);
5159 i40e_down(vsi);
5160
5161 /* Give a VF some time to respond to the reset. The
5162 * two second wait is based upon the watchdog cycle in
5163 * the VF driver.
5164 */
5165 if (vsi->type == I40E_VSI_SRIOV)
5166 msleep(2000);
5167 i40e_up(vsi);
5168 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5169}
5170
5171/**
5172 * i40e_up - Bring the connection back up after being down
5173 * @vsi: the VSI being configured
5174 **/
5175int i40e_up(struct i40e_vsi *vsi)
5176{
5177 int err;
5178
5179 err = i40e_vsi_configure(vsi);
5180 if (!err)
5181 err = i40e_up_complete(vsi);
5182
5183 return err;
5184}
5185
5186/**
5187 * i40e_down - Shutdown the connection processing
5188 * @vsi: the VSI being stopped
5189 **/
5190void i40e_down(struct i40e_vsi *vsi)
5191{
5192 int i;
5193
5194 /* It is assumed that the caller of this function
5195 * sets the vsi->state __I40E_DOWN bit.
5196 */
5197 if (vsi->netdev) {
5198 netif_carrier_off(vsi->netdev);
5199 netif_tx_disable(vsi->netdev);
5200 }
5201 i40e_vsi_disable_irq(vsi);
5202 i40e_vsi_control_rings(vsi, false);
5203 i40e_napi_disable_all(vsi);
5204
5205 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5206 i40e_clean_tx_ring(vsi->tx_rings[i]);
5207 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5208 }
5209}
5210
5211/**
5212 * i40e_setup_tc - configure multiple traffic classes
5213 * @netdev: net device to configure
5214 * @tc: number of traffic classes to enable
5215 **/
38e00438
VD		 5216#ifdef I40E_FCOE
5217int i40e_setup_tc(struct net_device *netdev, u8 tc)
5218#else
41c445ff 5219static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5220#endif
41c445ff
JB		 5221{
5222 struct i40e_netdev_priv *np = netdev_priv(netdev);
5223 struct i40e_vsi *vsi = np->vsi;
5224 struct i40e_pf *pf = vsi->back;
5225 u8 enabled_tc = 0;
5226 int ret = -EINVAL;
5227 int i;
5228
5229 /* Check if DCB enabled to continue */
5230 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5231 netdev_info(netdev, "DCB is not enabled for adapter\n");
5232 goto exit;
5233 }
5234
5235 /* Check if MFP enabled */
5236 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5237 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5238 goto exit;
5239 }
5240
5241 /* Check whether tc count is within enabled limit */
5242 if (tc > i40e_pf_get_num_tc(pf)) {
5243 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5244 goto exit;
5245 }
5246
5247 /* Generate TC map for number of tc requested */
5248 for (i = 0; i < tc; i++)
41a1d04b 5249 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5250
5251 /* Requesting same TC configuration as already enabled */
5252 if (enabled_tc == vsi->tc_config.enabled_tc)
5253 return 0;
5254
5255 /* Quiesce VSI queues */
5256 i40e_quiesce_vsi(vsi);
5257
5258 /* Configure VSI for enabled TCs */
5259 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5260 if (ret) {
5261 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5262 vsi->seid);
5263 goto exit;
5264 }
5265
5266 /* Unquiesce VSI */
5267 i40e_unquiesce_vsi(vsi);
5268
5269exit:
5270 return ret;
5271}
5272
5273/**
5274 * i40e_open - Called when a network interface is made active
5275 * @netdev: network interface device structure
5276 *
5277 * The open entry point is called when a network interface is made
5278 * active by the system (IFF_UP). At this point all resources needed
5279 * for transmit and receive operations are allocated, the interrupt
5280 * handler is registered with the OS, the netdev watchdog subtask is
5281 * enabled, and the stack is notified that the interface is ready.
5282 *
5283 * Returns 0 on success, negative value on failure
5284 **/
38e00438 5285int i40e_open(struct net_device *netdev)
41c445ff
JB		 5286{
5287 struct i40e_netdev_priv *np = netdev_priv(netdev);
5288 struct i40e_vsi *vsi = np->vsi;
5289 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5290 int err;
5291
4eb3f768
SN		 5292 /* disallow open during test or if eeprom is broken */
5293 if (test_bit(__I40E_TESTING, &pf->state) ||
5294 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5295 return -EBUSY;
5296
5297 netif_carrier_off(netdev);
5298
6c167f58
EK		 5299 err = i40e_vsi_open(vsi);
5300 if (err)
5301 return err;
5302
059dab69
JB		 5303 /* configure global TSO hardware offload settings */
5304 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5305 TCP_FLAG_FIN) >> 16);
5306 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5307 TCP_FLAG_FIN |
5308 TCP_FLAG_CWR) >> 16);
5309 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5310
6c167f58
EK		 5311#ifdef CONFIG_I40E_VXLAN
5312 vxlan_get_rx_port(netdev);
5313#endif
5314
5315 return 0;
5316}
5317
5318/**
5319 * i40e_vsi_open -
5320 * @vsi: the VSI to open
5321 *
5322 * Finish initialization of the VSI.
5323 *
5324 * Returns 0 on success, negative value on failure
5325 **/
5326int i40e_vsi_open(struct i40e_vsi *vsi)
5327{
5328 struct i40e_pf *pf = vsi->back;
b294ac70 5329 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5330 int err;
5331
41c445ff
JB		 5332 /* allocate descriptors */
5333 err = i40e_vsi_setup_tx_resources(vsi);
5334 if (err)
5335 goto err_setup_tx;
5336 err = i40e_vsi_setup_rx_resources(vsi);
5337 if (err)
5338 goto err_setup_rx;
5339
5340 err = i40e_vsi_configure(vsi);
5341 if (err)
5342 goto err_setup_rx;
5343
c22e3c6c
SN		 5344 if (vsi->netdev) {
5345 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5346 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5347 err = i40e_vsi_request_irq(vsi, int_name);
5348 if (err)
5349 goto err_setup_rx;
41c445ff 5350
c22e3c6c
SN		 5351 /* Notify the stack of the actual queue counts. */
5352 err = netif_set_real_num_tx_queues(vsi->netdev,
5353 vsi->num_queue_pairs);
5354 if (err)
5355 goto err_set_queues;
25946ddb 5356
c22e3c6c
SN		 5357 err = netif_set_real_num_rx_queues(vsi->netdev,
5358 vsi->num_queue_pairs);
5359 if (err)
5360 goto err_set_queues;
8a9eb7d3
SN		 5361
5362 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5363 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5364 dev_driver_string(&pf->pdev->dev),
5365 dev_name(&pf->pdev->dev));
8a9eb7d3 5366 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5367
c22e3c6c 5368 } else {
ce9ccb17 5369 err = -EINVAL;
6c167f58
EK		 5370 goto err_setup_rx;
5371 }
25946ddb 5372
41c445ff
JB		 5373 err = i40e_up_complete(vsi);
5374 if (err)
5375 goto err_up_complete;
5376
41c445ff
JB		 5377 return 0;
5378
5379err_up_complete:
5380 i40e_down(vsi);
25946ddb 5381err_set_queues:
41c445ff
JB		 5382 i40e_vsi_free_irq(vsi);
5383err_setup_rx:
5384 i40e_vsi_free_rx_resources(vsi);
5385err_setup_tx:
5386 i40e_vsi_free_tx_resources(vsi);
5387 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5388 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5389
5390 return err;
5391}
5392
17a73f6b
JG		 5393/**
5394 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5395 * @pf: Pointer to PF
17a73f6b
JG		 5396 *
5397 * This function destroys the hlist where all the Flow Director
5398 * filters were saved.
5399 **/
5400static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5401{
5402 struct i40e_fdir_filter *filter;
5403 struct hlist_node *node2;
5404
5405 hlist_for_each_entry_safe(filter, node2,
5406 &pf->fdir_filter_list, fdir_node) {
5407 hlist_del(&filter->fdir_node);
5408 kfree(filter);
5409 }
5410 pf->fdir_pf_active_filters = 0;
5411}
5412
41c445ff
JB		 5413/**
5414 * i40e_close - Disables a network interface
5415 * @netdev: network interface device structure
5416 *
5417 * The close entry point is called when an interface is de-activated
5418 * by the OS. The hardware is still under the driver's control, but
5419 * this netdev interface is disabled.
5420 *
5421 * Returns 0, this is not allowed to fail
5422 **/
38e00438
VD		 5423#ifdef I40E_FCOE
5424int i40e_close(struct net_device *netdev)
5425#else
41c445ff 5426static int i40e_close(struct net_device *netdev)
38e00438 5427#endif
41c445ff
JB		 5428{
5429 struct i40e_netdev_priv *np = netdev_priv(netdev);
5430 struct i40e_vsi *vsi = np->vsi;
5431
90ef8d47 5432 i40e_vsi_close(vsi);
41c445ff
JB		 5433
5434 return 0;
5435}
5436
5437/**
5438 * i40e_do_reset - Start a PF or Core Reset sequence
5439 * @pf: board private structure
5440 * @reset_flags: which reset is requested
5441 *
5442 * The essential difference in resets is that the PF Reset
5443 * doesn't clear the packet buffers, doesn't reset the PE
5444 * firmware, and doesn't bother the other PFs on the chip.
5445 **/
5446void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5447{
5448 u32 val;
5449
5450 WARN_ON(in_interrupt());
5451
263fc48f
MW		 5452 if (i40e_check_asq_alive(&pf->hw))
5453 i40e_vc_notify_reset(pf);
5454
41c445ff 5455 /* do the biggest reset indicated */
41a1d04b 5456 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5457
5458 /* Request a Global Reset
5459 *
5460 * This will start the chip's countdown to the actual full
5461 * chip reset event, and a warning interrupt to be sent
5462 * to all PFs, including the requestor. Our handler
5463 * for the warning interrupt will deal with the shutdown
5464 * and recovery of the switch setup.
5465 */
69bfb110 5466 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5467 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5468 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5469 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5470
41a1d04b 5471 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5472
5473 /* Request a Core Reset
5474 *
5475 * Same as Global Reset, except does *not* include the MAC/PHY
5476 */
69bfb110 5477 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5478 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5479 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5480 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5481 i40e_flush(&pf->hw);
5482
41a1d04b 5483 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5484
5485 /* Request a PF Reset
5486 *
5487 * Resets only the PF-specific registers
5488 *
5489 * This goes directly to the tear-down and rebuild of
5490 * the switch, since we need to do all the recovery as
5491 * for the Core Reset.
5492 */
69bfb110 5493 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5494 i40e_handle_reset_warning(pf);
5495
41a1d04b 5496 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5497 int v;
5498
5499 /* Find the VSI(s) that requested a re-init */
5500 dev_info(&pf->pdev->dev,
5501 "VSI reinit requested\n");
505682cd 5502 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5503 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5504
41c445ff
JB		 5505 if (vsi != NULL &&
5506 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5507 i40e_vsi_reinit_locked(pf->vsi[v]);
5508 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5509 }
5510 }
41a1d04b 5511 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5512 int v;
5513
5514 /* Find the VSI(s) that needs to be brought down */
5515 dev_info(&pf->pdev->dev, "VSI down requested\n");
5516 for (v = 0; v < pf->num_alloc_vsi; v++) {
5517 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5518
b5d06f05
NP		 5519 if (vsi != NULL &&
5520 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5521 set_bit(__I40E_DOWN, &vsi->state);
5522 i40e_down(vsi);
5523 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5524 }
5525 }
41c445ff
JB		 5526 } else {
5527 dev_info(&pf->pdev->dev,
5528 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5529 }
5530}
5531
4e3b35b0
NP		 5532#ifdef CONFIG_I40E_DCB
5533/**
5534 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5535 * @pf: board private structure
5536 * @old_cfg: current DCB config
5537 * @new_cfg: new DCB config
5538 **/
5539bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5540 struct i40e_dcbx_config *old_cfg,
5541 struct i40e_dcbx_config *new_cfg)
5542{
5543 bool need_reconfig = false;
5544
5545 /* Check if ETS configuration has changed */
5546 if (memcmp(&new_cfg->etscfg,
5547 &old_cfg->etscfg,
5548 sizeof(new_cfg->etscfg))) {
5549 /* If Priority Table has changed reconfig is needed */
5550 if (memcmp(&new_cfg->etscfg.prioritytable,
5551 &old_cfg->etscfg.prioritytable,
5552 sizeof(new_cfg->etscfg.prioritytable))) {
5553 need_reconfig = true;
69bfb110 5554 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5555 }
5556
5557 if (memcmp(&new_cfg->etscfg.tcbwtable,
5558 &old_cfg->etscfg.tcbwtable,
5559 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5560 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5561
5562 if (memcmp(&new_cfg->etscfg.tsatable,
5563 &old_cfg->etscfg.tsatable,
5564 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5565 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5566 }
5567
5568 /* Check if PFC configuration has changed */
5569 if (memcmp(&new_cfg->pfc,
5570 &old_cfg->pfc,
5571 sizeof(new_cfg->pfc))) {
5572 need_reconfig = true;
69bfb110 5573 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5574 }
5575
5576 /* Check if APP Table has changed */
5577 if (memcmp(&new_cfg->app,
5578 &old_cfg->app,
3d9667a9 5579 sizeof(new_cfg->app))) {
4e3b35b0 5580 need_reconfig = true;
69bfb110 5581 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5582 }
4e3b35b0 5583
fb43201f 5584 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5585 return need_reconfig;
5586}
5587
5588/**
5589 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5590 * @pf: board private structure
5591 * @e: event info posted on ARQ
5592 **/
5593static int i40e_handle_lldp_event(struct i40e_pf *pf,
5594 struct i40e_arq_event_info *e)
5595{
5596 struct i40e_aqc_lldp_get_mib *mib =
5597 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5598 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5599 struct i40e_dcbx_config tmp_dcbx_cfg;
5600 bool need_reconfig = false;
5601 int ret = 0;
5602 u8 type;
5603
4d9b6043
NP		 5604 /* Not DCB capable or capability disabled */
5605 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5606 return ret;
5607
4e3b35b0
NP		 5608 /* Ignore if event is not for Nearest Bridge */
5609 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5610 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5611 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5612 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5613 return ret;
5614
5615 /* Check MIB Type and return if event for Remote MIB update */
5616 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5617 dev_dbg(&pf->pdev->dev,
fb43201f 5618 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5619 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5620 /* Update the remote cached instance and return */
5621 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5622 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5623 &hw->remote_dcbx_config);
5624 goto exit;
5625 }
5626
9fa61dd2 5627 /* Store the old configuration */
1a2f6248 5628 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5629
750fcbcf
NP		 5630 /* Reset the old DCBx configuration data */
5631 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5632 /* Get updated DCBX data from firmware */
5633 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5634 if (ret) {
f1c7e72e
SN		 5635 dev_info(&pf->pdev->dev,
5636 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5637 i40e_stat_str(&pf->hw, ret),
5638 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5639 goto exit;
5640 }
5641
5642 /* No change detected in DCBX configs */
750fcbcf
NP		 5643 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5644 sizeof(tmp_dcbx_cfg))) {
69bfb110 5645 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5646 goto exit;
5647 }
5648
750fcbcf
NP		 5649 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5650 &hw->local_dcbx_config);
4e3b35b0 5651
750fcbcf 5652 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5653
5654 if (!need_reconfig)
5655 goto exit;
5656
4d9b6043 5657 /* Enable DCB tagging only when more than one TC */
750fcbcf 5658 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5659 pf->flags |= I40E_FLAG_DCB_ENABLED;
5660 else
5661 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5662
69129dc3 5663 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5664 /* Reconfiguration needed quiesce all VSIs */
5665 i40e_pf_quiesce_all_vsi(pf);
5666
5667 /* Changes in configuration update VEB/VSI */
5668 i40e_dcb_reconfigure(pf);
5669
2fd75f31
NP		 5670 ret = i40e_resume_port_tx(pf);
5671
69129dc3 5672 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5673 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5674 if (ret)
5675 goto exit;
5676
5677 /* Wait for the PF's Tx queues to be disabled */
5678 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5679 if (ret) {
5680 /* Schedule PF reset to recover */
5681 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5682 i40e_service_event_schedule(pf);
5683 } else {
2fd75f31 5684 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5685 }
5686
4e3b35b0
NP		 5687exit:
5688 return ret;
5689}
5690#endif /* CONFIG_I40E_DCB */
5691
23326186
ASJ		 5692/**
5693 * i40e_do_reset_safe - Protected reset path for userland calls.
5694 * @pf: board private structure
5695 * @reset_flags: which reset is requested
5696 *
5697 **/
5698void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5699{
5700 rtnl_lock();
5701 i40e_do_reset(pf, reset_flags);
5702 rtnl_unlock();
5703}
5704
41c445ff
JB		 5705/**
5706 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5707 * @pf: board private structure
5708 * @e: event info posted on ARQ
5709 *
5710 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5711 * and VF queues
5712 **/
5713static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5714 struct i40e_arq_event_info *e)
5715{
5716 struct i40e_aqc_lan_overflow *data =
5717 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5718 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5719 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5720 struct i40e_hw *hw = &pf->hw;
5721 struct i40e_vf *vf;
5722 u16 vf_id;
5723
69bfb110
JB		 5724 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5725 queue, qtx_ctl);
41c445ff
JB		 5726
5727 /* Queue belongs to VF, find the VF and issue VF reset */
5728 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5729 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5730 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5731 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5732 vf_id -= hw->func_caps.vf_base_id;
5733 vf = &pf->vf[vf_id];
5734 i40e_vc_notify_vf_reset(vf);
5735 /* Allow VF to process pending reset notification */
5736 msleep(20);
5737 i40e_reset_vf(vf, false);
5738 }
5739}
5740
5741/**
5742 * i40e_service_event_complete - Finish up the service event
5743 * @pf: board private structure
5744 **/
5745static void i40e_service_event_complete(struct i40e_pf *pf)
5746{
b875f99b 5747 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5748
5749 /* flush memory to make sure state is correct before next watchog */
4e857c58 5750 smp_mb__before_atomic();
41c445ff
JB		 5751 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5752}
5753
55a5e60b 5754/**
12957388
ASJ		 5755 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5756 * @pf: board private structure
5757 **/
04294e38 5758u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5759{
04294e38 5760 u32 val, fcnt_prog;
12957388
ASJ		 5761
5762 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5763 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5764 return fcnt_prog;
5765}
5766
5767/**
04294e38 5768 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5769 * @pf: board private structure
5770 **/
04294e38 5771u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5772{
04294e38
ASJ		 5773 u32 val, fcnt_prog;
5774
55a5e60b
ASJ		 5775 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5776 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5777 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5778 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5779 return fcnt_prog;
5780}
1e1be8f6 5781
04294e38
ASJ		 5782/**
5783 * i40e_get_global_fd_count - Get total FD filters programmed on device
5784 * @pf: board private structure
5785 **/
5786u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5787{
5788 u32 val, fcnt_prog;
5789
5790 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5791 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5792 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5793 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5794 return fcnt_prog;
5795}
5796
55a5e60b
ASJ		 5797/**
5798 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5799 * @pf: board private structure
5800 **/
5801void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5802{
3487b6c3 5803 struct i40e_fdir_filter *filter;
55a5e60b 5804 u32 fcnt_prog, fcnt_avail;
3487b6c3 5805 struct hlist_node *node;
55a5e60b 5806
1e1be8f6
ASJ		 5807 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5808 return;
5809
55a5e60b
ASJ		 5810 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5811 * to re-enable
5812 */
04294e38 5813 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5814 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5815 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5816 (pf->fd_add_err == 0) ||
5817 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5818 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5819 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5820 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5821 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5822 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5823 }
5824 }
5825 /* Wait for some more space to be available to turn on ATR */
5826 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5827 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5828 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5829 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5830 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5831 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5832 }
5833 }
3487b6c3
CW		 5834
5835 /* if hw had a problem adding a filter, delete it */
5836 if (pf->fd_inv > 0) {
5837 hlist_for_each_entry_safe(filter, node,
5838 &pf->fdir_filter_list, fdir_node) {
5839 if (filter->fd_id == pf->fd_inv) {
5840 hlist_del(&filter->fdir_node);
5841 kfree(filter);
5842 pf->fdir_pf_active_filters--;
5843 }
5844 }
5845 }
55a5e60b
ASJ		 5846}
5847
1e1be8f6 5848#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5849#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5850/**
5851 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5852 * @pf: board private structure
5853 **/
5854static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5855{
04294e38 5856 unsigned long min_flush_time;
1e1be8f6 5857 int flush_wait_retry = 50;
04294e38
ASJ		 5858 bool disable_atr = false;
5859 int fd_room;
1e1be8f6
ASJ		 5860 int reg;
5861
1790ed0c
AA		 5862 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5863 return;
5864
a5fdaf34
JB		 5865 if (!time_after(jiffies, pf->fd_flush_timestamp +
5866 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5867 return;
04294e38 5868
a5fdaf34
JB		 5869 /* If the flush is happening too quick and we have mostly SB rules we
5870 * should not re-enable ATR for some time.
5871 */
5872 min_flush_time = pf->fd_flush_timestamp +
5873 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5874 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5875
5876 if (!(time_after(jiffies, min_flush_time)) &&
5877 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5878 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5879 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5880 disable_atr = true;
5881 }
5882
5883 pf->fd_flush_timestamp = jiffies;
5884 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5885 /* flush all filters */
5886 wr32(&pf->hw, I40E_PFQF_CTL_1,
5887 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5888 i40e_flush(&pf->hw);
5889 pf->fd_flush_cnt++;
5890 pf->fd_add_err = 0;
5891 do {
5892 /* Check FD flush status every 5-6msec */
5893 usleep_range(5000, 6000);
5894 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5895 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5896 break;
5897 } while (flush_wait_retry--);
5898 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5899 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5900 } else {
5901 /* replay sideband filters */
5902 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5903 if (!disable_atr)
5904 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5905 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5906 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5907 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5908 }
a5fdaf34 5909
1e1be8f6
ASJ		 5910}
5911
5912/**
5913 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5914 * @pf: board private structure
5915 **/
04294e38 5916u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5917{
5918 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5919}
5920
5921/* We can see up to 256 filter programming desc in transit if the filters are
5922 * being applied really fast; before we see the first
5923 * filter miss error on Rx queue 0. Accumulating enough error messages before
5924 * reacting will make sure we don't cause flush too often.
5925 */
5926#define I40E_MAX_FD_PROGRAM_ERROR 256
5927
41c445ff
JB		 5928/**
5929 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5930 * @pf: board private structure
5931 **/
5932static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5933{
41c445ff 5934
41c445ff
JB		 5935 /* if interface is down do nothing */
5936 if (test_bit(__I40E_DOWN, &pf->state))
5937 return;
1e1be8f6 5938
1790ed0c
AA		 5939 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5940 return;
5941
04294e38 5942 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5943 i40e_fdir_flush_and_replay(pf);
5944
55a5e60b
ASJ		 5945 i40e_fdir_check_and_reenable(pf);
5946
41c445ff
JB		 5947}
5948
5949/**
5950 * i40e_vsi_link_event - notify VSI of a link event
5951 * @vsi: vsi to be notified
5952 * @link_up: link up or down
5953 **/
5954static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5955{
32b5b811 5956 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5957 return;
5958
5959 switch (vsi->type) {
5960 case I40E_VSI_MAIN:
38e00438
VD		 5961#ifdef I40E_FCOE
5962 case I40E_VSI_FCOE:
5963#endif
41c445ff
JB		 5964 if (!vsi->netdev || !vsi->netdev_registered)
5965 break;
5966
5967 if (link_up) {
5968 netif_carrier_on(vsi->netdev);
5969 netif_tx_wake_all_queues(vsi->netdev);
5970 } else {
5971 netif_carrier_off(vsi->netdev);
5972 netif_tx_stop_all_queues(vsi->netdev);
5973 }
5974 break;
5975
5976 case I40E_VSI_SRIOV:
41c445ff
JB		 5977 case I40E_VSI_VMDQ2:
5978 case I40E_VSI_CTRL:
5979 case I40E_VSI_MIRROR:
5980 default:
5981 /* there is no notification for other VSIs */
5982 break;
5983 }
5984}
5985
5986/**
5987 * i40e_veb_link_event - notify elements on the veb of a link event
5988 * @veb: veb to be notified
5989 * @link_up: link up or down
5990 **/
5991static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5992{
5993 struct i40e_pf *pf;
5994 int i;
5995
5996 if (!veb || !veb->pf)
5997 return;
5998 pf = veb->pf;
5999
6000 /* depth first... */
6001 for (i = 0; i < I40E_MAX_VEB; i++)
6002 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6003 i40e_veb_link_event(pf->veb[i], link_up);
6004
6005 /* ... now the local VSIs */
505682cd 6006 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6007 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6008 i40e_vsi_link_event(pf->vsi[i], link_up);
6009}
6010
6011/**
6012 * i40e_link_event - Update netif_carrier status
6013 * @pf: board private structure
6014 **/
6015static void i40e_link_event(struct i40e_pf *pf)
6016{
320684cd 6017 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6018 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6019 i40e_status status;
6020 bool new_link, old_link;
41c445ff 6021
1f9610e4
CS		 6022 /* save off old link status information */
6023 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6024
1e701e09
JB		 6025 /* set this to force the get_link_status call to refresh state */
6026 pf->hw.phy.get_link_info = true;
6027
41c445ff 6028 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6029
6030 status = i40e_get_link_status(&pf->hw, &new_link);
6031 if (status) {
6032 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6033 status);
6034 return;
6035 }
6036
fef59ddf
CS		 6037 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6038 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6039
1e701e09 6040 if (new_link == old_link &&
fef59ddf 6041 new_link_speed == old_link_speed &&
320684cd
MW		 6042 (test_bit(__I40E_DOWN, &vsi->state) ||
6043 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6044 return;
320684cd
MW		 6045
6046 if (!test_bit(__I40E_DOWN, &vsi->state))
6047 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6048
6049 /* Notify the base of the switch tree connected to
6050 * the link. Floating VEBs are not notified.
6051 */
6052 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6053 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6054 else
320684cd 6055 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6056
6057 if (pf->vf)
6058 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6059
6060 if (pf->flags & I40E_FLAG_PTP)
6061 i40e_ptp_set_increment(pf);
41c445ff
JB		 6062}
6063
41c445ff 6064/**
21536717 6065 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6066 * @pf: board private structure
6067 **/
6068static void i40e_watchdog_subtask(struct i40e_pf *pf)
6069{
6070 int i;
6071
6072 /* if interface is down do nothing */
6073 if (test_bit(__I40E_DOWN, &pf->state) ||
6074 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6075 return;
6076
21536717
SN		 6077 /* make sure we don't do these things too often */
6078 if (time_before(jiffies, (pf->service_timer_previous +
6079 pf->service_timer_period)))
6080 return;
6081 pf->service_timer_previous = jiffies;
6082
9ac77266
SN		 6083 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6084 i40e_link_event(pf);
21536717 6085
41c445ff
JB		 6086 /* Update the stats for active netdevs so the network stack
6087 * can look at updated numbers whenever it cares to
6088 */
505682cd 6089 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6090 if (pf->vsi[i] && pf->vsi[i]->netdev)
6091 i40e_update_stats(pf->vsi[i]);
6092
d1a8d275
ASJ		 6093 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6094 /* Update the stats for the active switching components */
6095 for (i = 0; i < I40E_MAX_VEB; i++)
6096 if (pf->veb[i])
6097 i40e_update_veb_stats(pf->veb[i]);
6098 }
beb0dff1
JK		 6099
6100 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6101}
6102
6103/**
6104 * i40e_reset_subtask - Set up for resetting the device and driver
6105 * @pf: board private structure
6106 **/
6107static void i40e_reset_subtask(struct i40e_pf *pf)
6108{
6109 u32 reset_flags = 0;
6110
23326186 6111 rtnl_lock();
41c445ff 6112 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 6113 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6114 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6115 }
6116 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 6117 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6118 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6119 }
6120 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 6121 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6122 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6123 }
6124 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 6125 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6126 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6127 }
b5d06f05 6128 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 6129 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6130 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6131 }
41c445ff
JB		 6132
6133 /* If there's a recovery already waiting, it takes
6134 * precedence before starting a new reset sequence.
6135 */
6136 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6137 i40e_handle_reset_warning(pf);
23326186 6138 goto unlock;
41c445ff
JB		 6139 }
6140
6141 /* If we're already down or resetting, just bail */
6142 if (reset_flags &&
6143 !test_bit(__I40E_DOWN, &pf->state) &&
6144 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6145 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6146
6147unlock:
6148 rtnl_unlock();
41c445ff
JB		 6149}
6150
6151/**
6152 * i40e_handle_link_event - Handle link event
6153 * @pf: board private structure
6154 * @e: event info posted on ARQ
6155 **/
6156static void i40e_handle_link_event(struct i40e_pf *pf,
6157 struct i40e_arq_event_info *e)
6158{
41c445ff
JB		 6159 struct i40e_aqc_get_link_status *status =
6160 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6161
1e701e09
JB		 6162 /* Do a new status request to re-enable LSE reporting
6163 * and load new status information into the hw struct
6164 * This completely ignores any state information
6165 * in the ARQ event info, instead choosing to always
6166 * issue the AQ update link status command.
6167 */
6168 i40e_link_event(pf);
6169
7b592f61
CW		 6170 /* check for unqualified module, if link is down */
6171 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6172 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6173 (!(status->link_info & I40E_AQ_LINK_UP)))
6174 dev_err(&pf->pdev->dev,
6175 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6176}
6177
6178/**
6179 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6180 * @pf: board private structure
6181 **/
6182static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6183{
6184 struct i40e_arq_event_info event;
6185 struct i40e_hw *hw = &pf->hw;
6186 u16 pending, i = 0;
6187 i40e_status ret;
6188 u16 opcode;
86df242b 6189 u32 oldval;
41c445ff
JB		 6190 u32 val;
6191
a316f651
ASJ		 6192 /* Do not run clean AQ when PF reset fails */
6193 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6194 return;
6195
86df242b
SN		 6196 /* check for error indications */
6197 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6198 oldval = val;
6199 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6200 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6201 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6202 }
6203 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6204 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6205 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6206 }
6207 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6208 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6209 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6210 }
6211 if (oldval != val)
6212 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6213
6214 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6215 oldval = val;
6216 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6217 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6218 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6219 }
6220 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6221 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6222 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6223 }
6224 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6225 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6226 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6227 }
6228 if (oldval != val)
6229 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6230
1001dc37
MW		 6231 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6232 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6233 if (!event.msg_buf)
6234 return;
6235
6236 do {
6237 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6238 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6239 break;
56497978 6240 else if (ret) {
41c445ff
JB		 6241 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6242 break;
6243 }
6244
6245 opcode = le16_to_cpu(event.desc.opcode);
6246 switch (opcode) {
6247
6248 case i40e_aqc_opc_get_link_status:
6249 i40e_handle_link_event(pf, &event);
6250 break;
6251 case i40e_aqc_opc_send_msg_to_pf:
6252 ret = i40e_vc_process_vf_msg(pf,
6253 le16_to_cpu(event.desc.retval),
6254 le32_to_cpu(event.desc.cookie_high),
6255 le32_to_cpu(event.desc.cookie_low),
6256 event.msg_buf,
1001dc37 6257 event.msg_len);
41c445ff
JB		 6258 break;
6259 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6260 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6261#ifdef CONFIG_I40E_DCB
6262 rtnl_lock();
6263 ret = i40e_handle_lldp_event(pf, &event);
6264 rtnl_unlock();
6265#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6266 break;
6267 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6268 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6269 i40e_handle_lan_overflow_event(pf, &event);
6270 break;
0467bc91
SN		 6271 case i40e_aqc_opc_send_msg_to_peer:
6272 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6273 break;
91a0f930
SN		 6274 case i40e_aqc_opc_nvm_erase:
6275 case i40e_aqc_opc_nvm_update:
6276 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6277 break;
41c445ff
JB		 6278 default:
6279 dev_info(&pf->pdev->dev,
0467bc91
SN		 6280 "ARQ Error: Unknown event 0x%04x received\n",
6281 opcode);
41c445ff
JB		 6282 break;
6283 }
6284 } while (pending && (i++ < pf->adminq_work_limit));
6285
6286 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6287 /* re-enable Admin queue interrupt cause */
6288 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6289 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6290 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6291 i40e_flush(hw);
6292
6293 kfree(event.msg_buf);
6294}
6295
4eb3f768
SN		 6296/**
6297 * i40e_verify_eeprom - make sure eeprom is good to use
6298 * @pf: board private structure
6299 **/
6300static void i40e_verify_eeprom(struct i40e_pf *pf)
6301{
6302 int err;
6303
6304 err = i40e_diag_eeprom_test(&pf->hw);
6305 if (err) {
6306 /* retry in case of garbage read */
6307 err = i40e_diag_eeprom_test(&pf->hw);
6308 if (err) {
6309 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6310 err);
6311 set_bit(__I40E_BAD_EEPROM, &pf->state);
6312 }
6313 }
6314
6315 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6316 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6317 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6318 }
6319}
6320
386a0afa
AA		 6321/**
6322 * i40e_enable_pf_switch_lb
b40c82e6 6323 * @pf: pointer to the PF structure
386a0afa
AA		 6324 *
6325 * enable switch loop back or die - no point in a return value
6326 **/
6327static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6328{
6329 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6330 struct i40e_vsi_context ctxt;
f1c7e72e 6331 int ret;
386a0afa
AA		 6332
6333 ctxt.seid = pf->main_vsi_seid;
6334 ctxt.pf_num = pf->hw.pf_id;
6335 ctxt.vf_num = 0;
f1c7e72e
SN		 6336 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6337 if (ret) {
386a0afa 6338 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6339 "couldn't get PF vsi config, err %s aq_err %s\n",
6340 i40e_stat_str(&pf->hw, ret),
6341 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6342 return;
6343 }
6344 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6345 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6346 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6347
f1c7e72e
SN		 6348 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6349 if (ret) {
386a0afa 6350 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6351 "update vsi switch failed, err %s aq_err %s\n",
6352 i40e_stat_str(&pf->hw, ret),
6353 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6354 }
6355}
6356
6357/**
6358 * i40e_disable_pf_switch_lb
b40c82e6 6359 * @pf: pointer to the PF structure
386a0afa
AA		 6360 *
6361 * disable switch loop back or die - no point in a return value
6362 **/
6363static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6364{
6365 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6366 struct i40e_vsi_context ctxt;
f1c7e72e 6367 int ret;
386a0afa
AA		 6368
6369 ctxt.seid = pf->main_vsi_seid;
6370 ctxt.pf_num = pf->hw.pf_id;
6371 ctxt.vf_num = 0;
f1c7e72e
SN		 6372 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6373 if (ret) {
386a0afa 6374 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6375 "couldn't get PF vsi config, err %s aq_err %s\n",
6376 i40e_stat_str(&pf->hw, ret),
6377 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6378 return;
6379 }
6380 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6381 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6382 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6383
f1c7e72e
SN		 6384 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6385 if (ret) {
386a0afa 6386 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6387 "update vsi switch failed, err %s aq_err %s\n",
6388 i40e_stat_str(&pf->hw, ret),
6389 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6390 }
6391}
6392
51616018
NP		 6393/**
6394 * i40e_config_bridge_mode - Configure the HW bridge mode
6395 * @veb: pointer to the bridge instance
6396 *
6397 * Configure the loop back mode for the LAN VSI that is downlink to the
6398 * specified HW bridge instance. It is expected this function is called
6399 * when a new HW bridge is instantiated.
6400 **/
6401static void i40e_config_bridge_mode(struct i40e_veb *veb)
6402{
6403 struct i40e_pf *pf = veb->pf;
6404
6dec1017
SN		 6405 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6406 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6407 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6408 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6409 i40e_disable_pf_switch_lb(pf);
6410 else
6411 i40e_enable_pf_switch_lb(pf);
6412}
6413
41c445ff
JB		 6414/**
6415 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6416 * @veb: pointer to the VEB instance
6417 *
6418 * This is a recursive function that first builds the attached VSIs then
6419 * recurses in to build the next layer of VEB. We track the connections
6420 * through our own index numbers because the seid's from the HW could
6421 * change across the reset.
6422 **/
6423static int i40e_reconstitute_veb(struct i40e_veb *veb)
6424{
6425 struct i40e_vsi *ctl_vsi = NULL;
6426 struct i40e_pf *pf = veb->pf;
6427 int v, veb_idx;
6428 int ret;
6429
6430 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6431 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6432 if (pf->vsi[v] &&
6433 pf->vsi[v]->veb_idx == veb->idx &&
6434 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6435 ctl_vsi = pf->vsi[v];
6436 break;
6437 }
6438 }
6439 if (!ctl_vsi) {
6440 dev_info(&pf->pdev->dev,
6441 "missing owner VSI for veb_idx %d\n", veb->idx);
6442 ret = -ENOENT;
6443 goto end_reconstitute;
6444 }
6445 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6446 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6447 ret = i40e_add_vsi(ctl_vsi);
6448 if (ret) {
6449 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6450 "rebuild of veb_idx %d owner VSI failed: %d\n",
6451 veb->idx, ret);
41c445ff
JB		 6452 goto end_reconstitute;
6453 }
6454 i40e_vsi_reset_stats(ctl_vsi);
6455
6456 /* create the VEB in the switch and move the VSI onto the VEB */
6457 ret = i40e_add_veb(veb, ctl_vsi);
6458 if (ret)
6459 goto end_reconstitute;
6460
fc60861e
ASJ		 6461 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6462 veb->bridge_mode = BRIDGE_MODE_VEB;
6463 else
6464 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6465 i40e_config_bridge_mode(veb);
b64ba084 6466
41c445ff 6467 /* create the remaining VSIs attached to this VEB */
505682cd 6468 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6469 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6470 continue;
6471
6472 if (pf->vsi[v]->veb_idx == veb->idx) {
6473 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6474
41c445ff
JB		 6475 vsi->uplink_seid = veb->seid;
6476 ret = i40e_add_vsi(vsi);
6477 if (ret) {
6478 dev_info(&pf->pdev->dev,
6479 "rebuild of vsi_idx %d failed: %d\n",
6480 v, ret);
6481 goto end_reconstitute;
6482 }
6483 i40e_vsi_reset_stats(vsi);
6484 }
6485 }
6486
6487 /* create any VEBs attached to this VEB - RECURSION */
6488 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6489 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6490 pf->veb[veb_idx]->uplink_seid = veb->seid;
6491 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6492 if (ret)
6493 break;
6494 }
6495 }
6496
6497end_reconstitute:
6498 return ret;
6499}
6500
6501/**
6502 * i40e_get_capabilities - get info about the HW
6503 * @pf: the PF struct
6504 **/
6505static int i40e_get_capabilities(struct i40e_pf *pf)
6506{
6507 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6508 u16 data_size;
6509 int buf_len;
6510 int err;
6511
6512 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6513 do {
6514 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6515 if (!cap_buf)
6516 return -ENOMEM;
6517
6518 /* this loads the data into the hw struct for us */
6519 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6520 &data_size,
6521 i40e_aqc_opc_list_func_capabilities,
6522 NULL);
6523 /* data loaded, buffer no longer needed */
6524 kfree(cap_buf);
6525
6526 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6527 /* retry with a larger buffer */
6528 buf_len = data_size;
6529 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6530 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6531 "capability discovery failed, err %s aq_err %s\n",
6532 i40e_stat_str(&pf->hw, err),
6533 i40e_aq_str(&pf->hw,
6534 pf->hw.aq.asq_last_status));
41c445ff
JB		 6535 return -ENODEV;
6536 }
6537 } while (err);
6538
6539 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6540 dev_info(&pf->pdev->dev,
6541 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6542 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6543 pf->hw.func_caps.num_msix_vectors,
6544 pf->hw.func_caps.num_msix_vectors_vf,
6545 pf->hw.func_caps.fd_filters_guaranteed,
6546 pf->hw.func_caps.fd_filters_best_effort,
6547 pf->hw.func_caps.num_tx_qp,
6548 pf->hw.func_caps.num_vsis);
6549
7134f9ce
JB		 6550#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6551 + pf->hw.func_caps.num_vfs)
6552 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6553 dev_info(&pf->pdev->dev,
6554 "got num_vsis %d, setting num_vsis to %d\n",
6555 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6556 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6557 }
6558
41c445ff
JB		 6559 return 0;
6560}
6561
cbf61325
ASJ		 6562static int i40e_vsi_clear(struct i40e_vsi *vsi);
6563
41c445ff 6564/**
cbf61325 6565 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6566 * @pf: board private structure
6567 **/
cbf61325 6568static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6569{
6570 struct i40e_vsi *vsi;
8a9eb7d3 6571 int i;
41c445ff 6572
407e063c
JB		 6573 /* quick workaround for an NVM issue that leaves a critical register
6574 * uninitialized
6575 */
6576 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6577 static const u32 hkey[] = {
6578 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6579 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6580 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6581 0x95b3a76d};
6582
6583 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6584 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6585 }
6586
cbf61325 6587 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6588 return;
6589
cbf61325 6590 /* find existing VSI and see if it needs configuring */
41c445ff 6591 vsi = NULL;
505682cd 6592 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6593 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6594 vsi = pf->vsi[i];
cbf61325
ASJ		 6595 break;
6596 }
6597 }
6598
6599 /* create a new VSI if none exists */
41c445ff 6600 if (!vsi) {
cbf61325
ASJ		 6601 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6602 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6603 if (!vsi) {
6604 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6605 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6606 return;
41c445ff 6607 }
cbf61325 6608 }
41c445ff 6609
8a9eb7d3 6610 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6611}
6612
6613/**
6614 * i40e_fdir_teardown - release the Flow Director resources
6615 * @pf: board private structure
6616 **/
6617static void i40e_fdir_teardown(struct i40e_pf *pf)
6618{
6619 int i;
6620
17a73f6b 6621 i40e_fdir_filter_exit(pf);
505682cd 6622 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6623 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6624 i40e_vsi_release(pf->vsi[i]);
6625 break;
6626 }
6627 }
6628}
6629
6630/**
f650a38b 6631 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6632 * @pf: board private structure
6633 *
b40c82e6 6634 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6635 **/
23cfbe07 6636static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6637{
41c445ff 6638 struct i40e_hw *hw = &pf->hw;
60442dea 6639 i40e_status ret = 0;
41c445ff
JB		 6640 u32 v;
6641
6642 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6643 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6644 return;
41c445ff 6645
69bfb110 6646 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6647
41c445ff
JB		 6648 /* quiesce the VSIs and their queues that are not already DOWN */
6649 i40e_pf_quiesce_all_vsi(pf);
6650
505682cd 6651 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6652 if (pf->vsi[v])
6653 pf->vsi[v]->seid = 0;
6654 }
6655
6656 i40e_shutdown_adminq(&pf->hw);
6657
f650a38b 6658 /* call shutdown HMC */
60442dea
SN		 6659 if (hw->hmc.hmc_obj) {
6660 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6661 if (ret)
60442dea
SN		 6662 dev_warn(&pf->pdev->dev,
6663 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6664 }
f650a38b
ASJ		 6665}
6666
44033fac
JB		 6667/**
6668 * i40e_send_version - update firmware with driver version
6669 * @pf: PF struct
6670 */
6671static void i40e_send_version(struct i40e_pf *pf)
6672{
6673 struct i40e_driver_version dv;
6674
6675 dv.major_version = DRV_VERSION_MAJOR;
6676 dv.minor_version = DRV_VERSION_MINOR;
6677 dv.build_version = DRV_VERSION_BUILD;
6678 dv.subbuild_version = 0;
35a7d804 6679 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6680 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6681}
6682
f650a38b 6683/**
4dda12e6 6684 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6685 * @pf: board private structure
bc7d338f 6686 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6687 **/
bc7d338f 6688static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6689{
f650a38b 6690 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6691 u8 set_fc_aq_fail = 0;
f650a38b 6692 i40e_status ret;
4f2f017c 6693 u32 val;
f650a38b
ASJ		 6694 u32 v;
6695
41c445ff
JB		 6696 /* Now we wait for GRST to settle out.
6697 * We don't have to delete the VEBs or VSIs from the hw switch
6698 * because the reset will make them disappear.
6699 */
6700 ret = i40e_pf_reset(hw);
b5565400 6701 if (ret) {
41c445ff 6702 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6703 set_bit(__I40E_RESET_FAILED, &pf->state);
6704 goto clear_recovery;
b5565400 6705 }
41c445ff
JB		 6706 pf->pfr_count++;
6707
6708 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6709 goto clear_recovery;
69bfb110 6710 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6711
6712 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6713 ret = i40e_init_adminq(&pf->hw);
6714 if (ret) {
f1c7e72e
SN		 6715 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6716 i40e_stat_str(&pf->hw, ret),
6717 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6718 goto clear_recovery;
41c445ff
JB		 6719 }
6720
4eb3f768 6721 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6722 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6723 i40e_verify_eeprom(pf);
4eb3f768 6724
e78ac4bf 6725 i40e_clear_pxe_mode(hw);
41c445ff 6726 ret = i40e_get_capabilities(pf);
f1c7e72e 6727 if (ret)
41c445ff 6728 goto end_core_reset;
41c445ff 6729
41c445ff
JB		 6730 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6731 hw->func_caps.num_rx_qp,
6732 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6733 if (ret) {
6734 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6735 goto end_core_reset;
6736 }
6737 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6738 if (ret) {
6739 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6740 goto end_core_reset;
6741 }
6742
4e3b35b0
NP		 6743#ifdef CONFIG_I40E_DCB
6744 ret = i40e_init_pf_dcb(pf);
6745 if (ret) {
aebfc816
SN		 6746 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6747 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6748 /* Continue without DCB enabled */
4e3b35b0
NP		 6749 }
6750#endif /* CONFIG_I40E_DCB */
38e00438 6751#ifdef I40E_FCOE
21364bcf 6752 i40e_init_pf_fcoe(pf);
4e3b35b0 6753
38e00438 6754#endif
41c445ff 6755 /* do basic switch setup */
bc7d338f 6756 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6757 if (ret)
6758 goto end_core_reset;
6759
7e2453fe
JB		 6760 /* driver is only interested in link up/down and module qualification
6761 * reports from firmware
6762 */
6763 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6764 I40E_AQ_EVENT_LINK_UPDOWN |
6765 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6766 if (ret)
f1c7e72e
SN		 6767 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6768 i40e_stat_str(&pf->hw, ret),
6769 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6770
cafa2ee6
ASJ		 6771 /* make sure our flow control settings are restored */
6772 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6773 if (ret)
8279e495
NP		 6774 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6775 i40e_stat_str(&pf->hw, ret),
6776 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6777
41c445ff
JB		 6778 /* Rebuild the VSIs and VEBs that existed before reset.
6779 * They are still in our local switch element arrays, so only
6780 * need to rebuild the switch model in the HW.
6781 *
6782 * If there were VEBs but the reconstitution failed, we'll try
6783 * try to recover minimal use by getting the basic PF VSI working.
6784 */
6785 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6786 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6787 /* find the one VEB connected to the MAC, and find orphans */
6788 for (v = 0; v < I40E_MAX_VEB; v++) {
6789 if (!pf->veb[v])
6790 continue;
6791
6792 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6793 pf->veb[v]->uplink_seid == 0) {
6794 ret = i40e_reconstitute_veb(pf->veb[v]);
6795
6796 if (!ret)
6797 continue;
6798
6799 /* If Main VEB failed, we're in deep doodoo,
6800 * so give up rebuilding the switch and set up
6801 * for minimal rebuild of PF VSI.
6802 * If orphan failed, we'll report the error
6803 * but try to keep going.
6804 */
6805 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6806 dev_info(&pf->pdev->dev,
6807 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6808 ret);
6809 pf->vsi[pf->lan_vsi]->uplink_seid
6810 = pf->mac_seid;
6811 break;
6812 } else if (pf->veb[v]->uplink_seid == 0) {
6813 dev_info(&pf->pdev->dev,
6814 "rebuild of orphan VEB failed: %d\n",
6815 ret);
6816 }
6817 }
6818 }
6819 }
6820
6821 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6822 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6823 /* no VEB, so rebuild only the Main VSI */
6824 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6825 if (ret) {
6826 dev_info(&pf->pdev->dev,
6827 "rebuild of Main VSI failed: %d\n", ret);
6828 goto end_core_reset;
6829 }
6830 }
6831
4f2f017c
ASJ		 6832 /* Reconfigure hardware for allowing smaller MSS in the case
6833 * of TSO, so that we avoid the MDD being fired and causing
6834 * a reset in the case of small MSS+TSO.
6835 */
6836#define I40E_REG_MSS 0x000E64DC
6837#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6838#define I40E_64BYTE_MSS 0x400000
6839 val = rd32(hw, I40E_REG_MSS);
6840 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6841 val &= ~I40E_REG_MSS_MIN_MASK;
6842 val |= I40E_64BYTE_MSS;
6843 wr32(hw, I40E_REG_MSS, val);
6844 }
6845
025b4a54
ASJ		 6846 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6847 (pf->hw.aq.fw_maj_ver < 4)) {
6848 msleep(75);
6849 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6850 if (ret)
f1c7e72e
SN		 6851 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6852 i40e_stat_str(&pf->hw, ret),
6853 i40e_aq_str(&pf->hw,
6854 pf->hw.aq.asq_last_status));
cafa2ee6 6855 }
41c445ff
JB		 6856 /* reinit the misc interrupt */
6857 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6858 ret = i40e_setup_misc_vector(pf);
6859
e7358f54
ASJ		 6860 /* Add a filter to drop all Flow control frames from any VSI from being
6861 * transmitted. By doing so we stop a malicious VF from sending out
6862 * PAUSE or PFC frames and potentially controlling traffic for other
6863 * PF/VF VSIs.
6864 * The FW can still send Flow control frames if enabled.
6865 */
6866 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6867 pf->main_vsi_seid);
6868
41c445ff
JB		 6869 /* restart the VSIs that were rebuilt and running before the reset */
6870 i40e_pf_unquiesce_all_vsi(pf);
6871
69f64b2b
MW		 6872 if (pf->num_alloc_vfs) {
6873 for (v = 0; v < pf->num_alloc_vfs; v++)
6874 i40e_reset_vf(&pf->vf[v], true);
6875 }
6876
41c445ff 6877 /* tell the firmware that we're starting */
44033fac 6878 i40e_send_version(pf);
41c445ff
JB		 6879
6880end_core_reset:
a316f651
ASJ		 6881 clear_bit(__I40E_RESET_FAILED, &pf->state);
6882clear_recovery:
41c445ff
JB		 6883 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6884}
6885
f650a38b 6886/**
b40c82e6 6887 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6888 * @pf: board private structure
6889 *
6890 * Close up the VFs and other things in prep for a Core Reset,
6891 * then get ready to rebuild the world.
6892 **/
6893static void i40e_handle_reset_warning(struct i40e_pf *pf)
6894{
23cfbe07
SN		 6895 i40e_prep_for_reset(pf);
6896 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6897}
6898
41c445ff
JB		 6899/**
6900 * i40e_handle_mdd_event
b40c82e6 6901 * @pf: pointer to the PF structure
41c445ff
JB		 6902 *
6903 * Called from the MDD irq handler to identify possibly malicious vfs
6904 **/
6905static void i40e_handle_mdd_event(struct i40e_pf *pf)
6906{
6907 struct i40e_hw *hw = &pf->hw;
6908 bool mdd_detected = false;
df430b12 6909 bool pf_mdd_detected = false;
41c445ff
JB		 6910 struct i40e_vf *vf;
6911 u32 reg;
6912 int i;
6913
6914 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6915 return;
6916
6917 /* find what triggered the MDD event */
6918 reg = rd32(hw, I40E_GL_MDET_TX);
6919 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6920 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6921 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6922 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6923 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6924 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6925 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6926 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6927 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6928 pf->hw.func_caps.base_queue;
faf32978 6929 if (netif_msg_tx_err(pf))
b40c82e6 6930 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6931 event, queue, pf_num, vf_num);
41c445ff
JB		 6932 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6933 mdd_detected = true;
6934 }
6935 reg = rd32(hw, I40E_GL_MDET_RX);
6936 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6937 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6938 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6939 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6940 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6941 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6942 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6943 pf->hw.func_caps.base_queue;
faf32978
JB		 6944 if (netif_msg_rx_err(pf))
6945 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6946 event, queue, func);
41c445ff
JB		 6947 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6948 mdd_detected = true;
6949 }
6950
df430b12
NP		 6951 if (mdd_detected) {
6952 reg = rd32(hw, I40E_PF_MDET_TX);
6953 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6954 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6955 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6956 pf_mdd_detected = true;
6957 }
6958 reg = rd32(hw, I40E_PF_MDET_RX);
6959 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6960 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6961 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6962 pf_mdd_detected = true;
6963 }
6964 /* Queue belongs to the PF, initiate a reset */
6965 if (pf_mdd_detected) {
6966 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6967 i40e_service_event_schedule(pf);
6968 }
6969 }
6970
41c445ff
JB		 6971 /* see if one of the VFs needs its hand slapped */
6972 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6973 vf = &(pf->vf[i]);
6974 reg = rd32(hw, I40E_VP_MDET_TX(i));
6975 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6976 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6977 vf->num_mdd_events++;
faf32978
JB		 6978 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6979 i);
41c445ff
JB		 6980 }
6981
6982 reg = rd32(hw, I40E_VP_MDET_RX(i));
6983 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6984 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6985 vf->num_mdd_events++;
faf32978
JB		 6986 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6987 i);
41c445ff
JB		 6988 }
6989
6990 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6991 dev_info(&pf->pdev->dev,
6992 "Too many MDD events on VF %d, disabled\n", i);
6993 dev_info(&pf->pdev->dev,
6994 "Use PF Control I/F to re-enable the VF\n");
6995 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6996 }
6997 }
6998
6999 /* re-enable mdd interrupt cause */
7000 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7001 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7002 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7003 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7004 i40e_flush(hw);
7005}
7006
a1c9a9d9
JK		 7007#ifdef CONFIG_I40E_VXLAN
7008/**
7009 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
7010 * @pf: board private structure
7011 **/
7012static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
7013{
a1c9a9d9
JK		 7014 struct i40e_hw *hw = &pf->hw;
7015 i40e_status ret;
a1c9a9d9
JK		 7016 __be16 port;
7017 int i;
7018
7019 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
7020 return;
7021
7022 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
7023
7024 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 7025 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
7026 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 7027 port = pf->vxlan_ports[i];
c22c06c8
SN		 7028 if (port)
7029 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 7030 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 7031 NULL, NULL);
7032 else
7033 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7034
7035 if (ret) {
c22c06c8 7036 dev_info(&pf->pdev->dev,
f1c7e72e 7037 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 7038 port ? "add" : "delete",
f1c7e72e
SN		 7039 ntohs(port), i,
7040 i40e_stat_str(&pf->hw, ret),
7041 i40e_aq_str(&pf->hw,
7042 pf->hw.aq.asq_last_status));
a1c9a9d9 7043 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 7044 }
7045 }
7046 }
7047}
7048
7049#endif
41c445ff
JB		 7050/**
7051 * i40e_service_task - Run the driver's async subtasks
7052 * @work: pointer to work_struct containing our data
7053 **/
7054static void i40e_service_task(struct work_struct *work)
7055{
7056 struct i40e_pf *pf = container_of(work,
7057 struct i40e_pf,
7058 service_task);
7059 unsigned long start_time = jiffies;
7060
e57a2fea
SN		 7061 /* don't bother with service tasks if a reset is in progress */
7062 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7063 i40e_service_event_complete(pf);
7064 return;
7065 }
7066
b03a8c1f 7067 i40e_detect_recover_hung(pf);
41c445ff
JB		 7068 i40e_reset_subtask(pf);
7069 i40e_handle_mdd_event(pf);
7070 i40e_vc_process_vflr_event(pf);
7071 i40e_watchdog_subtask(pf);
7072 i40e_fdir_reinit_subtask(pf);
41c445ff 7073 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 7074#ifdef CONFIG_I40E_VXLAN
7075 i40e_sync_vxlan_filters_subtask(pf);
7076#endif
41c445ff
JB		 7077 i40e_clean_adminq_subtask(pf);
7078
7079 i40e_service_event_complete(pf);
7080
7081 /* If the tasks have taken longer than one timer cycle or there
7082 * is more work to be done, reschedule the service task now
7083 * rather than wait for the timer to tick again.
7084 */
7085 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7086 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7087 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7088 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7089 i40e_service_event_schedule(pf);
7090}
7091
7092/**
7093 * i40e_service_timer - timer callback
7094 * @data: pointer to PF struct
7095 **/
7096static void i40e_service_timer(unsigned long data)
7097{
7098 struct i40e_pf *pf = (struct i40e_pf *)data;
7099
7100 mod_timer(&pf->service_timer,
7101 round_jiffies(jiffies + pf->service_timer_period));
7102 i40e_service_event_schedule(pf);
7103}
7104
7105/**
7106 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7107 * @vsi: the VSI being configured
7108 **/
7109static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7110{
7111 struct i40e_pf *pf = vsi->back;
7112
7113 switch (vsi->type) {
7114 case I40E_VSI_MAIN:
7115 vsi->alloc_queue_pairs = pf->num_lan_qps;
7116 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7117 I40E_REQ_DESCRIPTOR_MULTIPLE);
7118 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7119 vsi->num_q_vectors = pf->num_lan_msix;
7120 else
7121 vsi->num_q_vectors = 1;
7122
7123 break;
7124
7125 case I40E_VSI_FDIR:
7126 vsi->alloc_queue_pairs = 1;
7127 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7128 I40E_REQ_DESCRIPTOR_MULTIPLE);
7129 vsi->num_q_vectors = 1;
7130 break;
7131
7132 case I40E_VSI_VMDQ2:
7133 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7134 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7135 I40E_REQ_DESCRIPTOR_MULTIPLE);
7136 vsi->num_q_vectors = pf->num_vmdq_msix;
7137 break;
7138
7139 case I40E_VSI_SRIOV:
7140 vsi->alloc_queue_pairs = pf->num_vf_qps;
7141 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7142 I40E_REQ_DESCRIPTOR_MULTIPLE);
7143 break;
7144
38e00438
VD		 7145#ifdef I40E_FCOE
7146 case I40E_VSI_FCOE:
7147 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7148 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7149 I40E_REQ_DESCRIPTOR_MULTIPLE);
7150 vsi->num_q_vectors = pf->num_fcoe_msix;
7151 break;
7152
7153#endif /* I40E_FCOE */
41c445ff
JB		 7154 default:
7155 WARN_ON(1);
7156 return -ENODATA;
7157 }
7158
7159 return 0;
7160}
7161
f650a38b
ASJ		 7162/**
7163 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7164 * @type: VSI pointer
bc7d338f 7165 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7166 *
7167 * On error: returns error code (negative)
7168 * On success: returns 0
7169 **/
bc7d338f 7170static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7171{
7172 int size;
7173 int ret = 0;
7174
ac6c5e3d 7175 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7176 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7177 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7178 if (!vsi->tx_rings)
7179 return -ENOMEM;
f650a38b
ASJ		 7180 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7181
bc7d338f
ASJ		 7182 if (alloc_qvectors) {
7183 /* allocate memory for q_vector pointers */
f57e4fbd 7184 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7185 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7186 if (!vsi->q_vectors) {
7187 ret = -ENOMEM;
7188 goto err_vectors;
7189 }
f650a38b
ASJ		 7190 }
7191 return ret;
7192
7193err_vectors:
7194 kfree(vsi->tx_rings);
7195 return ret;
7196}
7197
41c445ff
JB		 7198/**
7199 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7200 * @pf: board private structure
7201 * @type: type of VSI
7202 *
7203 * On error: returns error code (negative)
7204 * On success: returns vsi index in PF (positive)
7205 **/
7206static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7207{
7208 int ret = -ENODEV;
7209 struct i40e_vsi *vsi;
7210 int vsi_idx;
7211 int i;
7212
7213 /* Need to protect the allocation of the VSIs at the PF level */
7214 mutex_lock(&pf->switch_mutex);
7215
7216 /* VSI list may be fragmented if VSI creation/destruction has
7217 * been happening. We can afford to do a quick scan to look
7218 * for any free VSIs in the list.
7219 *
7220 * find next empty vsi slot, looping back around if necessary
7221 */
7222 i = pf->next_vsi;
505682cd 7223 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7224 i++;
505682cd 7225 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7226 i = 0;
7227 while (i < pf->next_vsi && pf->vsi[i])
7228 i++;
7229 }
7230
505682cd 7231 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7232 vsi_idx = i; /* Found one! */
7233 } else {
7234 ret = -ENODEV;
493fb300 7235 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7236 }
7237 pf->next_vsi = ++i;
7238
7239 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7240 if (!vsi) {
7241 ret = -ENOMEM;
493fb300 7242 goto unlock_pf;
41c445ff
JB		 7243 }
7244 vsi->type = type;
7245 vsi->back = pf;
7246 set_bit(__I40E_DOWN, &vsi->state);
7247 vsi->flags = 0;
7248 vsi->idx = vsi_idx;
7249 vsi->rx_itr_setting = pf->rx_itr_default;
7250 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7251 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7252 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7253 pf->rss_table_size : 64;
41c445ff
JB		 7254 vsi->netdev_registered = false;
7255 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7256 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7257 vsi->irqs_ready = false;
41c445ff 7258
9f65e15b
AD		 7259 ret = i40e_set_num_rings_in_vsi(vsi);
7260 if (ret)
7261 goto err_rings;
7262
bc7d338f 7263 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7264 if (ret)
9f65e15b 7265 goto err_rings;
493fb300 7266
41c445ff
JB		 7267 /* Setup default MSIX irq handler for VSI */
7268 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7269
21659035
KP		 7270 /* Initialize VSI lock */
7271 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7272 pf->vsi[vsi_idx] = vsi;
7273 ret = vsi_idx;
493fb300
AD		 7274 goto unlock_pf;
7275
9f65e15b 7276err_rings:
493fb300
AD		 7277 pf->next_vsi = i - 1;
7278 kfree(vsi);
7279unlock_pf:
41c445ff
JB		 7280 mutex_unlock(&pf->switch_mutex);
7281 return ret;
7282}
7283
f650a38b
ASJ		 7284/**
7285 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7286 * @type: VSI pointer
bc7d338f 7287 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7288 *
7289 * On error: returns error code (negative)
7290 * On success: returns 0
7291 **/
bc7d338f 7292static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7293{
7294 /* free the ring and vector containers */
bc7d338f
ASJ		 7295 if (free_qvectors) {
7296 kfree(vsi->q_vectors);
7297 vsi->q_vectors = NULL;
7298 }
f650a38b
ASJ		 7299 kfree(vsi->tx_rings);
7300 vsi->tx_rings = NULL;
7301 vsi->rx_rings = NULL;
7302}
7303
28c5869f
HZ		 7304/**
7305 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7306 * and lookup table
7307 * @vsi: Pointer to VSI structure
7308 */
7309static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7310{
7311 if (!vsi)
7312 return;
7313
7314 kfree(vsi->rss_hkey_user);
7315 vsi->rss_hkey_user = NULL;
7316
7317 kfree(vsi->rss_lut_user);
7318 vsi->rss_lut_user = NULL;
7319}
7320
41c445ff
JB		 7321/**
7322 * i40e_vsi_clear - Deallocate the VSI provided
7323 * @vsi: the VSI being un-configured
7324 **/
7325static int i40e_vsi_clear(struct i40e_vsi *vsi)
7326{
7327 struct i40e_pf *pf;
7328
7329 if (!vsi)
7330 return 0;
7331
7332 if (!vsi->back)
7333 goto free_vsi;
7334 pf = vsi->back;
7335
7336 mutex_lock(&pf->switch_mutex);
7337 if (!pf->vsi[vsi->idx]) {
7338 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7339 vsi->idx, vsi->idx, vsi, vsi->type);
7340 goto unlock_vsi;
7341 }
7342
7343 if (pf->vsi[vsi->idx] != vsi) {
7344 dev_err(&pf->pdev->dev,
7345 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7346 pf->vsi[vsi->idx]->idx,
7347 pf->vsi[vsi->idx],
7348 pf->vsi[vsi->idx]->type,
7349 vsi->idx, vsi, vsi->type);
7350 goto unlock_vsi;
7351 }
7352
b40c82e6 7353 /* updates the PF for this cleared vsi */
41c445ff
JB		 7354 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7355 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7356
bc7d338f 7357 i40e_vsi_free_arrays(vsi, true);
28c5869f 7358 i40e_clear_rss_config_user(vsi);
493fb300 7359
41c445ff
JB		 7360 pf->vsi[vsi->idx] = NULL;
7361 if (vsi->idx < pf->next_vsi)
7362 pf->next_vsi = vsi->idx;
7363
7364unlock_vsi:
7365 mutex_unlock(&pf->switch_mutex);
7366free_vsi:
7367 kfree(vsi);
7368
7369 return 0;
7370}
7371
9f65e15b
AD		 7372/**
7373 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7374 * @vsi: the VSI being cleaned
7375 **/
be1d5eea 7376static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7377{
7378 int i;
7379
8e9dca53 7380 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7381 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7382 kfree_rcu(vsi->tx_rings[i], rcu);
7383 vsi->tx_rings[i] = NULL;
7384 vsi->rx_rings[i] = NULL;
7385 }
be1d5eea 7386 }
9f65e15b
AD		 7387}
7388
41c445ff
JB		 7389/**
7390 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7391 * @vsi: the VSI being configured
7392 **/
7393static int i40e_alloc_rings(struct i40e_vsi *vsi)
7394{
e7046ee1 7395 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7396 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7397 int i;
7398
41c445ff 7399 /* Set basic values in the rings to be used later during open() */
d7397644 7400 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7401 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7402 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7403 if (!tx_ring)
7404 goto err_out;
41c445ff
JB		 7405
7406 tx_ring->queue_index = i;
7407 tx_ring->reg_idx = vsi->base_queue + i;
7408 tx_ring->ring_active = false;
7409 tx_ring->vsi = vsi;
7410 tx_ring->netdev = vsi->netdev;
7411 tx_ring->dev = &pf->pdev->dev;
7412 tx_ring->count = vsi->num_desc;
7413 tx_ring->size = 0;
7414 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7415 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7416 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7417 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7418 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7419 vsi->tx_rings[i] = tx_ring;
41c445ff 7420
9f65e15b 7421 rx_ring = &tx_ring[1];
41c445ff
JB		 7422 rx_ring->queue_index = i;
7423 rx_ring->reg_idx = vsi->base_queue + i;
7424 rx_ring->ring_active = false;
7425 rx_ring->vsi = vsi;
7426 rx_ring->netdev = vsi->netdev;
7427 rx_ring->dev = &pf->pdev->dev;
7428 rx_ring->count = vsi->num_desc;
7429 rx_ring->size = 0;
7430 rx_ring->dcb_tc = 0;
7431 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7432 set_ring_16byte_desc_enabled(rx_ring);
7433 else
7434 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7435 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7436 }
7437
7438 return 0;
9f65e15b
AD		 7439
7440err_out:
7441 i40e_vsi_clear_rings(vsi);
7442 return -ENOMEM;
41c445ff
JB		 7443}
7444
7445/**
7446 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7447 * @pf: board private structure
7448 * @vectors: the number of MSI-X vectors to request
7449 *
7450 * Returns the number of vectors reserved, or error
7451 **/
7452static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7453{
7b37f376
AG		 7454 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7455 I40E_MIN_MSIX, vectors);
7456 if (vectors < 0) {
41c445ff 7457 dev_info(&pf->pdev->dev,
7b37f376 7458 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7459 vectors = 0;
7460 }
7461
7462 return vectors;
7463}
7464
7465/**
7466 * i40e_init_msix - Setup the MSIX capability
7467 * @pf: board private structure
7468 *
7469 * Work with the OS to set up the MSIX vectors needed.
7470 *
3b444399 7471 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7472 **/
7473static int i40e_init_msix(struct i40e_pf *pf)
7474{
41c445ff 7475 struct i40e_hw *hw = &pf->hw;
1e200e4a 7476 int vectors_left;
41c445ff 7477 int v_budget, i;
3b444399 7478 int v_actual;
41c445ff
JB		 7479
7480 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7481 return -ENODEV;
7482
7483 /* The number of vectors we'll request will be comprised of:
7484 * - Add 1 for "other" cause for Admin Queue events, etc.
7485 * - The number of LAN queue pairs
f8ff1464
ASJ		 7486 * - Queues being used for RSS.
7487 * We don't need as many as max_rss_size vectors.
7488 * use rss_size instead in the calculation since that
7489 * is governed by number of cpus in the system.
7490 * - assumes symmetric Tx/Rx pairing
41c445ff 7491 * - The number of VMDq pairs
38e00438
VD		 7492#ifdef I40E_FCOE
7493 * - The number of FCOE qps.
7494#endif
41c445ff
JB		 7495 * Once we count this up, try the request.
7496 *
7497 * If we can't get what we want, we'll simplify to nearly nothing
7498 * and try again. If that still fails, we punt.
7499 */
1e200e4a
SN		 7500 vectors_left = hw->func_caps.num_msix_vectors;
7501 v_budget = 0;
7502
7503 /* reserve one vector for miscellaneous handler */
7504 if (vectors_left) {
7505 v_budget++;
7506 vectors_left--;
7507 }
7508
7509 /* reserve vectors for the main PF traffic queues */
7510 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7511 vectors_left -= pf->num_lan_msix;
7512 v_budget += pf->num_lan_msix;
7513
7514 /* reserve one vector for sideband flow director */
7515 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7516 if (vectors_left) {
7517 v_budget++;
7518 vectors_left--;
7519 } else {
7520 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7521 }
7522 }
83840e4b 7523
38e00438 7524#ifdef I40E_FCOE
1e200e4a 7525 /* can we reserve enough for FCoE? */
38e00438 7526 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7527 if (!vectors_left)
7528 pf->num_fcoe_msix = 0;
7529 else if (vectors_left >= pf->num_fcoe_qps)
7530 pf->num_fcoe_msix = pf->num_fcoe_qps;
7531 else
7532 pf->num_fcoe_msix = 1;
38e00438 7533 v_budget += pf->num_fcoe_msix;
1e200e4a 7534 vectors_left -= pf->num_fcoe_msix;
38e00438 7535 }
1e200e4a 7536
38e00438 7537#endif
1e200e4a
SN		 7538 /* any vectors left over go for VMDq support */
7539 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7540 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7541 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7542
7543 /* if we're short on vectors for what's desired, we limit
7544 * the queues per vmdq. If this is still more than are
7545 * available, the user will need to change the number of
7546 * queues/vectors used by the PF later with the ethtool
7547 * channels command
7548 */
7549 if (vmdq_vecs < vmdq_vecs_wanted)
7550 pf->num_vmdq_qps = 1;
7551 pf->num_vmdq_msix = pf->num_vmdq_qps;
7552
7553 v_budget += vmdq_vecs;
7554 vectors_left -= vmdq_vecs;
7555 }
41c445ff
JB		 7556
7557 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7558 GFP_KERNEL);
7559 if (!pf->msix_entries)
7560 return -ENOMEM;
7561
7562 for (i = 0; i < v_budget; i++)
7563 pf->msix_entries[i].entry = i;
3b444399 7564 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7565
3b444399 7566 if (v_actual != v_budget) {
a34977ba
ASJ		 7567 /* If we have limited resources, we will start with no vectors
7568 * for the special features and then allocate vectors to some
7569 * of these features based on the policy and at the end disable
7570 * the features that did not get any vectors.
7571 */
38e00438
VD		 7572#ifdef I40E_FCOE
7573 pf->num_fcoe_qps = 0;
7574 pf->num_fcoe_msix = 0;
7575#endif
a34977ba
ASJ		 7576 pf->num_vmdq_msix = 0;
7577 }
7578
3b444399 7579 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7580 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7581 kfree(pf->msix_entries);
7582 pf->msix_entries = NULL;
7583 return -ENODEV;
7584
3b444399 7585 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7586 /* Adjust for minimal MSIX use */
41c445ff
JB		 7587 pf->num_vmdq_vsis = 0;
7588 pf->num_vmdq_qps = 0;
41c445ff
JB		 7589 pf->num_lan_qps = 1;
7590 pf->num_lan_msix = 1;
7591
3b444399
SN		 7592 } else if (v_actual != v_budget) {
7593 int vec;
7594
a34977ba 7595 /* reserve the misc vector */
3b444399 7596 vec = v_actual - 1;
a34977ba 7597
41c445ff
JB		 7598 /* Scale vector usage down */
7599 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7600 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7601 pf->num_vmdq_qps = 1;
7602 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7603
7604 /* partition out the remaining vectors */
7605 switch (vec) {
7606 case 2:
41c445ff
JB		 7607 pf->num_lan_msix = 1;
7608 break;
7609 case 3:
38e00438
VD		 7610#ifdef I40E_FCOE
7611 /* give one vector to FCoE */
7612 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7613 pf->num_lan_msix = 1;
7614 pf->num_fcoe_msix = 1;
7615 }
7616#else
41c445ff 7617 pf->num_lan_msix = 2;
38e00438 7618#endif
41c445ff
JB		 7619 break;
7620 default:
38e00438
VD		 7621#ifdef I40E_FCOE
7622 /* give one vector to FCoE */
7623 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7624 pf->num_fcoe_msix = 1;
7625 vec--;
7626 }
7627#endif
1e200e4a
SN		 7628 /* give the rest to the PF */
7629 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7630 break;
7631 }
7632 }
7633
a34977ba
ASJ		 7634 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7635 (pf->num_vmdq_msix == 0)) {
7636 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7637 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7638 }
38e00438
VD		 7639#ifdef I40E_FCOE
7640
7641 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7642 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7643 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7644 }
7645#endif
3b444399 7646 return v_actual;
41c445ff
JB		 7647}
7648
493fb300 7649/**
90e04070 7650 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7651 * @vsi: the VSI being configured
7652 * @v_idx: index of the vector in the vsi struct
7653 *
7654 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7655 **/
90e04070 7656static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7657{
7658 struct i40e_q_vector *q_vector;
7659
7660 /* allocate q_vector */
7661 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7662 if (!q_vector)
7663 return -ENOMEM;
7664
7665 q_vector->vsi = vsi;
7666 q_vector->v_idx = v_idx;
7667 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7668 if (vsi->netdev)
7669 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7670 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7671
cd0b6fa6
AD		 7672 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7673 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7674
493fb300
AD		 7675 /* tie q_vector and vsi together */
7676 vsi->q_vectors[v_idx] = q_vector;
7677
7678 return 0;
7679}
7680
41c445ff 7681/**
90e04070 7682 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7683 * @vsi: the VSI being configured
7684 *
7685 * We allocate one q_vector per queue interrupt. If allocation fails we
7686 * return -ENOMEM.
7687 **/
90e04070 7688static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7689{
7690 struct i40e_pf *pf = vsi->back;
7691 int v_idx, num_q_vectors;
493fb300 7692 int err;
41c445ff
JB		 7693
7694 /* if not MSIX, give the one vector only to the LAN VSI */
7695 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7696 num_q_vectors = vsi->num_q_vectors;
7697 else if (vsi == pf->vsi[pf->lan_vsi])
7698 num_q_vectors = 1;
7699 else
7700 return -EINVAL;
7701
41c445ff 7702 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7703 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7704 if (err)
7705 goto err_out;
41c445ff
JB		 7706 }
7707
7708 return 0;
493fb300
AD		 7709
7710err_out:
7711 while (v_idx--)
7712 i40e_free_q_vector(vsi, v_idx);
7713
7714 return err;
41c445ff
JB		 7715}
7716
7717/**
7718 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7719 * @pf: board private structure to initialize
7720 **/
c1147280 7721static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7722{
3b444399
SN		 7723 int vectors = 0;
7724 ssize_t size;
41c445ff
JB		 7725
7726 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7727 vectors = i40e_init_msix(pf);
7728 if (vectors < 0) {
60ea5f83 7729 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7730#ifdef I40E_FCOE
7731 I40E_FLAG_FCOE_ENABLED |
7732#endif
60ea5f83 7733 I40E_FLAG_RSS_ENABLED |
4d9b6043 7734 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7735 I40E_FLAG_SRIOV_ENABLED |
7736 I40E_FLAG_FD_SB_ENABLED |
7737 I40E_FLAG_FD_ATR_ENABLED |
7738 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7739
7740 /* rework the queue expectations without MSIX */
7741 i40e_determine_queue_usage(pf);
7742 }
7743 }
7744
7745 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7746 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7747 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7748 vectors = pci_enable_msi(pf->pdev);
7749 if (vectors < 0) {
7750 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7751 vectors);
41c445ff
JB		 7752 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7753 }
3b444399 7754 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7755 }
7756
958a3e3b 7757 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7758 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7759
3b444399
SN		 7760 /* set up vector assignment tracking */
7761 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7762 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7763 if (!pf->irq_pile) {
7764 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7765 return -ENOMEM;
7766 }
3b444399
SN		 7767 pf->irq_pile->num_entries = vectors;
7768 pf->irq_pile->search_hint = 0;
7769
c1147280 7770 /* track first vector for misc interrupts, ignore return */
3b444399 7771 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7772
7773 return 0;
41c445ff
JB		 7774}
7775
7776/**
7777 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7778 * @pf: board private structure
7779 *
7780 * This sets up the handler for MSIX 0, which is used to manage the
7781 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7782 * when in MSI or Legacy interrupt mode.
7783 **/
7784static int i40e_setup_misc_vector(struct i40e_pf *pf)
7785{
7786 struct i40e_hw *hw = &pf->hw;
7787 int err = 0;
7788
7789 /* Only request the irq if this is the first time through, and
7790 * not when we're rebuilding after a Reset
7791 */
7792 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7793 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7794 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7795 if (err) {
7796 dev_info(&pf->pdev->dev,
77fa28be 7797 "request_irq for %s failed: %d\n",
b294ac70 7798 pf->int_name, err);
41c445ff
JB		 7799 return -EFAULT;
7800 }
7801 }
7802
ab437b5a 7803 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7804
7805 /* associate no queues to the misc vector */
7806 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7807 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7808
7809 i40e_flush(hw);
7810
7811 i40e_irq_dynamic_enable_icr0(pf);
7812
7813 return err;
7814}
7815
7816/**
e25d00b8
ASJ		 7817 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7818 * @vsi: vsi structure
7819 * @seed: RSS hash seed
7820 **/
e69ff813
HZ		 7821static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7822 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7823{
7824 struct i40e_aqc_get_set_rss_key_data rss_key;
7825 struct i40e_pf *pf = vsi->back;
7826 struct i40e_hw *hw = &pf->hw;
7827 bool pf_lut = false;
7828 u8 *rss_lut;
7829 int ret, i;
7830
7831 memset(&rss_key, 0, sizeof(rss_key));
7832 memcpy(&rss_key, seed, sizeof(rss_key));
7833
7834 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7835 if (!rss_lut)
7836 return -ENOMEM;
7837
7838 /* Populate the LUT with max no. of queues in round robin fashion */
7839 for (i = 0; i < vsi->rss_table_size; i++)
7840 rss_lut[i] = i % vsi->rss_size;
7841
7842 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7843 if (ret) {
7844 dev_info(&pf->pdev->dev,
7845 "Cannot set RSS key, err %s aq_err %s\n",
7846 i40e_stat_str(&pf->hw, ret),
7847 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7848 goto config_rss_aq_out;
e25d00b8
ASJ		 7849 }
7850
7851 if (vsi->type == I40E_VSI_MAIN)
7852 pf_lut = true;
7853
7854 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7855 vsi->rss_table_size);
7856 if (ret)
7857 dev_info(&pf->pdev->dev,
7858 "Cannot set RSS lut, err %s aq_err %s\n",
7859 i40e_stat_str(&pf->hw, ret),
7860 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7861
126b63d9
AS		 7862config_rss_aq_out:
7863 kfree(rss_lut);
e25d00b8
ASJ		 7864 return ret;
7865}
7866
7867/**
7868 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7869 * @vsi: VSI structure
7870 **/
7871static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7872{
7873 u8 seed[I40E_HKEY_ARRAY_SIZE];
7874 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7875 u8 *lut;
7876 int ret;
7877
7878 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7879 return 0;
7880
7881 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7882 if (!lut)
7883 return -ENOMEM;
e25d00b8 7884
e69ff813 7885 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7886 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7887 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7888 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7889 kfree(lut);
e25d00b8 7890
e69ff813 7891 return ret;
e25d00b8
ASJ		 7892}
7893
7894/**
043dd650 7895 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 7896 * @vsi: Pointer to vsi structure
e25d00b8 7897 * @seed: RSS hash seed
e69ff813
HZ		 7898 * @lut: Lookup table
7899 * @lut_size: Lookup table size
7900 *
7901 * Returns 0 on success, negative on failure
41c445ff 7902 **/
e69ff813
HZ		 7903static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
7904 const u8 *lut, u16 lut_size)
41c445ff 7905{
e69ff813 7906 struct i40e_pf *pf = vsi->back;
4617e8c0 7907 struct i40e_hw *hw = &pf->hw;
e69ff813 7908 u8 i;
41c445ff 7909
e25d00b8 7910 /* Fill out hash function seed */
e69ff813
HZ		 7911 if (seed) {
7912 u32 *seed_dw = (u32 *)seed;
7913
7914 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7915 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7916 }
7917
7918 if (lut) {
7919 u32 *lut_dw = (u32 *)lut;
7920
7921 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7922 return -EINVAL;
7923
7924 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7925 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
e25d00b8
ASJ		 7926 }
7927 i40e_flush(hw);
7928
7929 return 0;
7930}
7931
043dd650
HZ		 7932/**
7933 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
7934 * @vsi: Pointer to VSI structure
7935 * @seed: Buffer to store the keys
7936 * @lut: Buffer to store the lookup table entries
7937 * @lut_size: Size of buffer to store the lookup table entries
7938 *
7939 * Returns 0 on success, negative on failure
7940 */
7941static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
7942 u8 *lut, u16 lut_size)
7943{
7944 struct i40e_pf *pf = vsi->back;
7945 struct i40e_hw *hw = &pf->hw;
7946 u16 i;
7947
7948 if (seed) {
7949 u32 *seed_dw = (u32 *)seed;
7950
7951 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7952 seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
7953 }
7954 if (lut) {
7955 u32 *lut_dw = (u32 *)lut;
7956
7957 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7958 return -EINVAL;
7959 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7960 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
7961 }
7962
7963 return 0;
7964}
7965
7966/**
7967 * i40e_config_rss - Configure RSS keys and lut
7968 * @vsi: Pointer to VSI structure
7969 * @seed: RSS hash seed
7970 * @lut: Lookup table
7971 * @lut_size: Lookup table size
7972 *
7973 * Returns 0 on success, negative on failure
7974 */
7975int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
7976{
7977 struct i40e_pf *pf = vsi->back;
7978
7979 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7980 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
7981 else
7982 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
7983}
7984
7985/**
7986 * i40e_get_rss - Get RSS keys and lut
7987 * @vsi: Pointer to VSI structure
7988 * @seed: Buffer to store the keys
7989 * @lut: Buffer to store the lookup table entries
7990 * lut_size: Size of buffer to store the lookup table entries
7991 *
7992 * Returns 0 on success, negative on failure
7993 */
7994int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
7995{
7996 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
7997}
7998
e69ff813
HZ		 7999/**
8000 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8001 * @pf: Pointer to board private structure
8002 * @lut: Lookup table
8003 * @rss_table_size: Lookup table size
8004 * @rss_size: Range of queue number for hashing
8005 */
8006static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8007 u16 rss_table_size, u16 rss_size)
8008{
8009 u16 i;
8010
8011 for (i = 0; i < rss_table_size; i++)
8012 lut[i] = i % rss_size;
8013}
8014
e25d00b8 8015/**
043dd650 8016 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8017 * @pf: board private structure
8018 **/
043dd650 8019static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8020{
8021 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8022 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8023 u8 *lut;
e25d00b8
ASJ		 8024 struct i40e_hw *hw = &pf->hw;
8025 u32 reg_val;
8026 u64 hena;
e69ff813 8027 int ret;
e25d00b8 8028
41c445ff
JB		 8029 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
8030 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
8031 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8032 hena |= i40e_pf_get_default_rss_hena(pf);
8033
41c445ff
JB		 8034 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
8035 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
8036
e25d00b8 8037 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 8038 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8039 reg_val = (pf->rss_table_size == 512) ?
8040 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8041 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 8042 wr32(hw, I40E_PFQF_CTL_0, reg_val);
8043
28c5869f
HZ		 8044 /* Determine the RSS size of the VSI */
8045 if (!vsi->rss_size)
acd65448
HZ		 8046 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8047 vsi->num_queue_pairs);
28c5869f 8048
e69ff813
HZ		 8049 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8050 if (!lut)
8051 return -ENOMEM;
8052
28c5869f
HZ		 8053 /* Use user configured lut if there is one, otherwise use default */
8054 if (vsi->rss_lut_user)
8055 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8056 else
8057 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8058
28c5869f
HZ		 8059 /* Use user configured hash key if there is one, otherwise
8060 * use default.
8061 */
8062 if (vsi->rss_hkey_user)
8063 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8064 else
8065 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8066 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8067 kfree(lut);
8068
8069 return ret;
41c445ff
JB		 8070}
8071
f8ff1464
ASJ		 8072/**
8073 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8074 * @pf: board private structure
8075 * @queue_count: the requested queue count for rss.
8076 *
8077 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8078 * count which may be different from the requested queue count.
8079 **/
8080int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8081{
9a3bd2f1
ASJ		 8082 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8083 int new_rss_size;
8084
f8ff1464
ASJ		 8085 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8086 return 0;
8087
9a3bd2f1 8088 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8089
9a3bd2f1
ASJ		 8090 if (queue_count != vsi->num_queue_pairs) {
8091 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8092 i40e_prep_for_reset(pf);
8093
acd65448 8094 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8095
8096 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8097
8098 /* Discard the user configured hash keys and lut, if less
8099 * queues are enabled.
8100 */
8101 if (queue_count < vsi->rss_size) {
8102 i40e_clear_rss_config_user(vsi);
8103 dev_dbg(&pf->pdev->dev,
8104 "discard user configured hash keys and lut\n");
8105 }
8106
8107 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8108 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8109 vsi->num_queue_pairs);
28c5869f 8110
043dd650 8111 i40e_pf_config_rss(pf);
f8ff1464 8112 }
acd65448
HZ		 8113 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->alloc_rss_size);
8114 return pf->alloc_rss_size;
f8ff1464
ASJ		 8115}
8116
f4492db1
GR		 8117/**
8118 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8119 * @pf: board private structure
8120 **/
8121i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8122{
8123 i40e_status status;
8124 bool min_valid, max_valid;
8125 u32 max_bw, min_bw;
8126
8127 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8128 &min_valid, &max_valid);
8129
8130 if (!status) {
8131 if (min_valid)
8132 pf->npar_min_bw = min_bw;
8133 if (max_valid)
8134 pf->npar_max_bw = max_bw;
8135 }
8136
8137 return status;
8138}
8139
8140/**
8141 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8142 * @pf: board private structure
8143 **/
8144i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8145{
8146 struct i40e_aqc_configure_partition_bw_data bw_data;
8147 i40e_status status;
8148
b40c82e6 8149 /* Set the valid bit for this PF */
41a1d04b 8150 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8151 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8152 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8153
8154 /* Set the new bandwidths */
8155 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8156
8157 return status;
8158}
8159
8160/**
8161 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8162 * @pf: board private structure
8163 **/
8164i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8165{
8166 /* Commit temporary BW setting to permanent NVM image */
8167 enum i40e_admin_queue_err last_aq_status;
8168 i40e_status ret;
8169 u16 nvm_word;
8170
8171 if (pf->hw.partition_id != 1) {
8172 dev_info(&pf->pdev->dev,
8173 "Commit BW only works on partition 1! This is partition %d",
8174 pf->hw.partition_id);
8175 ret = I40E_NOT_SUPPORTED;
8176 goto bw_commit_out;
8177 }
8178
8179 /* Acquire NVM for read access */
8180 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8181 last_aq_status = pf->hw.aq.asq_last_status;
8182 if (ret) {
8183 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8184 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8185 i40e_stat_str(&pf->hw, ret),
8186 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8187 goto bw_commit_out;
8188 }
8189
8190 /* Read word 0x10 of NVM - SW compatibility word 1 */
8191 ret = i40e_aq_read_nvm(&pf->hw,
8192 I40E_SR_NVM_CONTROL_WORD,
8193 0x10, sizeof(nvm_word), &nvm_word,
8194 false, NULL);
8195 /* Save off last admin queue command status before releasing
8196 * the NVM
8197 */
8198 last_aq_status = pf->hw.aq.asq_last_status;
8199 i40e_release_nvm(&pf->hw);
8200 if (ret) {
f1c7e72e
SN		 8201 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8202 i40e_stat_str(&pf->hw, ret),
8203 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8204 goto bw_commit_out;
8205 }
8206
8207 /* Wait a bit for NVM release to complete */
8208 msleep(50);
8209
8210 /* Acquire NVM for write access */
8211 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8212 last_aq_status = pf->hw.aq.asq_last_status;
8213 if (ret) {
8214 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8215 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8216 i40e_stat_str(&pf->hw, ret),
8217 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8218 goto bw_commit_out;
8219 }
8220 /* Write it back out unchanged to initiate update NVM,
8221 * which will force a write of the shadow (alt) RAM to
8222 * the NVM - thus storing the bandwidth values permanently.
8223 */
8224 ret = i40e_aq_update_nvm(&pf->hw,
8225 I40E_SR_NVM_CONTROL_WORD,
8226 0x10, sizeof(nvm_word),
8227 &nvm_word, true, NULL);
8228 /* Save off last admin queue command status before releasing
8229 * the NVM
8230 */
8231 last_aq_status = pf->hw.aq.asq_last_status;
8232 i40e_release_nvm(&pf->hw);
8233 if (ret)
8234 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8235 "BW settings NOT SAVED, err %s aq_err %s\n",
8236 i40e_stat_str(&pf->hw, ret),
8237 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8238bw_commit_out:
8239
8240 return ret;
8241}
8242
41c445ff
JB		 8243/**
8244 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8245 * @pf: board private structure to initialize
8246 *
8247 * i40e_sw_init initializes the Adapter private data structure.
8248 * Fields are initialized based on PCI device information and
8249 * OS network device settings (MTU size).
8250 **/
8251static int i40e_sw_init(struct i40e_pf *pf)
8252{
8253 int err = 0;
8254 int size;
8255
8256 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8257 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 8258 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 8259 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8260 if (I40E_DEBUG_USER & debug)
8261 pf->hw.debug_mask = debug;
8262 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8263 I40E_DEFAULT_MSG_ENABLE);
8264 }
8265
8266 /* Set default capability flags */
8267 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8268 I40E_FLAG_MSI_ENABLED |
9ac77266 8269 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 8270 I40E_FLAG_MSIX_ENABLED;
8271
8272 if (iommu_present(&pci_bus_type))
8273 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8274 else
8275 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8276
ca99eb99
MW		 8277 /* Set default ITR */
8278 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8279 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8280
7134f9ce
JB		 8281 /* Depending on PF configurations, it is possible that the RSS
8282 * maximum might end up larger than the available queues
8283 */
41a1d04b 8284 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8285 pf->alloc_rss_size = 1;
5db4cb59 8286 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8287 pf->rss_size_max = min_t(int, pf->rss_size_max,
8288 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8289 if (pf->hw.func_caps.rss) {
8290 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8291 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8292 num_online_cpus());
41c445ff
JB		 8293 }
8294
2050bc65 8295 /* MFP mode enabled */
c78b953e 8296 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8297 pf->flags |= I40E_FLAG_MFP_ENABLED;
8298 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8299 if (i40e_get_npar_bw_setting(pf))
8300 dev_warn(&pf->pdev->dev,
8301 "Could not get NPAR bw settings\n");
8302 else
8303 dev_info(&pf->pdev->dev,
8304 "Min BW = %8.8x, Max BW = %8.8x\n",
8305 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8306 }
8307
cbf61325
ASJ		 8308 /* FW/NVM is not yet fixed in this regard */
8309 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8310 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8311 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8312 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8313 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8314 pf->hw.num_partitions > 1)
cbf61325 8315 dev_info(&pf->pdev->dev,
0b67584f 8316 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8317 else
8318 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8319 pf->fdir_pf_filter_count =
8320 pf->hw.func_caps.fd_filters_guaranteed;
8321 pf->hw.fdir_shared_filter_count =
8322 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8323 }
8324
8325 if (pf->hw.func_caps.vmdq) {
41c445ff 8326 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8327 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8328 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8329 }
8330
38e00438 8331#ifdef I40E_FCOE
21364bcf 8332 i40e_init_pf_fcoe(pf);
38e00438
VD		 8333
8334#endif /* I40E_FCOE */
41c445ff 8335#ifdef CONFIG_PCI_IOV
ba252f13 8336 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8337 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8338 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8339 pf->num_req_vfs = min_t(int,
8340 pf->hw.func_caps.num_vfs,
8341 I40E_MAX_VF_COUNT);
8342 }
8343#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8344 if (pf->hw.mac.type == I40E_MAC_X722) {
8345 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8346 I40E_FLAG_128_QP_RSS_CAPABLE |
8347 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8348 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8349 I40E_FLAG_WB_ON_ITR_CAPABLE |
8350 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
8351 }
41c445ff
JB		 8352 pf->eeprom_version = 0xDEAD;
8353 pf->lan_veb = I40E_NO_VEB;
8354 pf->lan_vsi = I40E_NO_VSI;
8355
d1a8d275
ASJ		 8356 /* By default FW has this off for performance reasons */
8357 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8358
41c445ff
JB		 8359 /* set up queue assignment tracking */
8360 size = sizeof(struct i40e_lump_tracking)
8361 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8362 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8363 if (!pf->qp_pile) {
8364 err = -ENOMEM;
8365 goto sw_init_done;
8366 }
8367 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8368 pf->qp_pile->search_hint = 0;
8369
327fe04b
ASJ		 8370 pf->tx_timeout_recovery_level = 1;
8371
41c445ff
JB		 8372 mutex_init(&pf->switch_mutex);
8373
c668a12c
GR		 8374 /* If NPAR is enabled nudge the Tx scheduler */
8375 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8376 i40e_set_npar_bw_setting(pf);
8377
41c445ff
JB		 8378sw_init_done:
8379 return err;
8380}
8381
7c3c288b
ASJ		 8382/**
8383 * i40e_set_ntuple - set the ntuple feature flag and take action
8384 * @pf: board private structure to initialize
8385 * @features: the feature set that the stack is suggesting
8386 *
8387 * returns a bool to indicate if reset needs to happen
8388 **/
8389bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8390{
8391 bool need_reset = false;
8392
8393 /* Check if Flow Director n-tuple support was enabled or disabled. If
8394 * the state changed, we need to reset.
8395 */
8396 if (features & NETIF_F_NTUPLE) {
8397 /* Enable filters and mark for reset */
8398 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8399 need_reset = true;
8400 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8401 } else {
8402 /* turn off filters, mark for reset and clear SW filter list */
8403 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8404 need_reset = true;
8405 i40e_fdir_filter_exit(pf);
8406 }
8407 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8408 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8409 /* reset fd counters */
8410 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8411 pf->fdir_pf_active_filters = 0;
8412 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8413 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8414 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8415 /* if ATR was auto disabled it can be re-enabled. */
8416 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8417 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8418 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8419 }
8420 return need_reset;
8421}
8422
41c445ff
JB		 8423/**
8424 * i40e_set_features - set the netdev feature flags
8425 * @netdev: ptr to the netdev being adjusted
8426 * @features: the feature set that the stack is suggesting
8427 **/
8428static int i40e_set_features(struct net_device *netdev,
8429 netdev_features_t features)
8430{
8431 struct i40e_netdev_priv *np = netdev_priv(netdev);
8432 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8433 struct i40e_pf *pf = vsi->back;
8434 bool need_reset;
41c445ff
JB		 8435
8436 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8437 i40e_vlan_stripping_enable(vsi);
8438 else
8439 i40e_vlan_stripping_disable(vsi);
8440
7c3c288b
ASJ		 8441 need_reset = i40e_set_ntuple(pf, features);
8442
8443 if (need_reset)
41a1d04b 8444 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8445
41c445ff
JB		 8446 return 0;
8447}
8448
a1c9a9d9
JK		 8449#ifdef CONFIG_I40E_VXLAN
8450/**
8451 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8452 * @pf: board private structure
8453 * @port: The UDP port to look up
8454 *
8455 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8456 **/
8457static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8458{
8459 u8 i;
8460
8461 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8462 if (pf->vxlan_ports[i] == port)
8463 return i;
8464 }
8465
8466 return i;
8467}
8468
8469/**
8470 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8471 * @netdev: This physical port's netdev
8472 * @sa_family: Socket Family that VXLAN is notifying us about
8473 * @port: New UDP port number that VXLAN started listening to
8474 **/
8475static void i40e_add_vxlan_port(struct net_device *netdev,
8476 sa_family_t sa_family, __be16 port)
8477{
8478 struct i40e_netdev_priv *np = netdev_priv(netdev);
8479 struct i40e_vsi *vsi = np->vsi;
8480 struct i40e_pf *pf = vsi->back;
8481 u8 next_idx;
8482 u8 idx;
8483
8484 if (sa_family == AF_INET6)
8485 return;
8486
8487 idx = i40e_get_vxlan_port_idx(pf, port);
8488
8489 /* Check if port already exists */
8490 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8491 netdev_info(netdev, "vxlan port %d already offloaded\n",
8492 ntohs(port));
a1c9a9d9
JK		 8493 return;
8494 }
8495
8496 /* Now check if there is space to add the new port */
8497 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8498
8499 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8500 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8501 ntohs(port));
8502 return;
8503 }
8504
8505 /* New port: add it and mark its index in the bitmap */
8506 pf->vxlan_ports[next_idx] = port;
41a1d04b 8507 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8508 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8509}
8510
8511/**
8512 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8513 * @netdev: This physical port's netdev
8514 * @sa_family: Socket Family that VXLAN is notifying us about
8515 * @port: UDP port number that VXLAN stopped listening to
8516 **/
8517static void i40e_del_vxlan_port(struct net_device *netdev,
8518 sa_family_t sa_family, __be16 port)
8519{
8520 struct i40e_netdev_priv *np = netdev_priv(netdev);
8521 struct i40e_vsi *vsi = np->vsi;
8522 struct i40e_pf *pf = vsi->back;
8523 u8 idx;
8524
8525 if (sa_family == AF_INET6)
8526 return;
8527
8528 idx = i40e_get_vxlan_port_idx(pf, port);
8529
8530 /* Check if port already exists */
8531 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8532 /* if port exists, set it to 0 (mark for deletion)
8533 * and make it pending
8534 */
8535 pf->vxlan_ports[idx] = 0;
41a1d04b 8536 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8537 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8538 } else {
c22c06c8 8539 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8540 ntohs(port));
8541 }
8542}
8543
8544#endif
1f224ad2 8545static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8546 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8547{
8548 struct i40e_netdev_priv *np = netdev_priv(netdev);
8549 struct i40e_pf *pf = np->vsi->back;
8550 struct i40e_hw *hw = &pf->hw;
8551
8552 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8553 return -EOPNOTSUPP;
8554
8555 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8556 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8557
8558 return 0;
8559}
8560
2f90ade6
JB		 8561/**
8562 * i40e_ndo_fdb_add - add an entry to the hardware database
8563 * @ndm: the input from the stack
8564 * @tb: pointer to array of nladdr (unused)
8565 * @dev: the net device pointer
8566 * @addr: the MAC address entry being added
8567 * @flags: instructions from stack about fdb operation
8568 */
4ba0dea5
GR		 8569static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8570 struct net_device *dev,
f6f6424b 8571 const unsigned char *addr, u16 vid,
4ba0dea5 8572 u16 flags)
4ba0dea5
GR		 8573{
8574 struct i40e_netdev_priv *np = netdev_priv(dev);
8575 struct i40e_pf *pf = np->vsi->back;
8576 int err = 0;
8577
8578 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8579 return -EOPNOTSUPP;
8580
65891fea
OG		 8581 if (vid) {
8582 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8583 return -EINVAL;
8584 }
8585
4ba0dea5
GR		 8586 /* Hardware does not support aging addresses so if a
8587 * ndm_state is given only allow permanent addresses
8588 */
8589 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8590 netdev_info(dev, "FDB only supports static addresses\n");
8591 return -EINVAL;
8592 }
8593
8594 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8595 err = dev_uc_add_excl(dev, addr);
8596 else if (is_multicast_ether_addr(addr))
8597 err = dev_mc_add_excl(dev, addr);
8598 else
8599 err = -EINVAL;
8600
8601 /* Only return duplicate errors if NLM_F_EXCL is set */
8602 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8603 err = 0;
8604
8605 return err;
8606}
8607
51616018
NP		 8608/**
8609 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8610 * @dev: the netdev being configured
8611 * @nlh: RTNL message
8612 *
8613 * Inserts a new hardware bridge if not already created and
8614 * enables the bridging mode requested (VEB or VEPA). If the
8615 * hardware bridge has already been inserted and the request
8616 * is to change the mode then that requires a PF reset to
8617 * allow rebuild of the components with required hardware
8618 * bridge mode enabled.
8619 **/
8620static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8621 struct nlmsghdr *nlh,
8622 u16 flags)
51616018
NP		 8623{
8624 struct i40e_netdev_priv *np = netdev_priv(dev);
8625 struct i40e_vsi *vsi = np->vsi;
8626 struct i40e_pf *pf = vsi->back;
8627 struct i40e_veb *veb = NULL;
8628 struct nlattr *attr, *br_spec;
8629 int i, rem;
8630
8631 /* Only for PF VSI for now */
8632 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8633 return -EOPNOTSUPP;
8634
8635 /* Find the HW bridge for PF VSI */
8636 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8637 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8638 veb = pf->veb[i];
8639 }
8640
8641 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8642
8643 nla_for_each_nested(attr, br_spec, rem) {
8644 __u16 mode;
8645
8646 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8647 continue;
8648
8649 mode = nla_get_u16(attr);
8650 if ((mode != BRIDGE_MODE_VEPA) &&
8651 (mode != BRIDGE_MODE_VEB))
8652 return -EINVAL;
8653
8654 /* Insert a new HW bridge */
8655 if (!veb) {
8656 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8657 vsi->tc_config.enabled_tc);
8658 if (veb) {
8659 veb->bridge_mode = mode;
8660 i40e_config_bridge_mode(veb);
8661 } else {
8662 /* No Bridge HW offload available */
8663 return -ENOENT;
8664 }
8665 break;
8666 } else if (mode != veb->bridge_mode) {
8667 /* Existing HW bridge but different mode needs reset */
8668 veb->bridge_mode = mode;
fc60861e
ASJ		 8669 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8670 if (mode == BRIDGE_MODE_VEB)
8671 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8672 else
8673 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8674 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8675 break;
8676 }
8677 }
8678
8679 return 0;
8680}
8681
8682/**
8683 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8684 * @skb: skb buff
8685 * @pid: process id
8686 * @seq: RTNL message seq #
8687 * @dev: the netdev being configured
8688 * @filter_mask: unused
d4b2f9fe 8689 * @nlflags: netlink flags passed in
51616018
NP		 8690 *
8691 * Return the mode in which the hardware bridge is operating in
8692 * i.e VEB or VEPA.
8693 **/
51616018
NP		 8694static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8695 struct net_device *dev,
9f4ffc44
CW		 8696 u32 __always_unused filter_mask,
8697 int nlflags)
51616018
NP		 8698{
8699 struct i40e_netdev_priv *np = netdev_priv(dev);
8700 struct i40e_vsi *vsi = np->vsi;
8701 struct i40e_pf *pf = vsi->back;
8702 struct i40e_veb *veb = NULL;
8703 int i;
8704
8705 /* Only for PF VSI for now */
8706 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8707 return -EOPNOTSUPP;
8708
8709 /* Find the HW bridge for the PF VSI */
8710 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8711 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8712 veb = pf->veb[i];
8713 }
8714
8715 if (!veb)
8716 return 0;
8717
46c264da 8718 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8719 nlflags, 0, 0, filter_mask, NULL);
51616018 8720}
51616018 8721
f44a75e2
JS		 8722#define I40E_MAX_TUNNEL_HDR_LEN 80
8723/**
8724 * i40e_features_check - Validate encapsulated packet conforms to limits
8725 * @skb: skb buff
2bc11c63 8726 * @dev: This physical port's netdev
f44a75e2
JS		 8727 * @features: Offload features that the stack believes apply
8728 **/
8729static netdev_features_t i40e_features_check(struct sk_buff *skb,
8730 struct net_device *dev,
8731 netdev_features_t features)
8732{
8733 if (skb->encapsulation &&
8734 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8735 I40E_MAX_TUNNEL_HDR_LEN))
8736 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8737
8738 return features;
8739}
8740
37a2973a 8741static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8742 .ndo_open = i40e_open,
8743 .ndo_stop = i40e_close,
8744 .ndo_start_xmit = i40e_lan_xmit_frame,
8745 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8746 .ndo_set_rx_mode = i40e_set_rx_mode,
8747 .ndo_validate_addr = eth_validate_addr,
8748 .ndo_set_mac_address = i40e_set_mac,
8749 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8750 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8751 .ndo_tx_timeout = i40e_tx_timeout,
8752 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8753 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8754#ifdef CONFIG_NET_POLL_CONTROLLER
8755 .ndo_poll_controller = i40e_netpoll,
8756#endif
8757 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8758#ifdef I40E_FCOE
8759 .ndo_fcoe_enable = i40e_fcoe_enable,
8760 .ndo_fcoe_disable = i40e_fcoe_disable,
8761#endif
41c445ff
JB		 8762 .ndo_set_features = i40e_set_features,
8763 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8764 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8765 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8766 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8767 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8768 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8769#ifdef CONFIG_I40E_VXLAN
8770 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8771 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8772#endif
1f224ad2 8773 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8774 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8775 .ndo_features_check = i40e_features_check,
51616018
NP		 8776 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8777 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8778};
8779
8780/**
8781 * i40e_config_netdev - Setup the netdev flags
8782 * @vsi: the VSI being configured
8783 *
8784 * Returns 0 on success, negative value on failure
8785 **/
8786static int i40e_config_netdev(struct i40e_vsi *vsi)
8787{
1a10370a 8788 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8789 struct i40e_pf *pf = vsi->back;
8790 struct i40e_hw *hw = &pf->hw;
8791 struct i40e_netdev_priv *np;
8792 struct net_device *netdev;
8793 u8 mac_addr[ETH_ALEN];
8794 int etherdev_size;
8795
8796 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8797 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8798 if (!netdev)
8799 return -ENOMEM;
8800
8801 vsi->netdev = netdev;
8802 np = netdev_priv(netdev);
8803 np->vsi = vsi;
8804
d70e941b 8805 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8806 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8807 NETIF_F_GSO_GRE |
d70e941b 8808 NETIF_F_TSO;
41c445ff
JB		 8809
8810 netdev->features = NETIF_F_SG |
8811 NETIF_F_IP_CSUM |
8812 NETIF_F_SCTP_CSUM |
8813 NETIF_F_HIGHDMA |
8814 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8815 NETIF_F_GSO_GRE |
41c445ff
JB		 8816 NETIF_F_HW_VLAN_CTAG_TX |
8817 NETIF_F_HW_VLAN_CTAG_RX |
8818 NETIF_F_HW_VLAN_CTAG_FILTER |
8819 NETIF_F_IPV6_CSUM |
8820 NETIF_F_TSO |
059dab69 8821 NETIF_F_TSO_ECN |
41c445ff
JB		 8822 NETIF_F_TSO6 |
8823 NETIF_F_RXCSUM |
8824 NETIF_F_RXHASH |
8825 0;
8826
2e86a0b6
ASJ		 8827 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8828 netdev->features |= NETIF_F_NTUPLE;
8829
41c445ff
JB		 8830 /* copy netdev features into list of user selectable features */
8831 netdev->hw_features |= netdev->features;
8832
8833 if (vsi->type == I40E_VSI_MAIN) {
8834 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8835 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8836 /* The following steps are necessary to prevent reception
8837 * of tagged packets - some older NVM configurations load a
8838 * default a MAC-VLAN filter that accepts any tagged packet
8839 * which must be replaced by a normal filter.
8c27d42e 8840 */
21659035
KP		 8841 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
8842 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 8843 i40e_add_filter(vsi, mac_addr,
8844 I40E_VLAN_ANY, false, true);
21659035
KP		 8845 spin_unlock_bh(&vsi->mac_filter_list_lock);
8846 }
41c445ff
JB		 8847 } else {
8848 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8849 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8850 pf->vsi[pf->lan_vsi]->netdev->name);
8851 random_ether_addr(mac_addr);
21659035
KP		 8852
8853 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 8854 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 8855 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8856 }
21659035
KP		 8857
8858 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 8859 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 8860 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8861
9a173901
GR		 8862 ether_addr_copy(netdev->dev_addr, mac_addr);
8863 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8864 /* vlan gets same features (except vlan offload)
8865 * after any tweaks for specific VSI types
8866 */
8867 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8868 NETIF_F_HW_VLAN_CTAG_RX |
8869 NETIF_F_HW_VLAN_CTAG_FILTER);
8870 netdev->priv_flags |= IFF_UNICAST_FLT;
8871 netdev->priv_flags |= IFF_SUPP_NOFCS;
8872 /* Setup netdev TC information */
8873 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8874
8875 netdev->netdev_ops = &i40e_netdev_ops;
8876 netdev->watchdog_timeo = 5 * HZ;
8877 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8878#ifdef I40E_FCOE
8879 i40e_fcoe_config_netdev(netdev, vsi);
8880#endif
41c445ff
JB		 8881
8882 return 0;
8883}
8884
8885/**
8886 * i40e_vsi_delete - Delete a VSI from the switch
8887 * @vsi: the VSI being removed
8888 *
8889 * Returns 0 on success, negative value on failure
8890 **/
8891static void i40e_vsi_delete(struct i40e_vsi *vsi)
8892{
8893 /* remove default VSI is not allowed */
8894 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8895 return;
8896
41c445ff 8897 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8898}
8899
51616018
NP		 8900/**
8901 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8902 * @vsi: the VSI being queried
8903 *
8904 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8905 **/
8906int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8907{
8908 struct i40e_veb *veb;
8909 struct i40e_pf *pf = vsi->back;
8910
8911 /* Uplink is not a bridge so default to VEB */
8912 if (vsi->veb_idx == I40E_NO_VEB)
8913 return 1;
8914
8915 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 8916 if (!veb) {
8917 dev_info(&pf->pdev->dev,
8918 "There is no veb associated with the bridge\n");
8919 return -ENOENT;
8920 }
8921
51616018 8922 /* Uplink is a bridge in VEPA mode */
09603eaa 8923 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 8924 return 0;
09603eaa
AA		 8925 } else {
8926 /* Uplink is a bridge in VEB mode */
8927 return 1;
8928 }
51616018 8929
09603eaa
AA		 8930 /* VEPA is now default bridge, so return 0 */
8931 return 0;
51616018
NP		 8932}
8933
41c445ff
JB		 8934/**
8935 * i40e_add_vsi - Add a VSI to the switch
8936 * @vsi: the VSI being configured
8937 *
8938 * This initializes a VSI context depending on the VSI type to be added and
8939 * passes it down to the add_vsi aq command.
8940 **/
8941static int i40e_add_vsi(struct i40e_vsi *vsi)
8942{
8943 int ret = -ENODEV;
21659035
KP		 8944 u8 laa_macaddr[ETH_ALEN];
8945 bool found_laa_mac_filter = false;
41c445ff
JB		 8946 struct i40e_pf *pf = vsi->back;
8947 struct i40e_hw *hw = &pf->hw;
8948 struct i40e_vsi_context ctxt;
21659035
KP		 8949 struct i40e_mac_filter *f, *ftmp;
8950
41c445ff
JB		 8951 u8 enabled_tc = 0x1; /* TC0 enabled */
8952 int f_count = 0;
8953
8954 memset(&ctxt, 0, sizeof(ctxt));
8955 switch (vsi->type) {
8956 case I40E_VSI_MAIN:
8957 /* The PF's main VSI is already setup as part of the
8958 * device initialization, so we'll not bother with
8959 * the add_vsi call, but we will retrieve the current
8960 * VSI context.
8961 */
8962 ctxt.seid = pf->main_vsi_seid;
8963 ctxt.pf_num = pf->hw.pf_id;
8964 ctxt.vf_num = 0;
8965 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8966 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8967 if (ret) {
8968 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8969 "couldn't get PF vsi config, err %s aq_err %s\n",
8970 i40e_stat_str(&pf->hw, ret),
8971 i40e_aq_str(&pf->hw,
8972 pf->hw.aq.asq_last_status));
41c445ff
JB		 8973 return -ENOENT;
8974 }
1a2f6248 8975 vsi->info = ctxt.info;
41c445ff
JB		 8976 vsi->info.valid_sections = 0;
8977
8978 vsi->seid = ctxt.seid;
8979 vsi->id = ctxt.vsi_number;
8980
8981 enabled_tc = i40e_pf_get_tc_map(pf);
8982
8983 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8984 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8985 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8986 memset(&ctxt, 0, sizeof(ctxt));
8987 ctxt.seid = pf->main_vsi_seid;
8988 ctxt.pf_num = pf->hw.pf_id;
8989 ctxt.vf_num = 0;
8990 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8991 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8992 if (ret) {
8993 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8994 "update vsi failed, err %s aq_err %s\n",
8995 i40e_stat_str(&pf->hw, ret),
8996 i40e_aq_str(&pf->hw,
8997 pf->hw.aq.asq_last_status));
41c445ff
JB		 8998 ret = -ENOENT;
8999 goto err;
9000 }
9001 /* update the local VSI info queue map */
9002 i40e_vsi_update_queue_map(vsi, &ctxt);
9003 vsi->info.valid_sections = 0;
9004 } else {
9005 /* Default/Main VSI is only enabled for TC0
9006 * reconfigure it to enable all TCs that are
9007 * available on the port in SFP mode.
63d7e5a4
NP		 9008 * For MFP case the iSCSI PF would use this
9009 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9010 */
9011 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9012 if (ret) {
9013 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9014 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9015 enabled_tc,
9016 i40e_stat_str(&pf->hw, ret),
9017 i40e_aq_str(&pf->hw,
9018 pf->hw.aq.asq_last_status));
41c445ff
JB		 9019 ret = -ENOENT;
9020 }
9021 }
9022 break;
9023
9024 case I40E_VSI_FDIR:
cbf61325
ASJ		 9025 ctxt.pf_num = hw->pf_id;
9026 ctxt.vf_num = 0;
9027 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9028 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9029 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9030 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9031 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9032 ctxt.info.valid_sections |=
fc60861e 9033 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9034 ctxt.info.switch_id =
fc60861e 9035 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9036 }
41c445ff 9037 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9038 break;
9039
9040 case I40E_VSI_VMDQ2:
9041 ctxt.pf_num = hw->pf_id;
9042 ctxt.vf_num = 0;
9043 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9044 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9045 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9046
41c445ff
JB		 9047 /* This VSI is connected to VEB so the switch_id
9048 * should be set to zero by default.
9049 */
51616018
NP		 9050 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9051 ctxt.info.valid_sections |=
9052 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9053 ctxt.info.switch_id =
9054 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9055 }
41c445ff
JB		 9056
9057 /* Setup the VSI tx/rx queue map for TC0 only for now */
9058 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9059 break;
9060
9061 case I40E_VSI_SRIOV:
9062 ctxt.pf_num = hw->pf_id;
9063 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9064 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9065 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9066 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9067
41c445ff
JB		 9068 /* This VSI is connected to VEB so the switch_id
9069 * should be set to zero by default.
9070 */
51616018
NP		 9071 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9072 ctxt.info.valid_sections |=
9073 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9074 ctxt.info.switch_id =
9075 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9076 }
41c445ff
JB		 9077
9078 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9079 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9080 if (pf->vf[vsi->vf_id].spoofchk) {
9081 ctxt.info.valid_sections |=
9082 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9083 ctxt.info.sec_flags |=
9084 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9085 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9086 }
41c445ff
JB		 9087 /* Setup the VSI tx/rx queue map for TC0 only for now */
9088 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9089 break;
9090
38e00438
VD		 9091#ifdef I40E_FCOE
9092 case I40E_VSI_FCOE:
9093 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9094 if (ret) {
9095 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9096 return ret;
9097 }
9098 break;
9099
9100#endif /* I40E_FCOE */
41c445ff
JB		 9101 default:
9102 return -ENODEV;
9103 }
9104
9105 if (vsi->type != I40E_VSI_MAIN) {
9106 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9107 if (ret) {
9108 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9109 "add vsi failed, err %s aq_err %s\n",
9110 i40e_stat_str(&pf->hw, ret),
9111 i40e_aq_str(&pf->hw,
9112 pf->hw.aq.asq_last_status));
41c445ff
JB		 9113 ret = -ENOENT;
9114 goto err;
9115 }
1a2f6248 9116 vsi->info = ctxt.info;
41c445ff
JB		 9117 vsi->info.valid_sections = 0;
9118 vsi->seid = ctxt.seid;
9119 vsi->id = ctxt.vsi_number;
9120 }
9121
21659035 9122 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9123 /* If macvlan filters already exist, force them to get loaded */
9124 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9125 f->changed = true;
9126 f_count++;
6252c7e4 9127
21659035 9128 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9129 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9130 ether_addr_copy(laa_macaddr, f->macaddr);
9131 found_laa_mac_filter = true;
9132 }
9133 }
9134 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9135
21659035
KP		 9136 if (found_laa_mac_filter) {
9137 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9138
21659035
KP		 9139 memset(&element, 0, sizeof(element));
9140 ether_addr_copy(element.mac_addr, laa_macaddr);
9141 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9142 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9143 &element, 1, NULL);
9144 if (ret) {
9145 /* some older FW has a different default */
9146 element.flags |=
9147 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9148 i40e_aq_remove_macvlan(hw, vsi->seid,
9149 &element, 1, NULL);
6252c7e4 9150 }
21659035
KP		 9151
9152 i40e_aq_mac_address_write(hw,
9153 I40E_AQC_WRITE_TYPE_LAA_WOL,
9154 laa_macaddr, NULL);
41c445ff 9155 }
21659035 9156
41c445ff
JB		 9157 if (f_count) {
9158 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9159 pf->flags |= I40E_FLAG_FILTER_SYNC;
9160 }
9161
9162 /* Update VSI BW information */
9163 ret = i40e_vsi_get_bw_info(vsi);
9164 if (ret) {
9165 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9166 "couldn't get vsi bw info, err %s aq_err %s\n",
9167 i40e_stat_str(&pf->hw, ret),
9168 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9169 /* VSI is already added so not tearing that up */
9170 ret = 0;
9171 }
9172
9173err:
9174 return ret;
9175}
9176
9177/**
9178 * i40e_vsi_release - Delete a VSI and free its resources
9179 * @vsi: the VSI being removed
9180 *
9181 * Returns 0 on success or < 0 on error
9182 **/
9183int i40e_vsi_release(struct i40e_vsi *vsi)
9184{
9185 struct i40e_mac_filter *f, *ftmp;
9186 struct i40e_veb *veb = NULL;
9187 struct i40e_pf *pf;
9188 u16 uplink_seid;
9189 int i, n;
9190
9191 pf = vsi->back;
9192
9193 /* release of a VEB-owner or last VSI is not allowed */
9194 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9195 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9196 vsi->seid, vsi->uplink_seid);
9197 return -ENODEV;
9198 }
9199 if (vsi == pf->vsi[pf->lan_vsi] &&
9200 !test_bit(__I40E_DOWN, &pf->state)) {
9201 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9202 return -ENODEV;
9203 }
9204
9205 uplink_seid = vsi->uplink_seid;
9206 if (vsi->type != I40E_VSI_SRIOV) {
9207 if (vsi->netdev_registered) {
9208 vsi->netdev_registered = false;
9209 if (vsi->netdev) {
9210 /* results in a call to i40e_close() */
9211 unregister_netdev(vsi->netdev);
41c445ff
JB		 9212 }
9213 } else {
90ef8d47 9214 i40e_vsi_close(vsi);
41c445ff
JB		 9215 }
9216 i40e_vsi_disable_irq(vsi);
9217 }
9218
21659035 9219 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9220 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9221 i40e_del_filter(vsi, f->macaddr, f->vlan,
9222 f->is_vf, f->is_netdev);
21659035
KP		 9223 spin_unlock_bh(&vsi->mac_filter_list_lock);
9224
30e2561b 9225 i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 9226
9227 i40e_vsi_delete(vsi);
9228 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9229 if (vsi->netdev) {
9230 free_netdev(vsi->netdev);
9231 vsi->netdev = NULL;
9232 }
41c445ff
JB		 9233 i40e_vsi_clear_rings(vsi);
9234 i40e_vsi_clear(vsi);
9235
9236 /* If this was the last thing on the VEB, except for the
9237 * controlling VSI, remove the VEB, which puts the controlling
9238 * VSI onto the next level down in the switch.
9239 *
9240 * Well, okay, there's one more exception here: don't remove
9241 * the orphan VEBs yet. We'll wait for an explicit remove request
9242 * from up the network stack.
9243 */
505682cd 9244 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9245 if (pf->vsi[i] &&
9246 pf->vsi[i]->uplink_seid == uplink_seid &&
9247 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9248 n++; /* count the VSIs */
9249 }
9250 }
9251 for (i = 0; i < I40E_MAX_VEB; i++) {
9252 if (!pf->veb[i])
9253 continue;
9254 if (pf->veb[i]->uplink_seid == uplink_seid)
9255 n++; /* count the VEBs */
9256 if (pf->veb[i]->seid == uplink_seid)
9257 veb = pf->veb[i];
9258 }
9259 if (n == 0 && veb && veb->uplink_seid != 0)
9260 i40e_veb_release(veb);
9261
9262 return 0;
9263}
9264
9265/**
9266 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9267 * @vsi: ptr to the VSI
9268 *
9269 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9270 * corresponding SW VSI structure and initializes num_queue_pairs for the
9271 * newly allocated VSI.
9272 *
9273 * Returns 0 on success or negative on failure
9274 **/
9275static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9276{
9277 int ret = -ENOENT;
9278 struct i40e_pf *pf = vsi->back;
9279
493fb300 9280 if (vsi->q_vectors[0]) {
41c445ff
JB		 9281 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9282 vsi->seid);
9283 return -EEXIST;
9284 }
9285
9286 if (vsi->base_vector) {
f29eaa3d 9287 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9288 vsi->seid, vsi->base_vector);
9289 return -EEXIST;
9290 }
9291
90e04070 9292 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9293 if (ret) {
9294 dev_info(&pf->pdev->dev,
9295 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9296 vsi->num_q_vectors, vsi->seid, ret);
9297 vsi->num_q_vectors = 0;
9298 goto vector_setup_out;
9299 }
9300
26cdc443
ASJ		 9301 /* In Legacy mode, we do not have to get any other vector since we
9302 * piggyback on the misc/ICR0 for queue interrupts.
9303 */
9304 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9305 return ret;
958a3e3b
SN		 9306 if (vsi->num_q_vectors)
9307 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9308 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9309 if (vsi->base_vector < 0) {
9310 dev_info(&pf->pdev->dev,
049a2be8
SN		 9311 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9312 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9313 i40e_vsi_free_q_vectors(vsi);
9314 ret = -ENOENT;
9315 goto vector_setup_out;
9316 }
9317
9318vector_setup_out:
9319 return ret;
9320}
9321
bc7d338f
ASJ		 9322/**
9323 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9324 * @vsi: pointer to the vsi.
9325 *
9326 * This re-allocates a vsi's queue resources.
9327 *
9328 * Returns pointer to the successfully allocated and configured VSI sw struct
9329 * on success, otherwise returns NULL on failure.
9330 **/
9331static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9332{
9333 struct i40e_pf *pf = vsi->back;
9334 u8 enabled_tc;
9335 int ret;
9336
9337 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9338 i40e_vsi_clear_rings(vsi);
9339
9340 i40e_vsi_free_arrays(vsi, false);
9341 i40e_set_num_rings_in_vsi(vsi);
9342 ret = i40e_vsi_alloc_arrays(vsi, false);
9343 if (ret)
9344 goto err_vsi;
9345
9346 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9347 if (ret < 0) {
049a2be8 9348 dev_info(&pf->pdev->dev,
f1c7e72e 9349 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9350 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9351 goto err_vsi;
9352 }
9353 vsi->base_queue = ret;
9354
9355 /* Update the FW view of the VSI. Force a reset of TC and queue
9356 * layout configurations.
9357 */
9358 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9359 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9360 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9361 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9362
9363 /* assign it some queues */
9364 ret = i40e_alloc_rings(vsi);
9365 if (ret)
9366 goto err_rings;
9367
9368 /* map all of the rings to the q_vectors */
9369 i40e_vsi_map_rings_to_vectors(vsi);
9370 return vsi;
9371
9372err_rings:
9373 i40e_vsi_free_q_vectors(vsi);
9374 if (vsi->netdev_registered) {
9375 vsi->netdev_registered = false;
9376 unregister_netdev(vsi->netdev);
9377 free_netdev(vsi->netdev);
9378 vsi->netdev = NULL;
9379 }
9380 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9381err_vsi:
9382 i40e_vsi_clear(vsi);
9383 return NULL;
9384}
9385
41c445ff
JB		 9386/**
9387 * i40e_vsi_setup - Set up a VSI by a given type
9388 * @pf: board private structure
9389 * @type: VSI type
9390 * @uplink_seid: the switch element to link to
9391 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9392 *
9393 * This allocates the sw VSI structure and its queue resources, then add a VSI
9394 * to the identified VEB.
9395 *
9396 * Returns pointer to the successfully allocated and configure VSI sw struct on
9397 * success, otherwise returns NULL on failure.
9398 **/
9399struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9400 u16 uplink_seid, u32 param1)
9401{
9402 struct i40e_vsi *vsi = NULL;
9403 struct i40e_veb *veb = NULL;
9404 int ret, i;
9405 int v_idx;
9406
9407 /* The requested uplink_seid must be either
9408 * - the PF's port seid
9409 * no VEB is needed because this is the PF
9410 * or this is a Flow Director special case VSI
9411 * - seid of an existing VEB
9412 * - seid of a VSI that owns an existing VEB
9413 * - seid of a VSI that doesn't own a VEB
9414 * a new VEB is created and the VSI becomes the owner
9415 * - seid of the PF VSI, which is what creates the first VEB
9416 * this is a special case of the previous
9417 *
9418 * Find which uplink_seid we were given and create a new VEB if needed
9419 */
9420 for (i = 0; i < I40E_MAX_VEB; i++) {
9421 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9422 veb = pf->veb[i];
9423 break;
9424 }
9425 }
9426
9427 if (!veb && uplink_seid != pf->mac_seid) {
9428
505682cd 9429 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9430 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9431 vsi = pf->vsi[i];
9432 break;
9433 }
9434 }
9435 if (!vsi) {
9436 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9437 uplink_seid);
9438 return NULL;
9439 }
9440
9441 if (vsi->uplink_seid == pf->mac_seid)
9442 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9443 vsi->tc_config.enabled_tc);
9444 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9445 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9446 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9447 if (veb) {
9448 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9449 dev_info(&vsi->back->pdev->dev,
fb43201f 9450 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9451 return NULL;
9452 }
fa11cb3d
ASJ		 9453 /* We come up by default in VEPA mode if SRIOV is not
9454 * already enabled, in which case we can't force VEPA
9455 * mode.
9456 */
9457 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9458 veb->bridge_mode = BRIDGE_MODE_VEPA;
9459 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9460 }
51616018 9461 i40e_config_bridge_mode(veb);
79c21a82 9462 }
41c445ff
JB		 9463 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9464 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9465 veb = pf->veb[i];
9466 }
9467 if (!veb) {
9468 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9469 return NULL;
9470 }
9471
9472 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9473 uplink_seid = veb->seid;
9474 }
9475
9476 /* get vsi sw struct */
9477 v_idx = i40e_vsi_mem_alloc(pf, type);
9478 if (v_idx < 0)
9479 goto err_alloc;
9480 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9481 if (!vsi)
9482 goto err_alloc;
41c445ff
JB		 9483 vsi->type = type;
9484 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9485
9486 if (type == I40E_VSI_MAIN)
9487 pf->lan_vsi = v_idx;
9488 else if (type == I40E_VSI_SRIOV)
9489 vsi->vf_id = param1;
9490 /* assign it some queues */
cbf61325
ASJ		 9491 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9492 vsi->idx);
41c445ff 9493 if (ret < 0) {
049a2be8
SN		 9494 dev_info(&pf->pdev->dev,
9495 "failed to get tracking for %d queues for VSI %d err=%d\n",
9496 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9497 goto err_vsi;
9498 }
9499 vsi->base_queue = ret;
9500
9501 /* get a VSI from the hardware */
9502 vsi->uplink_seid = uplink_seid;
9503 ret = i40e_add_vsi(vsi);
9504 if (ret)
9505 goto err_vsi;
9506
9507 switch (vsi->type) {
9508 /* setup the netdev if needed */
9509 case I40E_VSI_MAIN:
9510 case I40E_VSI_VMDQ2:
38e00438 9511 case I40E_VSI_FCOE:
41c445ff
JB		 9512 ret = i40e_config_netdev(vsi);
9513 if (ret)
9514 goto err_netdev;
9515 ret = register_netdev(vsi->netdev);
9516 if (ret)
9517 goto err_netdev;
9518 vsi->netdev_registered = true;
9519 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9520#ifdef CONFIG_I40E_DCB
9521 /* Setup DCB netlink interface */
9522 i40e_dcbnl_setup(vsi);
9523#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9524 /* fall through */
9525
9526 case I40E_VSI_FDIR:
9527 /* set up vectors and rings if needed */
9528 ret = i40e_vsi_setup_vectors(vsi);
9529 if (ret)
9530 goto err_msix;
9531
9532 ret = i40e_alloc_rings(vsi);
9533 if (ret)
9534 goto err_rings;
9535
9536 /* map all of the rings to the q_vectors */
9537 i40e_vsi_map_rings_to_vectors(vsi);
9538
9539 i40e_vsi_reset_stats(vsi);
9540 break;
9541
9542 default:
9543 /* no netdev or rings for the other VSI types */
9544 break;
9545 }
9546
e25d00b8
ASJ		 9547 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9548 (vsi->type == I40E_VSI_VMDQ2)) {
9549 ret = i40e_vsi_config_rss(vsi);
9550 }
41c445ff
JB		 9551 return vsi;
9552
9553err_rings:
9554 i40e_vsi_free_q_vectors(vsi);
9555err_msix:
9556 if (vsi->netdev_registered) {
9557 vsi->netdev_registered = false;
9558 unregister_netdev(vsi->netdev);
9559 free_netdev(vsi->netdev);
9560 vsi->netdev = NULL;
9561 }
9562err_netdev:
9563 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9564err_vsi:
9565 i40e_vsi_clear(vsi);
9566err_alloc:
9567 return NULL;
9568}
9569
9570/**
9571 * i40e_veb_get_bw_info - Query VEB BW information
9572 * @veb: the veb to query
9573 *
9574 * Query the Tx scheduler BW configuration data for given VEB
9575 **/
9576static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9577{
9578 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9579 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9580 struct i40e_pf *pf = veb->pf;
9581 struct i40e_hw *hw = &pf->hw;
9582 u32 tc_bw_max;
9583 int ret = 0;
9584 int i;
9585
9586 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9587 &bw_data, NULL);
9588 if (ret) {
9589 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9590 "query veb bw config failed, err %s aq_err %s\n",
9591 i40e_stat_str(&pf->hw, ret),
9592 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9593 goto out;
9594 }
9595
9596 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9597 &ets_data, NULL);
9598 if (ret) {
9599 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9600 "query veb bw ets config failed, err %s aq_err %s\n",
9601 i40e_stat_str(&pf->hw, ret),
9602 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9603 goto out;
9604 }
9605
9606 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9607 veb->bw_max_quanta = ets_data.tc_bw_max;
9608 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9609 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9610 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9611 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9612 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9613 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9614 veb->bw_tc_limit_credits[i] =
9615 le16_to_cpu(bw_data.tc_bw_limits[i]);
9616 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9617 }
9618
9619out:
9620 return ret;
9621}
9622
9623/**
9624 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9625 * @pf: board private structure
9626 *
9627 * On error: returns error code (negative)
9628 * On success: returns vsi index in PF (positive)
9629 **/
9630static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9631{
9632 int ret = -ENOENT;
9633 struct i40e_veb *veb;
9634 int i;
9635
9636 /* Need to protect the allocation of switch elements at the PF level */
9637 mutex_lock(&pf->switch_mutex);
9638
9639 /* VEB list may be fragmented if VEB creation/destruction has
9640 * been happening. We can afford to do a quick scan to look
9641 * for any free slots in the list.
9642 *
9643 * find next empty veb slot, looping back around if necessary
9644 */
9645 i = 0;
9646 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9647 i++;
9648 if (i >= I40E_MAX_VEB) {
9649 ret = -ENOMEM;
9650 goto err_alloc_veb; /* out of VEB slots! */
9651 }
9652
9653 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9654 if (!veb) {
9655 ret = -ENOMEM;
9656 goto err_alloc_veb;
9657 }
9658 veb->pf = pf;
9659 veb->idx = i;
9660 veb->enabled_tc = 1;
9661
9662 pf->veb[i] = veb;
9663 ret = i;
9664err_alloc_veb:
9665 mutex_unlock(&pf->switch_mutex);
9666 return ret;
9667}
9668
9669/**
9670 * i40e_switch_branch_release - Delete a branch of the switch tree
9671 * @branch: where to start deleting
9672 *
9673 * This uses recursion to find the tips of the branch to be
9674 * removed, deleting until we get back to and can delete this VEB.
9675 **/
9676static void i40e_switch_branch_release(struct i40e_veb *branch)
9677{
9678 struct i40e_pf *pf = branch->pf;
9679 u16 branch_seid = branch->seid;
9680 u16 veb_idx = branch->idx;
9681 int i;
9682
9683 /* release any VEBs on this VEB - RECURSION */
9684 for (i = 0; i < I40E_MAX_VEB; i++) {
9685 if (!pf->veb[i])
9686 continue;
9687 if (pf->veb[i]->uplink_seid == branch->seid)
9688 i40e_switch_branch_release(pf->veb[i]);
9689 }
9690
9691 /* Release the VSIs on this VEB, but not the owner VSI.
9692 *
9693 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9694 * the VEB itself, so don't use (*branch) after this loop.
9695 */
505682cd 9696 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9697 if (!pf->vsi[i])
9698 continue;
9699 if (pf->vsi[i]->uplink_seid == branch_seid &&
9700 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9701 i40e_vsi_release(pf->vsi[i]);
9702 }
9703 }
9704
9705 /* There's one corner case where the VEB might not have been
9706 * removed, so double check it here and remove it if needed.
9707 * This case happens if the veb was created from the debugfs
9708 * commands and no VSIs were added to it.
9709 */
9710 if (pf->veb[veb_idx])
9711 i40e_veb_release(pf->veb[veb_idx]);
9712}
9713
9714/**
9715 * i40e_veb_clear - remove veb struct
9716 * @veb: the veb to remove
9717 **/
9718static void i40e_veb_clear(struct i40e_veb *veb)
9719{
9720 if (!veb)
9721 return;
9722
9723 if (veb->pf) {
9724 struct i40e_pf *pf = veb->pf;
9725
9726 mutex_lock(&pf->switch_mutex);
9727 if (pf->veb[veb->idx] == veb)
9728 pf->veb[veb->idx] = NULL;
9729 mutex_unlock(&pf->switch_mutex);
9730 }
9731
9732 kfree(veb);
9733}
9734
9735/**
9736 * i40e_veb_release - Delete a VEB and free its resources
9737 * @veb: the VEB being removed
9738 **/
9739void i40e_veb_release(struct i40e_veb *veb)
9740{
9741 struct i40e_vsi *vsi = NULL;
9742 struct i40e_pf *pf;
9743 int i, n = 0;
9744
9745 pf = veb->pf;
9746
9747 /* find the remaining VSI and check for extras */
505682cd 9748 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9749 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9750 n++;
9751 vsi = pf->vsi[i];
9752 }
9753 }
9754 if (n != 1) {
9755 dev_info(&pf->pdev->dev,
9756 "can't remove VEB %d with %d VSIs left\n",
9757 veb->seid, n);
9758 return;
9759 }
9760
9761 /* move the remaining VSI to uplink veb */
9762 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9763 if (veb->uplink_seid) {
9764 vsi->uplink_seid = veb->uplink_seid;
9765 if (veb->uplink_seid == pf->mac_seid)
9766 vsi->veb_idx = I40E_NO_VEB;
9767 else
9768 vsi->veb_idx = veb->veb_idx;
9769 } else {
9770 /* floating VEB */
9771 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9772 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9773 }
9774
9775 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9776 i40e_veb_clear(veb);
41c445ff
JB		 9777}
9778
9779/**
9780 * i40e_add_veb - create the VEB in the switch
9781 * @veb: the VEB to be instantiated
9782 * @vsi: the controlling VSI
9783 **/
9784static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9785{
f1c7e72e 9786 struct i40e_pf *pf = veb->pf;
92faef85 9787 bool is_default = veb->pf->cur_promisc;
e1c51b95 9788 bool is_cloud = false;
41c445ff
JB		 9789 int ret;
9790
9791 /* get a VEB from the hardware */
f1c7e72e 9792 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9793 veb->enabled_tc, is_default,
9794 is_cloud, &veb->seid, NULL);
41c445ff 9795 if (ret) {
f1c7e72e
SN		 9796 dev_info(&pf->pdev->dev,
9797 "couldn't add VEB, err %s aq_err %s\n",
9798 i40e_stat_str(&pf->hw, ret),
9799 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9800 return -EPERM;
9801 }
9802
9803 /* get statistics counter */
f1c7e72e 9804 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9805 &veb->stats_idx, NULL, NULL, NULL);
9806 if (ret) {
f1c7e72e
SN		 9807 dev_info(&pf->pdev->dev,
9808 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9809 i40e_stat_str(&pf->hw, ret),
9810 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9811 return -EPERM;
9812 }
9813 ret = i40e_veb_get_bw_info(veb);
9814 if (ret) {
f1c7e72e
SN		 9815 dev_info(&pf->pdev->dev,
9816 "couldn't get VEB bw info, err %s aq_err %s\n",
9817 i40e_stat_str(&pf->hw, ret),
9818 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9819 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9820 return -ENOENT;
9821 }
9822
9823 vsi->uplink_seid = veb->seid;
9824 vsi->veb_idx = veb->idx;
9825 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9826
9827 return 0;
9828}
9829
9830/**
9831 * i40e_veb_setup - Set up a VEB
9832 * @pf: board private structure
9833 * @flags: VEB setup flags
9834 * @uplink_seid: the switch element to link to
9835 * @vsi_seid: the initial VSI seid
9836 * @enabled_tc: Enabled TC bit-map
9837 *
9838 * This allocates the sw VEB structure and links it into the switch
9839 * It is possible and legal for this to be a duplicate of an already
9840 * existing VEB. It is also possible for both uplink and vsi seids
9841 * to be zero, in order to create a floating VEB.
9842 *
9843 * Returns pointer to the successfully allocated VEB sw struct on
9844 * success, otherwise returns NULL on failure.
9845 **/
9846struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9847 u16 uplink_seid, u16 vsi_seid,
9848 u8 enabled_tc)
9849{
9850 struct i40e_veb *veb, *uplink_veb = NULL;
9851 int vsi_idx, veb_idx;
9852 int ret;
9853
9854 /* if one seid is 0, the other must be 0 to create a floating relay */
9855 if ((uplink_seid == 0 || vsi_seid == 0) &&
9856 (uplink_seid + vsi_seid != 0)) {
9857 dev_info(&pf->pdev->dev,
9858 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9859 uplink_seid, vsi_seid);
9860 return NULL;
9861 }
9862
9863 /* make sure there is such a vsi and uplink */
505682cd 9864 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9865 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9866 break;
505682cd 9867 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9868 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9869 vsi_seid);
9870 return NULL;
9871 }
9872
9873 if (uplink_seid && uplink_seid != pf->mac_seid) {
9874 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9875 if (pf->veb[veb_idx] &&
9876 pf->veb[veb_idx]->seid == uplink_seid) {
9877 uplink_veb = pf->veb[veb_idx];
9878 break;
9879 }
9880 }
9881 if (!uplink_veb) {
9882 dev_info(&pf->pdev->dev,
9883 "uplink seid %d not found\n", uplink_seid);
9884 return NULL;
9885 }
9886 }
9887
9888 /* get veb sw struct */
9889 veb_idx = i40e_veb_mem_alloc(pf);
9890 if (veb_idx < 0)
9891 goto err_alloc;
9892 veb = pf->veb[veb_idx];
9893 veb->flags = flags;
9894 veb->uplink_seid = uplink_seid;
9895 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9896 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9897
9898 /* create the VEB in the switch */
9899 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9900 if (ret)
9901 goto err_veb;
1bb8b935
SN		 9902 if (vsi_idx == pf->lan_vsi)
9903 pf->lan_veb = veb->idx;
41c445ff
JB		 9904
9905 return veb;
9906
9907err_veb:
9908 i40e_veb_clear(veb);
9909err_alloc:
9910 return NULL;
9911}
9912
9913/**
b40c82e6 9914 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9915 * @pf: board private structure
9916 * @ele: element we are building info from
9917 * @num_reported: total number of elements
9918 * @printconfig: should we print the contents
9919 *
9920 * helper function to assist in extracting a few useful SEID values.
9921 **/
9922static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9923 struct i40e_aqc_switch_config_element_resp *ele,
9924 u16 num_reported, bool printconfig)
9925{
9926 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9927 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9928 u8 element_type = ele->element_type;
9929 u16 seid = le16_to_cpu(ele->seid);
9930
9931 if (printconfig)
9932 dev_info(&pf->pdev->dev,
9933 "type=%d seid=%d uplink=%d downlink=%d\n",
9934 element_type, seid, uplink_seid, downlink_seid);
9935
9936 switch (element_type) {
9937 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9938 pf->mac_seid = seid;
9939 break;
9940 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9941 /* Main VEB? */
9942 if (uplink_seid != pf->mac_seid)
9943 break;
9944 if (pf->lan_veb == I40E_NO_VEB) {
9945 int v;
9946
9947 /* find existing or else empty VEB */
9948 for (v = 0; v < I40E_MAX_VEB; v++) {
9949 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9950 pf->lan_veb = v;
9951 break;
9952 }
9953 }
9954 if (pf->lan_veb == I40E_NO_VEB) {
9955 v = i40e_veb_mem_alloc(pf);
9956 if (v < 0)
9957 break;
9958 pf->lan_veb = v;
9959 }
9960 }
9961
9962 pf->veb[pf->lan_veb]->seid = seid;
9963 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9964 pf->veb[pf->lan_veb]->pf = pf;
9965 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9966 break;
9967 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9968 if (num_reported != 1)
9969 break;
9970 /* This is immediately after a reset so we can assume this is
9971 * the PF's VSI
9972 */
9973 pf->mac_seid = uplink_seid;
9974 pf->pf_seid = downlink_seid;
9975 pf->main_vsi_seid = seid;
9976 if (printconfig)
9977 dev_info(&pf->pdev->dev,
9978 "pf_seid=%d main_vsi_seid=%d\n",
9979 pf->pf_seid, pf->main_vsi_seid);
9980 break;
9981 case I40E_SWITCH_ELEMENT_TYPE_PF:
9982 case I40E_SWITCH_ELEMENT_TYPE_VF:
9983 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9984 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9985 case I40E_SWITCH_ELEMENT_TYPE_PE:
9986 case I40E_SWITCH_ELEMENT_TYPE_PA:
9987 /* ignore these for now */
9988 break;
9989 default:
9990 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9991 element_type, seid);
9992 break;
9993 }
9994}
9995
9996/**
9997 * i40e_fetch_switch_configuration - Get switch config from firmware
9998 * @pf: board private structure
9999 * @printconfig: should we print the contents
10000 *
10001 * Get the current switch configuration from the device and
10002 * extract a few useful SEID values.
10003 **/
10004int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10005{
10006 struct i40e_aqc_get_switch_config_resp *sw_config;
10007 u16 next_seid = 0;
10008 int ret = 0;
10009 u8 *aq_buf;
10010 int i;
10011
10012 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10013 if (!aq_buf)
10014 return -ENOMEM;
10015
10016 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10017 do {
10018 u16 num_reported, num_total;
10019
10020 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10021 I40E_AQ_LARGE_BUF,
10022 &next_seid, NULL);
10023 if (ret) {
10024 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10025 "get switch config failed err %s aq_err %s\n",
10026 i40e_stat_str(&pf->hw, ret),
10027 i40e_aq_str(&pf->hw,
10028 pf->hw.aq.asq_last_status));
41c445ff
JB		 10029 kfree(aq_buf);
10030 return -ENOENT;
10031 }
10032
10033 num_reported = le16_to_cpu(sw_config->header.num_reported);
10034 num_total = le16_to_cpu(sw_config->header.num_total);
10035
10036 if (printconfig)
10037 dev_info(&pf->pdev->dev,
10038 "header: %d reported %d total\n",
10039 num_reported, num_total);
10040
41c445ff
JB		 10041 for (i = 0; i < num_reported; i++) {
10042 struct i40e_aqc_switch_config_element_resp *ele =
10043 &sw_config->element[i];
10044
10045 i40e_setup_pf_switch_element(pf, ele, num_reported,
10046 printconfig);
10047 }
10048 } while (next_seid != 0);
10049
10050 kfree(aq_buf);
10051 return ret;
10052}
10053
10054/**
10055 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10056 * @pf: board private structure
bc7d338f 10057 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10058 *
10059 * Returns 0 on success, negative value on failure
10060 **/
bc7d338f 10061static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10062{
10063 int ret;
10064
10065 /* find out what's out there already */
10066 ret = i40e_fetch_switch_configuration(pf, false);
10067 if (ret) {
10068 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10069 "couldn't fetch switch config, err %s aq_err %s\n",
10070 i40e_stat_str(&pf->hw, ret),
10071 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10072 return ret;
10073 }
10074 i40e_pf_reset_stats(pf);
10075
41c445ff 10076 /* first time setup */
bc7d338f 10077 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10078 struct i40e_vsi *vsi = NULL;
10079 u16 uplink_seid;
10080
10081 /* Set up the PF VSI associated with the PF's main VSI
10082 * that is already in the HW switch
10083 */
10084 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10085 uplink_seid = pf->veb[pf->lan_veb]->seid;
10086 else
10087 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10088 if (pf->lan_vsi == I40E_NO_VSI)
10089 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10090 else if (reinit)
10091 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10092 if (!vsi) {
10093 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10094 i40e_fdir_teardown(pf);
10095 return -EAGAIN;
10096 }
41c445ff
JB		 10097 } else {
10098 /* force a reset of TC and queue layout configurations */
10099 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10100
41c445ff
JB		 10101 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10102 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10103 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10104 }
10105 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10106
cbf61325
ASJ		 10107 i40e_fdir_sb_setup(pf);
10108
41c445ff
JB		 10109 /* Setup static PF queue filter control settings */
10110 ret = i40e_setup_pf_filter_control(pf);
10111 if (ret) {
10112 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10113 ret);
10114 /* Failure here should not stop continuing other steps */
10115 }
10116
10117 /* enable RSS in the HW, even for only one queue, as the stack can use
10118 * the hash
10119 */
10120 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10121 i40e_pf_config_rss(pf);
41c445ff
JB		 10122
10123 /* fill in link information and enable LSE reporting */
0a862b43 10124 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10125 i40e_link_event(pf);
10126
d52c20b7 10127 /* Initialize user-specific link properties */
41c445ff
JB		 10128 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10129 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10130
beb0dff1
JK		 10131 i40e_ptp_init(pf);
10132
41c445ff
JB		 10133 return ret;
10134}
10135
41c445ff
JB		 10136/**
10137 * i40e_determine_queue_usage - Work out queue distribution
10138 * @pf: board private structure
10139 **/
10140static void i40e_determine_queue_usage(struct i40e_pf *pf)
10141{
41c445ff
JB		 10142 int queues_left;
10143
10144 pf->num_lan_qps = 0;
38e00438
VD		 10145#ifdef I40E_FCOE
10146 pf->num_fcoe_qps = 0;
10147#endif
41c445ff
JB		 10148
10149 /* Find the max queues to be put into basic use. We'll always be
10150 * using TC0, whether or not DCB is running, and TC0 will get the
10151 * big RSS set.
10152 */
10153 queues_left = pf->hw.func_caps.num_tx_qp;
10154
cbf61325 10155 if ((queues_left == 1) ||
9aa7e935 10156 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10157 /* one qp for PF, no queues for anything else */
10158 queues_left = 0;
acd65448 10159 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10160
10161 /* make sure all the fancies are disabled */
60ea5f83 10162 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10163#ifdef I40E_FCOE
10164 I40E_FLAG_FCOE_ENABLED |
10165#endif
60ea5f83
JB		 10166 I40E_FLAG_FD_SB_ENABLED |
10167 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10168 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10169 I40E_FLAG_SRIOV_ENABLED |
10170 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10171 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10172 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10173 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10174 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10175 /* one qp for PF */
acd65448 10176 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10177 queues_left -= pf->num_lan_qps;
10178
10179 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10180#ifdef I40E_FCOE
10181 I40E_FLAG_FCOE_ENABLED |
10182#endif
9aa7e935
FZ		 10183 I40E_FLAG_FD_SB_ENABLED |
10184 I40E_FLAG_FD_ATR_ENABLED |
10185 I40E_FLAG_DCB_ENABLED |
10186 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10187 } else {
cbf61325 10188 /* Not enough queues for all TCs */
4d9b6043 10189 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10190 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10191 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10192 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10193 }
9a3bd2f1
ASJ		 10194 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10195 num_online_cpus());
10196 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10197 pf->hw.func_caps.num_tx_qp);
10198
cbf61325
ASJ		 10199 queues_left -= pf->num_lan_qps;
10200 }
10201
38e00438
VD		 10202#ifdef I40E_FCOE
10203 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10204 if (I40E_DEFAULT_FCOE <= queues_left) {
10205 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10206 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10207 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10208 } else {
10209 pf->num_fcoe_qps = 0;
10210 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10211 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10212 }
10213
10214 queues_left -= pf->num_fcoe_qps;
10215 }
10216
10217#endif
cbf61325
ASJ		 10218 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10219 if (queues_left > 1) {
10220 queues_left -= 1; /* save 1 queue for FD */
10221 } else {
10222 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10223 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10224 }
41c445ff
JB		 10225 }
10226
10227 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10228 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10229 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10230 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10231 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10232 }
10233
10234 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10235 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10236 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10237 (queues_left / pf->num_vmdq_qps));
10238 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10239 }
10240
f8ff1464 10241 pf->queues_left = queues_left;
8279e495
NP		 10242 dev_dbg(&pf->pdev->dev,
10243 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10244 pf->hw.func_caps.num_tx_qp,
10245 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10246 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10247 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10248 queues_left);
38e00438 10249#ifdef I40E_FCOE
8279e495 10250 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10251#endif
41c445ff
JB		 10252}
10253
10254/**
10255 * i40e_setup_pf_filter_control - Setup PF static filter control
10256 * @pf: PF to be setup
10257 *
b40c82e6 10258 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10259 * settings. If PE/FCoE are enabled then it will also set the per PF
10260 * based filter sizes required for them. It also enables Flow director,
10261 * ethertype and macvlan type filter settings for the pf.
10262 *
10263 * Returns 0 on success, negative on failure
10264 **/
10265static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10266{
10267 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10268
10269 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10270
10271 /* Flow Director is enabled */
60ea5f83 10272 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10273 settings->enable_fdir = true;
10274
10275 /* Ethtype and MACVLAN filters enabled for PF */
10276 settings->enable_ethtype = true;
10277 settings->enable_macvlan = true;
10278
10279 if (i40e_set_filter_control(&pf->hw, settings))
10280 return -ENOENT;
10281
10282 return 0;
10283}
10284
0c22b3dd 10285#define INFO_STRING_LEN 255
7fd89545 10286#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10287static void i40e_print_features(struct i40e_pf *pf)
10288{
10289 struct i40e_hw *hw = &pf->hw;
10290 char *buf, *string;
7fd89545 10291 int i = 0;
0c22b3dd
JB		 10292
10293 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
10294 if (!string) {
10295 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
10296 return;
10297 }
10298
10299 buf = string;
10300
7fd89545 10301 i += snprintf(&buf[i], REMAIN(i), "Features: PF-id[%d] ", hw->pf_id);
0c22b3dd 10302#ifdef CONFIG_PCI_IOV
7fd89545 10303 i += snprintf(&buf[i], REMAIN(i), "VFs: %d ", pf->num_req_vfs);
0c22b3dd 10304#endif
7fd89545
SN		 10305 i += snprintf(&buf[i], REMAIN(i), "VSIs: %d QP: %d RX: %s ",
10306 pf->hw.func_caps.num_vsis,
10307 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10308 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10309
10310 if (pf->flags & I40E_FLAG_RSS_ENABLED)
7fd89545 10311 i += snprintf(&buf[i], REMAIN(i), "RSS ");
0c22b3dd 10312 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
7fd89545 10313 i += snprintf(&buf[i], REMAIN(i), "FD_ATR ");
c6423ff1 10314 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7fd89545
SN		 10315 i += snprintf(&buf[i], REMAIN(i), "FD_SB ");
10316 i += snprintf(&buf[i], REMAIN(i), "NTUPLE ");
c6423ff1 10317 }
4d9b6043 10318 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
7fd89545 10319 i += snprintf(&buf[i], REMAIN(i), "DCB ");
ce6fcb3f 10320#if IS_ENABLED(CONFIG_VXLAN)
7fd89545 10321 i += snprintf(&buf[i], REMAIN(i), "VxLAN ");
ce6fcb3f 10322#endif
0c22b3dd 10323 if (pf->flags & I40E_FLAG_PTP)
7fd89545 10324 i += snprintf(&buf[i], REMAIN(i), "PTP ");
38e00438
VD		 10325#ifdef I40E_FCOE
10326 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
7fd89545 10327 i += snprintf(&buf[i], REMAIN(i), "FCOE ");
38e00438 10328#endif
6dec1017 10329 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
7fd89545 10330 i += snprintf(&buf[i], REMAIN(i), "VEPA ");
6dec1017
SN		 10331 else
10332 buf += sprintf(buf, "VEPA ");
0c22b3dd 10333
0c22b3dd
JB		 10334 dev_info(&pf->pdev->dev, "%s\n", string);
10335 kfree(string);
7fd89545 10336 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10337}
10338
41c445ff
JB		 10339/**
10340 * i40e_probe - Device initialization routine
10341 * @pdev: PCI device information struct
10342 * @ent: entry in i40e_pci_tbl
10343 *
b40c82e6
JK		 10344 * i40e_probe initializes a PF identified by a pci_dev structure.
10345 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10346 * and a hardware reset occur.
10347 *
10348 * Returns 0 on success, negative on failure
10349 **/
10350static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10351{
e827845c 10352 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10353 struct i40e_pf *pf;
10354 struct i40e_hw *hw;
93cd765b 10355 static u16 pfs_found;
1d5109d1 10356 u16 wol_nvm_bits;
d4dfb81a 10357 u16 link_status;
6f66a484 10358 int err;
41c445ff 10359 u32 len;
4f2f017c 10360 u32 val;
8a9eb7d3 10361 u32 i;
58fc3267 10362 u8 set_fc_aq_fail;
41c445ff
JB		 10363
10364 err = pci_enable_device_mem(pdev);
10365 if (err)
10366 return err;
10367
10368 /* set up for high or low dma */
6494294f 10369 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10370 if (err) {
e3e3bfdd
JS		 10371 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10372 if (err) {
10373 dev_err(&pdev->dev,
10374 "DMA configuration failed: 0x%x\n", err);
10375 goto err_dma;
10376 }
41c445ff
JB		 10377 }
10378
10379 /* set up pci connections */
10380 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10381 IORESOURCE_MEM), i40e_driver_name);
10382 if (err) {
10383 dev_info(&pdev->dev,
10384 "pci_request_selected_regions failed %d\n", err);
10385 goto err_pci_reg;
10386 }
10387
10388 pci_enable_pcie_error_reporting(pdev);
10389 pci_set_master(pdev);
10390
10391 /* Now that we have a PCI connection, we need to do the
10392 * low level device setup. This is primarily setting up
10393 * the Admin Queue structures and then querying for the
10394 * device's current profile information.
10395 */
10396 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10397 if (!pf) {
10398 err = -ENOMEM;
10399 goto err_pf_alloc;
10400 }
10401 pf->next_vsi = 0;
10402 pf->pdev = pdev;
10403 set_bit(__I40E_DOWN, &pf->state);
10404
10405 hw = &pf->hw;
10406 hw->back = pf;
232f4706 10407
2ac8b675
SN		 10408 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10409 I40E_MAX_CSR_SPACE);
232f4706 10410
2ac8b675 10411 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10412 if (!hw->hw_addr) {
10413 err = -EIO;
10414 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10415 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10416 pf->ioremap_len, err);
41c445ff
JB		 10417 goto err_ioremap;
10418 }
10419 hw->vendor_id = pdev->vendor;
10420 hw->device_id = pdev->device;
10421 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10422 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10423 hw->subsystem_device_id = pdev->subsystem_device;
10424 hw->bus.device = PCI_SLOT(pdev->devfn);
10425 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10426 pf->instance = pfs_found;
41c445ff 10427
5b5faa43
SN		 10428 if (debug != -1) {
10429 pf->msg_enable = pf->hw.debug_mask;
10430 pf->msg_enable = debug;
10431 }
10432
7134f9ce
JB		 10433 /* do a special CORER for clearing PXE mode once at init */
10434 if (hw->revision_id == 0 &&
10435 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10436 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10437 i40e_flush(hw);
10438 msleep(200);
10439 pf->corer_count++;
10440
10441 i40e_clear_pxe_mode(hw);
10442 }
10443
41c445ff 10444 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10445 i40e_clear_hw(hw);
41c445ff
JB		 10446 err = i40e_pf_reset(hw);
10447 if (err) {
10448 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10449 goto err_pf_reset;
10450 }
10451 pf->pfr_count++;
10452
10453 hw->aq.num_arq_entries = I40E_AQ_LEN;
10454 hw->aq.num_asq_entries = I40E_AQ_LEN;
10455 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10456 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10457 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10458
b294ac70 10459 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10460 "%s-%s:misc",
10461 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10462
10463 err = i40e_init_shared_code(hw);
10464 if (err) {
b2a75c58
ASJ		 10465 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10466 err);
41c445ff
JB		 10467 goto err_pf_reset;
10468 }
10469
d52c20b7
JB		 10470 /* set up a default setting for link flow control */
10471 pf->hw.fc.requested_mode = I40E_FC_NONE;
10472
41c445ff 10473 err = i40e_init_adminq(hw);
f0b44440 10474
6dec1017
SN		 10475 /* provide nvm, fw, api versions */
10476 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10477 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10478 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10479 i40e_nvm_version_str(hw));
f0b44440 10480
41c445ff
JB		 10481 if (err) {
10482 dev_info(&pdev->dev,
7aa67613 10483 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 10484 goto err_pf_reset;
10485 }
10486
7aa67613
CS		 10487 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10488 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10489 dev_info(&pdev->dev,
7aa67613
CS		 10490 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10491 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10492 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10493 dev_info(&pdev->dev,
7aa67613 10494 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10495
4eb3f768
SN		 10496 i40e_verify_eeprom(pf);
10497
2c5fe33b
JB		 10498 /* Rev 0 hardware was never productized */
10499 if (hw->revision_id < 1)
10500 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10501
6ff4ef86 10502 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10503 err = i40e_get_capabilities(pf);
10504 if (err)
10505 goto err_adminq_setup;
10506
10507 err = i40e_sw_init(pf);
10508 if (err) {
10509 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10510 goto err_sw_init;
10511 }
10512
10513 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10514 hw->func_caps.num_rx_qp,
10515 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10516 if (err) {
10517 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10518 goto err_init_lan_hmc;
10519 }
10520
10521 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10522 if (err) {
10523 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10524 err = -ENOENT;
10525 goto err_configure_lan_hmc;
10526 }
10527
b686ece5
NP		 10528 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10529 * Ignore error return codes because if it was already disabled via
10530 * hardware settings this will fail
10531 */
10532 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10533 (pf->hw.aq.fw_maj_ver < 4)) {
10534 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10535 i40e_aq_stop_lldp(hw, true, NULL);
10536 }
10537
41c445ff 10538 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10539 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10540 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10541 err = -EIO;
10542 goto err_mac_addr;
10543 }
10544 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10545 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10546 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10547 if (is_valid_ether_addr(hw->mac.port_addr))
10548 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10549#ifdef I40E_FCOE
10550 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10551 if (err)
10552 dev_info(&pdev->dev,
10553 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10554 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10555 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10556 hw->mac.san_addr);
10557 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10558 }
10559 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10560#endif /* I40E_FCOE */
41c445ff
JB		 10561
10562 pci_set_drvdata(pdev, pf);
10563 pci_save_state(pdev);
4e3b35b0
NP		 10564#ifdef CONFIG_I40E_DCB
10565 err = i40e_init_pf_dcb(pf);
10566 if (err) {
aebfc816 10567 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10568 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10569 /* Continue without DCB enabled */
4e3b35b0
NP		 10570 }
10571#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10572
10573 /* set up periodic task facility */
10574 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10575 pf->service_timer_period = HZ;
10576
10577 INIT_WORK(&pf->service_task, i40e_service_task);
10578 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10579 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10580
1d5109d1
SN		 10581 /* NVM bit on means WoL disabled for the port */
10582 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
10583 if ((1 << hw->port) & wol_nvm_bits || hw->partition_id != 1)
10584 pf->wol_en = false;
10585 else
10586 pf->wol_en = true;
8e2773ae
SN		 10587 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10588
41c445ff
JB		 10589 /* set up the main switch operations */
10590 i40e_determine_queue_usage(pf);
c1147280
JB		 10591 err = i40e_init_interrupt_scheme(pf);
10592 if (err)
10593 goto err_switch_setup;
41c445ff 10594
505682cd
MW		 10595 /* The number of VSIs reported by the FW is the minimum guaranteed
10596 * to us; HW supports far more and we share the remaining pool with
10597 * the other PFs. We allocate space for more than the guarantee with
10598 * the understanding that we might not get them all later.
41c445ff 10599 */
505682cd
MW		 10600 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10601 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10602 else
10603 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10604
10605 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10606 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10607 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10608 if (!pf->vsi) {
10609 err = -ENOMEM;
41c445ff 10610 goto err_switch_setup;
ed87ac09 10611 }
41c445ff 10612
fa11cb3d
ASJ		 10613#ifdef CONFIG_PCI_IOV
10614 /* prep for VF support */
10615 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10616 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10617 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10618 if (pci_num_vf(pdev))
10619 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10620 }
10621#endif
bc7d338f 10622 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10623 if (err) {
10624 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10625 goto err_vsis;
10626 }
58fc3267
HZ		 10627
10628 /* Make sure flow control is set according to current settings */
10629 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10630 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10631 dev_dbg(&pf->pdev->dev,
10632 "Set fc with err %s aq_err %s on get_phy_cap\n",
10633 i40e_stat_str(hw, err),
10634 i40e_aq_str(hw, hw->aq.asq_last_status));
10635 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10636 dev_dbg(&pf->pdev->dev,
10637 "Set fc with err %s aq_err %s on set_phy_config\n",
10638 i40e_stat_str(hw, err),
10639 i40e_aq_str(hw, hw->aq.asq_last_status));
10640 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10641 dev_dbg(&pf->pdev->dev,
10642 "Set fc with err %s aq_err %s on get_link_info\n",
10643 i40e_stat_str(hw, err),
10644 i40e_aq_str(hw, hw->aq.asq_last_status));
10645
8a9eb7d3 10646 /* if FDIR VSI was set up, start it now */
505682cd 10647 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10648 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10649 i40e_vsi_open(pf->vsi[i]);
10650 break;
10651 }
10652 }
41c445ff 10653
7e2453fe
JB		 10654 /* driver is only interested in link up/down and module qualification
10655 * reports from firmware
10656 */
10657 err = i40e_aq_set_phy_int_mask(&pf->hw,
10658 I40E_AQ_EVENT_LINK_UPDOWN |
10659 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10660 if (err)
f1c7e72e
SN		 10661 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10662 i40e_stat_str(&pf->hw, err),
10663 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10664
4f2f017c
ASJ		 10665 /* Reconfigure hardware for allowing smaller MSS in the case
10666 * of TSO, so that we avoid the MDD being fired and causing
10667 * a reset in the case of small MSS+TSO.
10668 */
10669 val = rd32(hw, I40E_REG_MSS);
10670 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10671 val &= ~I40E_REG_MSS_MIN_MASK;
10672 val |= I40E_64BYTE_MSS;
10673 wr32(hw, I40E_REG_MSS, val);
10674 }
10675
025b4a54
ASJ		 10676 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10677 (pf->hw.aq.fw_maj_ver < 4)) {
10678 msleep(75);
10679 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10680 if (err)
f1c7e72e
SN		 10681 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10682 i40e_stat_str(&pf->hw, err),
10683 i40e_aq_str(&pf->hw,
10684 pf->hw.aq.asq_last_status));
cafa2ee6 10685 }
41c445ff
JB		 10686 /* The main driver is (mostly) up and happy. We need to set this state
10687 * before setting up the misc vector or we get a race and the vector
10688 * ends up disabled forever.
10689 */
10690 clear_bit(__I40E_DOWN, &pf->state);
10691
10692 /* In case of MSIX we are going to setup the misc vector right here
10693 * to handle admin queue events etc. In case of legacy and MSI
10694 * the misc functionality and queue processing is combined in
10695 * the same vector and that gets setup at open.
10696 */
10697 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10698 err = i40e_setup_misc_vector(pf);
10699 if (err) {
10700 dev_info(&pdev->dev,
10701 "setup of misc vector failed: %d\n", err);
10702 goto err_vsis;
10703 }
10704 }
10705
df805f62 10706#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10707 /* prep for VF support */
10708 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10709 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10710 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10711 u32 val;
10712
10713 /* disable link interrupts for VFs */
10714 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10715 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10716 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10717 i40e_flush(hw);
4aeec010
MW		 10718
10719 if (pci_num_vf(pdev)) {
10720 dev_info(&pdev->dev,
10721 "Active VFs found, allocating resources.\n");
10722 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10723 if (err)
10724 dev_info(&pdev->dev,
10725 "Error %d allocating resources for existing VFs\n",
10726 err);
10727 }
41c445ff 10728 }
df805f62 10729#endif /* CONFIG_PCI_IOV */
41c445ff 10730
93cd765b
ASJ		 10731 pfs_found++;
10732
41c445ff
JB		 10733 i40e_dbg_pf_init(pf);
10734
10735 /* tell the firmware that we're starting */
44033fac 10736 i40e_send_version(pf);
41c445ff
JB		 10737
10738 /* since everything's happy, start the service_task timer */
10739 mod_timer(&pf->service_timer,
10740 round_jiffies(jiffies + pf->service_timer_period));
10741
38e00438
VD		 10742#ifdef I40E_FCOE
10743 /* create FCoE interface */
10744 i40e_fcoe_vsi_setup(pf);
10745
10746#endif
3fced535
ASJ		 10747#define PCI_SPEED_SIZE 8
10748#define PCI_WIDTH_SIZE 8
10749 /* Devices on the IOSF bus do not have this information
10750 * and will report PCI Gen 1 x 1 by default so don't bother
10751 * checking them.
10752 */
10753 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
10754 char speed[PCI_SPEED_SIZE] = "Unknown";
10755 char width[PCI_WIDTH_SIZE] = "Unknown";
10756
10757 /* Get the negotiated link width and speed from PCI config
10758 * space
10759 */
10760 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
10761 &link_status);
10762
10763 i40e_set_pci_config_data(hw, link_status);
10764
10765 switch (hw->bus.speed) {
10766 case i40e_bus_speed_8000:
10767 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
10768 case i40e_bus_speed_5000:
10769 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
10770 case i40e_bus_speed_2500:
10771 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
10772 default:
10773 break;
10774 }
10775 switch (hw->bus.width) {
10776 case i40e_bus_width_pcie_x8:
10777 strncpy(width, "8", PCI_WIDTH_SIZE); break;
10778 case i40e_bus_width_pcie_x4:
10779 strncpy(width, "4", PCI_WIDTH_SIZE); break;
10780 case i40e_bus_width_pcie_x2:
10781 strncpy(width, "2", PCI_WIDTH_SIZE); break;
10782 case i40e_bus_width_pcie_x1:
10783 strncpy(width, "1", PCI_WIDTH_SIZE); break;
10784 default:
10785 break;
10786 }
10787
10788 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
10789 speed, width);
10790
10791 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10792 hw->bus.speed < i40e_bus_speed_8000) {
10793 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10794 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10795 }
d4dfb81a
CS		 10796 }
10797
e827845c
CS		 10798 /* get the requested speeds from the fw */
10799 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10800 if (err)
8279e495
NP		 10801 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
10802 i40e_stat_str(&pf->hw, err),
10803 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10804 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10805
fc72dbce
CS		 10806 /* get the supported phy types from the fw */
10807 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
10808 if (err)
10809 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
10810 i40e_stat_str(&pf->hw, err),
10811 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10812 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
10813
e7358f54
ASJ		 10814 /* Add a filter to drop all Flow control frames from any VSI from being
10815 * transmitted. By doing so we stop a malicious VF from sending out
10816 * PAUSE or PFC frames and potentially controlling traffic for other
10817 * PF/VF VSIs.
10818 * The FW can still send Flow control frames if enabled.
10819 */
10820 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
10821 pf->main_vsi_seid);
10822
0c22b3dd
JB		 10823 /* print a string summarizing features */
10824 i40e_print_features(pf);
10825
41c445ff
JB		 10826 return 0;
10827
10828 /* Unwind what we've done if something failed in the setup */
10829err_vsis:
10830 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10831 i40e_clear_interrupt_scheme(pf);
10832 kfree(pf->vsi);
04b03013
SN		 10833err_switch_setup:
10834 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10835 del_timer_sync(&pf->service_timer);
10836err_mac_addr:
10837err_configure_lan_hmc:
10838 (void)i40e_shutdown_lan_hmc(hw);
10839err_init_lan_hmc:
10840 kfree(pf->qp_pile);
41c445ff
JB		 10841err_sw_init:
10842err_adminq_setup:
10843 (void)i40e_shutdown_adminq(hw);
10844err_pf_reset:
10845 iounmap(hw->hw_addr);
10846err_ioremap:
10847 kfree(pf);
10848err_pf_alloc:
10849 pci_disable_pcie_error_reporting(pdev);
10850 pci_release_selected_regions(pdev,
10851 pci_select_bars(pdev, IORESOURCE_MEM));
10852err_pci_reg:
10853err_dma:
10854 pci_disable_device(pdev);
10855 return err;
10856}
10857
10858/**
10859 * i40e_remove - Device removal routine
10860 * @pdev: PCI device information struct
10861 *
10862 * i40e_remove is called by the PCI subsystem to alert the driver
10863 * that is should release a PCI device. This could be caused by a
10864 * Hot-Plug event, or because the driver is going to be removed from
10865 * memory.
10866 **/
10867static void i40e_remove(struct pci_dev *pdev)
10868{
10869 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 10870 struct i40e_hw *hw = &pf->hw;
41c445ff 10871 i40e_status ret_code;
41c445ff
JB		 10872 int i;
10873
10874 i40e_dbg_pf_exit(pf);
10875
beb0dff1
JK		 10876 i40e_ptp_stop(pf);
10877
bcab2db9
CW		 10878 /* Disable RSS in hw */
10879 wr32(hw, I40E_PFQF_HENA(0), 0);
10880 wr32(hw, I40E_PFQF_HENA(1), 0);
10881
41c445ff
JB		 10882 /* no more scheduling of any task */
10883 set_bit(__I40E_DOWN, &pf->state);
10884 del_timer_sync(&pf->service_timer);
10885 cancel_work_sync(&pf->service_task);
33c62b34 10886 i40e_fdir_teardown(pf);
41c445ff 10887
eb2d80bc
MW		 10888 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10889 i40e_free_vfs(pf);
10890 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10891 }
10892
41c445ff
JB		 10893 i40e_fdir_teardown(pf);
10894
10895 /* If there is a switch structure or any orphans, remove them.
10896 * This will leave only the PF's VSI remaining.
10897 */
10898 for (i = 0; i < I40E_MAX_VEB; i++) {
10899 if (!pf->veb[i])
10900 continue;
10901
10902 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10903 pf->veb[i]->uplink_seid == 0)
10904 i40e_switch_branch_release(pf->veb[i]);
10905 }
10906
10907 /* Now we can shutdown the PF's VSI, just before we kill
10908 * adminq and hmc.
10909 */
10910 if (pf->vsi[pf->lan_vsi])
10911 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10912
41c445ff 10913 /* shutdown and destroy the HMC */
60442dea
SN		 10914 if (pf->hw.hmc.hmc_obj) {
10915 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10916 if (ret_code)
10917 dev_warn(&pdev->dev,
10918 "Failed to destroy the HMC resources: %d\n",
10919 ret_code);
10920 }
41c445ff
JB		 10921
10922 /* shutdown the adminq */
41c445ff
JB		 10923 ret_code = i40e_shutdown_adminq(&pf->hw);
10924 if (ret_code)
10925 dev_warn(&pdev->dev,
10926 "Failed to destroy the Admin Queue resources: %d\n",
10927 ret_code);
10928
10929 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10930 i40e_clear_interrupt_scheme(pf);
505682cd 10931 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10932 if (pf->vsi[i]) {
10933 i40e_vsi_clear_rings(pf->vsi[i]);
10934 i40e_vsi_clear(pf->vsi[i]);
10935 pf->vsi[i] = NULL;
10936 }
10937 }
10938
10939 for (i = 0; i < I40E_MAX_VEB; i++) {
10940 kfree(pf->veb[i]);
10941 pf->veb[i] = NULL;
10942 }
10943
10944 kfree(pf->qp_pile);
41c445ff
JB		 10945 kfree(pf->vsi);
10946
41c445ff
JB		 10947 iounmap(pf->hw.hw_addr);
10948 kfree(pf);
10949 pci_release_selected_regions(pdev,
10950 pci_select_bars(pdev, IORESOURCE_MEM));
10951
10952 pci_disable_pcie_error_reporting(pdev);
10953 pci_disable_device(pdev);
10954}
10955
10956/**
10957 * i40e_pci_error_detected - warning that something funky happened in PCI land
10958 * @pdev: PCI device information struct
10959 *
10960 * Called to warn that something happened and the error handling steps
10961 * are in progress. Allows the driver to quiesce things, be ready for
10962 * remediation.
10963 **/
10964static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10965 enum pci_channel_state error)
10966{
10967 struct i40e_pf *pf = pci_get_drvdata(pdev);
10968
10969 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10970
10971 /* shutdown all operations */
9007bccd
SN		 10972 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10973 rtnl_lock();
10974 i40e_prep_for_reset(pf);
10975 rtnl_unlock();
10976 }
41c445ff
JB		 10977
10978 /* Request a slot reset */
10979 return PCI_ERS_RESULT_NEED_RESET;
10980}
10981
10982/**
10983 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10984 * @pdev: PCI device information struct
10985 *
10986 * Called to find if the driver can work with the device now that
10987 * the pci slot has been reset. If a basic connection seems good
10988 * (registers are readable and have sane content) then return a
10989 * happy little PCI_ERS_RESULT_xxx.
10990 **/
10991static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10992{
10993 struct i40e_pf *pf = pci_get_drvdata(pdev);
10994 pci_ers_result_t result;
10995 int err;
10996 u32 reg;
10997
fb43201f 10998 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 10999 if (pci_enable_device_mem(pdev)) {
11000 dev_info(&pdev->dev,
11001 "Cannot re-enable PCI device after reset.\n");
11002 result = PCI_ERS_RESULT_DISCONNECT;
11003 } else {
11004 pci_set_master(pdev);
11005 pci_restore_state(pdev);
11006 pci_save_state(pdev);
11007 pci_wake_from_d3(pdev, false);
11008
11009 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11010 if (reg == 0)
11011 result = PCI_ERS_RESULT_RECOVERED;
11012 else
11013 result = PCI_ERS_RESULT_DISCONNECT;
11014 }
11015
11016 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11017 if (err) {
11018 dev_info(&pdev->dev,
11019 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11020 err);
11021 /* non-fatal, continue */
11022 }
11023
11024 return result;
11025}
11026
11027/**
11028 * i40e_pci_error_resume - restart operations after PCI error recovery
11029 * @pdev: PCI device information struct
11030 *
11031 * Called to allow the driver to bring things back up after PCI error
11032 * and/or reset recovery has finished.
11033 **/
11034static void i40e_pci_error_resume(struct pci_dev *pdev)
11035{
11036 struct i40e_pf *pf = pci_get_drvdata(pdev);
11037
fb43201f 11038 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11039 if (test_bit(__I40E_SUSPENDED, &pf->state))
11040 return;
11041
11042 rtnl_lock();
41c445ff 11043 i40e_handle_reset_warning(pf);
4c4935a9 11044 rtnl_unlock();
9007bccd
SN		 11045}
11046
11047/**
11048 * i40e_shutdown - PCI callback for shutting down
11049 * @pdev: PCI device information struct
11050 **/
11051static void i40e_shutdown(struct pci_dev *pdev)
11052{
11053 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11054 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11055
11056 set_bit(__I40E_SUSPENDED, &pf->state);
11057 set_bit(__I40E_DOWN, &pf->state);
11058 rtnl_lock();
11059 i40e_prep_for_reset(pf);
11060 rtnl_unlock();
11061
8e2773ae
SN		 11062 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11063 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11064
02b42498
CS		 11065 del_timer_sync(&pf->service_timer);
11066 cancel_work_sync(&pf->service_task);
11067 i40e_fdir_teardown(pf);
11068
11069 rtnl_lock();
11070 i40e_prep_for_reset(pf);
11071 rtnl_unlock();
11072
11073 wr32(hw, I40E_PFPM_APM,
11074 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11075 wr32(hw, I40E_PFPM_WUFC,
11076 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11077
e147758d
SN		 11078 i40e_clear_interrupt_scheme(pf);
11079
9007bccd 11080 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11081 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11082 pci_set_power_state(pdev, PCI_D3hot);
11083 }
11084}
11085
11086#ifdef CONFIG_PM
11087/**
11088 * i40e_suspend - PCI callback for moving to D3
11089 * @pdev: PCI device information struct
11090 **/
11091static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11092{
11093 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11094 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11095
11096 set_bit(__I40E_SUSPENDED, &pf->state);
11097 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11098
9007bccd
SN		 11099 rtnl_lock();
11100 i40e_prep_for_reset(pf);
11101 rtnl_unlock();
11102
8e2773ae
SN		 11103 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11104 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11105
11106 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11107 pci_set_power_state(pdev, PCI_D3hot);
11108
11109 return 0;
41c445ff
JB		 11110}
11111
9007bccd
SN		 11112/**
11113 * i40e_resume - PCI callback for waking up from D3
11114 * @pdev: PCI device information struct
11115 **/
11116static int i40e_resume(struct pci_dev *pdev)
11117{
11118 struct i40e_pf *pf = pci_get_drvdata(pdev);
11119 u32 err;
11120
11121 pci_set_power_state(pdev, PCI_D0);
11122 pci_restore_state(pdev);
11123 /* pci_restore_state() clears dev->state_saves, so
11124 * call pci_save_state() again to restore it.
11125 */
11126 pci_save_state(pdev);
11127
11128 err = pci_enable_device_mem(pdev);
11129 if (err) {
fb43201f 11130 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11131 return err;
11132 }
11133 pci_set_master(pdev);
11134
11135 /* no wakeup events while running */
11136 pci_wake_from_d3(pdev, false);
11137
11138 /* handling the reset will rebuild the device state */
11139 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11140 clear_bit(__I40E_DOWN, &pf->state);
11141 rtnl_lock();
11142 i40e_reset_and_rebuild(pf, false);
11143 rtnl_unlock();
11144 }
11145
11146 return 0;
11147}
11148
11149#endif
41c445ff
JB		 11150static const struct pci_error_handlers i40e_err_handler = {
11151 .error_detected = i40e_pci_error_detected,
11152 .slot_reset = i40e_pci_error_slot_reset,
11153 .resume = i40e_pci_error_resume,
11154};
11155
11156static struct pci_driver i40e_driver = {
11157 .name = i40e_driver_name,
11158 .id_table = i40e_pci_tbl,
11159 .probe = i40e_probe,
11160 .remove = i40e_remove,
9007bccd
SN		 11161#ifdef CONFIG_PM
11162 .suspend = i40e_suspend,
11163 .resume = i40e_resume,
11164#endif
11165 .shutdown = i40e_shutdown,
41c445ff
JB		 11166 .err_handler = &i40e_err_handler,
11167 .sriov_configure = i40e_pci_sriov_configure,
11168};
11169
11170/**
11171 * i40e_init_module - Driver registration routine
11172 *
11173 * i40e_init_module is the first routine called when the driver is
11174 * loaded. All it does is register with the PCI subsystem.
11175 **/
11176static int __init i40e_init_module(void)
11177{
11178 pr_info("%s: %s - version %s\n", i40e_driver_name,
11179 i40e_driver_string, i40e_driver_version_str);
11180 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11181
41c445ff
JB		 11182 i40e_dbg_init();
11183 return pci_register_driver(&i40e_driver);
11184}
11185module_init(i40e_init_module);
11186
11187/**
11188 * i40e_exit_module - Driver exit cleanup routine
11189 *
11190 * i40e_exit_module is called just before the driver is removed
11191 * from memory.
11192 **/
11193static void __exit i40e_exit_module(void)
11194{
11195 pci_unregister_driver(&i40e_driver);
11196 i40e_dbg_exit();
11197}
11198module_exit(i40e_exit_module);
Linux kernel - Deliverables
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