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41c445ff JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
2818ccd9 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
41c445ff JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
41c445ff JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
b499ffb0 SV |
27 | #include <linux/etherdevice.h> |
28 | #include <linux/of_net.h> | |
29 | #include <linux/pci.h> | |
30 | ||
41c445ff JB |
31 | /* Local includes */ |
32 | #include "i40e.h" | |
4eb3f768 | 33 | #include "i40e_diag.h" |
06a5f7f1 | 34 | #include <net/udp_tunnel.h> |
41c445ff JB |
35 | |
36 | const char i40e_driver_name[] = "i40e"; | |
37 | static const char i40e_driver_string[] = | |
38 | "Intel(R) Ethernet Connection XL710 Network Driver"; | |
39 | ||
40 | #define DRV_KERN "-k" | |
41 | ||
e8e724db | 42 | #define DRV_VERSION_MAJOR 1 |
07061958 | 43 | #define DRV_VERSION_MINOR 6 |
ae33256c | 44 | #define DRV_VERSION_BUILD 11 |
41c445ff JB |
45 | #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ |
46 | __stringify(DRV_VERSION_MINOR) "." \ | |
47 | __stringify(DRV_VERSION_BUILD) DRV_KERN | |
48 | const char i40e_driver_version_str[] = DRV_VERSION; | |
8fb905b3 | 49 | static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation."; |
41c445ff JB |
50 | |
51 | /* a bit of forward declarations */ | |
52 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi); | |
53 | static void i40e_handle_reset_warning(struct i40e_pf *pf); | |
54 | static int i40e_add_vsi(struct i40e_vsi *vsi); | |
55 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi); | |
bc7d338f | 56 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit); |
41c445ff JB |
57 | static int i40e_setup_misc_vector(struct i40e_pf *pf); |
58 | static void i40e_determine_queue_usage(struct i40e_pf *pf); | |
59 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf); | |
e69ff813 HZ |
60 | static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, |
61 | u16 rss_table_size, u16 rss_size); | |
cbf61325 | 62 | static void i40e_fdir_sb_setup(struct i40e_pf *pf); |
4e3b35b0 | 63 | static int i40e_veb_get_bw_info(struct i40e_veb *veb); |
41c445ff JB |
64 | |
65 | /* i40e_pci_tbl - PCI Device ID Table | |
66 | * | |
67 | * Last entry must be all 0s | |
68 | * | |
69 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
70 | * Class, Class Mask, private data (not used) } | |
71 | */ | |
9baa3c34 | 72 | static const struct pci_device_id i40e_pci_tbl[] = { |
ab60085e | 73 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0}, |
ab60085e | 74 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0}, |
ab60085e SN |
75 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0}, |
76 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0}, | |
ab60085e SN |
77 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0}, |
78 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0}, | |
79 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0}, | |
5960d33f | 80 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0}, |
bc5166b9 | 81 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0}, |
ae24b409 | 82 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, |
35dae51d ASJ |
83 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0}, |
84 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0}, | |
87e6c1d7 ASJ |
85 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0}, |
86 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0}, | |
87 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0}, | |
d6bf58c2 | 88 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0}, |
48a3b512 SN |
89 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, |
90 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0}, | |
41c445ff JB |
91 | /* required last entry */ |
92 | {0, } | |
93 | }; | |
94 | MODULE_DEVICE_TABLE(pci, i40e_pci_tbl); | |
95 | ||
96 | #define I40E_MAX_VF_COUNT 128 | |
97 | static int debug = -1; | |
98 | module_param(debug, int, 0); | |
99 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
100 | ||
101 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
102 | MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver"); | |
103 | MODULE_LICENSE("GPL"); | |
104 | MODULE_VERSION(DRV_VERSION); | |
105 | ||
2803b16c JB |
106 | static struct workqueue_struct *i40e_wq; |
107 | ||
41c445ff JB |
108 | /** |
109 | * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code | |
110 | * @hw: pointer to the HW structure | |
111 | * @mem: ptr to mem struct to fill out | |
112 | * @size: size of memory requested | |
113 | * @alignment: what to align the allocation to | |
114 | **/ | |
115 | int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem, | |
116 | u64 size, u32 alignment) | |
117 | { | |
118 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
119 | ||
120 | mem->size = ALIGN(size, alignment); | |
121 | mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size, | |
122 | &mem->pa, GFP_KERNEL); | |
93bc73b8 JB |
123 | if (!mem->va) |
124 | return -ENOMEM; | |
41c445ff | 125 | |
93bc73b8 | 126 | return 0; |
41c445ff JB |
127 | } |
128 | ||
129 | /** | |
130 | * i40e_free_dma_mem_d - OS specific memory free for shared code | |
131 | * @hw: pointer to the HW structure | |
132 | * @mem: ptr to mem struct to free | |
133 | **/ | |
134 | int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem) | |
135 | { | |
136 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
137 | ||
138 | dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa); | |
139 | mem->va = NULL; | |
140 | mem->pa = 0; | |
141 | mem->size = 0; | |
142 | ||
143 | return 0; | |
144 | } | |
145 | ||
146 | /** | |
147 | * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code | |
148 | * @hw: pointer to the HW structure | |
149 | * @mem: ptr to mem struct to fill out | |
150 | * @size: size of memory requested | |
151 | **/ | |
152 | int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem, | |
153 | u32 size) | |
154 | { | |
155 | mem->size = size; | |
156 | mem->va = kzalloc(size, GFP_KERNEL); | |
157 | ||
93bc73b8 JB |
158 | if (!mem->va) |
159 | return -ENOMEM; | |
41c445ff | 160 | |
93bc73b8 | 161 | return 0; |
41c445ff JB |
162 | } |
163 | ||
164 | /** | |
165 | * i40e_free_virt_mem_d - OS specific memory free for shared code | |
166 | * @hw: pointer to the HW structure | |
167 | * @mem: ptr to mem struct to free | |
168 | **/ | |
169 | int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem) | |
170 | { | |
171 | /* it's ok to kfree a NULL pointer */ | |
172 | kfree(mem->va); | |
173 | mem->va = NULL; | |
174 | mem->size = 0; | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | /** | |
180 | * i40e_get_lump - find a lump of free generic resource | |
181 | * @pf: board private structure | |
182 | * @pile: the pile of resource to search | |
183 | * @needed: the number of items needed | |
184 | * @id: an owner id to stick on the items assigned | |
185 | * | |
186 | * Returns the base item index of the lump, or negative for error | |
187 | * | |
188 | * The search_hint trick and lack of advanced fit-finding only work | |
189 | * because we're highly likely to have all the same size lump requests. | |
190 | * Linear search time and any fragmentation should be minimal. | |
191 | **/ | |
192 | static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile, | |
193 | u16 needed, u16 id) | |
194 | { | |
195 | int ret = -ENOMEM; | |
ddf434ac | 196 | int i, j; |
41c445ff JB |
197 | |
198 | if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) { | |
199 | dev_info(&pf->pdev->dev, | |
200 | "param err: pile=%p needed=%d id=0x%04x\n", | |
201 | pile, needed, id); | |
202 | return -EINVAL; | |
203 | } | |
204 | ||
205 | /* start the linear search with an imperfect hint */ | |
206 | i = pile->search_hint; | |
ddf434ac | 207 | while (i < pile->num_entries) { |
41c445ff JB |
208 | /* skip already allocated entries */ |
209 | if (pile->list[i] & I40E_PILE_VALID_BIT) { | |
210 | i++; | |
211 | continue; | |
212 | } | |
213 | ||
214 | /* do we have enough in this lump? */ | |
215 | for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) { | |
216 | if (pile->list[i+j] & I40E_PILE_VALID_BIT) | |
217 | break; | |
218 | } | |
219 | ||
220 | if (j == needed) { | |
221 | /* there was enough, so assign it to the requestor */ | |
222 | for (j = 0; j < needed; j++) | |
223 | pile->list[i+j] = id | I40E_PILE_VALID_BIT; | |
224 | ret = i; | |
225 | pile->search_hint = i + j; | |
ddf434ac | 226 | break; |
41c445ff | 227 | } |
6995b36c JB |
228 | |
229 | /* not enough, so skip over it and continue looking */ | |
230 | i += j; | |
41c445ff JB |
231 | } |
232 | ||
233 | return ret; | |
234 | } | |
235 | ||
236 | /** | |
237 | * i40e_put_lump - return a lump of generic resource | |
238 | * @pile: the pile of resource to search | |
239 | * @index: the base item index | |
240 | * @id: the owner id of the items assigned | |
241 | * | |
242 | * Returns the count of items in the lump | |
243 | **/ | |
244 | static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id) | |
245 | { | |
246 | int valid_id = (id | I40E_PILE_VALID_BIT); | |
247 | int count = 0; | |
248 | int i; | |
249 | ||
250 | if (!pile || index >= pile->num_entries) | |
251 | return -EINVAL; | |
252 | ||
253 | for (i = index; | |
254 | i < pile->num_entries && pile->list[i] == valid_id; | |
255 | i++) { | |
256 | pile->list[i] = 0; | |
257 | count++; | |
258 | } | |
259 | ||
260 | if (count && index < pile->search_hint) | |
261 | pile->search_hint = index; | |
262 | ||
263 | return count; | |
264 | } | |
265 | ||
fdf0e0bf ASJ |
266 | /** |
267 | * i40e_find_vsi_from_id - searches for the vsi with the given id | |
268 | * @pf - the pf structure to search for the vsi | |
269 | * @id - id of the vsi it is searching for | |
270 | **/ | |
271 | struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id) | |
272 | { | |
273 | int i; | |
274 | ||
275 | for (i = 0; i < pf->num_alloc_vsi; i++) | |
276 | if (pf->vsi[i] && (pf->vsi[i]->id == id)) | |
277 | return pf->vsi[i]; | |
278 | ||
279 | return NULL; | |
280 | } | |
281 | ||
41c445ff JB |
282 | /** |
283 | * i40e_service_event_schedule - Schedule the service task to wake up | |
284 | * @pf: board private structure | |
285 | * | |
286 | * If not already scheduled, this puts the task into the work queue | |
287 | **/ | |
e3219ce6 | 288 | void i40e_service_event_schedule(struct i40e_pf *pf) |
41c445ff JB |
289 | { |
290 | if (!test_bit(__I40E_DOWN, &pf->state) && | |
291 | !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) && | |
292 | !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state)) | |
2803b16c | 293 | queue_work(i40e_wq, &pf->service_task); |
41c445ff JB |
294 | } |
295 | ||
296 | /** | |
297 | * i40e_tx_timeout - Respond to a Tx Hang | |
298 | * @netdev: network interface device structure | |
299 | * | |
300 | * If any port has noticed a Tx timeout, it is likely that the whole | |
301 | * device is munged, not just the one netdev port, so go for the full | |
302 | * reset. | |
303 | **/ | |
38e00438 VD |
304 | #ifdef I40E_FCOE |
305 | void i40e_tx_timeout(struct net_device *netdev) | |
306 | #else | |
41c445ff | 307 | static void i40e_tx_timeout(struct net_device *netdev) |
38e00438 | 308 | #endif |
41c445ff JB |
309 | { |
310 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
311 | struct i40e_vsi *vsi = np->vsi; | |
312 | struct i40e_pf *pf = vsi->back; | |
b03a8c1f KP |
313 | struct i40e_ring *tx_ring = NULL; |
314 | unsigned int i, hung_queue = 0; | |
315 | u32 head, val; | |
41c445ff JB |
316 | |
317 | pf->tx_timeout_count++; | |
318 | ||
b03a8c1f KP |
319 | /* find the stopped queue the same way the stack does */ |
320 | for (i = 0; i < netdev->num_tx_queues; i++) { | |
321 | struct netdev_queue *q; | |
322 | unsigned long trans_start; | |
323 | ||
324 | q = netdev_get_tx_queue(netdev, i); | |
9b36627a | 325 | trans_start = q->trans_start; |
b03a8c1f KP |
326 | if (netif_xmit_stopped(q) && |
327 | time_after(jiffies, | |
328 | (trans_start + netdev->watchdog_timeo))) { | |
329 | hung_queue = i; | |
330 | break; | |
331 | } | |
332 | } | |
333 | ||
334 | if (i == netdev->num_tx_queues) { | |
335 | netdev_info(netdev, "tx_timeout: no netdev hung queue found\n"); | |
336 | } else { | |
337 | /* now that we have an index, find the tx_ring struct */ | |
338 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
339 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
340 | if (hung_queue == | |
341 | vsi->tx_rings[i]->queue_index) { | |
342 | tx_ring = vsi->tx_rings[i]; | |
343 | break; | |
344 | } | |
345 | } | |
346 | } | |
347 | } | |
348 | ||
41c445ff | 349 | if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20))) |
b03a8c1f KP |
350 | pf->tx_timeout_recovery_level = 1; /* reset after some time */ |
351 | else if (time_before(jiffies, | |
352 | (pf->tx_timeout_last_recovery + netdev->watchdog_timeo))) | |
353 | return; /* don't do any new action before the next timeout */ | |
354 | ||
355 | if (tx_ring) { | |
356 | head = i40e_get_head(tx_ring); | |
357 | /* Read interrupt register */ | |
358 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
359 | val = rd32(&pf->hw, | |
360 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
361 | tx_ring->vsi->base_vector - 1)); | |
362 | else | |
363 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
364 | ||
365 | netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n", | |
366 | vsi->seid, hung_queue, tx_ring->next_to_clean, | |
367 | head, tx_ring->next_to_use, | |
368 | readl(tx_ring->tail), val); | |
369 | } | |
370 | ||
41c445ff | 371 | pf->tx_timeout_last_recovery = jiffies; |
b03a8c1f KP |
372 | netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n", |
373 | pf->tx_timeout_recovery_level, hung_queue); | |
41c445ff JB |
374 | |
375 | switch (pf->tx_timeout_recovery_level) { | |
41c445ff JB |
376 | case 1: |
377 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
378 | break; | |
379 | case 2: | |
380 | set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state); | |
381 | break; | |
382 | case 3: | |
383 | set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state); | |
384 | break; | |
385 | default: | |
386 | netdev_err(netdev, "tx_timeout recovery unsuccessful\n"); | |
41c445ff JB |
387 | break; |
388 | } | |
b03a8c1f | 389 | |
41c445ff JB |
390 | i40e_service_event_schedule(pf); |
391 | pf->tx_timeout_recovery_level++; | |
392 | } | |
393 | ||
41c445ff JB |
394 | /** |
395 | * i40e_get_vsi_stats_struct - Get System Network Statistics | |
396 | * @vsi: the VSI we care about | |
397 | * | |
398 | * Returns the address of the device statistics structure. | |
399 | * The statistics are actually updated from the service task. | |
400 | **/ | |
401 | struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi) | |
402 | { | |
403 | return &vsi->net_stats; | |
404 | } | |
405 | ||
406 | /** | |
407 | * i40e_get_netdev_stats_struct - Get statistics for netdev interface | |
408 | * @netdev: network interface device structure | |
409 | * | |
410 | * Returns the address of the device statistics structure. | |
411 | * The statistics are actually updated from the service task. | |
412 | **/ | |
38e00438 VD |
413 | #ifdef I40E_FCOE |
414 | struct rtnl_link_stats64 *i40e_get_netdev_stats_struct( | |
415 | struct net_device *netdev, | |
416 | struct rtnl_link_stats64 *stats) | |
417 | #else | |
41c445ff JB |
418 | static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct( |
419 | struct net_device *netdev, | |
980e9b11 | 420 | struct rtnl_link_stats64 *stats) |
38e00438 | 421 | #endif |
41c445ff JB |
422 | { |
423 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
e7046ee1 | 424 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff | 425 | struct i40e_vsi *vsi = np->vsi; |
980e9b11 AD |
426 | struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi); |
427 | int i; | |
428 | ||
bc7d338f ASJ |
429 | if (test_bit(__I40E_DOWN, &vsi->state)) |
430 | return stats; | |
431 | ||
3c325ced JB |
432 | if (!vsi->tx_rings) |
433 | return stats; | |
434 | ||
980e9b11 AD |
435 | rcu_read_lock(); |
436 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
980e9b11 AD |
437 | u64 bytes, packets; |
438 | unsigned int start; | |
439 | ||
440 | tx_ring = ACCESS_ONCE(vsi->tx_rings[i]); | |
441 | if (!tx_ring) | |
442 | continue; | |
443 | ||
444 | do { | |
57a7744e | 445 | start = u64_stats_fetch_begin_irq(&tx_ring->syncp); |
980e9b11 AD |
446 | packets = tx_ring->stats.packets; |
447 | bytes = tx_ring->stats.bytes; | |
57a7744e | 448 | } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start)); |
980e9b11 AD |
449 | |
450 | stats->tx_packets += packets; | |
451 | stats->tx_bytes += bytes; | |
452 | rx_ring = &tx_ring[1]; | |
453 | ||
454 | do { | |
57a7744e | 455 | start = u64_stats_fetch_begin_irq(&rx_ring->syncp); |
980e9b11 AD |
456 | packets = rx_ring->stats.packets; |
457 | bytes = rx_ring->stats.bytes; | |
57a7744e | 458 | } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start)); |
41c445ff | 459 | |
980e9b11 AD |
460 | stats->rx_packets += packets; |
461 | stats->rx_bytes += bytes; | |
462 | } | |
463 | rcu_read_unlock(); | |
464 | ||
a5282f44 | 465 | /* following stats updated by i40e_watchdog_subtask() */ |
980e9b11 AD |
466 | stats->multicast = vsi_stats->multicast; |
467 | stats->tx_errors = vsi_stats->tx_errors; | |
468 | stats->tx_dropped = vsi_stats->tx_dropped; | |
469 | stats->rx_errors = vsi_stats->rx_errors; | |
d8201e20 | 470 | stats->rx_dropped = vsi_stats->rx_dropped; |
980e9b11 AD |
471 | stats->rx_crc_errors = vsi_stats->rx_crc_errors; |
472 | stats->rx_length_errors = vsi_stats->rx_length_errors; | |
41c445ff | 473 | |
980e9b11 | 474 | return stats; |
41c445ff JB |
475 | } |
476 | ||
477 | /** | |
478 | * i40e_vsi_reset_stats - Resets all stats of the given vsi | |
479 | * @vsi: the VSI to have its stats reset | |
480 | **/ | |
481 | void i40e_vsi_reset_stats(struct i40e_vsi *vsi) | |
482 | { | |
483 | struct rtnl_link_stats64 *ns; | |
484 | int i; | |
485 | ||
486 | if (!vsi) | |
487 | return; | |
488 | ||
489 | ns = i40e_get_vsi_stats_struct(vsi); | |
490 | memset(ns, 0, sizeof(*ns)); | |
491 | memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets)); | |
492 | memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats)); | |
493 | memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets)); | |
8e9dca53 | 494 | if (vsi->rx_rings && vsi->rx_rings[0]) { |
41c445ff | 495 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
6995b36c | 496 | memset(&vsi->rx_rings[i]->stats, 0, |
9f65e15b | 497 | sizeof(vsi->rx_rings[i]->stats)); |
6995b36c | 498 | memset(&vsi->rx_rings[i]->rx_stats, 0, |
9f65e15b | 499 | sizeof(vsi->rx_rings[i]->rx_stats)); |
6995b36c | 500 | memset(&vsi->tx_rings[i]->stats, 0, |
9f65e15b AD |
501 | sizeof(vsi->tx_rings[i]->stats)); |
502 | memset(&vsi->tx_rings[i]->tx_stats, 0, | |
503 | sizeof(vsi->tx_rings[i]->tx_stats)); | |
41c445ff | 504 | } |
8e9dca53 | 505 | } |
41c445ff JB |
506 | vsi->stat_offsets_loaded = false; |
507 | } | |
508 | ||
509 | /** | |
b40c82e6 | 510 | * i40e_pf_reset_stats - Reset all of the stats for the given PF |
41c445ff JB |
511 | * @pf: the PF to be reset |
512 | **/ | |
513 | void i40e_pf_reset_stats(struct i40e_pf *pf) | |
514 | { | |
e91fdf76 SN |
515 | int i; |
516 | ||
41c445ff JB |
517 | memset(&pf->stats, 0, sizeof(pf->stats)); |
518 | memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets)); | |
519 | pf->stat_offsets_loaded = false; | |
e91fdf76 SN |
520 | |
521 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
522 | if (pf->veb[i]) { | |
523 | memset(&pf->veb[i]->stats, 0, | |
524 | sizeof(pf->veb[i]->stats)); | |
525 | memset(&pf->veb[i]->stats_offsets, 0, | |
526 | sizeof(pf->veb[i]->stats_offsets)); | |
527 | pf->veb[i]->stat_offsets_loaded = false; | |
528 | } | |
529 | } | |
41c445ff JB |
530 | } |
531 | ||
532 | /** | |
533 | * i40e_stat_update48 - read and update a 48 bit stat from the chip | |
534 | * @hw: ptr to the hardware info | |
535 | * @hireg: the high 32 bit reg to read | |
536 | * @loreg: the low 32 bit reg to read | |
537 | * @offset_loaded: has the initial offset been loaded yet | |
538 | * @offset: ptr to current offset value | |
539 | * @stat: ptr to the stat | |
540 | * | |
541 | * Since the device stats are not reset at PFReset, they likely will not | |
542 | * be zeroed when the driver starts. We'll save the first values read | |
543 | * and use them as offsets to be subtracted from the raw values in order | |
544 | * to report stats that count from zero. In the process, we also manage | |
545 | * the potential roll-over. | |
546 | **/ | |
547 | static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, | |
548 | bool offset_loaded, u64 *offset, u64 *stat) | |
549 | { | |
550 | u64 new_data; | |
551 | ||
ab60085e | 552 | if (hw->device_id == I40E_DEV_ID_QEMU) { |
41c445ff JB |
553 | new_data = rd32(hw, loreg); |
554 | new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; | |
555 | } else { | |
556 | new_data = rd64(hw, loreg); | |
557 | } | |
558 | if (!offset_loaded) | |
559 | *offset = new_data; | |
560 | if (likely(new_data >= *offset)) | |
561 | *stat = new_data - *offset; | |
562 | else | |
41a1d04b | 563 | *stat = (new_data + BIT_ULL(48)) - *offset; |
41c445ff JB |
564 | *stat &= 0xFFFFFFFFFFFFULL; |
565 | } | |
566 | ||
567 | /** | |
568 | * i40e_stat_update32 - read and update a 32 bit stat from the chip | |
569 | * @hw: ptr to the hardware info | |
570 | * @reg: the hw reg to read | |
571 | * @offset_loaded: has the initial offset been loaded yet | |
572 | * @offset: ptr to current offset value | |
573 | * @stat: ptr to the stat | |
574 | **/ | |
575 | static void i40e_stat_update32(struct i40e_hw *hw, u32 reg, | |
576 | bool offset_loaded, u64 *offset, u64 *stat) | |
577 | { | |
578 | u32 new_data; | |
579 | ||
580 | new_data = rd32(hw, reg); | |
581 | if (!offset_loaded) | |
582 | *offset = new_data; | |
583 | if (likely(new_data >= *offset)) | |
584 | *stat = (u32)(new_data - *offset); | |
585 | else | |
41a1d04b | 586 | *stat = (u32)((new_data + BIT_ULL(32)) - *offset); |
41c445ff JB |
587 | } |
588 | ||
589 | /** | |
590 | * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters. | |
591 | * @vsi: the VSI to be updated | |
592 | **/ | |
593 | void i40e_update_eth_stats(struct i40e_vsi *vsi) | |
594 | { | |
595 | int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx); | |
596 | struct i40e_pf *pf = vsi->back; | |
597 | struct i40e_hw *hw = &pf->hw; | |
598 | struct i40e_eth_stats *oes; | |
599 | struct i40e_eth_stats *es; /* device's eth stats */ | |
600 | ||
601 | es = &vsi->eth_stats; | |
602 | oes = &vsi->eth_stats_offsets; | |
603 | ||
604 | /* Gather up the stats that the hw collects */ | |
605 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
606 | vsi->stat_offsets_loaded, | |
607 | &oes->tx_errors, &es->tx_errors); | |
608 | i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), | |
609 | vsi->stat_offsets_loaded, | |
610 | &oes->rx_discards, &es->rx_discards); | |
41a9e55c SN |
611 | i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx), |
612 | vsi->stat_offsets_loaded, | |
613 | &oes->rx_unknown_protocol, &es->rx_unknown_protocol); | |
614 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
615 | vsi->stat_offsets_loaded, | |
616 | &oes->tx_errors, &es->tx_errors); | |
41c445ff JB |
617 | |
618 | i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx), | |
619 | I40E_GLV_GORCL(stat_idx), | |
620 | vsi->stat_offsets_loaded, | |
621 | &oes->rx_bytes, &es->rx_bytes); | |
622 | i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), | |
623 | I40E_GLV_UPRCL(stat_idx), | |
624 | vsi->stat_offsets_loaded, | |
625 | &oes->rx_unicast, &es->rx_unicast); | |
626 | i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), | |
627 | I40E_GLV_MPRCL(stat_idx), | |
628 | vsi->stat_offsets_loaded, | |
629 | &oes->rx_multicast, &es->rx_multicast); | |
630 | i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), | |
631 | I40E_GLV_BPRCL(stat_idx), | |
632 | vsi->stat_offsets_loaded, | |
633 | &oes->rx_broadcast, &es->rx_broadcast); | |
634 | ||
635 | i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), | |
636 | I40E_GLV_GOTCL(stat_idx), | |
637 | vsi->stat_offsets_loaded, | |
638 | &oes->tx_bytes, &es->tx_bytes); | |
639 | i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), | |
640 | I40E_GLV_UPTCL(stat_idx), | |
641 | vsi->stat_offsets_loaded, | |
642 | &oes->tx_unicast, &es->tx_unicast); | |
643 | i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), | |
644 | I40E_GLV_MPTCL(stat_idx), | |
645 | vsi->stat_offsets_loaded, | |
646 | &oes->tx_multicast, &es->tx_multicast); | |
647 | i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), | |
648 | I40E_GLV_BPTCL(stat_idx), | |
649 | vsi->stat_offsets_loaded, | |
650 | &oes->tx_broadcast, &es->tx_broadcast); | |
651 | vsi->stat_offsets_loaded = true; | |
652 | } | |
653 | ||
654 | /** | |
655 | * i40e_update_veb_stats - Update Switch component statistics | |
656 | * @veb: the VEB being updated | |
657 | **/ | |
658 | static void i40e_update_veb_stats(struct i40e_veb *veb) | |
659 | { | |
660 | struct i40e_pf *pf = veb->pf; | |
661 | struct i40e_hw *hw = &pf->hw; | |
662 | struct i40e_eth_stats *oes; | |
663 | struct i40e_eth_stats *es; /* device's eth stats */ | |
fe860afb NP |
664 | struct i40e_veb_tc_stats *veb_oes; |
665 | struct i40e_veb_tc_stats *veb_es; | |
666 | int i, idx = 0; | |
41c445ff JB |
667 | |
668 | idx = veb->stats_idx; | |
669 | es = &veb->stats; | |
670 | oes = &veb->stats_offsets; | |
fe860afb NP |
671 | veb_es = &veb->tc_stats; |
672 | veb_oes = &veb->tc_stats_offsets; | |
41c445ff JB |
673 | |
674 | /* Gather up the stats that the hw collects */ | |
675 | i40e_stat_update32(hw, I40E_GLSW_TDPC(idx), | |
676 | veb->stat_offsets_loaded, | |
677 | &oes->tx_discards, &es->tx_discards); | |
7134f9ce JB |
678 | if (hw->revision_id > 0) |
679 | i40e_stat_update32(hw, I40E_GLSW_RUPP(idx), | |
680 | veb->stat_offsets_loaded, | |
681 | &oes->rx_unknown_protocol, | |
682 | &es->rx_unknown_protocol); | |
41c445ff JB |
683 | i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx), |
684 | veb->stat_offsets_loaded, | |
685 | &oes->rx_bytes, &es->rx_bytes); | |
686 | i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx), | |
687 | veb->stat_offsets_loaded, | |
688 | &oes->rx_unicast, &es->rx_unicast); | |
689 | i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx), | |
690 | veb->stat_offsets_loaded, | |
691 | &oes->rx_multicast, &es->rx_multicast); | |
692 | i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx), | |
693 | veb->stat_offsets_loaded, | |
694 | &oes->rx_broadcast, &es->rx_broadcast); | |
695 | ||
696 | i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx), | |
697 | veb->stat_offsets_loaded, | |
698 | &oes->tx_bytes, &es->tx_bytes); | |
699 | i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx), | |
700 | veb->stat_offsets_loaded, | |
701 | &oes->tx_unicast, &es->tx_unicast); | |
702 | i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx), | |
703 | veb->stat_offsets_loaded, | |
704 | &oes->tx_multicast, &es->tx_multicast); | |
705 | i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx), | |
706 | veb->stat_offsets_loaded, | |
707 | &oes->tx_broadcast, &es->tx_broadcast); | |
fe860afb NP |
708 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
709 | i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx), | |
710 | I40E_GLVEBTC_RPCL(i, idx), | |
711 | veb->stat_offsets_loaded, | |
712 | &veb_oes->tc_rx_packets[i], | |
713 | &veb_es->tc_rx_packets[i]); | |
714 | i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx), | |
715 | I40E_GLVEBTC_RBCL(i, idx), | |
716 | veb->stat_offsets_loaded, | |
717 | &veb_oes->tc_rx_bytes[i], | |
718 | &veb_es->tc_rx_bytes[i]); | |
719 | i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx), | |
720 | I40E_GLVEBTC_TPCL(i, idx), | |
721 | veb->stat_offsets_loaded, | |
722 | &veb_oes->tc_tx_packets[i], | |
723 | &veb_es->tc_tx_packets[i]); | |
724 | i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx), | |
725 | I40E_GLVEBTC_TBCL(i, idx), | |
726 | veb->stat_offsets_loaded, | |
727 | &veb_oes->tc_tx_bytes[i], | |
728 | &veb_es->tc_tx_bytes[i]); | |
729 | } | |
41c445ff JB |
730 | veb->stat_offsets_loaded = true; |
731 | } | |
732 | ||
38e00438 VD |
733 | #ifdef I40E_FCOE |
734 | /** | |
735 | * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters. | |
736 | * @vsi: the VSI that is capable of doing FCoE | |
737 | **/ | |
738 | static void i40e_update_fcoe_stats(struct i40e_vsi *vsi) | |
739 | { | |
740 | struct i40e_pf *pf = vsi->back; | |
741 | struct i40e_hw *hw = &pf->hw; | |
742 | struct i40e_fcoe_stats *ofs; | |
743 | struct i40e_fcoe_stats *fs; /* device's eth stats */ | |
744 | int idx; | |
745 | ||
746 | if (vsi->type != I40E_VSI_FCOE) | |
747 | return; | |
748 | ||
4147e2c5 | 749 | idx = hw->pf_id + I40E_FCOE_PF_STAT_OFFSET; |
38e00438 VD |
750 | fs = &vsi->fcoe_stats; |
751 | ofs = &vsi->fcoe_stats_offsets; | |
752 | ||
753 | i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx), | |
754 | vsi->fcoe_stat_offsets_loaded, | |
755 | &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets); | |
756 | i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx), | |
757 | vsi->fcoe_stat_offsets_loaded, | |
758 | &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords); | |
759 | i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx), | |
760 | vsi->fcoe_stat_offsets_loaded, | |
761 | &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped); | |
762 | i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx), | |
763 | vsi->fcoe_stat_offsets_loaded, | |
764 | &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets); | |
765 | i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx), | |
766 | vsi->fcoe_stat_offsets_loaded, | |
767 | &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords); | |
768 | i40e_stat_update32(hw, I40E_GL_FCOECRC(idx), | |
769 | vsi->fcoe_stat_offsets_loaded, | |
770 | &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc); | |
771 | i40e_stat_update32(hw, I40E_GL_FCOELAST(idx), | |
772 | vsi->fcoe_stat_offsets_loaded, | |
773 | &ofs->fcoe_last_error, &fs->fcoe_last_error); | |
774 | i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx), | |
775 | vsi->fcoe_stat_offsets_loaded, | |
776 | &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count); | |
777 | ||
778 | vsi->fcoe_stat_offsets_loaded = true; | |
779 | } | |
780 | ||
781 | #endif | |
41c445ff | 782 | /** |
7812fddc | 783 | * i40e_update_vsi_stats - Update the vsi statistics counters. |
41c445ff JB |
784 | * @vsi: the VSI to be updated |
785 | * | |
786 | * There are a few instances where we store the same stat in a | |
787 | * couple of different structs. This is partly because we have | |
788 | * the netdev stats that need to be filled out, which is slightly | |
789 | * different from the "eth_stats" defined by the chip and used in | |
7812fddc | 790 | * VF communications. We sort it out here. |
41c445ff | 791 | **/ |
7812fddc | 792 | static void i40e_update_vsi_stats(struct i40e_vsi *vsi) |
41c445ff JB |
793 | { |
794 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
795 | struct rtnl_link_stats64 *ons; |
796 | struct rtnl_link_stats64 *ns; /* netdev stats */ | |
797 | struct i40e_eth_stats *oes; | |
798 | struct i40e_eth_stats *es; /* device's eth stats */ | |
799 | u32 tx_restart, tx_busy; | |
dd353109 | 800 | u64 tx_lost_interrupt; |
bf00b376 | 801 | struct i40e_ring *p; |
41c445ff | 802 | u32 rx_page, rx_buf; |
bf00b376 AA |
803 | u64 bytes, packets; |
804 | unsigned int start; | |
2fc3d715 | 805 | u64 tx_linearize; |
164c9f54 | 806 | u64 tx_force_wb; |
41c445ff JB |
807 | u64 rx_p, rx_b; |
808 | u64 tx_p, tx_b; | |
41c445ff JB |
809 | u16 q; |
810 | ||
811 | if (test_bit(__I40E_DOWN, &vsi->state) || | |
812 | test_bit(__I40E_CONFIG_BUSY, &pf->state)) | |
813 | return; | |
814 | ||
815 | ns = i40e_get_vsi_stats_struct(vsi); | |
816 | ons = &vsi->net_stats_offsets; | |
817 | es = &vsi->eth_stats; | |
818 | oes = &vsi->eth_stats_offsets; | |
819 | ||
820 | /* Gather up the netdev and vsi stats that the driver collects | |
821 | * on the fly during packet processing | |
822 | */ | |
823 | rx_b = rx_p = 0; | |
824 | tx_b = tx_p = 0; | |
164c9f54 | 825 | tx_restart = tx_busy = tx_linearize = tx_force_wb = 0; |
dd353109 | 826 | tx_lost_interrupt = 0; |
41c445ff JB |
827 | rx_page = 0; |
828 | rx_buf = 0; | |
980e9b11 | 829 | rcu_read_lock(); |
41c445ff | 830 | for (q = 0; q < vsi->num_queue_pairs; q++) { |
980e9b11 AD |
831 | /* locate Tx ring */ |
832 | p = ACCESS_ONCE(vsi->tx_rings[q]); | |
833 | ||
834 | do { | |
57a7744e | 835 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
836 | packets = p->stats.packets; |
837 | bytes = p->stats.bytes; | |
57a7744e | 838 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
839 | tx_b += bytes; |
840 | tx_p += packets; | |
841 | tx_restart += p->tx_stats.restart_queue; | |
842 | tx_busy += p->tx_stats.tx_busy; | |
2fc3d715 | 843 | tx_linearize += p->tx_stats.tx_linearize; |
164c9f54 | 844 | tx_force_wb += p->tx_stats.tx_force_wb; |
dd353109 | 845 | tx_lost_interrupt += p->tx_stats.tx_lost_interrupt; |
41c445ff | 846 | |
980e9b11 AD |
847 | /* Rx queue is part of the same block as Tx queue */ |
848 | p = &p[1]; | |
849 | do { | |
57a7744e | 850 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
851 | packets = p->stats.packets; |
852 | bytes = p->stats.bytes; | |
57a7744e | 853 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
854 | rx_b += bytes; |
855 | rx_p += packets; | |
420136cc MW |
856 | rx_buf += p->rx_stats.alloc_buff_failed; |
857 | rx_page += p->rx_stats.alloc_page_failed; | |
41c445ff | 858 | } |
980e9b11 | 859 | rcu_read_unlock(); |
41c445ff JB |
860 | vsi->tx_restart = tx_restart; |
861 | vsi->tx_busy = tx_busy; | |
2fc3d715 | 862 | vsi->tx_linearize = tx_linearize; |
164c9f54 | 863 | vsi->tx_force_wb = tx_force_wb; |
dd353109 | 864 | vsi->tx_lost_interrupt = tx_lost_interrupt; |
41c445ff JB |
865 | vsi->rx_page_failed = rx_page; |
866 | vsi->rx_buf_failed = rx_buf; | |
867 | ||
868 | ns->rx_packets = rx_p; | |
869 | ns->rx_bytes = rx_b; | |
870 | ns->tx_packets = tx_p; | |
871 | ns->tx_bytes = tx_b; | |
872 | ||
41c445ff | 873 | /* update netdev stats from eth stats */ |
7812fddc | 874 | i40e_update_eth_stats(vsi); |
41c445ff JB |
875 | ons->tx_errors = oes->tx_errors; |
876 | ns->tx_errors = es->tx_errors; | |
877 | ons->multicast = oes->rx_multicast; | |
878 | ns->multicast = es->rx_multicast; | |
41a9e55c SN |
879 | ons->rx_dropped = oes->rx_discards; |
880 | ns->rx_dropped = es->rx_discards; | |
41c445ff JB |
881 | ons->tx_dropped = oes->tx_discards; |
882 | ns->tx_dropped = es->tx_discards; | |
883 | ||
7812fddc | 884 | /* pull in a couple PF stats if this is the main vsi */ |
41c445ff | 885 | if (vsi == pf->vsi[pf->lan_vsi]) { |
7812fddc SN |
886 | ns->rx_crc_errors = pf->stats.crc_errors; |
887 | ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes; | |
888 | ns->rx_length_errors = pf->stats.rx_length_errors; | |
889 | } | |
890 | } | |
41c445ff | 891 | |
7812fddc | 892 | /** |
b40c82e6 | 893 | * i40e_update_pf_stats - Update the PF statistics counters. |
7812fddc SN |
894 | * @pf: the PF to be updated |
895 | **/ | |
896 | static void i40e_update_pf_stats(struct i40e_pf *pf) | |
897 | { | |
898 | struct i40e_hw_port_stats *osd = &pf->stats_offsets; | |
899 | struct i40e_hw_port_stats *nsd = &pf->stats; | |
900 | struct i40e_hw *hw = &pf->hw; | |
901 | u32 val; | |
902 | int i; | |
41c445ff | 903 | |
7812fddc SN |
904 | i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), |
905 | I40E_GLPRT_GORCL(hw->port), | |
906 | pf->stat_offsets_loaded, | |
907 | &osd->eth.rx_bytes, &nsd->eth.rx_bytes); | |
908 | i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), | |
909 | I40E_GLPRT_GOTCL(hw->port), | |
910 | pf->stat_offsets_loaded, | |
911 | &osd->eth.tx_bytes, &nsd->eth.tx_bytes); | |
912 | i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), | |
913 | pf->stat_offsets_loaded, | |
914 | &osd->eth.rx_discards, | |
915 | &nsd->eth.rx_discards); | |
532d283d SN |
916 | i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), |
917 | I40E_GLPRT_UPRCL(hw->port), | |
918 | pf->stat_offsets_loaded, | |
919 | &osd->eth.rx_unicast, | |
920 | &nsd->eth.rx_unicast); | |
7812fddc SN |
921 | i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), |
922 | I40E_GLPRT_MPRCL(hw->port), | |
923 | pf->stat_offsets_loaded, | |
924 | &osd->eth.rx_multicast, | |
925 | &nsd->eth.rx_multicast); | |
532d283d SN |
926 | i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), |
927 | I40E_GLPRT_BPRCL(hw->port), | |
928 | pf->stat_offsets_loaded, | |
929 | &osd->eth.rx_broadcast, | |
930 | &nsd->eth.rx_broadcast); | |
931 | i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), | |
932 | I40E_GLPRT_UPTCL(hw->port), | |
933 | pf->stat_offsets_loaded, | |
934 | &osd->eth.tx_unicast, | |
935 | &nsd->eth.tx_unicast); | |
936 | i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), | |
937 | I40E_GLPRT_MPTCL(hw->port), | |
938 | pf->stat_offsets_loaded, | |
939 | &osd->eth.tx_multicast, | |
940 | &nsd->eth.tx_multicast); | |
941 | i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), | |
942 | I40E_GLPRT_BPTCL(hw->port), | |
943 | pf->stat_offsets_loaded, | |
944 | &osd->eth.tx_broadcast, | |
945 | &nsd->eth.tx_broadcast); | |
41c445ff | 946 | |
7812fddc SN |
947 | i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), |
948 | pf->stat_offsets_loaded, | |
949 | &osd->tx_dropped_link_down, | |
950 | &nsd->tx_dropped_link_down); | |
41c445ff | 951 | |
7812fddc SN |
952 | i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), |
953 | pf->stat_offsets_loaded, | |
954 | &osd->crc_errors, &nsd->crc_errors); | |
41c445ff | 955 | |
7812fddc SN |
956 | i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), |
957 | pf->stat_offsets_loaded, | |
958 | &osd->illegal_bytes, &nsd->illegal_bytes); | |
41c445ff | 959 | |
7812fddc SN |
960 | i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), |
961 | pf->stat_offsets_loaded, | |
962 | &osd->mac_local_faults, | |
963 | &nsd->mac_local_faults); | |
964 | i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), | |
965 | pf->stat_offsets_loaded, | |
966 | &osd->mac_remote_faults, | |
967 | &nsd->mac_remote_faults); | |
41c445ff | 968 | |
7812fddc SN |
969 | i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), |
970 | pf->stat_offsets_loaded, | |
971 | &osd->rx_length_errors, | |
972 | &nsd->rx_length_errors); | |
41c445ff | 973 | |
7812fddc SN |
974 | i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), |
975 | pf->stat_offsets_loaded, | |
976 | &osd->link_xon_rx, &nsd->link_xon_rx); | |
977 | i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), | |
978 | pf->stat_offsets_loaded, | |
979 | &osd->link_xon_tx, &nsd->link_xon_tx); | |
95db239f NP |
980 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), |
981 | pf->stat_offsets_loaded, | |
982 | &osd->link_xoff_rx, &nsd->link_xoff_rx); | |
7812fddc SN |
983 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), |
984 | pf->stat_offsets_loaded, | |
985 | &osd->link_xoff_tx, &nsd->link_xoff_tx); | |
41c445ff | 986 | |
7812fddc | 987 | for (i = 0; i < 8; i++) { |
95db239f NP |
988 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), |
989 | pf->stat_offsets_loaded, | |
990 | &osd->priority_xoff_rx[i], | |
991 | &nsd->priority_xoff_rx[i]); | |
7812fddc | 992 | i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i), |
41c445ff | 993 | pf->stat_offsets_loaded, |
7812fddc SN |
994 | &osd->priority_xon_rx[i], |
995 | &nsd->priority_xon_rx[i]); | |
996 | i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i), | |
41c445ff | 997 | pf->stat_offsets_loaded, |
7812fddc SN |
998 | &osd->priority_xon_tx[i], |
999 | &nsd->priority_xon_tx[i]); | |
1000 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), | |
41c445ff | 1001 | pf->stat_offsets_loaded, |
7812fddc SN |
1002 | &osd->priority_xoff_tx[i], |
1003 | &nsd->priority_xoff_tx[i]); | |
1004 | i40e_stat_update32(hw, | |
1005 | I40E_GLPRT_RXON2OFFCNT(hw->port, i), | |
bee5af7e | 1006 | pf->stat_offsets_loaded, |
7812fddc SN |
1007 | &osd->priority_xon_2_xoff[i], |
1008 | &nsd->priority_xon_2_xoff[i]); | |
41c445ff JB |
1009 | } |
1010 | ||
7812fddc SN |
1011 | i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), |
1012 | I40E_GLPRT_PRC64L(hw->port), | |
1013 | pf->stat_offsets_loaded, | |
1014 | &osd->rx_size_64, &nsd->rx_size_64); | |
1015 | i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), | |
1016 | I40E_GLPRT_PRC127L(hw->port), | |
1017 | pf->stat_offsets_loaded, | |
1018 | &osd->rx_size_127, &nsd->rx_size_127); | |
1019 | i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), | |
1020 | I40E_GLPRT_PRC255L(hw->port), | |
1021 | pf->stat_offsets_loaded, | |
1022 | &osd->rx_size_255, &nsd->rx_size_255); | |
1023 | i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), | |
1024 | I40E_GLPRT_PRC511L(hw->port), | |
1025 | pf->stat_offsets_loaded, | |
1026 | &osd->rx_size_511, &nsd->rx_size_511); | |
1027 | i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), | |
1028 | I40E_GLPRT_PRC1023L(hw->port), | |
1029 | pf->stat_offsets_loaded, | |
1030 | &osd->rx_size_1023, &nsd->rx_size_1023); | |
1031 | i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), | |
1032 | I40E_GLPRT_PRC1522L(hw->port), | |
1033 | pf->stat_offsets_loaded, | |
1034 | &osd->rx_size_1522, &nsd->rx_size_1522); | |
1035 | i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), | |
1036 | I40E_GLPRT_PRC9522L(hw->port), | |
1037 | pf->stat_offsets_loaded, | |
1038 | &osd->rx_size_big, &nsd->rx_size_big); | |
1039 | ||
1040 | i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), | |
1041 | I40E_GLPRT_PTC64L(hw->port), | |
1042 | pf->stat_offsets_loaded, | |
1043 | &osd->tx_size_64, &nsd->tx_size_64); | |
1044 | i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), | |
1045 | I40E_GLPRT_PTC127L(hw->port), | |
1046 | pf->stat_offsets_loaded, | |
1047 | &osd->tx_size_127, &nsd->tx_size_127); | |
1048 | i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), | |
1049 | I40E_GLPRT_PTC255L(hw->port), | |
1050 | pf->stat_offsets_loaded, | |
1051 | &osd->tx_size_255, &nsd->tx_size_255); | |
1052 | i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), | |
1053 | I40E_GLPRT_PTC511L(hw->port), | |
1054 | pf->stat_offsets_loaded, | |
1055 | &osd->tx_size_511, &nsd->tx_size_511); | |
1056 | i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), | |
1057 | I40E_GLPRT_PTC1023L(hw->port), | |
1058 | pf->stat_offsets_loaded, | |
1059 | &osd->tx_size_1023, &nsd->tx_size_1023); | |
1060 | i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), | |
1061 | I40E_GLPRT_PTC1522L(hw->port), | |
1062 | pf->stat_offsets_loaded, | |
1063 | &osd->tx_size_1522, &nsd->tx_size_1522); | |
1064 | i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), | |
1065 | I40E_GLPRT_PTC9522L(hw->port), | |
1066 | pf->stat_offsets_loaded, | |
1067 | &osd->tx_size_big, &nsd->tx_size_big); | |
1068 | ||
1069 | i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port), | |
1070 | pf->stat_offsets_loaded, | |
1071 | &osd->rx_undersize, &nsd->rx_undersize); | |
1072 | i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port), | |
1073 | pf->stat_offsets_loaded, | |
1074 | &osd->rx_fragments, &nsd->rx_fragments); | |
1075 | i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port), | |
1076 | pf->stat_offsets_loaded, | |
1077 | &osd->rx_oversize, &nsd->rx_oversize); | |
1078 | i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port), | |
1079 | pf->stat_offsets_loaded, | |
1080 | &osd->rx_jabber, &nsd->rx_jabber); | |
1081 | ||
433c47de | 1082 | /* FDIR stats */ |
0bf4b1b0 ASJ |
1083 | i40e_stat_update32(hw, |
1084 | I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)), | |
433c47de ASJ |
1085 | pf->stat_offsets_loaded, |
1086 | &osd->fd_atr_match, &nsd->fd_atr_match); | |
0bf4b1b0 ASJ |
1087 | i40e_stat_update32(hw, |
1088 | I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)), | |
433c47de ASJ |
1089 | pf->stat_offsets_loaded, |
1090 | &osd->fd_sb_match, &nsd->fd_sb_match); | |
60ccd45c ASJ |
1091 | i40e_stat_update32(hw, |
1092 | I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)), | |
1093 | pf->stat_offsets_loaded, | |
1094 | &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match); | |
433c47de | 1095 | |
7812fddc SN |
1096 | val = rd32(hw, I40E_PRTPM_EEE_STAT); |
1097 | nsd->tx_lpi_status = | |
1098 | (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> | |
1099 | I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; | |
1100 | nsd->rx_lpi_status = | |
1101 | (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> | |
1102 | I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; | |
1103 | i40e_stat_update32(hw, I40E_PRTPM_TLPIC, | |
1104 | pf->stat_offsets_loaded, | |
1105 | &osd->tx_lpi_count, &nsd->tx_lpi_count); | |
1106 | i40e_stat_update32(hw, I40E_PRTPM_RLPIC, | |
1107 | pf->stat_offsets_loaded, | |
1108 | &osd->rx_lpi_count, &nsd->rx_lpi_count); | |
1109 | ||
d0389e51 ASJ |
1110 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED && |
1111 | !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) | |
1112 | nsd->fd_sb_status = true; | |
1113 | else | |
1114 | nsd->fd_sb_status = false; | |
1115 | ||
1116 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED && | |
1117 | !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) | |
1118 | nsd->fd_atr_status = true; | |
1119 | else | |
1120 | nsd->fd_atr_status = false; | |
1121 | ||
41c445ff JB |
1122 | pf->stat_offsets_loaded = true; |
1123 | } | |
1124 | ||
7812fddc SN |
1125 | /** |
1126 | * i40e_update_stats - Update the various statistics counters. | |
1127 | * @vsi: the VSI to be updated | |
1128 | * | |
1129 | * Update the various stats for this VSI and its related entities. | |
1130 | **/ | |
1131 | void i40e_update_stats(struct i40e_vsi *vsi) | |
1132 | { | |
1133 | struct i40e_pf *pf = vsi->back; | |
1134 | ||
1135 | if (vsi == pf->vsi[pf->lan_vsi]) | |
1136 | i40e_update_pf_stats(pf); | |
1137 | ||
1138 | i40e_update_vsi_stats(vsi); | |
38e00438 VD |
1139 | #ifdef I40E_FCOE |
1140 | i40e_update_fcoe_stats(vsi); | |
1141 | #endif | |
7812fddc SN |
1142 | } |
1143 | ||
41c445ff JB |
1144 | /** |
1145 | * i40e_find_filter - Search VSI filter list for specific mac/vlan filter | |
1146 | * @vsi: the VSI to be searched | |
1147 | * @macaddr: the MAC address | |
1148 | * @vlan: the vlan | |
b40c82e6 | 1149 | * @is_vf: make sure its a VF filter, else doesn't matter |
41c445ff JB |
1150 | * @is_netdev: make sure its a netdev filter, else doesn't matter |
1151 | * | |
1152 | * Returns ptr to the filter object or NULL | |
1153 | **/ | |
1154 | static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi, | |
1155 | u8 *macaddr, s16 vlan, | |
1156 | bool is_vf, bool is_netdev) | |
1157 | { | |
1158 | struct i40e_mac_filter *f; | |
1159 | ||
1160 | if (!vsi || !macaddr) | |
1161 | return NULL; | |
1162 | ||
1163 | list_for_each_entry(f, &vsi->mac_filter_list, list) { | |
1164 | if ((ether_addr_equal(macaddr, f->macaddr)) && | |
1165 | (vlan == f->vlan) && | |
1166 | (!is_vf || f->is_vf) && | |
1167 | (!is_netdev || f->is_netdev)) | |
1168 | return f; | |
1169 | } | |
1170 | return NULL; | |
1171 | } | |
1172 | ||
1173 | /** | |
1174 | * i40e_find_mac - Find a mac addr in the macvlan filters list | |
1175 | * @vsi: the VSI to be searched | |
1176 | * @macaddr: the MAC address we are searching for | |
b40c82e6 | 1177 | * @is_vf: make sure its a VF filter, else doesn't matter |
41c445ff JB |
1178 | * @is_netdev: make sure its a netdev filter, else doesn't matter |
1179 | * | |
1180 | * Returns the first filter with the provided MAC address or NULL if | |
1181 | * MAC address was not found | |
1182 | **/ | |
1183 | struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr, | |
1184 | bool is_vf, bool is_netdev) | |
1185 | { | |
1186 | struct i40e_mac_filter *f; | |
1187 | ||
1188 | if (!vsi || !macaddr) | |
1189 | return NULL; | |
1190 | ||
1191 | list_for_each_entry(f, &vsi->mac_filter_list, list) { | |
1192 | if ((ether_addr_equal(macaddr, f->macaddr)) && | |
1193 | (!is_vf || f->is_vf) && | |
1194 | (!is_netdev || f->is_netdev)) | |
1195 | return f; | |
1196 | } | |
1197 | return NULL; | |
1198 | } | |
1199 | ||
1200 | /** | |
1201 | * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode | |
1202 | * @vsi: the VSI to be searched | |
1203 | * | |
1204 | * Returns true if VSI is in vlan mode or false otherwise | |
1205 | **/ | |
1206 | bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi) | |
1207 | { | |
1208 | struct i40e_mac_filter *f; | |
1209 | ||
1210 | /* Only -1 for all the filters denotes not in vlan mode | |
1211 | * so we have to go through all the list in order to make sure | |
1212 | */ | |
1213 | list_for_each_entry(f, &vsi->mac_filter_list, list) { | |
d9b68f8a | 1214 | if (f->vlan >= 0 || vsi->info.pvid) |
41c445ff JB |
1215 | return true; |
1216 | } | |
1217 | ||
1218 | return false; | |
1219 | } | |
1220 | ||
1221 | /** | |
1222 | * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans | |
1223 | * @vsi: the VSI to be searched | |
1224 | * @macaddr: the mac address to be filtered | |
b40c82e6 | 1225 | * @is_vf: true if it is a VF |
41c445ff JB |
1226 | * @is_netdev: true if it is a netdev |
1227 | * | |
1228 | * Goes through all the macvlan filters and adds a | |
1229 | * macvlan filter for each unique vlan that already exists | |
1230 | * | |
1231 | * Returns first filter found on success, else NULL | |
1232 | **/ | |
1233 | struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr, | |
1234 | bool is_vf, bool is_netdev) | |
1235 | { | |
1236 | struct i40e_mac_filter *f; | |
1237 | ||
1238 | list_for_each_entry(f, &vsi->mac_filter_list, list) { | |
ecbb44e8 MW |
1239 | if (vsi->info.pvid) |
1240 | f->vlan = le16_to_cpu(vsi->info.pvid); | |
41c445ff JB |
1241 | if (!i40e_find_filter(vsi, macaddr, f->vlan, |
1242 | is_vf, is_netdev)) { | |
1243 | if (!i40e_add_filter(vsi, macaddr, f->vlan, | |
8fb905b3 | 1244 | is_vf, is_netdev)) |
41c445ff JB |
1245 | return NULL; |
1246 | } | |
1247 | } | |
1248 | ||
1249 | return list_first_entry_or_null(&vsi->mac_filter_list, | |
1250 | struct i40e_mac_filter, list); | |
1251 | } | |
1252 | ||
b36e9ab5 MW |
1253 | /** |
1254 | * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS | |
1255 | * @vsi: the VSI to be searched | |
1256 | * @macaddr: the mac address to be removed | |
1257 | * @is_vf: true if it is a VF | |
1258 | * @is_netdev: true if it is a netdev | |
1259 | * | |
1260 | * Removes a given MAC address from a VSI, regardless of VLAN | |
1261 | * | |
1262 | * Returns 0 for success, or error | |
1263 | **/ | |
1264 | int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr, | |
1265 | bool is_vf, bool is_netdev) | |
1266 | { | |
1267 | struct i40e_mac_filter *f = NULL; | |
1268 | int changed = 0; | |
1269 | ||
1270 | WARN(!spin_is_locked(&vsi->mac_filter_list_lock), | |
1271 | "Missing mac_filter_list_lock\n"); | |
1272 | list_for_each_entry(f, &vsi->mac_filter_list, list) { | |
1273 | if ((ether_addr_equal(macaddr, f->macaddr)) && | |
1274 | (is_vf == f->is_vf) && | |
1275 | (is_netdev == f->is_netdev)) { | |
1276 | f->counter--; | |
b36e9ab5 | 1277 | changed = 1; |
c3c7ea27 MW |
1278 | if (f->counter == 0) |
1279 | f->state = I40E_FILTER_REMOVE; | |
b36e9ab5 MW |
1280 | } |
1281 | } | |
1282 | if (changed) { | |
1283 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
1284 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1285 | return 0; | |
1286 | } | |
1287 | return -ENOENT; | |
1288 | } | |
1289 | ||
8c27d42e GR |
1290 | /** |
1291 | * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM | |
1292 | * @vsi: the PF Main VSI - inappropriate for any other VSI | |
1293 | * @macaddr: the MAC address | |
30650cc5 | 1294 | * |
c3c7ea27 MW |
1295 | * Remove whatever filter the firmware set up so the driver can manage |
1296 | * its own filtering intelligently. | |
8c27d42e | 1297 | **/ |
c3c7ea27 | 1298 | static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr) |
8c27d42e GR |
1299 | { |
1300 | struct i40e_aqc_remove_macvlan_element_data element; | |
1301 | struct i40e_pf *pf = vsi->back; | |
8c27d42e GR |
1302 | |
1303 | /* Only appropriate for the PF main VSI */ | |
1304 | if (vsi->type != I40E_VSI_MAIN) | |
c3c7ea27 | 1305 | return; |
8c27d42e | 1306 | |
30650cc5 | 1307 | memset(&element, 0, sizeof(element)); |
8c27d42e GR |
1308 | ether_addr_copy(element.mac_addr, macaddr); |
1309 | element.vlan_tag = 0; | |
c3c7ea27 MW |
1310 | /* Ignore error returns, some firmware does it this way... */ |
1311 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; | |
1312 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
30650cc5 | 1313 | |
c3c7ea27 MW |
1314 | memset(&element, 0, sizeof(element)); |
1315 | ether_addr_copy(element.mac_addr, macaddr); | |
1316 | element.vlan_tag = 0; | |
1317 | /* ...and some firmware does it this way. */ | |
1318 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | | |
1319 | I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; | |
1320 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
8c27d42e GR |
1321 | } |
1322 | ||
41c445ff JB |
1323 | /** |
1324 | * i40e_add_filter - Add a mac/vlan filter to the VSI | |
1325 | * @vsi: the VSI to be searched | |
1326 | * @macaddr: the MAC address | |
1327 | * @vlan: the vlan | |
b40c82e6 | 1328 | * @is_vf: make sure its a VF filter, else doesn't matter |
41c445ff JB |
1329 | * @is_netdev: make sure its a netdev filter, else doesn't matter |
1330 | * | |
1331 | * Returns ptr to the filter object or NULL when no memory available. | |
21659035 KP |
1332 | * |
1333 | * NOTE: This function is expected to be called with mac_filter_list_lock | |
1334 | * being held. | |
41c445ff JB |
1335 | **/ |
1336 | struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, | |
1337 | u8 *macaddr, s16 vlan, | |
1338 | bool is_vf, bool is_netdev) | |
1339 | { | |
1340 | struct i40e_mac_filter *f; | |
c3c7ea27 | 1341 | int changed = false; |
41c445ff JB |
1342 | |
1343 | if (!vsi || !macaddr) | |
1344 | return NULL; | |
1345 | ||
1346 | f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev); | |
1347 | if (!f) { | |
1348 | f = kzalloc(sizeof(*f), GFP_ATOMIC); | |
1349 | if (!f) | |
1350 | goto add_filter_out; | |
1351 | ||
9a173901 | 1352 | ether_addr_copy(f->macaddr, macaddr); |
41c445ff | 1353 | f->vlan = vlan; |
c3c7ea27 MW |
1354 | /* If we're in overflow promisc mode, set the state directly |
1355 | * to failed, so we don't bother to try sending the filter | |
1356 | * to the hardware. | |
1357 | */ | |
1358 | if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state)) | |
1359 | f->state = I40E_FILTER_FAILED; | |
1360 | else | |
1361 | f->state = I40E_FILTER_NEW; | |
1362 | changed = true; | |
41c445ff | 1363 | INIT_LIST_HEAD(&f->list); |
04d5a21d | 1364 | list_add_tail(&f->list, &vsi->mac_filter_list); |
41c445ff JB |
1365 | } |
1366 | ||
1367 | /* increment counter and add a new flag if needed */ | |
1368 | if (is_vf) { | |
1369 | if (!f->is_vf) { | |
1370 | f->is_vf = true; | |
1371 | f->counter++; | |
1372 | } | |
1373 | } else if (is_netdev) { | |
1374 | if (!f->is_netdev) { | |
1375 | f->is_netdev = true; | |
1376 | f->counter++; | |
1377 | } | |
1378 | } else { | |
1379 | f->counter++; | |
1380 | } | |
1381 | ||
c3c7ea27 | 1382 | if (changed) { |
41c445ff JB |
1383 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; |
1384 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1385 | } | |
1386 | ||
1387 | add_filter_out: | |
1388 | return f; | |
1389 | } | |
1390 | ||
1391 | /** | |
1392 | * i40e_del_filter - Remove a mac/vlan filter from the VSI | |
1393 | * @vsi: the VSI to be searched | |
1394 | * @macaddr: the MAC address | |
1395 | * @vlan: the vlan | |
b40c82e6 | 1396 | * @is_vf: make sure it's a VF filter, else doesn't matter |
41c445ff | 1397 | * @is_netdev: make sure it's a netdev filter, else doesn't matter |
21659035 KP |
1398 | * |
1399 | * NOTE: This function is expected to be called with mac_filter_list_lock | |
1400 | * being held. | |
c3c7ea27 MW |
1401 | * ANOTHER NOTE: This function MUST be called from within the context of |
1402 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1403 | * instead of list_for_each_entry(). | |
41c445ff JB |
1404 | **/ |
1405 | void i40e_del_filter(struct i40e_vsi *vsi, | |
1406 | u8 *macaddr, s16 vlan, | |
1407 | bool is_vf, bool is_netdev) | |
1408 | { | |
1409 | struct i40e_mac_filter *f; | |
1410 | ||
1411 | if (!vsi || !macaddr) | |
1412 | return; | |
1413 | ||
1414 | f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev); | |
1415 | if (!f || f->counter == 0) | |
1416 | return; | |
1417 | ||
1418 | if (is_vf) { | |
1419 | if (f->is_vf) { | |
1420 | f->is_vf = false; | |
1421 | f->counter--; | |
1422 | } | |
1423 | } else if (is_netdev) { | |
1424 | if (f->is_netdev) { | |
1425 | f->is_netdev = false; | |
1426 | f->counter--; | |
1427 | } | |
1428 | } else { | |
b40c82e6 | 1429 | /* make sure we don't remove a filter in use by VF or netdev */ |
41c445ff | 1430 | int min_f = 0; |
6995b36c | 1431 | |
41c445ff JB |
1432 | min_f += (f->is_vf ? 1 : 0); |
1433 | min_f += (f->is_netdev ? 1 : 0); | |
1434 | ||
1435 | if (f->counter > min_f) | |
1436 | f->counter--; | |
1437 | } | |
1438 | ||
1439 | /* counter == 0 tells sync_filters_subtask to | |
1440 | * remove the filter from the firmware's list | |
1441 | */ | |
1442 | if (f->counter == 0) { | |
c3c7ea27 MW |
1443 | if ((f->state == I40E_FILTER_FAILED) || |
1444 | (f->state == I40E_FILTER_NEW)) { | |
1445 | /* this one never got added by the FW. Just remove it, | |
1446 | * no need to sync anything. | |
1447 | */ | |
1448 | list_del(&f->list); | |
1449 | kfree(f); | |
1450 | } else { | |
1451 | f->state = I40E_FILTER_REMOVE; | |
1452 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
1453 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1454 | } | |
41c445ff JB |
1455 | } |
1456 | } | |
1457 | ||
1458 | /** | |
1459 | * i40e_set_mac - NDO callback to set mac address | |
1460 | * @netdev: network interface device structure | |
1461 | * @p: pointer to an address structure | |
1462 | * | |
1463 | * Returns 0 on success, negative on failure | |
1464 | **/ | |
38e00438 VD |
1465 | #ifdef I40E_FCOE |
1466 | int i40e_set_mac(struct net_device *netdev, void *p) | |
1467 | #else | |
41c445ff | 1468 | static int i40e_set_mac(struct net_device *netdev, void *p) |
38e00438 | 1469 | #endif |
41c445ff JB |
1470 | { |
1471 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1472 | struct i40e_vsi *vsi = np->vsi; | |
30650cc5 SN |
1473 | struct i40e_pf *pf = vsi->back; |
1474 | struct i40e_hw *hw = &pf->hw; | |
41c445ff | 1475 | struct sockaddr *addr = p; |
41c445ff JB |
1476 | |
1477 | if (!is_valid_ether_addr(addr->sa_data)) | |
1478 | return -EADDRNOTAVAIL; | |
1479 | ||
30650cc5 SN |
1480 | if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) { |
1481 | netdev_info(netdev, "already using mac address %pM\n", | |
1482 | addr->sa_data); | |
1483 | return 0; | |
1484 | } | |
41c445ff | 1485 | |
80f6428f ASJ |
1486 | if (test_bit(__I40E_DOWN, &vsi->back->state) || |
1487 | test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state)) | |
1488 | return -EADDRNOTAVAIL; | |
1489 | ||
30650cc5 SN |
1490 | if (ether_addr_equal(hw->mac.addr, addr->sa_data)) |
1491 | netdev_info(netdev, "returning to hw mac address %pM\n", | |
1492 | hw->mac.addr); | |
1493 | else | |
1494 | netdev_info(netdev, "set new mac address %pM\n", addr->sa_data); | |
1495 | ||
c3c7ea27 MW |
1496 | spin_lock_bh(&vsi->mac_filter_list_lock); |
1497 | i40e_del_mac_all_vlan(vsi, netdev->dev_addr, false, true); | |
1498 | i40e_put_mac_in_vlan(vsi, addr->sa_data, false, true); | |
1499 | spin_unlock_bh(&vsi->mac_filter_list_lock); | |
1500 | ether_addr_copy(netdev->dev_addr, addr->sa_data); | |
41c445ff JB |
1501 | if (vsi->type == I40E_VSI_MAIN) { |
1502 | i40e_status ret; | |
6995b36c | 1503 | |
41c445ff | 1504 | ret = i40e_aq_mac_address_write(&vsi->back->hw, |
cc41222c | 1505 | I40E_AQC_WRITE_TYPE_LAA_WOL, |
41c445ff | 1506 | addr->sa_data, NULL); |
c3c7ea27 MW |
1507 | if (ret) |
1508 | netdev_info(netdev, "Ignoring error from firmware on LAA update, status %s, AQ ret %s\n", | |
1509 | i40e_stat_str(hw, ret), | |
1510 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
30650cc5 SN |
1511 | } |
1512 | ||
c53934c6 JB |
1513 | /* schedule our worker thread which will take care of |
1514 | * applying the new filter changes | |
1515 | */ | |
1516 | i40e_service_event_schedule(vsi->back); | |
1517 | return 0; | |
41c445ff JB |
1518 | } |
1519 | ||
1520 | /** | |
1521 | * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc | |
1522 | * @vsi: the VSI being setup | |
1523 | * @ctxt: VSI context structure | |
1524 | * @enabled_tc: Enabled TCs bitmap | |
1525 | * @is_add: True if called before Add VSI | |
1526 | * | |
1527 | * Setup VSI queue mapping for enabled traffic classes. | |
1528 | **/ | |
38e00438 VD |
1529 | #ifdef I40E_FCOE |
1530 | void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, | |
1531 | struct i40e_vsi_context *ctxt, | |
1532 | u8 enabled_tc, | |
1533 | bool is_add) | |
1534 | #else | |
41c445ff JB |
1535 | static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, |
1536 | struct i40e_vsi_context *ctxt, | |
1537 | u8 enabled_tc, | |
1538 | bool is_add) | |
38e00438 | 1539 | #endif |
41c445ff JB |
1540 | { |
1541 | struct i40e_pf *pf = vsi->back; | |
1542 | u16 sections = 0; | |
1543 | u8 netdev_tc = 0; | |
1544 | u16 numtc = 0; | |
1545 | u16 qcount; | |
1546 | u8 offset; | |
1547 | u16 qmap; | |
1548 | int i; | |
4e3b35b0 | 1549 | u16 num_tc_qps = 0; |
41c445ff JB |
1550 | |
1551 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
1552 | offset = 0; | |
1553 | ||
1554 | if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { | |
1555 | /* Find numtc from enabled TC bitmap */ | |
1556 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 1557 | if (enabled_tc & BIT(i)) /* TC is enabled */ |
41c445ff JB |
1558 | numtc++; |
1559 | } | |
1560 | if (!numtc) { | |
1561 | dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n"); | |
1562 | numtc = 1; | |
1563 | } | |
1564 | } else { | |
1565 | /* At least TC0 is enabled in case of non-DCB case */ | |
1566 | numtc = 1; | |
1567 | } | |
1568 | ||
1569 | vsi->tc_config.numtc = numtc; | |
1570 | vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; | |
4e3b35b0 | 1571 | /* Number of queues per enabled TC */ |
7d64402f CS |
1572 | qcount = vsi->alloc_queue_pairs; |
1573 | ||
7f9ff476 | 1574 | num_tc_qps = qcount / numtc; |
e25d00b8 | 1575 | num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf)); |
41c445ff JB |
1576 | |
1577 | /* Setup queue offset/count for all TCs for given VSI */ | |
1578 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
1579 | /* See if the given TC is enabled for the given VSI */ | |
75f5cea9 | 1580 | if (vsi->tc_config.enabled_tc & BIT(i)) { |
41a1d04b | 1581 | /* TC is enabled */ |
41c445ff JB |
1582 | int pow, num_qps; |
1583 | ||
41c445ff JB |
1584 | switch (vsi->type) { |
1585 | case I40E_VSI_MAIN: | |
acd65448 HZ |
1586 | qcount = min_t(int, pf->alloc_rss_size, |
1587 | num_tc_qps); | |
41c445ff | 1588 | break; |
38e00438 VD |
1589 | #ifdef I40E_FCOE |
1590 | case I40E_VSI_FCOE: | |
1591 | qcount = num_tc_qps; | |
1592 | break; | |
1593 | #endif | |
41c445ff JB |
1594 | case I40E_VSI_FDIR: |
1595 | case I40E_VSI_SRIOV: | |
1596 | case I40E_VSI_VMDQ2: | |
1597 | default: | |
4e3b35b0 | 1598 | qcount = num_tc_qps; |
41c445ff JB |
1599 | WARN_ON(i != 0); |
1600 | break; | |
1601 | } | |
4e3b35b0 NP |
1602 | vsi->tc_config.tc_info[i].qoffset = offset; |
1603 | vsi->tc_config.tc_info[i].qcount = qcount; | |
41c445ff | 1604 | |
1e200e4a | 1605 | /* find the next higher power-of-2 of num queue pairs */ |
4e3b35b0 | 1606 | num_qps = qcount; |
41c445ff | 1607 | pow = 0; |
41a1d04b | 1608 | while (num_qps && (BIT_ULL(pow) < qcount)) { |
41c445ff JB |
1609 | pow++; |
1610 | num_qps >>= 1; | |
1611 | } | |
1612 | ||
1613 | vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; | |
1614 | qmap = | |
1615 | (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
1616 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
1617 | ||
4e3b35b0 | 1618 | offset += qcount; |
41c445ff JB |
1619 | } else { |
1620 | /* TC is not enabled so set the offset to | |
1621 | * default queue and allocate one queue | |
1622 | * for the given TC. | |
1623 | */ | |
1624 | vsi->tc_config.tc_info[i].qoffset = 0; | |
1625 | vsi->tc_config.tc_info[i].qcount = 1; | |
1626 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
1627 | ||
1628 | qmap = 0; | |
1629 | } | |
1630 | ctxt->info.tc_mapping[i] = cpu_to_le16(qmap); | |
1631 | } | |
1632 | ||
1633 | /* Set actual Tx/Rx queue pairs */ | |
1634 | vsi->num_queue_pairs = offset; | |
9a3bd2f1 ASJ |
1635 | if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) { |
1636 | if (vsi->req_queue_pairs > 0) | |
1637 | vsi->num_queue_pairs = vsi->req_queue_pairs; | |
26cdc443 | 1638 | else if (pf->flags & I40E_FLAG_MSIX_ENABLED) |
9a3bd2f1 ASJ |
1639 | vsi->num_queue_pairs = pf->num_lan_msix; |
1640 | } | |
41c445ff JB |
1641 | |
1642 | /* Scheduler section valid can only be set for ADD VSI */ | |
1643 | if (is_add) { | |
1644 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
1645 | ||
1646 | ctxt->info.up_enable_bits = enabled_tc; | |
1647 | } | |
1648 | if (vsi->type == I40E_VSI_SRIOV) { | |
1649 | ctxt->info.mapping_flags |= | |
1650 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); | |
1651 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
1652 | ctxt->info.queue_mapping[i] = | |
1653 | cpu_to_le16(vsi->base_queue + i); | |
1654 | } else { | |
1655 | ctxt->info.mapping_flags |= | |
1656 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
1657 | ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
1658 | } | |
1659 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
1660 | } | |
1661 | ||
1662 | /** | |
1663 | * i40e_set_rx_mode - NDO callback to set the netdev filters | |
1664 | * @netdev: network interface device structure | |
1665 | **/ | |
38e00438 VD |
1666 | #ifdef I40E_FCOE |
1667 | void i40e_set_rx_mode(struct net_device *netdev) | |
1668 | #else | |
41c445ff | 1669 | static void i40e_set_rx_mode(struct net_device *netdev) |
38e00438 | 1670 | #endif |
41c445ff JB |
1671 | { |
1672 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1673 | struct i40e_mac_filter *f, *ftmp; | |
1674 | struct i40e_vsi *vsi = np->vsi; | |
1675 | struct netdev_hw_addr *uca; | |
1676 | struct netdev_hw_addr *mca; | |
1677 | struct netdev_hw_addr *ha; | |
1678 | ||
21659035 KP |
1679 | spin_lock_bh(&vsi->mac_filter_list_lock); |
1680 | ||
41c445ff JB |
1681 | /* add addr if not already in the filter list */ |
1682 | netdev_for_each_uc_addr(uca, netdev) { | |
1683 | if (!i40e_find_mac(vsi, uca->addr, false, true)) { | |
1684 | if (i40e_is_vsi_in_vlan(vsi)) | |
1685 | i40e_put_mac_in_vlan(vsi, uca->addr, | |
1686 | false, true); | |
1687 | else | |
1688 | i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY, | |
1689 | false, true); | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | netdev_for_each_mc_addr(mca, netdev) { | |
1694 | if (!i40e_find_mac(vsi, mca->addr, false, true)) { | |
1695 | if (i40e_is_vsi_in_vlan(vsi)) | |
1696 | i40e_put_mac_in_vlan(vsi, mca->addr, | |
1697 | false, true); | |
1698 | else | |
1699 | i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY, | |
1700 | false, true); | |
1701 | } | |
1702 | } | |
1703 | ||
1704 | /* remove filter if not in netdev list */ | |
1705 | list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { | |
41c445ff JB |
1706 | |
1707 | if (!f->is_netdev) | |
1708 | continue; | |
1709 | ||
2f41f335 SN |
1710 | netdev_for_each_mc_addr(mca, netdev) |
1711 | if (ether_addr_equal(mca->addr, f->macaddr)) | |
1712 | goto bottom_of_search_loop; | |
41c445ff | 1713 | |
2f41f335 SN |
1714 | netdev_for_each_uc_addr(uca, netdev) |
1715 | if (ether_addr_equal(uca->addr, f->macaddr)) | |
1716 | goto bottom_of_search_loop; | |
1717 | ||
1718 | for_each_dev_addr(netdev, ha) | |
1719 | if (ether_addr_equal(ha->addr, f->macaddr)) | |
1720 | goto bottom_of_search_loop; | |
1721 | ||
1722 | /* f->macaddr wasn't found in uc, mc, or ha list so delete it */ | |
1723 | i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true); | |
1724 | ||
1725 | bottom_of_search_loop: | |
1726 | continue; | |
41c445ff | 1727 | } |
21659035 | 1728 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
41c445ff JB |
1729 | |
1730 | /* check for other flag changes */ | |
1731 | if (vsi->current_netdev_flags != vsi->netdev->flags) { | |
1732 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
1733 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1734 | } | |
c53934c6 JB |
1735 | |
1736 | /* schedule our worker thread which will take care of | |
1737 | * applying the new filter changes | |
1738 | */ | |
1739 | i40e_service_event_schedule(vsi->back); | |
41c445ff JB |
1740 | } |
1741 | ||
21659035 KP |
1742 | /** |
1743 | * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries | |
1744 | * @vsi: pointer to vsi struct | |
1745 | * @from: Pointer to list which contains MAC filter entries - changes to | |
1746 | * those entries needs to be undone. | |
1747 | * | |
1748 | * MAC filter entries from list were slated to be removed from device. | |
1749 | **/ | |
1750 | static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi, | |
1751 | struct list_head *from) | |
1752 | { | |
1753 | struct i40e_mac_filter *f, *ftmp; | |
1754 | ||
1755 | list_for_each_entry_safe(f, ftmp, from, list) { | |
21659035 KP |
1756 | /* Move the element back into MAC filter list*/ |
1757 | list_move_tail(&f->list, &vsi->mac_filter_list); | |
1758 | } | |
1759 | } | |
1760 | ||
1761 | /** | |
c3c7ea27 MW |
1762 | * i40e_update_filter_state - Update filter state based on return data |
1763 | * from firmware | |
1764 | * @count: Number of filters added | |
1765 | * @add_list: return data from fw | |
1766 | * @head: pointer to first filter in current batch | |
1767 | * @aq_err: status from fw | |
21659035 | 1768 | * |
c3c7ea27 MW |
1769 | * MAC filter entries from list were slated to be added to device. Returns |
1770 | * number of successful filters. Note that 0 does NOT mean success! | |
21659035 | 1771 | **/ |
c3c7ea27 MW |
1772 | static int |
1773 | i40e_update_filter_state(int count, | |
1774 | struct i40e_aqc_add_macvlan_element_data *add_list, | |
1775 | struct i40e_mac_filter *add_head, int aq_err) | |
21659035 | 1776 | { |
c3c7ea27 MW |
1777 | int retval = 0; |
1778 | int i; | |
21659035 | 1779 | |
21659035 | 1780 | |
c3c7ea27 MW |
1781 | if (!aq_err) { |
1782 | retval = count; | |
1783 | /* Everything's good, mark all filters active. */ | |
1784 | for (i = 0; i < count ; i++) { | |
1785 | add_head->state = I40E_FILTER_ACTIVE; | |
1786 | add_head = list_next_entry(add_head, list); | |
1787 | } | |
1788 | } else if (aq_err == I40E_AQ_RC_ENOSPC) { | |
1789 | /* Device ran out of filter space. Check the return value | |
1790 | * for each filter to see which ones are active. | |
1791 | */ | |
1792 | for (i = 0; i < count ; i++) { | |
1793 | if (add_list[i].match_method == | |
1794 | I40E_AQC_MM_ERR_NO_RES) { | |
1795 | add_head->state = I40E_FILTER_FAILED; | |
1796 | } else { | |
1797 | add_head->state = I40E_FILTER_ACTIVE; | |
1798 | retval++; | |
1799 | } | |
1800 | add_head = list_next_entry(add_head, list); | |
1801 | } | |
1802 | } else { | |
1803 | /* Some other horrible thing happened, fail all filters */ | |
1804 | retval = 0; | |
1805 | for (i = 0; i < count ; i++) { | |
1806 | add_head->state = I40E_FILTER_FAILED; | |
1807 | add_head = list_next_entry(add_head, list); | |
1808 | } | |
21659035 | 1809 | } |
c3c7ea27 | 1810 | return retval; |
21659035 KP |
1811 | } |
1812 | ||
41c445ff JB |
1813 | /** |
1814 | * i40e_sync_vsi_filters - Update the VSI filter list to the HW | |
1815 | * @vsi: ptr to the VSI | |
1816 | * | |
1817 | * Push any outstanding VSI filter changes through the AdminQ. | |
1818 | * | |
1819 | * Returns 0 or error value | |
1820 | **/ | |
17652c63 | 1821 | int i40e_sync_vsi_filters(struct i40e_vsi *vsi) |
41c445ff | 1822 | { |
c3c7ea27 MW |
1823 | struct i40e_mac_filter *f, *ftmp, *add_head = NULL; |
1824 | struct list_head tmp_add_list, tmp_del_list; | |
3e25a8f3 | 1825 | struct i40e_hw *hw = &vsi->back->hw; |
c3c7ea27 | 1826 | bool promisc_changed = false; |
2d1de828 | 1827 | char vsi_name[16] = "PF"; |
41c445ff JB |
1828 | int filter_list_len = 0; |
1829 | u32 changed_flags = 0; | |
ea02e90b | 1830 | i40e_status aq_ret = 0; |
ea02e90b | 1831 | int retval = 0; |
41c445ff JB |
1832 | struct i40e_pf *pf; |
1833 | int num_add = 0; | |
1834 | int num_del = 0; | |
f1c7e72e | 1835 | int aq_err = 0; |
41c445ff | 1836 | u16 cmd_flags; |
c3c7ea27 MW |
1837 | int list_size; |
1838 | int fcnt; | |
41c445ff JB |
1839 | |
1840 | /* empty array typed pointers, kcalloc later */ | |
1841 | struct i40e_aqc_add_macvlan_element_data *add_list; | |
1842 | struct i40e_aqc_remove_macvlan_element_data *del_list; | |
1843 | ||
1844 | while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state)) | |
1845 | usleep_range(1000, 2000); | |
1846 | pf = vsi->back; | |
1847 | ||
1848 | if (vsi->netdev) { | |
1849 | changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags; | |
1850 | vsi->current_netdev_flags = vsi->netdev->flags; | |
1851 | } | |
1852 | ||
21659035 | 1853 | INIT_LIST_HEAD(&tmp_add_list); |
c3c7ea27 | 1854 | INIT_LIST_HEAD(&tmp_del_list); |
21659035 | 1855 | |
2d1de828 SN |
1856 | if (vsi->type == I40E_VSI_SRIOV) |
1857 | snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id); | |
1858 | else if (vsi->type != I40E_VSI_MAIN) | |
1859 | snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid); | |
1860 | ||
41c445ff JB |
1861 | if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) { |
1862 | vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED; | |
1863 | ||
21659035 | 1864 | spin_lock_bh(&vsi->mac_filter_list_lock); |
c3c7ea27 | 1865 | /* Create a list of filters to delete. */ |
41c445ff | 1866 | list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { |
c3c7ea27 MW |
1867 | if (f->state == I40E_FILTER_REMOVE) { |
1868 | WARN_ON(f->counter != 0); | |
1869 | /* Move the element into temporary del_list */ | |
1870 | list_move_tail(&f->list, &tmp_del_list); | |
1871 | vsi->active_filters--; | |
1872 | } | |
1873 | if (f->state == I40E_FILTER_NEW) { | |
1874 | WARN_ON(f->counter == 0); | |
1875 | /* Move the element into temporary add_list */ | |
1876 | list_move_tail(&f->list, &tmp_add_list); | |
21659035 | 1877 | } |
21659035 KP |
1878 | } |
1879 | spin_unlock_bh(&vsi->mac_filter_list_lock); | |
21659035 KP |
1880 | } |
1881 | ||
1882 | /* Now process 'del_list' outside the lock */ | |
1883 | if (!list_empty(&tmp_del_list)) { | |
3e25a8f3 | 1884 | filter_list_len = hw->aq.asq_buf_size / |
21659035 | 1885 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 1886 | list_size = filter_list_len * |
f1199998 | 1887 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 1888 | del_list = kzalloc(list_size, GFP_ATOMIC); |
21659035 | 1889 | if (!del_list) { |
21659035 KP |
1890 | /* Undo VSI's MAC filter entry element updates */ |
1891 | spin_lock_bh(&vsi->mac_filter_list_lock); | |
1892 | i40e_undo_del_filter_entries(vsi, &tmp_del_list); | |
21659035 | 1893 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
ea02e90b MW |
1894 | retval = -ENOMEM; |
1895 | goto out; | |
21659035 KP |
1896 | } |
1897 | ||
1898 | list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) { | |
41c445ff JB |
1899 | cmd_flags = 0; |
1900 | ||
1901 | /* add to delete list */ | |
9a173901 | 1902 | ether_addr_copy(del_list[num_del].mac_addr, f->macaddr); |
c3c7ea27 MW |
1903 | if (f->vlan == I40E_VLAN_ANY) { |
1904 | del_list[num_del].vlan_tag = 0; | |
1905 | cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; | |
1906 | } else { | |
1907 | del_list[num_del].vlan_tag = | |
1908 | cpu_to_le16((u16)(f->vlan)); | |
1909 | } | |
41c445ff | 1910 | |
41c445ff JB |
1911 | cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; |
1912 | del_list[num_del].flags = cmd_flags; | |
1913 | num_del++; | |
1914 | ||
41c445ff JB |
1915 | /* flush a full buffer */ |
1916 | if (num_del == filter_list_len) { | |
c3c7ea27 MW |
1917 | aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, |
1918 | del_list, | |
1919 | num_del, NULL); | |
3e25a8f3 | 1920 | aq_err = hw->aq.asq_last_status; |
41c445ff | 1921 | num_del = 0; |
c3c7ea27 | 1922 | memset(del_list, 0, list_size); |
41c445ff | 1923 | |
c3c7ea27 MW |
1924 | /* Explicitly ignore and do not report when |
1925 | * firmware returns ENOENT. | |
1926 | */ | |
1927 | if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) { | |
ea02e90b | 1928 | retval = -EIO; |
c3c7ea27 MW |
1929 | dev_info(&pf->pdev->dev, |
1930 | "ignoring delete macvlan error on %s, err %s, aq_err %s\n", | |
2d1de828 | 1931 | vsi_name, |
3e25a8f3 MW |
1932 | i40e_stat_str(hw, aq_ret), |
1933 | i40e_aq_str(hw, aq_err)); | |
ea02e90b | 1934 | } |
41c445ff | 1935 | } |
21659035 KP |
1936 | /* Release memory for MAC filter entries which were |
1937 | * synced up with HW. | |
1938 | */ | |
1939 | list_del(&f->list); | |
1940 | kfree(f); | |
41c445ff | 1941 | } |
21659035 | 1942 | |
41c445ff | 1943 | if (num_del) { |
3e25a8f3 MW |
1944 | aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, del_list, |
1945 | num_del, NULL); | |
1946 | aq_err = hw->aq.asq_last_status; | |
41c445ff JB |
1947 | num_del = 0; |
1948 | ||
c3c7ea27 MW |
1949 | /* Explicitly ignore and do not report when firmware |
1950 | * returns ENOENT. | |
1951 | */ | |
1952 | if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) { | |
1953 | retval = -EIO; | |
41c445ff | 1954 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
1955 | "ignoring delete macvlan error on %s, err %s aq_err %s\n", |
1956 | vsi_name, | |
3e25a8f3 MW |
1957 | i40e_stat_str(hw, aq_ret), |
1958 | i40e_aq_str(hw, aq_err)); | |
c3c7ea27 | 1959 | } |
41c445ff JB |
1960 | } |
1961 | ||
1962 | kfree(del_list); | |
1963 | del_list = NULL; | |
21659035 KP |
1964 | } |
1965 | ||
1966 | if (!list_empty(&tmp_add_list)) { | |
c3c7ea27 | 1967 | /* Do all the adds now. */ |
3e25a8f3 | 1968 | filter_list_len = hw->aq.asq_buf_size / |
f1199998 | 1969 | sizeof(struct i40e_aqc_add_macvlan_element_data); |
c3c7ea27 MW |
1970 | list_size = filter_list_len * |
1971 | sizeof(struct i40e_aqc_add_macvlan_element_data); | |
1972 | add_list = kzalloc(list_size, GFP_ATOMIC); | |
21659035 | 1973 | if (!add_list) { |
ea02e90b MW |
1974 | retval = -ENOMEM; |
1975 | goto out; | |
21659035 | 1976 | } |
c3c7ea27 MW |
1977 | num_add = 0; |
1978 | list_for_each_entry(f, &tmp_add_list, list) { | |
1979 | if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, | |
1980 | &vsi->state)) { | |
1981 | f->state = I40E_FILTER_FAILED; | |
1982 | continue; | |
1983 | } | |
41c445ff | 1984 | /* add to add array */ |
c3c7ea27 MW |
1985 | if (num_add == 0) |
1986 | add_head = f; | |
1987 | cmd_flags = 0; | |
9a173901 | 1988 | ether_addr_copy(add_list[num_add].mac_addr, f->macaddr); |
c3c7ea27 MW |
1989 | if (f->vlan == I40E_VLAN_ANY) { |
1990 | add_list[num_add].vlan_tag = 0; | |
1991 | cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; | |
1992 | } else { | |
1993 | add_list[num_add].vlan_tag = | |
1994 | cpu_to_le16((u16)(f->vlan)); | |
1995 | } | |
41c445ff | 1996 | add_list[num_add].queue_number = 0; |
41c445ff | 1997 | cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; |
41c445ff JB |
1998 | add_list[num_add].flags = cpu_to_le16(cmd_flags); |
1999 | num_add++; | |
2000 | ||
2001 | /* flush a full buffer */ | |
2002 | if (num_add == filter_list_len) { | |
3e25a8f3 | 2003 | aq_ret = i40e_aq_add_macvlan(hw, vsi->seid, |
ea02e90b MW |
2004 | add_list, num_add, |
2005 | NULL); | |
3e25a8f3 | 2006 | aq_err = hw->aq.asq_last_status; |
c3c7ea27 MW |
2007 | fcnt = i40e_update_filter_state(num_add, |
2008 | add_list, | |
2009 | add_head, | |
2010 | aq_ret); | |
2011 | vsi->active_filters += fcnt; | |
2012 | ||
2013 | if (fcnt != num_add) { | |
2014 | promisc_changed = true; | |
2015 | set_bit(__I40E_FILTER_OVERFLOW_PROMISC, | |
2016 | &vsi->state); | |
2017 | vsi->promisc_threshold = | |
2018 | (vsi->active_filters * 3) / 4; | |
2019 | dev_warn(&pf->pdev->dev, | |
2020 | "Error %s adding RX filters on %s, promiscuous mode forced on\n", | |
2021 | i40e_aq_str(hw, aq_err), | |
2022 | vsi_name); | |
2023 | } | |
2024 | memset(add_list, 0, list_size); | |
41c445ff | 2025 | num_add = 0; |
41c445ff JB |
2026 | } |
2027 | } | |
2028 | if (num_add) { | |
3e25a8f3 | 2029 | aq_ret = i40e_aq_add_macvlan(hw, vsi->seid, |
ea02e90b | 2030 | add_list, num_add, NULL); |
3e25a8f3 | 2031 | aq_err = hw->aq.asq_last_status; |
c3c7ea27 MW |
2032 | fcnt = i40e_update_filter_state(num_add, add_list, |
2033 | add_head, aq_ret); | |
2034 | vsi->active_filters += fcnt; | |
2035 | if (fcnt != num_add) { | |
2036 | promisc_changed = true; | |
2037 | set_bit(__I40E_FILTER_OVERFLOW_PROMISC, | |
2038 | &vsi->state); | |
2039 | vsi->promisc_threshold = | |
2040 | (vsi->active_filters * 3) / 4; | |
2041 | dev_warn(&pf->pdev->dev, | |
2042 | "Error %s adding RX filters on %s, promiscuous mode forced on\n", | |
2043 | i40e_aq_str(hw, aq_err), vsi_name); | |
2044 | } | |
41c445ff | 2045 | } |
c3c7ea27 MW |
2046 | /* Now move all of the filters from the temp add list back to |
2047 | * the VSI's list. | |
2048 | */ | |
2049 | spin_lock_bh(&vsi->mac_filter_list_lock); | |
2050 | list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) { | |
2051 | list_move_tail(&f->list, &vsi->mac_filter_list); | |
2052 | } | |
2053 | spin_unlock_bh(&vsi->mac_filter_list_lock); | |
41c445ff JB |
2054 | kfree(add_list); |
2055 | add_list = NULL; | |
c3c7ea27 | 2056 | } |
41c445ff | 2057 | |
c3c7ea27 MW |
2058 | /* Check to see if we can drop out of overflow promiscuous mode. */ |
2059 | if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state) && | |
2060 | (vsi->active_filters < vsi->promisc_threshold)) { | |
2061 | int failed_count = 0; | |
2062 | /* See if we have any failed filters. We can't drop out of | |
2063 | * promiscuous until these have all been deleted. | |
2064 | */ | |
2065 | spin_lock_bh(&vsi->mac_filter_list_lock); | |
2066 | list_for_each_entry(f, &vsi->mac_filter_list, list) { | |
2067 | if (f->state == I40E_FILTER_FAILED) | |
2068 | failed_count++; | |
2069 | } | |
2070 | spin_unlock_bh(&vsi->mac_filter_list_lock); | |
2071 | if (!failed_count) { | |
41c445ff | 2072 | dev_info(&pf->pdev->dev, |
c3c7ea27 MW |
2073 | "filter logjam cleared on %s, leaving overflow promiscuous mode\n", |
2074 | vsi_name); | |
2075 | clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); | |
2076 | promisc_changed = true; | |
2077 | vsi->promisc_threshold = 0; | |
41c445ff JB |
2078 | } |
2079 | } | |
2080 | ||
a856b5cb ASJ |
2081 | /* if the VF is not trusted do not do promisc */ |
2082 | if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) { | |
2083 | clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); | |
2084 | goto out; | |
2085 | } | |
2086 | ||
41c445ff JB |
2087 | /* check for changes in promiscuous modes */ |
2088 | if (changed_flags & IFF_ALLMULTI) { | |
2089 | bool cur_multipromisc; | |
6995b36c | 2090 | |
41c445ff | 2091 | cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI); |
ea02e90b MW |
2092 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw, |
2093 | vsi->seid, | |
2094 | cur_multipromisc, | |
2095 | NULL); | |
2096 | if (aq_ret) { | |
2097 | retval = i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2098 | hw->aq.asq_last_status); |
41c445ff | 2099 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2100 | "set multi promisc failed on %s, err %s aq_err %s\n", |
2101 | vsi_name, | |
3e25a8f3 MW |
2102 | i40e_stat_str(hw, aq_ret), |
2103 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
ea02e90b | 2104 | } |
41c445ff | 2105 | } |
c3c7ea27 MW |
2106 | if ((changed_flags & IFF_PROMISC) || |
2107 | (promisc_changed && | |
2108 | test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state))) { | |
41c445ff | 2109 | bool cur_promisc; |
6995b36c | 2110 | |
41c445ff JB |
2111 | cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) || |
2112 | test_bit(__I40E_FILTER_OVERFLOW_PROMISC, | |
2113 | &vsi->state)); | |
6784ed5a ASJ |
2114 | if ((vsi->type == I40E_VSI_MAIN) && |
2115 | (pf->lan_veb != I40E_NO_VEB) && | |
2116 | !(pf->flags & I40E_FLAG_MFP_ENABLED)) { | |
92faef85 ASJ |
2117 | /* set defport ON for Main VSI instead of true promisc |
2118 | * this way we will get all unicast/multicast and VLAN | |
2119 | * promisc behavior but will not get VF or VMDq traffic | |
2120 | * replicated on the Main VSI. | |
2121 | */ | |
2122 | if (pf->cur_promisc != cur_promisc) { | |
2123 | pf->cur_promisc = cur_promisc; | |
5bc16031 MW |
2124 | if (cur_promisc) |
2125 | aq_ret = | |
2126 | i40e_aq_set_default_vsi(hw, | |
2127 | vsi->seid, | |
2128 | NULL); | |
2129 | else | |
2130 | aq_ret = | |
2131 | i40e_aq_clear_default_vsi(hw, | |
2132 | vsi->seid, | |
2133 | NULL); | |
2134 | if (aq_ret) { | |
2135 | retval = i40e_aq_rc_to_posix(aq_ret, | |
2136 | hw->aq.asq_last_status); | |
2137 | dev_info(&pf->pdev->dev, | |
2d1de828 SN |
2138 | "Set default VSI failed on %s, err %s, aq_err %s\n", |
2139 | vsi_name, | |
5bc16031 MW |
2140 | i40e_stat_str(hw, aq_ret), |
2141 | i40e_aq_str(hw, | |
2142 | hw->aq.asq_last_status)); | |
2143 | } | |
92faef85 ASJ |
2144 | } |
2145 | } else { | |
ea02e90b | 2146 | aq_ret = i40e_aq_set_vsi_unicast_promiscuous( |
3e25a8f3 | 2147 | hw, |
f1c7e72e | 2148 | vsi->seid, |
b5569892 ASJ |
2149 | cur_promisc, NULL, |
2150 | true); | |
ea02e90b MW |
2151 | if (aq_ret) { |
2152 | retval = | |
2153 | i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2154 | hw->aq.asq_last_status); |
92faef85 | 2155 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2156 | "set unicast promisc failed on %s, err %s, aq_err %s\n", |
2157 | vsi_name, | |
3e25a8f3 MW |
2158 | i40e_stat_str(hw, aq_ret), |
2159 | i40e_aq_str(hw, | |
2160 | hw->aq.asq_last_status)); | |
ea02e90b MW |
2161 | } |
2162 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous( | |
3e25a8f3 | 2163 | hw, |
92faef85 ASJ |
2164 | vsi->seid, |
2165 | cur_promisc, NULL); | |
ea02e90b MW |
2166 | if (aq_ret) { |
2167 | retval = | |
2168 | i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2169 | hw->aq.asq_last_status); |
92faef85 | 2170 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2171 | "set multicast promisc failed on %s, err %s, aq_err %s\n", |
2172 | vsi_name, | |
3e25a8f3 MW |
2173 | i40e_stat_str(hw, aq_ret), |
2174 | i40e_aq_str(hw, | |
2175 | hw->aq.asq_last_status)); | |
ea02e90b | 2176 | } |
92faef85 | 2177 | } |
ea02e90b MW |
2178 | aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw, |
2179 | vsi->seid, | |
2180 | cur_promisc, NULL); | |
2181 | if (aq_ret) { | |
2182 | retval = i40e_aq_rc_to_posix(aq_ret, | |
2183 | pf->hw.aq.asq_last_status); | |
1a10370a | 2184 | dev_info(&pf->pdev->dev, |
f1c7e72e | 2185 | "set brdcast promisc failed, err %s, aq_err %s\n", |
3e25a8f3 MW |
2186 | i40e_stat_str(hw, aq_ret), |
2187 | i40e_aq_str(hw, | |
2188 | hw->aq.asq_last_status)); | |
ea02e90b | 2189 | } |
41c445ff | 2190 | } |
ea02e90b | 2191 | out: |
2818ccd9 JB |
2192 | /* if something went wrong then set the changed flag so we try again */ |
2193 | if (retval) | |
2194 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
2195 | ||
41c445ff | 2196 | clear_bit(__I40E_CONFIG_BUSY, &vsi->state); |
ea02e90b | 2197 | return retval; |
41c445ff JB |
2198 | } |
2199 | ||
2200 | /** | |
2201 | * i40e_sync_filters_subtask - Sync the VSI filter list with HW | |
2202 | * @pf: board private structure | |
2203 | **/ | |
2204 | static void i40e_sync_filters_subtask(struct i40e_pf *pf) | |
2205 | { | |
2206 | int v; | |
2207 | ||
2208 | if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC)) | |
2209 | return; | |
2210 | pf->flags &= ~I40E_FLAG_FILTER_SYNC; | |
2211 | ||
505682cd | 2212 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 2213 | if (pf->vsi[v] && |
17652c63 JB |
2214 | (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) { |
2215 | int ret = i40e_sync_vsi_filters(pf->vsi[v]); | |
2216 | ||
2217 | if (ret) { | |
2218 | /* come back and try again later */ | |
2219 | pf->flags |= I40E_FLAG_FILTER_SYNC; | |
2220 | break; | |
2221 | } | |
2222 | } | |
41c445ff JB |
2223 | } |
2224 | } | |
2225 | ||
2226 | /** | |
2227 | * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit | |
2228 | * @netdev: network interface device structure | |
2229 | * @new_mtu: new value for maximum frame size | |
2230 | * | |
2231 | * Returns 0 on success, negative on failure | |
2232 | **/ | |
2233 | static int i40e_change_mtu(struct net_device *netdev, int new_mtu) | |
2234 | { | |
2235 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
61a46a4c | 2236 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
41c445ff JB |
2237 | struct i40e_vsi *vsi = np->vsi; |
2238 | ||
2239 | /* MTU < 68 is an error and causes problems on some kernels */ | |
2240 | if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER)) | |
2241 | return -EINVAL; | |
2242 | ||
2243 | netdev_info(netdev, "changing MTU from %d to %d\n", | |
2244 | netdev->mtu, new_mtu); | |
2245 | netdev->mtu = new_mtu; | |
2246 | if (netif_running(netdev)) | |
2247 | i40e_vsi_reinit_locked(vsi); | |
e3219ce6 | 2248 | i40e_notify_client_of_l2_param_changes(vsi); |
41c445ff JB |
2249 | return 0; |
2250 | } | |
2251 | ||
beb0dff1 JK |
2252 | /** |
2253 | * i40e_ioctl - Access the hwtstamp interface | |
2254 | * @netdev: network interface device structure | |
2255 | * @ifr: interface request data | |
2256 | * @cmd: ioctl command | |
2257 | **/ | |
2258 | int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
2259 | { | |
2260 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2261 | struct i40e_pf *pf = np->vsi->back; | |
2262 | ||
2263 | switch (cmd) { | |
2264 | case SIOCGHWTSTAMP: | |
2265 | return i40e_ptp_get_ts_config(pf, ifr); | |
2266 | case SIOCSHWTSTAMP: | |
2267 | return i40e_ptp_set_ts_config(pf, ifr); | |
2268 | default: | |
2269 | return -EOPNOTSUPP; | |
2270 | } | |
2271 | } | |
2272 | ||
41c445ff JB |
2273 | /** |
2274 | * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI | |
2275 | * @vsi: the vsi being adjusted | |
2276 | **/ | |
2277 | void i40e_vlan_stripping_enable(struct i40e_vsi *vsi) | |
2278 | { | |
2279 | struct i40e_vsi_context ctxt; | |
2280 | i40e_status ret; | |
2281 | ||
2282 | if ((vsi->info.valid_sections & | |
2283 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2284 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0)) | |
2285 | return; /* already enabled */ | |
2286 | ||
2287 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2288 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2289 | I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; | |
2290 | ||
2291 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2292 | ctxt.info = vsi->info; |
41c445ff JB |
2293 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2294 | if (ret) { | |
2295 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2296 | "update vlan stripping failed, err %s aq_err %s\n", |
2297 | i40e_stat_str(&vsi->back->hw, ret), | |
2298 | i40e_aq_str(&vsi->back->hw, | |
2299 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2300 | } |
2301 | } | |
2302 | ||
2303 | /** | |
2304 | * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI | |
2305 | * @vsi: the vsi being adjusted | |
2306 | **/ | |
2307 | void i40e_vlan_stripping_disable(struct i40e_vsi *vsi) | |
2308 | { | |
2309 | struct i40e_vsi_context ctxt; | |
2310 | i40e_status ret; | |
2311 | ||
2312 | if ((vsi->info.valid_sections & | |
2313 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2314 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) == | |
2315 | I40E_AQ_VSI_PVLAN_EMOD_MASK)) | |
2316 | return; /* already disabled */ | |
2317 | ||
2318 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2319 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2320 | I40E_AQ_VSI_PVLAN_EMOD_NOTHING; | |
2321 | ||
2322 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2323 | ctxt.info = vsi->info; |
41c445ff JB |
2324 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2325 | if (ret) { | |
2326 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2327 | "update vlan stripping failed, err %s aq_err %s\n", |
2328 | i40e_stat_str(&vsi->back->hw, ret), | |
2329 | i40e_aq_str(&vsi->back->hw, | |
2330 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2331 | } |
2332 | } | |
2333 | ||
2334 | /** | |
2335 | * i40e_vlan_rx_register - Setup or shutdown vlan offload | |
2336 | * @netdev: network interface to be adjusted | |
2337 | * @features: netdev features to test if VLAN offload is enabled or not | |
2338 | **/ | |
2339 | static void i40e_vlan_rx_register(struct net_device *netdev, u32 features) | |
2340 | { | |
2341 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2342 | struct i40e_vsi *vsi = np->vsi; | |
2343 | ||
2344 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2345 | i40e_vlan_stripping_enable(vsi); | |
2346 | else | |
2347 | i40e_vlan_stripping_disable(vsi); | |
2348 | } | |
2349 | ||
2350 | /** | |
2351 | * i40e_vsi_add_vlan - Add vsi membership for given vlan | |
2352 | * @vsi: the vsi being configured | |
2353 | * @vid: vlan id to be added (0 = untagged only , -1 = any) | |
2354 | **/ | |
2355 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid) | |
2356 | { | |
c3c7ea27 | 2357 | struct i40e_mac_filter *f, *ftmp, *add_f; |
41c445ff | 2358 | bool is_netdev, is_vf; |
41c445ff JB |
2359 | |
2360 | is_vf = (vsi->type == I40E_VSI_SRIOV); | |
2361 | is_netdev = !!(vsi->netdev); | |
2362 | ||
21659035 KP |
2363 | /* Locked once because all functions invoked below iterates list*/ |
2364 | spin_lock_bh(&vsi->mac_filter_list_lock); | |
2365 | ||
41c445ff JB |
2366 | if (is_netdev) { |
2367 | add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid, | |
2368 | is_vf, is_netdev); | |
2369 | if (!add_f) { | |
2370 | dev_info(&vsi->back->pdev->dev, | |
2371 | "Could not add vlan filter %d for %pM\n", | |
2372 | vid, vsi->netdev->dev_addr); | |
21659035 | 2373 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
41c445ff JB |
2374 | return -ENOMEM; |
2375 | } | |
2376 | } | |
2377 | ||
c3c7ea27 | 2378 | list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { |
41c445ff JB |
2379 | add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev); |
2380 | if (!add_f) { | |
2381 | dev_info(&vsi->back->pdev->dev, | |
2382 | "Could not add vlan filter %d for %pM\n", | |
2383 | vid, f->macaddr); | |
21659035 | 2384 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
41c445ff JB |
2385 | return -ENOMEM; |
2386 | } | |
2387 | } | |
2388 | ||
41c445ff JB |
2389 | /* Now if we add a vlan tag, make sure to check if it is the first |
2390 | * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag" | |
2391 | * with 0, so we now accept untagged and specified tagged traffic | |
c3c7ea27 | 2392 | * (and not all tags along with untagged) |
41c445ff JB |
2393 | */ |
2394 | if (vid > 0) { | |
2395 | if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr, | |
2396 | I40E_VLAN_ANY, | |
2397 | is_vf, is_netdev)) { | |
2398 | i40e_del_filter(vsi, vsi->netdev->dev_addr, | |
2399 | I40E_VLAN_ANY, is_vf, is_netdev); | |
2400 | add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0, | |
2401 | is_vf, is_netdev); | |
2402 | if (!add_f) { | |
2403 | dev_info(&vsi->back->pdev->dev, | |
2404 | "Could not add filter 0 for %pM\n", | |
2405 | vsi->netdev->dev_addr); | |
21659035 | 2406 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
41c445ff JB |
2407 | return -ENOMEM; |
2408 | } | |
2409 | } | |
8d82a7c5 | 2410 | } |
41c445ff | 2411 | |
8d82a7c5 GR |
2412 | /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */ |
2413 | if (vid > 0 && !vsi->info.pvid) { | |
c3c7ea27 | 2414 | list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { |
21659035 KP |
2415 | if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY, |
2416 | is_vf, is_netdev)) | |
2417 | continue; | |
2418 | i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, | |
2419 | is_vf, is_netdev); | |
2420 | add_f = i40e_add_filter(vsi, f->macaddr, | |
2421 | 0, is_vf, is_netdev); | |
2422 | if (!add_f) { | |
2423 | dev_info(&vsi->back->pdev->dev, | |
2424 | "Could not add filter 0 for %pM\n", | |
2425 | f->macaddr); | |
2426 | spin_unlock_bh(&vsi->mac_filter_list_lock); | |
2427 | return -ENOMEM; | |
41c445ff JB |
2428 | } |
2429 | } | |
41c445ff JB |
2430 | } |
2431 | ||
21659035 KP |
2432 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
2433 | ||
0e4425ed JB |
2434 | /* schedule our worker thread which will take care of |
2435 | * applying the new filter changes | |
2436 | */ | |
2437 | i40e_service_event_schedule(vsi->back); | |
2438 | return 0; | |
41c445ff JB |
2439 | } |
2440 | ||
2441 | /** | |
2442 | * i40e_vsi_kill_vlan - Remove vsi membership for given vlan | |
2443 | * @vsi: the vsi being configured | |
2444 | * @vid: vlan id to be removed (0 = untagged only , -1 = any) | |
078b5876 JB |
2445 | * |
2446 | * Return: 0 on success or negative otherwise | |
41c445ff JB |
2447 | **/ |
2448 | int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid) | |
2449 | { | |
2450 | struct net_device *netdev = vsi->netdev; | |
c3c7ea27 | 2451 | struct i40e_mac_filter *f, *ftmp, *add_f; |
41c445ff JB |
2452 | bool is_vf, is_netdev; |
2453 | int filter_count = 0; | |
41c445ff JB |
2454 | |
2455 | is_vf = (vsi->type == I40E_VSI_SRIOV); | |
2456 | is_netdev = !!(netdev); | |
2457 | ||
21659035 KP |
2458 | /* Locked once because all functions invoked below iterates list */ |
2459 | spin_lock_bh(&vsi->mac_filter_list_lock); | |
2460 | ||
41c445ff JB |
2461 | if (is_netdev) |
2462 | i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev); | |
2463 | ||
c3c7ea27 | 2464 | list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) |
41c445ff JB |
2465 | i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev); |
2466 | ||
41c445ff JB |
2467 | /* go through all the filters for this VSI and if there is only |
2468 | * vid == 0 it means there are no other filters, so vid 0 must | |
2469 | * be replaced with -1. This signifies that we should from now | |
2470 | * on accept any traffic (with any tag present, or untagged) | |
2471 | */ | |
2472 | list_for_each_entry(f, &vsi->mac_filter_list, list) { | |
2473 | if (is_netdev) { | |
2474 | if (f->vlan && | |
2475 | ether_addr_equal(netdev->dev_addr, f->macaddr)) | |
2476 | filter_count++; | |
2477 | } | |
2478 | ||
2479 | if (f->vlan) | |
2480 | filter_count++; | |
2481 | } | |
2482 | ||
2483 | if (!filter_count && is_netdev) { | |
2484 | i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev); | |
2485 | f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, | |
2486 | is_vf, is_netdev); | |
2487 | if (!f) { | |
2488 | dev_info(&vsi->back->pdev->dev, | |
2489 | "Could not add filter %d for %pM\n", | |
2490 | I40E_VLAN_ANY, netdev->dev_addr); | |
21659035 | 2491 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
41c445ff JB |
2492 | return -ENOMEM; |
2493 | } | |
2494 | } | |
2495 | ||
2496 | if (!filter_count) { | |
c3c7ea27 | 2497 | list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { |
41c445ff JB |
2498 | i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev); |
2499 | add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY, | |
21659035 | 2500 | is_vf, is_netdev); |
41c445ff JB |
2501 | if (!add_f) { |
2502 | dev_info(&vsi->back->pdev->dev, | |
2503 | "Could not add filter %d for %pM\n", | |
2504 | I40E_VLAN_ANY, f->macaddr); | |
21659035 | 2505 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
41c445ff JB |
2506 | return -ENOMEM; |
2507 | } | |
2508 | } | |
2509 | } | |
2510 | ||
21659035 KP |
2511 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
2512 | ||
0e4425ed JB |
2513 | /* schedule our worker thread which will take care of |
2514 | * applying the new filter changes | |
2515 | */ | |
2516 | i40e_service_event_schedule(vsi->back); | |
2517 | return 0; | |
41c445ff JB |
2518 | } |
2519 | ||
2520 | /** | |
2521 | * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload | |
2522 | * @netdev: network interface to be adjusted | |
2523 | * @vid: vlan id to be added | |
078b5876 JB |
2524 | * |
2525 | * net_device_ops implementation for adding vlan ids | |
41c445ff | 2526 | **/ |
38e00438 VD |
2527 | #ifdef I40E_FCOE |
2528 | int i40e_vlan_rx_add_vid(struct net_device *netdev, | |
2529 | __always_unused __be16 proto, u16 vid) | |
2530 | #else | |
41c445ff JB |
2531 | static int i40e_vlan_rx_add_vid(struct net_device *netdev, |
2532 | __always_unused __be16 proto, u16 vid) | |
38e00438 | 2533 | #endif |
41c445ff JB |
2534 | { |
2535 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2536 | struct i40e_vsi *vsi = np->vsi; | |
078b5876 | 2537 | int ret = 0; |
41c445ff JB |
2538 | |
2539 | if (vid > 4095) | |
078b5876 JB |
2540 | return -EINVAL; |
2541 | ||
6982d429 ASJ |
2542 | /* If the network stack called us with vid = 0 then |
2543 | * it is asking to receive priority tagged packets with | |
2544 | * vlan id 0. Our HW receives them by default when configured | |
2545 | * to receive untagged packets so there is no need to add an | |
2546 | * extra filter for vlan 0 tagged packets. | |
41c445ff | 2547 | */ |
6982d429 ASJ |
2548 | if (vid) |
2549 | ret = i40e_vsi_add_vlan(vsi, vid); | |
41c445ff | 2550 | |
078b5876 JB |
2551 | if (!ret && (vid < VLAN_N_VID)) |
2552 | set_bit(vid, vsi->active_vlans); | |
41c445ff | 2553 | |
078b5876 | 2554 | return ret; |
41c445ff JB |
2555 | } |
2556 | ||
2557 | /** | |
2558 | * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload | |
2559 | * @netdev: network interface to be adjusted | |
2560 | * @vid: vlan id to be removed | |
078b5876 | 2561 | * |
fdfd943e | 2562 | * net_device_ops implementation for removing vlan ids |
41c445ff | 2563 | **/ |
38e00438 VD |
2564 | #ifdef I40E_FCOE |
2565 | int i40e_vlan_rx_kill_vid(struct net_device *netdev, | |
2566 | __always_unused __be16 proto, u16 vid) | |
2567 | #else | |
41c445ff JB |
2568 | static int i40e_vlan_rx_kill_vid(struct net_device *netdev, |
2569 | __always_unused __be16 proto, u16 vid) | |
38e00438 | 2570 | #endif |
41c445ff JB |
2571 | { |
2572 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2573 | struct i40e_vsi *vsi = np->vsi; | |
2574 | ||
41c445ff JB |
2575 | /* return code is ignored as there is nothing a user |
2576 | * can do about failure to remove and a log message was | |
078b5876 | 2577 | * already printed from the other function |
41c445ff JB |
2578 | */ |
2579 | i40e_vsi_kill_vlan(vsi, vid); | |
2580 | ||
2581 | clear_bit(vid, vsi->active_vlans); | |
078b5876 | 2582 | |
41c445ff JB |
2583 | return 0; |
2584 | } | |
2585 | ||
2586 | /** | |
2587 | * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up | |
2588 | * @vsi: the vsi being brought back up | |
2589 | **/ | |
2590 | static void i40e_restore_vlan(struct i40e_vsi *vsi) | |
2591 | { | |
2592 | u16 vid; | |
2593 | ||
2594 | if (!vsi->netdev) | |
2595 | return; | |
2596 | ||
2597 | i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features); | |
2598 | ||
2599 | for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID) | |
2600 | i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q), | |
2601 | vid); | |
2602 | } | |
2603 | ||
2604 | /** | |
2605 | * i40e_vsi_add_pvid - Add pvid for the VSI | |
2606 | * @vsi: the vsi being adjusted | |
2607 | * @vid: the vlan id to set as a PVID | |
2608 | **/ | |
dcae29be | 2609 | int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid) |
41c445ff JB |
2610 | { |
2611 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 2612 | i40e_status ret; |
41c445ff JB |
2613 | |
2614 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2615 | vsi->info.pvid = cpu_to_le16(vid); | |
6c12fcbf GR |
2616 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED | |
2617 | I40E_AQ_VSI_PVLAN_INSERT_PVID | | |
b774c7dd | 2618 | I40E_AQ_VSI_PVLAN_EMOD_STR; |
41c445ff JB |
2619 | |
2620 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2621 | ctxt.info = vsi->info; |
f1c7e72e SN |
2622 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2623 | if (ret) { | |
41c445ff | 2624 | dev_info(&vsi->back->pdev->dev, |
f1c7e72e SN |
2625 | "add pvid failed, err %s aq_err %s\n", |
2626 | i40e_stat_str(&vsi->back->hw, ret), | |
2627 | i40e_aq_str(&vsi->back->hw, | |
2628 | vsi->back->hw.aq.asq_last_status)); | |
dcae29be | 2629 | return -ENOENT; |
41c445ff JB |
2630 | } |
2631 | ||
dcae29be | 2632 | return 0; |
41c445ff JB |
2633 | } |
2634 | ||
2635 | /** | |
2636 | * i40e_vsi_remove_pvid - Remove the pvid from the VSI | |
2637 | * @vsi: the vsi being adjusted | |
2638 | * | |
2639 | * Just use the vlan_rx_register() service to put it back to normal | |
2640 | **/ | |
2641 | void i40e_vsi_remove_pvid(struct i40e_vsi *vsi) | |
2642 | { | |
6c12fcbf GR |
2643 | i40e_vlan_stripping_disable(vsi); |
2644 | ||
41c445ff | 2645 | vsi->info.pvid = 0; |
41c445ff JB |
2646 | } |
2647 | ||
2648 | /** | |
2649 | * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources | |
2650 | * @vsi: ptr to the VSI | |
2651 | * | |
2652 | * If this function returns with an error, then it's possible one or | |
2653 | * more of the rings is populated (while the rest are not). It is the | |
2654 | * callers duty to clean those orphaned rings. | |
2655 | * | |
2656 | * Return 0 on success, negative on failure | |
2657 | **/ | |
2658 | static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi) | |
2659 | { | |
2660 | int i, err = 0; | |
2661 | ||
2662 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 2663 | err = i40e_setup_tx_descriptors(vsi->tx_rings[i]); |
41c445ff JB |
2664 | |
2665 | return err; | |
2666 | } | |
2667 | ||
2668 | /** | |
2669 | * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues | |
2670 | * @vsi: ptr to the VSI | |
2671 | * | |
2672 | * Free VSI's transmit software resources | |
2673 | **/ | |
2674 | static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi) | |
2675 | { | |
2676 | int i; | |
2677 | ||
8e9dca53 GR |
2678 | if (!vsi->tx_rings) |
2679 | return; | |
2680 | ||
41c445ff | 2681 | for (i = 0; i < vsi->num_queue_pairs; i++) |
8e9dca53 | 2682 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) |
9f65e15b | 2683 | i40e_free_tx_resources(vsi->tx_rings[i]); |
41c445ff JB |
2684 | } |
2685 | ||
2686 | /** | |
2687 | * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources | |
2688 | * @vsi: ptr to the VSI | |
2689 | * | |
2690 | * If this function returns with an error, then it's possible one or | |
2691 | * more of the rings is populated (while the rest are not). It is the | |
2692 | * callers duty to clean those orphaned rings. | |
2693 | * | |
2694 | * Return 0 on success, negative on failure | |
2695 | **/ | |
2696 | static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi) | |
2697 | { | |
2698 | int i, err = 0; | |
2699 | ||
2700 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 2701 | err = i40e_setup_rx_descriptors(vsi->rx_rings[i]); |
38e00438 VD |
2702 | #ifdef I40E_FCOE |
2703 | i40e_fcoe_setup_ddp_resources(vsi); | |
2704 | #endif | |
41c445ff JB |
2705 | return err; |
2706 | } | |
2707 | ||
2708 | /** | |
2709 | * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues | |
2710 | * @vsi: ptr to the VSI | |
2711 | * | |
2712 | * Free all receive software resources | |
2713 | **/ | |
2714 | static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi) | |
2715 | { | |
2716 | int i; | |
2717 | ||
8e9dca53 GR |
2718 | if (!vsi->rx_rings) |
2719 | return; | |
2720 | ||
41c445ff | 2721 | for (i = 0; i < vsi->num_queue_pairs; i++) |
8e9dca53 | 2722 | if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc) |
9f65e15b | 2723 | i40e_free_rx_resources(vsi->rx_rings[i]); |
38e00438 VD |
2724 | #ifdef I40E_FCOE |
2725 | i40e_fcoe_free_ddp_resources(vsi); | |
2726 | #endif | |
41c445ff JB |
2727 | } |
2728 | ||
3ffa037d NP |
2729 | /** |
2730 | * i40e_config_xps_tx_ring - Configure XPS for a Tx ring | |
2731 | * @ring: The Tx ring to configure | |
2732 | * | |
2733 | * This enables/disables XPS for a given Tx descriptor ring | |
2734 | * based on the TCs enabled for the VSI that ring belongs to. | |
2735 | **/ | |
2736 | static void i40e_config_xps_tx_ring(struct i40e_ring *ring) | |
2737 | { | |
2738 | struct i40e_vsi *vsi = ring->vsi; | |
2739 | cpumask_var_t mask; | |
2740 | ||
9a660eea JB |
2741 | if (!ring->q_vector || !ring->netdev) |
2742 | return; | |
2743 | ||
2744 | /* Single TC mode enable XPS */ | |
2745 | if (vsi->tc_config.numtc <= 1) { | |
2746 | if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state)) | |
3ffa037d NP |
2747 | netif_set_xps_queue(ring->netdev, |
2748 | &ring->q_vector->affinity_mask, | |
2749 | ring->queue_index); | |
9a660eea JB |
2750 | } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) { |
2751 | /* Disable XPS to allow selection based on TC */ | |
2752 | bitmap_zero(cpumask_bits(mask), nr_cpumask_bits); | |
2753 | netif_set_xps_queue(ring->netdev, mask, ring->queue_index); | |
2754 | free_cpumask_var(mask); | |
3ffa037d | 2755 | } |
0e4425ed JB |
2756 | |
2757 | /* schedule our worker thread which will take care of | |
2758 | * applying the new filter changes | |
2759 | */ | |
2760 | i40e_service_event_schedule(vsi->back); | |
3ffa037d NP |
2761 | } |
2762 | ||
41c445ff JB |
2763 | /** |
2764 | * i40e_configure_tx_ring - Configure a transmit ring context and rest | |
2765 | * @ring: The Tx ring to configure | |
2766 | * | |
2767 | * Configure the Tx descriptor ring in the HMC context. | |
2768 | **/ | |
2769 | static int i40e_configure_tx_ring(struct i40e_ring *ring) | |
2770 | { | |
2771 | struct i40e_vsi *vsi = ring->vsi; | |
2772 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
2773 | struct i40e_hw *hw = &vsi->back->hw; | |
2774 | struct i40e_hmc_obj_txq tx_ctx; | |
2775 | i40e_status err = 0; | |
2776 | u32 qtx_ctl = 0; | |
2777 | ||
2778 | /* some ATR related tx ring init */ | |
60ea5f83 | 2779 | if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) { |
41c445ff JB |
2780 | ring->atr_sample_rate = vsi->back->atr_sample_rate; |
2781 | ring->atr_count = 0; | |
2782 | } else { | |
2783 | ring->atr_sample_rate = 0; | |
2784 | } | |
2785 | ||
3ffa037d NP |
2786 | /* configure XPS */ |
2787 | i40e_config_xps_tx_ring(ring); | |
41c445ff JB |
2788 | |
2789 | /* clear the context structure first */ | |
2790 | memset(&tx_ctx, 0, sizeof(tx_ctx)); | |
2791 | ||
2792 | tx_ctx.new_context = 1; | |
2793 | tx_ctx.base = (ring->dma / 128); | |
2794 | tx_ctx.qlen = ring->count; | |
60ea5f83 JB |
2795 | tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED | |
2796 | I40E_FLAG_FD_ATR_ENABLED)); | |
38e00438 VD |
2797 | #ifdef I40E_FCOE |
2798 | tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE); | |
2799 | #endif | |
beb0dff1 | 2800 | tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP); |
1943d8ba JB |
2801 | /* FDIR VSI tx ring can still use RS bit and writebacks */ |
2802 | if (vsi->type != I40E_VSI_FDIR) | |
2803 | tx_ctx.head_wb_ena = 1; | |
2804 | tx_ctx.head_wb_addr = ring->dma + | |
2805 | (ring->count * sizeof(struct i40e_tx_desc)); | |
41c445ff JB |
2806 | |
2807 | /* As part of VSI creation/update, FW allocates certain | |
2808 | * Tx arbitration queue sets for each TC enabled for | |
2809 | * the VSI. The FW returns the handles to these queue | |
2810 | * sets as part of the response buffer to Add VSI, | |
2811 | * Update VSI, etc. AQ commands. It is expected that | |
2812 | * these queue set handles be associated with the Tx | |
2813 | * queues by the driver as part of the TX queue context | |
2814 | * initialization. This has to be done regardless of | |
2815 | * DCB as by default everything is mapped to TC0. | |
2816 | */ | |
2817 | tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]); | |
2818 | tx_ctx.rdylist_act = 0; | |
2819 | ||
2820 | /* clear the context in the HMC */ | |
2821 | err = i40e_clear_lan_tx_queue_context(hw, pf_q); | |
2822 | if (err) { | |
2823 | dev_info(&vsi->back->pdev->dev, | |
2824 | "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n", | |
2825 | ring->queue_index, pf_q, err); | |
2826 | return -ENOMEM; | |
2827 | } | |
2828 | ||
2829 | /* set the context in the HMC */ | |
2830 | err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx); | |
2831 | if (err) { | |
2832 | dev_info(&vsi->back->pdev->dev, | |
2833 | "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n", | |
2834 | ring->queue_index, pf_q, err); | |
2835 | return -ENOMEM; | |
2836 | } | |
2837 | ||
2838 | /* Now associate this queue with this PCI function */ | |
7a28d885 | 2839 | if (vsi->type == I40E_VSI_VMDQ2) { |
9d8bf547 | 2840 | qtx_ctl = I40E_QTX_CTL_VM_QUEUE; |
7a28d885 MW |
2841 | qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) & |
2842 | I40E_QTX_CTL_VFVM_INDX_MASK; | |
2843 | } else { | |
9d8bf547 | 2844 | qtx_ctl = I40E_QTX_CTL_PF_QUEUE; |
7a28d885 MW |
2845 | } |
2846 | ||
13fd9774 SN |
2847 | qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & |
2848 | I40E_QTX_CTL_PF_INDX_MASK); | |
41c445ff JB |
2849 | wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); |
2850 | i40e_flush(hw); | |
2851 | ||
41c445ff JB |
2852 | /* cache tail off for easier writes later */ |
2853 | ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q); | |
2854 | ||
2855 | return 0; | |
2856 | } | |
2857 | ||
2858 | /** | |
2859 | * i40e_configure_rx_ring - Configure a receive ring context | |
2860 | * @ring: The Rx ring to configure | |
2861 | * | |
2862 | * Configure the Rx descriptor ring in the HMC context. | |
2863 | **/ | |
2864 | static int i40e_configure_rx_ring(struct i40e_ring *ring) | |
2865 | { | |
2866 | struct i40e_vsi *vsi = ring->vsi; | |
2867 | u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len; | |
2868 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
2869 | struct i40e_hw *hw = &vsi->back->hw; | |
2870 | struct i40e_hmc_obj_rxq rx_ctx; | |
2871 | i40e_status err = 0; | |
2872 | ||
2873 | ring->state = 0; | |
2874 | ||
2875 | /* clear the context structure first */ | |
2876 | memset(&rx_ctx, 0, sizeof(rx_ctx)); | |
2877 | ||
2878 | ring->rx_buf_len = vsi->rx_buf_len; | |
41c445ff JB |
2879 | |
2880 | rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT; | |
41c445ff JB |
2881 | |
2882 | rx_ctx.base = (ring->dma / 128); | |
2883 | rx_ctx.qlen = ring->count; | |
2884 | ||
bec60fc4 JB |
2885 | /* use 32 byte descriptors */ |
2886 | rx_ctx.dsize = 1; | |
41c445ff | 2887 | |
bec60fc4 JB |
2888 | /* descriptor type is always zero |
2889 | * rx_ctx.dtype = 0; | |
2890 | */ | |
b32bfa17 | 2891 | rx_ctx.hsplit_0 = 0; |
41c445ff | 2892 | |
b32bfa17 | 2893 | rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len); |
7134f9ce JB |
2894 | if (hw->revision_id == 0) |
2895 | rx_ctx.lrxqthresh = 0; | |
2896 | else | |
2897 | rx_ctx.lrxqthresh = 2; | |
41c445ff JB |
2898 | rx_ctx.crcstrip = 1; |
2899 | rx_ctx.l2tsel = 1; | |
c4bbac39 JB |
2900 | /* this controls whether VLAN is stripped from inner headers */ |
2901 | rx_ctx.showiv = 0; | |
38e00438 VD |
2902 | #ifdef I40E_FCOE |
2903 | rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE); | |
2904 | #endif | |
acb3676b CS |
2905 | /* set the prefena field to 1 because the manual says to */ |
2906 | rx_ctx.prefena = 1; | |
41c445ff JB |
2907 | |
2908 | /* clear the context in the HMC */ | |
2909 | err = i40e_clear_lan_rx_queue_context(hw, pf_q); | |
2910 | if (err) { | |
2911 | dev_info(&vsi->back->pdev->dev, | |
2912 | "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
2913 | ring->queue_index, pf_q, err); | |
2914 | return -ENOMEM; | |
2915 | } | |
2916 | ||
2917 | /* set the context in the HMC */ | |
2918 | err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx); | |
2919 | if (err) { | |
2920 | dev_info(&vsi->back->pdev->dev, | |
2921 | "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
2922 | ring->queue_index, pf_q, err); | |
2923 | return -ENOMEM; | |
2924 | } | |
2925 | ||
2926 | /* cache tail for quicker writes, and clear the reg before use */ | |
2927 | ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q); | |
2928 | writel(0, ring->tail); | |
2929 | ||
1a557afc | 2930 | i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring)); |
41c445ff JB |
2931 | |
2932 | return 0; | |
2933 | } | |
2934 | ||
2935 | /** | |
2936 | * i40e_vsi_configure_tx - Configure the VSI for Tx | |
2937 | * @vsi: VSI structure describing this set of rings and resources | |
2938 | * | |
2939 | * Configure the Tx VSI for operation. | |
2940 | **/ | |
2941 | static int i40e_vsi_configure_tx(struct i40e_vsi *vsi) | |
2942 | { | |
2943 | int err = 0; | |
2944 | u16 i; | |
2945 | ||
9f65e15b AD |
2946 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) |
2947 | err = i40e_configure_tx_ring(vsi->tx_rings[i]); | |
41c445ff JB |
2948 | |
2949 | return err; | |
2950 | } | |
2951 | ||
2952 | /** | |
2953 | * i40e_vsi_configure_rx - Configure the VSI for Rx | |
2954 | * @vsi: the VSI being configured | |
2955 | * | |
2956 | * Configure the Rx VSI for operation. | |
2957 | **/ | |
2958 | static int i40e_vsi_configure_rx(struct i40e_vsi *vsi) | |
2959 | { | |
2960 | int err = 0; | |
2961 | u16 i; | |
2962 | ||
2963 | if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN)) | |
2964 | vsi->max_frame = vsi->netdev->mtu + ETH_HLEN | |
2965 | + ETH_FCS_LEN + VLAN_HLEN; | |
2966 | else | |
2967 | vsi->max_frame = I40E_RXBUFFER_2048; | |
2968 | ||
1a557afc | 2969 | vsi->rx_buf_len = I40E_RXBUFFER_2048; |
41c445ff | 2970 | |
38e00438 VD |
2971 | #ifdef I40E_FCOE |
2972 | /* setup rx buffer for FCoE */ | |
2973 | if ((vsi->type == I40E_VSI_FCOE) && | |
2974 | (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) { | |
38e00438 VD |
2975 | vsi->rx_buf_len = I40E_RXBUFFER_3072; |
2976 | vsi->max_frame = I40E_RXBUFFER_3072; | |
38e00438 VD |
2977 | } |
2978 | ||
2979 | #endif /* I40E_FCOE */ | |
41c445ff | 2980 | /* round up for the chip's needs */ |
41c445ff | 2981 | vsi->rx_buf_len = ALIGN(vsi->rx_buf_len, |
41a1d04b | 2982 | BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT)); |
41c445ff JB |
2983 | |
2984 | /* set up individual rings */ | |
2985 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 2986 | err = i40e_configure_rx_ring(vsi->rx_rings[i]); |
41c445ff JB |
2987 | |
2988 | return err; | |
2989 | } | |
2990 | ||
2991 | /** | |
2992 | * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC | |
2993 | * @vsi: ptr to the VSI | |
2994 | **/ | |
2995 | static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi) | |
2996 | { | |
e7046ee1 | 2997 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff JB |
2998 | u16 qoffset, qcount; |
2999 | int i, n; | |
3000 | ||
cd238a3e PN |
3001 | if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { |
3002 | /* Reset the TC information */ | |
3003 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
3004 | rx_ring = vsi->rx_rings[i]; | |
3005 | tx_ring = vsi->tx_rings[i]; | |
3006 | rx_ring->dcb_tc = 0; | |
3007 | tx_ring->dcb_tc = 0; | |
3008 | } | |
3009 | } | |
41c445ff JB |
3010 | |
3011 | for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) { | |
41a1d04b | 3012 | if (!(vsi->tc_config.enabled_tc & BIT_ULL(n))) |
41c445ff JB |
3013 | continue; |
3014 | ||
3015 | qoffset = vsi->tc_config.tc_info[n].qoffset; | |
3016 | qcount = vsi->tc_config.tc_info[n].qcount; | |
3017 | for (i = qoffset; i < (qoffset + qcount); i++) { | |
e7046ee1 AA |
3018 | rx_ring = vsi->rx_rings[i]; |
3019 | tx_ring = vsi->tx_rings[i]; | |
41c445ff JB |
3020 | rx_ring->dcb_tc = n; |
3021 | tx_ring->dcb_tc = n; | |
3022 | } | |
3023 | } | |
3024 | } | |
3025 | ||
3026 | /** | |
3027 | * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI | |
3028 | * @vsi: ptr to the VSI | |
3029 | **/ | |
3030 | static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi) | |
3031 | { | |
3032 | if (vsi->netdev) | |
3033 | i40e_set_rx_mode(vsi->netdev); | |
3034 | } | |
3035 | ||
17a73f6b JG |
3036 | /** |
3037 | * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters | |
3038 | * @vsi: Pointer to the targeted VSI | |
3039 | * | |
3040 | * This function replays the hlist on the hw where all the SB Flow Director | |
3041 | * filters were saved. | |
3042 | **/ | |
3043 | static void i40e_fdir_filter_restore(struct i40e_vsi *vsi) | |
3044 | { | |
3045 | struct i40e_fdir_filter *filter; | |
3046 | struct i40e_pf *pf = vsi->back; | |
3047 | struct hlist_node *node; | |
3048 | ||
55a5e60b ASJ |
3049 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
3050 | return; | |
3051 | ||
17a73f6b JG |
3052 | hlist_for_each_entry_safe(filter, node, |
3053 | &pf->fdir_filter_list, fdir_node) { | |
3054 | i40e_add_del_fdir(vsi, filter, true); | |
3055 | } | |
3056 | } | |
3057 | ||
41c445ff JB |
3058 | /** |
3059 | * i40e_vsi_configure - Set up the VSI for action | |
3060 | * @vsi: the VSI being configured | |
3061 | **/ | |
3062 | static int i40e_vsi_configure(struct i40e_vsi *vsi) | |
3063 | { | |
3064 | int err; | |
3065 | ||
3066 | i40e_set_vsi_rx_mode(vsi); | |
3067 | i40e_restore_vlan(vsi); | |
3068 | i40e_vsi_config_dcb_rings(vsi); | |
3069 | err = i40e_vsi_configure_tx(vsi); | |
3070 | if (!err) | |
3071 | err = i40e_vsi_configure_rx(vsi); | |
3072 | ||
3073 | return err; | |
3074 | } | |
3075 | ||
3076 | /** | |
3077 | * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW | |
3078 | * @vsi: the VSI being configured | |
3079 | **/ | |
3080 | static void i40e_vsi_configure_msix(struct i40e_vsi *vsi) | |
3081 | { | |
3082 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
3083 | struct i40e_hw *hw = &pf->hw; |
3084 | u16 vector; | |
3085 | int i, q; | |
41c445ff JB |
3086 | u32 qp; |
3087 | ||
3088 | /* The interrupt indexing is offset by 1 in the PFINT_ITRn | |
3089 | * and PFINT_LNKLSTn registers, e.g.: | |
3090 | * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts) | |
3091 | */ | |
3092 | qp = vsi->base_queue; | |
3093 | vector = vsi->base_vector; | |
493fb300 | 3094 | for (i = 0; i < vsi->num_q_vectors; i++, vector++) { |
ac26fc13 JB |
3095 | struct i40e_q_vector *q_vector = vsi->q_vectors[i]; |
3096 | ||
ee2319cf | 3097 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
a75e8005 | 3098 | q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting); |
41c445ff JB |
3099 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
3100 | wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), | |
3101 | q_vector->rx.itr); | |
a75e8005 | 3102 | q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting); |
41c445ff JB |
3103 | q_vector->tx.latency_range = I40E_LOW_LATENCY; |
3104 | wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), | |
3105 | q_vector->tx.itr); | |
ac26fc13 JB |
3106 | wr32(hw, I40E_PFINT_RATEN(vector - 1), |
3107 | INTRL_USEC_TO_REG(vsi->int_rate_limit)); | |
41c445ff JB |
3108 | |
3109 | /* Linked list for the queuepairs assigned to this vector */ | |
3110 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp); | |
3111 | for (q = 0; q < q_vector->num_ringpairs; q++) { | |
ac26fc13 JB |
3112 | u32 val; |
3113 | ||
41c445ff JB |
3114 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
3115 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | |
3116 | (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | | |
3117 | (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)| | |
3118 | (I40E_QUEUE_TYPE_TX | |
3119 | << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); | |
3120 | ||
3121 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
3122 | ||
3123 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3124 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3125 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3126 | ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)| | |
3127 | (I40E_QUEUE_TYPE_RX | |
3128 | << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3129 | ||
3130 | /* Terminate the linked list */ | |
3131 | if (q == (q_vector->num_ringpairs - 1)) | |
3132 | val |= (I40E_QUEUE_END_OF_LIST | |
3133 | << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
3134 | ||
3135 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
3136 | qp++; | |
3137 | } | |
3138 | } | |
3139 | ||
3140 | i40e_flush(hw); | |
3141 | } | |
3142 | ||
3143 | /** | |
3144 | * i40e_enable_misc_int_causes - enable the non-queue interrupts | |
3145 | * @hw: ptr to the hardware info | |
3146 | **/ | |
ab437b5a | 3147 | static void i40e_enable_misc_int_causes(struct i40e_pf *pf) |
41c445ff | 3148 | { |
ab437b5a | 3149 | struct i40e_hw *hw = &pf->hw; |
41c445ff JB |
3150 | u32 val; |
3151 | ||
3152 | /* clear things first */ | |
3153 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ | |
3154 | rd32(hw, I40E_PFINT_ICR0); /* read to clear */ | |
3155 | ||
3156 | val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | | |
3157 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | | |
3158 | I40E_PFINT_ICR0_ENA_GRST_MASK | | |
3159 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | | |
3160 | I40E_PFINT_ICR0_ENA_GPIO_MASK | | |
41c445ff JB |
3161 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | |
3162 | I40E_PFINT_ICR0_ENA_VFLR_MASK | | |
3163 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
3164 | ||
0d8e1439 ASJ |
3165 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) |
3166 | val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
3167 | ||
ab437b5a JK |
3168 | if (pf->flags & I40E_FLAG_PTP) |
3169 | val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; | |
3170 | ||
41c445ff JB |
3171 | wr32(hw, I40E_PFINT_ICR0_ENA, val); |
3172 | ||
3173 | /* SW_ITR_IDX = 0, but don't change INTENA */ | |
84ed40e7 ASJ |
3174 | wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | |
3175 | I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); | |
41c445ff JB |
3176 | |
3177 | /* OTHER_ITR_IDX = 0 */ | |
3178 | wr32(hw, I40E_PFINT_STAT_CTL0, 0); | |
3179 | } | |
3180 | ||
3181 | /** | |
3182 | * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW | |
3183 | * @vsi: the VSI being configured | |
3184 | **/ | |
3185 | static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi) | |
3186 | { | |
493fb300 | 3187 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; |
41c445ff JB |
3188 | struct i40e_pf *pf = vsi->back; |
3189 | struct i40e_hw *hw = &pf->hw; | |
3190 | u32 val; | |
3191 | ||
3192 | /* set the ITR configuration */ | |
ee2319cf | 3193 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
a75e8005 | 3194 | q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting); |
41c445ff JB |
3195 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
3196 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr); | |
a75e8005 | 3197 | q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting); |
41c445ff JB |
3198 | q_vector->tx.latency_range = I40E_LOW_LATENCY; |
3199 | wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr); | |
3200 | ||
ab437b5a | 3201 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
3202 | |
3203 | /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ | |
3204 | wr32(hw, I40E_PFINT_LNKLST0, 0); | |
3205 | ||
f29eaa3d | 3206 | /* Associate the queue pair to the vector and enable the queue int */ |
41c445ff JB |
3207 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
3208 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | |
3209 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3210 | ||
3211 | wr32(hw, I40E_QINT_RQCTL(0), val); | |
3212 | ||
3213 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3214 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3215 | (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
3216 | ||
3217 | wr32(hw, I40E_QINT_TQCTL(0), val); | |
3218 | i40e_flush(hw); | |
3219 | } | |
3220 | ||
2ef28cfb MW |
3221 | /** |
3222 | * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0 | |
3223 | * @pf: board private structure | |
3224 | **/ | |
3225 | void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf) | |
3226 | { | |
3227 | struct i40e_hw *hw = &pf->hw; | |
3228 | ||
3229 | wr32(hw, I40E_PFINT_DYN_CTL0, | |
3230 | I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); | |
3231 | i40e_flush(hw); | |
3232 | } | |
3233 | ||
41c445ff JB |
3234 | /** |
3235 | * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0 | |
3236 | * @pf: board private structure | |
40d72a50 | 3237 | * @clearpba: true when all pending interrupt events should be cleared |
41c445ff | 3238 | **/ |
40d72a50 | 3239 | void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba) |
41c445ff JB |
3240 | { |
3241 | struct i40e_hw *hw = &pf->hw; | |
3242 | u32 val; | |
3243 | ||
3244 | val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
40d72a50 | 3245 | (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) | |
41c445ff JB |
3246 | (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); |
3247 | ||
3248 | wr32(hw, I40E_PFINT_DYN_CTL0, val); | |
3249 | i40e_flush(hw); | |
3250 | } | |
3251 | ||
41c445ff JB |
3252 | /** |
3253 | * i40e_msix_clean_rings - MSIX mode Interrupt Handler | |
3254 | * @irq: interrupt number | |
3255 | * @data: pointer to a q_vector | |
3256 | **/ | |
3257 | static irqreturn_t i40e_msix_clean_rings(int irq, void *data) | |
3258 | { | |
3259 | struct i40e_q_vector *q_vector = data; | |
3260 | ||
cd0b6fa6 | 3261 | if (!q_vector->tx.ring && !q_vector->rx.ring) |
41c445ff JB |
3262 | return IRQ_HANDLED; |
3263 | ||
5d3465a1 | 3264 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3265 | |
3266 | return IRQ_HANDLED; | |
3267 | } | |
3268 | ||
41c445ff JB |
3269 | /** |
3270 | * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts | |
3271 | * @vsi: the VSI being configured | |
3272 | * @basename: name for the vector | |
3273 | * | |
3274 | * Allocates MSI-X vectors and requests interrupts from the kernel. | |
3275 | **/ | |
3276 | static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename) | |
3277 | { | |
3278 | int q_vectors = vsi->num_q_vectors; | |
3279 | struct i40e_pf *pf = vsi->back; | |
3280 | int base = vsi->base_vector; | |
3281 | int rx_int_idx = 0; | |
3282 | int tx_int_idx = 0; | |
3283 | int vector, err; | |
3284 | ||
3285 | for (vector = 0; vector < q_vectors; vector++) { | |
493fb300 | 3286 | struct i40e_q_vector *q_vector = vsi->q_vectors[vector]; |
41c445ff | 3287 | |
cd0b6fa6 | 3288 | if (q_vector->tx.ring && q_vector->rx.ring) { |
41c445ff JB |
3289 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3290 | "%s-%s-%d", basename, "TxRx", rx_int_idx++); | |
3291 | tx_int_idx++; | |
cd0b6fa6 | 3292 | } else if (q_vector->rx.ring) { |
41c445ff JB |
3293 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3294 | "%s-%s-%d", basename, "rx", rx_int_idx++); | |
cd0b6fa6 | 3295 | } else if (q_vector->tx.ring) { |
41c445ff JB |
3296 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3297 | "%s-%s-%d", basename, "tx", tx_int_idx++); | |
3298 | } else { | |
3299 | /* skip this unused q_vector */ | |
3300 | continue; | |
3301 | } | |
3302 | err = request_irq(pf->msix_entries[base + vector].vector, | |
3303 | vsi->irq_handler, | |
3304 | 0, | |
3305 | q_vector->name, | |
3306 | q_vector); | |
3307 | if (err) { | |
3308 | dev_info(&pf->pdev->dev, | |
fb43201f | 3309 | "MSIX request_irq failed, error: %d\n", err); |
41c445ff JB |
3310 | goto free_queue_irqs; |
3311 | } | |
3312 | /* assign the mask for this irq */ | |
3313 | irq_set_affinity_hint(pf->msix_entries[base + vector].vector, | |
3314 | &q_vector->affinity_mask); | |
3315 | } | |
3316 | ||
63741846 | 3317 | vsi->irqs_ready = true; |
41c445ff JB |
3318 | return 0; |
3319 | ||
3320 | free_queue_irqs: | |
3321 | while (vector) { | |
3322 | vector--; | |
3323 | irq_set_affinity_hint(pf->msix_entries[base + vector].vector, | |
3324 | NULL); | |
3325 | free_irq(pf->msix_entries[base + vector].vector, | |
3326 | &(vsi->q_vectors[vector])); | |
3327 | } | |
3328 | return err; | |
3329 | } | |
3330 | ||
3331 | /** | |
3332 | * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI | |
3333 | * @vsi: the VSI being un-configured | |
3334 | **/ | |
3335 | static void i40e_vsi_disable_irq(struct i40e_vsi *vsi) | |
3336 | { | |
3337 | struct i40e_pf *pf = vsi->back; | |
3338 | struct i40e_hw *hw = &pf->hw; | |
3339 | int base = vsi->base_vector; | |
3340 | int i; | |
3341 | ||
3342 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
9f65e15b AD |
3343 | wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0); |
3344 | wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0); | |
41c445ff JB |
3345 | } |
3346 | ||
3347 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
3348 | for (i = vsi->base_vector; | |
3349 | i < (vsi->num_q_vectors + vsi->base_vector); i++) | |
3350 | wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0); | |
3351 | ||
3352 | i40e_flush(hw); | |
3353 | for (i = 0; i < vsi->num_q_vectors; i++) | |
3354 | synchronize_irq(pf->msix_entries[i + base].vector); | |
3355 | } else { | |
3356 | /* Legacy and MSI mode - this stops all interrupt handling */ | |
3357 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); | |
3358 | wr32(hw, I40E_PFINT_DYN_CTL0, 0); | |
3359 | i40e_flush(hw); | |
3360 | synchronize_irq(pf->pdev->irq); | |
3361 | } | |
3362 | } | |
3363 | ||
3364 | /** | |
3365 | * i40e_vsi_enable_irq - Enable IRQ for the given VSI | |
3366 | * @vsi: the VSI being configured | |
3367 | **/ | |
3368 | static int i40e_vsi_enable_irq(struct i40e_vsi *vsi) | |
3369 | { | |
3370 | struct i40e_pf *pf = vsi->back; | |
3371 | int i; | |
3372 | ||
3373 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
7845548d | 3374 | for (i = 0; i < vsi->num_q_vectors; i++) |
41c445ff JB |
3375 | i40e_irq_dynamic_enable(vsi, i); |
3376 | } else { | |
40d72a50 | 3377 | i40e_irq_dynamic_enable_icr0(pf, true); |
41c445ff JB |
3378 | } |
3379 | ||
1022cb6c | 3380 | i40e_flush(&pf->hw); |
41c445ff JB |
3381 | return 0; |
3382 | } | |
3383 | ||
3384 | /** | |
3385 | * i40e_stop_misc_vector - Stop the vector that handles non-queue events | |
3386 | * @pf: board private structure | |
3387 | **/ | |
3388 | static void i40e_stop_misc_vector(struct i40e_pf *pf) | |
3389 | { | |
3390 | /* Disable ICR 0 */ | |
3391 | wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0); | |
3392 | i40e_flush(&pf->hw); | |
3393 | } | |
3394 | ||
3395 | /** | |
3396 | * i40e_intr - MSI/Legacy and non-queue interrupt handler | |
3397 | * @irq: interrupt number | |
3398 | * @data: pointer to a q_vector | |
3399 | * | |
3400 | * This is the handler used for all MSI/Legacy interrupts, and deals | |
3401 | * with both queue and non-queue interrupts. This is also used in | |
3402 | * MSIX mode to handle the non-queue interrupts. | |
3403 | **/ | |
3404 | static irqreturn_t i40e_intr(int irq, void *data) | |
3405 | { | |
3406 | struct i40e_pf *pf = (struct i40e_pf *)data; | |
3407 | struct i40e_hw *hw = &pf->hw; | |
5e823066 | 3408 | irqreturn_t ret = IRQ_NONE; |
41c445ff JB |
3409 | u32 icr0, icr0_remaining; |
3410 | u32 val, ena_mask; | |
3411 | ||
3412 | icr0 = rd32(hw, I40E_PFINT_ICR0); | |
5e823066 | 3413 | ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA); |
41c445ff | 3414 | |
116a57d4 SN |
3415 | /* if sharing a legacy IRQ, we might get called w/o an intr pending */ |
3416 | if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0) | |
5e823066 | 3417 | goto enable_intr; |
41c445ff | 3418 | |
cd92e72f SN |
3419 | /* if interrupt but no bits showing, must be SWINT */ |
3420 | if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) || | |
3421 | (icr0 & I40E_PFINT_ICR0_SWINT_MASK)) | |
3422 | pf->sw_int_count++; | |
3423 | ||
0d8e1439 ASJ |
3424 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && |
3425 | (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) { | |
3426 | ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
3427 | icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
3428 | dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n"); | |
3429 | } | |
3430 | ||
41c445ff JB |
3431 | /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */ |
3432 | if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) { | |
5d3465a1 AD |
3433 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
3434 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; | |
41c445ff | 3435 | |
a16ae2d5 ASJ |
3436 | /* We do not have a way to disarm Queue causes while leaving |
3437 | * interrupt enabled for all other causes, ideally | |
3438 | * interrupt should be disabled while we are in NAPI but | |
3439 | * this is not a performance path and napi_schedule() | |
3440 | * can deal with rescheduling. | |
3441 | */ | |
41c445ff | 3442 | if (!test_bit(__I40E_DOWN, &pf->state)) |
5d3465a1 | 3443 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3444 | } |
3445 | ||
3446 | if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { | |
3447 | ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
3448 | set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state); | |
6e93d0c9 | 3449 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n"); |
41c445ff JB |
3450 | } |
3451 | ||
3452 | if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) { | |
3453 | ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
3454 | set_bit(__I40E_MDD_EVENT_PENDING, &pf->state); | |
3455 | } | |
3456 | ||
3457 | if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { | |
3458 | ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; | |
3459 | set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state); | |
3460 | } | |
3461 | ||
3462 | if (icr0 & I40E_PFINT_ICR0_GRST_MASK) { | |
3463 | if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) | |
3464 | set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state); | |
3465 | ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK; | |
3466 | val = rd32(hw, I40E_GLGEN_RSTAT); | |
3467 | val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK) | |
3468 | >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; | |
4eb3f768 | 3469 | if (val == I40E_RESET_CORER) { |
41c445ff | 3470 | pf->corer_count++; |
4eb3f768 | 3471 | } else if (val == I40E_RESET_GLOBR) { |
41c445ff | 3472 | pf->globr_count++; |
4eb3f768 | 3473 | } else if (val == I40E_RESET_EMPR) { |
41c445ff | 3474 | pf->empr_count++; |
9df42d1a | 3475 | set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state); |
4eb3f768 | 3476 | } |
41c445ff JB |
3477 | } |
3478 | ||
9c010ee0 ASJ |
3479 | if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) { |
3480 | icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK; | |
3481 | dev_info(&pf->pdev->dev, "HMC error interrupt\n"); | |
25fc0e65 ASJ |
3482 | dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n", |
3483 | rd32(hw, I40E_PFHMC_ERRORINFO), | |
3484 | rd32(hw, I40E_PFHMC_ERRORDATA)); | |
9c010ee0 ASJ |
3485 | } |
3486 | ||
beb0dff1 JK |
3487 | if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) { |
3488 | u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0); | |
3489 | ||
3490 | if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) { | |
cafa1fca | 3491 | icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; |
beb0dff1 | 3492 | i40e_ptp_tx_hwtstamp(pf); |
beb0dff1 | 3493 | } |
beb0dff1 JK |
3494 | } |
3495 | ||
41c445ff JB |
3496 | /* If a critical error is pending we have no choice but to reset the |
3497 | * device. | |
3498 | * Report and mask out any remaining unexpected interrupts. | |
3499 | */ | |
3500 | icr0_remaining = icr0 & ena_mask; | |
3501 | if (icr0_remaining) { | |
3502 | dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n", | |
3503 | icr0_remaining); | |
9c010ee0 | 3504 | if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) || |
41c445ff | 3505 | (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) || |
c0c28975 | 3506 | (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) { |
9c010ee0 ASJ |
3507 | dev_info(&pf->pdev->dev, "device will be reset\n"); |
3508 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
3509 | i40e_service_event_schedule(pf); | |
41c445ff JB |
3510 | } |
3511 | ena_mask &= ~icr0_remaining; | |
3512 | } | |
5e823066 | 3513 | ret = IRQ_HANDLED; |
41c445ff | 3514 | |
5e823066 | 3515 | enable_intr: |
41c445ff JB |
3516 | /* re-enable interrupt causes */ |
3517 | wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask); | |
41c445ff JB |
3518 | if (!test_bit(__I40E_DOWN, &pf->state)) { |
3519 | i40e_service_event_schedule(pf); | |
40d72a50 | 3520 | i40e_irq_dynamic_enable_icr0(pf, false); |
41c445ff JB |
3521 | } |
3522 | ||
5e823066 | 3523 | return ret; |
41c445ff JB |
3524 | } |
3525 | ||
cbf61325 ASJ |
3526 | /** |
3527 | * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes | |
3528 | * @tx_ring: tx ring to clean | |
3529 | * @budget: how many cleans we're allowed | |
3530 | * | |
3531 | * Returns true if there's any budget left (e.g. the clean is finished) | |
3532 | **/ | |
3533 | static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget) | |
3534 | { | |
3535 | struct i40e_vsi *vsi = tx_ring->vsi; | |
3536 | u16 i = tx_ring->next_to_clean; | |
3537 | struct i40e_tx_buffer *tx_buf; | |
3538 | struct i40e_tx_desc *tx_desc; | |
3539 | ||
3540 | tx_buf = &tx_ring->tx_bi[i]; | |
3541 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
3542 | i -= tx_ring->count; | |
3543 | ||
3544 | do { | |
3545 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
3546 | ||
3547 | /* if next_to_watch is not set then there is no work pending */ | |
3548 | if (!eop_desc) | |
3549 | break; | |
3550 | ||
3551 | /* prevent any other reads prior to eop_desc */ | |
3552 | read_barrier_depends(); | |
3553 | ||
3554 | /* if the descriptor isn't done, no work yet to do */ | |
3555 | if (!(eop_desc->cmd_type_offset_bsz & | |
3556 | cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) | |
3557 | break; | |
3558 | ||
3559 | /* clear next_to_watch to prevent false hangs */ | |
3560 | tx_buf->next_to_watch = NULL; | |
3561 | ||
49d7d933 ASJ |
3562 | tx_desc->buffer_addr = 0; |
3563 | tx_desc->cmd_type_offset_bsz = 0; | |
3564 | /* move past filter desc */ | |
3565 | tx_buf++; | |
3566 | tx_desc++; | |
3567 | i++; | |
3568 | if (unlikely(!i)) { | |
3569 | i -= tx_ring->count; | |
3570 | tx_buf = tx_ring->tx_bi; | |
3571 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
3572 | } | |
cbf61325 ASJ |
3573 | /* unmap skb header data */ |
3574 | dma_unmap_single(tx_ring->dev, | |
3575 | dma_unmap_addr(tx_buf, dma), | |
3576 | dma_unmap_len(tx_buf, len), | |
3577 | DMA_TO_DEVICE); | |
49d7d933 ASJ |
3578 | if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB) |
3579 | kfree(tx_buf->raw_buf); | |
cbf61325 | 3580 | |
49d7d933 ASJ |
3581 | tx_buf->raw_buf = NULL; |
3582 | tx_buf->tx_flags = 0; | |
3583 | tx_buf->next_to_watch = NULL; | |
cbf61325 | 3584 | dma_unmap_len_set(tx_buf, len, 0); |
49d7d933 ASJ |
3585 | tx_desc->buffer_addr = 0; |
3586 | tx_desc->cmd_type_offset_bsz = 0; | |
cbf61325 | 3587 | |
49d7d933 | 3588 | /* move us past the eop_desc for start of next FD desc */ |
cbf61325 ASJ |
3589 | tx_buf++; |
3590 | tx_desc++; | |
3591 | i++; | |
3592 | if (unlikely(!i)) { | |
3593 | i -= tx_ring->count; | |
3594 | tx_buf = tx_ring->tx_bi; | |
3595 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
3596 | } | |
3597 | ||
3598 | /* update budget accounting */ | |
3599 | budget--; | |
3600 | } while (likely(budget)); | |
3601 | ||
3602 | i += tx_ring->count; | |
3603 | tx_ring->next_to_clean = i; | |
3604 | ||
6995b36c | 3605 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) |
7845548d | 3606 | i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx); |
6995b36c | 3607 | |
cbf61325 ASJ |
3608 | return budget > 0; |
3609 | } | |
3610 | ||
3611 | /** | |
3612 | * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring | |
3613 | * @irq: interrupt number | |
3614 | * @data: pointer to a q_vector | |
3615 | **/ | |
3616 | static irqreturn_t i40e_fdir_clean_ring(int irq, void *data) | |
3617 | { | |
3618 | struct i40e_q_vector *q_vector = data; | |
3619 | struct i40e_vsi *vsi; | |
3620 | ||
3621 | if (!q_vector->tx.ring) | |
3622 | return IRQ_HANDLED; | |
3623 | ||
3624 | vsi = q_vector->tx.ring->vsi; | |
3625 | i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit); | |
3626 | ||
3627 | return IRQ_HANDLED; | |
3628 | } | |
3629 | ||
41c445ff | 3630 | /** |
cd0b6fa6 | 3631 | * i40e_map_vector_to_qp - Assigns the queue pair to the vector |
41c445ff JB |
3632 | * @vsi: the VSI being configured |
3633 | * @v_idx: vector index | |
cd0b6fa6 | 3634 | * @qp_idx: queue pair index |
41c445ff | 3635 | **/ |
26cdc443 | 3636 | static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx) |
41c445ff | 3637 | { |
493fb300 | 3638 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; |
9f65e15b AD |
3639 | struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx]; |
3640 | struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx]; | |
41c445ff JB |
3641 | |
3642 | tx_ring->q_vector = q_vector; | |
cd0b6fa6 AD |
3643 | tx_ring->next = q_vector->tx.ring; |
3644 | q_vector->tx.ring = tx_ring; | |
41c445ff | 3645 | q_vector->tx.count++; |
cd0b6fa6 AD |
3646 | |
3647 | rx_ring->q_vector = q_vector; | |
3648 | rx_ring->next = q_vector->rx.ring; | |
3649 | q_vector->rx.ring = rx_ring; | |
3650 | q_vector->rx.count++; | |
41c445ff JB |
3651 | } |
3652 | ||
3653 | /** | |
3654 | * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors | |
3655 | * @vsi: the VSI being configured | |
3656 | * | |
3657 | * This function maps descriptor rings to the queue-specific vectors | |
3658 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
3659 | * one vector per queue pair, but on a constrained vector budget, we | |
3660 | * group the queue pairs as "efficiently" as possible. | |
3661 | **/ | |
3662 | static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi) | |
3663 | { | |
3664 | int qp_remaining = vsi->num_queue_pairs; | |
3665 | int q_vectors = vsi->num_q_vectors; | |
cd0b6fa6 | 3666 | int num_ringpairs; |
41c445ff JB |
3667 | int v_start = 0; |
3668 | int qp_idx = 0; | |
3669 | ||
3670 | /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to | |
3671 | * group them so there are multiple queues per vector. | |
70114ec4 ASJ |
3672 | * It is also important to go through all the vectors available to be |
3673 | * sure that if we don't use all the vectors, that the remaining vectors | |
3674 | * are cleared. This is especially important when decreasing the | |
3675 | * number of queues in use. | |
41c445ff | 3676 | */ |
70114ec4 | 3677 | for (; v_start < q_vectors; v_start++) { |
cd0b6fa6 AD |
3678 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_start]; |
3679 | ||
3680 | num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start); | |
3681 | ||
3682 | q_vector->num_ringpairs = num_ringpairs; | |
3683 | ||
3684 | q_vector->rx.count = 0; | |
3685 | q_vector->tx.count = 0; | |
3686 | q_vector->rx.ring = NULL; | |
3687 | q_vector->tx.ring = NULL; | |
3688 | ||
3689 | while (num_ringpairs--) { | |
26cdc443 | 3690 | i40e_map_vector_to_qp(vsi, v_start, qp_idx); |
cd0b6fa6 AD |
3691 | qp_idx++; |
3692 | qp_remaining--; | |
41c445ff JB |
3693 | } |
3694 | } | |
3695 | } | |
3696 | ||
3697 | /** | |
3698 | * i40e_vsi_request_irq - Request IRQ from the OS | |
3699 | * @vsi: the VSI being configured | |
3700 | * @basename: name for the vector | |
3701 | **/ | |
3702 | static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename) | |
3703 | { | |
3704 | struct i40e_pf *pf = vsi->back; | |
3705 | int err; | |
3706 | ||
3707 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
3708 | err = i40e_vsi_request_irq_msix(vsi, basename); | |
3709 | else if (pf->flags & I40E_FLAG_MSI_ENABLED) | |
3710 | err = request_irq(pf->pdev->irq, i40e_intr, 0, | |
b294ac70 | 3711 | pf->int_name, pf); |
41c445ff JB |
3712 | else |
3713 | err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED, | |
b294ac70 | 3714 | pf->int_name, pf); |
41c445ff JB |
3715 | |
3716 | if (err) | |
3717 | dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err); | |
3718 | ||
3719 | return err; | |
3720 | } | |
3721 | ||
3722 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3723 | /** | |
d89d967f | 3724 | * i40e_netpoll - A Polling 'interrupt' handler |
41c445ff JB |
3725 | * @netdev: network interface device structure |
3726 | * | |
3727 | * This is used by netconsole to send skbs without having to re-enable | |
3728 | * interrupts. It's not called while the normal interrupt routine is executing. | |
3729 | **/ | |
38e00438 VD |
3730 | #ifdef I40E_FCOE |
3731 | void i40e_netpoll(struct net_device *netdev) | |
3732 | #else | |
41c445ff | 3733 | static void i40e_netpoll(struct net_device *netdev) |
38e00438 | 3734 | #endif |
41c445ff JB |
3735 | { |
3736 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
3737 | struct i40e_vsi *vsi = np->vsi; | |
3738 | struct i40e_pf *pf = vsi->back; | |
3739 | int i; | |
3740 | ||
3741 | /* if interface is down do nothing */ | |
3742 | if (test_bit(__I40E_DOWN, &vsi->state)) | |
3743 | return; | |
3744 | ||
41c445ff JB |
3745 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
3746 | for (i = 0; i < vsi->num_q_vectors; i++) | |
493fb300 | 3747 | i40e_msix_clean_rings(0, vsi->q_vectors[i]); |
41c445ff JB |
3748 | } else { |
3749 | i40e_intr(pf->pdev->irq, netdev); | |
3750 | } | |
41c445ff JB |
3751 | } |
3752 | #endif | |
3753 | ||
23527308 NP |
3754 | /** |
3755 | * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled | |
3756 | * @pf: the PF being configured | |
3757 | * @pf_q: the PF queue | |
3758 | * @enable: enable or disable state of the queue | |
3759 | * | |
3760 | * This routine will wait for the given Tx queue of the PF to reach the | |
3761 | * enabled or disabled state. | |
3762 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
3763 | * multiple retries; else will return 0 in case of success. | |
3764 | **/ | |
3765 | static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
3766 | { | |
3767 | int i; | |
3768 | u32 tx_reg; | |
3769 | ||
3770 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
3771 | tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q)); | |
3772 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
3773 | break; | |
3774 | ||
f98a2006 | 3775 | usleep_range(10, 20); |
23527308 NP |
3776 | } |
3777 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
3778 | return -ETIMEDOUT; | |
3779 | ||
3780 | return 0; | |
3781 | } | |
3782 | ||
41c445ff JB |
3783 | /** |
3784 | * i40e_vsi_control_tx - Start or stop a VSI's rings | |
3785 | * @vsi: the VSI being configured | |
3786 | * @enable: start or stop the rings | |
3787 | **/ | |
3788 | static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) | |
3789 | { | |
3790 | struct i40e_pf *pf = vsi->back; | |
3791 | struct i40e_hw *hw = &pf->hw; | |
23527308 | 3792 | int i, j, pf_q, ret = 0; |
41c445ff JB |
3793 | u32 tx_reg; |
3794 | ||
3795 | pf_q = vsi->base_queue; | |
3796 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
351499ab MJ |
3797 | |
3798 | /* warn the TX unit of coming changes */ | |
3799 | i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable); | |
3800 | if (!enable) | |
f98a2006 | 3801 | usleep_range(10, 20); |
351499ab | 3802 | |
6c5ef620 | 3803 | for (j = 0; j < 50; j++) { |
41c445ff | 3804 | tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); |
6c5ef620 MW |
3805 | if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) == |
3806 | ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1)) | |
3807 | break; | |
3808 | usleep_range(1000, 2000); | |
3809 | } | |
fda972f6 | 3810 | /* Skip if the queue is already in the requested state */ |
7c122007 | 3811 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) |
fda972f6 | 3812 | continue; |
41c445ff JB |
3813 | |
3814 | /* turn on/off the queue */ | |
c5c9eb9e SN |
3815 | if (enable) { |
3816 | wr32(hw, I40E_QTX_HEAD(pf_q), 0); | |
6c5ef620 | 3817 | tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK; |
c5c9eb9e | 3818 | } else { |
41c445ff | 3819 | tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; |
c5c9eb9e | 3820 | } |
41c445ff JB |
3821 | |
3822 | wr32(hw, I40E_QTX_ENA(pf_q), tx_reg); | |
69129dc3 NP |
3823 | /* No waiting for the Tx queue to disable */ |
3824 | if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state)) | |
3825 | continue; | |
41c445ff JB |
3826 | |
3827 | /* wait for the change to finish */ | |
23527308 NP |
3828 | ret = i40e_pf_txq_wait(pf, pf_q, enable); |
3829 | if (ret) { | |
3830 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
3831 | "VSI seid %d Tx ring %d %sable timeout\n", |
3832 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
23527308 | 3833 | break; |
41c445ff JB |
3834 | } |
3835 | } | |
3836 | ||
7134f9ce JB |
3837 | if (hw->revision_id == 0) |
3838 | mdelay(50); | |
23527308 NP |
3839 | return ret; |
3840 | } | |
3841 | ||
3842 | /** | |
3843 | * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled | |
3844 | * @pf: the PF being configured | |
3845 | * @pf_q: the PF queue | |
3846 | * @enable: enable or disable state of the queue | |
3847 | * | |
3848 | * This routine will wait for the given Rx queue of the PF to reach the | |
3849 | * enabled or disabled state. | |
3850 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
3851 | * multiple retries; else will return 0 in case of success. | |
3852 | **/ | |
3853 | static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
3854 | { | |
3855 | int i; | |
3856 | u32 rx_reg; | |
3857 | ||
3858 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
3859 | rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q)); | |
3860 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
3861 | break; | |
3862 | ||
f98a2006 | 3863 | usleep_range(10, 20); |
23527308 NP |
3864 | } |
3865 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
3866 | return -ETIMEDOUT; | |
7134f9ce | 3867 | |
41c445ff JB |
3868 | return 0; |
3869 | } | |
3870 | ||
3871 | /** | |
3872 | * i40e_vsi_control_rx - Start or stop a VSI's rings | |
3873 | * @vsi: the VSI being configured | |
3874 | * @enable: start or stop the rings | |
3875 | **/ | |
3876 | static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable) | |
3877 | { | |
3878 | struct i40e_pf *pf = vsi->back; | |
3879 | struct i40e_hw *hw = &pf->hw; | |
23527308 | 3880 | int i, j, pf_q, ret = 0; |
41c445ff JB |
3881 | u32 rx_reg; |
3882 | ||
3883 | pf_q = vsi->base_queue; | |
3884 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
6c5ef620 | 3885 | for (j = 0; j < 50; j++) { |
41c445ff | 3886 | rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); |
6c5ef620 MW |
3887 | if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) == |
3888 | ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1)) | |
3889 | break; | |
3890 | usleep_range(1000, 2000); | |
3891 | } | |
41c445ff | 3892 | |
7c122007 CS |
3893 | /* Skip if the queue is already in the requested state */ |
3894 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
3895 | continue; | |
41c445ff JB |
3896 | |
3897 | /* turn on/off the queue */ | |
3898 | if (enable) | |
6c5ef620 | 3899 | rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK; |
41c445ff | 3900 | else |
6c5ef620 | 3901 | rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; |
41c445ff | 3902 | wr32(hw, I40E_QRX_ENA(pf_q), rx_reg); |
3fe06f41 NP |
3903 | /* No waiting for the Tx queue to disable */ |
3904 | if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state)) | |
3905 | continue; | |
41c445ff JB |
3906 | |
3907 | /* wait for the change to finish */ | |
23527308 NP |
3908 | ret = i40e_pf_rxq_wait(pf, pf_q, enable); |
3909 | if (ret) { | |
3910 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
3911 | "VSI seid %d Rx ring %d %sable timeout\n", |
3912 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
23527308 | 3913 | break; |
41c445ff JB |
3914 | } |
3915 | } | |
3916 | ||
23527308 | 3917 | return ret; |
41c445ff JB |
3918 | } |
3919 | ||
3920 | /** | |
3921 | * i40e_vsi_control_rings - Start or stop a VSI's rings | |
3922 | * @vsi: the VSI being configured | |
3923 | * @enable: start or stop the rings | |
3924 | **/ | |
fc18eaa0 | 3925 | int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request) |
41c445ff | 3926 | { |
3b867b28 | 3927 | int ret = 0; |
41c445ff JB |
3928 | |
3929 | /* do rx first for enable and last for disable */ | |
3930 | if (request) { | |
3931 | ret = i40e_vsi_control_rx(vsi, request); | |
3932 | if (ret) | |
3933 | return ret; | |
3934 | ret = i40e_vsi_control_tx(vsi, request); | |
3935 | } else { | |
3b867b28 ASJ |
3936 | /* Ignore return value, we need to shutdown whatever we can */ |
3937 | i40e_vsi_control_tx(vsi, request); | |
3938 | i40e_vsi_control_rx(vsi, request); | |
41c445ff JB |
3939 | } |
3940 | ||
3941 | return ret; | |
3942 | } | |
3943 | ||
3944 | /** | |
3945 | * i40e_vsi_free_irq - Free the irq association with the OS | |
3946 | * @vsi: the VSI being configured | |
3947 | **/ | |
3948 | static void i40e_vsi_free_irq(struct i40e_vsi *vsi) | |
3949 | { | |
3950 | struct i40e_pf *pf = vsi->back; | |
3951 | struct i40e_hw *hw = &pf->hw; | |
3952 | int base = vsi->base_vector; | |
3953 | u32 val, qp; | |
3954 | int i; | |
3955 | ||
3956 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
3957 | if (!vsi->q_vectors) | |
3958 | return; | |
3959 | ||
63741846 SN |
3960 | if (!vsi->irqs_ready) |
3961 | return; | |
3962 | ||
3963 | vsi->irqs_ready = false; | |
41c445ff JB |
3964 | for (i = 0; i < vsi->num_q_vectors; i++) { |
3965 | u16 vector = i + base; | |
3966 | ||
3967 | /* free only the irqs that were actually requested */ | |
78681b1f SN |
3968 | if (!vsi->q_vectors[i] || |
3969 | !vsi->q_vectors[i]->num_ringpairs) | |
41c445ff JB |
3970 | continue; |
3971 | ||
3972 | /* clear the affinity_mask in the IRQ descriptor */ | |
3973 | irq_set_affinity_hint(pf->msix_entries[vector].vector, | |
3974 | NULL); | |
b33d3b73 | 3975 | synchronize_irq(pf->msix_entries[vector].vector); |
41c445ff | 3976 | free_irq(pf->msix_entries[vector].vector, |
493fb300 | 3977 | vsi->q_vectors[i]); |
41c445ff JB |
3978 | |
3979 | /* Tear down the interrupt queue link list | |
3980 | * | |
3981 | * We know that they come in pairs and always | |
3982 | * the Rx first, then the Tx. To clear the | |
3983 | * link list, stick the EOL value into the | |
3984 | * next_q field of the registers. | |
3985 | */ | |
3986 | val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1)); | |
3987 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
3988 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
3989 | val |= I40E_QUEUE_END_OF_LIST | |
3990 | << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
3991 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val); | |
3992 | ||
3993 | while (qp != I40E_QUEUE_END_OF_LIST) { | |
3994 | u32 next; | |
3995 | ||
3996 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
3997 | ||
3998 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
3999 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4000 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4001 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4002 | ||
4003 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4004 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4005 | ||
4006 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4007 | ||
4008 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4009 | ||
4010 | next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK) | |
4011 | >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT; | |
4012 | ||
4013 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4014 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4015 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4016 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4017 | ||
4018 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4019 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4020 | ||
4021 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4022 | qp = next; | |
4023 | } | |
4024 | } | |
4025 | } else { | |
4026 | free_irq(pf->pdev->irq, pf); | |
4027 | ||
4028 | val = rd32(hw, I40E_PFINT_LNKLST0); | |
4029 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4030 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4031 | val |= I40E_QUEUE_END_OF_LIST | |
4032 | << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; | |
4033 | wr32(hw, I40E_PFINT_LNKLST0, val); | |
4034 | ||
4035 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4036 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4037 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4038 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4039 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4040 | ||
4041 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4042 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4043 | ||
4044 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4045 | ||
4046 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4047 | ||
4048 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4049 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4050 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4051 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4052 | ||
4053 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4054 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4055 | ||
4056 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4057 | } | |
4058 | } | |
4059 | ||
493fb300 AD |
4060 | /** |
4061 | * i40e_free_q_vector - Free memory allocated for specific interrupt vector | |
4062 | * @vsi: the VSI being configured | |
4063 | * @v_idx: Index of vector to be freed | |
4064 | * | |
4065 | * This function frees the memory allocated to the q_vector. In addition if | |
4066 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4067 | * to freeing the q_vector. | |
4068 | **/ | |
4069 | static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx) | |
4070 | { | |
4071 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; | |
cd0b6fa6 | 4072 | struct i40e_ring *ring; |
493fb300 AD |
4073 | |
4074 | if (!q_vector) | |
4075 | return; | |
4076 | ||
4077 | /* disassociate q_vector from rings */ | |
cd0b6fa6 AD |
4078 | i40e_for_each_ring(ring, q_vector->tx) |
4079 | ring->q_vector = NULL; | |
4080 | ||
4081 | i40e_for_each_ring(ring, q_vector->rx) | |
4082 | ring->q_vector = NULL; | |
493fb300 AD |
4083 | |
4084 | /* only VSI w/ an associated netdev is set up w/ NAPI */ | |
4085 | if (vsi->netdev) | |
4086 | netif_napi_del(&q_vector->napi); | |
4087 | ||
4088 | vsi->q_vectors[v_idx] = NULL; | |
4089 | ||
4090 | kfree_rcu(q_vector, rcu); | |
4091 | } | |
4092 | ||
41c445ff JB |
4093 | /** |
4094 | * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors | |
4095 | * @vsi: the VSI being un-configured | |
4096 | * | |
4097 | * This frees the memory allocated to the q_vectors and | |
4098 | * deletes references to the NAPI struct. | |
4099 | **/ | |
4100 | static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi) | |
4101 | { | |
4102 | int v_idx; | |
4103 | ||
493fb300 AD |
4104 | for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) |
4105 | i40e_free_q_vector(vsi, v_idx); | |
41c445ff JB |
4106 | } |
4107 | ||
4108 | /** | |
4109 | * i40e_reset_interrupt_capability - Disable interrupt setup in OS | |
4110 | * @pf: board private structure | |
4111 | **/ | |
4112 | static void i40e_reset_interrupt_capability(struct i40e_pf *pf) | |
4113 | { | |
4114 | /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */ | |
4115 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4116 | pci_disable_msix(pf->pdev); | |
4117 | kfree(pf->msix_entries); | |
4118 | pf->msix_entries = NULL; | |
3b444399 SN |
4119 | kfree(pf->irq_pile); |
4120 | pf->irq_pile = NULL; | |
41c445ff JB |
4121 | } else if (pf->flags & I40E_FLAG_MSI_ENABLED) { |
4122 | pci_disable_msi(pf->pdev); | |
4123 | } | |
4124 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
4125 | } | |
4126 | ||
4127 | /** | |
4128 | * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4129 | * @pf: board private structure | |
4130 | * | |
4131 | * We go through and clear interrupt specific resources and reset the structure | |
4132 | * to pre-load conditions | |
4133 | **/ | |
4134 | static void i40e_clear_interrupt_scheme(struct i40e_pf *pf) | |
4135 | { | |
4136 | int i; | |
4137 | ||
e147758d | 4138 | i40e_stop_misc_vector(pf); |
69278398 | 4139 | if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) { |
e147758d SN |
4140 | synchronize_irq(pf->msix_entries[0].vector); |
4141 | free_irq(pf->msix_entries[0].vector, pf); | |
4142 | } | |
4143 | ||
e3219ce6 ASJ |
4144 | i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector, |
4145 | I40E_IWARP_IRQ_PILE_ID); | |
4146 | ||
41c445ff | 4147 | i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1); |
505682cd | 4148 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
4149 | if (pf->vsi[i]) |
4150 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
4151 | i40e_reset_interrupt_capability(pf); | |
4152 | } | |
4153 | ||
4154 | /** | |
4155 | * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI | |
4156 | * @vsi: the VSI being configured | |
4157 | **/ | |
4158 | static void i40e_napi_enable_all(struct i40e_vsi *vsi) | |
4159 | { | |
4160 | int q_idx; | |
4161 | ||
4162 | if (!vsi->netdev) | |
4163 | return; | |
4164 | ||
4165 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) | |
493fb300 | 4166 | napi_enable(&vsi->q_vectors[q_idx]->napi); |
41c445ff JB |
4167 | } |
4168 | ||
4169 | /** | |
4170 | * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI | |
4171 | * @vsi: the VSI being configured | |
4172 | **/ | |
4173 | static void i40e_napi_disable_all(struct i40e_vsi *vsi) | |
4174 | { | |
4175 | int q_idx; | |
4176 | ||
4177 | if (!vsi->netdev) | |
4178 | return; | |
4179 | ||
4180 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) | |
493fb300 | 4181 | napi_disable(&vsi->q_vectors[q_idx]->napi); |
41c445ff JB |
4182 | } |
4183 | ||
90ef8d47 SN |
4184 | /** |
4185 | * i40e_vsi_close - Shut down a VSI | |
4186 | * @vsi: the vsi to be quelled | |
4187 | **/ | |
4188 | static void i40e_vsi_close(struct i40e_vsi *vsi) | |
4189 | { | |
e3219ce6 ASJ |
4190 | bool reset = false; |
4191 | ||
90ef8d47 SN |
4192 | if (!test_and_set_bit(__I40E_DOWN, &vsi->state)) |
4193 | i40e_down(vsi); | |
4194 | i40e_vsi_free_irq(vsi); | |
4195 | i40e_vsi_free_tx_resources(vsi); | |
4196 | i40e_vsi_free_rx_resources(vsi); | |
92faef85 | 4197 | vsi->current_netdev_flags = 0; |
e3219ce6 ASJ |
4198 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state)) |
4199 | reset = true; | |
4200 | i40e_notify_client_of_netdev_close(vsi, reset); | |
90ef8d47 SN |
4201 | } |
4202 | ||
41c445ff JB |
4203 | /** |
4204 | * i40e_quiesce_vsi - Pause a given VSI | |
4205 | * @vsi: the VSI being paused | |
4206 | **/ | |
4207 | static void i40e_quiesce_vsi(struct i40e_vsi *vsi) | |
4208 | { | |
4209 | if (test_bit(__I40E_DOWN, &vsi->state)) | |
4210 | return; | |
4211 | ||
d341b7a5 NP |
4212 | /* No need to disable FCoE VSI when Tx suspended */ |
4213 | if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) && | |
4214 | vsi->type == I40E_VSI_FCOE) { | |
4215 | dev_dbg(&vsi->back->pdev->dev, | |
fb43201f | 4216 | "VSI seid %d skipping FCoE VSI disable\n", vsi->seid); |
d341b7a5 NP |
4217 | return; |
4218 | } | |
4219 | ||
41c445ff | 4220 | set_bit(__I40E_NEEDS_RESTART, &vsi->state); |
6995b36c | 4221 | if (vsi->netdev && netif_running(vsi->netdev)) |
41c445ff | 4222 | vsi->netdev->netdev_ops->ndo_stop(vsi->netdev); |
6995b36c | 4223 | else |
90ef8d47 | 4224 | i40e_vsi_close(vsi); |
41c445ff JB |
4225 | } |
4226 | ||
4227 | /** | |
4228 | * i40e_unquiesce_vsi - Resume a given VSI | |
4229 | * @vsi: the VSI being resumed | |
4230 | **/ | |
4231 | static void i40e_unquiesce_vsi(struct i40e_vsi *vsi) | |
4232 | { | |
4233 | if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state)) | |
4234 | return; | |
4235 | ||
4236 | clear_bit(__I40E_NEEDS_RESTART, &vsi->state); | |
4237 | if (vsi->netdev && netif_running(vsi->netdev)) | |
4238 | vsi->netdev->netdev_ops->ndo_open(vsi->netdev); | |
4239 | else | |
8276f757 | 4240 | i40e_vsi_open(vsi); /* this clears the DOWN bit */ |
41c445ff JB |
4241 | } |
4242 | ||
4243 | /** | |
4244 | * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF | |
4245 | * @pf: the PF | |
4246 | **/ | |
4247 | static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf) | |
4248 | { | |
4249 | int v; | |
4250 | ||
505682cd | 4251 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4252 | if (pf->vsi[v]) |
4253 | i40e_quiesce_vsi(pf->vsi[v]); | |
4254 | } | |
4255 | } | |
4256 | ||
4257 | /** | |
4258 | * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF | |
4259 | * @pf: the PF | |
4260 | **/ | |
4261 | static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf) | |
4262 | { | |
4263 | int v; | |
4264 | ||
505682cd | 4265 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4266 | if (pf->vsi[v]) |
4267 | i40e_unquiesce_vsi(pf->vsi[v]); | |
4268 | } | |
4269 | } | |
4270 | ||
69129dc3 NP |
4271 | #ifdef CONFIG_I40E_DCB |
4272 | /** | |
3fe06f41 | 4273 | * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled |
69129dc3 NP |
4274 | * @vsi: the VSI being configured |
4275 | * | |
3fe06f41 | 4276 | * This function waits for the given VSI's queues to be disabled. |
69129dc3 | 4277 | **/ |
3fe06f41 | 4278 | static int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi) |
69129dc3 NP |
4279 | { |
4280 | struct i40e_pf *pf = vsi->back; | |
4281 | int i, pf_q, ret; | |
4282 | ||
4283 | pf_q = vsi->base_queue; | |
4284 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
4285 | /* Check and wait for the disable status of the queue */ | |
4286 | ret = i40e_pf_txq_wait(pf, pf_q, false); | |
4287 | if (ret) { | |
4288 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
4289 | "VSI seid %d Tx ring %d disable timeout\n", |
4290 | vsi->seid, pf_q); | |
69129dc3 NP |
4291 | return ret; |
4292 | } | |
4293 | } | |
4294 | ||
3fe06f41 NP |
4295 | pf_q = vsi->base_queue; |
4296 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
4297 | /* Check and wait for the disable status of the queue */ | |
4298 | ret = i40e_pf_rxq_wait(pf, pf_q, false); | |
4299 | if (ret) { | |
4300 | dev_info(&pf->pdev->dev, | |
4301 | "VSI seid %d Rx ring %d disable timeout\n", | |
4302 | vsi->seid, pf_q); | |
4303 | return ret; | |
4304 | } | |
4305 | } | |
4306 | ||
69129dc3 NP |
4307 | return 0; |
4308 | } | |
4309 | ||
4310 | /** | |
3fe06f41 | 4311 | * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled |
69129dc3 NP |
4312 | * @pf: the PF |
4313 | * | |
3fe06f41 | 4314 | * This function waits for the queues to be in disabled state for all the |
69129dc3 NP |
4315 | * VSIs that are managed by this PF. |
4316 | **/ | |
3fe06f41 | 4317 | static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf) |
69129dc3 NP |
4318 | { |
4319 | int v, ret = 0; | |
4320 | ||
4321 | for (v = 0; v < pf->hw.func_caps.num_vsis; v++) { | |
d341b7a5 NP |
4322 | /* No need to wait for FCoE VSI queues */ |
4323 | if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) { | |
3fe06f41 | 4324 | ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]); |
69129dc3 NP |
4325 | if (ret) |
4326 | break; | |
4327 | } | |
4328 | } | |
4329 | ||
4330 | return ret; | |
4331 | } | |
4332 | ||
4333 | #endif | |
b03a8c1f KP |
4334 | |
4335 | /** | |
4336 | * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue | |
4337 | * @q_idx: TX queue number | |
4338 | * @vsi: Pointer to VSI struct | |
4339 | * | |
4340 | * This function checks specified queue for given VSI. Detects hung condition. | |
4341 | * Sets hung bit since it is two step process. Before next run of service task | |
4342 | * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not, | |
4343 | * hung condition remain unchanged and during subsequent run, this function | |
4344 | * issues SW interrupt to recover from hung condition. | |
4345 | **/ | |
4346 | static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi) | |
4347 | { | |
4348 | struct i40e_ring *tx_ring = NULL; | |
4349 | struct i40e_pf *pf; | |
dd353109 | 4350 | u32 head, val, tx_pending_hw; |
b03a8c1f KP |
4351 | int i; |
4352 | ||
4353 | pf = vsi->back; | |
4354 | ||
4355 | /* now that we have an index, find the tx_ring struct */ | |
4356 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
4357 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
4358 | if (q_idx == vsi->tx_rings[i]->queue_index) { | |
4359 | tx_ring = vsi->tx_rings[i]; | |
4360 | break; | |
4361 | } | |
4362 | } | |
4363 | } | |
4364 | ||
4365 | if (!tx_ring) | |
4366 | return; | |
4367 | ||
4368 | /* Read interrupt register */ | |
4369 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
4370 | val = rd32(&pf->hw, | |
4371 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
4372 | tx_ring->vsi->base_vector - 1)); | |
4373 | else | |
4374 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
4375 | ||
4376 | head = i40e_get_head(tx_ring); | |
4377 | ||
dd353109 | 4378 | tx_pending_hw = i40e_get_tx_pending(tx_ring, false); |
b03a8c1f | 4379 | |
9c6c1259 KP |
4380 | /* HW is done executing descriptors, updated HEAD write back, |
4381 | * but SW hasn't processed those descriptors. If interrupt is | |
4382 | * not generated from this point ON, it could result into | |
4383 | * dev_watchdog detecting timeout on those netdev_queue, | |
4384 | * hence proactively trigger SW interrupt. | |
b03a8c1f | 4385 | */ |
dd353109 | 4386 | if (tx_pending_hw && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) { |
9c6c1259 KP |
4387 | /* NAPI Poll didn't run and clear since it was set */ |
4388 | if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT, | |
4389 | &tx_ring->q_vector->hung_detected)) { | |
dd353109 ASJ |
4390 | netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending_hw: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n", |
4391 | vsi->seid, q_idx, tx_pending_hw, | |
9c6c1259 KP |
4392 | tx_ring->next_to_clean, head, |
4393 | tx_ring->next_to_use, | |
4394 | readl(tx_ring->tail)); | |
4395 | netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n", | |
4396 | vsi->seid, q_idx, val); | |
4397 | i40e_force_wb(vsi, tx_ring->q_vector); | |
4398 | } else { | |
4399 | /* First Chance - detected possible hung */ | |
4400 | set_bit(I40E_Q_VECTOR_HUNG_DETECT, | |
4401 | &tx_ring->q_vector->hung_detected); | |
4402 | } | |
4403 | } | |
dd353109 ASJ |
4404 | |
4405 | /* This is the case where we have interrupts missing, | |
4406 | * so the tx_pending in HW will most likely be 0, but we | |
4407 | * will have tx_pending in SW since the WB happened but the | |
4408 | * interrupt got lost. | |
4409 | */ | |
4410 | if ((!tx_pending_hw) && i40e_get_tx_pending(tx_ring, true) && | |
4411 | (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) { | |
4412 | if (napi_reschedule(&tx_ring->q_vector->napi)) | |
4413 | tx_ring->tx_stats.tx_lost_interrupt++; | |
4414 | } | |
b03a8c1f KP |
4415 | } |
4416 | ||
4417 | /** | |
4418 | * i40e_detect_recover_hung - Function to detect and recover hung_queues | |
4419 | * @pf: pointer to PF struct | |
4420 | * | |
4421 | * LAN VSI has netdev and netdev has TX queues. This function is to check | |
4422 | * each of those TX queues if they are hung, trigger recovery by issuing | |
4423 | * SW interrupt. | |
4424 | **/ | |
4425 | static void i40e_detect_recover_hung(struct i40e_pf *pf) | |
4426 | { | |
4427 | struct net_device *netdev; | |
4428 | struct i40e_vsi *vsi; | |
4429 | int i; | |
4430 | ||
4431 | /* Only for LAN VSI */ | |
4432 | vsi = pf->vsi[pf->lan_vsi]; | |
4433 | ||
4434 | if (!vsi) | |
4435 | return; | |
4436 | ||
4437 | /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */ | |
4438 | if (test_bit(__I40E_DOWN, &vsi->back->state) || | |
4439 | test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state)) | |
4440 | return; | |
4441 | ||
4442 | /* Make sure type is MAIN VSI */ | |
4443 | if (vsi->type != I40E_VSI_MAIN) | |
4444 | return; | |
4445 | ||
4446 | netdev = vsi->netdev; | |
4447 | if (!netdev) | |
4448 | return; | |
4449 | ||
4450 | /* Bail out if netif_carrier is not OK */ | |
4451 | if (!netif_carrier_ok(netdev)) | |
4452 | return; | |
4453 | ||
4454 | /* Go thru' TX queues for netdev */ | |
4455 | for (i = 0; i < netdev->num_tx_queues; i++) { | |
4456 | struct netdev_queue *q; | |
4457 | ||
4458 | q = netdev_get_tx_queue(netdev, i); | |
4459 | if (q) | |
4460 | i40e_detect_recover_hung_queue(i, vsi); | |
4461 | } | |
4462 | } | |
4463 | ||
63d7e5a4 NP |
4464 | /** |
4465 | * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP | |
b40c82e6 | 4466 | * @pf: pointer to PF |
63d7e5a4 NP |
4467 | * |
4468 | * Get TC map for ISCSI PF type that will include iSCSI TC | |
4469 | * and LAN TC. | |
4470 | **/ | |
4471 | static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf) | |
4472 | { | |
4473 | struct i40e_dcb_app_priority_table app; | |
4474 | struct i40e_hw *hw = &pf->hw; | |
4475 | u8 enabled_tc = 1; /* TC0 is always enabled */ | |
4476 | u8 tc, i; | |
4477 | /* Get the iSCSI APP TLV */ | |
4478 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4479 | ||
4480 | for (i = 0; i < dcbcfg->numapps; i++) { | |
4481 | app = dcbcfg->app[i]; | |
4482 | if (app.selector == I40E_APP_SEL_TCPIP && | |
4483 | app.protocolid == I40E_APP_PROTOID_ISCSI) { | |
4484 | tc = dcbcfg->etscfg.prioritytable[app.priority]; | |
75f5cea9 | 4485 | enabled_tc |= BIT(tc); |
63d7e5a4 NP |
4486 | break; |
4487 | } | |
4488 | } | |
4489 | ||
4490 | return enabled_tc; | |
4491 | } | |
4492 | ||
41c445ff JB |
4493 | /** |
4494 | * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config | |
4495 | * @dcbcfg: the corresponding DCBx configuration structure | |
4496 | * | |
4497 | * Return the number of TCs from given DCBx configuration | |
4498 | **/ | |
4499 | static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg) | |
4500 | { | |
078b5876 JB |
4501 | u8 num_tc = 0; |
4502 | int i; | |
41c445ff JB |
4503 | |
4504 | /* Scan the ETS Config Priority Table to find | |
4505 | * traffic class enabled for a given priority | |
4506 | * and use the traffic class index to get the | |
4507 | * number of traffic classes enabled | |
4508 | */ | |
4509 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) { | |
4510 | if (dcbcfg->etscfg.prioritytable[i] > num_tc) | |
4511 | num_tc = dcbcfg->etscfg.prioritytable[i]; | |
4512 | } | |
4513 | ||
4514 | /* Traffic class index starts from zero so | |
4515 | * increment to return the actual count | |
4516 | */ | |
078b5876 | 4517 | return num_tc + 1; |
41c445ff JB |
4518 | } |
4519 | ||
4520 | /** | |
4521 | * i40e_dcb_get_enabled_tc - Get enabled traffic classes | |
4522 | * @dcbcfg: the corresponding DCBx configuration structure | |
4523 | * | |
4524 | * Query the current DCB configuration and return the number of | |
4525 | * traffic classes enabled from the given DCBX config | |
4526 | **/ | |
4527 | static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg) | |
4528 | { | |
4529 | u8 num_tc = i40e_dcb_get_num_tc(dcbcfg); | |
4530 | u8 enabled_tc = 1; | |
4531 | u8 i; | |
4532 | ||
4533 | for (i = 0; i < num_tc; i++) | |
41a1d04b | 4534 | enabled_tc |= BIT(i); |
41c445ff JB |
4535 | |
4536 | return enabled_tc; | |
4537 | } | |
4538 | ||
4539 | /** | |
4540 | * i40e_pf_get_num_tc - Get enabled traffic classes for PF | |
4541 | * @pf: PF being queried | |
4542 | * | |
4543 | * Return number of traffic classes enabled for the given PF | |
4544 | **/ | |
4545 | static u8 i40e_pf_get_num_tc(struct i40e_pf *pf) | |
4546 | { | |
4547 | struct i40e_hw *hw = &pf->hw; | |
4548 | u8 i, enabled_tc; | |
4549 | u8 num_tc = 0; | |
4550 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4551 | ||
4552 | /* If DCB is not enabled then always in single TC */ | |
4553 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) | |
4554 | return 1; | |
4555 | ||
63d7e5a4 NP |
4556 | /* SFP mode will be enabled for all TCs on port */ |
4557 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) | |
4558 | return i40e_dcb_get_num_tc(dcbcfg); | |
4559 | ||
41c445ff | 4560 | /* MFP mode return count of enabled TCs for this PF */ |
63d7e5a4 NP |
4561 | if (pf->hw.func_caps.iscsi) |
4562 | enabled_tc = i40e_get_iscsi_tc_map(pf); | |
4563 | else | |
fc51de96 | 4564 | return 1; /* Only TC0 */ |
41c445ff | 4565 | |
63d7e5a4 NP |
4566 | /* At least have TC0 */ |
4567 | enabled_tc = (enabled_tc ? enabled_tc : 0x1); | |
4568 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 4569 | if (enabled_tc & BIT(i)) |
63d7e5a4 NP |
4570 | num_tc++; |
4571 | } | |
4572 | return num_tc; | |
41c445ff JB |
4573 | } |
4574 | ||
4575 | /** | |
4576 | * i40e_pf_get_default_tc - Get bitmap for first enabled TC | |
4577 | * @pf: PF being queried | |
4578 | * | |
4579 | * Return a bitmap for first enabled traffic class for this PF. | |
4580 | **/ | |
4581 | static u8 i40e_pf_get_default_tc(struct i40e_pf *pf) | |
4582 | { | |
4583 | u8 enabled_tc = pf->hw.func_caps.enabled_tcmap; | |
4584 | u8 i = 0; | |
4585 | ||
4586 | if (!enabled_tc) | |
4587 | return 0x1; /* TC0 */ | |
4588 | ||
4589 | /* Find the first enabled TC */ | |
4590 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 4591 | if (enabled_tc & BIT(i)) |
41c445ff JB |
4592 | break; |
4593 | } | |
4594 | ||
41a1d04b | 4595 | return BIT(i); |
41c445ff JB |
4596 | } |
4597 | ||
4598 | /** | |
4599 | * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes | |
4600 | * @pf: PF being queried | |
4601 | * | |
4602 | * Return a bitmap for enabled traffic classes for this PF. | |
4603 | **/ | |
4604 | static u8 i40e_pf_get_tc_map(struct i40e_pf *pf) | |
4605 | { | |
4606 | /* If DCB is not enabled for this PF then just return default TC */ | |
4607 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) | |
4608 | return i40e_pf_get_default_tc(pf); | |
4609 | ||
41c445ff | 4610 | /* SFP mode we want PF to be enabled for all TCs */ |
63d7e5a4 NP |
4611 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
4612 | return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config); | |
4613 | ||
fc51de96 | 4614 | /* MFP enabled and iSCSI PF type */ |
63d7e5a4 NP |
4615 | if (pf->hw.func_caps.iscsi) |
4616 | return i40e_get_iscsi_tc_map(pf); | |
4617 | else | |
fc51de96 | 4618 | return i40e_pf_get_default_tc(pf); |
41c445ff JB |
4619 | } |
4620 | ||
4621 | /** | |
4622 | * i40e_vsi_get_bw_info - Query VSI BW Information | |
4623 | * @vsi: the VSI being queried | |
4624 | * | |
4625 | * Returns 0 on success, negative value on failure | |
4626 | **/ | |
4627 | static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) | |
4628 | { | |
4629 | struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0}; | |
4630 | struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0}; | |
4631 | struct i40e_pf *pf = vsi->back; | |
4632 | struct i40e_hw *hw = &pf->hw; | |
f1c7e72e | 4633 | i40e_status ret; |
41c445ff | 4634 | u32 tc_bw_max; |
41c445ff JB |
4635 | int i; |
4636 | ||
4637 | /* Get the VSI level BW configuration */ | |
f1c7e72e SN |
4638 | ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); |
4639 | if (ret) { | |
41c445ff | 4640 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
4641 | "couldn't get PF vsi bw config, err %s aq_err %s\n", |
4642 | i40e_stat_str(&pf->hw, ret), | |
4643 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 4644 | return -EINVAL; |
41c445ff JB |
4645 | } |
4646 | ||
4647 | /* Get the VSI level BW configuration per TC */ | |
f1c7e72e SN |
4648 | ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config, |
4649 | NULL); | |
4650 | if (ret) { | |
41c445ff | 4651 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
4652 | "couldn't get PF vsi ets bw config, err %s aq_err %s\n", |
4653 | i40e_stat_str(&pf->hw, ret), | |
4654 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 4655 | return -EINVAL; |
41c445ff JB |
4656 | } |
4657 | ||
4658 | if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) { | |
4659 | dev_info(&pf->pdev->dev, | |
4660 | "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n", | |
4661 | bw_config.tc_valid_bits, | |
4662 | bw_ets_config.tc_valid_bits); | |
4663 | /* Still continuing */ | |
4664 | } | |
4665 | ||
4666 | vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit); | |
4667 | vsi->bw_max_quanta = bw_config.max_bw; | |
4668 | tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) | | |
4669 | (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16); | |
4670 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
4671 | vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i]; | |
4672 | vsi->bw_ets_limit_credits[i] = | |
4673 | le16_to_cpu(bw_ets_config.credits[i]); | |
4674 | /* 3 bits out of 4 for each TC */ | |
4675 | vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7); | |
4676 | } | |
078b5876 | 4677 | |
dcae29be | 4678 | return 0; |
41c445ff JB |
4679 | } |
4680 | ||
4681 | /** | |
4682 | * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC | |
4683 | * @vsi: the VSI being configured | |
4684 | * @enabled_tc: TC bitmap | |
4685 | * @bw_credits: BW shared credits per TC | |
4686 | * | |
4687 | * Returns 0 on success, negative value on failure | |
4688 | **/ | |
dcae29be | 4689 | static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc, |
41c445ff JB |
4690 | u8 *bw_share) |
4691 | { | |
4692 | struct i40e_aqc_configure_vsi_tc_bw_data bw_data; | |
f1c7e72e | 4693 | i40e_status ret; |
dcae29be | 4694 | int i; |
41c445ff JB |
4695 | |
4696 | bw_data.tc_valid_bits = enabled_tc; | |
4697 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
4698 | bw_data.tc_bw_credits[i] = bw_share[i]; | |
4699 | ||
f1c7e72e SN |
4700 | ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data, |
4701 | NULL); | |
4702 | if (ret) { | |
41c445ff | 4703 | dev_info(&vsi->back->pdev->dev, |
69bfb110 JB |
4704 | "AQ command Config VSI BW allocation per TC failed = %d\n", |
4705 | vsi->back->hw.aq.asq_last_status); | |
dcae29be | 4706 | return -EINVAL; |
41c445ff JB |
4707 | } |
4708 | ||
4709 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
4710 | vsi->info.qs_handle[i] = bw_data.qs_handles[i]; | |
4711 | ||
dcae29be | 4712 | return 0; |
41c445ff JB |
4713 | } |
4714 | ||
4715 | /** | |
4716 | * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration | |
4717 | * @vsi: the VSI being configured | |
4718 | * @enabled_tc: TC map to be enabled | |
4719 | * | |
4720 | **/ | |
4721 | static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
4722 | { | |
4723 | struct net_device *netdev = vsi->netdev; | |
4724 | struct i40e_pf *pf = vsi->back; | |
4725 | struct i40e_hw *hw = &pf->hw; | |
4726 | u8 netdev_tc = 0; | |
4727 | int i; | |
4728 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4729 | ||
4730 | if (!netdev) | |
4731 | return; | |
4732 | ||
4733 | if (!enabled_tc) { | |
4734 | netdev_reset_tc(netdev); | |
4735 | return; | |
4736 | } | |
4737 | ||
4738 | /* Set up actual enabled TCs on the VSI */ | |
4739 | if (netdev_set_num_tc(netdev, vsi->tc_config.numtc)) | |
4740 | return; | |
4741 | ||
4742 | /* set per TC queues for the VSI */ | |
4743 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
4744 | /* Only set TC queues for enabled tcs | |
4745 | * | |
4746 | * e.g. For a VSI that has TC0 and TC3 enabled the | |
4747 | * enabled_tc bitmap would be 0x00001001; the driver | |
4748 | * will set the numtc for netdev as 2 that will be | |
4749 | * referenced by the netdev layer as TC 0 and 1. | |
4750 | */ | |
75f5cea9 | 4751 | if (vsi->tc_config.enabled_tc & BIT(i)) |
41c445ff JB |
4752 | netdev_set_tc_queue(netdev, |
4753 | vsi->tc_config.tc_info[i].netdev_tc, | |
4754 | vsi->tc_config.tc_info[i].qcount, | |
4755 | vsi->tc_config.tc_info[i].qoffset); | |
4756 | } | |
4757 | ||
4758 | /* Assign UP2TC map for the VSI */ | |
4759 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) { | |
4760 | /* Get the actual TC# for the UP */ | |
4761 | u8 ets_tc = dcbcfg->etscfg.prioritytable[i]; | |
4762 | /* Get the mapped netdev TC# for the UP */ | |
4763 | netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc; | |
4764 | netdev_set_prio_tc_map(netdev, i, netdev_tc); | |
4765 | } | |
4766 | } | |
4767 | ||
4768 | /** | |
4769 | * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map | |
4770 | * @vsi: the VSI being configured | |
4771 | * @ctxt: the ctxt buffer returned from AQ VSI update param command | |
4772 | **/ | |
4773 | static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi, | |
4774 | struct i40e_vsi_context *ctxt) | |
4775 | { | |
4776 | /* copy just the sections touched not the entire info | |
4777 | * since not all sections are valid as returned by | |
4778 | * update vsi params | |
4779 | */ | |
4780 | vsi->info.mapping_flags = ctxt->info.mapping_flags; | |
4781 | memcpy(&vsi->info.queue_mapping, | |
4782 | &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping)); | |
4783 | memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping, | |
4784 | sizeof(vsi->info.tc_mapping)); | |
4785 | } | |
4786 | ||
4787 | /** | |
4788 | * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map | |
4789 | * @vsi: VSI to be configured | |
4790 | * @enabled_tc: TC bitmap | |
4791 | * | |
4792 | * This configures a particular VSI for TCs that are mapped to the | |
4793 | * given TC bitmap. It uses default bandwidth share for TCs across | |
4794 | * VSIs to configure TC for a particular VSI. | |
4795 | * | |
4796 | * NOTE: | |
4797 | * It is expected that the VSI queues have been quisced before calling | |
4798 | * this function. | |
4799 | **/ | |
4800 | static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
4801 | { | |
4802 | u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
4803 | struct i40e_vsi_context ctxt; | |
4804 | int ret = 0; | |
4805 | int i; | |
4806 | ||
4807 | /* Check if enabled_tc is same as existing or new TCs */ | |
4808 | if (vsi->tc_config.enabled_tc == enabled_tc) | |
4809 | return ret; | |
4810 | ||
4811 | /* Enable ETS TCs with equal BW Share for now across all VSIs */ | |
4812 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 4813 | if (enabled_tc & BIT(i)) |
41c445ff JB |
4814 | bw_share[i] = 1; |
4815 | } | |
4816 | ||
4817 | ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share); | |
4818 | if (ret) { | |
4819 | dev_info(&vsi->back->pdev->dev, | |
4820 | "Failed configuring TC map %d for VSI %d\n", | |
4821 | enabled_tc, vsi->seid); | |
4822 | goto out; | |
4823 | } | |
4824 | ||
4825 | /* Update Queue Pairs Mapping for currently enabled UPs */ | |
4826 | ctxt.seid = vsi->seid; | |
4827 | ctxt.pf_num = vsi->back->hw.pf_id; | |
4828 | ctxt.vf_num = 0; | |
4829 | ctxt.uplink_seid = vsi->uplink_seid; | |
1a2f6248 | 4830 | ctxt.info = vsi->info; |
41c445ff JB |
4831 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); |
4832 | ||
e3219ce6 ASJ |
4833 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
4834 | ctxt.info.valid_sections |= | |
4835 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
4836 | ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA; | |
4837 | } | |
4838 | ||
41c445ff JB |
4839 | /* Update the VSI after updating the VSI queue-mapping information */ |
4840 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); | |
4841 | if (ret) { | |
4842 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
4843 | "Update vsi tc config failed, err %s aq_err %s\n", |
4844 | i40e_stat_str(&vsi->back->hw, ret), | |
4845 | i40e_aq_str(&vsi->back->hw, | |
4846 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
4847 | goto out; |
4848 | } | |
4849 | /* update the local VSI info with updated queue map */ | |
4850 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
4851 | vsi->info.valid_sections = 0; | |
4852 | ||
4853 | /* Update current VSI BW information */ | |
4854 | ret = i40e_vsi_get_bw_info(vsi); | |
4855 | if (ret) { | |
4856 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
4857 | "Failed updating vsi bw info, err %s aq_err %s\n", |
4858 | i40e_stat_str(&vsi->back->hw, ret), | |
4859 | i40e_aq_str(&vsi->back->hw, | |
4860 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
4861 | goto out; |
4862 | } | |
4863 | ||
4864 | /* Update the netdev TC setup */ | |
4865 | i40e_vsi_config_netdev_tc(vsi, enabled_tc); | |
4866 | out: | |
4867 | return ret; | |
4868 | } | |
4869 | ||
4e3b35b0 NP |
4870 | /** |
4871 | * i40e_veb_config_tc - Configure TCs for given VEB | |
4872 | * @veb: given VEB | |
4873 | * @enabled_tc: TC bitmap | |
4874 | * | |
4875 | * Configures given TC bitmap for VEB (switching) element | |
4876 | **/ | |
4877 | int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc) | |
4878 | { | |
4879 | struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0}; | |
4880 | struct i40e_pf *pf = veb->pf; | |
4881 | int ret = 0; | |
4882 | int i; | |
4883 | ||
4884 | /* No TCs or already enabled TCs just return */ | |
4885 | if (!enabled_tc || veb->enabled_tc == enabled_tc) | |
4886 | return ret; | |
4887 | ||
4888 | bw_data.tc_valid_bits = enabled_tc; | |
4889 | /* bw_data.absolute_credits is not set (relative) */ | |
4890 | ||
4891 | /* Enable ETS TCs with equal BW Share for now */ | |
4892 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 4893 | if (enabled_tc & BIT(i)) |
4e3b35b0 NP |
4894 | bw_data.tc_bw_share_credits[i] = 1; |
4895 | } | |
4896 | ||
4897 | ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid, | |
4898 | &bw_data, NULL); | |
4899 | if (ret) { | |
4900 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
4901 | "VEB bw config failed, err %s aq_err %s\n", |
4902 | i40e_stat_str(&pf->hw, ret), | |
4903 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
4904 | goto out; |
4905 | } | |
4906 | ||
4907 | /* Update the BW information */ | |
4908 | ret = i40e_veb_get_bw_info(veb); | |
4909 | if (ret) { | |
4910 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
4911 | "Failed getting veb bw config, err %s aq_err %s\n", |
4912 | i40e_stat_str(&pf->hw, ret), | |
4913 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
4914 | } |
4915 | ||
4916 | out: | |
4917 | return ret; | |
4918 | } | |
4919 | ||
4920 | #ifdef CONFIG_I40E_DCB | |
4921 | /** | |
4922 | * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs | |
4923 | * @pf: PF struct | |
4924 | * | |
4925 | * Reconfigure VEB/VSIs on a given PF; it is assumed that | |
4926 | * the caller would've quiesce all the VSIs before calling | |
4927 | * this function | |
4928 | **/ | |
4929 | static void i40e_dcb_reconfigure(struct i40e_pf *pf) | |
4930 | { | |
4931 | u8 tc_map = 0; | |
4932 | int ret; | |
4933 | u8 v; | |
4934 | ||
4935 | /* Enable the TCs available on PF to all VEBs */ | |
4936 | tc_map = i40e_pf_get_tc_map(pf); | |
4937 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
4938 | if (!pf->veb[v]) | |
4939 | continue; | |
4940 | ret = i40e_veb_config_tc(pf->veb[v], tc_map); | |
4941 | if (ret) { | |
4942 | dev_info(&pf->pdev->dev, | |
4943 | "Failed configuring TC for VEB seid=%d\n", | |
4944 | pf->veb[v]->seid); | |
4945 | /* Will try to configure as many components */ | |
4946 | } | |
4947 | } | |
4948 | ||
4949 | /* Update each VSI */ | |
505682cd | 4950 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
4e3b35b0 NP |
4951 | if (!pf->vsi[v]) |
4952 | continue; | |
4953 | ||
4954 | /* - Enable all TCs for the LAN VSI | |
38e00438 VD |
4955 | #ifdef I40E_FCOE |
4956 | * - For FCoE VSI only enable the TC configured | |
4957 | * as per the APP TLV | |
4958 | #endif | |
4e3b35b0 NP |
4959 | * - For all others keep them at TC0 for now |
4960 | */ | |
4961 | if (v == pf->lan_vsi) | |
4962 | tc_map = i40e_pf_get_tc_map(pf); | |
4963 | else | |
4964 | tc_map = i40e_pf_get_default_tc(pf); | |
38e00438 VD |
4965 | #ifdef I40E_FCOE |
4966 | if (pf->vsi[v]->type == I40E_VSI_FCOE) | |
4967 | tc_map = i40e_get_fcoe_tc_map(pf); | |
4968 | #endif /* #ifdef I40E_FCOE */ | |
4e3b35b0 NP |
4969 | |
4970 | ret = i40e_vsi_config_tc(pf->vsi[v], tc_map); | |
4971 | if (ret) { | |
4972 | dev_info(&pf->pdev->dev, | |
4973 | "Failed configuring TC for VSI seid=%d\n", | |
4974 | pf->vsi[v]->seid); | |
4975 | /* Will try to configure as many components */ | |
4976 | } else { | |
0672a091 NP |
4977 | /* Re-configure VSI vectors based on updated TC map */ |
4978 | i40e_vsi_map_rings_to_vectors(pf->vsi[v]); | |
4e3b35b0 NP |
4979 | if (pf->vsi[v]->netdev) |
4980 | i40e_dcbnl_set_all(pf->vsi[v]); | |
4981 | } | |
4982 | } | |
4983 | } | |
4984 | ||
2fd75f31 NP |
4985 | /** |
4986 | * i40e_resume_port_tx - Resume port Tx | |
4987 | * @pf: PF struct | |
4988 | * | |
4989 | * Resume a port's Tx and issue a PF reset in case of failure to | |
4990 | * resume. | |
4991 | **/ | |
4992 | static int i40e_resume_port_tx(struct i40e_pf *pf) | |
4993 | { | |
4994 | struct i40e_hw *hw = &pf->hw; | |
4995 | int ret; | |
4996 | ||
4997 | ret = i40e_aq_resume_port_tx(hw, NULL); | |
4998 | if (ret) { | |
4999 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
5000 | "Resume Port Tx failed, err %s aq_err %s\n", |
5001 | i40e_stat_str(&pf->hw, ret), | |
5002 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
2fd75f31 NP |
5003 | /* Schedule PF reset to recover */ |
5004 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
5005 | i40e_service_event_schedule(pf); | |
5006 | } | |
5007 | ||
5008 | return ret; | |
5009 | } | |
5010 | ||
4e3b35b0 NP |
5011 | /** |
5012 | * i40e_init_pf_dcb - Initialize DCB configuration | |
5013 | * @pf: PF being configured | |
5014 | * | |
5015 | * Query the current DCB configuration and cache it | |
5016 | * in the hardware structure | |
5017 | **/ | |
5018 | static int i40e_init_pf_dcb(struct i40e_pf *pf) | |
5019 | { | |
5020 | struct i40e_hw *hw = &pf->hw; | |
5021 | int err = 0; | |
5022 | ||
025b4a54 | 5023 | /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */ |
f1bbad33 | 5024 | if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT) |
025b4a54 ASJ |
5025 | goto out; |
5026 | ||
4e3b35b0 NP |
5027 | /* Get the initial DCB configuration */ |
5028 | err = i40e_init_dcb(hw); | |
5029 | if (!err) { | |
5030 | /* Device/Function is not DCBX capable */ | |
5031 | if ((!hw->func_caps.dcb) || | |
5032 | (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) { | |
5033 | dev_info(&pf->pdev->dev, | |
5034 | "DCBX offload is not supported or is disabled for this PF.\n"); | |
5035 | ||
5036 | if (pf->flags & I40E_FLAG_MFP_ENABLED) | |
5037 | goto out; | |
5038 | ||
5039 | } else { | |
5040 | /* When status is not DISABLED then DCBX in FW */ | |
5041 | pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED | | |
5042 | DCB_CAP_DCBX_VER_IEEE; | |
4d9b6043 NP |
5043 | |
5044 | pf->flags |= I40E_FLAG_DCB_CAPABLE; | |
5045 | /* Enable DCB tagging only when more than one TC */ | |
5046 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) | |
5047 | pf->flags |= I40E_FLAG_DCB_ENABLED; | |
9fa61dd2 NP |
5048 | dev_dbg(&pf->pdev->dev, |
5049 | "DCBX offload is supported for this PF.\n"); | |
4e3b35b0 | 5050 | } |
014269ff | 5051 | } else { |
aebfc816 | 5052 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
5053 | "Query for DCB configuration failed, err %s aq_err %s\n", |
5054 | i40e_stat_str(&pf->hw, err), | |
5055 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
5056 | } |
5057 | ||
5058 | out: | |
5059 | return err; | |
5060 | } | |
5061 | #endif /* CONFIG_I40E_DCB */ | |
cf05ed08 JB |
5062 | #define SPEED_SIZE 14 |
5063 | #define FC_SIZE 8 | |
5064 | /** | |
5065 | * i40e_print_link_message - print link up or down | |
5066 | * @vsi: the VSI for which link needs a message | |
5067 | */ | |
c156f856 | 5068 | void i40e_print_link_message(struct i40e_vsi *vsi, bool isup) |
cf05ed08 | 5069 | { |
a9165490 SN |
5070 | char *speed = "Unknown"; |
5071 | char *fc = "Unknown"; | |
cf05ed08 | 5072 | |
c156f856 MJ |
5073 | if (vsi->current_isup == isup) |
5074 | return; | |
5075 | vsi->current_isup = isup; | |
cf05ed08 JB |
5076 | if (!isup) { |
5077 | netdev_info(vsi->netdev, "NIC Link is Down\n"); | |
5078 | return; | |
5079 | } | |
5080 | ||
148c2d80 GR |
5081 | /* Warn user if link speed on NPAR enabled partition is not at |
5082 | * least 10GB | |
5083 | */ | |
5084 | if (vsi->back->hw.func_caps.npar_enable && | |
5085 | (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB || | |
5086 | vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB)) | |
5087 | netdev_warn(vsi->netdev, | |
5088 | "The partition detected link speed that is less than 10Gbps\n"); | |
5089 | ||
cf05ed08 JB |
5090 | switch (vsi->back->hw.phy.link_info.link_speed) { |
5091 | case I40E_LINK_SPEED_40GB: | |
a9165490 | 5092 | speed = "40 G"; |
cf05ed08 | 5093 | break; |
ae24b409 | 5094 | case I40E_LINK_SPEED_20GB: |
a9165490 | 5095 | speed = "20 G"; |
ae24b409 | 5096 | break; |
cf05ed08 | 5097 | case I40E_LINK_SPEED_10GB: |
a9165490 | 5098 | speed = "10 G"; |
cf05ed08 JB |
5099 | break; |
5100 | case I40E_LINK_SPEED_1GB: | |
a9165490 | 5101 | speed = "1000 M"; |
cf05ed08 | 5102 | break; |
5960d33f | 5103 | case I40E_LINK_SPEED_100MB: |
a9165490 | 5104 | speed = "100 M"; |
5960d33f | 5105 | break; |
cf05ed08 JB |
5106 | default: |
5107 | break; | |
5108 | } | |
5109 | ||
5110 | switch (vsi->back->hw.fc.current_mode) { | |
5111 | case I40E_FC_FULL: | |
a9165490 | 5112 | fc = "RX/TX"; |
cf05ed08 JB |
5113 | break; |
5114 | case I40E_FC_TX_PAUSE: | |
a9165490 | 5115 | fc = "TX"; |
cf05ed08 JB |
5116 | break; |
5117 | case I40E_FC_RX_PAUSE: | |
a9165490 | 5118 | fc = "RX"; |
cf05ed08 JB |
5119 | break; |
5120 | default: | |
a9165490 | 5121 | fc = "None"; |
cf05ed08 JB |
5122 | break; |
5123 | } | |
5124 | ||
a9165490 | 5125 | netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n", |
cf05ed08 JB |
5126 | speed, fc); |
5127 | } | |
4e3b35b0 | 5128 | |
41c445ff JB |
5129 | /** |
5130 | * i40e_up_complete - Finish the last steps of bringing up a connection | |
5131 | * @vsi: the VSI being configured | |
5132 | **/ | |
5133 | static int i40e_up_complete(struct i40e_vsi *vsi) | |
5134 | { | |
5135 | struct i40e_pf *pf = vsi->back; | |
5136 | int err; | |
5137 | ||
5138 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
5139 | i40e_vsi_configure_msix(vsi); | |
5140 | else | |
5141 | i40e_configure_msi_and_legacy(vsi); | |
5142 | ||
5143 | /* start rings */ | |
5144 | err = i40e_vsi_control_rings(vsi, true); | |
5145 | if (err) | |
5146 | return err; | |
5147 | ||
5148 | clear_bit(__I40E_DOWN, &vsi->state); | |
5149 | i40e_napi_enable_all(vsi); | |
5150 | i40e_vsi_enable_irq(vsi); | |
5151 | ||
5152 | if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) && | |
5153 | (vsi->netdev)) { | |
cf05ed08 | 5154 | i40e_print_link_message(vsi, true); |
41c445ff JB |
5155 | netif_tx_start_all_queues(vsi->netdev); |
5156 | netif_carrier_on(vsi->netdev); | |
6d779b41 | 5157 | } else if (vsi->netdev) { |
cf05ed08 | 5158 | i40e_print_link_message(vsi, false); |
7b592f61 CW |
5159 | /* need to check for qualified module here*/ |
5160 | if ((pf->hw.phy.link_info.link_info & | |
5161 | I40E_AQ_MEDIA_AVAILABLE) && | |
5162 | (!(pf->hw.phy.link_info.an_info & | |
5163 | I40E_AQ_QUALIFIED_MODULE))) | |
5164 | netdev_err(vsi->netdev, | |
5165 | "the driver failed to link because an unqualified module was detected."); | |
41c445ff | 5166 | } |
ca64fa4e ASJ |
5167 | |
5168 | /* replay FDIR SB filters */ | |
1e1be8f6 ASJ |
5169 | if (vsi->type == I40E_VSI_FDIR) { |
5170 | /* reset fd counters */ | |
5171 | pf->fd_add_err = pf->fd_atr_cnt = 0; | |
5172 | if (pf->fd_tcp_rule > 0) { | |
5173 | pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; | |
2e4875e3 ASJ |
5174 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
5175 | dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n"); | |
1e1be8f6 ASJ |
5176 | pf->fd_tcp_rule = 0; |
5177 | } | |
ca64fa4e | 5178 | i40e_fdir_filter_restore(vsi); |
1e1be8f6 | 5179 | } |
e3219ce6 ASJ |
5180 | |
5181 | /* On the next run of the service_task, notify any clients of the new | |
5182 | * opened netdev | |
5183 | */ | |
5184 | pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED; | |
41c445ff JB |
5185 | i40e_service_event_schedule(pf); |
5186 | ||
5187 | return 0; | |
5188 | } | |
5189 | ||
5190 | /** | |
5191 | * i40e_vsi_reinit_locked - Reset the VSI | |
5192 | * @vsi: the VSI being configured | |
5193 | * | |
5194 | * Rebuild the ring structs after some configuration | |
5195 | * has changed, e.g. MTU size. | |
5196 | **/ | |
5197 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi) | |
5198 | { | |
5199 | struct i40e_pf *pf = vsi->back; | |
5200 | ||
5201 | WARN_ON(in_interrupt()); | |
5202 | while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state)) | |
5203 | usleep_range(1000, 2000); | |
5204 | i40e_down(vsi); | |
5205 | ||
41c445ff JB |
5206 | i40e_up(vsi); |
5207 | clear_bit(__I40E_CONFIG_BUSY, &pf->state); | |
5208 | } | |
5209 | ||
5210 | /** | |
5211 | * i40e_up - Bring the connection back up after being down | |
5212 | * @vsi: the VSI being configured | |
5213 | **/ | |
5214 | int i40e_up(struct i40e_vsi *vsi) | |
5215 | { | |
5216 | int err; | |
5217 | ||
5218 | err = i40e_vsi_configure(vsi); | |
5219 | if (!err) | |
5220 | err = i40e_up_complete(vsi); | |
5221 | ||
5222 | return err; | |
5223 | } | |
5224 | ||
5225 | /** | |
5226 | * i40e_down - Shutdown the connection processing | |
5227 | * @vsi: the VSI being stopped | |
5228 | **/ | |
5229 | void i40e_down(struct i40e_vsi *vsi) | |
5230 | { | |
5231 | int i; | |
5232 | ||
5233 | /* It is assumed that the caller of this function | |
5234 | * sets the vsi->state __I40E_DOWN bit. | |
5235 | */ | |
5236 | if (vsi->netdev) { | |
5237 | netif_carrier_off(vsi->netdev); | |
5238 | netif_tx_disable(vsi->netdev); | |
5239 | } | |
5240 | i40e_vsi_disable_irq(vsi); | |
5241 | i40e_vsi_control_rings(vsi, false); | |
5242 | i40e_napi_disable_all(vsi); | |
5243 | ||
5244 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
9f65e15b AD |
5245 | i40e_clean_tx_ring(vsi->tx_rings[i]); |
5246 | i40e_clean_rx_ring(vsi->rx_rings[i]); | |
41c445ff | 5247 | } |
f980d445 CS |
5248 | |
5249 | i40e_notify_client_of_netdev_close(vsi, false); | |
5250 | ||
41c445ff JB |
5251 | } |
5252 | ||
5253 | /** | |
5254 | * i40e_setup_tc - configure multiple traffic classes | |
5255 | * @netdev: net device to configure | |
5256 | * @tc: number of traffic classes to enable | |
5257 | **/ | |
5258 | static int i40e_setup_tc(struct net_device *netdev, u8 tc) | |
5259 | { | |
5260 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
5261 | struct i40e_vsi *vsi = np->vsi; | |
5262 | struct i40e_pf *pf = vsi->back; | |
5263 | u8 enabled_tc = 0; | |
5264 | int ret = -EINVAL; | |
5265 | int i; | |
5266 | ||
5267 | /* Check if DCB enabled to continue */ | |
5268 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) { | |
5269 | netdev_info(netdev, "DCB is not enabled for adapter\n"); | |
5270 | goto exit; | |
5271 | } | |
5272 | ||
5273 | /* Check if MFP enabled */ | |
5274 | if (pf->flags & I40E_FLAG_MFP_ENABLED) { | |
5275 | netdev_info(netdev, "Configuring TC not supported in MFP mode\n"); | |
5276 | goto exit; | |
5277 | } | |
5278 | ||
5279 | /* Check whether tc count is within enabled limit */ | |
5280 | if (tc > i40e_pf_get_num_tc(pf)) { | |
5281 | netdev_info(netdev, "TC count greater than enabled on link for adapter\n"); | |
5282 | goto exit; | |
5283 | } | |
5284 | ||
5285 | /* Generate TC map for number of tc requested */ | |
5286 | for (i = 0; i < tc; i++) | |
75f5cea9 | 5287 | enabled_tc |= BIT(i); |
41c445ff JB |
5288 | |
5289 | /* Requesting same TC configuration as already enabled */ | |
5290 | if (enabled_tc == vsi->tc_config.enabled_tc) | |
5291 | return 0; | |
5292 | ||
5293 | /* Quiesce VSI queues */ | |
5294 | i40e_quiesce_vsi(vsi); | |
5295 | ||
5296 | /* Configure VSI for enabled TCs */ | |
5297 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
5298 | if (ret) { | |
5299 | netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n", | |
5300 | vsi->seid); | |
5301 | goto exit; | |
5302 | } | |
5303 | ||
5304 | /* Unquiesce VSI */ | |
5305 | i40e_unquiesce_vsi(vsi); | |
5306 | ||
5307 | exit: | |
5308 | return ret; | |
5309 | } | |
5310 | ||
e4c6734e | 5311 | #ifdef I40E_FCOE |
16e5cc64 JF |
5312 | int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, |
5313 | struct tc_to_netdev *tc) | |
e4c6734e | 5314 | #else |
16e5cc64 JF |
5315 | static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, |
5316 | struct tc_to_netdev *tc) | |
e4c6734e JF |
5317 | #endif |
5318 | { | |
16e5cc64 | 5319 | if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO) |
e4c6734e | 5320 | return -EINVAL; |
16e5cc64 | 5321 | return i40e_setup_tc(netdev, tc->tc); |
e4c6734e JF |
5322 | } |
5323 | ||
41c445ff JB |
5324 | /** |
5325 | * i40e_open - Called when a network interface is made active | |
5326 | * @netdev: network interface device structure | |
5327 | * | |
5328 | * The open entry point is called when a network interface is made | |
5329 | * active by the system (IFF_UP). At this point all resources needed | |
5330 | * for transmit and receive operations are allocated, the interrupt | |
5331 | * handler is registered with the OS, the netdev watchdog subtask is | |
5332 | * enabled, and the stack is notified that the interface is ready. | |
5333 | * | |
5334 | * Returns 0 on success, negative value on failure | |
5335 | **/ | |
38e00438 | 5336 | int i40e_open(struct net_device *netdev) |
41c445ff JB |
5337 | { |
5338 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
5339 | struct i40e_vsi *vsi = np->vsi; | |
5340 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
5341 | int err; |
5342 | ||
4eb3f768 SN |
5343 | /* disallow open during test or if eeprom is broken */ |
5344 | if (test_bit(__I40E_TESTING, &pf->state) || | |
5345 | test_bit(__I40E_BAD_EEPROM, &pf->state)) | |
41c445ff JB |
5346 | return -EBUSY; |
5347 | ||
5348 | netif_carrier_off(netdev); | |
5349 | ||
6c167f58 EK |
5350 | err = i40e_vsi_open(vsi); |
5351 | if (err) | |
5352 | return err; | |
5353 | ||
059dab69 JB |
5354 | /* configure global TSO hardware offload settings */ |
5355 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH | | |
5356 | TCP_FLAG_FIN) >> 16); | |
5357 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH | | |
5358 | TCP_FLAG_FIN | | |
5359 | TCP_FLAG_CWR) >> 16); | |
5360 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16); | |
5361 | ||
06a5f7f1 | 5362 | udp_tunnel_get_rx_info(netdev); |
e3219ce6 ASJ |
5363 | i40e_notify_client_of_netdev_open(vsi); |
5364 | ||
6c167f58 EK |
5365 | return 0; |
5366 | } | |
5367 | ||
5368 | /** | |
5369 | * i40e_vsi_open - | |
5370 | * @vsi: the VSI to open | |
5371 | * | |
5372 | * Finish initialization of the VSI. | |
5373 | * | |
5374 | * Returns 0 on success, negative value on failure | |
5375 | **/ | |
5376 | int i40e_vsi_open(struct i40e_vsi *vsi) | |
5377 | { | |
5378 | struct i40e_pf *pf = vsi->back; | |
b294ac70 | 5379 | char int_name[I40E_INT_NAME_STR_LEN]; |
6c167f58 EK |
5380 | int err; |
5381 | ||
41c445ff JB |
5382 | /* allocate descriptors */ |
5383 | err = i40e_vsi_setup_tx_resources(vsi); | |
5384 | if (err) | |
5385 | goto err_setup_tx; | |
5386 | err = i40e_vsi_setup_rx_resources(vsi); | |
5387 | if (err) | |
5388 | goto err_setup_rx; | |
5389 | ||
5390 | err = i40e_vsi_configure(vsi); | |
5391 | if (err) | |
5392 | goto err_setup_rx; | |
5393 | ||
c22e3c6c SN |
5394 | if (vsi->netdev) { |
5395 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s", | |
5396 | dev_driver_string(&pf->pdev->dev), vsi->netdev->name); | |
5397 | err = i40e_vsi_request_irq(vsi, int_name); | |
5398 | if (err) | |
5399 | goto err_setup_rx; | |
41c445ff | 5400 | |
c22e3c6c SN |
5401 | /* Notify the stack of the actual queue counts. */ |
5402 | err = netif_set_real_num_tx_queues(vsi->netdev, | |
5403 | vsi->num_queue_pairs); | |
5404 | if (err) | |
5405 | goto err_set_queues; | |
25946ddb | 5406 | |
c22e3c6c SN |
5407 | err = netif_set_real_num_rx_queues(vsi->netdev, |
5408 | vsi->num_queue_pairs); | |
5409 | if (err) | |
5410 | goto err_set_queues; | |
8a9eb7d3 SN |
5411 | |
5412 | } else if (vsi->type == I40E_VSI_FDIR) { | |
e240f674 | 5413 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir", |
b2008cbf CW |
5414 | dev_driver_string(&pf->pdev->dev), |
5415 | dev_name(&pf->pdev->dev)); | |
8a9eb7d3 | 5416 | err = i40e_vsi_request_irq(vsi, int_name); |
b2008cbf | 5417 | |
c22e3c6c | 5418 | } else { |
ce9ccb17 | 5419 | err = -EINVAL; |
6c167f58 EK |
5420 | goto err_setup_rx; |
5421 | } | |
25946ddb | 5422 | |
41c445ff JB |
5423 | err = i40e_up_complete(vsi); |
5424 | if (err) | |
5425 | goto err_up_complete; | |
5426 | ||
41c445ff JB |
5427 | return 0; |
5428 | ||
5429 | err_up_complete: | |
5430 | i40e_down(vsi); | |
25946ddb | 5431 | err_set_queues: |
41c445ff JB |
5432 | i40e_vsi_free_irq(vsi); |
5433 | err_setup_rx: | |
5434 | i40e_vsi_free_rx_resources(vsi); | |
5435 | err_setup_tx: | |
5436 | i40e_vsi_free_tx_resources(vsi); | |
5437 | if (vsi == pf->vsi[pf->lan_vsi]) | |
41a1d04b | 5438 | i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); |
41c445ff JB |
5439 | |
5440 | return err; | |
5441 | } | |
5442 | ||
17a73f6b JG |
5443 | /** |
5444 | * i40e_fdir_filter_exit - Cleans up the Flow Director accounting | |
b40c82e6 | 5445 | * @pf: Pointer to PF |
17a73f6b JG |
5446 | * |
5447 | * This function destroys the hlist where all the Flow Director | |
5448 | * filters were saved. | |
5449 | **/ | |
5450 | static void i40e_fdir_filter_exit(struct i40e_pf *pf) | |
5451 | { | |
5452 | struct i40e_fdir_filter *filter; | |
5453 | struct hlist_node *node2; | |
5454 | ||
5455 | hlist_for_each_entry_safe(filter, node2, | |
5456 | &pf->fdir_filter_list, fdir_node) { | |
5457 | hlist_del(&filter->fdir_node); | |
5458 | kfree(filter); | |
5459 | } | |
5460 | pf->fdir_pf_active_filters = 0; | |
5461 | } | |
5462 | ||
41c445ff JB |
5463 | /** |
5464 | * i40e_close - Disables a network interface | |
5465 | * @netdev: network interface device structure | |
5466 | * | |
5467 | * The close entry point is called when an interface is de-activated | |
5468 | * by the OS. The hardware is still under the driver's control, but | |
5469 | * this netdev interface is disabled. | |
5470 | * | |
5471 | * Returns 0, this is not allowed to fail | |
5472 | **/ | |
38e00438 | 5473 | int i40e_close(struct net_device *netdev) |
41c445ff JB |
5474 | { |
5475 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
5476 | struct i40e_vsi *vsi = np->vsi; | |
5477 | ||
90ef8d47 | 5478 | i40e_vsi_close(vsi); |
41c445ff JB |
5479 | |
5480 | return 0; | |
5481 | } | |
5482 | ||
5483 | /** | |
5484 | * i40e_do_reset - Start a PF or Core Reset sequence | |
5485 | * @pf: board private structure | |
5486 | * @reset_flags: which reset is requested | |
5487 | * | |
5488 | * The essential difference in resets is that the PF Reset | |
5489 | * doesn't clear the packet buffers, doesn't reset the PE | |
5490 | * firmware, and doesn't bother the other PFs on the chip. | |
5491 | **/ | |
5492 | void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags) | |
5493 | { | |
5494 | u32 val; | |
5495 | ||
5496 | WARN_ON(in_interrupt()); | |
5497 | ||
263fc48f | 5498 | |
41c445ff | 5499 | /* do the biggest reset indicated */ |
41a1d04b | 5500 | if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) { |
41c445ff JB |
5501 | |
5502 | /* Request a Global Reset | |
5503 | * | |
5504 | * This will start the chip's countdown to the actual full | |
5505 | * chip reset event, and a warning interrupt to be sent | |
5506 | * to all PFs, including the requestor. Our handler | |
5507 | * for the warning interrupt will deal with the shutdown | |
5508 | * and recovery of the switch setup. | |
5509 | */ | |
69bfb110 | 5510 | dev_dbg(&pf->pdev->dev, "GlobalR requested\n"); |
41c445ff JB |
5511 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
5512 | val |= I40E_GLGEN_RTRIG_GLOBR_MASK; | |
5513 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
5514 | ||
41a1d04b | 5515 | } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) { |
41c445ff JB |
5516 | |
5517 | /* Request a Core Reset | |
5518 | * | |
5519 | * Same as Global Reset, except does *not* include the MAC/PHY | |
5520 | */ | |
69bfb110 | 5521 | dev_dbg(&pf->pdev->dev, "CoreR requested\n"); |
41c445ff JB |
5522 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
5523 | val |= I40E_GLGEN_RTRIG_CORER_MASK; | |
5524 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
5525 | i40e_flush(&pf->hw); | |
5526 | ||
41a1d04b | 5527 | } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) { |
41c445ff JB |
5528 | |
5529 | /* Request a PF Reset | |
5530 | * | |
5531 | * Resets only the PF-specific registers | |
5532 | * | |
5533 | * This goes directly to the tear-down and rebuild of | |
5534 | * the switch, since we need to do all the recovery as | |
5535 | * for the Core Reset. | |
5536 | */ | |
69bfb110 | 5537 | dev_dbg(&pf->pdev->dev, "PFR requested\n"); |
41c445ff JB |
5538 | i40e_handle_reset_warning(pf); |
5539 | ||
41a1d04b | 5540 | } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) { |
41c445ff JB |
5541 | int v; |
5542 | ||
5543 | /* Find the VSI(s) that requested a re-init */ | |
5544 | dev_info(&pf->pdev->dev, | |
5545 | "VSI reinit requested\n"); | |
505682cd | 5546 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 5547 | struct i40e_vsi *vsi = pf->vsi[v]; |
6995b36c | 5548 | |
41c445ff JB |
5549 | if (vsi != NULL && |
5550 | test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) { | |
5551 | i40e_vsi_reinit_locked(pf->vsi[v]); | |
5552 | clear_bit(__I40E_REINIT_REQUESTED, &vsi->state); | |
5553 | } | |
5554 | } | |
41a1d04b | 5555 | } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) { |
b5d06f05 NP |
5556 | int v; |
5557 | ||
5558 | /* Find the VSI(s) that needs to be brought down */ | |
5559 | dev_info(&pf->pdev->dev, "VSI down requested\n"); | |
5560 | for (v = 0; v < pf->num_alloc_vsi; v++) { | |
5561 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 5562 | |
b5d06f05 NP |
5563 | if (vsi != NULL && |
5564 | test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) { | |
5565 | set_bit(__I40E_DOWN, &vsi->state); | |
5566 | i40e_down(vsi); | |
5567 | clear_bit(__I40E_DOWN_REQUESTED, &vsi->state); | |
5568 | } | |
5569 | } | |
41c445ff JB |
5570 | } else { |
5571 | dev_info(&pf->pdev->dev, | |
5572 | "bad reset request 0x%08x\n", reset_flags); | |
41c445ff JB |
5573 | } |
5574 | } | |
5575 | ||
4e3b35b0 NP |
5576 | #ifdef CONFIG_I40E_DCB |
5577 | /** | |
5578 | * i40e_dcb_need_reconfig - Check if DCB needs reconfig | |
5579 | * @pf: board private structure | |
5580 | * @old_cfg: current DCB config | |
5581 | * @new_cfg: new DCB config | |
5582 | **/ | |
5583 | bool i40e_dcb_need_reconfig(struct i40e_pf *pf, | |
5584 | struct i40e_dcbx_config *old_cfg, | |
5585 | struct i40e_dcbx_config *new_cfg) | |
5586 | { | |
5587 | bool need_reconfig = false; | |
5588 | ||
5589 | /* Check if ETS configuration has changed */ | |
5590 | if (memcmp(&new_cfg->etscfg, | |
5591 | &old_cfg->etscfg, | |
5592 | sizeof(new_cfg->etscfg))) { | |
5593 | /* If Priority Table has changed reconfig is needed */ | |
5594 | if (memcmp(&new_cfg->etscfg.prioritytable, | |
5595 | &old_cfg->etscfg.prioritytable, | |
5596 | sizeof(new_cfg->etscfg.prioritytable))) { | |
5597 | need_reconfig = true; | |
69bfb110 | 5598 | dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n"); |
4e3b35b0 NP |
5599 | } |
5600 | ||
5601 | if (memcmp(&new_cfg->etscfg.tcbwtable, | |
5602 | &old_cfg->etscfg.tcbwtable, | |
5603 | sizeof(new_cfg->etscfg.tcbwtable))) | |
69bfb110 | 5604 | dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n"); |
4e3b35b0 NP |
5605 | |
5606 | if (memcmp(&new_cfg->etscfg.tsatable, | |
5607 | &old_cfg->etscfg.tsatable, | |
5608 | sizeof(new_cfg->etscfg.tsatable))) | |
69bfb110 | 5609 | dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n"); |
4e3b35b0 NP |
5610 | } |
5611 | ||
5612 | /* Check if PFC configuration has changed */ | |
5613 | if (memcmp(&new_cfg->pfc, | |
5614 | &old_cfg->pfc, | |
5615 | sizeof(new_cfg->pfc))) { | |
5616 | need_reconfig = true; | |
69bfb110 | 5617 | dev_dbg(&pf->pdev->dev, "PFC config change detected.\n"); |
4e3b35b0 NP |
5618 | } |
5619 | ||
5620 | /* Check if APP Table has changed */ | |
5621 | if (memcmp(&new_cfg->app, | |
5622 | &old_cfg->app, | |
3d9667a9 | 5623 | sizeof(new_cfg->app))) { |
4e3b35b0 | 5624 | need_reconfig = true; |
69bfb110 | 5625 | dev_dbg(&pf->pdev->dev, "APP Table change detected.\n"); |
3d9667a9 | 5626 | } |
4e3b35b0 | 5627 | |
fb43201f | 5628 | dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig); |
4e3b35b0 NP |
5629 | return need_reconfig; |
5630 | } | |
5631 | ||
5632 | /** | |
5633 | * i40e_handle_lldp_event - Handle LLDP Change MIB event | |
5634 | * @pf: board private structure | |
5635 | * @e: event info posted on ARQ | |
5636 | **/ | |
5637 | static int i40e_handle_lldp_event(struct i40e_pf *pf, | |
5638 | struct i40e_arq_event_info *e) | |
5639 | { | |
5640 | struct i40e_aqc_lldp_get_mib *mib = | |
5641 | (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw; | |
5642 | struct i40e_hw *hw = &pf->hw; | |
4e3b35b0 NP |
5643 | struct i40e_dcbx_config tmp_dcbx_cfg; |
5644 | bool need_reconfig = false; | |
5645 | int ret = 0; | |
5646 | u8 type; | |
5647 | ||
4d9b6043 NP |
5648 | /* Not DCB capable or capability disabled */ |
5649 | if (!(pf->flags & I40E_FLAG_DCB_CAPABLE)) | |
5650 | return ret; | |
5651 | ||
4e3b35b0 NP |
5652 | /* Ignore if event is not for Nearest Bridge */ |
5653 | type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) | |
5654 | & I40E_AQ_LLDP_BRIDGE_TYPE_MASK); | |
fb43201f | 5655 | dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type); |
4e3b35b0 NP |
5656 | if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE) |
5657 | return ret; | |
5658 | ||
5659 | /* Check MIB Type and return if event for Remote MIB update */ | |
5660 | type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK; | |
9fa61dd2 | 5661 | dev_dbg(&pf->pdev->dev, |
fb43201f | 5662 | "LLDP event mib type %s\n", type ? "remote" : "local"); |
4e3b35b0 NP |
5663 | if (type == I40E_AQ_LLDP_MIB_REMOTE) { |
5664 | /* Update the remote cached instance and return */ | |
5665 | ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE, | |
5666 | I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, | |
5667 | &hw->remote_dcbx_config); | |
5668 | goto exit; | |
5669 | } | |
5670 | ||
9fa61dd2 | 5671 | /* Store the old configuration */ |
1a2f6248 | 5672 | tmp_dcbx_cfg = hw->local_dcbx_config; |
9fa61dd2 | 5673 | |
750fcbcf NP |
5674 | /* Reset the old DCBx configuration data */ |
5675 | memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config)); | |
9fa61dd2 NP |
5676 | /* Get updated DCBX data from firmware */ |
5677 | ret = i40e_get_dcb_config(&pf->hw); | |
4e3b35b0 | 5678 | if (ret) { |
f1c7e72e SN |
5679 | dev_info(&pf->pdev->dev, |
5680 | "Failed querying DCB configuration data from firmware, err %s aq_err %s\n", | |
5681 | i40e_stat_str(&pf->hw, ret), | |
5682 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
5683 | goto exit; |
5684 | } | |
5685 | ||
5686 | /* No change detected in DCBX configs */ | |
750fcbcf NP |
5687 | if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config, |
5688 | sizeof(tmp_dcbx_cfg))) { | |
69bfb110 | 5689 | dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n"); |
4e3b35b0 NP |
5690 | goto exit; |
5691 | } | |
5692 | ||
750fcbcf NP |
5693 | need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, |
5694 | &hw->local_dcbx_config); | |
4e3b35b0 | 5695 | |
750fcbcf | 5696 | i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config); |
4e3b35b0 NP |
5697 | |
5698 | if (!need_reconfig) | |
5699 | goto exit; | |
5700 | ||
4d9b6043 | 5701 | /* Enable DCB tagging only when more than one TC */ |
750fcbcf | 5702 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
4d9b6043 NP |
5703 | pf->flags |= I40E_FLAG_DCB_ENABLED; |
5704 | else | |
5705 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
5706 | ||
69129dc3 | 5707 | set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state); |
4e3b35b0 NP |
5708 | /* Reconfiguration needed quiesce all VSIs */ |
5709 | i40e_pf_quiesce_all_vsi(pf); | |
5710 | ||
5711 | /* Changes in configuration update VEB/VSI */ | |
5712 | i40e_dcb_reconfigure(pf); | |
5713 | ||
2fd75f31 NP |
5714 | ret = i40e_resume_port_tx(pf); |
5715 | ||
69129dc3 | 5716 | clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state); |
2fd75f31 | 5717 | /* In case of error no point in resuming VSIs */ |
69129dc3 NP |
5718 | if (ret) |
5719 | goto exit; | |
5720 | ||
3fe06f41 NP |
5721 | /* Wait for the PF's queues to be disabled */ |
5722 | ret = i40e_pf_wait_queues_disabled(pf); | |
11e47708 PN |
5723 | if (ret) { |
5724 | /* Schedule PF reset to recover */ | |
5725 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
5726 | i40e_service_event_schedule(pf); | |
5727 | } else { | |
2fd75f31 | 5728 | i40e_pf_unquiesce_all_vsi(pf); |
85a1aab7 NP |
5729 | /* Notify the client for the DCB changes */ |
5730 | i40e_notify_client_of_l2_param_changes(pf->vsi[pf->lan_vsi]); | |
11e47708 PN |
5731 | } |
5732 | ||
4e3b35b0 NP |
5733 | exit: |
5734 | return ret; | |
5735 | } | |
5736 | #endif /* CONFIG_I40E_DCB */ | |
5737 | ||
23326186 ASJ |
5738 | /** |
5739 | * i40e_do_reset_safe - Protected reset path for userland calls. | |
5740 | * @pf: board private structure | |
5741 | * @reset_flags: which reset is requested | |
5742 | * | |
5743 | **/ | |
5744 | void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags) | |
5745 | { | |
5746 | rtnl_lock(); | |
5747 | i40e_do_reset(pf, reset_flags); | |
5748 | rtnl_unlock(); | |
5749 | } | |
5750 | ||
41c445ff JB |
5751 | /** |
5752 | * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event | |
5753 | * @pf: board private structure | |
5754 | * @e: event info posted on ARQ | |
5755 | * | |
5756 | * Handler for LAN Queue Overflow Event generated by the firmware for PF | |
5757 | * and VF queues | |
5758 | **/ | |
5759 | static void i40e_handle_lan_overflow_event(struct i40e_pf *pf, | |
5760 | struct i40e_arq_event_info *e) | |
5761 | { | |
5762 | struct i40e_aqc_lan_overflow *data = | |
5763 | (struct i40e_aqc_lan_overflow *)&e->desc.params.raw; | |
5764 | u32 queue = le32_to_cpu(data->prtdcb_rupto); | |
5765 | u32 qtx_ctl = le32_to_cpu(data->otx_ctl); | |
5766 | struct i40e_hw *hw = &pf->hw; | |
5767 | struct i40e_vf *vf; | |
5768 | u16 vf_id; | |
5769 | ||
69bfb110 JB |
5770 | dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n", |
5771 | queue, qtx_ctl); | |
41c445ff JB |
5772 | |
5773 | /* Queue belongs to VF, find the VF and issue VF reset */ | |
5774 | if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK) | |
5775 | >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) { | |
5776 | vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK) | |
5777 | >> I40E_QTX_CTL_VFVM_INDX_SHIFT); | |
5778 | vf_id -= hw->func_caps.vf_base_id; | |
5779 | vf = &pf->vf[vf_id]; | |
5780 | i40e_vc_notify_vf_reset(vf); | |
5781 | /* Allow VF to process pending reset notification */ | |
5782 | msleep(20); | |
5783 | i40e_reset_vf(vf, false); | |
5784 | } | |
5785 | } | |
5786 | ||
5787 | /** | |
5788 | * i40e_service_event_complete - Finish up the service event | |
5789 | * @pf: board private structure | |
5790 | **/ | |
5791 | static void i40e_service_event_complete(struct i40e_pf *pf) | |
5792 | { | |
b875f99b | 5793 | WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state)); |
41c445ff JB |
5794 | |
5795 | /* flush memory to make sure state is correct before next watchog */ | |
4e857c58 | 5796 | smp_mb__before_atomic(); |
41c445ff JB |
5797 | clear_bit(__I40E_SERVICE_SCHED, &pf->state); |
5798 | } | |
5799 | ||
55a5e60b | 5800 | /** |
12957388 ASJ |
5801 | * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters |
5802 | * @pf: board private structure | |
5803 | **/ | |
04294e38 | 5804 | u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf) |
12957388 | 5805 | { |
04294e38 | 5806 | u32 val, fcnt_prog; |
12957388 ASJ |
5807 | |
5808 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); | |
5809 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK); | |
5810 | return fcnt_prog; | |
5811 | } | |
5812 | ||
5813 | /** | |
04294e38 | 5814 | * i40e_get_current_fd_count - Get total FD filters programmed for this PF |
55a5e60b ASJ |
5815 | * @pf: board private structure |
5816 | **/ | |
04294e38 | 5817 | u32 i40e_get_current_fd_count(struct i40e_pf *pf) |
55a5e60b | 5818 | { |
04294e38 ASJ |
5819 | u32 val, fcnt_prog; |
5820 | ||
55a5e60b ASJ |
5821 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); |
5822 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) + | |
5823 | ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >> | |
5824 | I40E_PFQF_FDSTAT_BEST_CNT_SHIFT); | |
5825 | return fcnt_prog; | |
5826 | } | |
1e1be8f6 | 5827 | |
04294e38 ASJ |
5828 | /** |
5829 | * i40e_get_global_fd_count - Get total FD filters programmed on device | |
5830 | * @pf: board private structure | |
5831 | **/ | |
5832 | u32 i40e_get_global_fd_count(struct i40e_pf *pf) | |
5833 | { | |
5834 | u32 val, fcnt_prog; | |
5835 | ||
5836 | val = rd32(&pf->hw, I40E_GLQF_FDCNT_0); | |
5837 | fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) + | |
5838 | ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >> | |
5839 | I40E_GLQF_FDCNT_0_BESTCNT_SHIFT); | |
5840 | return fcnt_prog; | |
5841 | } | |
5842 | ||
55a5e60b ASJ |
5843 | /** |
5844 | * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled | |
5845 | * @pf: board private structure | |
5846 | **/ | |
5847 | void i40e_fdir_check_and_reenable(struct i40e_pf *pf) | |
5848 | { | |
3487b6c3 | 5849 | struct i40e_fdir_filter *filter; |
55a5e60b | 5850 | u32 fcnt_prog, fcnt_avail; |
3487b6c3 | 5851 | struct hlist_node *node; |
55a5e60b | 5852 | |
1e1be8f6 ASJ |
5853 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) |
5854 | return; | |
5855 | ||
55a5e60b ASJ |
5856 | /* Check if, FD SB or ATR was auto disabled and if there is enough room |
5857 | * to re-enable | |
5858 | */ | |
04294e38 | 5859 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 5860 | fcnt_avail = pf->fdir_pf_filter_count; |
1e1be8f6 ASJ |
5861 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) || |
5862 | (pf->fd_add_err == 0) || | |
5863 | (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) { | |
55a5e60b ASJ |
5864 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
5865 | (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) { | |
5866 | pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
2e4875e3 ASJ |
5867 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
5868 | dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n"); | |
55a5e60b ASJ |
5869 | } |
5870 | } | |
5871 | /* Wait for some more space to be available to turn on ATR */ | |
5872 | if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) { | |
5873 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && | |
5874 | (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) { | |
5875 | pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED; | |
2e4875e3 ASJ |
5876 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
5877 | dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n"); | |
55a5e60b ASJ |
5878 | } |
5879 | } | |
3487b6c3 CW |
5880 | |
5881 | /* if hw had a problem adding a filter, delete it */ | |
5882 | if (pf->fd_inv > 0) { | |
5883 | hlist_for_each_entry_safe(filter, node, | |
5884 | &pf->fdir_filter_list, fdir_node) { | |
5885 | if (filter->fd_id == pf->fd_inv) { | |
5886 | hlist_del(&filter->fdir_node); | |
5887 | kfree(filter); | |
5888 | pf->fdir_pf_active_filters--; | |
5889 | } | |
5890 | } | |
5891 | } | |
55a5e60b ASJ |
5892 | } |
5893 | ||
1e1be8f6 | 5894 | #define I40E_MIN_FD_FLUSH_INTERVAL 10 |
04294e38 | 5895 | #define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30 |
1e1be8f6 ASJ |
5896 | /** |
5897 | * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB | |
5898 | * @pf: board private structure | |
5899 | **/ | |
5900 | static void i40e_fdir_flush_and_replay(struct i40e_pf *pf) | |
5901 | { | |
04294e38 | 5902 | unsigned long min_flush_time; |
1e1be8f6 | 5903 | int flush_wait_retry = 50; |
04294e38 ASJ |
5904 | bool disable_atr = false; |
5905 | int fd_room; | |
1e1be8f6 ASJ |
5906 | int reg; |
5907 | ||
1790ed0c AA |
5908 | if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))) |
5909 | return; | |
5910 | ||
a5fdaf34 JB |
5911 | if (!time_after(jiffies, pf->fd_flush_timestamp + |
5912 | (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) | |
5913 | return; | |
04294e38 | 5914 | |
a5fdaf34 JB |
5915 | /* If the flush is happening too quick and we have mostly SB rules we |
5916 | * should not re-enable ATR for some time. | |
5917 | */ | |
5918 | min_flush_time = pf->fd_flush_timestamp + | |
5919 | (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ); | |
5920 | fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters; | |
5921 | ||
5922 | if (!(time_after(jiffies, min_flush_time)) && | |
5923 | (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) { | |
5924 | if (I40E_DEBUG_FD & pf->hw.debug_mask) | |
5925 | dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n"); | |
5926 | disable_atr = true; | |
5927 | } | |
5928 | ||
5929 | pf->fd_flush_timestamp = jiffies; | |
5930 | pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; | |
5931 | /* flush all filters */ | |
5932 | wr32(&pf->hw, I40E_PFQF_CTL_1, | |
5933 | I40E_PFQF_CTL_1_CLEARFDTABLE_MASK); | |
5934 | i40e_flush(&pf->hw); | |
5935 | pf->fd_flush_cnt++; | |
5936 | pf->fd_add_err = 0; | |
5937 | do { | |
5938 | /* Check FD flush status every 5-6msec */ | |
5939 | usleep_range(5000, 6000); | |
5940 | reg = rd32(&pf->hw, I40E_PFQF_CTL_1); | |
5941 | if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK)) | |
5942 | break; | |
5943 | } while (flush_wait_retry--); | |
5944 | if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) { | |
5945 | dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n"); | |
5946 | } else { | |
5947 | /* replay sideband filters */ | |
5948 | i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]); | |
5949 | if (!disable_atr) | |
5950 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
5951 | clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state); | |
5952 | if (I40E_DEBUG_FD & pf->hw.debug_mask) | |
5953 | dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n"); | |
1e1be8f6 ASJ |
5954 | } |
5955 | } | |
5956 | ||
5957 | /** | |
5958 | * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed | |
5959 | * @pf: board private structure | |
5960 | **/ | |
04294e38 | 5961 | u32 i40e_get_current_atr_cnt(struct i40e_pf *pf) |
1e1be8f6 ASJ |
5962 | { |
5963 | return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters; | |
5964 | } | |
5965 | ||
5966 | /* We can see up to 256 filter programming desc in transit if the filters are | |
5967 | * being applied really fast; before we see the first | |
5968 | * filter miss error on Rx queue 0. Accumulating enough error messages before | |
5969 | * reacting will make sure we don't cause flush too often. | |
5970 | */ | |
5971 | #define I40E_MAX_FD_PROGRAM_ERROR 256 | |
5972 | ||
41c445ff JB |
5973 | /** |
5974 | * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table | |
5975 | * @pf: board private structure | |
5976 | **/ | |
5977 | static void i40e_fdir_reinit_subtask(struct i40e_pf *pf) | |
5978 | { | |
41c445ff | 5979 | |
41c445ff JB |
5980 | /* if interface is down do nothing */ |
5981 | if (test_bit(__I40E_DOWN, &pf->state)) | |
5982 | return; | |
1e1be8f6 | 5983 | |
1790ed0c AA |
5984 | if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))) |
5985 | return; | |
5986 | ||
04294e38 | 5987 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) |
1e1be8f6 ASJ |
5988 | i40e_fdir_flush_and_replay(pf); |
5989 | ||
55a5e60b ASJ |
5990 | i40e_fdir_check_and_reenable(pf); |
5991 | ||
41c445ff JB |
5992 | } |
5993 | ||
5994 | /** | |
5995 | * i40e_vsi_link_event - notify VSI of a link event | |
5996 | * @vsi: vsi to be notified | |
5997 | * @link_up: link up or down | |
5998 | **/ | |
5999 | static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up) | |
6000 | { | |
32b5b811 | 6001 | if (!vsi || test_bit(__I40E_DOWN, &vsi->state)) |
41c445ff JB |
6002 | return; |
6003 | ||
6004 | switch (vsi->type) { | |
6005 | case I40E_VSI_MAIN: | |
38e00438 VD |
6006 | #ifdef I40E_FCOE |
6007 | case I40E_VSI_FCOE: | |
6008 | #endif | |
41c445ff JB |
6009 | if (!vsi->netdev || !vsi->netdev_registered) |
6010 | break; | |
6011 | ||
6012 | if (link_up) { | |
6013 | netif_carrier_on(vsi->netdev); | |
6014 | netif_tx_wake_all_queues(vsi->netdev); | |
6015 | } else { | |
6016 | netif_carrier_off(vsi->netdev); | |
6017 | netif_tx_stop_all_queues(vsi->netdev); | |
6018 | } | |
6019 | break; | |
6020 | ||
6021 | case I40E_VSI_SRIOV: | |
41c445ff JB |
6022 | case I40E_VSI_VMDQ2: |
6023 | case I40E_VSI_CTRL: | |
e3219ce6 | 6024 | case I40E_VSI_IWARP: |
41c445ff JB |
6025 | case I40E_VSI_MIRROR: |
6026 | default: | |
6027 | /* there is no notification for other VSIs */ | |
6028 | break; | |
6029 | } | |
6030 | } | |
6031 | ||
6032 | /** | |
6033 | * i40e_veb_link_event - notify elements on the veb of a link event | |
6034 | * @veb: veb to be notified | |
6035 | * @link_up: link up or down | |
6036 | **/ | |
6037 | static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up) | |
6038 | { | |
6039 | struct i40e_pf *pf; | |
6040 | int i; | |
6041 | ||
6042 | if (!veb || !veb->pf) | |
6043 | return; | |
6044 | pf = veb->pf; | |
6045 | ||
6046 | /* depth first... */ | |
6047 | for (i = 0; i < I40E_MAX_VEB; i++) | |
6048 | if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid)) | |
6049 | i40e_veb_link_event(pf->veb[i], link_up); | |
6050 | ||
6051 | /* ... now the local VSIs */ | |
505682cd | 6052 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
6053 | if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid)) |
6054 | i40e_vsi_link_event(pf->vsi[i], link_up); | |
6055 | } | |
6056 | ||
6057 | /** | |
6058 | * i40e_link_event - Update netif_carrier status | |
6059 | * @pf: board private structure | |
6060 | **/ | |
6061 | static void i40e_link_event(struct i40e_pf *pf) | |
6062 | { | |
320684cd | 6063 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
fef59ddf | 6064 | u8 new_link_speed, old_link_speed; |
a72a5abc JB |
6065 | i40e_status status; |
6066 | bool new_link, old_link; | |
41c445ff | 6067 | |
1f9610e4 CS |
6068 | /* save off old link status information */ |
6069 | pf->hw.phy.link_info_old = pf->hw.phy.link_info; | |
6070 | ||
1e701e09 JB |
6071 | /* set this to force the get_link_status call to refresh state */ |
6072 | pf->hw.phy.get_link_info = true; | |
6073 | ||
41c445ff | 6074 | old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP); |
a72a5abc JB |
6075 | |
6076 | status = i40e_get_link_status(&pf->hw, &new_link); | |
6077 | if (status) { | |
6078 | dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n", | |
6079 | status); | |
6080 | return; | |
6081 | } | |
6082 | ||
fef59ddf CS |
6083 | old_link_speed = pf->hw.phy.link_info_old.link_speed; |
6084 | new_link_speed = pf->hw.phy.link_info.link_speed; | |
41c445ff | 6085 | |
1e701e09 | 6086 | if (new_link == old_link && |
fef59ddf | 6087 | new_link_speed == old_link_speed && |
320684cd MW |
6088 | (test_bit(__I40E_DOWN, &vsi->state) || |
6089 | new_link == netif_carrier_ok(vsi->netdev))) | |
41c445ff | 6090 | return; |
320684cd MW |
6091 | |
6092 | if (!test_bit(__I40E_DOWN, &vsi->state)) | |
6093 | i40e_print_link_message(vsi, new_link); | |
41c445ff JB |
6094 | |
6095 | /* Notify the base of the switch tree connected to | |
6096 | * the link. Floating VEBs are not notified. | |
6097 | */ | |
6098 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
6099 | i40e_veb_link_event(pf->veb[pf->lan_veb], new_link); | |
6100 | else | |
320684cd | 6101 | i40e_vsi_link_event(vsi, new_link); |
41c445ff JB |
6102 | |
6103 | if (pf->vf) | |
6104 | i40e_vc_notify_link_state(pf); | |
beb0dff1 JK |
6105 | |
6106 | if (pf->flags & I40E_FLAG_PTP) | |
6107 | i40e_ptp_set_increment(pf); | |
41c445ff JB |
6108 | } |
6109 | ||
41c445ff | 6110 | /** |
21536717 | 6111 | * i40e_watchdog_subtask - periodic checks not using event driven response |
41c445ff JB |
6112 | * @pf: board private structure |
6113 | **/ | |
6114 | static void i40e_watchdog_subtask(struct i40e_pf *pf) | |
6115 | { | |
6116 | int i; | |
6117 | ||
6118 | /* if interface is down do nothing */ | |
6119 | if (test_bit(__I40E_DOWN, &pf->state) || | |
6120 | test_bit(__I40E_CONFIG_BUSY, &pf->state)) | |
6121 | return; | |
6122 | ||
21536717 SN |
6123 | /* make sure we don't do these things too often */ |
6124 | if (time_before(jiffies, (pf->service_timer_previous + | |
6125 | pf->service_timer_period))) | |
6126 | return; | |
6127 | pf->service_timer_previous = jiffies; | |
6128 | ||
9ac77266 SN |
6129 | if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED) |
6130 | i40e_link_event(pf); | |
21536717 | 6131 | |
41c445ff JB |
6132 | /* Update the stats for active netdevs so the network stack |
6133 | * can look at updated numbers whenever it cares to | |
6134 | */ | |
505682cd | 6135 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
6136 | if (pf->vsi[i] && pf->vsi[i]->netdev) |
6137 | i40e_update_stats(pf->vsi[i]); | |
6138 | ||
d1a8d275 ASJ |
6139 | if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) { |
6140 | /* Update the stats for the active switching components */ | |
6141 | for (i = 0; i < I40E_MAX_VEB; i++) | |
6142 | if (pf->veb[i]) | |
6143 | i40e_update_veb_stats(pf->veb[i]); | |
6144 | } | |
beb0dff1 JK |
6145 | |
6146 | i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]); | |
41c445ff JB |
6147 | } |
6148 | ||
6149 | /** | |
6150 | * i40e_reset_subtask - Set up for resetting the device and driver | |
6151 | * @pf: board private structure | |
6152 | **/ | |
6153 | static void i40e_reset_subtask(struct i40e_pf *pf) | |
6154 | { | |
6155 | u32 reset_flags = 0; | |
6156 | ||
23326186 | 6157 | rtnl_lock(); |
41c445ff | 6158 | if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) { |
75f5cea9 | 6159 | reset_flags |= BIT(__I40E_REINIT_REQUESTED); |
41c445ff JB |
6160 | clear_bit(__I40E_REINIT_REQUESTED, &pf->state); |
6161 | } | |
6162 | if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) { | |
75f5cea9 | 6163 | reset_flags |= BIT(__I40E_PF_RESET_REQUESTED); |
41c445ff JB |
6164 | clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state); |
6165 | } | |
6166 | if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) { | |
75f5cea9 | 6167 | reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED); |
41c445ff JB |
6168 | clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state); |
6169 | } | |
6170 | if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) { | |
75f5cea9 | 6171 | reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED); |
41c445ff JB |
6172 | clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state); |
6173 | } | |
b5d06f05 | 6174 | if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) { |
75f5cea9 | 6175 | reset_flags |= BIT(__I40E_DOWN_REQUESTED); |
b5d06f05 NP |
6176 | clear_bit(__I40E_DOWN_REQUESTED, &pf->state); |
6177 | } | |
41c445ff JB |
6178 | |
6179 | /* If there's a recovery already waiting, it takes | |
6180 | * precedence before starting a new reset sequence. | |
6181 | */ | |
6182 | if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) { | |
6183 | i40e_handle_reset_warning(pf); | |
23326186 | 6184 | goto unlock; |
41c445ff JB |
6185 | } |
6186 | ||
6187 | /* If we're already down or resetting, just bail */ | |
6188 | if (reset_flags && | |
6189 | !test_bit(__I40E_DOWN, &pf->state) && | |
6190 | !test_bit(__I40E_CONFIG_BUSY, &pf->state)) | |
6191 | i40e_do_reset(pf, reset_flags); | |
23326186 ASJ |
6192 | |
6193 | unlock: | |
6194 | rtnl_unlock(); | |
41c445ff JB |
6195 | } |
6196 | ||
6197 | /** | |
6198 | * i40e_handle_link_event - Handle link event | |
6199 | * @pf: board private structure | |
6200 | * @e: event info posted on ARQ | |
6201 | **/ | |
6202 | static void i40e_handle_link_event(struct i40e_pf *pf, | |
6203 | struct i40e_arq_event_info *e) | |
6204 | { | |
41c445ff JB |
6205 | struct i40e_aqc_get_link_status *status = |
6206 | (struct i40e_aqc_get_link_status *)&e->desc.params.raw; | |
41c445ff | 6207 | |
1e701e09 JB |
6208 | /* Do a new status request to re-enable LSE reporting |
6209 | * and load new status information into the hw struct | |
6210 | * This completely ignores any state information | |
6211 | * in the ARQ event info, instead choosing to always | |
6212 | * issue the AQ update link status command. | |
6213 | */ | |
6214 | i40e_link_event(pf); | |
6215 | ||
7b592f61 CW |
6216 | /* check for unqualified module, if link is down */ |
6217 | if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && | |
6218 | (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && | |
6219 | (!(status->link_info & I40E_AQ_LINK_UP))) | |
6220 | dev_err(&pf->pdev->dev, | |
6221 | "The driver failed to link because an unqualified module was detected.\n"); | |
41c445ff JB |
6222 | } |
6223 | ||
6224 | /** | |
6225 | * i40e_clean_adminq_subtask - Clean the AdminQ rings | |
6226 | * @pf: board private structure | |
6227 | **/ | |
6228 | static void i40e_clean_adminq_subtask(struct i40e_pf *pf) | |
6229 | { | |
6230 | struct i40e_arq_event_info event; | |
6231 | struct i40e_hw *hw = &pf->hw; | |
6232 | u16 pending, i = 0; | |
6233 | i40e_status ret; | |
6234 | u16 opcode; | |
86df242b | 6235 | u32 oldval; |
41c445ff JB |
6236 | u32 val; |
6237 | ||
a316f651 ASJ |
6238 | /* Do not run clean AQ when PF reset fails */ |
6239 | if (test_bit(__I40E_RESET_FAILED, &pf->state)) | |
6240 | return; | |
6241 | ||
86df242b SN |
6242 | /* check for error indications */ |
6243 | val = rd32(&pf->hw, pf->hw.aq.arq.len); | |
6244 | oldval = val; | |
6245 | if (val & I40E_PF_ARQLEN_ARQVFE_MASK) { | |
75eb73c1 MW |
6246 | if (hw->debug_mask & I40E_DEBUG_AQ) |
6247 | dev_info(&pf->pdev->dev, "ARQ VF Error detected\n"); | |
86df242b SN |
6248 | val &= ~I40E_PF_ARQLEN_ARQVFE_MASK; |
6249 | } | |
6250 | if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) { | |
75eb73c1 MW |
6251 | if (hw->debug_mask & I40E_DEBUG_AQ) |
6252 | dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n"); | |
86df242b | 6253 | val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK; |
1d0a4ada | 6254 | pf->arq_overflows++; |
86df242b SN |
6255 | } |
6256 | if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) { | |
75eb73c1 MW |
6257 | if (hw->debug_mask & I40E_DEBUG_AQ) |
6258 | dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n"); | |
86df242b SN |
6259 | val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK; |
6260 | } | |
6261 | if (oldval != val) | |
6262 | wr32(&pf->hw, pf->hw.aq.arq.len, val); | |
6263 | ||
6264 | val = rd32(&pf->hw, pf->hw.aq.asq.len); | |
6265 | oldval = val; | |
6266 | if (val & I40E_PF_ATQLEN_ATQVFE_MASK) { | |
75eb73c1 MW |
6267 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
6268 | dev_info(&pf->pdev->dev, "ASQ VF Error detected\n"); | |
86df242b SN |
6269 | val &= ~I40E_PF_ATQLEN_ATQVFE_MASK; |
6270 | } | |
6271 | if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) { | |
75eb73c1 MW |
6272 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
6273 | dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n"); | |
86df242b SN |
6274 | val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK; |
6275 | } | |
6276 | if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) { | |
75eb73c1 MW |
6277 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
6278 | dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n"); | |
86df242b SN |
6279 | val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK; |
6280 | } | |
6281 | if (oldval != val) | |
6282 | wr32(&pf->hw, pf->hw.aq.asq.len, val); | |
6283 | ||
1001dc37 MW |
6284 | event.buf_len = I40E_MAX_AQ_BUF_SIZE; |
6285 | event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); | |
41c445ff JB |
6286 | if (!event.msg_buf) |
6287 | return; | |
6288 | ||
6289 | do { | |
6290 | ret = i40e_clean_arq_element(hw, &event, &pending); | |
56497978 | 6291 | if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) |
41c445ff | 6292 | break; |
56497978 | 6293 | else if (ret) { |
41c445ff JB |
6294 | dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret); |
6295 | break; | |
6296 | } | |
6297 | ||
6298 | opcode = le16_to_cpu(event.desc.opcode); | |
6299 | switch (opcode) { | |
6300 | ||
6301 | case i40e_aqc_opc_get_link_status: | |
6302 | i40e_handle_link_event(pf, &event); | |
6303 | break; | |
6304 | case i40e_aqc_opc_send_msg_to_pf: | |
6305 | ret = i40e_vc_process_vf_msg(pf, | |
6306 | le16_to_cpu(event.desc.retval), | |
6307 | le32_to_cpu(event.desc.cookie_high), | |
6308 | le32_to_cpu(event.desc.cookie_low), | |
6309 | event.msg_buf, | |
1001dc37 | 6310 | event.msg_len); |
41c445ff JB |
6311 | break; |
6312 | case i40e_aqc_opc_lldp_update_mib: | |
69bfb110 | 6313 | dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n"); |
4e3b35b0 NP |
6314 | #ifdef CONFIG_I40E_DCB |
6315 | rtnl_lock(); | |
6316 | ret = i40e_handle_lldp_event(pf, &event); | |
6317 | rtnl_unlock(); | |
6318 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
6319 | break; |
6320 | case i40e_aqc_opc_event_lan_overflow: | |
69bfb110 | 6321 | dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n"); |
41c445ff JB |
6322 | i40e_handle_lan_overflow_event(pf, &event); |
6323 | break; | |
0467bc91 SN |
6324 | case i40e_aqc_opc_send_msg_to_peer: |
6325 | dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n"); | |
6326 | break; | |
91a0f930 SN |
6327 | case i40e_aqc_opc_nvm_erase: |
6328 | case i40e_aqc_opc_nvm_update: | |
00ada50d | 6329 | case i40e_aqc_opc_oem_post_update: |
6e93d0c9 SN |
6330 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, |
6331 | "ARQ NVM operation 0x%04x completed\n", | |
6332 | opcode); | |
91a0f930 | 6333 | break; |
41c445ff JB |
6334 | default: |
6335 | dev_info(&pf->pdev->dev, | |
56e5ca68 | 6336 | "ARQ: Unknown event 0x%04x ignored\n", |
0467bc91 | 6337 | opcode); |
41c445ff JB |
6338 | break; |
6339 | } | |
6340 | } while (pending && (i++ < pf->adminq_work_limit)); | |
6341 | ||
6342 | clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state); | |
6343 | /* re-enable Admin queue interrupt cause */ | |
6344 | val = rd32(hw, I40E_PFINT_ICR0_ENA); | |
6345 | val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
6346 | wr32(hw, I40E_PFINT_ICR0_ENA, val); | |
6347 | i40e_flush(hw); | |
6348 | ||
6349 | kfree(event.msg_buf); | |
6350 | } | |
6351 | ||
4eb3f768 SN |
6352 | /** |
6353 | * i40e_verify_eeprom - make sure eeprom is good to use | |
6354 | * @pf: board private structure | |
6355 | **/ | |
6356 | static void i40e_verify_eeprom(struct i40e_pf *pf) | |
6357 | { | |
6358 | int err; | |
6359 | ||
6360 | err = i40e_diag_eeprom_test(&pf->hw); | |
6361 | if (err) { | |
6362 | /* retry in case of garbage read */ | |
6363 | err = i40e_diag_eeprom_test(&pf->hw); | |
6364 | if (err) { | |
6365 | dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n", | |
6366 | err); | |
6367 | set_bit(__I40E_BAD_EEPROM, &pf->state); | |
6368 | } | |
6369 | } | |
6370 | ||
6371 | if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) { | |
6372 | dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n"); | |
6373 | clear_bit(__I40E_BAD_EEPROM, &pf->state); | |
6374 | } | |
6375 | } | |
6376 | ||
386a0afa AA |
6377 | /** |
6378 | * i40e_enable_pf_switch_lb | |
b40c82e6 | 6379 | * @pf: pointer to the PF structure |
386a0afa AA |
6380 | * |
6381 | * enable switch loop back or die - no point in a return value | |
6382 | **/ | |
6383 | static void i40e_enable_pf_switch_lb(struct i40e_pf *pf) | |
6384 | { | |
6385 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
6386 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 6387 | int ret; |
386a0afa AA |
6388 | |
6389 | ctxt.seid = pf->main_vsi_seid; | |
6390 | ctxt.pf_num = pf->hw.pf_id; | |
6391 | ctxt.vf_num = 0; | |
f1c7e72e SN |
6392 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
6393 | if (ret) { | |
386a0afa | 6394 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6395 | "couldn't get PF vsi config, err %s aq_err %s\n", |
6396 | i40e_stat_str(&pf->hw, ret), | |
6397 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6398 | return; |
6399 | } | |
6400 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
6401 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
6402 | ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
6403 | ||
f1c7e72e SN |
6404 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
6405 | if (ret) { | |
386a0afa | 6406 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6407 | "update vsi switch failed, err %s aq_err %s\n", |
6408 | i40e_stat_str(&pf->hw, ret), | |
6409 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6410 | } |
6411 | } | |
6412 | ||
6413 | /** | |
6414 | * i40e_disable_pf_switch_lb | |
b40c82e6 | 6415 | * @pf: pointer to the PF structure |
386a0afa AA |
6416 | * |
6417 | * disable switch loop back or die - no point in a return value | |
6418 | **/ | |
6419 | static void i40e_disable_pf_switch_lb(struct i40e_pf *pf) | |
6420 | { | |
6421 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
6422 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 6423 | int ret; |
386a0afa AA |
6424 | |
6425 | ctxt.seid = pf->main_vsi_seid; | |
6426 | ctxt.pf_num = pf->hw.pf_id; | |
6427 | ctxt.vf_num = 0; | |
f1c7e72e SN |
6428 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
6429 | if (ret) { | |
386a0afa | 6430 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6431 | "couldn't get PF vsi config, err %s aq_err %s\n", |
6432 | i40e_stat_str(&pf->hw, ret), | |
6433 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6434 | return; |
6435 | } | |
6436 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
6437 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
6438 | ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
6439 | ||
f1c7e72e SN |
6440 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
6441 | if (ret) { | |
386a0afa | 6442 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6443 | "update vsi switch failed, err %s aq_err %s\n", |
6444 | i40e_stat_str(&pf->hw, ret), | |
6445 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6446 | } |
6447 | } | |
6448 | ||
51616018 NP |
6449 | /** |
6450 | * i40e_config_bridge_mode - Configure the HW bridge mode | |
6451 | * @veb: pointer to the bridge instance | |
6452 | * | |
6453 | * Configure the loop back mode for the LAN VSI that is downlink to the | |
6454 | * specified HW bridge instance. It is expected this function is called | |
6455 | * when a new HW bridge is instantiated. | |
6456 | **/ | |
6457 | static void i40e_config_bridge_mode(struct i40e_veb *veb) | |
6458 | { | |
6459 | struct i40e_pf *pf = veb->pf; | |
6460 | ||
6dec1017 SN |
6461 | if (pf->hw.debug_mask & I40E_DEBUG_LAN) |
6462 | dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n", | |
6463 | veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
51616018 NP |
6464 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) |
6465 | i40e_disable_pf_switch_lb(pf); | |
6466 | else | |
6467 | i40e_enable_pf_switch_lb(pf); | |
6468 | } | |
6469 | ||
41c445ff JB |
6470 | /** |
6471 | * i40e_reconstitute_veb - rebuild the VEB and anything connected to it | |
6472 | * @veb: pointer to the VEB instance | |
6473 | * | |
6474 | * This is a recursive function that first builds the attached VSIs then | |
6475 | * recurses in to build the next layer of VEB. We track the connections | |
6476 | * through our own index numbers because the seid's from the HW could | |
6477 | * change across the reset. | |
6478 | **/ | |
6479 | static int i40e_reconstitute_veb(struct i40e_veb *veb) | |
6480 | { | |
6481 | struct i40e_vsi *ctl_vsi = NULL; | |
6482 | struct i40e_pf *pf = veb->pf; | |
6483 | int v, veb_idx; | |
6484 | int ret; | |
6485 | ||
6486 | /* build VSI that owns this VEB, temporarily attached to base VEB */ | |
505682cd | 6487 | for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) { |
41c445ff JB |
6488 | if (pf->vsi[v] && |
6489 | pf->vsi[v]->veb_idx == veb->idx && | |
6490 | pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
6491 | ctl_vsi = pf->vsi[v]; | |
6492 | break; | |
6493 | } | |
6494 | } | |
6495 | if (!ctl_vsi) { | |
6496 | dev_info(&pf->pdev->dev, | |
6497 | "missing owner VSI for veb_idx %d\n", veb->idx); | |
6498 | ret = -ENOENT; | |
6499 | goto end_reconstitute; | |
6500 | } | |
6501 | if (ctl_vsi != pf->vsi[pf->lan_vsi]) | |
6502 | ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
6503 | ret = i40e_add_vsi(ctl_vsi); | |
6504 | if (ret) { | |
6505 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6506 | "rebuild of veb_idx %d owner VSI failed: %d\n", |
6507 | veb->idx, ret); | |
41c445ff JB |
6508 | goto end_reconstitute; |
6509 | } | |
6510 | i40e_vsi_reset_stats(ctl_vsi); | |
6511 | ||
6512 | /* create the VEB in the switch and move the VSI onto the VEB */ | |
6513 | ret = i40e_add_veb(veb, ctl_vsi); | |
6514 | if (ret) | |
6515 | goto end_reconstitute; | |
6516 | ||
fc60861e ASJ |
6517 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
6518 | veb->bridge_mode = BRIDGE_MODE_VEB; | |
6519 | else | |
6520 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
51616018 | 6521 | i40e_config_bridge_mode(veb); |
b64ba084 | 6522 | |
41c445ff | 6523 | /* create the remaining VSIs attached to this VEB */ |
505682cd | 6524 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
6525 | if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi) |
6526 | continue; | |
6527 | ||
6528 | if (pf->vsi[v]->veb_idx == veb->idx) { | |
6529 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 6530 | |
41c445ff JB |
6531 | vsi->uplink_seid = veb->seid; |
6532 | ret = i40e_add_vsi(vsi); | |
6533 | if (ret) { | |
6534 | dev_info(&pf->pdev->dev, | |
6535 | "rebuild of vsi_idx %d failed: %d\n", | |
6536 | v, ret); | |
6537 | goto end_reconstitute; | |
6538 | } | |
6539 | i40e_vsi_reset_stats(vsi); | |
6540 | } | |
6541 | } | |
6542 | ||
6543 | /* create any VEBs attached to this VEB - RECURSION */ | |
6544 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
6545 | if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) { | |
6546 | pf->veb[veb_idx]->uplink_seid = veb->seid; | |
6547 | ret = i40e_reconstitute_veb(pf->veb[veb_idx]); | |
6548 | if (ret) | |
6549 | break; | |
6550 | } | |
6551 | } | |
6552 | ||
6553 | end_reconstitute: | |
6554 | return ret; | |
6555 | } | |
6556 | ||
6557 | /** | |
6558 | * i40e_get_capabilities - get info about the HW | |
6559 | * @pf: the PF struct | |
6560 | **/ | |
6561 | static int i40e_get_capabilities(struct i40e_pf *pf) | |
6562 | { | |
6563 | struct i40e_aqc_list_capabilities_element_resp *cap_buf; | |
6564 | u16 data_size; | |
6565 | int buf_len; | |
6566 | int err; | |
6567 | ||
6568 | buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); | |
6569 | do { | |
6570 | cap_buf = kzalloc(buf_len, GFP_KERNEL); | |
6571 | if (!cap_buf) | |
6572 | return -ENOMEM; | |
6573 | ||
6574 | /* this loads the data into the hw struct for us */ | |
6575 | err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len, | |
6576 | &data_size, | |
6577 | i40e_aqc_opc_list_func_capabilities, | |
6578 | NULL); | |
6579 | /* data loaded, buffer no longer needed */ | |
6580 | kfree(cap_buf); | |
6581 | ||
6582 | if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) { | |
6583 | /* retry with a larger buffer */ | |
6584 | buf_len = data_size; | |
6585 | } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { | |
6586 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6587 | "capability discovery failed, err %s aq_err %s\n", |
6588 | i40e_stat_str(&pf->hw, err), | |
6589 | i40e_aq_str(&pf->hw, | |
6590 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
6591 | return -ENODEV; |
6592 | } | |
6593 | } while (err); | |
6594 | ||
6595 | if (pf->hw.debug_mask & I40E_DEBUG_USER) | |
6596 | dev_info(&pf->pdev->dev, | |
6597 | "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n", | |
6598 | pf->hw.pf_id, pf->hw.func_caps.num_vfs, | |
6599 | pf->hw.func_caps.num_msix_vectors, | |
6600 | pf->hw.func_caps.num_msix_vectors_vf, | |
6601 | pf->hw.func_caps.fd_filters_guaranteed, | |
6602 | pf->hw.func_caps.fd_filters_best_effort, | |
6603 | pf->hw.func_caps.num_tx_qp, | |
6604 | pf->hw.func_caps.num_vsis); | |
6605 | ||
7134f9ce JB |
6606 | #define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \ |
6607 | + pf->hw.func_caps.num_vfs) | |
6608 | if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) { | |
6609 | dev_info(&pf->pdev->dev, | |
6610 | "got num_vsis %d, setting num_vsis to %d\n", | |
6611 | pf->hw.func_caps.num_vsis, DEF_NUM_VSI); | |
6612 | pf->hw.func_caps.num_vsis = DEF_NUM_VSI; | |
6613 | } | |
6614 | ||
41c445ff JB |
6615 | return 0; |
6616 | } | |
6617 | ||
cbf61325 ASJ |
6618 | static int i40e_vsi_clear(struct i40e_vsi *vsi); |
6619 | ||
41c445ff | 6620 | /** |
cbf61325 | 6621 | * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband |
41c445ff JB |
6622 | * @pf: board private structure |
6623 | **/ | |
cbf61325 | 6624 | static void i40e_fdir_sb_setup(struct i40e_pf *pf) |
41c445ff JB |
6625 | { |
6626 | struct i40e_vsi *vsi; | |
8a9eb7d3 | 6627 | int i; |
41c445ff | 6628 | |
407e063c JB |
6629 | /* quick workaround for an NVM issue that leaves a critical register |
6630 | * uninitialized | |
6631 | */ | |
6632 | if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) { | |
6633 | static const u32 hkey[] = { | |
6634 | 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36, | |
6635 | 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb, | |
6636 | 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21, | |
6637 | 0x95b3a76d}; | |
6638 | ||
6639 | for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++) | |
6640 | wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]); | |
6641 | } | |
6642 | ||
cbf61325 | 6643 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
41c445ff JB |
6644 | return; |
6645 | ||
cbf61325 | 6646 | /* find existing VSI and see if it needs configuring */ |
41c445ff | 6647 | vsi = NULL; |
505682cd | 6648 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
cbf61325 | 6649 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { |
41c445ff | 6650 | vsi = pf->vsi[i]; |
cbf61325 ASJ |
6651 | break; |
6652 | } | |
6653 | } | |
6654 | ||
6655 | /* create a new VSI if none exists */ | |
41c445ff | 6656 | if (!vsi) { |
cbf61325 ASJ |
6657 | vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, |
6658 | pf->vsi[pf->lan_vsi]->seid, 0); | |
41c445ff JB |
6659 | if (!vsi) { |
6660 | dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n"); | |
8a9eb7d3 SN |
6661 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; |
6662 | return; | |
41c445ff | 6663 | } |
cbf61325 | 6664 | } |
41c445ff | 6665 | |
8a9eb7d3 | 6666 | i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring); |
41c445ff JB |
6667 | } |
6668 | ||
6669 | /** | |
6670 | * i40e_fdir_teardown - release the Flow Director resources | |
6671 | * @pf: board private structure | |
6672 | **/ | |
6673 | static void i40e_fdir_teardown(struct i40e_pf *pf) | |
6674 | { | |
6675 | int i; | |
6676 | ||
17a73f6b | 6677 | i40e_fdir_filter_exit(pf); |
505682cd | 6678 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
6679 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { |
6680 | i40e_vsi_release(pf->vsi[i]); | |
6681 | break; | |
6682 | } | |
6683 | } | |
6684 | } | |
6685 | ||
6686 | /** | |
f650a38b | 6687 | * i40e_prep_for_reset - prep for the core to reset |
41c445ff JB |
6688 | * @pf: board private structure |
6689 | * | |
b40c82e6 | 6690 | * Close up the VFs and other things in prep for PF Reset. |
f650a38b | 6691 | **/ |
23cfbe07 | 6692 | static void i40e_prep_for_reset(struct i40e_pf *pf) |
41c445ff | 6693 | { |
41c445ff | 6694 | struct i40e_hw *hw = &pf->hw; |
60442dea | 6695 | i40e_status ret = 0; |
41c445ff JB |
6696 | u32 v; |
6697 | ||
6698 | clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state); | |
6699 | if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) | |
23cfbe07 | 6700 | return; |
d3ce5734 MW |
6701 | if (i40e_check_asq_alive(&pf->hw)) |
6702 | i40e_vc_notify_reset(pf); | |
41c445ff | 6703 | |
69bfb110 | 6704 | dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n"); |
41c445ff | 6705 | |
41c445ff JB |
6706 | /* quiesce the VSIs and their queues that are not already DOWN */ |
6707 | i40e_pf_quiesce_all_vsi(pf); | |
6708 | ||
505682cd | 6709 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
6710 | if (pf->vsi[v]) |
6711 | pf->vsi[v]->seid = 0; | |
6712 | } | |
6713 | ||
6714 | i40e_shutdown_adminq(&pf->hw); | |
6715 | ||
f650a38b | 6716 | /* call shutdown HMC */ |
60442dea SN |
6717 | if (hw->hmc.hmc_obj) { |
6718 | ret = i40e_shutdown_lan_hmc(hw); | |
23cfbe07 | 6719 | if (ret) |
60442dea SN |
6720 | dev_warn(&pf->pdev->dev, |
6721 | "shutdown_lan_hmc failed: %d\n", ret); | |
f650a38b | 6722 | } |
f650a38b ASJ |
6723 | } |
6724 | ||
44033fac JB |
6725 | /** |
6726 | * i40e_send_version - update firmware with driver version | |
6727 | * @pf: PF struct | |
6728 | */ | |
6729 | static void i40e_send_version(struct i40e_pf *pf) | |
6730 | { | |
6731 | struct i40e_driver_version dv; | |
6732 | ||
6733 | dv.major_version = DRV_VERSION_MAJOR; | |
6734 | dv.minor_version = DRV_VERSION_MINOR; | |
6735 | dv.build_version = DRV_VERSION_BUILD; | |
6736 | dv.subbuild_version = 0; | |
35a7d804 | 6737 | strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string)); |
44033fac JB |
6738 | i40e_aq_send_driver_version(&pf->hw, &dv, NULL); |
6739 | } | |
6740 | ||
f650a38b | 6741 | /** |
4dda12e6 | 6742 | * i40e_reset_and_rebuild - reset and rebuild using a saved config |
f650a38b | 6743 | * @pf: board private structure |
bc7d338f | 6744 | * @reinit: if the Main VSI needs to re-initialized. |
f650a38b | 6745 | **/ |
bc7d338f | 6746 | static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit) |
f650a38b | 6747 | { |
f650a38b | 6748 | struct i40e_hw *hw = &pf->hw; |
cafa2ee6 | 6749 | u8 set_fc_aq_fail = 0; |
f650a38b | 6750 | i40e_status ret; |
4f2f017c | 6751 | u32 val; |
f650a38b ASJ |
6752 | u32 v; |
6753 | ||
41c445ff JB |
6754 | /* Now we wait for GRST to settle out. |
6755 | * We don't have to delete the VEBs or VSIs from the hw switch | |
6756 | * because the reset will make them disappear. | |
6757 | */ | |
6758 | ret = i40e_pf_reset(hw); | |
b5565400 | 6759 | if (ret) { |
41c445ff | 6760 | dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret); |
a316f651 ASJ |
6761 | set_bit(__I40E_RESET_FAILED, &pf->state); |
6762 | goto clear_recovery; | |
b5565400 | 6763 | } |
41c445ff JB |
6764 | pf->pfr_count++; |
6765 | ||
6766 | if (test_bit(__I40E_DOWN, &pf->state)) | |
a316f651 | 6767 | goto clear_recovery; |
69bfb110 | 6768 | dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n"); |
41c445ff JB |
6769 | |
6770 | /* rebuild the basics for the AdminQ, HMC, and initial HW switch */ | |
6771 | ret = i40e_init_adminq(&pf->hw); | |
6772 | if (ret) { | |
f1c7e72e SN |
6773 | dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n", |
6774 | i40e_stat_str(&pf->hw, ret), | |
6775 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
a316f651 | 6776 | goto clear_recovery; |
41c445ff JB |
6777 | } |
6778 | ||
4eb3f768 | 6779 | /* re-verify the eeprom if we just had an EMP reset */ |
9df42d1a | 6780 | if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state)) |
4eb3f768 | 6781 | i40e_verify_eeprom(pf); |
4eb3f768 | 6782 | |
e78ac4bf | 6783 | i40e_clear_pxe_mode(hw); |
41c445ff | 6784 | ret = i40e_get_capabilities(pf); |
f1c7e72e | 6785 | if (ret) |
41c445ff | 6786 | goto end_core_reset; |
41c445ff | 6787 | |
41c445ff JB |
6788 | ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, |
6789 | hw->func_caps.num_rx_qp, | |
6790 | pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num); | |
6791 | if (ret) { | |
6792 | dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret); | |
6793 | goto end_core_reset; | |
6794 | } | |
6795 | ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
6796 | if (ret) { | |
6797 | dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret); | |
6798 | goto end_core_reset; | |
6799 | } | |
6800 | ||
4e3b35b0 NP |
6801 | #ifdef CONFIG_I40E_DCB |
6802 | ret = i40e_init_pf_dcb(pf); | |
6803 | if (ret) { | |
aebfc816 SN |
6804 | dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret); |
6805 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; | |
6806 | /* Continue without DCB enabled */ | |
4e3b35b0 NP |
6807 | } |
6808 | #endif /* CONFIG_I40E_DCB */ | |
38e00438 | 6809 | #ifdef I40E_FCOE |
21364bcf | 6810 | i40e_init_pf_fcoe(pf); |
4e3b35b0 | 6811 | |
38e00438 | 6812 | #endif |
41c445ff | 6813 | /* do basic switch setup */ |
bc7d338f | 6814 | ret = i40e_setup_pf_switch(pf, reinit); |
41c445ff JB |
6815 | if (ret) |
6816 | goto end_core_reset; | |
6817 | ||
2f0aff41 SN |
6818 | /* The driver only wants link up/down and module qualification |
6819 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
6820 | */ |
6821 | ret = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 6822 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 6823 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 6824 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 6825 | if (ret) |
f1c7e72e SN |
6826 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
6827 | i40e_stat_str(&pf->hw, ret), | |
6828 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 6829 | |
cafa2ee6 ASJ |
6830 | /* make sure our flow control settings are restored */ |
6831 | ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true); | |
6832 | if (ret) | |
8279e495 NP |
6833 | dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n", |
6834 | i40e_stat_str(&pf->hw, ret), | |
6835 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 6836 | |
41c445ff JB |
6837 | /* Rebuild the VSIs and VEBs that existed before reset. |
6838 | * They are still in our local switch element arrays, so only | |
6839 | * need to rebuild the switch model in the HW. | |
6840 | * | |
6841 | * If there were VEBs but the reconstitution failed, we'll try | |
6842 | * try to recover minimal use by getting the basic PF VSI working. | |
6843 | */ | |
6844 | if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) { | |
69bfb110 | 6845 | dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n"); |
41c445ff JB |
6846 | /* find the one VEB connected to the MAC, and find orphans */ |
6847 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
6848 | if (!pf->veb[v]) | |
6849 | continue; | |
6850 | ||
6851 | if (pf->veb[v]->uplink_seid == pf->mac_seid || | |
6852 | pf->veb[v]->uplink_seid == 0) { | |
6853 | ret = i40e_reconstitute_veb(pf->veb[v]); | |
6854 | ||
6855 | if (!ret) | |
6856 | continue; | |
6857 | ||
6858 | /* If Main VEB failed, we're in deep doodoo, | |
6859 | * so give up rebuilding the switch and set up | |
6860 | * for minimal rebuild of PF VSI. | |
6861 | * If orphan failed, we'll report the error | |
6862 | * but try to keep going. | |
6863 | */ | |
6864 | if (pf->veb[v]->uplink_seid == pf->mac_seid) { | |
6865 | dev_info(&pf->pdev->dev, | |
6866 | "rebuild of switch failed: %d, will try to set up simple PF connection\n", | |
6867 | ret); | |
6868 | pf->vsi[pf->lan_vsi]->uplink_seid | |
6869 | = pf->mac_seid; | |
6870 | break; | |
6871 | } else if (pf->veb[v]->uplink_seid == 0) { | |
6872 | dev_info(&pf->pdev->dev, | |
6873 | "rebuild of orphan VEB failed: %d\n", | |
6874 | ret); | |
6875 | } | |
6876 | } | |
6877 | } | |
6878 | } | |
6879 | ||
6880 | if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) { | |
cde4cbc7 | 6881 | dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n"); |
41c445ff JB |
6882 | /* no VEB, so rebuild only the Main VSI */ |
6883 | ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]); | |
6884 | if (ret) { | |
6885 | dev_info(&pf->pdev->dev, | |
6886 | "rebuild of Main VSI failed: %d\n", ret); | |
6887 | goto end_core_reset; | |
6888 | } | |
6889 | } | |
6890 | ||
4f2f017c ASJ |
6891 | /* Reconfigure hardware for allowing smaller MSS in the case |
6892 | * of TSO, so that we avoid the MDD being fired and causing | |
6893 | * a reset in the case of small MSS+TSO. | |
6894 | */ | |
6895 | #define I40E_REG_MSS 0x000E64DC | |
6896 | #define I40E_REG_MSS_MIN_MASK 0x3FF0000 | |
6897 | #define I40E_64BYTE_MSS 0x400000 | |
6898 | val = rd32(hw, I40E_REG_MSS); | |
6899 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
6900 | val &= ~I40E_REG_MSS_MIN_MASK; | |
6901 | val |= I40E_64BYTE_MSS; | |
6902 | wr32(hw, I40E_REG_MSS, val); | |
6903 | } | |
6904 | ||
8eed76fa | 6905 | if (pf->flags & I40E_FLAG_RESTART_AUTONEG) { |
025b4a54 ASJ |
6906 | msleep(75); |
6907 | ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
6908 | if (ret) | |
f1c7e72e SN |
6909 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
6910 | i40e_stat_str(&pf->hw, ret), | |
6911 | i40e_aq_str(&pf->hw, | |
6912 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 6913 | } |
41c445ff JB |
6914 | /* reinit the misc interrupt */ |
6915 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
6916 | ret = i40e_setup_misc_vector(pf); | |
6917 | ||
e7358f54 ASJ |
6918 | /* Add a filter to drop all Flow control frames from any VSI from being |
6919 | * transmitted. By doing so we stop a malicious VF from sending out | |
6920 | * PAUSE or PFC frames and potentially controlling traffic for other | |
6921 | * PF/VF VSIs. | |
6922 | * The FW can still send Flow control frames if enabled. | |
6923 | */ | |
6924 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
6925 | pf->main_vsi_seid); | |
6926 | ||
41c445ff JB |
6927 | /* restart the VSIs that were rebuilt and running before the reset */ |
6928 | i40e_pf_unquiesce_all_vsi(pf); | |
6929 | ||
69f64b2b MW |
6930 | if (pf->num_alloc_vfs) { |
6931 | for (v = 0; v < pf->num_alloc_vfs; v++) | |
6932 | i40e_reset_vf(&pf->vf[v], true); | |
6933 | } | |
6934 | ||
41c445ff | 6935 | /* tell the firmware that we're starting */ |
44033fac | 6936 | i40e_send_version(pf); |
41c445ff JB |
6937 | |
6938 | end_core_reset: | |
a316f651 ASJ |
6939 | clear_bit(__I40E_RESET_FAILED, &pf->state); |
6940 | clear_recovery: | |
41c445ff JB |
6941 | clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state); |
6942 | } | |
6943 | ||
f650a38b | 6944 | /** |
b40c82e6 | 6945 | * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild |
f650a38b ASJ |
6946 | * @pf: board private structure |
6947 | * | |
6948 | * Close up the VFs and other things in prep for a Core Reset, | |
6949 | * then get ready to rebuild the world. | |
6950 | **/ | |
6951 | static void i40e_handle_reset_warning(struct i40e_pf *pf) | |
6952 | { | |
23cfbe07 SN |
6953 | i40e_prep_for_reset(pf); |
6954 | i40e_reset_and_rebuild(pf, false); | |
f650a38b ASJ |
6955 | } |
6956 | ||
41c445ff JB |
6957 | /** |
6958 | * i40e_handle_mdd_event | |
b40c82e6 | 6959 | * @pf: pointer to the PF structure |
41c445ff JB |
6960 | * |
6961 | * Called from the MDD irq handler to identify possibly malicious vfs | |
6962 | **/ | |
6963 | static void i40e_handle_mdd_event(struct i40e_pf *pf) | |
6964 | { | |
6965 | struct i40e_hw *hw = &pf->hw; | |
6966 | bool mdd_detected = false; | |
df430b12 | 6967 | bool pf_mdd_detected = false; |
41c445ff JB |
6968 | struct i40e_vf *vf; |
6969 | u32 reg; | |
6970 | int i; | |
6971 | ||
6972 | if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state)) | |
6973 | return; | |
6974 | ||
6975 | /* find what triggered the MDD event */ | |
6976 | reg = rd32(hw, I40E_GL_MDET_TX); | |
6977 | if (reg & I40E_GL_MDET_TX_VALID_MASK) { | |
4c33f83a ASJ |
6978 | u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> |
6979 | I40E_GL_MDET_TX_PF_NUM_SHIFT; | |
2089ad03 | 6980 | u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> |
4c33f83a | 6981 | I40E_GL_MDET_TX_VF_NUM_SHIFT; |
013f6579 | 6982 | u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> |
4c33f83a | 6983 | I40E_GL_MDET_TX_EVENT_SHIFT; |
2089ad03 MW |
6984 | u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> |
6985 | I40E_GL_MDET_TX_QUEUE_SHIFT) - | |
6986 | pf->hw.func_caps.base_queue; | |
faf32978 | 6987 | if (netif_msg_tx_err(pf)) |
b40c82e6 | 6988 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n", |
faf32978 | 6989 | event, queue, pf_num, vf_num); |
41c445ff JB |
6990 | wr32(hw, I40E_GL_MDET_TX, 0xffffffff); |
6991 | mdd_detected = true; | |
6992 | } | |
6993 | reg = rd32(hw, I40E_GL_MDET_RX); | |
6994 | if (reg & I40E_GL_MDET_RX_VALID_MASK) { | |
4c33f83a ASJ |
6995 | u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> |
6996 | I40E_GL_MDET_RX_FUNCTION_SHIFT; | |
013f6579 | 6997 | u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> |
4c33f83a | 6998 | I40E_GL_MDET_RX_EVENT_SHIFT; |
2089ad03 MW |
6999 | u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> |
7000 | I40E_GL_MDET_RX_QUEUE_SHIFT) - | |
7001 | pf->hw.func_caps.base_queue; | |
faf32978 JB |
7002 | if (netif_msg_rx_err(pf)) |
7003 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", | |
7004 | event, queue, func); | |
41c445ff JB |
7005 | wr32(hw, I40E_GL_MDET_RX, 0xffffffff); |
7006 | mdd_detected = true; | |
7007 | } | |
7008 | ||
df430b12 NP |
7009 | if (mdd_detected) { |
7010 | reg = rd32(hw, I40E_PF_MDET_TX); | |
7011 | if (reg & I40E_PF_MDET_TX_VALID_MASK) { | |
7012 | wr32(hw, I40E_PF_MDET_TX, 0xFFFF); | |
faf32978 | 7013 | dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n"); |
df430b12 NP |
7014 | pf_mdd_detected = true; |
7015 | } | |
7016 | reg = rd32(hw, I40E_PF_MDET_RX); | |
7017 | if (reg & I40E_PF_MDET_RX_VALID_MASK) { | |
7018 | wr32(hw, I40E_PF_MDET_RX, 0xFFFF); | |
faf32978 | 7019 | dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n"); |
df430b12 NP |
7020 | pf_mdd_detected = true; |
7021 | } | |
7022 | /* Queue belongs to the PF, initiate a reset */ | |
7023 | if (pf_mdd_detected) { | |
7024 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
7025 | i40e_service_event_schedule(pf); | |
7026 | } | |
7027 | } | |
7028 | ||
41c445ff JB |
7029 | /* see if one of the VFs needs its hand slapped */ |
7030 | for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) { | |
7031 | vf = &(pf->vf[i]); | |
7032 | reg = rd32(hw, I40E_VP_MDET_TX(i)); | |
7033 | if (reg & I40E_VP_MDET_TX_VALID_MASK) { | |
7034 | wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF); | |
7035 | vf->num_mdd_events++; | |
faf32978 JB |
7036 | dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n", |
7037 | i); | |
41c445ff JB |
7038 | } |
7039 | ||
7040 | reg = rd32(hw, I40E_VP_MDET_RX(i)); | |
7041 | if (reg & I40E_VP_MDET_RX_VALID_MASK) { | |
7042 | wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF); | |
7043 | vf->num_mdd_events++; | |
faf32978 JB |
7044 | dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n", |
7045 | i); | |
41c445ff JB |
7046 | } |
7047 | ||
7048 | if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) { | |
7049 | dev_info(&pf->pdev->dev, | |
7050 | "Too many MDD events on VF %d, disabled\n", i); | |
7051 | dev_info(&pf->pdev->dev, | |
7052 | "Use PF Control I/F to re-enable the VF\n"); | |
7053 | set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states); | |
7054 | } | |
7055 | } | |
7056 | ||
7057 | /* re-enable mdd interrupt cause */ | |
7058 | clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state); | |
7059 | reg = rd32(hw, I40E_PFINT_ICR0_ENA); | |
7060 | reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
7061 | wr32(hw, I40E_PFINT_ICR0_ENA, reg); | |
7062 | i40e_flush(hw); | |
7063 | } | |
7064 | ||
a1c9a9d9 | 7065 | /** |
6a899024 | 7066 | * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW |
a1c9a9d9 JK |
7067 | * @pf: board private structure |
7068 | **/ | |
6a899024 | 7069 | static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf) |
a1c9a9d9 | 7070 | { |
a1c9a9d9 JK |
7071 | struct i40e_hw *hw = &pf->hw; |
7072 | i40e_status ret; | |
a1c9a9d9 JK |
7073 | __be16 port; |
7074 | int i; | |
7075 | ||
6a899024 | 7076 | if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC)) |
a1c9a9d9 JK |
7077 | return; |
7078 | ||
6a899024 | 7079 | pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC; |
a1c9a9d9 JK |
7080 | |
7081 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
6a899024 SA |
7082 | if (pf->pending_udp_bitmap & BIT_ULL(i)) { |
7083 | pf->pending_udp_bitmap &= ~BIT_ULL(i); | |
7084 | port = pf->udp_ports[i].index; | |
c22c06c8 SN |
7085 | if (port) |
7086 | ret = i40e_aq_add_udp_tunnel(hw, ntohs(port), | |
6a899024 | 7087 | pf->udp_ports[i].type, |
c22c06c8 SN |
7088 | NULL, NULL); |
7089 | else | |
7090 | ret = i40e_aq_del_udp_tunnel(hw, i, NULL); | |
a1c9a9d9 JK |
7091 | |
7092 | if (ret) { | |
730a8f87 CW |
7093 | dev_dbg(&pf->pdev->dev, |
7094 | "%s %s port %d, index %d failed, err %s aq_err %s\n", | |
7095 | pf->udp_ports[i].type ? "vxlan" : "geneve", | |
7096 | port ? "add" : "delete", | |
7097 | ntohs(port), i, | |
7098 | i40e_stat_str(&pf->hw, ret), | |
7099 | i40e_aq_str(&pf->hw, | |
f1c7e72e | 7100 | pf->hw.aq.asq_last_status)); |
6a899024 | 7101 | pf->udp_ports[i].index = 0; |
a1c9a9d9 JK |
7102 | } |
7103 | } | |
7104 | } | |
7105 | } | |
7106 | ||
41c445ff JB |
7107 | /** |
7108 | * i40e_service_task - Run the driver's async subtasks | |
7109 | * @work: pointer to work_struct containing our data | |
7110 | **/ | |
7111 | static void i40e_service_task(struct work_struct *work) | |
7112 | { | |
7113 | struct i40e_pf *pf = container_of(work, | |
7114 | struct i40e_pf, | |
7115 | service_task); | |
7116 | unsigned long start_time = jiffies; | |
7117 | ||
e57a2fea SN |
7118 | /* don't bother with service tasks if a reset is in progress */ |
7119 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) { | |
7120 | i40e_service_event_complete(pf); | |
7121 | return; | |
7122 | } | |
7123 | ||
b03a8c1f | 7124 | i40e_detect_recover_hung(pf); |
2818ccd9 | 7125 | i40e_sync_filters_subtask(pf); |
41c445ff JB |
7126 | i40e_reset_subtask(pf); |
7127 | i40e_handle_mdd_event(pf); | |
7128 | i40e_vc_process_vflr_event(pf); | |
7129 | i40e_watchdog_subtask(pf); | |
7130 | i40e_fdir_reinit_subtask(pf); | |
e3219ce6 | 7131 | i40e_client_subtask(pf); |
41c445ff | 7132 | i40e_sync_filters_subtask(pf); |
6a899024 | 7133 | i40e_sync_udp_filters_subtask(pf); |
41c445ff JB |
7134 | i40e_clean_adminq_subtask(pf); |
7135 | ||
7136 | i40e_service_event_complete(pf); | |
7137 | ||
7138 | /* If the tasks have taken longer than one timer cycle or there | |
7139 | * is more work to be done, reschedule the service task now | |
7140 | * rather than wait for the timer to tick again. | |
7141 | */ | |
7142 | if (time_after(jiffies, (start_time + pf->service_timer_period)) || | |
7143 | test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) || | |
7144 | test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) || | |
7145 | test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state)) | |
7146 | i40e_service_event_schedule(pf); | |
7147 | } | |
7148 | ||
7149 | /** | |
7150 | * i40e_service_timer - timer callback | |
7151 | * @data: pointer to PF struct | |
7152 | **/ | |
7153 | static void i40e_service_timer(unsigned long data) | |
7154 | { | |
7155 | struct i40e_pf *pf = (struct i40e_pf *)data; | |
7156 | ||
7157 | mod_timer(&pf->service_timer, | |
7158 | round_jiffies(jiffies + pf->service_timer_period)); | |
7159 | i40e_service_event_schedule(pf); | |
7160 | } | |
7161 | ||
7162 | /** | |
7163 | * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI | |
7164 | * @vsi: the VSI being configured | |
7165 | **/ | |
7166 | static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi) | |
7167 | { | |
7168 | struct i40e_pf *pf = vsi->back; | |
7169 | ||
7170 | switch (vsi->type) { | |
7171 | case I40E_VSI_MAIN: | |
7172 | vsi->alloc_queue_pairs = pf->num_lan_qps; | |
7173 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7174 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7175 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
7176 | vsi->num_q_vectors = pf->num_lan_msix; | |
7177 | else | |
7178 | vsi->num_q_vectors = 1; | |
7179 | ||
7180 | break; | |
7181 | ||
7182 | case I40E_VSI_FDIR: | |
7183 | vsi->alloc_queue_pairs = 1; | |
7184 | vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT, | |
7185 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
a70e407f | 7186 | vsi->num_q_vectors = pf->num_fdsb_msix; |
41c445ff JB |
7187 | break; |
7188 | ||
7189 | case I40E_VSI_VMDQ2: | |
7190 | vsi->alloc_queue_pairs = pf->num_vmdq_qps; | |
7191 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7192 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7193 | vsi->num_q_vectors = pf->num_vmdq_msix; | |
7194 | break; | |
7195 | ||
7196 | case I40E_VSI_SRIOV: | |
7197 | vsi->alloc_queue_pairs = pf->num_vf_qps; | |
7198 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7199 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7200 | break; | |
7201 | ||
38e00438 VD |
7202 | #ifdef I40E_FCOE |
7203 | case I40E_VSI_FCOE: | |
7204 | vsi->alloc_queue_pairs = pf->num_fcoe_qps; | |
7205 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7206 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7207 | vsi->num_q_vectors = pf->num_fcoe_msix; | |
7208 | break; | |
7209 | ||
7210 | #endif /* I40E_FCOE */ | |
41c445ff JB |
7211 | default: |
7212 | WARN_ON(1); | |
7213 | return -ENODATA; | |
7214 | } | |
7215 | ||
7216 | return 0; | |
7217 | } | |
7218 | ||
f650a38b ASJ |
7219 | /** |
7220 | * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi | |
7221 | * @type: VSI pointer | |
bc7d338f | 7222 | * @alloc_qvectors: a bool to specify if q_vectors need to be allocated. |
f650a38b ASJ |
7223 | * |
7224 | * On error: returns error code (negative) | |
7225 | * On success: returns 0 | |
7226 | **/ | |
bc7d338f | 7227 | static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors) |
f650a38b ASJ |
7228 | { |
7229 | int size; | |
7230 | int ret = 0; | |
7231 | ||
ac6c5e3d | 7232 | /* allocate memory for both Tx and Rx ring pointers */ |
f650a38b ASJ |
7233 | size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2; |
7234 | vsi->tx_rings = kzalloc(size, GFP_KERNEL); | |
7235 | if (!vsi->tx_rings) | |
7236 | return -ENOMEM; | |
f650a38b ASJ |
7237 | vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs]; |
7238 | ||
bc7d338f ASJ |
7239 | if (alloc_qvectors) { |
7240 | /* allocate memory for q_vector pointers */ | |
f57e4fbd | 7241 | size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors; |
bc7d338f ASJ |
7242 | vsi->q_vectors = kzalloc(size, GFP_KERNEL); |
7243 | if (!vsi->q_vectors) { | |
7244 | ret = -ENOMEM; | |
7245 | goto err_vectors; | |
7246 | } | |
f650a38b ASJ |
7247 | } |
7248 | return ret; | |
7249 | ||
7250 | err_vectors: | |
7251 | kfree(vsi->tx_rings); | |
7252 | return ret; | |
7253 | } | |
7254 | ||
41c445ff JB |
7255 | /** |
7256 | * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF | |
7257 | * @pf: board private structure | |
7258 | * @type: type of VSI | |
7259 | * | |
7260 | * On error: returns error code (negative) | |
7261 | * On success: returns vsi index in PF (positive) | |
7262 | **/ | |
7263 | static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type) | |
7264 | { | |
7265 | int ret = -ENODEV; | |
7266 | struct i40e_vsi *vsi; | |
7267 | int vsi_idx; | |
7268 | int i; | |
7269 | ||
7270 | /* Need to protect the allocation of the VSIs at the PF level */ | |
7271 | mutex_lock(&pf->switch_mutex); | |
7272 | ||
7273 | /* VSI list may be fragmented if VSI creation/destruction has | |
7274 | * been happening. We can afford to do a quick scan to look | |
7275 | * for any free VSIs in the list. | |
7276 | * | |
7277 | * find next empty vsi slot, looping back around if necessary | |
7278 | */ | |
7279 | i = pf->next_vsi; | |
505682cd | 7280 | while (i < pf->num_alloc_vsi && pf->vsi[i]) |
41c445ff | 7281 | i++; |
505682cd | 7282 | if (i >= pf->num_alloc_vsi) { |
41c445ff JB |
7283 | i = 0; |
7284 | while (i < pf->next_vsi && pf->vsi[i]) | |
7285 | i++; | |
7286 | } | |
7287 | ||
505682cd | 7288 | if (i < pf->num_alloc_vsi && !pf->vsi[i]) { |
41c445ff JB |
7289 | vsi_idx = i; /* Found one! */ |
7290 | } else { | |
7291 | ret = -ENODEV; | |
493fb300 | 7292 | goto unlock_pf; /* out of VSI slots! */ |
41c445ff JB |
7293 | } |
7294 | pf->next_vsi = ++i; | |
7295 | ||
7296 | vsi = kzalloc(sizeof(*vsi), GFP_KERNEL); | |
7297 | if (!vsi) { | |
7298 | ret = -ENOMEM; | |
493fb300 | 7299 | goto unlock_pf; |
41c445ff JB |
7300 | } |
7301 | vsi->type = type; | |
7302 | vsi->back = pf; | |
7303 | set_bit(__I40E_DOWN, &vsi->state); | |
7304 | vsi->flags = 0; | |
7305 | vsi->idx = vsi_idx; | |
ac26fc13 | 7306 | vsi->int_rate_limit = 0; |
5db4cb59 ASJ |
7307 | vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ? |
7308 | pf->rss_table_size : 64; | |
41c445ff JB |
7309 | vsi->netdev_registered = false; |
7310 | vsi->work_limit = I40E_DEFAULT_IRQ_WORK; | |
7311 | INIT_LIST_HEAD(&vsi->mac_filter_list); | |
63741846 | 7312 | vsi->irqs_ready = false; |
41c445ff | 7313 | |
9f65e15b AD |
7314 | ret = i40e_set_num_rings_in_vsi(vsi); |
7315 | if (ret) | |
7316 | goto err_rings; | |
7317 | ||
bc7d338f | 7318 | ret = i40e_vsi_alloc_arrays(vsi, true); |
f650a38b | 7319 | if (ret) |
9f65e15b | 7320 | goto err_rings; |
493fb300 | 7321 | |
41c445ff JB |
7322 | /* Setup default MSIX irq handler for VSI */ |
7323 | i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings); | |
7324 | ||
21659035 KP |
7325 | /* Initialize VSI lock */ |
7326 | spin_lock_init(&vsi->mac_filter_list_lock); | |
41c445ff JB |
7327 | pf->vsi[vsi_idx] = vsi; |
7328 | ret = vsi_idx; | |
493fb300 AD |
7329 | goto unlock_pf; |
7330 | ||
9f65e15b | 7331 | err_rings: |
493fb300 AD |
7332 | pf->next_vsi = i - 1; |
7333 | kfree(vsi); | |
7334 | unlock_pf: | |
41c445ff JB |
7335 | mutex_unlock(&pf->switch_mutex); |
7336 | return ret; | |
7337 | } | |
7338 | ||
f650a38b ASJ |
7339 | /** |
7340 | * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI | |
7341 | * @type: VSI pointer | |
bc7d338f | 7342 | * @free_qvectors: a bool to specify if q_vectors need to be freed. |
f650a38b ASJ |
7343 | * |
7344 | * On error: returns error code (negative) | |
7345 | * On success: returns 0 | |
7346 | **/ | |
bc7d338f | 7347 | static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors) |
f650a38b ASJ |
7348 | { |
7349 | /* free the ring and vector containers */ | |
bc7d338f ASJ |
7350 | if (free_qvectors) { |
7351 | kfree(vsi->q_vectors); | |
7352 | vsi->q_vectors = NULL; | |
7353 | } | |
f650a38b ASJ |
7354 | kfree(vsi->tx_rings); |
7355 | vsi->tx_rings = NULL; | |
7356 | vsi->rx_rings = NULL; | |
7357 | } | |
7358 | ||
28c5869f HZ |
7359 | /** |
7360 | * i40e_clear_rss_config_user - clear the user configured RSS hash keys | |
7361 | * and lookup table | |
7362 | * @vsi: Pointer to VSI structure | |
7363 | */ | |
7364 | static void i40e_clear_rss_config_user(struct i40e_vsi *vsi) | |
7365 | { | |
7366 | if (!vsi) | |
7367 | return; | |
7368 | ||
7369 | kfree(vsi->rss_hkey_user); | |
7370 | vsi->rss_hkey_user = NULL; | |
7371 | ||
7372 | kfree(vsi->rss_lut_user); | |
7373 | vsi->rss_lut_user = NULL; | |
7374 | } | |
7375 | ||
41c445ff JB |
7376 | /** |
7377 | * i40e_vsi_clear - Deallocate the VSI provided | |
7378 | * @vsi: the VSI being un-configured | |
7379 | **/ | |
7380 | static int i40e_vsi_clear(struct i40e_vsi *vsi) | |
7381 | { | |
7382 | struct i40e_pf *pf; | |
7383 | ||
7384 | if (!vsi) | |
7385 | return 0; | |
7386 | ||
7387 | if (!vsi->back) | |
7388 | goto free_vsi; | |
7389 | pf = vsi->back; | |
7390 | ||
7391 | mutex_lock(&pf->switch_mutex); | |
7392 | if (!pf->vsi[vsi->idx]) { | |
7393 | dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n", | |
7394 | vsi->idx, vsi->idx, vsi, vsi->type); | |
7395 | goto unlock_vsi; | |
7396 | } | |
7397 | ||
7398 | if (pf->vsi[vsi->idx] != vsi) { | |
7399 | dev_err(&pf->pdev->dev, | |
7400 | "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n", | |
7401 | pf->vsi[vsi->idx]->idx, | |
7402 | pf->vsi[vsi->idx], | |
7403 | pf->vsi[vsi->idx]->type, | |
7404 | vsi->idx, vsi, vsi->type); | |
7405 | goto unlock_vsi; | |
7406 | } | |
7407 | ||
b40c82e6 | 7408 | /* updates the PF for this cleared vsi */ |
41c445ff JB |
7409 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
7410 | i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx); | |
7411 | ||
bc7d338f | 7412 | i40e_vsi_free_arrays(vsi, true); |
28c5869f | 7413 | i40e_clear_rss_config_user(vsi); |
493fb300 | 7414 | |
41c445ff JB |
7415 | pf->vsi[vsi->idx] = NULL; |
7416 | if (vsi->idx < pf->next_vsi) | |
7417 | pf->next_vsi = vsi->idx; | |
7418 | ||
7419 | unlock_vsi: | |
7420 | mutex_unlock(&pf->switch_mutex); | |
7421 | free_vsi: | |
7422 | kfree(vsi); | |
7423 | ||
7424 | return 0; | |
7425 | } | |
7426 | ||
9f65e15b AD |
7427 | /** |
7428 | * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI | |
7429 | * @vsi: the VSI being cleaned | |
7430 | **/ | |
be1d5eea | 7431 | static void i40e_vsi_clear_rings(struct i40e_vsi *vsi) |
9f65e15b AD |
7432 | { |
7433 | int i; | |
7434 | ||
8e9dca53 | 7435 | if (vsi->tx_rings && vsi->tx_rings[0]) { |
d7397644 | 7436 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
00403f04 MW |
7437 | kfree_rcu(vsi->tx_rings[i], rcu); |
7438 | vsi->tx_rings[i] = NULL; | |
7439 | vsi->rx_rings[i] = NULL; | |
7440 | } | |
be1d5eea | 7441 | } |
9f65e15b AD |
7442 | } |
7443 | ||
41c445ff JB |
7444 | /** |
7445 | * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI | |
7446 | * @vsi: the VSI being configured | |
7447 | **/ | |
7448 | static int i40e_alloc_rings(struct i40e_vsi *vsi) | |
7449 | { | |
e7046ee1 | 7450 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff | 7451 | struct i40e_pf *pf = vsi->back; |
41c445ff JB |
7452 | int i; |
7453 | ||
41c445ff | 7454 | /* Set basic values in the rings to be used later during open() */ |
d7397644 | 7455 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
ac6c5e3d | 7456 | /* allocate space for both Tx and Rx in one shot */ |
9f65e15b AD |
7457 | tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL); |
7458 | if (!tx_ring) | |
7459 | goto err_out; | |
41c445ff JB |
7460 | |
7461 | tx_ring->queue_index = i; | |
7462 | tx_ring->reg_idx = vsi->base_queue + i; | |
7463 | tx_ring->ring_active = false; | |
7464 | tx_ring->vsi = vsi; | |
7465 | tx_ring->netdev = vsi->netdev; | |
7466 | tx_ring->dev = &pf->pdev->dev; | |
7467 | tx_ring->count = vsi->num_desc; | |
7468 | tx_ring->size = 0; | |
7469 | tx_ring->dcb_tc = 0; | |
8e0764b4 ASJ |
7470 | if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE) |
7471 | tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; | |
a75e8005 | 7472 | tx_ring->tx_itr_setting = pf->tx_itr_default; |
9f65e15b | 7473 | vsi->tx_rings[i] = tx_ring; |
41c445ff | 7474 | |
9f65e15b | 7475 | rx_ring = &tx_ring[1]; |
41c445ff JB |
7476 | rx_ring->queue_index = i; |
7477 | rx_ring->reg_idx = vsi->base_queue + i; | |
7478 | rx_ring->ring_active = false; | |
7479 | rx_ring->vsi = vsi; | |
7480 | rx_ring->netdev = vsi->netdev; | |
7481 | rx_ring->dev = &pf->pdev->dev; | |
7482 | rx_ring->count = vsi->num_desc; | |
7483 | rx_ring->size = 0; | |
7484 | rx_ring->dcb_tc = 0; | |
a75e8005 | 7485 | rx_ring->rx_itr_setting = pf->rx_itr_default; |
9f65e15b | 7486 | vsi->rx_rings[i] = rx_ring; |
41c445ff JB |
7487 | } |
7488 | ||
7489 | return 0; | |
9f65e15b AD |
7490 | |
7491 | err_out: | |
7492 | i40e_vsi_clear_rings(vsi); | |
7493 | return -ENOMEM; | |
41c445ff JB |
7494 | } |
7495 | ||
7496 | /** | |
7497 | * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel | |
7498 | * @pf: board private structure | |
7499 | * @vectors: the number of MSI-X vectors to request | |
7500 | * | |
7501 | * Returns the number of vectors reserved, or error | |
7502 | **/ | |
7503 | static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors) | |
7504 | { | |
7b37f376 AG |
7505 | vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries, |
7506 | I40E_MIN_MSIX, vectors); | |
7507 | if (vectors < 0) { | |
41c445ff | 7508 | dev_info(&pf->pdev->dev, |
7b37f376 | 7509 | "MSI-X vector reservation failed: %d\n", vectors); |
41c445ff JB |
7510 | vectors = 0; |
7511 | } | |
7512 | ||
7513 | return vectors; | |
7514 | } | |
7515 | ||
7516 | /** | |
7517 | * i40e_init_msix - Setup the MSIX capability | |
7518 | * @pf: board private structure | |
7519 | * | |
7520 | * Work with the OS to set up the MSIX vectors needed. | |
7521 | * | |
3b444399 | 7522 | * Returns the number of vectors reserved or negative on failure |
41c445ff JB |
7523 | **/ |
7524 | static int i40e_init_msix(struct i40e_pf *pf) | |
7525 | { | |
41c445ff | 7526 | struct i40e_hw *hw = &pf->hw; |
1e200e4a | 7527 | int vectors_left; |
41c445ff | 7528 | int v_budget, i; |
3b444399 | 7529 | int v_actual; |
e3219ce6 | 7530 | int iwarp_requested = 0; |
41c445ff JB |
7531 | |
7532 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
7533 | return -ENODEV; | |
7534 | ||
7535 | /* The number of vectors we'll request will be comprised of: | |
7536 | * - Add 1 for "other" cause for Admin Queue events, etc. | |
7537 | * - The number of LAN queue pairs | |
f8ff1464 ASJ |
7538 | * - Queues being used for RSS. |
7539 | * We don't need as many as max_rss_size vectors. | |
7540 | * use rss_size instead in the calculation since that | |
7541 | * is governed by number of cpus in the system. | |
7542 | * - assumes symmetric Tx/Rx pairing | |
41c445ff | 7543 | * - The number of VMDq pairs |
e3219ce6 | 7544 | * - The CPU count within the NUMA node if iWARP is enabled |
38e00438 VD |
7545 | #ifdef I40E_FCOE |
7546 | * - The number of FCOE qps. | |
7547 | #endif | |
41c445ff JB |
7548 | * Once we count this up, try the request. |
7549 | * | |
7550 | * If we can't get what we want, we'll simplify to nearly nothing | |
7551 | * and try again. If that still fails, we punt. | |
7552 | */ | |
1e200e4a SN |
7553 | vectors_left = hw->func_caps.num_msix_vectors; |
7554 | v_budget = 0; | |
7555 | ||
7556 | /* reserve one vector for miscellaneous handler */ | |
7557 | if (vectors_left) { | |
7558 | v_budget++; | |
7559 | vectors_left--; | |
7560 | } | |
7561 | ||
7562 | /* reserve vectors for the main PF traffic queues */ | |
7563 | pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left); | |
7564 | vectors_left -= pf->num_lan_msix; | |
7565 | v_budget += pf->num_lan_msix; | |
7566 | ||
7567 | /* reserve one vector for sideband flow director */ | |
7568 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
7569 | if (vectors_left) { | |
a70e407f | 7570 | pf->num_fdsb_msix = 1; |
1e200e4a SN |
7571 | v_budget++; |
7572 | vectors_left--; | |
7573 | } else { | |
a70e407f | 7574 | pf->num_fdsb_msix = 0; |
1e200e4a SN |
7575 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; |
7576 | } | |
7577 | } | |
83840e4b | 7578 | |
38e00438 | 7579 | #ifdef I40E_FCOE |
1e200e4a | 7580 | /* can we reserve enough for FCoE? */ |
38e00438 | 7581 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) { |
1e200e4a SN |
7582 | if (!vectors_left) |
7583 | pf->num_fcoe_msix = 0; | |
7584 | else if (vectors_left >= pf->num_fcoe_qps) | |
7585 | pf->num_fcoe_msix = pf->num_fcoe_qps; | |
7586 | else | |
7587 | pf->num_fcoe_msix = 1; | |
38e00438 | 7588 | v_budget += pf->num_fcoe_msix; |
1e200e4a | 7589 | vectors_left -= pf->num_fcoe_msix; |
38e00438 | 7590 | } |
1e200e4a | 7591 | |
38e00438 | 7592 | #endif |
e3219ce6 ASJ |
7593 | /* can we reserve enough for iWARP? */ |
7594 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { | |
7595 | if (!vectors_left) | |
7596 | pf->num_iwarp_msix = 0; | |
7597 | else if (vectors_left < pf->num_iwarp_msix) | |
7598 | pf->num_iwarp_msix = 1; | |
7599 | v_budget += pf->num_iwarp_msix; | |
7600 | vectors_left -= pf->num_iwarp_msix; | |
7601 | } | |
7602 | ||
1e200e4a SN |
7603 | /* any vectors left over go for VMDq support */ |
7604 | if (pf->flags & I40E_FLAG_VMDQ_ENABLED) { | |
7605 | int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps; | |
7606 | int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted); | |
7607 | ||
7608 | /* if we're short on vectors for what's desired, we limit | |
7609 | * the queues per vmdq. If this is still more than are | |
7610 | * available, the user will need to change the number of | |
7611 | * queues/vectors used by the PF later with the ethtool | |
7612 | * channels command | |
7613 | */ | |
7614 | if (vmdq_vecs < vmdq_vecs_wanted) | |
7615 | pf->num_vmdq_qps = 1; | |
7616 | pf->num_vmdq_msix = pf->num_vmdq_qps; | |
7617 | ||
7618 | v_budget += vmdq_vecs; | |
7619 | vectors_left -= vmdq_vecs; | |
7620 | } | |
41c445ff JB |
7621 | |
7622 | pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), | |
7623 | GFP_KERNEL); | |
7624 | if (!pf->msix_entries) | |
7625 | return -ENOMEM; | |
7626 | ||
7627 | for (i = 0; i < v_budget; i++) | |
7628 | pf->msix_entries[i].entry = i; | |
3b444399 | 7629 | v_actual = i40e_reserve_msix_vectors(pf, v_budget); |
a34977ba | 7630 | |
3b444399 | 7631 | if (v_actual != v_budget) { |
a34977ba ASJ |
7632 | /* If we have limited resources, we will start with no vectors |
7633 | * for the special features and then allocate vectors to some | |
7634 | * of these features based on the policy and at the end disable | |
7635 | * the features that did not get any vectors. | |
7636 | */ | |
e3219ce6 ASJ |
7637 | iwarp_requested = pf->num_iwarp_msix; |
7638 | pf->num_iwarp_msix = 0; | |
38e00438 VD |
7639 | #ifdef I40E_FCOE |
7640 | pf->num_fcoe_qps = 0; | |
7641 | pf->num_fcoe_msix = 0; | |
7642 | #endif | |
a34977ba ASJ |
7643 | pf->num_vmdq_msix = 0; |
7644 | } | |
7645 | ||
3b444399 | 7646 | if (v_actual < I40E_MIN_MSIX) { |
41c445ff JB |
7647 | pf->flags &= ~I40E_FLAG_MSIX_ENABLED; |
7648 | kfree(pf->msix_entries); | |
7649 | pf->msix_entries = NULL; | |
7650 | return -ENODEV; | |
7651 | ||
3b444399 | 7652 | } else if (v_actual == I40E_MIN_MSIX) { |
41c445ff | 7653 | /* Adjust for minimal MSIX use */ |
41c445ff JB |
7654 | pf->num_vmdq_vsis = 0; |
7655 | pf->num_vmdq_qps = 0; | |
41c445ff JB |
7656 | pf->num_lan_qps = 1; |
7657 | pf->num_lan_msix = 1; | |
7658 | ||
3b444399 SN |
7659 | } else if (v_actual != v_budget) { |
7660 | int vec; | |
7661 | ||
a34977ba | 7662 | /* reserve the misc vector */ |
3b444399 | 7663 | vec = v_actual - 1; |
a34977ba | 7664 | |
41c445ff JB |
7665 | /* Scale vector usage down */ |
7666 | pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */ | |
a34977ba | 7667 | pf->num_vmdq_vsis = 1; |
1e200e4a SN |
7668 | pf->num_vmdq_qps = 1; |
7669 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
41c445ff JB |
7670 | |
7671 | /* partition out the remaining vectors */ | |
7672 | switch (vec) { | |
7673 | case 2: | |
41c445ff JB |
7674 | pf->num_lan_msix = 1; |
7675 | break; | |
7676 | case 3: | |
e3219ce6 ASJ |
7677 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
7678 | pf->num_lan_msix = 1; | |
7679 | pf->num_iwarp_msix = 1; | |
7680 | } else { | |
7681 | pf->num_lan_msix = 2; | |
7682 | } | |
38e00438 VD |
7683 | #ifdef I40E_FCOE |
7684 | /* give one vector to FCoE */ | |
7685 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) { | |
7686 | pf->num_lan_msix = 1; | |
7687 | pf->num_fcoe_msix = 1; | |
7688 | } | |
38e00438 | 7689 | #endif |
41c445ff JB |
7690 | break; |
7691 | default: | |
e3219ce6 ASJ |
7692 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
7693 | pf->num_iwarp_msix = min_t(int, (vec / 3), | |
7694 | iwarp_requested); | |
7695 | pf->num_vmdq_vsis = min_t(int, (vec / 3), | |
7696 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
7697 | } else { | |
7698 | pf->num_vmdq_vsis = min_t(int, (vec / 2), | |
7699 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
7700 | } | |
7701 | pf->num_lan_msix = min_t(int, | |
7702 | (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)), | |
7703 | pf->num_lan_msix); | |
38e00438 VD |
7704 | #ifdef I40E_FCOE |
7705 | /* give one vector to FCoE */ | |
7706 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) { | |
7707 | pf->num_fcoe_msix = 1; | |
7708 | vec--; | |
7709 | } | |
7710 | #endif | |
41c445ff JB |
7711 | break; |
7712 | } | |
7713 | } | |
7714 | ||
a34977ba ASJ |
7715 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && |
7716 | (pf->num_vmdq_msix == 0)) { | |
7717 | dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n"); | |
7718 | pf->flags &= ~I40E_FLAG_VMDQ_ENABLED; | |
7719 | } | |
e3219ce6 ASJ |
7720 | |
7721 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && | |
7722 | (pf->num_iwarp_msix == 0)) { | |
7723 | dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n"); | |
7724 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
7725 | } | |
38e00438 VD |
7726 | #ifdef I40E_FCOE |
7727 | ||
7728 | if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) { | |
7729 | dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n"); | |
7730 | pf->flags &= ~I40E_FLAG_FCOE_ENABLED; | |
7731 | } | |
7732 | #endif | |
3b444399 | 7733 | return v_actual; |
41c445ff JB |
7734 | } |
7735 | ||
493fb300 | 7736 | /** |
90e04070 | 7737 | * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector |
493fb300 AD |
7738 | * @vsi: the VSI being configured |
7739 | * @v_idx: index of the vector in the vsi struct | |
7740 | * | |
7741 | * We allocate one q_vector. If allocation fails we return -ENOMEM. | |
7742 | **/ | |
90e04070 | 7743 | static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx) |
493fb300 AD |
7744 | { |
7745 | struct i40e_q_vector *q_vector; | |
7746 | ||
7747 | /* allocate q_vector */ | |
7748 | q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL); | |
7749 | if (!q_vector) | |
7750 | return -ENOMEM; | |
7751 | ||
7752 | q_vector->vsi = vsi; | |
7753 | q_vector->v_idx = v_idx; | |
7754 | cpumask_set_cpu(v_idx, &q_vector->affinity_mask); | |
7755 | if (vsi->netdev) | |
7756 | netif_napi_add(vsi->netdev, &q_vector->napi, | |
eefeacee | 7757 | i40e_napi_poll, NAPI_POLL_WEIGHT); |
493fb300 | 7758 | |
cd0b6fa6 AD |
7759 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
7760 | q_vector->tx.latency_range = I40E_LOW_LATENCY; | |
7761 | ||
493fb300 AD |
7762 | /* tie q_vector and vsi together */ |
7763 | vsi->q_vectors[v_idx] = q_vector; | |
7764 | ||
7765 | return 0; | |
7766 | } | |
7767 | ||
41c445ff | 7768 | /** |
90e04070 | 7769 | * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors |
41c445ff JB |
7770 | * @vsi: the VSI being configured |
7771 | * | |
7772 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
7773 | * return -ENOMEM. | |
7774 | **/ | |
90e04070 | 7775 | static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi) |
41c445ff JB |
7776 | { |
7777 | struct i40e_pf *pf = vsi->back; | |
7778 | int v_idx, num_q_vectors; | |
493fb300 | 7779 | int err; |
41c445ff JB |
7780 | |
7781 | /* if not MSIX, give the one vector only to the LAN VSI */ | |
7782 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
7783 | num_q_vectors = vsi->num_q_vectors; | |
7784 | else if (vsi == pf->vsi[pf->lan_vsi]) | |
7785 | num_q_vectors = 1; | |
7786 | else | |
7787 | return -EINVAL; | |
7788 | ||
41c445ff | 7789 | for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { |
90e04070 | 7790 | err = i40e_vsi_alloc_q_vector(vsi, v_idx); |
493fb300 AD |
7791 | if (err) |
7792 | goto err_out; | |
41c445ff JB |
7793 | } |
7794 | ||
7795 | return 0; | |
493fb300 AD |
7796 | |
7797 | err_out: | |
7798 | while (v_idx--) | |
7799 | i40e_free_q_vector(vsi, v_idx); | |
7800 | ||
7801 | return err; | |
41c445ff JB |
7802 | } |
7803 | ||
7804 | /** | |
7805 | * i40e_init_interrupt_scheme - Determine proper interrupt scheme | |
7806 | * @pf: board private structure to initialize | |
7807 | **/ | |
c1147280 | 7808 | static int i40e_init_interrupt_scheme(struct i40e_pf *pf) |
41c445ff | 7809 | { |
3b444399 SN |
7810 | int vectors = 0; |
7811 | ssize_t size; | |
41c445ff JB |
7812 | |
7813 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
3b444399 SN |
7814 | vectors = i40e_init_msix(pf); |
7815 | if (vectors < 0) { | |
60ea5f83 | 7816 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | |
e3219ce6 | 7817 | I40E_FLAG_IWARP_ENABLED | |
38e00438 VD |
7818 | #ifdef I40E_FCOE |
7819 | I40E_FLAG_FCOE_ENABLED | | |
7820 | #endif | |
60ea5f83 | 7821 | I40E_FLAG_RSS_ENABLED | |
4d9b6043 | 7822 | I40E_FLAG_DCB_CAPABLE | |
60ea5f83 JB |
7823 | I40E_FLAG_SRIOV_ENABLED | |
7824 | I40E_FLAG_FD_SB_ENABLED | | |
7825 | I40E_FLAG_FD_ATR_ENABLED | | |
7826 | I40E_FLAG_VMDQ_ENABLED); | |
41c445ff JB |
7827 | |
7828 | /* rework the queue expectations without MSIX */ | |
7829 | i40e_determine_queue_usage(pf); | |
7830 | } | |
7831 | } | |
7832 | ||
7833 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
7834 | (pf->flags & I40E_FLAG_MSI_ENABLED)) { | |
77fa28be | 7835 | dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n"); |
3b444399 SN |
7836 | vectors = pci_enable_msi(pf->pdev); |
7837 | if (vectors < 0) { | |
7838 | dev_info(&pf->pdev->dev, "MSI init failed - %d\n", | |
7839 | vectors); | |
41c445ff JB |
7840 | pf->flags &= ~I40E_FLAG_MSI_ENABLED; |
7841 | } | |
3b444399 | 7842 | vectors = 1; /* one MSI or Legacy vector */ |
41c445ff JB |
7843 | } |
7844 | ||
958a3e3b | 7845 | if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED))) |
77fa28be | 7846 | dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n"); |
958a3e3b | 7847 | |
3b444399 SN |
7848 | /* set up vector assignment tracking */ |
7849 | size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors); | |
7850 | pf->irq_pile = kzalloc(size, GFP_KERNEL); | |
c1147280 JB |
7851 | if (!pf->irq_pile) { |
7852 | dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n"); | |
7853 | return -ENOMEM; | |
7854 | } | |
3b444399 SN |
7855 | pf->irq_pile->num_entries = vectors; |
7856 | pf->irq_pile->search_hint = 0; | |
7857 | ||
c1147280 | 7858 | /* track first vector for misc interrupts, ignore return */ |
3b444399 | 7859 | (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1); |
c1147280 JB |
7860 | |
7861 | return 0; | |
41c445ff JB |
7862 | } |
7863 | ||
7864 | /** | |
7865 | * i40e_setup_misc_vector - Setup the misc vector to handle non queue events | |
7866 | * @pf: board private structure | |
7867 | * | |
7868 | * This sets up the handler for MSIX 0, which is used to manage the | |
7869 | * non-queue interrupts, e.g. AdminQ and errors. This is not used | |
7870 | * when in MSI or Legacy interrupt mode. | |
7871 | **/ | |
7872 | static int i40e_setup_misc_vector(struct i40e_pf *pf) | |
7873 | { | |
7874 | struct i40e_hw *hw = &pf->hw; | |
7875 | int err = 0; | |
7876 | ||
7877 | /* Only request the irq if this is the first time through, and | |
7878 | * not when we're rebuilding after a Reset | |
7879 | */ | |
7880 | if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) { | |
7881 | err = request_irq(pf->msix_entries[0].vector, | |
b294ac70 | 7882 | i40e_intr, 0, pf->int_name, pf); |
41c445ff JB |
7883 | if (err) { |
7884 | dev_info(&pf->pdev->dev, | |
77fa28be | 7885 | "request_irq for %s failed: %d\n", |
b294ac70 | 7886 | pf->int_name, err); |
41c445ff JB |
7887 | return -EFAULT; |
7888 | } | |
7889 | } | |
7890 | ||
ab437b5a | 7891 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
7892 | |
7893 | /* associate no queues to the misc vector */ | |
7894 | wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST); | |
7895 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K); | |
7896 | ||
7897 | i40e_flush(hw); | |
7898 | ||
40d72a50 | 7899 | i40e_irq_dynamic_enable_icr0(pf, true); |
41c445ff JB |
7900 | |
7901 | return err; | |
7902 | } | |
7903 | ||
7904 | /** | |
e25d00b8 ASJ |
7905 | * i40e_config_rss_aq - Prepare for RSS using AQ commands |
7906 | * @vsi: vsi structure | |
7907 | * @seed: RSS hash seed | |
7908 | **/ | |
e69ff813 HZ |
7909 | static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed, |
7910 | u8 *lut, u16 lut_size) | |
e25d00b8 ASJ |
7911 | { |
7912 | struct i40e_aqc_get_set_rss_key_data rss_key; | |
7913 | struct i40e_pf *pf = vsi->back; | |
7914 | struct i40e_hw *hw = &pf->hw; | |
7915 | bool pf_lut = false; | |
7916 | u8 *rss_lut; | |
7917 | int ret, i; | |
7918 | ||
7919 | memset(&rss_key, 0, sizeof(rss_key)); | |
7920 | memcpy(&rss_key, seed, sizeof(rss_key)); | |
7921 | ||
7922 | rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL); | |
7923 | if (!rss_lut) | |
7924 | return -ENOMEM; | |
7925 | ||
7926 | /* Populate the LUT with max no. of queues in round robin fashion */ | |
7927 | for (i = 0; i < vsi->rss_table_size; i++) | |
7928 | rss_lut[i] = i % vsi->rss_size; | |
7929 | ||
7930 | ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key); | |
7931 | if (ret) { | |
7932 | dev_info(&pf->pdev->dev, | |
7933 | "Cannot set RSS key, err %s aq_err %s\n", | |
7934 | i40e_stat_str(&pf->hw, ret), | |
7935 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
126b63d9 | 7936 | goto config_rss_aq_out; |
e25d00b8 ASJ |
7937 | } |
7938 | ||
7939 | if (vsi->type == I40E_VSI_MAIN) | |
7940 | pf_lut = true; | |
7941 | ||
7942 | ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut, | |
7943 | vsi->rss_table_size); | |
7944 | if (ret) | |
7945 | dev_info(&pf->pdev->dev, | |
7946 | "Cannot set RSS lut, err %s aq_err %s\n", | |
7947 | i40e_stat_str(&pf->hw, ret), | |
7948 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7949 | ||
126b63d9 AS |
7950 | config_rss_aq_out: |
7951 | kfree(rss_lut); | |
e25d00b8 ASJ |
7952 | return ret; |
7953 | } | |
7954 | ||
7955 | /** | |
7956 | * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used | |
7957 | * @vsi: VSI structure | |
7958 | **/ | |
7959 | static int i40e_vsi_config_rss(struct i40e_vsi *vsi) | |
7960 | { | |
7961 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
7962 | struct i40e_pf *pf = vsi->back; | |
e69ff813 HZ |
7963 | u8 *lut; |
7964 | int ret; | |
7965 | ||
7966 | if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) | |
7967 | return 0; | |
7968 | ||
7969 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); | |
7970 | if (!lut) | |
7971 | return -ENOMEM; | |
e25d00b8 | 7972 | |
e69ff813 | 7973 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); |
e25d00b8 | 7974 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); |
acd65448 | 7975 | vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs); |
e69ff813 HZ |
7976 | ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size); |
7977 | kfree(lut); | |
e25d00b8 | 7978 | |
e69ff813 | 7979 | return ret; |
e25d00b8 ASJ |
7980 | } |
7981 | ||
95a73780 ASJ |
7982 | /** |
7983 | * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands | |
7984 | * @vsi: Pointer to vsi structure | |
7985 | * @seed: Buffter to store the hash keys | |
7986 | * @lut: Buffer to store the lookup table entries | |
7987 | * @lut_size: Size of buffer to store the lookup table entries | |
7988 | * | |
7989 | * Return 0 on success, negative on failure | |
7990 | */ | |
7991 | static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed, | |
7992 | u8 *lut, u16 lut_size) | |
7993 | { | |
7994 | struct i40e_pf *pf = vsi->back; | |
7995 | struct i40e_hw *hw = &pf->hw; | |
7996 | int ret = 0; | |
7997 | ||
7998 | if (seed) { | |
7999 | ret = i40e_aq_get_rss_key(hw, vsi->id, | |
8000 | (struct i40e_aqc_get_set_rss_key_data *)seed); | |
8001 | if (ret) { | |
8002 | dev_info(&pf->pdev->dev, | |
8003 | "Cannot get RSS key, err %s aq_err %s\n", | |
8004 | i40e_stat_str(&pf->hw, ret), | |
8005 | i40e_aq_str(&pf->hw, | |
8006 | pf->hw.aq.asq_last_status)); | |
8007 | return ret; | |
8008 | } | |
8009 | } | |
8010 | ||
8011 | if (lut) { | |
8012 | bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; | |
8013 | ||
8014 | ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); | |
8015 | if (ret) { | |
8016 | dev_info(&pf->pdev->dev, | |
8017 | "Cannot get RSS lut, err %s aq_err %s\n", | |
8018 | i40e_stat_str(&pf->hw, ret), | |
8019 | i40e_aq_str(&pf->hw, | |
8020 | pf->hw.aq.asq_last_status)); | |
8021 | return ret; | |
8022 | } | |
8023 | } | |
8024 | ||
8025 | return ret; | |
8026 | } | |
8027 | ||
e25d00b8 | 8028 | /** |
043dd650 | 8029 | * i40e_config_rss_reg - Configure RSS keys and lut by writing registers |
e69ff813 | 8030 | * @vsi: Pointer to vsi structure |
e25d00b8 | 8031 | * @seed: RSS hash seed |
e69ff813 HZ |
8032 | * @lut: Lookup table |
8033 | * @lut_size: Lookup table size | |
8034 | * | |
8035 | * Returns 0 on success, negative on failure | |
41c445ff | 8036 | **/ |
e69ff813 HZ |
8037 | static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed, |
8038 | const u8 *lut, u16 lut_size) | |
41c445ff | 8039 | { |
e69ff813 | 8040 | struct i40e_pf *pf = vsi->back; |
4617e8c0 | 8041 | struct i40e_hw *hw = &pf->hw; |
c4e1868c | 8042 | u16 vf_id = vsi->vf_id; |
e69ff813 | 8043 | u8 i; |
41c445ff | 8044 | |
e25d00b8 | 8045 | /* Fill out hash function seed */ |
e69ff813 HZ |
8046 | if (seed) { |
8047 | u32 *seed_dw = (u32 *)seed; | |
8048 | ||
c4e1868c MW |
8049 | if (vsi->type == I40E_VSI_MAIN) { |
8050 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
8051 | i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), | |
8052 | seed_dw[i]); | |
8053 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
8054 | for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++) | |
8055 | i40e_write_rx_ctl(hw, | |
8056 | I40E_VFQF_HKEY1(i, vf_id), | |
8057 | seed_dw[i]); | |
8058 | } else { | |
8059 | dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n"); | |
8060 | } | |
e69ff813 HZ |
8061 | } |
8062 | ||
8063 | if (lut) { | |
8064 | u32 *lut_dw = (u32 *)lut; | |
8065 | ||
c4e1868c MW |
8066 | if (vsi->type == I40E_VSI_MAIN) { |
8067 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
8068 | return -EINVAL; | |
8069 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
8070 | wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]); | |
8071 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
8072 | if (lut_size != I40E_VF_HLUT_ARRAY_SIZE) | |
8073 | return -EINVAL; | |
8074 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
8075 | i40e_write_rx_ctl(hw, | |
8076 | I40E_VFQF_HLUT1(i, vf_id), | |
8077 | lut_dw[i]); | |
8078 | } else { | |
8079 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
8080 | } | |
e25d00b8 ASJ |
8081 | } |
8082 | i40e_flush(hw); | |
8083 | ||
8084 | return 0; | |
8085 | } | |
8086 | ||
043dd650 HZ |
8087 | /** |
8088 | * i40e_get_rss_reg - Get the RSS keys and lut by reading registers | |
8089 | * @vsi: Pointer to VSI structure | |
8090 | * @seed: Buffer to store the keys | |
8091 | * @lut: Buffer to store the lookup table entries | |
8092 | * @lut_size: Size of buffer to store the lookup table entries | |
8093 | * | |
8094 | * Returns 0 on success, negative on failure | |
8095 | */ | |
8096 | static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed, | |
8097 | u8 *lut, u16 lut_size) | |
8098 | { | |
8099 | struct i40e_pf *pf = vsi->back; | |
8100 | struct i40e_hw *hw = &pf->hw; | |
8101 | u16 i; | |
8102 | ||
8103 | if (seed) { | |
8104 | u32 *seed_dw = (u32 *)seed; | |
8105 | ||
8106 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
272cdaf2 | 8107 | seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i)); |
043dd650 HZ |
8108 | } |
8109 | if (lut) { | |
8110 | u32 *lut_dw = (u32 *)lut; | |
8111 | ||
8112 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
8113 | return -EINVAL; | |
8114 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
8115 | lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i)); | |
8116 | } | |
8117 | ||
8118 | return 0; | |
8119 | } | |
8120 | ||
8121 | /** | |
8122 | * i40e_config_rss - Configure RSS keys and lut | |
8123 | * @vsi: Pointer to VSI structure | |
8124 | * @seed: RSS hash seed | |
8125 | * @lut: Lookup table | |
8126 | * @lut_size: Lookup table size | |
8127 | * | |
8128 | * Returns 0 on success, negative on failure | |
8129 | */ | |
8130 | int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
8131 | { | |
8132 | struct i40e_pf *pf = vsi->back; | |
8133 | ||
8134 | if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) | |
8135 | return i40e_config_rss_aq(vsi, seed, lut, lut_size); | |
8136 | else | |
8137 | return i40e_config_rss_reg(vsi, seed, lut, lut_size); | |
8138 | } | |
8139 | ||
8140 | /** | |
8141 | * i40e_get_rss - Get RSS keys and lut | |
8142 | * @vsi: Pointer to VSI structure | |
8143 | * @seed: Buffer to store the keys | |
8144 | * @lut: Buffer to store the lookup table entries | |
8145 | * lut_size: Size of buffer to store the lookup table entries | |
8146 | * | |
8147 | * Returns 0 on success, negative on failure | |
8148 | */ | |
8149 | int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
8150 | { | |
95a73780 ASJ |
8151 | struct i40e_pf *pf = vsi->back; |
8152 | ||
8153 | if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) | |
8154 | return i40e_get_rss_aq(vsi, seed, lut, lut_size); | |
8155 | else | |
8156 | return i40e_get_rss_reg(vsi, seed, lut, lut_size); | |
043dd650 HZ |
8157 | } |
8158 | ||
e69ff813 HZ |
8159 | /** |
8160 | * i40e_fill_rss_lut - Fill the RSS lookup table with default values | |
8161 | * @pf: Pointer to board private structure | |
8162 | * @lut: Lookup table | |
8163 | * @rss_table_size: Lookup table size | |
8164 | * @rss_size: Range of queue number for hashing | |
8165 | */ | |
8166 | static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, | |
8167 | u16 rss_table_size, u16 rss_size) | |
8168 | { | |
8169 | u16 i; | |
8170 | ||
8171 | for (i = 0; i < rss_table_size; i++) | |
8172 | lut[i] = i % rss_size; | |
8173 | } | |
8174 | ||
e25d00b8 | 8175 | /** |
043dd650 | 8176 | * i40e_pf_config_rss - Prepare for RSS if used |
e25d00b8 ASJ |
8177 | * @pf: board private structure |
8178 | **/ | |
043dd650 | 8179 | static int i40e_pf_config_rss(struct i40e_pf *pf) |
e25d00b8 ASJ |
8180 | { |
8181 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
8182 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
e69ff813 | 8183 | u8 *lut; |
e25d00b8 ASJ |
8184 | struct i40e_hw *hw = &pf->hw; |
8185 | u32 reg_val; | |
8186 | u64 hena; | |
e69ff813 | 8187 | int ret; |
e25d00b8 | 8188 | |
41c445ff | 8189 | /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */ |
272cdaf2 SN |
8190 | hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) | |
8191 | ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32); | |
e25d00b8 ASJ |
8192 | hena |= i40e_pf_get_default_rss_hena(pf); |
8193 | ||
272cdaf2 SN |
8194 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena); |
8195 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); | |
41c445ff | 8196 | |
e25d00b8 | 8197 | /* Determine the RSS table size based on the hardware capabilities */ |
272cdaf2 | 8198 | reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); |
e25d00b8 ASJ |
8199 | reg_val = (pf->rss_table_size == 512) ? |
8200 | (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) : | |
8201 | (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512); | |
272cdaf2 | 8202 | i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val); |
e157ea30 | 8203 | |
28c5869f HZ |
8204 | /* Determine the RSS size of the VSI */ |
8205 | if (!vsi->rss_size) | |
acd65448 HZ |
8206 | vsi->rss_size = min_t(int, pf->alloc_rss_size, |
8207 | vsi->num_queue_pairs); | |
28c5869f | 8208 | |
e69ff813 HZ |
8209 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); |
8210 | if (!lut) | |
8211 | return -ENOMEM; | |
8212 | ||
28c5869f HZ |
8213 | /* Use user configured lut if there is one, otherwise use default */ |
8214 | if (vsi->rss_lut_user) | |
8215 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
8216 | else | |
8217 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
e69ff813 | 8218 | |
28c5869f HZ |
8219 | /* Use user configured hash key if there is one, otherwise |
8220 | * use default. | |
8221 | */ | |
8222 | if (vsi->rss_hkey_user) | |
8223 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
8224 | else | |
8225 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
043dd650 | 8226 | ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); |
e69ff813 HZ |
8227 | kfree(lut); |
8228 | ||
8229 | return ret; | |
41c445ff JB |
8230 | } |
8231 | ||
f8ff1464 ASJ |
8232 | /** |
8233 | * i40e_reconfig_rss_queues - change number of queues for rss and rebuild | |
8234 | * @pf: board private structure | |
8235 | * @queue_count: the requested queue count for rss. | |
8236 | * | |
8237 | * returns 0 if rss is not enabled, if enabled returns the final rss queue | |
8238 | * count which may be different from the requested queue count. | |
8239 | **/ | |
8240 | int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count) | |
8241 | { | |
9a3bd2f1 ASJ |
8242 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
8243 | int new_rss_size; | |
8244 | ||
f8ff1464 ASJ |
8245 | if (!(pf->flags & I40E_FLAG_RSS_ENABLED)) |
8246 | return 0; | |
8247 | ||
9a3bd2f1 | 8248 | new_rss_size = min_t(int, queue_count, pf->rss_size_max); |
f8ff1464 | 8249 | |
9a3bd2f1 ASJ |
8250 | if (queue_count != vsi->num_queue_pairs) { |
8251 | vsi->req_queue_pairs = queue_count; | |
f8ff1464 ASJ |
8252 | i40e_prep_for_reset(pf); |
8253 | ||
acd65448 | 8254 | pf->alloc_rss_size = new_rss_size; |
f8ff1464 ASJ |
8255 | |
8256 | i40e_reset_and_rebuild(pf, true); | |
28c5869f HZ |
8257 | |
8258 | /* Discard the user configured hash keys and lut, if less | |
8259 | * queues are enabled. | |
8260 | */ | |
8261 | if (queue_count < vsi->rss_size) { | |
8262 | i40e_clear_rss_config_user(vsi); | |
8263 | dev_dbg(&pf->pdev->dev, | |
8264 | "discard user configured hash keys and lut\n"); | |
8265 | } | |
8266 | ||
8267 | /* Reset vsi->rss_size, as number of enabled queues changed */ | |
acd65448 HZ |
8268 | vsi->rss_size = min_t(int, pf->alloc_rss_size, |
8269 | vsi->num_queue_pairs); | |
28c5869f | 8270 | |
043dd650 | 8271 | i40e_pf_config_rss(pf); |
f8ff1464 | 8272 | } |
e36b0b11 HZ |
8273 | dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n", |
8274 | pf->alloc_rss_size, pf->rss_size_max); | |
acd65448 | 8275 | return pf->alloc_rss_size; |
f8ff1464 ASJ |
8276 | } |
8277 | ||
f4492db1 GR |
8278 | /** |
8279 | * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition | |
8280 | * @pf: board private structure | |
8281 | **/ | |
8282 | i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf) | |
8283 | { | |
8284 | i40e_status status; | |
8285 | bool min_valid, max_valid; | |
8286 | u32 max_bw, min_bw; | |
8287 | ||
8288 | status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw, | |
8289 | &min_valid, &max_valid); | |
8290 | ||
8291 | if (!status) { | |
8292 | if (min_valid) | |
8293 | pf->npar_min_bw = min_bw; | |
8294 | if (max_valid) | |
8295 | pf->npar_max_bw = max_bw; | |
8296 | } | |
8297 | ||
8298 | return status; | |
8299 | } | |
8300 | ||
8301 | /** | |
8302 | * i40e_set_npar_bw_setting - Set BW settings for this PF partition | |
8303 | * @pf: board private structure | |
8304 | **/ | |
8305 | i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf) | |
8306 | { | |
8307 | struct i40e_aqc_configure_partition_bw_data bw_data; | |
8308 | i40e_status status; | |
8309 | ||
b40c82e6 | 8310 | /* Set the valid bit for this PF */ |
41a1d04b | 8311 | bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id)); |
f4492db1 GR |
8312 | bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK; |
8313 | bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK; | |
8314 | ||
8315 | /* Set the new bandwidths */ | |
8316 | status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL); | |
8317 | ||
8318 | return status; | |
8319 | } | |
8320 | ||
8321 | /** | |
8322 | * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition | |
8323 | * @pf: board private structure | |
8324 | **/ | |
8325 | i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf) | |
8326 | { | |
8327 | /* Commit temporary BW setting to permanent NVM image */ | |
8328 | enum i40e_admin_queue_err last_aq_status; | |
8329 | i40e_status ret; | |
8330 | u16 nvm_word; | |
8331 | ||
8332 | if (pf->hw.partition_id != 1) { | |
8333 | dev_info(&pf->pdev->dev, | |
8334 | "Commit BW only works on partition 1! This is partition %d", | |
8335 | pf->hw.partition_id); | |
8336 | ret = I40E_NOT_SUPPORTED; | |
8337 | goto bw_commit_out; | |
8338 | } | |
8339 | ||
8340 | /* Acquire NVM for read access */ | |
8341 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ); | |
8342 | last_aq_status = pf->hw.aq.asq_last_status; | |
8343 | if (ret) { | |
8344 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8345 | "Cannot acquire NVM for read access, err %s aq_err %s\n", |
8346 | i40e_stat_str(&pf->hw, ret), | |
8347 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8348 | goto bw_commit_out; |
8349 | } | |
8350 | ||
8351 | /* Read word 0x10 of NVM - SW compatibility word 1 */ | |
8352 | ret = i40e_aq_read_nvm(&pf->hw, | |
8353 | I40E_SR_NVM_CONTROL_WORD, | |
8354 | 0x10, sizeof(nvm_word), &nvm_word, | |
8355 | false, NULL); | |
8356 | /* Save off last admin queue command status before releasing | |
8357 | * the NVM | |
8358 | */ | |
8359 | last_aq_status = pf->hw.aq.asq_last_status; | |
8360 | i40e_release_nvm(&pf->hw); | |
8361 | if (ret) { | |
f1c7e72e SN |
8362 | dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n", |
8363 | i40e_stat_str(&pf->hw, ret), | |
8364 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8365 | goto bw_commit_out; |
8366 | } | |
8367 | ||
8368 | /* Wait a bit for NVM release to complete */ | |
8369 | msleep(50); | |
8370 | ||
8371 | /* Acquire NVM for write access */ | |
8372 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE); | |
8373 | last_aq_status = pf->hw.aq.asq_last_status; | |
8374 | if (ret) { | |
8375 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8376 | "Cannot acquire NVM for write access, err %s aq_err %s\n", |
8377 | i40e_stat_str(&pf->hw, ret), | |
8378 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8379 | goto bw_commit_out; |
8380 | } | |
8381 | /* Write it back out unchanged to initiate update NVM, | |
8382 | * which will force a write of the shadow (alt) RAM to | |
8383 | * the NVM - thus storing the bandwidth values permanently. | |
8384 | */ | |
8385 | ret = i40e_aq_update_nvm(&pf->hw, | |
8386 | I40E_SR_NVM_CONTROL_WORD, | |
8387 | 0x10, sizeof(nvm_word), | |
8388 | &nvm_word, true, NULL); | |
8389 | /* Save off last admin queue command status before releasing | |
8390 | * the NVM | |
8391 | */ | |
8392 | last_aq_status = pf->hw.aq.asq_last_status; | |
8393 | i40e_release_nvm(&pf->hw); | |
8394 | if (ret) | |
8395 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8396 | "BW settings NOT SAVED, err %s aq_err %s\n", |
8397 | i40e_stat_str(&pf->hw, ret), | |
8398 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8399 | bw_commit_out: |
8400 | ||
8401 | return ret; | |
8402 | } | |
8403 | ||
41c445ff JB |
8404 | /** |
8405 | * i40e_sw_init - Initialize general software structures (struct i40e_pf) | |
8406 | * @pf: board private structure to initialize | |
8407 | * | |
8408 | * i40e_sw_init initializes the Adapter private data structure. | |
8409 | * Fields are initialized based on PCI device information and | |
8410 | * OS network device settings (MTU size). | |
8411 | **/ | |
8412 | static int i40e_sw_init(struct i40e_pf *pf) | |
8413 | { | |
8414 | int err = 0; | |
8415 | int size; | |
8416 | ||
8417 | pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE, | |
8418 | (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)); | |
8419 | if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) { | |
8420 | if (I40E_DEBUG_USER & debug) | |
8421 | pf->hw.debug_mask = debug; | |
8422 | pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER), | |
8423 | I40E_DEFAULT_MSG_ENABLE); | |
8424 | } | |
8425 | ||
8426 | /* Set default capability flags */ | |
8427 | pf->flags = I40E_FLAG_RX_CSUM_ENABLED | | |
8428 | I40E_FLAG_MSI_ENABLED | | |
2bc7ee8a MW |
8429 | I40E_FLAG_MSIX_ENABLED; |
8430 | ||
ca99eb99 MW |
8431 | /* Set default ITR */ |
8432 | pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF; | |
8433 | pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF; | |
8434 | ||
7134f9ce JB |
8435 | /* Depending on PF configurations, it is possible that the RSS |
8436 | * maximum might end up larger than the available queues | |
8437 | */ | |
41a1d04b | 8438 | pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width); |
acd65448 | 8439 | pf->alloc_rss_size = 1; |
5db4cb59 | 8440 | pf->rss_table_size = pf->hw.func_caps.rss_table_size; |
7134f9ce JB |
8441 | pf->rss_size_max = min_t(int, pf->rss_size_max, |
8442 | pf->hw.func_caps.num_tx_qp); | |
41c445ff JB |
8443 | if (pf->hw.func_caps.rss) { |
8444 | pf->flags |= I40E_FLAG_RSS_ENABLED; | |
acd65448 HZ |
8445 | pf->alloc_rss_size = min_t(int, pf->rss_size_max, |
8446 | num_online_cpus()); | |
41c445ff JB |
8447 | } |
8448 | ||
2050bc65 | 8449 | /* MFP mode enabled */ |
c78b953e | 8450 | if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) { |
2050bc65 CS |
8451 | pf->flags |= I40E_FLAG_MFP_ENABLED; |
8452 | dev_info(&pf->pdev->dev, "MFP mode Enabled\n"); | |
f4492db1 GR |
8453 | if (i40e_get_npar_bw_setting(pf)) |
8454 | dev_warn(&pf->pdev->dev, | |
8455 | "Could not get NPAR bw settings\n"); | |
8456 | else | |
8457 | dev_info(&pf->pdev->dev, | |
8458 | "Min BW = %8.8x, Max BW = %8.8x\n", | |
8459 | pf->npar_min_bw, pf->npar_max_bw); | |
2050bc65 CS |
8460 | } |
8461 | ||
cbf61325 ASJ |
8462 | /* FW/NVM is not yet fixed in this regard */ |
8463 | if ((pf->hw.func_caps.fd_filters_guaranteed > 0) || | |
8464 | (pf->hw.func_caps.fd_filters_best_effort > 0)) { | |
8465 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
8466 | pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE; | |
6eae9c6a SN |
8467 | if (pf->flags & I40E_FLAG_MFP_ENABLED && |
8468 | pf->hw.num_partitions > 1) | |
cbf61325 | 8469 | dev_info(&pf->pdev->dev, |
0b67584f | 8470 | "Flow Director Sideband mode Disabled in MFP mode\n"); |
6eae9c6a SN |
8471 | else |
8472 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
cbf61325 ASJ |
8473 | pf->fdir_pf_filter_count = |
8474 | pf->hw.func_caps.fd_filters_guaranteed; | |
8475 | pf->hw.fdir_shared_filter_count = | |
8476 | pf->hw.func_caps.fd_filters_best_effort; | |
41c445ff JB |
8477 | } |
8478 | ||
f1bbad33 | 8479 | if (i40e_is_mac_710(&pf->hw) && |
8eed76fa | 8480 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) || |
f1bbad33 | 8481 | (pf->hw.aq.fw_maj_ver < 4))) { |
8eed76fa | 8482 | pf->flags |= I40E_FLAG_RESTART_AUTONEG; |
f1bbad33 NP |
8483 | /* No DCB support for FW < v4.33 */ |
8484 | pf->flags |= I40E_FLAG_NO_DCB_SUPPORT; | |
8485 | } | |
8486 | ||
8487 | /* Disable FW LLDP if FW < v4.3 */ | |
8488 | if (i40e_is_mac_710(&pf->hw) && | |
8489 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) || | |
8490 | (pf->hw.aq.fw_maj_ver < 4))) | |
8491 | pf->flags |= I40E_FLAG_STOP_FW_LLDP; | |
8492 | ||
8493 | /* Use the FW Set LLDP MIB API if FW > v4.40 */ | |
8494 | if (i40e_is_mac_710(&pf->hw) && | |
8495 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) || | |
8496 | (pf->hw.aq.fw_maj_ver >= 5))) | |
8497 | pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB; | |
8eed76fa | 8498 | |
41c445ff | 8499 | if (pf->hw.func_caps.vmdq) { |
41c445ff | 8500 | pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI; |
e25d00b8 | 8501 | pf->flags |= I40E_FLAG_VMDQ_ENABLED; |
e9e53662 | 8502 | pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf); |
41c445ff JB |
8503 | } |
8504 | ||
e3219ce6 ASJ |
8505 | if (pf->hw.func_caps.iwarp) { |
8506 | pf->flags |= I40E_FLAG_IWARP_ENABLED; | |
8507 | /* IWARP needs one extra vector for CQP just like MISC.*/ | |
8508 | pf->num_iwarp_msix = (int)num_online_cpus() + 1; | |
8509 | } | |
8510 | ||
38e00438 | 8511 | #ifdef I40E_FCOE |
21364bcf | 8512 | i40e_init_pf_fcoe(pf); |
38e00438 VD |
8513 | |
8514 | #endif /* I40E_FCOE */ | |
41c445ff | 8515 | #ifdef CONFIG_PCI_IOV |
ba252f13 | 8516 | if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) { |
41c445ff JB |
8517 | pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF; |
8518 | pf->flags |= I40E_FLAG_SRIOV_ENABLED; | |
8519 | pf->num_req_vfs = min_t(int, | |
8520 | pf->hw.func_caps.num_vfs, | |
8521 | I40E_MAX_VF_COUNT); | |
8522 | } | |
8523 | #endif /* CONFIG_PCI_IOV */ | |
d502ce01 ASJ |
8524 | if (pf->hw.mac.type == I40E_MAC_X722) { |
8525 | pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE | | |
8526 | I40E_FLAG_128_QP_RSS_CAPABLE | | |
8527 | I40E_FLAG_HW_ATR_EVICT_CAPABLE | | |
8528 | I40E_FLAG_OUTER_UDP_CSUM_CAPABLE | | |
8529 | I40E_FLAG_WB_ON_ITR_CAPABLE | | |
6a899024 | 8530 | I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE | |
8e2cc0e6 | 8531 | I40E_FLAG_NO_PCI_LINK_CHECK | |
f8db54cc | 8532 | I40E_FLAG_100M_SGMII_CAPABLE | |
f1bbad33 | 8533 | I40E_FLAG_USE_SET_LLDP_MIB | |
6a899024 | 8534 | I40E_FLAG_GENEVE_OFFLOAD_CAPABLE; |
a340c789 AS |
8535 | } else if ((pf->hw.aq.api_maj_ver > 1) || |
8536 | ((pf->hw.aq.api_maj_ver == 1) && | |
8537 | (pf->hw.aq.api_min_ver > 4))) { | |
8538 | /* Supported in FW API version higher than 1.4 */ | |
8539 | pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE; | |
72b74869 ASJ |
8540 | pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE; |
8541 | } else { | |
8542 | pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE; | |
d502ce01 | 8543 | } |
a340c789 | 8544 | |
41c445ff JB |
8545 | pf->eeprom_version = 0xDEAD; |
8546 | pf->lan_veb = I40E_NO_VEB; | |
8547 | pf->lan_vsi = I40E_NO_VSI; | |
8548 | ||
d1a8d275 ASJ |
8549 | /* By default FW has this off for performance reasons */ |
8550 | pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED; | |
8551 | ||
41c445ff JB |
8552 | /* set up queue assignment tracking */ |
8553 | size = sizeof(struct i40e_lump_tracking) | |
8554 | + (sizeof(u16) * pf->hw.func_caps.num_tx_qp); | |
8555 | pf->qp_pile = kzalloc(size, GFP_KERNEL); | |
8556 | if (!pf->qp_pile) { | |
8557 | err = -ENOMEM; | |
8558 | goto sw_init_done; | |
8559 | } | |
8560 | pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp; | |
8561 | pf->qp_pile->search_hint = 0; | |
8562 | ||
327fe04b ASJ |
8563 | pf->tx_timeout_recovery_level = 1; |
8564 | ||
41c445ff JB |
8565 | mutex_init(&pf->switch_mutex); |
8566 | ||
c668a12c GR |
8567 | /* If NPAR is enabled nudge the Tx scheduler */ |
8568 | if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf))) | |
8569 | i40e_set_npar_bw_setting(pf); | |
8570 | ||
41c445ff JB |
8571 | sw_init_done: |
8572 | return err; | |
8573 | } | |
8574 | ||
7c3c288b ASJ |
8575 | /** |
8576 | * i40e_set_ntuple - set the ntuple feature flag and take action | |
8577 | * @pf: board private structure to initialize | |
8578 | * @features: the feature set that the stack is suggesting | |
8579 | * | |
8580 | * returns a bool to indicate if reset needs to happen | |
8581 | **/ | |
8582 | bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features) | |
8583 | { | |
8584 | bool need_reset = false; | |
8585 | ||
8586 | /* Check if Flow Director n-tuple support was enabled or disabled. If | |
8587 | * the state changed, we need to reset. | |
8588 | */ | |
8589 | if (features & NETIF_F_NTUPLE) { | |
8590 | /* Enable filters and mark for reset */ | |
8591 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) | |
8592 | need_reset = true; | |
a70e407f TD |
8593 | /* enable FD_SB only if there is MSI-X vector */ |
8594 | if (pf->num_fdsb_msix > 0) | |
8595 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
7c3c288b ASJ |
8596 | } else { |
8597 | /* turn off filters, mark for reset and clear SW filter list */ | |
8598 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
8599 | need_reset = true; | |
8600 | i40e_fdir_filter_exit(pf); | |
8601 | } | |
8602 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
8a4f34fb | 8603 | pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED; |
1e1be8f6 ASJ |
8604 | /* reset fd counters */ |
8605 | pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0; | |
8606 | pf->fdir_pf_active_filters = 0; | |
8607 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
2e4875e3 ASJ |
8608 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
8609 | dev_info(&pf->pdev->dev, "ATR re-enabled.\n"); | |
8a4f34fb ASJ |
8610 | /* if ATR was auto disabled it can be re-enabled. */ |
8611 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && | |
8612 | (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) | |
8613 | pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED; | |
7c3c288b ASJ |
8614 | } |
8615 | return need_reset; | |
8616 | } | |
8617 | ||
41c445ff JB |
8618 | /** |
8619 | * i40e_set_features - set the netdev feature flags | |
8620 | * @netdev: ptr to the netdev being adjusted | |
8621 | * @features: the feature set that the stack is suggesting | |
8622 | **/ | |
8623 | static int i40e_set_features(struct net_device *netdev, | |
8624 | netdev_features_t features) | |
8625 | { | |
8626 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
8627 | struct i40e_vsi *vsi = np->vsi; | |
7c3c288b ASJ |
8628 | struct i40e_pf *pf = vsi->back; |
8629 | bool need_reset; | |
41c445ff JB |
8630 | |
8631 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
8632 | i40e_vlan_stripping_enable(vsi); | |
8633 | else | |
8634 | i40e_vlan_stripping_disable(vsi); | |
8635 | ||
7c3c288b ASJ |
8636 | need_reset = i40e_set_ntuple(pf, features); |
8637 | ||
8638 | if (need_reset) | |
41a1d04b | 8639 | i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); |
7c3c288b | 8640 | |
41c445ff JB |
8641 | return 0; |
8642 | } | |
8643 | ||
a1c9a9d9 | 8644 | /** |
6a899024 | 8645 | * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port |
a1c9a9d9 JK |
8646 | * @pf: board private structure |
8647 | * @port: The UDP port to look up | |
8648 | * | |
8649 | * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found | |
8650 | **/ | |
6a899024 | 8651 | static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port) |
a1c9a9d9 JK |
8652 | { |
8653 | u8 i; | |
8654 | ||
8655 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
6a899024 | 8656 | if (pf->udp_ports[i].index == port) |
a1c9a9d9 JK |
8657 | return i; |
8658 | } | |
8659 | ||
8660 | return i; | |
8661 | } | |
8662 | ||
8663 | /** | |
06a5f7f1 | 8664 | * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up |
a1c9a9d9 | 8665 | * @netdev: This physical port's netdev |
06a5f7f1 | 8666 | * @ti: Tunnel endpoint information |
a1c9a9d9 | 8667 | **/ |
06a5f7f1 AD |
8668 | static void i40e_udp_tunnel_add(struct net_device *netdev, |
8669 | struct udp_tunnel_info *ti) | |
a1c9a9d9 JK |
8670 | { |
8671 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
8672 | struct i40e_vsi *vsi = np->vsi; | |
8673 | struct i40e_pf *pf = vsi->back; | |
06a5f7f1 | 8674 | __be16 port = ti->port; |
a1c9a9d9 JK |
8675 | u8 next_idx; |
8676 | u8 idx; | |
8677 | ||
6a899024 | 8678 | idx = i40e_get_udp_port_idx(pf, port); |
a1c9a9d9 JK |
8679 | |
8680 | /* Check if port already exists */ | |
8681 | if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
06a5f7f1 | 8682 | netdev_info(netdev, "port %d already offloaded\n", |
c22c06c8 | 8683 | ntohs(port)); |
a1c9a9d9 JK |
8684 | return; |
8685 | } | |
8686 | ||
8687 | /* Now check if there is space to add the new port */ | |
6a899024 | 8688 | next_idx = i40e_get_udp_port_idx(pf, 0); |
a1c9a9d9 JK |
8689 | |
8690 | if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
06a5f7f1 | 8691 | netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n", |
6a899024 SA |
8692 | ntohs(port)); |
8693 | return; | |
8694 | } | |
8695 | ||
06a5f7f1 AD |
8696 | switch (ti->type) { |
8697 | case UDP_TUNNEL_TYPE_VXLAN: | |
8698 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN; | |
8699 | break; | |
8700 | case UDP_TUNNEL_TYPE_GENEVE: | |
8701 | if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE)) | |
8702 | return; | |
8703 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE; | |
8704 | break; | |
8705 | default: | |
6a899024 SA |
8706 | return; |
8707 | } | |
8708 | ||
8709 | /* New port: add it and mark its index in the bitmap */ | |
8710 | pf->udp_ports[next_idx].index = port; | |
6a899024 SA |
8711 | pf->pending_udp_bitmap |= BIT_ULL(next_idx); |
8712 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
a1c9a9d9 JK |
8713 | } |
8714 | ||
6a899024 | 8715 | /** |
06a5f7f1 | 8716 | * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away |
6a899024 | 8717 | * @netdev: This physical port's netdev |
06a5f7f1 | 8718 | * @ti: Tunnel endpoint information |
6a899024 | 8719 | **/ |
06a5f7f1 AD |
8720 | static void i40e_udp_tunnel_del(struct net_device *netdev, |
8721 | struct udp_tunnel_info *ti) | |
6a899024 | 8722 | { |
6a899024 SA |
8723 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
8724 | struct i40e_vsi *vsi = np->vsi; | |
8725 | struct i40e_pf *pf = vsi->back; | |
06a5f7f1 | 8726 | __be16 port = ti->port; |
6a899024 SA |
8727 | u8 idx; |
8728 | ||
6a899024 SA |
8729 | idx = i40e_get_udp_port_idx(pf, port); |
8730 | ||
8731 | /* Check if port already exists */ | |
06a5f7f1 AD |
8732 | if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS) |
8733 | goto not_found; | |
6a899024 | 8734 | |
06a5f7f1 AD |
8735 | switch (ti->type) { |
8736 | case UDP_TUNNEL_TYPE_VXLAN: | |
8737 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN) | |
8738 | goto not_found; | |
8739 | break; | |
8740 | case UDP_TUNNEL_TYPE_GENEVE: | |
8741 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE) | |
8742 | goto not_found; | |
8743 | break; | |
8744 | default: | |
8745 | goto not_found; | |
6a899024 | 8746 | } |
06a5f7f1 AD |
8747 | |
8748 | /* if port exists, set it to 0 (mark for deletion) | |
8749 | * and make it pending | |
8750 | */ | |
8751 | pf->udp_ports[idx].index = 0; | |
8752 | pf->pending_udp_bitmap |= BIT_ULL(idx); | |
8753 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
8754 | ||
8755 | return; | |
8756 | not_found: | |
8757 | netdev_warn(netdev, "UDP port %d was not found, not deleting\n", | |
8758 | ntohs(port)); | |
6a899024 SA |
8759 | } |
8760 | ||
1f224ad2 | 8761 | static int i40e_get_phys_port_id(struct net_device *netdev, |
02637fce | 8762 | struct netdev_phys_item_id *ppid) |
1f224ad2 NP |
8763 | { |
8764 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
8765 | struct i40e_pf *pf = np->vsi->back; | |
8766 | struct i40e_hw *hw = &pf->hw; | |
8767 | ||
8768 | if (!(pf->flags & I40E_FLAG_PORT_ID_VALID)) | |
8769 | return -EOPNOTSUPP; | |
8770 | ||
8771 | ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id)); | |
8772 | memcpy(ppid->id, hw->mac.port_addr, ppid->id_len); | |
8773 | ||
8774 | return 0; | |
8775 | } | |
8776 | ||
2f90ade6 JB |
8777 | /** |
8778 | * i40e_ndo_fdb_add - add an entry to the hardware database | |
8779 | * @ndm: the input from the stack | |
8780 | * @tb: pointer to array of nladdr (unused) | |
8781 | * @dev: the net device pointer | |
8782 | * @addr: the MAC address entry being added | |
8783 | * @flags: instructions from stack about fdb operation | |
8784 | */ | |
4ba0dea5 GR |
8785 | static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
8786 | struct net_device *dev, | |
f6f6424b | 8787 | const unsigned char *addr, u16 vid, |
4ba0dea5 | 8788 | u16 flags) |
4ba0dea5 GR |
8789 | { |
8790 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
8791 | struct i40e_pf *pf = np->vsi->back; | |
8792 | int err = 0; | |
8793 | ||
8794 | if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED)) | |
8795 | return -EOPNOTSUPP; | |
8796 | ||
65891fea OG |
8797 | if (vid) { |
8798 | pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name); | |
8799 | return -EINVAL; | |
8800 | } | |
8801 | ||
4ba0dea5 GR |
8802 | /* Hardware does not support aging addresses so if a |
8803 | * ndm_state is given only allow permanent addresses | |
8804 | */ | |
8805 | if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) { | |
8806 | netdev_info(dev, "FDB only supports static addresses\n"); | |
8807 | return -EINVAL; | |
8808 | } | |
8809 | ||
8810 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) | |
8811 | err = dev_uc_add_excl(dev, addr); | |
8812 | else if (is_multicast_ether_addr(addr)) | |
8813 | err = dev_mc_add_excl(dev, addr); | |
8814 | else | |
8815 | err = -EINVAL; | |
8816 | ||
8817 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
8818 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
8819 | err = 0; | |
8820 | ||
8821 | return err; | |
8822 | } | |
8823 | ||
51616018 NP |
8824 | /** |
8825 | * i40e_ndo_bridge_setlink - Set the hardware bridge mode | |
8826 | * @dev: the netdev being configured | |
8827 | * @nlh: RTNL message | |
8828 | * | |
8829 | * Inserts a new hardware bridge if not already created and | |
8830 | * enables the bridging mode requested (VEB or VEPA). If the | |
8831 | * hardware bridge has already been inserted and the request | |
8832 | * is to change the mode then that requires a PF reset to | |
8833 | * allow rebuild of the components with required hardware | |
8834 | * bridge mode enabled. | |
8835 | **/ | |
8836 | static int i40e_ndo_bridge_setlink(struct net_device *dev, | |
9df70b66 CW |
8837 | struct nlmsghdr *nlh, |
8838 | u16 flags) | |
51616018 NP |
8839 | { |
8840 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
8841 | struct i40e_vsi *vsi = np->vsi; | |
8842 | struct i40e_pf *pf = vsi->back; | |
8843 | struct i40e_veb *veb = NULL; | |
8844 | struct nlattr *attr, *br_spec; | |
8845 | int i, rem; | |
8846 | ||
8847 | /* Only for PF VSI for now */ | |
8848 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
8849 | return -EOPNOTSUPP; | |
8850 | ||
8851 | /* Find the HW bridge for PF VSI */ | |
8852 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
8853 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
8854 | veb = pf->veb[i]; | |
8855 | } | |
8856 | ||
8857 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
8858 | ||
8859 | nla_for_each_nested(attr, br_spec, rem) { | |
8860 | __u16 mode; | |
8861 | ||
8862 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
8863 | continue; | |
8864 | ||
8865 | mode = nla_get_u16(attr); | |
8866 | if ((mode != BRIDGE_MODE_VEPA) && | |
8867 | (mode != BRIDGE_MODE_VEB)) | |
8868 | return -EINVAL; | |
8869 | ||
8870 | /* Insert a new HW bridge */ | |
8871 | if (!veb) { | |
8872 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
8873 | vsi->tc_config.enabled_tc); | |
8874 | if (veb) { | |
8875 | veb->bridge_mode = mode; | |
8876 | i40e_config_bridge_mode(veb); | |
8877 | } else { | |
8878 | /* No Bridge HW offload available */ | |
8879 | return -ENOENT; | |
8880 | } | |
8881 | break; | |
8882 | } else if (mode != veb->bridge_mode) { | |
8883 | /* Existing HW bridge but different mode needs reset */ | |
8884 | veb->bridge_mode = mode; | |
fc60861e ASJ |
8885 | /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */ |
8886 | if (mode == BRIDGE_MODE_VEB) | |
8887 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
8888 | else | |
8889 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
8890 | i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); | |
51616018 NP |
8891 | break; |
8892 | } | |
8893 | } | |
8894 | ||
8895 | return 0; | |
8896 | } | |
8897 | ||
8898 | /** | |
8899 | * i40e_ndo_bridge_getlink - Get the hardware bridge mode | |
8900 | * @skb: skb buff | |
8901 | * @pid: process id | |
8902 | * @seq: RTNL message seq # | |
8903 | * @dev: the netdev being configured | |
8904 | * @filter_mask: unused | |
d4b2f9fe | 8905 | * @nlflags: netlink flags passed in |
51616018 NP |
8906 | * |
8907 | * Return the mode in which the hardware bridge is operating in | |
8908 | * i.e VEB or VEPA. | |
8909 | **/ | |
51616018 NP |
8910 | static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
8911 | struct net_device *dev, | |
9f4ffc44 CW |
8912 | u32 __always_unused filter_mask, |
8913 | int nlflags) | |
51616018 NP |
8914 | { |
8915 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
8916 | struct i40e_vsi *vsi = np->vsi; | |
8917 | struct i40e_pf *pf = vsi->back; | |
8918 | struct i40e_veb *veb = NULL; | |
8919 | int i; | |
8920 | ||
8921 | /* Only for PF VSI for now */ | |
8922 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
8923 | return -EOPNOTSUPP; | |
8924 | ||
8925 | /* Find the HW bridge for the PF VSI */ | |
8926 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
8927 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
8928 | veb = pf->veb[i]; | |
8929 | } | |
8930 | ||
8931 | if (!veb) | |
8932 | return 0; | |
8933 | ||
46c264da | 8934 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode, |
7d4f8d87 | 8935 | nlflags, 0, 0, filter_mask, NULL); |
51616018 | 8936 | } |
51616018 | 8937 | |
6a899024 SA |
8938 | /* Hardware supports L4 tunnel length of 128B (=2^7) which includes |
8939 | * inner mac plus all inner ethertypes. | |
8940 | */ | |
8941 | #define I40E_MAX_TUNNEL_HDR_LEN 128 | |
f44a75e2 JS |
8942 | /** |
8943 | * i40e_features_check - Validate encapsulated packet conforms to limits | |
8944 | * @skb: skb buff | |
2bc11c63 | 8945 | * @dev: This physical port's netdev |
f44a75e2 JS |
8946 | * @features: Offload features that the stack believes apply |
8947 | **/ | |
8948 | static netdev_features_t i40e_features_check(struct sk_buff *skb, | |
8949 | struct net_device *dev, | |
8950 | netdev_features_t features) | |
8951 | { | |
8952 | if (skb->encapsulation && | |
6a899024 | 8953 | ((skb_inner_network_header(skb) - skb_transport_header(skb)) > |
f44a75e2 | 8954 | I40E_MAX_TUNNEL_HDR_LEN)) |
a188222b | 8955 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); |
f44a75e2 JS |
8956 | |
8957 | return features; | |
8958 | } | |
8959 | ||
37a2973a | 8960 | static const struct net_device_ops i40e_netdev_ops = { |
41c445ff JB |
8961 | .ndo_open = i40e_open, |
8962 | .ndo_stop = i40e_close, | |
8963 | .ndo_start_xmit = i40e_lan_xmit_frame, | |
8964 | .ndo_get_stats64 = i40e_get_netdev_stats_struct, | |
8965 | .ndo_set_rx_mode = i40e_set_rx_mode, | |
8966 | .ndo_validate_addr = eth_validate_addr, | |
8967 | .ndo_set_mac_address = i40e_set_mac, | |
8968 | .ndo_change_mtu = i40e_change_mtu, | |
beb0dff1 | 8969 | .ndo_do_ioctl = i40e_ioctl, |
41c445ff JB |
8970 | .ndo_tx_timeout = i40e_tx_timeout, |
8971 | .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid, | |
8972 | .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid, | |
8973 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
8974 | .ndo_poll_controller = i40e_netpoll, | |
8975 | #endif | |
e4c6734e | 8976 | .ndo_setup_tc = __i40e_setup_tc, |
38e00438 VD |
8977 | #ifdef I40E_FCOE |
8978 | .ndo_fcoe_enable = i40e_fcoe_enable, | |
8979 | .ndo_fcoe_disable = i40e_fcoe_disable, | |
8980 | #endif | |
41c445ff JB |
8981 | .ndo_set_features = i40e_set_features, |
8982 | .ndo_set_vf_mac = i40e_ndo_set_vf_mac, | |
8983 | .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan, | |
ed616689 | 8984 | .ndo_set_vf_rate = i40e_ndo_set_vf_bw, |
41c445ff | 8985 | .ndo_get_vf_config = i40e_ndo_get_vf_config, |
588aefa0 | 8986 | .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state, |
e6d9004d | 8987 | .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk, |
c3bbbd20 | 8988 | .ndo_set_vf_trust = i40e_ndo_set_vf_trust, |
06a5f7f1 AD |
8989 | .ndo_udp_tunnel_add = i40e_udp_tunnel_add, |
8990 | .ndo_udp_tunnel_del = i40e_udp_tunnel_del, | |
1f224ad2 | 8991 | .ndo_get_phys_port_id = i40e_get_phys_port_id, |
4ba0dea5 | 8992 | .ndo_fdb_add = i40e_ndo_fdb_add, |
f44a75e2 | 8993 | .ndo_features_check = i40e_features_check, |
51616018 NP |
8994 | .ndo_bridge_getlink = i40e_ndo_bridge_getlink, |
8995 | .ndo_bridge_setlink = i40e_ndo_bridge_setlink, | |
41c445ff JB |
8996 | }; |
8997 | ||
8998 | /** | |
8999 | * i40e_config_netdev - Setup the netdev flags | |
9000 | * @vsi: the VSI being configured | |
9001 | * | |
9002 | * Returns 0 on success, negative value on failure | |
9003 | **/ | |
9004 | static int i40e_config_netdev(struct i40e_vsi *vsi) | |
9005 | { | |
9006 | struct i40e_pf *pf = vsi->back; | |
9007 | struct i40e_hw *hw = &pf->hw; | |
9008 | struct i40e_netdev_priv *np; | |
9009 | struct net_device *netdev; | |
9010 | u8 mac_addr[ETH_ALEN]; | |
9011 | int etherdev_size; | |
9012 | ||
9013 | etherdev_size = sizeof(struct i40e_netdev_priv); | |
f8ff1464 | 9014 | netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs); |
41c445ff JB |
9015 | if (!netdev) |
9016 | return -ENOMEM; | |
9017 | ||
9018 | vsi->netdev = netdev; | |
9019 | np = netdev_priv(netdev); | |
9020 | np->vsi = vsi; | |
9021 | ||
b0fe3306 AD |
9022 | netdev->hw_enc_features |= NETIF_F_SG | |
9023 | NETIF_F_IP_CSUM | | |
9024 | NETIF_F_IPV6_CSUM | | |
9025 | NETIF_F_HIGHDMA | | |
9026 | NETIF_F_SOFT_FEATURES | | |
9027 | NETIF_F_TSO | | |
9028 | NETIF_F_TSO_ECN | | |
9029 | NETIF_F_TSO6 | | |
9030 | NETIF_F_GSO_GRE | | |
1c7b4a23 | 9031 | NETIF_F_GSO_GRE_CSUM | |
7e13318d | 9032 | NETIF_F_GSO_IPXIP4 | |
bf2d1df3 | 9033 | NETIF_F_GSO_IPXIP6 | |
b0fe3306 AD |
9034 | NETIF_F_GSO_UDP_TUNNEL | |
9035 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
1c7b4a23 | 9036 | NETIF_F_GSO_PARTIAL | |
b0fe3306 AD |
9037 | NETIF_F_SCTP_CRC | |
9038 | NETIF_F_RXHASH | | |
9039 | NETIF_F_RXCSUM | | |
5afdaaa0 | 9040 | 0; |
41c445ff | 9041 | |
b0fe3306 | 9042 | if (!(pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)) |
1c7b4a23 AD |
9043 | netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; |
9044 | ||
9045 | netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; | |
b0fe3306 AD |
9046 | |
9047 | /* record features VLANs can make use of */ | |
1c7b4a23 AD |
9048 | netdev->vlan_features |= netdev->hw_enc_features | |
9049 | NETIF_F_TSO_MANGLEID; | |
41c445ff | 9050 | |
2e86a0b6 | 9051 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
b0fe3306 AD |
9052 | netdev->hw_features |= NETIF_F_NTUPLE; |
9053 | ||
9054 | netdev->hw_features |= netdev->hw_enc_features | | |
9055 | NETIF_F_HW_VLAN_CTAG_TX | | |
9056 | NETIF_F_HW_VLAN_CTAG_RX; | |
2e86a0b6 | 9057 | |
b0fe3306 | 9058 | netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; |
1c7b4a23 | 9059 | netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; |
41c445ff JB |
9060 | |
9061 | if (vsi->type == I40E_VSI_MAIN) { | |
9062 | SET_NETDEV_DEV(netdev, &pf->pdev->dev); | |
9a173901 | 9063 | ether_addr_copy(mac_addr, hw->mac.perm_addr); |
30650cc5 SN |
9064 | /* The following steps are necessary to prevent reception |
9065 | * of tagged packets - some older NVM configurations load a | |
9066 | * default a MAC-VLAN filter that accepts any tagged packet | |
9067 | * which must be replaced by a normal filter. | |
8c27d42e | 9068 | */ |
c3c7ea27 MW |
9069 | i40e_rm_default_mac_filter(vsi, mac_addr); |
9070 | spin_lock_bh(&vsi->mac_filter_list_lock); | |
9071 | i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, true); | |
9072 | spin_unlock_bh(&vsi->mac_filter_list_lock); | |
41c445ff JB |
9073 | } else { |
9074 | /* relate the VSI_VMDQ name to the VSI_MAIN name */ | |
9075 | snprintf(netdev->name, IFNAMSIZ, "%sv%%d", | |
9076 | pf->vsi[pf->lan_vsi]->netdev->name); | |
9077 | random_ether_addr(mac_addr); | |
21659035 KP |
9078 | |
9079 | spin_lock_bh(&vsi->mac_filter_list_lock); | |
41c445ff | 9080 | i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false); |
21659035 | 9081 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
41c445ff | 9082 | } |
21659035 | 9083 | |
9a173901 GR |
9084 | ether_addr_copy(netdev->dev_addr, mac_addr); |
9085 | ether_addr_copy(netdev->perm_addr, mac_addr); | |
b0fe3306 | 9086 | |
41c445ff JB |
9087 | netdev->priv_flags |= IFF_UNICAST_FLT; |
9088 | netdev->priv_flags |= IFF_SUPP_NOFCS; | |
9089 | /* Setup netdev TC information */ | |
9090 | i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc); | |
9091 | ||
9092 | netdev->netdev_ops = &i40e_netdev_ops; | |
9093 | netdev->watchdog_timeo = 5 * HZ; | |
9094 | i40e_set_ethtool_ops(netdev); | |
38e00438 VD |
9095 | #ifdef I40E_FCOE |
9096 | i40e_fcoe_config_netdev(netdev, vsi); | |
9097 | #endif | |
41c445ff JB |
9098 | |
9099 | return 0; | |
9100 | } | |
9101 | ||
9102 | /** | |
9103 | * i40e_vsi_delete - Delete a VSI from the switch | |
9104 | * @vsi: the VSI being removed | |
9105 | * | |
9106 | * Returns 0 on success, negative value on failure | |
9107 | **/ | |
9108 | static void i40e_vsi_delete(struct i40e_vsi *vsi) | |
9109 | { | |
9110 | /* remove default VSI is not allowed */ | |
9111 | if (vsi == vsi->back->vsi[vsi->back->lan_vsi]) | |
9112 | return; | |
9113 | ||
41c445ff | 9114 | i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL); |
41c445ff JB |
9115 | } |
9116 | ||
51616018 NP |
9117 | /** |
9118 | * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB | |
9119 | * @vsi: the VSI being queried | |
9120 | * | |
9121 | * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode | |
9122 | **/ | |
9123 | int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi) | |
9124 | { | |
9125 | struct i40e_veb *veb; | |
9126 | struct i40e_pf *pf = vsi->back; | |
9127 | ||
9128 | /* Uplink is not a bridge so default to VEB */ | |
9129 | if (vsi->veb_idx == I40E_NO_VEB) | |
9130 | return 1; | |
9131 | ||
9132 | veb = pf->veb[vsi->veb_idx]; | |
09603eaa AA |
9133 | if (!veb) { |
9134 | dev_info(&pf->pdev->dev, | |
9135 | "There is no veb associated with the bridge\n"); | |
9136 | return -ENOENT; | |
9137 | } | |
9138 | ||
51616018 | 9139 | /* Uplink is a bridge in VEPA mode */ |
09603eaa | 9140 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) { |
51616018 | 9141 | return 0; |
09603eaa AA |
9142 | } else { |
9143 | /* Uplink is a bridge in VEB mode */ | |
9144 | return 1; | |
9145 | } | |
51616018 | 9146 | |
09603eaa AA |
9147 | /* VEPA is now default bridge, so return 0 */ |
9148 | return 0; | |
51616018 NP |
9149 | } |
9150 | ||
41c445ff JB |
9151 | /** |
9152 | * i40e_add_vsi - Add a VSI to the switch | |
9153 | * @vsi: the VSI being configured | |
9154 | * | |
9155 | * This initializes a VSI context depending on the VSI type to be added and | |
9156 | * passes it down to the add_vsi aq command. | |
9157 | **/ | |
9158 | static int i40e_add_vsi(struct i40e_vsi *vsi) | |
9159 | { | |
9160 | int ret = -ENODEV; | |
41c445ff JB |
9161 | struct i40e_pf *pf = vsi->back; |
9162 | struct i40e_hw *hw = &pf->hw; | |
9163 | struct i40e_vsi_context ctxt; | |
21659035 KP |
9164 | struct i40e_mac_filter *f, *ftmp; |
9165 | ||
41c445ff JB |
9166 | u8 enabled_tc = 0x1; /* TC0 enabled */ |
9167 | int f_count = 0; | |
9168 | ||
9169 | memset(&ctxt, 0, sizeof(ctxt)); | |
9170 | switch (vsi->type) { | |
9171 | case I40E_VSI_MAIN: | |
9172 | /* The PF's main VSI is already setup as part of the | |
9173 | * device initialization, so we'll not bother with | |
9174 | * the add_vsi call, but we will retrieve the current | |
9175 | * VSI context. | |
9176 | */ | |
9177 | ctxt.seid = pf->main_vsi_seid; | |
9178 | ctxt.pf_num = pf->hw.pf_id; | |
9179 | ctxt.vf_num = 0; | |
9180 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); | |
9181 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
9182 | if (ret) { | |
9183 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9184 | "couldn't get PF vsi config, err %s aq_err %s\n", |
9185 | i40e_stat_str(&pf->hw, ret), | |
9186 | i40e_aq_str(&pf->hw, | |
9187 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9188 | return -ENOENT; |
9189 | } | |
1a2f6248 | 9190 | vsi->info = ctxt.info; |
41c445ff JB |
9191 | vsi->info.valid_sections = 0; |
9192 | ||
9193 | vsi->seid = ctxt.seid; | |
9194 | vsi->id = ctxt.vsi_number; | |
9195 | ||
9196 | enabled_tc = i40e_pf_get_tc_map(pf); | |
9197 | ||
9198 | /* MFP mode setup queue map and update VSI */ | |
63d7e5a4 NP |
9199 | if ((pf->flags & I40E_FLAG_MFP_ENABLED) && |
9200 | !(pf->hw.func_caps.iscsi)) { /* NIC type PF */ | |
41c445ff JB |
9201 | memset(&ctxt, 0, sizeof(ctxt)); |
9202 | ctxt.seid = pf->main_vsi_seid; | |
9203 | ctxt.pf_num = pf->hw.pf_id; | |
9204 | ctxt.vf_num = 0; | |
9205 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); | |
9206 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
9207 | if (ret) { | |
9208 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9209 | "update vsi failed, err %s aq_err %s\n", |
9210 | i40e_stat_str(&pf->hw, ret), | |
9211 | i40e_aq_str(&pf->hw, | |
9212 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9213 | ret = -ENOENT; |
9214 | goto err; | |
9215 | } | |
9216 | /* update the local VSI info queue map */ | |
9217 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
9218 | vsi->info.valid_sections = 0; | |
9219 | } else { | |
9220 | /* Default/Main VSI is only enabled for TC0 | |
9221 | * reconfigure it to enable all TCs that are | |
9222 | * available on the port in SFP mode. | |
63d7e5a4 NP |
9223 | * For MFP case the iSCSI PF would use this |
9224 | * flow to enable LAN+iSCSI TC. | |
41c445ff JB |
9225 | */ |
9226 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
9227 | if (ret) { | |
9228 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9229 | "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n", |
9230 | enabled_tc, | |
9231 | i40e_stat_str(&pf->hw, ret), | |
9232 | i40e_aq_str(&pf->hw, | |
9233 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9234 | ret = -ENOENT; |
9235 | } | |
9236 | } | |
9237 | break; | |
9238 | ||
9239 | case I40E_VSI_FDIR: | |
cbf61325 ASJ |
9240 | ctxt.pf_num = hw->pf_id; |
9241 | ctxt.vf_num = 0; | |
9242 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 9243 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
cbf61325 | 9244 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; |
fc60861e ASJ |
9245 | if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) && |
9246 | (i40e_is_vsi_uplink_mode_veb(vsi))) { | |
51616018 | 9247 | ctxt.info.valid_sections |= |
fc60861e | 9248 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); |
51616018 | 9249 | ctxt.info.switch_id = |
fc60861e | 9250 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); |
51616018 | 9251 | } |
41c445ff | 9252 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); |
41c445ff JB |
9253 | break; |
9254 | ||
9255 | case I40E_VSI_VMDQ2: | |
9256 | ctxt.pf_num = hw->pf_id; | |
9257 | ctxt.vf_num = 0; | |
9258 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 9259 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
9260 | ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; |
9261 | ||
41c445ff JB |
9262 | /* This VSI is connected to VEB so the switch_id |
9263 | * should be set to zero by default. | |
9264 | */ | |
51616018 NP |
9265 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
9266 | ctxt.info.valid_sections |= | |
9267 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
9268 | ctxt.info.switch_id = | |
9269 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
9270 | } | |
41c445ff JB |
9271 | |
9272 | /* Setup the VSI tx/rx queue map for TC0 only for now */ | |
9273 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
9274 | break; | |
9275 | ||
9276 | case I40E_VSI_SRIOV: | |
9277 | ctxt.pf_num = hw->pf_id; | |
9278 | ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id; | |
9279 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 9280 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
9281 | ctxt.flags = I40E_AQ_VSI_TYPE_VF; |
9282 | ||
41c445ff JB |
9283 | /* This VSI is connected to VEB so the switch_id |
9284 | * should be set to zero by default. | |
9285 | */ | |
51616018 NP |
9286 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
9287 | ctxt.info.valid_sections |= | |
9288 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
9289 | ctxt.info.switch_id = | |
9290 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
9291 | } | |
41c445ff | 9292 | |
e3219ce6 ASJ |
9293 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
9294 | ctxt.info.valid_sections |= | |
9295 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
9296 | ctxt.info.queueing_opt_flags |= | |
4b28cdba AS |
9297 | (I40E_AQ_VSI_QUE_OPT_TCP_ENA | |
9298 | I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI); | |
e3219ce6 ASJ |
9299 | } |
9300 | ||
41c445ff JB |
9301 | ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); |
9302 | ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; | |
c674d125 MW |
9303 | if (pf->vf[vsi->vf_id].spoofchk) { |
9304 | ctxt.info.valid_sections |= | |
9305 | cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID); | |
9306 | ctxt.info.sec_flags |= | |
9307 | (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK | | |
9308 | I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK); | |
9309 | } | |
41c445ff JB |
9310 | /* Setup the VSI tx/rx queue map for TC0 only for now */ |
9311 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
9312 | break; | |
9313 | ||
38e00438 VD |
9314 | #ifdef I40E_FCOE |
9315 | case I40E_VSI_FCOE: | |
9316 | ret = i40e_fcoe_vsi_init(vsi, &ctxt); | |
9317 | if (ret) { | |
9318 | dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n"); | |
9319 | return ret; | |
9320 | } | |
9321 | break; | |
9322 | ||
9323 | #endif /* I40E_FCOE */ | |
e3219ce6 ASJ |
9324 | case I40E_VSI_IWARP: |
9325 | /* send down message to iWARP */ | |
9326 | break; | |
9327 | ||
41c445ff JB |
9328 | default: |
9329 | return -ENODEV; | |
9330 | } | |
9331 | ||
9332 | if (vsi->type != I40E_VSI_MAIN) { | |
9333 | ret = i40e_aq_add_vsi(hw, &ctxt, NULL); | |
9334 | if (ret) { | |
9335 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
9336 | "add vsi failed, err %s aq_err %s\n", |
9337 | i40e_stat_str(&pf->hw, ret), | |
9338 | i40e_aq_str(&pf->hw, | |
9339 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9340 | ret = -ENOENT; |
9341 | goto err; | |
9342 | } | |
1a2f6248 | 9343 | vsi->info = ctxt.info; |
41c445ff JB |
9344 | vsi->info.valid_sections = 0; |
9345 | vsi->seid = ctxt.seid; | |
9346 | vsi->id = ctxt.vsi_number; | |
9347 | } | |
9348 | ||
c3c7ea27 MW |
9349 | vsi->active_filters = 0; |
9350 | clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); | |
21659035 | 9351 | spin_lock_bh(&vsi->mac_filter_list_lock); |
41c445ff JB |
9352 | /* If macvlan filters already exist, force them to get loaded */ |
9353 | list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { | |
c3c7ea27 | 9354 | f->state = I40E_FILTER_NEW; |
41c445ff | 9355 | f_count++; |
21659035 KP |
9356 | } |
9357 | spin_unlock_bh(&vsi->mac_filter_list_lock); | |
30650cc5 | 9358 | |
41c445ff JB |
9359 | if (f_count) { |
9360 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
9361 | pf->flags |= I40E_FLAG_FILTER_SYNC; | |
9362 | } | |
9363 | ||
9364 | /* Update VSI BW information */ | |
9365 | ret = i40e_vsi_get_bw_info(vsi); | |
9366 | if (ret) { | |
9367 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9368 | "couldn't get vsi bw info, err %s aq_err %s\n", |
9369 | i40e_stat_str(&pf->hw, ret), | |
9370 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9371 | /* VSI is already added so not tearing that up */ |
9372 | ret = 0; | |
9373 | } | |
9374 | ||
9375 | err: | |
9376 | return ret; | |
9377 | } | |
9378 | ||
9379 | /** | |
9380 | * i40e_vsi_release - Delete a VSI and free its resources | |
9381 | * @vsi: the VSI being removed | |
9382 | * | |
9383 | * Returns 0 on success or < 0 on error | |
9384 | **/ | |
9385 | int i40e_vsi_release(struct i40e_vsi *vsi) | |
9386 | { | |
9387 | struct i40e_mac_filter *f, *ftmp; | |
9388 | struct i40e_veb *veb = NULL; | |
9389 | struct i40e_pf *pf; | |
9390 | u16 uplink_seid; | |
9391 | int i, n; | |
9392 | ||
9393 | pf = vsi->back; | |
9394 | ||
9395 | /* release of a VEB-owner or last VSI is not allowed */ | |
9396 | if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
9397 | dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n", | |
9398 | vsi->seid, vsi->uplink_seid); | |
9399 | return -ENODEV; | |
9400 | } | |
9401 | if (vsi == pf->vsi[pf->lan_vsi] && | |
9402 | !test_bit(__I40E_DOWN, &pf->state)) { | |
9403 | dev_info(&pf->pdev->dev, "Can't remove PF VSI\n"); | |
9404 | return -ENODEV; | |
9405 | } | |
9406 | ||
9407 | uplink_seid = vsi->uplink_seid; | |
9408 | if (vsi->type != I40E_VSI_SRIOV) { | |
9409 | if (vsi->netdev_registered) { | |
9410 | vsi->netdev_registered = false; | |
9411 | if (vsi->netdev) { | |
9412 | /* results in a call to i40e_close() */ | |
9413 | unregister_netdev(vsi->netdev); | |
41c445ff JB |
9414 | } |
9415 | } else { | |
90ef8d47 | 9416 | i40e_vsi_close(vsi); |
41c445ff JB |
9417 | } |
9418 | i40e_vsi_disable_irq(vsi); | |
9419 | } | |
9420 | ||
21659035 | 9421 | spin_lock_bh(&vsi->mac_filter_list_lock); |
41c445ff JB |
9422 | list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) |
9423 | i40e_del_filter(vsi, f->macaddr, f->vlan, | |
9424 | f->is_vf, f->is_netdev); | |
21659035 KP |
9425 | spin_unlock_bh(&vsi->mac_filter_list_lock); |
9426 | ||
17652c63 | 9427 | i40e_sync_vsi_filters(vsi); |
41c445ff JB |
9428 | |
9429 | i40e_vsi_delete(vsi); | |
9430 | i40e_vsi_free_q_vectors(vsi); | |
a4866597 SN |
9431 | if (vsi->netdev) { |
9432 | free_netdev(vsi->netdev); | |
9433 | vsi->netdev = NULL; | |
9434 | } | |
41c445ff JB |
9435 | i40e_vsi_clear_rings(vsi); |
9436 | i40e_vsi_clear(vsi); | |
9437 | ||
9438 | /* If this was the last thing on the VEB, except for the | |
9439 | * controlling VSI, remove the VEB, which puts the controlling | |
9440 | * VSI onto the next level down in the switch. | |
9441 | * | |
9442 | * Well, okay, there's one more exception here: don't remove | |
9443 | * the orphan VEBs yet. We'll wait for an explicit remove request | |
9444 | * from up the network stack. | |
9445 | */ | |
505682cd | 9446 | for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
9447 | if (pf->vsi[i] && |
9448 | pf->vsi[i]->uplink_seid == uplink_seid && | |
9449 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
9450 | n++; /* count the VSIs */ | |
9451 | } | |
9452 | } | |
9453 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
9454 | if (!pf->veb[i]) | |
9455 | continue; | |
9456 | if (pf->veb[i]->uplink_seid == uplink_seid) | |
9457 | n++; /* count the VEBs */ | |
9458 | if (pf->veb[i]->seid == uplink_seid) | |
9459 | veb = pf->veb[i]; | |
9460 | } | |
9461 | if (n == 0 && veb && veb->uplink_seid != 0) | |
9462 | i40e_veb_release(veb); | |
9463 | ||
9464 | return 0; | |
9465 | } | |
9466 | ||
9467 | /** | |
9468 | * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI | |
9469 | * @vsi: ptr to the VSI | |
9470 | * | |
9471 | * This should only be called after i40e_vsi_mem_alloc() which allocates the | |
9472 | * corresponding SW VSI structure and initializes num_queue_pairs for the | |
9473 | * newly allocated VSI. | |
9474 | * | |
9475 | * Returns 0 on success or negative on failure | |
9476 | **/ | |
9477 | static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi) | |
9478 | { | |
9479 | int ret = -ENOENT; | |
9480 | struct i40e_pf *pf = vsi->back; | |
9481 | ||
493fb300 | 9482 | if (vsi->q_vectors[0]) { |
41c445ff JB |
9483 | dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n", |
9484 | vsi->seid); | |
9485 | return -EEXIST; | |
9486 | } | |
9487 | ||
9488 | if (vsi->base_vector) { | |
f29eaa3d | 9489 | dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n", |
41c445ff JB |
9490 | vsi->seid, vsi->base_vector); |
9491 | return -EEXIST; | |
9492 | } | |
9493 | ||
90e04070 | 9494 | ret = i40e_vsi_alloc_q_vectors(vsi); |
41c445ff JB |
9495 | if (ret) { |
9496 | dev_info(&pf->pdev->dev, | |
9497 | "failed to allocate %d q_vector for VSI %d, ret=%d\n", | |
9498 | vsi->num_q_vectors, vsi->seid, ret); | |
9499 | vsi->num_q_vectors = 0; | |
9500 | goto vector_setup_out; | |
9501 | } | |
9502 | ||
26cdc443 ASJ |
9503 | /* In Legacy mode, we do not have to get any other vector since we |
9504 | * piggyback on the misc/ICR0 for queue interrupts. | |
9505 | */ | |
9506 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
9507 | return ret; | |
958a3e3b SN |
9508 | if (vsi->num_q_vectors) |
9509 | vsi->base_vector = i40e_get_lump(pf, pf->irq_pile, | |
9510 | vsi->num_q_vectors, vsi->idx); | |
41c445ff JB |
9511 | if (vsi->base_vector < 0) { |
9512 | dev_info(&pf->pdev->dev, | |
049a2be8 SN |
9513 | "failed to get tracking for %d vectors for VSI %d, err=%d\n", |
9514 | vsi->num_q_vectors, vsi->seid, vsi->base_vector); | |
41c445ff JB |
9515 | i40e_vsi_free_q_vectors(vsi); |
9516 | ret = -ENOENT; | |
9517 | goto vector_setup_out; | |
9518 | } | |
9519 | ||
9520 | vector_setup_out: | |
9521 | return ret; | |
9522 | } | |
9523 | ||
bc7d338f ASJ |
9524 | /** |
9525 | * i40e_vsi_reinit_setup - return and reallocate resources for a VSI | |
9526 | * @vsi: pointer to the vsi. | |
9527 | * | |
9528 | * This re-allocates a vsi's queue resources. | |
9529 | * | |
9530 | * Returns pointer to the successfully allocated and configured VSI sw struct | |
9531 | * on success, otherwise returns NULL on failure. | |
9532 | **/ | |
9533 | static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi) | |
9534 | { | |
f534039d | 9535 | struct i40e_pf *pf; |
bc7d338f ASJ |
9536 | u8 enabled_tc; |
9537 | int ret; | |
9538 | ||
f534039d JU |
9539 | if (!vsi) |
9540 | return NULL; | |
9541 | ||
9542 | pf = vsi->back; | |
9543 | ||
bc7d338f ASJ |
9544 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
9545 | i40e_vsi_clear_rings(vsi); | |
9546 | ||
9547 | i40e_vsi_free_arrays(vsi, false); | |
9548 | i40e_set_num_rings_in_vsi(vsi); | |
9549 | ret = i40e_vsi_alloc_arrays(vsi, false); | |
9550 | if (ret) | |
9551 | goto err_vsi; | |
9552 | ||
9553 | ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx); | |
9554 | if (ret < 0) { | |
049a2be8 | 9555 | dev_info(&pf->pdev->dev, |
f1c7e72e | 9556 | "failed to get tracking for %d queues for VSI %d err %d\n", |
049a2be8 | 9557 | vsi->alloc_queue_pairs, vsi->seid, ret); |
bc7d338f ASJ |
9558 | goto err_vsi; |
9559 | } | |
9560 | vsi->base_queue = ret; | |
9561 | ||
9562 | /* Update the FW view of the VSI. Force a reset of TC and queue | |
9563 | * layout configurations. | |
9564 | */ | |
9565 | enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
9566 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; | |
9567 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
9568 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
c3c7ea27 MW |
9569 | if (vsi->type == I40E_VSI_MAIN) |
9570 | i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr); | |
bc7d338f ASJ |
9571 | |
9572 | /* assign it some queues */ | |
9573 | ret = i40e_alloc_rings(vsi); | |
9574 | if (ret) | |
9575 | goto err_rings; | |
9576 | ||
9577 | /* map all of the rings to the q_vectors */ | |
9578 | i40e_vsi_map_rings_to_vectors(vsi); | |
9579 | return vsi; | |
9580 | ||
9581 | err_rings: | |
9582 | i40e_vsi_free_q_vectors(vsi); | |
9583 | if (vsi->netdev_registered) { | |
9584 | vsi->netdev_registered = false; | |
9585 | unregister_netdev(vsi->netdev); | |
9586 | free_netdev(vsi->netdev); | |
9587 | vsi->netdev = NULL; | |
9588 | } | |
9589 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
9590 | err_vsi: | |
9591 | i40e_vsi_clear(vsi); | |
9592 | return NULL; | |
9593 | } | |
9594 | ||
b499ffb0 SV |
9595 | /** |
9596 | * i40e_macaddr_init - explicitly write the mac address filters. | |
9597 | * | |
9598 | * @vsi: pointer to the vsi. | |
9599 | * @macaddr: the MAC address | |
9600 | * | |
9601 | * This is needed when the macaddr has been obtained by other | |
9602 | * means than the default, e.g., from Open Firmware or IDPROM. | |
9603 | * Returns 0 on success, negative on failure | |
9604 | **/ | |
9605 | static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr) | |
9606 | { | |
9607 | int ret; | |
9608 | struct i40e_aqc_add_macvlan_element_data element; | |
9609 | ||
9610 | ret = i40e_aq_mac_address_write(&vsi->back->hw, | |
9611 | I40E_AQC_WRITE_TYPE_LAA_WOL, | |
9612 | macaddr, NULL); | |
9613 | if (ret) { | |
9614 | dev_info(&vsi->back->pdev->dev, | |
9615 | "Addr change for VSI failed: %d\n", ret); | |
9616 | return -EADDRNOTAVAIL; | |
9617 | } | |
9618 | ||
9619 | memset(&element, 0, sizeof(element)); | |
9620 | ether_addr_copy(element.mac_addr, macaddr); | |
9621 | element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH); | |
9622 | ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL); | |
9623 | if (ret) { | |
9624 | dev_info(&vsi->back->pdev->dev, | |
9625 | "add filter failed err %s aq_err %s\n", | |
9626 | i40e_stat_str(&vsi->back->hw, ret), | |
9627 | i40e_aq_str(&vsi->back->hw, | |
9628 | vsi->back->hw.aq.asq_last_status)); | |
9629 | } | |
9630 | return ret; | |
9631 | } | |
9632 | ||
41c445ff JB |
9633 | /** |
9634 | * i40e_vsi_setup - Set up a VSI by a given type | |
9635 | * @pf: board private structure | |
9636 | * @type: VSI type | |
9637 | * @uplink_seid: the switch element to link to | |
9638 | * @param1: usage depends upon VSI type. For VF types, indicates VF id | |
9639 | * | |
9640 | * This allocates the sw VSI structure and its queue resources, then add a VSI | |
9641 | * to the identified VEB. | |
9642 | * | |
9643 | * Returns pointer to the successfully allocated and configure VSI sw struct on | |
9644 | * success, otherwise returns NULL on failure. | |
9645 | **/ | |
9646 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, | |
9647 | u16 uplink_seid, u32 param1) | |
9648 | { | |
9649 | struct i40e_vsi *vsi = NULL; | |
9650 | struct i40e_veb *veb = NULL; | |
9651 | int ret, i; | |
9652 | int v_idx; | |
9653 | ||
9654 | /* The requested uplink_seid must be either | |
9655 | * - the PF's port seid | |
9656 | * no VEB is needed because this is the PF | |
9657 | * or this is a Flow Director special case VSI | |
9658 | * - seid of an existing VEB | |
9659 | * - seid of a VSI that owns an existing VEB | |
9660 | * - seid of a VSI that doesn't own a VEB | |
9661 | * a new VEB is created and the VSI becomes the owner | |
9662 | * - seid of the PF VSI, which is what creates the first VEB | |
9663 | * this is a special case of the previous | |
9664 | * | |
9665 | * Find which uplink_seid we were given and create a new VEB if needed | |
9666 | */ | |
9667 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
9668 | if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) { | |
9669 | veb = pf->veb[i]; | |
9670 | break; | |
9671 | } | |
9672 | } | |
9673 | ||
9674 | if (!veb && uplink_seid != pf->mac_seid) { | |
9675 | ||
505682cd | 9676 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
9677 | if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) { |
9678 | vsi = pf->vsi[i]; | |
9679 | break; | |
9680 | } | |
9681 | } | |
9682 | if (!vsi) { | |
9683 | dev_info(&pf->pdev->dev, "no such uplink_seid %d\n", | |
9684 | uplink_seid); | |
9685 | return NULL; | |
9686 | } | |
9687 | ||
9688 | if (vsi->uplink_seid == pf->mac_seid) | |
9689 | veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid, | |
9690 | vsi->tc_config.enabled_tc); | |
9691 | else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) | |
9692 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
9693 | vsi->tc_config.enabled_tc); | |
79c21a82 ASJ |
9694 | if (veb) { |
9695 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) { | |
9696 | dev_info(&vsi->back->pdev->dev, | |
fb43201f | 9697 | "New VSI creation error, uplink seid of LAN VSI expected.\n"); |
79c21a82 ASJ |
9698 | return NULL; |
9699 | } | |
fa11cb3d ASJ |
9700 | /* We come up by default in VEPA mode if SRIOV is not |
9701 | * already enabled, in which case we can't force VEPA | |
9702 | * mode. | |
9703 | */ | |
9704 | if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { | |
9705 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
9706 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
9707 | } | |
51616018 | 9708 | i40e_config_bridge_mode(veb); |
79c21a82 | 9709 | } |
41c445ff JB |
9710 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { |
9711 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
9712 | veb = pf->veb[i]; | |
9713 | } | |
9714 | if (!veb) { | |
9715 | dev_info(&pf->pdev->dev, "couldn't add VEB\n"); | |
9716 | return NULL; | |
9717 | } | |
9718 | ||
9719 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
9720 | uplink_seid = veb->seid; | |
9721 | } | |
9722 | ||
9723 | /* get vsi sw struct */ | |
9724 | v_idx = i40e_vsi_mem_alloc(pf, type); | |
9725 | if (v_idx < 0) | |
9726 | goto err_alloc; | |
9727 | vsi = pf->vsi[v_idx]; | |
cbf61325 ASJ |
9728 | if (!vsi) |
9729 | goto err_alloc; | |
41c445ff JB |
9730 | vsi->type = type; |
9731 | vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB); | |
9732 | ||
9733 | if (type == I40E_VSI_MAIN) | |
9734 | pf->lan_vsi = v_idx; | |
9735 | else if (type == I40E_VSI_SRIOV) | |
9736 | vsi->vf_id = param1; | |
9737 | /* assign it some queues */ | |
cbf61325 ASJ |
9738 | ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, |
9739 | vsi->idx); | |
41c445ff | 9740 | if (ret < 0) { |
049a2be8 SN |
9741 | dev_info(&pf->pdev->dev, |
9742 | "failed to get tracking for %d queues for VSI %d err=%d\n", | |
9743 | vsi->alloc_queue_pairs, vsi->seid, ret); | |
41c445ff JB |
9744 | goto err_vsi; |
9745 | } | |
9746 | vsi->base_queue = ret; | |
9747 | ||
9748 | /* get a VSI from the hardware */ | |
9749 | vsi->uplink_seid = uplink_seid; | |
9750 | ret = i40e_add_vsi(vsi); | |
9751 | if (ret) | |
9752 | goto err_vsi; | |
9753 | ||
9754 | switch (vsi->type) { | |
9755 | /* setup the netdev if needed */ | |
9756 | case I40E_VSI_MAIN: | |
b499ffb0 SV |
9757 | /* Apply relevant filters if a platform-specific mac |
9758 | * address was selected. | |
9759 | */ | |
9760 | if (!!(pf->flags & I40E_FLAG_PF_MAC)) { | |
9761 | ret = i40e_macaddr_init(vsi, pf->hw.mac.addr); | |
9762 | if (ret) { | |
9763 | dev_warn(&pf->pdev->dev, | |
9764 | "could not set up macaddr; err %d\n", | |
9765 | ret); | |
9766 | } | |
9767 | } | |
41c445ff | 9768 | case I40E_VSI_VMDQ2: |
38e00438 | 9769 | case I40E_VSI_FCOE: |
41c445ff JB |
9770 | ret = i40e_config_netdev(vsi); |
9771 | if (ret) | |
9772 | goto err_netdev; | |
9773 | ret = register_netdev(vsi->netdev); | |
9774 | if (ret) | |
9775 | goto err_netdev; | |
9776 | vsi->netdev_registered = true; | |
9777 | netif_carrier_off(vsi->netdev); | |
4e3b35b0 NP |
9778 | #ifdef CONFIG_I40E_DCB |
9779 | /* Setup DCB netlink interface */ | |
9780 | i40e_dcbnl_setup(vsi); | |
9781 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
9782 | /* fall through */ |
9783 | ||
9784 | case I40E_VSI_FDIR: | |
9785 | /* set up vectors and rings if needed */ | |
9786 | ret = i40e_vsi_setup_vectors(vsi); | |
9787 | if (ret) | |
9788 | goto err_msix; | |
9789 | ||
9790 | ret = i40e_alloc_rings(vsi); | |
9791 | if (ret) | |
9792 | goto err_rings; | |
9793 | ||
9794 | /* map all of the rings to the q_vectors */ | |
9795 | i40e_vsi_map_rings_to_vectors(vsi); | |
9796 | ||
9797 | i40e_vsi_reset_stats(vsi); | |
9798 | break; | |
9799 | ||
9800 | default: | |
9801 | /* no netdev or rings for the other VSI types */ | |
9802 | break; | |
9803 | } | |
9804 | ||
e25d00b8 ASJ |
9805 | if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) && |
9806 | (vsi->type == I40E_VSI_VMDQ2)) { | |
9807 | ret = i40e_vsi_config_rss(vsi); | |
9808 | } | |
41c445ff JB |
9809 | return vsi; |
9810 | ||
9811 | err_rings: | |
9812 | i40e_vsi_free_q_vectors(vsi); | |
9813 | err_msix: | |
9814 | if (vsi->netdev_registered) { | |
9815 | vsi->netdev_registered = false; | |
9816 | unregister_netdev(vsi->netdev); | |
9817 | free_netdev(vsi->netdev); | |
9818 | vsi->netdev = NULL; | |
9819 | } | |
9820 | err_netdev: | |
9821 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
9822 | err_vsi: | |
9823 | i40e_vsi_clear(vsi); | |
9824 | err_alloc: | |
9825 | return NULL; | |
9826 | } | |
9827 | ||
9828 | /** | |
9829 | * i40e_veb_get_bw_info - Query VEB BW information | |
9830 | * @veb: the veb to query | |
9831 | * | |
9832 | * Query the Tx scheduler BW configuration data for given VEB | |
9833 | **/ | |
9834 | static int i40e_veb_get_bw_info(struct i40e_veb *veb) | |
9835 | { | |
9836 | struct i40e_aqc_query_switching_comp_ets_config_resp ets_data; | |
9837 | struct i40e_aqc_query_switching_comp_bw_config_resp bw_data; | |
9838 | struct i40e_pf *pf = veb->pf; | |
9839 | struct i40e_hw *hw = &pf->hw; | |
9840 | u32 tc_bw_max; | |
9841 | int ret = 0; | |
9842 | int i; | |
9843 | ||
9844 | ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, | |
9845 | &bw_data, NULL); | |
9846 | if (ret) { | |
9847 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9848 | "query veb bw config failed, err %s aq_err %s\n", |
9849 | i40e_stat_str(&pf->hw, ret), | |
9850 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
9851 | goto out; |
9852 | } | |
9853 | ||
9854 | ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, | |
9855 | &ets_data, NULL); | |
9856 | if (ret) { | |
9857 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9858 | "query veb bw ets config failed, err %s aq_err %s\n", |
9859 | i40e_stat_str(&pf->hw, ret), | |
9860 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
9861 | goto out; |
9862 | } | |
9863 | ||
9864 | veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit); | |
9865 | veb->bw_max_quanta = ets_data.tc_bw_max; | |
9866 | veb->is_abs_credits = bw_data.absolute_credits_enable; | |
23cd1f09 | 9867 | veb->enabled_tc = ets_data.tc_valid_bits; |
41c445ff JB |
9868 | tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) | |
9869 | (le16_to_cpu(bw_data.tc_bw_max[1]) << 16); | |
9870 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
9871 | veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i]; | |
9872 | veb->bw_tc_limit_credits[i] = | |
9873 | le16_to_cpu(bw_data.tc_bw_limits[i]); | |
9874 | veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7); | |
9875 | } | |
9876 | ||
9877 | out: | |
9878 | return ret; | |
9879 | } | |
9880 | ||
9881 | /** | |
9882 | * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF | |
9883 | * @pf: board private structure | |
9884 | * | |
9885 | * On error: returns error code (negative) | |
9886 | * On success: returns vsi index in PF (positive) | |
9887 | **/ | |
9888 | static int i40e_veb_mem_alloc(struct i40e_pf *pf) | |
9889 | { | |
9890 | int ret = -ENOENT; | |
9891 | struct i40e_veb *veb; | |
9892 | int i; | |
9893 | ||
9894 | /* Need to protect the allocation of switch elements at the PF level */ | |
9895 | mutex_lock(&pf->switch_mutex); | |
9896 | ||
9897 | /* VEB list may be fragmented if VEB creation/destruction has | |
9898 | * been happening. We can afford to do a quick scan to look | |
9899 | * for any free slots in the list. | |
9900 | * | |
9901 | * find next empty veb slot, looping back around if necessary | |
9902 | */ | |
9903 | i = 0; | |
9904 | while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL)) | |
9905 | i++; | |
9906 | if (i >= I40E_MAX_VEB) { | |
9907 | ret = -ENOMEM; | |
9908 | goto err_alloc_veb; /* out of VEB slots! */ | |
9909 | } | |
9910 | ||
9911 | veb = kzalloc(sizeof(*veb), GFP_KERNEL); | |
9912 | if (!veb) { | |
9913 | ret = -ENOMEM; | |
9914 | goto err_alloc_veb; | |
9915 | } | |
9916 | veb->pf = pf; | |
9917 | veb->idx = i; | |
9918 | veb->enabled_tc = 1; | |
9919 | ||
9920 | pf->veb[i] = veb; | |
9921 | ret = i; | |
9922 | err_alloc_veb: | |
9923 | mutex_unlock(&pf->switch_mutex); | |
9924 | return ret; | |
9925 | } | |
9926 | ||
9927 | /** | |
9928 | * i40e_switch_branch_release - Delete a branch of the switch tree | |
9929 | * @branch: where to start deleting | |
9930 | * | |
9931 | * This uses recursion to find the tips of the branch to be | |
9932 | * removed, deleting until we get back to and can delete this VEB. | |
9933 | **/ | |
9934 | static void i40e_switch_branch_release(struct i40e_veb *branch) | |
9935 | { | |
9936 | struct i40e_pf *pf = branch->pf; | |
9937 | u16 branch_seid = branch->seid; | |
9938 | u16 veb_idx = branch->idx; | |
9939 | int i; | |
9940 | ||
9941 | /* release any VEBs on this VEB - RECURSION */ | |
9942 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
9943 | if (!pf->veb[i]) | |
9944 | continue; | |
9945 | if (pf->veb[i]->uplink_seid == branch->seid) | |
9946 | i40e_switch_branch_release(pf->veb[i]); | |
9947 | } | |
9948 | ||
9949 | /* Release the VSIs on this VEB, but not the owner VSI. | |
9950 | * | |
9951 | * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing | |
9952 | * the VEB itself, so don't use (*branch) after this loop. | |
9953 | */ | |
505682cd | 9954 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
9955 | if (!pf->vsi[i]) |
9956 | continue; | |
9957 | if (pf->vsi[i]->uplink_seid == branch_seid && | |
9958 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
9959 | i40e_vsi_release(pf->vsi[i]); | |
9960 | } | |
9961 | } | |
9962 | ||
9963 | /* There's one corner case where the VEB might not have been | |
9964 | * removed, so double check it here and remove it if needed. | |
9965 | * This case happens if the veb was created from the debugfs | |
9966 | * commands and no VSIs were added to it. | |
9967 | */ | |
9968 | if (pf->veb[veb_idx]) | |
9969 | i40e_veb_release(pf->veb[veb_idx]); | |
9970 | } | |
9971 | ||
9972 | /** | |
9973 | * i40e_veb_clear - remove veb struct | |
9974 | * @veb: the veb to remove | |
9975 | **/ | |
9976 | static void i40e_veb_clear(struct i40e_veb *veb) | |
9977 | { | |
9978 | if (!veb) | |
9979 | return; | |
9980 | ||
9981 | if (veb->pf) { | |
9982 | struct i40e_pf *pf = veb->pf; | |
9983 | ||
9984 | mutex_lock(&pf->switch_mutex); | |
9985 | if (pf->veb[veb->idx] == veb) | |
9986 | pf->veb[veb->idx] = NULL; | |
9987 | mutex_unlock(&pf->switch_mutex); | |
9988 | } | |
9989 | ||
9990 | kfree(veb); | |
9991 | } | |
9992 | ||
9993 | /** | |
9994 | * i40e_veb_release - Delete a VEB and free its resources | |
9995 | * @veb: the VEB being removed | |
9996 | **/ | |
9997 | void i40e_veb_release(struct i40e_veb *veb) | |
9998 | { | |
9999 | struct i40e_vsi *vsi = NULL; | |
10000 | struct i40e_pf *pf; | |
10001 | int i, n = 0; | |
10002 | ||
10003 | pf = veb->pf; | |
10004 | ||
10005 | /* find the remaining VSI and check for extras */ | |
505682cd | 10006 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
10007 | if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) { |
10008 | n++; | |
10009 | vsi = pf->vsi[i]; | |
10010 | } | |
10011 | } | |
10012 | if (n != 1) { | |
10013 | dev_info(&pf->pdev->dev, | |
10014 | "can't remove VEB %d with %d VSIs left\n", | |
10015 | veb->seid, n); | |
10016 | return; | |
10017 | } | |
10018 | ||
10019 | /* move the remaining VSI to uplink veb */ | |
10020 | vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER; | |
10021 | if (veb->uplink_seid) { | |
10022 | vsi->uplink_seid = veb->uplink_seid; | |
10023 | if (veb->uplink_seid == pf->mac_seid) | |
10024 | vsi->veb_idx = I40E_NO_VEB; | |
10025 | else | |
10026 | vsi->veb_idx = veb->veb_idx; | |
10027 | } else { | |
10028 | /* floating VEB */ | |
10029 | vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
10030 | vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx; | |
10031 | } | |
10032 | ||
10033 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
10034 | i40e_veb_clear(veb); | |
41c445ff JB |
10035 | } |
10036 | ||
10037 | /** | |
10038 | * i40e_add_veb - create the VEB in the switch | |
10039 | * @veb: the VEB to be instantiated | |
10040 | * @vsi: the controlling VSI | |
10041 | **/ | |
10042 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi) | |
10043 | { | |
f1c7e72e | 10044 | struct i40e_pf *pf = veb->pf; |
66fc360a | 10045 | bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED); |
41c445ff JB |
10046 | int ret; |
10047 | ||
f1c7e72e | 10048 | ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid, |
5bc16031 | 10049 | veb->enabled_tc, false, |
66fc360a | 10050 | &veb->seid, enable_stats, NULL); |
5bc16031 MW |
10051 | |
10052 | /* get a VEB from the hardware */ | |
41c445ff | 10053 | if (ret) { |
f1c7e72e SN |
10054 | dev_info(&pf->pdev->dev, |
10055 | "couldn't add VEB, err %s aq_err %s\n", | |
10056 | i40e_stat_str(&pf->hw, ret), | |
10057 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10058 | return -EPERM; |
10059 | } | |
10060 | ||
10061 | /* get statistics counter */ | |
f1c7e72e | 10062 | ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL, |
41c445ff JB |
10063 | &veb->stats_idx, NULL, NULL, NULL); |
10064 | if (ret) { | |
f1c7e72e SN |
10065 | dev_info(&pf->pdev->dev, |
10066 | "couldn't get VEB statistics idx, err %s aq_err %s\n", | |
10067 | i40e_stat_str(&pf->hw, ret), | |
10068 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10069 | return -EPERM; |
10070 | } | |
10071 | ret = i40e_veb_get_bw_info(veb); | |
10072 | if (ret) { | |
f1c7e72e SN |
10073 | dev_info(&pf->pdev->dev, |
10074 | "couldn't get VEB bw info, err %s aq_err %s\n", | |
10075 | i40e_stat_str(&pf->hw, ret), | |
10076 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
10077 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
41c445ff JB |
10078 | return -ENOENT; |
10079 | } | |
10080 | ||
10081 | vsi->uplink_seid = veb->seid; | |
10082 | vsi->veb_idx = veb->idx; | |
10083 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
10084 | ||
10085 | return 0; | |
10086 | } | |
10087 | ||
10088 | /** | |
10089 | * i40e_veb_setup - Set up a VEB | |
10090 | * @pf: board private structure | |
10091 | * @flags: VEB setup flags | |
10092 | * @uplink_seid: the switch element to link to | |
10093 | * @vsi_seid: the initial VSI seid | |
10094 | * @enabled_tc: Enabled TC bit-map | |
10095 | * | |
10096 | * This allocates the sw VEB structure and links it into the switch | |
10097 | * It is possible and legal for this to be a duplicate of an already | |
10098 | * existing VEB. It is also possible for both uplink and vsi seids | |
10099 | * to be zero, in order to create a floating VEB. | |
10100 | * | |
10101 | * Returns pointer to the successfully allocated VEB sw struct on | |
10102 | * success, otherwise returns NULL on failure. | |
10103 | **/ | |
10104 | struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, | |
10105 | u16 uplink_seid, u16 vsi_seid, | |
10106 | u8 enabled_tc) | |
10107 | { | |
10108 | struct i40e_veb *veb, *uplink_veb = NULL; | |
10109 | int vsi_idx, veb_idx; | |
10110 | int ret; | |
10111 | ||
10112 | /* if one seid is 0, the other must be 0 to create a floating relay */ | |
10113 | if ((uplink_seid == 0 || vsi_seid == 0) && | |
10114 | (uplink_seid + vsi_seid != 0)) { | |
10115 | dev_info(&pf->pdev->dev, | |
10116 | "one, not both seid's are 0: uplink=%d vsi=%d\n", | |
10117 | uplink_seid, vsi_seid); | |
10118 | return NULL; | |
10119 | } | |
10120 | ||
10121 | /* make sure there is such a vsi and uplink */ | |
505682cd | 10122 | for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++) |
41c445ff JB |
10123 | if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid) |
10124 | break; | |
505682cd | 10125 | if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) { |
41c445ff JB |
10126 | dev_info(&pf->pdev->dev, "vsi seid %d not found\n", |
10127 | vsi_seid); | |
10128 | return NULL; | |
10129 | } | |
10130 | ||
10131 | if (uplink_seid && uplink_seid != pf->mac_seid) { | |
10132 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
10133 | if (pf->veb[veb_idx] && | |
10134 | pf->veb[veb_idx]->seid == uplink_seid) { | |
10135 | uplink_veb = pf->veb[veb_idx]; | |
10136 | break; | |
10137 | } | |
10138 | } | |
10139 | if (!uplink_veb) { | |
10140 | dev_info(&pf->pdev->dev, | |
10141 | "uplink seid %d not found\n", uplink_seid); | |
10142 | return NULL; | |
10143 | } | |
10144 | } | |
10145 | ||
10146 | /* get veb sw struct */ | |
10147 | veb_idx = i40e_veb_mem_alloc(pf); | |
10148 | if (veb_idx < 0) | |
10149 | goto err_alloc; | |
10150 | veb = pf->veb[veb_idx]; | |
10151 | veb->flags = flags; | |
10152 | veb->uplink_seid = uplink_seid; | |
10153 | veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB); | |
10154 | veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1); | |
10155 | ||
10156 | /* create the VEB in the switch */ | |
10157 | ret = i40e_add_veb(veb, pf->vsi[vsi_idx]); | |
10158 | if (ret) | |
10159 | goto err_veb; | |
1bb8b935 SN |
10160 | if (vsi_idx == pf->lan_vsi) |
10161 | pf->lan_veb = veb->idx; | |
41c445ff JB |
10162 | |
10163 | return veb; | |
10164 | ||
10165 | err_veb: | |
10166 | i40e_veb_clear(veb); | |
10167 | err_alloc: | |
10168 | return NULL; | |
10169 | } | |
10170 | ||
10171 | /** | |
b40c82e6 | 10172 | * i40e_setup_pf_switch_element - set PF vars based on switch type |
41c445ff JB |
10173 | * @pf: board private structure |
10174 | * @ele: element we are building info from | |
10175 | * @num_reported: total number of elements | |
10176 | * @printconfig: should we print the contents | |
10177 | * | |
10178 | * helper function to assist in extracting a few useful SEID values. | |
10179 | **/ | |
10180 | static void i40e_setup_pf_switch_element(struct i40e_pf *pf, | |
10181 | struct i40e_aqc_switch_config_element_resp *ele, | |
10182 | u16 num_reported, bool printconfig) | |
10183 | { | |
10184 | u16 downlink_seid = le16_to_cpu(ele->downlink_seid); | |
10185 | u16 uplink_seid = le16_to_cpu(ele->uplink_seid); | |
10186 | u8 element_type = ele->element_type; | |
10187 | u16 seid = le16_to_cpu(ele->seid); | |
10188 | ||
10189 | if (printconfig) | |
10190 | dev_info(&pf->pdev->dev, | |
10191 | "type=%d seid=%d uplink=%d downlink=%d\n", | |
10192 | element_type, seid, uplink_seid, downlink_seid); | |
10193 | ||
10194 | switch (element_type) { | |
10195 | case I40E_SWITCH_ELEMENT_TYPE_MAC: | |
10196 | pf->mac_seid = seid; | |
10197 | break; | |
10198 | case I40E_SWITCH_ELEMENT_TYPE_VEB: | |
10199 | /* Main VEB? */ | |
10200 | if (uplink_seid != pf->mac_seid) | |
10201 | break; | |
10202 | if (pf->lan_veb == I40E_NO_VEB) { | |
10203 | int v; | |
10204 | ||
10205 | /* find existing or else empty VEB */ | |
10206 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
10207 | if (pf->veb[v] && (pf->veb[v]->seid == seid)) { | |
10208 | pf->lan_veb = v; | |
10209 | break; | |
10210 | } | |
10211 | } | |
10212 | if (pf->lan_veb == I40E_NO_VEB) { | |
10213 | v = i40e_veb_mem_alloc(pf); | |
10214 | if (v < 0) | |
10215 | break; | |
10216 | pf->lan_veb = v; | |
10217 | } | |
10218 | } | |
10219 | ||
10220 | pf->veb[pf->lan_veb]->seid = seid; | |
10221 | pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid; | |
10222 | pf->veb[pf->lan_veb]->pf = pf; | |
10223 | pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB; | |
10224 | break; | |
10225 | case I40E_SWITCH_ELEMENT_TYPE_VSI: | |
10226 | if (num_reported != 1) | |
10227 | break; | |
10228 | /* This is immediately after a reset so we can assume this is | |
10229 | * the PF's VSI | |
10230 | */ | |
10231 | pf->mac_seid = uplink_seid; | |
10232 | pf->pf_seid = downlink_seid; | |
10233 | pf->main_vsi_seid = seid; | |
10234 | if (printconfig) | |
10235 | dev_info(&pf->pdev->dev, | |
10236 | "pf_seid=%d main_vsi_seid=%d\n", | |
10237 | pf->pf_seid, pf->main_vsi_seid); | |
10238 | break; | |
10239 | case I40E_SWITCH_ELEMENT_TYPE_PF: | |
10240 | case I40E_SWITCH_ELEMENT_TYPE_VF: | |
10241 | case I40E_SWITCH_ELEMENT_TYPE_EMP: | |
10242 | case I40E_SWITCH_ELEMENT_TYPE_BMC: | |
10243 | case I40E_SWITCH_ELEMENT_TYPE_PE: | |
10244 | case I40E_SWITCH_ELEMENT_TYPE_PA: | |
10245 | /* ignore these for now */ | |
10246 | break; | |
10247 | default: | |
10248 | dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n", | |
10249 | element_type, seid); | |
10250 | break; | |
10251 | } | |
10252 | } | |
10253 | ||
10254 | /** | |
10255 | * i40e_fetch_switch_configuration - Get switch config from firmware | |
10256 | * @pf: board private structure | |
10257 | * @printconfig: should we print the contents | |
10258 | * | |
10259 | * Get the current switch configuration from the device and | |
10260 | * extract a few useful SEID values. | |
10261 | **/ | |
10262 | int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig) | |
10263 | { | |
10264 | struct i40e_aqc_get_switch_config_resp *sw_config; | |
10265 | u16 next_seid = 0; | |
10266 | int ret = 0; | |
10267 | u8 *aq_buf; | |
10268 | int i; | |
10269 | ||
10270 | aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL); | |
10271 | if (!aq_buf) | |
10272 | return -ENOMEM; | |
10273 | ||
10274 | sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; | |
10275 | do { | |
10276 | u16 num_reported, num_total; | |
10277 | ||
10278 | ret = i40e_aq_get_switch_config(&pf->hw, sw_config, | |
10279 | I40E_AQ_LARGE_BUF, | |
10280 | &next_seid, NULL); | |
10281 | if (ret) { | |
10282 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10283 | "get switch config failed err %s aq_err %s\n", |
10284 | i40e_stat_str(&pf->hw, ret), | |
10285 | i40e_aq_str(&pf->hw, | |
10286 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10287 | kfree(aq_buf); |
10288 | return -ENOENT; | |
10289 | } | |
10290 | ||
10291 | num_reported = le16_to_cpu(sw_config->header.num_reported); | |
10292 | num_total = le16_to_cpu(sw_config->header.num_total); | |
10293 | ||
10294 | if (printconfig) | |
10295 | dev_info(&pf->pdev->dev, | |
10296 | "header: %d reported %d total\n", | |
10297 | num_reported, num_total); | |
10298 | ||
41c445ff JB |
10299 | for (i = 0; i < num_reported; i++) { |
10300 | struct i40e_aqc_switch_config_element_resp *ele = | |
10301 | &sw_config->element[i]; | |
10302 | ||
10303 | i40e_setup_pf_switch_element(pf, ele, num_reported, | |
10304 | printconfig); | |
10305 | } | |
10306 | } while (next_seid != 0); | |
10307 | ||
10308 | kfree(aq_buf); | |
10309 | return ret; | |
10310 | } | |
10311 | ||
10312 | /** | |
10313 | * i40e_setup_pf_switch - Setup the HW switch on startup or after reset | |
10314 | * @pf: board private structure | |
bc7d338f | 10315 | * @reinit: if the Main VSI needs to re-initialized. |
41c445ff JB |
10316 | * |
10317 | * Returns 0 on success, negative value on failure | |
10318 | **/ | |
bc7d338f | 10319 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit) |
41c445ff | 10320 | { |
b5569892 | 10321 | u16 flags = 0; |
41c445ff JB |
10322 | int ret; |
10323 | ||
10324 | /* find out what's out there already */ | |
10325 | ret = i40e_fetch_switch_configuration(pf, false); | |
10326 | if (ret) { | |
10327 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10328 | "couldn't fetch switch config, err %s aq_err %s\n", |
10329 | i40e_stat_str(&pf->hw, ret), | |
10330 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10331 | return ret; |
10332 | } | |
10333 | i40e_pf_reset_stats(pf); | |
10334 | ||
b5569892 ASJ |
10335 | /* set the switch config bit for the whole device to |
10336 | * support limited promisc or true promisc | |
10337 | * when user requests promisc. The default is limited | |
10338 | * promisc. | |
10339 | */ | |
10340 | ||
10341 | if ((pf->hw.pf_id == 0) && | |
10342 | !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT)) | |
10343 | flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; | |
10344 | ||
10345 | if (pf->hw.pf_id == 0) { | |
10346 | u16 valid_flags; | |
10347 | ||
10348 | valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; | |
10349 | ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, | |
10350 | NULL); | |
10351 | if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) { | |
10352 | dev_info(&pf->pdev->dev, | |
10353 | "couldn't set switch config bits, err %s aq_err %s\n", | |
10354 | i40e_stat_str(&pf->hw, ret), | |
10355 | i40e_aq_str(&pf->hw, | |
10356 | pf->hw.aq.asq_last_status)); | |
10357 | /* not a fatal problem, just keep going */ | |
10358 | } | |
10359 | } | |
10360 | ||
41c445ff | 10361 | /* first time setup */ |
bc7d338f | 10362 | if (pf->lan_vsi == I40E_NO_VSI || reinit) { |
41c445ff JB |
10363 | struct i40e_vsi *vsi = NULL; |
10364 | u16 uplink_seid; | |
10365 | ||
10366 | /* Set up the PF VSI associated with the PF's main VSI | |
10367 | * that is already in the HW switch | |
10368 | */ | |
10369 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
10370 | uplink_seid = pf->veb[pf->lan_veb]->seid; | |
10371 | else | |
10372 | uplink_seid = pf->mac_seid; | |
bc7d338f ASJ |
10373 | if (pf->lan_vsi == I40E_NO_VSI) |
10374 | vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0); | |
10375 | else if (reinit) | |
10376 | vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]); | |
41c445ff JB |
10377 | if (!vsi) { |
10378 | dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n"); | |
10379 | i40e_fdir_teardown(pf); | |
10380 | return -EAGAIN; | |
10381 | } | |
41c445ff JB |
10382 | } else { |
10383 | /* force a reset of TC and queue layout configurations */ | |
10384 | u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
6995b36c | 10385 | |
41c445ff JB |
10386 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; |
10387 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
10388 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
10389 | } | |
10390 | i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]); | |
10391 | ||
cbf61325 ASJ |
10392 | i40e_fdir_sb_setup(pf); |
10393 | ||
41c445ff JB |
10394 | /* Setup static PF queue filter control settings */ |
10395 | ret = i40e_setup_pf_filter_control(pf); | |
10396 | if (ret) { | |
10397 | dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n", | |
10398 | ret); | |
10399 | /* Failure here should not stop continuing other steps */ | |
10400 | } | |
10401 | ||
10402 | /* enable RSS in the HW, even for only one queue, as the stack can use | |
10403 | * the hash | |
10404 | */ | |
10405 | if ((pf->flags & I40E_FLAG_RSS_ENABLED)) | |
043dd650 | 10406 | i40e_pf_config_rss(pf); |
41c445ff JB |
10407 | |
10408 | /* fill in link information and enable LSE reporting */ | |
0a862b43 | 10409 | i40e_update_link_info(&pf->hw); |
a34a6711 MW |
10410 | i40e_link_event(pf); |
10411 | ||
d52c20b7 | 10412 | /* Initialize user-specific link properties */ |
41c445ff JB |
10413 | pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info & |
10414 | I40E_AQ_AN_COMPLETED) ? true : false); | |
d52c20b7 | 10415 | |
beb0dff1 JK |
10416 | i40e_ptp_init(pf); |
10417 | ||
41c445ff JB |
10418 | return ret; |
10419 | } | |
10420 | ||
41c445ff JB |
10421 | /** |
10422 | * i40e_determine_queue_usage - Work out queue distribution | |
10423 | * @pf: board private structure | |
10424 | **/ | |
10425 | static void i40e_determine_queue_usage(struct i40e_pf *pf) | |
10426 | { | |
41c445ff JB |
10427 | int queues_left; |
10428 | ||
10429 | pf->num_lan_qps = 0; | |
38e00438 VD |
10430 | #ifdef I40E_FCOE |
10431 | pf->num_fcoe_qps = 0; | |
10432 | #endif | |
41c445ff JB |
10433 | |
10434 | /* Find the max queues to be put into basic use. We'll always be | |
10435 | * using TC0, whether or not DCB is running, and TC0 will get the | |
10436 | * big RSS set. | |
10437 | */ | |
10438 | queues_left = pf->hw.func_caps.num_tx_qp; | |
10439 | ||
cbf61325 | 10440 | if ((queues_left == 1) || |
9aa7e935 | 10441 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) { |
41c445ff JB |
10442 | /* one qp for PF, no queues for anything else */ |
10443 | queues_left = 0; | |
acd65448 | 10444 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
41c445ff JB |
10445 | |
10446 | /* make sure all the fancies are disabled */ | |
60ea5f83 | 10447 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | |
e3219ce6 | 10448 | I40E_FLAG_IWARP_ENABLED | |
38e00438 VD |
10449 | #ifdef I40E_FCOE |
10450 | I40E_FLAG_FCOE_ENABLED | | |
10451 | #endif | |
60ea5f83 JB |
10452 | I40E_FLAG_FD_SB_ENABLED | |
10453 | I40E_FLAG_FD_ATR_ENABLED | | |
4d9b6043 | 10454 | I40E_FLAG_DCB_CAPABLE | |
60ea5f83 JB |
10455 | I40E_FLAG_SRIOV_ENABLED | |
10456 | I40E_FLAG_VMDQ_ENABLED); | |
9aa7e935 FZ |
10457 | } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED | |
10458 | I40E_FLAG_FD_SB_ENABLED | | |
bbe7d0e0 | 10459 | I40E_FLAG_FD_ATR_ENABLED | |
4d9b6043 | 10460 | I40E_FLAG_DCB_CAPABLE))) { |
9aa7e935 | 10461 | /* one qp for PF */ |
acd65448 | 10462 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
9aa7e935 FZ |
10463 | queues_left -= pf->num_lan_qps; |
10464 | ||
10465 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | | |
e3219ce6 | 10466 | I40E_FLAG_IWARP_ENABLED | |
38e00438 VD |
10467 | #ifdef I40E_FCOE |
10468 | I40E_FLAG_FCOE_ENABLED | | |
10469 | #endif | |
9aa7e935 FZ |
10470 | I40E_FLAG_FD_SB_ENABLED | |
10471 | I40E_FLAG_FD_ATR_ENABLED | | |
10472 | I40E_FLAG_DCB_ENABLED | | |
10473 | I40E_FLAG_VMDQ_ENABLED); | |
41c445ff | 10474 | } else { |
cbf61325 | 10475 | /* Not enough queues for all TCs */ |
4d9b6043 | 10476 | if ((pf->flags & I40E_FLAG_DCB_CAPABLE) && |
cbf61325 | 10477 | (queues_left < I40E_MAX_TRAFFIC_CLASS)) { |
4d9b6043 | 10478 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; |
cbf61325 ASJ |
10479 | dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n"); |
10480 | } | |
9a3bd2f1 ASJ |
10481 | pf->num_lan_qps = max_t(int, pf->rss_size_max, |
10482 | num_online_cpus()); | |
10483 | pf->num_lan_qps = min_t(int, pf->num_lan_qps, | |
10484 | pf->hw.func_caps.num_tx_qp); | |
10485 | ||
cbf61325 ASJ |
10486 | queues_left -= pf->num_lan_qps; |
10487 | } | |
10488 | ||
38e00438 VD |
10489 | #ifdef I40E_FCOE |
10490 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) { | |
10491 | if (I40E_DEFAULT_FCOE <= queues_left) { | |
10492 | pf->num_fcoe_qps = I40E_DEFAULT_FCOE; | |
10493 | } else if (I40E_MINIMUM_FCOE <= queues_left) { | |
10494 | pf->num_fcoe_qps = I40E_MINIMUM_FCOE; | |
10495 | } else { | |
10496 | pf->num_fcoe_qps = 0; | |
10497 | pf->flags &= ~I40E_FLAG_FCOE_ENABLED; | |
10498 | dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n"); | |
10499 | } | |
10500 | ||
10501 | queues_left -= pf->num_fcoe_qps; | |
10502 | } | |
10503 | ||
10504 | #endif | |
cbf61325 ASJ |
10505 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
10506 | if (queues_left > 1) { | |
10507 | queues_left -= 1; /* save 1 queue for FD */ | |
10508 | } else { | |
10509 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
10510 | dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n"); | |
10511 | } | |
41c445ff JB |
10512 | } |
10513 | ||
10514 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
10515 | pf->num_vf_qps && pf->num_req_vfs && queues_left) { | |
cbf61325 ASJ |
10516 | pf->num_req_vfs = min_t(int, pf->num_req_vfs, |
10517 | (queues_left / pf->num_vf_qps)); | |
41c445ff JB |
10518 | queues_left -= (pf->num_req_vfs * pf->num_vf_qps); |
10519 | } | |
10520 | ||
10521 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && | |
10522 | pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) { | |
10523 | pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis, | |
10524 | (queues_left / pf->num_vmdq_qps)); | |
10525 | queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps); | |
10526 | } | |
10527 | ||
f8ff1464 | 10528 | pf->queues_left = queues_left; |
8279e495 NP |
10529 | dev_dbg(&pf->pdev->dev, |
10530 | "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n", | |
10531 | pf->hw.func_caps.num_tx_qp, | |
10532 | !!(pf->flags & I40E_FLAG_FD_SB_ENABLED), | |
acd65448 HZ |
10533 | pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs, |
10534 | pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps, | |
10535 | queues_left); | |
38e00438 | 10536 | #ifdef I40E_FCOE |
8279e495 | 10537 | dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps); |
38e00438 | 10538 | #endif |
41c445ff JB |
10539 | } |
10540 | ||
10541 | /** | |
10542 | * i40e_setup_pf_filter_control - Setup PF static filter control | |
10543 | * @pf: PF to be setup | |
10544 | * | |
b40c82e6 | 10545 | * i40e_setup_pf_filter_control sets up a PF's initial filter control |
41c445ff JB |
10546 | * settings. If PE/FCoE are enabled then it will also set the per PF |
10547 | * based filter sizes required for them. It also enables Flow director, | |
10548 | * ethertype and macvlan type filter settings for the pf. | |
10549 | * | |
10550 | * Returns 0 on success, negative on failure | |
10551 | **/ | |
10552 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf) | |
10553 | { | |
10554 | struct i40e_filter_control_settings *settings = &pf->filter_settings; | |
10555 | ||
10556 | settings->hash_lut_size = I40E_HASH_LUT_SIZE_128; | |
10557 | ||
10558 | /* Flow Director is enabled */ | |
60ea5f83 | 10559 | if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)) |
41c445ff JB |
10560 | settings->enable_fdir = true; |
10561 | ||
10562 | /* Ethtype and MACVLAN filters enabled for PF */ | |
10563 | settings->enable_ethtype = true; | |
10564 | settings->enable_macvlan = true; | |
10565 | ||
10566 | if (i40e_set_filter_control(&pf->hw, settings)) | |
10567 | return -ENOENT; | |
10568 | ||
10569 | return 0; | |
10570 | } | |
10571 | ||
0c22b3dd | 10572 | #define INFO_STRING_LEN 255 |
7fd89545 | 10573 | #define REMAIN(__x) (INFO_STRING_LEN - (__x)) |
0c22b3dd JB |
10574 | static void i40e_print_features(struct i40e_pf *pf) |
10575 | { | |
10576 | struct i40e_hw *hw = &pf->hw; | |
3b195843 JP |
10577 | char *buf; |
10578 | int i; | |
0c22b3dd | 10579 | |
3b195843 JP |
10580 | buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL); |
10581 | if (!buf) | |
0c22b3dd | 10582 | return; |
0c22b3dd | 10583 | |
3b195843 | 10584 | i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id); |
0c22b3dd | 10585 | #ifdef CONFIG_PCI_IOV |
3b195843 | 10586 | i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs); |
0c22b3dd | 10587 | #endif |
1a557afc | 10588 | i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d", |
7fd89545 | 10589 | pf->hw.func_caps.num_vsis, |
1a557afc | 10590 | pf->vsi[pf->lan_vsi]->num_queue_pairs); |
0c22b3dd | 10591 | if (pf->flags & I40E_FLAG_RSS_ENABLED) |
3b195843 | 10592 | i += snprintf(&buf[i], REMAIN(i), " RSS"); |
0c22b3dd | 10593 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) |
3b195843 | 10594 | i += snprintf(&buf[i], REMAIN(i), " FD_ATR"); |
c6423ff1 | 10595 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
3b195843 JP |
10596 | i += snprintf(&buf[i], REMAIN(i), " FD_SB"); |
10597 | i += snprintf(&buf[i], REMAIN(i), " NTUPLE"); | |
c6423ff1 | 10598 | } |
4d9b6043 | 10599 | if (pf->flags & I40E_FLAG_DCB_CAPABLE) |
3b195843 | 10600 | i += snprintf(&buf[i], REMAIN(i), " DCB"); |
3b195843 | 10601 | i += snprintf(&buf[i], REMAIN(i), " VxLAN"); |
6a899024 | 10602 | i += snprintf(&buf[i], REMAIN(i), " Geneve"); |
0c22b3dd | 10603 | if (pf->flags & I40E_FLAG_PTP) |
3b195843 | 10604 | i += snprintf(&buf[i], REMAIN(i), " PTP"); |
38e00438 VD |
10605 | #ifdef I40E_FCOE |
10606 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) | |
3b195843 | 10607 | i += snprintf(&buf[i], REMAIN(i), " FCOE"); |
38e00438 | 10608 | #endif |
6dec1017 | 10609 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
3b195843 | 10610 | i += snprintf(&buf[i], REMAIN(i), " VEB"); |
6dec1017 | 10611 | else |
3b195843 | 10612 | i += snprintf(&buf[i], REMAIN(i), " VEPA"); |
0c22b3dd | 10613 | |
3b195843 JP |
10614 | dev_info(&pf->pdev->dev, "%s\n", buf); |
10615 | kfree(buf); | |
7fd89545 | 10616 | WARN_ON(i > INFO_STRING_LEN); |
0c22b3dd JB |
10617 | } |
10618 | ||
b499ffb0 SV |
10619 | /** |
10620 | * i40e_get_platform_mac_addr - get platform-specific MAC address | |
10621 | * | |
10622 | * @pdev: PCI device information struct | |
10623 | * @pf: board private structure | |
10624 | * | |
10625 | * Look up the MAC address in Open Firmware on systems that support it, | |
10626 | * and use IDPROM on SPARC if no OF address is found. On return, the | |
10627 | * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value | |
10628 | * has been selected. | |
10629 | **/ | |
10630 | static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf) | |
10631 | { | |
b499ffb0 | 10632 | pf->flags &= ~I40E_FLAG_PF_MAC; |
ba94272d | 10633 | if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr)) |
b499ffb0 | 10634 | pf->flags |= I40E_FLAG_PF_MAC; |
b499ffb0 SV |
10635 | } |
10636 | ||
41c445ff JB |
10637 | /** |
10638 | * i40e_probe - Device initialization routine | |
10639 | * @pdev: PCI device information struct | |
10640 | * @ent: entry in i40e_pci_tbl | |
10641 | * | |
b40c82e6 JK |
10642 | * i40e_probe initializes a PF identified by a pci_dev structure. |
10643 | * The OS initialization, configuring of the PF private structure, | |
41c445ff JB |
10644 | * and a hardware reset occur. |
10645 | * | |
10646 | * Returns 0 on success, negative on failure | |
10647 | **/ | |
10648 | static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
10649 | { | |
e827845c | 10650 | struct i40e_aq_get_phy_abilities_resp abilities; |
41c445ff JB |
10651 | struct i40e_pf *pf; |
10652 | struct i40e_hw *hw; | |
93cd765b | 10653 | static u16 pfs_found; |
1d5109d1 | 10654 | u16 wol_nvm_bits; |
d4dfb81a | 10655 | u16 link_status; |
6f66a484 | 10656 | int err; |
4f2f017c | 10657 | u32 val; |
8a9eb7d3 | 10658 | u32 i; |
58fc3267 | 10659 | u8 set_fc_aq_fail; |
41c445ff JB |
10660 | |
10661 | err = pci_enable_device_mem(pdev); | |
10662 | if (err) | |
10663 | return err; | |
10664 | ||
10665 | /* set up for high or low dma */ | |
6494294f | 10666 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
6494294f | 10667 | if (err) { |
e3e3bfdd JS |
10668 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
10669 | if (err) { | |
10670 | dev_err(&pdev->dev, | |
10671 | "DMA configuration failed: 0x%x\n", err); | |
10672 | goto err_dma; | |
10673 | } | |
41c445ff JB |
10674 | } |
10675 | ||
10676 | /* set up pci connections */ | |
10677 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, | |
10678 | IORESOURCE_MEM), i40e_driver_name); | |
10679 | if (err) { | |
10680 | dev_info(&pdev->dev, | |
10681 | "pci_request_selected_regions failed %d\n", err); | |
10682 | goto err_pci_reg; | |
10683 | } | |
10684 | ||
10685 | pci_enable_pcie_error_reporting(pdev); | |
10686 | pci_set_master(pdev); | |
10687 | ||
10688 | /* Now that we have a PCI connection, we need to do the | |
10689 | * low level device setup. This is primarily setting up | |
10690 | * the Admin Queue structures and then querying for the | |
10691 | * device's current profile information. | |
10692 | */ | |
10693 | pf = kzalloc(sizeof(*pf), GFP_KERNEL); | |
10694 | if (!pf) { | |
10695 | err = -ENOMEM; | |
10696 | goto err_pf_alloc; | |
10697 | } | |
10698 | pf->next_vsi = 0; | |
10699 | pf->pdev = pdev; | |
10700 | set_bit(__I40E_DOWN, &pf->state); | |
10701 | ||
10702 | hw = &pf->hw; | |
10703 | hw->back = pf; | |
232f4706 | 10704 | |
2ac8b675 SN |
10705 | pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0), |
10706 | I40E_MAX_CSR_SPACE); | |
232f4706 | 10707 | |
2ac8b675 | 10708 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len); |
41c445ff JB |
10709 | if (!hw->hw_addr) { |
10710 | err = -EIO; | |
10711 | dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n", | |
10712 | (unsigned int)pci_resource_start(pdev, 0), | |
2ac8b675 | 10713 | pf->ioremap_len, err); |
41c445ff JB |
10714 | goto err_ioremap; |
10715 | } | |
10716 | hw->vendor_id = pdev->vendor; | |
10717 | hw->device_id = pdev->device; | |
10718 | pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); | |
10719 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
10720 | hw->subsystem_device_id = pdev->subsystem_device; | |
10721 | hw->bus.device = PCI_SLOT(pdev->devfn); | |
10722 | hw->bus.func = PCI_FUNC(pdev->devfn); | |
93cd765b | 10723 | pf->instance = pfs_found; |
41c445ff | 10724 | |
de03d2b0 SN |
10725 | /* set up the locks for the AQ, do this only once in probe |
10726 | * and destroy them only once in remove | |
10727 | */ | |
10728 | mutex_init(&hw->aq.asq_mutex); | |
10729 | mutex_init(&hw->aq.arq_mutex); | |
10730 | ||
5b5faa43 SN |
10731 | if (debug != -1) { |
10732 | pf->msg_enable = pf->hw.debug_mask; | |
10733 | pf->msg_enable = debug; | |
10734 | } | |
10735 | ||
7134f9ce JB |
10736 | /* do a special CORER for clearing PXE mode once at init */ |
10737 | if (hw->revision_id == 0 && | |
10738 | (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) { | |
10739 | wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK); | |
10740 | i40e_flush(hw); | |
10741 | msleep(200); | |
10742 | pf->corer_count++; | |
10743 | ||
10744 | i40e_clear_pxe_mode(hw); | |
10745 | } | |
10746 | ||
41c445ff | 10747 | /* Reset here to make sure all is clean and to define PF 'n' */ |
838d41d9 | 10748 | i40e_clear_hw(hw); |
41c445ff JB |
10749 | err = i40e_pf_reset(hw); |
10750 | if (err) { | |
10751 | dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err); | |
10752 | goto err_pf_reset; | |
10753 | } | |
10754 | pf->pfr_count++; | |
10755 | ||
10756 | hw->aq.num_arq_entries = I40E_AQ_LEN; | |
10757 | hw->aq.num_asq_entries = I40E_AQ_LEN; | |
10758 | hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
10759 | hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
10760 | pf->adminq_work_limit = I40E_AQ_WORK_LIMIT; | |
b2008cbf | 10761 | |
b294ac70 | 10762 | snprintf(pf->int_name, sizeof(pf->int_name) - 1, |
b2008cbf CW |
10763 | "%s-%s:misc", |
10764 | dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev)); | |
41c445ff JB |
10765 | |
10766 | err = i40e_init_shared_code(hw); | |
10767 | if (err) { | |
b2a75c58 ASJ |
10768 | dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n", |
10769 | err); | |
41c445ff JB |
10770 | goto err_pf_reset; |
10771 | } | |
10772 | ||
d52c20b7 JB |
10773 | /* set up a default setting for link flow control */ |
10774 | pf->hw.fc.requested_mode = I40E_FC_NONE; | |
10775 | ||
41c445ff | 10776 | err = i40e_init_adminq(hw); |
2b2426a7 CW |
10777 | if (err) { |
10778 | if (err == I40E_ERR_FIRMWARE_API_VERSION) | |
10779 | dev_info(&pdev->dev, | |
10780 | "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n"); | |
10781 | else | |
10782 | dev_info(&pdev->dev, | |
10783 | "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n"); | |
10784 | ||
10785 | goto err_pf_reset; | |
10786 | } | |
f0b44440 | 10787 | |
6dec1017 SN |
10788 | /* provide nvm, fw, api versions */ |
10789 | dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n", | |
10790 | hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build, | |
10791 | hw->aq.api_maj_ver, hw->aq.api_min_ver, | |
10792 | i40e_nvm_version_str(hw)); | |
f0b44440 | 10793 | |
7aa67613 CS |
10794 | if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && |
10795 | hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR) | |
278b6f62 | 10796 | dev_info(&pdev->dev, |
7aa67613 CS |
10797 | "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n"); |
10798 | else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR || | |
10799 | hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1)) | |
278b6f62 | 10800 | dev_info(&pdev->dev, |
7aa67613 | 10801 | "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n"); |
278b6f62 | 10802 | |
4eb3f768 SN |
10803 | i40e_verify_eeprom(pf); |
10804 | ||
2c5fe33b JB |
10805 | /* Rev 0 hardware was never productized */ |
10806 | if (hw->revision_id < 1) | |
10807 | dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); | |
10808 | ||
6ff4ef86 | 10809 | i40e_clear_pxe_mode(hw); |
41c445ff JB |
10810 | err = i40e_get_capabilities(pf); |
10811 | if (err) | |
10812 | goto err_adminq_setup; | |
10813 | ||
10814 | err = i40e_sw_init(pf); | |
10815 | if (err) { | |
10816 | dev_info(&pdev->dev, "sw_init failed: %d\n", err); | |
10817 | goto err_sw_init; | |
10818 | } | |
10819 | ||
10820 | err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, | |
10821 | hw->func_caps.num_rx_qp, | |
10822 | pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num); | |
10823 | if (err) { | |
10824 | dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err); | |
10825 | goto err_init_lan_hmc; | |
10826 | } | |
10827 | ||
10828 | err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
10829 | if (err) { | |
10830 | dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err); | |
10831 | err = -ENOENT; | |
10832 | goto err_configure_lan_hmc; | |
10833 | } | |
10834 | ||
b686ece5 NP |
10835 | /* Disable LLDP for NICs that have firmware versions lower than v4.3. |
10836 | * Ignore error return codes because if it was already disabled via | |
10837 | * hardware settings this will fail | |
10838 | */ | |
f1bbad33 | 10839 | if (pf->flags & I40E_FLAG_STOP_FW_LLDP) { |
b686ece5 NP |
10840 | dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n"); |
10841 | i40e_aq_stop_lldp(hw, true, NULL); | |
10842 | } | |
10843 | ||
41c445ff | 10844 | i40e_get_mac_addr(hw, hw->mac.addr); |
b499ffb0 SV |
10845 | /* allow a platform config to override the HW addr */ |
10846 | i40e_get_platform_mac_addr(pdev, pf); | |
f62b5060 | 10847 | if (!is_valid_ether_addr(hw->mac.addr)) { |
41c445ff JB |
10848 | dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr); |
10849 | err = -EIO; | |
10850 | goto err_mac_addr; | |
10851 | } | |
10852 | dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr); | |
9a173901 | 10853 | ether_addr_copy(hw->mac.perm_addr, hw->mac.addr); |
1f224ad2 NP |
10854 | i40e_get_port_mac_addr(hw, hw->mac.port_addr); |
10855 | if (is_valid_ether_addr(hw->mac.port_addr)) | |
10856 | pf->flags |= I40E_FLAG_PORT_ID_VALID; | |
38e00438 VD |
10857 | #ifdef I40E_FCOE |
10858 | err = i40e_get_san_mac_addr(hw, hw->mac.san_addr); | |
10859 | if (err) | |
10860 | dev_info(&pdev->dev, | |
10861 | "(non-fatal) SAN MAC retrieval failed: %d\n", err); | |
10862 | if (!is_valid_ether_addr(hw->mac.san_addr)) { | |
10863 | dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n", | |
10864 | hw->mac.san_addr); | |
10865 | ether_addr_copy(hw->mac.san_addr, hw->mac.addr); | |
10866 | } | |
10867 | dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr); | |
10868 | #endif /* I40E_FCOE */ | |
41c445ff JB |
10869 | |
10870 | pci_set_drvdata(pdev, pf); | |
10871 | pci_save_state(pdev); | |
4e3b35b0 NP |
10872 | #ifdef CONFIG_I40E_DCB |
10873 | err = i40e_init_pf_dcb(pf); | |
10874 | if (err) { | |
aebfc816 | 10875 | dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err); |
4d9b6043 | 10876 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; |
014269ff | 10877 | /* Continue without DCB enabled */ |
4e3b35b0 NP |
10878 | } |
10879 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
10880 | |
10881 | /* set up periodic task facility */ | |
10882 | setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf); | |
10883 | pf->service_timer_period = HZ; | |
10884 | ||
10885 | INIT_WORK(&pf->service_task, i40e_service_task); | |
10886 | clear_bit(__I40E_SERVICE_SCHED, &pf->state); | |
10887 | pf->flags |= I40E_FLAG_NEED_LINK_UPDATE; | |
41c445ff | 10888 | |
1d5109d1 SN |
10889 | /* NVM bit on means WoL disabled for the port */ |
10890 | i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits); | |
75f5cea9 | 10891 | if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1) |
1d5109d1 SN |
10892 | pf->wol_en = false; |
10893 | else | |
10894 | pf->wol_en = true; | |
8e2773ae SN |
10895 | device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en); |
10896 | ||
41c445ff JB |
10897 | /* set up the main switch operations */ |
10898 | i40e_determine_queue_usage(pf); | |
c1147280 JB |
10899 | err = i40e_init_interrupt_scheme(pf); |
10900 | if (err) | |
10901 | goto err_switch_setup; | |
41c445ff | 10902 | |
505682cd MW |
10903 | /* The number of VSIs reported by the FW is the minimum guaranteed |
10904 | * to us; HW supports far more and we share the remaining pool with | |
10905 | * the other PFs. We allocate space for more than the guarantee with | |
10906 | * the understanding that we might not get them all later. | |
41c445ff | 10907 | */ |
505682cd MW |
10908 | if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC) |
10909 | pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC; | |
10910 | else | |
10911 | pf->num_alloc_vsi = pf->hw.func_caps.num_vsis; | |
10912 | ||
10913 | /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */ | |
d17038d6 JB |
10914 | pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *), |
10915 | GFP_KERNEL); | |
ed87ac09 WY |
10916 | if (!pf->vsi) { |
10917 | err = -ENOMEM; | |
41c445ff | 10918 | goto err_switch_setup; |
ed87ac09 | 10919 | } |
41c445ff | 10920 | |
fa11cb3d ASJ |
10921 | #ifdef CONFIG_PCI_IOV |
10922 | /* prep for VF support */ | |
10923 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
10924 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
10925 | !test_bit(__I40E_BAD_EEPROM, &pf->state)) { | |
10926 | if (pci_num_vf(pdev)) | |
10927 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
10928 | } | |
10929 | #endif | |
bc7d338f | 10930 | err = i40e_setup_pf_switch(pf, false); |
41c445ff JB |
10931 | if (err) { |
10932 | dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err); | |
10933 | goto err_vsis; | |
10934 | } | |
58fc3267 HZ |
10935 | |
10936 | /* Make sure flow control is set according to current settings */ | |
10937 | err = i40e_set_fc(hw, &set_fc_aq_fail, true); | |
10938 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET) | |
10939 | dev_dbg(&pf->pdev->dev, | |
10940 | "Set fc with err %s aq_err %s on get_phy_cap\n", | |
10941 | i40e_stat_str(hw, err), | |
10942 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
10943 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET) | |
10944 | dev_dbg(&pf->pdev->dev, | |
10945 | "Set fc with err %s aq_err %s on set_phy_config\n", | |
10946 | i40e_stat_str(hw, err), | |
10947 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
10948 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE) | |
10949 | dev_dbg(&pf->pdev->dev, | |
10950 | "Set fc with err %s aq_err %s on get_link_info\n", | |
10951 | i40e_stat_str(hw, err), | |
10952 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
10953 | ||
8a9eb7d3 | 10954 | /* if FDIR VSI was set up, start it now */ |
505682cd | 10955 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
8a9eb7d3 SN |
10956 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { |
10957 | i40e_vsi_open(pf->vsi[i]); | |
10958 | break; | |
10959 | } | |
10960 | } | |
41c445ff | 10961 | |
2f0aff41 SN |
10962 | /* The driver only wants link up/down and module qualification |
10963 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
10964 | */ |
10965 | err = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 10966 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 10967 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 10968 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 10969 | if (err) |
f1c7e72e SN |
10970 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
10971 | i40e_stat_str(&pf->hw, err), | |
10972 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 10973 | |
4f2f017c ASJ |
10974 | /* Reconfigure hardware for allowing smaller MSS in the case |
10975 | * of TSO, so that we avoid the MDD being fired and causing | |
10976 | * a reset in the case of small MSS+TSO. | |
10977 | */ | |
10978 | val = rd32(hw, I40E_REG_MSS); | |
10979 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
10980 | val &= ~I40E_REG_MSS_MIN_MASK; | |
10981 | val |= I40E_64BYTE_MSS; | |
10982 | wr32(hw, I40E_REG_MSS, val); | |
10983 | } | |
10984 | ||
8eed76fa | 10985 | if (pf->flags & I40E_FLAG_RESTART_AUTONEG) { |
025b4a54 ASJ |
10986 | msleep(75); |
10987 | err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
10988 | if (err) | |
f1c7e72e SN |
10989 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
10990 | i40e_stat_str(&pf->hw, err), | |
10991 | i40e_aq_str(&pf->hw, | |
10992 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 10993 | } |
41c445ff JB |
10994 | /* The main driver is (mostly) up and happy. We need to set this state |
10995 | * before setting up the misc vector or we get a race and the vector | |
10996 | * ends up disabled forever. | |
10997 | */ | |
10998 | clear_bit(__I40E_DOWN, &pf->state); | |
10999 | ||
11000 | /* In case of MSIX we are going to setup the misc vector right here | |
11001 | * to handle admin queue events etc. In case of legacy and MSI | |
11002 | * the misc functionality and queue processing is combined in | |
11003 | * the same vector and that gets setup at open. | |
11004 | */ | |
11005 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
11006 | err = i40e_setup_misc_vector(pf); | |
11007 | if (err) { | |
11008 | dev_info(&pdev->dev, | |
11009 | "setup of misc vector failed: %d\n", err); | |
11010 | goto err_vsis; | |
11011 | } | |
11012 | } | |
11013 | ||
df805f62 | 11014 | #ifdef CONFIG_PCI_IOV |
41c445ff JB |
11015 | /* prep for VF support */ |
11016 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
4eb3f768 SN |
11017 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && |
11018 | !test_bit(__I40E_BAD_EEPROM, &pf->state)) { | |
41c445ff JB |
11019 | /* disable link interrupts for VFs */ |
11020 | val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM); | |
11021 | val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK; | |
11022 | wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val); | |
11023 | i40e_flush(hw); | |
4aeec010 MW |
11024 | |
11025 | if (pci_num_vf(pdev)) { | |
11026 | dev_info(&pdev->dev, | |
11027 | "Active VFs found, allocating resources.\n"); | |
11028 | err = i40e_alloc_vfs(pf, pci_num_vf(pdev)); | |
11029 | if (err) | |
11030 | dev_info(&pdev->dev, | |
11031 | "Error %d allocating resources for existing VFs\n", | |
11032 | err); | |
11033 | } | |
41c445ff | 11034 | } |
df805f62 | 11035 | #endif /* CONFIG_PCI_IOV */ |
41c445ff | 11036 | |
e3219ce6 ASJ |
11037 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
11038 | pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile, | |
11039 | pf->num_iwarp_msix, | |
11040 | I40E_IWARP_IRQ_PILE_ID); | |
11041 | if (pf->iwarp_base_vector < 0) { | |
11042 | dev_info(&pdev->dev, | |
11043 | "failed to get tracking for %d vectors for IWARP err=%d\n", | |
11044 | pf->num_iwarp_msix, pf->iwarp_base_vector); | |
11045 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
11046 | } | |
11047 | } | |
93cd765b | 11048 | |
41c445ff JB |
11049 | i40e_dbg_pf_init(pf); |
11050 | ||
11051 | /* tell the firmware that we're starting */ | |
44033fac | 11052 | i40e_send_version(pf); |
41c445ff JB |
11053 | |
11054 | /* since everything's happy, start the service_task timer */ | |
11055 | mod_timer(&pf->service_timer, | |
11056 | round_jiffies(jiffies + pf->service_timer_period)); | |
11057 | ||
e3219ce6 ASJ |
11058 | /* add this PF to client device list and launch a client service task */ |
11059 | err = i40e_lan_add_device(pf); | |
11060 | if (err) | |
11061 | dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n", | |
11062 | err); | |
11063 | ||
38e00438 VD |
11064 | #ifdef I40E_FCOE |
11065 | /* create FCoE interface */ | |
11066 | i40e_fcoe_vsi_setup(pf); | |
11067 | ||
11068 | #endif | |
3fced535 ASJ |
11069 | #define PCI_SPEED_SIZE 8 |
11070 | #define PCI_WIDTH_SIZE 8 | |
11071 | /* Devices on the IOSF bus do not have this information | |
11072 | * and will report PCI Gen 1 x 1 by default so don't bother | |
11073 | * checking them. | |
11074 | */ | |
11075 | if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) { | |
11076 | char speed[PCI_SPEED_SIZE] = "Unknown"; | |
11077 | char width[PCI_WIDTH_SIZE] = "Unknown"; | |
11078 | ||
11079 | /* Get the negotiated link width and speed from PCI config | |
11080 | * space | |
11081 | */ | |
11082 | pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, | |
11083 | &link_status); | |
11084 | ||
11085 | i40e_set_pci_config_data(hw, link_status); | |
11086 | ||
11087 | switch (hw->bus.speed) { | |
11088 | case i40e_bus_speed_8000: | |
11089 | strncpy(speed, "8.0", PCI_SPEED_SIZE); break; | |
11090 | case i40e_bus_speed_5000: | |
11091 | strncpy(speed, "5.0", PCI_SPEED_SIZE); break; | |
11092 | case i40e_bus_speed_2500: | |
11093 | strncpy(speed, "2.5", PCI_SPEED_SIZE); break; | |
11094 | default: | |
11095 | break; | |
11096 | } | |
11097 | switch (hw->bus.width) { | |
11098 | case i40e_bus_width_pcie_x8: | |
11099 | strncpy(width, "8", PCI_WIDTH_SIZE); break; | |
11100 | case i40e_bus_width_pcie_x4: | |
11101 | strncpy(width, "4", PCI_WIDTH_SIZE); break; | |
11102 | case i40e_bus_width_pcie_x2: | |
11103 | strncpy(width, "2", PCI_WIDTH_SIZE); break; | |
11104 | case i40e_bus_width_pcie_x1: | |
11105 | strncpy(width, "1", PCI_WIDTH_SIZE); break; | |
11106 | default: | |
11107 | break; | |
11108 | } | |
11109 | ||
11110 | dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n", | |
11111 | speed, width); | |
11112 | ||
11113 | if (hw->bus.width < i40e_bus_width_pcie_x8 || | |
11114 | hw->bus.speed < i40e_bus_speed_8000) { | |
11115 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n"); | |
11116 | dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n"); | |
11117 | } | |
d4dfb81a CS |
11118 | } |
11119 | ||
e827845c CS |
11120 | /* get the requested speeds from the fw */ |
11121 | err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL); | |
11122 | if (err) | |
8279e495 NP |
11123 | dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n", |
11124 | i40e_stat_str(&pf->hw, err), | |
11125 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
e827845c CS |
11126 | pf->hw.phy.link_info.requested_speeds = abilities.link_speed; |
11127 | ||
fc72dbce CS |
11128 | /* get the supported phy types from the fw */ |
11129 | err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL); | |
11130 | if (err) | |
11131 | dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n", | |
11132 | i40e_stat_str(&pf->hw, err), | |
11133 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
11134 | pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type); | |
11135 | ||
e7358f54 ASJ |
11136 | /* Add a filter to drop all Flow control frames from any VSI from being |
11137 | * transmitted. By doing so we stop a malicious VF from sending out | |
11138 | * PAUSE or PFC frames and potentially controlling traffic for other | |
11139 | * PF/VF VSIs. | |
11140 | * The FW can still send Flow control frames if enabled. | |
11141 | */ | |
11142 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
11143 | pf->main_vsi_seid); | |
11144 | ||
31b606d0 CW |
11145 | if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) || |
11146 | (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4)) | |
11147 | pf->flags |= I40E_FLAG_HAVE_10GBASET_PHY; | |
11148 | ||
0c22b3dd JB |
11149 | /* print a string summarizing features */ |
11150 | i40e_print_features(pf); | |
11151 | ||
41c445ff JB |
11152 | return 0; |
11153 | ||
11154 | /* Unwind what we've done if something failed in the setup */ | |
11155 | err_vsis: | |
11156 | set_bit(__I40E_DOWN, &pf->state); | |
41c445ff JB |
11157 | i40e_clear_interrupt_scheme(pf); |
11158 | kfree(pf->vsi); | |
04b03013 SN |
11159 | err_switch_setup: |
11160 | i40e_reset_interrupt_capability(pf); | |
41c445ff JB |
11161 | del_timer_sync(&pf->service_timer); |
11162 | err_mac_addr: | |
11163 | err_configure_lan_hmc: | |
11164 | (void)i40e_shutdown_lan_hmc(hw); | |
11165 | err_init_lan_hmc: | |
11166 | kfree(pf->qp_pile); | |
41c445ff JB |
11167 | err_sw_init: |
11168 | err_adminq_setup: | |
41c445ff JB |
11169 | err_pf_reset: |
11170 | iounmap(hw->hw_addr); | |
11171 | err_ioremap: | |
11172 | kfree(pf); | |
11173 | err_pf_alloc: | |
11174 | pci_disable_pcie_error_reporting(pdev); | |
11175 | pci_release_selected_regions(pdev, | |
11176 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
11177 | err_pci_reg: | |
11178 | err_dma: | |
11179 | pci_disable_device(pdev); | |
11180 | return err; | |
11181 | } | |
11182 | ||
11183 | /** | |
11184 | * i40e_remove - Device removal routine | |
11185 | * @pdev: PCI device information struct | |
11186 | * | |
11187 | * i40e_remove is called by the PCI subsystem to alert the driver | |
11188 | * that is should release a PCI device. This could be caused by a | |
11189 | * Hot-Plug event, or because the driver is going to be removed from | |
11190 | * memory. | |
11191 | **/ | |
11192 | static void i40e_remove(struct pci_dev *pdev) | |
11193 | { | |
11194 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
bcab2db9 | 11195 | struct i40e_hw *hw = &pf->hw; |
41c445ff | 11196 | i40e_status ret_code; |
41c445ff JB |
11197 | int i; |
11198 | ||
11199 | i40e_dbg_pf_exit(pf); | |
11200 | ||
beb0dff1 JK |
11201 | i40e_ptp_stop(pf); |
11202 | ||
bcab2db9 | 11203 | /* Disable RSS in hw */ |
272cdaf2 SN |
11204 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); |
11205 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); | |
bcab2db9 | 11206 | |
41c445ff | 11207 | /* no more scheduling of any task */ |
a4618ec8 | 11208 | set_bit(__I40E_SUSPENDED, &pf->state); |
41c445ff | 11209 | set_bit(__I40E_DOWN, &pf->state); |
c99abb4c SN |
11210 | if (pf->service_timer.data) |
11211 | del_timer_sync(&pf->service_timer); | |
11212 | if (pf->service_task.func) | |
11213 | cancel_work_sync(&pf->service_task); | |
41c445ff | 11214 | |
eb2d80bc MW |
11215 | if (pf->flags & I40E_FLAG_SRIOV_ENABLED) { |
11216 | i40e_free_vfs(pf); | |
11217 | pf->flags &= ~I40E_FLAG_SRIOV_ENABLED; | |
11218 | } | |
11219 | ||
41c445ff JB |
11220 | i40e_fdir_teardown(pf); |
11221 | ||
11222 | /* If there is a switch structure or any orphans, remove them. | |
11223 | * This will leave only the PF's VSI remaining. | |
11224 | */ | |
11225 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
11226 | if (!pf->veb[i]) | |
11227 | continue; | |
11228 | ||
11229 | if (pf->veb[i]->uplink_seid == pf->mac_seid || | |
11230 | pf->veb[i]->uplink_seid == 0) | |
11231 | i40e_switch_branch_release(pf->veb[i]); | |
11232 | } | |
11233 | ||
11234 | /* Now we can shutdown the PF's VSI, just before we kill | |
11235 | * adminq and hmc. | |
11236 | */ | |
11237 | if (pf->vsi[pf->lan_vsi]) | |
11238 | i40e_vsi_release(pf->vsi[pf->lan_vsi]); | |
11239 | ||
e3219ce6 ASJ |
11240 | /* remove attached clients */ |
11241 | ret_code = i40e_lan_del_device(pf); | |
11242 | if (ret_code) { | |
11243 | dev_warn(&pdev->dev, "Failed to delete client device: %d\n", | |
11244 | ret_code); | |
11245 | } | |
11246 | ||
41c445ff | 11247 | /* shutdown and destroy the HMC */ |
f734dfff JB |
11248 | if (hw->hmc.hmc_obj) { |
11249 | ret_code = i40e_shutdown_lan_hmc(hw); | |
60442dea SN |
11250 | if (ret_code) |
11251 | dev_warn(&pdev->dev, | |
11252 | "Failed to destroy the HMC resources: %d\n", | |
11253 | ret_code); | |
11254 | } | |
41c445ff JB |
11255 | |
11256 | /* shutdown the adminq */ | |
f734dfff | 11257 | ret_code = i40e_shutdown_adminq(hw); |
41c445ff JB |
11258 | if (ret_code) |
11259 | dev_warn(&pdev->dev, | |
11260 | "Failed to destroy the Admin Queue resources: %d\n", | |
11261 | ret_code); | |
11262 | ||
8ddb3326 JB |
11263 | /* destroy the locks only once, here */ |
11264 | mutex_destroy(&hw->aq.arq_mutex); | |
11265 | mutex_destroy(&hw->aq.asq_mutex); | |
11266 | ||
41c445ff JB |
11267 | /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */ |
11268 | i40e_clear_interrupt_scheme(pf); | |
505682cd | 11269 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
11270 | if (pf->vsi[i]) { |
11271 | i40e_vsi_clear_rings(pf->vsi[i]); | |
11272 | i40e_vsi_clear(pf->vsi[i]); | |
11273 | pf->vsi[i] = NULL; | |
11274 | } | |
11275 | } | |
11276 | ||
11277 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
11278 | kfree(pf->veb[i]); | |
11279 | pf->veb[i] = NULL; | |
11280 | } | |
11281 | ||
11282 | kfree(pf->qp_pile); | |
41c445ff JB |
11283 | kfree(pf->vsi); |
11284 | ||
f734dfff | 11285 | iounmap(hw->hw_addr); |
41c445ff JB |
11286 | kfree(pf); |
11287 | pci_release_selected_regions(pdev, | |
11288 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
11289 | ||
11290 | pci_disable_pcie_error_reporting(pdev); | |
11291 | pci_disable_device(pdev); | |
11292 | } | |
11293 | ||
11294 | /** | |
11295 | * i40e_pci_error_detected - warning that something funky happened in PCI land | |
11296 | * @pdev: PCI device information struct | |
11297 | * | |
11298 | * Called to warn that something happened and the error handling steps | |
11299 | * are in progress. Allows the driver to quiesce things, be ready for | |
11300 | * remediation. | |
11301 | **/ | |
11302 | static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev, | |
11303 | enum pci_channel_state error) | |
11304 | { | |
11305 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
11306 | ||
11307 | dev_info(&pdev->dev, "%s: error %d\n", __func__, error); | |
11308 | ||
11309 | /* shutdown all operations */ | |
9007bccd SN |
11310 | if (!test_bit(__I40E_SUSPENDED, &pf->state)) { |
11311 | rtnl_lock(); | |
11312 | i40e_prep_for_reset(pf); | |
11313 | rtnl_unlock(); | |
11314 | } | |
41c445ff JB |
11315 | |
11316 | /* Request a slot reset */ | |
11317 | return PCI_ERS_RESULT_NEED_RESET; | |
11318 | } | |
11319 | ||
11320 | /** | |
11321 | * i40e_pci_error_slot_reset - a PCI slot reset just happened | |
11322 | * @pdev: PCI device information struct | |
11323 | * | |
11324 | * Called to find if the driver can work with the device now that | |
11325 | * the pci slot has been reset. If a basic connection seems good | |
11326 | * (registers are readable and have sane content) then return a | |
11327 | * happy little PCI_ERS_RESULT_xxx. | |
11328 | **/ | |
11329 | static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev) | |
11330 | { | |
11331 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
11332 | pci_ers_result_t result; | |
11333 | int err; | |
11334 | u32 reg; | |
11335 | ||
fb43201f | 11336 | dev_dbg(&pdev->dev, "%s\n", __func__); |
41c445ff JB |
11337 | if (pci_enable_device_mem(pdev)) { |
11338 | dev_info(&pdev->dev, | |
11339 | "Cannot re-enable PCI device after reset.\n"); | |
11340 | result = PCI_ERS_RESULT_DISCONNECT; | |
11341 | } else { | |
11342 | pci_set_master(pdev); | |
11343 | pci_restore_state(pdev); | |
11344 | pci_save_state(pdev); | |
11345 | pci_wake_from_d3(pdev, false); | |
11346 | ||
11347 | reg = rd32(&pf->hw, I40E_GLGEN_RTRIG); | |
11348 | if (reg == 0) | |
11349 | result = PCI_ERS_RESULT_RECOVERED; | |
11350 | else | |
11351 | result = PCI_ERS_RESULT_DISCONNECT; | |
11352 | } | |
11353 | ||
11354 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
11355 | if (err) { | |
11356 | dev_info(&pdev->dev, | |
11357 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", | |
11358 | err); | |
11359 | /* non-fatal, continue */ | |
11360 | } | |
11361 | ||
11362 | return result; | |
11363 | } | |
11364 | ||
11365 | /** | |
11366 | * i40e_pci_error_resume - restart operations after PCI error recovery | |
11367 | * @pdev: PCI device information struct | |
11368 | * | |
11369 | * Called to allow the driver to bring things back up after PCI error | |
11370 | * and/or reset recovery has finished. | |
11371 | **/ | |
11372 | static void i40e_pci_error_resume(struct pci_dev *pdev) | |
11373 | { | |
11374 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
11375 | ||
fb43201f | 11376 | dev_dbg(&pdev->dev, "%s\n", __func__); |
9007bccd SN |
11377 | if (test_bit(__I40E_SUSPENDED, &pf->state)) |
11378 | return; | |
11379 | ||
11380 | rtnl_lock(); | |
41c445ff | 11381 | i40e_handle_reset_warning(pf); |
4c4935a9 | 11382 | rtnl_unlock(); |
9007bccd SN |
11383 | } |
11384 | ||
11385 | /** | |
11386 | * i40e_shutdown - PCI callback for shutting down | |
11387 | * @pdev: PCI device information struct | |
11388 | **/ | |
11389 | static void i40e_shutdown(struct pci_dev *pdev) | |
11390 | { | |
11391 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
8e2773ae | 11392 | struct i40e_hw *hw = &pf->hw; |
9007bccd SN |
11393 | |
11394 | set_bit(__I40E_SUSPENDED, &pf->state); | |
11395 | set_bit(__I40E_DOWN, &pf->state); | |
11396 | rtnl_lock(); | |
11397 | i40e_prep_for_reset(pf); | |
11398 | rtnl_unlock(); | |
11399 | ||
8e2773ae SN |
11400 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
11401 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
11402 | ||
02b42498 CS |
11403 | del_timer_sync(&pf->service_timer); |
11404 | cancel_work_sync(&pf->service_task); | |
11405 | i40e_fdir_teardown(pf); | |
11406 | ||
11407 | rtnl_lock(); | |
11408 | i40e_prep_for_reset(pf); | |
11409 | rtnl_unlock(); | |
11410 | ||
11411 | wr32(hw, I40E_PFPM_APM, | |
11412 | (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); | |
11413 | wr32(hw, I40E_PFPM_WUFC, | |
11414 | (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
11415 | ||
e147758d SN |
11416 | i40e_clear_interrupt_scheme(pf); |
11417 | ||
9007bccd | 11418 | if (system_state == SYSTEM_POWER_OFF) { |
8e2773ae | 11419 | pci_wake_from_d3(pdev, pf->wol_en); |
9007bccd SN |
11420 | pci_set_power_state(pdev, PCI_D3hot); |
11421 | } | |
11422 | } | |
11423 | ||
11424 | #ifdef CONFIG_PM | |
11425 | /** | |
11426 | * i40e_suspend - PCI callback for moving to D3 | |
11427 | * @pdev: PCI device information struct | |
11428 | **/ | |
11429 | static int i40e_suspend(struct pci_dev *pdev, pm_message_t state) | |
11430 | { | |
11431 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
8e2773ae | 11432 | struct i40e_hw *hw = &pf->hw; |
059ff69b | 11433 | int retval = 0; |
9007bccd SN |
11434 | |
11435 | set_bit(__I40E_SUSPENDED, &pf->state); | |
11436 | set_bit(__I40E_DOWN, &pf->state); | |
3932dbfe | 11437 | |
9007bccd SN |
11438 | rtnl_lock(); |
11439 | i40e_prep_for_reset(pf); | |
11440 | rtnl_unlock(); | |
11441 | ||
8e2773ae SN |
11442 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
11443 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
11444 | ||
b33d3b73 GR |
11445 | i40e_stop_misc_vector(pf); |
11446 | ||
059ff69b GR |
11447 | retval = pci_save_state(pdev); |
11448 | if (retval) | |
11449 | return retval; | |
11450 | ||
8e2773ae | 11451 | pci_wake_from_d3(pdev, pf->wol_en); |
9007bccd SN |
11452 | pci_set_power_state(pdev, PCI_D3hot); |
11453 | ||
059ff69b | 11454 | return retval; |
41c445ff JB |
11455 | } |
11456 | ||
9007bccd SN |
11457 | /** |
11458 | * i40e_resume - PCI callback for waking up from D3 | |
11459 | * @pdev: PCI device information struct | |
11460 | **/ | |
11461 | static int i40e_resume(struct pci_dev *pdev) | |
11462 | { | |
11463 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
11464 | u32 err; | |
11465 | ||
11466 | pci_set_power_state(pdev, PCI_D0); | |
11467 | pci_restore_state(pdev); | |
11468 | /* pci_restore_state() clears dev->state_saves, so | |
11469 | * call pci_save_state() again to restore it. | |
11470 | */ | |
11471 | pci_save_state(pdev); | |
11472 | ||
11473 | err = pci_enable_device_mem(pdev); | |
11474 | if (err) { | |
fb43201f | 11475 | dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n"); |
9007bccd SN |
11476 | return err; |
11477 | } | |
11478 | pci_set_master(pdev); | |
11479 | ||
11480 | /* no wakeup events while running */ | |
11481 | pci_wake_from_d3(pdev, false); | |
11482 | ||
11483 | /* handling the reset will rebuild the device state */ | |
11484 | if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) { | |
11485 | clear_bit(__I40E_DOWN, &pf->state); | |
11486 | rtnl_lock(); | |
11487 | i40e_reset_and_rebuild(pf, false); | |
11488 | rtnl_unlock(); | |
11489 | } | |
11490 | ||
11491 | return 0; | |
11492 | } | |
11493 | ||
11494 | #endif | |
41c445ff JB |
11495 | static const struct pci_error_handlers i40e_err_handler = { |
11496 | .error_detected = i40e_pci_error_detected, | |
11497 | .slot_reset = i40e_pci_error_slot_reset, | |
11498 | .resume = i40e_pci_error_resume, | |
11499 | }; | |
11500 | ||
11501 | static struct pci_driver i40e_driver = { | |
11502 | .name = i40e_driver_name, | |
11503 | .id_table = i40e_pci_tbl, | |
11504 | .probe = i40e_probe, | |
11505 | .remove = i40e_remove, | |
9007bccd SN |
11506 | #ifdef CONFIG_PM |
11507 | .suspend = i40e_suspend, | |
11508 | .resume = i40e_resume, | |
11509 | #endif | |
11510 | .shutdown = i40e_shutdown, | |
41c445ff JB |
11511 | .err_handler = &i40e_err_handler, |
11512 | .sriov_configure = i40e_pci_sriov_configure, | |
11513 | }; | |
11514 | ||
11515 | /** | |
11516 | * i40e_init_module - Driver registration routine | |
11517 | * | |
11518 | * i40e_init_module is the first routine called when the driver is | |
11519 | * loaded. All it does is register with the PCI subsystem. | |
11520 | **/ | |
11521 | static int __init i40e_init_module(void) | |
11522 | { | |
11523 | pr_info("%s: %s - version %s\n", i40e_driver_name, | |
11524 | i40e_driver_string, i40e_driver_version_str); | |
11525 | pr_info("%s: %s\n", i40e_driver_name, i40e_copyright); | |
96664483 | 11526 | |
2803b16c JB |
11527 | /* we will see if single thread per module is enough for now, |
11528 | * it can't be any worse than using the system workqueue which | |
11529 | * was already single threaded | |
11530 | */ | |
11531 | i40e_wq = create_singlethread_workqueue(i40e_driver_name); | |
11532 | if (!i40e_wq) { | |
11533 | pr_err("%s: Failed to create workqueue\n", i40e_driver_name); | |
11534 | return -ENOMEM; | |
11535 | } | |
11536 | ||
41c445ff JB |
11537 | i40e_dbg_init(); |
11538 | return pci_register_driver(&i40e_driver); | |
11539 | } | |
11540 | module_init(i40e_init_module); | |
11541 | ||
11542 | /** | |
11543 | * i40e_exit_module - Driver exit cleanup routine | |
11544 | * | |
11545 | * i40e_exit_module is called just before the driver is removed | |
11546 | * from memory. | |
11547 | **/ | |
11548 | static void __exit i40e_exit_module(void) | |
11549 | { | |
11550 | pci_unregister_driver(&i40e_driver); | |
2803b16c | 11551 | destroy_workqueue(i40e_wq); |
41c445ff JB |
11552 | i40e_dbg_exit(); |
11553 | } | |
11554 | module_exit(i40e_exit_module); |