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i40e/i40evf: Add a new offload for RSS PCTYPE V2 for X722
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
6633d381 30#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
1c2df9e5 41#define DRV_VERSION_MINOR 4
1e590660 42#define DRV_VERSION_BUILD 7
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 58static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
59 u16 rss_table_size, u16 rss_size);
cbf61325 60static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 61static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 62
63/* i40e_pci_tbl - PCI Device ID Table
64 *
65 * Last entry must be all 0s
66 *
67 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
68 * Class, Class Mask, private data (not used) }
69 */
9baa3c34 70static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 87 /* required last entry */
88 {0, }
89};
90MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
91
92#define I40E_MAX_VF_COUNT 128
93static int debug = -1;
94module_param(debug, int, 0);
95MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
96
97MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
98MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
99MODULE_LICENSE("GPL");
100MODULE_VERSION(DRV_VERSION);
101
102/**
103 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
104 * @hw: pointer to the HW structure
105 * @mem: ptr to mem struct to fill out
106 * @size: size of memory requested
107 * @alignment: what to align the allocation to
108 **/
109int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
110 u64 size, u32 alignment)
111{
112 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
113
114 mem->size = ALIGN(size, alignment);
115 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
116 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 117 if (!mem->va)
118 return -ENOMEM;
41c445ff 119
93bc73b8 120 return 0;
41c445ff
JB		 121}
122
123/**
124 * i40e_free_dma_mem_d - OS specific memory free for shared code
125 * @hw: pointer to the HW structure
126 * @mem: ptr to mem struct to free
127 **/
128int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
129{
130 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
131
132 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
133 mem->va = NULL;
134 mem->pa = 0;
135 mem->size = 0;
136
137 return 0;
138}
139
140/**
141 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
142 * @hw: pointer to the HW structure
143 * @mem: ptr to mem struct to fill out
144 * @size: size of memory requested
145 **/
146int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
147 u32 size)
148{
149 mem->size = size;
150 mem->va = kzalloc(size, GFP_KERNEL);
151
93bc73b8
JB		 152 if (!mem->va)
153 return -ENOMEM;
41c445ff 154
93bc73b8 155 return 0;
41c445ff
JB		 156}
157
158/**
159 * i40e_free_virt_mem_d - OS specific memory free for shared code
160 * @hw: pointer to the HW structure
161 * @mem: ptr to mem struct to free
162 **/
163int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
164{
165 /* it's ok to kfree a NULL pointer */
166 kfree(mem->va);
167 mem->va = NULL;
168 mem->size = 0;
169
170 return 0;
171}
172
173/**
174 * i40e_get_lump - find a lump of free generic resource
175 * @pf: board private structure
176 * @pile: the pile of resource to search
177 * @needed: the number of items needed
178 * @id: an owner id to stick on the items assigned
179 *
180 * Returns the base item index of the lump, or negative for error
181 *
182 * The search_hint trick and lack of advanced fit-finding only work
183 * because we're highly likely to have all the same size lump requests.
184 * Linear search time and any fragmentation should be minimal.
185 **/
186static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
187 u16 needed, u16 id)
188{
189 int ret = -ENOMEM;
ddf434ac 190 int i, j;
41c445ff
JB		 191
192 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
193 dev_info(&pf->pdev->dev,
194 "param err: pile=%p needed=%d id=0x%04x\n",
195 pile, needed, id);
196 return -EINVAL;
197 }
198
199 /* start the linear search with an imperfect hint */
200 i = pile->search_hint;
ddf434ac 201 while (i < pile->num_entries) {
41c445ff
JB		 202 /* skip already allocated entries */
203 if (pile->list[i] & I40E_PILE_VALID_BIT) {
204 i++;
205 continue;
206 }
207
208 /* do we have enough in this lump? */
209 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
210 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
211 break;
212 }
213
214 if (j == needed) {
215 /* there was enough, so assign it to the requestor */
216 for (j = 0; j < needed; j++)
217 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
218 ret = i;
219 pile->search_hint = i + j;
ddf434ac 220 break;
41c445ff 221 }
6995b36c
JB		 222
223 /* not enough, so skip over it and continue looking */
224 i += j;
41c445ff
JB		 225 }
226
227 return ret;
228}
229
230/**
231 * i40e_put_lump - return a lump of generic resource
232 * @pile: the pile of resource to search
233 * @index: the base item index
234 * @id: the owner id of the items assigned
235 *
236 * Returns the count of items in the lump
237 **/
238static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
239{
240 int valid_id = (id | I40E_PILE_VALID_BIT);
241 int count = 0;
242 int i;
243
244 if (!pile || index >= pile->num_entries)
245 return -EINVAL;
246
247 for (i = index;
248 i < pile->num_entries && pile->list[i] == valid_id;
249 i++) {
250 pile->list[i] = 0;
251 count++;
252 }
253
254 if (count && index < pile->search_hint)
255 pile->search_hint = index;
256
257 return count;
258}
259
fdf0e0bf
ASJ		 260/**
261 * i40e_find_vsi_from_id - searches for the vsi with the given id
262 * @pf - the pf structure to search for the vsi
263 * @id - id of the vsi it is searching for
264 **/
265struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
266{
267 int i;
268
269 for (i = 0; i < pf->num_alloc_vsi; i++)
270 if (pf->vsi[i] && (pf->vsi[i]->id == id))
271 return pf->vsi[i];
272
273 return NULL;
274}
275
41c445ff
JB		 276/**
277 * i40e_service_event_schedule - Schedule the service task to wake up
278 * @pf: board private structure
279 *
280 * If not already scheduled, this puts the task into the work queue
281 **/
282static void i40e_service_event_schedule(struct i40e_pf *pf)
283{
284 if (!test_bit(__I40E_DOWN, &pf->state) &&
285 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
286 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
287 schedule_work(&pf->service_task);
288}
289
290/**
291 * i40e_tx_timeout - Respond to a Tx Hang
292 * @netdev: network interface device structure
293 *
294 * If any port has noticed a Tx timeout, it is likely that the whole
295 * device is munged, not just the one netdev port, so go for the full
296 * reset.
297 **/
38e00438
VD		 298#ifdef I40E_FCOE
299void i40e_tx_timeout(struct net_device *netdev)
300#else
41c445ff 301static void i40e_tx_timeout(struct net_device *netdev)
38e00438 302#endif
41c445ff
JB		 303{
304 struct i40e_netdev_priv *np = netdev_priv(netdev);
305 struct i40e_vsi *vsi = np->vsi;
306 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 307 struct i40e_ring *tx_ring = NULL;
308 unsigned int i, hung_queue = 0;
309 u32 head, val;
41c445ff
JB		 310
311 pf->tx_timeout_count++;
312
b03a8c1f
KP		 313 /* find the stopped queue the same way the stack does */
314 for (i = 0; i < netdev->num_tx_queues; i++) {
315 struct netdev_queue *q;
316 unsigned long trans_start;
317
318 q = netdev_get_tx_queue(netdev, i);
319 trans_start = q->trans_start ? : netdev->trans_start;
320 if (netif_xmit_stopped(q) &&
321 time_after(jiffies,
322 (trans_start + netdev->watchdog_timeo))) {
323 hung_queue = i;
324 break;
325 }
326 }
327
328 if (i == netdev->num_tx_queues) {
329 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
330 } else {
331 /* now that we have an index, find the tx_ring struct */
332 for (i = 0; i < vsi->num_queue_pairs; i++) {
333 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
334 if (hung_queue ==
335 vsi->tx_rings[i]->queue_index) {
336 tx_ring = vsi->tx_rings[i];
337 break;
338 }
339 }
340 }
341 }
342
41c445ff 343 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 344 pf->tx_timeout_recovery_level = 1; /* reset after some time */
345 else if (time_before(jiffies,
346 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
347 return; /* don't do any new action before the next timeout */
348
349 if (tx_ring) {
350 head = i40e_get_head(tx_ring);
351 /* Read interrupt register */
352 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
353 val = rd32(&pf->hw,
354 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
355 tx_ring->vsi->base_vector - 1));
356 else
357 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
358
359 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
360 vsi->seid, hung_queue, tx_ring->next_to_clean,
361 head, tx_ring->next_to_use,
362 readl(tx_ring->tail), val);
363 }
364
41c445ff 365 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 366 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
367 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 368
369 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 370 case 1:
371 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
372 break;
373 case 2:
374 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
375 break;
376 case 3:
377 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
378 break;
379 default:
380 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 381 break;
382 }
b03a8c1f 383
41c445ff
JB		 384 i40e_service_event_schedule(pf);
385 pf->tx_timeout_recovery_level++;
386}
387
388/**
389 * i40e_release_rx_desc - Store the new tail and head values
390 * @rx_ring: ring to bump
391 * @val: new head index
392 **/
393static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
394{
395 rx_ring->next_to_use = val;
396
397 /* Force memory writes to complete before letting h/w
398 * know there are new descriptors to fetch. (Only
399 * applicable for weak-ordered memory model archs,
400 * such as IA-64).
401 */
402 wmb();
403 writel(val, rx_ring->tail);
404}
405
406/**
407 * i40e_get_vsi_stats_struct - Get System Network Statistics
408 * @vsi: the VSI we care about
409 *
410 * Returns the address of the device statistics structure.
411 * The statistics are actually updated from the service task.
412 **/
413struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
414{
415 return &vsi->net_stats;
416}
417
418/**
419 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
420 * @netdev: network interface device structure
421 *
422 * Returns the address of the device statistics structure.
423 * The statistics are actually updated from the service task.
424 **/
38e00438
VD		 425#ifdef I40E_FCOE
426struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
427 struct net_device *netdev,
428 struct rtnl_link_stats64 *stats)
429#else
41c445ff
JB		 430static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
431 struct net_device *netdev,
980e9b11 432 struct rtnl_link_stats64 *stats)
38e00438 433#endif
41c445ff
JB		 434{
435 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 436 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 437 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 438 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
439 int i;
440
bc7d338f
ASJ		 441 if (test_bit(__I40E_DOWN, &vsi->state))
442 return stats;
443
3c325ced
JB		 444 if (!vsi->tx_rings)
445 return stats;
446
980e9b11
AD		 447 rcu_read_lock();
448 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 449 u64 bytes, packets;
450 unsigned int start;
451
452 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
453 if (!tx_ring)
454 continue;
455
456 do {
57a7744e 457 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 458 packets = tx_ring->stats.packets;
459 bytes = tx_ring->stats.bytes;
57a7744e 460 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 461
462 stats->tx_packets += packets;
463 stats->tx_bytes += bytes;
464 rx_ring = &tx_ring[1];
465
466 do {
57a7744e 467 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 468 packets = rx_ring->stats.packets;
469 bytes = rx_ring->stats.bytes;
57a7744e 470 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 471
980e9b11
AD		 472 stats->rx_packets += packets;
473 stats->rx_bytes += bytes;
474 }
475 rcu_read_unlock();
476
a5282f44 477 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 478 stats->multicast = vsi_stats->multicast;
479 stats->tx_errors = vsi_stats->tx_errors;
480 stats->tx_dropped = vsi_stats->tx_dropped;
481 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 482 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 483 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
484 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 485
980e9b11 486 return stats;
41c445ff
JB		 487}
488
489/**
490 * i40e_vsi_reset_stats - Resets all stats of the given vsi
491 * @vsi: the VSI to have its stats reset
492 **/
493void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
494{
495 struct rtnl_link_stats64 *ns;
496 int i;
497
498 if (!vsi)
499 return;
500
501 ns = i40e_get_vsi_stats_struct(vsi);
502 memset(ns, 0, sizeof(*ns));
503 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
504 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
505 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 506 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 507 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 508 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 509 sizeof(vsi->rx_rings[i]->stats));
6995b36c 510 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 511 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 512 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 513 sizeof(vsi->tx_rings[i]->stats));
514 memset(&vsi->tx_rings[i]->tx_stats, 0,
515 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 516 }
8e9dca53 517 }
41c445ff
JB		 518 vsi->stat_offsets_loaded = false;
519}
520
521/**
b40c82e6 522 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 523 * @pf: the PF to be reset
524 **/
525void i40e_pf_reset_stats(struct i40e_pf *pf)
526{
e91fdf76
SN		 527 int i;
528
41c445ff
JB		 529 memset(&pf->stats, 0, sizeof(pf->stats));
530 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
531 pf->stat_offsets_loaded = false;
e91fdf76
SN		 532
533 for (i = 0; i < I40E_MAX_VEB; i++) {
534 if (pf->veb[i]) {
535 memset(&pf->veb[i]->stats, 0,
536 sizeof(pf->veb[i]->stats));
537 memset(&pf->veb[i]->stats_offsets, 0,
538 sizeof(pf->veb[i]->stats_offsets));
539 pf->veb[i]->stat_offsets_loaded = false;
540 }
541 }
41c445ff
JB		 542}
543
544/**
545 * i40e_stat_update48 - read and update a 48 bit stat from the chip
546 * @hw: ptr to the hardware info
547 * @hireg: the high 32 bit reg to read
548 * @loreg: the low 32 bit reg to read
549 * @offset_loaded: has the initial offset been loaded yet
550 * @offset: ptr to current offset value
551 * @stat: ptr to the stat
552 *
553 * Since the device stats are not reset at PFReset, they likely will not
554 * be zeroed when the driver starts. We'll save the first values read
555 * and use them as offsets to be subtracted from the raw values in order
556 * to report stats that count from zero. In the process, we also manage
557 * the potential roll-over.
558 **/
559static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
560 bool offset_loaded, u64 *offset, u64 *stat)
561{
562 u64 new_data;
563
ab60085e 564 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 565 new_data = rd32(hw, loreg);
566 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
567 } else {
568 new_data = rd64(hw, loreg);
569 }
570 if (!offset_loaded)
571 *offset = new_data;
572 if (likely(new_data >= *offset))
573 *stat = new_data - *offset;
574 else
41a1d04b 575 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 576 *stat &= 0xFFFFFFFFFFFFULL;
577}
578
579/**
580 * i40e_stat_update32 - read and update a 32 bit stat from the chip
581 * @hw: ptr to the hardware info
582 * @reg: the hw reg to read
583 * @offset_loaded: has the initial offset been loaded yet
584 * @offset: ptr to current offset value
585 * @stat: ptr to the stat
586 **/
587static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
588 bool offset_loaded, u64 *offset, u64 *stat)
589{
590 u32 new_data;
591
592 new_data = rd32(hw, reg);
593 if (!offset_loaded)
594 *offset = new_data;
595 if (likely(new_data >= *offset))
596 *stat = (u32)(new_data - *offset);
597 else
41a1d04b 598 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 599}
600
601/**
602 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
603 * @vsi: the VSI to be updated
604 **/
605void i40e_update_eth_stats(struct i40e_vsi *vsi)
606{
607 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
608 struct i40e_pf *pf = vsi->back;
609 struct i40e_hw *hw = &pf->hw;
610 struct i40e_eth_stats *oes;
611 struct i40e_eth_stats *es; /* device's eth stats */
612
613 es = &vsi->eth_stats;
614 oes = &vsi->eth_stats_offsets;
615
616 /* Gather up the stats that the hw collects */
617 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
618 vsi->stat_offsets_loaded,
619 &oes->tx_errors, &es->tx_errors);
620 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 623 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
624 vsi->stat_offsets_loaded,
625 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
626 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
627 vsi->stat_offsets_loaded,
628 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 629
630 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
631 I40E_GLV_GORCL(stat_idx),
632 vsi->stat_offsets_loaded,
633 &oes->rx_bytes, &es->rx_bytes);
634 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
635 I40E_GLV_UPRCL(stat_idx),
636 vsi->stat_offsets_loaded,
637 &oes->rx_unicast, &es->rx_unicast);
638 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
639 I40E_GLV_MPRCL(stat_idx),
640 vsi->stat_offsets_loaded,
641 &oes->rx_multicast, &es->rx_multicast);
642 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
643 I40E_GLV_BPRCL(stat_idx),
644 vsi->stat_offsets_loaded,
645 &oes->rx_broadcast, &es->rx_broadcast);
646
647 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
648 I40E_GLV_GOTCL(stat_idx),
649 vsi->stat_offsets_loaded,
650 &oes->tx_bytes, &es->tx_bytes);
651 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
652 I40E_GLV_UPTCL(stat_idx),
653 vsi->stat_offsets_loaded,
654 &oes->tx_unicast, &es->tx_unicast);
655 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
656 I40E_GLV_MPTCL(stat_idx),
657 vsi->stat_offsets_loaded,
658 &oes->tx_multicast, &es->tx_multicast);
659 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
660 I40E_GLV_BPTCL(stat_idx),
661 vsi->stat_offsets_loaded,
662 &oes->tx_broadcast, &es->tx_broadcast);
663 vsi->stat_offsets_loaded = true;
664}
665
666/**
667 * i40e_update_veb_stats - Update Switch component statistics
668 * @veb: the VEB being updated
669 **/
670static void i40e_update_veb_stats(struct i40e_veb *veb)
671{
672 struct i40e_pf *pf = veb->pf;
673 struct i40e_hw *hw = &pf->hw;
674 struct i40e_eth_stats *oes;
675 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 676 struct i40e_veb_tc_stats *veb_oes;
677 struct i40e_veb_tc_stats *veb_es;
678 int i, idx = 0;
41c445ff
JB		 679
680 idx = veb->stats_idx;
681 es = &veb->stats;
682 oes = &veb->stats_offsets;
fe860afb
NP		 683 veb_es = &veb->tc_stats;
684 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 685
686 /* Gather up the stats that the hw collects */
687 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
688 veb->stat_offsets_loaded,
689 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 690 if (hw->revision_id > 0)
691 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
692 veb->stat_offsets_loaded,
693 &oes->rx_unknown_protocol,
694 &es->rx_unknown_protocol);
41c445ff
JB		 695 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
696 veb->stat_offsets_loaded,
697 &oes->rx_bytes, &es->rx_bytes);
698 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
699 veb->stat_offsets_loaded,
700 &oes->rx_unicast, &es->rx_unicast);
701 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
702 veb->stat_offsets_loaded,
703 &oes->rx_multicast, &es->rx_multicast);
704 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
705 veb->stat_offsets_loaded,
706 &oes->rx_broadcast, &es->rx_broadcast);
707
708 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
709 veb->stat_offsets_loaded,
710 &oes->tx_bytes, &es->tx_bytes);
711 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
712 veb->stat_offsets_loaded,
713 &oes->tx_unicast, &es->tx_unicast);
714 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
715 veb->stat_offsets_loaded,
716 &oes->tx_multicast, &es->tx_multicast);
717 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
718 veb->stat_offsets_loaded,
719 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 720 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
721 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
722 I40E_GLVEBTC_RPCL(i, idx),
723 veb->stat_offsets_loaded,
724 &veb_oes->tc_rx_packets[i],
725 &veb_es->tc_rx_packets[i]);
726 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
727 I40E_GLVEBTC_RBCL(i, idx),
728 veb->stat_offsets_loaded,
729 &veb_oes->tc_rx_bytes[i],
730 &veb_es->tc_rx_bytes[i]);
731 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
732 I40E_GLVEBTC_TPCL(i, idx),
733 veb->stat_offsets_loaded,
734 &veb_oes->tc_tx_packets[i],
735 &veb_es->tc_tx_packets[i]);
736 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
737 I40E_GLVEBTC_TBCL(i, idx),
738 veb->stat_offsets_loaded,
739 &veb_oes->tc_tx_bytes[i],
740 &veb_es->tc_tx_bytes[i]);
741 }
41c445ff
JB		 742 veb->stat_offsets_loaded = true;
743}
744
38e00438
VD		 745#ifdef I40E_FCOE
746/**
747 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
748 * @vsi: the VSI that is capable of doing FCoE
749 **/
750static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
751{
752 struct i40e_pf *pf = vsi->back;
753 struct i40e_hw *hw = &pf->hw;
754 struct i40e_fcoe_stats *ofs;
755 struct i40e_fcoe_stats *fs; /* device's eth stats */
756 int idx;
757
758 if (vsi->type != I40E_VSI_FCOE)
759 return;
760
761 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
762 fs = &vsi->fcoe_stats;
763 ofs = &vsi->fcoe_stats_offsets;
764
765 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
766 vsi->fcoe_stat_offsets_loaded,
767 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
768 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
769 vsi->fcoe_stat_offsets_loaded,
770 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
771 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
772 vsi->fcoe_stat_offsets_loaded,
773 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
774 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
775 vsi->fcoe_stat_offsets_loaded,
776 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
777 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
778 vsi->fcoe_stat_offsets_loaded,
779 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
780 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
781 vsi->fcoe_stat_offsets_loaded,
782 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
783 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
784 vsi->fcoe_stat_offsets_loaded,
785 &ofs->fcoe_last_error, &fs->fcoe_last_error);
786 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
787 vsi->fcoe_stat_offsets_loaded,
788 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
789
790 vsi->fcoe_stat_offsets_loaded = true;
791}
792
793#endif
41c445ff 794/**
7812fddc 795 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 796 * @vsi: the VSI to be updated
797 *
798 * There are a few instances where we store the same stat in a
799 * couple of different structs. This is partly because we have
800 * the netdev stats that need to be filled out, which is slightly
801 * different from the "eth_stats" defined by the chip and used in
7812fddc 802 * VF communications. We sort it out here.
41c445ff 803 **/
7812fddc 804static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 805{
806 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 807 struct rtnl_link_stats64 *ons;
808 struct rtnl_link_stats64 *ns; /* netdev stats */
809 struct i40e_eth_stats *oes;
810 struct i40e_eth_stats *es; /* device's eth stats */
811 u32 tx_restart, tx_busy;
bf00b376 812 struct i40e_ring *p;
41c445ff 813 u32 rx_page, rx_buf;
bf00b376
AA		 814 u64 bytes, packets;
815 unsigned int start;
2fc3d715 816 u64 tx_linearize;
164c9f54 817 u64 tx_force_wb;
41c445ff
JB		 818 u64 rx_p, rx_b;
819 u64 tx_p, tx_b;
41c445ff
JB		 820 u16 q;
821
822 if (test_bit(__I40E_DOWN, &vsi->state) ||
823 test_bit(__I40E_CONFIG_BUSY, &pf->state))
824 return;
825
826 ns = i40e_get_vsi_stats_struct(vsi);
827 ons = &vsi->net_stats_offsets;
828 es = &vsi->eth_stats;
829 oes = &vsi->eth_stats_offsets;
830
831 /* Gather up the netdev and vsi stats that the driver collects
832 * on the fly during packet processing
833 */
834 rx_b = rx_p = 0;
835 tx_b = tx_p = 0;
164c9f54 836 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
41c445ff
JB		 837 rx_page = 0;
838 rx_buf = 0;
980e9b11 839 rcu_read_lock();
41c445ff 840 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 841 /* locate Tx ring */
842 p = ACCESS_ONCE(vsi->tx_rings[q]);
843
844 do {
57a7744e 845 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 846 packets = p->stats.packets;
847 bytes = p->stats.bytes;
57a7744e 848 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 849 tx_b += bytes;
850 tx_p += packets;
851 tx_restart += p->tx_stats.restart_queue;
852 tx_busy += p->tx_stats.tx_busy;
2fc3d715 853 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 854 tx_force_wb += p->tx_stats.tx_force_wb;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
2fc3d715 871 vsi->tx_linearize = tx_linearize;
164c9f54 872 vsi->tx_force_wb = tx_force_wb;
41c445ff
JB		 873 vsi->rx_page_failed = rx_page;
874 vsi->rx_buf_failed = rx_buf;
875
876 ns->rx_packets = rx_p;
877 ns->rx_bytes = rx_b;
878 ns->tx_packets = tx_p;
879 ns->tx_bytes = tx_b;
880
41c445ff 881 /* update netdev stats from eth stats */
7812fddc 882 i40e_update_eth_stats(vsi);
41c445ff
JB		 883 ons->tx_errors = oes->tx_errors;
884 ns->tx_errors = es->tx_errors;
885 ons->multicast = oes->rx_multicast;
886 ns->multicast = es->rx_multicast;
41a9e55c
SN		 887 ons->rx_dropped = oes->rx_discards;
888 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 889 ons->tx_dropped = oes->tx_discards;
890 ns->tx_dropped = es->tx_discards;
891
7812fddc 892 /* pull in a couple PF stats if this is the main vsi */
41c445ff 893 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 894 ns->rx_crc_errors = pf->stats.crc_errors;
895 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
896 ns->rx_length_errors = pf->stats.rx_length_errors;
897 }
898}
41c445ff 899
7812fddc 900/**
b40c82e6 901 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 902 * @pf: the PF to be updated
903 **/
904static void i40e_update_pf_stats(struct i40e_pf *pf)
905{
906 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
907 struct i40e_hw_port_stats *nsd = &pf->stats;
908 struct i40e_hw *hw = &pf->hw;
909 u32 val;
910 int i;
41c445ff 911
7812fddc
SN		 912 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
913 I40E_GLPRT_GORCL(hw->port),
914 pf->stat_offsets_loaded,
915 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
916 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
917 I40E_GLPRT_GOTCL(hw->port),
918 pf->stat_offsets_loaded,
919 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
920 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->eth.rx_discards,
923 &nsd->eth.rx_discards);
532d283d
SN		 924 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
925 I40E_GLPRT_UPRCL(hw->port),
926 pf->stat_offsets_loaded,
927 &osd->eth.rx_unicast,
928 &nsd->eth.rx_unicast);
7812fddc
SN		 929 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
930 I40E_GLPRT_MPRCL(hw->port),
931 pf->stat_offsets_loaded,
932 &osd->eth.rx_multicast,
933 &nsd->eth.rx_multicast);
532d283d
SN		 934 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
935 I40E_GLPRT_BPRCL(hw->port),
936 pf->stat_offsets_loaded,
937 &osd->eth.rx_broadcast,
938 &nsd->eth.rx_broadcast);
939 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
940 I40E_GLPRT_UPTCL(hw->port),
941 pf->stat_offsets_loaded,
942 &osd->eth.tx_unicast,
943 &nsd->eth.tx_unicast);
944 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
945 I40E_GLPRT_MPTCL(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->eth.tx_multicast,
948 &nsd->eth.tx_multicast);
949 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
950 I40E_GLPRT_BPTCL(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->eth.tx_broadcast,
953 &nsd->eth.tx_broadcast);
41c445ff 954
7812fddc
SN		 955 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->tx_dropped_link_down,
958 &nsd->tx_dropped_link_down);
41c445ff 959
7812fddc
SN		 960 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->crc_errors, &nsd->crc_errors);
41c445ff 963
7812fddc
SN		 964 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 967
7812fddc
SN		 968 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
969 pf->stat_offsets_loaded,
970 &osd->mac_local_faults,
971 &nsd->mac_local_faults);
972 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
973 pf->stat_offsets_loaded,
974 &osd->mac_remote_faults,
975 &nsd->mac_remote_faults);
41c445ff 976
7812fddc
SN		 977 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->rx_length_errors,
980 &nsd->rx_length_errors);
41c445ff 981
7812fddc
SN		 982 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
983 pf->stat_offsets_loaded,
984 &osd->link_xon_rx, &nsd->link_xon_rx);
985 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 988 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 991 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
992 pf->stat_offsets_loaded,
993 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 994
7812fddc 995 for (i = 0; i < 8; i++) {
95db239f
NP		 996 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
997 pf->stat_offsets_loaded,
998 &osd->priority_xoff_rx[i],
999 &nsd->priority_xoff_rx[i]);
7812fddc 1000 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1001 pf->stat_offsets_loaded,
7812fddc
SN		 1002 &osd->priority_xon_rx[i],
1003 &nsd->priority_xon_rx[i]);
1004 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1005 pf->stat_offsets_loaded,
7812fddc
SN		 1006 &osd->priority_xon_tx[i],
1007 &nsd->priority_xon_tx[i]);
1008 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1009 pf->stat_offsets_loaded,
7812fddc
SN		 1010 &osd->priority_xoff_tx[i],
1011 &nsd->priority_xoff_tx[i]);
1012 i40e_stat_update32(hw,
1013 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1014 pf->stat_offsets_loaded,
7812fddc
SN		 1015 &osd->priority_xon_2_xoff[i],
1016 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1017 }
1018
7812fddc
SN		 1019 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1020 I40E_GLPRT_PRC64L(hw->port),
1021 pf->stat_offsets_loaded,
1022 &osd->rx_size_64, &nsd->rx_size_64);
1023 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1024 I40E_GLPRT_PRC127L(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->rx_size_127, &nsd->rx_size_127);
1027 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1028 I40E_GLPRT_PRC255L(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->rx_size_255, &nsd->rx_size_255);
1031 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1032 I40E_GLPRT_PRC511L(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->rx_size_511, &nsd->rx_size_511);
1035 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1036 I40E_GLPRT_PRC1023L(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->rx_size_1023, &nsd->rx_size_1023);
1039 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1040 I40E_GLPRT_PRC1522L(hw->port),
1041 pf->stat_offsets_loaded,
1042 &osd->rx_size_1522, &nsd->rx_size_1522);
1043 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1044 I40E_GLPRT_PRC9522L(hw->port),
1045 pf->stat_offsets_loaded,
1046 &osd->rx_size_big, &nsd->rx_size_big);
1047
1048 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1049 I40E_GLPRT_PTC64L(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->tx_size_64, &nsd->tx_size_64);
1052 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1053 I40E_GLPRT_PTC127L(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->tx_size_127, &nsd->tx_size_127);
1056 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1057 I40E_GLPRT_PTC255L(hw->port),
1058 pf->stat_offsets_loaded,
1059 &osd->tx_size_255, &nsd->tx_size_255);
1060 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1061 I40E_GLPRT_PTC511L(hw->port),
1062 pf->stat_offsets_loaded,
1063 &osd->tx_size_511, &nsd->tx_size_511);
1064 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1065 I40E_GLPRT_PTC1023L(hw->port),
1066 pf->stat_offsets_loaded,
1067 &osd->tx_size_1023, &nsd->tx_size_1023);
1068 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1069 I40E_GLPRT_PTC1522L(hw->port),
1070 pf->stat_offsets_loaded,
1071 &osd->tx_size_1522, &nsd->tx_size_1522);
1072 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1073 I40E_GLPRT_PTC9522L(hw->port),
1074 pf->stat_offsets_loaded,
1075 &osd->tx_size_big, &nsd->tx_size_big);
1076
1077 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1078 pf->stat_offsets_loaded,
1079 &osd->rx_undersize, &nsd->rx_undersize);
1080 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_fragments, &nsd->rx_fragments);
1083 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_oversize, &nsd->rx_oversize);
1086 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1087 pf->stat_offsets_loaded,
1088 &osd->rx_jabber, &nsd->rx_jabber);
1089
433c47de 1090 /* FDIR stats */
0bf4b1b0
ASJ		 1091 i40e_stat_update32(hw,
1092 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1093 pf->stat_offsets_loaded,
1094 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1095 i40e_stat_update32(hw,
1096 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1097 pf->stat_offsets_loaded,
1098 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1099 i40e_stat_update32(hw,
1100 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1101 pf->stat_offsets_loaded,
1102 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1103
7812fddc
SN		 1104 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1105 nsd->tx_lpi_status =
1106 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1107 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1108 nsd->rx_lpi_status =
1109 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1110 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1111 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1112 pf->stat_offsets_loaded,
1113 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1114 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1115 pf->stat_offsets_loaded,
1116 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1117
d0389e51
ASJ		 1118 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1119 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1120 nsd->fd_sb_status = true;
1121 else
1122 nsd->fd_sb_status = false;
1123
1124 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1125 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1126 nsd->fd_atr_status = true;
1127 else
1128 nsd->fd_atr_status = false;
1129
41c445ff
JB		 1130 pf->stat_offsets_loaded = true;
1131}
1132
7812fddc
SN		 1133/**
1134 * i40e_update_stats - Update the various statistics counters.
1135 * @vsi: the VSI to be updated
1136 *
1137 * Update the various stats for this VSI and its related entities.
1138 **/
1139void i40e_update_stats(struct i40e_vsi *vsi)
1140{
1141 struct i40e_pf *pf = vsi->back;
1142
1143 if (vsi == pf->vsi[pf->lan_vsi])
1144 i40e_update_pf_stats(pf);
1145
1146 i40e_update_vsi_stats(vsi);
38e00438
VD		 1147#ifdef I40E_FCOE
1148 i40e_update_fcoe_stats(vsi);
1149#endif
7812fddc
SN		 1150}
1151
41c445ff
JB		 1152/**
1153 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1154 * @vsi: the VSI to be searched
1155 * @macaddr: the MAC address
1156 * @vlan: the vlan
b40c82e6 1157 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1158 * @is_netdev: make sure its a netdev filter, else doesn't matter
1159 *
1160 * Returns ptr to the filter object or NULL
1161 **/
1162static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1163 u8 *macaddr, s16 vlan,
1164 bool is_vf, bool is_netdev)
1165{
1166 struct i40e_mac_filter *f;
1167
1168 if (!vsi || !macaddr)
1169 return NULL;
1170
1171 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1172 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1173 (vlan == f->vlan) &&
1174 (!is_vf || f->is_vf) &&
1175 (!is_netdev || f->is_netdev))
1176 return f;
1177 }
1178 return NULL;
1179}
1180
1181/**
1182 * i40e_find_mac - Find a mac addr in the macvlan filters list
1183 * @vsi: the VSI to be searched
1184 * @macaddr: the MAC address we are searching for
b40c82e6 1185 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1186 * @is_netdev: make sure its a netdev filter, else doesn't matter
1187 *
1188 * Returns the first filter with the provided MAC address or NULL if
1189 * MAC address was not found
1190 **/
1191struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1192 bool is_vf, bool is_netdev)
1193{
1194 struct i40e_mac_filter *f;
1195
1196 if (!vsi || !macaddr)
1197 return NULL;
1198
1199 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1200 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1201 (!is_vf || f->is_vf) &&
1202 (!is_netdev || f->is_netdev))
1203 return f;
1204 }
1205 return NULL;
1206}
1207
1208/**
1209 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1210 * @vsi: the VSI to be searched
1211 *
1212 * Returns true if VSI is in vlan mode or false otherwise
1213 **/
1214bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1215{
1216 struct i40e_mac_filter *f;
1217
1218 /* Only -1 for all the filters denotes not in vlan mode
1219 * so we have to go through all the list in order to make sure
1220 */
1221 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1222 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1223 return true;
1224 }
1225
1226 return false;
1227}
1228
1229/**
1230 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1231 * @vsi: the VSI to be searched
1232 * @macaddr: the mac address to be filtered
b40c82e6 1233 * @is_vf: true if it is a VF
41c445ff
JB		 1234 * @is_netdev: true if it is a netdev
1235 *
1236 * Goes through all the macvlan filters and adds a
1237 * macvlan filter for each unique vlan that already exists
1238 *
1239 * Returns first filter found on success, else NULL
1240 **/
1241struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1242 bool is_vf, bool is_netdev)
1243{
1244 struct i40e_mac_filter *f;
1245
1246 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1247 if (vsi->info.pvid)
1248 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1249 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1250 is_vf, is_netdev)) {
1251 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1252 is_vf, is_netdev))
41c445ff
JB		 1253 return NULL;
1254 }
1255 }
1256
1257 return list_first_entry_or_null(&vsi->mac_filter_list,
1258 struct i40e_mac_filter, list);
1259}
1260
b36e9ab5
MW		 1261/**
1262 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1263 * @vsi: the VSI to be searched
1264 * @macaddr: the mac address to be removed
1265 * @is_vf: true if it is a VF
1266 * @is_netdev: true if it is a netdev
1267 *
1268 * Removes a given MAC address from a VSI, regardless of VLAN
1269 *
1270 * Returns 0 for success, or error
1271 **/
1272int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1273 bool is_vf, bool is_netdev)
1274{
1275 struct i40e_mac_filter *f = NULL;
1276 int changed = 0;
1277
1278 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1279 "Missing mac_filter_list_lock\n");
1280 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1281 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1282 (is_vf == f->is_vf) &&
1283 (is_netdev == f->is_netdev)) {
1284 f->counter--;
1285 f->changed = true;
1286 changed = 1;
1287 }
1288 }
1289 if (changed) {
1290 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1291 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1292 return 0;
1293 }
1294 return -ENOENT;
1295}
1296
8c27d42e
GR		 1297/**
1298 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1299 * @vsi: the PF Main VSI - inappropriate for any other VSI
1300 * @macaddr: the MAC address
30650cc5
SN		 1301 *
1302 * Some older firmware configurations set up a default promiscuous VLAN
1303 * filter that needs to be removed.
8c27d42e 1304 **/
30650cc5 1305static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1306{
1307 struct i40e_aqc_remove_macvlan_element_data element;
1308 struct i40e_pf *pf = vsi->back;
f1c7e72e 1309 i40e_status ret;
8c27d42e
GR		 1310
1311 /* Only appropriate for the PF main VSI */
1312 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1313 return -EINVAL;
8c27d42e 1314
30650cc5 1315 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1316 ether_addr_copy(element.mac_addr, macaddr);
1317 element.vlan_tag = 0;
1318 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1319 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1320 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1321 if (ret)
30650cc5
SN		 1322 return -ENOENT;
1323
1324 return 0;
8c27d42e
GR		 1325}
1326
41c445ff
JB		 1327/**
1328 * i40e_add_filter - Add a mac/vlan filter to the VSI
1329 * @vsi: the VSI to be searched
1330 * @macaddr: the MAC address
1331 * @vlan: the vlan
b40c82e6 1332 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1333 * @is_netdev: make sure its a netdev filter, else doesn't matter
1334 *
1335 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1336 *
1337 * NOTE: This function is expected to be called with mac_filter_list_lock
1338 * being held.
41c445ff
JB		 1339 **/
1340struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1341 u8 *macaddr, s16 vlan,
1342 bool is_vf, bool is_netdev)
1343{
1344 struct i40e_mac_filter *f;
1345
1346 if (!vsi || !macaddr)
1347 return NULL;
1348
1349 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1350 if (!f) {
1351 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1352 if (!f)
1353 goto add_filter_out;
1354
9a173901 1355 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1356 f->vlan = vlan;
1357 f->changed = true;
1358
1359 INIT_LIST_HEAD(&f->list);
1360 list_add(&f->list, &vsi->mac_filter_list);
1361 }
1362
1363 /* increment counter and add a new flag if needed */
1364 if (is_vf) {
1365 if (!f->is_vf) {
1366 f->is_vf = true;
1367 f->counter++;
1368 }
1369 } else if (is_netdev) {
1370 if (!f->is_netdev) {
1371 f->is_netdev = true;
1372 f->counter++;
1373 }
1374 } else {
1375 f->counter++;
1376 }
1377
1378 /* changed tells sync_filters_subtask to
1379 * push the filter down to the firmware
1380 */
1381 if (f->changed) {
1382 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1383 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1384 }
1385
1386add_filter_out:
1387 return f;
1388}
1389
1390/**
1391 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1392 * @vsi: the VSI to be searched
1393 * @macaddr: the MAC address
1394 * @vlan: the vlan
b40c82e6 1395 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1396 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1397 *
1398 * NOTE: This function is expected to be called with mac_filter_list_lock
1399 * being held.
41c445ff
JB		 1400 **/
1401void i40e_del_filter(struct i40e_vsi *vsi,
1402 u8 *macaddr, s16 vlan,
1403 bool is_vf, bool is_netdev)
1404{
1405 struct i40e_mac_filter *f;
1406
1407 if (!vsi || !macaddr)
1408 return;
1409
1410 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1411 if (!f || f->counter == 0)
1412 return;
1413
1414 if (is_vf) {
1415 if (f->is_vf) {
1416 f->is_vf = false;
1417 f->counter--;
1418 }
1419 } else if (is_netdev) {
1420 if (f->is_netdev) {
1421 f->is_netdev = false;
1422 f->counter--;
1423 }
1424 } else {
b40c82e6 1425 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1426 int min_f = 0;
6995b36c 1427
41c445ff
JB		 1428 min_f += (f->is_vf ? 1 : 0);
1429 min_f += (f->is_netdev ? 1 : 0);
1430
1431 if (f->counter > min_f)
1432 f->counter--;
1433 }
1434
1435 /* counter == 0 tells sync_filters_subtask to
1436 * remove the filter from the firmware's list
1437 */
1438 if (f->counter == 0) {
1439 f->changed = true;
1440 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1441 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1442 }
1443}
1444
1445/**
1446 * i40e_set_mac - NDO callback to set mac address
1447 * @netdev: network interface device structure
1448 * @p: pointer to an address structure
1449 *
1450 * Returns 0 on success, negative on failure
1451 **/
38e00438
VD		 1452#ifdef I40E_FCOE
1453int i40e_set_mac(struct net_device *netdev, void *p)
1454#else
41c445ff 1455static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1456#endif
41c445ff
JB		 1457{
1458 struct i40e_netdev_priv *np = netdev_priv(netdev);
1459 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1460 struct i40e_pf *pf = vsi->back;
1461 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1462 struct sockaddr *addr = p;
1463 struct i40e_mac_filter *f;
1464
1465 if (!is_valid_ether_addr(addr->sa_data))
1466 return -EADDRNOTAVAIL;
1467
30650cc5
SN		 1468 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1469 netdev_info(netdev, "already using mac address %pM\n",
1470 addr->sa_data);
1471 return 0;
1472 }
41c445ff 1473
80f6428f
ASJ		 1474 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1475 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1476 return -EADDRNOTAVAIL;
1477
30650cc5
SN		 1478 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1479 netdev_info(netdev, "returning to hw mac address %pM\n",
1480 hw->mac.addr);
1481 else
1482 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1483
41c445ff
JB		 1484 if (vsi->type == I40E_VSI_MAIN) {
1485 i40e_status ret;
6995b36c 1486
41c445ff 1487 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1488 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1489 addr->sa_data, NULL);
1490 if (ret) {
1491 netdev_info(netdev,
1492 "Addr change for Main VSI failed: %d\n",
1493 ret);
1494 return -EADDRNOTAVAIL;
1495 }
41c445ff
JB		 1496 }
1497
30650cc5
SN		 1498 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1499 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1500
30650cc5
SN		 1501 memset(&element, 0, sizeof(element));
1502 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1503 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1504 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1505 } else {
21659035 1506 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1507 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1508 false, false);
21659035 1509 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1510 }
41c445ff 1511
30650cc5
SN		 1512 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1513 struct i40e_aqc_add_macvlan_element_data element;
1514
1515 memset(&element, 0, sizeof(element));
1516 ether_addr_copy(element.mac_addr, hw->mac.addr);
1517 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1518 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1519 } else {
21659035 1520 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1521 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1522 false, false);
1523 if (f)
1524 f->is_laa = true;
21659035 1525 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1526 }
1527
30650cc5 1528 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b
MW		 1529
1530 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1531}
1532
1533/**
1534 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1535 * @vsi: the VSI being setup
1536 * @ctxt: VSI context structure
1537 * @enabled_tc: Enabled TCs bitmap
1538 * @is_add: True if called before Add VSI
1539 *
1540 * Setup VSI queue mapping for enabled traffic classes.
1541 **/
38e00438
VD		 1542#ifdef I40E_FCOE
1543void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1544 struct i40e_vsi_context *ctxt,
1545 u8 enabled_tc,
1546 bool is_add)
1547#else
41c445ff
JB		 1548static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1549 struct i40e_vsi_context *ctxt,
1550 u8 enabled_tc,
1551 bool is_add)
38e00438 1552#endif
41c445ff
JB		 1553{
1554 struct i40e_pf *pf = vsi->back;
1555 u16 sections = 0;
1556 u8 netdev_tc = 0;
1557 u16 numtc = 0;
1558 u16 qcount;
1559 u8 offset;
1560 u16 qmap;
1561 int i;
4e3b35b0 1562 u16 num_tc_qps = 0;
41c445ff
JB		 1563
1564 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1565 offset = 0;
1566
1567 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1568 /* Find numtc from enabled TC bitmap */
1569 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1570 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1571 numtc++;
1572 }
1573 if (!numtc) {
1574 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1575 numtc = 1;
1576 }
1577 } else {
1578 /* At least TC0 is enabled in case of non-DCB case */
1579 numtc = 1;
1580 }
1581
1582 vsi->tc_config.numtc = numtc;
1583 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1584 /* Number of queues per enabled TC */
7f9ff476
AS		 1585 /* In MFP case we can have a much lower count of MSIx
1586 * vectors available and so we need to lower the used
1587 * q count.
1588 */
26cdc443
ASJ		 1589 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1590 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1591 else
1592 qcount = vsi->alloc_queue_pairs;
7f9ff476 1593 num_tc_qps = qcount / numtc;
e25d00b8 1594 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1595
1596 /* Setup queue offset/count for all TCs for given VSI */
1597 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1598 /* See if the given TC is enabled for the given VSI */
75f5cea9 1599 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1600 /* TC is enabled */
41c445ff
JB		 1601 int pow, num_qps;
1602
41c445ff
JB		 1603 switch (vsi->type) {
1604 case I40E_VSI_MAIN:
acd65448
HZ		 1605 qcount = min_t(int, pf->alloc_rss_size,
1606 num_tc_qps);
41c445ff 1607 break;
38e00438
VD		 1608#ifdef I40E_FCOE
1609 case I40E_VSI_FCOE:
1610 qcount = num_tc_qps;
1611 break;
1612#endif
41c445ff
JB		 1613 case I40E_VSI_FDIR:
1614 case I40E_VSI_SRIOV:
1615 case I40E_VSI_VMDQ2:
1616 default:
4e3b35b0 1617 qcount = num_tc_qps;
41c445ff
JB		 1618 WARN_ON(i != 0);
1619 break;
1620 }
4e3b35b0
NP		 1621 vsi->tc_config.tc_info[i].qoffset = offset;
1622 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1623
1e200e4a 1624 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1625 num_qps = qcount;
41c445ff 1626 pow = 0;
41a1d04b 1627 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1628 pow++;
1629 num_qps >>= 1;
1630 }
1631
1632 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1633 qmap =
1634 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1635 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1636
4e3b35b0 1637 offset += qcount;
41c445ff
JB		 1638 } else {
1639 /* TC is not enabled so set the offset to
1640 * default queue and allocate one queue
1641 * for the given TC.
1642 */
1643 vsi->tc_config.tc_info[i].qoffset = 0;
1644 vsi->tc_config.tc_info[i].qcount = 1;
1645 vsi->tc_config.tc_info[i].netdev_tc = 0;
1646
1647 qmap = 0;
1648 }
1649 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1650 }
1651
1652 /* Set actual Tx/Rx queue pairs */
1653 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1654 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1655 if (vsi->req_queue_pairs > 0)
1656 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1657 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1658 vsi->num_queue_pairs = pf->num_lan_msix;
1659 }
41c445ff
JB		 1660
1661 /* Scheduler section valid can only be set for ADD VSI */
1662 if (is_add) {
1663 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1664
1665 ctxt->info.up_enable_bits = enabled_tc;
1666 }
1667 if (vsi->type == I40E_VSI_SRIOV) {
1668 ctxt->info.mapping_flags |=
1669 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1670 for (i = 0; i < vsi->num_queue_pairs; i++)
1671 ctxt->info.queue_mapping[i] =
1672 cpu_to_le16(vsi->base_queue + i);
1673 } else {
1674 ctxt->info.mapping_flags |=
1675 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1676 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1677 }
1678 ctxt->info.valid_sections |= cpu_to_le16(sections);
1679}
1680
1681/**
1682 * i40e_set_rx_mode - NDO callback to set the netdev filters
1683 * @netdev: network interface device structure
1684 **/
38e00438
VD		 1685#ifdef I40E_FCOE
1686void i40e_set_rx_mode(struct net_device *netdev)
1687#else
41c445ff 1688static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1689#endif
41c445ff
JB		 1690{
1691 struct i40e_netdev_priv *np = netdev_priv(netdev);
1692 struct i40e_mac_filter *f, *ftmp;
1693 struct i40e_vsi *vsi = np->vsi;
1694 struct netdev_hw_addr *uca;
1695 struct netdev_hw_addr *mca;
1696 struct netdev_hw_addr *ha;
1697
21659035
KP		 1698 spin_lock_bh(&vsi->mac_filter_list_lock);
1699
41c445ff
JB		 1700 /* add addr if not already in the filter list */
1701 netdev_for_each_uc_addr(uca, netdev) {
1702 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1703 if (i40e_is_vsi_in_vlan(vsi))
1704 i40e_put_mac_in_vlan(vsi, uca->addr,
1705 false, true);
1706 else
1707 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1708 false, true);
1709 }
1710 }
1711
1712 netdev_for_each_mc_addr(mca, netdev) {
1713 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1714 if (i40e_is_vsi_in_vlan(vsi))
1715 i40e_put_mac_in_vlan(vsi, mca->addr,
1716 false, true);
1717 else
1718 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1719 false, true);
1720 }
1721 }
1722
1723 /* remove filter if not in netdev list */
1724 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1725
1726 if (!f->is_netdev)
1727 continue;
1728
2f41f335
SN		 1729 netdev_for_each_mc_addr(mca, netdev)
1730 if (ether_addr_equal(mca->addr, f->macaddr))
1731 goto bottom_of_search_loop;
41c445ff 1732
2f41f335
SN		 1733 netdev_for_each_uc_addr(uca, netdev)
1734 if (ether_addr_equal(uca->addr, f->macaddr))
1735 goto bottom_of_search_loop;
1736
1737 for_each_dev_addr(netdev, ha)
1738 if (ether_addr_equal(ha->addr, f->macaddr))
1739 goto bottom_of_search_loop;
1740
1741 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1742 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1743
1744bottom_of_search_loop:
1745 continue;
41c445ff 1746 }
21659035 1747 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1748
1749 /* check for other flag changes */
1750 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1751 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1752 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1753 }
1754}
1755
21659035
KP		 1756/**
1757 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1758 * @src: source MAC filter entry to be clones
1759 *
1760 * Returns the pointer to newly cloned MAC filter entry or NULL
1761 * in case of error
1762 **/
1763static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1764 struct i40e_mac_filter *src)
1765{
1766 struct i40e_mac_filter *f;
1767
1768 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1769 if (!f)
1770 return NULL;
1771 *f = *src;
1772
1773 INIT_LIST_HEAD(&f->list);
1774
1775 return f;
1776}
1777
1778/**
1779 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1780 * @vsi: pointer to vsi struct
1781 * @from: Pointer to list which contains MAC filter entries - changes to
1782 * those entries needs to be undone.
1783 *
1784 * MAC filter entries from list were slated to be removed from device.
1785 **/
1786static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1787 struct list_head *from)
1788{
1789 struct i40e_mac_filter *f, *ftmp;
1790
1791 list_for_each_entry_safe(f, ftmp, from, list) {
1792 f->changed = true;
1793 /* Move the element back into MAC filter list*/
1794 list_move_tail(&f->list, &vsi->mac_filter_list);
1795 }
1796}
1797
1798/**
1799 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1800 * @vsi: pointer to vsi struct
1801 *
1802 * MAC filter entries from list were slated to be added from device.
1803 **/
1804static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1805{
1806 struct i40e_mac_filter *f, *ftmp;
1807
1808 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1809 if (!f->changed && f->counter)
1810 f->changed = true;
1811 }
1812}
1813
1814/**
1815 * i40e_cleanup_add_list - Deletes the element from add list and release
1816 * memory
1817 * @add_list: Pointer to list which contains MAC filter entries
1818 **/
1819static void i40e_cleanup_add_list(struct list_head *add_list)
1820{
1821 struct i40e_mac_filter *f, *ftmp;
1822
1823 list_for_each_entry_safe(f, ftmp, add_list, list) {
1824 list_del(&f->list);
1825 kfree(f);
1826 }
1827}
1828
41c445ff
JB		 1829/**
1830 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1831 * @vsi: ptr to the VSI
1832 *
1833 * Push any outstanding VSI filter changes through the AdminQ.
1834 *
1835 * Returns 0 or error value
1836 **/
17652c63 1837int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1838{
21659035
KP		 1839 struct list_head tmp_del_list, tmp_add_list;
1840 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1841 bool promisc_forced_on = false;
1842 bool add_happened = false;
1843 int filter_list_len = 0;
1844 u32 changed_flags = 0;
ea02e90b 1845 i40e_status aq_ret = 0;
21659035 1846 bool err_cond = false;
ea02e90b 1847 int retval = 0;
41c445ff
JB		 1848 struct i40e_pf *pf;
1849 int num_add = 0;
1850 int num_del = 0;
f1c7e72e 1851 int aq_err = 0;
41c445ff
JB		 1852 u16 cmd_flags;
1853
1854 /* empty array typed pointers, kcalloc later */
1855 struct i40e_aqc_add_macvlan_element_data *add_list;
1856 struct i40e_aqc_remove_macvlan_element_data *del_list;
1857
1858 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1859 usleep_range(1000, 2000);
1860 pf = vsi->back;
1861
1862 if (vsi->netdev) {
1863 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1864 vsi->current_netdev_flags = vsi->netdev->flags;
1865 }
1866
21659035
KP		 1867 INIT_LIST_HEAD(&tmp_del_list);
1868 INIT_LIST_HEAD(&tmp_add_list);
1869
41c445ff
JB		 1870 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1871 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1872
21659035 1873 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1874 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1875 if (!f->changed)
1876 continue;
1877
1878 if (f->counter != 0)
1879 continue;
1880 f->changed = false;
21659035
KP		 1881
1882 /* Move the element into temporary del_list */
1883 list_move_tail(&f->list, &tmp_del_list);
1884 }
1885
1886 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1887 if (!f->changed)
1888 continue;
1889
1890 if (f->counter == 0)
1891 continue;
1892 f->changed = false;
1893
1894 /* Clone MAC filter entry and add into temporary list */
1895 fclone = i40e_mac_filter_entry_clone(f);
1896 if (!fclone) {
1897 err_cond = true;
1898 break;
1899 }
1900 list_add_tail(&fclone->list, &tmp_add_list);
1901 }
1902
1903 /* if failed to clone MAC filter entry - undo */
1904 if (err_cond) {
1905 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1906 i40e_undo_add_filter_entries(vsi);
1907 }
1908 spin_unlock_bh(&vsi->mac_filter_list_lock);
1909
ea02e90b 1910 if (err_cond) {
21659035 1911 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1912 retval = -ENOMEM;
1913 goto out;
1914 }
21659035
KP		 1915 }
1916
1917 /* Now process 'del_list' outside the lock */
1918 if (!list_empty(&tmp_del_list)) {
1919 filter_list_len = pf->hw.aq.asq_buf_size /
1920 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1921 del_list = kcalloc(filter_list_len,
1922 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1923 GFP_KERNEL);
1924 if (!del_list) {
1925 i40e_cleanup_add_list(&tmp_add_list);
1926
1927 /* Undo VSI's MAC filter entry element updates */
1928 spin_lock_bh(&vsi->mac_filter_list_lock);
1929 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1930 i40e_undo_add_filter_entries(vsi);
1931 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1932 retval = -ENOMEM;
1933 goto out;
21659035
KP		 1934 }
1935
1936 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1937 cmd_flags = 0;
1938
1939 /* add to delete list */
9a173901 1940 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1941 del_list[num_del].vlan_tag =
1942 cpu_to_le16((u16)(f->vlan ==
1943 I40E_VLAN_ANY ? 0 : f->vlan));
1944
41c445ff
JB		 1945 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1946 del_list[num_del].flags = cmd_flags;
1947 num_del++;
1948
41c445ff
JB		 1949 /* flush a full buffer */
1950 if (num_del == filter_list_len) {
ea02e90b
MW		 1951 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1952 vsi->seid,
1953 del_list,
1954 num_del,
1955 NULL);
f1c7e72e 1956 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1957 num_del = 0;
1958 memset(del_list, 0, sizeof(*del_list));
1959
ea02e90b
MW		 1960 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1961 retval = -EIO;
21659035
KP		 1962 dev_err(&pf->pdev->dev,
1963 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
ea02e90b 1964 i40e_stat_str(&pf->hw, aq_ret),
21659035 1965 i40e_aq_str(&pf->hw, aq_err));
ea02e90b 1966 }
41c445ff 1967 }
21659035
KP		 1968 /* Release memory for MAC filter entries which were
1969 * synced up with HW.
1970 */
1971 list_del(&f->list);
1972 kfree(f);
41c445ff 1973 }
21659035 1974
41c445ff 1975 if (num_del) {
ea02e90b
MW		 1976 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
1977 del_list, num_del,
1978 NULL);
f1c7e72e 1979 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1980 num_del = 0;
1981
ea02e90b 1982 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1983 dev_info(&pf->pdev->dev,
f1c7e72e 1984 "ignoring delete macvlan error, err %s aq_err %s\n",
ea02e90b 1985 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 1986 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1987 }
1988
1989 kfree(del_list);
1990 del_list = NULL;
21659035
KP		 1991 }
1992
1993 if (!list_empty(&tmp_add_list)) {
41c445ff
JB		 1994
1995 /* do all the adds now */
1996 filter_list_len = pf->hw.aq.asq_buf_size /
1997 sizeof(struct i40e_aqc_add_macvlan_element_data),
1998 add_list = kcalloc(filter_list_len,
1999 sizeof(struct i40e_aqc_add_macvlan_element_data),
2000 GFP_KERNEL);
21659035
KP		 2001 if (!add_list) {
2002 /* Purge element from temporary lists */
2003 i40e_cleanup_add_list(&tmp_add_list);
2004
2005 /* Undo add filter entries from VSI MAC filter list */
2006 spin_lock_bh(&vsi->mac_filter_list_lock);
2007 i40e_undo_add_filter_entries(vsi);
2008 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2009 retval = -ENOMEM;
2010 goto out;
21659035 2011 }
41c445ff 2012
21659035 2013 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2014
41c445ff
JB		 2015 add_happened = true;
2016 cmd_flags = 0;
2017
2018 /* add to add array */
9a173901 2019 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2020 add_list[num_add].vlan_tag =
2021 cpu_to_le16(
2022 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2023 add_list[num_add].queue_number = 0;
2024
2025 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2026 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2027 num_add++;
2028
2029 /* flush a full buffer */
2030 if (num_add == filter_list_len) {
ea02e90b
MW		 2031 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2032 add_list, num_add,
2033 NULL);
f1c7e72e 2034 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2035 num_add = 0;
2036
ea02e90b 2037 if (aq_ret)
41c445ff
JB		 2038 break;
2039 memset(add_list, 0, sizeof(*add_list));
2040 }
21659035
KP		 2041 /* Entries from tmp_add_list were cloned from MAC
2042 * filter list, hence clean those cloned entries
2043 */
2044 list_del(&f->list);
2045 kfree(f);
41c445ff 2046 }
21659035 2047
41c445ff 2048 if (num_add) {
ea02e90b
MW		 2049 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2050 add_list, num_add, NULL);
f1c7e72e 2051 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2052 num_add = 0;
2053 }
2054 kfree(add_list);
2055 add_list = NULL;
2056
ea02e90b
MW		 2057 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2058 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2059 dev_info(&pf->pdev->dev,
f1c7e72e 2060 "add filter failed, err %s aq_err %s\n",
ea02e90b 2061 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2062 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2063 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2064 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2065 &vsi->state)) {
2066 promisc_forced_on = true;
2067 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2068 &vsi->state);
2069 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2070 }
2071 }
2072 }
2073
2074 /* check for changes in promiscuous modes */
2075 if (changed_flags & IFF_ALLMULTI) {
2076 bool cur_multipromisc;
6995b36c 2077
41c445ff 2078 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2079 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2080 vsi->seid,
2081 cur_multipromisc,
2082 NULL);
2083 if (aq_ret) {
2084 retval = i40e_aq_rc_to_posix(aq_ret,
2085 pf->hw.aq.asq_last_status);
41c445ff 2086 dev_info(&pf->pdev->dev,
f1c7e72e 2087 "set multi promisc failed, err %s aq_err %s\n",
ea02e90b 2088 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2089 i40e_aq_str(&pf->hw,
2090 pf->hw.aq.asq_last_status));
ea02e90b 2091 }
41c445ff
JB		 2092 }
2093 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2094 bool cur_promisc;
6995b36c 2095
41c445ff
JB		 2096 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2097 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2098 &vsi->state));
92faef85
ASJ		 2099 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
2100 /* set defport ON for Main VSI instead of true promisc
2101 * this way we will get all unicast/multicast and VLAN
2102 * promisc behavior but will not get VF or VMDq traffic
2103 * replicated on the Main VSI.
2104 */
2105 if (pf->cur_promisc != cur_promisc) {
2106 pf->cur_promisc = cur_promisc;
0e4425ed 2107 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2108 }
2109 } else {
ea02e90b 2110 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
92faef85 2111 &vsi->back->hw,
f1c7e72e
SN		 2112 vsi->seid,
2113 cur_promisc, NULL);
ea02e90b
MW		 2114 if (aq_ret) {
2115 retval =
2116 i40e_aq_rc_to_posix(aq_ret,
2117 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2118 dev_info(&pf->pdev->dev,
2119 "set unicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2120 aq_ret, pf->hw.aq.asq_last_status);
2121 }
2122 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
92faef85
ASJ		 2123 &vsi->back->hw,
2124 vsi->seid,
2125 cur_promisc, NULL);
ea02e90b
MW		 2126 if (aq_ret) {
2127 retval =
2128 i40e_aq_rc_to_posix(aq_ret,
2129 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2130 dev_info(&pf->pdev->dev,
2131 "set multicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2132 aq_ret, pf->hw.aq.asq_last_status);
2133 }
92faef85 2134 }
ea02e90b
MW		 2135 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2136 vsi->seid,
2137 cur_promisc, NULL);
2138 if (aq_ret) {
2139 retval = i40e_aq_rc_to_posix(aq_ret,
2140 pf->hw.aq.asq_last_status);
1a10370a 2141 dev_info(&pf->pdev->dev,
f1c7e72e 2142 "set brdcast promisc failed, err %s, aq_err %s\n",
ea02e90b 2143 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2144 i40e_aq_str(&pf->hw,
2145 pf->hw.aq.asq_last_status));
ea02e90b 2146 }
41c445ff 2147 }
ea02e90b 2148out:
41c445ff 2149 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2150 return retval;
41c445ff
JB		 2151}
2152
2153/**
2154 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2155 * @pf: board private structure
2156 **/
2157static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2158{
2159 int v;
2160
2161 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2162 return;
2163 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2164
505682cd 2165 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2166 if (pf->vsi[v] &&
17652c63
JB		 2167 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2168 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2169
2170 if (ret) {
2171 /* come back and try again later */
2172 pf->flags |= I40E_FLAG_FILTER_SYNC;
2173 break;
2174 }
2175 }
41c445ff
JB		 2176 }
2177}
2178
2179/**
2180 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2181 * @netdev: network interface device structure
2182 * @new_mtu: new value for maximum frame size
2183 *
2184 * Returns 0 on success, negative on failure
2185 **/
2186static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2187{
2188 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2189 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2190 struct i40e_vsi *vsi = np->vsi;
2191
2192 /* MTU < 68 is an error and causes problems on some kernels */
2193 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2194 return -EINVAL;
2195
2196 netdev_info(netdev, "changing MTU from %d to %d\n",
2197 netdev->mtu, new_mtu);
2198 netdev->mtu = new_mtu;
2199 if (netif_running(netdev))
2200 i40e_vsi_reinit_locked(vsi);
2201
2202 return 0;
2203}
2204
beb0dff1
JK		 2205/**
2206 * i40e_ioctl - Access the hwtstamp interface
2207 * @netdev: network interface device structure
2208 * @ifr: interface request data
2209 * @cmd: ioctl command
2210 **/
2211int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2212{
2213 struct i40e_netdev_priv *np = netdev_priv(netdev);
2214 struct i40e_pf *pf = np->vsi->back;
2215
2216 switch (cmd) {
2217 case SIOCGHWTSTAMP:
2218 return i40e_ptp_get_ts_config(pf, ifr);
2219 case SIOCSHWTSTAMP:
2220 return i40e_ptp_set_ts_config(pf, ifr);
2221 default:
2222 return -EOPNOTSUPP;
2223 }
2224}
2225
41c445ff
JB		 2226/**
2227 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2228 * @vsi: the vsi being adjusted
2229 **/
2230void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2231{
2232 struct i40e_vsi_context ctxt;
2233 i40e_status ret;
2234
2235 if ((vsi->info.valid_sections &
2236 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2237 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2238 return; /* already enabled */
2239
2240 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2241 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2242 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2243
2244 ctxt.seid = vsi->seid;
1a2f6248 2245 ctxt.info = vsi->info;
41c445ff
JB		 2246 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2247 if (ret) {
2248 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2249 "update vlan stripping failed, err %s aq_err %s\n",
2250 i40e_stat_str(&vsi->back->hw, ret),
2251 i40e_aq_str(&vsi->back->hw,
2252 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2253 }
2254}
2255
2256/**
2257 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2258 * @vsi: the vsi being adjusted
2259 **/
2260void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2261{
2262 struct i40e_vsi_context ctxt;
2263 i40e_status ret;
2264
2265 if ((vsi->info.valid_sections &
2266 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2267 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2268 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2269 return; /* already disabled */
2270
2271 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2272 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2273 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2274
2275 ctxt.seid = vsi->seid;
1a2f6248 2276 ctxt.info = vsi->info;
41c445ff
JB		 2277 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2278 if (ret) {
2279 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2280 "update vlan stripping failed, err %s aq_err %s\n",
2281 i40e_stat_str(&vsi->back->hw, ret),
2282 i40e_aq_str(&vsi->back->hw,
2283 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2284 }
2285}
2286
2287/**
2288 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2289 * @netdev: network interface to be adjusted
2290 * @features: netdev features to test if VLAN offload is enabled or not
2291 **/
2292static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2293{
2294 struct i40e_netdev_priv *np = netdev_priv(netdev);
2295 struct i40e_vsi *vsi = np->vsi;
2296
2297 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2298 i40e_vlan_stripping_enable(vsi);
2299 else
2300 i40e_vlan_stripping_disable(vsi);
2301}
2302
2303/**
2304 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2305 * @vsi: the vsi being configured
2306 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2307 **/
2308int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2309{
2310 struct i40e_mac_filter *f, *add_f;
2311 bool is_netdev, is_vf;
41c445ff
JB		 2312
2313 is_vf = (vsi->type == I40E_VSI_SRIOV);
2314 is_netdev = !!(vsi->netdev);
2315
21659035
KP		 2316 /* Locked once because all functions invoked below iterates list*/
2317 spin_lock_bh(&vsi->mac_filter_list_lock);
2318
41c445ff
JB		 2319 if (is_netdev) {
2320 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2321 is_vf, is_netdev);
2322 if (!add_f) {
2323 dev_info(&vsi->back->pdev->dev,
2324 "Could not add vlan filter %d for %pM\n",
2325 vid, vsi->netdev->dev_addr);
21659035 2326 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2327 return -ENOMEM;
2328 }
2329 }
2330
2331 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2332 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2333 if (!add_f) {
2334 dev_info(&vsi->back->pdev->dev,
2335 "Could not add vlan filter %d for %pM\n",
2336 vid, f->macaddr);
21659035 2337 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2338 return -ENOMEM;
2339 }
2340 }
2341
41c445ff
JB		 2342 /* Now if we add a vlan tag, make sure to check if it is the first
2343 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2344 * with 0, so we now accept untagged and specified tagged traffic
2345 * (and not any taged and untagged)
2346 */
2347 if (vid > 0) {
2348 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2349 I40E_VLAN_ANY,
2350 is_vf, is_netdev)) {
2351 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2352 I40E_VLAN_ANY, is_vf, is_netdev);
2353 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2354 is_vf, is_netdev);
2355 if (!add_f) {
2356 dev_info(&vsi->back->pdev->dev,
2357 "Could not add filter 0 for %pM\n",
2358 vsi->netdev->dev_addr);
21659035 2359 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2360 return -ENOMEM;
2361 }
2362 }
8d82a7c5 2363 }
41c445ff 2364
8d82a7c5
GR		 2365 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2366 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2367 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2368 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2369 is_vf, is_netdev))
2370 continue;
2371 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2372 is_vf, is_netdev);
2373 add_f = i40e_add_filter(vsi, f->macaddr,
2374 0, is_vf, is_netdev);
2375 if (!add_f) {
2376 dev_info(&vsi->back->pdev->dev,
2377 "Could not add filter 0 for %pM\n",
2378 f->macaddr);
2379 spin_unlock_bh(&vsi->mac_filter_list_lock);
2380 return -ENOMEM;
41c445ff
JB		 2381 }
2382 }
41c445ff
JB		 2383 }
2384
21659035
KP		 2385 spin_unlock_bh(&vsi->mac_filter_list_lock);
2386
0e4425ed
JB		 2387 /* schedule our worker thread which will take care of
2388 * applying the new filter changes
2389 */
2390 i40e_service_event_schedule(vsi->back);
2391 return 0;
41c445ff
JB		 2392}
2393
2394/**
2395 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2396 * @vsi: the vsi being configured
2397 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2398 *
2399 * Return: 0 on success or negative otherwise
41c445ff
JB		 2400 **/
2401int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2402{
2403 struct net_device *netdev = vsi->netdev;
2404 struct i40e_mac_filter *f, *add_f;
2405 bool is_vf, is_netdev;
2406 int filter_count = 0;
41c445ff
JB		 2407
2408 is_vf = (vsi->type == I40E_VSI_SRIOV);
2409 is_netdev = !!(netdev);
2410
21659035
KP		 2411 /* Locked once because all functions invoked below iterates list */
2412 spin_lock_bh(&vsi->mac_filter_list_lock);
2413
41c445ff
JB		 2414 if (is_netdev)
2415 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2416
2417 list_for_each_entry(f, &vsi->mac_filter_list, list)
2418 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2419
41c445ff
JB		 2420 /* go through all the filters for this VSI and if there is only
2421 * vid == 0 it means there are no other filters, so vid 0 must
2422 * be replaced with -1. This signifies that we should from now
2423 * on accept any traffic (with any tag present, or untagged)
2424 */
2425 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2426 if (is_netdev) {
2427 if (f->vlan &&
2428 ether_addr_equal(netdev->dev_addr, f->macaddr))
2429 filter_count++;
2430 }
2431
2432 if (f->vlan)
2433 filter_count++;
2434 }
2435
2436 if (!filter_count && is_netdev) {
2437 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2438 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2439 is_vf, is_netdev);
2440 if (!f) {
2441 dev_info(&vsi->back->pdev->dev,
2442 "Could not add filter %d for %pM\n",
2443 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2444 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2445 return -ENOMEM;
2446 }
2447 }
2448
2449 if (!filter_count) {
2450 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2451 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2452 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2453 is_vf, is_netdev);
41c445ff
JB		 2454 if (!add_f) {
2455 dev_info(&vsi->back->pdev->dev,
2456 "Could not add filter %d for %pM\n",
2457 I40E_VLAN_ANY, f->macaddr);
21659035 2458 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2459 return -ENOMEM;
2460 }
2461 }
2462 }
2463
21659035
KP		 2464 spin_unlock_bh(&vsi->mac_filter_list_lock);
2465
0e4425ed
JB		 2466 /* schedule our worker thread which will take care of
2467 * applying the new filter changes
2468 */
2469 i40e_service_event_schedule(vsi->back);
2470 return 0;
41c445ff
JB		 2471}
2472
2473/**
2474 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2475 * @netdev: network interface to be adjusted
2476 * @vid: vlan id to be added
078b5876
JB		 2477 *
2478 * net_device_ops implementation for adding vlan ids
41c445ff 2479 **/
38e00438
VD		 2480#ifdef I40E_FCOE
2481int i40e_vlan_rx_add_vid(struct net_device *netdev,
2482 __always_unused __be16 proto, u16 vid)
2483#else
41c445ff
JB		 2484static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2485 __always_unused __be16 proto, u16 vid)
38e00438 2486#endif
41c445ff
JB		 2487{
2488 struct i40e_netdev_priv *np = netdev_priv(netdev);
2489 struct i40e_vsi *vsi = np->vsi;
078b5876 2490 int ret = 0;
41c445ff
JB		 2491
2492 if (vid > 4095)
078b5876
JB		 2493 return -EINVAL;
2494
2495 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2496
6982d429
ASJ		 2497 /* If the network stack called us with vid = 0 then
2498 * it is asking to receive priority tagged packets with
2499 * vlan id 0. Our HW receives them by default when configured
2500 * to receive untagged packets so there is no need to add an
2501 * extra filter for vlan 0 tagged packets.
41c445ff 2502 */
6982d429
ASJ		 2503 if (vid)
2504 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2505
078b5876
JB		 2506 if (!ret && (vid < VLAN_N_VID))
2507 set_bit(vid, vsi->active_vlans);
41c445ff 2508
078b5876 2509 return ret;
41c445ff
JB		 2510}
2511
2512/**
2513 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2514 * @netdev: network interface to be adjusted
2515 * @vid: vlan id to be removed
078b5876 2516 *
fdfd943e 2517 * net_device_ops implementation for removing vlan ids
41c445ff 2518 **/
38e00438
VD		 2519#ifdef I40E_FCOE
2520int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2521 __always_unused __be16 proto, u16 vid)
2522#else
41c445ff
JB		 2523static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2524 __always_unused __be16 proto, u16 vid)
38e00438 2525#endif
41c445ff
JB		 2526{
2527 struct i40e_netdev_priv *np = netdev_priv(netdev);
2528 struct i40e_vsi *vsi = np->vsi;
2529
078b5876
JB		 2530 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2531
41c445ff
JB		 2532 /* return code is ignored as there is nothing a user
2533 * can do about failure to remove and a log message was
078b5876 2534 * already printed from the other function
41c445ff
JB		 2535 */
2536 i40e_vsi_kill_vlan(vsi, vid);
2537
2538 clear_bit(vid, vsi->active_vlans);
078b5876 2539
41c445ff
JB		 2540 return 0;
2541}
2542
2543/**
2544 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2545 * @vsi: the vsi being brought back up
2546 **/
2547static void i40e_restore_vlan(struct i40e_vsi *vsi)
2548{
2549 u16 vid;
2550
2551 if (!vsi->netdev)
2552 return;
2553
2554 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2555
2556 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2557 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2558 vid);
2559}
2560
2561/**
2562 * i40e_vsi_add_pvid - Add pvid for the VSI
2563 * @vsi: the vsi being adjusted
2564 * @vid: the vlan id to set as a PVID
2565 **/
dcae29be 2566int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2567{
2568 struct i40e_vsi_context ctxt;
f1c7e72e 2569 i40e_status ret;
41c445ff
JB		 2570
2571 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2572 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2573 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2574 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2575 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2576
2577 ctxt.seid = vsi->seid;
1a2f6248 2578 ctxt.info = vsi->info;
f1c7e72e
SN		 2579 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2580 if (ret) {
41c445ff 2581 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2582 "add pvid failed, err %s aq_err %s\n",
2583 i40e_stat_str(&vsi->back->hw, ret),
2584 i40e_aq_str(&vsi->back->hw,
2585 vsi->back->hw.aq.asq_last_status));
dcae29be 2586 return -ENOENT;
41c445ff
JB		 2587 }
2588
dcae29be 2589 return 0;
41c445ff
JB		 2590}
2591
2592/**
2593 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2594 * @vsi: the vsi being adjusted
2595 *
2596 * Just use the vlan_rx_register() service to put it back to normal
2597 **/
2598void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2599{
6c12fcbf
GR		 2600 i40e_vlan_stripping_disable(vsi);
2601
41c445ff 2602 vsi->info.pvid = 0;
41c445ff
JB		 2603}
2604
2605/**
2606 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2607 * @vsi: ptr to the VSI
2608 *
2609 * If this function returns with an error, then it's possible one or
2610 * more of the rings is populated (while the rest are not). It is the
2611 * callers duty to clean those orphaned rings.
2612 *
2613 * Return 0 on success, negative on failure
2614 **/
2615static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2616{
2617 int i, err = 0;
2618
2619 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2620 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2621
2622 return err;
2623}
2624
2625/**
2626 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2627 * @vsi: ptr to the VSI
2628 *
2629 * Free VSI's transmit software resources
2630 **/
2631static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2632{
2633 int i;
2634
8e9dca53
GR		 2635 if (!vsi->tx_rings)
2636 return;
2637
41c445ff 2638 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2639 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2640 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2641}
2642
2643/**
2644 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2645 * @vsi: ptr to the VSI
2646 *
2647 * If this function returns with an error, then it's possible one or
2648 * more of the rings is populated (while the rest are not). It is the
2649 * callers duty to clean those orphaned rings.
2650 *
2651 * Return 0 on success, negative on failure
2652 **/
2653static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2654{
2655 int i, err = 0;
2656
2657 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2658 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2659#ifdef I40E_FCOE
2660 i40e_fcoe_setup_ddp_resources(vsi);
2661#endif
41c445ff
JB		 2662 return err;
2663}
2664
2665/**
2666 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2667 * @vsi: ptr to the VSI
2668 *
2669 * Free all receive software resources
2670 **/
2671static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2672{
2673 int i;
2674
8e9dca53
GR		 2675 if (!vsi->rx_rings)
2676 return;
2677
41c445ff 2678 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2679 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2680 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2681#ifdef I40E_FCOE
2682 i40e_fcoe_free_ddp_resources(vsi);
2683#endif
41c445ff
JB		 2684}
2685
3ffa037d
NP		 2686/**
2687 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2688 * @ring: The Tx ring to configure
2689 *
2690 * This enables/disables XPS for a given Tx descriptor ring
2691 * based on the TCs enabled for the VSI that ring belongs to.
2692 **/
2693static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2694{
2695 struct i40e_vsi *vsi = ring->vsi;
2696 cpumask_var_t mask;
2697
9a660eea
JB		 2698 if (!ring->q_vector || !ring->netdev)
2699 return;
2700
2701 /* Single TC mode enable XPS */
2702 if (vsi->tc_config.numtc <= 1) {
2703 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2704 netif_set_xps_queue(ring->netdev,
2705 &ring->q_vector->affinity_mask,
2706 ring->queue_index);
9a660eea
JB		 2707 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2708 /* Disable XPS to allow selection based on TC */
2709 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2710 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2711 free_cpumask_var(mask);
3ffa037d 2712 }
0e4425ed
JB		 2713
2714 /* schedule our worker thread which will take care of
2715 * applying the new filter changes
2716 */
2717 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2718}
2719
41c445ff
JB		 2720/**
2721 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2722 * @ring: The Tx ring to configure
2723 *
2724 * Configure the Tx descriptor ring in the HMC context.
2725 **/
2726static int i40e_configure_tx_ring(struct i40e_ring *ring)
2727{
2728 struct i40e_vsi *vsi = ring->vsi;
2729 u16 pf_q = vsi->base_queue + ring->queue_index;
2730 struct i40e_hw *hw = &vsi->back->hw;
2731 struct i40e_hmc_obj_txq tx_ctx;
2732 i40e_status err = 0;
2733 u32 qtx_ctl = 0;
2734
2735 /* some ATR related tx ring init */
60ea5f83 2736 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2737 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2738 ring->atr_count = 0;
2739 } else {
2740 ring->atr_sample_rate = 0;
2741 }
2742
3ffa037d
NP		 2743 /* configure XPS */
2744 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2745
2746 /* clear the context structure first */
2747 memset(&tx_ctx, 0, sizeof(tx_ctx));
2748
2749 tx_ctx.new_context = 1;
2750 tx_ctx.base = (ring->dma / 128);
2751 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2752 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2753 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2754#ifdef I40E_FCOE
2755 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2756#endif
beb0dff1 2757 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2758 /* FDIR VSI tx ring can still use RS bit and writebacks */
2759 if (vsi->type != I40E_VSI_FDIR)
2760 tx_ctx.head_wb_ena = 1;
2761 tx_ctx.head_wb_addr = ring->dma +
2762 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2763
2764 /* As part of VSI creation/update, FW allocates certain
2765 * Tx arbitration queue sets for each TC enabled for
2766 * the VSI. The FW returns the handles to these queue
2767 * sets as part of the response buffer to Add VSI,
2768 * Update VSI, etc. AQ commands. It is expected that
2769 * these queue set handles be associated with the Tx
2770 * queues by the driver as part of the TX queue context
2771 * initialization. This has to be done regardless of
2772 * DCB as by default everything is mapped to TC0.
2773 */
2774 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2775 tx_ctx.rdylist_act = 0;
2776
2777 /* clear the context in the HMC */
2778 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2779 if (err) {
2780 dev_info(&vsi->back->pdev->dev,
2781 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2782 ring->queue_index, pf_q, err);
2783 return -ENOMEM;
2784 }
2785
2786 /* set the context in the HMC */
2787 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2788 if (err) {
2789 dev_info(&vsi->back->pdev->dev,
2790 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2791 ring->queue_index, pf_q, err);
2792 return -ENOMEM;
2793 }
2794
2795 /* Now associate this queue with this PCI function */
7a28d885 2796 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2797 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2798 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2799 I40E_QTX_CTL_VFVM_INDX_MASK;
2800 } else {
9d8bf547 2801 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2802 }
2803
13fd9774
SN		 2804 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2805 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2806 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2807 i40e_flush(hw);
2808
41c445ff
JB		 2809 /* cache tail off for easier writes later */
2810 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2811
2812 return 0;
2813}
2814
2815/**
2816 * i40e_configure_rx_ring - Configure a receive ring context
2817 * @ring: The Rx ring to configure
2818 *
2819 * Configure the Rx descriptor ring in the HMC context.
2820 **/
2821static int i40e_configure_rx_ring(struct i40e_ring *ring)
2822{
2823 struct i40e_vsi *vsi = ring->vsi;
2824 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2825 u16 pf_q = vsi->base_queue + ring->queue_index;
2826 struct i40e_hw *hw = &vsi->back->hw;
2827 struct i40e_hmc_obj_rxq rx_ctx;
2828 i40e_status err = 0;
2829
2830 ring->state = 0;
2831
2832 /* clear the context structure first */
2833 memset(&rx_ctx, 0, sizeof(rx_ctx));
2834
2835 ring->rx_buf_len = vsi->rx_buf_len;
2836 ring->rx_hdr_len = vsi->rx_hdr_len;
2837
2838 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2839 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2840
2841 rx_ctx.base = (ring->dma / 128);
2842 rx_ctx.qlen = ring->count;
2843
2844 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2845 set_ring_16byte_desc_enabled(ring);
2846 rx_ctx.dsize = 0;
2847 } else {
2848 rx_ctx.dsize = 1;
2849 }
2850
2851 rx_ctx.dtype = vsi->dtype;
2852 if (vsi->dtype) {
2853 set_ring_ps_enabled(ring);
2854 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2855 I40E_RX_SPLIT_IP |
2856 I40E_RX_SPLIT_TCP_UDP |
2857 I40E_RX_SPLIT_SCTP;
2858 } else {
2859 rx_ctx.hsplit_0 = 0;
2860 }
2861
2862 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2863 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2864 if (hw->revision_id == 0)
2865 rx_ctx.lrxqthresh = 0;
2866 else
2867 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2868 rx_ctx.crcstrip = 1;
2869 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2870 /* this controls whether VLAN is stripped from inner headers */
2871 rx_ctx.showiv = 0;
38e00438
VD		 2872#ifdef I40E_FCOE
2873 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2874#endif
acb3676b
CS		 2875 /* set the prefena field to 1 because the manual says to */
2876 rx_ctx.prefena = 1;
41c445ff
JB		 2877
2878 /* clear the context in the HMC */
2879 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2880 if (err) {
2881 dev_info(&vsi->back->pdev->dev,
2882 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2883 ring->queue_index, pf_q, err);
2884 return -ENOMEM;
2885 }
2886
2887 /* set the context in the HMC */
2888 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2889 if (err) {
2890 dev_info(&vsi->back->pdev->dev,
2891 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2892 ring->queue_index, pf_q, err);
2893 return -ENOMEM;
2894 }
2895
2896 /* cache tail for quicker writes, and clear the reg before use */
2897 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2898 writel(0, ring->tail);
2899
a132af24
MW		 2900 if (ring_is_ps_enabled(ring)) {
2901 i40e_alloc_rx_headers(ring);
2902 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2903 } else {
2904 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2905 }
41c445ff
JB		 2906
2907 return 0;
2908}
2909
2910/**
2911 * i40e_vsi_configure_tx - Configure the VSI for Tx
2912 * @vsi: VSI structure describing this set of rings and resources
2913 *
2914 * Configure the Tx VSI for operation.
2915 **/
2916static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2917{
2918 int err = 0;
2919 u16 i;
2920
9f65e15b
AD		 2921 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2922 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2923
2924 return err;
2925}
2926
2927/**
2928 * i40e_vsi_configure_rx - Configure the VSI for Rx
2929 * @vsi: the VSI being configured
2930 *
2931 * Configure the Rx VSI for operation.
2932 **/
2933static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2934{
2935 int err = 0;
2936 u16 i;
2937
2938 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2939 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2940 + ETH_FCS_LEN + VLAN_HLEN;
2941 else
2942 vsi->max_frame = I40E_RXBUFFER_2048;
2943
2944 /* figure out correct receive buffer length */
2945 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2946 I40E_FLAG_RX_PS_ENABLED)) {
2947 case I40E_FLAG_RX_1BUF_ENABLED:
2948 vsi->rx_hdr_len = 0;
2949 vsi->rx_buf_len = vsi->max_frame;
2950 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2951 break;
2952 case I40E_FLAG_RX_PS_ENABLED:
2953 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2954 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2955 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2956 break;
2957 default:
2958 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2959 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2960 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2961 break;
2962 }
2963
38e00438
VD		 2964#ifdef I40E_FCOE
2965 /* setup rx buffer for FCoE */
2966 if ((vsi->type == I40E_VSI_FCOE) &&
2967 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2968 vsi->rx_hdr_len = 0;
2969 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2970 vsi->max_frame = I40E_RXBUFFER_3072;
2971 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2972 }
2973
2974#endif /* I40E_FCOE */
41c445ff
JB		 2975 /* round up for the chip's needs */
2976 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2977 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2978 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2979 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2980
2981 /* set up individual rings */
2982 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2983 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2984
2985 return err;
2986}
2987
2988/**
2989 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2990 * @vsi: ptr to the VSI
2991 **/
2992static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2993{
e7046ee1 2994 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2995 u16 qoffset, qcount;
2996 int i, n;
2997
cd238a3e
PN		 2998 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2999 /* Reset the TC information */
3000 for (i = 0; i < vsi->num_queue_pairs; i++) {
3001 rx_ring = vsi->rx_rings[i];
3002 tx_ring = vsi->tx_rings[i];
3003 rx_ring->dcb_tc = 0;
3004 tx_ring->dcb_tc = 0;
3005 }
3006 }
41c445ff
JB		 3007
3008 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3009 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3010 continue;
3011
3012 qoffset = vsi->tc_config.tc_info[n].qoffset;
3013 qcount = vsi->tc_config.tc_info[n].qcount;
3014 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3015 rx_ring = vsi->rx_rings[i];
3016 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3017 rx_ring->dcb_tc = n;
3018 tx_ring->dcb_tc = n;
3019 }
3020 }
3021}
3022
3023/**
3024 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3025 * @vsi: ptr to the VSI
3026 **/
3027static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3028{
3029 if (vsi->netdev)
3030 i40e_set_rx_mode(vsi->netdev);
3031}
3032
17a73f6b
JG		 3033/**
3034 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3035 * @vsi: Pointer to the targeted VSI
3036 *
3037 * This function replays the hlist on the hw where all the SB Flow Director
3038 * filters were saved.
3039 **/
3040static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3041{
3042 struct i40e_fdir_filter *filter;
3043 struct i40e_pf *pf = vsi->back;
3044 struct hlist_node *node;
3045
55a5e60b
ASJ		 3046 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3047 return;
3048
17a73f6b
JG		 3049 hlist_for_each_entry_safe(filter, node,
3050 &pf->fdir_filter_list, fdir_node) {
3051 i40e_add_del_fdir(vsi, filter, true);
3052 }
3053}
3054
41c445ff
JB		 3055/**
3056 * i40e_vsi_configure - Set up the VSI for action
3057 * @vsi: the VSI being configured
3058 **/
3059static int i40e_vsi_configure(struct i40e_vsi *vsi)
3060{
3061 int err;
3062
3063 i40e_set_vsi_rx_mode(vsi);
3064 i40e_restore_vlan(vsi);
3065 i40e_vsi_config_dcb_rings(vsi);
3066 err = i40e_vsi_configure_tx(vsi);
3067 if (!err)
3068 err = i40e_vsi_configure_rx(vsi);
3069
3070 return err;
3071}
3072
3073/**
3074 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3075 * @vsi: the VSI being configured
3076 **/
3077static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3078{
3079 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3080 struct i40e_hw *hw = &pf->hw;
3081 u16 vector;
3082 int i, q;
41c445ff
JB		 3083 u32 qp;
3084
3085 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3086 * and PFINT_LNKLSTn registers, e.g.:
3087 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3088 */
3089 qp = vsi->base_queue;
3090 vector = vsi->base_vector;
493fb300 3091 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3092 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3093
ee2319cf 3094 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3095 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3096 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3097 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3098 q_vector->rx.itr);
3099 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3100 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3101 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3102 q_vector->tx.itr);
ac26fc13
JB		 3103 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3104 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3105
3106 /* Linked list for the queuepairs assigned to this vector */
3107 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3108 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3109 u32 val;
3110
41c445ff
JB		 3111 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3112 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3113 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3114 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3115 (I40E_QUEUE_TYPE_TX
3116 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3117
3118 wr32(hw, I40E_QINT_RQCTL(qp), val);
3119
3120 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3121 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3122 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3123 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3124 (I40E_QUEUE_TYPE_RX
3125 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3126
3127 /* Terminate the linked list */
3128 if (q == (q_vector->num_ringpairs - 1))
3129 val |= (I40E_QUEUE_END_OF_LIST
3130 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3131
3132 wr32(hw, I40E_QINT_TQCTL(qp), val);
3133 qp++;
3134 }
3135 }
3136
3137 i40e_flush(hw);
3138}
3139
3140/**
3141 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3142 * @hw: ptr to the hardware info
3143 **/
ab437b5a 3144static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3145{
ab437b5a 3146 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3147 u32 val;
3148
3149 /* clear things first */
3150 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3151 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3152
3153 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3154 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3155 I40E_PFINT_ICR0_ENA_GRST_MASK |
3156 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3157 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3158 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3159 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3160 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3161
0d8e1439
ASJ		 3162 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3163 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3164
ab437b5a
JK		 3165 if (pf->flags & I40E_FLAG_PTP)
3166 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3167
41c445ff
JB		 3168 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3169
3170 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3171 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3172 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3173
3174 /* OTHER_ITR_IDX = 0 */
3175 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3176}
3177
3178/**
3179 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3180 * @vsi: the VSI being configured
3181 **/
3182static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3183{
493fb300 3184 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3185 struct i40e_pf *pf = vsi->back;
3186 struct i40e_hw *hw = &pf->hw;
3187 u32 val;
3188
3189 /* set the ITR configuration */
ee2319cf 3190 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3191 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3192 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3193 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3194 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3195 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3196 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3197
ab437b5a 3198 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3199
3200 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3201 wr32(hw, I40E_PFINT_LNKLST0, 0);
3202
f29eaa3d 3203 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3204 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3205 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3206 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3207
3208 wr32(hw, I40E_QINT_RQCTL(0), val);
3209
3210 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3211 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3212 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3213
3214 wr32(hw, I40E_QINT_TQCTL(0), val);
3215 i40e_flush(hw);
3216}
3217
2ef28cfb
MW		 3218/**
3219 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3220 * @pf: board private structure
3221 **/
3222void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3223{
3224 struct i40e_hw *hw = &pf->hw;
3225
3226 wr32(hw, I40E_PFINT_DYN_CTL0,
3227 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3228 i40e_flush(hw);
3229}
3230
41c445ff
JB		 3231/**
3232 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3233 * @pf: board private structure
3234 **/
116a57d4 3235void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3236{
3237 struct i40e_hw *hw = &pf->hw;
3238 u32 val;
3239
3240 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3241 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3242 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3243
3244 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3245 i40e_flush(hw);
3246}
3247
5c2cebda
CW		 3248/**
3249 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3250 * @vsi: pointer to a vsi
03147773 3251 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3252 **/
3253void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3254{
3255 struct i40e_pf *pf = vsi->back;
3256 struct i40e_hw *hw = &pf->hw;
3257 u32 val;
3258
3259 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3260 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3261 i40e_flush(hw);
3262}
3263
41c445ff
JB		 3264/**
3265 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3266 * @irq: interrupt number
3267 * @data: pointer to a q_vector
3268 **/
3269static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3270{
3271 struct i40e_q_vector *q_vector = data;
3272
cd0b6fa6 3273 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3274 return IRQ_HANDLED;
3275
5d3465a1 3276 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3277
3278 return IRQ_HANDLED;
3279}
3280
41c445ff
JB		 3281/**
3282 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3283 * @vsi: the VSI being configured
3284 * @basename: name for the vector
3285 *
3286 * Allocates MSI-X vectors and requests interrupts from the kernel.
3287 **/
3288static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3289{
3290 int q_vectors = vsi->num_q_vectors;
3291 struct i40e_pf *pf = vsi->back;
3292 int base = vsi->base_vector;
3293 int rx_int_idx = 0;
3294 int tx_int_idx = 0;
3295 int vector, err;
3296
3297 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3298 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3299
cd0b6fa6 3300 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3301 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3302 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3303 tx_int_idx++;
cd0b6fa6 3304 } else if (q_vector->rx.ring) {
41c445ff
JB		 3305 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3306 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3307 } else if (q_vector->tx.ring) {
41c445ff
JB		 3308 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3309 "%s-%s-%d", basename, "tx", tx_int_idx++);
3310 } else {
3311 /* skip this unused q_vector */
3312 continue;
3313 }
3314 err = request_irq(pf->msix_entries[base + vector].vector,
3315 vsi->irq_handler,
3316 0,
3317 q_vector->name,
3318 q_vector);
3319 if (err) {
3320 dev_info(&pf->pdev->dev,
fb43201f 3321 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3322 goto free_queue_irqs;
3323 }
3324 /* assign the mask for this irq */
3325 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3326 &q_vector->affinity_mask);
3327 }
3328
63741846 3329 vsi->irqs_ready = true;
41c445ff
JB		 3330 return 0;
3331
3332free_queue_irqs:
3333 while (vector) {
3334 vector--;
3335 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3336 NULL);
3337 free_irq(pf->msix_entries[base + vector].vector,
3338 &(vsi->q_vectors[vector]));
3339 }
3340 return err;
3341}
3342
3343/**
3344 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3345 * @vsi: the VSI being un-configured
3346 **/
3347static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3348{
3349 struct i40e_pf *pf = vsi->back;
3350 struct i40e_hw *hw = &pf->hw;
3351 int base = vsi->base_vector;
3352 int i;
3353
3354 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3355 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3356 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3357 }
3358
3359 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3360 for (i = vsi->base_vector;
3361 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3362 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3363
3364 i40e_flush(hw);
3365 for (i = 0; i < vsi->num_q_vectors; i++)
3366 synchronize_irq(pf->msix_entries[i + base].vector);
3367 } else {
3368 /* Legacy and MSI mode - this stops all interrupt handling */
3369 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3370 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3371 i40e_flush(hw);
3372 synchronize_irq(pf->pdev->irq);
3373 }
3374}
3375
3376/**
3377 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3378 * @vsi: the VSI being configured
3379 **/
3380static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3381{
3382 struct i40e_pf *pf = vsi->back;
3383 int i;
3384
3385 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3386 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3387 i40e_irq_dynamic_enable(vsi, i);
3388 } else {
3389 i40e_irq_dynamic_enable_icr0(pf);
3390 }
3391
1022cb6c 3392 i40e_flush(&pf->hw);
41c445ff
JB		 3393 return 0;
3394}
3395
3396/**
3397 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3398 * @pf: board private structure
3399 **/
3400static void i40e_stop_misc_vector(struct i40e_pf *pf)
3401{
3402 /* Disable ICR 0 */
3403 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3404 i40e_flush(&pf->hw);
3405}
3406
3407/**
3408 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3409 * @irq: interrupt number
3410 * @data: pointer to a q_vector
3411 *
3412 * This is the handler used for all MSI/Legacy interrupts, and deals
3413 * with both queue and non-queue interrupts. This is also used in
3414 * MSIX mode to handle the non-queue interrupts.
3415 **/
3416static irqreturn_t i40e_intr(int irq, void *data)
3417{
3418 struct i40e_pf *pf = (struct i40e_pf *)data;
3419 struct i40e_hw *hw = &pf->hw;
5e823066 3420 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3421 u32 icr0, icr0_remaining;
3422 u32 val, ena_mask;
3423
3424 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3425 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3426
116a57d4
SN		 3427 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3428 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3429 goto enable_intr;
41c445ff 3430
cd92e72f
SN		 3431 /* if interrupt but no bits showing, must be SWINT */
3432 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3433 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3434 pf->sw_int_count++;
3435
0d8e1439
ASJ		 3436 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3437 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3438 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3439 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3440 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3441 }
3442
41c445ff
JB		 3443 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3444 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3445 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3446 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3447
3448 /* temporarily disable queue cause for NAPI processing */
3449 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3450
41c445ff
JB		 3451 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3452 wr32(hw, I40E_QINT_RQCTL(0), qval);
3453
3454 qval = rd32(hw, I40E_QINT_TQCTL(0));
3455 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3456 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3457
3458 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3459 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3460 }
3461
3462 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3463 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3464 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3465 }
3466
3467 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3468 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3469 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3470 }
3471
3472 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3473 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3474 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3475 }
3476
3477 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3478 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3479 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3480 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3481 val = rd32(hw, I40E_GLGEN_RSTAT);
3482 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3483 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3484 if (val == I40E_RESET_CORER) {
41c445ff 3485 pf->corer_count++;
4eb3f768 3486 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3487 pf->globr_count++;
4eb3f768 3488 } else if (val == I40E_RESET_EMPR) {
41c445ff 3489 pf->empr_count++;
9df42d1a 3490 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3491 }
41c445ff
JB		 3492 }
3493
9c010ee0
ASJ		 3494 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3495 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3496 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3497 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3498 rd32(hw, I40E_PFHMC_ERRORINFO),
3499 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3500 }
3501
beb0dff1
JK		 3502 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3503 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3504
3505 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3506 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3507 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3508 }
beb0dff1
JK		 3509 }
3510
41c445ff
JB		 3511 /* If a critical error is pending we have no choice but to reset the
3512 * device.
3513 * Report and mask out any remaining unexpected interrupts.
3514 */
3515 icr0_remaining = icr0 & ena_mask;
3516 if (icr0_remaining) {
3517 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3518 icr0_remaining);
9c010ee0 3519 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3520 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3521 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3522 dev_info(&pf->pdev->dev, "device will be reset\n");
3523 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3524 i40e_service_event_schedule(pf);
41c445ff
JB		 3525 }
3526 ena_mask &= ~icr0_remaining;
3527 }
5e823066 3528 ret = IRQ_HANDLED;
41c445ff 3529
5e823066 3530enable_intr:
41c445ff
JB		 3531 /* re-enable interrupt causes */
3532 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3533 if (!test_bit(__I40E_DOWN, &pf->state)) {
3534 i40e_service_event_schedule(pf);
3535 i40e_irq_dynamic_enable_icr0(pf);
3536 }
3537
5e823066 3538 return ret;
41c445ff
JB		 3539}
3540
cbf61325
ASJ		 3541/**
3542 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3543 * @tx_ring: tx ring to clean
3544 * @budget: how many cleans we're allowed
3545 *
3546 * Returns true if there's any budget left (e.g. the clean is finished)
3547 **/
3548static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3549{
3550 struct i40e_vsi *vsi = tx_ring->vsi;
3551 u16 i = tx_ring->next_to_clean;
3552 struct i40e_tx_buffer *tx_buf;
3553 struct i40e_tx_desc *tx_desc;
3554
3555 tx_buf = &tx_ring->tx_bi[i];
3556 tx_desc = I40E_TX_DESC(tx_ring, i);
3557 i -= tx_ring->count;
3558
3559 do {
3560 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3561
3562 /* if next_to_watch is not set then there is no work pending */
3563 if (!eop_desc)
3564 break;
3565
3566 /* prevent any other reads prior to eop_desc */
3567 read_barrier_depends();
3568
3569 /* if the descriptor isn't done, no work yet to do */
3570 if (!(eop_desc->cmd_type_offset_bsz &
3571 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3572 break;
3573
3574 /* clear next_to_watch to prevent false hangs */
3575 tx_buf->next_to_watch = NULL;
3576
49d7d933
ASJ		 3577 tx_desc->buffer_addr = 0;
3578 tx_desc->cmd_type_offset_bsz = 0;
3579 /* move past filter desc */
3580 tx_buf++;
3581 tx_desc++;
3582 i++;
3583 if (unlikely(!i)) {
3584 i -= tx_ring->count;
3585 tx_buf = tx_ring->tx_bi;
3586 tx_desc = I40E_TX_DESC(tx_ring, 0);
3587 }
cbf61325
ASJ		 3588 /* unmap skb header data */
3589 dma_unmap_single(tx_ring->dev,
3590 dma_unmap_addr(tx_buf, dma),
3591 dma_unmap_len(tx_buf, len),
3592 DMA_TO_DEVICE);
49d7d933
ASJ		 3593 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3594 kfree(tx_buf->raw_buf);
cbf61325 3595
49d7d933
ASJ		 3596 tx_buf->raw_buf = NULL;
3597 tx_buf->tx_flags = 0;
3598 tx_buf->next_to_watch = NULL;
cbf61325 3599 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3600 tx_desc->buffer_addr = 0;
3601 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3602
49d7d933 3603 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3604 tx_buf++;
3605 tx_desc++;
3606 i++;
3607 if (unlikely(!i)) {
3608 i -= tx_ring->count;
3609 tx_buf = tx_ring->tx_bi;
3610 tx_desc = I40E_TX_DESC(tx_ring, 0);
3611 }
3612
3613 /* update budget accounting */
3614 budget--;
3615 } while (likely(budget));
3616
3617 i += tx_ring->count;
3618 tx_ring->next_to_clean = i;
3619
6995b36c 3620 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3621 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3622
cbf61325
ASJ		 3623 return budget > 0;
3624}
3625
3626/**
3627 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3628 * @irq: interrupt number
3629 * @data: pointer to a q_vector
3630 **/
3631static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3632{
3633 struct i40e_q_vector *q_vector = data;
3634 struct i40e_vsi *vsi;
3635
3636 if (!q_vector->tx.ring)
3637 return IRQ_HANDLED;
3638
3639 vsi = q_vector->tx.ring->vsi;
3640 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3641
3642 return IRQ_HANDLED;
3643}
3644
41c445ff 3645/**
cd0b6fa6 3646 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3647 * @vsi: the VSI being configured
3648 * @v_idx: vector index
cd0b6fa6 3649 * @qp_idx: queue pair index
41c445ff 3650 **/
26cdc443 3651static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3652{
493fb300 3653 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3654 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3655 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3656
3657 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3658 tx_ring->next = q_vector->tx.ring;
3659 q_vector->tx.ring = tx_ring;
41c445ff 3660 q_vector->tx.count++;
cd0b6fa6
AD		 3661
3662 rx_ring->q_vector = q_vector;
3663 rx_ring->next = q_vector->rx.ring;
3664 q_vector->rx.ring = rx_ring;
3665 q_vector->rx.count++;
41c445ff
JB		 3666}
3667
3668/**
3669 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3670 * @vsi: the VSI being configured
3671 *
3672 * This function maps descriptor rings to the queue-specific vectors
3673 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3674 * one vector per queue pair, but on a constrained vector budget, we
3675 * group the queue pairs as "efficiently" as possible.
3676 **/
3677static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3678{
3679 int qp_remaining = vsi->num_queue_pairs;
3680 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3681 int num_ringpairs;
41c445ff
JB		 3682 int v_start = 0;
3683 int qp_idx = 0;
3684
3685 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3686 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3687 * It is also important to go through all the vectors available to be
3688 * sure that if we don't use all the vectors, that the remaining vectors
3689 * are cleared. This is especially important when decreasing the
3690 * number of queues in use.
41c445ff 3691 */
70114ec4 3692 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3693 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3694
3695 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3696
3697 q_vector->num_ringpairs = num_ringpairs;
3698
3699 q_vector->rx.count = 0;
3700 q_vector->tx.count = 0;
3701 q_vector->rx.ring = NULL;
3702 q_vector->tx.ring = NULL;
3703
3704 while (num_ringpairs--) {
26cdc443 3705 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3706 qp_idx++;
3707 qp_remaining--;
41c445ff
JB		 3708 }
3709 }
3710}
3711
3712/**
3713 * i40e_vsi_request_irq - Request IRQ from the OS
3714 * @vsi: the VSI being configured
3715 * @basename: name for the vector
3716 **/
3717static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3718{
3719 struct i40e_pf *pf = vsi->back;
3720 int err;
3721
3722 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3723 err = i40e_vsi_request_irq_msix(vsi, basename);
3724 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3725 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3726 pf->int_name, pf);
41c445ff
JB		 3727 else
3728 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3729 pf->int_name, pf);
41c445ff
JB		 3730
3731 if (err)
3732 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3733
3734 return err;
3735}
3736
3737#ifdef CONFIG_NET_POLL_CONTROLLER
3738/**
3739 * i40e_netpoll - A Polling 'interrupt'handler
3740 * @netdev: network interface device structure
3741 *
3742 * This is used by netconsole to send skbs without having to re-enable
3743 * interrupts. It's not called while the normal interrupt routine is executing.
3744 **/
38e00438
VD		 3745#ifdef I40E_FCOE
3746void i40e_netpoll(struct net_device *netdev)
3747#else
41c445ff 3748static void i40e_netpoll(struct net_device *netdev)
38e00438 3749#endif
41c445ff
JB		 3750{
3751 struct i40e_netdev_priv *np = netdev_priv(netdev);
3752 struct i40e_vsi *vsi = np->vsi;
3753 struct i40e_pf *pf = vsi->back;
3754 int i;
3755
3756 /* if interface is down do nothing */
3757 if (test_bit(__I40E_DOWN, &vsi->state))
3758 return;
3759
41c445ff
JB		 3760 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3761 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3762 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3763 } else {
3764 i40e_intr(pf->pdev->irq, netdev);
3765 }
41c445ff
JB		 3766}
3767#endif
3768
23527308
NP		 3769/**
3770 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3771 * @pf: the PF being configured
3772 * @pf_q: the PF queue
3773 * @enable: enable or disable state of the queue
3774 *
3775 * This routine will wait for the given Tx queue of the PF to reach the
3776 * enabled or disabled state.
3777 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3778 * multiple retries; else will return 0 in case of success.
3779 **/
3780static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3781{
3782 int i;
3783 u32 tx_reg;
3784
3785 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3786 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3787 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3788 break;
3789
f98a2006 3790 usleep_range(10, 20);
23527308
NP		 3791 }
3792 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3793 return -ETIMEDOUT;
3794
3795 return 0;
3796}
3797
41c445ff
JB		 3798/**
3799 * i40e_vsi_control_tx - Start or stop a VSI's rings
3800 * @vsi: the VSI being configured
3801 * @enable: start or stop the rings
3802 **/
3803static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3804{
3805 struct i40e_pf *pf = vsi->back;
3806 struct i40e_hw *hw = &pf->hw;
23527308 3807 int i, j, pf_q, ret = 0;
41c445ff
JB		 3808 u32 tx_reg;
3809
3810 pf_q = vsi->base_queue;
3811 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3812
3813 /* warn the TX unit of coming changes */
3814 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3815 if (!enable)
f98a2006 3816 usleep_range(10, 20);
351499ab 3817
6c5ef620 3818 for (j = 0; j < 50; j++) {
41c445ff 3819 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3820 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3821 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3822 break;
3823 usleep_range(1000, 2000);
3824 }
fda972f6 3825 /* Skip if the queue is already in the requested state */
7c122007 3826 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3827 continue;
41c445ff
JB		 3828
3829 /* turn on/off the queue */
c5c9eb9e
SN		 3830 if (enable) {
3831 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3832 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3833 } else {
41c445ff 3834 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3835 }
41c445ff
JB		 3836
3837 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3838 /* No waiting for the Tx queue to disable */
3839 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3840 continue;
41c445ff
JB		 3841
3842 /* wait for the change to finish */
23527308
NP		 3843 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3844 if (ret) {
3845 dev_info(&pf->pdev->dev,
fb43201f
SN		 3846 "VSI seid %d Tx ring %d %sable timeout\n",
3847 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3848 break;
41c445ff
JB		 3849 }
3850 }
3851
7134f9ce
JB		 3852 if (hw->revision_id == 0)
3853 mdelay(50);
23527308
NP		 3854 return ret;
3855}
3856
3857/**
3858 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3859 * @pf: the PF being configured
3860 * @pf_q: the PF queue
3861 * @enable: enable or disable state of the queue
3862 *
3863 * This routine will wait for the given Rx queue of the PF to reach the
3864 * enabled or disabled state.
3865 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3866 * multiple retries; else will return 0 in case of success.
3867 **/
3868static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3869{
3870 int i;
3871 u32 rx_reg;
3872
3873 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3874 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3875 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3876 break;
3877
f98a2006 3878 usleep_range(10, 20);
23527308
NP		 3879 }
3880 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3881 return -ETIMEDOUT;
7134f9ce 3882
41c445ff
JB		 3883 return 0;
3884}
3885
3886/**
3887 * i40e_vsi_control_rx - Start or stop a VSI's rings
3888 * @vsi: the VSI being configured
3889 * @enable: start or stop the rings
3890 **/
3891static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3892{
3893 struct i40e_pf *pf = vsi->back;
3894 struct i40e_hw *hw = &pf->hw;
23527308 3895 int i, j, pf_q, ret = 0;
41c445ff
JB		 3896 u32 rx_reg;
3897
3898 pf_q = vsi->base_queue;
3899 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3900 for (j = 0; j < 50; j++) {
41c445ff 3901 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3902 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3903 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3904 break;
3905 usleep_range(1000, 2000);
3906 }
41c445ff 3907
7c122007
CS		 3908 /* Skip if the queue is already in the requested state */
3909 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3910 continue;
41c445ff
JB		 3911
3912 /* turn on/off the queue */
3913 if (enable)
6c5ef620 3914 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3915 else
6c5ef620 3916 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3917 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3918
3919 /* wait for the change to finish */
23527308
NP		 3920 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3921 if (ret) {
3922 dev_info(&pf->pdev->dev,
fb43201f
SN		 3923 "VSI seid %d Rx ring %d %sable timeout\n",
3924 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3925 break;
41c445ff
JB		 3926 }
3927 }
3928
23527308 3929 return ret;
41c445ff
JB		 3930}
3931
3932/**
3933 * i40e_vsi_control_rings - Start or stop a VSI's rings
3934 * @vsi: the VSI being configured
3935 * @enable: start or stop the rings
3936 **/
fc18eaa0 3937int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3938{
3b867b28 3939 int ret = 0;
41c445ff
JB		 3940
3941 /* do rx first for enable and last for disable */
3942 if (request) {
3943 ret = i40e_vsi_control_rx(vsi, request);
3944 if (ret)
3945 return ret;
3946 ret = i40e_vsi_control_tx(vsi, request);
3947 } else {
3b867b28
ASJ		 3948 /* Ignore return value, we need to shutdown whatever we can */
3949 i40e_vsi_control_tx(vsi, request);
3950 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3951 }
3952
3953 return ret;
3954}
3955
3956/**
3957 * i40e_vsi_free_irq - Free the irq association with the OS
3958 * @vsi: the VSI being configured
3959 **/
3960static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3961{
3962 struct i40e_pf *pf = vsi->back;
3963 struct i40e_hw *hw = &pf->hw;
3964 int base = vsi->base_vector;
3965 u32 val, qp;
3966 int i;
3967
3968 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3969 if (!vsi->q_vectors)
3970 return;
3971
63741846
SN		 3972 if (!vsi->irqs_ready)
3973 return;
3974
3975 vsi->irqs_ready = false;
41c445ff
JB		 3976 for (i = 0; i < vsi->num_q_vectors; i++) {
3977 u16 vector = i + base;
3978
3979 /* free only the irqs that were actually requested */
78681b1f
SN		 3980 if (!vsi->q_vectors[i] ||
3981 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3982 continue;
3983
3984 /* clear the affinity_mask in the IRQ descriptor */
3985 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3986 NULL);
3987 free_irq(pf->msix_entries[vector].vector,
493fb300 3988 vsi->q_vectors[i]);
41c445ff
JB		 3989
3990 /* Tear down the interrupt queue link list
3991 *
3992 * We know that they come in pairs and always
3993 * the Rx first, then the Tx. To clear the
3994 * link list, stick the EOL value into the
3995 * next_q field of the registers.
3996 */
3997 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3998 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3999 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4000 val |= I40E_QUEUE_END_OF_LIST
4001 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4002 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4003
4004 while (qp != I40E_QUEUE_END_OF_LIST) {
4005 u32 next;
4006
4007 val = rd32(hw, I40E_QINT_RQCTL(qp));
4008
4009 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4010 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4011 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4012 I40E_QINT_RQCTL_INTEVENT_MASK);
4013
4014 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4015 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4016
4017 wr32(hw, I40E_QINT_RQCTL(qp), val);
4018
4019 val = rd32(hw, I40E_QINT_TQCTL(qp));
4020
4021 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4022 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4023
4024 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4025 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4026 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4027 I40E_QINT_TQCTL_INTEVENT_MASK);
4028
4029 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4030 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4031
4032 wr32(hw, I40E_QINT_TQCTL(qp), val);
4033 qp = next;
4034 }
4035 }
4036 } else {
4037 free_irq(pf->pdev->irq, pf);
4038
4039 val = rd32(hw, I40E_PFINT_LNKLST0);
4040 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4041 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4042 val |= I40E_QUEUE_END_OF_LIST
4043 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4044 wr32(hw, I40E_PFINT_LNKLST0, val);
4045
4046 val = rd32(hw, I40E_QINT_RQCTL(qp));
4047 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4048 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4049 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4050 I40E_QINT_RQCTL_INTEVENT_MASK);
4051
4052 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4053 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4054
4055 wr32(hw, I40E_QINT_RQCTL(qp), val);
4056
4057 val = rd32(hw, I40E_QINT_TQCTL(qp));
4058
4059 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4060 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4061 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4062 I40E_QINT_TQCTL_INTEVENT_MASK);
4063
4064 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4065 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4066
4067 wr32(hw, I40E_QINT_TQCTL(qp), val);
4068 }
4069}
4070
493fb300
AD		 4071/**
4072 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4073 * @vsi: the VSI being configured
4074 * @v_idx: Index of vector to be freed
4075 *
4076 * This function frees the memory allocated to the q_vector. In addition if
4077 * NAPI is enabled it will delete any references to the NAPI struct prior
4078 * to freeing the q_vector.
4079 **/
4080static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4081{
4082 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4083 struct i40e_ring *ring;
493fb300
AD		 4084
4085 if (!q_vector)
4086 return;
4087
4088 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4089 i40e_for_each_ring(ring, q_vector->tx)
4090 ring->q_vector = NULL;
4091
4092 i40e_for_each_ring(ring, q_vector->rx)
4093 ring->q_vector = NULL;
493fb300
AD		 4094
4095 /* only VSI w/ an associated netdev is set up w/ NAPI */
4096 if (vsi->netdev)
4097 netif_napi_del(&q_vector->napi);
4098
4099 vsi->q_vectors[v_idx] = NULL;
4100
4101 kfree_rcu(q_vector, rcu);
4102}
4103
41c445ff
JB		 4104/**
4105 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4106 * @vsi: the VSI being un-configured
4107 *
4108 * This frees the memory allocated to the q_vectors and
4109 * deletes references to the NAPI struct.
4110 **/
4111static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4112{
4113 int v_idx;
4114
493fb300
AD		 4115 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4116 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4117}
4118
4119/**
4120 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4121 * @pf: board private structure
4122 **/
4123static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4124{
4125 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4126 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4127 pci_disable_msix(pf->pdev);
4128 kfree(pf->msix_entries);
4129 pf->msix_entries = NULL;
3b444399
SN		 4130 kfree(pf->irq_pile);
4131 pf->irq_pile = NULL;
41c445ff
JB		 4132 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4133 pci_disable_msi(pf->pdev);
4134 }
4135 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4136}
4137
4138/**
4139 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4140 * @pf: board private structure
4141 *
4142 * We go through and clear interrupt specific resources and reset the structure
4143 * to pre-load conditions
4144 **/
4145static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4146{
4147 int i;
4148
e147758d
SN		 4149 i40e_stop_misc_vector(pf);
4150 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4151 synchronize_irq(pf->msix_entries[0].vector);
4152 free_irq(pf->msix_entries[0].vector, pf);
4153 }
4154
41c445ff 4155 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4156 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4157 if (pf->vsi[i])
4158 i40e_vsi_free_q_vectors(pf->vsi[i]);
4159 i40e_reset_interrupt_capability(pf);
4160}
4161
4162/**
4163 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4164 * @vsi: the VSI being configured
4165 **/
4166static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4167{
4168 int q_idx;
4169
4170 if (!vsi->netdev)
4171 return;
4172
4173 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4174 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4175}
4176
4177/**
4178 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4179 * @vsi: the VSI being configured
4180 **/
4181static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4182{
4183 int q_idx;
4184
4185 if (!vsi->netdev)
4186 return;
4187
4188 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4189 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4190}
4191
90ef8d47
SN		 4192/**
4193 * i40e_vsi_close - Shut down a VSI
4194 * @vsi: the vsi to be quelled
4195 **/
4196static void i40e_vsi_close(struct i40e_vsi *vsi)
4197{
4198 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4199 i40e_down(vsi);
4200 i40e_vsi_free_irq(vsi);
4201 i40e_vsi_free_tx_resources(vsi);
4202 i40e_vsi_free_rx_resources(vsi);
92faef85 4203 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4204}
4205
41c445ff
JB		 4206/**
4207 * i40e_quiesce_vsi - Pause a given VSI
4208 * @vsi: the VSI being paused
4209 **/
4210static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4211{
4212 if (test_bit(__I40E_DOWN, &vsi->state))
4213 return;
4214
d341b7a5
NP		 4215 /* No need to disable FCoE VSI when Tx suspended */
4216 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4217 vsi->type == I40E_VSI_FCOE) {
4218 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4219 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4220 return;
4221 }
4222
41c445ff 4223 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4224 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4225 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4226 else
90ef8d47 4227 i40e_vsi_close(vsi);
41c445ff
JB		 4228}
4229
4230/**
4231 * i40e_unquiesce_vsi - Resume a given VSI
4232 * @vsi: the VSI being resumed
4233 **/
4234static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4235{
4236 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4237 return;
4238
4239 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4240 if (vsi->netdev && netif_running(vsi->netdev))
4241 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4242 else
8276f757 4243 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4244}
4245
4246/**
4247 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4248 * @pf: the PF
4249 **/
4250static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4251{
4252 int v;
4253
505682cd 4254 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4255 if (pf->vsi[v])
4256 i40e_quiesce_vsi(pf->vsi[v]);
4257 }
4258}
4259
4260/**
4261 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4262 * @pf: the PF
4263 **/
4264static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4265{
4266 int v;
4267
505682cd 4268 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4269 if (pf->vsi[v])
4270 i40e_unquiesce_vsi(pf->vsi[v]);
4271 }
4272}
4273
69129dc3
NP		 4274#ifdef CONFIG_I40E_DCB
4275/**
4276 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4277 * @vsi: the VSI being configured
4278 *
4279 * This function waits for the given VSI's Tx queues to be disabled.
4280 **/
4281static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4282{
4283 struct i40e_pf *pf = vsi->back;
4284 int i, pf_q, ret;
4285
4286 pf_q = vsi->base_queue;
4287 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4288 /* Check and wait for the disable status of the queue */
4289 ret = i40e_pf_txq_wait(pf, pf_q, false);
4290 if (ret) {
4291 dev_info(&pf->pdev->dev,
fb43201f
SN		 4292 "VSI seid %d Tx ring %d disable timeout\n",
4293 vsi->seid, pf_q);
69129dc3
NP		 4294 return ret;
4295 }
4296 }
4297
4298 return 0;
4299}
4300
4301/**
4302 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4303 * @pf: the PF
4304 *
4305 * This function waits for the Tx queues to be in disabled state for all the
4306 * VSIs that are managed by this PF.
4307 **/
4308static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4309{
4310 int v, ret = 0;
4311
4312 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4313 /* No need to wait for FCoE VSI queues */
4314 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4315 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4316 if (ret)
4317 break;
4318 }
4319 }
4320
4321 return ret;
4322}
4323
4324#endif
b03a8c1f
KP		 4325
4326/**
4327 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4328 * @q_idx: TX queue number
4329 * @vsi: Pointer to VSI struct
4330 *
4331 * This function checks specified queue for given VSI. Detects hung condition.
4332 * Sets hung bit since it is two step process. Before next run of service task
4333 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4334 * hung condition remain unchanged and during subsequent run, this function
4335 * issues SW interrupt to recover from hung condition.
4336 **/
4337static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4338{
4339 struct i40e_ring *tx_ring = NULL;
4340 struct i40e_pf *pf;
4341 u32 head, val, tx_pending;
4342 int i;
4343
4344 pf = vsi->back;
4345
4346 /* now that we have an index, find the tx_ring struct */
4347 for (i = 0; i < vsi->num_queue_pairs; i++) {
4348 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4349 if (q_idx == vsi->tx_rings[i]->queue_index) {
4350 tx_ring = vsi->tx_rings[i];
4351 break;
4352 }
4353 }
4354 }
4355
4356 if (!tx_ring)
4357 return;
4358
4359 /* Read interrupt register */
4360 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4361 val = rd32(&pf->hw,
4362 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4363 tx_ring->vsi->base_vector - 1));
4364 else
4365 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4366
9c6c1259
KP		 4367 /* Bail out if interrupts are disabled because napi_poll
4368 * execution in-progress or will get scheduled soon.
4369 * napi_poll cleans TX and RX queues and updates 'next_to_clean'.
4370 */
4371 if (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))
4372 return;
4373
b03a8c1f
KP		 4374 head = i40e_get_head(tx_ring);
4375
4376 tx_pending = i40e_get_tx_pending(tx_ring);
4377
9c6c1259
KP		 4378 /* HW is done executing descriptors, updated HEAD write back,
4379 * but SW hasn't processed those descriptors. If interrupt is
4380 * not generated from this point ON, it could result into
4381 * dev_watchdog detecting timeout on those netdev_queue,
4382 * hence proactively trigger SW interrupt.
b03a8c1f 4383 */
9c6c1259
KP		 4384 if (tx_pending) {
4385 /* NAPI Poll didn't run and clear since it was set */
4386 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4387 &tx_ring->q_vector->hung_detected)) {
4388 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4389 vsi->seid, q_idx, tx_pending,
4390 tx_ring->next_to_clean, head,
4391 tx_ring->next_to_use,
4392 readl(tx_ring->tail));
4393 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4394 vsi->seid, q_idx, val);
4395 i40e_force_wb(vsi, tx_ring->q_vector);
4396 } else {
4397 /* First Chance - detected possible hung */
4398 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4399 &tx_ring->q_vector->hung_detected);
4400 }
4401 }
b03a8c1f
KP		 4402}
4403
4404/**
4405 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4406 * @pf: pointer to PF struct
4407 *
4408 * LAN VSI has netdev and netdev has TX queues. This function is to check
4409 * each of those TX queues if they are hung, trigger recovery by issuing
4410 * SW interrupt.
4411 **/
4412static void i40e_detect_recover_hung(struct i40e_pf *pf)
4413{
4414 struct net_device *netdev;
4415 struct i40e_vsi *vsi;
4416 int i;
4417
4418 /* Only for LAN VSI */
4419 vsi = pf->vsi[pf->lan_vsi];
4420
4421 if (!vsi)
4422 return;
4423
4424 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4425 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4426 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4427 return;
4428
4429 /* Make sure type is MAIN VSI */
4430 if (vsi->type != I40E_VSI_MAIN)
4431 return;
4432
4433 netdev = vsi->netdev;
4434 if (!netdev)
4435 return;
4436
4437 /* Bail out if netif_carrier is not OK */
4438 if (!netif_carrier_ok(netdev))
4439 return;
4440
4441 /* Go thru' TX queues for netdev */
4442 for (i = 0; i < netdev->num_tx_queues; i++) {
4443 struct netdev_queue *q;
4444
4445 q = netdev_get_tx_queue(netdev, i);
4446 if (q)
4447 i40e_detect_recover_hung_queue(i, vsi);
4448 }
4449}
4450
63d7e5a4
NP		 4451/**
4452 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4453 * @pf: pointer to PF
63d7e5a4
NP		 4454 *
4455 * Get TC map for ISCSI PF type that will include iSCSI TC
4456 * and LAN TC.
4457 **/
4458static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4459{
4460 struct i40e_dcb_app_priority_table app;
4461 struct i40e_hw *hw = &pf->hw;
4462 u8 enabled_tc = 1; /* TC0 is always enabled */
4463 u8 tc, i;
4464 /* Get the iSCSI APP TLV */
4465 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4466
4467 for (i = 0; i < dcbcfg->numapps; i++) {
4468 app = dcbcfg->app[i];
4469 if (app.selector == I40E_APP_SEL_TCPIP &&
4470 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4471 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4472 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4473 break;
4474 }
4475 }
4476
4477 return enabled_tc;
4478}
4479
41c445ff
JB		 4480/**
4481 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4482 * @dcbcfg: the corresponding DCBx configuration structure
4483 *
4484 * Return the number of TCs from given DCBx configuration
4485 **/
4486static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4487{
078b5876
JB		 4488 u8 num_tc = 0;
4489 int i;
41c445ff
JB		 4490
4491 /* Scan the ETS Config Priority Table to find
4492 * traffic class enabled for a given priority
4493 * and use the traffic class index to get the
4494 * number of traffic classes enabled
4495 */
4496 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4497 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4498 num_tc = dcbcfg->etscfg.prioritytable[i];
4499 }
4500
4501 /* Traffic class index starts from zero so
4502 * increment to return the actual count
4503 */
078b5876 4504 return num_tc + 1;
41c445ff
JB		 4505}
4506
4507/**
4508 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4509 * @dcbcfg: the corresponding DCBx configuration structure
4510 *
4511 * Query the current DCB configuration and return the number of
4512 * traffic classes enabled from the given DCBX config
4513 **/
4514static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4515{
4516 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4517 u8 enabled_tc = 1;
4518 u8 i;
4519
4520 for (i = 0; i < num_tc; i++)
41a1d04b 4521 enabled_tc |= BIT(i);
41c445ff
JB		 4522
4523 return enabled_tc;
4524}
4525
4526/**
4527 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4528 * @pf: PF being queried
4529 *
4530 * Return number of traffic classes enabled for the given PF
4531 **/
4532static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4533{
4534 struct i40e_hw *hw = &pf->hw;
4535 u8 i, enabled_tc;
4536 u8 num_tc = 0;
4537 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4538
4539 /* If DCB is not enabled then always in single TC */
4540 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4541 return 1;
4542
63d7e5a4
NP		 4543 /* SFP mode will be enabled for all TCs on port */
4544 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4545 return i40e_dcb_get_num_tc(dcbcfg);
4546
41c445ff 4547 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4548 if (pf->hw.func_caps.iscsi)
4549 enabled_tc = i40e_get_iscsi_tc_map(pf);
4550 else
fc51de96 4551 return 1; /* Only TC0 */
41c445ff 4552
63d7e5a4
NP		 4553 /* At least have TC0 */
4554 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4555 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4556 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4557 num_tc++;
4558 }
4559 return num_tc;
41c445ff
JB		 4560}
4561
4562/**
4563 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4564 * @pf: PF being queried
4565 *
4566 * Return a bitmap for first enabled traffic class for this PF.
4567 **/
4568static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4569{
4570 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4571 u8 i = 0;
4572
4573 if (!enabled_tc)
4574 return 0x1; /* TC0 */
4575
4576 /* Find the first enabled TC */
4577 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4578 if (enabled_tc & BIT(i))
41c445ff
JB		 4579 break;
4580 }
4581
41a1d04b 4582 return BIT(i);
41c445ff
JB		 4583}
4584
4585/**
4586 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4587 * @pf: PF being queried
4588 *
4589 * Return a bitmap for enabled traffic classes for this PF.
4590 **/
4591static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4592{
4593 /* If DCB is not enabled for this PF then just return default TC */
4594 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4595 return i40e_pf_get_default_tc(pf);
4596
41c445ff 4597 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4598 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4599 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4600
fc51de96 4601 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4602 if (pf->hw.func_caps.iscsi)
4603 return i40e_get_iscsi_tc_map(pf);
4604 else
fc51de96 4605 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4606}
4607
4608/**
4609 * i40e_vsi_get_bw_info - Query VSI BW Information
4610 * @vsi: the VSI being queried
4611 *
4612 * Returns 0 on success, negative value on failure
4613 **/
4614static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4615{
4616 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4617 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4618 struct i40e_pf *pf = vsi->back;
4619 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4620 i40e_status ret;
41c445ff 4621 u32 tc_bw_max;
41c445ff
JB		 4622 int i;
4623
4624 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4625 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4626 if (ret) {
41c445ff 4627 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4628 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4629 i40e_stat_str(&pf->hw, ret),
4630 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4631 return -EINVAL;
41c445ff
JB		 4632 }
4633
4634 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4635 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4636 NULL);
4637 if (ret) {
41c445ff 4638 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4639 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4640 i40e_stat_str(&pf->hw, ret),
4641 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4642 return -EINVAL;
41c445ff
JB		 4643 }
4644
4645 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4646 dev_info(&pf->pdev->dev,
4647 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4648 bw_config.tc_valid_bits,
4649 bw_ets_config.tc_valid_bits);
4650 /* Still continuing */
4651 }
4652
4653 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4654 vsi->bw_max_quanta = bw_config.max_bw;
4655 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4656 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4657 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4658 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4659 vsi->bw_ets_limit_credits[i] =
4660 le16_to_cpu(bw_ets_config.credits[i]);
4661 /* 3 bits out of 4 for each TC */
4662 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4663 }
078b5876 4664
dcae29be 4665 return 0;
41c445ff
JB		 4666}
4667
4668/**
4669 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4670 * @vsi: the VSI being configured
4671 * @enabled_tc: TC bitmap
4672 * @bw_credits: BW shared credits per TC
4673 *
4674 * Returns 0 on success, negative value on failure
4675 **/
dcae29be 4676static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4677 u8 *bw_share)
4678{
4679 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4680 i40e_status ret;
dcae29be 4681 int i;
41c445ff
JB		 4682
4683 bw_data.tc_valid_bits = enabled_tc;
4684 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4685 bw_data.tc_bw_credits[i] = bw_share[i];
4686
f1c7e72e
SN		 4687 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4688 NULL);
4689 if (ret) {
41c445ff 4690 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4691 "AQ command Config VSI BW allocation per TC failed = %d\n",
4692 vsi->back->hw.aq.asq_last_status);
dcae29be 4693 return -EINVAL;
41c445ff
JB		 4694 }
4695
4696 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4697 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4698
dcae29be 4699 return 0;
41c445ff
JB		 4700}
4701
4702/**
4703 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4704 * @vsi: the VSI being configured
4705 * @enabled_tc: TC map to be enabled
4706 *
4707 **/
4708static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4709{
4710 struct net_device *netdev = vsi->netdev;
4711 struct i40e_pf *pf = vsi->back;
4712 struct i40e_hw *hw = &pf->hw;
4713 u8 netdev_tc = 0;
4714 int i;
4715 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4716
4717 if (!netdev)
4718 return;
4719
4720 if (!enabled_tc) {
4721 netdev_reset_tc(netdev);
4722 return;
4723 }
4724
4725 /* Set up actual enabled TCs on the VSI */
4726 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4727 return;
4728
4729 /* set per TC queues for the VSI */
4730 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4731 /* Only set TC queues for enabled tcs
4732 *
4733 * e.g. For a VSI that has TC0 and TC3 enabled the
4734 * enabled_tc bitmap would be 0x00001001; the driver
4735 * will set the numtc for netdev as 2 that will be
4736 * referenced by the netdev layer as TC 0 and 1.
4737 */
75f5cea9 4738 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4739 netdev_set_tc_queue(netdev,
4740 vsi->tc_config.tc_info[i].netdev_tc,
4741 vsi->tc_config.tc_info[i].qcount,
4742 vsi->tc_config.tc_info[i].qoffset);
4743 }
4744
4745 /* Assign UP2TC map for the VSI */
4746 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4747 /* Get the actual TC# for the UP */
4748 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4749 /* Get the mapped netdev TC# for the UP */
4750 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4751 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4752 }
4753}
4754
4755/**
4756 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4757 * @vsi: the VSI being configured
4758 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4759 **/
4760static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4761 struct i40e_vsi_context *ctxt)
4762{
4763 /* copy just the sections touched not the entire info
4764 * since not all sections are valid as returned by
4765 * update vsi params
4766 */
4767 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4768 memcpy(&vsi->info.queue_mapping,
4769 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4770 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4771 sizeof(vsi->info.tc_mapping));
4772}
4773
4774/**
4775 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4776 * @vsi: VSI to be configured
4777 * @enabled_tc: TC bitmap
4778 *
4779 * This configures a particular VSI for TCs that are mapped to the
4780 * given TC bitmap. It uses default bandwidth share for TCs across
4781 * VSIs to configure TC for a particular VSI.
4782 *
4783 * NOTE:
4784 * It is expected that the VSI queues have been quisced before calling
4785 * this function.
4786 **/
4787static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4788{
4789 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4790 struct i40e_vsi_context ctxt;
4791 int ret = 0;
4792 int i;
4793
4794 /* Check if enabled_tc is same as existing or new TCs */
4795 if (vsi->tc_config.enabled_tc == enabled_tc)
4796 return ret;
4797
4798 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4799 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4800 if (enabled_tc & BIT(i))
41c445ff
JB		 4801 bw_share[i] = 1;
4802 }
4803
4804 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4805 if (ret) {
4806 dev_info(&vsi->back->pdev->dev,
4807 "Failed configuring TC map %d for VSI %d\n",
4808 enabled_tc, vsi->seid);
4809 goto out;
4810 }
4811
4812 /* Update Queue Pairs Mapping for currently enabled UPs */
4813 ctxt.seid = vsi->seid;
4814 ctxt.pf_num = vsi->back->hw.pf_id;
4815 ctxt.vf_num = 0;
4816 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4817 ctxt.info = vsi->info;
41c445ff
JB		 4818 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4819
4820 /* Update the VSI after updating the VSI queue-mapping information */
4821 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4822 if (ret) {
4823 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4824 "Update vsi tc config failed, err %s aq_err %s\n",
4825 i40e_stat_str(&vsi->back->hw, ret),
4826 i40e_aq_str(&vsi->back->hw,
4827 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4828 goto out;
4829 }
4830 /* update the local VSI info with updated queue map */
4831 i40e_vsi_update_queue_map(vsi, &ctxt);
4832 vsi->info.valid_sections = 0;
4833
4834 /* Update current VSI BW information */
4835 ret = i40e_vsi_get_bw_info(vsi);
4836 if (ret) {
4837 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4838 "Failed updating vsi bw info, err %s aq_err %s\n",
4839 i40e_stat_str(&vsi->back->hw, ret),
4840 i40e_aq_str(&vsi->back->hw,
4841 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4842 goto out;
4843 }
4844
4845 /* Update the netdev TC setup */
4846 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4847out:
4848 return ret;
4849}
4850
4e3b35b0
NP		 4851/**
4852 * i40e_veb_config_tc - Configure TCs for given VEB
4853 * @veb: given VEB
4854 * @enabled_tc: TC bitmap
4855 *
4856 * Configures given TC bitmap for VEB (switching) element
4857 **/
4858int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4859{
4860 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4861 struct i40e_pf *pf = veb->pf;
4862 int ret = 0;
4863 int i;
4864
4865 /* No TCs or already enabled TCs just return */
4866 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4867 return ret;
4868
4869 bw_data.tc_valid_bits = enabled_tc;
4870 /* bw_data.absolute_credits is not set (relative) */
4871
4872 /* Enable ETS TCs with equal BW Share for now */
4873 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4874 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4875 bw_data.tc_bw_share_credits[i] = 1;
4876 }
4877
4878 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4879 &bw_data, NULL);
4880 if (ret) {
4881 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4882 "VEB bw config failed, err %s aq_err %s\n",
4883 i40e_stat_str(&pf->hw, ret),
4884 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4885 goto out;
4886 }
4887
4888 /* Update the BW information */
4889 ret = i40e_veb_get_bw_info(veb);
4890 if (ret) {
4891 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4892 "Failed getting veb bw config, err %s aq_err %s\n",
4893 i40e_stat_str(&pf->hw, ret),
4894 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4895 }
4896
4897out:
4898 return ret;
4899}
4900
4901#ifdef CONFIG_I40E_DCB
4902/**
4903 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4904 * @pf: PF struct
4905 *
4906 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4907 * the caller would've quiesce all the VSIs before calling
4908 * this function
4909 **/
4910static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4911{
4912 u8 tc_map = 0;
4913 int ret;
4914 u8 v;
4915
4916 /* Enable the TCs available on PF to all VEBs */
4917 tc_map = i40e_pf_get_tc_map(pf);
4918 for (v = 0; v < I40E_MAX_VEB; v++) {
4919 if (!pf->veb[v])
4920 continue;
4921 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4922 if (ret) {
4923 dev_info(&pf->pdev->dev,
4924 "Failed configuring TC for VEB seid=%d\n",
4925 pf->veb[v]->seid);
4926 /* Will try to configure as many components */
4927 }
4928 }
4929
4930 /* Update each VSI */
505682cd 4931 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4932 if (!pf->vsi[v])
4933 continue;
4934
4935 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4936#ifdef I40E_FCOE
4937 * - For FCoE VSI only enable the TC configured
4938 * as per the APP TLV
4939#endif
4e3b35b0
NP		 4940 * - For all others keep them at TC0 for now
4941 */
4942 if (v == pf->lan_vsi)
4943 tc_map = i40e_pf_get_tc_map(pf);
4944 else
4945 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4946#ifdef I40E_FCOE
4947 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4948 tc_map = i40e_get_fcoe_tc_map(pf);
4949#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4950
4951 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4952 if (ret) {
4953 dev_info(&pf->pdev->dev,
4954 "Failed configuring TC for VSI seid=%d\n",
4955 pf->vsi[v]->seid);
4956 /* Will try to configure as many components */
4957 } else {
0672a091
NP		 4958 /* Re-configure VSI vectors based on updated TC map */
4959 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4960 if (pf->vsi[v]->netdev)
4961 i40e_dcbnl_set_all(pf->vsi[v]);
4962 }
4963 }
4964}
4965
2fd75f31
NP		 4966/**
4967 * i40e_resume_port_tx - Resume port Tx
4968 * @pf: PF struct
4969 *
4970 * Resume a port's Tx and issue a PF reset in case of failure to
4971 * resume.
4972 **/
4973static int i40e_resume_port_tx(struct i40e_pf *pf)
4974{
4975 struct i40e_hw *hw = &pf->hw;
4976 int ret;
4977
4978 ret = i40e_aq_resume_port_tx(hw, NULL);
4979 if (ret) {
4980 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4981 "Resume Port Tx failed, err %s aq_err %s\n",
4982 i40e_stat_str(&pf->hw, ret),
4983 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4984 /* Schedule PF reset to recover */
4985 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4986 i40e_service_event_schedule(pf);
4987 }
4988
4989 return ret;
4990}
4991
4e3b35b0
NP		 4992/**
4993 * i40e_init_pf_dcb - Initialize DCB configuration
4994 * @pf: PF being configured
4995 *
4996 * Query the current DCB configuration and cache it
4997 * in the hardware structure
4998 **/
4999static int i40e_init_pf_dcb(struct i40e_pf *pf)
5000{
5001 struct i40e_hw *hw = &pf->hw;
5002 int err = 0;
5003
025b4a54
ASJ		 5004 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
5005 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
5006 (pf->hw.aq.fw_maj_ver < 4))
5007 goto out;
5008
4e3b35b0
NP		 5009 /* Get the initial DCB configuration */
5010 err = i40e_init_dcb(hw);
5011 if (!err) {
5012 /* Device/Function is not DCBX capable */
5013 if ((!hw->func_caps.dcb) ||
5014 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5015 dev_info(&pf->pdev->dev,
5016 "DCBX offload is not supported or is disabled for this PF.\n");
5017
5018 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5019 goto out;
5020
5021 } else {
5022 /* When status is not DISABLED then DCBX in FW */
5023 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5024 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5025
5026 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5027 /* Enable DCB tagging only when more than one TC */
5028 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5029 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5030 dev_dbg(&pf->pdev->dev,
5031 "DCBX offload is supported for this PF.\n");
4e3b35b0 5032 }
014269ff 5033 } else {
aebfc816 5034 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5035 "Query for DCB configuration failed, err %s aq_err %s\n",
5036 i40e_stat_str(&pf->hw, err),
5037 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5038 }
5039
5040out:
5041 return err;
5042}
5043#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5044#define SPEED_SIZE 14
5045#define FC_SIZE 8
5046/**
5047 * i40e_print_link_message - print link up or down
5048 * @vsi: the VSI for which link needs a message
5049 */
c156f856 5050void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5051{
a9165490
SN		 5052 char *speed = "Unknown";
5053 char *fc = "Unknown";
cf05ed08 5054
c156f856
MJ		 5055 if (vsi->current_isup == isup)
5056 return;
5057 vsi->current_isup = isup;
cf05ed08
JB		 5058 if (!isup) {
5059 netdev_info(vsi->netdev, "NIC Link is Down\n");
5060 return;
5061 }
5062
148c2d80
GR		 5063 /* Warn user if link speed on NPAR enabled partition is not at
5064 * least 10GB
5065 */
5066 if (vsi->back->hw.func_caps.npar_enable &&
5067 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5068 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5069 netdev_warn(vsi->netdev,
5070 "The partition detected link speed that is less than 10Gbps\n");
5071
cf05ed08
JB		 5072 switch (vsi->back->hw.phy.link_info.link_speed) {
5073 case I40E_LINK_SPEED_40GB:
a9165490 5074 speed = "40 G";
cf05ed08 5075 break;
ae24b409 5076 case I40E_LINK_SPEED_20GB:
a9165490 5077 speed = "20 G";
ae24b409 5078 break;
cf05ed08 5079 case I40E_LINK_SPEED_10GB:
a9165490 5080 speed = "10 G";
cf05ed08
JB		 5081 break;
5082 case I40E_LINK_SPEED_1GB:
a9165490 5083 speed = "1000 M";
cf05ed08 5084 break;
5960d33f 5085 case I40E_LINK_SPEED_100MB:
a9165490 5086 speed = "100 M";
5960d33f 5087 break;
cf05ed08
JB		 5088 default:
5089 break;
5090 }
5091
5092 switch (vsi->back->hw.fc.current_mode) {
5093 case I40E_FC_FULL:
a9165490 5094 fc = "RX/TX";
cf05ed08
JB		 5095 break;
5096 case I40E_FC_TX_PAUSE:
a9165490 5097 fc = "TX";
cf05ed08
JB		 5098 break;
5099 case I40E_FC_RX_PAUSE:
a9165490 5100 fc = "RX";
cf05ed08
JB		 5101 break;
5102 default:
a9165490 5103 fc = "None";
cf05ed08
JB		 5104 break;
5105 }
5106
a9165490 5107 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5108 speed, fc);
5109}
4e3b35b0 5110
41c445ff
JB		 5111/**
5112 * i40e_up_complete - Finish the last steps of bringing up a connection
5113 * @vsi: the VSI being configured
5114 **/
5115static int i40e_up_complete(struct i40e_vsi *vsi)
5116{
5117 struct i40e_pf *pf = vsi->back;
5118 int err;
5119
5120 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5121 i40e_vsi_configure_msix(vsi);
5122 else
5123 i40e_configure_msi_and_legacy(vsi);
5124
5125 /* start rings */
5126 err = i40e_vsi_control_rings(vsi, true);
5127 if (err)
5128 return err;
5129
5130 clear_bit(__I40E_DOWN, &vsi->state);
5131 i40e_napi_enable_all(vsi);
5132 i40e_vsi_enable_irq(vsi);
5133
5134 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5135 (vsi->netdev)) {
cf05ed08 5136 i40e_print_link_message(vsi, true);
41c445ff
JB		 5137 netif_tx_start_all_queues(vsi->netdev);
5138 netif_carrier_on(vsi->netdev);
6d779b41 5139 } else if (vsi->netdev) {
cf05ed08 5140 i40e_print_link_message(vsi, false);
7b592f61
CW		 5141 /* need to check for qualified module here*/
5142 if ((pf->hw.phy.link_info.link_info &
5143 I40E_AQ_MEDIA_AVAILABLE) &&
5144 (!(pf->hw.phy.link_info.an_info &
5145 I40E_AQ_QUALIFIED_MODULE)))
5146 netdev_err(vsi->netdev,
5147 "the driver failed to link because an unqualified module was detected.");
41c445ff 5148 }
ca64fa4e
ASJ		 5149
5150 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5151 if (vsi->type == I40E_VSI_FDIR) {
5152 /* reset fd counters */
5153 pf->fd_add_err = pf->fd_atr_cnt = 0;
5154 if (pf->fd_tcp_rule > 0) {
5155 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5156 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5157 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5158 pf->fd_tcp_rule = 0;
5159 }
ca64fa4e 5160 i40e_fdir_filter_restore(vsi);
1e1be8f6 5161 }
41c445ff
JB		 5162 i40e_service_event_schedule(pf);
5163
5164 return 0;
5165}
5166
5167/**
5168 * i40e_vsi_reinit_locked - Reset the VSI
5169 * @vsi: the VSI being configured
5170 *
5171 * Rebuild the ring structs after some configuration
5172 * has changed, e.g. MTU size.
5173 **/
5174static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5175{
5176 struct i40e_pf *pf = vsi->back;
5177
5178 WARN_ON(in_interrupt());
5179 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5180 usleep_range(1000, 2000);
5181 i40e_down(vsi);
5182
5183 /* Give a VF some time to respond to the reset. The
5184 * two second wait is based upon the watchdog cycle in
5185 * the VF driver.
5186 */
5187 if (vsi->type == I40E_VSI_SRIOV)
5188 msleep(2000);
5189 i40e_up(vsi);
5190 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5191}
5192
5193/**
5194 * i40e_up - Bring the connection back up after being down
5195 * @vsi: the VSI being configured
5196 **/
5197int i40e_up(struct i40e_vsi *vsi)
5198{
5199 int err;
5200
5201 err = i40e_vsi_configure(vsi);
5202 if (!err)
5203 err = i40e_up_complete(vsi);
5204
5205 return err;
5206}
5207
5208/**
5209 * i40e_down - Shutdown the connection processing
5210 * @vsi: the VSI being stopped
5211 **/
5212void i40e_down(struct i40e_vsi *vsi)
5213{
5214 int i;
5215
5216 /* It is assumed that the caller of this function
5217 * sets the vsi->state __I40E_DOWN bit.
5218 */
5219 if (vsi->netdev) {
5220 netif_carrier_off(vsi->netdev);
5221 netif_tx_disable(vsi->netdev);
5222 }
5223 i40e_vsi_disable_irq(vsi);
5224 i40e_vsi_control_rings(vsi, false);
5225 i40e_napi_disable_all(vsi);
5226
5227 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5228 i40e_clean_tx_ring(vsi->tx_rings[i]);
5229 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5230 }
5231}
5232
5233/**
5234 * i40e_setup_tc - configure multiple traffic classes
5235 * @netdev: net device to configure
5236 * @tc: number of traffic classes to enable
5237 **/
38e00438
VD		 5238#ifdef I40E_FCOE
5239int i40e_setup_tc(struct net_device *netdev, u8 tc)
5240#else
41c445ff 5241static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5242#endif
41c445ff
JB		 5243{
5244 struct i40e_netdev_priv *np = netdev_priv(netdev);
5245 struct i40e_vsi *vsi = np->vsi;
5246 struct i40e_pf *pf = vsi->back;
5247 u8 enabled_tc = 0;
5248 int ret = -EINVAL;
5249 int i;
5250
5251 /* Check if DCB enabled to continue */
5252 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5253 netdev_info(netdev, "DCB is not enabled for adapter\n");
5254 goto exit;
5255 }
5256
5257 /* Check if MFP enabled */
5258 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5259 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5260 goto exit;
5261 }
5262
5263 /* Check whether tc count is within enabled limit */
5264 if (tc > i40e_pf_get_num_tc(pf)) {
5265 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5266 goto exit;
5267 }
5268
5269 /* Generate TC map for number of tc requested */
5270 for (i = 0; i < tc; i++)
75f5cea9 5271 enabled_tc |= BIT(i);
41c445ff
JB		 5272
5273 /* Requesting same TC configuration as already enabled */
5274 if (enabled_tc == vsi->tc_config.enabled_tc)
5275 return 0;
5276
5277 /* Quiesce VSI queues */
5278 i40e_quiesce_vsi(vsi);
5279
5280 /* Configure VSI for enabled TCs */
5281 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5282 if (ret) {
5283 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5284 vsi->seid);
5285 goto exit;
5286 }
5287
5288 /* Unquiesce VSI */
5289 i40e_unquiesce_vsi(vsi);
5290
5291exit:
5292 return ret;
5293}
5294
5295/**
5296 * i40e_open - Called when a network interface is made active
5297 * @netdev: network interface device structure
5298 *
5299 * The open entry point is called when a network interface is made
5300 * active by the system (IFF_UP). At this point all resources needed
5301 * for transmit and receive operations are allocated, the interrupt
5302 * handler is registered with the OS, the netdev watchdog subtask is
5303 * enabled, and the stack is notified that the interface is ready.
5304 *
5305 * Returns 0 on success, negative value on failure
5306 **/
38e00438 5307int i40e_open(struct net_device *netdev)
41c445ff
JB		 5308{
5309 struct i40e_netdev_priv *np = netdev_priv(netdev);
5310 struct i40e_vsi *vsi = np->vsi;
5311 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5312 int err;
5313
4eb3f768
SN		 5314 /* disallow open during test or if eeprom is broken */
5315 if (test_bit(__I40E_TESTING, &pf->state) ||
5316 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5317 return -EBUSY;
5318
5319 netif_carrier_off(netdev);
5320
6c167f58
EK		 5321 err = i40e_vsi_open(vsi);
5322 if (err)
5323 return err;
5324
059dab69
JB		 5325 /* configure global TSO hardware offload settings */
5326 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5327 TCP_FLAG_FIN) >> 16);
5328 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5329 TCP_FLAG_FIN |
5330 TCP_FLAG_CWR) >> 16);
5331 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5332
6633d381 5333#ifdef CONFIG_I40E_VXLAN
6c167f58
EK		 5334 vxlan_get_rx_port(netdev);
5335#endif
5336
5337 return 0;
5338}
5339
5340/**
5341 * i40e_vsi_open -
5342 * @vsi: the VSI to open
5343 *
5344 * Finish initialization of the VSI.
5345 *
5346 * Returns 0 on success, negative value on failure
5347 **/
5348int i40e_vsi_open(struct i40e_vsi *vsi)
5349{
5350 struct i40e_pf *pf = vsi->back;
b294ac70 5351 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5352 int err;
5353
41c445ff
JB		 5354 /* allocate descriptors */
5355 err = i40e_vsi_setup_tx_resources(vsi);
5356 if (err)
5357 goto err_setup_tx;
5358 err = i40e_vsi_setup_rx_resources(vsi);
5359 if (err)
5360 goto err_setup_rx;
5361
5362 err = i40e_vsi_configure(vsi);
5363 if (err)
5364 goto err_setup_rx;
5365
c22e3c6c
SN		 5366 if (vsi->netdev) {
5367 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5368 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5369 err = i40e_vsi_request_irq(vsi, int_name);
5370 if (err)
5371 goto err_setup_rx;
41c445ff 5372
c22e3c6c
SN		 5373 /* Notify the stack of the actual queue counts. */
5374 err = netif_set_real_num_tx_queues(vsi->netdev,
5375 vsi->num_queue_pairs);
5376 if (err)
5377 goto err_set_queues;
25946ddb 5378
c22e3c6c
SN		 5379 err = netif_set_real_num_rx_queues(vsi->netdev,
5380 vsi->num_queue_pairs);
5381 if (err)
5382 goto err_set_queues;
8a9eb7d3
SN		 5383
5384 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5385 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5386 dev_driver_string(&pf->pdev->dev),
5387 dev_name(&pf->pdev->dev));
8a9eb7d3 5388 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5389
c22e3c6c 5390 } else {
ce9ccb17 5391 err = -EINVAL;
6c167f58
EK		 5392 goto err_setup_rx;
5393 }
25946ddb 5394
41c445ff
JB		 5395 err = i40e_up_complete(vsi);
5396 if (err)
5397 goto err_up_complete;
5398
41c445ff
JB		 5399 return 0;
5400
5401err_up_complete:
5402 i40e_down(vsi);
25946ddb 5403err_set_queues:
41c445ff
JB		 5404 i40e_vsi_free_irq(vsi);
5405err_setup_rx:
5406 i40e_vsi_free_rx_resources(vsi);
5407err_setup_tx:
5408 i40e_vsi_free_tx_resources(vsi);
5409 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5410 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5411
5412 return err;
5413}
5414
17a73f6b
JG		 5415/**
5416 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5417 * @pf: Pointer to PF
17a73f6b
JG		 5418 *
5419 * This function destroys the hlist where all the Flow Director
5420 * filters were saved.
5421 **/
5422static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5423{
5424 struct i40e_fdir_filter *filter;
5425 struct hlist_node *node2;
5426
5427 hlist_for_each_entry_safe(filter, node2,
5428 &pf->fdir_filter_list, fdir_node) {
5429 hlist_del(&filter->fdir_node);
5430 kfree(filter);
5431 }
5432 pf->fdir_pf_active_filters = 0;
5433}
5434
41c445ff
JB		 5435/**
5436 * i40e_close - Disables a network interface
5437 * @netdev: network interface device structure
5438 *
5439 * The close entry point is called when an interface is de-activated
5440 * by the OS. The hardware is still under the driver's control, but
5441 * this netdev interface is disabled.
5442 *
5443 * Returns 0, this is not allowed to fail
5444 **/
38e00438
VD		 5445#ifdef I40E_FCOE
5446int i40e_close(struct net_device *netdev)
5447#else
41c445ff 5448static int i40e_close(struct net_device *netdev)
38e00438 5449#endif
41c445ff
JB		 5450{
5451 struct i40e_netdev_priv *np = netdev_priv(netdev);
5452 struct i40e_vsi *vsi = np->vsi;
5453
90ef8d47 5454 i40e_vsi_close(vsi);
41c445ff
JB		 5455
5456 return 0;
5457}
5458
5459/**
5460 * i40e_do_reset - Start a PF or Core Reset sequence
5461 * @pf: board private structure
5462 * @reset_flags: which reset is requested
5463 *
5464 * The essential difference in resets is that the PF Reset
5465 * doesn't clear the packet buffers, doesn't reset the PE
5466 * firmware, and doesn't bother the other PFs on the chip.
5467 **/
5468void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5469{
5470 u32 val;
5471
5472 WARN_ON(in_interrupt());
5473
263fc48f
MW		 5474 if (i40e_check_asq_alive(&pf->hw))
5475 i40e_vc_notify_reset(pf);
5476
41c445ff 5477 /* do the biggest reset indicated */
41a1d04b 5478 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5479
5480 /* Request a Global Reset
5481 *
5482 * This will start the chip's countdown to the actual full
5483 * chip reset event, and a warning interrupt to be sent
5484 * to all PFs, including the requestor. Our handler
5485 * for the warning interrupt will deal with the shutdown
5486 * and recovery of the switch setup.
5487 */
69bfb110 5488 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5489 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5490 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5491 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5492
41a1d04b 5493 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5494
5495 /* Request a Core Reset
5496 *
5497 * Same as Global Reset, except does *not* include the MAC/PHY
5498 */
69bfb110 5499 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5500 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5501 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5502 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5503 i40e_flush(&pf->hw);
5504
41a1d04b 5505 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5506
5507 /* Request a PF Reset
5508 *
5509 * Resets only the PF-specific registers
5510 *
5511 * This goes directly to the tear-down and rebuild of
5512 * the switch, since we need to do all the recovery as
5513 * for the Core Reset.
5514 */
69bfb110 5515 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5516 i40e_handle_reset_warning(pf);
5517
41a1d04b 5518 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5519 int v;
5520
5521 /* Find the VSI(s) that requested a re-init */
5522 dev_info(&pf->pdev->dev,
5523 "VSI reinit requested\n");
505682cd 5524 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5525 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5526
41c445ff
JB		 5527 if (vsi != NULL &&
5528 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5529 i40e_vsi_reinit_locked(pf->vsi[v]);
5530 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5531 }
5532 }
41a1d04b 5533 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5534 int v;
5535
5536 /* Find the VSI(s) that needs to be brought down */
5537 dev_info(&pf->pdev->dev, "VSI down requested\n");
5538 for (v = 0; v < pf->num_alloc_vsi; v++) {
5539 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5540
b5d06f05
NP		 5541 if (vsi != NULL &&
5542 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5543 set_bit(__I40E_DOWN, &vsi->state);
5544 i40e_down(vsi);
5545 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5546 }
5547 }
41c445ff
JB		 5548 } else {
5549 dev_info(&pf->pdev->dev,
5550 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5551 }
5552}
5553
4e3b35b0
NP		 5554#ifdef CONFIG_I40E_DCB
5555/**
5556 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5557 * @pf: board private structure
5558 * @old_cfg: current DCB config
5559 * @new_cfg: new DCB config
5560 **/
5561bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5562 struct i40e_dcbx_config *old_cfg,
5563 struct i40e_dcbx_config *new_cfg)
5564{
5565 bool need_reconfig = false;
5566
5567 /* Check if ETS configuration has changed */
5568 if (memcmp(&new_cfg->etscfg,
5569 &old_cfg->etscfg,
5570 sizeof(new_cfg->etscfg))) {
5571 /* If Priority Table has changed reconfig is needed */
5572 if (memcmp(&new_cfg->etscfg.prioritytable,
5573 &old_cfg->etscfg.prioritytable,
5574 sizeof(new_cfg->etscfg.prioritytable))) {
5575 need_reconfig = true;
69bfb110 5576 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5577 }
5578
5579 if (memcmp(&new_cfg->etscfg.tcbwtable,
5580 &old_cfg->etscfg.tcbwtable,
5581 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5582 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5583
5584 if (memcmp(&new_cfg->etscfg.tsatable,
5585 &old_cfg->etscfg.tsatable,
5586 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5587 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5588 }
5589
5590 /* Check if PFC configuration has changed */
5591 if (memcmp(&new_cfg->pfc,
5592 &old_cfg->pfc,
5593 sizeof(new_cfg->pfc))) {
5594 need_reconfig = true;
69bfb110 5595 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5596 }
5597
5598 /* Check if APP Table has changed */
5599 if (memcmp(&new_cfg->app,
5600 &old_cfg->app,
3d9667a9 5601 sizeof(new_cfg->app))) {
4e3b35b0 5602 need_reconfig = true;
69bfb110 5603 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5604 }
4e3b35b0 5605
fb43201f 5606 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5607 return need_reconfig;
5608}
5609
5610/**
5611 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5612 * @pf: board private structure
5613 * @e: event info posted on ARQ
5614 **/
5615static int i40e_handle_lldp_event(struct i40e_pf *pf,
5616 struct i40e_arq_event_info *e)
5617{
5618 struct i40e_aqc_lldp_get_mib *mib =
5619 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5620 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5621 struct i40e_dcbx_config tmp_dcbx_cfg;
5622 bool need_reconfig = false;
5623 int ret = 0;
5624 u8 type;
5625
4d9b6043
NP		 5626 /* Not DCB capable or capability disabled */
5627 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5628 return ret;
5629
4e3b35b0
NP		 5630 /* Ignore if event is not for Nearest Bridge */
5631 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5632 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5633 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5634 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5635 return ret;
5636
5637 /* Check MIB Type and return if event for Remote MIB update */
5638 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5639 dev_dbg(&pf->pdev->dev,
fb43201f 5640 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5641 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5642 /* Update the remote cached instance and return */
5643 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5644 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5645 &hw->remote_dcbx_config);
5646 goto exit;
5647 }
5648
9fa61dd2 5649 /* Store the old configuration */
1a2f6248 5650 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5651
750fcbcf
NP		 5652 /* Reset the old DCBx configuration data */
5653 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5654 /* Get updated DCBX data from firmware */
5655 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5656 if (ret) {
f1c7e72e
SN		 5657 dev_info(&pf->pdev->dev,
5658 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5659 i40e_stat_str(&pf->hw, ret),
5660 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5661 goto exit;
5662 }
5663
5664 /* No change detected in DCBX configs */
750fcbcf
NP		 5665 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5666 sizeof(tmp_dcbx_cfg))) {
69bfb110 5667 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5668 goto exit;
5669 }
5670
750fcbcf
NP		 5671 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5672 &hw->local_dcbx_config);
4e3b35b0 5673
750fcbcf 5674 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5675
5676 if (!need_reconfig)
5677 goto exit;
5678
4d9b6043 5679 /* Enable DCB tagging only when more than one TC */
750fcbcf 5680 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5681 pf->flags |= I40E_FLAG_DCB_ENABLED;
5682 else
5683 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5684
69129dc3 5685 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5686 /* Reconfiguration needed quiesce all VSIs */
5687 i40e_pf_quiesce_all_vsi(pf);
5688
5689 /* Changes in configuration update VEB/VSI */
5690 i40e_dcb_reconfigure(pf);
5691
2fd75f31
NP		 5692 ret = i40e_resume_port_tx(pf);
5693
69129dc3 5694 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5695 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5696 if (ret)
5697 goto exit;
5698
5699 /* Wait for the PF's Tx queues to be disabled */
5700 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5701 if (ret) {
5702 /* Schedule PF reset to recover */
5703 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5704 i40e_service_event_schedule(pf);
5705 } else {
2fd75f31 5706 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5707 }
5708
4e3b35b0
NP		 5709exit:
5710 return ret;
5711}
5712#endif /* CONFIG_I40E_DCB */
5713
23326186
ASJ		 5714/**
5715 * i40e_do_reset_safe - Protected reset path for userland calls.
5716 * @pf: board private structure
5717 * @reset_flags: which reset is requested
5718 *
5719 **/
5720void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5721{
5722 rtnl_lock();
5723 i40e_do_reset(pf, reset_flags);
5724 rtnl_unlock();
5725}
5726
41c445ff
JB		 5727/**
5728 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5729 * @pf: board private structure
5730 * @e: event info posted on ARQ
5731 *
5732 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5733 * and VF queues
5734 **/
5735static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5736 struct i40e_arq_event_info *e)
5737{
5738 struct i40e_aqc_lan_overflow *data =
5739 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5740 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5741 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5742 struct i40e_hw *hw = &pf->hw;
5743 struct i40e_vf *vf;
5744 u16 vf_id;
5745
69bfb110
JB		 5746 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5747 queue, qtx_ctl);
41c445ff
JB		 5748
5749 /* Queue belongs to VF, find the VF and issue VF reset */
5750 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5751 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5752 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5753 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5754 vf_id -= hw->func_caps.vf_base_id;
5755 vf = &pf->vf[vf_id];
5756 i40e_vc_notify_vf_reset(vf);
5757 /* Allow VF to process pending reset notification */
5758 msleep(20);
5759 i40e_reset_vf(vf, false);
5760 }
5761}
5762
5763/**
5764 * i40e_service_event_complete - Finish up the service event
5765 * @pf: board private structure
5766 **/
5767static void i40e_service_event_complete(struct i40e_pf *pf)
5768{
b875f99b 5769 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5770
5771 /* flush memory to make sure state is correct before next watchog */
4e857c58 5772 smp_mb__before_atomic();
41c445ff
JB		 5773 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5774}
5775
55a5e60b 5776/**
12957388
ASJ		 5777 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5778 * @pf: board private structure
5779 **/
04294e38 5780u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5781{
04294e38 5782 u32 val, fcnt_prog;
12957388
ASJ		 5783
5784 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5785 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5786 return fcnt_prog;
5787}
5788
5789/**
04294e38 5790 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5791 * @pf: board private structure
5792 **/
04294e38 5793u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5794{
04294e38
ASJ		 5795 u32 val, fcnt_prog;
5796
55a5e60b
ASJ		 5797 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5798 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5799 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5800 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5801 return fcnt_prog;
5802}
1e1be8f6 5803
04294e38
ASJ		 5804/**
5805 * i40e_get_global_fd_count - Get total FD filters programmed on device
5806 * @pf: board private structure
5807 **/
5808u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5809{
5810 u32 val, fcnt_prog;
5811
5812 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5813 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5814 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5815 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5816 return fcnt_prog;
5817}
5818
55a5e60b
ASJ		 5819/**
5820 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5821 * @pf: board private structure
5822 **/
5823void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5824{
3487b6c3 5825 struct i40e_fdir_filter *filter;
55a5e60b 5826 u32 fcnt_prog, fcnt_avail;
3487b6c3 5827 struct hlist_node *node;
55a5e60b 5828
1e1be8f6
ASJ		 5829 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5830 return;
5831
55a5e60b
ASJ		 5832 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5833 * to re-enable
5834 */
04294e38 5835 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5836 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5837 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5838 (pf->fd_add_err == 0) ||
5839 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5840 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5841 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5842 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5843 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5844 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5845 }
5846 }
5847 /* Wait for some more space to be available to turn on ATR */
5848 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5849 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5850 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5851 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5852 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5853 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5854 }
5855 }
3487b6c3
CW		 5856
5857 /* if hw had a problem adding a filter, delete it */
5858 if (pf->fd_inv > 0) {
5859 hlist_for_each_entry_safe(filter, node,
5860 &pf->fdir_filter_list, fdir_node) {
5861 if (filter->fd_id == pf->fd_inv) {
5862 hlist_del(&filter->fdir_node);
5863 kfree(filter);
5864 pf->fdir_pf_active_filters--;
5865 }
5866 }
5867 }
55a5e60b
ASJ		 5868}
5869
1e1be8f6 5870#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5871#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5872/**
5873 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5874 * @pf: board private structure
5875 **/
5876static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5877{
04294e38 5878 unsigned long min_flush_time;
1e1be8f6 5879 int flush_wait_retry = 50;
04294e38
ASJ		 5880 bool disable_atr = false;
5881 int fd_room;
1e1be8f6
ASJ		 5882 int reg;
5883
1790ed0c
AA		 5884 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5885 return;
5886
a5fdaf34
JB		 5887 if (!time_after(jiffies, pf->fd_flush_timestamp +
5888 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5889 return;
04294e38 5890
a5fdaf34
JB		 5891 /* If the flush is happening too quick and we have mostly SB rules we
5892 * should not re-enable ATR for some time.
5893 */
5894 min_flush_time = pf->fd_flush_timestamp +
5895 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5896 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5897
5898 if (!(time_after(jiffies, min_flush_time)) &&
5899 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5900 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5901 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5902 disable_atr = true;
5903 }
5904
5905 pf->fd_flush_timestamp = jiffies;
5906 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5907 /* flush all filters */
5908 wr32(&pf->hw, I40E_PFQF_CTL_1,
5909 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5910 i40e_flush(&pf->hw);
5911 pf->fd_flush_cnt++;
5912 pf->fd_add_err = 0;
5913 do {
5914 /* Check FD flush status every 5-6msec */
5915 usleep_range(5000, 6000);
5916 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5917 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5918 break;
5919 } while (flush_wait_retry--);
5920 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5921 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5922 } else {
5923 /* replay sideband filters */
5924 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5925 if (!disable_atr)
5926 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5927 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5928 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5929 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5930 }
a5fdaf34 5931
1e1be8f6
ASJ		 5932}
5933
5934/**
5935 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5936 * @pf: board private structure
5937 **/
04294e38 5938u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5939{
5940 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5941}
5942
5943/* We can see up to 256 filter programming desc in transit if the filters are
5944 * being applied really fast; before we see the first
5945 * filter miss error on Rx queue 0. Accumulating enough error messages before
5946 * reacting will make sure we don't cause flush too often.
5947 */
5948#define I40E_MAX_FD_PROGRAM_ERROR 256
5949
41c445ff
JB		 5950/**
5951 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5952 * @pf: board private structure
5953 **/
5954static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5955{
41c445ff 5956
41c445ff
JB		 5957 /* if interface is down do nothing */
5958 if (test_bit(__I40E_DOWN, &pf->state))
5959 return;
1e1be8f6 5960
1790ed0c
AA		 5961 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5962 return;
5963
04294e38 5964 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5965 i40e_fdir_flush_and_replay(pf);
5966
55a5e60b
ASJ		 5967 i40e_fdir_check_and_reenable(pf);
5968
41c445ff
JB		 5969}
5970
5971/**
5972 * i40e_vsi_link_event - notify VSI of a link event
5973 * @vsi: vsi to be notified
5974 * @link_up: link up or down
5975 **/
5976static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5977{
32b5b811 5978 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5979 return;
5980
5981 switch (vsi->type) {
5982 case I40E_VSI_MAIN:
38e00438
VD		 5983#ifdef I40E_FCOE
5984 case I40E_VSI_FCOE:
5985#endif
41c445ff
JB		 5986 if (!vsi->netdev || !vsi->netdev_registered)
5987 break;
5988
5989 if (link_up) {
5990 netif_carrier_on(vsi->netdev);
5991 netif_tx_wake_all_queues(vsi->netdev);
5992 } else {
5993 netif_carrier_off(vsi->netdev);
5994 netif_tx_stop_all_queues(vsi->netdev);
5995 }
5996 break;
5997
5998 case I40E_VSI_SRIOV:
41c445ff
JB		 5999 case I40E_VSI_VMDQ2:
6000 case I40E_VSI_CTRL:
6001 case I40E_VSI_MIRROR:
6002 default:
6003 /* there is no notification for other VSIs */
6004 break;
6005 }
6006}
6007
6008/**
6009 * i40e_veb_link_event - notify elements on the veb of a link event
6010 * @veb: veb to be notified
6011 * @link_up: link up or down
6012 **/
6013static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6014{
6015 struct i40e_pf *pf;
6016 int i;
6017
6018 if (!veb || !veb->pf)
6019 return;
6020 pf = veb->pf;
6021
6022 /* depth first... */
6023 for (i = 0; i < I40E_MAX_VEB; i++)
6024 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6025 i40e_veb_link_event(pf->veb[i], link_up);
6026
6027 /* ... now the local VSIs */
505682cd 6028 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6029 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6030 i40e_vsi_link_event(pf->vsi[i], link_up);
6031}
6032
6033/**
6034 * i40e_link_event - Update netif_carrier status
6035 * @pf: board private structure
6036 **/
6037static void i40e_link_event(struct i40e_pf *pf)
6038{
320684cd 6039 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6040 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6041 i40e_status status;
6042 bool new_link, old_link;
41c445ff 6043
1f9610e4
CS		 6044 /* save off old link status information */
6045 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6046
1e701e09
JB		 6047 /* set this to force the get_link_status call to refresh state */
6048 pf->hw.phy.get_link_info = true;
6049
41c445ff 6050 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6051
6052 status = i40e_get_link_status(&pf->hw, &new_link);
6053 if (status) {
6054 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6055 status);
6056 return;
6057 }
6058
fef59ddf
CS		 6059 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6060 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6061
1e701e09 6062 if (new_link == old_link &&
fef59ddf 6063 new_link_speed == old_link_speed &&
320684cd
MW		 6064 (test_bit(__I40E_DOWN, &vsi->state) ||
6065 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6066 return;
320684cd
MW		 6067
6068 if (!test_bit(__I40E_DOWN, &vsi->state))
6069 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6070
6071 /* Notify the base of the switch tree connected to
6072 * the link. Floating VEBs are not notified.
6073 */
6074 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6075 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6076 else
320684cd 6077 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6078
6079 if (pf->vf)
6080 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6081
6082 if (pf->flags & I40E_FLAG_PTP)
6083 i40e_ptp_set_increment(pf);
41c445ff
JB		 6084}
6085
41c445ff 6086/**
21536717 6087 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6088 * @pf: board private structure
6089 **/
6090static void i40e_watchdog_subtask(struct i40e_pf *pf)
6091{
6092 int i;
6093
6094 /* if interface is down do nothing */
6095 if (test_bit(__I40E_DOWN, &pf->state) ||
6096 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6097 return;
6098
21536717
SN		 6099 /* make sure we don't do these things too often */
6100 if (time_before(jiffies, (pf->service_timer_previous +
6101 pf->service_timer_period)))
6102 return;
6103 pf->service_timer_previous = jiffies;
6104
9ac77266
SN		 6105 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6106 i40e_link_event(pf);
21536717 6107
41c445ff
JB		 6108 /* Update the stats for active netdevs so the network stack
6109 * can look at updated numbers whenever it cares to
6110 */
505682cd 6111 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6112 if (pf->vsi[i] && pf->vsi[i]->netdev)
6113 i40e_update_stats(pf->vsi[i]);
6114
d1a8d275
ASJ		 6115 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6116 /* Update the stats for the active switching components */
6117 for (i = 0; i < I40E_MAX_VEB; i++)
6118 if (pf->veb[i])
6119 i40e_update_veb_stats(pf->veb[i]);
6120 }
beb0dff1
JK		 6121
6122 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6123}
6124
6125/**
6126 * i40e_reset_subtask - Set up for resetting the device and driver
6127 * @pf: board private structure
6128 **/
6129static void i40e_reset_subtask(struct i40e_pf *pf)
6130{
6131 u32 reset_flags = 0;
6132
23326186 6133 rtnl_lock();
41c445ff 6134 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6135 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6136 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6137 }
6138 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6139 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6140 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6141 }
6142 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6143 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6144 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6145 }
6146 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6147 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6148 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6149 }
b5d06f05 6150 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6151 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6152 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6153 }
41c445ff
JB		 6154
6155 /* If there's a recovery already waiting, it takes
6156 * precedence before starting a new reset sequence.
6157 */
6158 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6159 i40e_handle_reset_warning(pf);
23326186 6160 goto unlock;
41c445ff
JB		 6161 }
6162
6163 /* If we're already down or resetting, just bail */
6164 if (reset_flags &&
6165 !test_bit(__I40E_DOWN, &pf->state) &&
6166 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6167 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6168
6169unlock:
6170 rtnl_unlock();
41c445ff
JB		 6171}
6172
6173/**
6174 * i40e_handle_link_event - Handle link event
6175 * @pf: board private structure
6176 * @e: event info posted on ARQ
6177 **/
6178static void i40e_handle_link_event(struct i40e_pf *pf,
6179 struct i40e_arq_event_info *e)
6180{
41c445ff
JB		 6181 struct i40e_aqc_get_link_status *status =
6182 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6183
1e701e09
JB		 6184 /* Do a new status request to re-enable LSE reporting
6185 * and load new status information into the hw struct
6186 * This completely ignores any state information
6187 * in the ARQ event info, instead choosing to always
6188 * issue the AQ update link status command.
6189 */
6190 i40e_link_event(pf);
6191
7b592f61
CW		 6192 /* check for unqualified module, if link is down */
6193 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6194 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6195 (!(status->link_info & I40E_AQ_LINK_UP)))
6196 dev_err(&pf->pdev->dev,
6197 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6198}
6199
6200/**
6201 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6202 * @pf: board private structure
6203 **/
6204static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6205{
6206 struct i40e_arq_event_info event;
6207 struct i40e_hw *hw = &pf->hw;
6208 u16 pending, i = 0;
6209 i40e_status ret;
6210 u16 opcode;
86df242b 6211 u32 oldval;
41c445ff
JB		 6212 u32 val;
6213
a316f651
ASJ		 6214 /* Do not run clean AQ when PF reset fails */
6215 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6216 return;
6217
86df242b
SN		 6218 /* check for error indications */
6219 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6220 oldval = val;
6221 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6222 if (hw->debug_mask & I40E_DEBUG_AQ)
6223 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6224 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6225 }
6226 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6227 if (hw->debug_mask & I40E_DEBUG_AQ)
6228 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b
SN		 6229 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6230 }
6231 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6232 if (hw->debug_mask & I40E_DEBUG_AQ)
6233 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6234 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6235 }
6236 if (oldval != val)
6237 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6238
6239 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6240 oldval = val;
6241 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6242 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6243 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6244 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6245 }
6246 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6247 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6248 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6249 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6250 }
6251 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6252 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6253 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6254 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6255 }
6256 if (oldval != val)
6257 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6258
1001dc37
MW		 6259 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6260 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6261 if (!event.msg_buf)
6262 return;
6263
6264 do {
6265 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6266 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6267 break;
56497978 6268 else if (ret) {
41c445ff
JB		 6269 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6270 break;
6271 }
6272
6273 opcode = le16_to_cpu(event.desc.opcode);
6274 switch (opcode) {
6275
6276 case i40e_aqc_opc_get_link_status:
6277 i40e_handle_link_event(pf, &event);
6278 break;
6279 case i40e_aqc_opc_send_msg_to_pf:
6280 ret = i40e_vc_process_vf_msg(pf,
6281 le16_to_cpu(event.desc.retval),
6282 le32_to_cpu(event.desc.cookie_high),
6283 le32_to_cpu(event.desc.cookie_low),
6284 event.msg_buf,
1001dc37 6285 event.msg_len);
41c445ff
JB		 6286 break;
6287 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6288 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6289#ifdef CONFIG_I40E_DCB
6290 rtnl_lock();
6291 ret = i40e_handle_lldp_event(pf, &event);
6292 rtnl_unlock();
6293#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6294 break;
6295 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6296 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6297 i40e_handle_lan_overflow_event(pf, &event);
6298 break;
0467bc91
SN		 6299 case i40e_aqc_opc_send_msg_to_peer:
6300 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6301 break;
91a0f930
SN		 6302 case i40e_aqc_opc_nvm_erase:
6303 case i40e_aqc_opc_nvm_update:
00ada50d 6304 case i40e_aqc_opc_oem_post_update:
91a0f930
SN		 6305 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6306 break;
41c445ff
JB		 6307 default:
6308 dev_info(&pf->pdev->dev,
0467bc91
SN		 6309 "ARQ Error: Unknown event 0x%04x received\n",
6310 opcode);
41c445ff
JB		 6311 break;
6312 }
6313 } while (pending && (i++ < pf->adminq_work_limit));
6314
6315 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6316 /* re-enable Admin queue interrupt cause */
6317 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6318 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6319 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6320 i40e_flush(hw);
6321
6322 kfree(event.msg_buf);
6323}
6324
4eb3f768
SN		 6325/**
6326 * i40e_verify_eeprom - make sure eeprom is good to use
6327 * @pf: board private structure
6328 **/
6329static void i40e_verify_eeprom(struct i40e_pf *pf)
6330{
6331 int err;
6332
6333 err = i40e_diag_eeprom_test(&pf->hw);
6334 if (err) {
6335 /* retry in case of garbage read */
6336 err = i40e_diag_eeprom_test(&pf->hw);
6337 if (err) {
6338 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6339 err);
6340 set_bit(__I40E_BAD_EEPROM, &pf->state);
6341 }
6342 }
6343
6344 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6345 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6346 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6347 }
6348}
6349
386a0afa
AA		 6350/**
6351 * i40e_enable_pf_switch_lb
b40c82e6 6352 * @pf: pointer to the PF structure
386a0afa
AA		 6353 *
6354 * enable switch loop back or die - no point in a return value
6355 **/
6356static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6357{
6358 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6359 struct i40e_vsi_context ctxt;
f1c7e72e 6360 int ret;
386a0afa
AA		 6361
6362 ctxt.seid = pf->main_vsi_seid;
6363 ctxt.pf_num = pf->hw.pf_id;
6364 ctxt.vf_num = 0;
f1c7e72e
SN		 6365 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6366 if (ret) {
386a0afa 6367 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6368 "couldn't get PF vsi config, err %s aq_err %s\n",
6369 i40e_stat_str(&pf->hw, ret),
6370 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6371 return;
6372 }
6373 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6374 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6375 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6376
f1c7e72e
SN		 6377 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6378 if (ret) {
386a0afa 6379 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6380 "update vsi switch failed, err %s aq_err %s\n",
6381 i40e_stat_str(&pf->hw, ret),
6382 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6383 }
6384}
6385
6386/**
6387 * i40e_disable_pf_switch_lb
b40c82e6 6388 * @pf: pointer to the PF structure
386a0afa
AA		 6389 *
6390 * disable switch loop back or die - no point in a return value
6391 **/
6392static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6393{
6394 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6395 struct i40e_vsi_context ctxt;
f1c7e72e 6396 int ret;
386a0afa
AA		 6397
6398 ctxt.seid = pf->main_vsi_seid;
6399 ctxt.pf_num = pf->hw.pf_id;
6400 ctxt.vf_num = 0;
f1c7e72e
SN		 6401 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6402 if (ret) {
386a0afa 6403 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6404 "couldn't get PF vsi config, err %s aq_err %s\n",
6405 i40e_stat_str(&pf->hw, ret),
6406 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6407 return;
6408 }
6409 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6410 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6411 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6412
f1c7e72e
SN		 6413 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6414 if (ret) {
386a0afa 6415 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6416 "update vsi switch failed, err %s aq_err %s\n",
6417 i40e_stat_str(&pf->hw, ret),
6418 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6419 }
6420}
6421
51616018
NP		 6422/**
6423 * i40e_config_bridge_mode - Configure the HW bridge mode
6424 * @veb: pointer to the bridge instance
6425 *
6426 * Configure the loop back mode for the LAN VSI that is downlink to the
6427 * specified HW bridge instance. It is expected this function is called
6428 * when a new HW bridge is instantiated.
6429 **/
6430static void i40e_config_bridge_mode(struct i40e_veb *veb)
6431{
6432 struct i40e_pf *pf = veb->pf;
6433
6dec1017
SN		 6434 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6435 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6436 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6437 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6438 i40e_disable_pf_switch_lb(pf);
6439 else
6440 i40e_enable_pf_switch_lb(pf);
6441}
6442
41c445ff
JB		 6443/**
6444 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6445 * @veb: pointer to the VEB instance
6446 *
6447 * This is a recursive function that first builds the attached VSIs then
6448 * recurses in to build the next layer of VEB. We track the connections
6449 * through our own index numbers because the seid's from the HW could
6450 * change across the reset.
6451 **/
6452static int i40e_reconstitute_veb(struct i40e_veb *veb)
6453{
6454 struct i40e_vsi *ctl_vsi = NULL;
6455 struct i40e_pf *pf = veb->pf;
6456 int v, veb_idx;
6457 int ret;
6458
6459 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6460 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6461 if (pf->vsi[v] &&
6462 pf->vsi[v]->veb_idx == veb->idx &&
6463 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6464 ctl_vsi = pf->vsi[v];
6465 break;
6466 }
6467 }
6468 if (!ctl_vsi) {
6469 dev_info(&pf->pdev->dev,
6470 "missing owner VSI for veb_idx %d\n", veb->idx);
6471 ret = -ENOENT;
6472 goto end_reconstitute;
6473 }
6474 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6475 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6476 ret = i40e_add_vsi(ctl_vsi);
6477 if (ret) {
6478 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6479 "rebuild of veb_idx %d owner VSI failed: %d\n",
6480 veb->idx, ret);
41c445ff
JB		 6481 goto end_reconstitute;
6482 }
6483 i40e_vsi_reset_stats(ctl_vsi);
6484
6485 /* create the VEB in the switch and move the VSI onto the VEB */
6486 ret = i40e_add_veb(veb, ctl_vsi);
6487 if (ret)
6488 goto end_reconstitute;
6489
fc60861e
ASJ		 6490 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6491 veb->bridge_mode = BRIDGE_MODE_VEB;
6492 else
6493 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6494 i40e_config_bridge_mode(veb);
b64ba084 6495
41c445ff 6496 /* create the remaining VSIs attached to this VEB */
505682cd 6497 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6498 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6499 continue;
6500
6501 if (pf->vsi[v]->veb_idx == veb->idx) {
6502 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6503
41c445ff
JB		 6504 vsi->uplink_seid = veb->seid;
6505 ret = i40e_add_vsi(vsi);
6506 if (ret) {
6507 dev_info(&pf->pdev->dev,
6508 "rebuild of vsi_idx %d failed: %d\n",
6509 v, ret);
6510 goto end_reconstitute;
6511 }
6512 i40e_vsi_reset_stats(vsi);
6513 }
6514 }
6515
6516 /* create any VEBs attached to this VEB - RECURSION */
6517 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6518 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6519 pf->veb[veb_idx]->uplink_seid = veb->seid;
6520 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6521 if (ret)
6522 break;
6523 }
6524 }
6525
6526end_reconstitute:
6527 return ret;
6528}
6529
6530/**
6531 * i40e_get_capabilities - get info about the HW
6532 * @pf: the PF struct
6533 **/
6534static int i40e_get_capabilities(struct i40e_pf *pf)
6535{
6536 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6537 u16 data_size;
6538 int buf_len;
6539 int err;
6540
6541 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6542 do {
6543 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6544 if (!cap_buf)
6545 return -ENOMEM;
6546
6547 /* this loads the data into the hw struct for us */
6548 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6549 &data_size,
6550 i40e_aqc_opc_list_func_capabilities,
6551 NULL);
6552 /* data loaded, buffer no longer needed */
6553 kfree(cap_buf);
6554
6555 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6556 /* retry with a larger buffer */
6557 buf_len = data_size;
6558 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6559 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6560 "capability discovery failed, err %s aq_err %s\n",
6561 i40e_stat_str(&pf->hw, err),
6562 i40e_aq_str(&pf->hw,
6563 pf->hw.aq.asq_last_status));
41c445ff
JB		 6564 return -ENODEV;
6565 }
6566 } while (err);
6567
6568 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6569 dev_info(&pf->pdev->dev,
6570 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6571 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6572 pf->hw.func_caps.num_msix_vectors,
6573 pf->hw.func_caps.num_msix_vectors_vf,
6574 pf->hw.func_caps.fd_filters_guaranteed,
6575 pf->hw.func_caps.fd_filters_best_effort,
6576 pf->hw.func_caps.num_tx_qp,
6577 pf->hw.func_caps.num_vsis);
6578
7134f9ce
JB		 6579#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6580 + pf->hw.func_caps.num_vfs)
6581 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6582 dev_info(&pf->pdev->dev,
6583 "got num_vsis %d, setting num_vsis to %d\n",
6584 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6585 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6586 }
6587
41c445ff
JB		 6588 return 0;
6589}
6590
cbf61325
ASJ		 6591static int i40e_vsi_clear(struct i40e_vsi *vsi);
6592
41c445ff 6593/**
cbf61325 6594 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6595 * @pf: board private structure
6596 **/
cbf61325 6597static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6598{
6599 struct i40e_vsi *vsi;
8a9eb7d3 6600 int i;
41c445ff 6601
407e063c
JB		 6602 /* quick workaround for an NVM issue that leaves a critical register
6603 * uninitialized
6604 */
6605 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6606 static const u32 hkey[] = {
6607 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6608 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6609 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6610 0x95b3a76d};
6611
6612 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6613 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6614 }
6615
cbf61325 6616 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6617 return;
6618
cbf61325 6619 /* find existing VSI and see if it needs configuring */
41c445ff 6620 vsi = NULL;
505682cd 6621 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6622 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6623 vsi = pf->vsi[i];
cbf61325
ASJ		 6624 break;
6625 }
6626 }
6627
6628 /* create a new VSI if none exists */
41c445ff 6629 if (!vsi) {
cbf61325
ASJ		 6630 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6631 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6632 if (!vsi) {
6633 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6634 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6635 return;
41c445ff 6636 }
cbf61325 6637 }
41c445ff 6638
8a9eb7d3 6639 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6640}
6641
6642/**
6643 * i40e_fdir_teardown - release the Flow Director resources
6644 * @pf: board private structure
6645 **/
6646static void i40e_fdir_teardown(struct i40e_pf *pf)
6647{
6648 int i;
6649
17a73f6b 6650 i40e_fdir_filter_exit(pf);
505682cd 6651 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6652 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6653 i40e_vsi_release(pf->vsi[i]);
6654 break;
6655 }
6656 }
6657}
6658
6659/**
f650a38b 6660 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6661 * @pf: board private structure
6662 *
b40c82e6 6663 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6664 **/
23cfbe07 6665static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6666{
41c445ff 6667 struct i40e_hw *hw = &pf->hw;
60442dea 6668 i40e_status ret = 0;
41c445ff
JB		 6669 u32 v;
6670
6671 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6672 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6673 return;
41c445ff 6674
69bfb110 6675 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6676
41c445ff
JB		 6677 /* quiesce the VSIs and their queues that are not already DOWN */
6678 i40e_pf_quiesce_all_vsi(pf);
6679
505682cd 6680 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6681 if (pf->vsi[v])
6682 pf->vsi[v]->seid = 0;
6683 }
6684
6685 i40e_shutdown_adminq(&pf->hw);
6686
f650a38b 6687 /* call shutdown HMC */
60442dea
SN		 6688 if (hw->hmc.hmc_obj) {
6689 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6690 if (ret)
60442dea
SN		 6691 dev_warn(&pf->pdev->dev,
6692 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6693 }
f650a38b
ASJ		 6694}
6695
44033fac
JB		 6696/**
6697 * i40e_send_version - update firmware with driver version
6698 * @pf: PF struct
6699 */
6700static void i40e_send_version(struct i40e_pf *pf)
6701{
6702 struct i40e_driver_version dv;
6703
6704 dv.major_version = DRV_VERSION_MAJOR;
6705 dv.minor_version = DRV_VERSION_MINOR;
6706 dv.build_version = DRV_VERSION_BUILD;
6707 dv.subbuild_version = 0;
35a7d804 6708 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6709 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6710}
6711
f650a38b 6712/**
4dda12e6 6713 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6714 * @pf: board private structure
bc7d338f 6715 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6716 **/
bc7d338f 6717static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6718{
f650a38b 6719 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6720 u8 set_fc_aq_fail = 0;
f650a38b 6721 i40e_status ret;
4f2f017c 6722 u32 val;
f650a38b
ASJ		 6723 u32 v;
6724
41c445ff
JB		 6725 /* Now we wait for GRST to settle out.
6726 * We don't have to delete the VEBs or VSIs from the hw switch
6727 * because the reset will make them disappear.
6728 */
6729 ret = i40e_pf_reset(hw);
b5565400 6730 if (ret) {
41c445ff 6731 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6732 set_bit(__I40E_RESET_FAILED, &pf->state);
6733 goto clear_recovery;
b5565400 6734 }
41c445ff
JB		 6735 pf->pfr_count++;
6736
6737 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6738 goto clear_recovery;
69bfb110 6739 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6740
6741 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6742 ret = i40e_init_adminq(&pf->hw);
6743 if (ret) {
f1c7e72e
SN		 6744 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6745 i40e_stat_str(&pf->hw, ret),
6746 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6747 goto clear_recovery;
41c445ff
JB		 6748 }
6749
4eb3f768 6750 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6751 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6752 i40e_verify_eeprom(pf);
4eb3f768 6753
e78ac4bf 6754 i40e_clear_pxe_mode(hw);
41c445ff 6755 ret = i40e_get_capabilities(pf);
f1c7e72e 6756 if (ret)
41c445ff 6757 goto end_core_reset;
41c445ff 6758
41c445ff
JB		 6759 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6760 hw->func_caps.num_rx_qp,
6761 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6762 if (ret) {
6763 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6764 goto end_core_reset;
6765 }
6766 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6767 if (ret) {
6768 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6769 goto end_core_reset;
6770 }
6771
4e3b35b0
NP		 6772#ifdef CONFIG_I40E_DCB
6773 ret = i40e_init_pf_dcb(pf);
6774 if (ret) {
aebfc816
SN		 6775 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6776 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6777 /* Continue without DCB enabled */
4e3b35b0
NP		 6778 }
6779#endif /* CONFIG_I40E_DCB */
38e00438 6780#ifdef I40E_FCOE
21364bcf 6781 i40e_init_pf_fcoe(pf);
4e3b35b0 6782
38e00438 6783#endif
41c445ff 6784 /* do basic switch setup */
bc7d338f 6785 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6786 if (ret)
6787 goto end_core_reset;
6788
7e2453fe
JB		 6789 /* driver is only interested in link up/down and module qualification
6790 * reports from firmware
6791 */
6792 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6793 I40E_AQ_EVENT_LINK_UPDOWN |
6794 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6795 if (ret)
f1c7e72e
SN		 6796 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6797 i40e_stat_str(&pf->hw, ret),
6798 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6799
cafa2ee6
ASJ		 6800 /* make sure our flow control settings are restored */
6801 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6802 if (ret)
8279e495
NP		 6803 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6804 i40e_stat_str(&pf->hw, ret),
6805 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6806
41c445ff
JB		 6807 /* Rebuild the VSIs and VEBs that existed before reset.
6808 * They are still in our local switch element arrays, so only
6809 * need to rebuild the switch model in the HW.
6810 *
6811 * If there were VEBs but the reconstitution failed, we'll try
6812 * try to recover minimal use by getting the basic PF VSI working.
6813 */
6814 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6815 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6816 /* find the one VEB connected to the MAC, and find orphans */
6817 for (v = 0; v < I40E_MAX_VEB; v++) {
6818 if (!pf->veb[v])
6819 continue;
6820
6821 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6822 pf->veb[v]->uplink_seid == 0) {
6823 ret = i40e_reconstitute_veb(pf->veb[v]);
6824
6825 if (!ret)
6826 continue;
6827
6828 /* If Main VEB failed, we're in deep doodoo,
6829 * so give up rebuilding the switch and set up
6830 * for minimal rebuild of PF VSI.
6831 * If orphan failed, we'll report the error
6832 * but try to keep going.
6833 */
6834 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6835 dev_info(&pf->pdev->dev,
6836 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6837 ret);
6838 pf->vsi[pf->lan_vsi]->uplink_seid
6839 = pf->mac_seid;
6840 break;
6841 } else if (pf->veb[v]->uplink_seid == 0) {
6842 dev_info(&pf->pdev->dev,
6843 "rebuild of orphan VEB failed: %d\n",
6844 ret);
6845 }
6846 }
6847 }
6848 }
6849
6850 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6851 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6852 /* no VEB, so rebuild only the Main VSI */
6853 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6854 if (ret) {
6855 dev_info(&pf->pdev->dev,
6856 "rebuild of Main VSI failed: %d\n", ret);
6857 goto end_core_reset;
6858 }
6859 }
6860
4f2f017c
ASJ		 6861 /* Reconfigure hardware for allowing smaller MSS in the case
6862 * of TSO, so that we avoid the MDD being fired and causing
6863 * a reset in the case of small MSS+TSO.
6864 */
6865#define I40E_REG_MSS 0x000E64DC
6866#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6867#define I40E_64BYTE_MSS 0x400000
6868 val = rd32(hw, I40E_REG_MSS);
6869 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6870 val &= ~I40E_REG_MSS_MIN_MASK;
6871 val |= I40E_64BYTE_MSS;
6872 wr32(hw, I40E_REG_MSS, val);
6873 }
6874
025b4a54
ASJ		 6875 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6876 (pf->hw.aq.fw_maj_ver < 4)) {
6877 msleep(75);
6878 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6879 if (ret)
f1c7e72e
SN		 6880 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6881 i40e_stat_str(&pf->hw, ret),
6882 i40e_aq_str(&pf->hw,
6883 pf->hw.aq.asq_last_status));
cafa2ee6 6884 }
41c445ff
JB		 6885 /* reinit the misc interrupt */
6886 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6887 ret = i40e_setup_misc_vector(pf);
6888
e7358f54
ASJ		 6889 /* Add a filter to drop all Flow control frames from any VSI from being
6890 * transmitted. By doing so we stop a malicious VF from sending out
6891 * PAUSE or PFC frames and potentially controlling traffic for other
6892 * PF/VF VSIs.
6893 * The FW can still send Flow control frames if enabled.
6894 */
6895 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6896 pf->main_vsi_seid);
6897
41c445ff
JB		 6898 /* restart the VSIs that were rebuilt and running before the reset */
6899 i40e_pf_unquiesce_all_vsi(pf);
6900
69f64b2b
MW		 6901 if (pf->num_alloc_vfs) {
6902 for (v = 0; v < pf->num_alloc_vfs; v++)
6903 i40e_reset_vf(&pf->vf[v], true);
6904 }
6905
41c445ff 6906 /* tell the firmware that we're starting */
44033fac 6907 i40e_send_version(pf);
41c445ff
JB		 6908
6909end_core_reset:
a316f651
ASJ		 6910 clear_bit(__I40E_RESET_FAILED, &pf->state);
6911clear_recovery:
41c445ff
JB		 6912 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6913}
6914
f650a38b 6915/**
b40c82e6 6916 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6917 * @pf: board private structure
6918 *
6919 * Close up the VFs and other things in prep for a Core Reset,
6920 * then get ready to rebuild the world.
6921 **/
6922static void i40e_handle_reset_warning(struct i40e_pf *pf)
6923{
23cfbe07
SN		 6924 i40e_prep_for_reset(pf);
6925 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6926}
6927
41c445ff
JB		 6928/**
6929 * i40e_handle_mdd_event
b40c82e6 6930 * @pf: pointer to the PF structure
41c445ff
JB		 6931 *
6932 * Called from the MDD irq handler to identify possibly malicious vfs
6933 **/
6934static void i40e_handle_mdd_event(struct i40e_pf *pf)
6935{
6936 struct i40e_hw *hw = &pf->hw;
6937 bool mdd_detected = false;
df430b12 6938 bool pf_mdd_detected = false;
41c445ff
JB		 6939 struct i40e_vf *vf;
6940 u32 reg;
6941 int i;
6942
6943 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6944 return;
6945
6946 /* find what triggered the MDD event */
6947 reg = rd32(hw, I40E_GL_MDET_TX);
6948 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6949 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6950 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6951 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6952 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6953 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6954 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6955 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6956 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6957 pf->hw.func_caps.base_queue;
faf32978 6958 if (netif_msg_tx_err(pf))
b40c82e6 6959 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6960 event, queue, pf_num, vf_num);
41c445ff
JB		 6961 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6962 mdd_detected = true;
6963 }
6964 reg = rd32(hw, I40E_GL_MDET_RX);
6965 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6966 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6967 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6968 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6969 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6970 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6971 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6972 pf->hw.func_caps.base_queue;
faf32978
JB		 6973 if (netif_msg_rx_err(pf))
6974 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6975 event, queue, func);
41c445ff
JB		 6976 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6977 mdd_detected = true;
6978 }
6979
df430b12
NP		 6980 if (mdd_detected) {
6981 reg = rd32(hw, I40E_PF_MDET_TX);
6982 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6983 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6984 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6985 pf_mdd_detected = true;
6986 }
6987 reg = rd32(hw, I40E_PF_MDET_RX);
6988 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6989 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6990 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6991 pf_mdd_detected = true;
6992 }
6993 /* Queue belongs to the PF, initiate a reset */
6994 if (pf_mdd_detected) {
6995 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6996 i40e_service_event_schedule(pf);
6997 }
6998 }
6999
41c445ff
JB		 7000 /* see if one of the VFs needs its hand slapped */
7001 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7002 vf = &(pf->vf[i]);
7003 reg = rd32(hw, I40E_VP_MDET_TX(i));
7004 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7005 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7006 vf->num_mdd_events++;
faf32978
JB		 7007 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7008 i);
41c445ff
JB		 7009 }
7010
7011 reg = rd32(hw, I40E_VP_MDET_RX(i));
7012 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7013 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7014 vf->num_mdd_events++;
faf32978
JB		 7015 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7016 i);
41c445ff
JB		 7017 }
7018
7019 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7020 dev_info(&pf->pdev->dev,
7021 "Too many MDD events on VF %d, disabled\n", i);
7022 dev_info(&pf->pdev->dev,
7023 "Use PF Control I/F to re-enable the VF\n");
7024 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7025 }
7026 }
7027
7028 /* re-enable mdd interrupt cause */
7029 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7030 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7031 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7032 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7033 i40e_flush(hw);
7034}
7035
6633d381 7036#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 7037/**
7038 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
7039 * @pf: board private structure
7040 **/
7041static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
7042{
a1c9a9d9
JK		 7043 struct i40e_hw *hw = &pf->hw;
7044 i40e_status ret;
a1c9a9d9
JK		 7045 __be16 port;
7046 int i;
7047
7048 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
7049 return;
7050
7051 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
7052
7053 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 7054 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
7055 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 7056 port = pf->vxlan_ports[i];
c22c06c8
SN		 7057 if (port)
7058 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 7059 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 7060 NULL, NULL);
7061 else
7062 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7063
7064 if (ret) {
c22c06c8 7065 dev_info(&pf->pdev->dev,
f1c7e72e 7066 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 7067 port ? "add" : "delete",
f1c7e72e
SN		 7068 ntohs(port), i,
7069 i40e_stat_str(&pf->hw, ret),
7070 i40e_aq_str(&pf->hw,
7071 pf->hw.aq.asq_last_status));
a1c9a9d9 7072 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 7073 }
7074 }
7075 }
7076}
7077
7078#endif
41c445ff
JB		 7079/**
7080 * i40e_service_task - Run the driver's async subtasks
7081 * @work: pointer to work_struct containing our data
7082 **/
7083static void i40e_service_task(struct work_struct *work)
7084{
7085 struct i40e_pf *pf = container_of(work,
7086 struct i40e_pf,
7087 service_task);
7088 unsigned long start_time = jiffies;
7089
e57a2fea
SN		 7090 /* don't bother with service tasks if a reset is in progress */
7091 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7092 i40e_service_event_complete(pf);
7093 return;
7094 }
7095
b03a8c1f 7096 i40e_detect_recover_hung(pf);
41c445ff
JB		 7097 i40e_reset_subtask(pf);
7098 i40e_handle_mdd_event(pf);
7099 i40e_vc_process_vflr_event(pf);
7100 i40e_watchdog_subtask(pf);
7101 i40e_fdir_reinit_subtask(pf);
41c445ff 7102 i40e_sync_filters_subtask(pf);
6633d381 7103#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 7104 i40e_sync_vxlan_filters_subtask(pf);
7105#endif
41c445ff
JB		 7106 i40e_clean_adminq_subtask(pf);
7107
7108 i40e_service_event_complete(pf);
7109
7110 /* If the tasks have taken longer than one timer cycle or there
7111 * is more work to be done, reschedule the service task now
7112 * rather than wait for the timer to tick again.
7113 */
7114 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7115 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7116 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7117 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7118 i40e_service_event_schedule(pf);
7119}
7120
7121/**
7122 * i40e_service_timer - timer callback
7123 * @data: pointer to PF struct
7124 **/
7125static void i40e_service_timer(unsigned long data)
7126{
7127 struct i40e_pf *pf = (struct i40e_pf *)data;
7128
7129 mod_timer(&pf->service_timer,
7130 round_jiffies(jiffies + pf->service_timer_period));
7131 i40e_service_event_schedule(pf);
7132}
7133
7134/**
7135 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7136 * @vsi: the VSI being configured
7137 **/
7138static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7139{
7140 struct i40e_pf *pf = vsi->back;
7141
7142 switch (vsi->type) {
7143 case I40E_VSI_MAIN:
7144 vsi->alloc_queue_pairs = pf->num_lan_qps;
7145 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7146 I40E_REQ_DESCRIPTOR_MULTIPLE);
7147 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7148 vsi->num_q_vectors = pf->num_lan_msix;
7149 else
7150 vsi->num_q_vectors = 1;
7151
7152 break;
7153
7154 case I40E_VSI_FDIR:
7155 vsi->alloc_queue_pairs = 1;
7156 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7157 I40E_REQ_DESCRIPTOR_MULTIPLE);
7158 vsi->num_q_vectors = 1;
7159 break;
7160
7161 case I40E_VSI_VMDQ2:
7162 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7163 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7164 I40E_REQ_DESCRIPTOR_MULTIPLE);
7165 vsi->num_q_vectors = pf->num_vmdq_msix;
7166 break;
7167
7168 case I40E_VSI_SRIOV:
7169 vsi->alloc_queue_pairs = pf->num_vf_qps;
7170 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7171 I40E_REQ_DESCRIPTOR_MULTIPLE);
7172 break;
7173
38e00438
VD		 7174#ifdef I40E_FCOE
7175 case I40E_VSI_FCOE:
7176 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7177 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7178 I40E_REQ_DESCRIPTOR_MULTIPLE);
7179 vsi->num_q_vectors = pf->num_fcoe_msix;
7180 break;
7181
7182#endif /* I40E_FCOE */
41c445ff
JB		 7183 default:
7184 WARN_ON(1);
7185 return -ENODATA;
7186 }
7187
7188 return 0;
7189}
7190
f650a38b
ASJ		 7191/**
7192 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7193 * @type: VSI pointer
bc7d338f 7194 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7195 *
7196 * On error: returns error code (negative)
7197 * On success: returns 0
7198 **/
bc7d338f 7199static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7200{
7201 int size;
7202 int ret = 0;
7203
ac6c5e3d 7204 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7205 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7206 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7207 if (!vsi->tx_rings)
7208 return -ENOMEM;
f650a38b
ASJ		 7209 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7210
bc7d338f
ASJ		 7211 if (alloc_qvectors) {
7212 /* allocate memory for q_vector pointers */
f57e4fbd 7213 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7214 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7215 if (!vsi->q_vectors) {
7216 ret = -ENOMEM;
7217 goto err_vectors;
7218 }
f650a38b
ASJ		 7219 }
7220 return ret;
7221
7222err_vectors:
7223 kfree(vsi->tx_rings);
7224 return ret;
7225}
7226
41c445ff
JB		 7227/**
7228 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7229 * @pf: board private structure
7230 * @type: type of VSI
7231 *
7232 * On error: returns error code (negative)
7233 * On success: returns vsi index in PF (positive)
7234 **/
7235static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7236{
7237 int ret = -ENODEV;
7238 struct i40e_vsi *vsi;
7239 int vsi_idx;
7240 int i;
7241
7242 /* Need to protect the allocation of the VSIs at the PF level */
7243 mutex_lock(&pf->switch_mutex);
7244
7245 /* VSI list may be fragmented if VSI creation/destruction has
7246 * been happening. We can afford to do a quick scan to look
7247 * for any free VSIs in the list.
7248 *
7249 * find next empty vsi slot, looping back around if necessary
7250 */
7251 i = pf->next_vsi;
505682cd 7252 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7253 i++;
505682cd 7254 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7255 i = 0;
7256 while (i < pf->next_vsi && pf->vsi[i])
7257 i++;
7258 }
7259
505682cd 7260 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7261 vsi_idx = i; /* Found one! */
7262 } else {
7263 ret = -ENODEV;
493fb300 7264 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7265 }
7266 pf->next_vsi = ++i;
7267
7268 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7269 if (!vsi) {
7270 ret = -ENOMEM;
493fb300 7271 goto unlock_pf;
41c445ff
JB		 7272 }
7273 vsi->type = type;
7274 vsi->back = pf;
7275 set_bit(__I40E_DOWN, &vsi->state);
7276 vsi->flags = 0;
7277 vsi->idx = vsi_idx;
7278 vsi->rx_itr_setting = pf->rx_itr_default;
7279 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7280 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7281 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7282 pf->rss_table_size : 64;
41c445ff
JB		 7283 vsi->netdev_registered = false;
7284 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7285 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7286 vsi->irqs_ready = false;
41c445ff 7287
9f65e15b
AD		 7288 ret = i40e_set_num_rings_in_vsi(vsi);
7289 if (ret)
7290 goto err_rings;
7291
bc7d338f 7292 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7293 if (ret)
9f65e15b 7294 goto err_rings;
493fb300 7295
41c445ff
JB		 7296 /* Setup default MSIX irq handler for VSI */
7297 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7298
21659035
KP		 7299 /* Initialize VSI lock */
7300 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7301 pf->vsi[vsi_idx] = vsi;
7302 ret = vsi_idx;
493fb300
AD		 7303 goto unlock_pf;
7304
9f65e15b 7305err_rings:
493fb300
AD		 7306 pf->next_vsi = i - 1;
7307 kfree(vsi);
7308unlock_pf:
41c445ff
JB		 7309 mutex_unlock(&pf->switch_mutex);
7310 return ret;
7311}
7312
f650a38b
ASJ		 7313/**
7314 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7315 * @type: VSI pointer
bc7d338f 7316 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7317 *
7318 * On error: returns error code (negative)
7319 * On success: returns 0
7320 **/
bc7d338f 7321static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7322{
7323 /* free the ring and vector containers */
bc7d338f
ASJ		 7324 if (free_qvectors) {
7325 kfree(vsi->q_vectors);
7326 vsi->q_vectors = NULL;
7327 }
f650a38b
ASJ		 7328 kfree(vsi->tx_rings);
7329 vsi->tx_rings = NULL;
7330 vsi->rx_rings = NULL;
7331}
7332
28c5869f
HZ		 7333/**
7334 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7335 * and lookup table
7336 * @vsi: Pointer to VSI structure
7337 */
7338static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7339{
7340 if (!vsi)
7341 return;
7342
7343 kfree(vsi->rss_hkey_user);
7344 vsi->rss_hkey_user = NULL;
7345
7346 kfree(vsi->rss_lut_user);
7347 vsi->rss_lut_user = NULL;
7348}
7349
41c445ff
JB		 7350/**
7351 * i40e_vsi_clear - Deallocate the VSI provided
7352 * @vsi: the VSI being un-configured
7353 **/
7354static int i40e_vsi_clear(struct i40e_vsi *vsi)
7355{
7356 struct i40e_pf *pf;
7357
7358 if (!vsi)
7359 return 0;
7360
7361 if (!vsi->back)
7362 goto free_vsi;
7363 pf = vsi->back;
7364
7365 mutex_lock(&pf->switch_mutex);
7366 if (!pf->vsi[vsi->idx]) {
7367 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7368 vsi->idx, vsi->idx, vsi, vsi->type);
7369 goto unlock_vsi;
7370 }
7371
7372 if (pf->vsi[vsi->idx] != vsi) {
7373 dev_err(&pf->pdev->dev,
7374 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7375 pf->vsi[vsi->idx]->idx,
7376 pf->vsi[vsi->idx],
7377 pf->vsi[vsi->idx]->type,
7378 vsi->idx, vsi, vsi->type);
7379 goto unlock_vsi;
7380 }
7381
b40c82e6 7382 /* updates the PF for this cleared vsi */
41c445ff
JB		 7383 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7384 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7385
bc7d338f 7386 i40e_vsi_free_arrays(vsi, true);
28c5869f 7387 i40e_clear_rss_config_user(vsi);
493fb300 7388
41c445ff
JB		 7389 pf->vsi[vsi->idx] = NULL;
7390 if (vsi->idx < pf->next_vsi)
7391 pf->next_vsi = vsi->idx;
7392
7393unlock_vsi:
7394 mutex_unlock(&pf->switch_mutex);
7395free_vsi:
7396 kfree(vsi);
7397
7398 return 0;
7399}
7400
9f65e15b
AD		 7401/**
7402 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7403 * @vsi: the VSI being cleaned
7404 **/
be1d5eea 7405static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7406{
7407 int i;
7408
8e9dca53 7409 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7410 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7411 kfree_rcu(vsi->tx_rings[i], rcu);
7412 vsi->tx_rings[i] = NULL;
7413 vsi->rx_rings[i] = NULL;
7414 }
be1d5eea 7415 }
9f65e15b
AD		 7416}
7417
41c445ff
JB		 7418/**
7419 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7420 * @vsi: the VSI being configured
7421 **/
7422static int i40e_alloc_rings(struct i40e_vsi *vsi)
7423{
e7046ee1 7424 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7425 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7426 int i;
7427
41c445ff 7428 /* Set basic values in the rings to be used later during open() */
d7397644 7429 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7430 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7431 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7432 if (!tx_ring)
7433 goto err_out;
41c445ff
JB		 7434
7435 tx_ring->queue_index = i;
7436 tx_ring->reg_idx = vsi->base_queue + i;
7437 tx_ring->ring_active = false;
7438 tx_ring->vsi = vsi;
7439 tx_ring->netdev = vsi->netdev;
7440 tx_ring->dev = &pf->pdev->dev;
7441 tx_ring->count = vsi->num_desc;
7442 tx_ring->size = 0;
7443 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7444 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7445 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7446 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7447 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7448 vsi->tx_rings[i] = tx_ring;
41c445ff 7449
9f65e15b 7450 rx_ring = &tx_ring[1];
41c445ff
JB		 7451 rx_ring->queue_index = i;
7452 rx_ring->reg_idx = vsi->base_queue + i;
7453 rx_ring->ring_active = false;
7454 rx_ring->vsi = vsi;
7455 rx_ring->netdev = vsi->netdev;
7456 rx_ring->dev = &pf->pdev->dev;
7457 rx_ring->count = vsi->num_desc;
7458 rx_ring->size = 0;
7459 rx_ring->dcb_tc = 0;
7460 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7461 set_ring_16byte_desc_enabled(rx_ring);
7462 else
7463 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7464 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7465 }
7466
7467 return 0;
9f65e15b
AD		 7468
7469err_out:
7470 i40e_vsi_clear_rings(vsi);
7471 return -ENOMEM;
41c445ff
JB		 7472}
7473
7474/**
7475 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7476 * @pf: board private structure
7477 * @vectors: the number of MSI-X vectors to request
7478 *
7479 * Returns the number of vectors reserved, or error
7480 **/
7481static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7482{
7b37f376
AG		 7483 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7484 I40E_MIN_MSIX, vectors);
7485 if (vectors < 0) {
41c445ff 7486 dev_info(&pf->pdev->dev,
7b37f376 7487 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7488 vectors = 0;
7489 }
7490
7491 return vectors;
7492}
7493
7494/**
7495 * i40e_init_msix - Setup the MSIX capability
7496 * @pf: board private structure
7497 *
7498 * Work with the OS to set up the MSIX vectors needed.
7499 *
3b444399 7500 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7501 **/
7502static int i40e_init_msix(struct i40e_pf *pf)
7503{
41c445ff 7504 struct i40e_hw *hw = &pf->hw;
1e200e4a 7505 int vectors_left;
41c445ff 7506 int v_budget, i;
3b444399 7507 int v_actual;
41c445ff
JB		 7508
7509 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7510 return -ENODEV;
7511
7512 /* The number of vectors we'll request will be comprised of:
7513 * - Add 1 for "other" cause for Admin Queue events, etc.
7514 * - The number of LAN queue pairs
f8ff1464
ASJ		 7515 * - Queues being used for RSS.
7516 * We don't need as many as max_rss_size vectors.
7517 * use rss_size instead in the calculation since that
7518 * is governed by number of cpus in the system.
7519 * - assumes symmetric Tx/Rx pairing
41c445ff 7520 * - The number of VMDq pairs
38e00438
VD		 7521#ifdef I40E_FCOE
7522 * - The number of FCOE qps.
7523#endif
41c445ff
JB		 7524 * Once we count this up, try the request.
7525 *
7526 * If we can't get what we want, we'll simplify to nearly nothing
7527 * and try again. If that still fails, we punt.
7528 */
1e200e4a
SN		 7529 vectors_left = hw->func_caps.num_msix_vectors;
7530 v_budget = 0;
7531
7532 /* reserve one vector for miscellaneous handler */
7533 if (vectors_left) {
7534 v_budget++;
7535 vectors_left--;
7536 }
7537
7538 /* reserve vectors for the main PF traffic queues */
7539 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7540 vectors_left -= pf->num_lan_msix;
7541 v_budget += pf->num_lan_msix;
7542
7543 /* reserve one vector for sideband flow director */
7544 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7545 if (vectors_left) {
7546 v_budget++;
7547 vectors_left--;
7548 } else {
7549 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7550 }
7551 }
83840e4b 7552
38e00438 7553#ifdef I40E_FCOE
1e200e4a 7554 /* can we reserve enough for FCoE? */
38e00438 7555 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7556 if (!vectors_left)
7557 pf->num_fcoe_msix = 0;
7558 else if (vectors_left >= pf->num_fcoe_qps)
7559 pf->num_fcoe_msix = pf->num_fcoe_qps;
7560 else
7561 pf->num_fcoe_msix = 1;
38e00438 7562 v_budget += pf->num_fcoe_msix;
1e200e4a 7563 vectors_left -= pf->num_fcoe_msix;
38e00438 7564 }
1e200e4a 7565
38e00438 7566#endif
1e200e4a
SN		 7567 /* any vectors left over go for VMDq support */
7568 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7569 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7570 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7571
7572 /* if we're short on vectors for what's desired, we limit
7573 * the queues per vmdq. If this is still more than are
7574 * available, the user will need to change the number of
7575 * queues/vectors used by the PF later with the ethtool
7576 * channels command
7577 */
7578 if (vmdq_vecs < vmdq_vecs_wanted)
7579 pf->num_vmdq_qps = 1;
7580 pf->num_vmdq_msix = pf->num_vmdq_qps;
7581
7582 v_budget += vmdq_vecs;
7583 vectors_left -= vmdq_vecs;
7584 }
41c445ff
JB		 7585
7586 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7587 GFP_KERNEL);
7588 if (!pf->msix_entries)
7589 return -ENOMEM;
7590
7591 for (i = 0; i < v_budget; i++)
7592 pf->msix_entries[i].entry = i;
3b444399 7593 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7594
3b444399 7595 if (v_actual != v_budget) {
a34977ba
ASJ		 7596 /* If we have limited resources, we will start with no vectors
7597 * for the special features and then allocate vectors to some
7598 * of these features based on the policy and at the end disable
7599 * the features that did not get any vectors.
7600 */
38e00438
VD		 7601#ifdef I40E_FCOE
7602 pf->num_fcoe_qps = 0;
7603 pf->num_fcoe_msix = 0;
7604#endif
a34977ba
ASJ		 7605 pf->num_vmdq_msix = 0;
7606 }
7607
3b444399 7608 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7609 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7610 kfree(pf->msix_entries);
7611 pf->msix_entries = NULL;
7612 return -ENODEV;
7613
3b444399 7614 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7615 /* Adjust for minimal MSIX use */
41c445ff
JB		 7616 pf->num_vmdq_vsis = 0;
7617 pf->num_vmdq_qps = 0;
41c445ff
JB		 7618 pf->num_lan_qps = 1;
7619 pf->num_lan_msix = 1;
7620
3b444399
SN		 7621 } else if (v_actual != v_budget) {
7622 int vec;
7623
a34977ba 7624 /* reserve the misc vector */
3b444399 7625 vec = v_actual - 1;
a34977ba 7626
41c445ff
JB		 7627 /* Scale vector usage down */
7628 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7629 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7630 pf->num_vmdq_qps = 1;
7631 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7632
7633 /* partition out the remaining vectors */
7634 switch (vec) {
7635 case 2:
41c445ff
JB		 7636 pf->num_lan_msix = 1;
7637 break;
7638 case 3:
38e00438
VD		 7639#ifdef I40E_FCOE
7640 /* give one vector to FCoE */
7641 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7642 pf->num_lan_msix = 1;
7643 pf->num_fcoe_msix = 1;
7644 }
7645#else
41c445ff 7646 pf->num_lan_msix = 2;
38e00438 7647#endif
41c445ff
JB		 7648 break;
7649 default:
38e00438
VD		 7650#ifdef I40E_FCOE
7651 /* give one vector to FCoE */
7652 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7653 pf->num_fcoe_msix = 1;
7654 vec--;
7655 }
7656#endif
1e200e4a
SN		 7657 /* give the rest to the PF */
7658 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7659 break;
7660 }
7661 }
7662
a34977ba
ASJ		 7663 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7664 (pf->num_vmdq_msix == 0)) {
7665 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7666 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7667 }
38e00438
VD		 7668#ifdef I40E_FCOE
7669
7670 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7671 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7672 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7673 }
7674#endif
3b444399 7675 return v_actual;
41c445ff
JB		 7676}
7677
493fb300 7678/**
90e04070 7679 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7680 * @vsi: the VSI being configured
7681 * @v_idx: index of the vector in the vsi struct
7682 *
7683 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7684 **/
90e04070 7685static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7686{
7687 struct i40e_q_vector *q_vector;
7688
7689 /* allocate q_vector */
7690 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7691 if (!q_vector)
7692 return -ENOMEM;
7693
7694 q_vector->vsi = vsi;
7695 q_vector->v_idx = v_idx;
7696 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7697 if (vsi->netdev)
7698 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7699 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7700
cd0b6fa6
AD		 7701 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7702 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7703
493fb300
AD		 7704 /* tie q_vector and vsi together */
7705 vsi->q_vectors[v_idx] = q_vector;
7706
7707 return 0;
7708}
7709
41c445ff 7710/**
90e04070 7711 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7712 * @vsi: the VSI being configured
7713 *
7714 * We allocate one q_vector per queue interrupt. If allocation fails we
7715 * return -ENOMEM.
7716 **/
90e04070 7717static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7718{
7719 struct i40e_pf *pf = vsi->back;
7720 int v_idx, num_q_vectors;
493fb300 7721 int err;
41c445ff
JB		 7722
7723 /* if not MSIX, give the one vector only to the LAN VSI */
7724 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7725 num_q_vectors = vsi->num_q_vectors;
7726 else if (vsi == pf->vsi[pf->lan_vsi])
7727 num_q_vectors = 1;
7728 else
7729 return -EINVAL;
7730
41c445ff 7731 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7732 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7733 if (err)
7734 goto err_out;
41c445ff
JB		 7735 }
7736
7737 return 0;
493fb300
AD		 7738
7739err_out:
7740 while (v_idx--)
7741 i40e_free_q_vector(vsi, v_idx);
7742
7743 return err;
41c445ff
JB		 7744}
7745
7746/**
7747 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7748 * @pf: board private structure to initialize
7749 **/
c1147280 7750static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7751{
3b444399
SN		 7752 int vectors = 0;
7753 ssize_t size;
41c445ff
JB		 7754
7755 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7756 vectors = i40e_init_msix(pf);
7757 if (vectors < 0) {
60ea5f83 7758 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7759#ifdef I40E_FCOE
7760 I40E_FLAG_FCOE_ENABLED |
7761#endif
60ea5f83 7762 I40E_FLAG_RSS_ENABLED |
4d9b6043 7763 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7764 I40E_FLAG_SRIOV_ENABLED |
7765 I40E_FLAG_FD_SB_ENABLED |
7766 I40E_FLAG_FD_ATR_ENABLED |
7767 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7768
7769 /* rework the queue expectations without MSIX */
7770 i40e_determine_queue_usage(pf);
7771 }
7772 }
7773
7774 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7775 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7776 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7777 vectors = pci_enable_msi(pf->pdev);
7778 if (vectors < 0) {
7779 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7780 vectors);
41c445ff
JB		 7781 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7782 }
3b444399 7783 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7784 }
7785
958a3e3b 7786 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7787 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7788
3b444399
SN		 7789 /* set up vector assignment tracking */
7790 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7791 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7792 if (!pf->irq_pile) {
7793 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7794 return -ENOMEM;
7795 }
3b444399
SN		 7796 pf->irq_pile->num_entries = vectors;
7797 pf->irq_pile->search_hint = 0;
7798
c1147280 7799 /* track first vector for misc interrupts, ignore return */
3b444399 7800 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7801
7802 return 0;
41c445ff
JB		 7803}
7804
7805/**
7806 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7807 * @pf: board private structure
7808 *
7809 * This sets up the handler for MSIX 0, which is used to manage the
7810 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7811 * when in MSI or Legacy interrupt mode.
7812 **/
7813static int i40e_setup_misc_vector(struct i40e_pf *pf)
7814{
7815 struct i40e_hw *hw = &pf->hw;
7816 int err = 0;
7817
7818 /* Only request the irq if this is the first time through, and
7819 * not when we're rebuilding after a Reset
7820 */
7821 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7822 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7823 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7824 if (err) {
7825 dev_info(&pf->pdev->dev,
77fa28be 7826 "request_irq for %s failed: %d\n",
b294ac70 7827 pf->int_name, err);
41c445ff
JB		 7828 return -EFAULT;
7829 }
7830 }
7831
ab437b5a 7832 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7833
7834 /* associate no queues to the misc vector */
7835 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7836 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7837
7838 i40e_flush(hw);
7839
7840 i40e_irq_dynamic_enable_icr0(pf);
7841
7842 return err;
7843}
7844
7845/**
e25d00b8
ASJ		 7846 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7847 * @vsi: vsi structure
7848 * @seed: RSS hash seed
7849 **/
e69ff813
HZ		 7850static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7851 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7852{
7853 struct i40e_aqc_get_set_rss_key_data rss_key;
7854 struct i40e_pf *pf = vsi->back;
7855 struct i40e_hw *hw = &pf->hw;
7856 bool pf_lut = false;
7857 u8 *rss_lut;
7858 int ret, i;
7859
7860 memset(&rss_key, 0, sizeof(rss_key));
7861 memcpy(&rss_key, seed, sizeof(rss_key));
7862
7863 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7864 if (!rss_lut)
7865 return -ENOMEM;
7866
7867 /* Populate the LUT with max no. of queues in round robin fashion */
7868 for (i = 0; i < vsi->rss_table_size; i++)
7869 rss_lut[i] = i % vsi->rss_size;
7870
7871 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7872 if (ret) {
7873 dev_info(&pf->pdev->dev,
7874 "Cannot set RSS key, err %s aq_err %s\n",
7875 i40e_stat_str(&pf->hw, ret),
7876 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7877 goto config_rss_aq_out;
e25d00b8
ASJ		 7878 }
7879
7880 if (vsi->type == I40E_VSI_MAIN)
7881 pf_lut = true;
7882
7883 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7884 vsi->rss_table_size);
7885 if (ret)
7886 dev_info(&pf->pdev->dev,
7887 "Cannot set RSS lut, err %s aq_err %s\n",
7888 i40e_stat_str(&pf->hw, ret),
7889 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7890
126b63d9
AS		 7891config_rss_aq_out:
7892 kfree(rss_lut);
e25d00b8
ASJ		 7893 return ret;
7894}
7895
7896/**
7897 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7898 * @vsi: VSI structure
7899 **/
7900static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7901{
7902 u8 seed[I40E_HKEY_ARRAY_SIZE];
7903 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7904 u8 *lut;
7905 int ret;
7906
7907 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7908 return 0;
7909
7910 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7911 if (!lut)
7912 return -ENOMEM;
e25d00b8 7913
e69ff813 7914 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7915 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7916 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7917 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7918 kfree(lut);
e25d00b8 7919
e69ff813 7920 return ret;
e25d00b8
ASJ		 7921}
7922
7923/**
043dd650 7924 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 7925 * @vsi: Pointer to vsi structure
e25d00b8 7926 * @seed: RSS hash seed
e69ff813
HZ		 7927 * @lut: Lookup table
7928 * @lut_size: Lookup table size
7929 *
7930 * Returns 0 on success, negative on failure
41c445ff 7931 **/
e69ff813
HZ		 7932static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
7933 const u8 *lut, u16 lut_size)
41c445ff 7934{
e69ff813 7935 struct i40e_pf *pf = vsi->back;
4617e8c0 7936 struct i40e_hw *hw = &pf->hw;
e69ff813 7937 u8 i;
41c445ff 7938
e25d00b8 7939 /* Fill out hash function seed */
e69ff813
HZ		 7940 if (seed) {
7941 u32 *seed_dw = (u32 *)seed;
7942
7943 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7944 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7945 }
7946
7947 if (lut) {
7948 u32 *lut_dw = (u32 *)lut;
7949
7950 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7951 return -EINVAL;
7952
7953 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7954 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
e25d00b8
ASJ		 7955 }
7956 i40e_flush(hw);
7957
7958 return 0;
7959}
7960
043dd650
HZ		 7961/**
7962 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
7963 * @vsi: Pointer to VSI structure
7964 * @seed: Buffer to store the keys
7965 * @lut: Buffer to store the lookup table entries
7966 * @lut_size: Size of buffer to store the lookup table entries
7967 *
7968 * Returns 0 on success, negative on failure
7969 */
7970static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
7971 u8 *lut, u16 lut_size)
7972{
7973 struct i40e_pf *pf = vsi->back;
7974 struct i40e_hw *hw = &pf->hw;
7975 u16 i;
7976
7977 if (seed) {
7978 u32 *seed_dw = (u32 *)seed;
7979
7980 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7981 seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
7982 }
7983 if (lut) {
7984 u32 *lut_dw = (u32 *)lut;
7985
7986 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7987 return -EINVAL;
7988 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7989 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
7990 }
7991
7992 return 0;
7993}
7994
7995/**
7996 * i40e_config_rss - Configure RSS keys and lut
7997 * @vsi: Pointer to VSI structure
7998 * @seed: RSS hash seed
7999 * @lut: Lookup table
8000 * @lut_size: Lookup table size
8001 *
8002 * Returns 0 on success, negative on failure
8003 */
8004int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8005{
8006 struct i40e_pf *pf = vsi->back;
8007
8008 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8009 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8010 else
8011 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8012}
8013
8014/**
8015 * i40e_get_rss - Get RSS keys and lut
8016 * @vsi: Pointer to VSI structure
8017 * @seed: Buffer to store the keys
8018 * @lut: Buffer to store the lookup table entries
8019 * lut_size: Size of buffer to store the lookup table entries
8020 *
8021 * Returns 0 on success, negative on failure
8022 */
8023int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8024{
8025 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
8026}
8027
e69ff813
HZ		 8028/**
8029 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8030 * @pf: Pointer to board private structure
8031 * @lut: Lookup table
8032 * @rss_table_size: Lookup table size
8033 * @rss_size: Range of queue number for hashing
8034 */
8035static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8036 u16 rss_table_size, u16 rss_size)
8037{
8038 u16 i;
8039
8040 for (i = 0; i < rss_table_size; i++)
8041 lut[i] = i % rss_size;
8042}
8043
e25d00b8 8044/**
043dd650 8045 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8046 * @pf: board private structure
8047 **/
043dd650 8048static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8049{
8050 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8051 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8052 u8 *lut;
e25d00b8
ASJ		 8053 struct i40e_hw *hw = &pf->hw;
8054 u32 reg_val;
8055 u64 hena;
e69ff813 8056 int ret;
e25d00b8 8057
41c445ff
JB		 8058 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
8059 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
8060 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8061 hena |= i40e_pf_get_default_rss_hena(pf);
8062
41c445ff
JB		 8063 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
8064 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
8065
e25d00b8 8066 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 8067 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8068 reg_val = (pf->rss_table_size == 512) ?
8069 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8070 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 8071 wr32(hw, I40E_PFQF_CTL_0, reg_val);
8072
28c5869f
HZ		 8073 /* Determine the RSS size of the VSI */
8074 if (!vsi->rss_size)
acd65448
HZ		 8075 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8076 vsi->num_queue_pairs);
28c5869f 8077
e69ff813
HZ		 8078 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8079 if (!lut)
8080 return -ENOMEM;
8081
28c5869f
HZ		 8082 /* Use user configured lut if there is one, otherwise use default */
8083 if (vsi->rss_lut_user)
8084 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8085 else
8086 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8087
28c5869f
HZ		 8088 /* Use user configured hash key if there is one, otherwise
8089 * use default.
8090 */
8091 if (vsi->rss_hkey_user)
8092 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8093 else
8094 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8095 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8096 kfree(lut);
8097
8098 return ret;
41c445ff
JB		 8099}
8100
f8ff1464
ASJ		 8101/**
8102 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8103 * @pf: board private structure
8104 * @queue_count: the requested queue count for rss.
8105 *
8106 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8107 * count which may be different from the requested queue count.
8108 **/
8109int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8110{
9a3bd2f1
ASJ		 8111 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8112 int new_rss_size;
8113
f8ff1464
ASJ		 8114 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8115 return 0;
8116
9a3bd2f1 8117 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8118
9a3bd2f1
ASJ		 8119 if (queue_count != vsi->num_queue_pairs) {
8120 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8121 i40e_prep_for_reset(pf);
8122
acd65448 8123 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8124
8125 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8126
8127 /* Discard the user configured hash keys and lut, if less
8128 * queues are enabled.
8129 */
8130 if (queue_count < vsi->rss_size) {
8131 i40e_clear_rss_config_user(vsi);
8132 dev_dbg(&pf->pdev->dev,
8133 "discard user configured hash keys and lut\n");
8134 }
8135
8136 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8137 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8138 vsi->num_queue_pairs);
28c5869f 8139
043dd650 8140 i40e_pf_config_rss(pf);
f8ff1464 8141 }
e36b0b11
HZ		 8142 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8143 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8144 return pf->alloc_rss_size;
f8ff1464
ASJ		 8145}
8146
f4492db1
GR		 8147/**
8148 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8149 * @pf: board private structure
8150 **/
8151i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8152{
8153 i40e_status status;
8154 bool min_valid, max_valid;
8155 u32 max_bw, min_bw;
8156
8157 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8158 &min_valid, &max_valid);
8159
8160 if (!status) {
8161 if (min_valid)
8162 pf->npar_min_bw = min_bw;
8163 if (max_valid)
8164 pf->npar_max_bw = max_bw;
8165 }
8166
8167 return status;
8168}
8169
8170/**
8171 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8172 * @pf: board private structure
8173 **/
8174i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8175{
8176 struct i40e_aqc_configure_partition_bw_data bw_data;
8177 i40e_status status;
8178
b40c82e6 8179 /* Set the valid bit for this PF */
41a1d04b 8180 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8181 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8182 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8183
8184 /* Set the new bandwidths */
8185 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8186
8187 return status;
8188}
8189
8190/**
8191 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8192 * @pf: board private structure
8193 **/
8194i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8195{
8196 /* Commit temporary BW setting to permanent NVM image */
8197 enum i40e_admin_queue_err last_aq_status;
8198 i40e_status ret;
8199 u16 nvm_word;
8200
8201 if (pf->hw.partition_id != 1) {
8202 dev_info(&pf->pdev->dev,
8203 "Commit BW only works on partition 1! This is partition %d",
8204 pf->hw.partition_id);
8205 ret = I40E_NOT_SUPPORTED;
8206 goto bw_commit_out;
8207 }
8208
8209 /* Acquire NVM for read access */
8210 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8211 last_aq_status = pf->hw.aq.asq_last_status;
8212 if (ret) {
8213 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8214 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8215 i40e_stat_str(&pf->hw, ret),
8216 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8217 goto bw_commit_out;
8218 }
8219
8220 /* Read word 0x10 of NVM - SW compatibility word 1 */
8221 ret = i40e_aq_read_nvm(&pf->hw,
8222 I40E_SR_NVM_CONTROL_WORD,
8223 0x10, sizeof(nvm_word), &nvm_word,
8224 false, NULL);
8225 /* Save off last admin queue command status before releasing
8226 * the NVM
8227 */
8228 last_aq_status = pf->hw.aq.asq_last_status;
8229 i40e_release_nvm(&pf->hw);
8230 if (ret) {
f1c7e72e
SN		 8231 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8232 i40e_stat_str(&pf->hw, ret),
8233 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8234 goto bw_commit_out;
8235 }
8236
8237 /* Wait a bit for NVM release to complete */
8238 msleep(50);
8239
8240 /* Acquire NVM for write access */
8241 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8242 last_aq_status = pf->hw.aq.asq_last_status;
8243 if (ret) {
8244 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8245 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8246 i40e_stat_str(&pf->hw, ret),
8247 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8248 goto bw_commit_out;
8249 }
8250 /* Write it back out unchanged to initiate update NVM,
8251 * which will force a write of the shadow (alt) RAM to
8252 * the NVM - thus storing the bandwidth values permanently.
8253 */
8254 ret = i40e_aq_update_nvm(&pf->hw,
8255 I40E_SR_NVM_CONTROL_WORD,
8256 0x10, sizeof(nvm_word),
8257 &nvm_word, true, NULL);
8258 /* Save off last admin queue command status before releasing
8259 * the NVM
8260 */
8261 last_aq_status = pf->hw.aq.asq_last_status;
8262 i40e_release_nvm(&pf->hw);
8263 if (ret)
8264 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8265 "BW settings NOT SAVED, err %s aq_err %s\n",
8266 i40e_stat_str(&pf->hw, ret),
8267 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8268bw_commit_out:
8269
8270 return ret;
8271}
8272
41c445ff
JB		 8273/**
8274 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8275 * @pf: board private structure to initialize
8276 *
8277 * i40e_sw_init initializes the Adapter private data structure.
8278 * Fields are initialized based on PCI device information and
8279 * OS network device settings (MTU size).
8280 **/
8281static int i40e_sw_init(struct i40e_pf *pf)
8282{
8283 int err = 0;
8284 int size;
8285
8286 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8287 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 8288 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 8289 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8290 if (I40E_DEBUG_USER & debug)
8291 pf->hw.debug_mask = debug;
8292 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8293 I40E_DEFAULT_MSG_ENABLE);
8294 }
8295
8296 /* Set default capability flags */
8297 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8298 I40E_FLAG_MSI_ENABLED |
9ac77266 8299 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 8300 I40E_FLAG_MSIX_ENABLED;
8301
8302 if (iommu_present(&pci_bus_type))
8303 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8304 else
8305 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8306
ca99eb99
MW		 8307 /* Set default ITR */
8308 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8309 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8310
7134f9ce
JB		 8311 /* Depending on PF configurations, it is possible that the RSS
8312 * maximum might end up larger than the available queues
8313 */
41a1d04b 8314 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8315 pf->alloc_rss_size = 1;
5db4cb59 8316 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8317 pf->rss_size_max = min_t(int, pf->rss_size_max,
8318 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8319 if (pf->hw.func_caps.rss) {
8320 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8321 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8322 num_online_cpus());
41c445ff
JB		 8323 }
8324
2050bc65 8325 /* MFP mode enabled */
c78b953e 8326 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8327 pf->flags |= I40E_FLAG_MFP_ENABLED;
8328 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8329 if (i40e_get_npar_bw_setting(pf))
8330 dev_warn(&pf->pdev->dev,
8331 "Could not get NPAR bw settings\n");
8332 else
8333 dev_info(&pf->pdev->dev,
8334 "Min BW = %8.8x, Max BW = %8.8x\n",
8335 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8336 }
8337
cbf61325
ASJ		 8338 /* FW/NVM is not yet fixed in this regard */
8339 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8340 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8341 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8342 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8343 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8344 pf->hw.num_partitions > 1)
cbf61325 8345 dev_info(&pf->pdev->dev,
0b67584f 8346 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8347 else
8348 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8349 pf->fdir_pf_filter_count =
8350 pf->hw.func_caps.fd_filters_guaranteed;
8351 pf->hw.fdir_shared_filter_count =
8352 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8353 }
8354
8355 if (pf->hw.func_caps.vmdq) {
41c445ff 8356 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8357 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8358 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8359 }
8360
38e00438 8361#ifdef I40E_FCOE
21364bcf 8362 i40e_init_pf_fcoe(pf);
38e00438
VD		 8363
8364#endif /* I40E_FCOE */
41c445ff 8365#ifdef CONFIG_PCI_IOV
ba252f13 8366 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8367 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8368 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8369 pf->num_req_vfs = min_t(int,
8370 pf->hw.func_caps.num_vfs,
8371 I40E_MAX_VF_COUNT);
8372 }
8373#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8374 if (pf->hw.mac.type == I40E_MAC_X722) {
8375 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8376 I40E_FLAG_128_QP_RSS_CAPABLE |
8377 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8378 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8379 I40E_FLAG_WB_ON_ITR_CAPABLE |
8380 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
8381 }
41c445ff
JB		 8382 pf->eeprom_version = 0xDEAD;
8383 pf->lan_veb = I40E_NO_VEB;
8384 pf->lan_vsi = I40E_NO_VSI;
8385
d1a8d275
ASJ		 8386 /* By default FW has this off for performance reasons */
8387 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8388
41c445ff
JB		 8389 /* set up queue assignment tracking */
8390 size = sizeof(struct i40e_lump_tracking)
8391 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8392 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8393 if (!pf->qp_pile) {
8394 err = -ENOMEM;
8395 goto sw_init_done;
8396 }
8397 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8398 pf->qp_pile->search_hint = 0;
8399
327fe04b
ASJ		 8400 pf->tx_timeout_recovery_level = 1;
8401
41c445ff
JB		 8402 mutex_init(&pf->switch_mutex);
8403
c668a12c
GR		 8404 /* If NPAR is enabled nudge the Tx scheduler */
8405 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8406 i40e_set_npar_bw_setting(pf);
8407
41c445ff
JB		 8408sw_init_done:
8409 return err;
8410}
8411
7c3c288b
ASJ		 8412/**
8413 * i40e_set_ntuple - set the ntuple feature flag and take action
8414 * @pf: board private structure to initialize
8415 * @features: the feature set that the stack is suggesting
8416 *
8417 * returns a bool to indicate if reset needs to happen
8418 **/
8419bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8420{
8421 bool need_reset = false;
8422
8423 /* Check if Flow Director n-tuple support was enabled or disabled. If
8424 * the state changed, we need to reset.
8425 */
8426 if (features & NETIF_F_NTUPLE) {
8427 /* Enable filters and mark for reset */
8428 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8429 need_reset = true;
8430 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8431 } else {
8432 /* turn off filters, mark for reset and clear SW filter list */
8433 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8434 need_reset = true;
8435 i40e_fdir_filter_exit(pf);
8436 }
8437 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8438 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8439 /* reset fd counters */
8440 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8441 pf->fdir_pf_active_filters = 0;
8442 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8443 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8444 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8445 /* if ATR was auto disabled it can be re-enabled. */
8446 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8447 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8448 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8449 }
8450 return need_reset;
8451}
8452
41c445ff
JB		 8453/**
8454 * i40e_set_features - set the netdev feature flags
8455 * @netdev: ptr to the netdev being adjusted
8456 * @features: the feature set that the stack is suggesting
8457 **/
8458static int i40e_set_features(struct net_device *netdev,
8459 netdev_features_t features)
8460{
8461 struct i40e_netdev_priv *np = netdev_priv(netdev);
8462 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8463 struct i40e_pf *pf = vsi->back;
8464 bool need_reset;
41c445ff
JB		 8465
8466 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8467 i40e_vlan_stripping_enable(vsi);
8468 else
8469 i40e_vlan_stripping_disable(vsi);
8470
7c3c288b
ASJ		 8471 need_reset = i40e_set_ntuple(pf, features);
8472
8473 if (need_reset)
41a1d04b 8474 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8475
41c445ff
JB		 8476 return 0;
8477}
8478
6633d381 8479#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 8480/**
8481 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8482 * @pf: board private structure
8483 * @port: The UDP port to look up
8484 *
8485 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8486 **/
8487static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8488{
8489 u8 i;
8490
8491 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8492 if (pf->vxlan_ports[i] == port)
8493 return i;
8494 }
8495
8496 return i;
8497}
8498
8499/**
8500 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8501 * @netdev: This physical port's netdev
8502 * @sa_family: Socket Family that VXLAN is notifying us about
8503 * @port: New UDP port number that VXLAN started listening to
8504 **/
8505static void i40e_add_vxlan_port(struct net_device *netdev,
8506 sa_family_t sa_family, __be16 port)
8507{
8508 struct i40e_netdev_priv *np = netdev_priv(netdev);
8509 struct i40e_vsi *vsi = np->vsi;
8510 struct i40e_pf *pf = vsi->back;
8511 u8 next_idx;
8512 u8 idx;
8513
8514 if (sa_family == AF_INET6)
8515 return;
8516
8517 idx = i40e_get_vxlan_port_idx(pf, port);
8518
8519 /* Check if port already exists */
8520 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8521 netdev_info(netdev, "vxlan port %d already offloaded\n",
8522 ntohs(port));
a1c9a9d9
JK		 8523 return;
8524 }
8525
8526 /* Now check if there is space to add the new port */
8527 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8528
8529 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8530 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8531 ntohs(port));
8532 return;
8533 }
8534
8535 /* New port: add it and mark its index in the bitmap */
8536 pf->vxlan_ports[next_idx] = port;
41a1d04b 8537 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8538 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8539}
8540
8541/**
8542 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8543 * @netdev: This physical port's netdev
8544 * @sa_family: Socket Family that VXLAN is notifying us about
8545 * @port: UDP port number that VXLAN stopped listening to
8546 **/
8547static void i40e_del_vxlan_port(struct net_device *netdev,
8548 sa_family_t sa_family, __be16 port)
8549{
8550 struct i40e_netdev_priv *np = netdev_priv(netdev);
8551 struct i40e_vsi *vsi = np->vsi;
8552 struct i40e_pf *pf = vsi->back;
8553 u8 idx;
8554
8555 if (sa_family == AF_INET6)
8556 return;
8557
8558 idx = i40e_get_vxlan_port_idx(pf, port);
8559
8560 /* Check if port already exists */
8561 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8562 /* if port exists, set it to 0 (mark for deletion)
8563 * and make it pending
8564 */
8565 pf->vxlan_ports[idx] = 0;
41a1d04b 8566 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8567 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8568 } else {
c22c06c8 8569 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8570 ntohs(port));
8571 }
8572}
8573
8574#endif
1f224ad2 8575static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8576 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8577{
8578 struct i40e_netdev_priv *np = netdev_priv(netdev);
8579 struct i40e_pf *pf = np->vsi->back;
8580 struct i40e_hw *hw = &pf->hw;
8581
8582 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8583 return -EOPNOTSUPP;
8584
8585 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8586 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8587
8588 return 0;
8589}
8590
2f90ade6
JB		 8591/**
8592 * i40e_ndo_fdb_add - add an entry to the hardware database
8593 * @ndm: the input from the stack
8594 * @tb: pointer to array of nladdr (unused)
8595 * @dev: the net device pointer
8596 * @addr: the MAC address entry being added
8597 * @flags: instructions from stack about fdb operation
8598 */
4ba0dea5
GR		 8599static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8600 struct net_device *dev,
f6f6424b 8601 const unsigned char *addr, u16 vid,
4ba0dea5 8602 u16 flags)
4ba0dea5
GR		 8603{
8604 struct i40e_netdev_priv *np = netdev_priv(dev);
8605 struct i40e_pf *pf = np->vsi->back;
8606 int err = 0;
8607
8608 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8609 return -EOPNOTSUPP;
8610
65891fea
OG		 8611 if (vid) {
8612 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8613 return -EINVAL;
8614 }
8615
4ba0dea5
GR		 8616 /* Hardware does not support aging addresses so if a
8617 * ndm_state is given only allow permanent addresses
8618 */
8619 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8620 netdev_info(dev, "FDB only supports static addresses\n");
8621 return -EINVAL;
8622 }
8623
8624 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8625 err = dev_uc_add_excl(dev, addr);
8626 else if (is_multicast_ether_addr(addr))
8627 err = dev_mc_add_excl(dev, addr);
8628 else
8629 err = -EINVAL;
8630
8631 /* Only return duplicate errors if NLM_F_EXCL is set */
8632 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8633 err = 0;
8634
8635 return err;
8636}
8637
51616018
NP		 8638/**
8639 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8640 * @dev: the netdev being configured
8641 * @nlh: RTNL message
8642 *
8643 * Inserts a new hardware bridge if not already created and
8644 * enables the bridging mode requested (VEB or VEPA). If the
8645 * hardware bridge has already been inserted and the request
8646 * is to change the mode then that requires a PF reset to
8647 * allow rebuild of the components with required hardware
8648 * bridge mode enabled.
8649 **/
8650static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8651 struct nlmsghdr *nlh,
8652 u16 flags)
51616018
NP		 8653{
8654 struct i40e_netdev_priv *np = netdev_priv(dev);
8655 struct i40e_vsi *vsi = np->vsi;
8656 struct i40e_pf *pf = vsi->back;
8657 struct i40e_veb *veb = NULL;
8658 struct nlattr *attr, *br_spec;
8659 int i, rem;
8660
8661 /* Only for PF VSI for now */
8662 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8663 return -EOPNOTSUPP;
8664
8665 /* Find the HW bridge for PF VSI */
8666 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8667 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8668 veb = pf->veb[i];
8669 }
8670
8671 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8672
8673 nla_for_each_nested(attr, br_spec, rem) {
8674 __u16 mode;
8675
8676 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8677 continue;
8678
8679 mode = nla_get_u16(attr);
8680 if ((mode != BRIDGE_MODE_VEPA) &&
8681 (mode != BRIDGE_MODE_VEB))
8682 return -EINVAL;
8683
8684 /* Insert a new HW bridge */
8685 if (!veb) {
8686 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8687 vsi->tc_config.enabled_tc);
8688 if (veb) {
8689 veb->bridge_mode = mode;
8690 i40e_config_bridge_mode(veb);
8691 } else {
8692 /* No Bridge HW offload available */
8693 return -ENOENT;
8694 }
8695 break;
8696 } else if (mode != veb->bridge_mode) {
8697 /* Existing HW bridge but different mode needs reset */
8698 veb->bridge_mode = mode;
fc60861e
ASJ		 8699 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8700 if (mode == BRIDGE_MODE_VEB)
8701 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8702 else
8703 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8704 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8705 break;
8706 }
8707 }
8708
8709 return 0;
8710}
8711
8712/**
8713 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8714 * @skb: skb buff
8715 * @pid: process id
8716 * @seq: RTNL message seq #
8717 * @dev: the netdev being configured
8718 * @filter_mask: unused
d4b2f9fe 8719 * @nlflags: netlink flags passed in
51616018
NP		 8720 *
8721 * Return the mode in which the hardware bridge is operating in
8722 * i.e VEB or VEPA.
8723 **/
51616018
NP		 8724static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8725 struct net_device *dev,
9f4ffc44
CW		 8726 u32 __always_unused filter_mask,
8727 int nlflags)
51616018
NP		 8728{
8729 struct i40e_netdev_priv *np = netdev_priv(dev);
8730 struct i40e_vsi *vsi = np->vsi;
8731 struct i40e_pf *pf = vsi->back;
8732 struct i40e_veb *veb = NULL;
8733 int i;
8734
8735 /* Only for PF VSI for now */
8736 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8737 return -EOPNOTSUPP;
8738
8739 /* Find the HW bridge for the PF VSI */
8740 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8741 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8742 veb = pf->veb[i];
8743 }
8744
8745 if (!veb)
8746 return 0;
8747
46c264da 8748 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8749 nlflags, 0, 0, filter_mask, NULL);
51616018 8750}
51616018 8751
f44a75e2
JS		 8752#define I40E_MAX_TUNNEL_HDR_LEN 80
8753/**
8754 * i40e_features_check - Validate encapsulated packet conforms to limits
8755 * @skb: skb buff
2bc11c63 8756 * @dev: This physical port's netdev
f44a75e2
JS		 8757 * @features: Offload features that the stack believes apply
8758 **/
8759static netdev_features_t i40e_features_check(struct sk_buff *skb,
8760 struct net_device *dev,
8761 netdev_features_t features)
8762{
8763 if (skb->encapsulation &&
8764 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8765 I40E_MAX_TUNNEL_HDR_LEN))
8766 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8767
8768 return features;
8769}
8770
37a2973a 8771static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8772 .ndo_open = i40e_open,
8773 .ndo_stop = i40e_close,
8774 .ndo_start_xmit = i40e_lan_xmit_frame,
8775 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8776 .ndo_set_rx_mode = i40e_set_rx_mode,
8777 .ndo_validate_addr = eth_validate_addr,
8778 .ndo_set_mac_address = i40e_set_mac,
8779 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8780 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8781 .ndo_tx_timeout = i40e_tx_timeout,
8782 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8783 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8784#ifdef CONFIG_NET_POLL_CONTROLLER
8785 .ndo_poll_controller = i40e_netpoll,
8786#endif
8787 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8788#ifdef I40E_FCOE
8789 .ndo_fcoe_enable = i40e_fcoe_enable,
8790 .ndo_fcoe_disable = i40e_fcoe_disable,
8791#endif
41c445ff
JB		 8792 .ndo_set_features = i40e_set_features,
8793 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8794 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8795 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8796 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8797 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8798 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
6633d381 8799#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 8800 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8801 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8802#endif
1f224ad2 8803 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8804 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8805 .ndo_features_check = i40e_features_check,
51616018
NP		 8806 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8807 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8808};
8809
8810/**
8811 * i40e_config_netdev - Setup the netdev flags
8812 * @vsi: the VSI being configured
8813 *
8814 * Returns 0 on success, negative value on failure
8815 **/
8816static int i40e_config_netdev(struct i40e_vsi *vsi)
8817{
1a10370a 8818 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8819 struct i40e_pf *pf = vsi->back;
8820 struct i40e_hw *hw = &pf->hw;
8821 struct i40e_netdev_priv *np;
8822 struct net_device *netdev;
8823 u8 mac_addr[ETH_ALEN];
8824 int etherdev_size;
8825
8826 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8827 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8828 if (!netdev)
8829 return -ENOMEM;
8830
8831 vsi->netdev = netdev;
8832 np = netdev_priv(netdev);
8833 np->vsi = vsi;
8834
d70e941b 8835 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8836 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8837 NETIF_F_GSO_GRE |
d70e941b 8838 NETIF_F_TSO;
41c445ff
JB		 8839
8840 netdev->features = NETIF_F_SG |
8841 NETIF_F_IP_CSUM |
8842 NETIF_F_SCTP_CSUM |
8843 NETIF_F_HIGHDMA |
8844 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8845 NETIF_F_GSO_GRE |
41c445ff
JB		 8846 NETIF_F_HW_VLAN_CTAG_TX |
8847 NETIF_F_HW_VLAN_CTAG_RX |
8848 NETIF_F_HW_VLAN_CTAG_FILTER |
8849 NETIF_F_IPV6_CSUM |
8850 NETIF_F_TSO |
059dab69 8851 NETIF_F_TSO_ECN |
41c445ff
JB		 8852 NETIF_F_TSO6 |
8853 NETIF_F_RXCSUM |
8854 NETIF_F_RXHASH |
8855 0;
8856
2e86a0b6
ASJ		 8857 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8858 netdev->features |= NETIF_F_NTUPLE;
8859
41c445ff
JB		 8860 /* copy netdev features into list of user selectable features */
8861 netdev->hw_features |= netdev->features;
8862
8863 if (vsi->type == I40E_VSI_MAIN) {
8864 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8865 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8866 /* The following steps are necessary to prevent reception
8867 * of tagged packets - some older NVM configurations load a
8868 * default a MAC-VLAN filter that accepts any tagged packet
8869 * which must be replaced by a normal filter.
8c27d42e 8870 */
21659035
KP		 8871 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
8872 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 8873 i40e_add_filter(vsi, mac_addr,
8874 I40E_VLAN_ANY, false, true);
21659035
KP		 8875 spin_unlock_bh(&vsi->mac_filter_list_lock);
8876 }
41c445ff
JB		 8877 } else {
8878 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8879 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8880 pf->vsi[pf->lan_vsi]->netdev->name);
8881 random_ether_addr(mac_addr);
21659035
KP		 8882
8883 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 8884 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 8885 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8886 }
21659035
KP		 8887
8888 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 8889 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 8890 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8891
9a173901
GR		 8892 ether_addr_copy(netdev->dev_addr, mac_addr);
8893 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8894 /* vlan gets same features (except vlan offload)
8895 * after any tweaks for specific VSI types
8896 */
8897 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8898 NETIF_F_HW_VLAN_CTAG_RX |
8899 NETIF_F_HW_VLAN_CTAG_FILTER);
8900 netdev->priv_flags |= IFF_UNICAST_FLT;
8901 netdev->priv_flags |= IFF_SUPP_NOFCS;
8902 /* Setup netdev TC information */
8903 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8904
8905 netdev->netdev_ops = &i40e_netdev_ops;
8906 netdev->watchdog_timeo = 5 * HZ;
8907 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8908#ifdef I40E_FCOE
8909 i40e_fcoe_config_netdev(netdev, vsi);
8910#endif
41c445ff
JB		 8911
8912 return 0;
8913}
8914
8915/**
8916 * i40e_vsi_delete - Delete a VSI from the switch
8917 * @vsi: the VSI being removed
8918 *
8919 * Returns 0 on success, negative value on failure
8920 **/
8921static void i40e_vsi_delete(struct i40e_vsi *vsi)
8922{
8923 /* remove default VSI is not allowed */
8924 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8925 return;
8926
41c445ff 8927 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8928}
8929
51616018
NP		 8930/**
8931 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8932 * @vsi: the VSI being queried
8933 *
8934 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8935 **/
8936int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8937{
8938 struct i40e_veb *veb;
8939 struct i40e_pf *pf = vsi->back;
8940
8941 /* Uplink is not a bridge so default to VEB */
8942 if (vsi->veb_idx == I40E_NO_VEB)
8943 return 1;
8944
8945 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 8946 if (!veb) {
8947 dev_info(&pf->pdev->dev,
8948 "There is no veb associated with the bridge\n");
8949 return -ENOENT;
8950 }
8951
51616018 8952 /* Uplink is a bridge in VEPA mode */
09603eaa 8953 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 8954 return 0;
09603eaa
AA		 8955 } else {
8956 /* Uplink is a bridge in VEB mode */
8957 return 1;
8958 }
51616018 8959
09603eaa
AA		 8960 /* VEPA is now default bridge, so return 0 */
8961 return 0;
51616018
NP		 8962}
8963
41c445ff
JB		 8964/**
8965 * i40e_add_vsi - Add a VSI to the switch
8966 * @vsi: the VSI being configured
8967 *
8968 * This initializes a VSI context depending on the VSI type to be added and
8969 * passes it down to the add_vsi aq command.
8970 **/
8971static int i40e_add_vsi(struct i40e_vsi *vsi)
8972{
8973 int ret = -ENODEV;
21659035
KP		 8974 u8 laa_macaddr[ETH_ALEN];
8975 bool found_laa_mac_filter = false;
41c445ff
JB		 8976 struct i40e_pf *pf = vsi->back;
8977 struct i40e_hw *hw = &pf->hw;
8978 struct i40e_vsi_context ctxt;
21659035
KP		 8979 struct i40e_mac_filter *f, *ftmp;
8980
41c445ff
JB		 8981 u8 enabled_tc = 0x1; /* TC0 enabled */
8982 int f_count = 0;
8983
8984 memset(&ctxt, 0, sizeof(ctxt));
8985 switch (vsi->type) {
8986 case I40E_VSI_MAIN:
8987 /* The PF's main VSI is already setup as part of the
8988 * device initialization, so we'll not bother with
8989 * the add_vsi call, but we will retrieve the current
8990 * VSI context.
8991 */
8992 ctxt.seid = pf->main_vsi_seid;
8993 ctxt.pf_num = pf->hw.pf_id;
8994 ctxt.vf_num = 0;
8995 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8996 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8997 if (ret) {
8998 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8999 "couldn't get PF vsi config, err %s aq_err %s\n",
9000 i40e_stat_str(&pf->hw, ret),
9001 i40e_aq_str(&pf->hw,
9002 pf->hw.aq.asq_last_status));
41c445ff
JB		 9003 return -ENOENT;
9004 }
1a2f6248 9005 vsi->info = ctxt.info;
41c445ff
JB		 9006 vsi->info.valid_sections = 0;
9007
9008 vsi->seid = ctxt.seid;
9009 vsi->id = ctxt.vsi_number;
9010
9011 enabled_tc = i40e_pf_get_tc_map(pf);
9012
9013 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9014 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9015 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9016 memset(&ctxt, 0, sizeof(ctxt));
9017 ctxt.seid = pf->main_vsi_seid;
9018 ctxt.pf_num = pf->hw.pf_id;
9019 ctxt.vf_num = 0;
9020 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9021 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9022 if (ret) {
9023 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9024 "update vsi failed, err %s aq_err %s\n",
9025 i40e_stat_str(&pf->hw, ret),
9026 i40e_aq_str(&pf->hw,
9027 pf->hw.aq.asq_last_status));
41c445ff
JB		 9028 ret = -ENOENT;
9029 goto err;
9030 }
9031 /* update the local VSI info queue map */
9032 i40e_vsi_update_queue_map(vsi, &ctxt);
9033 vsi->info.valid_sections = 0;
9034 } else {
9035 /* Default/Main VSI is only enabled for TC0
9036 * reconfigure it to enable all TCs that are
9037 * available on the port in SFP mode.
63d7e5a4
NP		 9038 * For MFP case the iSCSI PF would use this
9039 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9040 */
9041 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9042 if (ret) {
9043 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9044 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9045 enabled_tc,
9046 i40e_stat_str(&pf->hw, ret),
9047 i40e_aq_str(&pf->hw,
9048 pf->hw.aq.asq_last_status));
41c445ff
JB		 9049 ret = -ENOENT;
9050 }
9051 }
9052 break;
9053
9054 case I40E_VSI_FDIR:
cbf61325
ASJ		 9055 ctxt.pf_num = hw->pf_id;
9056 ctxt.vf_num = 0;
9057 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9058 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9059 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9060 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9061 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9062 ctxt.info.valid_sections |=
fc60861e 9063 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9064 ctxt.info.switch_id =
fc60861e 9065 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9066 }
41c445ff 9067 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9068 break;
9069
9070 case I40E_VSI_VMDQ2:
9071 ctxt.pf_num = hw->pf_id;
9072 ctxt.vf_num = 0;
9073 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9074 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9075 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9076
41c445ff
JB		 9077 /* This VSI is connected to VEB so the switch_id
9078 * should be set to zero by default.
9079 */
51616018
NP		 9080 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9081 ctxt.info.valid_sections |=
9082 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9083 ctxt.info.switch_id =
9084 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9085 }
41c445ff
JB		 9086
9087 /* Setup the VSI tx/rx queue map for TC0 only for now */
9088 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9089 break;
9090
9091 case I40E_VSI_SRIOV:
9092 ctxt.pf_num = hw->pf_id;
9093 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9094 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9095 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9096 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9097
41c445ff
JB		 9098 /* This VSI is connected to VEB so the switch_id
9099 * should be set to zero by default.
9100 */
51616018
NP		 9101 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9102 ctxt.info.valid_sections |=
9103 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9104 ctxt.info.switch_id =
9105 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9106 }
41c445ff
JB		 9107
9108 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9109 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9110 if (pf->vf[vsi->vf_id].spoofchk) {
9111 ctxt.info.valid_sections |=
9112 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9113 ctxt.info.sec_flags |=
9114 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9115 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9116 }
41c445ff
JB		 9117 /* Setup the VSI tx/rx queue map for TC0 only for now */
9118 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9119 break;
9120
38e00438
VD		 9121#ifdef I40E_FCOE
9122 case I40E_VSI_FCOE:
9123 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9124 if (ret) {
9125 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9126 return ret;
9127 }
9128 break;
9129
9130#endif /* I40E_FCOE */
41c445ff
JB		 9131 default:
9132 return -ENODEV;
9133 }
9134
9135 if (vsi->type != I40E_VSI_MAIN) {
9136 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9137 if (ret) {
9138 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9139 "add vsi failed, err %s aq_err %s\n",
9140 i40e_stat_str(&pf->hw, ret),
9141 i40e_aq_str(&pf->hw,
9142 pf->hw.aq.asq_last_status));
41c445ff
JB		 9143 ret = -ENOENT;
9144 goto err;
9145 }
1a2f6248 9146 vsi->info = ctxt.info;
41c445ff
JB		 9147 vsi->info.valid_sections = 0;
9148 vsi->seid = ctxt.seid;
9149 vsi->id = ctxt.vsi_number;
9150 }
9151
21659035 9152 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9153 /* If macvlan filters already exist, force them to get loaded */
9154 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9155 f->changed = true;
9156 f_count++;
6252c7e4 9157
21659035 9158 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9159 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9160 ether_addr_copy(laa_macaddr, f->macaddr);
9161 found_laa_mac_filter = true;
9162 }
9163 }
9164 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9165
21659035
KP		 9166 if (found_laa_mac_filter) {
9167 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9168
21659035
KP		 9169 memset(&element, 0, sizeof(element));
9170 ether_addr_copy(element.mac_addr, laa_macaddr);
9171 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9172 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9173 &element, 1, NULL);
9174 if (ret) {
9175 /* some older FW has a different default */
9176 element.flags |=
9177 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9178 i40e_aq_remove_macvlan(hw, vsi->seid,
9179 &element, 1, NULL);
6252c7e4 9180 }
21659035
KP		 9181
9182 i40e_aq_mac_address_write(hw,
9183 I40E_AQC_WRITE_TYPE_LAA_WOL,
9184 laa_macaddr, NULL);
41c445ff 9185 }
21659035 9186
41c445ff
JB		 9187 if (f_count) {
9188 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9189 pf->flags |= I40E_FLAG_FILTER_SYNC;
9190 }
9191
9192 /* Update VSI BW information */
9193 ret = i40e_vsi_get_bw_info(vsi);
9194 if (ret) {
9195 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9196 "couldn't get vsi bw info, err %s aq_err %s\n",
9197 i40e_stat_str(&pf->hw, ret),
9198 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9199 /* VSI is already added so not tearing that up */
9200 ret = 0;
9201 }
9202
9203err:
9204 return ret;
9205}
9206
9207/**
9208 * i40e_vsi_release - Delete a VSI and free its resources
9209 * @vsi: the VSI being removed
9210 *
9211 * Returns 0 on success or < 0 on error
9212 **/
9213int i40e_vsi_release(struct i40e_vsi *vsi)
9214{
9215 struct i40e_mac_filter *f, *ftmp;
9216 struct i40e_veb *veb = NULL;
9217 struct i40e_pf *pf;
9218 u16 uplink_seid;
9219 int i, n;
9220
9221 pf = vsi->back;
9222
9223 /* release of a VEB-owner or last VSI is not allowed */
9224 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9225 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9226 vsi->seid, vsi->uplink_seid);
9227 return -ENODEV;
9228 }
9229 if (vsi == pf->vsi[pf->lan_vsi] &&
9230 !test_bit(__I40E_DOWN, &pf->state)) {
9231 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9232 return -ENODEV;
9233 }
9234
9235 uplink_seid = vsi->uplink_seid;
9236 if (vsi->type != I40E_VSI_SRIOV) {
9237 if (vsi->netdev_registered) {
9238 vsi->netdev_registered = false;
9239 if (vsi->netdev) {
9240 /* results in a call to i40e_close() */
9241 unregister_netdev(vsi->netdev);
41c445ff
JB		 9242 }
9243 } else {
90ef8d47 9244 i40e_vsi_close(vsi);
41c445ff
JB		 9245 }
9246 i40e_vsi_disable_irq(vsi);
9247 }
9248
21659035 9249 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9250 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9251 i40e_del_filter(vsi, f->macaddr, f->vlan,
9252 f->is_vf, f->is_netdev);
21659035
KP		 9253 spin_unlock_bh(&vsi->mac_filter_list_lock);
9254
17652c63 9255 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9256
9257 i40e_vsi_delete(vsi);
9258 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9259 if (vsi->netdev) {
9260 free_netdev(vsi->netdev);
9261 vsi->netdev = NULL;
9262 }
41c445ff
JB		 9263 i40e_vsi_clear_rings(vsi);
9264 i40e_vsi_clear(vsi);
9265
9266 /* If this was the last thing on the VEB, except for the
9267 * controlling VSI, remove the VEB, which puts the controlling
9268 * VSI onto the next level down in the switch.
9269 *
9270 * Well, okay, there's one more exception here: don't remove
9271 * the orphan VEBs yet. We'll wait for an explicit remove request
9272 * from up the network stack.
9273 */
505682cd 9274 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9275 if (pf->vsi[i] &&
9276 pf->vsi[i]->uplink_seid == uplink_seid &&
9277 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9278 n++; /* count the VSIs */
9279 }
9280 }
9281 for (i = 0; i < I40E_MAX_VEB; i++) {
9282 if (!pf->veb[i])
9283 continue;
9284 if (pf->veb[i]->uplink_seid == uplink_seid)
9285 n++; /* count the VEBs */
9286 if (pf->veb[i]->seid == uplink_seid)
9287 veb = pf->veb[i];
9288 }
9289 if (n == 0 && veb && veb->uplink_seid != 0)
9290 i40e_veb_release(veb);
9291
9292 return 0;
9293}
9294
9295/**
9296 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9297 * @vsi: ptr to the VSI
9298 *
9299 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9300 * corresponding SW VSI structure and initializes num_queue_pairs for the
9301 * newly allocated VSI.
9302 *
9303 * Returns 0 on success or negative on failure
9304 **/
9305static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9306{
9307 int ret = -ENOENT;
9308 struct i40e_pf *pf = vsi->back;
9309
493fb300 9310 if (vsi->q_vectors[0]) {
41c445ff
JB		 9311 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9312 vsi->seid);
9313 return -EEXIST;
9314 }
9315
9316 if (vsi->base_vector) {
f29eaa3d 9317 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9318 vsi->seid, vsi->base_vector);
9319 return -EEXIST;
9320 }
9321
90e04070 9322 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9323 if (ret) {
9324 dev_info(&pf->pdev->dev,
9325 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9326 vsi->num_q_vectors, vsi->seid, ret);
9327 vsi->num_q_vectors = 0;
9328 goto vector_setup_out;
9329 }
9330
26cdc443
ASJ		 9331 /* In Legacy mode, we do not have to get any other vector since we
9332 * piggyback on the misc/ICR0 for queue interrupts.
9333 */
9334 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9335 return ret;
958a3e3b
SN		 9336 if (vsi->num_q_vectors)
9337 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9338 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9339 if (vsi->base_vector < 0) {
9340 dev_info(&pf->pdev->dev,
049a2be8
SN		 9341 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9342 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9343 i40e_vsi_free_q_vectors(vsi);
9344 ret = -ENOENT;
9345 goto vector_setup_out;
9346 }
9347
9348vector_setup_out:
9349 return ret;
9350}
9351
bc7d338f
ASJ		 9352/**
9353 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9354 * @vsi: pointer to the vsi.
9355 *
9356 * This re-allocates a vsi's queue resources.
9357 *
9358 * Returns pointer to the successfully allocated and configured VSI sw struct
9359 * on success, otherwise returns NULL on failure.
9360 **/
9361static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9362{
9363 struct i40e_pf *pf = vsi->back;
9364 u8 enabled_tc;
9365 int ret;
9366
9367 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9368 i40e_vsi_clear_rings(vsi);
9369
9370 i40e_vsi_free_arrays(vsi, false);
9371 i40e_set_num_rings_in_vsi(vsi);
9372 ret = i40e_vsi_alloc_arrays(vsi, false);
9373 if (ret)
9374 goto err_vsi;
9375
9376 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9377 if (ret < 0) {
049a2be8 9378 dev_info(&pf->pdev->dev,
f1c7e72e 9379 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9380 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9381 goto err_vsi;
9382 }
9383 vsi->base_queue = ret;
9384
9385 /* Update the FW view of the VSI. Force a reset of TC and queue
9386 * layout configurations.
9387 */
9388 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9389 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9390 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9391 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9392
9393 /* assign it some queues */
9394 ret = i40e_alloc_rings(vsi);
9395 if (ret)
9396 goto err_rings;
9397
9398 /* map all of the rings to the q_vectors */
9399 i40e_vsi_map_rings_to_vectors(vsi);
9400 return vsi;
9401
9402err_rings:
9403 i40e_vsi_free_q_vectors(vsi);
9404 if (vsi->netdev_registered) {
9405 vsi->netdev_registered = false;
9406 unregister_netdev(vsi->netdev);
9407 free_netdev(vsi->netdev);
9408 vsi->netdev = NULL;
9409 }
9410 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9411err_vsi:
9412 i40e_vsi_clear(vsi);
9413 return NULL;
9414}
9415
41c445ff
JB		 9416/**
9417 * i40e_vsi_setup - Set up a VSI by a given type
9418 * @pf: board private structure
9419 * @type: VSI type
9420 * @uplink_seid: the switch element to link to
9421 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9422 *
9423 * This allocates the sw VSI structure and its queue resources, then add a VSI
9424 * to the identified VEB.
9425 *
9426 * Returns pointer to the successfully allocated and configure VSI sw struct on
9427 * success, otherwise returns NULL on failure.
9428 **/
9429struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9430 u16 uplink_seid, u32 param1)
9431{
9432 struct i40e_vsi *vsi = NULL;
9433 struct i40e_veb *veb = NULL;
9434 int ret, i;
9435 int v_idx;
9436
9437 /* The requested uplink_seid must be either
9438 * - the PF's port seid
9439 * no VEB is needed because this is the PF
9440 * or this is a Flow Director special case VSI
9441 * - seid of an existing VEB
9442 * - seid of a VSI that owns an existing VEB
9443 * - seid of a VSI that doesn't own a VEB
9444 * a new VEB is created and the VSI becomes the owner
9445 * - seid of the PF VSI, which is what creates the first VEB
9446 * this is a special case of the previous
9447 *
9448 * Find which uplink_seid we were given and create a new VEB if needed
9449 */
9450 for (i = 0; i < I40E_MAX_VEB; i++) {
9451 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9452 veb = pf->veb[i];
9453 break;
9454 }
9455 }
9456
9457 if (!veb && uplink_seid != pf->mac_seid) {
9458
505682cd 9459 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9460 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9461 vsi = pf->vsi[i];
9462 break;
9463 }
9464 }
9465 if (!vsi) {
9466 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9467 uplink_seid);
9468 return NULL;
9469 }
9470
9471 if (vsi->uplink_seid == pf->mac_seid)
9472 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9473 vsi->tc_config.enabled_tc);
9474 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9475 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9476 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9477 if (veb) {
9478 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9479 dev_info(&vsi->back->pdev->dev,
fb43201f 9480 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9481 return NULL;
9482 }
fa11cb3d
ASJ		 9483 /* We come up by default in VEPA mode if SRIOV is not
9484 * already enabled, in which case we can't force VEPA
9485 * mode.
9486 */
9487 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9488 veb->bridge_mode = BRIDGE_MODE_VEPA;
9489 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9490 }
51616018 9491 i40e_config_bridge_mode(veb);
79c21a82 9492 }
41c445ff
JB		 9493 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9494 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9495 veb = pf->veb[i];
9496 }
9497 if (!veb) {
9498 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9499 return NULL;
9500 }
9501
9502 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9503 uplink_seid = veb->seid;
9504 }
9505
9506 /* get vsi sw struct */
9507 v_idx = i40e_vsi_mem_alloc(pf, type);
9508 if (v_idx < 0)
9509 goto err_alloc;
9510 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9511 if (!vsi)
9512 goto err_alloc;
41c445ff
JB		 9513 vsi->type = type;
9514 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9515
9516 if (type == I40E_VSI_MAIN)
9517 pf->lan_vsi = v_idx;
9518 else if (type == I40E_VSI_SRIOV)
9519 vsi->vf_id = param1;
9520 /* assign it some queues */
cbf61325
ASJ		 9521 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9522 vsi->idx);
41c445ff 9523 if (ret < 0) {
049a2be8
SN		 9524 dev_info(&pf->pdev->dev,
9525 "failed to get tracking for %d queues for VSI %d err=%d\n",
9526 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9527 goto err_vsi;
9528 }
9529 vsi->base_queue = ret;
9530
9531 /* get a VSI from the hardware */
9532 vsi->uplink_seid = uplink_seid;
9533 ret = i40e_add_vsi(vsi);
9534 if (ret)
9535 goto err_vsi;
9536
9537 switch (vsi->type) {
9538 /* setup the netdev if needed */
9539 case I40E_VSI_MAIN:
9540 case I40E_VSI_VMDQ2:
38e00438 9541 case I40E_VSI_FCOE:
41c445ff
JB		 9542 ret = i40e_config_netdev(vsi);
9543 if (ret)
9544 goto err_netdev;
9545 ret = register_netdev(vsi->netdev);
9546 if (ret)
9547 goto err_netdev;
9548 vsi->netdev_registered = true;
9549 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9550#ifdef CONFIG_I40E_DCB
9551 /* Setup DCB netlink interface */
9552 i40e_dcbnl_setup(vsi);
9553#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9554 /* fall through */
9555
9556 case I40E_VSI_FDIR:
9557 /* set up vectors and rings if needed */
9558 ret = i40e_vsi_setup_vectors(vsi);
9559 if (ret)
9560 goto err_msix;
9561
9562 ret = i40e_alloc_rings(vsi);
9563 if (ret)
9564 goto err_rings;
9565
9566 /* map all of the rings to the q_vectors */
9567 i40e_vsi_map_rings_to_vectors(vsi);
9568
9569 i40e_vsi_reset_stats(vsi);
9570 break;
9571
9572 default:
9573 /* no netdev or rings for the other VSI types */
9574 break;
9575 }
9576
e25d00b8
ASJ		 9577 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9578 (vsi->type == I40E_VSI_VMDQ2)) {
9579 ret = i40e_vsi_config_rss(vsi);
9580 }
41c445ff
JB		 9581 return vsi;
9582
9583err_rings:
9584 i40e_vsi_free_q_vectors(vsi);
9585err_msix:
9586 if (vsi->netdev_registered) {
9587 vsi->netdev_registered = false;
9588 unregister_netdev(vsi->netdev);
9589 free_netdev(vsi->netdev);
9590 vsi->netdev = NULL;
9591 }
9592err_netdev:
9593 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9594err_vsi:
9595 i40e_vsi_clear(vsi);
9596err_alloc:
9597 return NULL;
9598}
9599
9600/**
9601 * i40e_veb_get_bw_info - Query VEB BW information
9602 * @veb: the veb to query
9603 *
9604 * Query the Tx scheduler BW configuration data for given VEB
9605 **/
9606static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9607{
9608 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9609 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9610 struct i40e_pf *pf = veb->pf;
9611 struct i40e_hw *hw = &pf->hw;
9612 u32 tc_bw_max;
9613 int ret = 0;
9614 int i;
9615
9616 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9617 &bw_data, NULL);
9618 if (ret) {
9619 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9620 "query veb bw config failed, err %s aq_err %s\n",
9621 i40e_stat_str(&pf->hw, ret),
9622 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9623 goto out;
9624 }
9625
9626 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9627 &ets_data, NULL);
9628 if (ret) {
9629 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9630 "query veb bw ets config failed, err %s aq_err %s\n",
9631 i40e_stat_str(&pf->hw, ret),
9632 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9633 goto out;
9634 }
9635
9636 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9637 veb->bw_max_quanta = ets_data.tc_bw_max;
9638 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9639 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9640 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9641 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9642 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9643 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9644 veb->bw_tc_limit_credits[i] =
9645 le16_to_cpu(bw_data.tc_bw_limits[i]);
9646 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9647 }
9648
9649out:
9650 return ret;
9651}
9652
9653/**
9654 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9655 * @pf: board private structure
9656 *
9657 * On error: returns error code (negative)
9658 * On success: returns vsi index in PF (positive)
9659 **/
9660static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9661{
9662 int ret = -ENOENT;
9663 struct i40e_veb *veb;
9664 int i;
9665
9666 /* Need to protect the allocation of switch elements at the PF level */
9667 mutex_lock(&pf->switch_mutex);
9668
9669 /* VEB list may be fragmented if VEB creation/destruction has
9670 * been happening. We can afford to do a quick scan to look
9671 * for any free slots in the list.
9672 *
9673 * find next empty veb slot, looping back around if necessary
9674 */
9675 i = 0;
9676 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9677 i++;
9678 if (i >= I40E_MAX_VEB) {
9679 ret = -ENOMEM;
9680 goto err_alloc_veb; /* out of VEB slots! */
9681 }
9682
9683 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9684 if (!veb) {
9685 ret = -ENOMEM;
9686 goto err_alloc_veb;
9687 }
9688 veb->pf = pf;
9689 veb->idx = i;
9690 veb->enabled_tc = 1;
9691
9692 pf->veb[i] = veb;
9693 ret = i;
9694err_alloc_veb:
9695 mutex_unlock(&pf->switch_mutex);
9696 return ret;
9697}
9698
9699/**
9700 * i40e_switch_branch_release - Delete a branch of the switch tree
9701 * @branch: where to start deleting
9702 *
9703 * This uses recursion to find the tips of the branch to be
9704 * removed, deleting until we get back to and can delete this VEB.
9705 **/
9706static void i40e_switch_branch_release(struct i40e_veb *branch)
9707{
9708 struct i40e_pf *pf = branch->pf;
9709 u16 branch_seid = branch->seid;
9710 u16 veb_idx = branch->idx;
9711 int i;
9712
9713 /* release any VEBs on this VEB - RECURSION */
9714 for (i = 0; i < I40E_MAX_VEB; i++) {
9715 if (!pf->veb[i])
9716 continue;
9717 if (pf->veb[i]->uplink_seid == branch->seid)
9718 i40e_switch_branch_release(pf->veb[i]);
9719 }
9720
9721 /* Release the VSIs on this VEB, but not the owner VSI.
9722 *
9723 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9724 * the VEB itself, so don't use (*branch) after this loop.
9725 */
505682cd 9726 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9727 if (!pf->vsi[i])
9728 continue;
9729 if (pf->vsi[i]->uplink_seid == branch_seid &&
9730 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9731 i40e_vsi_release(pf->vsi[i]);
9732 }
9733 }
9734
9735 /* There's one corner case where the VEB might not have been
9736 * removed, so double check it here and remove it if needed.
9737 * This case happens if the veb was created from the debugfs
9738 * commands and no VSIs were added to it.
9739 */
9740 if (pf->veb[veb_idx])
9741 i40e_veb_release(pf->veb[veb_idx]);
9742}
9743
9744/**
9745 * i40e_veb_clear - remove veb struct
9746 * @veb: the veb to remove
9747 **/
9748static void i40e_veb_clear(struct i40e_veb *veb)
9749{
9750 if (!veb)
9751 return;
9752
9753 if (veb->pf) {
9754 struct i40e_pf *pf = veb->pf;
9755
9756 mutex_lock(&pf->switch_mutex);
9757 if (pf->veb[veb->idx] == veb)
9758 pf->veb[veb->idx] = NULL;
9759 mutex_unlock(&pf->switch_mutex);
9760 }
9761
9762 kfree(veb);
9763}
9764
9765/**
9766 * i40e_veb_release - Delete a VEB and free its resources
9767 * @veb: the VEB being removed
9768 **/
9769void i40e_veb_release(struct i40e_veb *veb)
9770{
9771 struct i40e_vsi *vsi = NULL;
9772 struct i40e_pf *pf;
9773 int i, n = 0;
9774
9775 pf = veb->pf;
9776
9777 /* find the remaining VSI and check for extras */
505682cd 9778 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9779 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9780 n++;
9781 vsi = pf->vsi[i];
9782 }
9783 }
9784 if (n != 1) {
9785 dev_info(&pf->pdev->dev,
9786 "can't remove VEB %d with %d VSIs left\n",
9787 veb->seid, n);
9788 return;
9789 }
9790
9791 /* move the remaining VSI to uplink veb */
9792 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9793 if (veb->uplink_seid) {
9794 vsi->uplink_seid = veb->uplink_seid;
9795 if (veb->uplink_seid == pf->mac_seid)
9796 vsi->veb_idx = I40E_NO_VEB;
9797 else
9798 vsi->veb_idx = veb->veb_idx;
9799 } else {
9800 /* floating VEB */
9801 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9802 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9803 }
9804
9805 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9806 i40e_veb_clear(veb);
41c445ff
JB		 9807}
9808
9809/**
9810 * i40e_add_veb - create the VEB in the switch
9811 * @veb: the VEB to be instantiated
9812 * @vsi: the controlling VSI
9813 **/
9814static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9815{
f1c7e72e 9816 struct i40e_pf *pf = veb->pf;
92faef85 9817 bool is_default = veb->pf->cur_promisc;
e1c51b95 9818 bool is_cloud = false;
41c445ff
JB		 9819 int ret;
9820
9821 /* get a VEB from the hardware */
f1c7e72e 9822 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9823 veb->enabled_tc, is_default,
9824 is_cloud, &veb->seid, NULL);
41c445ff 9825 if (ret) {
f1c7e72e
SN		 9826 dev_info(&pf->pdev->dev,
9827 "couldn't add VEB, err %s aq_err %s\n",
9828 i40e_stat_str(&pf->hw, ret),
9829 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9830 return -EPERM;
9831 }
9832
9833 /* get statistics counter */
f1c7e72e 9834 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9835 &veb->stats_idx, NULL, NULL, NULL);
9836 if (ret) {
f1c7e72e
SN		 9837 dev_info(&pf->pdev->dev,
9838 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9839 i40e_stat_str(&pf->hw, ret),
9840 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9841 return -EPERM;
9842 }
9843 ret = i40e_veb_get_bw_info(veb);
9844 if (ret) {
f1c7e72e
SN		 9845 dev_info(&pf->pdev->dev,
9846 "couldn't get VEB bw info, err %s aq_err %s\n",
9847 i40e_stat_str(&pf->hw, ret),
9848 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9849 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9850 return -ENOENT;
9851 }
9852
9853 vsi->uplink_seid = veb->seid;
9854 vsi->veb_idx = veb->idx;
9855 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9856
9857 return 0;
9858}
9859
9860/**
9861 * i40e_veb_setup - Set up a VEB
9862 * @pf: board private structure
9863 * @flags: VEB setup flags
9864 * @uplink_seid: the switch element to link to
9865 * @vsi_seid: the initial VSI seid
9866 * @enabled_tc: Enabled TC bit-map
9867 *
9868 * This allocates the sw VEB structure and links it into the switch
9869 * It is possible and legal for this to be a duplicate of an already
9870 * existing VEB. It is also possible for both uplink and vsi seids
9871 * to be zero, in order to create a floating VEB.
9872 *
9873 * Returns pointer to the successfully allocated VEB sw struct on
9874 * success, otherwise returns NULL on failure.
9875 **/
9876struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9877 u16 uplink_seid, u16 vsi_seid,
9878 u8 enabled_tc)
9879{
9880 struct i40e_veb *veb, *uplink_veb = NULL;
9881 int vsi_idx, veb_idx;
9882 int ret;
9883
9884 /* if one seid is 0, the other must be 0 to create a floating relay */
9885 if ((uplink_seid == 0 || vsi_seid == 0) &&
9886 (uplink_seid + vsi_seid != 0)) {
9887 dev_info(&pf->pdev->dev,
9888 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9889 uplink_seid, vsi_seid);
9890 return NULL;
9891 }
9892
9893 /* make sure there is such a vsi and uplink */
505682cd 9894 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9895 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9896 break;
505682cd 9897 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9898 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9899 vsi_seid);
9900 return NULL;
9901 }
9902
9903 if (uplink_seid && uplink_seid != pf->mac_seid) {
9904 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9905 if (pf->veb[veb_idx] &&
9906 pf->veb[veb_idx]->seid == uplink_seid) {
9907 uplink_veb = pf->veb[veb_idx];
9908 break;
9909 }
9910 }
9911 if (!uplink_veb) {
9912 dev_info(&pf->pdev->dev,
9913 "uplink seid %d not found\n", uplink_seid);
9914 return NULL;
9915 }
9916 }
9917
9918 /* get veb sw struct */
9919 veb_idx = i40e_veb_mem_alloc(pf);
9920 if (veb_idx < 0)
9921 goto err_alloc;
9922 veb = pf->veb[veb_idx];
9923 veb->flags = flags;
9924 veb->uplink_seid = uplink_seid;
9925 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9926 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9927
9928 /* create the VEB in the switch */
9929 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9930 if (ret)
9931 goto err_veb;
1bb8b935
SN		 9932 if (vsi_idx == pf->lan_vsi)
9933 pf->lan_veb = veb->idx;
41c445ff
JB		 9934
9935 return veb;
9936
9937err_veb:
9938 i40e_veb_clear(veb);
9939err_alloc:
9940 return NULL;
9941}
9942
9943/**
b40c82e6 9944 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9945 * @pf: board private structure
9946 * @ele: element we are building info from
9947 * @num_reported: total number of elements
9948 * @printconfig: should we print the contents
9949 *
9950 * helper function to assist in extracting a few useful SEID values.
9951 **/
9952static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9953 struct i40e_aqc_switch_config_element_resp *ele,
9954 u16 num_reported, bool printconfig)
9955{
9956 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9957 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9958 u8 element_type = ele->element_type;
9959 u16 seid = le16_to_cpu(ele->seid);
9960
9961 if (printconfig)
9962 dev_info(&pf->pdev->dev,
9963 "type=%d seid=%d uplink=%d downlink=%d\n",
9964 element_type, seid, uplink_seid, downlink_seid);
9965
9966 switch (element_type) {
9967 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9968 pf->mac_seid = seid;
9969 break;
9970 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9971 /* Main VEB? */
9972 if (uplink_seid != pf->mac_seid)
9973 break;
9974 if (pf->lan_veb == I40E_NO_VEB) {
9975 int v;
9976
9977 /* find existing or else empty VEB */
9978 for (v = 0; v < I40E_MAX_VEB; v++) {
9979 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9980 pf->lan_veb = v;
9981 break;
9982 }
9983 }
9984 if (pf->lan_veb == I40E_NO_VEB) {
9985 v = i40e_veb_mem_alloc(pf);
9986 if (v < 0)
9987 break;
9988 pf->lan_veb = v;
9989 }
9990 }
9991
9992 pf->veb[pf->lan_veb]->seid = seid;
9993 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9994 pf->veb[pf->lan_veb]->pf = pf;
9995 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9996 break;
9997 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9998 if (num_reported != 1)
9999 break;
10000 /* This is immediately after a reset so we can assume this is
10001 * the PF's VSI
10002 */
10003 pf->mac_seid = uplink_seid;
10004 pf->pf_seid = downlink_seid;
10005 pf->main_vsi_seid = seid;
10006 if (printconfig)
10007 dev_info(&pf->pdev->dev,
10008 "pf_seid=%d main_vsi_seid=%d\n",
10009 pf->pf_seid, pf->main_vsi_seid);
10010 break;
10011 case I40E_SWITCH_ELEMENT_TYPE_PF:
10012 case I40E_SWITCH_ELEMENT_TYPE_VF:
10013 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10014 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10015 case I40E_SWITCH_ELEMENT_TYPE_PE:
10016 case I40E_SWITCH_ELEMENT_TYPE_PA:
10017 /* ignore these for now */
10018 break;
10019 default:
10020 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10021 element_type, seid);
10022 break;
10023 }
10024}
10025
10026/**
10027 * i40e_fetch_switch_configuration - Get switch config from firmware
10028 * @pf: board private structure
10029 * @printconfig: should we print the contents
10030 *
10031 * Get the current switch configuration from the device and
10032 * extract a few useful SEID values.
10033 **/
10034int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10035{
10036 struct i40e_aqc_get_switch_config_resp *sw_config;
10037 u16 next_seid = 0;
10038 int ret = 0;
10039 u8 *aq_buf;
10040 int i;
10041
10042 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10043 if (!aq_buf)
10044 return -ENOMEM;
10045
10046 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10047 do {
10048 u16 num_reported, num_total;
10049
10050 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10051 I40E_AQ_LARGE_BUF,
10052 &next_seid, NULL);
10053 if (ret) {
10054 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10055 "get switch config failed err %s aq_err %s\n",
10056 i40e_stat_str(&pf->hw, ret),
10057 i40e_aq_str(&pf->hw,
10058 pf->hw.aq.asq_last_status));
41c445ff
JB		 10059 kfree(aq_buf);
10060 return -ENOENT;
10061 }
10062
10063 num_reported = le16_to_cpu(sw_config->header.num_reported);
10064 num_total = le16_to_cpu(sw_config->header.num_total);
10065
10066 if (printconfig)
10067 dev_info(&pf->pdev->dev,
10068 "header: %d reported %d total\n",
10069 num_reported, num_total);
10070
41c445ff
JB		 10071 for (i = 0; i < num_reported; i++) {
10072 struct i40e_aqc_switch_config_element_resp *ele =
10073 &sw_config->element[i];
10074
10075 i40e_setup_pf_switch_element(pf, ele, num_reported,
10076 printconfig);
10077 }
10078 } while (next_seid != 0);
10079
10080 kfree(aq_buf);
10081 return ret;
10082}
10083
10084/**
10085 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10086 * @pf: board private structure
bc7d338f 10087 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10088 *
10089 * Returns 0 on success, negative value on failure
10090 **/
bc7d338f 10091static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10092{
10093 int ret;
10094
10095 /* find out what's out there already */
10096 ret = i40e_fetch_switch_configuration(pf, false);
10097 if (ret) {
10098 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10099 "couldn't fetch switch config, err %s aq_err %s\n",
10100 i40e_stat_str(&pf->hw, ret),
10101 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10102 return ret;
10103 }
10104 i40e_pf_reset_stats(pf);
10105
41c445ff 10106 /* first time setup */
bc7d338f 10107 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10108 struct i40e_vsi *vsi = NULL;
10109 u16 uplink_seid;
10110
10111 /* Set up the PF VSI associated with the PF's main VSI
10112 * that is already in the HW switch
10113 */
10114 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10115 uplink_seid = pf->veb[pf->lan_veb]->seid;
10116 else
10117 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10118 if (pf->lan_vsi == I40E_NO_VSI)
10119 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10120 else if (reinit)
10121 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10122 if (!vsi) {
10123 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10124 i40e_fdir_teardown(pf);
10125 return -EAGAIN;
10126 }
41c445ff
JB		 10127 } else {
10128 /* force a reset of TC and queue layout configurations */
10129 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10130
41c445ff
JB		 10131 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10132 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10133 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10134 }
10135 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10136
cbf61325
ASJ		 10137 i40e_fdir_sb_setup(pf);
10138
41c445ff
JB		 10139 /* Setup static PF queue filter control settings */
10140 ret = i40e_setup_pf_filter_control(pf);
10141 if (ret) {
10142 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10143 ret);
10144 /* Failure here should not stop continuing other steps */
10145 }
10146
10147 /* enable RSS in the HW, even for only one queue, as the stack can use
10148 * the hash
10149 */
10150 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10151 i40e_pf_config_rss(pf);
41c445ff
JB		 10152
10153 /* fill in link information and enable LSE reporting */
0a862b43 10154 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10155 i40e_link_event(pf);
10156
d52c20b7 10157 /* Initialize user-specific link properties */
41c445ff
JB		 10158 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10159 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10160
beb0dff1
JK		 10161 i40e_ptp_init(pf);
10162
41c445ff
JB		 10163 return ret;
10164}
10165
41c445ff
JB		 10166/**
10167 * i40e_determine_queue_usage - Work out queue distribution
10168 * @pf: board private structure
10169 **/
10170static void i40e_determine_queue_usage(struct i40e_pf *pf)
10171{
41c445ff
JB		 10172 int queues_left;
10173
10174 pf->num_lan_qps = 0;
38e00438
VD		 10175#ifdef I40E_FCOE
10176 pf->num_fcoe_qps = 0;
10177#endif
41c445ff
JB		 10178
10179 /* Find the max queues to be put into basic use. We'll always be
10180 * using TC0, whether or not DCB is running, and TC0 will get the
10181 * big RSS set.
10182 */
10183 queues_left = pf->hw.func_caps.num_tx_qp;
10184
cbf61325 10185 if ((queues_left == 1) ||
9aa7e935 10186 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10187 /* one qp for PF, no queues for anything else */
10188 queues_left = 0;
acd65448 10189 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10190
10191 /* make sure all the fancies are disabled */
60ea5f83 10192 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10193#ifdef I40E_FCOE
10194 I40E_FLAG_FCOE_ENABLED |
10195#endif
60ea5f83
JB		 10196 I40E_FLAG_FD_SB_ENABLED |
10197 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10198 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10199 I40E_FLAG_SRIOV_ENABLED |
10200 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10201 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10202 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10203 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10204 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10205 /* one qp for PF */
acd65448 10206 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10207 queues_left -= pf->num_lan_qps;
10208
10209 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10210#ifdef I40E_FCOE
10211 I40E_FLAG_FCOE_ENABLED |
10212#endif
9aa7e935
FZ		 10213 I40E_FLAG_FD_SB_ENABLED |
10214 I40E_FLAG_FD_ATR_ENABLED |
10215 I40E_FLAG_DCB_ENABLED |
10216 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10217 } else {
cbf61325 10218 /* Not enough queues for all TCs */
4d9b6043 10219 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10220 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10221 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10222 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10223 }
9a3bd2f1
ASJ		 10224 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10225 num_online_cpus());
10226 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10227 pf->hw.func_caps.num_tx_qp);
10228
cbf61325
ASJ		 10229 queues_left -= pf->num_lan_qps;
10230 }
10231
38e00438
VD		 10232#ifdef I40E_FCOE
10233 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10234 if (I40E_DEFAULT_FCOE <= queues_left) {
10235 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10236 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10237 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10238 } else {
10239 pf->num_fcoe_qps = 0;
10240 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10241 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10242 }
10243
10244 queues_left -= pf->num_fcoe_qps;
10245 }
10246
10247#endif
cbf61325
ASJ		 10248 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10249 if (queues_left > 1) {
10250 queues_left -= 1; /* save 1 queue for FD */
10251 } else {
10252 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10253 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10254 }
41c445ff
JB		 10255 }
10256
10257 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10258 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10259 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10260 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10261 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10262 }
10263
10264 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10265 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10266 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10267 (queues_left / pf->num_vmdq_qps));
10268 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10269 }
10270
f8ff1464 10271 pf->queues_left = queues_left;
8279e495
NP		 10272 dev_dbg(&pf->pdev->dev,
10273 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10274 pf->hw.func_caps.num_tx_qp,
10275 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10276 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10277 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10278 queues_left);
38e00438 10279#ifdef I40E_FCOE
8279e495 10280 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10281#endif
41c445ff
JB		 10282}
10283
10284/**
10285 * i40e_setup_pf_filter_control - Setup PF static filter control
10286 * @pf: PF to be setup
10287 *
b40c82e6 10288 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10289 * settings. If PE/FCoE are enabled then it will also set the per PF
10290 * based filter sizes required for them. It also enables Flow director,
10291 * ethertype and macvlan type filter settings for the pf.
10292 *
10293 * Returns 0 on success, negative on failure
10294 **/
10295static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10296{
10297 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10298
10299 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10300
10301 /* Flow Director is enabled */
60ea5f83 10302 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10303 settings->enable_fdir = true;
10304
10305 /* Ethtype and MACVLAN filters enabled for PF */
10306 settings->enable_ethtype = true;
10307 settings->enable_macvlan = true;
10308
10309 if (i40e_set_filter_control(&pf->hw, settings))
10310 return -ENOENT;
10311
10312 return 0;
10313}
10314
0c22b3dd 10315#define INFO_STRING_LEN 255
7fd89545 10316#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10317static void i40e_print_features(struct i40e_pf *pf)
10318{
10319 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10320 char *buf;
10321 int i;
0c22b3dd 10322
3b195843
JP		 10323 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10324 if (!buf)
0c22b3dd 10325 return;
0c22b3dd 10326
3b195843 10327 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10328#ifdef CONFIG_PCI_IOV
3b195843 10329 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10330#endif
3b195843 10331 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d RX: %s",
7fd89545
SN		 10332 pf->hw.func_caps.num_vsis,
10333 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10334 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10335
10336 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10337 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10338 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10339 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10340 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10341 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10342 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10343 }
4d9b6043 10344 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10345 i += snprintf(&buf[i], REMAIN(i), " DCB");
ce6fcb3f 10346#if IS_ENABLED(CONFIG_VXLAN)
3b195843 10347 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
ce6fcb3f 10348#endif
0c22b3dd 10349 if (pf->flags & I40E_FLAG_PTP)
3b195843 10350 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10351#ifdef I40E_FCOE
10352 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10353 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10354#endif
6dec1017 10355 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10356 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10357 else
3b195843 10358 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10359
3b195843
JP		 10360 dev_info(&pf->pdev->dev, "%s\n", buf);
10361 kfree(buf);
7fd89545 10362 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10363}
10364
41c445ff
JB		 10365/**
10366 * i40e_probe - Device initialization routine
10367 * @pdev: PCI device information struct
10368 * @ent: entry in i40e_pci_tbl
10369 *
b40c82e6
JK		 10370 * i40e_probe initializes a PF identified by a pci_dev structure.
10371 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10372 * and a hardware reset occur.
10373 *
10374 * Returns 0 on success, negative on failure
10375 **/
10376static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10377{
e827845c 10378 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10379 struct i40e_pf *pf;
10380 struct i40e_hw *hw;
93cd765b 10381 static u16 pfs_found;
1d5109d1 10382 u16 wol_nvm_bits;
d4dfb81a 10383 u16 link_status;
6f66a484 10384 int err;
41c445ff 10385 u32 len;
4f2f017c 10386 u32 val;
8a9eb7d3 10387 u32 i;
58fc3267 10388 u8 set_fc_aq_fail;
41c445ff
JB		 10389
10390 err = pci_enable_device_mem(pdev);
10391 if (err)
10392 return err;
10393
10394 /* set up for high or low dma */
6494294f 10395 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10396 if (err) {
e3e3bfdd
JS		 10397 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10398 if (err) {
10399 dev_err(&pdev->dev,
10400 "DMA configuration failed: 0x%x\n", err);
10401 goto err_dma;
10402 }
41c445ff
JB		 10403 }
10404
10405 /* set up pci connections */
10406 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10407 IORESOURCE_MEM), i40e_driver_name);
10408 if (err) {
10409 dev_info(&pdev->dev,
10410 "pci_request_selected_regions failed %d\n", err);
10411 goto err_pci_reg;
10412 }
10413
10414 pci_enable_pcie_error_reporting(pdev);
10415 pci_set_master(pdev);
10416
10417 /* Now that we have a PCI connection, we need to do the
10418 * low level device setup. This is primarily setting up
10419 * the Admin Queue structures and then querying for the
10420 * device's current profile information.
10421 */
10422 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10423 if (!pf) {
10424 err = -ENOMEM;
10425 goto err_pf_alloc;
10426 }
10427 pf->next_vsi = 0;
10428 pf->pdev = pdev;
10429 set_bit(__I40E_DOWN, &pf->state);
10430
10431 hw = &pf->hw;
10432 hw->back = pf;
232f4706 10433
2ac8b675
SN		 10434 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10435 I40E_MAX_CSR_SPACE);
232f4706 10436
2ac8b675 10437 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10438 if (!hw->hw_addr) {
10439 err = -EIO;
10440 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10441 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10442 pf->ioremap_len, err);
41c445ff
JB		 10443 goto err_ioremap;
10444 }
10445 hw->vendor_id = pdev->vendor;
10446 hw->device_id = pdev->device;
10447 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10448 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10449 hw->subsystem_device_id = pdev->subsystem_device;
10450 hw->bus.device = PCI_SLOT(pdev->devfn);
10451 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10452 pf->instance = pfs_found;
41c445ff 10453
5b5faa43
SN		 10454 if (debug != -1) {
10455 pf->msg_enable = pf->hw.debug_mask;
10456 pf->msg_enable = debug;
10457 }
10458
7134f9ce
JB		 10459 /* do a special CORER for clearing PXE mode once at init */
10460 if (hw->revision_id == 0 &&
10461 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10462 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10463 i40e_flush(hw);
10464 msleep(200);
10465 pf->corer_count++;
10466
10467 i40e_clear_pxe_mode(hw);
10468 }
10469
41c445ff 10470 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10471 i40e_clear_hw(hw);
41c445ff
JB		 10472 err = i40e_pf_reset(hw);
10473 if (err) {
10474 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10475 goto err_pf_reset;
10476 }
10477 pf->pfr_count++;
10478
10479 hw->aq.num_arq_entries = I40E_AQ_LEN;
10480 hw->aq.num_asq_entries = I40E_AQ_LEN;
10481 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10482 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10483 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10484
b294ac70 10485 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10486 "%s-%s:misc",
10487 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10488
10489 err = i40e_init_shared_code(hw);
10490 if (err) {
b2a75c58
ASJ		 10491 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10492 err);
41c445ff
JB		 10493 goto err_pf_reset;
10494 }
10495
d52c20b7
JB		 10496 /* set up a default setting for link flow control */
10497 pf->hw.fc.requested_mode = I40E_FC_NONE;
10498
41c445ff 10499 err = i40e_init_adminq(hw);
2b2426a7
CW		 10500 if (err) {
10501 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10502 dev_info(&pdev->dev,
10503 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10504 else
10505 dev_info(&pdev->dev,
10506 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10507
10508 goto err_pf_reset;
10509 }
f0b44440 10510
6dec1017
SN		 10511 /* provide nvm, fw, api versions */
10512 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10513 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10514 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10515 i40e_nvm_version_str(hw));
f0b44440 10516
7aa67613
CS		 10517 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10518 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10519 dev_info(&pdev->dev,
7aa67613
CS		 10520 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10521 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10522 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10523 dev_info(&pdev->dev,
7aa67613 10524 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10525
4eb3f768
SN		 10526 i40e_verify_eeprom(pf);
10527
2c5fe33b
JB		 10528 /* Rev 0 hardware was never productized */
10529 if (hw->revision_id < 1)
10530 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10531
6ff4ef86 10532 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10533 err = i40e_get_capabilities(pf);
10534 if (err)
10535 goto err_adminq_setup;
10536
10537 err = i40e_sw_init(pf);
10538 if (err) {
10539 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10540 goto err_sw_init;
10541 }
10542
10543 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10544 hw->func_caps.num_rx_qp,
10545 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10546 if (err) {
10547 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10548 goto err_init_lan_hmc;
10549 }
10550
10551 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10552 if (err) {
10553 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10554 err = -ENOENT;
10555 goto err_configure_lan_hmc;
10556 }
10557
b686ece5
NP		 10558 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10559 * Ignore error return codes because if it was already disabled via
10560 * hardware settings this will fail
10561 */
10562 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10563 (pf->hw.aq.fw_maj_ver < 4)) {
10564 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10565 i40e_aq_stop_lldp(hw, true, NULL);
10566 }
10567
41c445ff 10568 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10569 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10570 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10571 err = -EIO;
10572 goto err_mac_addr;
10573 }
10574 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10575 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10576 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10577 if (is_valid_ether_addr(hw->mac.port_addr))
10578 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10579#ifdef I40E_FCOE
10580 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10581 if (err)
10582 dev_info(&pdev->dev,
10583 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10584 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10585 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10586 hw->mac.san_addr);
10587 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10588 }
10589 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10590#endif /* I40E_FCOE */
41c445ff
JB		 10591
10592 pci_set_drvdata(pdev, pf);
10593 pci_save_state(pdev);
4e3b35b0
NP		 10594#ifdef CONFIG_I40E_DCB
10595 err = i40e_init_pf_dcb(pf);
10596 if (err) {
aebfc816 10597 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10598 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10599 /* Continue without DCB enabled */
4e3b35b0
NP		 10600 }
10601#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10602
10603 /* set up periodic task facility */
10604 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10605 pf->service_timer_period = HZ;
10606
10607 INIT_WORK(&pf->service_task, i40e_service_task);
10608 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10609 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10610
1d5109d1
SN		 10611 /* NVM bit on means WoL disabled for the port */
10612 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10613 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10614 pf->wol_en = false;
10615 else
10616 pf->wol_en = true;
8e2773ae
SN		 10617 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10618
41c445ff
JB		 10619 /* set up the main switch operations */
10620 i40e_determine_queue_usage(pf);
c1147280
JB		 10621 err = i40e_init_interrupt_scheme(pf);
10622 if (err)
10623 goto err_switch_setup;
41c445ff 10624
505682cd
MW		 10625 /* The number of VSIs reported by the FW is the minimum guaranteed
10626 * to us; HW supports far more and we share the remaining pool with
10627 * the other PFs. We allocate space for more than the guarantee with
10628 * the understanding that we might not get them all later.
41c445ff 10629 */
505682cd
MW		 10630 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10631 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10632 else
10633 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10634
10635 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10636 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10637 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10638 if (!pf->vsi) {
10639 err = -ENOMEM;
41c445ff 10640 goto err_switch_setup;
ed87ac09 10641 }
41c445ff 10642
fa11cb3d
ASJ		 10643#ifdef CONFIG_PCI_IOV
10644 /* prep for VF support */
10645 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10646 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10647 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10648 if (pci_num_vf(pdev))
10649 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10650 }
10651#endif
bc7d338f 10652 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10653 if (err) {
10654 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10655 goto err_vsis;
10656 }
58fc3267
HZ		 10657
10658 /* Make sure flow control is set according to current settings */
10659 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10660 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10661 dev_dbg(&pf->pdev->dev,
10662 "Set fc with err %s aq_err %s on get_phy_cap\n",
10663 i40e_stat_str(hw, err),
10664 i40e_aq_str(hw, hw->aq.asq_last_status));
10665 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10666 dev_dbg(&pf->pdev->dev,
10667 "Set fc with err %s aq_err %s on set_phy_config\n",
10668 i40e_stat_str(hw, err),
10669 i40e_aq_str(hw, hw->aq.asq_last_status));
10670 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10671 dev_dbg(&pf->pdev->dev,
10672 "Set fc with err %s aq_err %s on get_link_info\n",
10673 i40e_stat_str(hw, err),
10674 i40e_aq_str(hw, hw->aq.asq_last_status));
10675
8a9eb7d3 10676 /* if FDIR VSI was set up, start it now */
505682cd 10677 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10678 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10679 i40e_vsi_open(pf->vsi[i]);
10680 break;
10681 }
10682 }
41c445ff 10683
7e2453fe
JB		 10684 /* driver is only interested in link up/down and module qualification
10685 * reports from firmware
10686 */
10687 err = i40e_aq_set_phy_int_mask(&pf->hw,
10688 I40E_AQ_EVENT_LINK_UPDOWN |
10689 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10690 if (err)
f1c7e72e
SN		 10691 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10692 i40e_stat_str(&pf->hw, err),
10693 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10694
4f2f017c
ASJ		 10695 /* Reconfigure hardware for allowing smaller MSS in the case
10696 * of TSO, so that we avoid the MDD being fired and causing
10697 * a reset in the case of small MSS+TSO.
10698 */
10699 val = rd32(hw, I40E_REG_MSS);
10700 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10701 val &= ~I40E_REG_MSS_MIN_MASK;
10702 val |= I40E_64BYTE_MSS;
10703 wr32(hw, I40E_REG_MSS, val);
10704 }
10705
025b4a54
ASJ		 10706 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10707 (pf->hw.aq.fw_maj_ver < 4)) {
10708 msleep(75);
10709 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10710 if (err)
f1c7e72e
SN		 10711 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10712 i40e_stat_str(&pf->hw, err),
10713 i40e_aq_str(&pf->hw,
10714 pf->hw.aq.asq_last_status));
cafa2ee6 10715 }
41c445ff
JB		 10716 /* The main driver is (mostly) up and happy. We need to set this state
10717 * before setting up the misc vector or we get a race and the vector
10718 * ends up disabled forever.
10719 */
10720 clear_bit(__I40E_DOWN, &pf->state);
10721
10722 /* In case of MSIX we are going to setup the misc vector right here
10723 * to handle admin queue events etc. In case of legacy and MSI
10724 * the misc functionality and queue processing is combined in
10725 * the same vector and that gets setup at open.
10726 */
10727 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10728 err = i40e_setup_misc_vector(pf);
10729 if (err) {
10730 dev_info(&pdev->dev,
10731 "setup of misc vector failed: %d\n", err);
10732 goto err_vsis;
10733 }
10734 }
10735
df805f62 10736#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10737 /* prep for VF support */
10738 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10739 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10740 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10741 u32 val;
10742
10743 /* disable link interrupts for VFs */
10744 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10745 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10746 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10747 i40e_flush(hw);
4aeec010
MW		 10748
10749 if (pci_num_vf(pdev)) {
10750 dev_info(&pdev->dev,
10751 "Active VFs found, allocating resources.\n");
10752 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10753 if (err)
10754 dev_info(&pdev->dev,
10755 "Error %d allocating resources for existing VFs\n",
10756 err);
10757 }
41c445ff 10758 }
df805f62 10759#endif /* CONFIG_PCI_IOV */
41c445ff 10760
93cd765b
ASJ		 10761 pfs_found++;
10762
41c445ff
JB		 10763 i40e_dbg_pf_init(pf);
10764
10765 /* tell the firmware that we're starting */
44033fac 10766 i40e_send_version(pf);
41c445ff
JB		 10767
10768 /* since everything's happy, start the service_task timer */
10769 mod_timer(&pf->service_timer,
10770 round_jiffies(jiffies + pf->service_timer_period));
10771
38e00438
VD		 10772#ifdef I40E_FCOE
10773 /* create FCoE interface */
10774 i40e_fcoe_vsi_setup(pf);
10775
10776#endif
3fced535
ASJ		 10777#define PCI_SPEED_SIZE 8
10778#define PCI_WIDTH_SIZE 8
10779 /* Devices on the IOSF bus do not have this information
10780 * and will report PCI Gen 1 x 1 by default so don't bother
10781 * checking them.
10782 */
10783 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
10784 char speed[PCI_SPEED_SIZE] = "Unknown";
10785 char width[PCI_WIDTH_SIZE] = "Unknown";
10786
10787 /* Get the negotiated link width and speed from PCI config
10788 * space
10789 */
10790 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
10791 &link_status);
10792
10793 i40e_set_pci_config_data(hw, link_status);
10794
10795 switch (hw->bus.speed) {
10796 case i40e_bus_speed_8000:
10797 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
10798 case i40e_bus_speed_5000:
10799 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
10800 case i40e_bus_speed_2500:
10801 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
10802 default:
10803 break;
10804 }
10805 switch (hw->bus.width) {
10806 case i40e_bus_width_pcie_x8:
10807 strncpy(width, "8", PCI_WIDTH_SIZE); break;
10808 case i40e_bus_width_pcie_x4:
10809 strncpy(width, "4", PCI_WIDTH_SIZE); break;
10810 case i40e_bus_width_pcie_x2:
10811 strncpy(width, "2", PCI_WIDTH_SIZE); break;
10812 case i40e_bus_width_pcie_x1:
10813 strncpy(width, "1", PCI_WIDTH_SIZE); break;
10814 default:
10815 break;
10816 }
10817
10818 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
10819 speed, width);
10820
10821 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10822 hw->bus.speed < i40e_bus_speed_8000) {
10823 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10824 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10825 }
d4dfb81a
CS		 10826 }
10827
e827845c
CS		 10828 /* get the requested speeds from the fw */
10829 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10830 if (err)
8279e495
NP		 10831 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
10832 i40e_stat_str(&pf->hw, err),
10833 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10834 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10835
fc72dbce
CS		 10836 /* get the supported phy types from the fw */
10837 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
10838 if (err)
10839 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
10840 i40e_stat_str(&pf->hw, err),
10841 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10842 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
10843
e7358f54
ASJ		 10844 /* Add a filter to drop all Flow control frames from any VSI from being
10845 * transmitted. By doing so we stop a malicious VF from sending out
10846 * PAUSE or PFC frames and potentially controlling traffic for other
10847 * PF/VF VSIs.
10848 * The FW can still send Flow control frames if enabled.
10849 */
10850 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
10851 pf->main_vsi_seid);
10852
0c22b3dd
JB		 10853 /* print a string summarizing features */
10854 i40e_print_features(pf);
10855
41c445ff
JB		 10856 return 0;
10857
10858 /* Unwind what we've done if something failed in the setup */
10859err_vsis:
10860 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10861 i40e_clear_interrupt_scheme(pf);
10862 kfree(pf->vsi);
04b03013
SN		 10863err_switch_setup:
10864 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10865 del_timer_sync(&pf->service_timer);
10866err_mac_addr:
10867err_configure_lan_hmc:
10868 (void)i40e_shutdown_lan_hmc(hw);
10869err_init_lan_hmc:
10870 kfree(pf->qp_pile);
41c445ff
JB		 10871err_sw_init:
10872err_adminq_setup:
10873 (void)i40e_shutdown_adminq(hw);
10874err_pf_reset:
10875 iounmap(hw->hw_addr);
10876err_ioremap:
10877 kfree(pf);
10878err_pf_alloc:
10879 pci_disable_pcie_error_reporting(pdev);
10880 pci_release_selected_regions(pdev,
10881 pci_select_bars(pdev, IORESOURCE_MEM));
10882err_pci_reg:
10883err_dma:
10884 pci_disable_device(pdev);
10885 return err;
10886}
10887
10888/**
10889 * i40e_remove - Device removal routine
10890 * @pdev: PCI device information struct
10891 *
10892 * i40e_remove is called by the PCI subsystem to alert the driver
10893 * that is should release a PCI device. This could be caused by a
10894 * Hot-Plug event, or because the driver is going to be removed from
10895 * memory.
10896 **/
10897static void i40e_remove(struct pci_dev *pdev)
10898{
10899 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 10900 struct i40e_hw *hw = &pf->hw;
41c445ff 10901 i40e_status ret_code;
41c445ff
JB		 10902 int i;
10903
10904 i40e_dbg_pf_exit(pf);
10905
beb0dff1
JK		 10906 i40e_ptp_stop(pf);
10907
bcab2db9
CW		 10908 /* Disable RSS in hw */
10909 wr32(hw, I40E_PFQF_HENA(0), 0);
10910 wr32(hw, I40E_PFQF_HENA(1), 0);
10911
41c445ff
JB		 10912 /* no more scheduling of any task */
10913 set_bit(__I40E_DOWN, &pf->state);
10914 del_timer_sync(&pf->service_timer);
10915 cancel_work_sync(&pf->service_task);
33c62b34 10916 i40e_fdir_teardown(pf);
41c445ff 10917
eb2d80bc
MW		 10918 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10919 i40e_free_vfs(pf);
10920 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10921 }
10922
41c445ff
JB		 10923 i40e_fdir_teardown(pf);
10924
10925 /* If there is a switch structure or any orphans, remove them.
10926 * This will leave only the PF's VSI remaining.
10927 */
10928 for (i = 0; i < I40E_MAX_VEB; i++) {
10929 if (!pf->veb[i])
10930 continue;
10931
10932 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10933 pf->veb[i]->uplink_seid == 0)
10934 i40e_switch_branch_release(pf->veb[i]);
10935 }
10936
10937 /* Now we can shutdown the PF's VSI, just before we kill
10938 * adminq and hmc.
10939 */
10940 if (pf->vsi[pf->lan_vsi])
10941 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10942
41c445ff 10943 /* shutdown and destroy the HMC */
60442dea
SN		 10944 if (pf->hw.hmc.hmc_obj) {
10945 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10946 if (ret_code)
10947 dev_warn(&pdev->dev,
10948 "Failed to destroy the HMC resources: %d\n",
10949 ret_code);
10950 }
41c445ff
JB		 10951
10952 /* shutdown the adminq */
41c445ff
JB		 10953 ret_code = i40e_shutdown_adminq(&pf->hw);
10954 if (ret_code)
10955 dev_warn(&pdev->dev,
10956 "Failed to destroy the Admin Queue resources: %d\n",
10957 ret_code);
10958
10959 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10960 i40e_clear_interrupt_scheme(pf);
505682cd 10961 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10962 if (pf->vsi[i]) {
10963 i40e_vsi_clear_rings(pf->vsi[i]);
10964 i40e_vsi_clear(pf->vsi[i]);
10965 pf->vsi[i] = NULL;
10966 }
10967 }
10968
10969 for (i = 0; i < I40E_MAX_VEB; i++) {
10970 kfree(pf->veb[i]);
10971 pf->veb[i] = NULL;
10972 }
10973
10974 kfree(pf->qp_pile);
41c445ff
JB		 10975 kfree(pf->vsi);
10976
41c445ff
JB		 10977 iounmap(pf->hw.hw_addr);
10978 kfree(pf);
10979 pci_release_selected_regions(pdev,
10980 pci_select_bars(pdev, IORESOURCE_MEM));
10981
10982 pci_disable_pcie_error_reporting(pdev);
10983 pci_disable_device(pdev);
10984}
10985
10986/**
10987 * i40e_pci_error_detected - warning that something funky happened in PCI land
10988 * @pdev: PCI device information struct
10989 *
10990 * Called to warn that something happened and the error handling steps
10991 * are in progress. Allows the driver to quiesce things, be ready for
10992 * remediation.
10993 **/
10994static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10995 enum pci_channel_state error)
10996{
10997 struct i40e_pf *pf = pci_get_drvdata(pdev);
10998
10999 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11000
11001 /* shutdown all operations */
9007bccd
SN		 11002 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11003 rtnl_lock();
11004 i40e_prep_for_reset(pf);
11005 rtnl_unlock();
11006 }
41c445ff
JB		 11007
11008 /* Request a slot reset */
11009 return PCI_ERS_RESULT_NEED_RESET;
11010}
11011
11012/**
11013 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11014 * @pdev: PCI device information struct
11015 *
11016 * Called to find if the driver can work with the device now that
11017 * the pci slot has been reset. If a basic connection seems good
11018 * (registers are readable and have sane content) then return a
11019 * happy little PCI_ERS_RESULT_xxx.
11020 **/
11021static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11022{
11023 struct i40e_pf *pf = pci_get_drvdata(pdev);
11024 pci_ers_result_t result;
11025 int err;
11026 u32 reg;
11027
fb43201f 11028 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11029 if (pci_enable_device_mem(pdev)) {
11030 dev_info(&pdev->dev,
11031 "Cannot re-enable PCI device after reset.\n");
11032 result = PCI_ERS_RESULT_DISCONNECT;
11033 } else {
11034 pci_set_master(pdev);
11035 pci_restore_state(pdev);
11036 pci_save_state(pdev);
11037 pci_wake_from_d3(pdev, false);
11038
11039 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11040 if (reg == 0)
11041 result = PCI_ERS_RESULT_RECOVERED;
11042 else
11043 result = PCI_ERS_RESULT_DISCONNECT;
11044 }
11045
11046 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11047 if (err) {
11048 dev_info(&pdev->dev,
11049 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11050 err);
11051 /* non-fatal, continue */
11052 }
11053
11054 return result;
11055}
11056
11057/**
11058 * i40e_pci_error_resume - restart operations after PCI error recovery
11059 * @pdev: PCI device information struct
11060 *
11061 * Called to allow the driver to bring things back up after PCI error
11062 * and/or reset recovery has finished.
11063 **/
11064static void i40e_pci_error_resume(struct pci_dev *pdev)
11065{
11066 struct i40e_pf *pf = pci_get_drvdata(pdev);
11067
fb43201f 11068 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11069 if (test_bit(__I40E_SUSPENDED, &pf->state))
11070 return;
11071
11072 rtnl_lock();
41c445ff 11073 i40e_handle_reset_warning(pf);
4c4935a9 11074 rtnl_unlock();
9007bccd
SN		 11075}
11076
11077/**
11078 * i40e_shutdown - PCI callback for shutting down
11079 * @pdev: PCI device information struct
11080 **/
11081static void i40e_shutdown(struct pci_dev *pdev)
11082{
11083 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11084 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11085
11086 set_bit(__I40E_SUSPENDED, &pf->state);
11087 set_bit(__I40E_DOWN, &pf->state);
11088 rtnl_lock();
11089 i40e_prep_for_reset(pf);
11090 rtnl_unlock();
11091
8e2773ae
SN		 11092 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11093 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11094
02b42498
CS		 11095 del_timer_sync(&pf->service_timer);
11096 cancel_work_sync(&pf->service_task);
11097 i40e_fdir_teardown(pf);
11098
11099 rtnl_lock();
11100 i40e_prep_for_reset(pf);
11101 rtnl_unlock();
11102
11103 wr32(hw, I40E_PFPM_APM,
11104 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11105 wr32(hw, I40E_PFPM_WUFC,
11106 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11107
e147758d
SN		 11108 i40e_clear_interrupt_scheme(pf);
11109
9007bccd 11110 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11111 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11112 pci_set_power_state(pdev, PCI_D3hot);
11113 }
11114}
11115
11116#ifdef CONFIG_PM
11117/**
11118 * i40e_suspend - PCI callback for moving to D3
11119 * @pdev: PCI device information struct
11120 **/
11121static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11122{
11123 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11124 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11125
11126 set_bit(__I40E_SUSPENDED, &pf->state);
11127 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11128
9007bccd
SN		 11129 rtnl_lock();
11130 i40e_prep_for_reset(pf);
11131 rtnl_unlock();
11132
8e2773ae
SN		 11133 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11134 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11135
11136 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11137 pci_set_power_state(pdev, PCI_D3hot);
11138
11139 return 0;
41c445ff
JB		 11140}
11141
9007bccd
SN		 11142/**
11143 * i40e_resume - PCI callback for waking up from D3
11144 * @pdev: PCI device information struct
11145 **/
11146static int i40e_resume(struct pci_dev *pdev)
11147{
11148 struct i40e_pf *pf = pci_get_drvdata(pdev);
11149 u32 err;
11150
11151 pci_set_power_state(pdev, PCI_D0);
11152 pci_restore_state(pdev);
11153 /* pci_restore_state() clears dev->state_saves, so
11154 * call pci_save_state() again to restore it.
11155 */
11156 pci_save_state(pdev);
11157
11158 err = pci_enable_device_mem(pdev);
11159 if (err) {
fb43201f 11160 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11161 return err;
11162 }
11163 pci_set_master(pdev);
11164
11165 /* no wakeup events while running */
11166 pci_wake_from_d3(pdev, false);
11167
11168 /* handling the reset will rebuild the device state */
11169 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11170 clear_bit(__I40E_DOWN, &pf->state);
11171 rtnl_lock();
11172 i40e_reset_and_rebuild(pf, false);
11173 rtnl_unlock();
11174 }
11175
11176 return 0;
11177}
11178
11179#endif
41c445ff
JB		 11180static const struct pci_error_handlers i40e_err_handler = {
11181 .error_detected = i40e_pci_error_detected,
11182 .slot_reset = i40e_pci_error_slot_reset,
11183 .resume = i40e_pci_error_resume,
11184};
11185
11186static struct pci_driver i40e_driver = {
11187 .name = i40e_driver_name,
11188 .id_table = i40e_pci_tbl,
11189 .probe = i40e_probe,
11190 .remove = i40e_remove,
9007bccd
SN		 11191#ifdef CONFIG_PM
11192 .suspend = i40e_suspend,
11193 .resume = i40e_resume,
11194#endif
11195 .shutdown = i40e_shutdown,
41c445ff
JB		 11196 .err_handler = &i40e_err_handler,
11197 .sriov_configure = i40e_pci_sriov_configure,
11198};
11199
11200/**
11201 * i40e_init_module - Driver registration routine
11202 *
11203 * i40e_init_module is the first routine called when the driver is
11204 * loaded. All it does is register with the PCI subsystem.
11205 **/
11206static int __init i40e_init_module(void)
11207{
11208 pr_info("%s: %s - version %s\n", i40e_driver_name,
11209 i40e_driver_string, i40e_driver_version_str);
11210 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11211
41c445ff
JB		 11212 i40e_dbg_init();
11213 return pci_register_driver(&i40e_driver);
11214}
11215module_init(i40e_init_module);
11216
11217/**
11218 * i40e_exit_module - Driver exit cleanup routine
11219 *
11220 * i40e_exit_module is called just before the driver is removed
11221 * from memory.
11222 **/
11223static void __exit i40e_exit_module(void)
11224{
11225 pci_unregister_driver(&i40e_driver);
11226 i40e_dbg_exit();
11227}
11228module_exit(i40e_exit_module);
Linux kernel - Deliverables
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