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i40e: Don't register/de-register apps on NIC partitions in MFP mode
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
a36fdd8e 41#define DRV_VERSION_MINOR 2
3182b25e 42#define DRV_VERSION_BUILD 43
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
ae24b409 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
41c445ff
JB		 79 /* required last entry */
80 {0, }
81};
82MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
83
84#define I40E_MAX_VF_COUNT 128
85static int debug = -1;
86module_param(debug, int, 0);
87MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
88
89MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
90MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_VERSION);
93
94/**
95 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
96 * @hw: pointer to the HW structure
97 * @mem: ptr to mem struct to fill out
98 * @size: size of memory requested
99 * @alignment: what to align the allocation to
100 **/
101int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
102 u64 size, u32 alignment)
103{
104 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
105
106 mem->size = ALIGN(size, alignment);
107 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
108 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 109 if (!mem->va)
110 return -ENOMEM;
41c445ff 111
93bc73b8 112 return 0;
41c445ff
JB		 113}
114
115/**
116 * i40e_free_dma_mem_d - OS specific memory free for shared code
117 * @hw: pointer to the HW structure
118 * @mem: ptr to mem struct to free
119 **/
120int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
121{
122 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
123
124 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
125 mem->va = NULL;
126 mem->pa = 0;
127 mem->size = 0;
128
129 return 0;
130}
131
132/**
133 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
134 * @hw: pointer to the HW structure
135 * @mem: ptr to mem struct to fill out
136 * @size: size of memory requested
137 **/
138int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
139 u32 size)
140{
141 mem->size = size;
142 mem->va = kzalloc(size, GFP_KERNEL);
143
93bc73b8
JB		 144 if (!mem->va)
145 return -ENOMEM;
41c445ff 146
93bc73b8 147 return 0;
41c445ff
JB		 148}
149
150/**
151 * i40e_free_virt_mem_d - OS specific memory free for shared code
152 * @hw: pointer to the HW structure
153 * @mem: ptr to mem struct to free
154 **/
155int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
156{
157 /* it's ok to kfree a NULL pointer */
158 kfree(mem->va);
159 mem->va = NULL;
160 mem->size = 0;
161
162 return 0;
163}
164
165/**
166 * i40e_get_lump - find a lump of free generic resource
167 * @pf: board private structure
168 * @pile: the pile of resource to search
169 * @needed: the number of items needed
170 * @id: an owner id to stick on the items assigned
171 *
172 * Returns the base item index of the lump, or negative for error
173 *
174 * The search_hint trick and lack of advanced fit-finding only work
175 * because we're highly likely to have all the same size lump requests.
176 * Linear search time and any fragmentation should be minimal.
177 **/
178static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
179 u16 needed, u16 id)
180{
181 int ret = -ENOMEM;
ddf434ac 182 int i, j;
41c445ff
JB		 183
184 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
185 dev_info(&pf->pdev->dev,
186 "param err: pile=%p needed=%d id=0x%04x\n",
187 pile, needed, id);
188 return -EINVAL;
189 }
190
191 /* start the linear search with an imperfect hint */
192 i = pile->search_hint;
ddf434ac 193 while (i < pile->num_entries) {
41c445ff
JB		 194 /* skip already allocated entries */
195 if (pile->list[i] & I40E_PILE_VALID_BIT) {
196 i++;
197 continue;
198 }
199
200 /* do we have enough in this lump? */
201 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
202 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
203 break;
204 }
205
206 if (j == needed) {
207 /* there was enough, so assign it to the requestor */
208 for (j = 0; j < needed; j++)
209 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
210 ret = i;
211 pile->search_hint = i + j;
ddf434ac 212 break;
41c445ff
JB		 213 } else {
214 /* not enough, so skip over it and continue looking */
215 i += j;
216 }
217 }
218
219 return ret;
220}
221
222/**
223 * i40e_put_lump - return a lump of generic resource
224 * @pile: the pile of resource to search
225 * @index: the base item index
226 * @id: the owner id of the items assigned
227 *
228 * Returns the count of items in the lump
229 **/
230static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
231{
232 int valid_id = (id | I40E_PILE_VALID_BIT);
233 int count = 0;
234 int i;
235
236 if (!pile || index >= pile->num_entries)
237 return -EINVAL;
238
239 for (i = index;
240 i < pile->num_entries && pile->list[i] == valid_id;
241 i++) {
242 pile->list[i] = 0;
243 count++;
244 }
245
246 if (count && index < pile->search_hint)
247 pile->search_hint = index;
248
249 return count;
250}
251
252/**
253 * i40e_service_event_schedule - Schedule the service task to wake up
254 * @pf: board private structure
255 *
256 * If not already scheduled, this puts the task into the work queue
257 **/
258static void i40e_service_event_schedule(struct i40e_pf *pf)
259{
260 if (!test_bit(__I40E_DOWN, &pf->state) &&
261 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
262 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
263 schedule_work(&pf->service_task);
264}
265
266/**
267 * i40e_tx_timeout - Respond to a Tx Hang
268 * @netdev: network interface device structure
269 *
270 * If any port has noticed a Tx timeout, it is likely that the whole
271 * device is munged, not just the one netdev port, so go for the full
272 * reset.
273 **/
38e00438
VD		 274#ifdef I40E_FCOE
275void i40e_tx_timeout(struct net_device *netdev)
276#else
41c445ff 277static void i40e_tx_timeout(struct net_device *netdev)
38e00438 278#endif
41c445ff
JB		 279{
280 struct i40e_netdev_priv *np = netdev_priv(netdev);
281 struct i40e_vsi *vsi = np->vsi;
282 struct i40e_pf *pf = vsi->back;
283
284 pf->tx_timeout_count++;
285
286 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 287 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 288 pf->tx_timeout_last_recovery = jiffies;
289 netdev_info(netdev, "tx_timeout recovery level %d\n",
290 pf->tx_timeout_recovery_level);
291
292 switch (pf->tx_timeout_recovery_level) {
293 case 0:
294 /* disable and re-enable queues for the VSI */
295 if (in_interrupt()) {
296 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
297 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
298 } else {
299 i40e_vsi_reinit_locked(vsi);
300 }
301 break;
302 case 1:
303 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
304 break;
305 case 2:
306 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
307 break;
308 case 3:
309 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
310 break;
311 default:
312 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 313 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
314 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 315 break;
316 }
317 i40e_service_event_schedule(pf);
318 pf->tx_timeout_recovery_level++;
319}
320
321/**
322 * i40e_release_rx_desc - Store the new tail and head values
323 * @rx_ring: ring to bump
324 * @val: new head index
325 **/
326static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
327{
328 rx_ring->next_to_use = val;
329
330 /* Force memory writes to complete before letting h/w
331 * know there are new descriptors to fetch. (Only
332 * applicable for weak-ordered memory model archs,
333 * such as IA-64).
334 */
335 wmb();
336 writel(val, rx_ring->tail);
337}
338
339/**
340 * i40e_get_vsi_stats_struct - Get System Network Statistics
341 * @vsi: the VSI we care about
342 *
343 * Returns the address of the device statistics structure.
344 * The statistics are actually updated from the service task.
345 **/
346struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
347{
348 return &vsi->net_stats;
349}
350
351/**
352 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
353 * @netdev: network interface device structure
354 *
355 * Returns the address of the device statistics structure.
356 * The statistics are actually updated from the service task.
357 **/
38e00438
VD		 358#ifdef I40E_FCOE
359struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
360 struct net_device *netdev,
361 struct rtnl_link_stats64 *stats)
362#else
41c445ff
JB		 363static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
364 struct net_device *netdev,
980e9b11 365 struct rtnl_link_stats64 *stats)
38e00438 366#endif
41c445ff
JB		 367{
368 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 369 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 370 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 371 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
372 int i;
373
bc7d338f
ASJ		 374 if (test_bit(__I40E_DOWN, &vsi->state))
375 return stats;
376
3c325ced
JB		 377 if (!vsi->tx_rings)
378 return stats;
379
980e9b11
AD		 380 rcu_read_lock();
381 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 382 u64 bytes, packets;
383 unsigned int start;
384
385 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
386 if (!tx_ring)
387 continue;
388
389 do {
57a7744e 390 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 391 packets = tx_ring->stats.packets;
392 bytes = tx_ring->stats.bytes;
57a7744e 393 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 394
395 stats->tx_packets += packets;
396 stats->tx_bytes += bytes;
397 rx_ring = &tx_ring[1];
398
399 do {
57a7744e 400 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 401 packets = rx_ring->stats.packets;
402 bytes = rx_ring->stats.bytes;
57a7744e 403 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 404
980e9b11
AD		 405 stats->rx_packets += packets;
406 stats->rx_bytes += bytes;
407 }
408 rcu_read_unlock();
409
a5282f44 410 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 411 stats->multicast = vsi_stats->multicast;
412 stats->tx_errors = vsi_stats->tx_errors;
413 stats->tx_dropped = vsi_stats->tx_dropped;
414 stats->rx_errors = vsi_stats->rx_errors;
415 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
416 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 417
980e9b11 418 return stats;
41c445ff
JB		 419}
420
421/**
422 * i40e_vsi_reset_stats - Resets all stats of the given vsi
423 * @vsi: the VSI to have its stats reset
424 **/
425void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
426{
427 struct rtnl_link_stats64 *ns;
428 int i;
429
430 if (!vsi)
431 return;
432
433 ns = i40e_get_vsi_stats_struct(vsi);
434 memset(ns, 0, sizeof(*ns));
435 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
436 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
437 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 438 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 439 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 440 memset(&vsi->rx_rings[i]->stats, 0 ,
441 sizeof(vsi->rx_rings[i]->stats));
442 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
443 sizeof(vsi->rx_rings[i]->rx_stats));
444 memset(&vsi->tx_rings[i]->stats, 0 ,
445 sizeof(vsi->tx_rings[i]->stats));
446 memset(&vsi->tx_rings[i]->tx_stats, 0,
447 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 448 }
8e9dca53 449 }
41c445ff
JB		 450 vsi->stat_offsets_loaded = false;
451}
452
453/**
b40c82e6 454 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 455 * @pf: the PF to be reset
456 **/
457void i40e_pf_reset_stats(struct i40e_pf *pf)
458{
e91fdf76
SN		 459 int i;
460
41c445ff
JB		 461 memset(&pf->stats, 0, sizeof(pf->stats));
462 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
463 pf->stat_offsets_loaded = false;
e91fdf76
SN		 464
465 for (i = 0; i < I40E_MAX_VEB; i++) {
466 if (pf->veb[i]) {
467 memset(&pf->veb[i]->stats, 0,
468 sizeof(pf->veb[i]->stats));
469 memset(&pf->veb[i]->stats_offsets, 0,
470 sizeof(pf->veb[i]->stats_offsets));
471 pf->veb[i]->stat_offsets_loaded = false;
472 }
473 }
41c445ff
JB		 474}
475
476/**
477 * i40e_stat_update48 - read and update a 48 bit stat from the chip
478 * @hw: ptr to the hardware info
479 * @hireg: the high 32 bit reg to read
480 * @loreg: the low 32 bit reg to read
481 * @offset_loaded: has the initial offset been loaded yet
482 * @offset: ptr to current offset value
483 * @stat: ptr to the stat
484 *
485 * Since the device stats are not reset at PFReset, they likely will not
486 * be zeroed when the driver starts. We'll save the first values read
487 * and use them as offsets to be subtracted from the raw values in order
488 * to report stats that count from zero. In the process, we also manage
489 * the potential roll-over.
490 **/
491static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
492 bool offset_loaded, u64 *offset, u64 *stat)
493{
494 u64 new_data;
495
ab60085e 496 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 497 new_data = rd32(hw, loreg);
498 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
499 } else {
500 new_data = rd64(hw, loreg);
501 }
502 if (!offset_loaded)
503 *offset = new_data;
504 if (likely(new_data >= *offset))
505 *stat = new_data - *offset;
506 else
507 *stat = (new_data + ((u64)1 << 48)) - *offset;
508 *stat &= 0xFFFFFFFFFFFFULL;
509}
510
511/**
512 * i40e_stat_update32 - read and update a 32 bit stat from the chip
513 * @hw: ptr to the hardware info
514 * @reg: the hw reg to read
515 * @offset_loaded: has the initial offset been loaded yet
516 * @offset: ptr to current offset value
517 * @stat: ptr to the stat
518 **/
519static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
520 bool offset_loaded, u64 *offset, u64 *stat)
521{
522 u32 new_data;
523
524 new_data = rd32(hw, reg);
525 if (!offset_loaded)
526 *offset = new_data;
527 if (likely(new_data >= *offset))
528 *stat = (u32)(new_data - *offset);
529 else
530 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
531}
532
533/**
534 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
535 * @vsi: the VSI to be updated
536 **/
537void i40e_update_eth_stats(struct i40e_vsi *vsi)
538{
539 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
540 struct i40e_pf *pf = vsi->back;
541 struct i40e_hw *hw = &pf->hw;
542 struct i40e_eth_stats *oes;
543 struct i40e_eth_stats *es; /* device's eth stats */
544
545 es = &vsi->eth_stats;
546 oes = &vsi->eth_stats_offsets;
547
548 /* Gather up the stats that the hw collects */
549 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
550 vsi->stat_offsets_loaded,
551 &oes->tx_errors, &es->tx_errors);
552 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
553 vsi->stat_offsets_loaded,
554 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 555 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
556 vsi->stat_offsets_loaded,
557 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
558 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
559 vsi->stat_offsets_loaded,
560 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 561
562 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
563 I40E_GLV_GORCL(stat_idx),
564 vsi->stat_offsets_loaded,
565 &oes->rx_bytes, &es->rx_bytes);
566 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
567 I40E_GLV_UPRCL(stat_idx),
568 vsi->stat_offsets_loaded,
569 &oes->rx_unicast, &es->rx_unicast);
570 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
571 I40E_GLV_MPRCL(stat_idx),
572 vsi->stat_offsets_loaded,
573 &oes->rx_multicast, &es->rx_multicast);
574 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
575 I40E_GLV_BPRCL(stat_idx),
576 vsi->stat_offsets_loaded,
577 &oes->rx_broadcast, &es->rx_broadcast);
578
579 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
580 I40E_GLV_GOTCL(stat_idx),
581 vsi->stat_offsets_loaded,
582 &oes->tx_bytes, &es->tx_bytes);
583 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
584 I40E_GLV_UPTCL(stat_idx),
585 vsi->stat_offsets_loaded,
586 &oes->tx_unicast, &es->tx_unicast);
587 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
588 I40E_GLV_MPTCL(stat_idx),
589 vsi->stat_offsets_loaded,
590 &oes->tx_multicast, &es->tx_multicast);
591 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
592 I40E_GLV_BPTCL(stat_idx),
593 vsi->stat_offsets_loaded,
594 &oes->tx_broadcast, &es->tx_broadcast);
595 vsi->stat_offsets_loaded = true;
596}
597
598/**
599 * i40e_update_veb_stats - Update Switch component statistics
600 * @veb: the VEB being updated
601 **/
602static void i40e_update_veb_stats(struct i40e_veb *veb)
603{
604 struct i40e_pf *pf = veb->pf;
605 struct i40e_hw *hw = &pf->hw;
606 struct i40e_eth_stats *oes;
607 struct i40e_eth_stats *es; /* device's eth stats */
608 int idx = 0;
609
610 idx = veb->stats_idx;
611 es = &veb->stats;
612 oes = &veb->stats_offsets;
613
614 /* Gather up the stats that the hw collects */
615 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
616 veb->stat_offsets_loaded,
617 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 618 if (hw->revision_id > 0)
619 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
620 veb->stat_offsets_loaded,
621 &oes->rx_unknown_protocol,
622 &es->rx_unknown_protocol);
41c445ff
JB		 623 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
624 veb->stat_offsets_loaded,
625 &oes->rx_bytes, &es->rx_bytes);
626 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
627 veb->stat_offsets_loaded,
628 &oes->rx_unicast, &es->rx_unicast);
629 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
630 veb->stat_offsets_loaded,
631 &oes->rx_multicast, &es->rx_multicast);
632 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
633 veb->stat_offsets_loaded,
634 &oes->rx_broadcast, &es->rx_broadcast);
635
636 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
637 veb->stat_offsets_loaded,
638 &oes->tx_bytes, &es->tx_bytes);
639 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
640 veb->stat_offsets_loaded,
641 &oes->tx_unicast, &es->tx_unicast);
642 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
643 veb->stat_offsets_loaded,
644 &oes->tx_multicast, &es->tx_multicast);
645 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
646 veb->stat_offsets_loaded,
647 &oes->tx_broadcast, &es->tx_broadcast);
648 veb->stat_offsets_loaded = true;
649}
650
38e00438
VD		 651#ifdef I40E_FCOE
652/**
653 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
654 * @vsi: the VSI that is capable of doing FCoE
655 **/
656static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
657{
658 struct i40e_pf *pf = vsi->back;
659 struct i40e_hw *hw = &pf->hw;
660 struct i40e_fcoe_stats *ofs;
661 struct i40e_fcoe_stats *fs; /* device's eth stats */
662 int idx;
663
664 if (vsi->type != I40E_VSI_FCOE)
665 return;
666
667 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
668 fs = &vsi->fcoe_stats;
669 ofs = &vsi->fcoe_stats_offsets;
670
671 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
672 vsi->fcoe_stat_offsets_loaded,
673 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
674 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
675 vsi->fcoe_stat_offsets_loaded,
676 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
677 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
678 vsi->fcoe_stat_offsets_loaded,
679 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
680 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
681 vsi->fcoe_stat_offsets_loaded,
682 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
683 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
684 vsi->fcoe_stat_offsets_loaded,
685 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
686 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
687 vsi->fcoe_stat_offsets_loaded,
688 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
689 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
690 vsi->fcoe_stat_offsets_loaded,
691 &ofs->fcoe_last_error, &fs->fcoe_last_error);
692 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
693 vsi->fcoe_stat_offsets_loaded,
694 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
695
696 vsi->fcoe_stat_offsets_loaded = true;
697}
698
699#endif
41c445ff
JB		 700/**
701 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
702 * @pf: the corresponding PF
703 *
704 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
705 **/
706static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
707{
708 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
709 struct i40e_hw_port_stats *nsd = &pf->stats;
710 struct i40e_hw *hw = &pf->hw;
711 u64 xoff = 0;
712 u16 i, v;
713
714 if ((hw->fc.current_mode != I40E_FC_FULL) &&
715 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
716 return;
717
718 xoff = nsd->link_xoff_rx;
719 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
720 pf->stat_offsets_loaded,
721 &osd->link_xoff_rx, &nsd->link_xoff_rx);
722
723 /* No new LFC xoff rx */
724 if (!(nsd->link_xoff_rx - xoff))
725 return;
726
727 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 728 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 729 struct i40e_vsi *vsi = pf->vsi[v];
730
ddfda80f 731 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 732 continue;
733
734 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 735 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 736 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
737 }
738 }
739}
740
741/**
742 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
743 * @pf: the corresponding PF
744 *
745 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
746 **/
747static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
748{
749 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
750 struct i40e_hw_port_stats *nsd = &pf->stats;
751 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
752 struct i40e_dcbx_config *dcb_cfg;
753 struct i40e_hw *hw = &pf->hw;
754 u16 i, v;
755 u8 tc;
756
757 dcb_cfg = &hw->local_dcbx_config;
758
759 /* See if DCB enabled with PFC TC */
760 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
761 !(dcb_cfg->pfc.pfcenable)) {
762 i40e_update_link_xoff_rx(pf);
763 return;
764 }
765
766 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
767 u64 prio_xoff = nsd->priority_xoff_rx[i];
768 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
769 pf->stat_offsets_loaded,
770 &osd->priority_xoff_rx[i],
771 &nsd->priority_xoff_rx[i]);
772
773 /* No new PFC xoff rx */
774 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
775 continue;
776 /* Get the TC for given priority */
777 tc = dcb_cfg->etscfg.prioritytable[i];
778 xoff[tc] = true;
779 }
780
781 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 782 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 783 struct i40e_vsi *vsi = pf->vsi[v];
784
ddfda80f 785 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 786 continue;
787
788 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 789 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 790
791 tc = ring->dcb_tc;
792 if (xoff[tc])
793 clear_bit(__I40E_HANG_CHECK_ARMED,
794 &ring->state);
795 }
796 }
797}
798
799/**
7812fddc 800 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 801 * @vsi: the VSI to be updated
802 *
803 * There are a few instances where we store the same stat in a
804 * couple of different structs. This is partly because we have
805 * the netdev stats that need to be filled out, which is slightly
806 * different from the "eth_stats" defined by the chip and used in
7812fddc 807 * VF communications. We sort it out here.
41c445ff 808 **/
7812fddc 809static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 810{
811 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 812 struct rtnl_link_stats64 *ons;
813 struct rtnl_link_stats64 *ns; /* netdev stats */
814 struct i40e_eth_stats *oes;
815 struct i40e_eth_stats *es; /* device's eth stats */
816 u32 tx_restart, tx_busy;
bf00b376 817 struct i40e_ring *p;
41c445ff 818 u32 rx_page, rx_buf;
bf00b376
AA		 819 u64 bytes, packets;
820 unsigned int start;
41c445ff
JB		 821 u64 rx_p, rx_b;
822 u64 tx_p, tx_b;
41c445ff
JB		 823 u16 q;
824
825 if (test_bit(__I40E_DOWN, &vsi->state) ||
826 test_bit(__I40E_CONFIG_BUSY, &pf->state))
827 return;
828
829 ns = i40e_get_vsi_stats_struct(vsi);
830 ons = &vsi->net_stats_offsets;
831 es = &vsi->eth_stats;
832 oes = &vsi->eth_stats_offsets;
833
834 /* Gather up the netdev and vsi stats that the driver collects
835 * on the fly during packet processing
836 */
837 rx_b = rx_p = 0;
838 tx_b = tx_p = 0;
839 tx_restart = tx_busy = 0;
840 rx_page = 0;
841 rx_buf = 0;
980e9b11 842 rcu_read_lock();
41c445ff 843 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 844 /* locate Tx ring */
845 p = ACCESS_ONCE(vsi->tx_rings[q]);
846
847 do {
57a7744e 848 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 849 packets = p->stats.packets;
850 bytes = p->stats.bytes;
57a7744e 851 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 852 tx_b += bytes;
853 tx_p += packets;
854 tx_restart += p->tx_stats.restart_queue;
855 tx_busy += p->tx_stats.tx_busy;
41c445ff 856
980e9b11
AD		 857 /* Rx queue is part of the same block as Tx queue */
858 p = &p[1];
859 do {
57a7744e 860 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 861 packets = p->stats.packets;
862 bytes = p->stats.bytes;
57a7744e 863 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 864 rx_b += bytes;
865 rx_p += packets;
420136cc
MW		 866 rx_buf += p->rx_stats.alloc_buff_failed;
867 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 868 }
980e9b11 869 rcu_read_unlock();
41c445ff
JB		 870 vsi->tx_restart = tx_restart;
871 vsi->tx_busy = tx_busy;
872 vsi->rx_page_failed = rx_page;
873 vsi->rx_buf_failed = rx_buf;
874
875 ns->rx_packets = rx_p;
876 ns->rx_bytes = rx_b;
877 ns->tx_packets = tx_p;
878 ns->tx_bytes = tx_b;
879
41c445ff 880 /* update netdev stats from eth stats */
7812fddc 881 i40e_update_eth_stats(vsi);
41c445ff
JB		 882 ons->tx_errors = oes->tx_errors;
883 ns->tx_errors = es->tx_errors;
884 ons->multicast = oes->rx_multicast;
885 ns->multicast = es->rx_multicast;
41a9e55c
SN		 886 ons->rx_dropped = oes->rx_discards;
887 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 888 ons->tx_dropped = oes->tx_discards;
889 ns->tx_dropped = es->tx_discards;
890
7812fddc 891 /* pull in a couple PF stats if this is the main vsi */
41c445ff 892 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 893 ns->rx_crc_errors = pf->stats.crc_errors;
894 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
895 ns->rx_length_errors = pf->stats.rx_length_errors;
896 }
897}
41c445ff 898
7812fddc 899/**
b40c82e6 900 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 901 * @pf: the PF to be updated
902 **/
903static void i40e_update_pf_stats(struct i40e_pf *pf)
904{
905 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
906 struct i40e_hw_port_stats *nsd = &pf->stats;
907 struct i40e_hw *hw = &pf->hw;
908 u32 val;
909 int i;
41c445ff 910
7812fddc
SN		 911 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
912 I40E_GLPRT_GORCL(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
915 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
916 I40E_GLPRT_GOTCL(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
919 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
920 pf->stat_offsets_loaded,
921 &osd->eth.rx_discards,
922 &nsd->eth.rx_discards);
532d283d
SN		 923 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
924 I40E_GLPRT_UPRCL(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->eth.rx_unicast,
927 &nsd->eth.rx_unicast);
7812fddc
SN		 928 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
929 I40E_GLPRT_MPRCL(hw->port),
930 pf->stat_offsets_loaded,
931 &osd->eth.rx_multicast,
932 &nsd->eth.rx_multicast);
532d283d
SN		 933 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
934 I40E_GLPRT_BPRCL(hw->port),
935 pf->stat_offsets_loaded,
936 &osd->eth.rx_broadcast,
937 &nsd->eth.rx_broadcast);
938 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
939 I40E_GLPRT_UPTCL(hw->port),
940 pf->stat_offsets_loaded,
941 &osd->eth.tx_unicast,
942 &nsd->eth.tx_unicast);
943 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
944 I40E_GLPRT_MPTCL(hw->port),
945 pf->stat_offsets_loaded,
946 &osd->eth.tx_multicast,
947 &nsd->eth.tx_multicast);
948 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
949 I40E_GLPRT_BPTCL(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->eth.tx_broadcast,
952 &nsd->eth.tx_broadcast);
41c445ff 953
7812fddc
SN		 954 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
955 pf->stat_offsets_loaded,
956 &osd->tx_dropped_link_down,
957 &nsd->tx_dropped_link_down);
41c445ff 958
7812fddc
SN		 959 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
960 pf->stat_offsets_loaded,
961 &osd->crc_errors, &nsd->crc_errors);
41c445ff 962
7812fddc
SN		 963 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 966
7812fddc
SN		 967 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->mac_local_faults,
970 &nsd->mac_local_faults);
971 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->mac_remote_faults,
974 &nsd->mac_remote_faults);
41c445ff 975
7812fddc
SN		 976 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
977 pf->stat_offsets_loaded,
978 &osd->rx_length_errors,
979 &nsd->rx_length_errors);
41c445ff 980
7812fddc
SN		 981 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
982 pf->stat_offsets_loaded,
983 &osd->link_xon_rx, &nsd->link_xon_rx);
984 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
985 pf->stat_offsets_loaded,
986 &osd->link_xon_tx, &nsd->link_xon_tx);
987 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
988 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 991
7812fddc
SN		 992 for (i = 0; i < 8; i++) {
993 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 994 pf->stat_offsets_loaded,
7812fddc
SN		 995 &osd->priority_xon_rx[i],
996 &nsd->priority_xon_rx[i]);
997 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_tx[i],
1000 &nsd->priority_xon_tx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xoff_tx[i],
1004 &nsd->priority_xoff_tx[i]);
1005 i40e_stat_update32(hw,
1006 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1007 pf->stat_offsets_loaded,
7812fddc
SN		 1008 &osd->priority_xon_2_xoff[i],
1009 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1010 }
1011
7812fddc
SN		 1012 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1013 I40E_GLPRT_PRC64L(hw->port),
1014 pf->stat_offsets_loaded,
1015 &osd->rx_size_64, &nsd->rx_size_64);
1016 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1017 I40E_GLPRT_PRC127L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_127, &nsd->rx_size_127);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1021 I40E_GLPRT_PRC255L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_255, &nsd->rx_size_255);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1025 I40E_GLPRT_PRC511L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_511, &nsd->rx_size_511);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1029 I40E_GLPRT_PRC1023L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_1023, &nsd->rx_size_1023);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1033 I40E_GLPRT_PRC1522L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1522, &nsd->rx_size_1522);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1037 I40E_GLPRT_PRC9522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_big, &nsd->rx_size_big);
1040
1041 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1042 I40E_GLPRT_PTC64L(hw->port),
1043 pf->stat_offsets_loaded,
1044 &osd->tx_size_64, &nsd->tx_size_64);
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1046 I40E_GLPRT_PTC127L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_127, &nsd->tx_size_127);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1050 I40E_GLPRT_PTC255L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_255, &nsd->tx_size_255);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1054 I40E_GLPRT_PTC511L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_511, &nsd->tx_size_511);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1058 I40E_GLPRT_PTC1023L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_1023, &nsd->tx_size_1023);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1062 I40E_GLPRT_PTC1522L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1522, &nsd->tx_size_1522);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1066 I40E_GLPRT_PTC9522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_big, &nsd->tx_size_big);
1069
1070 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->rx_undersize, &nsd->rx_undersize);
1073 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1074 pf->stat_offsets_loaded,
1075 &osd->rx_fragments, &nsd->rx_fragments);
1076 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1077 pf->stat_offsets_loaded,
1078 &osd->rx_oversize, &nsd->rx_oversize);
1079 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1080 pf->stat_offsets_loaded,
1081 &osd->rx_jabber, &nsd->rx_jabber);
1082
433c47de
ASJ		 1083 /* FDIR stats */
1084 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1085 pf->stat_offsets_loaded,
1086 &osd->fd_atr_match, &nsd->fd_atr_match);
1087 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1088 pf->stat_offsets_loaded,
1089 &osd->fd_sb_match, &nsd->fd_sb_match);
1090
7812fddc
SN		 1091 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1092 nsd->tx_lpi_status =
1093 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1094 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1095 nsd->rx_lpi_status =
1096 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1097 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1098 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1099 pf->stat_offsets_loaded,
1100 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1101 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1102 pf->stat_offsets_loaded,
1103 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1104
41c445ff
JB		 1105 pf->stat_offsets_loaded = true;
1106}
1107
7812fddc
SN		 1108/**
1109 * i40e_update_stats - Update the various statistics counters.
1110 * @vsi: the VSI to be updated
1111 *
1112 * Update the various stats for this VSI and its related entities.
1113 **/
1114void i40e_update_stats(struct i40e_vsi *vsi)
1115{
1116 struct i40e_pf *pf = vsi->back;
1117
1118 if (vsi == pf->vsi[pf->lan_vsi])
1119 i40e_update_pf_stats(pf);
1120
1121 i40e_update_vsi_stats(vsi);
38e00438
VD		 1122#ifdef I40E_FCOE
1123 i40e_update_fcoe_stats(vsi);
1124#endif
7812fddc
SN		 1125}
1126
41c445ff
JB		 1127/**
1128 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1129 * @vsi: the VSI to be searched
1130 * @macaddr: the MAC address
1131 * @vlan: the vlan
b40c82e6 1132 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1133 * @is_netdev: make sure its a netdev filter, else doesn't matter
1134 *
1135 * Returns ptr to the filter object or NULL
1136 **/
1137static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1138 u8 *macaddr, s16 vlan,
1139 bool is_vf, bool is_netdev)
1140{
1141 struct i40e_mac_filter *f;
1142
1143 if (!vsi || !macaddr)
1144 return NULL;
1145
1146 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1147 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1148 (vlan == f->vlan) &&
1149 (!is_vf || f->is_vf) &&
1150 (!is_netdev || f->is_netdev))
1151 return f;
1152 }
1153 return NULL;
1154}
1155
1156/**
1157 * i40e_find_mac - Find a mac addr in the macvlan filters list
1158 * @vsi: the VSI to be searched
1159 * @macaddr: the MAC address we are searching for
b40c82e6 1160 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1161 * @is_netdev: make sure its a netdev filter, else doesn't matter
1162 *
1163 * Returns the first filter with the provided MAC address or NULL if
1164 * MAC address was not found
1165 **/
1166struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1167 bool is_vf, bool is_netdev)
1168{
1169 struct i40e_mac_filter *f;
1170
1171 if (!vsi || !macaddr)
1172 return NULL;
1173
1174 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1175 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1176 (!is_vf || f->is_vf) &&
1177 (!is_netdev || f->is_netdev))
1178 return f;
1179 }
1180 return NULL;
1181}
1182
1183/**
1184 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1185 * @vsi: the VSI to be searched
1186 *
1187 * Returns true if VSI is in vlan mode or false otherwise
1188 **/
1189bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1190{
1191 struct i40e_mac_filter *f;
1192
1193 /* Only -1 for all the filters denotes not in vlan mode
1194 * so we have to go through all the list in order to make sure
1195 */
1196 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1197 if (f->vlan >= 0)
1198 return true;
1199 }
1200
1201 return false;
1202}
1203
1204/**
1205 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1206 * @vsi: the VSI to be searched
1207 * @macaddr: the mac address to be filtered
b40c82e6 1208 * @is_vf: true if it is a VF
41c445ff
JB		 1209 * @is_netdev: true if it is a netdev
1210 *
1211 * Goes through all the macvlan filters and adds a
1212 * macvlan filter for each unique vlan that already exists
1213 *
1214 * Returns first filter found on success, else NULL
1215 **/
1216struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1217 bool is_vf, bool is_netdev)
1218{
1219 struct i40e_mac_filter *f;
1220
1221 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1222 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1223 is_vf, is_netdev)) {
1224 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1225 is_vf, is_netdev))
41c445ff
JB		 1226 return NULL;
1227 }
1228 }
1229
1230 return list_first_entry_or_null(&vsi->mac_filter_list,
1231 struct i40e_mac_filter, list);
1232}
1233
8c27d42e
GR		 1234/**
1235 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1236 * @vsi: the PF Main VSI - inappropriate for any other VSI
1237 * @macaddr: the MAC address
30650cc5
SN		 1238 *
1239 * Some older firmware configurations set up a default promiscuous VLAN
1240 * filter that needs to be removed.
8c27d42e 1241 **/
30650cc5 1242static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1243{
1244 struct i40e_aqc_remove_macvlan_element_data element;
1245 struct i40e_pf *pf = vsi->back;
1246 i40e_status aq_ret;
1247
1248 /* Only appropriate for the PF main VSI */
1249 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1250 return -EINVAL;
8c27d42e 1251
30650cc5 1252 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1253 ether_addr_copy(element.mac_addr, macaddr);
1254 element.vlan_tag = 0;
1255 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1256 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1257 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1258 if (aq_ret)
30650cc5
SN		 1259 return -ENOENT;
1260
1261 return 0;
8c27d42e
GR		 1262}
1263
41c445ff
JB		 1264/**
1265 * i40e_add_filter - Add a mac/vlan filter to the VSI
1266 * @vsi: the VSI to be searched
1267 * @macaddr: the MAC address
1268 * @vlan: the vlan
b40c82e6 1269 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1270 * @is_netdev: make sure its a netdev filter, else doesn't matter
1271 *
1272 * Returns ptr to the filter object or NULL when no memory available.
1273 **/
1274struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1275 u8 *macaddr, s16 vlan,
1276 bool is_vf, bool is_netdev)
1277{
1278 struct i40e_mac_filter *f;
1279
1280 if (!vsi || !macaddr)
1281 return NULL;
1282
1283 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1284 if (!f) {
1285 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1286 if (!f)
1287 goto add_filter_out;
1288
9a173901 1289 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1290 f->vlan = vlan;
1291 f->changed = true;
1292
1293 INIT_LIST_HEAD(&f->list);
1294 list_add(&f->list, &vsi->mac_filter_list);
1295 }
1296
1297 /* increment counter and add a new flag if needed */
1298 if (is_vf) {
1299 if (!f->is_vf) {
1300 f->is_vf = true;
1301 f->counter++;
1302 }
1303 } else if (is_netdev) {
1304 if (!f->is_netdev) {
1305 f->is_netdev = true;
1306 f->counter++;
1307 }
1308 } else {
1309 f->counter++;
1310 }
1311
1312 /* changed tells sync_filters_subtask to
1313 * push the filter down to the firmware
1314 */
1315 if (f->changed) {
1316 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1317 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1318 }
1319
1320add_filter_out:
1321 return f;
1322}
1323
1324/**
1325 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1326 * @vsi: the VSI to be searched
1327 * @macaddr: the MAC address
1328 * @vlan: the vlan
b40c82e6 1329 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff
JB		 1330 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1331 **/
1332void i40e_del_filter(struct i40e_vsi *vsi,
1333 u8 *macaddr, s16 vlan,
1334 bool is_vf, bool is_netdev)
1335{
1336 struct i40e_mac_filter *f;
1337
1338 if (!vsi || !macaddr)
1339 return;
1340
1341 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1342 if (!f || f->counter == 0)
1343 return;
1344
1345 if (is_vf) {
1346 if (f->is_vf) {
1347 f->is_vf = false;
1348 f->counter--;
1349 }
1350 } else if (is_netdev) {
1351 if (f->is_netdev) {
1352 f->is_netdev = false;
1353 f->counter--;
1354 }
1355 } else {
b40c82e6 1356 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff
JB		 1357 int min_f = 0;
1358 min_f += (f->is_vf ? 1 : 0);
1359 min_f += (f->is_netdev ? 1 : 0);
1360
1361 if (f->counter > min_f)
1362 f->counter--;
1363 }
1364
1365 /* counter == 0 tells sync_filters_subtask to
1366 * remove the filter from the firmware's list
1367 */
1368 if (f->counter == 0) {
1369 f->changed = true;
1370 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1371 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1372 }
1373}
1374
1375/**
1376 * i40e_set_mac - NDO callback to set mac address
1377 * @netdev: network interface device structure
1378 * @p: pointer to an address structure
1379 *
1380 * Returns 0 on success, negative on failure
1381 **/
38e00438
VD		 1382#ifdef I40E_FCOE
1383int i40e_set_mac(struct net_device *netdev, void *p)
1384#else
41c445ff 1385static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1386#endif
41c445ff
JB		 1387{
1388 struct i40e_netdev_priv *np = netdev_priv(netdev);
1389 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1390 struct i40e_pf *pf = vsi->back;
1391 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1392 struct sockaddr *addr = p;
1393 struct i40e_mac_filter *f;
1394
1395 if (!is_valid_ether_addr(addr->sa_data))
1396 return -EADDRNOTAVAIL;
1397
30650cc5
SN		 1398 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1399 netdev_info(netdev, "already using mac address %pM\n",
1400 addr->sa_data);
1401 return 0;
1402 }
41c445ff 1403
80f6428f
ASJ		 1404 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1405 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1406 return -EADDRNOTAVAIL;
1407
30650cc5
SN		 1408 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1409 netdev_info(netdev, "returning to hw mac address %pM\n",
1410 hw->mac.addr);
1411 else
1412 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1413
41c445ff
JB		 1414 if (vsi->type == I40E_VSI_MAIN) {
1415 i40e_status ret;
1416 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1417 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1418 addr->sa_data, NULL);
1419 if (ret) {
1420 netdev_info(netdev,
1421 "Addr change for Main VSI failed: %d\n",
1422 ret);
1423 return -EADDRNOTAVAIL;
1424 }
41c445ff
JB		 1425 }
1426
30650cc5
SN		 1427 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1428 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1429
30650cc5
SN		 1430 memset(&element, 0, sizeof(element));
1431 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1432 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1433 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1434 } else {
6c8ad1ba
SN		 1435 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1436 false, false);
6c8ad1ba 1437 }
41c445ff 1438
30650cc5
SN		 1439 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1440 struct i40e_aqc_add_macvlan_element_data element;
1441
1442 memset(&element, 0, sizeof(element));
1443 ether_addr_copy(element.mac_addr, hw->mac.addr);
1444 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1445 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1446 } else {
1447 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1448 false, false);
1449 if (f)
1450 f->is_laa = true;
1451 }
1452
1453 i40e_sync_vsi_filters(vsi);
1454 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1455
1456 return 0;
1457}
1458
1459/**
1460 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1461 * @vsi: the VSI being setup
1462 * @ctxt: VSI context structure
1463 * @enabled_tc: Enabled TCs bitmap
1464 * @is_add: True if called before Add VSI
1465 *
1466 * Setup VSI queue mapping for enabled traffic classes.
1467 **/
38e00438
VD		 1468#ifdef I40E_FCOE
1469void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1470 struct i40e_vsi_context *ctxt,
1471 u8 enabled_tc,
1472 bool is_add)
1473#else
41c445ff
JB		 1474static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1475 struct i40e_vsi_context *ctxt,
1476 u8 enabled_tc,
1477 bool is_add)
38e00438 1478#endif
41c445ff
JB		 1479{
1480 struct i40e_pf *pf = vsi->back;
1481 u16 sections = 0;
1482 u8 netdev_tc = 0;
1483 u16 numtc = 0;
1484 u16 qcount;
1485 u8 offset;
1486 u16 qmap;
1487 int i;
4e3b35b0 1488 u16 num_tc_qps = 0;
41c445ff
JB		 1489
1490 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1491 offset = 0;
1492
1493 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1494 /* Find numtc from enabled TC bitmap */
1495 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1496 if (enabled_tc & (1 << i)) /* TC is enabled */
1497 numtc++;
1498 }
1499 if (!numtc) {
1500 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1501 numtc = 1;
1502 }
1503 } else {
1504 /* At least TC0 is enabled in case of non-DCB case */
1505 numtc = 1;
1506 }
1507
1508 vsi->tc_config.numtc = numtc;
1509 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1510 /* Number of queues per enabled TC */
7f9ff476
AS		 1511 /* In MFP case we can have a much lower count of MSIx
1512 * vectors available and so we need to lower the used
1513 * q count.
1514 */
1515 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1516 num_tc_qps = qcount / numtc;
4e3b35b0 1517 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1518
1519 /* Setup queue offset/count for all TCs for given VSI */
1520 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1521 /* See if the given TC is enabled for the given VSI */
1522 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1523 int pow, num_qps;
1524
41c445ff
JB		 1525 switch (vsi->type) {
1526 case I40E_VSI_MAIN:
4e3b35b0 1527 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1528 break;
38e00438
VD		 1529#ifdef I40E_FCOE
1530 case I40E_VSI_FCOE:
1531 qcount = num_tc_qps;
1532 break;
1533#endif
41c445ff
JB		 1534 case I40E_VSI_FDIR:
1535 case I40E_VSI_SRIOV:
1536 case I40E_VSI_VMDQ2:
1537 default:
4e3b35b0 1538 qcount = num_tc_qps;
41c445ff
JB		 1539 WARN_ON(i != 0);
1540 break;
1541 }
4e3b35b0
NP		 1542 vsi->tc_config.tc_info[i].qoffset = offset;
1543 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1544
1e200e4a 1545 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1546 num_qps = qcount;
41c445ff 1547 pow = 0;
4e3b35b0 1548 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1549 pow++;
1550 num_qps >>= 1;
1551 }
1552
1553 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1554 qmap =
1555 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1556 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1557
4e3b35b0 1558 offset += qcount;
41c445ff
JB		 1559 } else {
1560 /* TC is not enabled so set the offset to
1561 * default queue and allocate one queue
1562 * for the given TC.
1563 */
1564 vsi->tc_config.tc_info[i].qoffset = 0;
1565 vsi->tc_config.tc_info[i].qcount = 1;
1566 vsi->tc_config.tc_info[i].netdev_tc = 0;
1567
1568 qmap = 0;
1569 }
1570 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1571 }
1572
1573 /* Set actual Tx/Rx queue pairs */
1574 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1575 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1576 if (vsi->req_queue_pairs > 0)
1577 vsi->num_queue_pairs = vsi->req_queue_pairs;
1578 else
1579 vsi->num_queue_pairs = pf->num_lan_msix;
1580 }
41c445ff
JB		 1581
1582 /* Scheduler section valid can only be set for ADD VSI */
1583 if (is_add) {
1584 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1585
1586 ctxt->info.up_enable_bits = enabled_tc;
1587 }
1588 if (vsi->type == I40E_VSI_SRIOV) {
1589 ctxt->info.mapping_flags |=
1590 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1591 for (i = 0; i < vsi->num_queue_pairs; i++)
1592 ctxt->info.queue_mapping[i] =
1593 cpu_to_le16(vsi->base_queue + i);
1594 } else {
1595 ctxt->info.mapping_flags |=
1596 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1597 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1598 }
1599 ctxt->info.valid_sections |= cpu_to_le16(sections);
1600}
1601
1602/**
1603 * i40e_set_rx_mode - NDO callback to set the netdev filters
1604 * @netdev: network interface device structure
1605 **/
38e00438
VD		 1606#ifdef I40E_FCOE
1607void i40e_set_rx_mode(struct net_device *netdev)
1608#else
41c445ff 1609static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1610#endif
41c445ff
JB		 1611{
1612 struct i40e_netdev_priv *np = netdev_priv(netdev);
1613 struct i40e_mac_filter *f, *ftmp;
1614 struct i40e_vsi *vsi = np->vsi;
1615 struct netdev_hw_addr *uca;
1616 struct netdev_hw_addr *mca;
1617 struct netdev_hw_addr *ha;
1618
1619 /* add addr if not already in the filter list */
1620 netdev_for_each_uc_addr(uca, netdev) {
1621 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1622 if (i40e_is_vsi_in_vlan(vsi))
1623 i40e_put_mac_in_vlan(vsi, uca->addr,
1624 false, true);
1625 else
1626 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1627 false, true);
1628 }
1629 }
1630
1631 netdev_for_each_mc_addr(mca, netdev) {
1632 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1633 if (i40e_is_vsi_in_vlan(vsi))
1634 i40e_put_mac_in_vlan(vsi, mca->addr,
1635 false, true);
1636 else
1637 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1638 false, true);
1639 }
1640 }
1641
1642 /* remove filter if not in netdev list */
1643 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1644 bool found = false;
1645
1646 if (!f->is_netdev)
1647 continue;
1648
1649 if (is_multicast_ether_addr(f->macaddr)) {
1650 netdev_for_each_mc_addr(mca, netdev) {
1651 if (ether_addr_equal(mca->addr, f->macaddr)) {
1652 found = true;
1653 break;
1654 }
1655 }
1656 } else {
1657 netdev_for_each_uc_addr(uca, netdev) {
1658 if (ether_addr_equal(uca->addr, f->macaddr)) {
1659 found = true;
1660 break;
1661 }
1662 }
1663
1664 for_each_dev_addr(netdev, ha) {
1665 if (ether_addr_equal(ha->addr, f->macaddr)) {
1666 found = true;
1667 break;
1668 }
1669 }
1670 }
1671 if (!found)
1672 i40e_del_filter(
1673 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1674 }
1675
1676 /* check for other flag changes */
1677 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1678 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1679 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1680 }
1681}
1682
1683/**
1684 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1685 * @vsi: ptr to the VSI
1686 *
1687 * Push any outstanding VSI filter changes through the AdminQ.
1688 *
1689 * Returns 0 or error value
1690 **/
1691int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1692{
1693 struct i40e_mac_filter *f, *ftmp;
1694 bool promisc_forced_on = false;
1695 bool add_happened = false;
1696 int filter_list_len = 0;
1697 u32 changed_flags = 0;
dcae29be 1698 i40e_status aq_ret = 0;
41c445ff
JB		 1699 struct i40e_pf *pf;
1700 int num_add = 0;
1701 int num_del = 0;
1702 u16 cmd_flags;
1703
1704 /* empty array typed pointers, kcalloc later */
1705 struct i40e_aqc_add_macvlan_element_data *add_list;
1706 struct i40e_aqc_remove_macvlan_element_data *del_list;
1707
1708 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1709 usleep_range(1000, 2000);
1710 pf = vsi->back;
1711
1712 if (vsi->netdev) {
1713 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1714 vsi->current_netdev_flags = vsi->netdev->flags;
1715 }
1716
1717 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1718 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1719
1720 filter_list_len = pf->hw.aq.asq_buf_size /
1721 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1722 del_list = kcalloc(filter_list_len,
1723 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1724 GFP_KERNEL);
1725 if (!del_list)
1726 return -ENOMEM;
1727
1728 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1729 if (!f->changed)
1730 continue;
1731
1732 if (f->counter != 0)
1733 continue;
1734 f->changed = false;
1735 cmd_flags = 0;
1736
1737 /* add to delete list */
9a173901 1738 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1739 del_list[num_del].vlan_tag =
1740 cpu_to_le16((u16)(f->vlan ==
1741 I40E_VLAN_ANY ? 0 : f->vlan));
1742
41c445ff
JB		 1743 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1744 del_list[num_del].flags = cmd_flags;
1745 num_del++;
1746
1747 /* unlink from filter list */
1748 list_del(&f->list);
1749 kfree(f);
1750
1751 /* flush a full buffer */
1752 if (num_del == filter_list_len) {
dcae29be 1753 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1754 vsi->seid, del_list, num_del,
1755 NULL);
1756 num_del = 0;
1757 memset(del_list, 0, sizeof(*del_list));
1758
fdfe9cbe
SN		 1759 if (aq_ret &&
1760 pf->hw.aq.asq_last_status !=
1761 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1762 dev_info(&pf->pdev->dev,
1763 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1764 aq_ret,
41c445ff
JB		 1765 pf->hw.aq.asq_last_status);
1766 }
1767 }
1768 if (num_del) {
dcae29be 1769 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1770 del_list, num_del, NULL);
1771 num_del = 0;
1772
fdfe9cbe
SN		 1773 if (aq_ret &&
1774 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1775 dev_info(&pf->pdev->dev,
1776 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1777 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1778 }
1779
1780 kfree(del_list);
1781 del_list = NULL;
1782
1783 /* do all the adds now */
1784 filter_list_len = pf->hw.aq.asq_buf_size /
1785 sizeof(struct i40e_aqc_add_macvlan_element_data),
1786 add_list = kcalloc(filter_list_len,
1787 sizeof(struct i40e_aqc_add_macvlan_element_data),
1788 GFP_KERNEL);
1789 if (!add_list)
1790 return -ENOMEM;
1791
1792 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1793 if (!f->changed)
1794 continue;
1795
1796 if (f->counter == 0)
1797 continue;
1798 f->changed = false;
1799 add_happened = true;
1800 cmd_flags = 0;
1801
1802 /* add to add array */
9a173901 1803 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1804 add_list[num_add].vlan_tag =
1805 cpu_to_le16(
1806 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1807 add_list[num_add].queue_number = 0;
1808
1809 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1810 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1811 num_add++;
1812
1813 /* flush a full buffer */
1814 if (num_add == filter_list_len) {
dcae29be
JB		 1815 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1816 add_list, num_add,
1817 NULL);
41c445ff
JB		 1818 num_add = 0;
1819
dcae29be 1820 if (aq_ret)
41c445ff
JB		 1821 break;
1822 memset(add_list, 0, sizeof(*add_list));
1823 }
1824 }
1825 if (num_add) {
dcae29be
JB		 1826 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1827 add_list, num_add, NULL);
41c445ff
JB		 1828 num_add = 0;
1829 }
1830 kfree(add_list);
1831 add_list = NULL;
1832
30650cc5
SN		 1833 if (add_happened && aq_ret &&
1834 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1835 dev_info(&pf->pdev->dev,
1836 "add filter failed, err %d, aq_err %d\n",
dcae29be 1837 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1838 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1839 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1840 &vsi->state)) {
1841 promisc_forced_on = true;
1842 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1843 &vsi->state);
1844 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1845 }
1846 }
1847 }
1848
1849 /* check for changes in promiscuous modes */
1850 if (changed_flags & IFF_ALLMULTI) {
1851 bool cur_multipromisc;
1852 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1853 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1854 vsi->seid,
1855 cur_multipromisc,
1856 NULL);
1857 if (aq_ret)
41c445ff
JB		 1858 dev_info(&pf->pdev->dev,
1859 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1860 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1861 }
1862 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1863 bool cur_promisc;
1864 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1865 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1866 &vsi->state));
dcae29be
JB		 1867 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1868 vsi->seid,
1869 cur_promisc, NULL);
1870 if (aq_ret)
41c445ff
JB		 1871 dev_info(&pf->pdev->dev,
1872 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1873 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1874 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1875 vsi->seid,
1876 cur_promisc, NULL);
1877 if (aq_ret)
1878 dev_info(&pf->pdev->dev,
1879 "set brdcast promisc failed, err %d, aq_err %d\n",
1880 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1881 }
1882
1883 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1884 return 0;
1885}
1886
1887/**
1888 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1889 * @pf: board private structure
1890 **/
1891static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1892{
1893 int v;
1894
1895 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1896 return;
1897 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1898
505682cd 1899 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1900 if (pf->vsi[v] &&
1901 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1902 i40e_sync_vsi_filters(pf->vsi[v]);
1903 }
1904}
1905
1906/**
1907 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1908 * @netdev: network interface device structure
1909 * @new_mtu: new value for maximum frame size
1910 *
1911 * Returns 0 on success, negative on failure
1912 **/
1913static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1914{
1915 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1916 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1917 struct i40e_vsi *vsi = np->vsi;
1918
1919 /* MTU < 68 is an error and causes problems on some kernels */
1920 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1921 return -EINVAL;
1922
1923 netdev_info(netdev, "changing MTU from %d to %d\n",
1924 netdev->mtu, new_mtu);
1925 netdev->mtu = new_mtu;
1926 if (netif_running(netdev))
1927 i40e_vsi_reinit_locked(vsi);
1928
1929 return 0;
1930}
1931
beb0dff1
JK		 1932/**
1933 * i40e_ioctl - Access the hwtstamp interface
1934 * @netdev: network interface device structure
1935 * @ifr: interface request data
1936 * @cmd: ioctl command
1937 **/
1938int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1939{
1940 struct i40e_netdev_priv *np = netdev_priv(netdev);
1941 struct i40e_pf *pf = np->vsi->back;
1942
1943 switch (cmd) {
1944 case SIOCGHWTSTAMP:
1945 return i40e_ptp_get_ts_config(pf, ifr);
1946 case SIOCSHWTSTAMP:
1947 return i40e_ptp_set_ts_config(pf, ifr);
1948 default:
1949 return -EOPNOTSUPP;
1950 }
1951}
1952
41c445ff
JB		 1953/**
1954 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1955 * @vsi: the vsi being adjusted
1956 **/
1957void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1958{
1959 struct i40e_vsi_context ctxt;
1960 i40e_status ret;
1961
1962 if ((vsi->info.valid_sections &
1963 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1964 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1965 return; /* already enabled */
1966
1967 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1968 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1969 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1970
1971 ctxt.seid = vsi->seid;
1a2f6248 1972 ctxt.info = vsi->info;
41c445ff
JB		 1973 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1974 if (ret) {
1975 dev_info(&vsi->back->pdev->dev,
1976 "%s: update vsi failed, aq_err=%d\n",
1977 __func__, vsi->back->hw.aq.asq_last_status);
1978 }
1979}
1980
1981/**
1982 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1983 * @vsi: the vsi being adjusted
1984 **/
1985void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1986{
1987 struct i40e_vsi_context ctxt;
1988 i40e_status ret;
1989
1990 if ((vsi->info.valid_sections &
1991 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1992 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1993 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1994 return; /* already disabled */
1995
1996 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1997 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1998 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1999
2000 ctxt.seid = vsi->seid;
1a2f6248 2001 ctxt.info = vsi->info;
41c445ff
JB		 2002 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2003 if (ret) {
2004 dev_info(&vsi->back->pdev->dev,
2005 "%s: update vsi failed, aq_err=%d\n",
2006 __func__, vsi->back->hw.aq.asq_last_status);
2007 }
2008}
2009
2010/**
2011 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2012 * @netdev: network interface to be adjusted
2013 * @features: netdev features to test if VLAN offload is enabled or not
2014 **/
2015static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2016{
2017 struct i40e_netdev_priv *np = netdev_priv(netdev);
2018 struct i40e_vsi *vsi = np->vsi;
2019
2020 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2021 i40e_vlan_stripping_enable(vsi);
2022 else
2023 i40e_vlan_stripping_disable(vsi);
2024}
2025
2026/**
2027 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2028 * @vsi: the vsi being configured
2029 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2030 **/
2031int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2032{
2033 struct i40e_mac_filter *f, *add_f;
2034 bool is_netdev, is_vf;
41c445ff
JB		 2035
2036 is_vf = (vsi->type == I40E_VSI_SRIOV);
2037 is_netdev = !!(vsi->netdev);
2038
2039 if (is_netdev) {
2040 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2041 is_vf, is_netdev);
2042 if (!add_f) {
2043 dev_info(&vsi->back->pdev->dev,
2044 "Could not add vlan filter %d for %pM\n",
2045 vid, vsi->netdev->dev_addr);
2046 return -ENOMEM;
2047 }
2048 }
2049
2050 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2051 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2052 if (!add_f) {
2053 dev_info(&vsi->back->pdev->dev,
2054 "Could not add vlan filter %d for %pM\n",
2055 vid, f->macaddr);
2056 return -ENOMEM;
2057 }
2058 }
2059
41c445ff
JB		 2060 /* Now if we add a vlan tag, make sure to check if it is the first
2061 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2062 * with 0, so we now accept untagged and specified tagged traffic
2063 * (and not any taged and untagged)
2064 */
2065 if (vid > 0) {
2066 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2067 I40E_VLAN_ANY,
2068 is_vf, is_netdev)) {
2069 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2070 I40E_VLAN_ANY, is_vf, is_netdev);
2071 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2072 is_vf, is_netdev);
2073 if (!add_f) {
2074 dev_info(&vsi->back->pdev->dev,
2075 "Could not add filter 0 for %pM\n",
2076 vsi->netdev->dev_addr);
2077 return -ENOMEM;
2078 }
2079 }
8d82a7c5 2080 }
41c445ff 2081
8d82a7c5
GR		 2082 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2083 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2084 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2085 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2086 is_vf, is_netdev)) {
2087 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2088 is_vf, is_netdev);
2089 add_f = i40e_add_filter(vsi, f->macaddr,
2090 0, is_vf, is_netdev);
2091 if (!add_f) {
2092 dev_info(&vsi->back->pdev->dev,
2093 "Could not add filter 0 for %pM\n",
2094 f->macaddr);
2095 return -ENOMEM;
2096 }
2097 }
2098 }
41c445ff
JB		 2099 }
2100
80f6428f
ASJ		 2101 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2102 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2103 return 0;
2104
2105 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2106}
2107
2108/**
2109 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2110 * @vsi: the vsi being configured
2111 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2112 *
2113 * Return: 0 on success or negative otherwise
41c445ff
JB		 2114 **/
2115int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2116{
2117 struct net_device *netdev = vsi->netdev;
2118 struct i40e_mac_filter *f, *add_f;
2119 bool is_vf, is_netdev;
2120 int filter_count = 0;
41c445ff
JB		 2121
2122 is_vf = (vsi->type == I40E_VSI_SRIOV);
2123 is_netdev = !!(netdev);
2124
2125 if (is_netdev)
2126 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2127
2128 list_for_each_entry(f, &vsi->mac_filter_list, list)
2129 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2130
41c445ff
JB		 2131 /* go through all the filters for this VSI and if there is only
2132 * vid == 0 it means there are no other filters, so vid 0 must
2133 * be replaced with -1. This signifies that we should from now
2134 * on accept any traffic (with any tag present, or untagged)
2135 */
2136 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2137 if (is_netdev) {
2138 if (f->vlan &&
2139 ether_addr_equal(netdev->dev_addr, f->macaddr))
2140 filter_count++;
2141 }
2142
2143 if (f->vlan)
2144 filter_count++;
2145 }
2146
2147 if (!filter_count && is_netdev) {
2148 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2149 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2150 is_vf, is_netdev);
2151 if (!f) {
2152 dev_info(&vsi->back->pdev->dev,
2153 "Could not add filter %d for %pM\n",
2154 I40E_VLAN_ANY, netdev->dev_addr);
2155 return -ENOMEM;
2156 }
2157 }
2158
2159 if (!filter_count) {
2160 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2161 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2162 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2163 is_vf, is_netdev);
2164 if (!add_f) {
2165 dev_info(&vsi->back->pdev->dev,
2166 "Could not add filter %d for %pM\n",
2167 I40E_VLAN_ANY, f->macaddr);
2168 return -ENOMEM;
2169 }
2170 }
2171 }
2172
80f6428f
ASJ		 2173 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2174 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2175 return 0;
2176
41c445ff
JB		 2177 return i40e_sync_vsi_filters(vsi);
2178}
2179
2180/**
2181 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2182 * @netdev: network interface to be adjusted
2183 * @vid: vlan id to be added
078b5876
JB		 2184 *
2185 * net_device_ops implementation for adding vlan ids
41c445ff 2186 **/
38e00438
VD		 2187#ifdef I40E_FCOE
2188int i40e_vlan_rx_add_vid(struct net_device *netdev,
2189 __always_unused __be16 proto, u16 vid)
2190#else
41c445ff
JB		 2191static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2192 __always_unused __be16 proto, u16 vid)
38e00438 2193#endif
41c445ff
JB		 2194{
2195 struct i40e_netdev_priv *np = netdev_priv(netdev);
2196 struct i40e_vsi *vsi = np->vsi;
078b5876 2197 int ret = 0;
41c445ff
JB		 2198
2199 if (vid > 4095)
078b5876
JB		 2200 return -EINVAL;
2201
2202 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2203
6982d429
ASJ		 2204 /* If the network stack called us with vid = 0 then
2205 * it is asking to receive priority tagged packets with
2206 * vlan id 0. Our HW receives them by default when configured
2207 * to receive untagged packets so there is no need to add an
2208 * extra filter for vlan 0 tagged packets.
41c445ff 2209 */
6982d429
ASJ		 2210 if (vid)
2211 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2212
078b5876
JB		 2213 if (!ret && (vid < VLAN_N_VID))
2214 set_bit(vid, vsi->active_vlans);
41c445ff 2215
078b5876 2216 return ret;
41c445ff
JB		 2217}
2218
2219/**
2220 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2221 * @netdev: network interface to be adjusted
2222 * @vid: vlan id to be removed
078b5876 2223 *
fdfd943e 2224 * net_device_ops implementation for removing vlan ids
41c445ff 2225 **/
38e00438
VD		 2226#ifdef I40E_FCOE
2227int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2228 __always_unused __be16 proto, u16 vid)
2229#else
41c445ff
JB		 2230static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2231 __always_unused __be16 proto, u16 vid)
38e00438 2232#endif
41c445ff
JB		 2233{
2234 struct i40e_netdev_priv *np = netdev_priv(netdev);
2235 struct i40e_vsi *vsi = np->vsi;
2236
078b5876
JB		 2237 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2238
41c445ff
JB		 2239 /* return code is ignored as there is nothing a user
2240 * can do about failure to remove and a log message was
078b5876 2241 * already printed from the other function
41c445ff
JB		 2242 */
2243 i40e_vsi_kill_vlan(vsi, vid);
2244
2245 clear_bit(vid, vsi->active_vlans);
078b5876 2246
41c445ff
JB		 2247 return 0;
2248}
2249
2250/**
2251 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2252 * @vsi: the vsi being brought back up
2253 **/
2254static void i40e_restore_vlan(struct i40e_vsi *vsi)
2255{
2256 u16 vid;
2257
2258 if (!vsi->netdev)
2259 return;
2260
2261 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2262
2263 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2264 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2265 vid);
2266}
2267
2268/**
2269 * i40e_vsi_add_pvid - Add pvid for the VSI
2270 * @vsi: the vsi being adjusted
2271 * @vid: the vlan id to set as a PVID
2272 **/
dcae29be 2273int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2274{
2275 struct i40e_vsi_context ctxt;
dcae29be 2276 i40e_status aq_ret;
41c445ff
JB		 2277
2278 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2279 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2280 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2281 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2282 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2283
2284 ctxt.seid = vsi->seid;
1a2f6248 2285 ctxt.info = vsi->info;
dcae29be
JB		 2286 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2287 if (aq_ret) {
41c445ff
JB		 2288 dev_info(&vsi->back->pdev->dev,
2289 "%s: update vsi failed, aq_err=%d\n",
2290 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2291 return -ENOENT;
41c445ff
JB		 2292 }
2293
dcae29be 2294 return 0;
41c445ff
JB		 2295}
2296
2297/**
2298 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2299 * @vsi: the vsi being adjusted
2300 *
2301 * Just use the vlan_rx_register() service to put it back to normal
2302 **/
2303void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2304{
6c12fcbf
GR		 2305 i40e_vlan_stripping_disable(vsi);
2306
41c445ff 2307 vsi->info.pvid = 0;
41c445ff
JB		 2308}
2309
2310/**
2311 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2312 * @vsi: ptr to the VSI
2313 *
2314 * If this function returns with an error, then it's possible one or
2315 * more of the rings is populated (while the rest are not). It is the
2316 * callers duty to clean those orphaned rings.
2317 *
2318 * Return 0 on success, negative on failure
2319 **/
2320static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2321{
2322 int i, err = 0;
2323
2324 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2325 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2326
2327 return err;
2328}
2329
2330/**
2331 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2332 * @vsi: ptr to the VSI
2333 *
2334 * Free VSI's transmit software resources
2335 **/
2336static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2337{
2338 int i;
2339
8e9dca53
GR		 2340 if (!vsi->tx_rings)
2341 return;
2342
41c445ff 2343 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2344 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2345 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2346}
2347
2348/**
2349 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2350 * @vsi: ptr to the VSI
2351 *
2352 * If this function returns with an error, then it's possible one or
2353 * more of the rings is populated (while the rest are not). It is the
2354 * callers duty to clean those orphaned rings.
2355 *
2356 * Return 0 on success, negative on failure
2357 **/
2358static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2359{
2360 int i, err = 0;
2361
2362 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2363 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2364#ifdef I40E_FCOE
2365 i40e_fcoe_setup_ddp_resources(vsi);
2366#endif
41c445ff
JB		 2367 return err;
2368}
2369
2370/**
2371 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2372 * @vsi: ptr to the VSI
2373 *
2374 * Free all receive software resources
2375 **/
2376static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2377{
2378 int i;
2379
8e9dca53
GR		 2380 if (!vsi->rx_rings)
2381 return;
2382
41c445ff 2383 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2384 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2385 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2386#ifdef I40E_FCOE
2387 i40e_fcoe_free_ddp_resources(vsi);
2388#endif
41c445ff
JB		 2389}
2390
3ffa037d
NP		 2391/**
2392 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2393 * @ring: The Tx ring to configure
2394 *
2395 * This enables/disables XPS for a given Tx descriptor ring
2396 * based on the TCs enabled for the VSI that ring belongs to.
2397 **/
2398static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2399{
2400 struct i40e_vsi *vsi = ring->vsi;
2401 cpumask_var_t mask;
2402
9a660eea
JB		 2403 if (!ring->q_vector || !ring->netdev)
2404 return;
2405
2406 /* Single TC mode enable XPS */
2407 if (vsi->tc_config.numtc <= 1) {
2408 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2409 netif_set_xps_queue(ring->netdev,
2410 &ring->q_vector->affinity_mask,
2411 ring->queue_index);
9a660eea
JB		 2412 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2413 /* Disable XPS to allow selection based on TC */
2414 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2415 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2416 free_cpumask_var(mask);
3ffa037d
NP		 2417 }
2418}
2419
41c445ff
JB		 2420/**
2421 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2422 * @ring: The Tx ring to configure
2423 *
2424 * Configure the Tx descriptor ring in the HMC context.
2425 **/
2426static int i40e_configure_tx_ring(struct i40e_ring *ring)
2427{
2428 struct i40e_vsi *vsi = ring->vsi;
2429 u16 pf_q = vsi->base_queue + ring->queue_index;
2430 struct i40e_hw *hw = &vsi->back->hw;
2431 struct i40e_hmc_obj_txq tx_ctx;
2432 i40e_status err = 0;
2433 u32 qtx_ctl = 0;
2434
2435 /* some ATR related tx ring init */
60ea5f83 2436 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2437 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2438 ring->atr_count = 0;
2439 } else {
2440 ring->atr_sample_rate = 0;
2441 }
2442
3ffa037d
NP		 2443 /* configure XPS */
2444 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2445
2446 /* clear the context structure first */
2447 memset(&tx_ctx, 0, sizeof(tx_ctx));
2448
2449 tx_ctx.new_context = 1;
2450 tx_ctx.base = (ring->dma / 128);
2451 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2452 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2453 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2454#ifdef I40E_FCOE
2455 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2456#endif
beb0dff1 2457 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2458 /* FDIR VSI tx ring can still use RS bit and writebacks */
2459 if (vsi->type != I40E_VSI_FDIR)
2460 tx_ctx.head_wb_ena = 1;
2461 tx_ctx.head_wb_addr = ring->dma +
2462 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2463
2464 /* As part of VSI creation/update, FW allocates certain
2465 * Tx arbitration queue sets for each TC enabled for
2466 * the VSI. The FW returns the handles to these queue
2467 * sets as part of the response buffer to Add VSI,
2468 * Update VSI, etc. AQ commands. It is expected that
2469 * these queue set handles be associated with the Tx
2470 * queues by the driver as part of the TX queue context
2471 * initialization. This has to be done regardless of
2472 * DCB as by default everything is mapped to TC0.
2473 */
2474 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2475 tx_ctx.rdylist_act = 0;
2476
2477 /* clear the context in the HMC */
2478 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2479 if (err) {
2480 dev_info(&vsi->back->pdev->dev,
2481 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2482 ring->queue_index, pf_q, err);
2483 return -ENOMEM;
2484 }
2485
2486 /* set the context in the HMC */
2487 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2488 if (err) {
2489 dev_info(&vsi->back->pdev->dev,
2490 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2491 ring->queue_index, pf_q, err);
2492 return -ENOMEM;
2493 }
2494
2495 /* Now associate this queue with this PCI function */
7a28d885 2496 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2497 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2498 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2499 I40E_QTX_CTL_VFVM_INDX_MASK;
2500 } else {
9d8bf547 2501 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2502 }
2503
13fd9774
SN		 2504 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2505 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2506 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2507 i40e_flush(hw);
2508
2509 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2510
2511 /* cache tail off for easier writes later */
2512 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2513
2514 return 0;
2515}
2516
2517/**
2518 * i40e_configure_rx_ring - Configure a receive ring context
2519 * @ring: The Rx ring to configure
2520 *
2521 * Configure the Rx descriptor ring in the HMC context.
2522 **/
2523static int i40e_configure_rx_ring(struct i40e_ring *ring)
2524{
2525 struct i40e_vsi *vsi = ring->vsi;
2526 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2527 u16 pf_q = vsi->base_queue + ring->queue_index;
2528 struct i40e_hw *hw = &vsi->back->hw;
2529 struct i40e_hmc_obj_rxq rx_ctx;
2530 i40e_status err = 0;
2531
2532 ring->state = 0;
2533
2534 /* clear the context structure first */
2535 memset(&rx_ctx, 0, sizeof(rx_ctx));
2536
2537 ring->rx_buf_len = vsi->rx_buf_len;
2538 ring->rx_hdr_len = vsi->rx_hdr_len;
2539
2540 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2541 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2542
2543 rx_ctx.base = (ring->dma / 128);
2544 rx_ctx.qlen = ring->count;
2545
2546 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2547 set_ring_16byte_desc_enabled(ring);
2548 rx_ctx.dsize = 0;
2549 } else {
2550 rx_ctx.dsize = 1;
2551 }
2552
2553 rx_ctx.dtype = vsi->dtype;
2554 if (vsi->dtype) {
2555 set_ring_ps_enabled(ring);
2556 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2557 I40E_RX_SPLIT_IP |
2558 I40E_RX_SPLIT_TCP_UDP |
2559 I40E_RX_SPLIT_SCTP;
2560 } else {
2561 rx_ctx.hsplit_0 = 0;
2562 }
2563
2564 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2565 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2566 if (hw->revision_id == 0)
2567 rx_ctx.lrxqthresh = 0;
2568 else
2569 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2570 rx_ctx.crcstrip = 1;
2571 rx_ctx.l2tsel = 1;
2572 rx_ctx.showiv = 1;
38e00438
VD		 2573#ifdef I40E_FCOE
2574 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2575#endif
acb3676b
CS		 2576 /* set the prefena field to 1 because the manual says to */
2577 rx_ctx.prefena = 1;
41c445ff
JB		 2578
2579 /* clear the context in the HMC */
2580 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2581 if (err) {
2582 dev_info(&vsi->back->pdev->dev,
2583 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2584 ring->queue_index, pf_q, err);
2585 return -ENOMEM;
2586 }
2587
2588 /* set the context in the HMC */
2589 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2590 if (err) {
2591 dev_info(&vsi->back->pdev->dev,
2592 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2593 ring->queue_index, pf_q, err);
2594 return -ENOMEM;
2595 }
2596
2597 /* cache tail for quicker writes, and clear the reg before use */
2598 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2599 writel(0, ring->tail);
2600
a132af24
MW		 2601 if (ring_is_ps_enabled(ring)) {
2602 i40e_alloc_rx_headers(ring);
2603 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2604 } else {
2605 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2606 }
41c445ff
JB		 2607
2608 return 0;
2609}
2610
2611/**
2612 * i40e_vsi_configure_tx - Configure the VSI for Tx
2613 * @vsi: VSI structure describing this set of rings and resources
2614 *
2615 * Configure the Tx VSI for operation.
2616 **/
2617static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2618{
2619 int err = 0;
2620 u16 i;
2621
9f65e15b
AD		 2622 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2623 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2624
2625 return err;
2626}
2627
2628/**
2629 * i40e_vsi_configure_rx - Configure the VSI for Rx
2630 * @vsi: the VSI being configured
2631 *
2632 * Configure the Rx VSI for operation.
2633 **/
2634static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2635{
2636 int err = 0;
2637 u16 i;
2638
2639 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2640 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2641 + ETH_FCS_LEN + VLAN_HLEN;
2642 else
2643 vsi->max_frame = I40E_RXBUFFER_2048;
2644
2645 /* figure out correct receive buffer length */
2646 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2647 I40E_FLAG_RX_PS_ENABLED)) {
2648 case I40E_FLAG_RX_1BUF_ENABLED:
2649 vsi->rx_hdr_len = 0;
2650 vsi->rx_buf_len = vsi->max_frame;
2651 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2652 break;
2653 case I40E_FLAG_RX_PS_ENABLED:
2654 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2655 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2656 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2657 break;
2658 default:
2659 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2660 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2661 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2662 break;
2663 }
2664
38e00438
VD		 2665#ifdef I40E_FCOE
2666 /* setup rx buffer for FCoE */
2667 if ((vsi->type == I40E_VSI_FCOE) &&
2668 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2669 vsi->rx_hdr_len = 0;
2670 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2671 vsi->max_frame = I40E_RXBUFFER_3072;
2672 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2673 }
2674
2675#endif /* I40E_FCOE */
41c445ff
JB		 2676 /* round up for the chip's needs */
2677 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2678 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2679 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2680 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2681
2682 /* set up individual rings */
2683 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2684 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2685
2686 return err;
2687}
2688
2689/**
2690 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2691 * @vsi: ptr to the VSI
2692 **/
2693static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2694{
e7046ee1 2695 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2696 u16 qoffset, qcount;
2697 int i, n;
2698
cd238a3e
PN		 2699 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2700 /* Reset the TC information */
2701 for (i = 0; i < vsi->num_queue_pairs; i++) {
2702 rx_ring = vsi->rx_rings[i];
2703 tx_ring = vsi->tx_rings[i];
2704 rx_ring->dcb_tc = 0;
2705 tx_ring->dcb_tc = 0;
2706 }
2707 }
41c445ff
JB		 2708
2709 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2710 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2711 continue;
2712
2713 qoffset = vsi->tc_config.tc_info[n].qoffset;
2714 qcount = vsi->tc_config.tc_info[n].qcount;
2715 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2716 rx_ring = vsi->rx_rings[i];
2717 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2718 rx_ring->dcb_tc = n;
2719 tx_ring->dcb_tc = n;
2720 }
2721 }
2722}
2723
2724/**
2725 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2726 * @vsi: ptr to the VSI
2727 **/
2728static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2729{
2730 if (vsi->netdev)
2731 i40e_set_rx_mode(vsi->netdev);
2732}
2733
17a73f6b
JG		 2734/**
2735 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2736 * @vsi: Pointer to the targeted VSI
2737 *
2738 * This function replays the hlist on the hw where all the SB Flow Director
2739 * filters were saved.
2740 **/
2741static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2742{
2743 struct i40e_fdir_filter *filter;
2744 struct i40e_pf *pf = vsi->back;
2745 struct hlist_node *node;
2746
55a5e60b
ASJ		 2747 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2748 return;
2749
17a73f6b
JG		 2750 hlist_for_each_entry_safe(filter, node,
2751 &pf->fdir_filter_list, fdir_node) {
2752 i40e_add_del_fdir(vsi, filter, true);
2753 }
2754}
2755
41c445ff
JB		 2756/**
2757 * i40e_vsi_configure - Set up the VSI for action
2758 * @vsi: the VSI being configured
2759 **/
2760static int i40e_vsi_configure(struct i40e_vsi *vsi)
2761{
2762 int err;
2763
2764 i40e_set_vsi_rx_mode(vsi);
2765 i40e_restore_vlan(vsi);
2766 i40e_vsi_config_dcb_rings(vsi);
2767 err = i40e_vsi_configure_tx(vsi);
2768 if (!err)
2769 err = i40e_vsi_configure_rx(vsi);
2770
2771 return err;
2772}
2773
2774/**
2775 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2776 * @vsi: the VSI being configured
2777 **/
2778static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2779{
2780 struct i40e_pf *pf = vsi->back;
2781 struct i40e_q_vector *q_vector;
2782 struct i40e_hw *hw = &pf->hw;
2783 u16 vector;
2784 int i, q;
2785 u32 val;
2786 u32 qp;
2787
2788 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2789 * and PFINT_LNKLSTn registers, e.g.:
2790 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2791 */
2792 qp = vsi->base_queue;
2793 vector = vsi->base_vector;
493fb300
AD		 2794 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2795 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2796 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2797 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2798 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2799 q_vector->rx.itr);
2800 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2801 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2802 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2803 q_vector->tx.itr);
2804
2805 /* Linked list for the queuepairs assigned to this vector */
2806 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2807 for (q = 0; q < q_vector->num_ringpairs; q++) {
2808 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2809 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2810 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2811 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2812 (I40E_QUEUE_TYPE_TX
2813 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2814
2815 wr32(hw, I40E_QINT_RQCTL(qp), val);
2816
2817 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2818 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2819 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2820 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2821 (I40E_QUEUE_TYPE_RX
2822 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2823
2824 /* Terminate the linked list */
2825 if (q == (q_vector->num_ringpairs - 1))
2826 val |= (I40E_QUEUE_END_OF_LIST
2827 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2828
2829 wr32(hw, I40E_QINT_TQCTL(qp), val);
2830 qp++;
2831 }
2832 }
2833
2834 i40e_flush(hw);
2835}
2836
2837/**
2838 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2839 * @hw: ptr to the hardware info
2840 **/
ab437b5a 2841static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2842{
ab437b5a 2843 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2844 u32 val;
2845
2846 /* clear things first */
2847 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2848 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2849
2850 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2851 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2852 I40E_PFINT_ICR0_ENA_GRST_MASK |
2853 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2854 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2855 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2856 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2857 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2858
ab437b5a
JK		 2859 if (pf->flags & I40E_FLAG_PTP)
2860 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2861
41c445ff
JB		 2862 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2863
2864 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2865 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2866 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2867
2868 /* OTHER_ITR_IDX = 0 */
2869 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2870}
2871
2872/**
2873 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2874 * @vsi: the VSI being configured
2875 **/
2876static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2877{
493fb300 2878 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2879 struct i40e_pf *pf = vsi->back;
2880 struct i40e_hw *hw = &pf->hw;
2881 u32 val;
2882
2883 /* set the ITR configuration */
2884 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2885 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2886 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2887 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2888 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2889 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2890
ab437b5a 2891 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 2892
2893 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2894 wr32(hw, I40E_PFINT_LNKLST0, 0);
2895
f29eaa3d 2896 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2897 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2898 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2899 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2900
2901 wr32(hw, I40E_QINT_RQCTL(0), val);
2902
2903 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2904 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2905 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2906
2907 wr32(hw, I40E_QINT_TQCTL(0), val);
2908 i40e_flush(hw);
2909}
2910
2ef28cfb
MW		 2911/**
2912 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2913 * @pf: board private structure
2914 **/
2915void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2916{
2917 struct i40e_hw *hw = &pf->hw;
2918
2919 wr32(hw, I40E_PFINT_DYN_CTL0,
2920 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2921 i40e_flush(hw);
2922}
2923
41c445ff
JB		 2924/**
2925 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2926 * @pf: board private structure
2927 **/
116a57d4 2928void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2929{
2930 struct i40e_hw *hw = &pf->hw;
2931 u32 val;
2932
2933 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2934 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2935 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2936
2937 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2938 i40e_flush(hw);
2939}
2940
2941/**
2942 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2943 * @vsi: pointer to a vsi
2944 * @vector: enable a particular Hw Interrupt vector
2945 **/
2946void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2947{
2948 struct i40e_pf *pf = vsi->back;
2949 struct i40e_hw *hw = &pf->hw;
2950 u32 val;
2951
2952 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2953 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2954 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2955 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2956 /* skip the flush */
41c445ff
JB		 2957}
2958
5c2cebda
CW		 2959/**
2960 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2961 * @vsi: pointer to a vsi
03147773 2962 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 2963 **/
2964void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2965{
2966 struct i40e_pf *pf = vsi->back;
2967 struct i40e_hw *hw = &pf->hw;
2968 u32 val;
2969
2970 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2971 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2972 i40e_flush(hw);
2973}
2974
41c445ff
JB		 2975/**
2976 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2977 * @irq: interrupt number
2978 * @data: pointer to a q_vector
2979 **/
2980static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2981{
2982 struct i40e_q_vector *q_vector = data;
2983
cd0b6fa6 2984 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2985 return IRQ_HANDLED;
2986
2987 napi_schedule(&q_vector->napi);
2988
2989 return IRQ_HANDLED;
2990}
2991
41c445ff
JB		 2992/**
2993 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2994 * @vsi: the VSI being configured
2995 * @basename: name for the vector
2996 *
2997 * Allocates MSI-X vectors and requests interrupts from the kernel.
2998 **/
2999static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3000{
3001 int q_vectors = vsi->num_q_vectors;
3002 struct i40e_pf *pf = vsi->back;
3003 int base = vsi->base_vector;
3004 int rx_int_idx = 0;
3005 int tx_int_idx = 0;
3006 int vector, err;
3007
3008 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3009 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3010
cd0b6fa6 3011 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3012 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3013 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3014 tx_int_idx++;
cd0b6fa6 3015 } else if (q_vector->rx.ring) {
41c445ff
JB		 3016 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3017 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3018 } else if (q_vector->tx.ring) {
41c445ff
JB		 3019 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3020 "%s-%s-%d", basename, "tx", tx_int_idx++);
3021 } else {
3022 /* skip this unused q_vector */
3023 continue;
3024 }
3025 err = request_irq(pf->msix_entries[base + vector].vector,
3026 vsi->irq_handler,
3027 0,
3028 q_vector->name,
3029 q_vector);
3030 if (err) {
3031 dev_info(&pf->pdev->dev,
3032 "%s: request_irq failed, error: %d\n",
3033 __func__, err);
3034 goto free_queue_irqs;
3035 }
3036 /* assign the mask for this irq */
3037 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3038 &q_vector->affinity_mask);
3039 }
3040
63741846 3041 vsi->irqs_ready = true;
41c445ff
JB		 3042 return 0;
3043
3044free_queue_irqs:
3045 while (vector) {
3046 vector--;
3047 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3048 NULL);
3049 free_irq(pf->msix_entries[base + vector].vector,
3050 &(vsi->q_vectors[vector]));
3051 }
3052 return err;
3053}
3054
3055/**
3056 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3057 * @vsi: the VSI being un-configured
3058 **/
3059static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3060{
3061 struct i40e_pf *pf = vsi->back;
3062 struct i40e_hw *hw = &pf->hw;
3063 int base = vsi->base_vector;
3064 int i;
3065
3066 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3067 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3068 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3069 }
3070
3071 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3072 for (i = vsi->base_vector;
3073 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3074 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3075
3076 i40e_flush(hw);
3077 for (i = 0; i < vsi->num_q_vectors; i++)
3078 synchronize_irq(pf->msix_entries[i + base].vector);
3079 } else {
3080 /* Legacy and MSI mode - this stops all interrupt handling */
3081 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3082 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3083 i40e_flush(hw);
3084 synchronize_irq(pf->pdev->irq);
3085 }
3086}
3087
3088/**
3089 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3090 * @vsi: the VSI being configured
3091 **/
3092static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3093{
3094 struct i40e_pf *pf = vsi->back;
3095 int i;
3096
3097 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3098 for (i = vsi->base_vector;
3099 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3100 i40e_irq_dynamic_enable(vsi, i);
3101 } else {
3102 i40e_irq_dynamic_enable_icr0(pf);
3103 }
3104
1022cb6c 3105 i40e_flush(&pf->hw);
41c445ff
JB		 3106 return 0;
3107}
3108
3109/**
3110 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3111 * @pf: board private structure
3112 **/
3113static void i40e_stop_misc_vector(struct i40e_pf *pf)
3114{
3115 /* Disable ICR 0 */
3116 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3117 i40e_flush(&pf->hw);
3118}
3119
3120/**
3121 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3122 * @irq: interrupt number
3123 * @data: pointer to a q_vector
3124 *
3125 * This is the handler used for all MSI/Legacy interrupts, and deals
3126 * with both queue and non-queue interrupts. This is also used in
3127 * MSIX mode to handle the non-queue interrupts.
3128 **/
3129static irqreturn_t i40e_intr(int irq, void *data)
3130{
3131 struct i40e_pf *pf = (struct i40e_pf *)data;
3132 struct i40e_hw *hw = &pf->hw;
5e823066 3133 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3134 u32 icr0, icr0_remaining;
3135 u32 val, ena_mask;
3136
3137 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3138 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3139
116a57d4
SN		 3140 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3141 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3142 goto enable_intr;
41c445ff 3143
cd92e72f
SN		 3144 /* if interrupt but no bits showing, must be SWINT */
3145 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3146 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3147 pf->sw_int_count++;
3148
41c445ff
JB		 3149 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3150 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3151
3152 /* temporarily disable queue cause for NAPI processing */
3153 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3154 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3155 wr32(hw, I40E_QINT_RQCTL(0), qval);
3156
3157 qval = rd32(hw, I40E_QINT_TQCTL(0));
3158 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3159 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3160
3161 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3162 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3163 }
3164
3165 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3166 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3167 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3168 }
3169
3170 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3171 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3172 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3173 }
3174
3175 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3176 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3177 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3178 }
3179
3180 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3181 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3182 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3183 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3184 val = rd32(hw, I40E_GLGEN_RSTAT);
3185 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3186 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3187 if (val == I40E_RESET_CORER) {
41c445ff 3188 pf->corer_count++;
4eb3f768 3189 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3190 pf->globr_count++;
4eb3f768 3191 } else if (val == I40E_RESET_EMPR) {
41c445ff 3192 pf->empr_count++;
9df42d1a 3193 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3194 }
41c445ff
JB		 3195 }
3196
9c010ee0
ASJ		 3197 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3198 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3199 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3200 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3201 rd32(hw, I40E_PFHMC_ERRORINFO),
3202 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3203 }
3204
beb0dff1
JK		 3205 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3206 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3207
3208 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3209 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3210 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3211 }
beb0dff1
JK		 3212 }
3213
41c445ff
JB		 3214 /* If a critical error is pending we have no choice but to reset the
3215 * device.
3216 * Report and mask out any remaining unexpected interrupts.
3217 */
3218 icr0_remaining = icr0 & ena_mask;
3219 if (icr0_remaining) {
3220 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3221 icr0_remaining);
9c010ee0 3222 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3223 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3224 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3225 dev_info(&pf->pdev->dev, "device will be reset\n");
3226 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3227 i40e_service_event_schedule(pf);
41c445ff
JB		 3228 }
3229 ena_mask &= ~icr0_remaining;
3230 }
5e823066 3231 ret = IRQ_HANDLED;
41c445ff 3232
5e823066 3233enable_intr:
41c445ff
JB		 3234 /* re-enable interrupt causes */
3235 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3236 if (!test_bit(__I40E_DOWN, &pf->state)) {
3237 i40e_service_event_schedule(pf);
3238 i40e_irq_dynamic_enable_icr0(pf);
3239 }
3240
5e823066 3241 return ret;
41c445ff
JB		 3242}
3243
cbf61325
ASJ		 3244/**
3245 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3246 * @tx_ring: tx ring to clean
3247 * @budget: how many cleans we're allowed
3248 *
3249 * Returns true if there's any budget left (e.g. the clean is finished)
3250 **/
3251static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3252{
3253 struct i40e_vsi *vsi = tx_ring->vsi;
3254 u16 i = tx_ring->next_to_clean;
3255 struct i40e_tx_buffer *tx_buf;
3256 struct i40e_tx_desc *tx_desc;
3257
3258 tx_buf = &tx_ring->tx_bi[i];
3259 tx_desc = I40E_TX_DESC(tx_ring, i);
3260 i -= tx_ring->count;
3261
3262 do {
3263 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3264
3265 /* if next_to_watch is not set then there is no work pending */
3266 if (!eop_desc)
3267 break;
3268
3269 /* prevent any other reads prior to eop_desc */
3270 read_barrier_depends();
3271
3272 /* if the descriptor isn't done, no work yet to do */
3273 if (!(eop_desc->cmd_type_offset_bsz &
3274 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3275 break;
3276
3277 /* clear next_to_watch to prevent false hangs */
3278 tx_buf->next_to_watch = NULL;
3279
49d7d933
ASJ		 3280 tx_desc->buffer_addr = 0;
3281 tx_desc->cmd_type_offset_bsz = 0;
3282 /* move past filter desc */
3283 tx_buf++;
3284 tx_desc++;
3285 i++;
3286 if (unlikely(!i)) {
3287 i -= tx_ring->count;
3288 tx_buf = tx_ring->tx_bi;
3289 tx_desc = I40E_TX_DESC(tx_ring, 0);
3290 }
cbf61325
ASJ		 3291 /* unmap skb header data */
3292 dma_unmap_single(tx_ring->dev,
3293 dma_unmap_addr(tx_buf, dma),
3294 dma_unmap_len(tx_buf, len),
3295 DMA_TO_DEVICE);
49d7d933
ASJ		 3296 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3297 kfree(tx_buf->raw_buf);
cbf61325 3298
49d7d933
ASJ		 3299 tx_buf->raw_buf = NULL;
3300 tx_buf->tx_flags = 0;
3301 tx_buf->next_to_watch = NULL;
cbf61325 3302 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3303 tx_desc->buffer_addr = 0;
3304 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3305
49d7d933 3306 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3307 tx_buf++;
3308 tx_desc++;
3309 i++;
3310 if (unlikely(!i)) {
3311 i -= tx_ring->count;
3312 tx_buf = tx_ring->tx_bi;
3313 tx_desc = I40E_TX_DESC(tx_ring, 0);
3314 }
3315
3316 /* update budget accounting */
3317 budget--;
3318 } while (likely(budget));
3319
3320 i += tx_ring->count;
3321 tx_ring->next_to_clean = i;
3322
3323 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3324 i40e_irq_dynamic_enable(vsi,
3325 tx_ring->q_vector->v_idx + vsi->base_vector);
3326 }
3327 return budget > 0;
3328}
3329
3330/**
3331 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3332 * @irq: interrupt number
3333 * @data: pointer to a q_vector
3334 **/
3335static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3336{
3337 struct i40e_q_vector *q_vector = data;
3338 struct i40e_vsi *vsi;
3339
3340 if (!q_vector->tx.ring)
3341 return IRQ_HANDLED;
3342
3343 vsi = q_vector->tx.ring->vsi;
3344 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3345
3346 return IRQ_HANDLED;
3347}
3348
41c445ff 3349/**
cd0b6fa6 3350 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3351 * @vsi: the VSI being configured
3352 * @v_idx: vector index
cd0b6fa6 3353 * @qp_idx: queue pair index
41c445ff 3354 **/
cd0b6fa6 3355static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3356{
493fb300 3357 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3358 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3359 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3360
3361 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3362 tx_ring->next = q_vector->tx.ring;
3363 q_vector->tx.ring = tx_ring;
41c445ff 3364 q_vector->tx.count++;
cd0b6fa6
AD		 3365
3366 rx_ring->q_vector = q_vector;
3367 rx_ring->next = q_vector->rx.ring;
3368 q_vector->rx.ring = rx_ring;
3369 q_vector->rx.count++;
41c445ff
JB		 3370}
3371
3372/**
3373 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3374 * @vsi: the VSI being configured
3375 *
3376 * This function maps descriptor rings to the queue-specific vectors
3377 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3378 * one vector per queue pair, but on a constrained vector budget, we
3379 * group the queue pairs as "efficiently" as possible.
3380 **/
3381static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3382{
3383 int qp_remaining = vsi->num_queue_pairs;
3384 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3385 int num_ringpairs;
41c445ff
JB		 3386 int v_start = 0;
3387 int qp_idx = 0;
3388
3389 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3390 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3391 * It is also important to go through all the vectors available to be
3392 * sure that if we don't use all the vectors, that the remaining vectors
3393 * are cleared. This is especially important when decreasing the
3394 * number of queues in use.
41c445ff 3395 */
70114ec4 3396 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3397 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3398
3399 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3400
3401 q_vector->num_ringpairs = num_ringpairs;
3402
3403 q_vector->rx.count = 0;
3404 q_vector->tx.count = 0;
3405 q_vector->rx.ring = NULL;
3406 q_vector->tx.ring = NULL;
3407
3408 while (num_ringpairs--) {
3409 map_vector_to_qp(vsi, v_start, qp_idx);
3410 qp_idx++;
3411 qp_remaining--;
41c445ff
JB		 3412 }
3413 }
3414}
3415
3416/**
3417 * i40e_vsi_request_irq - Request IRQ from the OS
3418 * @vsi: the VSI being configured
3419 * @basename: name for the vector
3420 **/
3421static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3422{
3423 struct i40e_pf *pf = vsi->back;
3424 int err;
3425
3426 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3427 err = i40e_vsi_request_irq_msix(vsi, basename);
3428 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3429 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3430 pf->int_name, pf);
41c445ff
JB		 3431 else
3432 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3433 pf->int_name, pf);
41c445ff
JB		 3434
3435 if (err)
3436 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3437
3438 return err;
3439}
3440
3441#ifdef CONFIG_NET_POLL_CONTROLLER
3442/**
3443 * i40e_netpoll - A Polling 'interrupt'handler
3444 * @netdev: network interface device structure
3445 *
3446 * This is used by netconsole to send skbs without having to re-enable
3447 * interrupts. It's not called while the normal interrupt routine is executing.
3448 **/
38e00438
VD		 3449#ifdef I40E_FCOE
3450void i40e_netpoll(struct net_device *netdev)
3451#else
41c445ff 3452static void i40e_netpoll(struct net_device *netdev)
38e00438 3453#endif
41c445ff
JB		 3454{
3455 struct i40e_netdev_priv *np = netdev_priv(netdev);
3456 struct i40e_vsi *vsi = np->vsi;
3457 struct i40e_pf *pf = vsi->back;
3458 int i;
3459
3460 /* if interface is down do nothing */
3461 if (test_bit(__I40E_DOWN, &vsi->state))
3462 return;
3463
3464 pf->flags |= I40E_FLAG_IN_NETPOLL;
3465 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3466 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3467 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3468 } else {
3469 i40e_intr(pf->pdev->irq, netdev);
3470 }
3471 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3472}
3473#endif
3474
23527308
NP		 3475/**
3476 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3477 * @pf: the PF being configured
3478 * @pf_q: the PF queue
3479 * @enable: enable or disable state of the queue
3480 *
3481 * This routine will wait for the given Tx queue of the PF to reach the
3482 * enabled or disabled state.
3483 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3484 * multiple retries; else will return 0 in case of success.
3485 **/
3486static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3487{
3488 int i;
3489 u32 tx_reg;
3490
3491 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3492 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3493 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3494 break;
3495
f98a2006 3496 usleep_range(10, 20);
23527308
NP		 3497 }
3498 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3499 return -ETIMEDOUT;
3500
3501 return 0;
3502}
3503
41c445ff
JB		 3504/**
3505 * i40e_vsi_control_tx - Start or stop a VSI's rings
3506 * @vsi: the VSI being configured
3507 * @enable: start or stop the rings
3508 **/
3509static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3510{
3511 struct i40e_pf *pf = vsi->back;
3512 struct i40e_hw *hw = &pf->hw;
23527308 3513 int i, j, pf_q, ret = 0;
41c445ff
JB		 3514 u32 tx_reg;
3515
3516 pf_q = vsi->base_queue;
3517 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3518
3519 /* warn the TX unit of coming changes */
3520 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3521 if (!enable)
f98a2006 3522 usleep_range(10, 20);
351499ab 3523
6c5ef620 3524 for (j = 0; j < 50; j++) {
41c445ff 3525 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3526 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3527 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3528 break;
3529 usleep_range(1000, 2000);
3530 }
fda972f6 3531 /* Skip if the queue is already in the requested state */
7c122007 3532 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3533 continue;
41c445ff
JB		 3534
3535 /* turn on/off the queue */
c5c9eb9e
SN		 3536 if (enable) {
3537 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3538 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3539 } else {
41c445ff 3540 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3541 }
41c445ff
JB		 3542
3543 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3544 /* No waiting for the Tx queue to disable */
3545 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3546 continue;
41c445ff
JB		 3547
3548 /* wait for the change to finish */
23527308
NP		 3549 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3550 if (ret) {
3551 dev_info(&pf->pdev->dev,
3552 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3553 __func__, vsi->seid, pf_q,
3554 (enable ? "en" : "dis"));
3555 break;
41c445ff
JB		 3556 }
3557 }
3558
7134f9ce
JB		 3559 if (hw->revision_id == 0)
3560 mdelay(50);
23527308
NP		 3561 return ret;
3562}
3563
3564/**
3565 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3566 * @pf: the PF being configured
3567 * @pf_q: the PF queue
3568 * @enable: enable or disable state of the queue
3569 *
3570 * This routine will wait for the given Rx queue of the PF to reach the
3571 * enabled or disabled state.
3572 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3573 * multiple retries; else will return 0 in case of success.
3574 **/
3575static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3576{
3577 int i;
3578 u32 rx_reg;
3579
3580 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3581 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3582 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3583 break;
3584
f98a2006 3585 usleep_range(10, 20);
23527308
NP		 3586 }
3587 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3588 return -ETIMEDOUT;
7134f9ce 3589
41c445ff
JB		 3590 return 0;
3591}
3592
3593/**
3594 * i40e_vsi_control_rx - Start or stop a VSI's rings
3595 * @vsi: the VSI being configured
3596 * @enable: start or stop the rings
3597 **/
3598static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3599{
3600 struct i40e_pf *pf = vsi->back;
3601 struct i40e_hw *hw = &pf->hw;
23527308 3602 int i, j, pf_q, ret = 0;
41c445ff
JB		 3603 u32 rx_reg;
3604
3605 pf_q = vsi->base_queue;
3606 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3607 for (j = 0; j < 50; j++) {
41c445ff 3608 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3609 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3610 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3611 break;
3612 usleep_range(1000, 2000);
3613 }
41c445ff 3614
7c122007
CS		 3615 /* Skip if the queue is already in the requested state */
3616 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3617 continue;
41c445ff
JB		 3618
3619 /* turn on/off the queue */
3620 if (enable)
6c5ef620 3621 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3622 else
6c5ef620 3623 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3624 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3625
3626 /* wait for the change to finish */
23527308
NP		 3627 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3628 if (ret) {
3629 dev_info(&pf->pdev->dev,
3630 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3631 __func__, vsi->seid, pf_q,
3632 (enable ? "en" : "dis"));
3633 break;
41c445ff
JB		 3634 }
3635 }
3636
23527308 3637 return ret;
41c445ff
JB		 3638}
3639
3640/**
3641 * i40e_vsi_control_rings - Start or stop a VSI's rings
3642 * @vsi: the VSI being configured
3643 * @enable: start or stop the rings
3644 **/
fc18eaa0 3645int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3646{
3b867b28 3647 int ret = 0;
41c445ff
JB		 3648
3649 /* do rx first for enable and last for disable */
3650 if (request) {
3651 ret = i40e_vsi_control_rx(vsi, request);
3652 if (ret)
3653 return ret;
3654 ret = i40e_vsi_control_tx(vsi, request);
3655 } else {
3b867b28
ASJ		 3656 /* Ignore return value, we need to shutdown whatever we can */
3657 i40e_vsi_control_tx(vsi, request);
3658 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3659 }
3660
3661 return ret;
3662}
3663
3664/**
3665 * i40e_vsi_free_irq - Free the irq association with the OS
3666 * @vsi: the VSI being configured
3667 **/
3668static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3669{
3670 struct i40e_pf *pf = vsi->back;
3671 struct i40e_hw *hw = &pf->hw;
3672 int base = vsi->base_vector;
3673 u32 val, qp;
3674 int i;
3675
3676 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3677 if (!vsi->q_vectors)
3678 return;
3679
63741846
SN		 3680 if (!vsi->irqs_ready)
3681 return;
3682
3683 vsi->irqs_ready = false;
41c445ff
JB		 3684 for (i = 0; i < vsi->num_q_vectors; i++) {
3685 u16 vector = i + base;
3686
3687 /* free only the irqs that were actually requested */
78681b1f
SN		 3688 if (!vsi->q_vectors[i] ||
3689 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3690 continue;
3691
3692 /* clear the affinity_mask in the IRQ descriptor */
3693 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3694 NULL);
3695 free_irq(pf->msix_entries[vector].vector,
493fb300 3696 vsi->q_vectors[i]);
41c445ff
JB		 3697
3698 /* Tear down the interrupt queue link list
3699 *
3700 * We know that they come in pairs and always
3701 * the Rx first, then the Tx. To clear the
3702 * link list, stick the EOL value into the
3703 * next_q field of the registers.
3704 */
3705 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3706 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3707 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3708 val |= I40E_QUEUE_END_OF_LIST
3709 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3710 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3711
3712 while (qp != I40E_QUEUE_END_OF_LIST) {
3713 u32 next;
3714
3715 val = rd32(hw, I40E_QINT_RQCTL(qp));
3716
3717 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3718 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3719 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3720 I40E_QINT_RQCTL_INTEVENT_MASK);
3721
3722 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3723 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3724
3725 wr32(hw, I40E_QINT_RQCTL(qp), val);
3726
3727 val = rd32(hw, I40E_QINT_TQCTL(qp));
3728
3729 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3730 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3731
3732 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3733 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3734 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3735 I40E_QINT_TQCTL_INTEVENT_MASK);
3736
3737 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3738 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3739
3740 wr32(hw, I40E_QINT_TQCTL(qp), val);
3741 qp = next;
3742 }
3743 }
3744 } else {
3745 free_irq(pf->pdev->irq, pf);
3746
3747 val = rd32(hw, I40E_PFINT_LNKLST0);
3748 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3749 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3750 val |= I40E_QUEUE_END_OF_LIST
3751 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3752 wr32(hw, I40E_PFINT_LNKLST0, val);
3753
3754 val = rd32(hw, I40E_QINT_RQCTL(qp));
3755 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3756 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3757 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3758 I40E_QINT_RQCTL_INTEVENT_MASK);
3759
3760 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3761 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3762
3763 wr32(hw, I40E_QINT_RQCTL(qp), val);
3764
3765 val = rd32(hw, I40E_QINT_TQCTL(qp));
3766
3767 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3768 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3769 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3770 I40E_QINT_TQCTL_INTEVENT_MASK);
3771
3772 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3773 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3774
3775 wr32(hw, I40E_QINT_TQCTL(qp), val);
3776 }
3777}
3778
493fb300
AD		 3779/**
3780 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3781 * @vsi: the VSI being configured
3782 * @v_idx: Index of vector to be freed
3783 *
3784 * This function frees the memory allocated to the q_vector. In addition if
3785 * NAPI is enabled it will delete any references to the NAPI struct prior
3786 * to freeing the q_vector.
3787 **/
3788static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3789{
3790 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3791 struct i40e_ring *ring;
493fb300
AD		 3792
3793 if (!q_vector)
3794 return;
3795
3796 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3797 i40e_for_each_ring(ring, q_vector->tx)
3798 ring->q_vector = NULL;
3799
3800 i40e_for_each_ring(ring, q_vector->rx)
3801 ring->q_vector = NULL;
493fb300
AD		 3802
3803 /* only VSI w/ an associated netdev is set up w/ NAPI */
3804 if (vsi->netdev)
3805 netif_napi_del(&q_vector->napi);
3806
3807 vsi->q_vectors[v_idx] = NULL;
3808
3809 kfree_rcu(q_vector, rcu);
3810}
3811
41c445ff
JB		 3812/**
3813 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3814 * @vsi: the VSI being un-configured
3815 *
3816 * This frees the memory allocated to the q_vectors and
3817 * deletes references to the NAPI struct.
3818 **/
3819static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3820{
3821 int v_idx;
3822
493fb300
AD		 3823 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3824 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3825}
3826
3827/**
3828 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3829 * @pf: board private structure
3830 **/
3831static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3832{
3833 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3834 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3835 pci_disable_msix(pf->pdev);
3836 kfree(pf->msix_entries);
3837 pf->msix_entries = NULL;
3b444399
SN		 3838 kfree(pf->irq_pile);
3839 pf->irq_pile = NULL;
41c445ff
JB		 3840 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3841 pci_disable_msi(pf->pdev);
3842 }
3843 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3844}
3845
3846/**
3847 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3848 * @pf: board private structure
3849 *
3850 * We go through and clear interrupt specific resources and reset the structure
3851 * to pre-load conditions
3852 **/
3853static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3854{
3855 int i;
3856
e147758d
SN		 3857 i40e_stop_misc_vector(pf);
3858 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3859 synchronize_irq(pf->msix_entries[0].vector);
3860 free_irq(pf->msix_entries[0].vector, pf);
3861 }
3862
41c445ff 3863 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3864 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3865 if (pf->vsi[i])
3866 i40e_vsi_free_q_vectors(pf->vsi[i]);
3867 i40e_reset_interrupt_capability(pf);
3868}
3869
3870/**
3871 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3872 * @vsi: the VSI being configured
3873 **/
3874static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3875{
3876 int q_idx;
3877
3878 if (!vsi->netdev)
3879 return;
3880
3881 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3882 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3883}
3884
3885/**
3886 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3887 * @vsi: the VSI being configured
3888 **/
3889static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3890{
3891 int q_idx;
3892
3893 if (!vsi->netdev)
3894 return;
3895
3896 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3897 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3898}
3899
90ef8d47
SN		 3900/**
3901 * i40e_vsi_close - Shut down a VSI
3902 * @vsi: the vsi to be quelled
3903 **/
3904static void i40e_vsi_close(struct i40e_vsi *vsi)
3905{
3906 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3907 i40e_down(vsi);
3908 i40e_vsi_free_irq(vsi);
3909 i40e_vsi_free_tx_resources(vsi);
3910 i40e_vsi_free_rx_resources(vsi);
3911}
3912
41c445ff
JB		 3913/**
3914 * i40e_quiesce_vsi - Pause a given VSI
3915 * @vsi: the VSI being paused
3916 **/
3917static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3918{
3919 if (test_bit(__I40E_DOWN, &vsi->state))
3920 return;
3921
d341b7a5
NP		 3922 /* No need to disable FCoE VSI when Tx suspended */
3923 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
3924 vsi->type == I40E_VSI_FCOE) {
3925 dev_dbg(&vsi->back->pdev->dev,
3926 "%s: VSI seid %d skipping FCoE VSI disable\n",
3927 __func__, vsi->seid);
3928 return;
3929 }
3930
41c445ff
JB		 3931 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3932 if (vsi->netdev && netif_running(vsi->netdev)) {
3933 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3934 } else {
90ef8d47 3935 i40e_vsi_close(vsi);
41c445ff
JB		 3936 }
3937}
3938
3939/**
3940 * i40e_unquiesce_vsi - Resume a given VSI
3941 * @vsi: the VSI being resumed
3942 **/
3943static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3944{
3945 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3946 return;
3947
3948 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3949 if (vsi->netdev && netif_running(vsi->netdev))
3950 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3951 else
8276f757 3952 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3953}
3954
3955/**
3956 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3957 * @pf: the PF
3958 **/
3959static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3960{
3961 int v;
3962
505682cd 3963 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3964 if (pf->vsi[v])
3965 i40e_quiesce_vsi(pf->vsi[v]);
3966 }
3967}
3968
3969/**
3970 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3971 * @pf: the PF
3972 **/
3973static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3974{
3975 int v;
3976
505682cd 3977 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3978 if (pf->vsi[v])
3979 i40e_unquiesce_vsi(pf->vsi[v]);
3980 }
3981}
3982
69129dc3
NP		 3983#ifdef CONFIG_I40E_DCB
3984/**
3985 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
3986 * @vsi: the VSI being configured
3987 *
3988 * This function waits for the given VSI's Tx queues to be disabled.
3989 **/
3990static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
3991{
3992 struct i40e_pf *pf = vsi->back;
3993 int i, pf_q, ret;
3994
3995 pf_q = vsi->base_queue;
3996 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3997 /* Check and wait for the disable status of the queue */
3998 ret = i40e_pf_txq_wait(pf, pf_q, false);
3999 if (ret) {
4000 dev_info(&pf->pdev->dev,
4001 "%s: VSI seid %d Tx ring %d disable timeout\n",
4002 __func__, vsi->seid, pf_q);
4003 return ret;
4004 }
4005 }
4006
4007 return 0;
4008}
4009
4010/**
4011 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4012 * @pf: the PF
4013 *
4014 * This function waits for the Tx queues to be in disabled state for all the
4015 * VSIs that are managed by this PF.
4016 **/
4017static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4018{
4019 int v, ret = 0;
4020
4021 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4022 /* No need to wait for FCoE VSI queues */
4023 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4024 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4025 if (ret)
4026 break;
4027 }
4028 }
4029
4030 return ret;
4031}
4032
4033#endif
63d7e5a4
NP		 4034/**
4035 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4036 * @pf: pointer to PF
63d7e5a4
NP		 4037 *
4038 * Get TC map for ISCSI PF type that will include iSCSI TC
4039 * and LAN TC.
4040 **/
4041static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4042{
4043 struct i40e_dcb_app_priority_table app;
4044 struct i40e_hw *hw = &pf->hw;
4045 u8 enabled_tc = 1; /* TC0 is always enabled */
4046 u8 tc, i;
4047 /* Get the iSCSI APP TLV */
4048 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4049
4050 for (i = 0; i < dcbcfg->numapps; i++) {
4051 app = dcbcfg->app[i];
4052 if (app.selector == I40E_APP_SEL_TCPIP &&
4053 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4054 tc = dcbcfg->etscfg.prioritytable[app.priority];
4055 enabled_tc |= (1 << tc);
4056 break;
4057 }
4058 }
4059
4060 return enabled_tc;
4061}
4062
41c445ff
JB		 4063/**
4064 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4065 * @dcbcfg: the corresponding DCBx configuration structure
4066 *
4067 * Return the number of TCs from given DCBx configuration
4068 **/
4069static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4070{
078b5876
JB		 4071 u8 num_tc = 0;
4072 int i;
41c445ff
JB		 4073
4074 /* Scan the ETS Config Priority Table to find
4075 * traffic class enabled for a given priority
4076 * and use the traffic class index to get the
4077 * number of traffic classes enabled
4078 */
4079 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4080 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4081 num_tc = dcbcfg->etscfg.prioritytable[i];
4082 }
4083
4084 /* Traffic class index starts from zero so
4085 * increment to return the actual count
4086 */
078b5876 4087 return num_tc + 1;
41c445ff
JB		 4088}
4089
4090/**
4091 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4092 * @dcbcfg: the corresponding DCBx configuration structure
4093 *
4094 * Query the current DCB configuration and return the number of
4095 * traffic classes enabled from the given DCBX config
4096 **/
4097static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4098{
4099 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4100 u8 enabled_tc = 1;
4101 u8 i;
4102
4103 for (i = 0; i < num_tc; i++)
4104 enabled_tc |= 1 << i;
4105
4106 return enabled_tc;
4107}
4108
4109/**
4110 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4111 * @pf: PF being queried
4112 *
4113 * Return number of traffic classes enabled for the given PF
4114 **/
4115static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4116{
4117 struct i40e_hw *hw = &pf->hw;
4118 u8 i, enabled_tc;
4119 u8 num_tc = 0;
4120 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4121
4122 /* If DCB is not enabled then always in single TC */
4123 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4124 return 1;
4125
63d7e5a4
NP		 4126 /* SFP mode will be enabled for all TCs on port */
4127 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4128 return i40e_dcb_get_num_tc(dcbcfg);
4129
41c445ff 4130 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4131 if (pf->hw.func_caps.iscsi)
4132 enabled_tc = i40e_get_iscsi_tc_map(pf);
4133 else
fc51de96 4134 return 1; /* Only TC0 */
41c445ff 4135
63d7e5a4
NP		 4136 /* At least have TC0 */
4137 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4138 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4139 if (enabled_tc & (1 << i))
4140 num_tc++;
4141 }
4142 return num_tc;
41c445ff
JB		 4143}
4144
4145/**
4146 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4147 * @pf: PF being queried
4148 *
4149 * Return a bitmap for first enabled traffic class for this PF.
4150 **/
4151static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4152{
4153 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4154 u8 i = 0;
4155
4156 if (!enabled_tc)
4157 return 0x1; /* TC0 */
4158
4159 /* Find the first enabled TC */
4160 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4161 if (enabled_tc & (1 << i))
4162 break;
4163 }
4164
4165 return 1 << i;
4166}
4167
4168/**
4169 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4170 * @pf: PF being queried
4171 *
4172 * Return a bitmap for enabled traffic classes for this PF.
4173 **/
4174static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4175{
4176 /* If DCB is not enabled for this PF then just return default TC */
4177 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4178 return i40e_pf_get_default_tc(pf);
4179
41c445ff 4180 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4181 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4182 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4183
fc51de96 4184 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4185 if (pf->hw.func_caps.iscsi)
4186 return i40e_get_iscsi_tc_map(pf);
4187 else
fc51de96 4188 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4189}
4190
4191/**
4192 * i40e_vsi_get_bw_info - Query VSI BW Information
4193 * @vsi: the VSI being queried
4194 *
4195 * Returns 0 on success, negative value on failure
4196 **/
4197static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4198{
4199 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4200 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4201 struct i40e_pf *pf = vsi->back;
4202 struct i40e_hw *hw = &pf->hw;
dcae29be 4203 i40e_status aq_ret;
41c445ff 4204 u32 tc_bw_max;
41c445ff
JB		 4205 int i;
4206
4207 /* Get the VSI level BW configuration */
dcae29be
JB		 4208 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4209 if (aq_ret) {
41c445ff 4210 dev_info(&pf->pdev->dev,
b40c82e6 4211 "couldn't get PF vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4212 aq_ret, pf->hw.aq.asq_last_status);
4213 return -EINVAL;
41c445ff
JB		 4214 }
4215
4216 /* Get the VSI level BW configuration per TC */
dcae29be 4217 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4218 NULL);
dcae29be 4219 if (aq_ret) {
41c445ff 4220 dev_info(&pf->pdev->dev,
b40c82e6 4221 "couldn't get PF vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4222 aq_ret, pf->hw.aq.asq_last_status);
4223 return -EINVAL;
41c445ff
JB		 4224 }
4225
4226 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4227 dev_info(&pf->pdev->dev,
4228 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4229 bw_config.tc_valid_bits,
4230 bw_ets_config.tc_valid_bits);
4231 /* Still continuing */
4232 }
4233
4234 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4235 vsi->bw_max_quanta = bw_config.max_bw;
4236 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4237 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4238 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4239 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4240 vsi->bw_ets_limit_credits[i] =
4241 le16_to_cpu(bw_ets_config.credits[i]);
4242 /* 3 bits out of 4 for each TC */
4243 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4244 }
078b5876 4245
dcae29be 4246 return 0;
41c445ff
JB		 4247}
4248
4249/**
4250 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4251 * @vsi: the VSI being configured
4252 * @enabled_tc: TC bitmap
4253 * @bw_credits: BW shared credits per TC
4254 *
4255 * Returns 0 on success, negative value on failure
4256 **/
dcae29be 4257static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4258 u8 *bw_share)
4259{
4260 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4261 i40e_status aq_ret;
4262 int i;
41c445ff
JB		 4263
4264 bw_data.tc_valid_bits = enabled_tc;
4265 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4266 bw_data.tc_bw_credits[i] = bw_share[i];
4267
dcae29be
JB		 4268 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4269 NULL);
4270 if (aq_ret) {
41c445ff 4271 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4272 "AQ command Config VSI BW allocation per TC failed = %d\n",
4273 vsi->back->hw.aq.asq_last_status);
dcae29be 4274 return -EINVAL;
41c445ff
JB		 4275 }
4276
4277 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4278 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4279
dcae29be 4280 return 0;
41c445ff
JB		 4281}
4282
4283/**
4284 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4285 * @vsi: the VSI being configured
4286 * @enabled_tc: TC map to be enabled
4287 *
4288 **/
4289static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4290{
4291 struct net_device *netdev = vsi->netdev;
4292 struct i40e_pf *pf = vsi->back;
4293 struct i40e_hw *hw = &pf->hw;
4294 u8 netdev_tc = 0;
4295 int i;
4296 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4297
4298 if (!netdev)
4299 return;
4300
4301 if (!enabled_tc) {
4302 netdev_reset_tc(netdev);
4303 return;
4304 }
4305
4306 /* Set up actual enabled TCs on the VSI */
4307 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4308 return;
4309
4310 /* set per TC queues for the VSI */
4311 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4312 /* Only set TC queues for enabled tcs
4313 *
4314 * e.g. For a VSI that has TC0 and TC3 enabled the
4315 * enabled_tc bitmap would be 0x00001001; the driver
4316 * will set the numtc for netdev as 2 that will be
4317 * referenced by the netdev layer as TC 0 and 1.
4318 */
4319 if (vsi->tc_config.enabled_tc & (1 << i))
4320 netdev_set_tc_queue(netdev,
4321 vsi->tc_config.tc_info[i].netdev_tc,
4322 vsi->tc_config.tc_info[i].qcount,
4323 vsi->tc_config.tc_info[i].qoffset);
4324 }
4325
4326 /* Assign UP2TC map for the VSI */
4327 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4328 /* Get the actual TC# for the UP */
4329 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4330 /* Get the mapped netdev TC# for the UP */
4331 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4332 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4333 }
4334}
4335
4336/**
4337 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4338 * @vsi: the VSI being configured
4339 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4340 **/
4341static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4342 struct i40e_vsi_context *ctxt)
4343{
4344 /* copy just the sections touched not the entire info
4345 * since not all sections are valid as returned by
4346 * update vsi params
4347 */
4348 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4349 memcpy(&vsi->info.queue_mapping,
4350 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4351 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4352 sizeof(vsi->info.tc_mapping));
4353}
4354
4355/**
4356 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4357 * @vsi: VSI to be configured
4358 * @enabled_tc: TC bitmap
4359 *
4360 * This configures a particular VSI for TCs that are mapped to the
4361 * given TC bitmap. It uses default bandwidth share for TCs across
4362 * VSIs to configure TC for a particular VSI.
4363 *
4364 * NOTE:
4365 * It is expected that the VSI queues have been quisced before calling
4366 * this function.
4367 **/
4368static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4369{
4370 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4371 struct i40e_vsi_context ctxt;
4372 int ret = 0;
4373 int i;
4374
4375 /* Check if enabled_tc is same as existing or new TCs */
4376 if (vsi->tc_config.enabled_tc == enabled_tc)
4377 return ret;
4378
4379 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4380 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4381 if (enabled_tc & (1 << i))
4382 bw_share[i] = 1;
4383 }
4384
4385 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4386 if (ret) {
4387 dev_info(&vsi->back->pdev->dev,
4388 "Failed configuring TC map %d for VSI %d\n",
4389 enabled_tc, vsi->seid);
4390 goto out;
4391 }
4392
4393 /* Update Queue Pairs Mapping for currently enabled UPs */
4394 ctxt.seid = vsi->seid;
4395 ctxt.pf_num = vsi->back->hw.pf_id;
4396 ctxt.vf_num = 0;
4397 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4398 ctxt.info = vsi->info;
41c445ff
JB		 4399 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4400
4401 /* Update the VSI after updating the VSI queue-mapping information */
4402 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4403 if (ret) {
4404 dev_info(&vsi->back->pdev->dev,
4405 "update vsi failed, aq_err=%d\n",
4406 vsi->back->hw.aq.asq_last_status);
4407 goto out;
4408 }
4409 /* update the local VSI info with updated queue map */
4410 i40e_vsi_update_queue_map(vsi, &ctxt);
4411 vsi->info.valid_sections = 0;
4412
4413 /* Update current VSI BW information */
4414 ret = i40e_vsi_get_bw_info(vsi);
4415 if (ret) {
4416 dev_info(&vsi->back->pdev->dev,
4417 "Failed updating vsi bw info, aq_err=%d\n",
4418 vsi->back->hw.aq.asq_last_status);
4419 goto out;
4420 }
4421
4422 /* Update the netdev TC setup */
4423 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4424out:
4425 return ret;
4426}
4427
4e3b35b0
NP		 4428/**
4429 * i40e_veb_config_tc - Configure TCs for given VEB
4430 * @veb: given VEB
4431 * @enabled_tc: TC bitmap
4432 *
4433 * Configures given TC bitmap for VEB (switching) element
4434 **/
4435int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4436{
4437 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4438 struct i40e_pf *pf = veb->pf;
4439 int ret = 0;
4440 int i;
4441
4442 /* No TCs or already enabled TCs just return */
4443 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4444 return ret;
4445
4446 bw_data.tc_valid_bits = enabled_tc;
4447 /* bw_data.absolute_credits is not set (relative) */
4448
4449 /* Enable ETS TCs with equal BW Share for now */
4450 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4451 if (enabled_tc & (1 << i))
4452 bw_data.tc_bw_share_credits[i] = 1;
4453 }
4454
4455 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4456 &bw_data, NULL);
4457 if (ret) {
4458 dev_info(&pf->pdev->dev,
4459 "veb bw config failed, aq_err=%d\n",
4460 pf->hw.aq.asq_last_status);
4461 goto out;
4462 }
4463
4464 /* Update the BW information */
4465 ret = i40e_veb_get_bw_info(veb);
4466 if (ret) {
4467 dev_info(&pf->pdev->dev,
4468 "Failed getting veb bw config, aq_err=%d\n",
4469 pf->hw.aq.asq_last_status);
4470 }
4471
4472out:
4473 return ret;
4474}
4475
4476#ifdef CONFIG_I40E_DCB
4477/**
4478 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4479 * @pf: PF struct
4480 *
4481 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4482 * the caller would've quiesce all the VSIs before calling
4483 * this function
4484 **/
4485static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4486{
4487 u8 tc_map = 0;
4488 int ret;
4489 u8 v;
4490
4491 /* Enable the TCs available on PF to all VEBs */
4492 tc_map = i40e_pf_get_tc_map(pf);
4493 for (v = 0; v < I40E_MAX_VEB; v++) {
4494 if (!pf->veb[v])
4495 continue;
4496 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4497 if (ret) {
4498 dev_info(&pf->pdev->dev,
4499 "Failed configuring TC for VEB seid=%d\n",
4500 pf->veb[v]->seid);
4501 /* Will try to configure as many components */
4502 }
4503 }
4504
4505 /* Update each VSI */
505682cd 4506 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4507 if (!pf->vsi[v])
4508 continue;
4509
4510 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4511#ifdef I40E_FCOE
4512 * - For FCoE VSI only enable the TC configured
4513 * as per the APP TLV
4514#endif
4e3b35b0
NP		 4515 * - For all others keep them at TC0 for now
4516 */
4517 if (v == pf->lan_vsi)
4518 tc_map = i40e_pf_get_tc_map(pf);
4519 else
4520 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4521#ifdef I40E_FCOE
4522 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4523 tc_map = i40e_get_fcoe_tc_map(pf);
4524#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4525
4526 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4527 if (ret) {
4528 dev_info(&pf->pdev->dev,
4529 "Failed configuring TC for VSI seid=%d\n",
4530 pf->vsi[v]->seid);
4531 /* Will try to configure as many components */
4532 } else {
0672a091
NP		 4533 /* Re-configure VSI vectors based on updated TC map */
4534 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4535 if (pf->vsi[v]->netdev)
4536 i40e_dcbnl_set_all(pf->vsi[v]);
4537 }
4538 }
4539}
4540
2fd75f31
NP		 4541/**
4542 * i40e_resume_port_tx - Resume port Tx
4543 * @pf: PF struct
4544 *
4545 * Resume a port's Tx and issue a PF reset in case of failure to
4546 * resume.
4547 **/
4548static int i40e_resume_port_tx(struct i40e_pf *pf)
4549{
4550 struct i40e_hw *hw = &pf->hw;
4551 int ret;
4552
4553 ret = i40e_aq_resume_port_tx(hw, NULL);
4554 if (ret) {
4555 dev_info(&pf->pdev->dev,
4556 "AQ command Resume Port Tx failed = %d\n",
4557 pf->hw.aq.asq_last_status);
4558 /* Schedule PF reset to recover */
4559 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4560 i40e_service_event_schedule(pf);
4561 }
4562
4563 return ret;
4564}
4565
4e3b35b0
NP		 4566/**
4567 * i40e_init_pf_dcb - Initialize DCB configuration
4568 * @pf: PF being configured
4569 *
4570 * Query the current DCB configuration and cache it
4571 * in the hardware structure
4572 **/
4573static int i40e_init_pf_dcb(struct i40e_pf *pf)
4574{
4575 struct i40e_hw *hw = &pf->hw;
4576 int err = 0;
4577
025b4a54
ASJ		 4578 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4579 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4580 (pf->hw.aq.fw_maj_ver < 4))
4581 goto out;
4582
4e3b35b0
NP		 4583 /* Get the initial DCB configuration */
4584 err = i40e_init_dcb(hw);
4585 if (!err) {
4586 /* Device/Function is not DCBX capable */
4587 if ((!hw->func_caps.dcb) ||
4588 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4589 dev_info(&pf->pdev->dev,
4590 "DCBX offload is not supported or is disabled for this PF.\n");
4591
4592 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4593 goto out;
4594
4595 } else {
4596 /* When status is not DISABLED then DCBX in FW */
4597 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4598 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4599
4600 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4601 /* Enable DCB tagging only when more than one TC */
4602 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4603 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4604 dev_dbg(&pf->pdev->dev,
4605 "DCBX offload is supported for this PF.\n");
4e3b35b0 4606 }
014269ff 4607 } else {
aebfc816
SN		 4608 dev_info(&pf->pdev->dev,
4609 "AQ Querying DCB configuration failed: aq_err %d\n",
014269ff 4610 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4611 }
4612
4613out:
4614 return err;
4615}
4616#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4617#define SPEED_SIZE 14
4618#define FC_SIZE 8
4619/**
4620 * i40e_print_link_message - print link up or down
4621 * @vsi: the VSI for which link needs a message
4622 */
4623static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4624{
4625 char speed[SPEED_SIZE] = "Unknown";
4626 char fc[FC_SIZE] = "RX/TX";
4627
4628 if (!isup) {
4629 netdev_info(vsi->netdev, "NIC Link is Down\n");
4630 return;
4631 }
4632
148c2d80
GR		 4633 /* Warn user if link speed on NPAR enabled partition is not at
4634 * least 10GB
4635 */
4636 if (vsi->back->hw.func_caps.npar_enable &&
4637 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4638 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4639 netdev_warn(vsi->netdev,
4640 "The partition detected link speed that is less than 10Gbps\n");
4641
cf05ed08
JB		 4642 switch (vsi->back->hw.phy.link_info.link_speed) {
4643 case I40E_LINK_SPEED_40GB:
35a7d804 4644 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08 4645 break;
ae24b409
JB		 4646 case I40E_LINK_SPEED_20GB:
4647 strncpy(speed, "20 Gbps", SPEED_SIZE);
4648 break;
cf05ed08 4649 case I40E_LINK_SPEED_10GB:
35a7d804 4650 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4651 break;
4652 case I40E_LINK_SPEED_1GB:
35a7d804 4653 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4654 break;
5960d33f
MW		 4655 case I40E_LINK_SPEED_100MB:
4656 strncpy(speed, "100 Mbps", SPEED_SIZE);
4657 break;
cf05ed08
JB		 4658 default:
4659 break;
4660 }
4661
4662 switch (vsi->back->hw.fc.current_mode) {
4663 case I40E_FC_FULL:
35a7d804 4664 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4665 break;
4666 case I40E_FC_TX_PAUSE:
35a7d804 4667 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4668 break;
4669 case I40E_FC_RX_PAUSE:
35a7d804 4670 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4671 break;
4672 default:
35a7d804 4673 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4674 break;
4675 }
4676
4677 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4678 speed, fc);
4679}
4e3b35b0 4680
41c445ff
JB		 4681/**
4682 * i40e_up_complete - Finish the last steps of bringing up a connection
4683 * @vsi: the VSI being configured
4684 **/
4685static int i40e_up_complete(struct i40e_vsi *vsi)
4686{
4687 struct i40e_pf *pf = vsi->back;
4688 int err;
4689
4690 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4691 i40e_vsi_configure_msix(vsi);
4692 else
4693 i40e_configure_msi_and_legacy(vsi);
4694
4695 /* start rings */
4696 err = i40e_vsi_control_rings(vsi, true);
4697 if (err)
4698 return err;
4699
4700 clear_bit(__I40E_DOWN, &vsi->state);
4701 i40e_napi_enable_all(vsi);
4702 i40e_vsi_enable_irq(vsi);
4703
4704 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4705 (vsi->netdev)) {
cf05ed08 4706 i40e_print_link_message(vsi, true);
41c445ff
JB		 4707 netif_tx_start_all_queues(vsi->netdev);
4708 netif_carrier_on(vsi->netdev);
6d779b41 4709 } else if (vsi->netdev) {
cf05ed08 4710 i40e_print_link_message(vsi, false);
7b592f61
CW		 4711 /* need to check for qualified module here*/
4712 if ((pf->hw.phy.link_info.link_info &
4713 I40E_AQ_MEDIA_AVAILABLE) &&
4714 (!(pf->hw.phy.link_info.an_info &
4715 I40E_AQ_QUALIFIED_MODULE)))
4716 netdev_err(vsi->netdev,
4717 "the driver failed to link because an unqualified module was detected.");
41c445ff 4718 }
ca64fa4e
ASJ		 4719
4720 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4721 if (vsi->type == I40E_VSI_FDIR) {
4722 /* reset fd counters */
4723 pf->fd_add_err = pf->fd_atr_cnt = 0;
4724 if (pf->fd_tcp_rule > 0) {
4725 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4726 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4727 pf->fd_tcp_rule = 0;
4728 }
ca64fa4e 4729 i40e_fdir_filter_restore(vsi);
1e1be8f6 4730 }
41c445ff
JB		 4731 i40e_service_event_schedule(pf);
4732
4733 return 0;
4734}
4735
4736/**
4737 * i40e_vsi_reinit_locked - Reset the VSI
4738 * @vsi: the VSI being configured
4739 *
4740 * Rebuild the ring structs after some configuration
4741 * has changed, e.g. MTU size.
4742 **/
4743static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4744{
4745 struct i40e_pf *pf = vsi->back;
4746
4747 WARN_ON(in_interrupt());
4748 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4749 usleep_range(1000, 2000);
4750 i40e_down(vsi);
4751
4752 /* Give a VF some time to respond to the reset. The
4753 * two second wait is based upon the watchdog cycle in
4754 * the VF driver.
4755 */
4756 if (vsi->type == I40E_VSI_SRIOV)
4757 msleep(2000);
4758 i40e_up(vsi);
4759 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4760}
4761
4762/**
4763 * i40e_up - Bring the connection back up after being down
4764 * @vsi: the VSI being configured
4765 **/
4766int i40e_up(struct i40e_vsi *vsi)
4767{
4768 int err;
4769
4770 err = i40e_vsi_configure(vsi);
4771 if (!err)
4772 err = i40e_up_complete(vsi);
4773
4774 return err;
4775}
4776
4777/**
4778 * i40e_down - Shutdown the connection processing
4779 * @vsi: the VSI being stopped
4780 **/
4781void i40e_down(struct i40e_vsi *vsi)
4782{
4783 int i;
4784
4785 /* It is assumed that the caller of this function
4786 * sets the vsi->state __I40E_DOWN bit.
4787 */
4788 if (vsi->netdev) {
4789 netif_carrier_off(vsi->netdev);
4790 netif_tx_disable(vsi->netdev);
4791 }
4792 i40e_vsi_disable_irq(vsi);
4793 i40e_vsi_control_rings(vsi, false);
4794 i40e_napi_disable_all(vsi);
4795
4796 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4797 i40e_clean_tx_ring(vsi->tx_rings[i]);
4798 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4799 }
4800}
4801
4802/**
4803 * i40e_setup_tc - configure multiple traffic classes
4804 * @netdev: net device to configure
4805 * @tc: number of traffic classes to enable
4806 **/
38e00438
VD		 4807#ifdef I40E_FCOE
4808int i40e_setup_tc(struct net_device *netdev, u8 tc)
4809#else
41c445ff 4810static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4811#endif
41c445ff
JB		 4812{
4813 struct i40e_netdev_priv *np = netdev_priv(netdev);
4814 struct i40e_vsi *vsi = np->vsi;
4815 struct i40e_pf *pf = vsi->back;
4816 u8 enabled_tc = 0;
4817 int ret = -EINVAL;
4818 int i;
4819
4820 /* Check if DCB enabled to continue */
4821 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4822 netdev_info(netdev, "DCB is not enabled for adapter\n");
4823 goto exit;
4824 }
4825
4826 /* Check if MFP enabled */
4827 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4828 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4829 goto exit;
4830 }
4831
4832 /* Check whether tc count is within enabled limit */
4833 if (tc > i40e_pf_get_num_tc(pf)) {
4834 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4835 goto exit;
4836 }
4837
4838 /* Generate TC map for number of tc requested */
4839 for (i = 0; i < tc; i++)
4840 enabled_tc |= (1 << i);
4841
4842 /* Requesting same TC configuration as already enabled */
4843 if (enabled_tc == vsi->tc_config.enabled_tc)
4844 return 0;
4845
4846 /* Quiesce VSI queues */
4847 i40e_quiesce_vsi(vsi);
4848
4849 /* Configure VSI for enabled TCs */
4850 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4851 if (ret) {
4852 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4853 vsi->seid);
4854 goto exit;
4855 }
4856
4857 /* Unquiesce VSI */
4858 i40e_unquiesce_vsi(vsi);
4859
4860exit:
4861 return ret;
4862}
4863
4864/**
4865 * i40e_open - Called when a network interface is made active
4866 * @netdev: network interface device structure
4867 *
4868 * The open entry point is called when a network interface is made
4869 * active by the system (IFF_UP). At this point all resources needed
4870 * for transmit and receive operations are allocated, the interrupt
4871 * handler is registered with the OS, the netdev watchdog subtask is
4872 * enabled, and the stack is notified that the interface is ready.
4873 *
4874 * Returns 0 on success, negative value on failure
4875 **/
38e00438 4876int i40e_open(struct net_device *netdev)
41c445ff
JB		 4877{
4878 struct i40e_netdev_priv *np = netdev_priv(netdev);
4879 struct i40e_vsi *vsi = np->vsi;
4880 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4881 int err;
4882
4eb3f768
SN		 4883 /* disallow open during test or if eeprom is broken */
4884 if (test_bit(__I40E_TESTING, &pf->state) ||
4885 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4886 return -EBUSY;
4887
4888 netif_carrier_off(netdev);
4889
6c167f58
EK		 4890 err = i40e_vsi_open(vsi);
4891 if (err)
4892 return err;
4893
059dab69
JB		 4894 /* configure global TSO hardware offload settings */
4895 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4896 TCP_FLAG_FIN) >> 16);
4897 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4898 TCP_FLAG_FIN |
4899 TCP_FLAG_CWR) >> 16);
4900 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4901
6c167f58
EK		 4902#ifdef CONFIG_I40E_VXLAN
4903 vxlan_get_rx_port(netdev);
4904#endif
4905
4906 return 0;
4907}
4908
4909/**
4910 * i40e_vsi_open -
4911 * @vsi: the VSI to open
4912 *
4913 * Finish initialization of the VSI.
4914 *
4915 * Returns 0 on success, negative value on failure
4916 **/
4917int i40e_vsi_open(struct i40e_vsi *vsi)
4918{
4919 struct i40e_pf *pf = vsi->back;
b294ac70 4920 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 4921 int err;
4922
41c445ff
JB		 4923 /* allocate descriptors */
4924 err = i40e_vsi_setup_tx_resources(vsi);
4925 if (err)
4926 goto err_setup_tx;
4927 err = i40e_vsi_setup_rx_resources(vsi);
4928 if (err)
4929 goto err_setup_rx;
4930
4931 err = i40e_vsi_configure(vsi);
4932 if (err)
4933 goto err_setup_rx;
4934
c22e3c6c
SN		 4935 if (vsi->netdev) {
4936 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4937 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4938 err = i40e_vsi_request_irq(vsi, int_name);
4939 if (err)
4940 goto err_setup_rx;
41c445ff 4941
c22e3c6c
SN		 4942 /* Notify the stack of the actual queue counts. */
4943 err = netif_set_real_num_tx_queues(vsi->netdev,
4944 vsi->num_queue_pairs);
4945 if (err)
4946 goto err_set_queues;
25946ddb 4947
c22e3c6c
SN		 4948 err = netif_set_real_num_rx_queues(vsi->netdev,
4949 vsi->num_queue_pairs);
4950 if (err)
4951 goto err_set_queues;
8a9eb7d3
SN		 4952
4953 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 4954 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 4955 dev_driver_string(&pf->pdev->dev),
4956 dev_name(&pf->pdev->dev));
8a9eb7d3 4957 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 4958
c22e3c6c 4959 } else {
ce9ccb17 4960 err = -EINVAL;
6c167f58
EK		 4961 goto err_setup_rx;
4962 }
25946ddb 4963
41c445ff
JB		 4964 err = i40e_up_complete(vsi);
4965 if (err)
4966 goto err_up_complete;
4967
41c445ff
JB		 4968 return 0;
4969
4970err_up_complete:
4971 i40e_down(vsi);
25946ddb 4972err_set_queues:
41c445ff
JB		 4973 i40e_vsi_free_irq(vsi);
4974err_setup_rx:
4975 i40e_vsi_free_rx_resources(vsi);
4976err_setup_tx:
4977 i40e_vsi_free_tx_resources(vsi);
4978 if (vsi == pf->vsi[pf->lan_vsi])
4979 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4980
4981 return err;
4982}
4983
17a73f6b
JG		 4984/**
4985 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 4986 * @pf: Pointer to PF
17a73f6b
JG		 4987 *
4988 * This function destroys the hlist where all the Flow Director
4989 * filters were saved.
4990 **/
4991static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4992{
4993 struct i40e_fdir_filter *filter;
4994 struct hlist_node *node2;
4995
4996 hlist_for_each_entry_safe(filter, node2,
4997 &pf->fdir_filter_list, fdir_node) {
4998 hlist_del(&filter->fdir_node);
4999 kfree(filter);
5000 }
5001 pf->fdir_pf_active_filters = 0;
5002}
5003
41c445ff
JB		 5004/**
5005 * i40e_close - Disables a network interface
5006 * @netdev: network interface device structure
5007 *
5008 * The close entry point is called when an interface is de-activated
5009 * by the OS. The hardware is still under the driver's control, but
5010 * this netdev interface is disabled.
5011 *
5012 * Returns 0, this is not allowed to fail
5013 **/
38e00438
VD		 5014#ifdef I40E_FCOE
5015int i40e_close(struct net_device *netdev)
5016#else
41c445ff 5017static int i40e_close(struct net_device *netdev)
38e00438 5018#endif
41c445ff
JB		 5019{
5020 struct i40e_netdev_priv *np = netdev_priv(netdev);
5021 struct i40e_vsi *vsi = np->vsi;
5022
90ef8d47 5023 i40e_vsi_close(vsi);
41c445ff
JB		 5024
5025 return 0;
5026}
5027
5028/**
5029 * i40e_do_reset - Start a PF or Core Reset sequence
5030 * @pf: board private structure
5031 * @reset_flags: which reset is requested
5032 *
5033 * The essential difference in resets is that the PF Reset
5034 * doesn't clear the packet buffers, doesn't reset the PE
5035 * firmware, and doesn't bother the other PFs on the chip.
5036 **/
5037void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5038{
5039 u32 val;
5040
5041 WARN_ON(in_interrupt());
5042
263fc48f
MW		 5043 if (i40e_check_asq_alive(&pf->hw))
5044 i40e_vc_notify_reset(pf);
5045
41c445ff
JB		 5046 /* do the biggest reset indicated */
5047 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
5048
5049 /* Request a Global Reset
5050 *
5051 * This will start the chip's countdown to the actual full
5052 * chip reset event, and a warning interrupt to be sent
5053 * to all PFs, including the requestor. Our handler
5054 * for the warning interrupt will deal with the shutdown
5055 * and recovery of the switch setup.
5056 */
69bfb110 5057 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5058 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5059 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5060 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5061
5062 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
5063
5064 /* Request a Core Reset
5065 *
5066 * Same as Global Reset, except does *not* include the MAC/PHY
5067 */
69bfb110 5068 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5069 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5070 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5071 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5072 i40e_flush(&pf->hw);
5073
5074 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
5075
5076 /* Request a PF Reset
5077 *
5078 * Resets only the PF-specific registers
5079 *
5080 * This goes directly to the tear-down and rebuild of
5081 * the switch, since we need to do all the recovery as
5082 * for the Core Reset.
5083 */
69bfb110 5084 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5085 i40e_handle_reset_warning(pf);
5086
5087 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
5088 int v;
5089
5090 /* Find the VSI(s) that requested a re-init */
5091 dev_info(&pf->pdev->dev,
5092 "VSI reinit requested\n");
505682cd 5093 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5094 struct i40e_vsi *vsi = pf->vsi[v];
5095 if (vsi != NULL &&
5096 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5097 i40e_vsi_reinit_locked(pf->vsi[v]);
5098 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5099 }
5100 }
5101
b5d06f05
NP		 5102 /* no further action needed, so return now */
5103 return;
5104 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
5105 int v;
5106
5107 /* Find the VSI(s) that needs to be brought down */
5108 dev_info(&pf->pdev->dev, "VSI down requested\n");
5109 for (v = 0; v < pf->num_alloc_vsi; v++) {
5110 struct i40e_vsi *vsi = pf->vsi[v];
5111 if (vsi != NULL &&
5112 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5113 set_bit(__I40E_DOWN, &vsi->state);
5114 i40e_down(vsi);
5115 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5116 }
5117 }
5118
41c445ff
JB		 5119 /* no further action needed, so return now */
5120 return;
5121 } else {
5122 dev_info(&pf->pdev->dev,
5123 "bad reset request 0x%08x\n", reset_flags);
5124 return;
5125 }
5126}
5127
4e3b35b0
NP		 5128#ifdef CONFIG_I40E_DCB
5129/**
5130 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5131 * @pf: board private structure
5132 * @old_cfg: current DCB config
5133 * @new_cfg: new DCB config
5134 **/
5135bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5136 struct i40e_dcbx_config *old_cfg,
5137 struct i40e_dcbx_config *new_cfg)
5138{
5139 bool need_reconfig = false;
5140
5141 /* Check if ETS configuration has changed */
5142 if (memcmp(&new_cfg->etscfg,
5143 &old_cfg->etscfg,
5144 sizeof(new_cfg->etscfg))) {
5145 /* If Priority Table has changed reconfig is needed */
5146 if (memcmp(&new_cfg->etscfg.prioritytable,
5147 &old_cfg->etscfg.prioritytable,
5148 sizeof(new_cfg->etscfg.prioritytable))) {
5149 need_reconfig = true;
69bfb110 5150 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5151 }
5152
5153 if (memcmp(&new_cfg->etscfg.tcbwtable,
5154 &old_cfg->etscfg.tcbwtable,
5155 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5156 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5157
5158 if (memcmp(&new_cfg->etscfg.tsatable,
5159 &old_cfg->etscfg.tsatable,
5160 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5161 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5162 }
5163
5164 /* Check if PFC configuration has changed */
5165 if (memcmp(&new_cfg->pfc,
5166 &old_cfg->pfc,
5167 sizeof(new_cfg->pfc))) {
5168 need_reconfig = true;
69bfb110 5169 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5170 }
5171
5172 /* Check if APP Table has changed */
5173 if (memcmp(&new_cfg->app,
5174 &old_cfg->app,
3d9667a9 5175 sizeof(new_cfg->app))) {
4e3b35b0 5176 need_reconfig = true;
69bfb110 5177 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5178 }
4e3b35b0 5179
9fa61dd2
NP		 5180 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5181 need_reconfig);
4e3b35b0
NP		 5182 return need_reconfig;
5183}
5184
5185/**
5186 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5187 * @pf: board private structure
5188 * @e: event info posted on ARQ
5189 **/
5190static int i40e_handle_lldp_event(struct i40e_pf *pf,
5191 struct i40e_arq_event_info *e)
5192{
5193 struct i40e_aqc_lldp_get_mib *mib =
5194 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5195 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5196 struct i40e_dcbx_config tmp_dcbx_cfg;
5197 bool need_reconfig = false;
5198 int ret = 0;
5199 u8 type;
5200
4d9b6043
NP		 5201 /* Not DCB capable or capability disabled */
5202 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5203 return ret;
5204
4e3b35b0
NP		 5205 /* Ignore if event is not for Nearest Bridge */
5206 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5207 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5208 dev_dbg(&pf->pdev->dev,
5209 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5210 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5211 return ret;
5212
5213 /* Check MIB Type and return if event for Remote MIB update */
5214 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5215 dev_dbg(&pf->pdev->dev,
5216 "%s: LLDP event mib type %s\n", __func__,
5217 type ? "remote" : "local");
4e3b35b0
NP		 5218 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5219 /* Update the remote cached instance and return */
5220 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5221 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5222 &hw->remote_dcbx_config);
5223 goto exit;
5224 }
5225
9fa61dd2 5226 /* Store the old configuration */
1a2f6248 5227 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5228
750fcbcf
NP		 5229 /* Reset the old DCBx configuration data */
5230 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5231 /* Get updated DCBX data from firmware */
5232 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5233 if (ret) {
9fa61dd2 5234 dev_info(&pf->pdev->dev, "Failed querying DCB configuration data from firmware.\n");
4e3b35b0
NP		 5235 goto exit;
5236 }
5237
5238 /* No change detected in DCBX configs */
750fcbcf
NP		 5239 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5240 sizeof(tmp_dcbx_cfg))) {
69bfb110 5241 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5242 goto exit;
5243 }
5244
750fcbcf
NP		 5245 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5246 &hw->local_dcbx_config);
4e3b35b0 5247
750fcbcf 5248 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5249
5250 if (!need_reconfig)
5251 goto exit;
5252
4d9b6043 5253 /* Enable DCB tagging only when more than one TC */
750fcbcf 5254 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5255 pf->flags |= I40E_FLAG_DCB_ENABLED;
5256 else
5257 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5258
69129dc3 5259 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5260 /* Reconfiguration needed quiesce all VSIs */
5261 i40e_pf_quiesce_all_vsi(pf);
5262
5263 /* Changes in configuration update VEB/VSI */
5264 i40e_dcb_reconfigure(pf);
5265
2fd75f31
NP		 5266 ret = i40e_resume_port_tx(pf);
5267
69129dc3 5268 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5269 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5270 if (ret)
5271 goto exit;
5272
5273 /* Wait for the PF's Tx queues to be disabled */
5274 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5275 if (ret) {
5276 /* Schedule PF reset to recover */
5277 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5278 i40e_service_event_schedule(pf);
5279 } else {
2fd75f31 5280 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5281 }
5282
4e3b35b0
NP		 5283exit:
5284 return ret;
5285}
5286#endif /* CONFIG_I40E_DCB */
5287
23326186
ASJ		 5288/**
5289 * i40e_do_reset_safe - Protected reset path for userland calls.
5290 * @pf: board private structure
5291 * @reset_flags: which reset is requested
5292 *
5293 **/
5294void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5295{
5296 rtnl_lock();
5297 i40e_do_reset(pf, reset_flags);
5298 rtnl_unlock();
5299}
5300
41c445ff
JB		 5301/**
5302 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5303 * @pf: board private structure
5304 * @e: event info posted on ARQ
5305 *
5306 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5307 * and VF queues
5308 **/
5309static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5310 struct i40e_arq_event_info *e)
5311{
5312 struct i40e_aqc_lan_overflow *data =
5313 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5314 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5315 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5316 struct i40e_hw *hw = &pf->hw;
5317 struct i40e_vf *vf;
5318 u16 vf_id;
5319
69bfb110
JB		 5320 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5321 queue, qtx_ctl);
41c445ff
JB		 5322
5323 /* Queue belongs to VF, find the VF and issue VF reset */
5324 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5325 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5326 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5327 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5328 vf_id -= hw->func_caps.vf_base_id;
5329 vf = &pf->vf[vf_id];
5330 i40e_vc_notify_vf_reset(vf);
5331 /* Allow VF to process pending reset notification */
5332 msleep(20);
5333 i40e_reset_vf(vf, false);
5334 }
5335}
5336
5337/**
5338 * i40e_service_event_complete - Finish up the service event
5339 * @pf: board private structure
5340 **/
5341static void i40e_service_event_complete(struct i40e_pf *pf)
5342{
5343 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5344
5345 /* flush memory to make sure state is correct before next watchog */
4e857c58 5346 smp_mb__before_atomic();
41c445ff
JB		 5347 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5348}
5349
55a5e60b 5350/**
12957388
ASJ		 5351 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5352 * @pf: board private structure
5353 **/
04294e38 5354u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5355{
04294e38 5356 u32 val, fcnt_prog;
12957388
ASJ		 5357
5358 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5359 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5360 return fcnt_prog;
5361}
5362
5363/**
04294e38 5364 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5365 * @pf: board private structure
5366 **/
04294e38 5367u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5368{
04294e38
ASJ		 5369 u32 val, fcnt_prog;
5370
55a5e60b
ASJ		 5371 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5372 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5373 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5374 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5375 return fcnt_prog;
5376}
1e1be8f6 5377
04294e38
ASJ		 5378/**
5379 * i40e_get_global_fd_count - Get total FD filters programmed on device
5380 * @pf: board private structure
5381 **/
5382u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5383{
5384 u32 val, fcnt_prog;
5385
5386 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5387 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5388 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5389 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5390 return fcnt_prog;
5391}
5392
55a5e60b
ASJ		 5393/**
5394 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5395 * @pf: board private structure
5396 **/
5397void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5398{
5399 u32 fcnt_prog, fcnt_avail;
5400
1e1be8f6
ASJ		 5401 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5402 return;
5403
55a5e60b
ASJ		 5404 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5405 * to re-enable
5406 */
04294e38 5407 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5408 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5409 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5410 (pf->fd_add_err == 0) ||
5411 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5412 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5413 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5414 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5415 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5416 }
5417 }
5418 /* Wait for some more space to be available to turn on ATR */
5419 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5420 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5421 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5422 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5423 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5424 }
5425 }
5426}
5427
1e1be8f6 5428#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5429#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5430/**
5431 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5432 * @pf: board private structure
5433 **/
5434static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5435{
04294e38 5436 unsigned long min_flush_time;
1e1be8f6 5437 int flush_wait_retry = 50;
04294e38
ASJ		 5438 bool disable_atr = false;
5439 int fd_room;
1e1be8f6
ASJ		 5440 int reg;
5441
1790ed0c
AA		 5442 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5443 return;
5444
1e1be8f6
ASJ		 5445 if (time_after(jiffies, pf->fd_flush_timestamp +
5446 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
04294e38
ASJ		 5447 /* If the flush is happening too quick and we have mostly
5448 * SB rules we should not re-enable ATR for some time.
5449 */
5450 min_flush_time = pf->fd_flush_timestamp
5451 + (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5452 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5453
5454 if (!(time_after(jiffies, min_flush_time)) &&
5455 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5456 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5457 disable_atr = true;
5458 }
5459
1e1be8f6 5460 pf->fd_flush_timestamp = jiffies;
1e1be8f6
ASJ		 5461 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5462 /* flush all filters */
5463 wr32(&pf->hw, I40E_PFQF_CTL_1,
5464 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5465 i40e_flush(&pf->hw);
60793f4a 5466 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5467 pf->fd_add_err = 0;
5468 do {
5469 /* Check FD flush status every 5-6msec */
5470 usleep_range(5000, 6000);
5471 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5472 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5473 break;
5474 } while (flush_wait_retry--);
5475 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5476 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5477 } else {
5478 /* replay sideband filters */
5479 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
04294e38
ASJ		 5480 if (!disable_atr)
5481 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
1e1be8f6
ASJ		 5482 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5483 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5484 }
5485 }
5486}
5487
5488/**
5489 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5490 * @pf: board private structure
5491 **/
04294e38 5492u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5493{
5494 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5495}
5496
5497/* We can see up to 256 filter programming desc in transit if the filters are
5498 * being applied really fast; before we see the first
5499 * filter miss error on Rx queue 0. Accumulating enough error messages before
5500 * reacting will make sure we don't cause flush too often.
5501 */
5502#define I40E_MAX_FD_PROGRAM_ERROR 256
5503
41c445ff
JB		 5504/**
5505 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5506 * @pf: board private structure
5507 **/
5508static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5509{
41c445ff 5510
41c445ff
JB		 5511 /* if interface is down do nothing */
5512 if (test_bit(__I40E_DOWN, &pf->state))
5513 return;
1e1be8f6 5514
1790ed0c
AA		 5515 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5516 return;
5517
04294e38 5518 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5519 i40e_fdir_flush_and_replay(pf);
5520
55a5e60b
ASJ		 5521 i40e_fdir_check_and_reenable(pf);
5522
41c445ff
JB		 5523}
5524
5525/**
5526 * i40e_vsi_link_event - notify VSI of a link event
5527 * @vsi: vsi to be notified
5528 * @link_up: link up or down
5529 **/
5530static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5531{
32b5b811 5532 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5533 return;
5534
5535 switch (vsi->type) {
5536 case I40E_VSI_MAIN:
38e00438
VD		 5537#ifdef I40E_FCOE
5538 case I40E_VSI_FCOE:
5539#endif
41c445ff
JB		 5540 if (!vsi->netdev || !vsi->netdev_registered)
5541 break;
5542
5543 if (link_up) {
5544 netif_carrier_on(vsi->netdev);
5545 netif_tx_wake_all_queues(vsi->netdev);
5546 } else {
5547 netif_carrier_off(vsi->netdev);
5548 netif_tx_stop_all_queues(vsi->netdev);
5549 }
5550 break;
5551
5552 case I40E_VSI_SRIOV:
41c445ff
JB		 5553 case I40E_VSI_VMDQ2:
5554 case I40E_VSI_CTRL:
5555 case I40E_VSI_MIRROR:
5556 default:
5557 /* there is no notification for other VSIs */
5558 break;
5559 }
5560}
5561
5562/**
5563 * i40e_veb_link_event - notify elements on the veb of a link event
5564 * @veb: veb to be notified
5565 * @link_up: link up or down
5566 **/
5567static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5568{
5569 struct i40e_pf *pf;
5570 int i;
5571
5572 if (!veb || !veb->pf)
5573 return;
5574 pf = veb->pf;
5575
5576 /* depth first... */
5577 for (i = 0; i < I40E_MAX_VEB; i++)
5578 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5579 i40e_veb_link_event(pf->veb[i], link_up);
5580
5581 /* ... now the local VSIs */
505682cd 5582 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5583 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5584 i40e_vsi_link_event(pf->vsi[i], link_up);
5585}
5586
5587/**
5588 * i40e_link_event - Update netif_carrier status
5589 * @pf: board private structure
5590 **/
5591static void i40e_link_event(struct i40e_pf *pf)
5592{
5593 bool new_link, old_link;
320684cd 5594 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5595 u8 new_link_speed, old_link_speed;
41c445ff 5596
1e701e09
JB		 5597 /* set this to force the get_link_status call to refresh state */
5598 pf->hw.phy.get_link_info = true;
5599
41c445ff 5600 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5601 new_link = i40e_get_link_status(&pf->hw);
fef59ddf
CS		 5602 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5603 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5604
1e701e09 5605 if (new_link == old_link &&
fef59ddf 5606 new_link_speed == old_link_speed &&
320684cd
MW		 5607 (test_bit(__I40E_DOWN, &vsi->state) ||
5608 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5609 return;
320684cd
MW		 5610
5611 if (!test_bit(__I40E_DOWN, &vsi->state))
5612 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5613
5614 /* Notify the base of the switch tree connected to
5615 * the link. Floating VEBs are not notified.
5616 */
5617 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5618 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5619 else
320684cd 5620 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5621
5622 if (pf->vf)
5623 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5624
5625 if (pf->flags & I40E_FLAG_PTP)
5626 i40e_ptp_set_increment(pf);
41c445ff
JB		 5627}
5628
5629/**
5630 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5631 * @pf: board private structure
5632 *
5633 * Set the per-queue flags to request a check for stuck queues in the irq
5634 * clean functions, then force interrupts to be sure the irq clean is called.
5635 **/
5636static void i40e_check_hang_subtask(struct i40e_pf *pf)
5637{
5638 int i, v;
5639
5640 /* If we're down or resetting, just bail */
b67a0335
AA		 5641 if (test_bit(__I40E_DOWN, &pf->state) ||
5642 test_bit(__I40E_CONFIG_BUSY, &pf->state))
41c445ff
JB		 5643 return;
5644
5645 /* for each VSI/netdev
5646 * for each Tx queue
5647 * set the check flag
5648 * for each q_vector
5649 * force an interrupt
5650 */
505682cd 5651 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5652 struct i40e_vsi *vsi = pf->vsi[v];
5653 int armed = 0;
5654
5655 if (!pf->vsi[v] ||
5656 test_bit(__I40E_DOWN, &vsi->state) ||
5657 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5658 continue;
5659
5660 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5661 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5662 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5663 &vsi->tx_rings[i]->state))
41c445ff
JB		 5664 armed++;
5665 }
5666
5667 if (armed) {
5668 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5669 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5670 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5d1ff106
SN		 5671 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
5672 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
5673 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
5674 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
41c445ff
JB		 5675 } else {
5676 u16 vec = vsi->base_vector - 1;
5677 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5d1ff106
SN		 5678 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
5679 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK |
5680 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK |
5681 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK);
41c445ff
JB		 5682 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5683 wr32(&vsi->back->hw,
5684 I40E_PFINT_DYN_CTLN(vec), val);
5685 }
5686 i40e_flush(&vsi->back->hw);
5687 }
5688 }
5689}
5690
5691/**
21536717 5692 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5693 * @pf: board private structure
5694 **/
5695static void i40e_watchdog_subtask(struct i40e_pf *pf)
5696{
5697 int i;
5698
5699 /* if interface is down do nothing */
5700 if (test_bit(__I40E_DOWN, &pf->state) ||
5701 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5702 return;
5703
21536717
SN		 5704 /* make sure we don't do these things too often */
5705 if (time_before(jiffies, (pf->service_timer_previous +
5706 pf->service_timer_period)))
5707 return;
5708 pf->service_timer_previous = jiffies;
5709
5710 i40e_check_hang_subtask(pf);
5711 i40e_link_event(pf);
5712
41c445ff
JB		 5713 /* Update the stats for active netdevs so the network stack
5714 * can look at updated numbers whenever it cares to
5715 */
505682cd 5716 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5717 if (pf->vsi[i] && pf->vsi[i]->netdev)
5718 i40e_update_stats(pf->vsi[i]);
5719
5720 /* Update the stats for the active switching components */
5721 for (i = 0; i < I40E_MAX_VEB; i++)
5722 if (pf->veb[i])
5723 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5724
5725 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5726}
5727
5728/**
5729 * i40e_reset_subtask - Set up for resetting the device and driver
5730 * @pf: board private structure
5731 **/
5732static void i40e_reset_subtask(struct i40e_pf *pf)
5733{
5734 u32 reset_flags = 0;
5735
23326186 5736 rtnl_lock();
41c445ff
JB		 5737 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5738 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5739 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5740 }
5741 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5742 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5743 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5744 }
5745 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5746 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5747 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5748 }
5749 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5750 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5751 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5752 }
b5d06f05
NP		 5753 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5754 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5755 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5756 }
41c445ff
JB		 5757
5758 /* If there's a recovery already waiting, it takes
5759 * precedence before starting a new reset sequence.
5760 */
5761 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5762 i40e_handle_reset_warning(pf);
23326186 5763 goto unlock;
41c445ff
JB		 5764 }
5765
5766 /* If we're already down or resetting, just bail */
5767 if (reset_flags &&
5768 !test_bit(__I40E_DOWN, &pf->state) &&
5769 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5770 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5771
5772unlock:
5773 rtnl_unlock();
41c445ff
JB		 5774}
5775
5776/**
5777 * i40e_handle_link_event - Handle link event
5778 * @pf: board private structure
5779 * @e: event info posted on ARQ
5780 **/
5781static void i40e_handle_link_event(struct i40e_pf *pf,
5782 struct i40e_arq_event_info *e)
5783{
5784 struct i40e_hw *hw = &pf->hw;
5785 struct i40e_aqc_get_link_status *status =
5786 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff
JB		 5787
5788 /* save off old link status information */
1a2f6248 5789 hw->phy.link_info_old = hw->phy.link_info;
41c445ff 5790
1e701e09
JB		 5791 /* Do a new status request to re-enable LSE reporting
5792 * and load new status information into the hw struct
5793 * This completely ignores any state information
5794 * in the ARQ event info, instead choosing to always
5795 * issue the AQ update link status command.
5796 */
5797 i40e_link_event(pf);
5798
7b592f61
CW		 5799 /* check for unqualified module, if link is down */
5800 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5801 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5802 (!(status->link_info & I40E_AQ_LINK_UP)))
5803 dev_err(&pf->pdev->dev,
5804 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5805}
5806
5807/**
5808 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5809 * @pf: board private structure
5810 **/
5811static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5812{
5813 struct i40e_arq_event_info event;
5814 struct i40e_hw *hw = &pf->hw;
5815 u16 pending, i = 0;
5816 i40e_status ret;
5817 u16 opcode;
86df242b 5818 u32 oldval;
41c445ff
JB		 5819 u32 val;
5820
a316f651
ASJ		 5821 /* Do not run clean AQ when PF reset fails */
5822 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5823 return;
5824
86df242b
SN		 5825 /* check for error indications */
5826 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5827 oldval = val;
5828 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5829 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5830 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5831 }
5832 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5833 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5834 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5835 }
5836 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5837 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5838 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5839 }
5840 if (oldval != val)
5841 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5842
5843 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5844 oldval = val;
5845 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5846 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5847 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5848 }
5849 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5850 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5851 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5852 }
5853 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5854 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5855 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5856 }
5857 if (oldval != val)
5858 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5859
1001dc37
MW		 5860 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
5861 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 5862 if (!event.msg_buf)
5863 return;
5864
5865 do {
5866 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5867 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5868 break;
56497978 5869 else if (ret) {
41c445ff
JB		 5870 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5871 break;
5872 }
5873
5874 opcode = le16_to_cpu(event.desc.opcode);
5875 switch (opcode) {
5876
5877 case i40e_aqc_opc_get_link_status:
5878 i40e_handle_link_event(pf, &event);
5879 break;
5880 case i40e_aqc_opc_send_msg_to_pf:
5881 ret = i40e_vc_process_vf_msg(pf,
5882 le16_to_cpu(event.desc.retval),
5883 le32_to_cpu(event.desc.cookie_high),
5884 le32_to_cpu(event.desc.cookie_low),
5885 event.msg_buf,
1001dc37 5886 event.msg_len);
41c445ff
JB		 5887 break;
5888 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5889 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5890#ifdef CONFIG_I40E_DCB
5891 rtnl_lock();
5892 ret = i40e_handle_lldp_event(pf, &event);
5893 rtnl_unlock();
5894#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5895 break;
5896 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5897 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5898 i40e_handle_lan_overflow_event(pf, &event);
5899 break;
0467bc91
SN		 5900 case i40e_aqc_opc_send_msg_to_peer:
5901 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5902 break;
91a0f930
SN		 5903 case i40e_aqc_opc_nvm_erase:
5904 case i40e_aqc_opc_nvm_update:
5905 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
5906 break;
41c445ff
JB		 5907 default:
5908 dev_info(&pf->pdev->dev,
0467bc91
SN		 5909 "ARQ Error: Unknown event 0x%04x received\n",
5910 opcode);
41c445ff
JB		 5911 break;
5912 }
5913 } while (pending && (i++ < pf->adminq_work_limit));
5914
5915 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5916 /* re-enable Admin queue interrupt cause */
5917 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5918 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5919 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5920 i40e_flush(hw);
5921
5922 kfree(event.msg_buf);
5923}
5924
4eb3f768
SN		 5925/**
5926 * i40e_verify_eeprom - make sure eeprom is good to use
5927 * @pf: board private structure
5928 **/
5929static void i40e_verify_eeprom(struct i40e_pf *pf)
5930{
5931 int err;
5932
5933 err = i40e_diag_eeprom_test(&pf->hw);
5934 if (err) {
5935 /* retry in case of garbage read */
5936 err = i40e_diag_eeprom_test(&pf->hw);
5937 if (err) {
5938 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5939 err);
5940 set_bit(__I40E_BAD_EEPROM, &pf->state);
5941 }
5942 }
5943
5944 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5945 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5946 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5947 }
5948}
5949
386a0afa
AA		 5950/**
5951 * i40e_enable_pf_switch_lb
b40c82e6 5952 * @pf: pointer to the PF structure
386a0afa
AA		 5953 *
5954 * enable switch loop back or die - no point in a return value
5955 **/
5956static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
5957{
5958 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
5959 struct i40e_vsi_context ctxt;
5960 int aq_ret;
5961
5962 ctxt.seid = pf->main_vsi_seid;
5963 ctxt.pf_num = pf->hw.pf_id;
5964 ctxt.vf_num = 0;
5965 aq_ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
5966 if (aq_ret) {
5967 dev_info(&pf->pdev->dev,
b40c82e6 5968 "%s couldn't get PF vsi config, err %d, aq_err %d\n",
386a0afa
AA		 5969 __func__, aq_ret, pf->hw.aq.asq_last_status);
5970 return;
5971 }
5972 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5973 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5974 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5975
5976 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
5977 if (aq_ret) {
5978 dev_info(&pf->pdev->dev,
5979 "%s: update vsi switch failed, aq_err=%d\n",
5980 __func__, vsi->back->hw.aq.asq_last_status);
5981 }
5982}
5983
5984/**
5985 * i40e_disable_pf_switch_lb
b40c82e6 5986 * @pf: pointer to the PF structure
386a0afa
AA		 5987 *
5988 * disable switch loop back or die - no point in a return value
5989 **/
5990static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
5991{
5992 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
5993 struct i40e_vsi_context ctxt;
5994 int aq_ret;
5995
5996 ctxt.seid = pf->main_vsi_seid;
5997 ctxt.pf_num = pf->hw.pf_id;
5998 ctxt.vf_num = 0;
5999 aq_ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6000 if (aq_ret) {
6001 dev_info(&pf->pdev->dev,
b40c82e6 6002 "%s couldn't get PF vsi config, err %d, aq_err %d\n",
386a0afa
AA		 6003 __func__, aq_ret, pf->hw.aq.asq_last_status);
6004 return;
6005 }
6006 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6007 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6008 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6009
6010 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6011 if (aq_ret) {
6012 dev_info(&pf->pdev->dev,
6013 "%s: update vsi switch failed, aq_err=%d\n",
6014 __func__, vsi->back->hw.aq.asq_last_status);
6015 }
6016}
6017
51616018
NP		 6018/**
6019 * i40e_config_bridge_mode - Configure the HW bridge mode
6020 * @veb: pointer to the bridge instance
6021 *
6022 * Configure the loop back mode for the LAN VSI that is downlink to the
6023 * specified HW bridge instance. It is expected this function is called
6024 * when a new HW bridge is instantiated.
6025 **/
6026static void i40e_config_bridge_mode(struct i40e_veb *veb)
6027{
6028 struct i40e_pf *pf = veb->pf;
6029
6030 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6031 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
6032 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6033 i40e_disable_pf_switch_lb(pf);
6034 else
6035 i40e_enable_pf_switch_lb(pf);
6036}
6037
41c445ff
JB		 6038/**
6039 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6040 * @veb: pointer to the VEB instance
6041 *
6042 * This is a recursive function that first builds the attached VSIs then
6043 * recurses in to build the next layer of VEB. We track the connections
6044 * through our own index numbers because the seid's from the HW could
6045 * change across the reset.
6046 **/
6047static int i40e_reconstitute_veb(struct i40e_veb *veb)
6048{
6049 struct i40e_vsi *ctl_vsi = NULL;
6050 struct i40e_pf *pf = veb->pf;
6051 int v, veb_idx;
6052 int ret;
6053
6054 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6055 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6056 if (pf->vsi[v] &&
6057 pf->vsi[v]->veb_idx == veb->idx &&
6058 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6059 ctl_vsi = pf->vsi[v];
6060 break;
6061 }
6062 }
6063 if (!ctl_vsi) {
6064 dev_info(&pf->pdev->dev,
6065 "missing owner VSI for veb_idx %d\n", veb->idx);
6066 ret = -ENOENT;
6067 goto end_reconstitute;
6068 }
6069 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6070 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6071 ret = i40e_add_vsi(ctl_vsi);
6072 if (ret) {
6073 dev_info(&pf->pdev->dev,
6074 "rebuild of owner VSI failed: %d\n", ret);
6075 goto end_reconstitute;
6076 }
6077 i40e_vsi_reset_stats(ctl_vsi);
6078
6079 /* create the VEB in the switch and move the VSI onto the VEB */
6080 ret = i40e_add_veb(veb, ctl_vsi);
6081 if (ret)
6082 goto end_reconstitute;
6083
51616018 6084 i40e_config_bridge_mode(veb);
b64ba084 6085
41c445ff 6086 /* create the remaining VSIs attached to this VEB */
505682cd 6087 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6088 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6089 continue;
6090
6091 if (pf->vsi[v]->veb_idx == veb->idx) {
6092 struct i40e_vsi *vsi = pf->vsi[v];
6093 vsi->uplink_seid = veb->seid;
6094 ret = i40e_add_vsi(vsi);
6095 if (ret) {
6096 dev_info(&pf->pdev->dev,
6097 "rebuild of vsi_idx %d failed: %d\n",
6098 v, ret);
6099 goto end_reconstitute;
6100 }
6101 i40e_vsi_reset_stats(vsi);
6102 }
6103 }
6104
6105 /* create any VEBs attached to this VEB - RECURSION */
6106 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6107 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6108 pf->veb[veb_idx]->uplink_seid = veb->seid;
6109 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6110 if (ret)
6111 break;
6112 }
6113 }
6114
6115end_reconstitute:
6116 return ret;
6117}
6118
6119/**
6120 * i40e_get_capabilities - get info about the HW
6121 * @pf: the PF struct
6122 **/
6123static int i40e_get_capabilities(struct i40e_pf *pf)
6124{
6125 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6126 u16 data_size;
6127 int buf_len;
6128 int err;
6129
6130 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6131 do {
6132 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6133 if (!cap_buf)
6134 return -ENOMEM;
6135
6136 /* this loads the data into the hw struct for us */
6137 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6138 &data_size,
6139 i40e_aqc_opc_list_func_capabilities,
6140 NULL);
6141 /* data loaded, buffer no longer needed */
6142 kfree(cap_buf);
6143
6144 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6145 /* retry with a larger buffer */
6146 buf_len = data_size;
6147 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6148 dev_info(&pf->pdev->dev,
6149 "capability discovery failed: aq=%d\n",
6150 pf->hw.aq.asq_last_status);
6151 return -ENODEV;
6152 }
6153 } while (err);
6154
ac71b7ba
ASJ		 6155 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6156 (pf->hw.aq.fw_maj_ver < 2)) {
6157 pf->hw.func_caps.num_msix_vectors++;
6158 pf->hw.func_caps.num_msix_vectors_vf++;
6159 }
6160
41c445ff
JB		 6161 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6162 dev_info(&pf->pdev->dev,
6163 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6164 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6165 pf->hw.func_caps.num_msix_vectors,
6166 pf->hw.func_caps.num_msix_vectors_vf,
6167 pf->hw.func_caps.fd_filters_guaranteed,
6168 pf->hw.func_caps.fd_filters_best_effort,
6169 pf->hw.func_caps.num_tx_qp,
6170 pf->hw.func_caps.num_vsis);
6171
7134f9ce
JB		 6172#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6173 + pf->hw.func_caps.num_vfs)
6174 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6175 dev_info(&pf->pdev->dev,
6176 "got num_vsis %d, setting num_vsis to %d\n",
6177 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6178 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6179 }
6180
41c445ff
JB		 6181 return 0;
6182}
6183
cbf61325
ASJ		 6184static int i40e_vsi_clear(struct i40e_vsi *vsi);
6185
41c445ff 6186/**
cbf61325 6187 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6188 * @pf: board private structure
6189 **/
cbf61325 6190static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6191{
6192 struct i40e_vsi *vsi;
8a9eb7d3 6193 int i;
41c445ff 6194
407e063c
JB		 6195 /* quick workaround for an NVM issue that leaves a critical register
6196 * uninitialized
6197 */
6198 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6199 static const u32 hkey[] = {
6200 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6201 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6202 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6203 0x95b3a76d};
6204
6205 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6206 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6207 }
6208
cbf61325 6209 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6210 return;
6211
cbf61325 6212 /* find existing VSI and see if it needs configuring */
41c445ff 6213 vsi = NULL;
505682cd 6214 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6215 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6216 vsi = pf->vsi[i];
cbf61325
ASJ		 6217 break;
6218 }
6219 }
6220
6221 /* create a new VSI if none exists */
41c445ff 6222 if (!vsi) {
cbf61325
ASJ		 6223 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6224 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6225 if (!vsi) {
6226 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6227 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6228 return;
41c445ff 6229 }
cbf61325 6230 }
41c445ff 6231
8a9eb7d3 6232 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6233}
6234
6235/**
6236 * i40e_fdir_teardown - release the Flow Director resources
6237 * @pf: board private structure
6238 **/
6239static void i40e_fdir_teardown(struct i40e_pf *pf)
6240{
6241 int i;
6242
17a73f6b 6243 i40e_fdir_filter_exit(pf);
505682cd 6244 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6245 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6246 i40e_vsi_release(pf->vsi[i]);
6247 break;
6248 }
6249 }
6250}
6251
6252/**
f650a38b 6253 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6254 * @pf: board private structure
6255 *
b40c82e6 6256 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6257 **/
23cfbe07 6258static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6259{
41c445ff 6260 struct i40e_hw *hw = &pf->hw;
60442dea 6261 i40e_status ret = 0;
41c445ff
JB		 6262 u32 v;
6263
6264 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6265 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6266 return;
41c445ff 6267
69bfb110 6268 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6269
41c445ff
JB		 6270 /* quiesce the VSIs and their queues that are not already DOWN */
6271 i40e_pf_quiesce_all_vsi(pf);
6272
505682cd 6273 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6274 if (pf->vsi[v])
6275 pf->vsi[v]->seid = 0;
6276 }
6277
6278 i40e_shutdown_adminq(&pf->hw);
6279
f650a38b 6280 /* call shutdown HMC */
60442dea
SN		 6281 if (hw->hmc.hmc_obj) {
6282 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6283 if (ret)
60442dea
SN		 6284 dev_warn(&pf->pdev->dev,
6285 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6286 }
f650a38b
ASJ		 6287}
6288
44033fac
JB		 6289/**
6290 * i40e_send_version - update firmware with driver version
6291 * @pf: PF struct
6292 */
6293static void i40e_send_version(struct i40e_pf *pf)
6294{
6295 struct i40e_driver_version dv;
6296
6297 dv.major_version = DRV_VERSION_MAJOR;
6298 dv.minor_version = DRV_VERSION_MINOR;
6299 dv.build_version = DRV_VERSION_BUILD;
6300 dv.subbuild_version = 0;
35a7d804 6301 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6302 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6303}
6304
f650a38b 6305/**
4dda12e6 6306 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6307 * @pf: board private structure
bc7d338f 6308 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6309 **/
bc7d338f 6310static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6311{
f650a38b 6312 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6313 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6314 i40e_status ret;
6315 u32 v;
6316
41c445ff
JB		 6317 /* Now we wait for GRST to settle out.
6318 * We don't have to delete the VEBs or VSIs from the hw switch
6319 * because the reset will make them disappear.
6320 */
6321 ret = i40e_pf_reset(hw);
b5565400 6322 if (ret) {
41c445ff 6323 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6324 set_bit(__I40E_RESET_FAILED, &pf->state);
6325 goto clear_recovery;
b5565400 6326 }
41c445ff
JB		 6327 pf->pfr_count++;
6328
6329 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6330 goto clear_recovery;
69bfb110 6331 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6332
6333 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6334 ret = i40e_init_adminq(&pf->hw);
6335 if (ret) {
6336 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 6337 goto clear_recovery;
41c445ff
JB		 6338 }
6339
4eb3f768 6340 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6341 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6342 i40e_verify_eeprom(pf);
4eb3f768 6343
e78ac4bf 6344 i40e_clear_pxe_mode(hw);
41c445ff
JB		 6345 ret = i40e_get_capabilities(pf);
6346 if (ret) {
6347 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
6348 ret);
6349 goto end_core_reset;
6350 }
6351
41c445ff
JB		 6352 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6353 hw->func_caps.num_rx_qp,
6354 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6355 if (ret) {
6356 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6357 goto end_core_reset;
6358 }
6359 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6360 if (ret) {
6361 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6362 goto end_core_reset;
6363 }
6364
4e3b35b0
NP		 6365#ifdef CONFIG_I40E_DCB
6366 ret = i40e_init_pf_dcb(pf);
6367 if (ret) {
aebfc816
SN		 6368 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6369 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6370 /* Continue without DCB enabled */
4e3b35b0
NP		 6371 }
6372#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6373#ifdef I40E_FCOE
6374 ret = i40e_init_pf_fcoe(pf);
6375 if (ret)
6376 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6377
38e00438 6378#endif
41c445ff 6379 /* do basic switch setup */
bc7d338f 6380 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6381 if (ret)
6382 goto end_core_reset;
6383
7e2453fe
JB		 6384 /* driver is only interested in link up/down and module qualification
6385 * reports from firmware
6386 */
6387 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6388 I40E_AQ_EVENT_LINK_UPDOWN |
6389 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6390 if (ret)
6391 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6392
cafa2ee6
ASJ		 6393 /* make sure our flow control settings are restored */
6394 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6395 if (ret)
6396 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6397
41c445ff
JB		 6398 /* Rebuild the VSIs and VEBs that existed before reset.
6399 * They are still in our local switch element arrays, so only
6400 * need to rebuild the switch model in the HW.
6401 *
6402 * If there were VEBs but the reconstitution failed, we'll try
6403 * try to recover minimal use by getting the basic PF VSI working.
6404 */
6405 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6406 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6407 /* find the one VEB connected to the MAC, and find orphans */
6408 for (v = 0; v < I40E_MAX_VEB; v++) {
6409 if (!pf->veb[v])
6410 continue;
6411
6412 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6413 pf->veb[v]->uplink_seid == 0) {
6414 ret = i40e_reconstitute_veb(pf->veb[v]);
6415
6416 if (!ret)
6417 continue;
6418
6419 /* If Main VEB failed, we're in deep doodoo,
6420 * so give up rebuilding the switch and set up
6421 * for minimal rebuild of PF VSI.
6422 * If orphan failed, we'll report the error
6423 * but try to keep going.
6424 */
6425 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6426 dev_info(&pf->pdev->dev,
6427 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6428 ret);
6429 pf->vsi[pf->lan_vsi]->uplink_seid
6430 = pf->mac_seid;
6431 break;
6432 } else if (pf->veb[v]->uplink_seid == 0) {
6433 dev_info(&pf->pdev->dev,
6434 "rebuild of orphan VEB failed: %d\n",
6435 ret);
6436 }
6437 }
6438 }
6439 }
6440
6441 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6442 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6443 /* no VEB, so rebuild only the Main VSI */
6444 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6445 if (ret) {
6446 dev_info(&pf->pdev->dev,
6447 "rebuild of Main VSI failed: %d\n", ret);
6448 goto end_core_reset;
6449 }
6450 }
6451
025b4a54
ASJ		 6452 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6453 (pf->hw.aq.fw_maj_ver < 4)) {
6454 msleep(75);
6455 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6456 if (ret)
6457 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6458 pf->hw.aq.asq_last_status);
cafa2ee6 6459 }
41c445ff
JB		 6460 /* reinit the misc interrupt */
6461 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6462 ret = i40e_setup_misc_vector(pf);
6463
6464 /* restart the VSIs that were rebuilt and running before the reset */
6465 i40e_pf_unquiesce_all_vsi(pf);
6466
69f64b2b
MW		 6467 if (pf->num_alloc_vfs) {
6468 for (v = 0; v < pf->num_alloc_vfs; v++)
6469 i40e_reset_vf(&pf->vf[v], true);
6470 }
6471
41c445ff 6472 /* tell the firmware that we're starting */
44033fac 6473 i40e_send_version(pf);
41c445ff
JB		 6474
6475end_core_reset:
a316f651
ASJ		 6476 clear_bit(__I40E_RESET_FAILED, &pf->state);
6477clear_recovery:
41c445ff
JB		 6478 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6479}
6480
f650a38b 6481/**
b40c82e6 6482 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6483 * @pf: board private structure
6484 *
6485 * Close up the VFs and other things in prep for a Core Reset,
6486 * then get ready to rebuild the world.
6487 **/
6488static void i40e_handle_reset_warning(struct i40e_pf *pf)
6489{
23cfbe07
SN		 6490 i40e_prep_for_reset(pf);
6491 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6492}
6493
41c445ff
JB		 6494/**
6495 * i40e_handle_mdd_event
b40c82e6 6496 * @pf: pointer to the PF structure
41c445ff
JB		 6497 *
6498 * Called from the MDD irq handler to identify possibly malicious vfs
6499 **/
6500static void i40e_handle_mdd_event(struct i40e_pf *pf)
6501{
6502 struct i40e_hw *hw = &pf->hw;
6503 bool mdd_detected = false;
df430b12 6504 bool pf_mdd_detected = false;
41c445ff
JB		 6505 struct i40e_vf *vf;
6506 u32 reg;
6507 int i;
6508
6509 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6510 return;
6511
6512 /* find what triggered the MDD event */
6513 reg = rd32(hw, I40E_GL_MDET_TX);
6514 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6515 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6516 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6517 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6518 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6519 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6520 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6521 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6522 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6523 pf->hw.func_caps.base_queue;
faf32978 6524 if (netif_msg_tx_err(pf))
b40c82e6 6525 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6526 event, queue, pf_num, vf_num);
41c445ff
JB		 6527 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6528 mdd_detected = true;
6529 }
6530 reg = rd32(hw, I40E_GL_MDET_RX);
6531 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6532 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6533 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6534 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6535 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6536 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6537 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6538 pf->hw.func_caps.base_queue;
faf32978
JB		 6539 if (netif_msg_rx_err(pf))
6540 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6541 event, queue, func);
41c445ff
JB		 6542 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6543 mdd_detected = true;
6544 }
6545
df430b12
NP		 6546 if (mdd_detected) {
6547 reg = rd32(hw, I40E_PF_MDET_TX);
6548 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6549 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6550 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6551 pf_mdd_detected = true;
6552 }
6553 reg = rd32(hw, I40E_PF_MDET_RX);
6554 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6555 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6556 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6557 pf_mdd_detected = true;
6558 }
6559 /* Queue belongs to the PF, initiate a reset */
6560 if (pf_mdd_detected) {
6561 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6562 i40e_service_event_schedule(pf);
6563 }
6564 }
6565
41c445ff
JB		 6566 /* see if one of the VFs needs its hand slapped */
6567 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6568 vf = &(pf->vf[i]);
6569 reg = rd32(hw, I40E_VP_MDET_TX(i));
6570 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6571 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6572 vf->num_mdd_events++;
faf32978
JB		 6573 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6574 i);
41c445ff
JB		 6575 }
6576
6577 reg = rd32(hw, I40E_VP_MDET_RX(i));
6578 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6579 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6580 vf->num_mdd_events++;
faf32978
JB		 6581 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6582 i);
41c445ff
JB		 6583 }
6584
6585 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6586 dev_info(&pf->pdev->dev,
6587 "Too many MDD events on VF %d, disabled\n", i);
6588 dev_info(&pf->pdev->dev,
6589 "Use PF Control I/F to re-enable the VF\n");
6590 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6591 }
6592 }
6593
6594 /* re-enable mdd interrupt cause */
6595 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6596 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6597 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6598 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6599 i40e_flush(hw);
6600}
6601
a1c9a9d9
JK		 6602#ifdef CONFIG_I40E_VXLAN
6603/**
6604 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6605 * @pf: board private structure
6606 **/
6607static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6608{
a1c9a9d9
JK		 6609 struct i40e_hw *hw = &pf->hw;
6610 i40e_status ret;
6611 u8 filter_index;
6612 __be16 port;
6613 int i;
6614
6615 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6616 return;
6617
6618 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6619
6620 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6621 if (pf->pending_vxlan_bitmap & (1 << i)) {
6622 pf->pending_vxlan_bitmap &= ~(1 << i);
6623 port = pf->vxlan_ports[i];
6624 ret = port ?
6625 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6626 I40E_AQC_TUNNEL_TYPE_VXLAN,
6627 &filter_index, NULL)
6628 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6629
6630 if (ret) {
6631 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6632 port ? "adding" : "deleting",
6633 ntohs(port), port ? i : i);
6634
6635 pf->vxlan_ports[i] = 0;
6636 } else {
6637 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6638 port ? "Added" : "Deleted",
6639 ntohs(port), port ? i : filter_index);
6640 }
6641 }
6642 }
6643}
6644
6645#endif
41c445ff
JB		 6646/**
6647 * i40e_service_task - Run the driver's async subtasks
6648 * @work: pointer to work_struct containing our data
6649 **/
6650static void i40e_service_task(struct work_struct *work)
6651{
6652 struct i40e_pf *pf = container_of(work,
6653 struct i40e_pf,
6654 service_task);
6655 unsigned long start_time = jiffies;
6656
e57a2fea
SN		 6657 /* don't bother with service tasks if a reset is in progress */
6658 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6659 i40e_service_event_complete(pf);
6660 return;
6661 }
6662
41c445ff
JB		 6663 i40e_reset_subtask(pf);
6664 i40e_handle_mdd_event(pf);
6665 i40e_vc_process_vflr_event(pf);
6666 i40e_watchdog_subtask(pf);
6667 i40e_fdir_reinit_subtask(pf);
41c445ff 6668 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6669#ifdef CONFIG_I40E_VXLAN
6670 i40e_sync_vxlan_filters_subtask(pf);
6671#endif
41c445ff
JB		 6672 i40e_clean_adminq_subtask(pf);
6673
6674 i40e_service_event_complete(pf);
6675
6676 /* If the tasks have taken longer than one timer cycle or there
6677 * is more work to be done, reschedule the service task now
6678 * rather than wait for the timer to tick again.
6679 */
6680 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6681 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6682 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6683 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6684 i40e_service_event_schedule(pf);
6685}
6686
6687/**
6688 * i40e_service_timer - timer callback
6689 * @data: pointer to PF struct
6690 **/
6691static void i40e_service_timer(unsigned long data)
6692{
6693 struct i40e_pf *pf = (struct i40e_pf *)data;
6694
6695 mod_timer(&pf->service_timer,
6696 round_jiffies(jiffies + pf->service_timer_period));
6697 i40e_service_event_schedule(pf);
6698}
6699
6700/**
6701 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6702 * @vsi: the VSI being configured
6703 **/
6704static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6705{
6706 struct i40e_pf *pf = vsi->back;
6707
6708 switch (vsi->type) {
6709 case I40E_VSI_MAIN:
6710 vsi->alloc_queue_pairs = pf->num_lan_qps;
6711 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6712 I40E_REQ_DESCRIPTOR_MULTIPLE);
6713 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6714 vsi->num_q_vectors = pf->num_lan_msix;
6715 else
6716 vsi->num_q_vectors = 1;
6717
6718 break;
6719
6720 case I40E_VSI_FDIR:
6721 vsi->alloc_queue_pairs = 1;
6722 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6723 I40E_REQ_DESCRIPTOR_MULTIPLE);
6724 vsi->num_q_vectors = 1;
6725 break;
6726
6727 case I40E_VSI_VMDQ2:
6728 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6729 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6730 I40E_REQ_DESCRIPTOR_MULTIPLE);
6731 vsi->num_q_vectors = pf->num_vmdq_msix;
6732 break;
6733
6734 case I40E_VSI_SRIOV:
6735 vsi->alloc_queue_pairs = pf->num_vf_qps;
6736 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6737 I40E_REQ_DESCRIPTOR_MULTIPLE);
6738 break;
6739
38e00438
VD		 6740#ifdef I40E_FCOE
6741 case I40E_VSI_FCOE:
6742 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6743 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6744 I40E_REQ_DESCRIPTOR_MULTIPLE);
6745 vsi->num_q_vectors = pf->num_fcoe_msix;
6746 break;
6747
6748#endif /* I40E_FCOE */
41c445ff
JB		 6749 default:
6750 WARN_ON(1);
6751 return -ENODATA;
6752 }
6753
6754 return 0;
6755}
6756
f650a38b
ASJ		 6757/**
6758 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6759 * @type: VSI pointer
bc7d338f 6760 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6761 *
6762 * On error: returns error code (negative)
6763 * On success: returns 0
6764 **/
bc7d338f 6765static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6766{
6767 int size;
6768 int ret = 0;
6769
ac6c5e3d 6770 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6771 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6772 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6773 if (!vsi->tx_rings)
6774 return -ENOMEM;
f650a38b
ASJ		 6775 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6776
bc7d338f
ASJ		 6777 if (alloc_qvectors) {
6778 /* allocate memory for q_vector pointers */
f57e4fbd 6779 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6780 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6781 if (!vsi->q_vectors) {
6782 ret = -ENOMEM;
6783 goto err_vectors;
6784 }
f650a38b
ASJ		 6785 }
6786 return ret;
6787
6788err_vectors:
6789 kfree(vsi->tx_rings);
6790 return ret;
6791}
6792
41c445ff
JB		 6793/**
6794 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6795 * @pf: board private structure
6796 * @type: type of VSI
6797 *
6798 * On error: returns error code (negative)
6799 * On success: returns vsi index in PF (positive)
6800 **/
6801static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6802{
6803 int ret = -ENODEV;
6804 struct i40e_vsi *vsi;
6805 int vsi_idx;
6806 int i;
6807
6808 /* Need to protect the allocation of the VSIs at the PF level */
6809 mutex_lock(&pf->switch_mutex);
6810
6811 /* VSI list may be fragmented if VSI creation/destruction has
6812 * been happening. We can afford to do a quick scan to look
6813 * for any free VSIs in the list.
6814 *
6815 * find next empty vsi slot, looping back around if necessary
6816 */
6817 i = pf->next_vsi;
505682cd 6818 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6819 i++;
505682cd 6820 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6821 i = 0;
6822 while (i < pf->next_vsi && pf->vsi[i])
6823 i++;
6824 }
6825
505682cd 6826 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6827 vsi_idx = i; /* Found one! */
6828 } else {
6829 ret = -ENODEV;
493fb300 6830 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6831 }
6832 pf->next_vsi = ++i;
6833
6834 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6835 if (!vsi) {
6836 ret = -ENOMEM;
493fb300 6837 goto unlock_pf;
41c445ff
JB		 6838 }
6839 vsi->type = type;
6840 vsi->back = pf;
6841 set_bit(__I40E_DOWN, &vsi->state);
6842 vsi->flags = 0;
6843 vsi->idx = vsi_idx;
6844 vsi->rx_itr_setting = pf->rx_itr_default;
6845 vsi->tx_itr_setting = pf->tx_itr_default;
5db4cb59
ASJ		 6846 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
6847 pf->rss_table_size : 64;
41c445ff
JB		 6848 vsi->netdev_registered = false;
6849 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6850 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6851 vsi->irqs_ready = false;
41c445ff 6852
9f65e15b
AD		 6853 ret = i40e_set_num_rings_in_vsi(vsi);
6854 if (ret)
6855 goto err_rings;
6856
bc7d338f 6857 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6858 if (ret)
9f65e15b 6859 goto err_rings;
493fb300 6860
41c445ff
JB		 6861 /* Setup default MSIX irq handler for VSI */
6862 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6863
6864 pf->vsi[vsi_idx] = vsi;
6865 ret = vsi_idx;
493fb300
AD		 6866 goto unlock_pf;
6867
9f65e15b 6868err_rings:
493fb300
AD		 6869 pf->next_vsi = i - 1;
6870 kfree(vsi);
6871unlock_pf:
41c445ff
JB		 6872 mutex_unlock(&pf->switch_mutex);
6873 return ret;
6874}
6875
f650a38b
ASJ		 6876/**
6877 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6878 * @type: VSI pointer
bc7d338f 6879 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6880 *
6881 * On error: returns error code (negative)
6882 * On success: returns 0
6883 **/
bc7d338f 6884static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6885{
6886 /* free the ring and vector containers */
bc7d338f
ASJ		 6887 if (free_qvectors) {
6888 kfree(vsi->q_vectors);
6889 vsi->q_vectors = NULL;
6890 }
f650a38b
ASJ		 6891 kfree(vsi->tx_rings);
6892 vsi->tx_rings = NULL;
6893 vsi->rx_rings = NULL;
6894}
6895
41c445ff
JB		 6896/**
6897 * i40e_vsi_clear - Deallocate the VSI provided
6898 * @vsi: the VSI being un-configured
6899 **/
6900static int i40e_vsi_clear(struct i40e_vsi *vsi)
6901{
6902 struct i40e_pf *pf;
6903
6904 if (!vsi)
6905 return 0;
6906
6907 if (!vsi->back)
6908 goto free_vsi;
6909 pf = vsi->back;
6910
6911 mutex_lock(&pf->switch_mutex);
6912 if (!pf->vsi[vsi->idx]) {
6913 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6914 vsi->idx, vsi->idx, vsi, vsi->type);
6915 goto unlock_vsi;
6916 }
6917
6918 if (pf->vsi[vsi->idx] != vsi) {
6919 dev_err(&pf->pdev->dev,
6920 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6921 pf->vsi[vsi->idx]->idx,
6922 pf->vsi[vsi->idx],
6923 pf->vsi[vsi->idx]->type,
6924 vsi->idx, vsi, vsi->type);
6925 goto unlock_vsi;
6926 }
6927
b40c82e6 6928 /* updates the PF for this cleared vsi */
41c445ff
JB		 6929 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6930 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6931
bc7d338f 6932 i40e_vsi_free_arrays(vsi, true);
493fb300 6933
41c445ff
JB		 6934 pf->vsi[vsi->idx] = NULL;
6935 if (vsi->idx < pf->next_vsi)
6936 pf->next_vsi = vsi->idx;
6937
6938unlock_vsi:
6939 mutex_unlock(&pf->switch_mutex);
6940free_vsi:
6941 kfree(vsi);
6942
6943 return 0;
6944}
6945
9f65e15b
AD		 6946/**
6947 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6948 * @vsi: the VSI being cleaned
6949 **/
be1d5eea 6950static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6951{
6952 int i;
6953
8e9dca53 6954 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6955 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6956 kfree_rcu(vsi->tx_rings[i], rcu);
6957 vsi->tx_rings[i] = NULL;
6958 vsi->rx_rings[i] = NULL;
6959 }
be1d5eea 6960 }
9f65e15b
AD		 6961}
6962
41c445ff
JB		 6963/**
6964 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6965 * @vsi: the VSI being configured
6966 **/
6967static int i40e_alloc_rings(struct i40e_vsi *vsi)
6968{
e7046ee1 6969 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6970 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6971 int i;
6972
41c445ff 6973 /* Set basic values in the rings to be used later during open() */
d7397644 6974 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6975 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6976 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6977 if (!tx_ring)
6978 goto err_out;
41c445ff
JB		 6979
6980 tx_ring->queue_index = i;
6981 tx_ring->reg_idx = vsi->base_queue + i;
6982 tx_ring->ring_active = false;
6983 tx_ring->vsi = vsi;
6984 tx_ring->netdev = vsi->netdev;
6985 tx_ring->dev = &pf->pdev->dev;
6986 tx_ring->count = vsi->num_desc;
6987 tx_ring->size = 0;
6988 tx_ring->dcb_tc = 0;
9f65e15b 6989 vsi->tx_rings[i] = tx_ring;
41c445ff 6990
9f65e15b 6991 rx_ring = &tx_ring[1];
41c445ff
JB		 6992 rx_ring->queue_index = i;
6993 rx_ring->reg_idx = vsi->base_queue + i;
6994 rx_ring->ring_active = false;
6995 rx_ring->vsi = vsi;
6996 rx_ring->netdev = vsi->netdev;
6997 rx_ring->dev = &pf->pdev->dev;
6998 rx_ring->count = vsi->num_desc;
6999 rx_ring->size = 0;
7000 rx_ring->dcb_tc = 0;
7001 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7002 set_ring_16byte_desc_enabled(rx_ring);
7003 else
7004 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7005 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7006 }
7007
7008 return 0;
9f65e15b
AD		 7009
7010err_out:
7011 i40e_vsi_clear_rings(vsi);
7012 return -ENOMEM;
41c445ff
JB		 7013}
7014
7015/**
7016 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7017 * @pf: board private structure
7018 * @vectors: the number of MSI-X vectors to request
7019 *
7020 * Returns the number of vectors reserved, or error
7021 **/
7022static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7023{
7b37f376
AG		 7024 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7025 I40E_MIN_MSIX, vectors);
7026 if (vectors < 0) {
41c445ff 7027 dev_info(&pf->pdev->dev,
7b37f376 7028 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7029 vectors = 0;
7030 }
7031
7032 return vectors;
7033}
7034
7035/**
7036 * i40e_init_msix - Setup the MSIX capability
7037 * @pf: board private structure
7038 *
7039 * Work with the OS to set up the MSIX vectors needed.
7040 *
3b444399 7041 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7042 **/
7043static int i40e_init_msix(struct i40e_pf *pf)
7044{
41c445ff 7045 struct i40e_hw *hw = &pf->hw;
1e200e4a 7046 int vectors_left;
41c445ff 7047 int v_budget, i;
3b444399 7048 int v_actual;
41c445ff
JB		 7049
7050 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7051 return -ENODEV;
7052
7053 /* The number of vectors we'll request will be comprised of:
7054 * - Add 1 for "other" cause for Admin Queue events, etc.
7055 * - The number of LAN queue pairs
f8ff1464
ASJ		 7056 * - Queues being used for RSS.
7057 * We don't need as many as max_rss_size vectors.
7058 * use rss_size instead in the calculation since that
7059 * is governed by number of cpus in the system.
7060 * - assumes symmetric Tx/Rx pairing
41c445ff 7061 * - The number of VMDq pairs
38e00438
VD		 7062#ifdef I40E_FCOE
7063 * - The number of FCOE qps.
7064#endif
41c445ff
JB		 7065 * Once we count this up, try the request.
7066 *
7067 * If we can't get what we want, we'll simplify to nearly nothing
7068 * and try again. If that still fails, we punt.
7069 */
1e200e4a
SN		 7070 vectors_left = hw->func_caps.num_msix_vectors;
7071 v_budget = 0;
7072
7073 /* reserve one vector for miscellaneous handler */
7074 if (vectors_left) {
7075 v_budget++;
7076 vectors_left--;
7077 }
7078
7079 /* reserve vectors for the main PF traffic queues */
7080 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7081 vectors_left -= pf->num_lan_msix;
7082 v_budget += pf->num_lan_msix;
7083
7084 /* reserve one vector for sideband flow director */
7085 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7086 if (vectors_left) {
7087 v_budget++;
7088 vectors_left--;
7089 } else {
7090 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7091 }
7092 }
83840e4b 7093
38e00438 7094#ifdef I40E_FCOE
1e200e4a 7095 /* can we reserve enough for FCoE? */
38e00438 7096 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7097 if (!vectors_left)
7098 pf->num_fcoe_msix = 0;
7099 else if (vectors_left >= pf->num_fcoe_qps)
7100 pf->num_fcoe_msix = pf->num_fcoe_qps;
7101 else
7102 pf->num_fcoe_msix = 1;
38e00438 7103 v_budget += pf->num_fcoe_msix;
1e200e4a 7104 vectors_left -= pf->num_fcoe_msix;
38e00438 7105 }
1e200e4a 7106
38e00438 7107#endif
1e200e4a
SN		 7108 /* any vectors left over go for VMDq support */
7109 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7110 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7111 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7112
7113 /* if we're short on vectors for what's desired, we limit
7114 * the queues per vmdq. If this is still more than are
7115 * available, the user will need to change the number of
7116 * queues/vectors used by the PF later with the ethtool
7117 * channels command
7118 */
7119 if (vmdq_vecs < vmdq_vecs_wanted)
7120 pf->num_vmdq_qps = 1;
7121 pf->num_vmdq_msix = pf->num_vmdq_qps;
7122
7123 v_budget += vmdq_vecs;
7124 vectors_left -= vmdq_vecs;
7125 }
41c445ff
JB		 7126
7127 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7128 GFP_KERNEL);
7129 if (!pf->msix_entries)
7130 return -ENOMEM;
7131
7132 for (i = 0; i < v_budget; i++)
7133 pf->msix_entries[i].entry = i;
3b444399 7134 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7135
3b444399 7136 if (v_actual != v_budget) {
a34977ba
ASJ		 7137 /* If we have limited resources, we will start with no vectors
7138 * for the special features and then allocate vectors to some
7139 * of these features based on the policy and at the end disable
7140 * the features that did not get any vectors.
7141 */
38e00438
VD		 7142#ifdef I40E_FCOE
7143 pf->num_fcoe_qps = 0;
7144 pf->num_fcoe_msix = 0;
7145#endif
a34977ba
ASJ		 7146 pf->num_vmdq_msix = 0;
7147 }
7148
3b444399 7149 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7150 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7151 kfree(pf->msix_entries);
7152 pf->msix_entries = NULL;
7153 return -ENODEV;
7154
3b444399 7155 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7156 /* Adjust for minimal MSIX use */
41c445ff
JB		 7157 pf->num_vmdq_vsis = 0;
7158 pf->num_vmdq_qps = 0;
41c445ff
JB		 7159 pf->num_lan_qps = 1;
7160 pf->num_lan_msix = 1;
7161
3b444399
SN		 7162 } else if (v_actual != v_budget) {
7163 int vec;
7164
a34977ba 7165 /* reserve the misc vector */
3b444399 7166 vec = v_actual - 1;
a34977ba 7167
41c445ff
JB		 7168 /* Scale vector usage down */
7169 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7170 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7171 pf->num_vmdq_qps = 1;
7172 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7173
7174 /* partition out the remaining vectors */
7175 switch (vec) {
7176 case 2:
41c445ff
JB		 7177 pf->num_lan_msix = 1;
7178 break;
7179 case 3:
38e00438
VD		 7180#ifdef I40E_FCOE
7181 /* give one vector to FCoE */
7182 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7183 pf->num_lan_msix = 1;
7184 pf->num_fcoe_msix = 1;
7185 }
7186#else
41c445ff 7187 pf->num_lan_msix = 2;
38e00438 7188#endif
41c445ff
JB		 7189 break;
7190 default:
38e00438
VD		 7191#ifdef I40E_FCOE
7192 /* give one vector to FCoE */
7193 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7194 pf->num_fcoe_msix = 1;
7195 vec--;
7196 }
7197#endif
1e200e4a
SN		 7198 /* give the rest to the PF */
7199 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7200 break;
7201 }
7202 }
7203
a34977ba
ASJ		 7204 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7205 (pf->num_vmdq_msix == 0)) {
7206 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7207 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7208 }
38e00438
VD		 7209#ifdef I40E_FCOE
7210
7211 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7212 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7213 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7214 }
7215#endif
3b444399 7216 return v_actual;
41c445ff
JB		 7217}
7218
493fb300 7219/**
90e04070 7220 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7221 * @vsi: the VSI being configured
7222 * @v_idx: index of the vector in the vsi struct
7223 *
7224 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7225 **/
90e04070 7226static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7227{
7228 struct i40e_q_vector *q_vector;
7229
7230 /* allocate q_vector */
7231 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7232 if (!q_vector)
7233 return -ENOMEM;
7234
7235 q_vector->vsi = vsi;
7236 q_vector->v_idx = v_idx;
7237 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7238 if (vsi->netdev)
7239 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7240 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7241
cd0b6fa6
AD		 7242 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7243 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7244
493fb300
AD		 7245 /* tie q_vector and vsi together */
7246 vsi->q_vectors[v_idx] = q_vector;
7247
7248 return 0;
7249}
7250
41c445ff 7251/**
90e04070 7252 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7253 * @vsi: the VSI being configured
7254 *
7255 * We allocate one q_vector per queue interrupt. If allocation fails we
7256 * return -ENOMEM.
7257 **/
90e04070 7258static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7259{
7260 struct i40e_pf *pf = vsi->back;
7261 int v_idx, num_q_vectors;
493fb300 7262 int err;
41c445ff
JB		 7263
7264 /* if not MSIX, give the one vector only to the LAN VSI */
7265 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7266 num_q_vectors = vsi->num_q_vectors;
7267 else if (vsi == pf->vsi[pf->lan_vsi])
7268 num_q_vectors = 1;
7269 else
7270 return -EINVAL;
7271
41c445ff 7272 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7273 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7274 if (err)
7275 goto err_out;
41c445ff
JB		 7276 }
7277
7278 return 0;
493fb300
AD		 7279
7280err_out:
7281 while (v_idx--)
7282 i40e_free_q_vector(vsi, v_idx);
7283
7284 return err;
41c445ff
JB		 7285}
7286
7287/**
7288 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7289 * @pf: board private structure to initialize
7290 **/
7291static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
7292{
3b444399
SN		 7293 int vectors = 0;
7294 ssize_t size;
41c445ff
JB		 7295
7296 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7297 vectors = i40e_init_msix(pf);
7298 if (vectors < 0) {
60ea5f83 7299 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7300#ifdef I40E_FCOE
7301 I40E_FLAG_FCOE_ENABLED |
7302#endif
60ea5f83 7303 I40E_FLAG_RSS_ENABLED |
4d9b6043 7304 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7305 I40E_FLAG_SRIOV_ENABLED |
7306 I40E_FLAG_FD_SB_ENABLED |
7307 I40E_FLAG_FD_ATR_ENABLED |
7308 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7309
7310 /* rework the queue expectations without MSIX */
7311 i40e_determine_queue_usage(pf);
7312 }
7313 }
7314
7315 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7316 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7317 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7318 vectors = pci_enable_msi(pf->pdev);
7319 if (vectors < 0) {
7320 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7321 vectors);
41c445ff
JB		 7322 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7323 }
3b444399 7324 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7325 }
7326
958a3e3b 7327 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7328 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7329
3b444399
SN		 7330 /* set up vector assignment tracking */
7331 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7332 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7333 pf->irq_pile->num_entries = vectors;
7334 pf->irq_pile->search_hint = 0;
7335
41c445ff 7336 /* track first vector for misc interrupts */
3b444399 7337 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
41c445ff
JB		 7338}
7339
7340/**
7341 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7342 * @pf: board private structure
7343 *
7344 * This sets up the handler for MSIX 0, which is used to manage the
7345 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7346 * when in MSI or Legacy interrupt mode.
7347 **/
7348static int i40e_setup_misc_vector(struct i40e_pf *pf)
7349{
7350 struct i40e_hw *hw = &pf->hw;
7351 int err = 0;
7352
7353 /* Only request the irq if this is the first time through, and
7354 * not when we're rebuilding after a Reset
7355 */
7356 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7357 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7358 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7359 if (err) {
7360 dev_info(&pf->pdev->dev,
77fa28be 7361 "request_irq for %s failed: %d\n",
b294ac70 7362 pf->int_name, err);
41c445ff
JB		 7363 return -EFAULT;
7364 }
7365 }
7366
ab437b5a 7367 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7368
7369 /* associate no queues to the misc vector */
7370 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7371 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7372
7373 i40e_flush(hw);
7374
7375 i40e_irq_dynamic_enable_icr0(pf);
7376
7377 return err;
7378}
7379
7380/**
7381 * i40e_config_rss - Prepare for RSS if used
7382 * @pf: board private structure
7383 **/
7384static int i40e_config_rss(struct i40e_pf *pf)
7385{
22f258a1 7386 u32 rss_key[I40E_PFQF_HKEY_MAX_INDEX + 1];
66ddcffb 7387 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0
ASJ		 7388 struct i40e_hw *hw = &pf->hw;
7389 u32 lut = 0;
7390 int i, j;
7391 u64 hena;
e157ea30 7392 u32 reg_val;
41c445ff 7393
22f258a1 7394 netdev_rss_key_fill(rss_key, sizeof(rss_key));
41c445ff 7395 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
22f258a1 7396 wr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);
41c445ff
JB		 7397
7398 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7399 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7400 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7401 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7402 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7403 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7404
66ddcffb
ASJ		 7405 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7406
e157ea30
CW		 7407 /* Check capability and Set table size and register per hw expectation*/
7408 reg_val = rd32(hw, I40E_PFQF_CTL_0);
d9e894ee 7409 if (pf->rss_table_size == 512)
e157ea30 7410 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
d9e894ee 7411 else
e157ea30 7412 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
e157ea30
CW		 7413 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7414
41c445ff 7415 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7416 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7417
7418 /* The assumption is that lan qp count will be the highest
7419 * qp count for any PF VSI that needs RSS.
7420 * If multiple VSIs need RSS support, all the qp counts
7421 * for those VSIs should be a power of 2 for RSS to work.
7422 * If LAN VSI is the only consumer for RSS then this requirement
7423 * is not necessary.
7424 */
66ddcffb 7425 if (j == vsi->rss_size)
41c445ff
JB		 7426 j = 0;
7427 /* lut = 4-byte sliding window of 4 lut entries */
7428 lut = (lut << 8) | (j &
7429 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7430 /* On i = 3, we have 4 entries in lut; write to the register */
7431 if ((i & 3) == 3)
7432 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7433 }
7434 i40e_flush(hw);
7435
7436 return 0;
7437}
7438
f8ff1464
ASJ		 7439/**
7440 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7441 * @pf: board private structure
7442 * @queue_count: the requested queue count for rss.
7443 *
7444 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7445 * count which may be different from the requested queue count.
7446 **/
7447int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7448{
9a3bd2f1
ASJ		 7449 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7450 int new_rss_size;
7451
f8ff1464
ASJ		 7452 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7453 return 0;
7454
9a3bd2f1 7455 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7456
9a3bd2f1
ASJ		 7457 if (queue_count != vsi->num_queue_pairs) {
7458 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7459 i40e_prep_for_reset(pf);
7460
9a3bd2f1 7461 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7462
7463 i40e_reset_and_rebuild(pf, true);
7464 i40e_config_rss(pf);
7465 }
7466 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7467 return pf->rss_size;
7468}
7469
f4492db1
GR		 7470/**
7471 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7472 * @pf: board private structure
7473 **/
7474i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7475{
7476 i40e_status status;
7477 bool min_valid, max_valid;
7478 u32 max_bw, min_bw;
7479
7480 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7481 &min_valid, &max_valid);
7482
7483 if (!status) {
7484 if (min_valid)
7485 pf->npar_min_bw = min_bw;
7486 if (max_valid)
7487 pf->npar_max_bw = max_bw;
7488 }
7489
7490 return status;
7491}
7492
7493/**
7494 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7495 * @pf: board private structure
7496 **/
7497i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7498{
7499 struct i40e_aqc_configure_partition_bw_data bw_data;
7500 i40e_status status;
7501
b40c82e6 7502 /* Set the valid bit for this PF */
f4492db1
GR		 7503 bw_data.pf_valid_bits = cpu_to_le16(1 << pf->hw.pf_id);
7504 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7505 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7506
7507 /* Set the new bandwidths */
7508 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7509
7510 return status;
7511}
7512
7513/**
7514 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7515 * @pf: board private structure
7516 **/
7517i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7518{
7519 /* Commit temporary BW setting to permanent NVM image */
7520 enum i40e_admin_queue_err last_aq_status;
7521 i40e_status ret;
7522 u16 nvm_word;
7523
7524 if (pf->hw.partition_id != 1) {
7525 dev_info(&pf->pdev->dev,
7526 "Commit BW only works on partition 1! This is partition %d",
7527 pf->hw.partition_id);
7528 ret = I40E_NOT_SUPPORTED;
7529 goto bw_commit_out;
7530 }
7531
7532 /* Acquire NVM for read access */
7533 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7534 last_aq_status = pf->hw.aq.asq_last_status;
7535 if (ret) {
7536 dev_info(&pf->pdev->dev,
7537 "Cannot acquire NVM for read access, err %d: aq_err %d\n",
7538 ret, last_aq_status);
7539 goto bw_commit_out;
7540 }
7541
7542 /* Read word 0x10 of NVM - SW compatibility word 1 */
7543 ret = i40e_aq_read_nvm(&pf->hw,
7544 I40E_SR_NVM_CONTROL_WORD,
7545 0x10, sizeof(nvm_word), &nvm_word,
7546 false, NULL);
7547 /* Save off last admin queue command status before releasing
7548 * the NVM
7549 */
7550 last_aq_status = pf->hw.aq.asq_last_status;
7551 i40e_release_nvm(&pf->hw);
7552 if (ret) {
7553 dev_info(&pf->pdev->dev, "NVM read error, err %d aq_err %d\n",
7554 ret, last_aq_status);
7555 goto bw_commit_out;
7556 }
7557
7558 /* Wait a bit for NVM release to complete */
7559 msleep(50);
7560
7561 /* Acquire NVM for write access */
7562 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7563 last_aq_status = pf->hw.aq.asq_last_status;
7564 if (ret) {
7565 dev_info(&pf->pdev->dev,
7566 "Cannot acquire NVM for write access, err %d: aq_err %d\n",
7567 ret, last_aq_status);
7568 goto bw_commit_out;
7569 }
7570 /* Write it back out unchanged to initiate update NVM,
7571 * which will force a write of the shadow (alt) RAM to
7572 * the NVM - thus storing the bandwidth values permanently.
7573 */
7574 ret = i40e_aq_update_nvm(&pf->hw,
7575 I40E_SR_NVM_CONTROL_WORD,
7576 0x10, sizeof(nvm_word),
7577 &nvm_word, true, NULL);
7578 /* Save off last admin queue command status before releasing
7579 * the NVM
7580 */
7581 last_aq_status = pf->hw.aq.asq_last_status;
7582 i40e_release_nvm(&pf->hw);
7583 if (ret)
7584 dev_info(&pf->pdev->dev,
7585 "BW settings NOT SAVED, err %d aq_err %d\n",
7586 ret, last_aq_status);
7587bw_commit_out:
7588
7589 return ret;
7590}
7591
41c445ff
JB		 7592/**
7593 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7594 * @pf: board private structure to initialize
7595 *
7596 * i40e_sw_init initializes the Adapter private data structure.
7597 * Fields are initialized based on PCI device information and
7598 * OS network device settings (MTU size).
7599 **/
7600static int i40e_sw_init(struct i40e_pf *pf)
7601{
7602 int err = 0;
7603 int size;
7604
7605 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7606 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7607 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7608 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7609 if (I40E_DEBUG_USER & debug)
7610 pf->hw.debug_mask = debug;
7611 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7612 I40E_DEFAULT_MSG_ENABLE);
7613 }
7614
7615 /* Set default capability flags */
7616 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7617 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 7618 I40E_FLAG_MSIX_ENABLED;
7619
7620 if (iommu_present(&pci_bus_type))
7621 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7622 else
7623 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7624
ca99eb99
MW		 7625 /* Set default ITR */
7626 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7627 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7628
7134f9ce
JB		 7629 /* Depending on PF configurations, it is possible that the RSS
7630 * maximum might end up larger than the available queues
7631 */
41c445ff 7632 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7633 pf->rss_size = 1;
5db4cb59 7634 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7635 pf->rss_size_max = min_t(int, pf->rss_size_max,
7636 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7637 if (pf->hw.func_caps.rss) {
7638 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7639 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7640 }
7641
2050bc65
CS		 7642 /* MFP mode enabled */
7643 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7644 pf->flags |= I40E_FLAG_MFP_ENABLED;
7645 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7646 if (i40e_get_npar_bw_setting(pf))
7647 dev_warn(&pf->pdev->dev,
7648 "Could not get NPAR bw settings\n");
7649 else
7650 dev_info(&pf->pdev->dev,
7651 "Min BW = %8.8x, Max BW = %8.8x\n",
7652 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7653 }
7654
cbf61325
ASJ		 7655 /* FW/NVM is not yet fixed in this regard */
7656 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7657 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7658 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7659 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
b40c82e6 7660 /* Setup a counter for fd_atr per PF */
433c47de 7661 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7662 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7663 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
b40c82e6 7664 /* Setup a counter for fd_sb per PF */
433c47de 7665 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7666 } else {
7667 dev_info(&pf->pdev->dev,
0b67584f 7668 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7669 }
cbf61325
ASJ		 7670 pf->fdir_pf_filter_count =
7671 pf->hw.func_caps.fd_filters_guaranteed;
7672 pf->hw.fdir_shared_filter_count =
7673 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7674 }
7675
7676 if (pf->hw.func_caps.vmdq) {
7677 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7678 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7679 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7680 }
7681
38e00438
VD		 7682#ifdef I40E_FCOE
7683 err = i40e_init_pf_fcoe(pf);
7684 if (err)
7685 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7686
7687#endif /* I40E_FCOE */
41c445ff 7688#ifdef CONFIG_PCI_IOV
ba252f13 7689 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7690 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7691 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7692 pf->num_req_vfs = min_t(int,
7693 pf->hw.func_caps.num_vfs,
7694 I40E_MAX_VF_COUNT);
7695 }
7696#endif /* CONFIG_PCI_IOV */
7697 pf->eeprom_version = 0xDEAD;
7698 pf->lan_veb = I40E_NO_VEB;
7699 pf->lan_vsi = I40E_NO_VSI;
7700
7701 /* set up queue assignment tracking */
7702 size = sizeof(struct i40e_lump_tracking)
7703 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7704 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7705 if (!pf->qp_pile) {
7706 err = -ENOMEM;
7707 goto sw_init_done;
7708 }
7709 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7710 pf->qp_pile->search_hint = 0;
7711
327fe04b
ASJ		 7712 pf->tx_timeout_recovery_level = 1;
7713
41c445ff
JB		 7714 mutex_init(&pf->switch_mutex);
7715
c668a12c
GR		 7716 /* If NPAR is enabled nudge the Tx scheduler */
7717 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
7718 i40e_set_npar_bw_setting(pf);
7719
41c445ff
JB		 7720sw_init_done:
7721 return err;
7722}
7723
7c3c288b
ASJ		 7724/**
7725 * i40e_set_ntuple - set the ntuple feature flag and take action
7726 * @pf: board private structure to initialize
7727 * @features: the feature set that the stack is suggesting
7728 *
7729 * returns a bool to indicate if reset needs to happen
7730 **/
7731bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7732{
7733 bool need_reset = false;
7734
7735 /* Check if Flow Director n-tuple support was enabled or disabled. If
7736 * the state changed, we need to reset.
7737 */
7738 if (features & NETIF_F_NTUPLE) {
7739 /* Enable filters and mark for reset */
7740 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7741 need_reset = true;
7742 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7743 } else {
7744 /* turn off filters, mark for reset and clear SW filter list */
7745 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7746 need_reset = true;
7747 i40e_fdir_filter_exit(pf);
7748 }
7749 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7750 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7751 /* reset fd counters */
7752 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7753 pf->fdir_pf_active_filters = 0;
7754 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7755 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7756 /* if ATR was auto disabled it can be re-enabled. */
7757 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7758 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7759 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7760 }
7761 return need_reset;
7762}
7763
41c445ff
JB		 7764/**
7765 * i40e_set_features - set the netdev feature flags
7766 * @netdev: ptr to the netdev being adjusted
7767 * @features: the feature set that the stack is suggesting
7768 **/
7769static int i40e_set_features(struct net_device *netdev,
7770 netdev_features_t features)
7771{
7772 struct i40e_netdev_priv *np = netdev_priv(netdev);
7773 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7774 struct i40e_pf *pf = vsi->back;
7775 bool need_reset;
41c445ff
JB		 7776
7777 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7778 i40e_vlan_stripping_enable(vsi);
7779 else
7780 i40e_vlan_stripping_disable(vsi);
7781
7c3c288b
ASJ		 7782 need_reset = i40e_set_ntuple(pf, features);
7783
7784 if (need_reset)
7785 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7786
41c445ff
JB		 7787 return 0;
7788}
7789
a1c9a9d9
JK		 7790#ifdef CONFIG_I40E_VXLAN
7791/**
7792 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7793 * @pf: board private structure
7794 * @port: The UDP port to look up
7795 *
7796 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7797 **/
7798static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7799{
7800 u8 i;
7801
7802 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7803 if (pf->vxlan_ports[i] == port)
7804 return i;
7805 }
7806
7807 return i;
7808}
7809
7810/**
7811 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7812 * @netdev: This physical port's netdev
7813 * @sa_family: Socket Family that VXLAN is notifying us about
7814 * @port: New UDP port number that VXLAN started listening to
7815 **/
7816static void i40e_add_vxlan_port(struct net_device *netdev,
7817 sa_family_t sa_family, __be16 port)
7818{
7819 struct i40e_netdev_priv *np = netdev_priv(netdev);
7820 struct i40e_vsi *vsi = np->vsi;
7821 struct i40e_pf *pf = vsi->back;
7822 u8 next_idx;
7823 u8 idx;
7824
7825 if (sa_family == AF_INET6)
7826 return;
7827
7828 idx = i40e_get_vxlan_port_idx(pf, port);
7829
7830 /* Check if port already exists */
7831 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7832 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7833 return;
7834 }
7835
7836 /* Now check if there is space to add the new port */
7837 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7838
7839 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7840 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7841 ntohs(port));
7842 return;
7843 }
7844
7845 /* New port: add it and mark its index in the bitmap */
7846 pf->vxlan_ports[next_idx] = port;
7847 pf->pending_vxlan_bitmap |= (1 << next_idx);
7848
7849 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7850}
7851
7852/**
7853 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7854 * @netdev: This physical port's netdev
7855 * @sa_family: Socket Family that VXLAN is notifying us about
7856 * @port: UDP port number that VXLAN stopped listening to
7857 **/
7858static void i40e_del_vxlan_port(struct net_device *netdev,
7859 sa_family_t sa_family, __be16 port)
7860{
7861 struct i40e_netdev_priv *np = netdev_priv(netdev);
7862 struct i40e_vsi *vsi = np->vsi;
7863 struct i40e_pf *pf = vsi->back;
7864 u8 idx;
7865
7866 if (sa_family == AF_INET6)
7867 return;
7868
7869 idx = i40e_get_vxlan_port_idx(pf, port);
7870
7871 /* Check if port already exists */
7872 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7873 /* if port exists, set it to 0 (mark for deletion)
7874 * and make it pending
7875 */
7876 pf->vxlan_ports[idx] = 0;
7877
7878 pf->pending_vxlan_bitmap |= (1 << idx);
7879
7880 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7881 } else {
7882 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7883 ntohs(port));
7884 }
7885}
7886
7887#endif
1f224ad2 7888static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 7889 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 7890{
7891 struct i40e_netdev_priv *np = netdev_priv(netdev);
7892 struct i40e_pf *pf = np->vsi->back;
7893 struct i40e_hw *hw = &pf->hw;
7894
7895 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7896 return -EOPNOTSUPP;
7897
7898 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7899 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7900
7901 return 0;
7902}
7903
2f90ade6
JB		 7904/**
7905 * i40e_ndo_fdb_add - add an entry to the hardware database
7906 * @ndm: the input from the stack
7907 * @tb: pointer to array of nladdr (unused)
7908 * @dev: the net device pointer
7909 * @addr: the MAC address entry being added
7910 * @flags: instructions from stack about fdb operation
7911 */
4ba0dea5
GR		 7912static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7913 struct net_device *dev,
f6f6424b 7914 const unsigned char *addr, u16 vid,
4ba0dea5 7915 u16 flags)
4ba0dea5
GR		 7916{
7917 struct i40e_netdev_priv *np = netdev_priv(dev);
7918 struct i40e_pf *pf = np->vsi->back;
7919 int err = 0;
7920
7921 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7922 return -EOPNOTSUPP;
7923
65891fea
OG		 7924 if (vid) {
7925 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
7926 return -EINVAL;
7927 }
7928
4ba0dea5
GR		 7929 /* Hardware does not support aging addresses so if a
7930 * ndm_state is given only allow permanent addresses
7931 */
7932 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7933 netdev_info(dev, "FDB only supports static addresses\n");
7934 return -EINVAL;
7935 }
7936
7937 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7938 err = dev_uc_add_excl(dev, addr);
7939 else if (is_multicast_ether_addr(addr))
7940 err = dev_mc_add_excl(dev, addr);
7941 else
7942 err = -EINVAL;
7943
7944 /* Only return duplicate errors if NLM_F_EXCL is set */
7945 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7946 err = 0;
7947
7948 return err;
7949}
7950
51616018
NP		 7951#ifdef HAVE_BRIDGE_ATTRIBS
7952/**
7953 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
7954 * @dev: the netdev being configured
7955 * @nlh: RTNL message
7956 *
7957 * Inserts a new hardware bridge if not already created and
7958 * enables the bridging mode requested (VEB or VEPA). If the
7959 * hardware bridge has already been inserted and the request
7960 * is to change the mode then that requires a PF reset to
7961 * allow rebuild of the components with required hardware
7962 * bridge mode enabled.
7963 **/
7964static int i40e_ndo_bridge_setlink(struct net_device *dev,
7965 struct nlmsghdr *nlh)
7966{
7967 struct i40e_netdev_priv *np = netdev_priv(dev);
7968 struct i40e_vsi *vsi = np->vsi;
7969 struct i40e_pf *pf = vsi->back;
7970 struct i40e_veb *veb = NULL;
7971 struct nlattr *attr, *br_spec;
7972 int i, rem;
7973
7974 /* Only for PF VSI for now */
7975 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
7976 return -EOPNOTSUPP;
7977
7978 /* Find the HW bridge for PF VSI */
7979 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7980 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7981 veb = pf->veb[i];
7982 }
7983
7984 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7985
7986 nla_for_each_nested(attr, br_spec, rem) {
7987 __u16 mode;
7988
7989 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7990 continue;
7991
7992 mode = nla_get_u16(attr);
7993 if ((mode != BRIDGE_MODE_VEPA) &&
7994 (mode != BRIDGE_MODE_VEB))
7995 return -EINVAL;
7996
7997 /* Insert a new HW bridge */
7998 if (!veb) {
7999 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8000 vsi->tc_config.enabled_tc);
8001 if (veb) {
8002 veb->bridge_mode = mode;
8003 i40e_config_bridge_mode(veb);
8004 } else {
8005 /* No Bridge HW offload available */
8006 return -ENOENT;
8007 }
8008 break;
8009 } else if (mode != veb->bridge_mode) {
8010 /* Existing HW bridge but different mode needs reset */
8011 veb->bridge_mode = mode;
8012 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
8013 break;
8014 }
8015 }
8016
8017 return 0;
8018}
8019
8020/**
8021 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8022 * @skb: skb buff
8023 * @pid: process id
8024 * @seq: RTNL message seq #
8025 * @dev: the netdev being configured
8026 * @filter_mask: unused
8027 *
8028 * Return the mode in which the hardware bridge is operating in
8029 * i.e VEB or VEPA.
8030 **/
8031#ifdef HAVE_BRIDGE_FILTER
8032static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8033 struct net_device *dev,
8034 u32 __always_unused filter_mask)
8035#else
8036static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8037 struct net_device *dev)
8038#endif /* HAVE_BRIDGE_FILTER */
8039{
8040 struct i40e_netdev_priv *np = netdev_priv(dev);
8041 struct i40e_vsi *vsi = np->vsi;
8042 struct i40e_pf *pf = vsi->back;
8043 struct i40e_veb *veb = NULL;
8044 int i;
8045
8046 /* Only for PF VSI for now */
8047 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8048 return -EOPNOTSUPP;
8049
8050 /* Find the HW bridge for the PF VSI */
8051 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8052 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8053 veb = pf->veb[i];
8054 }
8055
8056 if (!veb)
8057 return 0;
8058
8059 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode);
8060}
8061#endif /* HAVE_BRIDGE_ATTRIBS */
8062
37a2973a 8063static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8064 .ndo_open = i40e_open,
8065 .ndo_stop = i40e_close,
8066 .ndo_start_xmit = i40e_lan_xmit_frame,
8067 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8068 .ndo_set_rx_mode = i40e_set_rx_mode,
8069 .ndo_validate_addr = eth_validate_addr,
8070 .ndo_set_mac_address = i40e_set_mac,
8071 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8072 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8073 .ndo_tx_timeout = i40e_tx_timeout,
8074 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8075 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8076#ifdef CONFIG_NET_POLL_CONTROLLER
8077 .ndo_poll_controller = i40e_netpoll,
8078#endif
8079 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8080#ifdef I40E_FCOE
8081 .ndo_fcoe_enable = i40e_fcoe_enable,
8082 .ndo_fcoe_disable = i40e_fcoe_disable,
8083#endif
41c445ff
JB		 8084 .ndo_set_features = i40e_set_features,
8085 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8086 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8087 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8088 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8089 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8090 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8091#ifdef CONFIG_I40E_VXLAN
8092 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8093 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8094#endif
1f224ad2 8095 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8096 .ndo_fdb_add = i40e_ndo_fdb_add,
51616018
NP		 8097#ifdef HAVE_BRIDGE_ATTRIBS
8098 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8099 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
8100#endif /* HAVE_BRIDGE_ATTRIBS */
41c445ff
JB		 8101};
8102
8103/**
8104 * i40e_config_netdev - Setup the netdev flags
8105 * @vsi: the VSI being configured
8106 *
8107 * Returns 0 on success, negative value on failure
8108 **/
8109static int i40e_config_netdev(struct i40e_vsi *vsi)
8110{
1a10370a 8111 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8112 struct i40e_pf *pf = vsi->back;
8113 struct i40e_hw *hw = &pf->hw;
8114 struct i40e_netdev_priv *np;
8115 struct net_device *netdev;
8116 u8 mac_addr[ETH_ALEN];
8117 int etherdev_size;
8118
8119 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8120 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8121 if (!netdev)
8122 return -ENOMEM;
8123
8124 vsi->netdev = netdev;
8125 np = netdev_priv(netdev);
8126 np->vsi = vsi;
8127
d70e941b 8128 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8129 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 8130 NETIF_F_TSO;
41c445ff
JB		 8131
8132 netdev->features = NETIF_F_SG |
8133 NETIF_F_IP_CSUM |
8134 NETIF_F_SCTP_CSUM |
8135 NETIF_F_HIGHDMA |
8136 NETIF_F_GSO_UDP_TUNNEL |
8137 NETIF_F_HW_VLAN_CTAG_TX |
8138 NETIF_F_HW_VLAN_CTAG_RX |
8139 NETIF_F_HW_VLAN_CTAG_FILTER |
8140 NETIF_F_IPV6_CSUM |
8141 NETIF_F_TSO |
059dab69 8142 NETIF_F_TSO_ECN |
41c445ff
JB		 8143 NETIF_F_TSO6 |
8144 NETIF_F_RXCSUM |
8145 NETIF_F_RXHASH |
8146 0;
8147
2e86a0b6
ASJ		 8148 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8149 netdev->features |= NETIF_F_NTUPLE;
8150
41c445ff
JB		 8151 /* copy netdev features into list of user selectable features */
8152 netdev->hw_features |= netdev->features;
8153
8154 if (vsi->type == I40E_VSI_MAIN) {
8155 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8156 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8157 /* The following steps are necessary to prevent reception
8158 * of tagged packets - some older NVM configurations load a
8159 * default a MAC-VLAN filter that accepts any tagged packet
8160 * which must be replaced by a normal filter.
8c27d42e 8161 */
30650cc5
SN		 8162 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8163 i40e_add_filter(vsi, mac_addr,
8164 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8165 } else {
8166 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8167 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8168 pf->vsi[pf->lan_vsi]->netdev->name);
8169 random_ether_addr(mac_addr);
8170 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8171 }
1a10370a 8172 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8173
9a173901
GR		 8174 ether_addr_copy(netdev->dev_addr, mac_addr);
8175 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8176 /* vlan gets same features (except vlan offload)
8177 * after any tweaks for specific VSI types
8178 */
8179 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8180 NETIF_F_HW_VLAN_CTAG_RX |
8181 NETIF_F_HW_VLAN_CTAG_FILTER);
8182 netdev->priv_flags |= IFF_UNICAST_FLT;
8183 netdev->priv_flags |= IFF_SUPP_NOFCS;
8184 /* Setup netdev TC information */
8185 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8186
8187 netdev->netdev_ops = &i40e_netdev_ops;
8188 netdev->watchdog_timeo = 5 * HZ;
8189 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8190#ifdef I40E_FCOE
8191 i40e_fcoe_config_netdev(netdev, vsi);
8192#endif
41c445ff
JB		 8193
8194 return 0;
8195}
8196
8197/**
8198 * i40e_vsi_delete - Delete a VSI from the switch
8199 * @vsi: the VSI being removed
8200 *
8201 * Returns 0 on success, negative value on failure
8202 **/
8203static void i40e_vsi_delete(struct i40e_vsi *vsi)
8204{
8205 /* remove default VSI is not allowed */
8206 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8207 return;
8208
41c445ff 8209 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8210}
8211
51616018
NP		 8212/**
8213 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8214 * @vsi: the VSI being queried
8215 *
8216 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8217 **/
8218int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8219{
8220 struct i40e_veb *veb;
8221 struct i40e_pf *pf = vsi->back;
8222
8223 /* Uplink is not a bridge so default to VEB */
8224 if (vsi->veb_idx == I40E_NO_VEB)
8225 return 1;
8226
8227 veb = pf->veb[vsi->veb_idx];
8228 /* Uplink is a bridge in VEPA mode */
8229 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8230 return 0;
8231
8232 /* Uplink is a bridge in VEB mode */
8233 return 1;
8234}
8235
41c445ff
JB		 8236/**
8237 * i40e_add_vsi - Add a VSI to the switch
8238 * @vsi: the VSI being configured
8239 *
8240 * This initializes a VSI context depending on the VSI type to be added and
8241 * passes it down to the add_vsi aq command.
8242 **/
8243static int i40e_add_vsi(struct i40e_vsi *vsi)
8244{
8245 int ret = -ENODEV;
8246 struct i40e_mac_filter *f, *ftmp;
8247 struct i40e_pf *pf = vsi->back;
8248 struct i40e_hw *hw = &pf->hw;
8249 struct i40e_vsi_context ctxt;
8250 u8 enabled_tc = 0x1; /* TC0 enabled */
8251 int f_count = 0;
8252
8253 memset(&ctxt, 0, sizeof(ctxt));
8254 switch (vsi->type) {
8255 case I40E_VSI_MAIN:
8256 /* The PF's main VSI is already setup as part of the
8257 * device initialization, so we'll not bother with
8258 * the add_vsi call, but we will retrieve the current
8259 * VSI context.
8260 */
8261 ctxt.seid = pf->main_vsi_seid;
8262 ctxt.pf_num = pf->hw.pf_id;
8263 ctxt.vf_num = 0;
8264 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8265 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8266 if (ret) {
8267 dev_info(&pf->pdev->dev,
b40c82e6 8268 "couldn't get PF vsi config, err %d, aq_err %d\n",
41c445ff
JB		 8269 ret, pf->hw.aq.asq_last_status);
8270 return -ENOENT;
8271 }
1a2f6248 8272 vsi->info = ctxt.info;
41c445ff
JB		 8273 vsi->info.valid_sections = 0;
8274
8275 vsi->seid = ctxt.seid;
8276 vsi->id = ctxt.vsi_number;
8277
8278 enabled_tc = i40e_pf_get_tc_map(pf);
8279
8280 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8281 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8282 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8283 memset(&ctxt, 0, sizeof(ctxt));
8284 ctxt.seid = pf->main_vsi_seid;
8285 ctxt.pf_num = pf->hw.pf_id;
8286 ctxt.vf_num = 0;
8287 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8288 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8289 if (ret) {
8290 dev_info(&pf->pdev->dev,
8291 "update vsi failed, aq_err=%d\n",
8292 pf->hw.aq.asq_last_status);
8293 ret = -ENOENT;
8294 goto err;
8295 }
8296 /* update the local VSI info queue map */
8297 i40e_vsi_update_queue_map(vsi, &ctxt);
8298 vsi->info.valid_sections = 0;
8299 } else {
8300 /* Default/Main VSI is only enabled for TC0
8301 * reconfigure it to enable all TCs that are
8302 * available on the port in SFP mode.
63d7e5a4
NP		 8303 * For MFP case the iSCSI PF would use this
8304 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8305 */
8306 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8307 if (ret) {
8308 dev_info(&pf->pdev->dev,
8309 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
8310 enabled_tc, ret,
8311 pf->hw.aq.asq_last_status);
8312 ret = -ENOENT;
8313 }
8314 }
8315 break;
8316
8317 case I40E_VSI_FDIR:
cbf61325
ASJ		 8318 ctxt.pf_num = hw->pf_id;
8319 ctxt.vf_num = 0;
8320 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8321 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8322 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
51616018
NP		 8323 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8324 ctxt.info.valid_sections |=
79c21a82 8325 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8326 ctxt.info.switch_id =
79c21a82 8327 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8328 }
41c445ff 8329 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8330 break;
8331
8332 case I40E_VSI_VMDQ2:
8333 ctxt.pf_num = hw->pf_id;
8334 ctxt.vf_num = 0;
8335 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8336 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8337 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8338
41c445ff
JB		 8339 /* This VSI is connected to VEB so the switch_id
8340 * should be set to zero by default.
8341 */
51616018
NP		 8342 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8343 ctxt.info.valid_sections |=
8344 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8345 ctxt.info.switch_id =
8346 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8347 }
41c445ff
JB		 8348
8349 /* Setup the VSI tx/rx queue map for TC0 only for now */
8350 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8351 break;
8352
8353 case I40E_VSI_SRIOV:
8354 ctxt.pf_num = hw->pf_id;
8355 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8356 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8357 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8358 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8359
41c445ff
JB		 8360 /* This VSI is connected to VEB so the switch_id
8361 * should be set to zero by default.
8362 */
51616018
NP		 8363 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8364 ctxt.info.valid_sections |=
8365 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8366 ctxt.info.switch_id =
8367 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8368 }
41c445ff
JB		 8369
8370 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8371 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8372 if (pf->vf[vsi->vf_id].spoofchk) {
8373 ctxt.info.valid_sections |=
8374 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8375 ctxt.info.sec_flags |=
8376 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8377 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8378 }
41c445ff
JB		 8379 /* Setup the VSI tx/rx queue map for TC0 only for now */
8380 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8381 break;
8382
38e00438
VD		 8383#ifdef I40E_FCOE
8384 case I40E_VSI_FCOE:
8385 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8386 if (ret) {
8387 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8388 return ret;
8389 }
8390 break;
8391
8392#endif /* I40E_FCOE */
41c445ff
JB		 8393 default:
8394 return -ENODEV;
8395 }
8396
8397 if (vsi->type != I40E_VSI_MAIN) {
8398 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8399 if (ret) {
8400 dev_info(&vsi->back->pdev->dev,
8401 "add vsi failed, aq_err=%d\n",
8402 vsi->back->hw.aq.asq_last_status);
8403 ret = -ENOENT;
8404 goto err;
8405 }
1a2f6248 8406 vsi->info = ctxt.info;
41c445ff
JB		 8407 vsi->info.valid_sections = 0;
8408 vsi->seid = ctxt.seid;
8409 vsi->id = ctxt.vsi_number;
8410 }
8411
8412 /* If macvlan filters already exist, force them to get loaded */
8413 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8414 f->changed = true;
8415 f_count++;
6252c7e4
SN		 8416
8417 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8418 struct i40e_aqc_remove_macvlan_element_data element;
8419
8420 memset(&element, 0, sizeof(element));
8421 ether_addr_copy(element.mac_addr, f->macaddr);
8422 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8423 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8424 &element, 1, NULL);
8425 if (ret) {
8426 /* some older FW has a different default */
8427 element.flags |=
8428 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8429 i40e_aq_remove_macvlan(hw, vsi->seid,
8430 &element, 1, NULL);
8431 }
8432
8433 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8434 I40E_AQC_WRITE_TYPE_LAA_WOL,
8435 f->macaddr, NULL);
8436 }
41c445ff
JB		 8437 }
8438 if (f_count) {
8439 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8440 pf->flags |= I40E_FLAG_FILTER_SYNC;
8441 }
8442
8443 /* Update VSI BW information */
8444 ret = i40e_vsi_get_bw_info(vsi);
8445 if (ret) {
8446 dev_info(&pf->pdev->dev,
8447 "couldn't get vsi bw info, err %d, aq_err %d\n",
8448 ret, pf->hw.aq.asq_last_status);
8449 /* VSI is already added so not tearing that up */
8450 ret = 0;
8451 }
8452
8453err:
8454 return ret;
8455}
8456
8457/**
8458 * i40e_vsi_release - Delete a VSI and free its resources
8459 * @vsi: the VSI being removed
8460 *
8461 * Returns 0 on success or < 0 on error
8462 **/
8463int i40e_vsi_release(struct i40e_vsi *vsi)
8464{
8465 struct i40e_mac_filter *f, *ftmp;
8466 struct i40e_veb *veb = NULL;
8467 struct i40e_pf *pf;
8468 u16 uplink_seid;
8469 int i, n;
8470
8471 pf = vsi->back;
8472
8473 /* release of a VEB-owner or last VSI is not allowed */
8474 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8475 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8476 vsi->seid, vsi->uplink_seid);
8477 return -ENODEV;
8478 }
8479 if (vsi == pf->vsi[pf->lan_vsi] &&
8480 !test_bit(__I40E_DOWN, &pf->state)) {
8481 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8482 return -ENODEV;
8483 }
8484
8485 uplink_seid = vsi->uplink_seid;
8486 if (vsi->type != I40E_VSI_SRIOV) {
8487 if (vsi->netdev_registered) {
8488 vsi->netdev_registered = false;
8489 if (vsi->netdev) {
8490 /* results in a call to i40e_close() */
8491 unregister_netdev(vsi->netdev);
41c445ff
JB		 8492 }
8493 } else {
90ef8d47 8494 i40e_vsi_close(vsi);
41c445ff
JB		 8495 }
8496 i40e_vsi_disable_irq(vsi);
8497 }
8498
8499 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8500 i40e_del_filter(vsi, f->macaddr, f->vlan,
8501 f->is_vf, f->is_netdev);
8502 i40e_sync_vsi_filters(vsi);
8503
8504 i40e_vsi_delete(vsi);
8505 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8506 if (vsi->netdev) {
8507 free_netdev(vsi->netdev);
8508 vsi->netdev = NULL;
8509 }
41c445ff
JB		 8510 i40e_vsi_clear_rings(vsi);
8511 i40e_vsi_clear(vsi);
8512
8513 /* If this was the last thing on the VEB, except for the
8514 * controlling VSI, remove the VEB, which puts the controlling
8515 * VSI onto the next level down in the switch.
8516 *
8517 * Well, okay, there's one more exception here: don't remove
8518 * the orphan VEBs yet. We'll wait for an explicit remove request
8519 * from up the network stack.
8520 */
505682cd 8521 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8522 if (pf->vsi[i] &&
8523 pf->vsi[i]->uplink_seid == uplink_seid &&
8524 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8525 n++; /* count the VSIs */
8526 }
8527 }
8528 for (i = 0; i < I40E_MAX_VEB; i++) {
8529 if (!pf->veb[i])
8530 continue;
8531 if (pf->veb[i]->uplink_seid == uplink_seid)
8532 n++; /* count the VEBs */
8533 if (pf->veb[i]->seid == uplink_seid)
8534 veb = pf->veb[i];
8535 }
8536 if (n == 0 && veb && veb->uplink_seid != 0)
8537 i40e_veb_release(veb);
8538
8539 return 0;
8540}
8541
8542/**
8543 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8544 * @vsi: ptr to the VSI
8545 *
8546 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8547 * corresponding SW VSI structure and initializes num_queue_pairs for the
8548 * newly allocated VSI.
8549 *
8550 * Returns 0 on success or negative on failure
8551 **/
8552static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8553{
8554 int ret = -ENOENT;
8555 struct i40e_pf *pf = vsi->back;
8556
493fb300 8557 if (vsi->q_vectors[0]) {
41c445ff
JB		 8558 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8559 vsi->seid);
8560 return -EEXIST;
8561 }
8562
8563 if (vsi->base_vector) {
f29eaa3d 8564 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8565 vsi->seid, vsi->base_vector);
8566 return -EEXIST;
8567 }
8568
90e04070 8569 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8570 if (ret) {
8571 dev_info(&pf->pdev->dev,
8572 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8573 vsi->num_q_vectors, vsi->seid, ret);
8574 vsi->num_q_vectors = 0;
8575 goto vector_setup_out;
8576 }
8577
958a3e3b
SN		 8578 if (vsi->num_q_vectors)
8579 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8580 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8581 if (vsi->base_vector < 0) {
8582 dev_info(&pf->pdev->dev,
049a2be8
SN		 8583 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8584 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8585 i40e_vsi_free_q_vectors(vsi);
8586 ret = -ENOENT;
8587 goto vector_setup_out;
8588 }
8589
8590vector_setup_out:
8591 return ret;
8592}
8593
bc7d338f
ASJ		 8594/**
8595 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8596 * @vsi: pointer to the vsi.
8597 *
8598 * This re-allocates a vsi's queue resources.
8599 *
8600 * Returns pointer to the successfully allocated and configured VSI sw struct
8601 * on success, otherwise returns NULL on failure.
8602 **/
8603static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8604{
8605 struct i40e_pf *pf = vsi->back;
8606 u8 enabled_tc;
8607 int ret;
8608
8609 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8610 i40e_vsi_clear_rings(vsi);
8611
8612 i40e_vsi_free_arrays(vsi, false);
8613 i40e_set_num_rings_in_vsi(vsi);
8614 ret = i40e_vsi_alloc_arrays(vsi, false);
8615 if (ret)
8616 goto err_vsi;
8617
8618 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8619 if (ret < 0) {
049a2be8
SN		 8620 dev_info(&pf->pdev->dev,
8621 "failed to get tracking for %d queues for VSI %d err=%d\n",
8622 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8623 goto err_vsi;
8624 }
8625 vsi->base_queue = ret;
8626
8627 /* Update the FW view of the VSI. Force a reset of TC and queue
8628 * layout configurations.
8629 */
8630 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8631 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8632 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8633 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8634
8635 /* assign it some queues */
8636 ret = i40e_alloc_rings(vsi);
8637 if (ret)
8638 goto err_rings;
8639
8640 /* map all of the rings to the q_vectors */
8641 i40e_vsi_map_rings_to_vectors(vsi);
8642 return vsi;
8643
8644err_rings:
8645 i40e_vsi_free_q_vectors(vsi);
8646 if (vsi->netdev_registered) {
8647 vsi->netdev_registered = false;
8648 unregister_netdev(vsi->netdev);
8649 free_netdev(vsi->netdev);
8650 vsi->netdev = NULL;
8651 }
8652 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8653err_vsi:
8654 i40e_vsi_clear(vsi);
8655 return NULL;
8656}
8657
41c445ff
JB		 8658/**
8659 * i40e_vsi_setup - Set up a VSI by a given type
8660 * @pf: board private structure
8661 * @type: VSI type
8662 * @uplink_seid: the switch element to link to
8663 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8664 *
8665 * This allocates the sw VSI structure and its queue resources, then add a VSI
8666 * to the identified VEB.
8667 *
8668 * Returns pointer to the successfully allocated and configure VSI sw struct on
8669 * success, otherwise returns NULL on failure.
8670 **/
8671struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8672 u16 uplink_seid, u32 param1)
8673{
8674 struct i40e_vsi *vsi = NULL;
8675 struct i40e_veb *veb = NULL;
8676 int ret, i;
8677 int v_idx;
8678
8679 /* The requested uplink_seid must be either
8680 * - the PF's port seid
8681 * no VEB is needed because this is the PF
8682 * or this is a Flow Director special case VSI
8683 * - seid of an existing VEB
8684 * - seid of a VSI that owns an existing VEB
8685 * - seid of a VSI that doesn't own a VEB
8686 * a new VEB is created and the VSI becomes the owner
8687 * - seid of the PF VSI, which is what creates the first VEB
8688 * this is a special case of the previous
8689 *
8690 * Find which uplink_seid we were given and create a new VEB if needed
8691 */
8692 for (i = 0; i < I40E_MAX_VEB; i++) {
8693 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8694 veb = pf->veb[i];
8695 break;
8696 }
8697 }
8698
8699 if (!veb && uplink_seid != pf->mac_seid) {
8700
505682cd 8701 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8702 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8703 vsi = pf->vsi[i];
8704 break;
8705 }
8706 }
8707 if (!vsi) {
8708 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8709 uplink_seid);
8710 return NULL;
8711 }
8712
8713 if (vsi->uplink_seid == pf->mac_seid)
8714 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8715 vsi->tc_config.enabled_tc);
8716 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8717 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8718 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 8719 if (veb) {
8720 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
8721 dev_info(&vsi->back->pdev->dev,
8722 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
8723 __func__);
8724 return NULL;
8725 }
51616018 8726 i40e_config_bridge_mode(veb);
79c21a82 8727 }
41c445ff
JB		 8728 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8729 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8730 veb = pf->veb[i];
8731 }
8732 if (!veb) {
8733 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8734 return NULL;
8735 }
8736
8737 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8738 uplink_seid = veb->seid;
8739 }
8740
8741 /* get vsi sw struct */
8742 v_idx = i40e_vsi_mem_alloc(pf, type);
8743 if (v_idx < 0)
8744 goto err_alloc;
8745 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8746 if (!vsi)
8747 goto err_alloc;
41c445ff
JB		 8748 vsi->type = type;
8749 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8750
8751 if (type == I40E_VSI_MAIN)
8752 pf->lan_vsi = v_idx;
8753 else if (type == I40E_VSI_SRIOV)
8754 vsi->vf_id = param1;
8755 /* assign it some queues */
cbf61325
ASJ		 8756 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8757 vsi->idx);
41c445ff 8758 if (ret < 0) {
049a2be8
SN		 8759 dev_info(&pf->pdev->dev,
8760 "failed to get tracking for %d queues for VSI %d err=%d\n",
8761 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 8762 goto err_vsi;
8763 }
8764 vsi->base_queue = ret;
8765
8766 /* get a VSI from the hardware */
8767 vsi->uplink_seid = uplink_seid;
8768 ret = i40e_add_vsi(vsi);
8769 if (ret)
8770 goto err_vsi;
8771
8772 switch (vsi->type) {
8773 /* setup the netdev if needed */
8774 case I40E_VSI_MAIN:
8775 case I40E_VSI_VMDQ2:
38e00438 8776 case I40E_VSI_FCOE:
41c445ff
JB		 8777 ret = i40e_config_netdev(vsi);
8778 if (ret)
8779 goto err_netdev;
8780 ret = register_netdev(vsi->netdev);
8781 if (ret)
8782 goto err_netdev;
8783 vsi->netdev_registered = true;
8784 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8785#ifdef CONFIG_I40E_DCB
8786 /* Setup DCB netlink interface */
8787 i40e_dcbnl_setup(vsi);
8788#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8789 /* fall through */
8790
8791 case I40E_VSI_FDIR:
8792 /* set up vectors and rings if needed */
8793 ret = i40e_vsi_setup_vectors(vsi);
8794 if (ret)
8795 goto err_msix;
8796
8797 ret = i40e_alloc_rings(vsi);
8798 if (ret)
8799 goto err_rings;
8800
8801 /* map all of the rings to the q_vectors */
8802 i40e_vsi_map_rings_to_vectors(vsi);
8803
8804 i40e_vsi_reset_stats(vsi);
8805 break;
8806
8807 default:
8808 /* no netdev or rings for the other VSI types */
8809 break;
8810 }
8811
8812 return vsi;
8813
8814err_rings:
8815 i40e_vsi_free_q_vectors(vsi);
8816err_msix:
8817 if (vsi->netdev_registered) {
8818 vsi->netdev_registered = false;
8819 unregister_netdev(vsi->netdev);
8820 free_netdev(vsi->netdev);
8821 vsi->netdev = NULL;
8822 }
8823err_netdev:
8824 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8825err_vsi:
8826 i40e_vsi_clear(vsi);
8827err_alloc:
8828 return NULL;
8829}
8830
8831/**
8832 * i40e_veb_get_bw_info - Query VEB BW information
8833 * @veb: the veb to query
8834 *
8835 * Query the Tx scheduler BW configuration data for given VEB
8836 **/
8837static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8838{
8839 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8840 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8841 struct i40e_pf *pf = veb->pf;
8842 struct i40e_hw *hw = &pf->hw;
8843 u32 tc_bw_max;
8844 int ret = 0;
8845 int i;
8846
8847 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8848 &bw_data, NULL);
8849 if (ret) {
8850 dev_info(&pf->pdev->dev,
8851 "query veb bw config failed, aq_err=%d\n",
8852 hw->aq.asq_last_status);
8853 goto out;
8854 }
8855
8856 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8857 &ets_data, NULL);
8858 if (ret) {
8859 dev_info(&pf->pdev->dev,
8860 "query veb bw ets config failed, aq_err=%d\n",
8861 hw->aq.asq_last_status);
8862 goto out;
8863 }
8864
8865 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8866 veb->bw_max_quanta = ets_data.tc_bw_max;
8867 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 8868 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 8869 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8870 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8871 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8872 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8873 veb->bw_tc_limit_credits[i] =
8874 le16_to_cpu(bw_data.tc_bw_limits[i]);
8875 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8876 }
8877
8878out:
8879 return ret;
8880}
8881
8882/**
8883 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8884 * @pf: board private structure
8885 *
8886 * On error: returns error code (negative)
8887 * On success: returns vsi index in PF (positive)
8888 **/
8889static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8890{
8891 int ret = -ENOENT;
8892 struct i40e_veb *veb;
8893 int i;
8894
8895 /* Need to protect the allocation of switch elements at the PF level */
8896 mutex_lock(&pf->switch_mutex);
8897
8898 /* VEB list may be fragmented if VEB creation/destruction has
8899 * been happening. We can afford to do a quick scan to look
8900 * for any free slots in the list.
8901 *
8902 * find next empty veb slot, looping back around if necessary
8903 */
8904 i = 0;
8905 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8906 i++;
8907 if (i >= I40E_MAX_VEB) {
8908 ret = -ENOMEM;
8909 goto err_alloc_veb; /* out of VEB slots! */
8910 }
8911
8912 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8913 if (!veb) {
8914 ret = -ENOMEM;
8915 goto err_alloc_veb;
8916 }
8917 veb->pf = pf;
8918 veb->idx = i;
8919 veb->enabled_tc = 1;
8920
8921 pf->veb[i] = veb;
8922 ret = i;
8923err_alloc_veb:
8924 mutex_unlock(&pf->switch_mutex);
8925 return ret;
8926}
8927
8928/**
8929 * i40e_switch_branch_release - Delete a branch of the switch tree
8930 * @branch: where to start deleting
8931 *
8932 * This uses recursion to find the tips of the branch to be
8933 * removed, deleting until we get back to and can delete this VEB.
8934 **/
8935static void i40e_switch_branch_release(struct i40e_veb *branch)
8936{
8937 struct i40e_pf *pf = branch->pf;
8938 u16 branch_seid = branch->seid;
8939 u16 veb_idx = branch->idx;
8940 int i;
8941
8942 /* release any VEBs on this VEB - RECURSION */
8943 for (i = 0; i < I40E_MAX_VEB; i++) {
8944 if (!pf->veb[i])
8945 continue;
8946 if (pf->veb[i]->uplink_seid == branch->seid)
8947 i40e_switch_branch_release(pf->veb[i]);
8948 }
8949
8950 /* Release the VSIs on this VEB, but not the owner VSI.
8951 *
8952 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8953 * the VEB itself, so don't use (*branch) after this loop.
8954 */
505682cd 8955 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8956 if (!pf->vsi[i])
8957 continue;
8958 if (pf->vsi[i]->uplink_seid == branch_seid &&
8959 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8960 i40e_vsi_release(pf->vsi[i]);
8961 }
8962 }
8963
8964 /* There's one corner case where the VEB might not have been
8965 * removed, so double check it here and remove it if needed.
8966 * This case happens if the veb was created from the debugfs
8967 * commands and no VSIs were added to it.
8968 */
8969 if (pf->veb[veb_idx])
8970 i40e_veb_release(pf->veb[veb_idx]);
8971}
8972
8973/**
8974 * i40e_veb_clear - remove veb struct
8975 * @veb: the veb to remove
8976 **/
8977static void i40e_veb_clear(struct i40e_veb *veb)
8978{
8979 if (!veb)
8980 return;
8981
8982 if (veb->pf) {
8983 struct i40e_pf *pf = veb->pf;
8984
8985 mutex_lock(&pf->switch_mutex);
8986 if (pf->veb[veb->idx] == veb)
8987 pf->veb[veb->idx] = NULL;
8988 mutex_unlock(&pf->switch_mutex);
8989 }
8990
8991 kfree(veb);
8992}
8993
8994/**
8995 * i40e_veb_release - Delete a VEB and free its resources
8996 * @veb: the VEB being removed
8997 **/
8998void i40e_veb_release(struct i40e_veb *veb)
8999{
9000 struct i40e_vsi *vsi = NULL;
9001 struct i40e_pf *pf;
9002 int i, n = 0;
9003
9004 pf = veb->pf;
9005
9006 /* find the remaining VSI and check for extras */
505682cd 9007 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9008 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9009 n++;
9010 vsi = pf->vsi[i];
9011 }
9012 }
9013 if (n != 1) {
9014 dev_info(&pf->pdev->dev,
9015 "can't remove VEB %d with %d VSIs left\n",
9016 veb->seid, n);
9017 return;
9018 }
9019
9020 /* move the remaining VSI to uplink veb */
9021 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9022 if (veb->uplink_seid) {
9023 vsi->uplink_seid = veb->uplink_seid;
9024 if (veb->uplink_seid == pf->mac_seid)
9025 vsi->veb_idx = I40E_NO_VEB;
9026 else
9027 vsi->veb_idx = veb->veb_idx;
9028 } else {
9029 /* floating VEB */
9030 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9031 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9032 }
9033
9034 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9035 i40e_veb_clear(veb);
41c445ff
JB		 9036}
9037
9038/**
9039 * i40e_add_veb - create the VEB in the switch
9040 * @veb: the VEB to be instantiated
9041 * @vsi: the controlling VSI
9042 **/
9043static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9044{
56747264 9045 bool is_default = false;
e1c51b95 9046 bool is_cloud = false;
41c445ff
JB		 9047 int ret;
9048
9049 /* get a VEB from the hardware */
9050 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9051 veb->enabled_tc, is_default,
9052 is_cloud, &veb->seid, NULL);
41c445ff
JB		 9053 if (ret) {
9054 dev_info(&veb->pf->pdev->dev,
9055 "couldn't add VEB, err %d, aq_err %d\n",
9056 ret, veb->pf->hw.aq.asq_last_status);
9057 return -EPERM;
9058 }
9059
9060 /* get statistics counter */
9061 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
9062 &veb->stats_idx, NULL, NULL, NULL);
9063 if (ret) {
9064 dev_info(&veb->pf->pdev->dev,
9065 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
9066 ret, veb->pf->hw.aq.asq_last_status);
9067 return -EPERM;
9068 }
9069 ret = i40e_veb_get_bw_info(veb);
9070 if (ret) {
9071 dev_info(&veb->pf->pdev->dev,
9072 "couldn't get VEB bw info, err %d, aq_err %d\n",
9073 ret, veb->pf->hw.aq.asq_last_status);
9074 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
9075 return -ENOENT;
9076 }
9077
9078 vsi->uplink_seid = veb->seid;
9079 vsi->veb_idx = veb->idx;
9080 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9081
9082 return 0;
9083}
9084
9085/**
9086 * i40e_veb_setup - Set up a VEB
9087 * @pf: board private structure
9088 * @flags: VEB setup flags
9089 * @uplink_seid: the switch element to link to
9090 * @vsi_seid: the initial VSI seid
9091 * @enabled_tc: Enabled TC bit-map
9092 *
9093 * This allocates the sw VEB structure and links it into the switch
9094 * It is possible and legal for this to be a duplicate of an already
9095 * existing VEB. It is also possible for both uplink and vsi seids
9096 * to be zero, in order to create a floating VEB.
9097 *
9098 * Returns pointer to the successfully allocated VEB sw struct on
9099 * success, otherwise returns NULL on failure.
9100 **/
9101struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9102 u16 uplink_seid, u16 vsi_seid,
9103 u8 enabled_tc)
9104{
9105 struct i40e_veb *veb, *uplink_veb = NULL;
9106 int vsi_idx, veb_idx;
9107 int ret;
9108
9109 /* if one seid is 0, the other must be 0 to create a floating relay */
9110 if ((uplink_seid == 0 || vsi_seid == 0) &&
9111 (uplink_seid + vsi_seid != 0)) {
9112 dev_info(&pf->pdev->dev,
9113 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9114 uplink_seid, vsi_seid);
9115 return NULL;
9116 }
9117
9118 /* make sure there is such a vsi and uplink */
505682cd 9119 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9120 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9121 break;
505682cd 9122 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9123 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9124 vsi_seid);
9125 return NULL;
9126 }
9127
9128 if (uplink_seid && uplink_seid != pf->mac_seid) {
9129 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9130 if (pf->veb[veb_idx] &&
9131 pf->veb[veb_idx]->seid == uplink_seid) {
9132 uplink_veb = pf->veb[veb_idx];
9133 break;
9134 }
9135 }
9136 if (!uplink_veb) {
9137 dev_info(&pf->pdev->dev,
9138 "uplink seid %d not found\n", uplink_seid);
9139 return NULL;
9140 }
9141 }
9142
9143 /* get veb sw struct */
9144 veb_idx = i40e_veb_mem_alloc(pf);
9145 if (veb_idx < 0)
9146 goto err_alloc;
9147 veb = pf->veb[veb_idx];
9148 veb->flags = flags;
9149 veb->uplink_seid = uplink_seid;
9150 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9151 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9152
9153 /* create the VEB in the switch */
9154 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9155 if (ret)
9156 goto err_veb;
1bb8b935
SN		 9157 if (vsi_idx == pf->lan_vsi)
9158 pf->lan_veb = veb->idx;
41c445ff
JB		 9159
9160 return veb;
9161
9162err_veb:
9163 i40e_veb_clear(veb);
9164err_alloc:
9165 return NULL;
9166}
9167
9168/**
b40c82e6 9169 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9170 * @pf: board private structure
9171 * @ele: element we are building info from
9172 * @num_reported: total number of elements
9173 * @printconfig: should we print the contents
9174 *
9175 * helper function to assist in extracting a few useful SEID values.
9176 **/
9177static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9178 struct i40e_aqc_switch_config_element_resp *ele,
9179 u16 num_reported, bool printconfig)
9180{
9181 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9182 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9183 u8 element_type = ele->element_type;
9184 u16 seid = le16_to_cpu(ele->seid);
9185
9186 if (printconfig)
9187 dev_info(&pf->pdev->dev,
9188 "type=%d seid=%d uplink=%d downlink=%d\n",
9189 element_type, seid, uplink_seid, downlink_seid);
9190
9191 switch (element_type) {
9192 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9193 pf->mac_seid = seid;
9194 break;
9195 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9196 /* Main VEB? */
9197 if (uplink_seid != pf->mac_seid)
9198 break;
9199 if (pf->lan_veb == I40E_NO_VEB) {
9200 int v;
9201
9202 /* find existing or else empty VEB */
9203 for (v = 0; v < I40E_MAX_VEB; v++) {
9204 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9205 pf->lan_veb = v;
9206 break;
9207 }
9208 }
9209 if (pf->lan_veb == I40E_NO_VEB) {
9210 v = i40e_veb_mem_alloc(pf);
9211 if (v < 0)
9212 break;
9213 pf->lan_veb = v;
9214 }
9215 }
9216
9217 pf->veb[pf->lan_veb]->seid = seid;
9218 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9219 pf->veb[pf->lan_veb]->pf = pf;
9220 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9221 break;
9222 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9223 if (num_reported != 1)
9224 break;
9225 /* This is immediately after a reset so we can assume this is
9226 * the PF's VSI
9227 */
9228 pf->mac_seid = uplink_seid;
9229 pf->pf_seid = downlink_seid;
9230 pf->main_vsi_seid = seid;
9231 if (printconfig)
9232 dev_info(&pf->pdev->dev,
9233 "pf_seid=%d main_vsi_seid=%d\n",
9234 pf->pf_seid, pf->main_vsi_seid);
9235 break;
9236 case I40E_SWITCH_ELEMENT_TYPE_PF:
9237 case I40E_SWITCH_ELEMENT_TYPE_VF:
9238 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9239 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9240 case I40E_SWITCH_ELEMENT_TYPE_PE:
9241 case I40E_SWITCH_ELEMENT_TYPE_PA:
9242 /* ignore these for now */
9243 break;
9244 default:
9245 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9246 element_type, seid);
9247 break;
9248 }
9249}
9250
9251/**
9252 * i40e_fetch_switch_configuration - Get switch config from firmware
9253 * @pf: board private structure
9254 * @printconfig: should we print the contents
9255 *
9256 * Get the current switch configuration from the device and
9257 * extract a few useful SEID values.
9258 **/
9259int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9260{
9261 struct i40e_aqc_get_switch_config_resp *sw_config;
9262 u16 next_seid = 0;
9263 int ret = 0;
9264 u8 *aq_buf;
9265 int i;
9266
9267 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9268 if (!aq_buf)
9269 return -ENOMEM;
9270
9271 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9272 do {
9273 u16 num_reported, num_total;
9274
9275 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9276 I40E_AQ_LARGE_BUF,
9277 &next_seid, NULL);
9278 if (ret) {
9279 dev_info(&pf->pdev->dev,
9280 "get switch config failed %d aq_err=%x\n",
9281 ret, pf->hw.aq.asq_last_status);
9282 kfree(aq_buf);
9283 return -ENOENT;
9284 }
9285
9286 num_reported = le16_to_cpu(sw_config->header.num_reported);
9287 num_total = le16_to_cpu(sw_config->header.num_total);
9288
9289 if (printconfig)
9290 dev_info(&pf->pdev->dev,
9291 "header: %d reported %d total\n",
9292 num_reported, num_total);
9293
41c445ff
JB		 9294 for (i = 0; i < num_reported; i++) {
9295 struct i40e_aqc_switch_config_element_resp *ele =
9296 &sw_config->element[i];
9297
9298 i40e_setup_pf_switch_element(pf, ele, num_reported,
9299 printconfig);
9300 }
9301 } while (next_seid != 0);
9302
9303 kfree(aq_buf);
9304 return ret;
9305}
9306
9307/**
9308 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9309 * @pf: board private structure
bc7d338f 9310 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9311 *
9312 * Returns 0 on success, negative value on failure
9313 **/
bc7d338f 9314static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9315{
9316 int ret;
9317
9318 /* find out what's out there already */
9319 ret = i40e_fetch_switch_configuration(pf, false);
9320 if (ret) {
9321 dev_info(&pf->pdev->dev,
9322 "couldn't fetch switch config, err %d, aq_err %d\n",
9323 ret, pf->hw.aq.asq_last_status);
9324 return ret;
9325 }
9326 i40e_pf_reset_stats(pf);
9327
41c445ff 9328 /* first time setup */
bc7d338f 9329 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9330 struct i40e_vsi *vsi = NULL;
9331 u16 uplink_seid;
9332
9333 /* Set up the PF VSI associated with the PF's main VSI
9334 * that is already in the HW switch
9335 */
9336 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9337 uplink_seid = pf->veb[pf->lan_veb]->seid;
9338 else
9339 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9340 if (pf->lan_vsi == I40E_NO_VSI)
9341 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9342 else if (reinit)
9343 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9344 if (!vsi) {
9345 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9346 i40e_fdir_teardown(pf);
9347 return -EAGAIN;
9348 }
41c445ff
JB		 9349 } else {
9350 /* force a reset of TC and queue layout configurations */
9351 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9352 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9353 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9354 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9355 }
9356 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9357
cbf61325
ASJ		 9358 i40e_fdir_sb_setup(pf);
9359
41c445ff
JB		 9360 /* Setup static PF queue filter control settings */
9361 ret = i40e_setup_pf_filter_control(pf);
9362 if (ret) {
9363 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9364 ret);
9365 /* Failure here should not stop continuing other steps */
9366 }
9367
9368 /* enable RSS in the HW, even for only one queue, as the stack can use
9369 * the hash
9370 */
9371 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9372 i40e_config_rss(pf);
9373
9374 /* fill in link information and enable LSE reporting */
21af70fb 9375 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9376 i40e_link_event(pf);
9377
d52c20b7 9378 /* Initialize user-specific link properties */
41c445ff
JB		 9379 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9380 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9381
beb0dff1
JK		 9382 i40e_ptp_init(pf);
9383
41c445ff
JB		 9384 return ret;
9385}
9386
41c445ff
JB		 9387/**
9388 * i40e_determine_queue_usage - Work out queue distribution
9389 * @pf: board private structure
9390 **/
9391static void i40e_determine_queue_usage(struct i40e_pf *pf)
9392{
41c445ff
JB		 9393 int queues_left;
9394
9395 pf->num_lan_qps = 0;
38e00438
VD		 9396#ifdef I40E_FCOE
9397 pf->num_fcoe_qps = 0;
9398#endif
41c445ff
JB		 9399
9400 /* Find the max queues to be put into basic use. We'll always be
9401 * using TC0, whether or not DCB is running, and TC0 will get the
9402 * big RSS set.
9403 */
9404 queues_left = pf->hw.func_caps.num_tx_qp;
9405
cbf61325 9406 if ((queues_left == 1) ||
9aa7e935 9407 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9408 /* one qp for PF, no queues for anything else */
9409 queues_left = 0;
9410 pf->rss_size = pf->num_lan_qps = 1;
9411
9412 /* make sure all the fancies are disabled */
60ea5f83 9413 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9414#ifdef I40E_FCOE
9415 I40E_FLAG_FCOE_ENABLED |
9416#endif
60ea5f83
JB		 9417 I40E_FLAG_FD_SB_ENABLED |
9418 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9419 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9420 I40E_FLAG_SRIOV_ENABLED |
9421 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9422 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9423 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9424 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9425 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9426 /* one qp for PF */
9427 pf->rss_size = pf->num_lan_qps = 1;
9428 queues_left -= pf->num_lan_qps;
9429
9430 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9431#ifdef I40E_FCOE
9432 I40E_FLAG_FCOE_ENABLED |
9433#endif
9aa7e935
FZ		 9434 I40E_FLAG_FD_SB_ENABLED |
9435 I40E_FLAG_FD_ATR_ENABLED |
9436 I40E_FLAG_DCB_ENABLED |
9437 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9438 } else {
cbf61325 9439 /* Not enough queues for all TCs */
4d9b6043 9440 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9441 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9442 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9443 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9444 }
9a3bd2f1
ASJ		 9445 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9446 num_online_cpus());
9447 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9448 pf->hw.func_caps.num_tx_qp);
9449
cbf61325
ASJ		 9450 queues_left -= pf->num_lan_qps;
9451 }
9452
38e00438
VD		 9453#ifdef I40E_FCOE
9454 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9455 if (I40E_DEFAULT_FCOE <= queues_left) {
9456 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9457 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9458 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9459 } else {
9460 pf->num_fcoe_qps = 0;
9461 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9462 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9463 }
9464
9465 queues_left -= pf->num_fcoe_qps;
9466 }
9467
9468#endif
cbf61325
ASJ		 9469 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9470 if (queues_left > 1) {
9471 queues_left -= 1; /* save 1 queue for FD */
9472 } else {
9473 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9474 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9475 }
41c445ff
JB		 9476 }
9477
9478 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9479 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9480 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9481 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9482 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9483 }
9484
9485 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9486 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9487 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9488 (queues_left / pf->num_vmdq_qps));
9489 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9490 }
9491
f8ff1464 9492 pf->queues_left = queues_left;
38e00438
VD		 9493#ifdef I40E_FCOE
9494 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9495#endif
41c445ff
JB		 9496}
9497
9498/**
9499 * i40e_setup_pf_filter_control - Setup PF static filter control
9500 * @pf: PF to be setup
9501 *
b40c82e6 9502 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 9503 * settings. If PE/FCoE are enabled then it will also set the per PF
9504 * based filter sizes required for them. It also enables Flow director,
9505 * ethertype and macvlan type filter settings for the pf.
9506 *
9507 * Returns 0 on success, negative on failure
9508 **/
9509static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9510{
9511 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9512
9513 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9514
9515 /* Flow Director is enabled */
60ea5f83 9516 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9517 settings->enable_fdir = true;
9518
9519 /* Ethtype and MACVLAN filters enabled for PF */
9520 settings->enable_ethtype = true;
9521 settings->enable_macvlan = true;
9522
9523 if (i40e_set_filter_control(&pf->hw, settings))
9524 return -ENOENT;
9525
9526 return 0;
9527}
9528
0c22b3dd
JB		 9529#define INFO_STRING_LEN 255
9530static void i40e_print_features(struct i40e_pf *pf)
9531{
9532 struct i40e_hw *hw = &pf->hw;
9533 char *buf, *string;
9534
9535 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9536 if (!string) {
9537 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9538 return;
9539 }
9540
9541 buf = string;
9542
9543 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9544#ifdef CONFIG_PCI_IOV
9545 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9546#endif
aba237d1
MW		 9547 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9548 pf->hw.func_caps.num_vsis,
9549 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9550 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9551
9552 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9553 buf += sprintf(buf, "RSS ");
0c22b3dd 9554 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9555 buf += sprintf(buf, "FD_ATR ");
9556 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9557 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9558 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9559 }
4d9b6043 9560 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9561 buf += sprintf(buf, "DCB ");
9562 if (pf->flags & I40E_FLAG_PTP)
9563 buf += sprintf(buf, "PTP ");
38e00438
VD		 9564#ifdef I40E_FCOE
9565 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9566 buf += sprintf(buf, "FCOE ");
9567#endif
0c22b3dd
JB		 9568
9569 BUG_ON(buf > (string + INFO_STRING_LEN));
9570 dev_info(&pf->pdev->dev, "%s\n", string);
9571 kfree(string);
9572}
9573
41c445ff
JB		 9574/**
9575 * i40e_probe - Device initialization routine
9576 * @pdev: PCI device information struct
9577 * @ent: entry in i40e_pci_tbl
9578 *
b40c82e6
JK		 9579 * i40e_probe initializes a PF identified by a pci_dev structure.
9580 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 9581 * and a hardware reset occur.
9582 *
9583 * Returns 0 on success, negative on failure
9584 **/
9585static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9586{
e827845c 9587 struct i40e_aq_get_phy_abilities_resp abilities;
e815665e 9588 unsigned long ioremap_len;
41c445ff
JB		 9589 struct i40e_pf *pf;
9590 struct i40e_hw *hw;
93cd765b 9591 static u16 pfs_found;
d4dfb81a 9592 u16 link_status;
41c445ff
JB		 9593 int err = 0;
9594 u32 len;
8a9eb7d3 9595 u32 i;
41c445ff
JB		 9596
9597 err = pci_enable_device_mem(pdev);
9598 if (err)
9599 return err;
9600
9601 /* set up for high or low dma */
6494294f 9602 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9603 if (err) {
e3e3bfdd
JS		 9604 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9605 if (err) {
9606 dev_err(&pdev->dev,
9607 "DMA configuration failed: 0x%x\n", err);
9608 goto err_dma;
9609 }
41c445ff
JB		 9610 }
9611
9612 /* set up pci connections */
9613 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9614 IORESOURCE_MEM), i40e_driver_name);
9615 if (err) {
9616 dev_info(&pdev->dev,
9617 "pci_request_selected_regions failed %d\n", err);
9618 goto err_pci_reg;
9619 }
9620
9621 pci_enable_pcie_error_reporting(pdev);
9622 pci_set_master(pdev);
9623
9624 /* Now that we have a PCI connection, we need to do the
9625 * low level device setup. This is primarily setting up
9626 * the Admin Queue structures and then querying for the
9627 * device's current profile information.
9628 */
9629 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9630 if (!pf) {
9631 err = -ENOMEM;
9632 goto err_pf_alloc;
9633 }
9634 pf->next_vsi = 0;
9635 pf->pdev = pdev;
9636 set_bit(__I40E_DOWN, &pf->state);
9637
9638 hw = &pf->hw;
9639 hw->back = pf;
232f4706 9640
e815665e 9641 ioremap_len = min_t(unsigned long, pci_resource_len(pdev, 0),
232f4706
AS		 9642 I40E_MAX_CSR_SPACE);
9643
9644 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), ioremap_len);
41c445ff
JB		 9645 if (!hw->hw_addr) {
9646 err = -EIO;
9647 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9648 (unsigned int)pci_resource_start(pdev, 0),
9649 (unsigned int)pci_resource_len(pdev, 0), err);
9650 goto err_ioremap;
9651 }
9652 hw->vendor_id = pdev->vendor;
9653 hw->device_id = pdev->device;
9654 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9655 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9656 hw->subsystem_device_id = pdev->subsystem_device;
9657 hw->bus.device = PCI_SLOT(pdev->devfn);
9658 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9659 pf->instance = pfs_found;
41c445ff 9660
5b5faa43
SN		 9661 if (debug != -1) {
9662 pf->msg_enable = pf->hw.debug_mask;
9663 pf->msg_enable = debug;
9664 }
9665
7134f9ce
JB		 9666 /* do a special CORER for clearing PXE mode once at init */
9667 if (hw->revision_id == 0 &&
9668 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9669 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9670 i40e_flush(hw);
9671 msleep(200);
9672 pf->corer_count++;
9673
9674 i40e_clear_pxe_mode(hw);
9675 }
9676
41c445ff 9677 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9678 i40e_clear_hw(hw);
41c445ff
JB		 9679 err = i40e_pf_reset(hw);
9680 if (err) {
9681 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9682 goto err_pf_reset;
9683 }
9684 pf->pfr_count++;
9685
9686 hw->aq.num_arq_entries = I40E_AQ_LEN;
9687 hw->aq.num_asq_entries = I40E_AQ_LEN;
9688 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9689 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9690 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 9691
b294ac70 9692 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 9693 "%s-%s:misc",
9694 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 9695
9696 err = i40e_init_shared_code(hw);
9697 if (err) {
9698 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9699 goto err_pf_reset;
9700 }
9701
d52c20b7
JB		 9702 /* set up a default setting for link flow control */
9703 pf->hw.fc.requested_mode = I40E_FC_NONE;
9704
41c445ff
JB		 9705 err = i40e_init_adminq(hw);
9706 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9707 if (err) {
9708 dev_info(&pdev->dev,
7aa67613 9709 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9710 goto err_pf_reset;
9711 }
9712
7aa67613
CS		 9713 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9714 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9715 dev_info(&pdev->dev,
7aa67613
CS		 9716 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9717 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9718 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9719 dev_info(&pdev->dev,
7aa67613 9720 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 9721
4eb3f768
SN		 9722 i40e_verify_eeprom(pf);
9723
2c5fe33b
JB		 9724 /* Rev 0 hardware was never productized */
9725 if (hw->revision_id < 1)
9726 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9727
6ff4ef86 9728 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9729 err = i40e_get_capabilities(pf);
9730 if (err)
9731 goto err_adminq_setup;
9732
9733 err = i40e_sw_init(pf);
9734 if (err) {
9735 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9736 goto err_sw_init;
9737 }
9738
9739 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9740 hw->func_caps.num_rx_qp,
9741 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9742 if (err) {
9743 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9744 goto err_init_lan_hmc;
9745 }
9746
9747 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9748 if (err) {
9749 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9750 err = -ENOENT;
9751 goto err_configure_lan_hmc;
9752 }
9753
b686ece5
NP		 9754 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
9755 * Ignore error return codes because if it was already disabled via
9756 * hardware settings this will fail
9757 */
9758 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
9759 (pf->hw.aq.fw_maj_ver < 4)) {
9760 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
9761 i40e_aq_stop_lldp(hw, true, NULL);
9762 }
9763
41c445ff 9764 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9765 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9766 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9767 err = -EIO;
9768 goto err_mac_addr;
9769 }
9770 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9771 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9772 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9773 if (is_valid_ether_addr(hw->mac.port_addr))
9774 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9775#ifdef I40E_FCOE
9776 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9777 if (err)
9778 dev_info(&pdev->dev,
9779 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9780 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9781 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9782 hw->mac.san_addr);
9783 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9784 }
9785 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9786#endif /* I40E_FCOE */
41c445ff
JB		 9787
9788 pci_set_drvdata(pdev, pf);
9789 pci_save_state(pdev);
4e3b35b0
NP		 9790#ifdef CONFIG_I40E_DCB
9791 err = i40e_init_pf_dcb(pf);
9792 if (err) {
aebfc816 9793 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 9794 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9795 /* Continue without DCB enabled */
4e3b35b0
NP		 9796 }
9797#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9798
9799 /* set up periodic task facility */
9800 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9801 pf->service_timer_period = HZ;
9802
9803 INIT_WORK(&pf->service_task, i40e_service_task);
9804 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9805 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9806 pf->link_check_timeout = jiffies;
9807
8e2773ae
SN		 9808 /* WoL defaults to disabled */
9809 pf->wol_en = false;
9810 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9811
41c445ff
JB		 9812 /* set up the main switch operations */
9813 i40e_determine_queue_usage(pf);
9814 i40e_init_interrupt_scheme(pf);
9815
505682cd
MW		 9816 /* The number of VSIs reported by the FW is the minimum guaranteed
9817 * to us; HW supports far more and we share the remaining pool with
9818 * the other PFs. We allocate space for more than the guarantee with
9819 * the understanding that we might not get them all later.
41c445ff 9820 */
505682cd
MW		 9821 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9822 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9823 else
9824 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9825
9826 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9827 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9828 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9829 if (!pf->vsi) {
9830 err = -ENOMEM;
41c445ff 9831 goto err_switch_setup;
ed87ac09 9832 }
41c445ff 9833
bc7d338f 9834 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9835 if (err) {
9836 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9837 goto err_vsis;
9838 }
8a9eb7d3 9839 /* if FDIR VSI was set up, start it now */
505682cd 9840 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9841 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9842 i40e_vsi_open(pf->vsi[i]);
9843 break;
9844 }
9845 }
41c445ff 9846
7e2453fe
JB		 9847 /* driver is only interested in link up/down and module qualification
9848 * reports from firmware
9849 */
9850 err = i40e_aq_set_phy_int_mask(&pf->hw,
9851 I40E_AQ_EVENT_LINK_UPDOWN |
9852 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9853 if (err)
9854 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9855
025b4a54
ASJ		 9856 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
9857 (pf->hw.aq.fw_maj_ver < 4)) {
9858 msleep(75);
9859 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9860 if (err)
9861 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9862 pf->hw.aq.asq_last_status);
cafa2ee6 9863 }
41c445ff
JB		 9864 /* The main driver is (mostly) up and happy. We need to set this state
9865 * before setting up the misc vector or we get a race and the vector
9866 * ends up disabled forever.
9867 */
9868 clear_bit(__I40E_DOWN, &pf->state);
9869
9870 /* In case of MSIX we are going to setup the misc vector right here
9871 * to handle admin queue events etc. In case of legacy and MSI
9872 * the misc functionality and queue processing is combined in
9873 * the same vector and that gets setup at open.
9874 */
9875 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9876 err = i40e_setup_misc_vector(pf);
9877 if (err) {
9878 dev_info(&pdev->dev,
9879 "setup of misc vector failed: %d\n", err);
9880 goto err_vsis;
9881 }
9882 }
9883
df805f62 9884#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9885 /* prep for VF support */
9886 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9887 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9888 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9889 u32 val;
9890
9891 /* disable link interrupts for VFs */
9892 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9893 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9894 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9895 i40e_flush(hw);
4aeec010
MW		 9896
9897 if (pci_num_vf(pdev)) {
9898 dev_info(&pdev->dev,
9899 "Active VFs found, allocating resources.\n");
9900 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9901 if (err)
9902 dev_info(&pdev->dev,
9903 "Error %d allocating resources for existing VFs\n",
9904 err);
9905 }
41c445ff 9906 }
df805f62 9907#endif /* CONFIG_PCI_IOV */
41c445ff 9908
93cd765b
ASJ		 9909 pfs_found++;
9910
41c445ff
JB		 9911 i40e_dbg_pf_init(pf);
9912
9913 /* tell the firmware that we're starting */
44033fac 9914 i40e_send_version(pf);
41c445ff
JB		 9915
9916 /* since everything's happy, start the service_task timer */
9917 mod_timer(&pf->service_timer,
9918 round_jiffies(jiffies + pf->service_timer_period));
9919
38e00438
VD		 9920#ifdef I40E_FCOE
9921 /* create FCoE interface */
9922 i40e_fcoe_vsi_setup(pf);
9923
9924#endif
d4dfb81a
CS		 9925 /* Get the negotiated link width and speed from PCI config space */
9926 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9927
9928 i40e_set_pci_config_data(hw, link_status);
9929
69bfb110 9930 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9931 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9932 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9933 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9934 "Unknown"),
9935 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9936 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9937 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9938 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9939 "Unknown"));
9940
9941 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9942 hw->bus.speed < i40e_bus_speed_8000) {
9943 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9944 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9945 }
9946
e827845c
CS		 9947 /* get the requested speeds from the fw */
9948 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
9949 if (err)
9950 dev_info(&pf->pdev->dev, "get phy abilities failed, aq_err %d, advertised speed settings may not be correct\n",
9951 err);
9952 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
9953
0c22b3dd
JB		 9954 /* print a string summarizing features */
9955 i40e_print_features(pf);
9956
41c445ff
JB		 9957 return 0;
9958
9959 /* Unwind what we've done if something failed in the setup */
9960err_vsis:
9961 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9962 i40e_clear_interrupt_scheme(pf);
9963 kfree(pf->vsi);
04b03013
SN		 9964err_switch_setup:
9965 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9966 del_timer_sync(&pf->service_timer);
9967err_mac_addr:
9968err_configure_lan_hmc:
9969 (void)i40e_shutdown_lan_hmc(hw);
9970err_init_lan_hmc:
9971 kfree(pf->qp_pile);
41c445ff
JB		 9972err_sw_init:
9973err_adminq_setup:
9974 (void)i40e_shutdown_adminq(hw);
9975err_pf_reset:
9976 iounmap(hw->hw_addr);
9977err_ioremap:
9978 kfree(pf);
9979err_pf_alloc:
9980 pci_disable_pcie_error_reporting(pdev);
9981 pci_release_selected_regions(pdev,
9982 pci_select_bars(pdev, IORESOURCE_MEM));
9983err_pci_reg:
9984err_dma:
9985 pci_disable_device(pdev);
9986 return err;
9987}
9988
9989/**
9990 * i40e_remove - Device removal routine
9991 * @pdev: PCI device information struct
9992 *
9993 * i40e_remove is called by the PCI subsystem to alert the driver
9994 * that is should release a PCI device. This could be caused by a
9995 * Hot-Plug event, or because the driver is going to be removed from
9996 * memory.
9997 **/
9998static void i40e_remove(struct pci_dev *pdev)
9999{
10000 struct i40e_pf *pf = pci_get_drvdata(pdev);
10001 i40e_status ret_code;
41c445ff
JB		 10002 int i;
10003
10004 i40e_dbg_pf_exit(pf);
10005
beb0dff1
JK		 10006 i40e_ptp_stop(pf);
10007
41c445ff
JB		 10008 /* no more scheduling of any task */
10009 set_bit(__I40E_DOWN, &pf->state);
10010 del_timer_sync(&pf->service_timer);
10011 cancel_work_sync(&pf->service_task);
33c62b34 10012 i40e_fdir_teardown(pf);
41c445ff 10013
eb2d80bc
MW		 10014 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10015 i40e_free_vfs(pf);
10016 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10017 }
10018
41c445ff
JB		 10019 i40e_fdir_teardown(pf);
10020
10021 /* If there is a switch structure or any orphans, remove them.
10022 * This will leave only the PF's VSI remaining.
10023 */
10024 for (i = 0; i < I40E_MAX_VEB; i++) {
10025 if (!pf->veb[i])
10026 continue;
10027
10028 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10029 pf->veb[i]->uplink_seid == 0)
10030 i40e_switch_branch_release(pf->veb[i]);
10031 }
10032
10033 /* Now we can shutdown the PF's VSI, just before we kill
10034 * adminq and hmc.
10035 */
10036 if (pf->vsi[pf->lan_vsi])
10037 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10038
41c445ff 10039 /* shutdown and destroy the HMC */
60442dea
SN		 10040 if (pf->hw.hmc.hmc_obj) {
10041 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10042 if (ret_code)
10043 dev_warn(&pdev->dev,
10044 "Failed to destroy the HMC resources: %d\n",
10045 ret_code);
10046 }
41c445ff
JB		 10047
10048 /* shutdown the adminq */
41c445ff
JB		 10049 ret_code = i40e_shutdown_adminq(&pf->hw);
10050 if (ret_code)
10051 dev_warn(&pdev->dev,
10052 "Failed to destroy the Admin Queue resources: %d\n",
10053 ret_code);
10054
10055 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10056 i40e_clear_interrupt_scheme(pf);
505682cd 10057 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10058 if (pf->vsi[i]) {
10059 i40e_vsi_clear_rings(pf->vsi[i]);
10060 i40e_vsi_clear(pf->vsi[i]);
10061 pf->vsi[i] = NULL;
10062 }
10063 }
10064
10065 for (i = 0; i < I40E_MAX_VEB; i++) {
10066 kfree(pf->veb[i]);
10067 pf->veb[i] = NULL;
10068 }
10069
10070 kfree(pf->qp_pile);
41c445ff
JB		 10071 kfree(pf->vsi);
10072
41c445ff
JB		 10073 iounmap(pf->hw.hw_addr);
10074 kfree(pf);
10075 pci_release_selected_regions(pdev,
10076 pci_select_bars(pdev, IORESOURCE_MEM));
10077
10078 pci_disable_pcie_error_reporting(pdev);
10079 pci_disable_device(pdev);
10080}
10081
10082/**
10083 * i40e_pci_error_detected - warning that something funky happened in PCI land
10084 * @pdev: PCI device information struct
10085 *
10086 * Called to warn that something happened and the error handling steps
10087 * are in progress. Allows the driver to quiesce things, be ready for
10088 * remediation.
10089 **/
10090static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10091 enum pci_channel_state error)
10092{
10093 struct i40e_pf *pf = pci_get_drvdata(pdev);
10094
10095 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10096
10097 /* shutdown all operations */
9007bccd
SN		 10098 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10099 rtnl_lock();
10100 i40e_prep_for_reset(pf);
10101 rtnl_unlock();
10102 }
41c445ff
JB		 10103
10104 /* Request a slot reset */
10105 return PCI_ERS_RESULT_NEED_RESET;
10106}
10107
10108/**
10109 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10110 * @pdev: PCI device information struct
10111 *
10112 * Called to find if the driver can work with the device now that
10113 * the pci slot has been reset. If a basic connection seems good
10114 * (registers are readable and have sane content) then return a
10115 * happy little PCI_ERS_RESULT_xxx.
10116 **/
10117static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10118{
10119 struct i40e_pf *pf = pci_get_drvdata(pdev);
10120 pci_ers_result_t result;
10121 int err;
10122 u32 reg;
10123
10124 dev_info(&pdev->dev, "%s\n", __func__);
10125 if (pci_enable_device_mem(pdev)) {
10126 dev_info(&pdev->dev,
10127 "Cannot re-enable PCI device after reset.\n");
10128 result = PCI_ERS_RESULT_DISCONNECT;
10129 } else {
10130 pci_set_master(pdev);
10131 pci_restore_state(pdev);
10132 pci_save_state(pdev);
10133 pci_wake_from_d3(pdev, false);
10134
10135 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10136 if (reg == 0)
10137 result = PCI_ERS_RESULT_RECOVERED;
10138 else
10139 result = PCI_ERS_RESULT_DISCONNECT;
10140 }
10141
10142 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10143 if (err) {
10144 dev_info(&pdev->dev,
10145 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10146 err);
10147 /* non-fatal, continue */
10148 }
10149
10150 return result;
10151}
10152
10153/**
10154 * i40e_pci_error_resume - restart operations after PCI error recovery
10155 * @pdev: PCI device information struct
10156 *
10157 * Called to allow the driver to bring things back up after PCI error
10158 * and/or reset recovery has finished.
10159 **/
10160static void i40e_pci_error_resume(struct pci_dev *pdev)
10161{
10162 struct i40e_pf *pf = pci_get_drvdata(pdev);
10163
10164 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10165 if (test_bit(__I40E_SUSPENDED, &pf->state))
10166 return;
10167
10168 rtnl_lock();
41c445ff 10169 i40e_handle_reset_warning(pf);
9007bccd
SN		 10170 rtnl_lock();
10171}
10172
10173/**
10174 * i40e_shutdown - PCI callback for shutting down
10175 * @pdev: PCI device information struct
10176 **/
10177static void i40e_shutdown(struct pci_dev *pdev)
10178{
10179 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10180 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10181
10182 set_bit(__I40E_SUSPENDED, &pf->state);
10183 set_bit(__I40E_DOWN, &pf->state);
10184 rtnl_lock();
10185 i40e_prep_for_reset(pf);
10186 rtnl_unlock();
10187
8e2773ae
SN		 10188 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10189 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10190
e147758d
SN		 10191 i40e_clear_interrupt_scheme(pf);
10192
9007bccd 10193 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10194 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10195 pci_set_power_state(pdev, PCI_D3hot);
10196 }
10197}
10198
10199#ifdef CONFIG_PM
10200/**
10201 * i40e_suspend - PCI callback for moving to D3
10202 * @pdev: PCI device information struct
10203 **/
10204static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10205{
10206 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10207 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10208
10209 set_bit(__I40E_SUSPENDED, &pf->state);
10210 set_bit(__I40E_DOWN, &pf->state);
88086e5d
MW		 10211 del_timer_sync(&pf->service_timer);
10212 cancel_work_sync(&pf->service_task);
9007bccd
SN		 10213 rtnl_lock();
10214 i40e_prep_for_reset(pf);
10215 rtnl_unlock();
10216
8e2773ae
SN		 10217 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10218 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10219
10220 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10221 pci_set_power_state(pdev, PCI_D3hot);
10222
10223 return 0;
41c445ff
JB		 10224}
10225
9007bccd
SN		 10226/**
10227 * i40e_resume - PCI callback for waking up from D3
10228 * @pdev: PCI device information struct
10229 **/
10230static int i40e_resume(struct pci_dev *pdev)
10231{
10232 struct i40e_pf *pf = pci_get_drvdata(pdev);
10233 u32 err;
10234
10235 pci_set_power_state(pdev, PCI_D0);
10236 pci_restore_state(pdev);
10237 /* pci_restore_state() clears dev->state_saves, so
10238 * call pci_save_state() again to restore it.
10239 */
10240 pci_save_state(pdev);
10241
10242 err = pci_enable_device_mem(pdev);
10243 if (err) {
10244 dev_err(&pdev->dev,
10245 "%s: Cannot enable PCI device from suspend\n",
10246 __func__);
10247 return err;
10248 }
10249 pci_set_master(pdev);
10250
10251 /* no wakeup events while running */
10252 pci_wake_from_d3(pdev, false);
10253
10254 /* handling the reset will rebuild the device state */
10255 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10256 clear_bit(__I40E_DOWN, &pf->state);
10257 rtnl_lock();
10258 i40e_reset_and_rebuild(pf, false);
10259 rtnl_unlock();
10260 }
10261
10262 return 0;
10263}
10264
10265#endif
41c445ff
JB		 10266static const struct pci_error_handlers i40e_err_handler = {
10267 .error_detected = i40e_pci_error_detected,
10268 .slot_reset = i40e_pci_error_slot_reset,
10269 .resume = i40e_pci_error_resume,
10270};
10271
10272static struct pci_driver i40e_driver = {
10273 .name = i40e_driver_name,
10274 .id_table = i40e_pci_tbl,
10275 .probe = i40e_probe,
10276 .remove = i40e_remove,
9007bccd
SN		 10277#ifdef CONFIG_PM
10278 .suspend = i40e_suspend,
10279 .resume = i40e_resume,
10280#endif
10281 .shutdown = i40e_shutdown,
41c445ff
JB		 10282 .err_handler = &i40e_err_handler,
10283 .sriov_configure = i40e_pci_sriov_configure,
10284};
10285
10286/**
10287 * i40e_init_module - Driver registration routine
10288 *
10289 * i40e_init_module is the first routine called when the driver is
10290 * loaded. All it does is register with the PCI subsystem.
10291 **/
10292static int __init i40e_init_module(void)
10293{
10294 pr_info("%s: %s - version %s\n", i40e_driver_name,
10295 i40e_driver_string, i40e_driver_version_str);
10296 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10297
41c445ff
JB		 10298 i40e_dbg_init();
10299 return pci_register_driver(&i40e_driver);
10300}
10301module_init(i40e_init_module);
10302
10303/**
10304 * i40e_exit_module - Driver exit cleanup routine
10305 *
10306 * i40e_exit_module is called just before the driver is removed
10307 * from memory.
10308 **/
10309static void __exit i40e_exit_module(void)
10310{
10311 pci_unregister_driver(&i40e_driver);
10312 i40e_dbg_exit();
10313}
10314module_exit(i40e_exit_module);
Linux kernel - Deliverables
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