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i40e: count drops in netstat interface
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
42d255ce 41#define DRV_VERSION_MINOR 3
f91638af 42#define DRV_VERSION_BUILD 21
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
ae24b409 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
41c445ff
JB		 82 /* required last entry */
83 {0, }
84};
85MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
86
87#define I40E_MAX_VF_COUNT 128
88static int debug = -1;
89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
92MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
93MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
94MODULE_LICENSE("GPL");
95MODULE_VERSION(DRV_VERSION);
96
97/**
98 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
99 * @hw: pointer to the HW structure
100 * @mem: ptr to mem struct to fill out
101 * @size: size of memory requested
102 * @alignment: what to align the allocation to
103 **/
104int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
105 u64 size, u32 alignment)
106{
107 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
108
109 mem->size = ALIGN(size, alignment);
110 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
111 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 112 if (!mem->va)
113 return -ENOMEM;
41c445ff 114
93bc73b8 115 return 0;
41c445ff
JB		 116}
117
118/**
119 * i40e_free_dma_mem_d - OS specific memory free for shared code
120 * @hw: pointer to the HW structure
121 * @mem: ptr to mem struct to free
122 **/
123int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
124{
125 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
126
127 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
128 mem->va = NULL;
129 mem->pa = 0;
130 mem->size = 0;
131
132 return 0;
133}
134
135/**
136 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
137 * @hw: pointer to the HW structure
138 * @mem: ptr to mem struct to fill out
139 * @size: size of memory requested
140 **/
141int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
142 u32 size)
143{
144 mem->size = size;
145 mem->va = kzalloc(size, GFP_KERNEL);
146
93bc73b8
JB		 147 if (!mem->va)
148 return -ENOMEM;
41c445ff 149
93bc73b8 150 return 0;
41c445ff
JB		 151}
152
153/**
154 * i40e_free_virt_mem_d - OS specific memory free for shared code
155 * @hw: pointer to the HW structure
156 * @mem: ptr to mem struct to free
157 **/
158int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
159{
160 /* it's ok to kfree a NULL pointer */
161 kfree(mem->va);
162 mem->va = NULL;
163 mem->size = 0;
164
165 return 0;
166}
167
168/**
169 * i40e_get_lump - find a lump of free generic resource
170 * @pf: board private structure
171 * @pile: the pile of resource to search
172 * @needed: the number of items needed
173 * @id: an owner id to stick on the items assigned
174 *
175 * Returns the base item index of the lump, or negative for error
176 *
177 * The search_hint trick and lack of advanced fit-finding only work
178 * because we're highly likely to have all the same size lump requests.
179 * Linear search time and any fragmentation should be minimal.
180 **/
181static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
182 u16 needed, u16 id)
183{
184 int ret = -ENOMEM;
ddf434ac 185 int i, j;
41c445ff
JB		 186
187 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
188 dev_info(&pf->pdev->dev,
189 "param err: pile=%p needed=%d id=0x%04x\n",
190 pile, needed, id);
191 return -EINVAL;
192 }
193
194 /* start the linear search with an imperfect hint */
195 i = pile->search_hint;
ddf434ac 196 while (i < pile->num_entries) {
41c445ff
JB		 197 /* skip already allocated entries */
198 if (pile->list[i] & I40E_PILE_VALID_BIT) {
199 i++;
200 continue;
201 }
202
203 /* do we have enough in this lump? */
204 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
205 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
206 break;
207 }
208
209 if (j == needed) {
210 /* there was enough, so assign it to the requestor */
211 for (j = 0; j < needed; j++)
212 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
213 ret = i;
214 pile->search_hint = i + j;
ddf434ac 215 break;
41c445ff
JB		 216 } else {
217 /* not enough, so skip over it and continue looking */
218 i += j;
219 }
220 }
221
222 return ret;
223}
224
225/**
226 * i40e_put_lump - return a lump of generic resource
227 * @pile: the pile of resource to search
228 * @index: the base item index
229 * @id: the owner id of the items assigned
230 *
231 * Returns the count of items in the lump
232 **/
233static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
234{
235 int valid_id = (id | I40E_PILE_VALID_BIT);
236 int count = 0;
237 int i;
238
239 if (!pile || index >= pile->num_entries)
240 return -EINVAL;
241
242 for (i = index;
243 i < pile->num_entries && pile->list[i] == valid_id;
244 i++) {
245 pile->list[i] = 0;
246 count++;
247 }
248
249 if (count && index < pile->search_hint)
250 pile->search_hint = index;
251
252 return count;
253}
254
fdf0e0bf
ASJ		 255/**
256 * i40e_find_vsi_from_id - searches for the vsi with the given id
257 * @pf - the pf structure to search for the vsi
258 * @id - id of the vsi it is searching for
259 **/
260struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
261{
262 int i;
263
264 for (i = 0; i < pf->num_alloc_vsi; i++)
265 if (pf->vsi[i] && (pf->vsi[i]->id == id))
266 return pf->vsi[i];
267
268 return NULL;
269}
270
41c445ff
JB		 271/**
272 * i40e_service_event_schedule - Schedule the service task to wake up
273 * @pf: board private structure
274 *
275 * If not already scheduled, this puts the task into the work queue
276 **/
277static void i40e_service_event_schedule(struct i40e_pf *pf)
278{
279 if (!test_bit(__I40E_DOWN, &pf->state) &&
280 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
281 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
282 schedule_work(&pf->service_task);
283}
284
285/**
286 * i40e_tx_timeout - Respond to a Tx Hang
287 * @netdev: network interface device structure
288 *
289 * If any port has noticed a Tx timeout, it is likely that the whole
290 * device is munged, not just the one netdev port, so go for the full
291 * reset.
292 **/
38e00438
VD		 293#ifdef I40E_FCOE
294void i40e_tx_timeout(struct net_device *netdev)
295#else
41c445ff 296static void i40e_tx_timeout(struct net_device *netdev)
38e00438 297#endif
41c445ff
JB		 298{
299 struct i40e_netdev_priv *np = netdev_priv(netdev);
300 struct i40e_vsi *vsi = np->vsi;
301 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 302 struct i40e_ring *tx_ring = NULL;
303 unsigned int i, hung_queue = 0;
304 u32 head, val;
41c445ff
JB		 305
306 pf->tx_timeout_count++;
307
b03a8c1f
KP		 308 /* find the stopped queue the same way the stack does */
309 for (i = 0; i < netdev->num_tx_queues; i++) {
310 struct netdev_queue *q;
311 unsigned long trans_start;
312
313 q = netdev_get_tx_queue(netdev, i);
314 trans_start = q->trans_start ? : netdev->trans_start;
315 if (netif_xmit_stopped(q) &&
316 time_after(jiffies,
317 (trans_start + netdev->watchdog_timeo))) {
318 hung_queue = i;
319 break;
320 }
321 }
322
323 if (i == netdev->num_tx_queues) {
324 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
325 } else {
326 /* now that we have an index, find the tx_ring struct */
327 for (i = 0; i < vsi->num_queue_pairs; i++) {
328 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
329 if (hung_queue ==
330 vsi->tx_rings[i]->queue_index) {
331 tx_ring = vsi->tx_rings[i];
332 break;
333 }
334 }
335 }
336 }
337
41c445ff 338 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 339 pf->tx_timeout_recovery_level = 1; /* reset after some time */
340 else if (time_before(jiffies,
341 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
342 return; /* don't do any new action before the next timeout */
343
344 if (tx_ring) {
345 head = i40e_get_head(tx_ring);
346 /* Read interrupt register */
347 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
348 val = rd32(&pf->hw,
349 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
350 tx_ring->vsi->base_vector - 1));
351 else
352 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
353
354 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
355 vsi->seid, hung_queue, tx_ring->next_to_clean,
356 head, tx_ring->next_to_use,
357 readl(tx_ring->tail), val);
358 }
359
41c445ff 360 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 361 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
362 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 363
364 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 365 case 1:
366 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
367 break;
368 case 2:
369 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
370 break;
371 case 3:
372 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
373 break;
374 default:
375 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 376 break;
377 }
b03a8c1f 378
41c445ff
JB		 379 i40e_service_event_schedule(pf);
380 pf->tx_timeout_recovery_level++;
381}
382
383/**
384 * i40e_release_rx_desc - Store the new tail and head values
385 * @rx_ring: ring to bump
386 * @val: new head index
387 **/
388static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
389{
390 rx_ring->next_to_use = val;
391
392 /* Force memory writes to complete before letting h/w
393 * know there are new descriptors to fetch. (Only
394 * applicable for weak-ordered memory model archs,
395 * such as IA-64).
396 */
397 wmb();
398 writel(val, rx_ring->tail);
399}
400
401/**
402 * i40e_get_vsi_stats_struct - Get System Network Statistics
403 * @vsi: the VSI we care about
404 *
405 * Returns the address of the device statistics structure.
406 * The statistics are actually updated from the service task.
407 **/
408struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
409{
410 return &vsi->net_stats;
411}
412
413/**
414 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
415 * @netdev: network interface device structure
416 *
417 * Returns the address of the device statistics structure.
418 * The statistics are actually updated from the service task.
419 **/
38e00438
VD		 420#ifdef I40E_FCOE
421struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
422 struct net_device *netdev,
423 struct rtnl_link_stats64 *stats)
424#else
41c445ff
JB		 425static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
426 struct net_device *netdev,
980e9b11 427 struct rtnl_link_stats64 *stats)
38e00438 428#endif
41c445ff
JB		 429{
430 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 431 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 432 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 433 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
434 int i;
435
bc7d338f
ASJ		 436 if (test_bit(__I40E_DOWN, &vsi->state))
437 return stats;
438
3c325ced
JB		 439 if (!vsi->tx_rings)
440 return stats;
441
980e9b11
AD		 442 rcu_read_lock();
443 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 444 u64 bytes, packets;
445 unsigned int start;
446
447 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
448 if (!tx_ring)
449 continue;
450
451 do {
57a7744e 452 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 453 packets = tx_ring->stats.packets;
454 bytes = tx_ring->stats.bytes;
57a7744e 455 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 456
457 stats->tx_packets += packets;
458 stats->tx_bytes += bytes;
459 rx_ring = &tx_ring[1];
460
461 do {
57a7744e 462 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 463 packets = rx_ring->stats.packets;
464 bytes = rx_ring->stats.bytes;
57a7744e 465 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 466
980e9b11
AD		 467 stats->rx_packets += packets;
468 stats->rx_bytes += bytes;
469 }
470 rcu_read_unlock();
471
a5282f44 472 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 473 stats->multicast = vsi_stats->multicast;
474 stats->tx_errors = vsi_stats->tx_errors;
475 stats->tx_dropped = vsi_stats->tx_dropped;
476 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 477 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 478 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
479 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 480
980e9b11 481 return stats;
41c445ff
JB		 482}
483
484/**
485 * i40e_vsi_reset_stats - Resets all stats of the given vsi
486 * @vsi: the VSI to have its stats reset
487 **/
488void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
489{
490 struct rtnl_link_stats64 *ns;
491 int i;
492
493 if (!vsi)
494 return;
495
496 ns = i40e_get_vsi_stats_struct(vsi);
497 memset(ns, 0, sizeof(*ns));
498 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
499 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
500 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 501 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 502 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 503 memset(&vsi->rx_rings[i]->stats, 0 ,
504 sizeof(vsi->rx_rings[i]->stats));
505 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
506 sizeof(vsi->rx_rings[i]->rx_stats));
507 memset(&vsi->tx_rings[i]->stats, 0 ,
508 sizeof(vsi->tx_rings[i]->stats));
509 memset(&vsi->tx_rings[i]->tx_stats, 0,
510 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 511 }
8e9dca53 512 }
41c445ff
JB		 513 vsi->stat_offsets_loaded = false;
514}
515
516/**
b40c82e6 517 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 518 * @pf: the PF to be reset
519 **/
520void i40e_pf_reset_stats(struct i40e_pf *pf)
521{
e91fdf76
SN		 522 int i;
523
41c445ff
JB		 524 memset(&pf->stats, 0, sizeof(pf->stats));
525 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
526 pf->stat_offsets_loaded = false;
e91fdf76
SN		 527
528 for (i = 0; i < I40E_MAX_VEB; i++) {
529 if (pf->veb[i]) {
530 memset(&pf->veb[i]->stats, 0,
531 sizeof(pf->veb[i]->stats));
532 memset(&pf->veb[i]->stats_offsets, 0,
533 sizeof(pf->veb[i]->stats_offsets));
534 pf->veb[i]->stat_offsets_loaded = false;
535 }
536 }
41c445ff
JB		 537}
538
539/**
540 * i40e_stat_update48 - read and update a 48 bit stat from the chip
541 * @hw: ptr to the hardware info
542 * @hireg: the high 32 bit reg to read
543 * @loreg: the low 32 bit reg to read
544 * @offset_loaded: has the initial offset been loaded yet
545 * @offset: ptr to current offset value
546 * @stat: ptr to the stat
547 *
548 * Since the device stats are not reset at PFReset, they likely will not
549 * be zeroed when the driver starts. We'll save the first values read
550 * and use them as offsets to be subtracted from the raw values in order
551 * to report stats that count from zero. In the process, we also manage
552 * the potential roll-over.
553 **/
554static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
555 bool offset_loaded, u64 *offset, u64 *stat)
556{
557 u64 new_data;
558
ab60085e 559 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 560 new_data = rd32(hw, loreg);
561 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
562 } else {
563 new_data = rd64(hw, loreg);
564 }
565 if (!offset_loaded)
566 *offset = new_data;
567 if (likely(new_data >= *offset))
568 *stat = new_data - *offset;
569 else
41a1d04b 570 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 571 *stat &= 0xFFFFFFFFFFFFULL;
572}
573
574/**
575 * i40e_stat_update32 - read and update a 32 bit stat from the chip
576 * @hw: ptr to the hardware info
577 * @reg: the hw reg to read
578 * @offset_loaded: has the initial offset been loaded yet
579 * @offset: ptr to current offset value
580 * @stat: ptr to the stat
581 **/
582static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
583 bool offset_loaded, u64 *offset, u64 *stat)
584{
585 u32 new_data;
586
587 new_data = rd32(hw, reg);
588 if (!offset_loaded)
589 *offset = new_data;
590 if (likely(new_data >= *offset))
591 *stat = (u32)(new_data - *offset);
592 else
41a1d04b 593 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 594}
595
596/**
597 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
598 * @vsi: the VSI to be updated
599 **/
600void i40e_update_eth_stats(struct i40e_vsi *vsi)
601{
602 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
603 struct i40e_pf *pf = vsi->back;
604 struct i40e_hw *hw = &pf->hw;
605 struct i40e_eth_stats *oes;
606 struct i40e_eth_stats *es; /* device's eth stats */
607
608 es = &vsi->eth_stats;
609 oes = &vsi->eth_stats_offsets;
610
611 /* Gather up the stats that the hw collects */
612 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
613 vsi->stat_offsets_loaded,
614 &oes->tx_errors, &es->tx_errors);
615 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
616 vsi->stat_offsets_loaded,
617 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 618 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
619 vsi->stat_offsets_loaded,
620 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
621 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
622 vsi->stat_offsets_loaded,
623 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 624
625 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
626 I40E_GLV_GORCL(stat_idx),
627 vsi->stat_offsets_loaded,
628 &oes->rx_bytes, &es->rx_bytes);
629 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
630 I40E_GLV_UPRCL(stat_idx),
631 vsi->stat_offsets_loaded,
632 &oes->rx_unicast, &es->rx_unicast);
633 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
634 I40E_GLV_MPRCL(stat_idx),
635 vsi->stat_offsets_loaded,
636 &oes->rx_multicast, &es->rx_multicast);
637 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
638 I40E_GLV_BPRCL(stat_idx),
639 vsi->stat_offsets_loaded,
640 &oes->rx_broadcast, &es->rx_broadcast);
641
642 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
643 I40E_GLV_GOTCL(stat_idx),
644 vsi->stat_offsets_loaded,
645 &oes->tx_bytes, &es->tx_bytes);
646 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
647 I40E_GLV_UPTCL(stat_idx),
648 vsi->stat_offsets_loaded,
649 &oes->tx_unicast, &es->tx_unicast);
650 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
651 I40E_GLV_MPTCL(stat_idx),
652 vsi->stat_offsets_loaded,
653 &oes->tx_multicast, &es->tx_multicast);
654 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
655 I40E_GLV_BPTCL(stat_idx),
656 vsi->stat_offsets_loaded,
657 &oes->tx_broadcast, &es->tx_broadcast);
658 vsi->stat_offsets_loaded = true;
659}
660
661/**
662 * i40e_update_veb_stats - Update Switch component statistics
663 * @veb: the VEB being updated
664 **/
665static void i40e_update_veb_stats(struct i40e_veb *veb)
666{
667 struct i40e_pf *pf = veb->pf;
668 struct i40e_hw *hw = &pf->hw;
669 struct i40e_eth_stats *oes;
670 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 671 struct i40e_veb_tc_stats *veb_oes;
672 struct i40e_veb_tc_stats *veb_es;
673 int i, idx = 0;
41c445ff
JB		 674
675 idx = veb->stats_idx;
676 es = &veb->stats;
677 oes = &veb->stats_offsets;
fe860afb
NP		 678 veb_es = &veb->tc_stats;
679 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 680
681 /* Gather up the stats that the hw collects */
682 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
683 veb->stat_offsets_loaded,
684 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 685 if (hw->revision_id > 0)
686 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
687 veb->stat_offsets_loaded,
688 &oes->rx_unknown_protocol,
689 &es->rx_unknown_protocol);
41c445ff
JB		 690 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
691 veb->stat_offsets_loaded,
692 &oes->rx_bytes, &es->rx_bytes);
693 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
694 veb->stat_offsets_loaded,
695 &oes->rx_unicast, &es->rx_unicast);
696 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
697 veb->stat_offsets_loaded,
698 &oes->rx_multicast, &es->rx_multicast);
699 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
700 veb->stat_offsets_loaded,
701 &oes->rx_broadcast, &es->rx_broadcast);
702
703 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
704 veb->stat_offsets_loaded,
705 &oes->tx_bytes, &es->tx_bytes);
706 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_unicast, &es->tx_unicast);
709 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
710 veb->stat_offsets_loaded,
711 &oes->tx_multicast, &es->tx_multicast);
712 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
713 veb->stat_offsets_loaded,
714 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 715 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
716 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
717 I40E_GLVEBTC_RPCL(i, idx),
718 veb->stat_offsets_loaded,
719 &veb_oes->tc_rx_packets[i],
720 &veb_es->tc_rx_packets[i]);
721 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
722 I40E_GLVEBTC_RBCL(i, idx),
723 veb->stat_offsets_loaded,
724 &veb_oes->tc_rx_bytes[i],
725 &veb_es->tc_rx_bytes[i]);
726 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
727 I40E_GLVEBTC_TPCL(i, idx),
728 veb->stat_offsets_loaded,
729 &veb_oes->tc_tx_packets[i],
730 &veb_es->tc_tx_packets[i]);
731 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
732 I40E_GLVEBTC_TBCL(i, idx),
733 veb->stat_offsets_loaded,
734 &veb_oes->tc_tx_bytes[i],
735 &veb_es->tc_tx_bytes[i]);
736 }
41c445ff
JB		 737 veb->stat_offsets_loaded = true;
738}
739
38e00438
VD		 740#ifdef I40E_FCOE
741/**
742 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
743 * @vsi: the VSI that is capable of doing FCoE
744 **/
745static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
746{
747 struct i40e_pf *pf = vsi->back;
748 struct i40e_hw *hw = &pf->hw;
749 struct i40e_fcoe_stats *ofs;
750 struct i40e_fcoe_stats *fs; /* device's eth stats */
751 int idx;
752
753 if (vsi->type != I40E_VSI_FCOE)
754 return;
755
756 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
757 fs = &vsi->fcoe_stats;
758 ofs = &vsi->fcoe_stats_offsets;
759
760 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
761 vsi->fcoe_stat_offsets_loaded,
762 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
763 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
764 vsi->fcoe_stat_offsets_loaded,
765 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
766 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
767 vsi->fcoe_stat_offsets_loaded,
768 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
769 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
770 vsi->fcoe_stat_offsets_loaded,
771 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
772 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
773 vsi->fcoe_stat_offsets_loaded,
774 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
775 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
778 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
779 vsi->fcoe_stat_offsets_loaded,
780 &ofs->fcoe_last_error, &fs->fcoe_last_error);
781 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
782 vsi->fcoe_stat_offsets_loaded,
783 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
784
785 vsi->fcoe_stat_offsets_loaded = true;
786}
787
788#endif
41c445ff
JB		 789/**
790 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
791 * @pf: the corresponding PF
792 *
793 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
794 **/
795static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
796{
797 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
798 struct i40e_hw_port_stats *nsd = &pf->stats;
799 struct i40e_hw *hw = &pf->hw;
800 u64 xoff = 0;
41c445ff
JB		 801
802 if ((hw->fc.current_mode != I40E_FC_FULL) &&
803 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
804 return;
805
806 xoff = nsd->link_xoff_rx;
807 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
808 pf->stat_offsets_loaded,
809 &osd->link_xoff_rx, &nsd->link_xoff_rx);
810
811 /* No new LFC xoff rx */
812 if (!(nsd->link_xoff_rx - xoff))
813 return;
814
41c445ff
JB		 815}
816
817/**
818 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
819 * @pf: the corresponding PF
820 *
821 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
822 **/
823static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
824{
825 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
826 struct i40e_hw_port_stats *nsd = &pf->stats;
827 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
828 struct i40e_dcbx_config *dcb_cfg;
829 struct i40e_hw *hw = &pf->hw;
b03a8c1f 830 u16 i;
41c445ff
JB		 831 u8 tc;
832
833 dcb_cfg = &hw->local_dcbx_config;
834
e120814d
NP		 835 /* Collect Link XOFF stats when PFC is disabled */
836 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 837 i40e_update_link_xoff_rx(pf);
838 return;
839 }
840
841 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
842 u64 prio_xoff = nsd->priority_xoff_rx[i];
843 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
844 pf->stat_offsets_loaded,
845 &osd->priority_xoff_rx[i],
846 &nsd->priority_xoff_rx[i]);
847
848 /* No new PFC xoff rx */
849 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
850 continue;
851 /* Get the TC for given priority */
852 tc = dcb_cfg->etscfg.prioritytable[i];
853 xoff[tc] = true;
854 }
41c445ff
JB		 855}
856
857/**
7812fddc 858 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 859 * @vsi: the VSI to be updated
860 *
861 * There are a few instances where we store the same stat in a
862 * couple of different structs. This is partly because we have
863 * the netdev stats that need to be filled out, which is slightly
864 * different from the "eth_stats" defined by the chip and used in
7812fddc 865 * VF communications. We sort it out here.
41c445ff 866 **/
7812fddc 867static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 868{
869 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 870 struct rtnl_link_stats64 *ons;
871 struct rtnl_link_stats64 *ns; /* netdev stats */
872 struct i40e_eth_stats *oes;
873 struct i40e_eth_stats *es; /* device's eth stats */
874 u32 tx_restart, tx_busy;
bf00b376 875 struct i40e_ring *p;
41c445ff 876 u32 rx_page, rx_buf;
bf00b376
AA		 877 u64 bytes, packets;
878 unsigned int start;
41c445ff
JB		 879 u64 rx_p, rx_b;
880 u64 tx_p, tx_b;
41c445ff
JB		 881 u16 q;
882
883 if (test_bit(__I40E_DOWN, &vsi->state) ||
884 test_bit(__I40E_CONFIG_BUSY, &pf->state))
885 return;
886
887 ns = i40e_get_vsi_stats_struct(vsi);
888 ons = &vsi->net_stats_offsets;
889 es = &vsi->eth_stats;
890 oes = &vsi->eth_stats_offsets;
891
892 /* Gather up the netdev and vsi stats that the driver collects
893 * on the fly during packet processing
894 */
895 rx_b = rx_p = 0;
896 tx_b = tx_p = 0;
897 tx_restart = tx_busy = 0;
898 rx_page = 0;
899 rx_buf = 0;
980e9b11 900 rcu_read_lock();
41c445ff 901 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 902 /* locate Tx ring */
903 p = ACCESS_ONCE(vsi->tx_rings[q]);
904
905 do {
57a7744e 906 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 907 packets = p->stats.packets;
908 bytes = p->stats.bytes;
57a7744e 909 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 910 tx_b += bytes;
911 tx_p += packets;
912 tx_restart += p->tx_stats.restart_queue;
913 tx_busy += p->tx_stats.tx_busy;
41c445ff 914
980e9b11
AD		 915 /* Rx queue is part of the same block as Tx queue */
916 p = &p[1];
917 do {
57a7744e 918 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 919 packets = p->stats.packets;
920 bytes = p->stats.bytes;
57a7744e 921 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 922 rx_b += bytes;
923 rx_p += packets;
420136cc
MW		 924 rx_buf += p->rx_stats.alloc_buff_failed;
925 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 926 }
980e9b11 927 rcu_read_unlock();
41c445ff
JB		 928 vsi->tx_restart = tx_restart;
929 vsi->tx_busy = tx_busy;
930 vsi->rx_page_failed = rx_page;
931 vsi->rx_buf_failed = rx_buf;
932
933 ns->rx_packets = rx_p;
934 ns->rx_bytes = rx_b;
935 ns->tx_packets = tx_p;
936 ns->tx_bytes = tx_b;
937
41c445ff 938 /* update netdev stats from eth stats */
7812fddc 939 i40e_update_eth_stats(vsi);
41c445ff
JB		 940 ons->tx_errors = oes->tx_errors;
941 ns->tx_errors = es->tx_errors;
942 ons->multicast = oes->rx_multicast;
943 ns->multicast = es->rx_multicast;
41a9e55c
SN		 944 ons->rx_dropped = oes->rx_discards;
945 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 946 ons->tx_dropped = oes->tx_discards;
947 ns->tx_dropped = es->tx_discards;
948
7812fddc 949 /* pull in a couple PF stats if this is the main vsi */
41c445ff 950 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 951 ns->rx_crc_errors = pf->stats.crc_errors;
952 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
953 ns->rx_length_errors = pf->stats.rx_length_errors;
954 }
955}
41c445ff 956
7812fddc 957/**
b40c82e6 958 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 959 * @pf: the PF to be updated
960 **/
961static void i40e_update_pf_stats(struct i40e_pf *pf)
962{
963 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
964 struct i40e_hw_port_stats *nsd = &pf->stats;
965 struct i40e_hw *hw = &pf->hw;
966 u32 val;
967 int i;
41c445ff 968
7812fddc
SN		 969 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
970 I40E_GLPRT_GORCL(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
973 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
974 I40E_GLPRT_GOTCL(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
977 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->eth.rx_discards,
980 &nsd->eth.rx_discards);
532d283d
SN		 981 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
982 I40E_GLPRT_UPRCL(hw->port),
983 pf->stat_offsets_loaded,
984 &osd->eth.rx_unicast,
985 &nsd->eth.rx_unicast);
7812fddc
SN		 986 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
987 I40E_GLPRT_MPRCL(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->eth.rx_multicast,
990 &nsd->eth.rx_multicast);
532d283d
SN		 991 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
992 I40E_GLPRT_BPRCL(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->eth.rx_broadcast,
995 &nsd->eth.rx_broadcast);
996 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
997 I40E_GLPRT_UPTCL(hw->port),
998 pf->stat_offsets_loaded,
999 &osd->eth.tx_unicast,
1000 &nsd->eth.tx_unicast);
1001 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
1002 I40E_GLPRT_MPTCL(hw->port),
1003 pf->stat_offsets_loaded,
1004 &osd->eth.tx_multicast,
1005 &nsd->eth.tx_multicast);
1006 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
1007 I40E_GLPRT_BPTCL(hw->port),
1008 pf->stat_offsets_loaded,
1009 &osd->eth.tx_broadcast,
1010 &nsd->eth.tx_broadcast);
41c445ff 1011
7812fddc
SN		 1012 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->tx_dropped_link_down,
1015 &nsd->tx_dropped_link_down);
41c445ff 1016
7812fddc
SN		 1017 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->crc_errors, &nsd->crc_errors);
41c445ff 1020
7812fddc
SN		 1021 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 1024
7812fddc
SN		 1025 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->mac_local_faults,
1028 &nsd->mac_local_faults);
1029 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->mac_remote_faults,
1032 &nsd->mac_remote_faults);
41c445ff 1033
7812fddc
SN		 1034 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
1035 pf->stat_offsets_loaded,
1036 &osd->rx_length_errors,
1037 &nsd->rx_length_errors);
41c445ff 1038
7812fddc
SN		 1039 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1040 pf->stat_offsets_loaded,
1041 &osd->link_xon_rx, &nsd->link_xon_rx);
1042 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1043 pf->stat_offsets_loaded,
1044 &osd->link_xon_tx, &nsd->link_xon_tx);
1045 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1046 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1049
7812fddc
SN		 1050 for (i = 0; i < 8; i++) {
1051 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1052 pf->stat_offsets_loaded,
7812fddc
SN		 1053 &osd->priority_xon_rx[i],
1054 &nsd->priority_xon_rx[i]);
1055 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1056 pf->stat_offsets_loaded,
7812fddc
SN		 1057 &osd->priority_xon_tx[i],
1058 &nsd->priority_xon_tx[i]);
1059 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1060 pf->stat_offsets_loaded,
7812fddc
SN		 1061 &osd->priority_xoff_tx[i],
1062 &nsd->priority_xoff_tx[i]);
1063 i40e_stat_update32(hw,
1064 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1065 pf->stat_offsets_loaded,
7812fddc
SN		 1066 &osd->priority_xon_2_xoff[i],
1067 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1068 }
1069
7812fddc
SN		 1070 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1071 I40E_GLPRT_PRC64L(hw->port),
1072 pf->stat_offsets_loaded,
1073 &osd->rx_size_64, &nsd->rx_size_64);
1074 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1075 I40E_GLPRT_PRC127L(hw->port),
1076 pf->stat_offsets_loaded,
1077 &osd->rx_size_127, &nsd->rx_size_127);
1078 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1079 I40E_GLPRT_PRC255L(hw->port),
1080 pf->stat_offsets_loaded,
1081 &osd->rx_size_255, &nsd->rx_size_255);
1082 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1083 I40E_GLPRT_PRC511L(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_size_511, &nsd->rx_size_511);
1086 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1087 I40E_GLPRT_PRC1023L(hw->port),
1088 pf->stat_offsets_loaded,
1089 &osd->rx_size_1023, &nsd->rx_size_1023);
1090 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1091 I40E_GLPRT_PRC1522L(hw->port),
1092 pf->stat_offsets_loaded,
1093 &osd->rx_size_1522, &nsd->rx_size_1522);
1094 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1095 I40E_GLPRT_PRC9522L(hw->port),
1096 pf->stat_offsets_loaded,
1097 &osd->rx_size_big, &nsd->rx_size_big);
1098
1099 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1100 I40E_GLPRT_PTC64L(hw->port),
1101 pf->stat_offsets_loaded,
1102 &osd->tx_size_64, &nsd->tx_size_64);
1103 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1104 I40E_GLPRT_PTC127L(hw->port),
1105 pf->stat_offsets_loaded,
1106 &osd->tx_size_127, &nsd->tx_size_127);
1107 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1108 I40E_GLPRT_PTC255L(hw->port),
1109 pf->stat_offsets_loaded,
1110 &osd->tx_size_255, &nsd->tx_size_255);
1111 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1112 I40E_GLPRT_PTC511L(hw->port),
1113 pf->stat_offsets_loaded,
1114 &osd->tx_size_511, &nsd->tx_size_511);
1115 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1116 I40E_GLPRT_PTC1023L(hw->port),
1117 pf->stat_offsets_loaded,
1118 &osd->tx_size_1023, &nsd->tx_size_1023);
1119 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1120 I40E_GLPRT_PTC1522L(hw->port),
1121 pf->stat_offsets_loaded,
1122 &osd->tx_size_1522, &nsd->tx_size_1522);
1123 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1124 I40E_GLPRT_PTC9522L(hw->port),
1125 pf->stat_offsets_loaded,
1126 &osd->tx_size_big, &nsd->tx_size_big);
1127
1128 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1129 pf->stat_offsets_loaded,
1130 &osd->rx_undersize, &nsd->rx_undersize);
1131 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1132 pf->stat_offsets_loaded,
1133 &osd->rx_fragments, &nsd->rx_fragments);
1134 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1135 pf->stat_offsets_loaded,
1136 &osd->rx_oversize, &nsd->rx_oversize);
1137 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1138 pf->stat_offsets_loaded,
1139 &osd->rx_jabber, &nsd->rx_jabber);
1140
433c47de 1141 /* FDIR stats */
0bf4b1b0
ASJ		 1142 i40e_stat_update32(hw,
1143 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1144 pf->stat_offsets_loaded,
1145 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1146 i40e_stat_update32(hw,
1147 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1148 pf->stat_offsets_loaded,
1149 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1150 i40e_stat_update32(hw,
1151 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1152 pf->stat_offsets_loaded,
1153 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1154
7812fddc
SN		 1155 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1156 nsd->tx_lpi_status =
1157 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1158 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1159 nsd->rx_lpi_status =
1160 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1161 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1162 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1163 pf->stat_offsets_loaded,
1164 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1165 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1166 pf->stat_offsets_loaded,
1167 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1168
d0389e51
ASJ		 1169 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1170 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1171 nsd->fd_sb_status = true;
1172 else
1173 nsd->fd_sb_status = false;
1174
1175 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1176 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1177 nsd->fd_atr_status = true;
1178 else
1179 nsd->fd_atr_status = false;
1180
41c445ff
JB		 1181 pf->stat_offsets_loaded = true;
1182}
1183
7812fddc
SN		 1184/**
1185 * i40e_update_stats - Update the various statistics counters.
1186 * @vsi: the VSI to be updated
1187 *
1188 * Update the various stats for this VSI and its related entities.
1189 **/
1190void i40e_update_stats(struct i40e_vsi *vsi)
1191{
1192 struct i40e_pf *pf = vsi->back;
1193
1194 if (vsi == pf->vsi[pf->lan_vsi])
1195 i40e_update_pf_stats(pf);
1196
1197 i40e_update_vsi_stats(vsi);
38e00438
VD		 1198#ifdef I40E_FCOE
1199 i40e_update_fcoe_stats(vsi);
1200#endif
7812fddc
SN		 1201}
1202
41c445ff
JB		 1203/**
1204 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1205 * @vsi: the VSI to be searched
1206 * @macaddr: the MAC address
1207 * @vlan: the vlan
b40c82e6 1208 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1209 * @is_netdev: make sure its a netdev filter, else doesn't matter
1210 *
1211 * Returns ptr to the filter object or NULL
1212 **/
1213static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1214 u8 *macaddr, s16 vlan,
1215 bool is_vf, bool is_netdev)
1216{
1217 struct i40e_mac_filter *f;
1218
1219 if (!vsi || !macaddr)
1220 return NULL;
1221
1222 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1223 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1224 (vlan == f->vlan) &&
1225 (!is_vf || f->is_vf) &&
1226 (!is_netdev || f->is_netdev))
1227 return f;
1228 }
1229 return NULL;
1230}
1231
1232/**
1233 * i40e_find_mac - Find a mac addr in the macvlan filters list
1234 * @vsi: the VSI to be searched
1235 * @macaddr: the MAC address we are searching for
b40c82e6 1236 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1237 * @is_netdev: make sure its a netdev filter, else doesn't matter
1238 *
1239 * Returns the first filter with the provided MAC address or NULL if
1240 * MAC address was not found
1241 **/
1242struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1243 bool is_vf, bool is_netdev)
1244{
1245 struct i40e_mac_filter *f;
1246
1247 if (!vsi || !macaddr)
1248 return NULL;
1249
1250 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1251 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1252 (!is_vf || f->is_vf) &&
1253 (!is_netdev || f->is_netdev))
1254 return f;
1255 }
1256 return NULL;
1257}
1258
1259/**
1260 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1261 * @vsi: the VSI to be searched
1262 *
1263 * Returns true if VSI is in vlan mode or false otherwise
1264 **/
1265bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1266{
1267 struct i40e_mac_filter *f;
1268
1269 /* Only -1 for all the filters denotes not in vlan mode
1270 * so we have to go through all the list in order to make sure
1271 */
1272 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1273 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1274 return true;
1275 }
1276
1277 return false;
1278}
1279
1280/**
1281 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1282 * @vsi: the VSI to be searched
1283 * @macaddr: the mac address to be filtered
b40c82e6 1284 * @is_vf: true if it is a VF
41c445ff
JB		 1285 * @is_netdev: true if it is a netdev
1286 *
1287 * Goes through all the macvlan filters and adds a
1288 * macvlan filter for each unique vlan that already exists
1289 *
1290 * Returns first filter found on success, else NULL
1291 **/
1292struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1293 bool is_vf, bool is_netdev)
1294{
1295 struct i40e_mac_filter *f;
1296
1297 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1298 if (vsi->info.pvid)
1299 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1300 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1301 is_vf, is_netdev)) {
1302 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1303 is_vf, is_netdev))
41c445ff
JB		 1304 return NULL;
1305 }
1306 }
1307
1308 return list_first_entry_or_null(&vsi->mac_filter_list,
1309 struct i40e_mac_filter, list);
1310}
1311
8c27d42e
GR		 1312/**
1313 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1314 * @vsi: the PF Main VSI - inappropriate for any other VSI
1315 * @macaddr: the MAC address
30650cc5
SN		 1316 *
1317 * Some older firmware configurations set up a default promiscuous VLAN
1318 * filter that needs to be removed.
8c27d42e 1319 **/
30650cc5 1320static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1321{
1322 struct i40e_aqc_remove_macvlan_element_data element;
1323 struct i40e_pf *pf = vsi->back;
f1c7e72e 1324 i40e_status ret;
8c27d42e
GR		 1325
1326 /* Only appropriate for the PF main VSI */
1327 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1328 return -EINVAL;
8c27d42e 1329
30650cc5 1330 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1331 ether_addr_copy(element.mac_addr, macaddr);
1332 element.vlan_tag = 0;
1333 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1334 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1335 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1336 if (ret)
30650cc5
SN		 1337 return -ENOENT;
1338
1339 return 0;
8c27d42e
GR		 1340}
1341
41c445ff
JB		 1342/**
1343 * i40e_add_filter - Add a mac/vlan filter to the VSI
1344 * @vsi: the VSI to be searched
1345 * @macaddr: the MAC address
1346 * @vlan: the vlan
b40c82e6 1347 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1348 * @is_netdev: make sure its a netdev filter, else doesn't matter
1349 *
1350 * Returns ptr to the filter object or NULL when no memory available.
1351 **/
1352struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1353 u8 *macaddr, s16 vlan,
1354 bool is_vf, bool is_netdev)
1355{
1356 struct i40e_mac_filter *f;
1357
1358 if (!vsi || !macaddr)
1359 return NULL;
1360
1361 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1362 if (!f) {
1363 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1364 if (!f)
1365 goto add_filter_out;
1366
9a173901 1367 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1368 f->vlan = vlan;
1369 f->changed = true;
1370
1371 INIT_LIST_HEAD(&f->list);
1372 list_add(&f->list, &vsi->mac_filter_list);
1373 }
1374
1375 /* increment counter and add a new flag if needed */
1376 if (is_vf) {
1377 if (!f->is_vf) {
1378 f->is_vf = true;
1379 f->counter++;
1380 }
1381 } else if (is_netdev) {
1382 if (!f->is_netdev) {
1383 f->is_netdev = true;
1384 f->counter++;
1385 }
1386 } else {
1387 f->counter++;
1388 }
1389
1390 /* changed tells sync_filters_subtask to
1391 * push the filter down to the firmware
1392 */
1393 if (f->changed) {
1394 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1395 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1396 }
1397
1398add_filter_out:
1399 return f;
1400}
1401
1402/**
1403 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1404 * @vsi: the VSI to be searched
1405 * @macaddr: the MAC address
1406 * @vlan: the vlan
b40c82e6 1407 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff
JB		 1408 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1409 **/
1410void i40e_del_filter(struct i40e_vsi *vsi,
1411 u8 *macaddr, s16 vlan,
1412 bool is_vf, bool is_netdev)
1413{
1414 struct i40e_mac_filter *f;
1415
1416 if (!vsi || !macaddr)
1417 return;
1418
1419 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1420 if (!f || f->counter == 0)
1421 return;
1422
1423 if (is_vf) {
1424 if (f->is_vf) {
1425 f->is_vf = false;
1426 f->counter--;
1427 }
1428 } else if (is_netdev) {
1429 if (f->is_netdev) {
1430 f->is_netdev = false;
1431 f->counter--;
1432 }
1433 } else {
b40c82e6 1434 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff
JB		 1435 int min_f = 0;
1436 min_f += (f->is_vf ? 1 : 0);
1437 min_f += (f->is_netdev ? 1 : 0);
1438
1439 if (f->counter > min_f)
1440 f->counter--;
1441 }
1442
1443 /* counter == 0 tells sync_filters_subtask to
1444 * remove the filter from the firmware's list
1445 */
1446 if (f->counter == 0) {
1447 f->changed = true;
1448 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1449 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1450 }
1451}
1452
1453/**
1454 * i40e_set_mac - NDO callback to set mac address
1455 * @netdev: network interface device structure
1456 * @p: pointer to an address structure
1457 *
1458 * Returns 0 on success, negative on failure
1459 **/
38e00438
VD		 1460#ifdef I40E_FCOE
1461int i40e_set_mac(struct net_device *netdev, void *p)
1462#else
41c445ff 1463static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1464#endif
41c445ff
JB		 1465{
1466 struct i40e_netdev_priv *np = netdev_priv(netdev);
1467 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1468 struct i40e_pf *pf = vsi->back;
1469 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1470 struct sockaddr *addr = p;
1471 struct i40e_mac_filter *f;
1472
1473 if (!is_valid_ether_addr(addr->sa_data))
1474 return -EADDRNOTAVAIL;
1475
30650cc5
SN		 1476 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1477 netdev_info(netdev, "already using mac address %pM\n",
1478 addr->sa_data);
1479 return 0;
1480 }
41c445ff 1481
80f6428f
ASJ		 1482 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1483 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1484 return -EADDRNOTAVAIL;
1485
30650cc5
SN		 1486 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1487 netdev_info(netdev, "returning to hw mac address %pM\n",
1488 hw->mac.addr);
1489 else
1490 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1491
41c445ff
JB		 1492 if (vsi->type == I40E_VSI_MAIN) {
1493 i40e_status ret;
1494 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1495 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1496 addr->sa_data, NULL);
1497 if (ret) {
1498 netdev_info(netdev,
1499 "Addr change for Main VSI failed: %d\n",
1500 ret);
1501 return -EADDRNOTAVAIL;
1502 }
41c445ff
JB		 1503 }
1504
30650cc5
SN		 1505 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1506 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1507
30650cc5
SN		 1508 memset(&element, 0, sizeof(element));
1509 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1510 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1511 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1512 } else {
6c8ad1ba
SN		 1513 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1514 false, false);
6c8ad1ba 1515 }
41c445ff 1516
30650cc5
SN		 1517 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1518 struct i40e_aqc_add_macvlan_element_data element;
1519
1520 memset(&element, 0, sizeof(element));
1521 ether_addr_copy(element.mac_addr, hw->mac.addr);
1522 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1523 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1524 } else {
1525 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1526 false, false);
1527 if (f)
1528 f->is_laa = true;
1529 }
1530
30e2561b 1531 i40e_sync_vsi_filters(vsi, false);
30650cc5 1532 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1533
1534 return 0;
1535}
1536
1537/**
1538 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1539 * @vsi: the VSI being setup
1540 * @ctxt: VSI context structure
1541 * @enabled_tc: Enabled TCs bitmap
1542 * @is_add: True if called before Add VSI
1543 *
1544 * Setup VSI queue mapping for enabled traffic classes.
1545 **/
38e00438
VD		 1546#ifdef I40E_FCOE
1547void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1548 struct i40e_vsi_context *ctxt,
1549 u8 enabled_tc,
1550 bool is_add)
1551#else
41c445ff
JB		 1552static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1553 struct i40e_vsi_context *ctxt,
1554 u8 enabled_tc,
1555 bool is_add)
38e00438 1556#endif
41c445ff
JB		 1557{
1558 struct i40e_pf *pf = vsi->back;
1559 u16 sections = 0;
1560 u8 netdev_tc = 0;
1561 u16 numtc = 0;
1562 u16 qcount;
1563 u8 offset;
1564 u16 qmap;
1565 int i;
4e3b35b0 1566 u16 num_tc_qps = 0;
41c445ff
JB		 1567
1568 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1569 offset = 0;
1570
1571 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1572 /* Find numtc from enabled TC bitmap */
1573 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1574 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1575 numtc++;
1576 }
1577 if (!numtc) {
1578 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1579 numtc = 1;
1580 }
1581 } else {
1582 /* At least TC0 is enabled in case of non-DCB case */
1583 numtc = 1;
1584 }
1585
1586 vsi->tc_config.numtc = numtc;
1587 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1588 /* Number of queues per enabled TC */
7f9ff476
AS		 1589 /* In MFP case we can have a much lower count of MSIx
1590 * vectors available and so we need to lower the used
1591 * q count.
1592 */
26cdc443
ASJ		 1593 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1594 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1595 else
1596 qcount = vsi->alloc_queue_pairs;
7f9ff476 1597 num_tc_qps = qcount / numtc;
e25d00b8 1598 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1599
1600 /* Setup queue offset/count for all TCs for given VSI */
1601 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1602 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1603 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1604 /* TC is enabled */
41c445ff
JB		 1605 int pow, num_qps;
1606
41c445ff
JB		 1607 switch (vsi->type) {
1608 case I40E_VSI_MAIN:
4e3b35b0 1609 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1610 break;
38e00438
VD		 1611#ifdef I40E_FCOE
1612 case I40E_VSI_FCOE:
1613 qcount = num_tc_qps;
1614 break;
1615#endif
41c445ff
JB		 1616 case I40E_VSI_FDIR:
1617 case I40E_VSI_SRIOV:
1618 case I40E_VSI_VMDQ2:
1619 default:
4e3b35b0 1620 qcount = num_tc_qps;
41c445ff
JB		 1621 WARN_ON(i != 0);
1622 break;
1623 }
4e3b35b0
NP		 1624 vsi->tc_config.tc_info[i].qoffset = offset;
1625 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1626
1e200e4a 1627 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1628 num_qps = qcount;
41c445ff 1629 pow = 0;
41a1d04b 1630 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1631 pow++;
1632 num_qps >>= 1;
1633 }
1634
1635 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1636 qmap =
1637 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1638 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1639
4e3b35b0 1640 offset += qcount;
41c445ff
JB		 1641 } else {
1642 /* TC is not enabled so set the offset to
1643 * default queue and allocate one queue
1644 * for the given TC.
1645 */
1646 vsi->tc_config.tc_info[i].qoffset = 0;
1647 vsi->tc_config.tc_info[i].qcount = 1;
1648 vsi->tc_config.tc_info[i].netdev_tc = 0;
1649
1650 qmap = 0;
1651 }
1652 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1653 }
1654
1655 /* Set actual Tx/Rx queue pairs */
1656 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1657 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1658 if (vsi->req_queue_pairs > 0)
1659 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1660 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1661 vsi->num_queue_pairs = pf->num_lan_msix;
1662 }
41c445ff
JB		 1663
1664 /* Scheduler section valid can only be set for ADD VSI */
1665 if (is_add) {
1666 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1667
1668 ctxt->info.up_enable_bits = enabled_tc;
1669 }
1670 if (vsi->type == I40E_VSI_SRIOV) {
1671 ctxt->info.mapping_flags |=
1672 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1673 for (i = 0; i < vsi->num_queue_pairs; i++)
1674 ctxt->info.queue_mapping[i] =
1675 cpu_to_le16(vsi->base_queue + i);
1676 } else {
1677 ctxt->info.mapping_flags |=
1678 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1679 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1680 }
1681 ctxt->info.valid_sections |= cpu_to_le16(sections);
1682}
1683
1684/**
1685 * i40e_set_rx_mode - NDO callback to set the netdev filters
1686 * @netdev: network interface device structure
1687 **/
38e00438
VD		 1688#ifdef I40E_FCOE
1689void i40e_set_rx_mode(struct net_device *netdev)
1690#else
41c445ff 1691static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1692#endif
41c445ff
JB		 1693{
1694 struct i40e_netdev_priv *np = netdev_priv(netdev);
1695 struct i40e_mac_filter *f, *ftmp;
1696 struct i40e_vsi *vsi = np->vsi;
1697 struct netdev_hw_addr *uca;
1698 struct netdev_hw_addr *mca;
1699 struct netdev_hw_addr *ha;
1700
1701 /* add addr if not already in the filter list */
1702 netdev_for_each_uc_addr(uca, netdev) {
1703 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1704 if (i40e_is_vsi_in_vlan(vsi))
1705 i40e_put_mac_in_vlan(vsi, uca->addr,
1706 false, true);
1707 else
1708 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1709 false, true);
1710 }
1711 }
1712
1713 netdev_for_each_mc_addr(mca, netdev) {
1714 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1715 if (i40e_is_vsi_in_vlan(vsi))
1716 i40e_put_mac_in_vlan(vsi, mca->addr,
1717 false, true);
1718 else
1719 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1720 false, true);
1721 }
1722 }
1723
1724 /* remove filter if not in netdev list */
1725 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1726 bool found = false;
1727
1728 if (!f->is_netdev)
1729 continue;
1730
1731 if (is_multicast_ether_addr(f->macaddr)) {
1732 netdev_for_each_mc_addr(mca, netdev) {
1733 if (ether_addr_equal(mca->addr, f->macaddr)) {
1734 found = true;
1735 break;
1736 }
1737 }
1738 } else {
1739 netdev_for_each_uc_addr(uca, netdev) {
1740 if (ether_addr_equal(uca->addr, f->macaddr)) {
1741 found = true;
1742 break;
1743 }
1744 }
1745
1746 for_each_dev_addr(netdev, ha) {
1747 if (ether_addr_equal(ha->addr, f->macaddr)) {
1748 found = true;
1749 break;
1750 }
1751 }
1752 }
1753 if (!found)
1754 i40e_del_filter(
1755 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1756 }
1757
1758 /* check for other flag changes */
1759 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1760 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1761 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1762 }
1763}
1764
1765/**
1766 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1767 * @vsi: ptr to the VSI
30e2561b 1768 * @grab_rtnl: whether RTNL needs to be grabbed
41c445ff
JB		 1769 *
1770 * Push any outstanding VSI filter changes through the AdminQ.
1771 *
1772 * Returns 0 or error value
1773 **/
30e2561b 1774int i40e_sync_vsi_filters(struct i40e_vsi *vsi, bool grab_rtnl)
41c445ff
JB		 1775{
1776 struct i40e_mac_filter *f, *ftmp;
1777 bool promisc_forced_on = false;
1778 bool add_happened = false;
1779 int filter_list_len = 0;
1780 u32 changed_flags = 0;
f1c7e72e 1781 i40e_status ret = 0;
41c445ff
JB		 1782 struct i40e_pf *pf;
1783 int num_add = 0;
1784 int num_del = 0;
f1c7e72e 1785 int aq_err = 0;
41c445ff
JB		 1786 u16 cmd_flags;
1787
1788 /* empty array typed pointers, kcalloc later */
1789 struct i40e_aqc_add_macvlan_element_data *add_list;
1790 struct i40e_aqc_remove_macvlan_element_data *del_list;
1791
1792 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1793 usleep_range(1000, 2000);
1794 pf = vsi->back;
1795
1796 if (vsi->netdev) {
1797 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1798 vsi->current_netdev_flags = vsi->netdev->flags;
1799 }
1800
1801 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1802 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1803
1804 filter_list_len = pf->hw.aq.asq_buf_size /
1805 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1806 del_list = kcalloc(filter_list_len,
1807 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1808 GFP_KERNEL);
1809 if (!del_list)
1810 return -ENOMEM;
1811
1812 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1813 if (!f->changed)
1814 continue;
1815
1816 if (f->counter != 0)
1817 continue;
1818 f->changed = false;
1819 cmd_flags = 0;
1820
1821 /* add to delete list */
9a173901 1822 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1823 del_list[num_del].vlan_tag =
1824 cpu_to_le16((u16)(f->vlan ==
1825 I40E_VLAN_ANY ? 0 : f->vlan));
1826
41c445ff
JB		 1827 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1828 del_list[num_del].flags = cmd_flags;
1829 num_del++;
1830
1831 /* unlink from filter list */
1832 list_del(&f->list);
1833 kfree(f);
1834
1835 /* flush a full buffer */
1836 if (num_del == filter_list_len) {
f1c7e72e
SN		 1837 ret = i40e_aq_remove_macvlan(&pf->hw,
1838 vsi->seid, del_list, num_del,
1839 NULL);
1840 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1841 num_del = 0;
1842 memset(del_list, 0, sizeof(*del_list));
1843
f1c7e72e 1844 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1845 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1846 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1847 i40e_stat_str(&pf->hw, ret),
1848 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1849 }
1850 }
1851 if (num_del) {
f1c7e72e 1852 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1853 del_list, num_del, NULL);
f1c7e72e 1854 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1855 num_del = 0;
1856
f1c7e72e 1857 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1858 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1859 "ignoring delete macvlan error, err %s aq_err %s\n",
1860 i40e_stat_str(&pf->hw, ret),
1861 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1862 }
1863
1864 kfree(del_list);
1865 del_list = NULL;
1866
1867 /* do all the adds now */
1868 filter_list_len = pf->hw.aq.asq_buf_size /
1869 sizeof(struct i40e_aqc_add_macvlan_element_data),
1870 add_list = kcalloc(filter_list_len,
1871 sizeof(struct i40e_aqc_add_macvlan_element_data),
1872 GFP_KERNEL);
1873 if (!add_list)
1874 return -ENOMEM;
1875
1876 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1877 if (!f->changed)
1878 continue;
1879
1880 if (f->counter == 0)
1881 continue;
1882 f->changed = false;
1883 add_happened = true;
1884 cmd_flags = 0;
1885
1886 /* add to add array */
9a173901 1887 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1888 add_list[num_add].vlan_tag =
1889 cpu_to_le16(
1890 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1891 add_list[num_add].queue_number = 0;
1892
1893 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1894 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1895 num_add++;
1896
1897 /* flush a full buffer */
1898 if (num_add == filter_list_len) {
f1c7e72e
SN		 1899 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1900 add_list, num_add,
1901 NULL);
1902 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1903 num_add = 0;
1904
f1c7e72e 1905 if (ret)
41c445ff
JB		 1906 break;
1907 memset(add_list, 0, sizeof(*add_list));
1908 }
1909 }
1910 if (num_add) {
f1c7e72e
SN		 1911 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1912 add_list, num_add, NULL);
1913 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1914 num_add = 0;
1915 }
1916 kfree(add_list);
1917 add_list = NULL;
1918
f1c7e72e 1919 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 1920 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1921 "add filter failed, err %s aq_err %s\n",
1922 i40e_stat_str(&pf->hw, ret),
1923 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1924 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1925 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1926 &vsi->state)) {
1927 promisc_forced_on = true;
1928 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1929 &vsi->state);
1930 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1931 }
1932 }
1933 }
1934
1935 /* check for changes in promiscuous modes */
1936 if (changed_flags & IFF_ALLMULTI) {
1937 bool cur_multipromisc;
1938 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 1939 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1940 vsi->seid,
1941 cur_multipromisc,
1942 NULL);
1943 if (ret)
41c445ff 1944 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1945 "set multi promisc failed, err %s aq_err %s\n",
1946 i40e_stat_str(&pf->hw, ret),
1947 i40e_aq_str(&pf->hw,
1948 pf->hw.aq.asq_last_status));
41c445ff
JB		 1949 }
1950 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1951 bool cur_promisc;
1952 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1953 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1954 &vsi->state));
92faef85
ASJ		 1955 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
1956 /* set defport ON for Main VSI instead of true promisc
1957 * this way we will get all unicast/multicast and VLAN
1958 * promisc behavior but will not get VF or VMDq traffic
1959 * replicated on the Main VSI.
1960 */
1961 if (pf->cur_promisc != cur_promisc) {
1962 pf->cur_promisc = cur_promisc;
30e2561b
AS		 1963 if (grab_rtnl)
1964 i40e_do_reset_safe(pf,
1965 BIT(__I40E_PF_RESET_REQUESTED));
1966 else
1967 i40e_do_reset(pf,
92faef85
ASJ		 1968 BIT(__I40E_PF_RESET_REQUESTED));
1969 }
1970 } else {
1971 ret = i40e_aq_set_vsi_unicast_promiscuous(
1972 &vsi->back->hw,
f1c7e72e
SN		 1973 vsi->seid,
1974 cur_promisc, NULL);
92faef85
ASJ		 1975 if (ret)
1976 dev_info(&pf->pdev->dev,
1977 "set unicast promisc failed, err %d, aq_err %d\n",
1978 ret, pf->hw.aq.asq_last_status);
1979 ret = i40e_aq_set_vsi_multicast_promiscuous(
1980 &vsi->back->hw,
1981 vsi->seid,
1982 cur_promisc, NULL);
1983 if (ret)
1984 dev_info(&pf->pdev->dev,
1985 "set multicast promisc failed, err %d, aq_err %d\n",
1986 ret, pf->hw.aq.asq_last_status);
1987 }
f1c7e72e
SN		 1988 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1989 vsi->seid,
1990 cur_promisc, NULL);
1991 if (ret)
1a10370a 1992 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1993 "set brdcast promisc failed, err %s, aq_err %s\n",
1994 i40e_stat_str(&pf->hw, ret),
1995 i40e_aq_str(&pf->hw,
1996 pf->hw.aq.asq_last_status));
41c445ff
JB		 1997 }
1998
1999 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
2000 return 0;
2001}
2002
2003/**
2004 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2005 * @pf: board private structure
2006 **/
2007static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2008{
2009 int v;
2010
2011 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2012 return;
2013 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2014
505682cd 2015 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 2016 if (pf->vsi[v] &&
2017 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
30e2561b 2018 i40e_sync_vsi_filters(pf->vsi[v], true);
41c445ff
JB		 2019 }
2020}
2021
2022/**
2023 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2024 * @netdev: network interface device structure
2025 * @new_mtu: new value for maximum frame size
2026 *
2027 * Returns 0 on success, negative on failure
2028 **/
2029static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2030{
2031 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2032 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2033 struct i40e_vsi *vsi = np->vsi;
2034
2035 /* MTU < 68 is an error and causes problems on some kernels */
2036 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2037 return -EINVAL;
2038
2039 netdev_info(netdev, "changing MTU from %d to %d\n",
2040 netdev->mtu, new_mtu);
2041 netdev->mtu = new_mtu;
2042 if (netif_running(netdev))
2043 i40e_vsi_reinit_locked(vsi);
2044
2045 return 0;
2046}
2047
beb0dff1
JK		 2048/**
2049 * i40e_ioctl - Access the hwtstamp interface
2050 * @netdev: network interface device structure
2051 * @ifr: interface request data
2052 * @cmd: ioctl command
2053 **/
2054int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2055{
2056 struct i40e_netdev_priv *np = netdev_priv(netdev);
2057 struct i40e_pf *pf = np->vsi->back;
2058
2059 switch (cmd) {
2060 case SIOCGHWTSTAMP:
2061 return i40e_ptp_get_ts_config(pf, ifr);
2062 case SIOCSHWTSTAMP:
2063 return i40e_ptp_set_ts_config(pf, ifr);
2064 default:
2065 return -EOPNOTSUPP;
2066 }
2067}
2068
41c445ff
JB		 2069/**
2070 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2071 * @vsi: the vsi being adjusted
2072 **/
2073void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2074{
2075 struct i40e_vsi_context ctxt;
2076 i40e_status ret;
2077
2078 if ((vsi->info.valid_sections &
2079 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2080 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2081 return; /* already enabled */
2082
2083 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2084 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2085 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2086
2087 ctxt.seid = vsi->seid;
1a2f6248 2088 ctxt.info = vsi->info;
41c445ff
JB		 2089 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2090 if (ret) {
2091 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2092 "update vlan stripping failed, err %s aq_err %s\n",
2093 i40e_stat_str(&vsi->back->hw, ret),
2094 i40e_aq_str(&vsi->back->hw,
2095 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2096 }
2097}
2098
2099/**
2100 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2101 * @vsi: the vsi being adjusted
2102 **/
2103void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2104{
2105 struct i40e_vsi_context ctxt;
2106 i40e_status ret;
2107
2108 if ((vsi->info.valid_sections &
2109 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2110 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2111 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2112 return; /* already disabled */
2113
2114 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2115 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2116 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2117
2118 ctxt.seid = vsi->seid;
1a2f6248 2119 ctxt.info = vsi->info;
41c445ff
JB		 2120 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2121 if (ret) {
2122 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2123 "update vlan stripping failed, err %s aq_err %s\n",
2124 i40e_stat_str(&vsi->back->hw, ret),
2125 i40e_aq_str(&vsi->back->hw,
2126 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2127 }
2128}
2129
2130/**
2131 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2132 * @netdev: network interface to be adjusted
2133 * @features: netdev features to test if VLAN offload is enabled or not
2134 **/
2135static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2136{
2137 struct i40e_netdev_priv *np = netdev_priv(netdev);
2138 struct i40e_vsi *vsi = np->vsi;
2139
2140 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2141 i40e_vlan_stripping_enable(vsi);
2142 else
2143 i40e_vlan_stripping_disable(vsi);
2144}
2145
2146/**
2147 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2148 * @vsi: the vsi being configured
2149 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2150 **/
2151int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2152{
2153 struct i40e_mac_filter *f, *add_f;
2154 bool is_netdev, is_vf;
41c445ff
JB		 2155
2156 is_vf = (vsi->type == I40E_VSI_SRIOV);
2157 is_netdev = !!(vsi->netdev);
2158
2159 if (is_netdev) {
2160 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2161 is_vf, is_netdev);
2162 if (!add_f) {
2163 dev_info(&vsi->back->pdev->dev,
2164 "Could not add vlan filter %d for %pM\n",
2165 vid, vsi->netdev->dev_addr);
2166 return -ENOMEM;
2167 }
2168 }
2169
2170 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2171 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2172 if (!add_f) {
2173 dev_info(&vsi->back->pdev->dev,
2174 "Could not add vlan filter %d for %pM\n",
2175 vid, f->macaddr);
2176 return -ENOMEM;
2177 }
2178 }
2179
41c445ff
JB		 2180 /* Now if we add a vlan tag, make sure to check if it is the first
2181 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2182 * with 0, so we now accept untagged and specified tagged traffic
2183 * (and not any taged and untagged)
2184 */
2185 if (vid > 0) {
2186 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2187 I40E_VLAN_ANY,
2188 is_vf, is_netdev)) {
2189 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2190 I40E_VLAN_ANY, is_vf, is_netdev);
2191 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2192 is_vf, is_netdev);
2193 if (!add_f) {
2194 dev_info(&vsi->back->pdev->dev,
2195 "Could not add filter 0 for %pM\n",
2196 vsi->netdev->dev_addr);
2197 return -ENOMEM;
2198 }
2199 }
8d82a7c5 2200 }
41c445ff 2201
8d82a7c5
GR		 2202 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2203 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2204 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2205 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2206 is_vf, is_netdev)) {
2207 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2208 is_vf, is_netdev);
2209 add_f = i40e_add_filter(vsi, f->macaddr,
2210 0, is_vf, is_netdev);
2211 if (!add_f) {
2212 dev_info(&vsi->back->pdev->dev,
2213 "Could not add filter 0 for %pM\n",
2214 f->macaddr);
2215 return -ENOMEM;
2216 }
2217 }
2218 }
41c445ff
JB		 2219 }
2220
80f6428f
ASJ		 2221 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2222 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2223 return 0;
2224
30e2561b 2225 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2226}
2227
2228/**
2229 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2230 * @vsi: the vsi being configured
2231 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2232 *
2233 * Return: 0 on success or negative otherwise
41c445ff
JB		 2234 **/
2235int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2236{
2237 struct net_device *netdev = vsi->netdev;
2238 struct i40e_mac_filter *f, *add_f;
2239 bool is_vf, is_netdev;
2240 int filter_count = 0;
41c445ff
JB		 2241
2242 is_vf = (vsi->type == I40E_VSI_SRIOV);
2243 is_netdev = !!(netdev);
2244
2245 if (is_netdev)
2246 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2247
2248 list_for_each_entry(f, &vsi->mac_filter_list, list)
2249 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2250
41c445ff
JB		 2251 /* go through all the filters for this VSI and if there is only
2252 * vid == 0 it means there are no other filters, so vid 0 must
2253 * be replaced with -1. This signifies that we should from now
2254 * on accept any traffic (with any tag present, or untagged)
2255 */
2256 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2257 if (is_netdev) {
2258 if (f->vlan &&
2259 ether_addr_equal(netdev->dev_addr, f->macaddr))
2260 filter_count++;
2261 }
2262
2263 if (f->vlan)
2264 filter_count++;
2265 }
2266
2267 if (!filter_count && is_netdev) {
2268 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2269 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2270 is_vf, is_netdev);
2271 if (!f) {
2272 dev_info(&vsi->back->pdev->dev,
2273 "Could not add filter %d for %pM\n",
2274 I40E_VLAN_ANY, netdev->dev_addr);
2275 return -ENOMEM;
2276 }
2277 }
2278
2279 if (!filter_count) {
2280 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2281 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2282 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2283 is_vf, is_netdev);
2284 if (!add_f) {
2285 dev_info(&vsi->back->pdev->dev,
2286 "Could not add filter %d for %pM\n",
2287 I40E_VLAN_ANY, f->macaddr);
2288 return -ENOMEM;
2289 }
2290 }
2291 }
2292
80f6428f
ASJ		 2293 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2294 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2295 return 0;
2296
30e2561b 2297 return i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 2298}
2299
2300/**
2301 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2302 * @netdev: network interface to be adjusted
2303 * @vid: vlan id to be added
078b5876
JB		 2304 *
2305 * net_device_ops implementation for adding vlan ids
41c445ff 2306 **/
38e00438
VD		 2307#ifdef I40E_FCOE
2308int i40e_vlan_rx_add_vid(struct net_device *netdev,
2309 __always_unused __be16 proto, u16 vid)
2310#else
41c445ff
JB		 2311static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2312 __always_unused __be16 proto, u16 vid)
38e00438 2313#endif
41c445ff
JB		 2314{
2315 struct i40e_netdev_priv *np = netdev_priv(netdev);
2316 struct i40e_vsi *vsi = np->vsi;
078b5876 2317 int ret = 0;
41c445ff
JB		 2318
2319 if (vid > 4095)
078b5876
JB		 2320 return -EINVAL;
2321
2322 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2323
6982d429
ASJ		 2324 /* If the network stack called us with vid = 0 then
2325 * it is asking to receive priority tagged packets with
2326 * vlan id 0. Our HW receives them by default when configured
2327 * to receive untagged packets so there is no need to add an
2328 * extra filter for vlan 0 tagged packets.
41c445ff 2329 */
6982d429
ASJ		 2330 if (vid)
2331 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2332
078b5876
JB		 2333 if (!ret && (vid < VLAN_N_VID))
2334 set_bit(vid, vsi->active_vlans);
41c445ff 2335
078b5876 2336 return ret;
41c445ff
JB		 2337}
2338
2339/**
2340 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2341 * @netdev: network interface to be adjusted
2342 * @vid: vlan id to be removed
078b5876 2343 *
fdfd943e 2344 * net_device_ops implementation for removing vlan ids
41c445ff 2345 **/
38e00438
VD		 2346#ifdef I40E_FCOE
2347int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2348 __always_unused __be16 proto, u16 vid)
2349#else
41c445ff
JB		 2350static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2351 __always_unused __be16 proto, u16 vid)
38e00438 2352#endif
41c445ff
JB		 2353{
2354 struct i40e_netdev_priv *np = netdev_priv(netdev);
2355 struct i40e_vsi *vsi = np->vsi;
2356
078b5876
JB		 2357 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2358
41c445ff
JB		 2359 /* return code is ignored as there is nothing a user
2360 * can do about failure to remove and a log message was
078b5876 2361 * already printed from the other function
41c445ff
JB		 2362 */
2363 i40e_vsi_kill_vlan(vsi, vid);
2364
2365 clear_bit(vid, vsi->active_vlans);
078b5876 2366
41c445ff
JB		 2367 return 0;
2368}
2369
2370/**
2371 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2372 * @vsi: the vsi being brought back up
2373 **/
2374static void i40e_restore_vlan(struct i40e_vsi *vsi)
2375{
2376 u16 vid;
2377
2378 if (!vsi->netdev)
2379 return;
2380
2381 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2382
2383 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2384 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2385 vid);
2386}
2387
2388/**
2389 * i40e_vsi_add_pvid - Add pvid for the VSI
2390 * @vsi: the vsi being adjusted
2391 * @vid: the vlan id to set as a PVID
2392 **/
dcae29be 2393int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2394{
2395 struct i40e_vsi_context ctxt;
f1c7e72e 2396 i40e_status ret;
41c445ff
JB		 2397
2398 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2399 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2400 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2401 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2402 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2403
2404 ctxt.seid = vsi->seid;
1a2f6248 2405 ctxt.info = vsi->info;
f1c7e72e
SN		 2406 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2407 if (ret) {
41c445ff 2408 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2409 "add pvid failed, err %s aq_err %s\n",
2410 i40e_stat_str(&vsi->back->hw, ret),
2411 i40e_aq_str(&vsi->back->hw,
2412 vsi->back->hw.aq.asq_last_status));
dcae29be 2413 return -ENOENT;
41c445ff
JB		 2414 }
2415
dcae29be 2416 return 0;
41c445ff
JB		 2417}
2418
2419/**
2420 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2421 * @vsi: the vsi being adjusted
2422 *
2423 * Just use the vlan_rx_register() service to put it back to normal
2424 **/
2425void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2426{
6c12fcbf
GR		 2427 i40e_vlan_stripping_disable(vsi);
2428
41c445ff 2429 vsi->info.pvid = 0;
41c445ff
JB		 2430}
2431
2432/**
2433 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2434 * @vsi: ptr to the VSI
2435 *
2436 * If this function returns with an error, then it's possible one or
2437 * more of the rings is populated (while the rest are not). It is the
2438 * callers duty to clean those orphaned rings.
2439 *
2440 * Return 0 on success, negative on failure
2441 **/
2442static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2443{
2444 int i, err = 0;
2445
2446 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2447 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2448
2449 return err;
2450}
2451
2452/**
2453 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2454 * @vsi: ptr to the VSI
2455 *
2456 * Free VSI's transmit software resources
2457 **/
2458static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2459{
2460 int i;
2461
8e9dca53
GR		 2462 if (!vsi->tx_rings)
2463 return;
2464
41c445ff 2465 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2466 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2467 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2468}
2469
2470/**
2471 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2472 * @vsi: ptr to the VSI
2473 *
2474 * If this function returns with an error, then it's possible one or
2475 * more of the rings is populated (while the rest are not). It is the
2476 * callers duty to clean those orphaned rings.
2477 *
2478 * Return 0 on success, negative on failure
2479 **/
2480static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2481{
2482 int i, err = 0;
2483
2484 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2485 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2486#ifdef I40E_FCOE
2487 i40e_fcoe_setup_ddp_resources(vsi);
2488#endif
41c445ff
JB		 2489 return err;
2490}
2491
2492/**
2493 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2494 * @vsi: ptr to the VSI
2495 *
2496 * Free all receive software resources
2497 **/
2498static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2499{
2500 int i;
2501
8e9dca53
GR		 2502 if (!vsi->rx_rings)
2503 return;
2504
41c445ff 2505 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2506 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2507 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2508#ifdef I40E_FCOE
2509 i40e_fcoe_free_ddp_resources(vsi);
2510#endif
41c445ff
JB		 2511}
2512
3ffa037d
NP		 2513/**
2514 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2515 * @ring: The Tx ring to configure
2516 *
2517 * This enables/disables XPS for a given Tx descriptor ring
2518 * based on the TCs enabled for the VSI that ring belongs to.
2519 **/
2520static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2521{
2522 struct i40e_vsi *vsi = ring->vsi;
2523 cpumask_var_t mask;
2524
9a660eea
JB		 2525 if (!ring->q_vector || !ring->netdev)
2526 return;
2527
2528 /* Single TC mode enable XPS */
2529 if (vsi->tc_config.numtc <= 1) {
2530 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2531 netif_set_xps_queue(ring->netdev,
2532 &ring->q_vector->affinity_mask,
2533 ring->queue_index);
9a660eea
JB		 2534 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2535 /* Disable XPS to allow selection based on TC */
2536 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2537 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2538 free_cpumask_var(mask);
3ffa037d
NP		 2539 }
2540}
2541
41c445ff
JB		 2542/**
2543 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2544 * @ring: The Tx ring to configure
2545 *
2546 * Configure the Tx descriptor ring in the HMC context.
2547 **/
2548static int i40e_configure_tx_ring(struct i40e_ring *ring)
2549{
2550 struct i40e_vsi *vsi = ring->vsi;
2551 u16 pf_q = vsi->base_queue + ring->queue_index;
2552 struct i40e_hw *hw = &vsi->back->hw;
2553 struct i40e_hmc_obj_txq tx_ctx;
2554 i40e_status err = 0;
2555 u32 qtx_ctl = 0;
2556
2557 /* some ATR related tx ring init */
60ea5f83 2558 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2559 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2560 ring->atr_count = 0;
2561 } else {
2562 ring->atr_sample_rate = 0;
2563 }
2564
3ffa037d
NP		 2565 /* configure XPS */
2566 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2567
2568 /* clear the context structure first */
2569 memset(&tx_ctx, 0, sizeof(tx_ctx));
2570
2571 tx_ctx.new_context = 1;
2572 tx_ctx.base = (ring->dma / 128);
2573 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2574 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2575 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2576#ifdef I40E_FCOE
2577 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2578#endif
beb0dff1 2579 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2580 /* FDIR VSI tx ring can still use RS bit and writebacks */
2581 if (vsi->type != I40E_VSI_FDIR)
2582 tx_ctx.head_wb_ena = 1;
2583 tx_ctx.head_wb_addr = ring->dma +
2584 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2585
2586 /* As part of VSI creation/update, FW allocates certain
2587 * Tx arbitration queue sets for each TC enabled for
2588 * the VSI. The FW returns the handles to these queue
2589 * sets as part of the response buffer to Add VSI,
2590 * Update VSI, etc. AQ commands. It is expected that
2591 * these queue set handles be associated with the Tx
2592 * queues by the driver as part of the TX queue context
2593 * initialization. This has to be done regardless of
2594 * DCB as by default everything is mapped to TC0.
2595 */
2596 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2597 tx_ctx.rdylist_act = 0;
2598
2599 /* clear the context in the HMC */
2600 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2601 if (err) {
2602 dev_info(&vsi->back->pdev->dev,
2603 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2604 ring->queue_index, pf_q, err);
2605 return -ENOMEM;
2606 }
2607
2608 /* set the context in the HMC */
2609 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2610 if (err) {
2611 dev_info(&vsi->back->pdev->dev,
2612 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2613 ring->queue_index, pf_q, err);
2614 return -ENOMEM;
2615 }
2616
2617 /* Now associate this queue with this PCI function */
7a28d885 2618 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2619 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2620 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2621 I40E_QTX_CTL_VFVM_INDX_MASK;
2622 } else {
9d8bf547 2623 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2624 }
2625
13fd9774
SN		 2626 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2627 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2628 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2629 i40e_flush(hw);
2630
41c445ff
JB		 2631 /* cache tail off for easier writes later */
2632 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2633
2634 return 0;
2635}
2636
2637/**
2638 * i40e_configure_rx_ring - Configure a receive ring context
2639 * @ring: The Rx ring to configure
2640 *
2641 * Configure the Rx descriptor ring in the HMC context.
2642 **/
2643static int i40e_configure_rx_ring(struct i40e_ring *ring)
2644{
2645 struct i40e_vsi *vsi = ring->vsi;
2646 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2647 u16 pf_q = vsi->base_queue + ring->queue_index;
2648 struct i40e_hw *hw = &vsi->back->hw;
2649 struct i40e_hmc_obj_rxq rx_ctx;
2650 i40e_status err = 0;
2651
2652 ring->state = 0;
2653
2654 /* clear the context structure first */
2655 memset(&rx_ctx, 0, sizeof(rx_ctx));
2656
2657 ring->rx_buf_len = vsi->rx_buf_len;
2658 ring->rx_hdr_len = vsi->rx_hdr_len;
2659
2660 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2661 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2662
2663 rx_ctx.base = (ring->dma / 128);
2664 rx_ctx.qlen = ring->count;
2665
2666 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2667 set_ring_16byte_desc_enabled(ring);
2668 rx_ctx.dsize = 0;
2669 } else {
2670 rx_ctx.dsize = 1;
2671 }
2672
2673 rx_ctx.dtype = vsi->dtype;
2674 if (vsi->dtype) {
2675 set_ring_ps_enabled(ring);
2676 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2677 I40E_RX_SPLIT_IP |
2678 I40E_RX_SPLIT_TCP_UDP |
2679 I40E_RX_SPLIT_SCTP;
2680 } else {
2681 rx_ctx.hsplit_0 = 0;
2682 }
2683
2684 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2685 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2686 if (hw->revision_id == 0)
2687 rx_ctx.lrxqthresh = 0;
2688 else
2689 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2690 rx_ctx.crcstrip = 1;
2691 rx_ctx.l2tsel = 1;
2692 rx_ctx.showiv = 1;
38e00438
VD		 2693#ifdef I40E_FCOE
2694 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2695#endif
acb3676b
CS		 2696 /* set the prefena field to 1 because the manual says to */
2697 rx_ctx.prefena = 1;
41c445ff
JB		 2698
2699 /* clear the context in the HMC */
2700 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2701 if (err) {
2702 dev_info(&vsi->back->pdev->dev,
2703 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2704 ring->queue_index, pf_q, err);
2705 return -ENOMEM;
2706 }
2707
2708 /* set the context in the HMC */
2709 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2710 if (err) {
2711 dev_info(&vsi->back->pdev->dev,
2712 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2713 ring->queue_index, pf_q, err);
2714 return -ENOMEM;
2715 }
2716
2717 /* cache tail for quicker writes, and clear the reg before use */
2718 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2719 writel(0, ring->tail);
2720
a132af24
MW		 2721 if (ring_is_ps_enabled(ring)) {
2722 i40e_alloc_rx_headers(ring);
2723 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2724 } else {
2725 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2726 }
41c445ff
JB		 2727
2728 return 0;
2729}
2730
2731/**
2732 * i40e_vsi_configure_tx - Configure the VSI for Tx
2733 * @vsi: VSI structure describing this set of rings and resources
2734 *
2735 * Configure the Tx VSI for operation.
2736 **/
2737static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2738{
2739 int err = 0;
2740 u16 i;
2741
9f65e15b
AD		 2742 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2743 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2744
2745 return err;
2746}
2747
2748/**
2749 * i40e_vsi_configure_rx - Configure the VSI for Rx
2750 * @vsi: the VSI being configured
2751 *
2752 * Configure the Rx VSI for operation.
2753 **/
2754static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2755{
2756 int err = 0;
2757 u16 i;
2758
2759 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2760 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2761 + ETH_FCS_LEN + VLAN_HLEN;
2762 else
2763 vsi->max_frame = I40E_RXBUFFER_2048;
2764
2765 /* figure out correct receive buffer length */
2766 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2767 I40E_FLAG_RX_PS_ENABLED)) {
2768 case I40E_FLAG_RX_1BUF_ENABLED:
2769 vsi->rx_hdr_len = 0;
2770 vsi->rx_buf_len = vsi->max_frame;
2771 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2772 break;
2773 case I40E_FLAG_RX_PS_ENABLED:
2774 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2775 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2776 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2777 break;
2778 default:
2779 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2780 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2781 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2782 break;
2783 }
2784
38e00438
VD		 2785#ifdef I40E_FCOE
2786 /* setup rx buffer for FCoE */
2787 if ((vsi->type == I40E_VSI_FCOE) &&
2788 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2789 vsi->rx_hdr_len = 0;
2790 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2791 vsi->max_frame = I40E_RXBUFFER_3072;
2792 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2793 }
2794
2795#endif /* I40E_FCOE */
41c445ff
JB		 2796 /* round up for the chip's needs */
2797 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2798 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2799 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2800 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2801
2802 /* set up individual rings */
2803 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2804 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2805
2806 return err;
2807}
2808
2809/**
2810 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2811 * @vsi: ptr to the VSI
2812 **/
2813static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2814{
e7046ee1 2815 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2816 u16 qoffset, qcount;
2817 int i, n;
2818
cd238a3e
PN		 2819 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2820 /* Reset the TC information */
2821 for (i = 0; i < vsi->num_queue_pairs; i++) {
2822 rx_ring = vsi->rx_rings[i];
2823 tx_ring = vsi->tx_rings[i];
2824 rx_ring->dcb_tc = 0;
2825 tx_ring->dcb_tc = 0;
2826 }
2827 }
41c445ff
JB		 2828
2829 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2830 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2831 continue;
2832
2833 qoffset = vsi->tc_config.tc_info[n].qoffset;
2834 qcount = vsi->tc_config.tc_info[n].qcount;
2835 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2836 rx_ring = vsi->rx_rings[i];
2837 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2838 rx_ring->dcb_tc = n;
2839 tx_ring->dcb_tc = n;
2840 }
2841 }
2842}
2843
2844/**
2845 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2846 * @vsi: ptr to the VSI
2847 **/
2848static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2849{
2850 if (vsi->netdev)
2851 i40e_set_rx_mode(vsi->netdev);
2852}
2853
17a73f6b
JG		 2854/**
2855 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2856 * @vsi: Pointer to the targeted VSI
2857 *
2858 * This function replays the hlist on the hw where all the SB Flow Director
2859 * filters were saved.
2860 **/
2861static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2862{
2863 struct i40e_fdir_filter *filter;
2864 struct i40e_pf *pf = vsi->back;
2865 struct hlist_node *node;
2866
55a5e60b
ASJ		 2867 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2868 return;
2869
17a73f6b
JG		 2870 hlist_for_each_entry_safe(filter, node,
2871 &pf->fdir_filter_list, fdir_node) {
2872 i40e_add_del_fdir(vsi, filter, true);
2873 }
2874}
2875
41c445ff
JB		 2876/**
2877 * i40e_vsi_configure - Set up the VSI for action
2878 * @vsi: the VSI being configured
2879 **/
2880static int i40e_vsi_configure(struct i40e_vsi *vsi)
2881{
2882 int err;
2883
2884 i40e_set_vsi_rx_mode(vsi);
2885 i40e_restore_vlan(vsi);
2886 i40e_vsi_config_dcb_rings(vsi);
2887 err = i40e_vsi_configure_tx(vsi);
2888 if (!err)
2889 err = i40e_vsi_configure_rx(vsi);
2890
2891 return err;
2892}
2893
2894/**
2895 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2896 * @vsi: the VSI being configured
2897 **/
2898static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2899{
2900 struct i40e_pf *pf = vsi->back;
2901 struct i40e_q_vector *q_vector;
2902 struct i40e_hw *hw = &pf->hw;
2903 u16 vector;
2904 int i, q;
2905 u32 val;
2906 u32 qp;
2907
2908 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2909 * and PFINT_LNKLSTn registers, e.g.:
2910 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2911 */
2912 qp = vsi->base_queue;
2913 vector = vsi->base_vector;
493fb300
AD		 2914 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2915 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2916 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2917 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2918 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2919 q_vector->rx.itr);
2920 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2921 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2922 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2923 q_vector->tx.itr);
2924
2925 /* Linked list for the queuepairs assigned to this vector */
2926 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2927 for (q = 0; q < q_vector->num_ringpairs; q++) {
2928 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2929 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2930 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2931 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2932 (I40E_QUEUE_TYPE_TX
2933 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2934
2935 wr32(hw, I40E_QINT_RQCTL(qp), val);
2936
2937 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2938 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2939 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2940 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2941 (I40E_QUEUE_TYPE_RX
2942 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2943
2944 /* Terminate the linked list */
2945 if (q == (q_vector->num_ringpairs - 1))
2946 val |= (I40E_QUEUE_END_OF_LIST
2947 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2948
2949 wr32(hw, I40E_QINT_TQCTL(qp), val);
2950 qp++;
2951 }
2952 }
2953
2954 i40e_flush(hw);
2955}
2956
2957/**
2958 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2959 * @hw: ptr to the hardware info
2960 **/
ab437b5a 2961static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2962{
ab437b5a 2963 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2964 u32 val;
2965
2966 /* clear things first */
2967 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2968 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2969
2970 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2971 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2972 I40E_PFINT_ICR0_ENA_GRST_MASK |
2973 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2974 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2975 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2976 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2977 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2978
0d8e1439
ASJ		 2979 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
2980 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
2981
ab437b5a
JK		 2982 if (pf->flags & I40E_FLAG_PTP)
2983 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2984
41c445ff
JB		 2985 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2986
2987 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2988 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2989 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2990
2991 /* OTHER_ITR_IDX = 0 */
2992 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2993}
2994
2995/**
2996 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2997 * @vsi: the VSI being configured
2998 **/
2999static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3000{
493fb300 3001 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3002 struct i40e_pf *pf = vsi->back;
3003 struct i40e_hw *hw = &pf->hw;
3004 u32 val;
3005
3006 /* set the ITR configuration */
3007 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3008 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3009 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3010 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3011 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3012 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3013
ab437b5a 3014 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3015
3016 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3017 wr32(hw, I40E_PFINT_LNKLST0, 0);
3018
f29eaa3d 3019 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3020 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3021 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3022 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3023
3024 wr32(hw, I40E_QINT_RQCTL(0), val);
3025
3026 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3027 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3028 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3029
3030 wr32(hw, I40E_QINT_TQCTL(0), val);
3031 i40e_flush(hw);
3032}
3033
2ef28cfb
MW		 3034/**
3035 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3036 * @pf: board private structure
3037 **/
3038void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3039{
3040 struct i40e_hw *hw = &pf->hw;
3041
3042 wr32(hw, I40E_PFINT_DYN_CTL0,
3043 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3044 i40e_flush(hw);
3045}
3046
41c445ff
JB		 3047/**
3048 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3049 * @pf: board private structure
3050 **/
116a57d4 3051void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3052{
3053 struct i40e_hw *hw = &pf->hw;
3054 u32 val;
3055
3056 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3057 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3058 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3059
3060 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3061 i40e_flush(hw);
3062}
3063
3064/**
3065 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
3066 * @vsi: pointer to a vsi
3067 * @vector: enable a particular Hw Interrupt vector
3068 **/
3069void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
3070{
3071 struct i40e_pf *pf = vsi->back;
3072 struct i40e_hw *hw = &pf->hw;
3073 u32 val;
3074
3075 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
3076 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
3077 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3078 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 3079 /* skip the flush */
41c445ff
JB		 3080}
3081
5c2cebda
CW		 3082/**
3083 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3084 * @vsi: pointer to a vsi
03147773 3085 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3086 **/
3087void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3088{
3089 struct i40e_pf *pf = vsi->back;
3090 struct i40e_hw *hw = &pf->hw;
3091 u32 val;
3092
3093 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3094 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3095 i40e_flush(hw);
3096}
3097
41c445ff
JB		 3098/**
3099 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3100 * @irq: interrupt number
3101 * @data: pointer to a q_vector
3102 **/
3103static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3104{
3105 struct i40e_q_vector *q_vector = data;
3106
cd0b6fa6 3107 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3108 return IRQ_HANDLED;
3109
3110 napi_schedule(&q_vector->napi);
3111
3112 return IRQ_HANDLED;
3113}
3114
41c445ff
JB		 3115/**
3116 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3117 * @vsi: the VSI being configured
3118 * @basename: name for the vector
3119 *
3120 * Allocates MSI-X vectors and requests interrupts from the kernel.
3121 **/
3122static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3123{
3124 int q_vectors = vsi->num_q_vectors;
3125 struct i40e_pf *pf = vsi->back;
3126 int base = vsi->base_vector;
3127 int rx_int_idx = 0;
3128 int tx_int_idx = 0;
3129 int vector, err;
3130
3131 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3132 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3133
cd0b6fa6 3134 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3135 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3136 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3137 tx_int_idx++;
cd0b6fa6 3138 } else if (q_vector->rx.ring) {
41c445ff
JB		 3139 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3140 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3141 } else if (q_vector->tx.ring) {
41c445ff
JB		 3142 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3143 "%s-%s-%d", basename, "tx", tx_int_idx++);
3144 } else {
3145 /* skip this unused q_vector */
3146 continue;
3147 }
3148 err = request_irq(pf->msix_entries[base + vector].vector,
3149 vsi->irq_handler,
3150 0,
3151 q_vector->name,
3152 q_vector);
3153 if (err) {
3154 dev_info(&pf->pdev->dev,
3155 "%s: request_irq failed, error: %d\n",
3156 __func__, err);
3157 goto free_queue_irqs;
3158 }
3159 /* assign the mask for this irq */
3160 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3161 &q_vector->affinity_mask);
3162 }
3163
63741846 3164 vsi->irqs_ready = true;
41c445ff
JB		 3165 return 0;
3166
3167free_queue_irqs:
3168 while (vector) {
3169 vector--;
3170 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3171 NULL);
3172 free_irq(pf->msix_entries[base + vector].vector,
3173 &(vsi->q_vectors[vector]));
3174 }
3175 return err;
3176}
3177
3178/**
3179 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3180 * @vsi: the VSI being un-configured
3181 **/
3182static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3183{
3184 struct i40e_pf *pf = vsi->back;
3185 struct i40e_hw *hw = &pf->hw;
3186 int base = vsi->base_vector;
3187 int i;
3188
3189 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3190 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3191 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3192 }
3193
3194 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3195 for (i = vsi->base_vector;
3196 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3197 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3198
3199 i40e_flush(hw);
3200 for (i = 0; i < vsi->num_q_vectors; i++)
3201 synchronize_irq(pf->msix_entries[i + base].vector);
3202 } else {
3203 /* Legacy and MSI mode - this stops all interrupt handling */
3204 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3205 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3206 i40e_flush(hw);
3207 synchronize_irq(pf->pdev->irq);
3208 }
3209}
3210
3211/**
3212 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3213 * @vsi: the VSI being configured
3214 **/
3215static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3216{
3217 struct i40e_pf *pf = vsi->back;
3218 int i;
3219
3220 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3221 for (i = vsi->base_vector;
3222 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3223 i40e_irq_dynamic_enable(vsi, i);
3224 } else {
3225 i40e_irq_dynamic_enable_icr0(pf);
3226 }
3227
1022cb6c 3228 i40e_flush(&pf->hw);
41c445ff
JB		 3229 return 0;
3230}
3231
3232/**
3233 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3234 * @pf: board private structure
3235 **/
3236static void i40e_stop_misc_vector(struct i40e_pf *pf)
3237{
3238 /* Disable ICR 0 */
3239 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3240 i40e_flush(&pf->hw);
3241}
3242
3243/**
3244 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3245 * @irq: interrupt number
3246 * @data: pointer to a q_vector
3247 *
3248 * This is the handler used for all MSI/Legacy interrupts, and deals
3249 * with both queue and non-queue interrupts. This is also used in
3250 * MSIX mode to handle the non-queue interrupts.
3251 **/
3252static irqreturn_t i40e_intr(int irq, void *data)
3253{
3254 struct i40e_pf *pf = (struct i40e_pf *)data;
3255 struct i40e_hw *hw = &pf->hw;
5e823066 3256 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3257 u32 icr0, icr0_remaining;
3258 u32 val, ena_mask;
3259
3260 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3261 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3262
116a57d4
SN		 3263 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3264 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3265 goto enable_intr;
41c445ff 3266
cd92e72f
SN		 3267 /* if interrupt but no bits showing, must be SWINT */
3268 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3269 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3270 pf->sw_int_count++;
3271
0d8e1439
ASJ		 3272 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3273 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3274 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3275 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3276 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3277 }
3278
41c445ff
JB		 3279 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3280 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3281
3282 /* temporarily disable queue cause for NAPI processing */
3283 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3284 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3285 wr32(hw, I40E_QINT_RQCTL(0), qval);
3286
3287 qval = rd32(hw, I40E_QINT_TQCTL(0));
3288 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3289 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3290
3291 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3292 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3293 }
3294
3295 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3296 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3297 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3298 }
3299
3300 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3301 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3302 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3303 }
3304
3305 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3306 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3307 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3308 }
3309
3310 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3311 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3312 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3313 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3314 val = rd32(hw, I40E_GLGEN_RSTAT);
3315 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3316 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3317 if (val == I40E_RESET_CORER) {
41c445ff 3318 pf->corer_count++;
4eb3f768 3319 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3320 pf->globr_count++;
4eb3f768 3321 } else if (val == I40E_RESET_EMPR) {
41c445ff 3322 pf->empr_count++;
9df42d1a 3323 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3324 }
41c445ff
JB		 3325 }
3326
9c010ee0
ASJ		 3327 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3328 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3329 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3330 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3331 rd32(hw, I40E_PFHMC_ERRORINFO),
3332 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3333 }
3334
beb0dff1
JK		 3335 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3336 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3337
3338 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3339 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3340 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3341 }
beb0dff1
JK		 3342 }
3343
41c445ff
JB		 3344 /* If a critical error is pending we have no choice but to reset the
3345 * device.
3346 * Report and mask out any remaining unexpected interrupts.
3347 */
3348 icr0_remaining = icr0 & ena_mask;
3349 if (icr0_remaining) {
3350 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3351 icr0_remaining);
9c010ee0 3352 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3353 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3354 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3355 dev_info(&pf->pdev->dev, "device will be reset\n");
3356 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3357 i40e_service_event_schedule(pf);
41c445ff
JB		 3358 }
3359 ena_mask &= ~icr0_remaining;
3360 }
5e823066 3361 ret = IRQ_HANDLED;
41c445ff 3362
5e823066 3363enable_intr:
41c445ff
JB		 3364 /* re-enable interrupt causes */
3365 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3366 if (!test_bit(__I40E_DOWN, &pf->state)) {
3367 i40e_service_event_schedule(pf);
3368 i40e_irq_dynamic_enable_icr0(pf);
3369 }
3370
5e823066 3371 return ret;
41c445ff
JB		 3372}
3373
cbf61325
ASJ		 3374/**
3375 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3376 * @tx_ring: tx ring to clean
3377 * @budget: how many cleans we're allowed
3378 *
3379 * Returns true if there's any budget left (e.g. the clean is finished)
3380 **/
3381static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3382{
3383 struct i40e_vsi *vsi = tx_ring->vsi;
3384 u16 i = tx_ring->next_to_clean;
3385 struct i40e_tx_buffer *tx_buf;
3386 struct i40e_tx_desc *tx_desc;
3387
3388 tx_buf = &tx_ring->tx_bi[i];
3389 tx_desc = I40E_TX_DESC(tx_ring, i);
3390 i -= tx_ring->count;
3391
3392 do {
3393 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3394
3395 /* if next_to_watch is not set then there is no work pending */
3396 if (!eop_desc)
3397 break;
3398
3399 /* prevent any other reads prior to eop_desc */
3400 read_barrier_depends();
3401
3402 /* if the descriptor isn't done, no work yet to do */
3403 if (!(eop_desc->cmd_type_offset_bsz &
3404 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3405 break;
3406
3407 /* clear next_to_watch to prevent false hangs */
3408 tx_buf->next_to_watch = NULL;
3409
49d7d933
ASJ		 3410 tx_desc->buffer_addr = 0;
3411 tx_desc->cmd_type_offset_bsz = 0;
3412 /* move past filter desc */
3413 tx_buf++;
3414 tx_desc++;
3415 i++;
3416 if (unlikely(!i)) {
3417 i -= tx_ring->count;
3418 tx_buf = tx_ring->tx_bi;
3419 tx_desc = I40E_TX_DESC(tx_ring, 0);
3420 }
cbf61325
ASJ		 3421 /* unmap skb header data */
3422 dma_unmap_single(tx_ring->dev,
3423 dma_unmap_addr(tx_buf, dma),
3424 dma_unmap_len(tx_buf, len),
3425 DMA_TO_DEVICE);
49d7d933
ASJ		 3426 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3427 kfree(tx_buf->raw_buf);
cbf61325 3428
49d7d933
ASJ		 3429 tx_buf->raw_buf = NULL;
3430 tx_buf->tx_flags = 0;
3431 tx_buf->next_to_watch = NULL;
cbf61325 3432 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3433 tx_desc->buffer_addr = 0;
3434 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3435
49d7d933 3436 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3437 tx_buf++;
3438 tx_desc++;
3439 i++;
3440 if (unlikely(!i)) {
3441 i -= tx_ring->count;
3442 tx_buf = tx_ring->tx_bi;
3443 tx_desc = I40E_TX_DESC(tx_ring, 0);
3444 }
3445
3446 /* update budget accounting */
3447 budget--;
3448 } while (likely(budget));
3449
3450 i += tx_ring->count;
3451 tx_ring->next_to_clean = i;
3452
3453 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3454 i40e_irq_dynamic_enable(vsi,
3455 tx_ring->q_vector->v_idx + vsi->base_vector);
3456 }
3457 return budget > 0;
3458}
3459
3460/**
3461 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3462 * @irq: interrupt number
3463 * @data: pointer to a q_vector
3464 **/
3465static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3466{
3467 struct i40e_q_vector *q_vector = data;
3468 struct i40e_vsi *vsi;
3469
3470 if (!q_vector->tx.ring)
3471 return IRQ_HANDLED;
3472
3473 vsi = q_vector->tx.ring->vsi;
3474 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3475
3476 return IRQ_HANDLED;
3477}
3478
41c445ff 3479/**
cd0b6fa6 3480 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3481 * @vsi: the VSI being configured
3482 * @v_idx: vector index
cd0b6fa6 3483 * @qp_idx: queue pair index
41c445ff 3484 **/
26cdc443 3485static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3486{
493fb300 3487 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3488 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3489 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3490
3491 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3492 tx_ring->next = q_vector->tx.ring;
3493 q_vector->tx.ring = tx_ring;
41c445ff 3494 q_vector->tx.count++;
cd0b6fa6
AD		 3495
3496 rx_ring->q_vector = q_vector;
3497 rx_ring->next = q_vector->rx.ring;
3498 q_vector->rx.ring = rx_ring;
3499 q_vector->rx.count++;
41c445ff
JB		 3500}
3501
3502/**
3503 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3504 * @vsi: the VSI being configured
3505 *
3506 * This function maps descriptor rings to the queue-specific vectors
3507 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3508 * one vector per queue pair, but on a constrained vector budget, we
3509 * group the queue pairs as "efficiently" as possible.
3510 **/
3511static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3512{
3513 int qp_remaining = vsi->num_queue_pairs;
3514 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3515 int num_ringpairs;
41c445ff
JB		 3516 int v_start = 0;
3517 int qp_idx = 0;
3518
3519 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3520 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3521 * It is also important to go through all the vectors available to be
3522 * sure that if we don't use all the vectors, that the remaining vectors
3523 * are cleared. This is especially important when decreasing the
3524 * number of queues in use.
41c445ff 3525 */
70114ec4 3526 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3527 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3528
3529 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3530
3531 q_vector->num_ringpairs = num_ringpairs;
3532
3533 q_vector->rx.count = 0;
3534 q_vector->tx.count = 0;
3535 q_vector->rx.ring = NULL;
3536 q_vector->tx.ring = NULL;
3537
3538 while (num_ringpairs--) {
26cdc443 3539 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3540 qp_idx++;
3541 qp_remaining--;
41c445ff
JB		 3542 }
3543 }
3544}
3545
3546/**
3547 * i40e_vsi_request_irq - Request IRQ from the OS
3548 * @vsi: the VSI being configured
3549 * @basename: name for the vector
3550 **/
3551static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3552{
3553 struct i40e_pf *pf = vsi->back;
3554 int err;
3555
3556 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3557 err = i40e_vsi_request_irq_msix(vsi, basename);
3558 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3559 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3560 pf->int_name, pf);
41c445ff
JB		 3561 else
3562 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3563 pf->int_name, pf);
41c445ff
JB		 3564
3565 if (err)
3566 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3567
3568 return err;
3569}
3570
3571#ifdef CONFIG_NET_POLL_CONTROLLER
3572/**
3573 * i40e_netpoll - A Polling 'interrupt'handler
3574 * @netdev: network interface device structure
3575 *
3576 * This is used by netconsole to send skbs without having to re-enable
3577 * interrupts. It's not called while the normal interrupt routine is executing.
3578 **/
38e00438
VD		 3579#ifdef I40E_FCOE
3580void i40e_netpoll(struct net_device *netdev)
3581#else
41c445ff 3582static void i40e_netpoll(struct net_device *netdev)
38e00438 3583#endif
41c445ff
JB		 3584{
3585 struct i40e_netdev_priv *np = netdev_priv(netdev);
3586 struct i40e_vsi *vsi = np->vsi;
3587 struct i40e_pf *pf = vsi->back;
3588 int i;
3589
3590 /* if interface is down do nothing */
3591 if (test_bit(__I40E_DOWN, &vsi->state))
3592 return;
3593
3594 pf->flags |= I40E_FLAG_IN_NETPOLL;
3595 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3596 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3597 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3598 } else {
3599 i40e_intr(pf->pdev->irq, netdev);
3600 }
3601 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3602}
3603#endif
3604
23527308
NP		 3605/**
3606 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3607 * @pf: the PF being configured
3608 * @pf_q: the PF queue
3609 * @enable: enable or disable state of the queue
3610 *
3611 * This routine will wait for the given Tx queue of the PF to reach the
3612 * enabled or disabled state.
3613 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3614 * multiple retries; else will return 0 in case of success.
3615 **/
3616static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3617{
3618 int i;
3619 u32 tx_reg;
3620
3621 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3622 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3623 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3624 break;
3625
f98a2006 3626 usleep_range(10, 20);
23527308
NP		 3627 }
3628 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3629 return -ETIMEDOUT;
3630
3631 return 0;
3632}
3633
41c445ff
JB		 3634/**
3635 * i40e_vsi_control_tx - Start or stop a VSI's rings
3636 * @vsi: the VSI being configured
3637 * @enable: start or stop the rings
3638 **/
3639static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3640{
3641 struct i40e_pf *pf = vsi->back;
3642 struct i40e_hw *hw = &pf->hw;
23527308 3643 int i, j, pf_q, ret = 0;
41c445ff
JB		 3644 u32 tx_reg;
3645
3646 pf_q = vsi->base_queue;
3647 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3648
3649 /* warn the TX unit of coming changes */
3650 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3651 if (!enable)
f98a2006 3652 usleep_range(10, 20);
351499ab 3653
6c5ef620 3654 for (j = 0; j < 50; j++) {
41c445ff 3655 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3656 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3657 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3658 break;
3659 usleep_range(1000, 2000);
3660 }
fda972f6 3661 /* Skip if the queue is already in the requested state */
7c122007 3662 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3663 continue;
41c445ff
JB		 3664
3665 /* turn on/off the queue */
c5c9eb9e
SN		 3666 if (enable) {
3667 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3668 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3669 } else {
41c445ff 3670 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3671 }
41c445ff
JB		 3672
3673 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3674 /* No waiting for the Tx queue to disable */
3675 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3676 continue;
41c445ff
JB		 3677
3678 /* wait for the change to finish */
23527308
NP		 3679 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3680 if (ret) {
3681 dev_info(&pf->pdev->dev,
3682 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3683 __func__, vsi->seid, pf_q,
3684 (enable ? "en" : "dis"));
3685 break;
41c445ff
JB		 3686 }
3687 }
3688
7134f9ce
JB		 3689 if (hw->revision_id == 0)
3690 mdelay(50);
23527308
NP		 3691 return ret;
3692}
3693
3694/**
3695 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3696 * @pf: the PF being configured
3697 * @pf_q: the PF queue
3698 * @enable: enable or disable state of the queue
3699 *
3700 * This routine will wait for the given Rx queue of the PF to reach the
3701 * enabled or disabled state.
3702 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3703 * multiple retries; else will return 0 in case of success.
3704 **/
3705static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3706{
3707 int i;
3708 u32 rx_reg;
3709
3710 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3711 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3712 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3713 break;
3714
f98a2006 3715 usleep_range(10, 20);
23527308
NP		 3716 }
3717 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3718 return -ETIMEDOUT;
7134f9ce 3719
41c445ff
JB		 3720 return 0;
3721}
3722
3723/**
3724 * i40e_vsi_control_rx - Start or stop a VSI's rings
3725 * @vsi: the VSI being configured
3726 * @enable: start or stop the rings
3727 **/
3728static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3729{
3730 struct i40e_pf *pf = vsi->back;
3731 struct i40e_hw *hw = &pf->hw;
23527308 3732 int i, j, pf_q, ret = 0;
41c445ff
JB		 3733 u32 rx_reg;
3734
3735 pf_q = vsi->base_queue;
3736 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3737 for (j = 0; j < 50; j++) {
41c445ff 3738 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3739 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3740 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3741 break;
3742 usleep_range(1000, 2000);
3743 }
41c445ff 3744
7c122007
CS		 3745 /* Skip if the queue is already in the requested state */
3746 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3747 continue;
41c445ff
JB		 3748
3749 /* turn on/off the queue */
3750 if (enable)
6c5ef620 3751 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3752 else
6c5ef620 3753 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3754 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3755
3756 /* wait for the change to finish */
23527308
NP		 3757 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3758 if (ret) {
3759 dev_info(&pf->pdev->dev,
3760 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3761 __func__, vsi->seid, pf_q,
3762 (enable ? "en" : "dis"));
3763 break;
41c445ff
JB		 3764 }
3765 }
3766
23527308 3767 return ret;
41c445ff
JB		 3768}
3769
3770/**
3771 * i40e_vsi_control_rings - Start or stop a VSI's rings
3772 * @vsi: the VSI being configured
3773 * @enable: start or stop the rings
3774 **/
fc18eaa0 3775int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3776{
3b867b28 3777 int ret = 0;
41c445ff
JB		 3778
3779 /* do rx first for enable and last for disable */
3780 if (request) {
3781 ret = i40e_vsi_control_rx(vsi, request);
3782 if (ret)
3783 return ret;
3784 ret = i40e_vsi_control_tx(vsi, request);
3785 } else {
3b867b28
ASJ		 3786 /* Ignore return value, we need to shutdown whatever we can */
3787 i40e_vsi_control_tx(vsi, request);
3788 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3789 }
3790
3791 return ret;
3792}
3793
3794/**
3795 * i40e_vsi_free_irq - Free the irq association with the OS
3796 * @vsi: the VSI being configured
3797 **/
3798static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3799{
3800 struct i40e_pf *pf = vsi->back;
3801 struct i40e_hw *hw = &pf->hw;
3802 int base = vsi->base_vector;
3803 u32 val, qp;
3804 int i;
3805
3806 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3807 if (!vsi->q_vectors)
3808 return;
3809
63741846
SN		 3810 if (!vsi->irqs_ready)
3811 return;
3812
3813 vsi->irqs_ready = false;
41c445ff
JB		 3814 for (i = 0; i < vsi->num_q_vectors; i++) {
3815 u16 vector = i + base;
3816
3817 /* free only the irqs that were actually requested */
78681b1f
SN		 3818 if (!vsi->q_vectors[i] ||
3819 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3820 continue;
3821
3822 /* clear the affinity_mask in the IRQ descriptor */
3823 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3824 NULL);
3825 free_irq(pf->msix_entries[vector].vector,
493fb300 3826 vsi->q_vectors[i]);
41c445ff
JB		 3827
3828 /* Tear down the interrupt queue link list
3829 *
3830 * We know that they come in pairs and always
3831 * the Rx first, then the Tx. To clear the
3832 * link list, stick the EOL value into the
3833 * next_q field of the registers.
3834 */
3835 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3836 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3837 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3838 val |= I40E_QUEUE_END_OF_LIST
3839 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3840 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3841
3842 while (qp != I40E_QUEUE_END_OF_LIST) {
3843 u32 next;
3844
3845 val = rd32(hw, I40E_QINT_RQCTL(qp));
3846
3847 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3848 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3849 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3850 I40E_QINT_RQCTL_INTEVENT_MASK);
3851
3852 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3853 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3854
3855 wr32(hw, I40E_QINT_RQCTL(qp), val);
3856
3857 val = rd32(hw, I40E_QINT_TQCTL(qp));
3858
3859 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3860 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3861
3862 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3863 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3864 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3865 I40E_QINT_TQCTL_INTEVENT_MASK);
3866
3867 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3868 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3869
3870 wr32(hw, I40E_QINT_TQCTL(qp), val);
3871 qp = next;
3872 }
3873 }
3874 } else {
3875 free_irq(pf->pdev->irq, pf);
3876
3877 val = rd32(hw, I40E_PFINT_LNKLST0);
3878 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3879 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3880 val |= I40E_QUEUE_END_OF_LIST
3881 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3882 wr32(hw, I40E_PFINT_LNKLST0, val);
3883
3884 val = rd32(hw, I40E_QINT_RQCTL(qp));
3885 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3886 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3887 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3888 I40E_QINT_RQCTL_INTEVENT_MASK);
3889
3890 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3891 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3892
3893 wr32(hw, I40E_QINT_RQCTL(qp), val);
3894
3895 val = rd32(hw, I40E_QINT_TQCTL(qp));
3896
3897 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3898 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3899 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3900 I40E_QINT_TQCTL_INTEVENT_MASK);
3901
3902 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3903 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3904
3905 wr32(hw, I40E_QINT_TQCTL(qp), val);
3906 }
3907}
3908
493fb300
AD		 3909/**
3910 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3911 * @vsi: the VSI being configured
3912 * @v_idx: Index of vector to be freed
3913 *
3914 * This function frees the memory allocated to the q_vector. In addition if
3915 * NAPI is enabled it will delete any references to the NAPI struct prior
3916 * to freeing the q_vector.
3917 **/
3918static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3919{
3920 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3921 struct i40e_ring *ring;
493fb300
AD		 3922
3923 if (!q_vector)
3924 return;
3925
3926 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3927 i40e_for_each_ring(ring, q_vector->tx)
3928 ring->q_vector = NULL;
3929
3930 i40e_for_each_ring(ring, q_vector->rx)
3931 ring->q_vector = NULL;
493fb300
AD		 3932
3933 /* only VSI w/ an associated netdev is set up w/ NAPI */
3934 if (vsi->netdev)
3935 netif_napi_del(&q_vector->napi);
3936
3937 vsi->q_vectors[v_idx] = NULL;
3938
3939 kfree_rcu(q_vector, rcu);
3940}
3941
41c445ff
JB		 3942/**
3943 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3944 * @vsi: the VSI being un-configured
3945 *
3946 * This frees the memory allocated to the q_vectors and
3947 * deletes references to the NAPI struct.
3948 **/
3949static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3950{
3951 int v_idx;
3952
493fb300
AD		 3953 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3954 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3955}
3956
3957/**
3958 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3959 * @pf: board private structure
3960 **/
3961static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3962{
3963 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3964 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3965 pci_disable_msix(pf->pdev);
3966 kfree(pf->msix_entries);
3967 pf->msix_entries = NULL;
3b444399
SN		 3968 kfree(pf->irq_pile);
3969 pf->irq_pile = NULL;
41c445ff
JB		 3970 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3971 pci_disable_msi(pf->pdev);
3972 }
3973 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3974}
3975
3976/**
3977 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3978 * @pf: board private structure
3979 *
3980 * We go through and clear interrupt specific resources and reset the structure
3981 * to pre-load conditions
3982 **/
3983static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3984{
3985 int i;
3986
e147758d
SN		 3987 i40e_stop_misc_vector(pf);
3988 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3989 synchronize_irq(pf->msix_entries[0].vector);
3990 free_irq(pf->msix_entries[0].vector, pf);
3991 }
3992
41c445ff 3993 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3994 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3995 if (pf->vsi[i])
3996 i40e_vsi_free_q_vectors(pf->vsi[i]);
3997 i40e_reset_interrupt_capability(pf);
3998}
3999
4000/**
4001 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4002 * @vsi: the VSI being configured
4003 **/
4004static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4005{
4006 int q_idx;
4007
4008 if (!vsi->netdev)
4009 return;
4010
4011 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4012 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4013}
4014
4015/**
4016 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4017 * @vsi: the VSI being configured
4018 **/
4019static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4020{
4021 int q_idx;
4022
4023 if (!vsi->netdev)
4024 return;
4025
4026 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4027 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4028}
4029
90ef8d47
SN		 4030/**
4031 * i40e_vsi_close - Shut down a VSI
4032 * @vsi: the vsi to be quelled
4033 **/
4034static void i40e_vsi_close(struct i40e_vsi *vsi)
4035{
4036 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4037 i40e_down(vsi);
4038 i40e_vsi_free_irq(vsi);
4039 i40e_vsi_free_tx_resources(vsi);
4040 i40e_vsi_free_rx_resources(vsi);
92faef85 4041 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4042}
4043
41c445ff
JB		 4044/**
4045 * i40e_quiesce_vsi - Pause a given VSI
4046 * @vsi: the VSI being paused
4047 **/
4048static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4049{
4050 if (test_bit(__I40E_DOWN, &vsi->state))
4051 return;
4052
d341b7a5
NP		 4053 /* No need to disable FCoE VSI when Tx suspended */
4054 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4055 vsi->type == I40E_VSI_FCOE) {
4056 dev_dbg(&vsi->back->pdev->dev,
4057 "%s: VSI seid %d skipping FCoE VSI disable\n",
4058 __func__, vsi->seid);
4059 return;
4060 }
4061
41c445ff
JB		 4062 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
4063 if (vsi->netdev && netif_running(vsi->netdev)) {
4064 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
4065 } else {
90ef8d47 4066 i40e_vsi_close(vsi);
41c445ff
JB		 4067 }
4068}
4069
4070/**
4071 * i40e_unquiesce_vsi - Resume a given VSI
4072 * @vsi: the VSI being resumed
4073 **/
4074static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4075{
4076 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4077 return;
4078
4079 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4080 if (vsi->netdev && netif_running(vsi->netdev))
4081 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4082 else
8276f757 4083 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4084}
4085
4086/**
4087 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4088 * @pf: the PF
4089 **/
4090static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4091{
4092 int v;
4093
505682cd 4094 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4095 if (pf->vsi[v])
4096 i40e_quiesce_vsi(pf->vsi[v]);
4097 }
4098}
4099
4100/**
4101 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4102 * @pf: the PF
4103 **/
4104static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4105{
4106 int v;
4107
505682cd 4108 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4109 if (pf->vsi[v])
4110 i40e_unquiesce_vsi(pf->vsi[v]);
4111 }
4112}
4113
69129dc3
NP		 4114#ifdef CONFIG_I40E_DCB
4115/**
4116 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4117 * @vsi: the VSI being configured
4118 *
4119 * This function waits for the given VSI's Tx queues to be disabled.
4120 **/
4121static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4122{
4123 struct i40e_pf *pf = vsi->back;
4124 int i, pf_q, ret;
4125
4126 pf_q = vsi->base_queue;
4127 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4128 /* Check and wait for the disable status of the queue */
4129 ret = i40e_pf_txq_wait(pf, pf_q, false);
4130 if (ret) {
4131 dev_info(&pf->pdev->dev,
4132 "%s: VSI seid %d Tx ring %d disable timeout\n",
4133 __func__, vsi->seid, pf_q);
4134 return ret;
4135 }
4136 }
4137
4138 return 0;
4139}
4140
4141/**
4142 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4143 * @pf: the PF
4144 *
4145 * This function waits for the Tx queues to be in disabled state for all the
4146 * VSIs that are managed by this PF.
4147 **/
4148static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4149{
4150 int v, ret = 0;
4151
4152 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4153 /* No need to wait for FCoE VSI queues */
4154 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4155 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4156 if (ret)
4157 break;
4158 }
4159 }
4160
4161 return ret;
4162}
4163
4164#endif
b03a8c1f
KP		 4165
4166/**
4167 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4168 * @q_idx: TX queue number
4169 * @vsi: Pointer to VSI struct
4170 *
4171 * This function checks specified queue for given VSI. Detects hung condition.
4172 * Sets hung bit since it is two step process. Before next run of service task
4173 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4174 * hung condition remain unchanged and during subsequent run, this function
4175 * issues SW interrupt to recover from hung condition.
4176 **/
4177static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4178{
4179 struct i40e_ring *tx_ring = NULL;
4180 struct i40e_pf *pf;
4181 u32 head, val, tx_pending;
4182 int i;
4183
4184 pf = vsi->back;
4185
4186 /* now that we have an index, find the tx_ring struct */
4187 for (i = 0; i < vsi->num_queue_pairs; i++) {
4188 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4189 if (q_idx == vsi->tx_rings[i]->queue_index) {
4190 tx_ring = vsi->tx_rings[i];
4191 break;
4192 }
4193 }
4194 }
4195
4196 if (!tx_ring)
4197 return;
4198
4199 /* Read interrupt register */
4200 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4201 val = rd32(&pf->hw,
4202 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4203 tx_ring->vsi->base_vector - 1));
4204 else
4205 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4206
4207 head = i40e_get_head(tx_ring);
4208
4209 tx_pending = i40e_get_tx_pending(tx_ring);
4210
4211 /* Interrupts are disabled and TX pending is non-zero,
4212 * trigger the SW interrupt (don't wait). Worst case
4213 * there will be one extra interrupt which may result
4214 * into not cleaning any queues because queues are cleaned.
4215 */
4216 if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK)))
4217 i40e_force_wb(vsi, tx_ring->q_vector);
4218}
4219
4220/**
4221 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4222 * @pf: pointer to PF struct
4223 *
4224 * LAN VSI has netdev and netdev has TX queues. This function is to check
4225 * each of those TX queues if they are hung, trigger recovery by issuing
4226 * SW interrupt.
4227 **/
4228static void i40e_detect_recover_hung(struct i40e_pf *pf)
4229{
4230 struct net_device *netdev;
4231 struct i40e_vsi *vsi;
4232 int i;
4233
4234 /* Only for LAN VSI */
4235 vsi = pf->vsi[pf->lan_vsi];
4236
4237 if (!vsi)
4238 return;
4239
4240 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4241 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4242 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4243 return;
4244
4245 /* Make sure type is MAIN VSI */
4246 if (vsi->type != I40E_VSI_MAIN)
4247 return;
4248
4249 netdev = vsi->netdev;
4250 if (!netdev)
4251 return;
4252
4253 /* Bail out if netif_carrier is not OK */
4254 if (!netif_carrier_ok(netdev))
4255 return;
4256
4257 /* Go thru' TX queues for netdev */
4258 for (i = 0; i < netdev->num_tx_queues; i++) {
4259 struct netdev_queue *q;
4260
4261 q = netdev_get_tx_queue(netdev, i);
4262 if (q)
4263 i40e_detect_recover_hung_queue(i, vsi);
4264 }
4265}
4266
63d7e5a4
NP		 4267/**
4268 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4269 * @pf: pointer to PF
63d7e5a4
NP		 4270 *
4271 * Get TC map for ISCSI PF type that will include iSCSI TC
4272 * and LAN TC.
4273 **/
4274static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4275{
4276 struct i40e_dcb_app_priority_table app;
4277 struct i40e_hw *hw = &pf->hw;
4278 u8 enabled_tc = 1; /* TC0 is always enabled */
4279 u8 tc, i;
4280 /* Get the iSCSI APP TLV */
4281 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4282
4283 for (i = 0; i < dcbcfg->numapps; i++) {
4284 app = dcbcfg->app[i];
4285 if (app.selector == I40E_APP_SEL_TCPIP &&
4286 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4287 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4288 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4289 break;
4290 }
4291 }
4292
4293 return enabled_tc;
4294}
4295
41c445ff
JB		 4296/**
4297 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4298 * @dcbcfg: the corresponding DCBx configuration structure
4299 *
4300 * Return the number of TCs from given DCBx configuration
4301 **/
4302static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4303{
078b5876
JB		 4304 u8 num_tc = 0;
4305 int i;
41c445ff
JB		 4306
4307 /* Scan the ETS Config Priority Table to find
4308 * traffic class enabled for a given priority
4309 * and use the traffic class index to get the
4310 * number of traffic classes enabled
4311 */
4312 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4313 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4314 num_tc = dcbcfg->etscfg.prioritytable[i];
4315 }
4316
4317 /* Traffic class index starts from zero so
4318 * increment to return the actual count
4319 */
078b5876 4320 return num_tc + 1;
41c445ff
JB		 4321}
4322
4323/**
4324 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4325 * @dcbcfg: the corresponding DCBx configuration structure
4326 *
4327 * Query the current DCB configuration and return the number of
4328 * traffic classes enabled from the given DCBX config
4329 **/
4330static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4331{
4332 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4333 u8 enabled_tc = 1;
4334 u8 i;
4335
4336 for (i = 0; i < num_tc; i++)
41a1d04b 4337 enabled_tc |= BIT(i);
41c445ff
JB		 4338
4339 return enabled_tc;
4340}
4341
4342/**
4343 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4344 * @pf: PF being queried
4345 *
4346 * Return number of traffic classes enabled for the given PF
4347 **/
4348static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4349{
4350 struct i40e_hw *hw = &pf->hw;
4351 u8 i, enabled_tc;
4352 u8 num_tc = 0;
4353 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4354
4355 /* If DCB is not enabled then always in single TC */
4356 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4357 return 1;
4358
63d7e5a4
NP		 4359 /* SFP mode will be enabled for all TCs on port */
4360 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4361 return i40e_dcb_get_num_tc(dcbcfg);
4362
41c445ff 4363 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4364 if (pf->hw.func_caps.iscsi)
4365 enabled_tc = i40e_get_iscsi_tc_map(pf);
4366 else
fc51de96 4367 return 1; /* Only TC0 */
41c445ff 4368
63d7e5a4
NP		 4369 /* At least have TC0 */
4370 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4371 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4372 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4373 num_tc++;
4374 }
4375 return num_tc;
41c445ff
JB		 4376}
4377
4378/**
4379 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4380 * @pf: PF being queried
4381 *
4382 * Return a bitmap for first enabled traffic class for this PF.
4383 **/
4384static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4385{
4386 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4387 u8 i = 0;
4388
4389 if (!enabled_tc)
4390 return 0x1; /* TC0 */
4391
4392 /* Find the first enabled TC */
4393 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4394 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4395 break;
4396 }
4397
41a1d04b 4398 return BIT(i);
41c445ff
JB		 4399}
4400
4401/**
4402 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4403 * @pf: PF being queried
4404 *
4405 * Return a bitmap for enabled traffic classes for this PF.
4406 **/
4407static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4408{
4409 /* If DCB is not enabled for this PF then just return default TC */
4410 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4411 return i40e_pf_get_default_tc(pf);
4412
41c445ff 4413 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4414 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4415 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4416
fc51de96 4417 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4418 if (pf->hw.func_caps.iscsi)
4419 return i40e_get_iscsi_tc_map(pf);
4420 else
fc51de96 4421 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4422}
4423
4424/**
4425 * i40e_vsi_get_bw_info - Query VSI BW Information
4426 * @vsi: the VSI being queried
4427 *
4428 * Returns 0 on success, negative value on failure
4429 **/
4430static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4431{
4432 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4433 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4434 struct i40e_pf *pf = vsi->back;
4435 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4436 i40e_status ret;
41c445ff 4437 u32 tc_bw_max;
41c445ff
JB		 4438 int i;
4439
4440 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4441 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4442 if (ret) {
41c445ff 4443 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4444 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4445 i40e_stat_str(&pf->hw, ret),
4446 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4447 return -EINVAL;
41c445ff
JB		 4448 }
4449
4450 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4451 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4452 NULL);
4453 if (ret) {
41c445ff 4454 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4455 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4456 i40e_stat_str(&pf->hw, ret),
4457 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4458 return -EINVAL;
41c445ff
JB		 4459 }
4460
4461 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4462 dev_info(&pf->pdev->dev,
4463 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4464 bw_config.tc_valid_bits,
4465 bw_ets_config.tc_valid_bits);
4466 /* Still continuing */
4467 }
4468
4469 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4470 vsi->bw_max_quanta = bw_config.max_bw;
4471 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4472 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4473 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4474 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4475 vsi->bw_ets_limit_credits[i] =
4476 le16_to_cpu(bw_ets_config.credits[i]);
4477 /* 3 bits out of 4 for each TC */
4478 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4479 }
078b5876 4480
dcae29be 4481 return 0;
41c445ff
JB		 4482}
4483
4484/**
4485 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4486 * @vsi: the VSI being configured
4487 * @enabled_tc: TC bitmap
4488 * @bw_credits: BW shared credits per TC
4489 *
4490 * Returns 0 on success, negative value on failure
4491 **/
dcae29be 4492static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4493 u8 *bw_share)
4494{
4495 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4496 i40e_status ret;
dcae29be 4497 int i;
41c445ff
JB		 4498
4499 bw_data.tc_valid_bits = enabled_tc;
4500 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4501 bw_data.tc_bw_credits[i] = bw_share[i];
4502
f1c7e72e
SN		 4503 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4504 NULL);
4505 if (ret) {
41c445ff 4506 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4507 "AQ command Config VSI BW allocation per TC failed = %d\n",
4508 vsi->back->hw.aq.asq_last_status);
dcae29be 4509 return -EINVAL;
41c445ff
JB		 4510 }
4511
4512 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4513 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4514
dcae29be 4515 return 0;
41c445ff
JB		 4516}
4517
4518/**
4519 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4520 * @vsi: the VSI being configured
4521 * @enabled_tc: TC map to be enabled
4522 *
4523 **/
4524static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4525{
4526 struct net_device *netdev = vsi->netdev;
4527 struct i40e_pf *pf = vsi->back;
4528 struct i40e_hw *hw = &pf->hw;
4529 u8 netdev_tc = 0;
4530 int i;
4531 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4532
4533 if (!netdev)
4534 return;
4535
4536 if (!enabled_tc) {
4537 netdev_reset_tc(netdev);
4538 return;
4539 }
4540
4541 /* Set up actual enabled TCs on the VSI */
4542 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4543 return;
4544
4545 /* set per TC queues for the VSI */
4546 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4547 /* Only set TC queues for enabled tcs
4548 *
4549 * e.g. For a VSI that has TC0 and TC3 enabled the
4550 * enabled_tc bitmap would be 0x00001001; the driver
4551 * will set the numtc for netdev as 2 that will be
4552 * referenced by the netdev layer as TC 0 and 1.
4553 */
41a1d04b 4554 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4555 netdev_set_tc_queue(netdev,
4556 vsi->tc_config.tc_info[i].netdev_tc,
4557 vsi->tc_config.tc_info[i].qcount,
4558 vsi->tc_config.tc_info[i].qoffset);
4559 }
4560
4561 /* Assign UP2TC map for the VSI */
4562 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4563 /* Get the actual TC# for the UP */
4564 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4565 /* Get the mapped netdev TC# for the UP */
4566 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4567 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4568 }
4569}
4570
4571/**
4572 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4573 * @vsi: the VSI being configured
4574 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4575 **/
4576static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4577 struct i40e_vsi_context *ctxt)
4578{
4579 /* copy just the sections touched not the entire info
4580 * since not all sections are valid as returned by
4581 * update vsi params
4582 */
4583 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4584 memcpy(&vsi->info.queue_mapping,
4585 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4586 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4587 sizeof(vsi->info.tc_mapping));
4588}
4589
4590/**
4591 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4592 * @vsi: VSI to be configured
4593 * @enabled_tc: TC bitmap
4594 *
4595 * This configures a particular VSI for TCs that are mapped to the
4596 * given TC bitmap. It uses default bandwidth share for TCs across
4597 * VSIs to configure TC for a particular VSI.
4598 *
4599 * NOTE:
4600 * It is expected that the VSI queues have been quisced before calling
4601 * this function.
4602 **/
4603static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4604{
4605 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4606 struct i40e_vsi_context ctxt;
4607 int ret = 0;
4608 int i;
4609
4610 /* Check if enabled_tc is same as existing or new TCs */
4611 if (vsi->tc_config.enabled_tc == enabled_tc)
4612 return ret;
4613
4614 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4615 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4616 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4617 bw_share[i] = 1;
4618 }
4619
4620 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4621 if (ret) {
4622 dev_info(&vsi->back->pdev->dev,
4623 "Failed configuring TC map %d for VSI %d\n",
4624 enabled_tc, vsi->seid);
4625 goto out;
4626 }
4627
4628 /* Update Queue Pairs Mapping for currently enabled UPs */
4629 ctxt.seid = vsi->seid;
4630 ctxt.pf_num = vsi->back->hw.pf_id;
4631 ctxt.vf_num = 0;
4632 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4633 ctxt.info = vsi->info;
41c445ff
JB		 4634 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4635
4636 /* Update the VSI after updating the VSI queue-mapping information */
4637 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4638 if (ret) {
4639 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4640 "Update vsi tc config failed, err %s aq_err %s\n",
4641 i40e_stat_str(&vsi->back->hw, ret),
4642 i40e_aq_str(&vsi->back->hw,
4643 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4644 goto out;
4645 }
4646 /* update the local VSI info with updated queue map */
4647 i40e_vsi_update_queue_map(vsi, &ctxt);
4648 vsi->info.valid_sections = 0;
4649
4650 /* Update current VSI BW information */
4651 ret = i40e_vsi_get_bw_info(vsi);
4652 if (ret) {
4653 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4654 "Failed updating vsi bw info, err %s aq_err %s\n",
4655 i40e_stat_str(&vsi->back->hw, ret),
4656 i40e_aq_str(&vsi->back->hw,
4657 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4658 goto out;
4659 }
4660
4661 /* Update the netdev TC setup */
4662 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4663out:
4664 return ret;
4665}
4666
4e3b35b0
NP		 4667/**
4668 * i40e_veb_config_tc - Configure TCs for given VEB
4669 * @veb: given VEB
4670 * @enabled_tc: TC bitmap
4671 *
4672 * Configures given TC bitmap for VEB (switching) element
4673 **/
4674int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4675{
4676 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4677 struct i40e_pf *pf = veb->pf;
4678 int ret = 0;
4679 int i;
4680
4681 /* No TCs or already enabled TCs just return */
4682 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4683 return ret;
4684
4685 bw_data.tc_valid_bits = enabled_tc;
4686 /* bw_data.absolute_credits is not set (relative) */
4687
4688 /* Enable ETS TCs with equal BW Share for now */
4689 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4690 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4691 bw_data.tc_bw_share_credits[i] = 1;
4692 }
4693
4694 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4695 &bw_data, NULL);
4696 if (ret) {
4697 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4698 "VEB bw config failed, err %s aq_err %s\n",
4699 i40e_stat_str(&pf->hw, ret),
4700 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4701 goto out;
4702 }
4703
4704 /* Update the BW information */
4705 ret = i40e_veb_get_bw_info(veb);
4706 if (ret) {
4707 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4708 "Failed getting veb bw config, err %s aq_err %s\n",
4709 i40e_stat_str(&pf->hw, ret),
4710 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4711 }
4712
4713out:
4714 return ret;
4715}
4716
4717#ifdef CONFIG_I40E_DCB
4718/**
4719 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4720 * @pf: PF struct
4721 *
4722 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4723 * the caller would've quiesce all the VSIs before calling
4724 * this function
4725 **/
4726static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4727{
4728 u8 tc_map = 0;
4729 int ret;
4730 u8 v;
4731
4732 /* Enable the TCs available on PF to all VEBs */
4733 tc_map = i40e_pf_get_tc_map(pf);
4734 for (v = 0; v < I40E_MAX_VEB; v++) {
4735 if (!pf->veb[v])
4736 continue;
4737 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4738 if (ret) {
4739 dev_info(&pf->pdev->dev,
4740 "Failed configuring TC for VEB seid=%d\n",
4741 pf->veb[v]->seid);
4742 /* Will try to configure as many components */
4743 }
4744 }
4745
4746 /* Update each VSI */
505682cd 4747 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4748 if (!pf->vsi[v])
4749 continue;
4750
4751 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4752#ifdef I40E_FCOE
4753 * - For FCoE VSI only enable the TC configured
4754 * as per the APP TLV
4755#endif
4e3b35b0
NP		 4756 * - For all others keep them at TC0 for now
4757 */
4758 if (v == pf->lan_vsi)
4759 tc_map = i40e_pf_get_tc_map(pf);
4760 else
4761 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4762#ifdef I40E_FCOE
4763 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4764 tc_map = i40e_get_fcoe_tc_map(pf);
4765#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4766
4767 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4768 if (ret) {
4769 dev_info(&pf->pdev->dev,
4770 "Failed configuring TC for VSI seid=%d\n",
4771 pf->vsi[v]->seid);
4772 /* Will try to configure as many components */
4773 } else {
0672a091
NP		 4774 /* Re-configure VSI vectors based on updated TC map */
4775 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4776 if (pf->vsi[v]->netdev)
4777 i40e_dcbnl_set_all(pf->vsi[v]);
4778 }
4779 }
4780}
4781
2fd75f31
NP		 4782/**
4783 * i40e_resume_port_tx - Resume port Tx
4784 * @pf: PF struct
4785 *
4786 * Resume a port's Tx and issue a PF reset in case of failure to
4787 * resume.
4788 **/
4789static int i40e_resume_port_tx(struct i40e_pf *pf)
4790{
4791 struct i40e_hw *hw = &pf->hw;
4792 int ret;
4793
4794 ret = i40e_aq_resume_port_tx(hw, NULL);
4795 if (ret) {
4796 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4797 "Resume Port Tx failed, err %s aq_err %s\n",
4798 i40e_stat_str(&pf->hw, ret),
4799 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4800 /* Schedule PF reset to recover */
4801 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4802 i40e_service_event_schedule(pf);
4803 }
4804
4805 return ret;
4806}
4807
4e3b35b0
NP		 4808/**
4809 * i40e_init_pf_dcb - Initialize DCB configuration
4810 * @pf: PF being configured
4811 *
4812 * Query the current DCB configuration and cache it
4813 * in the hardware structure
4814 **/
4815static int i40e_init_pf_dcb(struct i40e_pf *pf)
4816{
4817 struct i40e_hw *hw = &pf->hw;
4818 int err = 0;
4819
025b4a54
ASJ		 4820 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4821 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4822 (pf->hw.aq.fw_maj_ver < 4))
4823 goto out;
4824
4e3b35b0
NP		 4825 /* Get the initial DCB configuration */
4826 err = i40e_init_dcb(hw);
4827 if (!err) {
4828 /* Device/Function is not DCBX capable */
4829 if ((!hw->func_caps.dcb) ||
4830 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4831 dev_info(&pf->pdev->dev,
4832 "DCBX offload is not supported or is disabled for this PF.\n");
4833
4834 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4835 goto out;
4836
4837 } else {
4838 /* When status is not DISABLED then DCBX in FW */
4839 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4840 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4841
4842 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4843 /* Enable DCB tagging only when more than one TC */
4844 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4845 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4846 dev_dbg(&pf->pdev->dev,
4847 "DCBX offload is supported for this PF.\n");
4e3b35b0 4848 }
014269ff 4849 } else {
aebfc816 4850 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4851 "Query for DCB configuration failed, err %s aq_err %s\n",
4852 i40e_stat_str(&pf->hw, err),
4853 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4854 }
4855
4856out:
4857 return err;
4858}
4859#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4860#define SPEED_SIZE 14
4861#define FC_SIZE 8
4862/**
4863 * i40e_print_link_message - print link up or down
4864 * @vsi: the VSI for which link needs a message
4865 */
4866static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4867{
4868 char speed[SPEED_SIZE] = "Unknown";
4869 char fc[FC_SIZE] = "RX/TX";
4870
4871 if (!isup) {
4872 netdev_info(vsi->netdev, "NIC Link is Down\n");
4873 return;
4874 }
4875
148c2d80
GR		 4876 /* Warn user if link speed on NPAR enabled partition is not at
4877 * least 10GB
4878 */
4879 if (vsi->back->hw.func_caps.npar_enable &&
4880 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4881 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4882 netdev_warn(vsi->netdev,
4883 "The partition detected link speed that is less than 10Gbps\n");
4884
cf05ed08
JB		 4885 switch (vsi->back->hw.phy.link_info.link_speed) {
4886 case I40E_LINK_SPEED_40GB:
35a7d804 4887 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08 4888 break;
ae24b409
JB		 4889 case I40E_LINK_SPEED_20GB:
4890 strncpy(speed, "20 Gbps", SPEED_SIZE);
4891 break;
cf05ed08 4892 case I40E_LINK_SPEED_10GB:
35a7d804 4893 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4894 break;
4895 case I40E_LINK_SPEED_1GB:
35a7d804 4896 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4897 break;
5960d33f
MW		 4898 case I40E_LINK_SPEED_100MB:
4899 strncpy(speed, "100 Mbps", SPEED_SIZE);
4900 break;
cf05ed08
JB		 4901 default:
4902 break;
4903 }
4904
4905 switch (vsi->back->hw.fc.current_mode) {
4906 case I40E_FC_FULL:
35a7d804 4907 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4908 break;
4909 case I40E_FC_TX_PAUSE:
35a7d804 4910 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4911 break;
4912 case I40E_FC_RX_PAUSE:
35a7d804 4913 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4914 break;
4915 default:
35a7d804 4916 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4917 break;
4918 }
4919
4920 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4921 speed, fc);
4922}
4e3b35b0 4923
41c445ff
JB		 4924/**
4925 * i40e_up_complete - Finish the last steps of bringing up a connection
4926 * @vsi: the VSI being configured
4927 **/
4928static int i40e_up_complete(struct i40e_vsi *vsi)
4929{
4930 struct i40e_pf *pf = vsi->back;
4931 int err;
4932
4933 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4934 i40e_vsi_configure_msix(vsi);
4935 else
4936 i40e_configure_msi_and_legacy(vsi);
4937
4938 /* start rings */
4939 err = i40e_vsi_control_rings(vsi, true);
4940 if (err)
4941 return err;
4942
4943 clear_bit(__I40E_DOWN, &vsi->state);
4944 i40e_napi_enable_all(vsi);
4945 i40e_vsi_enable_irq(vsi);
4946
4947 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4948 (vsi->netdev)) {
cf05ed08 4949 i40e_print_link_message(vsi, true);
41c445ff
JB		 4950 netif_tx_start_all_queues(vsi->netdev);
4951 netif_carrier_on(vsi->netdev);
6d779b41 4952 } else if (vsi->netdev) {
cf05ed08 4953 i40e_print_link_message(vsi, false);
7b592f61
CW		 4954 /* need to check for qualified module here*/
4955 if ((pf->hw.phy.link_info.link_info &
4956 I40E_AQ_MEDIA_AVAILABLE) &&
4957 (!(pf->hw.phy.link_info.an_info &
4958 I40E_AQ_QUALIFIED_MODULE)))
4959 netdev_err(vsi->netdev,
4960 "the driver failed to link because an unqualified module was detected.");
41c445ff 4961 }
ca64fa4e
ASJ		 4962
4963 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4964 if (vsi->type == I40E_VSI_FDIR) {
4965 /* reset fd counters */
4966 pf->fd_add_err = pf->fd_atr_cnt = 0;
4967 if (pf->fd_tcp_rule > 0) {
4968 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 4969 if (I40E_DEBUG_FD & pf->hw.debug_mask)
4970 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 4971 pf->fd_tcp_rule = 0;
4972 }
ca64fa4e 4973 i40e_fdir_filter_restore(vsi);
1e1be8f6 4974 }
41c445ff
JB		 4975 i40e_service_event_schedule(pf);
4976
4977 return 0;
4978}
4979
4980/**
4981 * i40e_vsi_reinit_locked - Reset the VSI
4982 * @vsi: the VSI being configured
4983 *
4984 * Rebuild the ring structs after some configuration
4985 * has changed, e.g. MTU size.
4986 **/
4987static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4988{
4989 struct i40e_pf *pf = vsi->back;
4990
4991 WARN_ON(in_interrupt());
4992 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4993 usleep_range(1000, 2000);
4994 i40e_down(vsi);
4995
4996 /* Give a VF some time to respond to the reset. The
4997 * two second wait is based upon the watchdog cycle in
4998 * the VF driver.
4999 */
5000 if (vsi->type == I40E_VSI_SRIOV)
5001 msleep(2000);
5002 i40e_up(vsi);
5003 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5004}
5005
5006/**
5007 * i40e_up - Bring the connection back up after being down
5008 * @vsi: the VSI being configured
5009 **/
5010int i40e_up(struct i40e_vsi *vsi)
5011{
5012 int err;
5013
5014 err = i40e_vsi_configure(vsi);
5015 if (!err)
5016 err = i40e_up_complete(vsi);
5017
5018 return err;
5019}
5020
5021/**
5022 * i40e_down - Shutdown the connection processing
5023 * @vsi: the VSI being stopped
5024 **/
5025void i40e_down(struct i40e_vsi *vsi)
5026{
5027 int i;
5028
5029 /* It is assumed that the caller of this function
5030 * sets the vsi->state __I40E_DOWN bit.
5031 */
5032 if (vsi->netdev) {
5033 netif_carrier_off(vsi->netdev);
5034 netif_tx_disable(vsi->netdev);
5035 }
5036 i40e_vsi_disable_irq(vsi);
5037 i40e_vsi_control_rings(vsi, false);
5038 i40e_napi_disable_all(vsi);
5039
5040 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5041 i40e_clean_tx_ring(vsi->tx_rings[i]);
5042 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5043 }
5044}
5045
5046/**
5047 * i40e_setup_tc - configure multiple traffic classes
5048 * @netdev: net device to configure
5049 * @tc: number of traffic classes to enable
5050 **/
38e00438
VD		 5051#ifdef I40E_FCOE
5052int i40e_setup_tc(struct net_device *netdev, u8 tc)
5053#else
41c445ff 5054static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5055#endif
41c445ff
JB		 5056{
5057 struct i40e_netdev_priv *np = netdev_priv(netdev);
5058 struct i40e_vsi *vsi = np->vsi;
5059 struct i40e_pf *pf = vsi->back;
5060 u8 enabled_tc = 0;
5061 int ret = -EINVAL;
5062 int i;
5063
5064 /* Check if DCB enabled to continue */
5065 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5066 netdev_info(netdev, "DCB is not enabled for adapter\n");
5067 goto exit;
5068 }
5069
5070 /* Check if MFP enabled */
5071 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5072 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5073 goto exit;
5074 }
5075
5076 /* Check whether tc count is within enabled limit */
5077 if (tc > i40e_pf_get_num_tc(pf)) {
5078 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5079 goto exit;
5080 }
5081
5082 /* Generate TC map for number of tc requested */
5083 for (i = 0; i < tc; i++)
41a1d04b 5084 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5085
5086 /* Requesting same TC configuration as already enabled */
5087 if (enabled_tc == vsi->tc_config.enabled_tc)
5088 return 0;
5089
5090 /* Quiesce VSI queues */
5091 i40e_quiesce_vsi(vsi);
5092
5093 /* Configure VSI for enabled TCs */
5094 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5095 if (ret) {
5096 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5097 vsi->seid);
5098 goto exit;
5099 }
5100
5101 /* Unquiesce VSI */
5102 i40e_unquiesce_vsi(vsi);
5103
5104exit:
5105 return ret;
5106}
5107
5108/**
5109 * i40e_open - Called when a network interface is made active
5110 * @netdev: network interface device structure
5111 *
5112 * The open entry point is called when a network interface is made
5113 * active by the system (IFF_UP). At this point all resources needed
5114 * for transmit and receive operations are allocated, the interrupt
5115 * handler is registered with the OS, the netdev watchdog subtask is
5116 * enabled, and the stack is notified that the interface is ready.
5117 *
5118 * Returns 0 on success, negative value on failure
5119 **/
38e00438 5120int i40e_open(struct net_device *netdev)
41c445ff
JB		 5121{
5122 struct i40e_netdev_priv *np = netdev_priv(netdev);
5123 struct i40e_vsi *vsi = np->vsi;
5124 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5125 int err;
5126
4eb3f768
SN		 5127 /* disallow open during test or if eeprom is broken */
5128 if (test_bit(__I40E_TESTING, &pf->state) ||
5129 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5130 return -EBUSY;
5131
5132 netif_carrier_off(netdev);
5133
6c167f58
EK		 5134 err = i40e_vsi_open(vsi);
5135 if (err)
5136 return err;
5137
059dab69
JB		 5138 /* configure global TSO hardware offload settings */
5139 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5140 TCP_FLAG_FIN) >> 16);
5141 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5142 TCP_FLAG_FIN |
5143 TCP_FLAG_CWR) >> 16);
5144 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5145
6c167f58
EK		 5146#ifdef CONFIG_I40E_VXLAN
5147 vxlan_get_rx_port(netdev);
5148#endif
5149
5150 return 0;
5151}
5152
5153/**
5154 * i40e_vsi_open -
5155 * @vsi: the VSI to open
5156 *
5157 * Finish initialization of the VSI.
5158 *
5159 * Returns 0 on success, negative value on failure
5160 **/
5161int i40e_vsi_open(struct i40e_vsi *vsi)
5162{
5163 struct i40e_pf *pf = vsi->back;
b294ac70 5164 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5165 int err;
5166
41c445ff
JB		 5167 /* allocate descriptors */
5168 err = i40e_vsi_setup_tx_resources(vsi);
5169 if (err)
5170 goto err_setup_tx;
5171 err = i40e_vsi_setup_rx_resources(vsi);
5172 if (err)
5173 goto err_setup_rx;
5174
5175 err = i40e_vsi_configure(vsi);
5176 if (err)
5177 goto err_setup_rx;
5178
c22e3c6c
SN		 5179 if (vsi->netdev) {
5180 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5181 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5182 err = i40e_vsi_request_irq(vsi, int_name);
5183 if (err)
5184 goto err_setup_rx;
41c445ff 5185
c22e3c6c
SN		 5186 /* Notify the stack of the actual queue counts. */
5187 err = netif_set_real_num_tx_queues(vsi->netdev,
5188 vsi->num_queue_pairs);
5189 if (err)
5190 goto err_set_queues;
25946ddb 5191
c22e3c6c
SN		 5192 err = netif_set_real_num_rx_queues(vsi->netdev,
5193 vsi->num_queue_pairs);
5194 if (err)
5195 goto err_set_queues;
8a9eb7d3
SN		 5196
5197 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5198 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5199 dev_driver_string(&pf->pdev->dev),
5200 dev_name(&pf->pdev->dev));
8a9eb7d3 5201 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5202
c22e3c6c 5203 } else {
ce9ccb17 5204 err = -EINVAL;
6c167f58
EK		 5205 goto err_setup_rx;
5206 }
25946ddb 5207
41c445ff
JB		 5208 err = i40e_up_complete(vsi);
5209 if (err)
5210 goto err_up_complete;
5211
41c445ff
JB		 5212 return 0;
5213
5214err_up_complete:
5215 i40e_down(vsi);
25946ddb 5216err_set_queues:
41c445ff
JB		 5217 i40e_vsi_free_irq(vsi);
5218err_setup_rx:
5219 i40e_vsi_free_rx_resources(vsi);
5220err_setup_tx:
5221 i40e_vsi_free_tx_resources(vsi);
5222 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5223 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5224
5225 return err;
5226}
5227
17a73f6b
JG		 5228/**
5229 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5230 * @pf: Pointer to PF
17a73f6b
JG		 5231 *
5232 * This function destroys the hlist where all the Flow Director
5233 * filters were saved.
5234 **/
5235static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5236{
5237 struct i40e_fdir_filter *filter;
5238 struct hlist_node *node2;
5239
5240 hlist_for_each_entry_safe(filter, node2,
5241 &pf->fdir_filter_list, fdir_node) {
5242 hlist_del(&filter->fdir_node);
5243 kfree(filter);
5244 }
5245 pf->fdir_pf_active_filters = 0;
5246}
5247
41c445ff
JB		 5248/**
5249 * i40e_close - Disables a network interface
5250 * @netdev: network interface device structure
5251 *
5252 * The close entry point is called when an interface is de-activated
5253 * by the OS. The hardware is still under the driver's control, but
5254 * this netdev interface is disabled.
5255 *
5256 * Returns 0, this is not allowed to fail
5257 **/
38e00438
VD		 5258#ifdef I40E_FCOE
5259int i40e_close(struct net_device *netdev)
5260#else
41c445ff 5261static int i40e_close(struct net_device *netdev)
38e00438 5262#endif
41c445ff
JB		 5263{
5264 struct i40e_netdev_priv *np = netdev_priv(netdev);
5265 struct i40e_vsi *vsi = np->vsi;
5266
90ef8d47 5267 i40e_vsi_close(vsi);
41c445ff
JB		 5268
5269 return 0;
5270}
5271
5272/**
5273 * i40e_do_reset - Start a PF or Core Reset sequence
5274 * @pf: board private structure
5275 * @reset_flags: which reset is requested
5276 *
5277 * The essential difference in resets is that the PF Reset
5278 * doesn't clear the packet buffers, doesn't reset the PE
5279 * firmware, and doesn't bother the other PFs on the chip.
5280 **/
5281void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5282{
5283 u32 val;
5284
5285 WARN_ON(in_interrupt());
5286
263fc48f
MW		 5287 if (i40e_check_asq_alive(&pf->hw))
5288 i40e_vc_notify_reset(pf);
5289
41c445ff 5290 /* do the biggest reset indicated */
41a1d04b 5291 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5292
5293 /* Request a Global Reset
5294 *
5295 * This will start the chip's countdown to the actual full
5296 * chip reset event, and a warning interrupt to be sent
5297 * to all PFs, including the requestor. Our handler
5298 * for the warning interrupt will deal with the shutdown
5299 * and recovery of the switch setup.
5300 */
69bfb110 5301 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5302 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5303 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5304 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5305
41a1d04b 5306 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5307
5308 /* Request a Core Reset
5309 *
5310 * Same as Global Reset, except does *not* include the MAC/PHY
5311 */
69bfb110 5312 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5313 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5314 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5315 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5316 i40e_flush(&pf->hw);
5317
41a1d04b 5318 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5319
5320 /* Request a PF Reset
5321 *
5322 * Resets only the PF-specific registers
5323 *
5324 * This goes directly to the tear-down and rebuild of
5325 * the switch, since we need to do all the recovery as
5326 * for the Core Reset.
5327 */
69bfb110 5328 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5329 i40e_handle_reset_warning(pf);
5330
41a1d04b 5331 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5332 int v;
5333
5334 /* Find the VSI(s) that requested a re-init */
5335 dev_info(&pf->pdev->dev,
5336 "VSI reinit requested\n");
505682cd 5337 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5338 struct i40e_vsi *vsi = pf->vsi[v];
5339 if (vsi != NULL &&
5340 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5341 i40e_vsi_reinit_locked(pf->vsi[v]);
5342 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5343 }
5344 }
5345
b5d06f05
NP		 5346 /* no further action needed, so return now */
5347 return;
41a1d04b 5348 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5349 int v;
5350
5351 /* Find the VSI(s) that needs to be brought down */
5352 dev_info(&pf->pdev->dev, "VSI down requested\n");
5353 for (v = 0; v < pf->num_alloc_vsi; v++) {
5354 struct i40e_vsi *vsi = pf->vsi[v];
5355 if (vsi != NULL &&
5356 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5357 set_bit(__I40E_DOWN, &vsi->state);
5358 i40e_down(vsi);
5359 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5360 }
5361 }
5362
41c445ff
JB		 5363 /* no further action needed, so return now */
5364 return;
5365 } else {
5366 dev_info(&pf->pdev->dev,
5367 "bad reset request 0x%08x\n", reset_flags);
5368 return;
5369 }
5370}
5371
4e3b35b0
NP		 5372#ifdef CONFIG_I40E_DCB
5373/**
5374 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5375 * @pf: board private structure
5376 * @old_cfg: current DCB config
5377 * @new_cfg: new DCB config
5378 **/
5379bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5380 struct i40e_dcbx_config *old_cfg,
5381 struct i40e_dcbx_config *new_cfg)
5382{
5383 bool need_reconfig = false;
5384
5385 /* Check if ETS configuration has changed */
5386 if (memcmp(&new_cfg->etscfg,
5387 &old_cfg->etscfg,
5388 sizeof(new_cfg->etscfg))) {
5389 /* If Priority Table has changed reconfig is needed */
5390 if (memcmp(&new_cfg->etscfg.prioritytable,
5391 &old_cfg->etscfg.prioritytable,
5392 sizeof(new_cfg->etscfg.prioritytable))) {
5393 need_reconfig = true;
69bfb110 5394 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5395 }
5396
5397 if (memcmp(&new_cfg->etscfg.tcbwtable,
5398 &old_cfg->etscfg.tcbwtable,
5399 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5400 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5401
5402 if (memcmp(&new_cfg->etscfg.tsatable,
5403 &old_cfg->etscfg.tsatable,
5404 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5405 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5406 }
5407
5408 /* Check if PFC configuration has changed */
5409 if (memcmp(&new_cfg->pfc,
5410 &old_cfg->pfc,
5411 sizeof(new_cfg->pfc))) {
5412 need_reconfig = true;
69bfb110 5413 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5414 }
5415
5416 /* Check if APP Table has changed */
5417 if (memcmp(&new_cfg->app,
5418 &old_cfg->app,
3d9667a9 5419 sizeof(new_cfg->app))) {
4e3b35b0 5420 need_reconfig = true;
69bfb110 5421 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5422 }
4e3b35b0 5423
9fa61dd2
NP		 5424 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5425 need_reconfig);
4e3b35b0
NP		 5426 return need_reconfig;
5427}
5428
5429/**
5430 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5431 * @pf: board private structure
5432 * @e: event info posted on ARQ
5433 **/
5434static int i40e_handle_lldp_event(struct i40e_pf *pf,
5435 struct i40e_arq_event_info *e)
5436{
5437 struct i40e_aqc_lldp_get_mib *mib =
5438 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5439 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5440 struct i40e_dcbx_config tmp_dcbx_cfg;
5441 bool need_reconfig = false;
5442 int ret = 0;
5443 u8 type;
5444
4d9b6043
NP		 5445 /* Not DCB capable or capability disabled */
5446 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5447 return ret;
5448
4e3b35b0
NP		 5449 /* Ignore if event is not for Nearest Bridge */
5450 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5451 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5452 dev_dbg(&pf->pdev->dev,
5453 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5454 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5455 return ret;
5456
5457 /* Check MIB Type and return if event for Remote MIB update */
5458 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5459 dev_dbg(&pf->pdev->dev,
5460 "%s: LLDP event mib type %s\n", __func__,
5461 type ? "remote" : "local");
4e3b35b0
NP		 5462 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5463 /* Update the remote cached instance and return */
5464 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5465 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5466 &hw->remote_dcbx_config);
5467 goto exit;
5468 }
5469
9fa61dd2 5470 /* Store the old configuration */
1a2f6248 5471 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5472
750fcbcf
NP		 5473 /* Reset the old DCBx configuration data */
5474 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5475 /* Get updated DCBX data from firmware */
5476 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5477 if (ret) {
f1c7e72e
SN		 5478 dev_info(&pf->pdev->dev,
5479 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5480 i40e_stat_str(&pf->hw, ret),
5481 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5482 goto exit;
5483 }
5484
5485 /* No change detected in DCBX configs */
750fcbcf
NP		 5486 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5487 sizeof(tmp_dcbx_cfg))) {
69bfb110 5488 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5489 goto exit;
5490 }
5491
750fcbcf
NP		 5492 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5493 &hw->local_dcbx_config);
4e3b35b0 5494
750fcbcf 5495 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5496
5497 if (!need_reconfig)
5498 goto exit;
5499
4d9b6043 5500 /* Enable DCB tagging only when more than one TC */
750fcbcf 5501 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5502 pf->flags |= I40E_FLAG_DCB_ENABLED;
5503 else
5504 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5505
69129dc3 5506 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5507 /* Reconfiguration needed quiesce all VSIs */
5508 i40e_pf_quiesce_all_vsi(pf);
5509
5510 /* Changes in configuration update VEB/VSI */
5511 i40e_dcb_reconfigure(pf);
5512
2fd75f31
NP		 5513 ret = i40e_resume_port_tx(pf);
5514
69129dc3 5515 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5516 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5517 if (ret)
5518 goto exit;
5519
5520 /* Wait for the PF's Tx queues to be disabled */
5521 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5522 if (ret) {
5523 /* Schedule PF reset to recover */
5524 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5525 i40e_service_event_schedule(pf);
5526 } else {
2fd75f31 5527 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5528 }
5529
4e3b35b0
NP		 5530exit:
5531 return ret;
5532}
5533#endif /* CONFIG_I40E_DCB */
5534
23326186
ASJ		 5535/**
5536 * i40e_do_reset_safe - Protected reset path for userland calls.
5537 * @pf: board private structure
5538 * @reset_flags: which reset is requested
5539 *
5540 **/
5541void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5542{
5543 rtnl_lock();
5544 i40e_do_reset(pf, reset_flags);
5545 rtnl_unlock();
5546}
5547
41c445ff
JB		 5548/**
5549 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5550 * @pf: board private structure
5551 * @e: event info posted on ARQ
5552 *
5553 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5554 * and VF queues
5555 **/
5556static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5557 struct i40e_arq_event_info *e)
5558{
5559 struct i40e_aqc_lan_overflow *data =
5560 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5561 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5562 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5563 struct i40e_hw *hw = &pf->hw;
5564 struct i40e_vf *vf;
5565 u16 vf_id;
5566
69bfb110
JB		 5567 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5568 queue, qtx_ctl);
41c445ff
JB		 5569
5570 /* Queue belongs to VF, find the VF and issue VF reset */
5571 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5572 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5573 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5574 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5575 vf_id -= hw->func_caps.vf_base_id;
5576 vf = &pf->vf[vf_id];
5577 i40e_vc_notify_vf_reset(vf);
5578 /* Allow VF to process pending reset notification */
5579 msleep(20);
5580 i40e_reset_vf(vf, false);
5581 }
5582}
5583
5584/**
5585 * i40e_service_event_complete - Finish up the service event
5586 * @pf: board private structure
5587 **/
5588static void i40e_service_event_complete(struct i40e_pf *pf)
5589{
5590 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5591
5592 /* flush memory to make sure state is correct before next watchog */
4e857c58 5593 smp_mb__before_atomic();
41c445ff
JB		 5594 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5595}
5596
55a5e60b 5597/**
12957388
ASJ		 5598 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5599 * @pf: board private structure
5600 **/
04294e38 5601u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5602{
04294e38 5603 u32 val, fcnt_prog;
12957388
ASJ		 5604
5605 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5606 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5607 return fcnt_prog;
5608}
5609
5610/**
04294e38 5611 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5612 * @pf: board private structure
5613 **/
04294e38 5614u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5615{
04294e38
ASJ		 5616 u32 val, fcnt_prog;
5617
55a5e60b
ASJ		 5618 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5619 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5620 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5621 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5622 return fcnt_prog;
5623}
1e1be8f6 5624
04294e38
ASJ		 5625/**
5626 * i40e_get_global_fd_count - Get total FD filters programmed on device
5627 * @pf: board private structure
5628 **/
5629u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5630{
5631 u32 val, fcnt_prog;
5632
5633 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5634 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5635 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5636 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5637 return fcnt_prog;
5638}
5639
55a5e60b
ASJ		 5640/**
5641 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5642 * @pf: board private structure
5643 **/
5644void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5645{
5646 u32 fcnt_prog, fcnt_avail;
5647
1e1be8f6
ASJ		 5648 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5649 return;
5650
55a5e60b
ASJ		 5651 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5652 * to re-enable
5653 */
04294e38 5654 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5655 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5656 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5657 (pf->fd_add_err == 0) ||
5658 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5659 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5660 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5661 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5662 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5663 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5664 }
5665 }
5666 /* Wait for some more space to be available to turn on ATR */
5667 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5668 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5669 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5670 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5671 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5672 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5673 }
5674 }
5675}
5676
1e1be8f6 5677#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5678#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5679/**
5680 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5681 * @pf: board private structure
5682 **/
5683static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5684{
04294e38 5685 unsigned long min_flush_time;
1e1be8f6 5686 int flush_wait_retry = 50;
04294e38
ASJ		 5687 bool disable_atr = false;
5688 int fd_room;
1e1be8f6
ASJ		 5689 int reg;
5690
1790ed0c
AA		 5691 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5692 return;
5693
1e1be8f6
ASJ		 5694 if (time_after(jiffies, pf->fd_flush_timestamp +
5695 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
04294e38
ASJ		 5696 /* If the flush is happening too quick and we have mostly
5697 * SB rules we should not re-enable ATR for some time.
5698 */
5699 min_flush_time = pf->fd_flush_timestamp
5700 + (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5701 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5702
5703 if (!(time_after(jiffies, min_flush_time)) &&
5704 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
2e4875e3
ASJ		 5705 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5706 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
04294e38
ASJ		 5707 disable_atr = true;
5708 }
5709
1e1be8f6 5710 pf->fd_flush_timestamp = jiffies;
1e1be8f6
ASJ		 5711 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5712 /* flush all filters */
5713 wr32(&pf->hw, I40E_PFQF_CTL_1,
5714 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5715 i40e_flush(&pf->hw);
60793f4a 5716 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5717 pf->fd_add_err = 0;
5718 do {
5719 /* Check FD flush status every 5-6msec */
5720 usleep_range(5000, 6000);
5721 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5722 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5723 break;
5724 } while (flush_wait_retry--);
5725 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5726 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5727 } else {
5728 /* replay sideband filters */
5729 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
04294e38
ASJ		 5730 if (!disable_atr)
5731 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
1e1be8f6 5732 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
2e4875e3
ASJ		 5733 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5734 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6
ASJ		 5735 }
5736 }
5737}
5738
5739/**
5740 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5741 * @pf: board private structure
5742 **/
04294e38 5743u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5744{
5745 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5746}
5747
5748/* We can see up to 256 filter programming desc in transit if the filters are
5749 * being applied really fast; before we see the first
5750 * filter miss error on Rx queue 0. Accumulating enough error messages before
5751 * reacting will make sure we don't cause flush too often.
5752 */
5753#define I40E_MAX_FD_PROGRAM_ERROR 256
5754
41c445ff
JB		 5755/**
5756 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5757 * @pf: board private structure
5758 **/
5759static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5760{
41c445ff 5761
41c445ff
JB		 5762 /* if interface is down do nothing */
5763 if (test_bit(__I40E_DOWN, &pf->state))
5764 return;
1e1be8f6 5765
1790ed0c
AA		 5766 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5767 return;
5768
04294e38 5769 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5770 i40e_fdir_flush_and_replay(pf);
5771
55a5e60b
ASJ		 5772 i40e_fdir_check_and_reenable(pf);
5773
41c445ff
JB		 5774}
5775
5776/**
5777 * i40e_vsi_link_event - notify VSI of a link event
5778 * @vsi: vsi to be notified
5779 * @link_up: link up or down
5780 **/
5781static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5782{
32b5b811 5783 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5784 return;
5785
5786 switch (vsi->type) {
5787 case I40E_VSI_MAIN:
38e00438
VD		 5788#ifdef I40E_FCOE
5789 case I40E_VSI_FCOE:
5790#endif
41c445ff
JB		 5791 if (!vsi->netdev || !vsi->netdev_registered)
5792 break;
5793
5794 if (link_up) {
5795 netif_carrier_on(vsi->netdev);
5796 netif_tx_wake_all_queues(vsi->netdev);
5797 } else {
5798 netif_carrier_off(vsi->netdev);
5799 netif_tx_stop_all_queues(vsi->netdev);
5800 }
5801 break;
5802
5803 case I40E_VSI_SRIOV:
41c445ff
JB		 5804 case I40E_VSI_VMDQ2:
5805 case I40E_VSI_CTRL:
5806 case I40E_VSI_MIRROR:
5807 default:
5808 /* there is no notification for other VSIs */
5809 break;
5810 }
5811}
5812
5813/**
5814 * i40e_veb_link_event - notify elements on the veb of a link event
5815 * @veb: veb to be notified
5816 * @link_up: link up or down
5817 **/
5818static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5819{
5820 struct i40e_pf *pf;
5821 int i;
5822
5823 if (!veb || !veb->pf)
5824 return;
5825 pf = veb->pf;
5826
5827 /* depth first... */
5828 for (i = 0; i < I40E_MAX_VEB; i++)
5829 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5830 i40e_veb_link_event(pf->veb[i], link_up);
5831
5832 /* ... now the local VSIs */
505682cd 5833 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5834 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5835 i40e_vsi_link_event(pf->vsi[i], link_up);
5836}
5837
5838/**
5839 * i40e_link_event - Update netif_carrier status
5840 * @pf: board private structure
5841 **/
5842static void i40e_link_event(struct i40e_pf *pf)
5843{
5844 bool new_link, old_link;
320684cd 5845 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5846 u8 new_link_speed, old_link_speed;
41c445ff 5847
1e701e09
JB		 5848 /* set this to force the get_link_status call to refresh state */
5849 pf->hw.phy.get_link_info = true;
5850
41c445ff 5851 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5852 new_link = i40e_get_link_status(&pf->hw);
fef59ddf
CS		 5853 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5854 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5855
1e701e09 5856 if (new_link == old_link &&
fef59ddf 5857 new_link_speed == old_link_speed &&
320684cd
MW		 5858 (test_bit(__I40E_DOWN, &vsi->state) ||
5859 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5860 return;
320684cd
MW		 5861
5862 if (!test_bit(__I40E_DOWN, &vsi->state))
5863 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5864
5865 /* Notify the base of the switch tree connected to
5866 * the link. Floating VEBs are not notified.
5867 */
5868 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5869 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5870 else
320684cd 5871 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5872
5873 if (pf->vf)
5874 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5875
5876 if (pf->flags & I40E_FLAG_PTP)
5877 i40e_ptp_set_increment(pf);
41c445ff
JB		 5878}
5879
41c445ff 5880/**
21536717 5881 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5882 * @pf: board private structure
5883 **/
5884static void i40e_watchdog_subtask(struct i40e_pf *pf)
5885{
5886 int i;
5887
5888 /* if interface is down do nothing */
5889 if (test_bit(__I40E_DOWN, &pf->state) ||
5890 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5891 return;
5892
21536717
SN		 5893 /* make sure we don't do these things too often */
5894 if (time_before(jiffies, (pf->service_timer_previous +
5895 pf->service_timer_period)))
5896 return;
5897 pf->service_timer_previous = jiffies;
5898
21536717
SN		 5899 i40e_link_event(pf);
5900
41c445ff
JB		 5901 /* Update the stats for active netdevs so the network stack
5902 * can look at updated numbers whenever it cares to
5903 */
505682cd 5904 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5905 if (pf->vsi[i] && pf->vsi[i]->netdev)
5906 i40e_update_stats(pf->vsi[i]);
5907
5908 /* Update the stats for the active switching components */
5909 for (i = 0; i < I40E_MAX_VEB; i++)
5910 if (pf->veb[i])
5911 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5912
5913 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5914}
5915
5916/**
5917 * i40e_reset_subtask - Set up for resetting the device and driver
5918 * @pf: board private structure
5919 **/
5920static void i40e_reset_subtask(struct i40e_pf *pf)
5921{
5922 u32 reset_flags = 0;
5923
23326186 5924 rtnl_lock();
41c445ff 5925 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 5926 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 5927 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5928 }
5929 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 5930 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 5931 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5932 }
5933 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 5934 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 5935 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5936 }
5937 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 5938 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 5939 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5940 }
b5d06f05 5941 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 5942 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 5943 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5944 }
41c445ff
JB		 5945
5946 /* If there's a recovery already waiting, it takes
5947 * precedence before starting a new reset sequence.
5948 */
5949 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5950 i40e_handle_reset_warning(pf);
23326186 5951 goto unlock;
41c445ff
JB		 5952 }
5953
5954 /* If we're already down or resetting, just bail */
5955 if (reset_flags &&
5956 !test_bit(__I40E_DOWN, &pf->state) &&
5957 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5958 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5959
5960unlock:
5961 rtnl_unlock();
41c445ff
JB		 5962}
5963
5964/**
5965 * i40e_handle_link_event - Handle link event
5966 * @pf: board private structure
5967 * @e: event info posted on ARQ
5968 **/
5969static void i40e_handle_link_event(struct i40e_pf *pf,
5970 struct i40e_arq_event_info *e)
5971{
5972 struct i40e_hw *hw = &pf->hw;
5973 struct i40e_aqc_get_link_status *status =
5974 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff
JB		 5975
5976 /* save off old link status information */
1a2f6248 5977 hw->phy.link_info_old = hw->phy.link_info;
41c445ff 5978
1e701e09
JB		 5979 /* Do a new status request to re-enable LSE reporting
5980 * and load new status information into the hw struct
5981 * This completely ignores any state information
5982 * in the ARQ event info, instead choosing to always
5983 * issue the AQ update link status command.
5984 */
5985 i40e_link_event(pf);
5986
7b592f61
CW		 5987 /* check for unqualified module, if link is down */
5988 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5989 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5990 (!(status->link_info & I40E_AQ_LINK_UP)))
5991 dev_err(&pf->pdev->dev,
5992 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5993}
5994
5995/**
5996 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5997 * @pf: board private structure
5998 **/
5999static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6000{
6001 struct i40e_arq_event_info event;
6002 struct i40e_hw *hw = &pf->hw;
6003 u16 pending, i = 0;
6004 i40e_status ret;
6005 u16 opcode;
86df242b 6006 u32 oldval;
41c445ff
JB		 6007 u32 val;
6008
a316f651
ASJ		 6009 /* Do not run clean AQ when PF reset fails */
6010 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6011 return;
6012
86df242b
SN		 6013 /* check for error indications */
6014 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6015 oldval = val;
6016 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6017 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6018 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6019 }
6020 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6021 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6022 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6023 }
6024 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6025 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6026 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6027 }
6028 if (oldval != val)
6029 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6030
6031 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6032 oldval = val;
6033 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6034 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6035 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6036 }
6037 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6038 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6039 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6040 }
6041 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6042 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6043 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6044 }
6045 if (oldval != val)
6046 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6047
1001dc37
MW		 6048 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6049 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6050 if (!event.msg_buf)
6051 return;
6052
6053 do {
6054 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6055 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6056 break;
56497978 6057 else if (ret) {
41c445ff
JB		 6058 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6059 break;
6060 }
6061
6062 opcode = le16_to_cpu(event.desc.opcode);
6063 switch (opcode) {
6064
6065 case i40e_aqc_opc_get_link_status:
6066 i40e_handle_link_event(pf, &event);
6067 break;
6068 case i40e_aqc_opc_send_msg_to_pf:
6069 ret = i40e_vc_process_vf_msg(pf,
6070 le16_to_cpu(event.desc.retval),
6071 le32_to_cpu(event.desc.cookie_high),
6072 le32_to_cpu(event.desc.cookie_low),
6073 event.msg_buf,
1001dc37 6074 event.msg_len);
41c445ff
JB		 6075 break;
6076 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6077 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6078#ifdef CONFIG_I40E_DCB
6079 rtnl_lock();
6080 ret = i40e_handle_lldp_event(pf, &event);
6081 rtnl_unlock();
6082#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6083 break;
6084 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6085 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6086 i40e_handle_lan_overflow_event(pf, &event);
6087 break;
0467bc91
SN		 6088 case i40e_aqc_opc_send_msg_to_peer:
6089 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6090 break;
91a0f930
SN		 6091 case i40e_aqc_opc_nvm_erase:
6092 case i40e_aqc_opc_nvm_update:
6093 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6094 break;
41c445ff
JB		 6095 default:
6096 dev_info(&pf->pdev->dev,
0467bc91
SN		 6097 "ARQ Error: Unknown event 0x%04x received\n",
6098 opcode);
41c445ff
JB		 6099 break;
6100 }
6101 } while (pending && (i++ < pf->adminq_work_limit));
6102
6103 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6104 /* re-enable Admin queue interrupt cause */
6105 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6106 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6107 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6108 i40e_flush(hw);
6109
6110 kfree(event.msg_buf);
6111}
6112
4eb3f768
SN		 6113/**
6114 * i40e_verify_eeprom - make sure eeprom is good to use
6115 * @pf: board private structure
6116 **/
6117static void i40e_verify_eeprom(struct i40e_pf *pf)
6118{
6119 int err;
6120
6121 err = i40e_diag_eeprom_test(&pf->hw);
6122 if (err) {
6123 /* retry in case of garbage read */
6124 err = i40e_diag_eeprom_test(&pf->hw);
6125 if (err) {
6126 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6127 err);
6128 set_bit(__I40E_BAD_EEPROM, &pf->state);
6129 }
6130 }
6131
6132 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6133 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6134 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6135 }
6136}
6137
386a0afa
AA		 6138/**
6139 * i40e_enable_pf_switch_lb
b40c82e6 6140 * @pf: pointer to the PF structure
386a0afa
AA		 6141 *
6142 * enable switch loop back or die - no point in a return value
6143 **/
6144static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6145{
6146 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6147 struct i40e_vsi_context ctxt;
f1c7e72e 6148 int ret;
386a0afa
AA		 6149
6150 ctxt.seid = pf->main_vsi_seid;
6151 ctxt.pf_num = pf->hw.pf_id;
6152 ctxt.vf_num = 0;
f1c7e72e
SN		 6153 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6154 if (ret) {
386a0afa 6155 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6156 "couldn't get PF vsi config, err %s aq_err %s\n",
6157 i40e_stat_str(&pf->hw, ret),
6158 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6159 return;
6160 }
6161 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6162 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6163 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6164
f1c7e72e
SN		 6165 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6166 if (ret) {
386a0afa 6167 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6168 "update vsi switch failed, err %s aq_err %s\n",
6169 i40e_stat_str(&pf->hw, ret),
6170 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6171 }
6172}
6173
6174/**
6175 * i40e_disable_pf_switch_lb
b40c82e6 6176 * @pf: pointer to the PF structure
386a0afa
AA		 6177 *
6178 * disable switch loop back or die - no point in a return value
6179 **/
6180static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6181{
6182 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6183 struct i40e_vsi_context ctxt;
f1c7e72e 6184 int ret;
386a0afa
AA		 6185
6186 ctxt.seid = pf->main_vsi_seid;
6187 ctxt.pf_num = pf->hw.pf_id;
6188 ctxt.vf_num = 0;
f1c7e72e
SN		 6189 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6190 if (ret) {
386a0afa 6191 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6192 "couldn't get PF vsi config, err %s aq_err %s\n",
6193 i40e_stat_str(&pf->hw, ret),
6194 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6195 return;
6196 }
6197 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6198 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6199 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6200
f1c7e72e
SN		 6201 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6202 if (ret) {
386a0afa 6203 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6204 "update vsi switch failed, err %s aq_err %s\n",
6205 i40e_stat_str(&pf->hw, ret),
6206 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6207 }
6208}
6209
51616018
NP		 6210/**
6211 * i40e_config_bridge_mode - Configure the HW bridge mode
6212 * @veb: pointer to the bridge instance
6213 *
6214 * Configure the loop back mode for the LAN VSI that is downlink to the
6215 * specified HW bridge instance. It is expected this function is called
6216 * when a new HW bridge is instantiated.
6217 **/
6218static void i40e_config_bridge_mode(struct i40e_veb *veb)
6219{
6220 struct i40e_pf *pf = veb->pf;
6221
6222 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6223 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
6224 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6225 i40e_disable_pf_switch_lb(pf);
6226 else
6227 i40e_enable_pf_switch_lb(pf);
6228}
6229
41c445ff
JB		 6230/**
6231 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6232 * @veb: pointer to the VEB instance
6233 *
6234 * This is a recursive function that first builds the attached VSIs then
6235 * recurses in to build the next layer of VEB. We track the connections
6236 * through our own index numbers because the seid's from the HW could
6237 * change across the reset.
6238 **/
6239static int i40e_reconstitute_veb(struct i40e_veb *veb)
6240{
6241 struct i40e_vsi *ctl_vsi = NULL;
6242 struct i40e_pf *pf = veb->pf;
6243 int v, veb_idx;
6244 int ret;
6245
6246 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6247 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6248 if (pf->vsi[v] &&
6249 pf->vsi[v]->veb_idx == veb->idx &&
6250 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6251 ctl_vsi = pf->vsi[v];
6252 break;
6253 }
6254 }
6255 if (!ctl_vsi) {
6256 dev_info(&pf->pdev->dev,
6257 "missing owner VSI for veb_idx %d\n", veb->idx);
6258 ret = -ENOENT;
6259 goto end_reconstitute;
6260 }
6261 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6262 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6263 ret = i40e_add_vsi(ctl_vsi);
6264 if (ret) {
6265 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6266 "rebuild of veb_idx %d owner VSI failed: %d\n",
6267 veb->idx, ret);
41c445ff
JB		 6268 goto end_reconstitute;
6269 }
6270 i40e_vsi_reset_stats(ctl_vsi);
6271
6272 /* create the VEB in the switch and move the VSI onto the VEB */
6273 ret = i40e_add_veb(veb, ctl_vsi);
6274 if (ret)
6275 goto end_reconstitute;
6276
fc60861e
ASJ		 6277 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6278 veb->bridge_mode = BRIDGE_MODE_VEB;
6279 else
6280 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6281 i40e_config_bridge_mode(veb);
b64ba084 6282
41c445ff 6283 /* create the remaining VSIs attached to this VEB */
505682cd 6284 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6285 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6286 continue;
6287
6288 if (pf->vsi[v]->veb_idx == veb->idx) {
6289 struct i40e_vsi *vsi = pf->vsi[v];
6290 vsi->uplink_seid = veb->seid;
6291 ret = i40e_add_vsi(vsi);
6292 if (ret) {
6293 dev_info(&pf->pdev->dev,
6294 "rebuild of vsi_idx %d failed: %d\n",
6295 v, ret);
6296 goto end_reconstitute;
6297 }
6298 i40e_vsi_reset_stats(vsi);
6299 }
6300 }
6301
6302 /* create any VEBs attached to this VEB - RECURSION */
6303 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6304 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6305 pf->veb[veb_idx]->uplink_seid = veb->seid;
6306 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6307 if (ret)
6308 break;
6309 }
6310 }
6311
6312end_reconstitute:
6313 return ret;
6314}
6315
6316/**
6317 * i40e_get_capabilities - get info about the HW
6318 * @pf: the PF struct
6319 **/
6320static int i40e_get_capabilities(struct i40e_pf *pf)
6321{
6322 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6323 u16 data_size;
6324 int buf_len;
6325 int err;
6326
6327 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6328 do {
6329 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6330 if (!cap_buf)
6331 return -ENOMEM;
6332
6333 /* this loads the data into the hw struct for us */
6334 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6335 &data_size,
6336 i40e_aqc_opc_list_func_capabilities,
6337 NULL);
6338 /* data loaded, buffer no longer needed */
6339 kfree(cap_buf);
6340
6341 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6342 /* retry with a larger buffer */
6343 buf_len = data_size;
6344 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6345 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6346 "capability discovery failed, err %s aq_err %s\n",
6347 i40e_stat_str(&pf->hw, err),
6348 i40e_aq_str(&pf->hw,
6349 pf->hw.aq.asq_last_status));
41c445ff
JB		 6350 return -ENODEV;
6351 }
6352 } while (err);
6353
ac71b7ba
ASJ		 6354 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6355 (pf->hw.aq.fw_maj_ver < 2)) {
6356 pf->hw.func_caps.num_msix_vectors++;
6357 pf->hw.func_caps.num_msix_vectors_vf++;
6358 }
6359
41c445ff
JB		 6360 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6361 dev_info(&pf->pdev->dev,
6362 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6363 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6364 pf->hw.func_caps.num_msix_vectors,
6365 pf->hw.func_caps.num_msix_vectors_vf,
6366 pf->hw.func_caps.fd_filters_guaranteed,
6367 pf->hw.func_caps.fd_filters_best_effort,
6368 pf->hw.func_caps.num_tx_qp,
6369 pf->hw.func_caps.num_vsis);
6370
7134f9ce
JB		 6371#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6372 + pf->hw.func_caps.num_vfs)
6373 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6374 dev_info(&pf->pdev->dev,
6375 "got num_vsis %d, setting num_vsis to %d\n",
6376 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6377 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6378 }
6379
41c445ff
JB		 6380 return 0;
6381}
6382
cbf61325
ASJ		 6383static int i40e_vsi_clear(struct i40e_vsi *vsi);
6384
41c445ff 6385/**
cbf61325 6386 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6387 * @pf: board private structure
6388 **/
cbf61325 6389static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6390{
6391 struct i40e_vsi *vsi;
8a9eb7d3 6392 int i;
41c445ff 6393
407e063c
JB		 6394 /* quick workaround for an NVM issue that leaves a critical register
6395 * uninitialized
6396 */
6397 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6398 static const u32 hkey[] = {
6399 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6400 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6401 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6402 0x95b3a76d};
6403
6404 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6405 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6406 }
6407
cbf61325 6408 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6409 return;
6410
cbf61325 6411 /* find existing VSI and see if it needs configuring */
41c445ff 6412 vsi = NULL;
505682cd 6413 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6414 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6415 vsi = pf->vsi[i];
cbf61325
ASJ		 6416 break;
6417 }
6418 }
6419
6420 /* create a new VSI if none exists */
41c445ff 6421 if (!vsi) {
cbf61325
ASJ		 6422 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6423 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6424 if (!vsi) {
6425 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6426 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6427 return;
41c445ff 6428 }
cbf61325 6429 }
41c445ff 6430
8a9eb7d3 6431 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6432}
6433
6434/**
6435 * i40e_fdir_teardown - release the Flow Director resources
6436 * @pf: board private structure
6437 **/
6438static void i40e_fdir_teardown(struct i40e_pf *pf)
6439{
6440 int i;
6441
17a73f6b 6442 i40e_fdir_filter_exit(pf);
505682cd 6443 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6444 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6445 i40e_vsi_release(pf->vsi[i]);
6446 break;
6447 }
6448 }
6449}
6450
6451/**
f650a38b 6452 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6453 * @pf: board private structure
6454 *
b40c82e6 6455 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6456 **/
23cfbe07 6457static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6458{
41c445ff 6459 struct i40e_hw *hw = &pf->hw;
60442dea 6460 i40e_status ret = 0;
41c445ff
JB		 6461 u32 v;
6462
6463 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6464 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6465 return;
41c445ff 6466
69bfb110 6467 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6468
41c445ff
JB		 6469 /* quiesce the VSIs and their queues that are not already DOWN */
6470 i40e_pf_quiesce_all_vsi(pf);
6471
505682cd 6472 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6473 if (pf->vsi[v])
6474 pf->vsi[v]->seid = 0;
6475 }
6476
6477 i40e_shutdown_adminq(&pf->hw);
6478
f650a38b 6479 /* call shutdown HMC */
60442dea
SN		 6480 if (hw->hmc.hmc_obj) {
6481 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6482 if (ret)
60442dea
SN		 6483 dev_warn(&pf->pdev->dev,
6484 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6485 }
f650a38b
ASJ		 6486}
6487
44033fac
JB		 6488/**
6489 * i40e_send_version - update firmware with driver version
6490 * @pf: PF struct
6491 */
6492static void i40e_send_version(struct i40e_pf *pf)
6493{
6494 struct i40e_driver_version dv;
6495
6496 dv.major_version = DRV_VERSION_MAJOR;
6497 dv.minor_version = DRV_VERSION_MINOR;
6498 dv.build_version = DRV_VERSION_BUILD;
6499 dv.subbuild_version = 0;
35a7d804 6500 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6501 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6502}
6503
f650a38b 6504/**
4dda12e6 6505 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6506 * @pf: board private structure
bc7d338f 6507 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6508 **/
bc7d338f 6509static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6510{
f650a38b 6511 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6512 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6513 i40e_status ret;
6514 u32 v;
6515
41c445ff
JB		 6516 /* Now we wait for GRST to settle out.
6517 * We don't have to delete the VEBs or VSIs from the hw switch
6518 * because the reset will make them disappear.
6519 */
6520 ret = i40e_pf_reset(hw);
b5565400 6521 if (ret) {
41c445ff 6522 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6523 set_bit(__I40E_RESET_FAILED, &pf->state);
6524 goto clear_recovery;
b5565400 6525 }
41c445ff
JB		 6526 pf->pfr_count++;
6527
6528 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6529 goto clear_recovery;
69bfb110 6530 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6531
6532 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6533 ret = i40e_init_adminq(&pf->hw);
6534 if (ret) {
f1c7e72e
SN		 6535 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6536 i40e_stat_str(&pf->hw, ret),
6537 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6538 goto clear_recovery;
41c445ff
JB		 6539 }
6540
4eb3f768 6541 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6542 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6543 i40e_verify_eeprom(pf);
4eb3f768 6544
e78ac4bf 6545 i40e_clear_pxe_mode(hw);
41c445ff 6546 ret = i40e_get_capabilities(pf);
f1c7e72e 6547 if (ret)
41c445ff 6548 goto end_core_reset;
41c445ff 6549
41c445ff
JB		 6550 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6551 hw->func_caps.num_rx_qp,
6552 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6553 if (ret) {
6554 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6555 goto end_core_reset;
6556 }
6557 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6558 if (ret) {
6559 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6560 goto end_core_reset;
6561 }
6562
4e3b35b0
NP		 6563#ifdef CONFIG_I40E_DCB
6564 ret = i40e_init_pf_dcb(pf);
6565 if (ret) {
aebfc816
SN		 6566 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6567 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6568 /* Continue without DCB enabled */
4e3b35b0
NP		 6569 }
6570#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6571#ifdef I40E_FCOE
6572 ret = i40e_init_pf_fcoe(pf);
6573 if (ret)
6574 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6575
38e00438 6576#endif
41c445ff 6577 /* do basic switch setup */
bc7d338f 6578 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6579 if (ret)
6580 goto end_core_reset;
6581
7e2453fe
JB		 6582 /* driver is only interested in link up/down and module qualification
6583 * reports from firmware
6584 */
6585 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6586 I40E_AQ_EVENT_LINK_UPDOWN |
6587 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6588 if (ret)
f1c7e72e
SN		 6589 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6590 i40e_stat_str(&pf->hw, ret),
6591 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6592
cafa2ee6
ASJ		 6593 /* make sure our flow control settings are restored */
6594 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6595 if (ret)
f1c7e72e
SN		 6596 dev_info(&pf->pdev->dev, "set fc fail, err %s aq_err %s\n",
6597 i40e_stat_str(&pf->hw, ret),
6598 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6599
41c445ff
JB		 6600 /* Rebuild the VSIs and VEBs that existed before reset.
6601 * They are still in our local switch element arrays, so only
6602 * need to rebuild the switch model in the HW.
6603 *
6604 * If there were VEBs but the reconstitution failed, we'll try
6605 * try to recover minimal use by getting the basic PF VSI working.
6606 */
6607 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6608 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6609 /* find the one VEB connected to the MAC, and find orphans */
6610 for (v = 0; v < I40E_MAX_VEB; v++) {
6611 if (!pf->veb[v])
6612 continue;
6613
6614 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6615 pf->veb[v]->uplink_seid == 0) {
6616 ret = i40e_reconstitute_veb(pf->veb[v]);
6617
6618 if (!ret)
6619 continue;
6620
6621 /* If Main VEB failed, we're in deep doodoo,
6622 * so give up rebuilding the switch and set up
6623 * for minimal rebuild of PF VSI.
6624 * If orphan failed, we'll report the error
6625 * but try to keep going.
6626 */
6627 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6628 dev_info(&pf->pdev->dev,
6629 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6630 ret);
6631 pf->vsi[pf->lan_vsi]->uplink_seid
6632 = pf->mac_seid;
6633 break;
6634 } else if (pf->veb[v]->uplink_seid == 0) {
6635 dev_info(&pf->pdev->dev,
6636 "rebuild of orphan VEB failed: %d\n",
6637 ret);
6638 }
6639 }
6640 }
6641 }
6642
6643 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6644 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6645 /* no VEB, so rebuild only the Main VSI */
6646 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6647 if (ret) {
6648 dev_info(&pf->pdev->dev,
6649 "rebuild of Main VSI failed: %d\n", ret);
6650 goto end_core_reset;
6651 }
6652 }
6653
025b4a54
ASJ		 6654 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6655 (pf->hw.aq.fw_maj_ver < 4)) {
6656 msleep(75);
6657 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6658 if (ret)
f1c7e72e
SN		 6659 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6660 i40e_stat_str(&pf->hw, ret),
6661 i40e_aq_str(&pf->hw,
6662 pf->hw.aq.asq_last_status));
cafa2ee6 6663 }
41c445ff
JB		 6664 /* reinit the misc interrupt */
6665 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6666 ret = i40e_setup_misc_vector(pf);
6667
6668 /* restart the VSIs that were rebuilt and running before the reset */
6669 i40e_pf_unquiesce_all_vsi(pf);
6670
69f64b2b
MW		 6671 if (pf->num_alloc_vfs) {
6672 for (v = 0; v < pf->num_alloc_vfs; v++)
6673 i40e_reset_vf(&pf->vf[v], true);
6674 }
6675
41c445ff 6676 /* tell the firmware that we're starting */
44033fac 6677 i40e_send_version(pf);
41c445ff
JB		 6678
6679end_core_reset:
a316f651
ASJ		 6680 clear_bit(__I40E_RESET_FAILED, &pf->state);
6681clear_recovery:
41c445ff
JB		 6682 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6683}
6684
f650a38b 6685/**
b40c82e6 6686 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6687 * @pf: board private structure
6688 *
6689 * Close up the VFs and other things in prep for a Core Reset,
6690 * then get ready to rebuild the world.
6691 **/
6692static void i40e_handle_reset_warning(struct i40e_pf *pf)
6693{
23cfbe07
SN		 6694 i40e_prep_for_reset(pf);
6695 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6696}
6697
41c445ff
JB		 6698/**
6699 * i40e_handle_mdd_event
b40c82e6 6700 * @pf: pointer to the PF structure
41c445ff
JB		 6701 *
6702 * Called from the MDD irq handler to identify possibly malicious vfs
6703 **/
6704static void i40e_handle_mdd_event(struct i40e_pf *pf)
6705{
6706 struct i40e_hw *hw = &pf->hw;
6707 bool mdd_detected = false;
df430b12 6708 bool pf_mdd_detected = false;
41c445ff
JB		 6709 struct i40e_vf *vf;
6710 u32 reg;
6711 int i;
6712
6713 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6714 return;
6715
6716 /* find what triggered the MDD event */
6717 reg = rd32(hw, I40E_GL_MDET_TX);
6718 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6719 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6720 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6721 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6722 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6723 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6724 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6725 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6726 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6727 pf->hw.func_caps.base_queue;
faf32978 6728 if (netif_msg_tx_err(pf))
b40c82e6 6729 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6730 event, queue, pf_num, vf_num);
41c445ff
JB		 6731 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6732 mdd_detected = true;
6733 }
6734 reg = rd32(hw, I40E_GL_MDET_RX);
6735 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6736 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6737 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6738 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6739 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6740 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6741 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6742 pf->hw.func_caps.base_queue;
faf32978
JB		 6743 if (netif_msg_rx_err(pf))
6744 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6745 event, queue, func);
41c445ff
JB		 6746 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6747 mdd_detected = true;
6748 }
6749
df430b12
NP		 6750 if (mdd_detected) {
6751 reg = rd32(hw, I40E_PF_MDET_TX);
6752 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6753 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6754 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6755 pf_mdd_detected = true;
6756 }
6757 reg = rd32(hw, I40E_PF_MDET_RX);
6758 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6759 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6760 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6761 pf_mdd_detected = true;
6762 }
6763 /* Queue belongs to the PF, initiate a reset */
6764 if (pf_mdd_detected) {
6765 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6766 i40e_service_event_schedule(pf);
6767 }
6768 }
6769
41c445ff
JB		 6770 /* see if one of the VFs needs its hand slapped */
6771 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6772 vf = &(pf->vf[i]);
6773 reg = rd32(hw, I40E_VP_MDET_TX(i));
6774 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6775 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6776 vf->num_mdd_events++;
faf32978
JB		 6777 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6778 i);
41c445ff
JB		 6779 }
6780
6781 reg = rd32(hw, I40E_VP_MDET_RX(i));
6782 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6783 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6784 vf->num_mdd_events++;
faf32978
JB		 6785 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6786 i);
41c445ff
JB		 6787 }
6788
6789 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6790 dev_info(&pf->pdev->dev,
6791 "Too many MDD events on VF %d, disabled\n", i);
6792 dev_info(&pf->pdev->dev,
6793 "Use PF Control I/F to re-enable the VF\n");
6794 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6795 }
6796 }
6797
6798 /* re-enable mdd interrupt cause */
6799 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6800 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6801 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6802 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6803 i40e_flush(hw);
6804}
6805
a1c9a9d9
JK		 6806#ifdef CONFIG_I40E_VXLAN
6807/**
6808 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6809 * @pf: board private structure
6810 **/
6811static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6812{
a1c9a9d9
JK		 6813 struct i40e_hw *hw = &pf->hw;
6814 i40e_status ret;
a1c9a9d9
JK		 6815 __be16 port;
6816 int i;
6817
6818 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6819 return;
6820
6821 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6822
6823 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 6824 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
6825 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 6826 port = pf->vxlan_ports[i];
c22c06c8
SN		 6827 if (port)
6828 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 6829 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 6830 NULL, NULL);
6831 else
6832 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 6833
6834 if (ret) {
c22c06c8 6835 dev_info(&pf->pdev->dev,
f1c7e72e 6836 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 6837 port ? "add" : "delete",
f1c7e72e
SN		 6838 ntohs(port), i,
6839 i40e_stat_str(&pf->hw, ret),
6840 i40e_aq_str(&pf->hw,
6841 pf->hw.aq.asq_last_status));
a1c9a9d9 6842 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 6843 }
6844 }
6845 }
6846}
6847
6848#endif
41c445ff
JB		 6849/**
6850 * i40e_service_task - Run the driver's async subtasks
6851 * @work: pointer to work_struct containing our data
6852 **/
6853static void i40e_service_task(struct work_struct *work)
6854{
6855 struct i40e_pf *pf = container_of(work,
6856 struct i40e_pf,
6857 service_task);
6858 unsigned long start_time = jiffies;
6859
e57a2fea
SN		 6860 /* don't bother with service tasks if a reset is in progress */
6861 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6862 i40e_service_event_complete(pf);
6863 return;
6864 }
6865
b03a8c1f 6866 i40e_detect_recover_hung(pf);
41c445ff
JB		 6867 i40e_reset_subtask(pf);
6868 i40e_handle_mdd_event(pf);
6869 i40e_vc_process_vflr_event(pf);
6870 i40e_watchdog_subtask(pf);
6871 i40e_fdir_reinit_subtask(pf);
41c445ff 6872 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6873#ifdef CONFIG_I40E_VXLAN
6874 i40e_sync_vxlan_filters_subtask(pf);
6875#endif
41c445ff
JB		 6876 i40e_clean_adminq_subtask(pf);
6877
6878 i40e_service_event_complete(pf);
6879
6880 /* If the tasks have taken longer than one timer cycle or there
6881 * is more work to be done, reschedule the service task now
6882 * rather than wait for the timer to tick again.
6883 */
6884 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6885 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6886 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6887 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6888 i40e_service_event_schedule(pf);
6889}
6890
6891/**
6892 * i40e_service_timer - timer callback
6893 * @data: pointer to PF struct
6894 **/
6895static void i40e_service_timer(unsigned long data)
6896{
6897 struct i40e_pf *pf = (struct i40e_pf *)data;
6898
6899 mod_timer(&pf->service_timer,
6900 round_jiffies(jiffies + pf->service_timer_period));
6901 i40e_service_event_schedule(pf);
6902}
6903
6904/**
6905 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6906 * @vsi: the VSI being configured
6907 **/
6908static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6909{
6910 struct i40e_pf *pf = vsi->back;
6911
6912 switch (vsi->type) {
6913 case I40E_VSI_MAIN:
6914 vsi->alloc_queue_pairs = pf->num_lan_qps;
6915 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6916 I40E_REQ_DESCRIPTOR_MULTIPLE);
6917 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6918 vsi->num_q_vectors = pf->num_lan_msix;
6919 else
6920 vsi->num_q_vectors = 1;
6921
6922 break;
6923
6924 case I40E_VSI_FDIR:
6925 vsi->alloc_queue_pairs = 1;
6926 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6927 I40E_REQ_DESCRIPTOR_MULTIPLE);
6928 vsi->num_q_vectors = 1;
6929 break;
6930
6931 case I40E_VSI_VMDQ2:
6932 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6933 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6934 I40E_REQ_DESCRIPTOR_MULTIPLE);
6935 vsi->num_q_vectors = pf->num_vmdq_msix;
6936 break;
6937
6938 case I40E_VSI_SRIOV:
6939 vsi->alloc_queue_pairs = pf->num_vf_qps;
6940 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6941 I40E_REQ_DESCRIPTOR_MULTIPLE);
6942 break;
6943
38e00438
VD		 6944#ifdef I40E_FCOE
6945 case I40E_VSI_FCOE:
6946 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6947 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6948 I40E_REQ_DESCRIPTOR_MULTIPLE);
6949 vsi->num_q_vectors = pf->num_fcoe_msix;
6950 break;
6951
6952#endif /* I40E_FCOE */
41c445ff
JB		 6953 default:
6954 WARN_ON(1);
6955 return -ENODATA;
6956 }
6957
6958 return 0;
6959}
6960
f650a38b
ASJ		 6961/**
6962 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6963 * @type: VSI pointer
bc7d338f 6964 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6965 *
6966 * On error: returns error code (negative)
6967 * On success: returns 0
6968 **/
bc7d338f 6969static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6970{
6971 int size;
6972 int ret = 0;
6973
ac6c5e3d 6974 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6975 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6976 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6977 if (!vsi->tx_rings)
6978 return -ENOMEM;
f650a38b
ASJ		 6979 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6980
bc7d338f
ASJ		 6981 if (alloc_qvectors) {
6982 /* allocate memory for q_vector pointers */
f57e4fbd 6983 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6984 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6985 if (!vsi->q_vectors) {
6986 ret = -ENOMEM;
6987 goto err_vectors;
6988 }
f650a38b
ASJ		 6989 }
6990 return ret;
6991
6992err_vectors:
6993 kfree(vsi->tx_rings);
6994 return ret;
6995}
6996
41c445ff
JB		 6997/**
6998 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6999 * @pf: board private structure
7000 * @type: type of VSI
7001 *
7002 * On error: returns error code (negative)
7003 * On success: returns vsi index in PF (positive)
7004 **/
7005static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7006{
7007 int ret = -ENODEV;
7008 struct i40e_vsi *vsi;
7009 int vsi_idx;
7010 int i;
7011
7012 /* Need to protect the allocation of the VSIs at the PF level */
7013 mutex_lock(&pf->switch_mutex);
7014
7015 /* VSI list may be fragmented if VSI creation/destruction has
7016 * been happening. We can afford to do a quick scan to look
7017 * for any free VSIs in the list.
7018 *
7019 * find next empty vsi slot, looping back around if necessary
7020 */
7021 i = pf->next_vsi;
505682cd 7022 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7023 i++;
505682cd 7024 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7025 i = 0;
7026 while (i < pf->next_vsi && pf->vsi[i])
7027 i++;
7028 }
7029
505682cd 7030 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7031 vsi_idx = i; /* Found one! */
7032 } else {
7033 ret = -ENODEV;
493fb300 7034 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7035 }
7036 pf->next_vsi = ++i;
7037
7038 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7039 if (!vsi) {
7040 ret = -ENOMEM;
493fb300 7041 goto unlock_pf;
41c445ff
JB		 7042 }
7043 vsi->type = type;
7044 vsi->back = pf;
7045 set_bit(__I40E_DOWN, &vsi->state);
7046 vsi->flags = 0;
7047 vsi->idx = vsi_idx;
7048 vsi->rx_itr_setting = pf->rx_itr_default;
7049 vsi->tx_itr_setting = pf->tx_itr_default;
5db4cb59
ASJ		 7050 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7051 pf->rss_table_size : 64;
41c445ff
JB		 7052 vsi->netdev_registered = false;
7053 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7054 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7055 vsi->irqs_ready = false;
41c445ff 7056
9f65e15b
AD		 7057 ret = i40e_set_num_rings_in_vsi(vsi);
7058 if (ret)
7059 goto err_rings;
7060
bc7d338f 7061 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7062 if (ret)
9f65e15b 7063 goto err_rings;
493fb300 7064
41c445ff
JB		 7065 /* Setup default MSIX irq handler for VSI */
7066 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7067
7068 pf->vsi[vsi_idx] = vsi;
7069 ret = vsi_idx;
493fb300
AD		 7070 goto unlock_pf;
7071
9f65e15b 7072err_rings:
493fb300
AD		 7073 pf->next_vsi = i - 1;
7074 kfree(vsi);
7075unlock_pf:
41c445ff
JB		 7076 mutex_unlock(&pf->switch_mutex);
7077 return ret;
7078}
7079
f650a38b
ASJ		 7080/**
7081 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7082 * @type: VSI pointer
bc7d338f 7083 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7084 *
7085 * On error: returns error code (negative)
7086 * On success: returns 0
7087 **/
bc7d338f 7088static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7089{
7090 /* free the ring and vector containers */
bc7d338f
ASJ		 7091 if (free_qvectors) {
7092 kfree(vsi->q_vectors);
7093 vsi->q_vectors = NULL;
7094 }
f650a38b
ASJ		 7095 kfree(vsi->tx_rings);
7096 vsi->tx_rings = NULL;
7097 vsi->rx_rings = NULL;
7098}
7099
41c445ff
JB		 7100/**
7101 * i40e_vsi_clear - Deallocate the VSI provided
7102 * @vsi: the VSI being un-configured
7103 **/
7104static int i40e_vsi_clear(struct i40e_vsi *vsi)
7105{
7106 struct i40e_pf *pf;
7107
7108 if (!vsi)
7109 return 0;
7110
7111 if (!vsi->back)
7112 goto free_vsi;
7113 pf = vsi->back;
7114
7115 mutex_lock(&pf->switch_mutex);
7116 if (!pf->vsi[vsi->idx]) {
7117 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7118 vsi->idx, vsi->idx, vsi, vsi->type);
7119 goto unlock_vsi;
7120 }
7121
7122 if (pf->vsi[vsi->idx] != vsi) {
7123 dev_err(&pf->pdev->dev,
7124 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7125 pf->vsi[vsi->idx]->idx,
7126 pf->vsi[vsi->idx],
7127 pf->vsi[vsi->idx]->type,
7128 vsi->idx, vsi, vsi->type);
7129 goto unlock_vsi;
7130 }
7131
b40c82e6 7132 /* updates the PF for this cleared vsi */
41c445ff
JB		 7133 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7134 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7135
bc7d338f 7136 i40e_vsi_free_arrays(vsi, true);
493fb300 7137
41c445ff
JB		 7138 pf->vsi[vsi->idx] = NULL;
7139 if (vsi->idx < pf->next_vsi)
7140 pf->next_vsi = vsi->idx;
7141
7142unlock_vsi:
7143 mutex_unlock(&pf->switch_mutex);
7144free_vsi:
7145 kfree(vsi);
7146
7147 return 0;
7148}
7149
9f65e15b
AD		 7150/**
7151 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7152 * @vsi: the VSI being cleaned
7153 **/
be1d5eea 7154static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7155{
7156 int i;
7157
8e9dca53 7158 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7159 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7160 kfree_rcu(vsi->tx_rings[i], rcu);
7161 vsi->tx_rings[i] = NULL;
7162 vsi->rx_rings[i] = NULL;
7163 }
be1d5eea 7164 }
9f65e15b
AD		 7165}
7166
41c445ff
JB		 7167/**
7168 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7169 * @vsi: the VSI being configured
7170 **/
7171static int i40e_alloc_rings(struct i40e_vsi *vsi)
7172{
e7046ee1 7173 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7174 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7175 int i;
7176
41c445ff 7177 /* Set basic values in the rings to be used later during open() */
d7397644 7178 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7179 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7180 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7181 if (!tx_ring)
7182 goto err_out;
41c445ff
JB		 7183
7184 tx_ring->queue_index = i;
7185 tx_ring->reg_idx = vsi->base_queue + i;
7186 tx_ring->ring_active = false;
7187 tx_ring->vsi = vsi;
7188 tx_ring->netdev = vsi->netdev;
7189 tx_ring->dev = &pf->pdev->dev;
7190 tx_ring->count = vsi->num_desc;
7191 tx_ring->size = 0;
7192 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7193 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7194 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7195 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7196 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7197 vsi->tx_rings[i] = tx_ring;
41c445ff 7198
9f65e15b 7199 rx_ring = &tx_ring[1];
41c445ff
JB		 7200 rx_ring->queue_index = i;
7201 rx_ring->reg_idx = vsi->base_queue + i;
7202 rx_ring->ring_active = false;
7203 rx_ring->vsi = vsi;
7204 rx_ring->netdev = vsi->netdev;
7205 rx_ring->dev = &pf->pdev->dev;
7206 rx_ring->count = vsi->num_desc;
7207 rx_ring->size = 0;
7208 rx_ring->dcb_tc = 0;
7209 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7210 set_ring_16byte_desc_enabled(rx_ring);
7211 else
7212 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7213 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7214 }
7215
7216 return 0;
9f65e15b
AD		 7217
7218err_out:
7219 i40e_vsi_clear_rings(vsi);
7220 return -ENOMEM;
41c445ff
JB		 7221}
7222
7223/**
7224 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7225 * @pf: board private structure
7226 * @vectors: the number of MSI-X vectors to request
7227 *
7228 * Returns the number of vectors reserved, or error
7229 **/
7230static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7231{
7b37f376
AG		 7232 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7233 I40E_MIN_MSIX, vectors);
7234 if (vectors < 0) {
41c445ff 7235 dev_info(&pf->pdev->dev,
7b37f376 7236 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7237 vectors = 0;
7238 }
7239
7240 return vectors;
7241}
7242
7243/**
7244 * i40e_init_msix - Setup the MSIX capability
7245 * @pf: board private structure
7246 *
7247 * Work with the OS to set up the MSIX vectors needed.
7248 *
3b444399 7249 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7250 **/
7251static int i40e_init_msix(struct i40e_pf *pf)
7252{
41c445ff 7253 struct i40e_hw *hw = &pf->hw;
1e200e4a 7254 int vectors_left;
41c445ff 7255 int v_budget, i;
3b444399 7256 int v_actual;
41c445ff
JB		 7257
7258 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7259 return -ENODEV;
7260
7261 /* The number of vectors we'll request will be comprised of:
7262 * - Add 1 for "other" cause for Admin Queue events, etc.
7263 * - The number of LAN queue pairs
f8ff1464
ASJ		 7264 * - Queues being used for RSS.
7265 * We don't need as many as max_rss_size vectors.
7266 * use rss_size instead in the calculation since that
7267 * is governed by number of cpus in the system.
7268 * - assumes symmetric Tx/Rx pairing
41c445ff 7269 * - The number of VMDq pairs
38e00438
VD		 7270#ifdef I40E_FCOE
7271 * - The number of FCOE qps.
7272#endif
41c445ff
JB		 7273 * Once we count this up, try the request.
7274 *
7275 * If we can't get what we want, we'll simplify to nearly nothing
7276 * and try again. If that still fails, we punt.
7277 */
1e200e4a
SN		 7278 vectors_left = hw->func_caps.num_msix_vectors;
7279 v_budget = 0;
7280
7281 /* reserve one vector for miscellaneous handler */
7282 if (vectors_left) {
7283 v_budget++;
7284 vectors_left--;
7285 }
7286
7287 /* reserve vectors for the main PF traffic queues */
7288 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7289 vectors_left -= pf->num_lan_msix;
7290 v_budget += pf->num_lan_msix;
7291
7292 /* reserve one vector for sideband flow director */
7293 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7294 if (vectors_left) {
7295 v_budget++;
7296 vectors_left--;
7297 } else {
7298 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7299 }
7300 }
83840e4b 7301
38e00438 7302#ifdef I40E_FCOE
1e200e4a 7303 /* can we reserve enough for FCoE? */
38e00438 7304 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7305 if (!vectors_left)
7306 pf->num_fcoe_msix = 0;
7307 else if (vectors_left >= pf->num_fcoe_qps)
7308 pf->num_fcoe_msix = pf->num_fcoe_qps;
7309 else
7310 pf->num_fcoe_msix = 1;
38e00438 7311 v_budget += pf->num_fcoe_msix;
1e200e4a 7312 vectors_left -= pf->num_fcoe_msix;
38e00438 7313 }
1e200e4a 7314
38e00438 7315#endif
1e200e4a
SN		 7316 /* any vectors left over go for VMDq support */
7317 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7318 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7319 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7320
7321 /* if we're short on vectors for what's desired, we limit
7322 * the queues per vmdq. If this is still more than are
7323 * available, the user will need to change the number of
7324 * queues/vectors used by the PF later with the ethtool
7325 * channels command
7326 */
7327 if (vmdq_vecs < vmdq_vecs_wanted)
7328 pf->num_vmdq_qps = 1;
7329 pf->num_vmdq_msix = pf->num_vmdq_qps;
7330
7331 v_budget += vmdq_vecs;
7332 vectors_left -= vmdq_vecs;
7333 }
41c445ff
JB		 7334
7335 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7336 GFP_KERNEL);
7337 if (!pf->msix_entries)
7338 return -ENOMEM;
7339
7340 for (i = 0; i < v_budget; i++)
7341 pf->msix_entries[i].entry = i;
3b444399 7342 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7343
3b444399 7344 if (v_actual != v_budget) {
a34977ba
ASJ		 7345 /* If we have limited resources, we will start with no vectors
7346 * for the special features and then allocate vectors to some
7347 * of these features based on the policy and at the end disable
7348 * the features that did not get any vectors.
7349 */
38e00438
VD		 7350#ifdef I40E_FCOE
7351 pf->num_fcoe_qps = 0;
7352 pf->num_fcoe_msix = 0;
7353#endif
a34977ba
ASJ		 7354 pf->num_vmdq_msix = 0;
7355 }
7356
3b444399 7357 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7358 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7359 kfree(pf->msix_entries);
7360 pf->msix_entries = NULL;
7361 return -ENODEV;
7362
3b444399 7363 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7364 /* Adjust for minimal MSIX use */
41c445ff
JB		 7365 pf->num_vmdq_vsis = 0;
7366 pf->num_vmdq_qps = 0;
41c445ff
JB		 7367 pf->num_lan_qps = 1;
7368 pf->num_lan_msix = 1;
7369
3b444399
SN		 7370 } else if (v_actual != v_budget) {
7371 int vec;
7372
a34977ba 7373 /* reserve the misc vector */
3b444399 7374 vec = v_actual - 1;
a34977ba 7375
41c445ff
JB		 7376 /* Scale vector usage down */
7377 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7378 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7379 pf->num_vmdq_qps = 1;
7380 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7381
7382 /* partition out the remaining vectors */
7383 switch (vec) {
7384 case 2:
41c445ff
JB		 7385 pf->num_lan_msix = 1;
7386 break;
7387 case 3:
38e00438
VD		 7388#ifdef I40E_FCOE
7389 /* give one vector to FCoE */
7390 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7391 pf->num_lan_msix = 1;
7392 pf->num_fcoe_msix = 1;
7393 }
7394#else
41c445ff 7395 pf->num_lan_msix = 2;
38e00438 7396#endif
41c445ff
JB		 7397 break;
7398 default:
38e00438
VD		 7399#ifdef I40E_FCOE
7400 /* give one vector to FCoE */
7401 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7402 pf->num_fcoe_msix = 1;
7403 vec--;
7404 }
7405#endif
1e200e4a
SN		 7406 /* give the rest to the PF */
7407 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7408 break;
7409 }
7410 }
7411
a34977ba
ASJ		 7412 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7413 (pf->num_vmdq_msix == 0)) {
7414 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7415 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7416 }
38e00438
VD		 7417#ifdef I40E_FCOE
7418
7419 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7420 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7421 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7422 }
7423#endif
3b444399 7424 return v_actual;
41c445ff
JB		 7425}
7426
493fb300 7427/**
90e04070 7428 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7429 * @vsi: the VSI being configured
7430 * @v_idx: index of the vector in the vsi struct
7431 *
7432 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7433 **/
90e04070 7434static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7435{
7436 struct i40e_q_vector *q_vector;
7437
7438 /* allocate q_vector */
7439 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7440 if (!q_vector)
7441 return -ENOMEM;
7442
7443 q_vector->vsi = vsi;
7444 q_vector->v_idx = v_idx;
7445 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7446 if (vsi->netdev)
7447 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7448 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7449
cd0b6fa6
AD		 7450 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7451 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7452
493fb300
AD		 7453 /* tie q_vector and vsi together */
7454 vsi->q_vectors[v_idx] = q_vector;
7455
7456 return 0;
7457}
7458
41c445ff 7459/**
90e04070 7460 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7461 * @vsi: the VSI being configured
7462 *
7463 * We allocate one q_vector per queue interrupt. If allocation fails we
7464 * return -ENOMEM.
7465 **/
90e04070 7466static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7467{
7468 struct i40e_pf *pf = vsi->back;
7469 int v_idx, num_q_vectors;
493fb300 7470 int err;
41c445ff
JB		 7471
7472 /* if not MSIX, give the one vector only to the LAN VSI */
7473 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7474 num_q_vectors = vsi->num_q_vectors;
7475 else if (vsi == pf->vsi[pf->lan_vsi])
7476 num_q_vectors = 1;
7477 else
7478 return -EINVAL;
7479
41c445ff 7480 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7481 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7482 if (err)
7483 goto err_out;
41c445ff
JB		 7484 }
7485
7486 return 0;
493fb300
AD		 7487
7488err_out:
7489 while (v_idx--)
7490 i40e_free_q_vector(vsi, v_idx);
7491
7492 return err;
41c445ff
JB		 7493}
7494
7495/**
7496 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7497 * @pf: board private structure to initialize
7498 **/
c1147280 7499static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7500{
3b444399
SN		 7501 int vectors = 0;
7502 ssize_t size;
41c445ff
JB		 7503
7504 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7505 vectors = i40e_init_msix(pf);
7506 if (vectors < 0) {
60ea5f83 7507 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7508#ifdef I40E_FCOE
7509 I40E_FLAG_FCOE_ENABLED |
7510#endif
60ea5f83 7511 I40E_FLAG_RSS_ENABLED |
4d9b6043 7512 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7513 I40E_FLAG_SRIOV_ENABLED |
7514 I40E_FLAG_FD_SB_ENABLED |
7515 I40E_FLAG_FD_ATR_ENABLED |
7516 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7517
7518 /* rework the queue expectations without MSIX */
7519 i40e_determine_queue_usage(pf);
7520 }
7521 }
7522
7523 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7524 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7525 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7526 vectors = pci_enable_msi(pf->pdev);
7527 if (vectors < 0) {
7528 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7529 vectors);
41c445ff
JB		 7530 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7531 }
3b444399 7532 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7533 }
7534
958a3e3b 7535 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7536 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7537
3b444399
SN		 7538 /* set up vector assignment tracking */
7539 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7540 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7541 if (!pf->irq_pile) {
7542 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7543 return -ENOMEM;
7544 }
3b444399
SN		 7545 pf->irq_pile->num_entries = vectors;
7546 pf->irq_pile->search_hint = 0;
7547
c1147280 7548 /* track first vector for misc interrupts, ignore return */
3b444399 7549 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7550
7551 return 0;
41c445ff
JB		 7552}
7553
7554/**
7555 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7556 * @pf: board private structure
7557 *
7558 * This sets up the handler for MSIX 0, which is used to manage the
7559 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7560 * when in MSI or Legacy interrupt mode.
7561 **/
7562static int i40e_setup_misc_vector(struct i40e_pf *pf)
7563{
7564 struct i40e_hw *hw = &pf->hw;
7565 int err = 0;
7566
7567 /* Only request the irq if this is the first time through, and
7568 * not when we're rebuilding after a Reset
7569 */
7570 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7571 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7572 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7573 if (err) {
7574 dev_info(&pf->pdev->dev,
77fa28be 7575 "request_irq for %s failed: %d\n",
b294ac70 7576 pf->int_name, err);
41c445ff
JB		 7577 return -EFAULT;
7578 }
7579 }
7580
ab437b5a 7581 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7582
7583 /* associate no queues to the misc vector */
7584 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7585 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7586
7587 i40e_flush(hw);
7588
7589 i40e_irq_dynamic_enable_icr0(pf);
7590
7591 return err;
7592}
7593
7594/**
e25d00b8
ASJ		 7595 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7596 * @vsi: vsi structure
7597 * @seed: RSS hash seed
7598 **/
7599static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed)
7600{
7601 struct i40e_aqc_get_set_rss_key_data rss_key;
7602 struct i40e_pf *pf = vsi->back;
7603 struct i40e_hw *hw = &pf->hw;
7604 bool pf_lut = false;
7605 u8 *rss_lut;
7606 int ret, i;
7607
7608 memset(&rss_key, 0, sizeof(rss_key));
7609 memcpy(&rss_key, seed, sizeof(rss_key));
7610
7611 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7612 if (!rss_lut)
7613 return -ENOMEM;
7614
7615 /* Populate the LUT with max no. of queues in round robin fashion */
7616 for (i = 0; i < vsi->rss_table_size; i++)
7617 rss_lut[i] = i % vsi->rss_size;
7618
7619 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7620 if (ret) {
7621 dev_info(&pf->pdev->dev,
7622 "Cannot set RSS key, err %s aq_err %s\n",
7623 i40e_stat_str(&pf->hw, ret),
7624 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7625 return ret;
7626 }
7627
7628 if (vsi->type == I40E_VSI_MAIN)
7629 pf_lut = true;
7630
7631 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7632 vsi->rss_table_size);
7633 if (ret)
7634 dev_info(&pf->pdev->dev,
7635 "Cannot set RSS lut, err %s aq_err %s\n",
7636 i40e_stat_str(&pf->hw, ret),
7637 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7638
7639 return ret;
7640}
7641
7642/**
7643 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7644 * @vsi: VSI structure
7645 **/
7646static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7647{
7648 u8 seed[I40E_HKEY_ARRAY_SIZE];
7649 struct i40e_pf *pf = vsi->back;
7650
7651 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
7652 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7653
7654 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7655 return i40e_config_rss_aq(vsi, seed);
7656
7657 return 0;
7658}
7659
7660/**
7661 * i40e_config_rss_reg - Prepare for RSS if used
41c445ff 7662 * @pf: board private structure
e25d00b8 7663 * @seed: RSS hash seed
41c445ff 7664 **/
e25d00b8 7665static int i40e_config_rss_reg(struct i40e_pf *pf, const u8 *seed)
41c445ff 7666{
66ddcffb 7667 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0 7668 struct i40e_hw *hw = &pf->hw;
e25d00b8
ASJ		 7669 u32 *seed_dw = (u32 *)seed;
7670 u32 current_queue = 0;
4617e8c0
ASJ		 7671 u32 lut = 0;
7672 int i, j;
41c445ff 7673
e25d00b8 7674 /* Fill out hash function seed */
41c445ff 7675 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
e25d00b8
ASJ		 7676 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7677
7678 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) {
7679 lut = 0;
7680 for (j = 0; j < 4; j++) {
7681 if (current_queue == vsi->rss_size)
7682 current_queue = 0;
7683 lut |= ((current_queue) << (8 * j));
7684 current_queue++;
7685 }
7686 wr32(&pf->hw, I40E_PFQF_HLUT(i), lut);
7687 }
7688 i40e_flush(hw);
7689
7690 return 0;
7691}
7692
7693/**
7694 * i40e_config_rss - Prepare for RSS if used
7695 * @pf: board private structure
7696 **/
7697static int i40e_config_rss(struct i40e_pf *pf)
7698{
7699 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7700 u8 seed[I40E_HKEY_ARRAY_SIZE];
7701 struct i40e_hw *hw = &pf->hw;
7702 u32 reg_val;
7703 u64 hena;
7704
7705 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
41c445ff
JB		 7706
7707 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7708 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7709 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 7710 hena |= i40e_pf_get_default_rss_hena(pf);
7711
41c445ff
JB		 7712 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7713 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7714
66ddcffb
ASJ		 7715 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7716
e25d00b8 7717 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 7718 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 7719 reg_val = (pf->rss_table_size == 512) ?
7720 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
7721 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 7722 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7723
e25d00b8
ASJ		 7724 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7725 return i40e_config_rss_aq(pf->vsi[pf->lan_vsi], seed);
7726 else
7727 return i40e_config_rss_reg(pf, seed);
41c445ff
JB		 7728}
7729
f8ff1464
ASJ		 7730/**
7731 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7732 * @pf: board private structure
7733 * @queue_count: the requested queue count for rss.
7734 *
7735 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7736 * count which may be different from the requested queue count.
7737 **/
7738int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7739{
9a3bd2f1
ASJ		 7740 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7741 int new_rss_size;
7742
f8ff1464
ASJ		 7743 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7744 return 0;
7745
9a3bd2f1 7746 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7747
9a3bd2f1
ASJ		 7748 if (queue_count != vsi->num_queue_pairs) {
7749 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7750 i40e_prep_for_reset(pf);
7751
9a3bd2f1 7752 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7753
7754 i40e_reset_and_rebuild(pf, true);
7755 i40e_config_rss(pf);
7756 }
7757 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7758 return pf->rss_size;
7759}
7760
f4492db1
GR		 7761/**
7762 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7763 * @pf: board private structure
7764 **/
7765i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7766{
7767 i40e_status status;
7768 bool min_valid, max_valid;
7769 u32 max_bw, min_bw;
7770
7771 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7772 &min_valid, &max_valid);
7773
7774 if (!status) {
7775 if (min_valid)
7776 pf->npar_min_bw = min_bw;
7777 if (max_valid)
7778 pf->npar_max_bw = max_bw;
7779 }
7780
7781 return status;
7782}
7783
7784/**
7785 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7786 * @pf: board private structure
7787 **/
7788i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7789{
7790 struct i40e_aqc_configure_partition_bw_data bw_data;
7791 i40e_status status;
7792
b40c82e6 7793 /* Set the valid bit for this PF */
41a1d04b 7794 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 7795 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7796 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7797
7798 /* Set the new bandwidths */
7799 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7800
7801 return status;
7802}
7803
7804/**
7805 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7806 * @pf: board private structure
7807 **/
7808i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7809{
7810 /* Commit temporary BW setting to permanent NVM image */
7811 enum i40e_admin_queue_err last_aq_status;
7812 i40e_status ret;
7813 u16 nvm_word;
7814
7815 if (pf->hw.partition_id != 1) {
7816 dev_info(&pf->pdev->dev,
7817 "Commit BW only works on partition 1! This is partition %d",
7818 pf->hw.partition_id);
7819 ret = I40E_NOT_SUPPORTED;
7820 goto bw_commit_out;
7821 }
7822
7823 /* Acquire NVM for read access */
7824 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7825 last_aq_status = pf->hw.aq.asq_last_status;
7826 if (ret) {
7827 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7828 "Cannot acquire NVM for read access, err %s aq_err %s\n",
7829 i40e_stat_str(&pf->hw, ret),
7830 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7831 goto bw_commit_out;
7832 }
7833
7834 /* Read word 0x10 of NVM - SW compatibility word 1 */
7835 ret = i40e_aq_read_nvm(&pf->hw,
7836 I40E_SR_NVM_CONTROL_WORD,
7837 0x10, sizeof(nvm_word), &nvm_word,
7838 false, NULL);
7839 /* Save off last admin queue command status before releasing
7840 * the NVM
7841 */
7842 last_aq_status = pf->hw.aq.asq_last_status;
7843 i40e_release_nvm(&pf->hw);
7844 if (ret) {
f1c7e72e
SN		 7845 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
7846 i40e_stat_str(&pf->hw, ret),
7847 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7848 goto bw_commit_out;
7849 }
7850
7851 /* Wait a bit for NVM release to complete */
7852 msleep(50);
7853
7854 /* Acquire NVM for write access */
7855 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7856 last_aq_status = pf->hw.aq.asq_last_status;
7857 if (ret) {
7858 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7859 "Cannot acquire NVM for write access, err %s aq_err %s\n",
7860 i40e_stat_str(&pf->hw, ret),
7861 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7862 goto bw_commit_out;
7863 }
7864 /* Write it back out unchanged to initiate update NVM,
7865 * which will force a write of the shadow (alt) RAM to
7866 * the NVM - thus storing the bandwidth values permanently.
7867 */
7868 ret = i40e_aq_update_nvm(&pf->hw,
7869 I40E_SR_NVM_CONTROL_WORD,
7870 0x10, sizeof(nvm_word),
7871 &nvm_word, true, NULL);
7872 /* Save off last admin queue command status before releasing
7873 * the NVM
7874 */
7875 last_aq_status = pf->hw.aq.asq_last_status;
7876 i40e_release_nvm(&pf->hw);
7877 if (ret)
7878 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7879 "BW settings NOT SAVED, err %s aq_err %s\n",
7880 i40e_stat_str(&pf->hw, ret),
7881 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7882bw_commit_out:
7883
7884 return ret;
7885}
7886
41c445ff
JB		 7887/**
7888 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7889 * @pf: board private structure to initialize
7890 *
7891 * i40e_sw_init initializes the Adapter private data structure.
7892 * Fields are initialized based on PCI device information and
7893 * OS network device settings (MTU size).
7894 **/
7895static int i40e_sw_init(struct i40e_pf *pf)
7896{
7897 int err = 0;
7898 int size;
7899
7900 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7901 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7902 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7903 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7904 if (I40E_DEBUG_USER & debug)
7905 pf->hw.debug_mask = debug;
7906 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7907 I40E_DEFAULT_MSG_ENABLE);
7908 }
7909
7910 /* Set default capability flags */
7911 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7912 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 7913 I40E_FLAG_MSIX_ENABLED;
7914
7915 if (iommu_present(&pci_bus_type))
7916 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7917 else
7918 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7919
ca99eb99
MW		 7920 /* Set default ITR */
7921 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7922 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7923
7134f9ce
JB		 7924 /* Depending on PF configurations, it is possible that the RSS
7925 * maximum might end up larger than the available queues
7926 */
41a1d04b 7927 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
ec9a7db7 7928 pf->rss_size = 1;
5db4cb59 7929 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7930 pf->rss_size_max = min_t(int, pf->rss_size_max,
7931 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7932 if (pf->hw.func_caps.rss) {
7933 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7934 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7935 }
7936
2050bc65 7937 /* MFP mode enabled */
c78b953e 7938 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 7939 pf->flags |= I40E_FLAG_MFP_ENABLED;
7940 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7941 if (i40e_get_npar_bw_setting(pf))
7942 dev_warn(&pf->pdev->dev,
7943 "Could not get NPAR bw settings\n");
7944 else
7945 dev_info(&pf->pdev->dev,
7946 "Min BW = %8.8x, Max BW = %8.8x\n",
7947 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7948 }
7949
cbf61325
ASJ		 7950 /* FW/NVM is not yet fixed in this regard */
7951 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7952 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7953 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7954 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 7955 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7956 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 7957 } else {
7958 dev_info(&pf->pdev->dev,
0b67584f 7959 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7960 }
cbf61325
ASJ		 7961 pf->fdir_pf_filter_count =
7962 pf->hw.func_caps.fd_filters_guaranteed;
7963 pf->hw.fdir_shared_filter_count =
7964 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7965 }
7966
7967 if (pf->hw.func_caps.vmdq) {
41c445ff 7968 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 7969 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
41c445ff
JB		 7970 }
7971
38e00438
VD		 7972#ifdef I40E_FCOE
7973 err = i40e_init_pf_fcoe(pf);
7974 if (err)
7975 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7976
7977#endif /* I40E_FCOE */
41c445ff 7978#ifdef CONFIG_PCI_IOV
ba252f13 7979 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7980 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7981 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7982 pf->num_req_vfs = min_t(int,
7983 pf->hw.func_caps.num_vfs,
7984 I40E_MAX_VF_COUNT);
7985 }
7986#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 7987 if (pf->hw.mac.type == I40E_MAC_X722) {
7988 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
7989 I40E_FLAG_128_QP_RSS_CAPABLE |
7990 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
7991 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
7992 I40E_FLAG_WB_ON_ITR_CAPABLE |
7993 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
7994 }
41c445ff
JB		 7995 pf->eeprom_version = 0xDEAD;
7996 pf->lan_veb = I40E_NO_VEB;
7997 pf->lan_vsi = I40E_NO_VSI;
7998
7999 /* set up queue assignment tracking */
8000 size = sizeof(struct i40e_lump_tracking)
8001 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8002 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8003 if (!pf->qp_pile) {
8004 err = -ENOMEM;
8005 goto sw_init_done;
8006 }
8007 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8008 pf->qp_pile->search_hint = 0;
8009
327fe04b
ASJ		 8010 pf->tx_timeout_recovery_level = 1;
8011
41c445ff
JB		 8012 mutex_init(&pf->switch_mutex);
8013
c668a12c
GR		 8014 /* If NPAR is enabled nudge the Tx scheduler */
8015 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8016 i40e_set_npar_bw_setting(pf);
8017
41c445ff
JB		 8018sw_init_done:
8019 return err;
8020}
8021
7c3c288b
ASJ		 8022/**
8023 * i40e_set_ntuple - set the ntuple feature flag and take action
8024 * @pf: board private structure to initialize
8025 * @features: the feature set that the stack is suggesting
8026 *
8027 * returns a bool to indicate if reset needs to happen
8028 **/
8029bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8030{
8031 bool need_reset = false;
8032
8033 /* Check if Flow Director n-tuple support was enabled or disabled. If
8034 * the state changed, we need to reset.
8035 */
8036 if (features & NETIF_F_NTUPLE) {
8037 /* Enable filters and mark for reset */
8038 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8039 need_reset = true;
8040 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8041 } else {
8042 /* turn off filters, mark for reset and clear SW filter list */
8043 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8044 need_reset = true;
8045 i40e_fdir_filter_exit(pf);
8046 }
8047 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8048 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8049 /* reset fd counters */
8050 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8051 pf->fdir_pf_active_filters = 0;
8052 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8053 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8054 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8055 /* if ATR was auto disabled it can be re-enabled. */
8056 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8057 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8058 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8059 }
8060 return need_reset;
8061}
8062
41c445ff
JB		 8063/**
8064 * i40e_set_features - set the netdev feature flags
8065 * @netdev: ptr to the netdev being adjusted
8066 * @features: the feature set that the stack is suggesting
8067 **/
8068static int i40e_set_features(struct net_device *netdev,
8069 netdev_features_t features)
8070{
8071 struct i40e_netdev_priv *np = netdev_priv(netdev);
8072 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8073 struct i40e_pf *pf = vsi->back;
8074 bool need_reset;
41c445ff
JB		 8075
8076 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8077 i40e_vlan_stripping_enable(vsi);
8078 else
8079 i40e_vlan_stripping_disable(vsi);
8080
7c3c288b
ASJ		 8081 need_reset = i40e_set_ntuple(pf, features);
8082
8083 if (need_reset)
41a1d04b 8084 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8085
41c445ff
JB		 8086 return 0;
8087}
8088
a1c9a9d9
JK		 8089#ifdef CONFIG_I40E_VXLAN
8090/**
8091 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8092 * @pf: board private structure
8093 * @port: The UDP port to look up
8094 *
8095 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8096 **/
8097static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8098{
8099 u8 i;
8100
8101 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8102 if (pf->vxlan_ports[i] == port)
8103 return i;
8104 }
8105
8106 return i;
8107}
8108
8109/**
8110 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8111 * @netdev: This physical port's netdev
8112 * @sa_family: Socket Family that VXLAN is notifying us about
8113 * @port: New UDP port number that VXLAN started listening to
8114 **/
8115static void i40e_add_vxlan_port(struct net_device *netdev,
8116 sa_family_t sa_family, __be16 port)
8117{
8118 struct i40e_netdev_priv *np = netdev_priv(netdev);
8119 struct i40e_vsi *vsi = np->vsi;
8120 struct i40e_pf *pf = vsi->back;
8121 u8 next_idx;
8122 u8 idx;
8123
8124 if (sa_family == AF_INET6)
8125 return;
8126
8127 idx = i40e_get_vxlan_port_idx(pf, port);
8128
8129 /* Check if port already exists */
8130 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8131 netdev_info(netdev, "vxlan port %d already offloaded\n",
8132 ntohs(port));
a1c9a9d9
JK		 8133 return;
8134 }
8135
8136 /* Now check if there is space to add the new port */
8137 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8138
8139 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8140 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8141 ntohs(port));
8142 return;
8143 }
8144
8145 /* New port: add it and mark its index in the bitmap */
8146 pf->vxlan_ports[next_idx] = port;
41a1d04b 8147 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8148 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8149}
8150
8151/**
8152 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8153 * @netdev: This physical port's netdev
8154 * @sa_family: Socket Family that VXLAN is notifying us about
8155 * @port: UDP port number that VXLAN stopped listening to
8156 **/
8157static void i40e_del_vxlan_port(struct net_device *netdev,
8158 sa_family_t sa_family, __be16 port)
8159{
8160 struct i40e_netdev_priv *np = netdev_priv(netdev);
8161 struct i40e_vsi *vsi = np->vsi;
8162 struct i40e_pf *pf = vsi->back;
8163 u8 idx;
8164
8165 if (sa_family == AF_INET6)
8166 return;
8167
8168 idx = i40e_get_vxlan_port_idx(pf, port);
8169
8170 /* Check if port already exists */
8171 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8172 /* if port exists, set it to 0 (mark for deletion)
8173 * and make it pending
8174 */
8175 pf->vxlan_ports[idx] = 0;
41a1d04b 8176 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9 8177 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
c22c06c8
SN		 8178
8179 dev_info(&pf->pdev->dev, "deleting vxlan port %d\n",
8180 ntohs(port));
a1c9a9d9 8181 } else {
c22c06c8 8182 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8183 ntohs(port));
8184 }
8185}
8186
8187#endif
1f224ad2 8188static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8189 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8190{
8191 struct i40e_netdev_priv *np = netdev_priv(netdev);
8192 struct i40e_pf *pf = np->vsi->back;
8193 struct i40e_hw *hw = &pf->hw;
8194
8195 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8196 return -EOPNOTSUPP;
8197
8198 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8199 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8200
8201 return 0;
8202}
8203
2f90ade6
JB		 8204/**
8205 * i40e_ndo_fdb_add - add an entry to the hardware database
8206 * @ndm: the input from the stack
8207 * @tb: pointer to array of nladdr (unused)
8208 * @dev: the net device pointer
8209 * @addr: the MAC address entry being added
8210 * @flags: instructions from stack about fdb operation
8211 */
4ba0dea5
GR		 8212static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8213 struct net_device *dev,
f6f6424b 8214 const unsigned char *addr, u16 vid,
4ba0dea5 8215 u16 flags)
4ba0dea5
GR		 8216{
8217 struct i40e_netdev_priv *np = netdev_priv(dev);
8218 struct i40e_pf *pf = np->vsi->back;
8219 int err = 0;
8220
8221 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8222 return -EOPNOTSUPP;
8223
65891fea
OG		 8224 if (vid) {
8225 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8226 return -EINVAL;
8227 }
8228
4ba0dea5
GR		 8229 /* Hardware does not support aging addresses so if a
8230 * ndm_state is given only allow permanent addresses
8231 */
8232 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8233 netdev_info(dev, "FDB only supports static addresses\n");
8234 return -EINVAL;
8235 }
8236
8237 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8238 err = dev_uc_add_excl(dev, addr);
8239 else if (is_multicast_ether_addr(addr))
8240 err = dev_mc_add_excl(dev, addr);
8241 else
8242 err = -EINVAL;
8243
8244 /* Only return duplicate errors if NLM_F_EXCL is set */
8245 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8246 err = 0;
8247
8248 return err;
8249}
8250
51616018
NP		 8251/**
8252 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8253 * @dev: the netdev being configured
8254 * @nlh: RTNL message
8255 *
8256 * Inserts a new hardware bridge if not already created and
8257 * enables the bridging mode requested (VEB or VEPA). If the
8258 * hardware bridge has already been inserted and the request
8259 * is to change the mode then that requires a PF reset to
8260 * allow rebuild of the components with required hardware
8261 * bridge mode enabled.
8262 **/
8263static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8264 struct nlmsghdr *nlh,
8265 u16 flags)
51616018
NP		 8266{
8267 struct i40e_netdev_priv *np = netdev_priv(dev);
8268 struct i40e_vsi *vsi = np->vsi;
8269 struct i40e_pf *pf = vsi->back;
8270 struct i40e_veb *veb = NULL;
8271 struct nlattr *attr, *br_spec;
8272 int i, rem;
8273
8274 /* Only for PF VSI for now */
8275 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8276 return -EOPNOTSUPP;
8277
8278 /* Find the HW bridge for PF VSI */
8279 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8280 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8281 veb = pf->veb[i];
8282 }
8283
8284 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8285
8286 nla_for_each_nested(attr, br_spec, rem) {
8287 __u16 mode;
8288
8289 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8290 continue;
8291
8292 mode = nla_get_u16(attr);
8293 if ((mode != BRIDGE_MODE_VEPA) &&
8294 (mode != BRIDGE_MODE_VEB))
8295 return -EINVAL;
8296
8297 /* Insert a new HW bridge */
8298 if (!veb) {
8299 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8300 vsi->tc_config.enabled_tc);
8301 if (veb) {
8302 veb->bridge_mode = mode;
8303 i40e_config_bridge_mode(veb);
8304 } else {
8305 /* No Bridge HW offload available */
8306 return -ENOENT;
8307 }
8308 break;
8309 } else if (mode != veb->bridge_mode) {
8310 /* Existing HW bridge but different mode needs reset */
8311 veb->bridge_mode = mode;
fc60861e
ASJ		 8312 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8313 if (mode == BRIDGE_MODE_VEB)
8314 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8315 else
8316 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8317 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8318 break;
8319 }
8320 }
8321
8322 return 0;
8323}
8324
8325/**
8326 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8327 * @skb: skb buff
8328 * @pid: process id
8329 * @seq: RTNL message seq #
8330 * @dev: the netdev being configured
8331 * @filter_mask: unused
8332 *
8333 * Return the mode in which the hardware bridge is operating in
8334 * i.e VEB or VEPA.
8335 **/
51616018
NP		 8336static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8337 struct net_device *dev,
7d4f8d87 8338 u32 filter_mask, int nlflags)
51616018
NP		 8339{
8340 struct i40e_netdev_priv *np = netdev_priv(dev);
8341 struct i40e_vsi *vsi = np->vsi;
8342 struct i40e_pf *pf = vsi->back;
8343 struct i40e_veb *veb = NULL;
8344 int i;
8345
8346 /* Only for PF VSI for now */
8347 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8348 return -EOPNOTSUPP;
8349
8350 /* Find the HW bridge for the PF VSI */
8351 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8352 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8353 veb = pf->veb[i];
8354 }
8355
8356 if (!veb)
8357 return 0;
8358
46c264da 8359 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8360 nlflags, 0, 0, filter_mask, NULL);
51616018 8361}
51616018 8362
f44a75e2
JS		 8363#define I40E_MAX_TUNNEL_HDR_LEN 80
8364/**
8365 * i40e_features_check - Validate encapsulated packet conforms to limits
8366 * @skb: skb buff
8367 * @netdev: This physical port's netdev
8368 * @features: Offload features that the stack believes apply
8369 **/
8370static netdev_features_t i40e_features_check(struct sk_buff *skb,
8371 struct net_device *dev,
8372 netdev_features_t features)
8373{
8374 if (skb->encapsulation &&
8375 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8376 I40E_MAX_TUNNEL_HDR_LEN))
8377 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8378
8379 return features;
8380}
8381
37a2973a 8382static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8383 .ndo_open = i40e_open,
8384 .ndo_stop = i40e_close,
8385 .ndo_start_xmit = i40e_lan_xmit_frame,
8386 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8387 .ndo_set_rx_mode = i40e_set_rx_mode,
8388 .ndo_validate_addr = eth_validate_addr,
8389 .ndo_set_mac_address = i40e_set_mac,
8390 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8391 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8392 .ndo_tx_timeout = i40e_tx_timeout,
8393 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8394 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8395#ifdef CONFIG_NET_POLL_CONTROLLER
8396 .ndo_poll_controller = i40e_netpoll,
8397#endif
8398 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8399#ifdef I40E_FCOE
8400 .ndo_fcoe_enable = i40e_fcoe_enable,
8401 .ndo_fcoe_disable = i40e_fcoe_disable,
8402#endif
41c445ff
JB		 8403 .ndo_set_features = i40e_set_features,
8404 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8405 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8406 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8407 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8408 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8409 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8410#ifdef CONFIG_I40E_VXLAN
8411 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8412 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8413#endif
1f224ad2 8414 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8415 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8416 .ndo_features_check = i40e_features_check,
51616018
NP		 8417 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8418 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8419};
8420
8421/**
8422 * i40e_config_netdev - Setup the netdev flags
8423 * @vsi: the VSI being configured
8424 *
8425 * Returns 0 on success, negative value on failure
8426 **/
8427static int i40e_config_netdev(struct i40e_vsi *vsi)
8428{
1a10370a 8429 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8430 struct i40e_pf *pf = vsi->back;
8431 struct i40e_hw *hw = &pf->hw;
8432 struct i40e_netdev_priv *np;
8433 struct net_device *netdev;
8434 u8 mac_addr[ETH_ALEN];
8435 int etherdev_size;
8436
8437 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8438 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8439 if (!netdev)
8440 return -ENOMEM;
8441
8442 vsi->netdev = netdev;
8443 np = netdev_priv(netdev);
8444 np->vsi = vsi;
8445
d70e941b 8446 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8447 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 8448 NETIF_F_TSO;
41c445ff
JB		 8449
8450 netdev->features = NETIF_F_SG |
8451 NETIF_F_IP_CSUM |
8452 NETIF_F_SCTP_CSUM |
8453 NETIF_F_HIGHDMA |
8454 NETIF_F_GSO_UDP_TUNNEL |
8455 NETIF_F_HW_VLAN_CTAG_TX |
8456 NETIF_F_HW_VLAN_CTAG_RX |
8457 NETIF_F_HW_VLAN_CTAG_FILTER |
8458 NETIF_F_IPV6_CSUM |
8459 NETIF_F_TSO |
059dab69 8460 NETIF_F_TSO_ECN |
41c445ff
JB		 8461 NETIF_F_TSO6 |
8462 NETIF_F_RXCSUM |
8463 NETIF_F_RXHASH |
8464 0;
8465
2e86a0b6
ASJ		 8466 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8467 netdev->features |= NETIF_F_NTUPLE;
8468
41c445ff
JB		 8469 /* copy netdev features into list of user selectable features */
8470 netdev->hw_features |= netdev->features;
8471
8472 if (vsi->type == I40E_VSI_MAIN) {
8473 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8474 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8475 /* The following steps are necessary to prevent reception
8476 * of tagged packets - some older NVM configurations load a
8477 * default a MAC-VLAN filter that accepts any tagged packet
8478 * which must be replaced by a normal filter.
8c27d42e 8479 */
30650cc5
SN		 8480 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8481 i40e_add_filter(vsi, mac_addr,
8482 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8483 } else {
8484 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8485 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8486 pf->vsi[pf->lan_vsi]->netdev->name);
8487 random_ether_addr(mac_addr);
8488 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8489 }
1a10370a 8490 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8491
9a173901
GR		 8492 ether_addr_copy(netdev->dev_addr, mac_addr);
8493 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8494 /* vlan gets same features (except vlan offload)
8495 * after any tweaks for specific VSI types
8496 */
8497 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8498 NETIF_F_HW_VLAN_CTAG_RX |
8499 NETIF_F_HW_VLAN_CTAG_FILTER);
8500 netdev->priv_flags |= IFF_UNICAST_FLT;
8501 netdev->priv_flags |= IFF_SUPP_NOFCS;
8502 /* Setup netdev TC information */
8503 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8504
8505 netdev->netdev_ops = &i40e_netdev_ops;
8506 netdev->watchdog_timeo = 5 * HZ;
8507 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8508#ifdef I40E_FCOE
8509 i40e_fcoe_config_netdev(netdev, vsi);
8510#endif
41c445ff
JB		 8511
8512 return 0;
8513}
8514
8515/**
8516 * i40e_vsi_delete - Delete a VSI from the switch
8517 * @vsi: the VSI being removed
8518 *
8519 * Returns 0 on success, negative value on failure
8520 **/
8521static void i40e_vsi_delete(struct i40e_vsi *vsi)
8522{
8523 /* remove default VSI is not allowed */
8524 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8525 return;
8526
41c445ff 8527 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8528}
8529
51616018
NP		 8530/**
8531 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8532 * @vsi: the VSI being queried
8533 *
8534 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8535 **/
8536int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8537{
8538 struct i40e_veb *veb;
8539 struct i40e_pf *pf = vsi->back;
8540
8541 /* Uplink is not a bridge so default to VEB */
8542 if (vsi->veb_idx == I40E_NO_VEB)
8543 return 1;
8544
8545 veb = pf->veb[vsi->veb_idx];
8546 /* Uplink is a bridge in VEPA mode */
8547 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8548 return 0;
8549
8550 /* Uplink is a bridge in VEB mode */
8551 return 1;
8552}
8553
41c445ff
JB		 8554/**
8555 * i40e_add_vsi - Add a VSI to the switch
8556 * @vsi: the VSI being configured
8557 *
8558 * This initializes a VSI context depending on the VSI type to be added and
8559 * passes it down to the add_vsi aq command.
8560 **/
8561static int i40e_add_vsi(struct i40e_vsi *vsi)
8562{
8563 int ret = -ENODEV;
8564 struct i40e_mac_filter *f, *ftmp;
8565 struct i40e_pf *pf = vsi->back;
8566 struct i40e_hw *hw = &pf->hw;
8567 struct i40e_vsi_context ctxt;
8568 u8 enabled_tc = 0x1; /* TC0 enabled */
8569 int f_count = 0;
8570
8571 memset(&ctxt, 0, sizeof(ctxt));
8572 switch (vsi->type) {
8573 case I40E_VSI_MAIN:
8574 /* The PF's main VSI is already setup as part of the
8575 * device initialization, so we'll not bother with
8576 * the add_vsi call, but we will retrieve the current
8577 * VSI context.
8578 */
8579 ctxt.seid = pf->main_vsi_seid;
8580 ctxt.pf_num = pf->hw.pf_id;
8581 ctxt.vf_num = 0;
8582 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8583 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8584 if (ret) {
8585 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8586 "couldn't get PF vsi config, err %s aq_err %s\n",
8587 i40e_stat_str(&pf->hw, ret),
8588 i40e_aq_str(&pf->hw,
8589 pf->hw.aq.asq_last_status));
41c445ff
JB		 8590 return -ENOENT;
8591 }
1a2f6248 8592 vsi->info = ctxt.info;
41c445ff
JB		 8593 vsi->info.valid_sections = 0;
8594
8595 vsi->seid = ctxt.seid;
8596 vsi->id = ctxt.vsi_number;
8597
8598 enabled_tc = i40e_pf_get_tc_map(pf);
8599
8600 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8601 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8602 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8603 memset(&ctxt, 0, sizeof(ctxt));
8604 ctxt.seid = pf->main_vsi_seid;
8605 ctxt.pf_num = pf->hw.pf_id;
8606 ctxt.vf_num = 0;
8607 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8608 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8609 if (ret) {
8610 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8611 "update vsi failed, err %s aq_err %s\n",
8612 i40e_stat_str(&pf->hw, ret),
8613 i40e_aq_str(&pf->hw,
8614 pf->hw.aq.asq_last_status));
41c445ff
JB		 8615 ret = -ENOENT;
8616 goto err;
8617 }
8618 /* update the local VSI info queue map */
8619 i40e_vsi_update_queue_map(vsi, &ctxt);
8620 vsi->info.valid_sections = 0;
8621 } else {
8622 /* Default/Main VSI is only enabled for TC0
8623 * reconfigure it to enable all TCs that are
8624 * available on the port in SFP mode.
63d7e5a4
NP		 8625 * For MFP case the iSCSI PF would use this
8626 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8627 */
8628 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8629 if (ret) {
8630 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8631 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
8632 enabled_tc,
8633 i40e_stat_str(&pf->hw, ret),
8634 i40e_aq_str(&pf->hw,
8635 pf->hw.aq.asq_last_status));
41c445ff
JB		 8636 ret = -ENOENT;
8637 }
8638 }
8639 break;
8640
8641 case I40E_VSI_FDIR:
cbf61325
ASJ		 8642 ctxt.pf_num = hw->pf_id;
8643 ctxt.vf_num = 0;
8644 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8645 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8646 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 8647 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
8648 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 8649 ctxt.info.valid_sections |=
fc60861e 8650 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8651 ctxt.info.switch_id =
fc60861e 8652 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8653 }
41c445ff 8654 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8655 break;
8656
8657 case I40E_VSI_VMDQ2:
8658 ctxt.pf_num = hw->pf_id;
8659 ctxt.vf_num = 0;
8660 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8661 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8662 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8663
41c445ff
JB		 8664 /* This VSI is connected to VEB so the switch_id
8665 * should be set to zero by default.
8666 */
51616018
NP		 8667 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8668 ctxt.info.valid_sections |=
8669 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8670 ctxt.info.switch_id =
8671 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8672 }
41c445ff
JB		 8673
8674 /* Setup the VSI tx/rx queue map for TC0 only for now */
8675 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8676 break;
8677
8678 case I40E_VSI_SRIOV:
8679 ctxt.pf_num = hw->pf_id;
8680 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8681 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8682 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8683 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8684
41c445ff
JB		 8685 /* This VSI is connected to VEB so the switch_id
8686 * should be set to zero by default.
8687 */
51616018
NP		 8688 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8689 ctxt.info.valid_sections |=
8690 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8691 ctxt.info.switch_id =
8692 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8693 }
41c445ff
JB		 8694
8695 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8696 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8697 if (pf->vf[vsi->vf_id].spoofchk) {
8698 ctxt.info.valid_sections |=
8699 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8700 ctxt.info.sec_flags |=
8701 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8702 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8703 }
41c445ff
JB		 8704 /* Setup the VSI tx/rx queue map for TC0 only for now */
8705 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8706 break;
8707
38e00438
VD		 8708#ifdef I40E_FCOE
8709 case I40E_VSI_FCOE:
8710 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8711 if (ret) {
8712 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8713 return ret;
8714 }
8715 break;
8716
8717#endif /* I40E_FCOE */
41c445ff
JB		 8718 default:
8719 return -ENODEV;
8720 }
8721
8722 if (vsi->type != I40E_VSI_MAIN) {
8723 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8724 if (ret) {
8725 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 8726 "add vsi failed, err %s aq_err %s\n",
8727 i40e_stat_str(&pf->hw, ret),
8728 i40e_aq_str(&pf->hw,
8729 pf->hw.aq.asq_last_status));
41c445ff
JB		 8730 ret = -ENOENT;
8731 goto err;
8732 }
1a2f6248 8733 vsi->info = ctxt.info;
41c445ff
JB		 8734 vsi->info.valid_sections = 0;
8735 vsi->seid = ctxt.seid;
8736 vsi->id = ctxt.vsi_number;
8737 }
8738
8739 /* If macvlan filters already exist, force them to get loaded */
8740 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8741 f->changed = true;
8742 f_count++;
6252c7e4
SN		 8743
8744 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8745 struct i40e_aqc_remove_macvlan_element_data element;
8746
8747 memset(&element, 0, sizeof(element));
8748 ether_addr_copy(element.mac_addr, f->macaddr);
8749 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8750 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8751 &element, 1, NULL);
8752 if (ret) {
8753 /* some older FW has a different default */
8754 element.flags |=
8755 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8756 i40e_aq_remove_macvlan(hw, vsi->seid,
8757 &element, 1, NULL);
8758 }
8759
8760 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8761 I40E_AQC_WRITE_TYPE_LAA_WOL,
8762 f->macaddr, NULL);
8763 }
41c445ff
JB		 8764 }
8765 if (f_count) {
8766 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8767 pf->flags |= I40E_FLAG_FILTER_SYNC;
8768 }
8769
8770 /* Update VSI BW information */
8771 ret = i40e_vsi_get_bw_info(vsi);
8772 if (ret) {
8773 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8774 "couldn't get vsi bw info, err %s aq_err %s\n",
8775 i40e_stat_str(&pf->hw, ret),
8776 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 8777 /* VSI is already added so not tearing that up */
8778 ret = 0;
8779 }
8780
8781err:
8782 return ret;
8783}
8784
8785/**
8786 * i40e_vsi_release - Delete a VSI and free its resources
8787 * @vsi: the VSI being removed
8788 *
8789 * Returns 0 on success or < 0 on error
8790 **/
8791int i40e_vsi_release(struct i40e_vsi *vsi)
8792{
8793 struct i40e_mac_filter *f, *ftmp;
8794 struct i40e_veb *veb = NULL;
8795 struct i40e_pf *pf;
8796 u16 uplink_seid;
8797 int i, n;
8798
8799 pf = vsi->back;
8800
8801 /* release of a VEB-owner or last VSI is not allowed */
8802 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8803 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8804 vsi->seid, vsi->uplink_seid);
8805 return -ENODEV;
8806 }
8807 if (vsi == pf->vsi[pf->lan_vsi] &&
8808 !test_bit(__I40E_DOWN, &pf->state)) {
8809 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8810 return -ENODEV;
8811 }
8812
8813 uplink_seid = vsi->uplink_seid;
8814 if (vsi->type != I40E_VSI_SRIOV) {
8815 if (vsi->netdev_registered) {
8816 vsi->netdev_registered = false;
8817 if (vsi->netdev) {
8818 /* results in a call to i40e_close() */
8819 unregister_netdev(vsi->netdev);
41c445ff
JB		 8820 }
8821 } else {
90ef8d47 8822 i40e_vsi_close(vsi);
41c445ff
JB		 8823 }
8824 i40e_vsi_disable_irq(vsi);
8825 }
8826
8827 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8828 i40e_del_filter(vsi, f->macaddr, f->vlan,
8829 f->is_vf, f->is_netdev);
30e2561b 8830 i40e_sync_vsi_filters(vsi, false);
41c445ff
JB		 8831
8832 i40e_vsi_delete(vsi);
8833 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8834 if (vsi->netdev) {
8835 free_netdev(vsi->netdev);
8836 vsi->netdev = NULL;
8837 }
41c445ff
JB		 8838 i40e_vsi_clear_rings(vsi);
8839 i40e_vsi_clear(vsi);
8840
8841 /* If this was the last thing on the VEB, except for the
8842 * controlling VSI, remove the VEB, which puts the controlling
8843 * VSI onto the next level down in the switch.
8844 *
8845 * Well, okay, there's one more exception here: don't remove
8846 * the orphan VEBs yet. We'll wait for an explicit remove request
8847 * from up the network stack.
8848 */
505682cd 8849 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8850 if (pf->vsi[i] &&
8851 pf->vsi[i]->uplink_seid == uplink_seid &&
8852 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8853 n++; /* count the VSIs */
8854 }
8855 }
8856 for (i = 0; i < I40E_MAX_VEB; i++) {
8857 if (!pf->veb[i])
8858 continue;
8859 if (pf->veb[i]->uplink_seid == uplink_seid)
8860 n++; /* count the VEBs */
8861 if (pf->veb[i]->seid == uplink_seid)
8862 veb = pf->veb[i];
8863 }
8864 if (n == 0 && veb && veb->uplink_seid != 0)
8865 i40e_veb_release(veb);
8866
8867 return 0;
8868}
8869
8870/**
8871 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8872 * @vsi: ptr to the VSI
8873 *
8874 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8875 * corresponding SW VSI structure and initializes num_queue_pairs for the
8876 * newly allocated VSI.
8877 *
8878 * Returns 0 on success or negative on failure
8879 **/
8880static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8881{
8882 int ret = -ENOENT;
8883 struct i40e_pf *pf = vsi->back;
8884
493fb300 8885 if (vsi->q_vectors[0]) {
41c445ff
JB		 8886 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8887 vsi->seid);
8888 return -EEXIST;
8889 }
8890
8891 if (vsi->base_vector) {
f29eaa3d 8892 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8893 vsi->seid, vsi->base_vector);
8894 return -EEXIST;
8895 }
8896
90e04070 8897 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8898 if (ret) {
8899 dev_info(&pf->pdev->dev,
8900 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8901 vsi->num_q_vectors, vsi->seid, ret);
8902 vsi->num_q_vectors = 0;
8903 goto vector_setup_out;
8904 }
8905
26cdc443
ASJ		 8906 /* In Legacy mode, we do not have to get any other vector since we
8907 * piggyback on the misc/ICR0 for queue interrupts.
8908 */
8909 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
8910 return ret;
958a3e3b
SN		 8911 if (vsi->num_q_vectors)
8912 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8913 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8914 if (vsi->base_vector < 0) {
8915 dev_info(&pf->pdev->dev,
049a2be8
SN		 8916 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8917 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8918 i40e_vsi_free_q_vectors(vsi);
8919 ret = -ENOENT;
8920 goto vector_setup_out;
8921 }
8922
8923vector_setup_out:
8924 return ret;
8925}
8926
bc7d338f
ASJ		 8927/**
8928 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8929 * @vsi: pointer to the vsi.
8930 *
8931 * This re-allocates a vsi's queue resources.
8932 *
8933 * Returns pointer to the successfully allocated and configured VSI sw struct
8934 * on success, otherwise returns NULL on failure.
8935 **/
8936static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8937{
8938 struct i40e_pf *pf = vsi->back;
8939 u8 enabled_tc;
8940 int ret;
8941
8942 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8943 i40e_vsi_clear_rings(vsi);
8944
8945 i40e_vsi_free_arrays(vsi, false);
8946 i40e_set_num_rings_in_vsi(vsi);
8947 ret = i40e_vsi_alloc_arrays(vsi, false);
8948 if (ret)
8949 goto err_vsi;
8950
8951 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8952 if (ret < 0) {
049a2be8 8953 dev_info(&pf->pdev->dev,
f1c7e72e 8954 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 8955 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8956 goto err_vsi;
8957 }
8958 vsi->base_queue = ret;
8959
8960 /* Update the FW view of the VSI. Force a reset of TC and queue
8961 * layout configurations.
8962 */
8963 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8964 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8965 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8966 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8967
8968 /* assign it some queues */
8969 ret = i40e_alloc_rings(vsi);
8970 if (ret)
8971 goto err_rings;
8972
8973 /* map all of the rings to the q_vectors */
8974 i40e_vsi_map_rings_to_vectors(vsi);
8975 return vsi;
8976
8977err_rings:
8978 i40e_vsi_free_q_vectors(vsi);
8979 if (vsi->netdev_registered) {
8980 vsi->netdev_registered = false;
8981 unregister_netdev(vsi->netdev);
8982 free_netdev(vsi->netdev);
8983 vsi->netdev = NULL;
8984 }
8985 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8986err_vsi:
8987 i40e_vsi_clear(vsi);
8988 return NULL;
8989}
8990
41c445ff
JB		 8991/**
8992 * i40e_vsi_setup - Set up a VSI by a given type
8993 * @pf: board private structure
8994 * @type: VSI type
8995 * @uplink_seid: the switch element to link to
8996 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8997 *
8998 * This allocates the sw VSI structure and its queue resources, then add a VSI
8999 * to the identified VEB.
9000 *
9001 * Returns pointer to the successfully allocated and configure VSI sw struct on
9002 * success, otherwise returns NULL on failure.
9003 **/
9004struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9005 u16 uplink_seid, u32 param1)
9006{
9007 struct i40e_vsi *vsi = NULL;
9008 struct i40e_veb *veb = NULL;
9009 int ret, i;
9010 int v_idx;
9011
9012 /* The requested uplink_seid must be either
9013 * - the PF's port seid
9014 * no VEB is needed because this is the PF
9015 * or this is a Flow Director special case VSI
9016 * - seid of an existing VEB
9017 * - seid of a VSI that owns an existing VEB
9018 * - seid of a VSI that doesn't own a VEB
9019 * a new VEB is created and the VSI becomes the owner
9020 * - seid of the PF VSI, which is what creates the first VEB
9021 * this is a special case of the previous
9022 *
9023 * Find which uplink_seid we were given and create a new VEB if needed
9024 */
9025 for (i = 0; i < I40E_MAX_VEB; i++) {
9026 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9027 veb = pf->veb[i];
9028 break;
9029 }
9030 }
9031
9032 if (!veb && uplink_seid != pf->mac_seid) {
9033
505682cd 9034 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9035 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9036 vsi = pf->vsi[i];
9037 break;
9038 }
9039 }
9040 if (!vsi) {
9041 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9042 uplink_seid);
9043 return NULL;
9044 }
9045
9046 if (vsi->uplink_seid == pf->mac_seid)
9047 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9048 vsi->tc_config.enabled_tc);
9049 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9050 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9051 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9052 if (veb) {
9053 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9054 dev_info(&vsi->back->pdev->dev,
9055 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
9056 __func__);
9057 return NULL;
9058 }
fa11cb3d
ASJ		 9059 /* We come up by default in VEPA mode if SRIOV is not
9060 * already enabled, in which case we can't force VEPA
9061 * mode.
9062 */
9063 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9064 veb->bridge_mode = BRIDGE_MODE_VEPA;
9065 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9066 }
51616018 9067 i40e_config_bridge_mode(veb);
79c21a82 9068 }
41c445ff
JB		 9069 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9070 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9071 veb = pf->veb[i];
9072 }
9073 if (!veb) {
9074 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9075 return NULL;
9076 }
9077
9078 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9079 uplink_seid = veb->seid;
9080 }
9081
9082 /* get vsi sw struct */
9083 v_idx = i40e_vsi_mem_alloc(pf, type);
9084 if (v_idx < 0)
9085 goto err_alloc;
9086 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9087 if (!vsi)
9088 goto err_alloc;
41c445ff
JB		 9089 vsi->type = type;
9090 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9091
9092 if (type == I40E_VSI_MAIN)
9093 pf->lan_vsi = v_idx;
9094 else if (type == I40E_VSI_SRIOV)
9095 vsi->vf_id = param1;
9096 /* assign it some queues */
cbf61325
ASJ		 9097 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9098 vsi->idx);
41c445ff 9099 if (ret < 0) {
049a2be8
SN		 9100 dev_info(&pf->pdev->dev,
9101 "failed to get tracking for %d queues for VSI %d err=%d\n",
9102 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9103 goto err_vsi;
9104 }
9105 vsi->base_queue = ret;
9106
9107 /* get a VSI from the hardware */
9108 vsi->uplink_seid = uplink_seid;
9109 ret = i40e_add_vsi(vsi);
9110 if (ret)
9111 goto err_vsi;
9112
9113 switch (vsi->type) {
9114 /* setup the netdev if needed */
9115 case I40E_VSI_MAIN:
9116 case I40E_VSI_VMDQ2:
38e00438 9117 case I40E_VSI_FCOE:
41c445ff
JB		 9118 ret = i40e_config_netdev(vsi);
9119 if (ret)
9120 goto err_netdev;
9121 ret = register_netdev(vsi->netdev);
9122 if (ret)
9123 goto err_netdev;
9124 vsi->netdev_registered = true;
9125 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9126#ifdef CONFIG_I40E_DCB
9127 /* Setup DCB netlink interface */
9128 i40e_dcbnl_setup(vsi);
9129#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9130 /* fall through */
9131
9132 case I40E_VSI_FDIR:
9133 /* set up vectors and rings if needed */
9134 ret = i40e_vsi_setup_vectors(vsi);
9135 if (ret)
9136 goto err_msix;
9137
9138 ret = i40e_alloc_rings(vsi);
9139 if (ret)
9140 goto err_rings;
9141
9142 /* map all of the rings to the q_vectors */
9143 i40e_vsi_map_rings_to_vectors(vsi);
9144
9145 i40e_vsi_reset_stats(vsi);
9146 break;
9147
9148 default:
9149 /* no netdev or rings for the other VSI types */
9150 break;
9151 }
9152
e25d00b8
ASJ		 9153 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9154 (vsi->type == I40E_VSI_VMDQ2)) {
9155 ret = i40e_vsi_config_rss(vsi);
9156 }
41c445ff
JB		 9157 return vsi;
9158
9159err_rings:
9160 i40e_vsi_free_q_vectors(vsi);
9161err_msix:
9162 if (vsi->netdev_registered) {
9163 vsi->netdev_registered = false;
9164 unregister_netdev(vsi->netdev);
9165 free_netdev(vsi->netdev);
9166 vsi->netdev = NULL;
9167 }
9168err_netdev:
9169 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9170err_vsi:
9171 i40e_vsi_clear(vsi);
9172err_alloc:
9173 return NULL;
9174}
9175
9176/**
9177 * i40e_veb_get_bw_info - Query VEB BW information
9178 * @veb: the veb to query
9179 *
9180 * Query the Tx scheduler BW configuration data for given VEB
9181 **/
9182static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9183{
9184 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9185 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9186 struct i40e_pf *pf = veb->pf;
9187 struct i40e_hw *hw = &pf->hw;
9188 u32 tc_bw_max;
9189 int ret = 0;
9190 int i;
9191
9192 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9193 &bw_data, NULL);
9194 if (ret) {
9195 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9196 "query veb bw config failed, err %s aq_err %s\n",
9197 i40e_stat_str(&pf->hw, ret),
9198 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9199 goto out;
9200 }
9201
9202 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9203 &ets_data, NULL);
9204 if (ret) {
9205 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9206 "query veb bw ets config failed, err %s aq_err %s\n",
9207 i40e_stat_str(&pf->hw, ret),
9208 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9209 goto out;
9210 }
9211
9212 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9213 veb->bw_max_quanta = ets_data.tc_bw_max;
9214 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9215 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9216 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9217 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9218 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9219 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9220 veb->bw_tc_limit_credits[i] =
9221 le16_to_cpu(bw_data.tc_bw_limits[i]);
9222 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9223 }
9224
9225out:
9226 return ret;
9227}
9228
9229/**
9230 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9231 * @pf: board private structure
9232 *
9233 * On error: returns error code (negative)
9234 * On success: returns vsi index in PF (positive)
9235 **/
9236static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9237{
9238 int ret = -ENOENT;
9239 struct i40e_veb *veb;
9240 int i;
9241
9242 /* Need to protect the allocation of switch elements at the PF level */
9243 mutex_lock(&pf->switch_mutex);
9244
9245 /* VEB list may be fragmented if VEB creation/destruction has
9246 * been happening. We can afford to do a quick scan to look
9247 * for any free slots in the list.
9248 *
9249 * find next empty veb slot, looping back around if necessary
9250 */
9251 i = 0;
9252 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9253 i++;
9254 if (i >= I40E_MAX_VEB) {
9255 ret = -ENOMEM;
9256 goto err_alloc_veb; /* out of VEB slots! */
9257 }
9258
9259 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9260 if (!veb) {
9261 ret = -ENOMEM;
9262 goto err_alloc_veb;
9263 }
9264 veb->pf = pf;
9265 veb->idx = i;
9266 veb->enabled_tc = 1;
9267
9268 pf->veb[i] = veb;
9269 ret = i;
9270err_alloc_veb:
9271 mutex_unlock(&pf->switch_mutex);
9272 return ret;
9273}
9274
9275/**
9276 * i40e_switch_branch_release - Delete a branch of the switch tree
9277 * @branch: where to start deleting
9278 *
9279 * This uses recursion to find the tips of the branch to be
9280 * removed, deleting until we get back to and can delete this VEB.
9281 **/
9282static void i40e_switch_branch_release(struct i40e_veb *branch)
9283{
9284 struct i40e_pf *pf = branch->pf;
9285 u16 branch_seid = branch->seid;
9286 u16 veb_idx = branch->idx;
9287 int i;
9288
9289 /* release any VEBs on this VEB - RECURSION */
9290 for (i = 0; i < I40E_MAX_VEB; i++) {
9291 if (!pf->veb[i])
9292 continue;
9293 if (pf->veb[i]->uplink_seid == branch->seid)
9294 i40e_switch_branch_release(pf->veb[i]);
9295 }
9296
9297 /* Release the VSIs on this VEB, but not the owner VSI.
9298 *
9299 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9300 * the VEB itself, so don't use (*branch) after this loop.
9301 */
505682cd 9302 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9303 if (!pf->vsi[i])
9304 continue;
9305 if (pf->vsi[i]->uplink_seid == branch_seid &&
9306 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9307 i40e_vsi_release(pf->vsi[i]);
9308 }
9309 }
9310
9311 /* There's one corner case where the VEB might not have been
9312 * removed, so double check it here and remove it if needed.
9313 * This case happens if the veb was created from the debugfs
9314 * commands and no VSIs were added to it.
9315 */
9316 if (pf->veb[veb_idx])
9317 i40e_veb_release(pf->veb[veb_idx]);
9318}
9319
9320/**
9321 * i40e_veb_clear - remove veb struct
9322 * @veb: the veb to remove
9323 **/
9324static void i40e_veb_clear(struct i40e_veb *veb)
9325{
9326 if (!veb)
9327 return;
9328
9329 if (veb->pf) {
9330 struct i40e_pf *pf = veb->pf;
9331
9332 mutex_lock(&pf->switch_mutex);
9333 if (pf->veb[veb->idx] == veb)
9334 pf->veb[veb->idx] = NULL;
9335 mutex_unlock(&pf->switch_mutex);
9336 }
9337
9338 kfree(veb);
9339}
9340
9341/**
9342 * i40e_veb_release - Delete a VEB and free its resources
9343 * @veb: the VEB being removed
9344 **/
9345void i40e_veb_release(struct i40e_veb *veb)
9346{
9347 struct i40e_vsi *vsi = NULL;
9348 struct i40e_pf *pf;
9349 int i, n = 0;
9350
9351 pf = veb->pf;
9352
9353 /* find the remaining VSI and check for extras */
505682cd 9354 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9355 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9356 n++;
9357 vsi = pf->vsi[i];
9358 }
9359 }
9360 if (n != 1) {
9361 dev_info(&pf->pdev->dev,
9362 "can't remove VEB %d with %d VSIs left\n",
9363 veb->seid, n);
9364 return;
9365 }
9366
9367 /* move the remaining VSI to uplink veb */
9368 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9369 if (veb->uplink_seid) {
9370 vsi->uplink_seid = veb->uplink_seid;
9371 if (veb->uplink_seid == pf->mac_seid)
9372 vsi->veb_idx = I40E_NO_VEB;
9373 else
9374 vsi->veb_idx = veb->veb_idx;
9375 } else {
9376 /* floating VEB */
9377 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9378 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9379 }
9380
9381 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9382 i40e_veb_clear(veb);
41c445ff
JB		 9383}
9384
9385/**
9386 * i40e_add_veb - create the VEB in the switch
9387 * @veb: the VEB to be instantiated
9388 * @vsi: the controlling VSI
9389 **/
9390static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9391{
f1c7e72e 9392 struct i40e_pf *pf = veb->pf;
92faef85 9393 bool is_default = veb->pf->cur_promisc;
e1c51b95 9394 bool is_cloud = false;
41c445ff
JB		 9395 int ret;
9396
9397 /* get a VEB from the hardware */
f1c7e72e 9398 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9399 veb->enabled_tc, is_default,
9400 is_cloud, &veb->seid, NULL);
41c445ff 9401 if (ret) {
f1c7e72e
SN		 9402 dev_info(&pf->pdev->dev,
9403 "couldn't add VEB, err %s aq_err %s\n",
9404 i40e_stat_str(&pf->hw, ret),
9405 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9406 return -EPERM;
9407 }
9408
9409 /* get statistics counter */
f1c7e72e 9410 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9411 &veb->stats_idx, NULL, NULL, NULL);
9412 if (ret) {
f1c7e72e
SN		 9413 dev_info(&pf->pdev->dev,
9414 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9415 i40e_stat_str(&pf->hw, ret),
9416 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9417 return -EPERM;
9418 }
9419 ret = i40e_veb_get_bw_info(veb);
9420 if (ret) {
f1c7e72e
SN		 9421 dev_info(&pf->pdev->dev,
9422 "couldn't get VEB bw info, err %s aq_err %s\n",
9423 i40e_stat_str(&pf->hw, ret),
9424 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9425 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9426 return -ENOENT;
9427 }
9428
9429 vsi->uplink_seid = veb->seid;
9430 vsi->veb_idx = veb->idx;
9431 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9432
9433 return 0;
9434}
9435
9436/**
9437 * i40e_veb_setup - Set up a VEB
9438 * @pf: board private structure
9439 * @flags: VEB setup flags
9440 * @uplink_seid: the switch element to link to
9441 * @vsi_seid: the initial VSI seid
9442 * @enabled_tc: Enabled TC bit-map
9443 *
9444 * This allocates the sw VEB structure and links it into the switch
9445 * It is possible and legal for this to be a duplicate of an already
9446 * existing VEB. It is also possible for both uplink and vsi seids
9447 * to be zero, in order to create a floating VEB.
9448 *
9449 * Returns pointer to the successfully allocated VEB sw struct on
9450 * success, otherwise returns NULL on failure.
9451 **/
9452struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9453 u16 uplink_seid, u16 vsi_seid,
9454 u8 enabled_tc)
9455{
9456 struct i40e_veb *veb, *uplink_veb = NULL;
9457 int vsi_idx, veb_idx;
9458 int ret;
9459
9460 /* if one seid is 0, the other must be 0 to create a floating relay */
9461 if ((uplink_seid == 0 || vsi_seid == 0) &&
9462 (uplink_seid + vsi_seid != 0)) {
9463 dev_info(&pf->pdev->dev,
9464 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9465 uplink_seid, vsi_seid);
9466 return NULL;
9467 }
9468
9469 /* make sure there is such a vsi and uplink */
505682cd 9470 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9471 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9472 break;
505682cd 9473 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9474 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9475 vsi_seid);
9476 return NULL;
9477 }
9478
9479 if (uplink_seid && uplink_seid != pf->mac_seid) {
9480 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9481 if (pf->veb[veb_idx] &&
9482 pf->veb[veb_idx]->seid == uplink_seid) {
9483 uplink_veb = pf->veb[veb_idx];
9484 break;
9485 }
9486 }
9487 if (!uplink_veb) {
9488 dev_info(&pf->pdev->dev,
9489 "uplink seid %d not found\n", uplink_seid);
9490 return NULL;
9491 }
9492 }
9493
9494 /* get veb sw struct */
9495 veb_idx = i40e_veb_mem_alloc(pf);
9496 if (veb_idx < 0)
9497 goto err_alloc;
9498 veb = pf->veb[veb_idx];
9499 veb->flags = flags;
9500 veb->uplink_seid = uplink_seid;
9501 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9502 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9503
9504 /* create the VEB in the switch */
9505 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9506 if (ret)
9507 goto err_veb;
1bb8b935
SN		 9508 if (vsi_idx == pf->lan_vsi)
9509 pf->lan_veb = veb->idx;
41c445ff
JB		 9510
9511 return veb;
9512
9513err_veb:
9514 i40e_veb_clear(veb);
9515err_alloc:
9516 return NULL;
9517}
9518
9519/**
b40c82e6 9520 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9521 * @pf: board private structure
9522 * @ele: element we are building info from
9523 * @num_reported: total number of elements
9524 * @printconfig: should we print the contents
9525 *
9526 * helper function to assist in extracting a few useful SEID values.
9527 **/
9528static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9529 struct i40e_aqc_switch_config_element_resp *ele,
9530 u16 num_reported, bool printconfig)
9531{
9532 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9533 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9534 u8 element_type = ele->element_type;
9535 u16 seid = le16_to_cpu(ele->seid);
9536
9537 if (printconfig)
9538 dev_info(&pf->pdev->dev,
9539 "type=%d seid=%d uplink=%d downlink=%d\n",
9540 element_type, seid, uplink_seid, downlink_seid);
9541
9542 switch (element_type) {
9543 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9544 pf->mac_seid = seid;
9545 break;
9546 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9547 /* Main VEB? */
9548 if (uplink_seid != pf->mac_seid)
9549 break;
9550 if (pf->lan_veb == I40E_NO_VEB) {
9551 int v;
9552
9553 /* find existing or else empty VEB */
9554 for (v = 0; v < I40E_MAX_VEB; v++) {
9555 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9556 pf->lan_veb = v;
9557 break;
9558 }
9559 }
9560 if (pf->lan_veb == I40E_NO_VEB) {
9561 v = i40e_veb_mem_alloc(pf);
9562 if (v < 0)
9563 break;
9564 pf->lan_veb = v;
9565 }
9566 }
9567
9568 pf->veb[pf->lan_veb]->seid = seid;
9569 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9570 pf->veb[pf->lan_veb]->pf = pf;
9571 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9572 break;
9573 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9574 if (num_reported != 1)
9575 break;
9576 /* This is immediately after a reset so we can assume this is
9577 * the PF's VSI
9578 */
9579 pf->mac_seid = uplink_seid;
9580 pf->pf_seid = downlink_seid;
9581 pf->main_vsi_seid = seid;
9582 if (printconfig)
9583 dev_info(&pf->pdev->dev,
9584 "pf_seid=%d main_vsi_seid=%d\n",
9585 pf->pf_seid, pf->main_vsi_seid);
9586 break;
9587 case I40E_SWITCH_ELEMENT_TYPE_PF:
9588 case I40E_SWITCH_ELEMENT_TYPE_VF:
9589 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9590 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9591 case I40E_SWITCH_ELEMENT_TYPE_PE:
9592 case I40E_SWITCH_ELEMENT_TYPE_PA:
9593 /* ignore these for now */
9594 break;
9595 default:
9596 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9597 element_type, seid);
9598 break;
9599 }
9600}
9601
9602/**
9603 * i40e_fetch_switch_configuration - Get switch config from firmware
9604 * @pf: board private structure
9605 * @printconfig: should we print the contents
9606 *
9607 * Get the current switch configuration from the device and
9608 * extract a few useful SEID values.
9609 **/
9610int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9611{
9612 struct i40e_aqc_get_switch_config_resp *sw_config;
9613 u16 next_seid = 0;
9614 int ret = 0;
9615 u8 *aq_buf;
9616 int i;
9617
9618 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9619 if (!aq_buf)
9620 return -ENOMEM;
9621
9622 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9623 do {
9624 u16 num_reported, num_total;
9625
9626 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9627 I40E_AQ_LARGE_BUF,
9628 &next_seid, NULL);
9629 if (ret) {
9630 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9631 "get switch config failed err %s aq_err %s\n",
9632 i40e_stat_str(&pf->hw, ret),
9633 i40e_aq_str(&pf->hw,
9634 pf->hw.aq.asq_last_status));
41c445ff
JB		 9635 kfree(aq_buf);
9636 return -ENOENT;
9637 }
9638
9639 num_reported = le16_to_cpu(sw_config->header.num_reported);
9640 num_total = le16_to_cpu(sw_config->header.num_total);
9641
9642 if (printconfig)
9643 dev_info(&pf->pdev->dev,
9644 "header: %d reported %d total\n",
9645 num_reported, num_total);
9646
41c445ff
JB		 9647 for (i = 0; i < num_reported; i++) {
9648 struct i40e_aqc_switch_config_element_resp *ele =
9649 &sw_config->element[i];
9650
9651 i40e_setup_pf_switch_element(pf, ele, num_reported,
9652 printconfig);
9653 }
9654 } while (next_seid != 0);
9655
9656 kfree(aq_buf);
9657 return ret;
9658}
9659
9660/**
9661 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9662 * @pf: board private structure
bc7d338f 9663 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9664 *
9665 * Returns 0 on success, negative value on failure
9666 **/
bc7d338f 9667static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9668{
9669 int ret;
9670
9671 /* find out what's out there already */
9672 ret = i40e_fetch_switch_configuration(pf, false);
9673 if (ret) {
9674 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9675 "couldn't fetch switch config, err %s aq_err %s\n",
9676 i40e_stat_str(&pf->hw, ret),
9677 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9678 return ret;
9679 }
9680 i40e_pf_reset_stats(pf);
9681
41c445ff 9682 /* first time setup */
bc7d338f 9683 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9684 struct i40e_vsi *vsi = NULL;
9685 u16 uplink_seid;
9686
9687 /* Set up the PF VSI associated with the PF's main VSI
9688 * that is already in the HW switch
9689 */
9690 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9691 uplink_seid = pf->veb[pf->lan_veb]->seid;
9692 else
9693 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9694 if (pf->lan_vsi == I40E_NO_VSI)
9695 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9696 else if (reinit)
9697 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9698 if (!vsi) {
9699 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9700 i40e_fdir_teardown(pf);
9701 return -EAGAIN;
9702 }
41c445ff
JB		 9703 } else {
9704 /* force a reset of TC and queue layout configurations */
9705 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9706 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9707 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9708 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9709 }
9710 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9711
cbf61325
ASJ		 9712 i40e_fdir_sb_setup(pf);
9713
41c445ff
JB		 9714 /* Setup static PF queue filter control settings */
9715 ret = i40e_setup_pf_filter_control(pf);
9716 if (ret) {
9717 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9718 ret);
9719 /* Failure here should not stop continuing other steps */
9720 }
9721
9722 /* enable RSS in the HW, even for only one queue, as the stack can use
9723 * the hash
9724 */
9725 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9726 i40e_config_rss(pf);
9727
9728 /* fill in link information and enable LSE reporting */
21af70fb 9729 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9730 i40e_link_event(pf);
9731
d52c20b7 9732 /* Initialize user-specific link properties */
41c445ff
JB		 9733 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9734 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9735
beb0dff1
JK		 9736 i40e_ptp_init(pf);
9737
41c445ff
JB		 9738 return ret;
9739}
9740
41c445ff
JB		 9741/**
9742 * i40e_determine_queue_usage - Work out queue distribution
9743 * @pf: board private structure
9744 **/
9745static void i40e_determine_queue_usage(struct i40e_pf *pf)
9746{
41c445ff
JB		 9747 int queues_left;
9748
9749 pf->num_lan_qps = 0;
38e00438
VD		 9750#ifdef I40E_FCOE
9751 pf->num_fcoe_qps = 0;
9752#endif
41c445ff
JB		 9753
9754 /* Find the max queues to be put into basic use. We'll always be
9755 * using TC0, whether or not DCB is running, and TC0 will get the
9756 * big RSS set.
9757 */
9758 queues_left = pf->hw.func_caps.num_tx_qp;
9759
cbf61325 9760 if ((queues_left == 1) ||
9aa7e935 9761 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9762 /* one qp for PF, no queues for anything else */
9763 queues_left = 0;
9764 pf->rss_size = pf->num_lan_qps = 1;
9765
9766 /* make sure all the fancies are disabled */
60ea5f83 9767 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9768#ifdef I40E_FCOE
9769 I40E_FLAG_FCOE_ENABLED |
9770#endif
60ea5f83
JB		 9771 I40E_FLAG_FD_SB_ENABLED |
9772 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9773 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9774 I40E_FLAG_SRIOV_ENABLED |
9775 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9776 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9777 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9778 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9779 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9780 /* one qp for PF */
9781 pf->rss_size = pf->num_lan_qps = 1;
9782 queues_left -= pf->num_lan_qps;
9783
9784 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9785#ifdef I40E_FCOE
9786 I40E_FLAG_FCOE_ENABLED |
9787#endif
9aa7e935
FZ		 9788 I40E_FLAG_FD_SB_ENABLED |
9789 I40E_FLAG_FD_ATR_ENABLED |
9790 I40E_FLAG_DCB_ENABLED |
9791 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9792 } else {
cbf61325 9793 /* Not enough queues for all TCs */
4d9b6043 9794 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9795 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9796 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9797 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9798 }
9a3bd2f1
ASJ		 9799 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9800 num_online_cpus());
9801 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9802 pf->hw.func_caps.num_tx_qp);
9803
cbf61325
ASJ		 9804 queues_left -= pf->num_lan_qps;
9805 }
9806
38e00438
VD		 9807#ifdef I40E_FCOE
9808 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9809 if (I40E_DEFAULT_FCOE <= queues_left) {
9810 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9811 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9812 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9813 } else {
9814 pf->num_fcoe_qps = 0;
9815 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9816 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9817 }
9818
9819 queues_left -= pf->num_fcoe_qps;
9820 }
9821
9822#endif
cbf61325
ASJ		 9823 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9824 if (queues_left > 1) {
9825 queues_left -= 1; /* save 1 queue for FD */
9826 } else {
9827 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9828 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9829 }
41c445ff
JB		 9830 }
9831
9832 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9833 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9834 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9835 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9836 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9837 }
9838
9839 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9840 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9841 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9842 (queues_left / pf->num_vmdq_qps));
9843 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9844 }
9845
f8ff1464 9846 pf->queues_left = queues_left;
38e00438
VD		 9847#ifdef I40E_FCOE
9848 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9849#endif
41c445ff
JB		 9850}
9851
9852/**
9853 * i40e_setup_pf_filter_control - Setup PF static filter control
9854 * @pf: PF to be setup
9855 *
b40c82e6 9856 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 9857 * settings. If PE/FCoE are enabled then it will also set the per PF
9858 * based filter sizes required for them. It also enables Flow director,
9859 * ethertype and macvlan type filter settings for the pf.
9860 *
9861 * Returns 0 on success, negative on failure
9862 **/
9863static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9864{
9865 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9866
9867 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9868
9869 /* Flow Director is enabled */
60ea5f83 9870 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9871 settings->enable_fdir = true;
9872
9873 /* Ethtype and MACVLAN filters enabled for PF */
9874 settings->enable_ethtype = true;
9875 settings->enable_macvlan = true;
9876
9877 if (i40e_set_filter_control(&pf->hw, settings))
9878 return -ENOENT;
9879
9880 return 0;
9881}
9882
0c22b3dd
JB		 9883#define INFO_STRING_LEN 255
9884static void i40e_print_features(struct i40e_pf *pf)
9885{
9886 struct i40e_hw *hw = &pf->hw;
9887 char *buf, *string;
9888
9889 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9890 if (!string) {
9891 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9892 return;
9893 }
9894
9895 buf = string;
9896
9897 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9898#ifdef CONFIG_PCI_IOV
9899 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9900#endif
aba237d1
MW		 9901 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9902 pf->hw.func_caps.num_vsis,
9903 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9904 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9905
9906 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9907 buf += sprintf(buf, "RSS ");
0c22b3dd 9908 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9909 buf += sprintf(buf, "FD_ATR ");
9910 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9911 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9912 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9913 }
4d9b6043 9914 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9915 buf += sprintf(buf, "DCB ");
9916 if (pf->flags & I40E_FLAG_PTP)
9917 buf += sprintf(buf, "PTP ");
38e00438
VD		 9918#ifdef I40E_FCOE
9919 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9920 buf += sprintf(buf, "FCOE ");
9921#endif
0c22b3dd
JB		 9922
9923 BUG_ON(buf > (string + INFO_STRING_LEN));
9924 dev_info(&pf->pdev->dev, "%s\n", string);
9925 kfree(string);
9926}
9927
41c445ff
JB		 9928/**
9929 * i40e_probe - Device initialization routine
9930 * @pdev: PCI device information struct
9931 * @ent: entry in i40e_pci_tbl
9932 *
b40c82e6
JK		 9933 * i40e_probe initializes a PF identified by a pci_dev structure.
9934 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 9935 * and a hardware reset occur.
9936 *
9937 * Returns 0 on success, negative on failure
9938 **/
9939static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9940{
e827845c 9941 struct i40e_aq_get_phy_abilities_resp abilities;
e815665e 9942 unsigned long ioremap_len;
41c445ff
JB		 9943 struct i40e_pf *pf;
9944 struct i40e_hw *hw;
93cd765b 9945 static u16 pfs_found;
d4dfb81a 9946 u16 link_status;
41c445ff
JB		 9947 int err = 0;
9948 u32 len;
8a9eb7d3 9949 u32 i;
41c445ff
JB		 9950
9951 err = pci_enable_device_mem(pdev);
9952 if (err)
9953 return err;
9954
9955 /* set up for high or low dma */
6494294f 9956 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9957 if (err) {
e3e3bfdd
JS		 9958 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9959 if (err) {
9960 dev_err(&pdev->dev,
9961 "DMA configuration failed: 0x%x\n", err);
9962 goto err_dma;
9963 }
41c445ff
JB		 9964 }
9965
9966 /* set up pci connections */
9967 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9968 IORESOURCE_MEM), i40e_driver_name);
9969 if (err) {
9970 dev_info(&pdev->dev,
9971 "pci_request_selected_regions failed %d\n", err);
9972 goto err_pci_reg;
9973 }
9974
9975 pci_enable_pcie_error_reporting(pdev);
9976 pci_set_master(pdev);
9977
9978 /* Now that we have a PCI connection, we need to do the
9979 * low level device setup. This is primarily setting up
9980 * the Admin Queue structures and then querying for the
9981 * device's current profile information.
9982 */
9983 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9984 if (!pf) {
9985 err = -ENOMEM;
9986 goto err_pf_alloc;
9987 }
9988 pf->next_vsi = 0;
9989 pf->pdev = pdev;
9990 set_bit(__I40E_DOWN, &pf->state);
9991
9992 hw = &pf->hw;
9993 hw->back = pf;
232f4706 9994
e815665e 9995 ioremap_len = min_t(unsigned long, pci_resource_len(pdev, 0),
232f4706
AS		 9996 I40E_MAX_CSR_SPACE);
9997
9998 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), ioremap_len);
41c445ff
JB		 9999 if (!hw->hw_addr) {
10000 err = -EIO;
10001 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10002 (unsigned int)pci_resource_start(pdev, 0),
10003 (unsigned int)pci_resource_len(pdev, 0), err);
10004 goto err_ioremap;
10005 }
10006 hw->vendor_id = pdev->vendor;
10007 hw->device_id = pdev->device;
10008 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10009 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10010 hw->subsystem_device_id = pdev->subsystem_device;
10011 hw->bus.device = PCI_SLOT(pdev->devfn);
10012 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10013 pf->instance = pfs_found;
41c445ff 10014
5b5faa43
SN		 10015 if (debug != -1) {
10016 pf->msg_enable = pf->hw.debug_mask;
10017 pf->msg_enable = debug;
10018 }
10019
7134f9ce
JB		 10020 /* do a special CORER for clearing PXE mode once at init */
10021 if (hw->revision_id == 0 &&
10022 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10023 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10024 i40e_flush(hw);
10025 msleep(200);
10026 pf->corer_count++;
10027
10028 i40e_clear_pxe_mode(hw);
10029 }
10030
41c445ff 10031 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10032 i40e_clear_hw(hw);
41c445ff
JB		 10033 err = i40e_pf_reset(hw);
10034 if (err) {
10035 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10036 goto err_pf_reset;
10037 }
10038 pf->pfr_count++;
10039
10040 hw->aq.num_arq_entries = I40E_AQ_LEN;
10041 hw->aq.num_asq_entries = I40E_AQ_LEN;
10042 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10043 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10044 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10045
b294ac70 10046 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10047 "%s-%s:misc",
10048 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10049
10050 err = i40e_init_shared_code(hw);
10051 if (err) {
b2a75c58
ASJ		 10052 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10053 err);
41c445ff
JB		 10054 goto err_pf_reset;
10055 }
10056
d52c20b7
JB		 10057 /* set up a default setting for link flow control */
10058 pf->hw.fc.requested_mode = I40E_FC_NONE;
10059
41c445ff
JB		 10060 err = i40e_init_adminq(hw);
10061 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
10062 if (err) {
10063 dev_info(&pdev->dev,
7aa67613 10064 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 10065 goto err_pf_reset;
10066 }
10067
7aa67613
CS		 10068 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10069 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10070 dev_info(&pdev->dev,
7aa67613
CS		 10071 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10072 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10073 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10074 dev_info(&pdev->dev,
7aa67613 10075 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10076
4eb3f768
SN		 10077 i40e_verify_eeprom(pf);
10078
2c5fe33b
JB		 10079 /* Rev 0 hardware was never productized */
10080 if (hw->revision_id < 1)
10081 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10082
6ff4ef86 10083 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10084 err = i40e_get_capabilities(pf);
10085 if (err)
10086 goto err_adminq_setup;
10087
10088 err = i40e_sw_init(pf);
10089 if (err) {
10090 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10091 goto err_sw_init;
10092 }
10093
10094 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10095 hw->func_caps.num_rx_qp,
10096 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10097 if (err) {
10098 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10099 goto err_init_lan_hmc;
10100 }
10101
10102 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10103 if (err) {
10104 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10105 err = -ENOENT;
10106 goto err_configure_lan_hmc;
10107 }
10108
b686ece5
NP		 10109 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10110 * Ignore error return codes because if it was already disabled via
10111 * hardware settings this will fail
10112 */
10113 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10114 (pf->hw.aq.fw_maj_ver < 4)) {
10115 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10116 i40e_aq_stop_lldp(hw, true, NULL);
10117 }
10118
41c445ff 10119 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10120 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10121 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10122 err = -EIO;
10123 goto err_mac_addr;
10124 }
10125 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10126 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10127 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10128 if (is_valid_ether_addr(hw->mac.port_addr))
10129 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10130#ifdef I40E_FCOE
10131 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10132 if (err)
10133 dev_info(&pdev->dev,
10134 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10135 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10136 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10137 hw->mac.san_addr);
10138 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10139 }
10140 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10141#endif /* I40E_FCOE */
41c445ff
JB		 10142
10143 pci_set_drvdata(pdev, pf);
10144 pci_save_state(pdev);
4e3b35b0
NP		 10145#ifdef CONFIG_I40E_DCB
10146 err = i40e_init_pf_dcb(pf);
10147 if (err) {
aebfc816 10148 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10149 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10150 /* Continue without DCB enabled */
4e3b35b0
NP		 10151 }
10152#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10153
10154 /* set up periodic task facility */
10155 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10156 pf->service_timer_period = HZ;
10157
10158 INIT_WORK(&pf->service_task, i40e_service_task);
10159 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10160 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10161
8e2773ae
SN		 10162 /* WoL defaults to disabled */
10163 pf->wol_en = false;
10164 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10165
41c445ff
JB		 10166 /* set up the main switch operations */
10167 i40e_determine_queue_usage(pf);
c1147280
JB		 10168 err = i40e_init_interrupt_scheme(pf);
10169 if (err)
10170 goto err_switch_setup;
41c445ff 10171
505682cd
MW		 10172 /* The number of VSIs reported by the FW is the minimum guaranteed
10173 * to us; HW supports far more and we share the remaining pool with
10174 * the other PFs. We allocate space for more than the guarantee with
10175 * the understanding that we might not get them all later.
41c445ff 10176 */
505682cd
MW		 10177 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10178 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10179 else
10180 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10181
10182 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10183 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10184 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10185 if (!pf->vsi) {
10186 err = -ENOMEM;
41c445ff 10187 goto err_switch_setup;
ed87ac09 10188 }
41c445ff 10189
fa11cb3d
ASJ		 10190#ifdef CONFIG_PCI_IOV
10191 /* prep for VF support */
10192 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10193 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10194 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10195 if (pci_num_vf(pdev))
10196 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10197 }
10198#endif
bc7d338f 10199 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10200 if (err) {
10201 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10202 goto err_vsis;
10203 }
8a9eb7d3 10204 /* if FDIR VSI was set up, start it now */
505682cd 10205 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10206 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10207 i40e_vsi_open(pf->vsi[i]);
10208 break;
10209 }
10210 }
41c445ff 10211
7e2453fe
JB		 10212 /* driver is only interested in link up/down and module qualification
10213 * reports from firmware
10214 */
10215 err = i40e_aq_set_phy_int_mask(&pf->hw,
10216 I40E_AQ_EVENT_LINK_UPDOWN |
10217 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10218 if (err)
f1c7e72e
SN		 10219 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10220 i40e_stat_str(&pf->hw, err),
10221 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10222
025b4a54
ASJ		 10223 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10224 (pf->hw.aq.fw_maj_ver < 4)) {
10225 msleep(75);
10226 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10227 if (err)
f1c7e72e
SN		 10228 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10229 i40e_stat_str(&pf->hw, err),
10230 i40e_aq_str(&pf->hw,
10231 pf->hw.aq.asq_last_status));
cafa2ee6 10232 }
41c445ff
JB		 10233 /* The main driver is (mostly) up and happy. We need to set this state
10234 * before setting up the misc vector or we get a race and the vector
10235 * ends up disabled forever.
10236 */
10237 clear_bit(__I40E_DOWN, &pf->state);
10238
10239 /* In case of MSIX we are going to setup the misc vector right here
10240 * to handle admin queue events etc. In case of legacy and MSI
10241 * the misc functionality and queue processing is combined in
10242 * the same vector and that gets setup at open.
10243 */
10244 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10245 err = i40e_setup_misc_vector(pf);
10246 if (err) {
10247 dev_info(&pdev->dev,
10248 "setup of misc vector failed: %d\n", err);
10249 goto err_vsis;
10250 }
10251 }
10252
df805f62 10253#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10254 /* prep for VF support */
10255 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10256 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10257 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10258 u32 val;
10259
10260 /* disable link interrupts for VFs */
10261 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10262 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10263 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10264 i40e_flush(hw);
4aeec010
MW		 10265
10266 if (pci_num_vf(pdev)) {
10267 dev_info(&pdev->dev,
10268 "Active VFs found, allocating resources.\n");
10269 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10270 if (err)
10271 dev_info(&pdev->dev,
10272 "Error %d allocating resources for existing VFs\n",
10273 err);
10274 }
41c445ff 10275 }
df805f62 10276#endif /* CONFIG_PCI_IOV */
41c445ff 10277
93cd765b
ASJ		 10278 pfs_found++;
10279
41c445ff
JB		 10280 i40e_dbg_pf_init(pf);
10281
10282 /* tell the firmware that we're starting */
44033fac 10283 i40e_send_version(pf);
41c445ff
JB		 10284
10285 /* since everything's happy, start the service_task timer */
10286 mod_timer(&pf->service_timer,
10287 round_jiffies(jiffies + pf->service_timer_period));
10288
38e00438
VD		 10289#ifdef I40E_FCOE
10290 /* create FCoE interface */
10291 i40e_fcoe_vsi_setup(pf);
10292
10293#endif
d4dfb81a
CS		 10294 /* Get the negotiated link width and speed from PCI config space */
10295 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
10296
10297 i40e_set_pci_config_data(hw, link_status);
10298
69bfb110 10299 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 10300 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
10301 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
10302 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
10303 "Unknown"),
10304 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
10305 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
10306 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
10307 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
10308 "Unknown"));
10309
10310 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10311 hw->bus.speed < i40e_bus_speed_8000) {
10312 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10313 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10314 }
10315
e827845c
CS		 10316 /* get the requested speeds from the fw */
10317 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10318 if (err)
f1c7e72e
SN		 10319 dev_info(&pf->pdev->dev,
10320 "get phy capabilities failed, err %s aq_err %s, advertised speed settings may not be correct\n",
10321 i40e_stat_str(&pf->hw, err),
10322 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10323 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10324
0c22b3dd
JB		 10325 /* print a string summarizing features */
10326 i40e_print_features(pf);
10327
41c445ff
JB		 10328 return 0;
10329
10330 /* Unwind what we've done if something failed in the setup */
10331err_vsis:
10332 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10333 i40e_clear_interrupt_scheme(pf);
10334 kfree(pf->vsi);
04b03013
SN		 10335err_switch_setup:
10336 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10337 del_timer_sync(&pf->service_timer);
10338err_mac_addr:
10339err_configure_lan_hmc:
10340 (void)i40e_shutdown_lan_hmc(hw);
10341err_init_lan_hmc:
10342 kfree(pf->qp_pile);
41c445ff
JB		 10343err_sw_init:
10344err_adminq_setup:
10345 (void)i40e_shutdown_adminq(hw);
10346err_pf_reset:
10347 iounmap(hw->hw_addr);
10348err_ioremap:
10349 kfree(pf);
10350err_pf_alloc:
10351 pci_disable_pcie_error_reporting(pdev);
10352 pci_release_selected_regions(pdev,
10353 pci_select_bars(pdev, IORESOURCE_MEM));
10354err_pci_reg:
10355err_dma:
10356 pci_disable_device(pdev);
10357 return err;
10358}
10359
10360/**
10361 * i40e_remove - Device removal routine
10362 * @pdev: PCI device information struct
10363 *
10364 * i40e_remove is called by the PCI subsystem to alert the driver
10365 * that is should release a PCI device. This could be caused by a
10366 * Hot-Plug event, or because the driver is going to be removed from
10367 * memory.
10368 **/
10369static void i40e_remove(struct pci_dev *pdev)
10370{
10371 struct i40e_pf *pf = pci_get_drvdata(pdev);
10372 i40e_status ret_code;
41c445ff
JB		 10373 int i;
10374
10375 i40e_dbg_pf_exit(pf);
10376
beb0dff1
JK		 10377 i40e_ptp_stop(pf);
10378
41c445ff
JB		 10379 /* no more scheduling of any task */
10380 set_bit(__I40E_DOWN, &pf->state);
10381 del_timer_sync(&pf->service_timer);
10382 cancel_work_sync(&pf->service_task);
33c62b34 10383 i40e_fdir_teardown(pf);
41c445ff 10384
eb2d80bc
MW		 10385 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10386 i40e_free_vfs(pf);
10387 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10388 }
10389
41c445ff
JB		 10390 i40e_fdir_teardown(pf);
10391
10392 /* If there is a switch structure or any orphans, remove them.
10393 * This will leave only the PF's VSI remaining.
10394 */
10395 for (i = 0; i < I40E_MAX_VEB; i++) {
10396 if (!pf->veb[i])
10397 continue;
10398
10399 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10400 pf->veb[i]->uplink_seid == 0)
10401 i40e_switch_branch_release(pf->veb[i]);
10402 }
10403
10404 /* Now we can shutdown the PF's VSI, just before we kill
10405 * adminq and hmc.
10406 */
10407 if (pf->vsi[pf->lan_vsi])
10408 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10409
41c445ff 10410 /* shutdown and destroy the HMC */
60442dea
SN		 10411 if (pf->hw.hmc.hmc_obj) {
10412 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10413 if (ret_code)
10414 dev_warn(&pdev->dev,
10415 "Failed to destroy the HMC resources: %d\n",
10416 ret_code);
10417 }
41c445ff
JB		 10418
10419 /* shutdown the adminq */
41c445ff
JB		 10420 ret_code = i40e_shutdown_adminq(&pf->hw);
10421 if (ret_code)
10422 dev_warn(&pdev->dev,
10423 "Failed to destroy the Admin Queue resources: %d\n",
10424 ret_code);
10425
10426 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10427 i40e_clear_interrupt_scheme(pf);
505682cd 10428 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10429 if (pf->vsi[i]) {
10430 i40e_vsi_clear_rings(pf->vsi[i]);
10431 i40e_vsi_clear(pf->vsi[i]);
10432 pf->vsi[i] = NULL;
10433 }
10434 }
10435
10436 for (i = 0; i < I40E_MAX_VEB; i++) {
10437 kfree(pf->veb[i]);
10438 pf->veb[i] = NULL;
10439 }
10440
10441 kfree(pf->qp_pile);
41c445ff
JB		 10442 kfree(pf->vsi);
10443
41c445ff
JB		 10444 iounmap(pf->hw.hw_addr);
10445 kfree(pf);
10446 pci_release_selected_regions(pdev,
10447 pci_select_bars(pdev, IORESOURCE_MEM));
10448
10449 pci_disable_pcie_error_reporting(pdev);
10450 pci_disable_device(pdev);
10451}
10452
10453/**
10454 * i40e_pci_error_detected - warning that something funky happened in PCI land
10455 * @pdev: PCI device information struct
10456 *
10457 * Called to warn that something happened and the error handling steps
10458 * are in progress. Allows the driver to quiesce things, be ready for
10459 * remediation.
10460 **/
10461static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10462 enum pci_channel_state error)
10463{
10464 struct i40e_pf *pf = pci_get_drvdata(pdev);
10465
10466 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10467
10468 /* shutdown all operations */
9007bccd
SN		 10469 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10470 rtnl_lock();
10471 i40e_prep_for_reset(pf);
10472 rtnl_unlock();
10473 }
41c445ff
JB		 10474
10475 /* Request a slot reset */
10476 return PCI_ERS_RESULT_NEED_RESET;
10477}
10478
10479/**
10480 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10481 * @pdev: PCI device information struct
10482 *
10483 * Called to find if the driver can work with the device now that
10484 * the pci slot has been reset. If a basic connection seems good
10485 * (registers are readable and have sane content) then return a
10486 * happy little PCI_ERS_RESULT_xxx.
10487 **/
10488static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10489{
10490 struct i40e_pf *pf = pci_get_drvdata(pdev);
10491 pci_ers_result_t result;
10492 int err;
10493 u32 reg;
10494
10495 dev_info(&pdev->dev, "%s\n", __func__);
10496 if (pci_enable_device_mem(pdev)) {
10497 dev_info(&pdev->dev,
10498 "Cannot re-enable PCI device after reset.\n");
10499 result = PCI_ERS_RESULT_DISCONNECT;
10500 } else {
10501 pci_set_master(pdev);
10502 pci_restore_state(pdev);
10503 pci_save_state(pdev);
10504 pci_wake_from_d3(pdev, false);
10505
10506 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10507 if (reg == 0)
10508 result = PCI_ERS_RESULT_RECOVERED;
10509 else
10510 result = PCI_ERS_RESULT_DISCONNECT;
10511 }
10512
10513 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10514 if (err) {
10515 dev_info(&pdev->dev,
10516 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10517 err);
10518 /* non-fatal, continue */
10519 }
10520
10521 return result;
10522}
10523
10524/**
10525 * i40e_pci_error_resume - restart operations after PCI error recovery
10526 * @pdev: PCI device information struct
10527 *
10528 * Called to allow the driver to bring things back up after PCI error
10529 * and/or reset recovery has finished.
10530 **/
10531static void i40e_pci_error_resume(struct pci_dev *pdev)
10532{
10533 struct i40e_pf *pf = pci_get_drvdata(pdev);
10534
10535 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10536 if (test_bit(__I40E_SUSPENDED, &pf->state))
10537 return;
10538
10539 rtnl_lock();
41c445ff 10540 i40e_handle_reset_warning(pf);
4c4935a9 10541 rtnl_unlock();
9007bccd
SN		 10542}
10543
10544/**
10545 * i40e_shutdown - PCI callback for shutting down
10546 * @pdev: PCI device information struct
10547 **/
10548static void i40e_shutdown(struct pci_dev *pdev)
10549{
10550 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10551 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10552
10553 set_bit(__I40E_SUSPENDED, &pf->state);
10554 set_bit(__I40E_DOWN, &pf->state);
10555 rtnl_lock();
10556 i40e_prep_for_reset(pf);
10557 rtnl_unlock();
10558
8e2773ae
SN		 10559 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10560 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10561
02b42498
CS		 10562 del_timer_sync(&pf->service_timer);
10563 cancel_work_sync(&pf->service_task);
10564 i40e_fdir_teardown(pf);
10565
10566 rtnl_lock();
10567 i40e_prep_for_reset(pf);
10568 rtnl_unlock();
10569
10570 wr32(hw, I40E_PFPM_APM,
10571 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10572 wr32(hw, I40E_PFPM_WUFC,
10573 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10574
e147758d
SN		 10575 i40e_clear_interrupt_scheme(pf);
10576
9007bccd 10577 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10578 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10579 pci_set_power_state(pdev, PCI_D3hot);
10580 }
10581}
10582
10583#ifdef CONFIG_PM
10584/**
10585 * i40e_suspend - PCI callback for moving to D3
10586 * @pdev: PCI device information struct
10587 **/
10588static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10589{
10590 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10591 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10592
10593 set_bit(__I40E_SUSPENDED, &pf->state);
10594 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 10595
9007bccd
SN		 10596 rtnl_lock();
10597 i40e_prep_for_reset(pf);
10598 rtnl_unlock();
10599
8e2773ae
SN		 10600 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10601 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10602
10603 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10604 pci_set_power_state(pdev, PCI_D3hot);
10605
10606 return 0;
41c445ff
JB		 10607}
10608
9007bccd
SN		 10609/**
10610 * i40e_resume - PCI callback for waking up from D3
10611 * @pdev: PCI device information struct
10612 **/
10613static int i40e_resume(struct pci_dev *pdev)
10614{
10615 struct i40e_pf *pf = pci_get_drvdata(pdev);
10616 u32 err;
10617
10618 pci_set_power_state(pdev, PCI_D0);
10619 pci_restore_state(pdev);
10620 /* pci_restore_state() clears dev->state_saves, so
10621 * call pci_save_state() again to restore it.
10622 */
10623 pci_save_state(pdev);
10624
10625 err = pci_enable_device_mem(pdev);
10626 if (err) {
10627 dev_err(&pdev->dev,
10628 "%s: Cannot enable PCI device from suspend\n",
10629 __func__);
10630 return err;
10631 }
10632 pci_set_master(pdev);
10633
10634 /* no wakeup events while running */
10635 pci_wake_from_d3(pdev, false);
10636
10637 /* handling the reset will rebuild the device state */
10638 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10639 clear_bit(__I40E_DOWN, &pf->state);
10640 rtnl_lock();
10641 i40e_reset_and_rebuild(pf, false);
10642 rtnl_unlock();
10643 }
10644
10645 return 0;
10646}
10647
10648#endif
41c445ff
JB		 10649static const struct pci_error_handlers i40e_err_handler = {
10650 .error_detected = i40e_pci_error_detected,
10651 .slot_reset = i40e_pci_error_slot_reset,
10652 .resume = i40e_pci_error_resume,
10653};
10654
10655static struct pci_driver i40e_driver = {
10656 .name = i40e_driver_name,
10657 .id_table = i40e_pci_tbl,
10658 .probe = i40e_probe,
10659 .remove = i40e_remove,
9007bccd
SN		 10660#ifdef CONFIG_PM
10661 .suspend = i40e_suspend,
10662 .resume = i40e_resume,
10663#endif
10664 .shutdown = i40e_shutdown,
41c445ff
JB		 10665 .err_handler = &i40e_err_handler,
10666 .sriov_configure = i40e_pci_sriov_configure,
10667};
10668
10669/**
10670 * i40e_init_module - Driver registration routine
10671 *
10672 * i40e_init_module is the first routine called when the driver is
10673 * loaded. All it does is register with the PCI subsystem.
10674 **/
10675static int __init i40e_init_module(void)
10676{
10677 pr_info("%s: %s - version %s\n", i40e_driver_name,
10678 i40e_driver_string, i40e_driver_version_str);
10679 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10680
41c445ff
JB		 10681 i40e_dbg_init();
10682 return pci_register_driver(&i40e_driver);
10683}
10684module_init(i40e_init_module);
10685
10686/**
10687 * i40e_exit_module - Driver exit cleanup routine
10688 *
10689 * i40e_exit_module is called just before the driver is removed
10690 * from memory.
10691 **/
10692static void __exit i40e_exit_module(void)
10693{
10694 pci_unregister_driver(&i40e_driver);
10695 i40e_dbg_exit();
10696}
10697module_exit(i40e_exit_module);
Linux kernel - Deliverables
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