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i40e: fix compile warning on checksum_local
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
a1c9a9d9
JK		 29#ifdef CONFIG_I40E_VXLAN
30#include <net/vxlan.h>
31#endif
41c445ff
JB		 32
33const char i40e_driver_name[] = "i40e";
34static const char i40e_driver_string[] =
35 "Intel(R) Ethernet Connection XL710 Network Driver";
36
37#define DRV_KERN "-k"
38
39#define DRV_VERSION_MAJOR 0
40#define DRV_VERSION_MINOR 3
962dd666 41#define DRV_VERSION_BUILD 30
41c445ff
JB		 42#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
43 __stringify(DRV_VERSION_MINOR) "." \
44 __stringify(DRV_VERSION_BUILD) DRV_KERN
45const char i40e_driver_version_str[] = DRV_VERSION;
46static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
47
48/* a bit of forward declarations */
49static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
50static void i40e_handle_reset_warning(struct i40e_pf *pf);
51static int i40e_add_vsi(struct i40e_vsi *vsi);
52static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 53static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 54static int i40e_setup_misc_vector(struct i40e_pf *pf);
55static void i40e_determine_queue_usage(struct i40e_pf *pf);
56static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
57
58/* i40e_pci_tbl - PCI Device ID Table
59 *
60 * Last entry must be all 0s
61 *
62 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
63 * Class, Class Mask, private data (not used) }
64 */
65static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
66 {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
67 {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
68 {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
69 {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
70 {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
71 {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
72 {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
73 {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
74 {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
75 {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
76 /* required last entry */
77 {0, }
78};
79MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
80
81#define I40E_MAX_VF_COUNT 128
82static int debug = -1;
83module_param(debug, int, 0);
84MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
85
86MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
87MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
88MODULE_LICENSE("GPL");
89MODULE_VERSION(DRV_VERSION);
90
91/**
92 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
93 * @hw: pointer to the HW structure
94 * @mem: ptr to mem struct to fill out
95 * @size: size of memory requested
96 * @alignment: what to align the allocation to
97 **/
98int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
99 u64 size, u32 alignment)
100{
101 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
102
103 mem->size = ALIGN(size, alignment);
104 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
105 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 106 if (!mem->va)
107 return -ENOMEM;
41c445ff 108
93bc73b8 109 return 0;
41c445ff
JB		 110}
111
112/**
113 * i40e_free_dma_mem_d - OS specific memory free for shared code
114 * @hw: pointer to the HW structure
115 * @mem: ptr to mem struct to free
116 **/
117int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
118{
119 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
120
121 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
122 mem->va = NULL;
123 mem->pa = 0;
124 mem->size = 0;
125
126 return 0;
127}
128
129/**
130 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
131 * @hw: pointer to the HW structure
132 * @mem: ptr to mem struct to fill out
133 * @size: size of memory requested
134 **/
135int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
136 u32 size)
137{
138 mem->size = size;
139 mem->va = kzalloc(size, GFP_KERNEL);
140
93bc73b8
JB		 141 if (!mem->va)
142 return -ENOMEM;
41c445ff 143
93bc73b8 144 return 0;
41c445ff
JB		 145}
146
147/**
148 * i40e_free_virt_mem_d - OS specific memory free for shared code
149 * @hw: pointer to the HW structure
150 * @mem: ptr to mem struct to free
151 **/
152int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
153{
154 /* it's ok to kfree a NULL pointer */
155 kfree(mem->va);
156 mem->va = NULL;
157 mem->size = 0;
158
159 return 0;
160}
161
162/**
163 * i40e_get_lump - find a lump of free generic resource
164 * @pf: board private structure
165 * @pile: the pile of resource to search
166 * @needed: the number of items needed
167 * @id: an owner id to stick on the items assigned
168 *
169 * Returns the base item index of the lump, or negative for error
170 *
171 * The search_hint trick and lack of advanced fit-finding only work
172 * because we're highly likely to have all the same size lump requests.
173 * Linear search time and any fragmentation should be minimal.
174 **/
175static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
176 u16 needed, u16 id)
177{
178 int ret = -ENOMEM;
ddf434ac 179 int i, j;
41c445ff
JB		 180
181 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
182 dev_info(&pf->pdev->dev,
183 "param err: pile=%p needed=%d id=0x%04x\n",
184 pile, needed, id);
185 return -EINVAL;
186 }
187
188 /* start the linear search with an imperfect hint */
189 i = pile->search_hint;
ddf434ac 190 while (i < pile->num_entries) {
41c445ff
JB		 191 /* skip already allocated entries */
192 if (pile->list[i] & I40E_PILE_VALID_BIT) {
193 i++;
194 continue;
195 }
196
197 /* do we have enough in this lump? */
198 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
199 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
200 break;
201 }
202
203 if (j == needed) {
204 /* there was enough, so assign it to the requestor */
205 for (j = 0; j < needed; j++)
206 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
207 ret = i;
208 pile->search_hint = i + j;
ddf434ac 209 break;
41c445ff
JB		 210 } else {
211 /* not enough, so skip over it and continue looking */
212 i += j;
213 }
214 }
215
216 return ret;
217}
218
219/**
220 * i40e_put_lump - return a lump of generic resource
221 * @pile: the pile of resource to search
222 * @index: the base item index
223 * @id: the owner id of the items assigned
224 *
225 * Returns the count of items in the lump
226 **/
227static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
228{
229 int valid_id = (id | I40E_PILE_VALID_BIT);
230 int count = 0;
231 int i;
232
233 if (!pile || index >= pile->num_entries)
234 return -EINVAL;
235
236 for (i = index;
237 i < pile->num_entries && pile->list[i] == valid_id;
238 i++) {
239 pile->list[i] = 0;
240 count++;
241 }
242
243 if (count && index < pile->search_hint)
244 pile->search_hint = index;
245
246 return count;
247}
248
249/**
250 * i40e_service_event_schedule - Schedule the service task to wake up
251 * @pf: board private structure
252 *
253 * If not already scheduled, this puts the task into the work queue
254 **/
255static void i40e_service_event_schedule(struct i40e_pf *pf)
256{
257 if (!test_bit(__I40E_DOWN, &pf->state) &&
258 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
259 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
260 schedule_work(&pf->service_task);
261}
262
263/**
264 * i40e_tx_timeout - Respond to a Tx Hang
265 * @netdev: network interface device structure
266 *
267 * If any port has noticed a Tx timeout, it is likely that the whole
268 * device is munged, not just the one netdev port, so go for the full
269 * reset.
270 **/
271static void i40e_tx_timeout(struct net_device *netdev)
272{
273 struct i40e_netdev_priv *np = netdev_priv(netdev);
274 struct i40e_vsi *vsi = np->vsi;
275 struct i40e_pf *pf = vsi->back;
276
277 pf->tx_timeout_count++;
278
279 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
280 pf->tx_timeout_recovery_level = 0;
281 pf->tx_timeout_last_recovery = jiffies;
282 netdev_info(netdev, "tx_timeout recovery level %d\n",
283 pf->tx_timeout_recovery_level);
284
285 switch (pf->tx_timeout_recovery_level) {
286 case 0:
287 /* disable and re-enable queues for the VSI */
288 if (in_interrupt()) {
289 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
290 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
291 } else {
292 i40e_vsi_reinit_locked(vsi);
293 }
294 break;
295 case 1:
296 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
297 break;
298 case 2:
299 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
300 break;
301 case 3:
302 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
303 break;
304 default:
305 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
306 i40e_down(vsi);
307 break;
308 }
309 i40e_service_event_schedule(pf);
310 pf->tx_timeout_recovery_level++;
311}
312
313/**
314 * i40e_release_rx_desc - Store the new tail and head values
315 * @rx_ring: ring to bump
316 * @val: new head index
317 **/
318static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
319{
320 rx_ring->next_to_use = val;
321
322 /* Force memory writes to complete before letting h/w
323 * know there are new descriptors to fetch. (Only
324 * applicable for weak-ordered memory model archs,
325 * such as IA-64).
326 */
327 wmb();
328 writel(val, rx_ring->tail);
329}
330
331/**
332 * i40e_get_vsi_stats_struct - Get System Network Statistics
333 * @vsi: the VSI we care about
334 *
335 * Returns the address of the device statistics structure.
336 * The statistics are actually updated from the service task.
337 **/
338struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
339{
340 return &vsi->net_stats;
341}
342
343/**
344 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
345 * @netdev: network interface device structure
346 *
347 * Returns the address of the device statistics structure.
348 * The statistics are actually updated from the service task.
349 **/
350static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
351 struct net_device *netdev,
980e9b11 352 struct rtnl_link_stats64 *stats)
41c445ff
JB		 353{
354 struct i40e_netdev_priv *np = netdev_priv(netdev);
355 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 356 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
357 int i;
358
bc7d338f
ASJ		 359 if (test_bit(__I40E_DOWN, &vsi->state))
360 return stats;
361
3c325ced
JB		 362 if (!vsi->tx_rings)
363 return stats;
364
980e9b11
AD		 365 rcu_read_lock();
366 for (i = 0; i < vsi->num_queue_pairs; i++) {
367 struct i40e_ring *tx_ring, *rx_ring;
368 u64 bytes, packets;
369 unsigned int start;
370
371 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
372 if (!tx_ring)
373 continue;
374
375 do {
376 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
377 packets = tx_ring->stats.packets;
378 bytes = tx_ring->stats.bytes;
379 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
380
381 stats->tx_packets += packets;
382 stats->tx_bytes += bytes;
383 rx_ring = &tx_ring[1];
384
385 do {
386 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
387 packets = rx_ring->stats.packets;
388 bytes = rx_ring->stats.bytes;
389 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 390
980e9b11
AD		 391 stats->rx_packets += packets;
392 stats->rx_bytes += bytes;
393 }
394 rcu_read_unlock();
395
396 /* following stats updated by ixgbe_watchdog_task() */
397 stats->multicast = vsi_stats->multicast;
398 stats->tx_errors = vsi_stats->tx_errors;
399 stats->tx_dropped = vsi_stats->tx_dropped;
400 stats->rx_errors = vsi_stats->rx_errors;
401 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
402 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 403
980e9b11 404 return stats;
41c445ff
JB		 405}
406
407/**
408 * i40e_vsi_reset_stats - Resets all stats of the given vsi
409 * @vsi: the VSI to have its stats reset
410 **/
411void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
412{
413 struct rtnl_link_stats64 *ns;
414 int i;
415
416 if (!vsi)
417 return;
418
419 ns = i40e_get_vsi_stats_struct(vsi);
420 memset(ns, 0, sizeof(*ns));
421 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
422 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
423 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 424 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 425 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 426 memset(&vsi->rx_rings[i]->stats, 0 ,
427 sizeof(vsi->rx_rings[i]->stats));
428 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
429 sizeof(vsi->rx_rings[i]->rx_stats));
430 memset(&vsi->tx_rings[i]->stats, 0 ,
431 sizeof(vsi->tx_rings[i]->stats));
432 memset(&vsi->tx_rings[i]->tx_stats, 0,
433 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 434 }
8e9dca53 435 }
41c445ff
JB		 436 vsi->stat_offsets_loaded = false;
437}
438
439/**
440 * i40e_pf_reset_stats - Reset all of the stats for the given pf
441 * @pf: the PF to be reset
442 **/
443void i40e_pf_reset_stats(struct i40e_pf *pf)
444{
445 memset(&pf->stats, 0, sizeof(pf->stats));
446 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
447 pf->stat_offsets_loaded = false;
448}
449
450/**
451 * i40e_stat_update48 - read and update a 48 bit stat from the chip
452 * @hw: ptr to the hardware info
453 * @hireg: the high 32 bit reg to read
454 * @loreg: the low 32 bit reg to read
455 * @offset_loaded: has the initial offset been loaded yet
456 * @offset: ptr to current offset value
457 * @stat: ptr to the stat
458 *
459 * Since the device stats are not reset at PFReset, they likely will not
460 * be zeroed when the driver starts. We'll save the first values read
461 * and use them as offsets to be subtracted from the raw values in order
462 * to report stats that count from zero. In the process, we also manage
463 * the potential roll-over.
464 **/
465static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
466 bool offset_loaded, u64 *offset, u64 *stat)
467{
468 u64 new_data;
469
470 if (hw->device_id == I40E_QEMU_DEVICE_ID) {
471 new_data = rd32(hw, loreg);
472 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
473 } else {
474 new_data = rd64(hw, loreg);
475 }
476 if (!offset_loaded)
477 *offset = new_data;
478 if (likely(new_data >= *offset))
479 *stat = new_data - *offset;
480 else
481 *stat = (new_data + ((u64)1 << 48)) - *offset;
482 *stat &= 0xFFFFFFFFFFFFULL;
483}
484
485/**
486 * i40e_stat_update32 - read and update a 32 bit stat from the chip
487 * @hw: ptr to the hardware info
488 * @reg: the hw reg to read
489 * @offset_loaded: has the initial offset been loaded yet
490 * @offset: ptr to current offset value
491 * @stat: ptr to the stat
492 **/
493static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
494 bool offset_loaded, u64 *offset, u64 *stat)
495{
496 u32 new_data;
497
498 new_data = rd32(hw, reg);
499 if (!offset_loaded)
500 *offset = new_data;
501 if (likely(new_data >= *offset))
502 *stat = (u32)(new_data - *offset);
503 else
504 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
505}
506
507/**
508 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
509 * @vsi: the VSI to be updated
510 **/
511void i40e_update_eth_stats(struct i40e_vsi *vsi)
512{
513 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
514 struct i40e_pf *pf = vsi->back;
515 struct i40e_hw *hw = &pf->hw;
516 struct i40e_eth_stats *oes;
517 struct i40e_eth_stats *es; /* device's eth stats */
518
519 es = &vsi->eth_stats;
520 oes = &vsi->eth_stats_offsets;
521
522 /* Gather up the stats that the hw collects */
523 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
524 vsi->stat_offsets_loaded,
525 &oes->tx_errors, &es->tx_errors);
526 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
527 vsi->stat_offsets_loaded,
528 &oes->rx_discards, &es->rx_discards);
529
530 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
531 I40E_GLV_GORCL(stat_idx),
532 vsi->stat_offsets_loaded,
533 &oes->rx_bytes, &es->rx_bytes);
534 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
535 I40E_GLV_UPRCL(stat_idx),
536 vsi->stat_offsets_loaded,
537 &oes->rx_unicast, &es->rx_unicast);
538 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
539 I40E_GLV_MPRCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_multicast, &es->rx_multicast);
542 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
543 I40E_GLV_BPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_broadcast, &es->rx_broadcast);
546
547 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
548 I40E_GLV_GOTCL(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_bytes, &es->tx_bytes);
551 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
552 I40E_GLV_UPTCL(stat_idx),
553 vsi->stat_offsets_loaded,
554 &oes->tx_unicast, &es->tx_unicast);
555 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
556 I40E_GLV_MPTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_multicast, &es->tx_multicast);
559 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
560 I40E_GLV_BPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_broadcast, &es->tx_broadcast);
563 vsi->stat_offsets_loaded = true;
564}
565
566/**
567 * i40e_update_veb_stats - Update Switch component statistics
568 * @veb: the VEB being updated
569 **/
570static void i40e_update_veb_stats(struct i40e_veb *veb)
571{
572 struct i40e_pf *pf = veb->pf;
573 struct i40e_hw *hw = &pf->hw;
574 struct i40e_eth_stats *oes;
575 struct i40e_eth_stats *es; /* device's eth stats */
576 int idx = 0;
577
578 idx = veb->stats_idx;
579 es = &veb->stats;
580 oes = &veb->stats_offsets;
581
582 /* Gather up the stats that the hw collects */
583 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
584 veb->stat_offsets_loaded,
585 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 586 if (hw->revision_id > 0)
587 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
588 veb->stat_offsets_loaded,
589 &oes->rx_unknown_protocol,
590 &es->rx_unknown_protocol);
41c445ff
JB		 591 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
592 veb->stat_offsets_loaded,
593 &oes->rx_bytes, &es->rx_bytes);
594 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
595 veb->stat_offsets_loaded,
596 &oes->rx_unicast, &es->rx_unicast);
597 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
598 veb->stat_offsets_loaded,
599 &oes->rx_multicast, &es->rx_multicast);
600 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
601 veb->stat_offsets_loaded,
602 &oes->rx_broadcast, &es->rx_broadcast);
603
604 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
605 veb->stat_offsets_loaded,
606 &oes->tx_bytes, &es->tx_bytes);
607 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
608 veb->stat_offsets_loaded,
609 &oes->tx_unicast, &es->tx_unicast);
610 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
611 veb->stat_offsets_loaded,
612 &oes->tx_multicast, &es->tx_multicast);
613 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
614 veb->stat_offsets_loaded,
615 &oes->tx_broadcast, &es->tx_broadcast);
616 veb->stat_offsets_loaded = true;
617}
618
619/**
620 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
621 * @pf: the corresponding PF
622 *
623 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
624 **/
625static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
626{
627 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
628 struct i40e_hw_port_stats *nsd = &pf->stats;
629 struct i40e_hw *hw = &pf->hw;
630 u64 xoff = 0;
631 u16 i, v;
632
633 if ((hw->fc.current_mode != I40E_FC_FULL) &&
634 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
635 return;
636
637 xoff = nsd->link_xoff_rx;
638 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
639 pf->stat_offsets_loaded,
640 &osd->link_xoff_rx, &nsd->link_xoff_rx);
641
642 /* No new LFC xoff rx */
643 if (!(nsd->link_xoff_rx - xoff))
644 return;
645
646 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
647 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
648 struct i40e_vsi *vsi = pf->vsi[v];
649
650 if (!vsi)
651 continue;
652
653 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 654 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 655 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
656 }
657 }
658}
659
660/**
661 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
662 * @pf: the corresponding PF
663 *
664 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
665 **/
666static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
667{
668 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
669 struct i40e_hw_port_stats *nsd = &pf->stats;
670 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
671 struct i40e_dcbx_config *dcb_cfg;
672 struct i40e_hw *hw = &pf->hw;
673 u16 i, v;
674 u8 tc;
675
676 dcb_cfg = &hw->local_dcbx_config;
677
678 /* See if DCB enabled with PFC TC */
679 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
680 !(dcb_cfg->pfc.pfcenable)) {
681 i40e_update_link_xoff_rx(pf);
682 return;
683 }
684
685 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
686 u64 prio_xoff = nsd->priority_xoff_rx[i];
687 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
688 pf->stat_offsets_loaded,
689 &osd->priority_xoff_rx[i],
690 &nsd->priority_xoff_rx[i]);
691
692 /* No new PFC xoff rx */
693 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
694 continue;
695 /* Get the TC for given priority */
696 tc = dcb_cfg->etscfg.prioritytable[i];
697 xoff[tc] = true;
698 }
699
700 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
701 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
702 struct i40e_vsi *vsi = pf->vsi[v];
703
704 if (!vsi)
705 continue;
706
707 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 708 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 709
710 tc = ring->dcb_tc;
711 if (xoff[tc])
712 clear_bit(__I40E_HANG_CHECK_ARMED,
713 &ring->state);
714 }
715 }
716}
717
718/**
719 * i40e_update_stats - Update the board statistics counters.
720 * @vsi: the VSI to be updated
721 *
722 * There are a few instances where we store the same stat in a
723 * couple of different structs. This is partly because we have
724 * the netdev stats that need to be filled out, which is slightly
725 * different from the "eth_stats" defined by the chip and used in
726 * VF communications. We sort it all out here in a central place.
727 **/
728void i40e_update_stats(struct i40e_vsi *vsi)
729{
730 struct i40e_pf *pf = vsi->back;
731 struct i40e_hw *hw = &pf->hw;
732 struct rtnl_link_stats64 *ons;
733 struct rtnl_link_stats64 *ns; /* netdev stats */
734 struct i40e_eth_stats *oes;
735 struct i40e_eth_stats *es; /* device's eth stats */
736 u32 tx_restart, tx_busy;
737 u32 rx_page, rx_buf;
738 u64 rx_p, rx_b;
739 u64 tx_p, tx_b;
740 int i;
741 u16 q;
742
743 if (test_bit(__I40E_DOWN, &vsi->state) ||
744 test_bit(__I40E_CONFIG_BUSY, &pf->state))
745 return;
746
747 ns = i40e_get_vsi_stats_struct(vsi);
748 ons = &vsi->net_stats_offsets;
749 es = &vsi->eth_stats;
750 oes = &vsi->eth_stats_offsets;
751
752 /* Gather up the netdev and vsi stats that the driver collects
753 * on the fly during packet processing
754 */
755 rx_b = rx_p = 0;
756 tx_b = tx_p = 0;
757 tx_restart = tx_busy = 0;
758 rx_page = 0;
759 rx_buf = 0;
980e9b11 760 rcu_read_lock();
41c445ff
JB		 761 for (q = 0; q < vsi->num_queue_pairs; q++) {
762 struct i40e_ring *p;
980e9b11
AD		 763 u64 bytes, packets;
764 unsigned int start;
765
766 /* locate Tx ring */
767 p = ACCESS_ONCE(vsi->tx_rings[q]);
768
769 do {
770 start = u64_stats_fetch_begin_bh(&p->syncp);
771 packets = p->stats.packets;
772 bytes = p->stats.bytes;
773 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
774 tx_b += bytes;
775 tx_p += packets;
776 tx_restart += p->tx_stats.restart_queue;
777 tx_busy += p->tx_stats.tx_busy;
41c445ff 778
980e9b11
AD		 779 /* Rx queue is part of the same block as Tx queue */
780 p = &p[1];
781 do {
782 start = u64_stats_fetch_begin_bh(&p->syncp);
783 packets = p->stats.packets;
784 bytes = p->stats.bytes;
785 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
786 rx_b += bytes;
787 rx_p += packets;
420136cc
MW		 788 rx_buf += p->rx_stats.alloc_buff_failed;
789 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 790 }
980e9b11 791 rcu_read_unlock();
41c445ff
JB		 792 vsi->tx_restart = tx_restart;
793 vsi->tx_busy = tx_busy;
794 vsi->rx_page_failed = rx_page;
795 vsi->rx_buf_failed = rx_buf;
796
797 ns->rx_packets = rx_p;
798 ns->rx_bytes = rx_b;
799 ns->tx_packets = tx_p;
800 ns->tx_bytes = tx_b;
801
802 i40e_update_eth_stats(vsi);
803 /* update netdev stats from eth stats */
804 ons->rx_errors = oes->rx_errors;
805 ns->rx_errors = es->rx_errors;
806 ons->tx_errors = oes->tx_errors;
807 ns->tx_errors = es->tx_errors;
808 ons->multicast = oes->rx_multicast;
809 ns->multicast = es->rx_multicast;
810 ons->tx_dropped = oes->tx_discards;
811 ns->tx_dropped = es->tx_discards;
812
813 /* Get the port data only if this is the main PF VSI */
814 if (vsi == pf->vsi[pf->lan_vsi]) {
815 struct i40e_hw_port_stats *nsd = &pf->stats;
816 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
817
818 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
819 I40E_GLPRT_GORCL(hw->port),
820 pf->stat_offsets_loaded,
821 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
822 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
823 I40E_GLPRT_GOTCL(hw->port),
824 pf->stat_offsets_loaded,
825 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
826 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
827 pf->stat_offsets_loaded,
828 &osd->eth.rx_discards,
829 &nsd->eth.rx_discards);
830 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
831 pf->stat_offsets_loaded,
832 &osd->eth.tx_discards,
833 &nsd->eth.tx_discards);
834 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
835 I40E_GLPRT_MPRCL(hw->port),
836 pf->stat_offsets_loaded,
837 &osd->eth.rx_multicast,
838 &nsd->eth.rx_multicast);
839
840 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->tx_dropped_link_down,
843 &nsd->tx_dropped_link_down);
844
845 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
846 pf->stat_offsets_loaded,
847 &osd->crc_errors, &nsd->crc_errors);
848 ns->rx_crc_errors = nsd->crc_errors;
849
850 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
851 pf->stat_offsets_loaded,
852 &osd->illegal_bytes, &nsd->illegal_bytes);
853 ns->rx_errors = nsd->crc_errors
854 + nsd->illegal_bytes;
855
856 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
857 pf->stat_offsets_loaded,
858 &osd->mac_local_faults,
859 &nsd->mac_local_faults);
860 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
861 pf->stat_offsets_loaded,
862 &osd->mac_remote_faults,
863 &nsd->mac_remote_faults);
864
865 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
866 pf->stat_offsets_loaded,
867 &osd->rx_length_errors,
868 &nsd->rx_length_errors);
869 ns->rx_length_errors = nsd->rx_length_errors;
870
871 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
872 pf->stat_offsets_loaded,
873 &osd->link_xon_rx, &nsd->link_xon_rx);
874 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
875 pf->stat_offsets_loaded,
876 &osd->link_xon_tx, &nsd->link_xon_tx);
877 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
878 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
879 pf->stat_offsets_loaded,
880 &osd->link_xoff_tx, &nsd->link_xoff_tx);
881
882 for (i = 0; i < 8; i++) {
883 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
884 pf->stat_offsets_loaded,
885 &osd->priority_xon_rx[i],
886 &nsd->priority_xon_rx[i]);
887 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
888 pf->stat_offsets_loaded,
889 &osd->priority_xon_tx[i],
890 &nsd->priority_xon_tx[i]);
891 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
892 pf->stat_offsets_loaded,
893 &osd->priority_xoff_tx[i],
894 &nsd->priority_xoff_tx[i]);
895 i40e_stat_update32(hw,
896 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
897 pf->stat_offsets_loaded,
898 &osd->priority_xon_2_xoff[i],
899 &nsd->priority_xon_2_xoff[i]);
900 }
901
902 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
903 I40E_GLPRT_PRC64L(hw->port),
904 pf->stat_offsets_loaded,
905 &osd->rx_size_64, &nsd->rx_size_64);
906 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
907 I40E_GLPRT_PRC127L(hw->port),
908 pf->stat_offsets_loaded,
909 &osd->rx_size_127, &nsd->rx_size_127);
910 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
911 I40E_GLPRT_PRC255L(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->rx_size_255, &nsd->rx_size_255);
914 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
915 I40E_GLPRT_PRC511L(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->rx_size_511, &nsd->rx_size_511);
918 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
919 I40E_GLPRT_PRC1023L(hw->port),
920 pf->stat_offsets_loaded,
921 &osd->rx_size_1023, &nsd->rx_size_1023);
922 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
923 I40E_GLPRT_PRC1522L(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->rx_size_1522, &nsd->rx_size_1522);
926 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
927 I40E_GLPRT_PRC9522L(hw->port),
928 pf->stat_offsets_loaded,
929 &osd->rx_size_big, &nsd->rx_size_big);
930
931 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
932 I40E_GLPRT_PTC64L(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->tx_size_64, &nsd->tx_size_64);
935 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
936 I40E_GLPRT_PTC127L(hw->port),
937 pf->stat_offsets_loaded,
938 &osd->tx_size_127, &nsd->tx_size_127);
939 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
940 I40E_GLPRT_PTC255L(hw->port),
941 pf->stat_offsets_loaded,
942 &osd->tx_size_255, &nsd->tx_size_255);
943 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
944 I40E_GLPRT_PTC511L(hw->port),
945 pf->stat_offsets_loaded,
946 &osd->tx_size_511, &nsd->tx_size_511);
947 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
948 I40E_GLPRT_PTC1023L(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->tx_size_1023, &nsd->tx_size_1023);
951 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
952 I40E_GLPRT_PTC1522L(hw->port),
953 pf->stat_offsets_loaded,
954 &osd->tx_size_1522, &nsd->tx_size_1522);
955 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
956 I40E_GLPRT_PTC9522L(hw->port),
957 pf->stat_offsets_loaded,
958 &osd->tx_size_big, &nsd->tx_size_big);
959
960 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->rx_undersize, &nsd->rx_undersize);
963 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->rx_fragments, &nsd->rx_fragments);
966 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->rx_oversize, &nsd->rx_oversize);
969 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
970 pf->stat_offsets_loaded,
971 &osd->rx_jabber, &nsd->rx_jabber);
972 }
973
974 pf->stat_offsets_loaded = true;
975}
976
977/**
978 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
979 * @vsi: the VSI to be searched
980 * @macaddr: the MAC address
981 * @vlan: the vlan
982 * @is_vf: make sure its a vf filter, else doesn't matter
983 * @is_netdev: make sure its a netdev filter, else doesn't matter
984 *
985 * Returns ptr to the filter object or NULL
986 **/
987static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
988 u8 *macaddr, s16 vlan,
989 bool is_vf, bool is_netdev)
990{
991 struct i40e_mac_filter *f;
992
993 if (!vsi || !macaddr)
994 return NULL;
995
996 list_for_each_entry(f, &vsi->mac_filter_list, list) {
997 if ((ether_addr_equal(macaddr, f->macaddr)) &&
998 (vlan == f->vlan) &&
999 (!is_vf || f->is_vf) &&
1000 (!is_netdev || f->is_netdev))
1001 return f;
1002 }
1003 return NULL;
1004}
1005
1006/**
1007 * i40e_find_mac - Find a mac addr in the macvlan filters list
1008 * @vsi: the VSI to be searched
1009 * @macaddr: the MAC address we are searching for
1010 * @is_vf: make sure its a vf filter, else doesn't matter
1011 * @is_netdev: make sure its a netdev filter, else doesn't matter
1012 *
1013 * Returns the first filter with the provided MAC address or NULL if
1014 * MAC address was not found
1015 **/
1016struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1017 bool is_vf, bool is_netdev)
1018{
1019 struct i40e_mac_filter *f;
1020
1021 if (!vsi || !macaddr)
1022 return NULL;
1023
1024 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1025 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1026 (!is_vf || f->is_vf) &&
1027 (!is_netdev || f->is_netdev))
1028 return f;
1029 }
1030 return NULL;
1031}
1032
1033/**
1034 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1035 * @vsi: the VSI to be searched
1036 *
1037 * Returns true if VSI is in vlan mode or false otherwise
1038 **/
1039bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1040{
1041 struct i40e_mac_filter *f;
1042
1043 /* Only -1 for all the filters denotes not in vlan mode
1044 * so we have to go through all the list in order to make sure
1045 */
1046 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1047 if (f->vlan >= 0)
1048 return true;
1049 }
1050
1051 return false;
1052}
1053
1054/**
1055 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1056 * @vsi: the VSI to be searched
1057 * @macaddr: the mac address to be filtered
1058 * @is_vf: true if it is a vf
1059 * @is_netdev: true if it is a netdev
1060 *
1061 * Goes through all the macvlan filters and adds a
1062 * macvlan filter for each unique vlan that already exists
1063 *
1064 * Returns first filter found on success, else NULL
1065 **/
1066struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1067 bool is_vf, bool is_netdev)
1068{
1069 struct i40e_mac_filter *f;
1070
1071 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1072 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1073 is_vf, is_netdev)) {
1074 if (!i40e_add_filter(vsi, macaddr, f->vlan,
1075 is_vf, is_netdev))
1076 return NULL;
1077 }
1078 }
1079
1080 return list_first_entry_or_null(&vsi->mac_filter_list,
1081 struct i40e_mac_filter, list);
1082}
1083
1084/**
1085 * i40e_add_filter - Add a mac/vlan filter to the VSI
1086 * @vsi: the VSI to be searched
1087 * @macaddr: the MAC address
1088 * @vlan: the vlan
1089 * @is_vf: make sure its a vf filter, else doesn't matter
1090 * @is_netdev: make sure its a netdev filter, else doesn't matter
1091 *
1092 * Returns ptr to the filter object or NULL when no memory available.
1093 **/
1094struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1095 u8 *macaddr, s16 vlan,
1096 bool is_vf, bool is_netdev)
1097{
1098 struct i40e_mac_filter *f;
1099
1100 if (!vsi || !macaddr)
1101 return NULL;
1102
1103 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1104 if (!f) {
1105 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1106 if (!f)
1107 goto add_filter_out;
1108
1109 memcpy(f->macaddr, macaddr, ETH_ALEN);
1110 f->vlan = vlan;
1111 f->changed = true;
1112
1113 INIT_LIST_HEAD(&f->list);
1114 list_add(&f->list, &vsi->mac_filter_list);
1115 }
1116
1117 /* increment counter and add a new flag if needed */
1118 if (is_vf) {
1119 if (!f->is_vf) {
1120 f->is_vf = true;
1121 f->counter++;
1122 }
1123 } else if (is_netdev) {
1124 if (!f->is_netdev) {
1125 f->is_netdev = true;
1126 f->counter++;
1127 }
1128 } else {
1129 f->counter++;
1130 }
1131
1132 /* changed tells sync_filters_subtask to
1133 * push the filter down to the firmware
1134 */
1135 if (f->changed) {
1136 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1137 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1138 }
1139
1140add_filter_out:
1141 return f;
1142}
1143
1144/**
1145 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1146 * @vsi: the VSI to be searched
1147 * @macaddr: the MAC address
1148 * @vlan: the vlan
1149 * @is_vf: make sure it's a vf filter, else doesn't matter
1150 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1151 **/
1152void i40e_del_filter(struct i40e_vsi *vsi,
1153 u8 *macaddr, s16 vlan,
1154 bool is_vf, bool is_netdev)
1155{
1156 struct i40e_mac_filter *f;
1157
1158 if (!vsi || !macaddr)
1159 return;
1160
1161 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1162 if (!f || f->counter == 0)
1163 return;
1164
1165 if (is_vf) {
1166 if (f->is_vf) {
1167 f->is_vf = false;
1168 f->counter--;
1169 }
1170 } else if (is_netdev) {
1171 if (f->is_netdev) {
1172 f->is_netdev = false;
1173 f->counter--;
1174 }
1175 } else {
1176 /* make sure we don't remove a filter in use by vf or netdev */
1177 int min_f = 0;
1178 min_f += (f->is_vf ? 1 : 0);
1179 min_f += (f->is_netdev ? 1 : 0);
1180
1181 if (f->counter > min_f)
1182 f->counter--;
1183 }
1184
1185 /* counter == 0 tells sync_filters_subtask to
1186 * remove the filter from the firmware's list
1187 */
1188 if (f->counter == 0) {
1189 f->changed = true;
1190 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1191 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1192 }
1193}
1194
1195/**
1196 * i40e_set_mac - NDO callback to set mac address
1197 * @netdev: network interface device structure
1198 * @p: pointer to an address structure
1199 *
1200 * Returns 0 on success, negative on failure
1201 **/
1202static int i40e_set_mac(struct net_device *netdev, void *p)
1203{
1204 struct i40e_netdev_priv *np = netdev_priv(netdev);
1205 struct i40e_vsi *vsi = np->vsi;
1206 struct sockaddr *addr = p;
1207 struct i40e_mac_filter *f;
1208
1209 if (!is_valid_ether_addr(addr->sa_data))
1210 return -EADDRNOTAVAIL;
1211
1212 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1213
1214 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1215 return 0;
1216
80f6428f
ASJ		 1217 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1218 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1219 return -EADDRNOTAVAIL;
1220
41c445ff
JB		 1221 if (vsi->type == I40E_VSI_MAIN) {
1222 i40e_status ret;
1223 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1224 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1225 addr->sa_data, NULL);
1226 if (ret) {
1227 netdev_info(netdev,
1228 "Addr change for Main VSI failed: %d\n",
1229 ret);
1230 return -EADDRNOTAVAIL;
1231 }
1232
1233 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1234 }
1235
1236 /* In order to be sure to not drop any packets, add the new address
1237 * then delete the old one.
1238 */
1239 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1240 if (!f)
1241 return -ENOMEM;
1242
1243 i40e_sync_vsi_filters(vsi);
1244 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1245 i40e_sync_vsi_filters(vsi);
1246
1247 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1248
1249 return 0;
1250}
1251
1252/**
1253 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1254 * @vsi: the VSI being setup
1255 * @ctxt: VSI context structure
1256 * @enabled_tc: Enabled TCs bitmap
1257 * @is_add: True if called before Add VSI
1258 *
1259 * Setup VSI queue mapping for enabled traffic classes.
1260 **/
1261static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1262 struct i40e_vsi_context *ctxt,
1263 u8 enabled_tc,
1264 bool is_add)
1265{
1266 struct i40e_pf *pf = vsi->back;
1267 u16 sections = 0;
1268 u8 netdev_tc = 0;
1269 u16 numtc = 0;
1270 u16 qcount;
1271 u8 offset;
1272 u16 qmap;
1273 int i;
1274
1275 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1276 offset = 0;
1277
1278 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1279 /* Find numtc from enabled TC bitmap */
1280 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1281 if (enabled_tc & (1 << i)) /* TC is enabled */
1282 numtc++;
1283 }
1284 if (!numtc) {
1285 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1286 numtc = 1;
1287 }
1288 } else {
1289 /* At least TC0 is enabled in case of non-DCB case */
1290 numtc = 1;
1291 }
1292
1293 vsi->tc_config.numtc = numtc;
1294 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1295
1296 /* Setup queue offset/count for all TCs for given VSI */
1297 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1298 /* See if the given TC is enabled for the given VSI */
1299 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1300 int pow, num_qps;
1301
1302 vsi->tc_config.tc_info[i].qoffset = offset;
1303 switch (vsi->type) {
1304 case I40E_VSI_MAIN:
1305 if (i == 0)
1306 qcount = pf->rss_size;
1307 else
1308 qcount = pf->num_tc_qps;
1309 vsi->tc_config.tc_info[i].qcount = qcount;
1310 break;
1311 case I40E_VSI_FDIR:
1312 case I40E_VSI_SRIOV:
1313 case I40E_VSI_VMDQ2:
1314 default:
1315 qcount = vsi->alloc_queue_pairs;
1316 vsi->tc_config.tc_info[i].qcount = qcount;
1317 WARN_ON(i != 0);
1318 break;
1319 }
1320
1321 /* find the power-of-2 of the number of queue pairs */
1322 num_qps = vsi->tc_config.tc_info[i].qcount;
1323 pow = 0;
1324 while (num_qps &&
1325 ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
1326 pow++;
1327 num_qps >>= 1;
1328 }
1329
1330 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1331 qmap =
1332 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1333 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1334
1335 offset += vsi->tc_config.tc_info[i].qcount;
1336 } else {
1337 /* TC is not enabled so set the offset to
1338 * default queue and allocate one queue
1339 * for the given TC.
1340 */
1341 vsi->tc_config.tc_info[i].qoffset = 0;
1342 vsi->tc_config.tc_info[i].qcount = 1;
1343 vsi->tc_config.tc_info[i].netdev_tc = 0;
1344
1345 qmap = 0;
1346 }
1347 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1348 }
1349
1350 /* Set actual Tx/Rx queue pairs */
1351 vsi->num_queue_pairs = offset;
1352
1353 /* Scheduler section valid can only be set for ADD VSI */
1354 if (is_add) {
1355 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1356
1357 ctxt->info.up_enable_bits = enabled_tc;
1358 }
1359 if (vsi->type == I40E_VSI_SRIOV) {
1360 ctxt->info.mapping_flags |=
1361 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1362 for (i = 0; i < vsi->num_queue_pairs; i++)
1363 ctxt->info.queue_mapping[i] =
1364 cpu_to_le16(vsi->base_queue + i);
1365 } else {
1366 ctxt->info.mapping_flags |=
1367 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1368 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1369 }
1370 ctxt->info.valid_sections |= cpu_to_le16(sections);
1371}
1372
1373/**
1374 * i40e_set_rx_mode - NDO callback to set the netdev filters
1375 * @netdev: network interface device structure
1376 **/
1377static void i40e_set_rx_mode(struct net_device *netdev)
1378{
1379 struct i40e_netdev_priv *np = netdev_priv(netdev);
1380 struct i40e_mac_filter *f, *ftmp;
1381 struct i40e_vsi *vsi = np->vsi;
1382 struct netdev_hw_addr *uca;
1383 struct netdev_hw_addr *mca;
1384 struct netdev_hw_addr *ha;
1385
1386 /* add addr if not already in the filter list */
1387 netdev_for_each_uc_addr(uca, netdev) {
1388 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1389 if (i40e_is_vsi_in_vlan(vsi))
1390 i40e_put_mac_in_vlan(vsi, uca->addr,
1391 false, true);
1392 else
1393 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1394 false, true);
1395 }
1396 }
1397
1398 netdev_for_each_mc_addr(mca, netdev) {
1399 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1400 if (i40e_is_vsi_in_vlan(vsi))
1401 i40e_put_mac_in_vlan(vsi, mca->addr,
1402 false, true);
1403 else
1404 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1405 false, true);
1406 }
1407 }
1408
1409 /* remove filter if not in netdev list */
1410 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1411 bool found = false;
1412
1413 if (!f->is_netdev)
1414 continue;
1415
1416 if (is_multicast_ether_addr(f->macaddr)) {
1417 netdev_for_each_mc_addr(mca, netdev) {
1418 if (ether_addr_equal(mca->addr, f->macaddr)) {
1419 found = true;
1420 break;
1421 }
1422 }
1423 } else {
1424 netdev_for_each_uc_addr(uca, netdev) {
1425 if (ether_addr_equal(uca->addr, f->macaddr)) {
1426 found = true;
1427 break;
1428 }
1429 }
1430
1431 for_each_dev_addr(netdev, ha) {
1432 if (ether_addr_equal(ha->addr, f->macaddr)) {
1433 found = true;
1434 break;
1435 }
1436 }
1437 }
1438 if (!found)
1439 i40e_del_filter(
1440 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1441 }
1442
1443 /* check for other flag changes */
1444 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1445 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1446 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1447 }
1448}
1449
1450/**
1451 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1452 * @vsi: ptr to the VSI
1453 *
1454 * Push any outstanding VSI filter changes through the AdminQ.
1455 *
1456 * Returns 0 or error value
1457 **/
1458int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1459{
1460 struct i40e_mac_filter *f, *ftmp;
1461 bool promisc_forced_on = false;
1462 bool add_happened = false;
1463 int filter_list_len = 0;
1464 u32 changed_flags = 0;
dcae29be 1465 i40e_status aq_ret = 0;
41c445ff
JB		 1466 struct i40e_pf *pf;
1467 int num_add = 0;
1468 int num_del = 0;
1469 u16 cmd_flags;
1470
1471 /* empty array typed pointers, kcalloc later */
1472 struct i40e_aqc_add_macvlan_element_data *add_list;
1473 struct i40e_aqc_remove_macvlan_element_data *del_list;
1474
1475 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1476 usleep_range(1000, 2000);
1477 pf = vsi->back;
1478
1479 if (vsi->netdev) {
1480 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1481 vsi->current_netdev_flags = vsi->netdev->flags;
1482 }
1483
1484 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1485 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1486
1487 filter_list_len = pf->hw.aq.asq_buf_size /
1488 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1489 del_list = kcalloc(filter_list_len,
1490 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1491 GFP_KERNEL);
1492 if (!del_list)
1493 return -ENOMEM;
1494
1495 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1496 if (!f->changed)
1497 continue;
1498
1499 if (f->counter != 0)
1500 continue;
1501 f->changed = false;
1502 cmd_flags = 0;
1503
1504 /* add to delete list */
1505 memcpy(del_list[num_del].mac_addr,
1506 f->macaddr, ETH_ALEN);
1507 del_list[num_del].vlan_tag =
1508 cpu_to_le16((u16)(f->vlan ==
1509 I40E_VLAN_ANY ? 0 : f->vlan));
1510
41c445ff
JB		 1511 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1512 del_list[num_del].flags = cmd_flags;
1513 num_del++;
1514
1515 /* unlink from filter list */
1516 list_del(&f->list);
1517 kfree(f);
1518
1519 /* flush a full buffer */
1520 if (num_del == filter_list_len) {
dcae29be 1521 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1522 vsi->seid, del_list, num_del,
1523 NULL);
1524 num_del = 0;
1525 memset(del_list, 0, sizeof(*del_list));
1526
dcae29be 1527 if (aq_ret)
41c445ff
JB		 1528 dev_info(&pf->pdev->dev,
1529 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1530 aq_ret,
41c445ff
JB		 1531 pf->hw.aq.asq_last_status);
1532 }
1533 }
1534 if (num_del) {
dcae29be 1535 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1536 del_list, num_del, NULL);
1537 num_del = 0;
1538
dcae29be 1539 if (aq_ret)
41c445ff
JB		 1540 dev_info(&pf->pdev->dev,
1541 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1542 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1543 }
1544
1545 kfree(del_list);
1546 del_list = NULL;
1547
1548 /* do all the adds now */
1549 filter_list_len = pf->hw.aq.asq_buf_size /
1550 sizeof(struct i40e_aqc_add_macvlan_element_data),
1551 add_list = kcalloc(filter_list_len,
1552 sizeof(struct i40e_aqc_add_macvlan_element_data),
1553 GFP_KERNEL);
1554 if (!add_list)
1555 return -ENOMEM;
1556
1557 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1558 if (!f->changed)
1559 continue;
1560
1561 if (f->counter == 0)
1562 continue;
1563 f->changed = false;
1564 add_happened = true;
1565 cmd_flags = 0;
1566
1567 /* add to add array */
1568 memcpy(add_list[num_add].mac_addr,
1569 f->macaddr, ETH_ALEN);
1570 add_list[num_add].vlan_tag =
1571 cpu_to_le16(
1572 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1573 add_list[num_add].queue_number = 0;
1574
1575 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1576 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1577 num_add++;
1578
1579 /* flush a full buffer */
1580 if (num_add == filter_list_len) {
dcae29be
JB		 1581 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1582 add_list, num_add,
1583 NULL);
41c445ff
JB		 1584 num_add = 0;
1585
dcae29be 1586 if (aq_ret)
41c445ff
JB		 1587 break;
1588 memset(add_list, 0, sizeof(*add_list));
1589 }
1590 }
1591 if (num_add) {
dcae29be
JB		 1592 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1593 add_list, num_add, NULL);
41c445ff
JB		 1594 num_add = 0;
1595 }
1596 kfree(add_list);
1597 add_list = NULL;
1598
dcae29be 1599 if (add_happened && (!aq_ret)) {
41c445ff 1600 /* do nothing */;
dcae29be 1601 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1602 dev_info(&pf->pdev->dev,
1603 "add filter failed, err %d, aq_err %d\n",
dcae29be 1604 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1605 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1606 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1607 &vsi->state)) {
1608 promisc_forced_on = true;
1609 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1610 &vsi->state);
1611 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1612 }
1613 }
1614 }
1615
1616 /* check for changes in promiscuous modes */
1617 if (changed_flags & IFF_ALLMULTI) {
1618 bool cur_multipromisc;
1619 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1620 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1621 vsi->seid,
1622 cur_multipromisc,
1623 NULL);
1624 if (aq_ret)
41c445ff
JB		 1625 dev_info(&pf->pdev->dev,
1626 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1627 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1628 }
1629 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1630 bool cur_promisc;
1631 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1632 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1633 &vsi->state));
dcae29be
JB		 1634 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1635 vsi->seid,
1636 cur_promisc, NULL);
1637 if (aq_ret)
41c445ff
JB		 1638 dev_info(&pf->pdev->dev,
1639 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1640 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1641 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1642 vsi->seid,
1643 cur_promisc, NULL);
1644 if (aq_ret)
1645 dev_info(&pf->pdev->dev,
1646 "set brdcast promisc failed, err %d, aq_err %d\n",
1647 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1648 }
1649
1650 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1651 return 0;
1652}
1653
1654/**
1655 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1656 * @pf: board private structure
1657 **/
1658static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1659{
1660 int v;
1661
1662 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1663 return;
1664 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1665
1666 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1667 if (pf->vsi[v] &&
1668 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1669 i40e_sync_vsi_filters(pf->vsi[v]);
1670 }
1671}
1672
1673/**
1674 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1675 * @netdev: network interface device structure
1676 * @new_mtu: new value for maximum frame size
1677 *
1678 * Returns 0 on success, negative on failure
1679 **/
1680static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1681{
1682 struct i40e_netdev_priv *np = netdev_priv(netdev);
1683 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1684 struct i40e_vsi *vsi = np->vsi;
1685
1686 /* MTU < 68 is an error and causes problems on some kernels */
1687 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1688 return -EINVAL;
1689
1690 netdev_info(netdev, "changing MTU from %d to %d\n",
1691 netdev->mtu, new_mtu);
1692 netdev->mtu = new_mtu;
1693 if (netif_running(netdev))
1694 i40e_vsi_reinit_locked(vsi);
1695
1696 return 0;
1697}
1698
beb0dff1
JK		 1699/**
1700 * i40e_ioctl - Access the hwtstamp interface
1701 * @netdev: network interface device structure
1702 * @ifr: interface request data
1703 * @cmd: ioctl command
1704 **/
1705int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1706{
1707 struct i40e_netdev_priv *np = netdev_priv(netdev);
1708 struct i40e_pf *pf = np->vsi->back;
1709
1710 switch (cmd) {
1711 case SIOCGHWTSTAMP:
1712 return i40e_ptp_get_ts_config(pf, ifr);
1713 case SIOCSHWTSTAMP:
1714 return i40e_ptp_set_ts_config(pf, ifr);
1715 default:
1716 return -EOPNOTSUPP;
1717 }
1718}
1719
41c445ff
JB		 1720/**
1721 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1722 * @vsi: the vsi being adjusted
1723 **/
1724void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1725{
1726 struct i40e_vsi_context ctxt;
1727 i40e_status ret;
1728
1729 if ((vsi->info.valid_sections &
1730 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1731 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1732 return; /* already enabled */
1733
1734 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1735 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1736 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1737
1738 ctxt.seid = vsi->seid;
1739 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1740 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1741 if (ret) {
1742 dev_info(&vsi->back->pdev->dev,
1743 "%s: update vsi failed, aq_err=%d\n",
1744 __func__, vsi->back->hw.aq.asq_last_status);
1745 }
1746}
1747
1748/**
1749 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1750 * @vsi: the vsi being adjusted
1751 **/
1752void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1753{
1754 struct i40e_vsi_context ctxt;
1755 i40e_status ret;
1756
1757 if ((vsi->info.valid_sections &
1758 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1759 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1760 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1761 return; /* already disabled */
1762
1763 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1764 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1765 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1766
1767 ctxt.seid = vsi->seid;
1768 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1769 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1770 if (ret) {
1771 dev_info(&vsi->back->pdev->dev,
1772 "%s: update vsi failed, aq_err=%d\n",
1773 __func__, vsi->back->hw.aq.asq_last_status);
1774 }
1775}
1776
1777/**
1778 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1779 * @netdev: network interface to be adjusted
1780 * @features: netdev features to test if VLAN offload is enabled or not
1781 **/
1782static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1783{
1784 struct i40e_netdev_priv *np = netdev_priv(netdev);
1785 struct i40e_vsi *vsi = np->vsi;
1786
1787 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1788 i40e_vlan_stripping_enable(vsi);
1789 else
1790 i40e_vlan_stripping_disable(vsi);
1791}
1792
1793/**
1794 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1795 * @vsi: the vsi being configured
1796 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1797 **/
1798int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1799{
1800 struct i40e_mac_filter *f, *add_f;
1801 bool is_netdev, is_vf;
41c445ff
JB		 1802
1803 is_vf = (vsi->type == I40E_VSI_SRIOV);
1804 is_netdev = !!(vsi->netdev);
1805
1806 if (is_netdev) {
1807 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1808 is_vf, is_netdev);
1809 if (!add_f) {
1810 dev_info(&vsi->back->pdev->dev,
1811 "Could not add vlan filter %d for %pM\n",
1812 vid, vsi->netdev->dev_addr);
1813 return -ENOMEM;
1814 }
1815 }
1816
1817 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1818 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1819 if (!add_f) {
1820 dev_info(&vsi->back->pdev->dev,
1821 "Could not add vlan filter %d for %pM\n",
1822 vid, f->macaddr);
1823 return -ENOMEM;
1824 }
1825 }
1826
41c445ff
JB		 1827 /* Now if we add a vlan tag, make sure to check if it is the first
1828 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1829 * with 0, so we now accept untagged and specified tagged traffic
1830 * (and not any taged and untagged)
1831 */
1832 if (vid > 0) {
1833 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1834 I40E_VLAN_ANY,
1835 is_vf, is_netdev)) {
1836 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1837 I40E_VLAN_ANY, is_vf, is_netdev);
1838 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1839 is_vf, is_netdev);
1840 if (!add_f) {
1841 dev_info(&vsi->back->pdev->dev,
1842 "Could not add filter 0 for %pM\n",
1843 vsi->netdev->dev_addr);
1844 return -ENOMEM;
1845 }
1846 }
8d82a7c5 1847 }
41c445ff 1848
8d82a7c5
GR		 1849 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1850 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1851 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1852 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1853 is_vf, is_netdev)) {
1854 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1855 is_vf, is_netdev);
1856 add_f = i40e_add_filter(vsi, f->macaddr,
1857 0, is_vf, is_netdev);
1858 if (!add_f) {
1859 dev_info(&vsi->back->pdev->dev,
1860 "Could not add filter 0 for %pM\n",
1861 f->macaddr);
1862 return -ENOMEM;
1863 }
1864 }
1865 }
41c445ff
JB		 1866 }
1867
80f6428f
ASJ		 1868 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1869 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1870 return 0;
1871
1872 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1873}
1874
1875/**
1876 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1877 * @vsi: the vsi being configured
1878 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1879 *
1880 * Return: 0 on success or negative otherwise
41c445ff
JB		 1881 **/
1882int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1883{
1884 struct net_device *netdev = vsi->netdev;
1885 struct i40e_mac_filter *f, *add_f;
1886 bool is_vf, is_netdev;
1887 int filter_count = 0;
41c445ff
JB		 1888
1889 is_vf = (vsi->type == I40E_VSI_SRIOV);
1890 is_netdev = !!(netdev);
1891
1892 if (is_netdev)
1893 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1894
1895 list_for_each_entry(f, &vsi->mac_filter_list, list)
1896 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1897
41c445ff
JB		 1898 /* go through all the filters for this VSI and if there is only
1899 * vid == 0 it means there are no other filters, so vid 0 must
1900 * be replaced with -1. This signifies that we should from now
1901 * on accept any traffic (with any tag present, or untagged)
1902 */
1903 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1904 if (is_netdev) {
1905 if (f->vlan &&
1906 ether_addr_equal(netdev->dev_addr, f->macaddr))
1907 filter_count++;
1908 }
1909
1910 if (f->vlan)
1911 filter_count++;
1912 }
1913
1914 if (!filter_count && is_netdev) {
1915 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1916 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1917 is_vf, is_netdev);
1918 if (!f) {
1919 dev_info(&vsi->back->pdev->dev,
1920 "Could not add filter %d for %pM\n",
1921 I40E_VLAN_ANY, netdev->dev_addr);
1922 return -ENOMEM;
1923 }
1924 }
1925
1926 if (!filter_count) {
1927 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1928 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1929 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1930 is_vf, is_netdev);
1931 if (!add_f) {
1932 dev_info(&vsi->back->pdev->dev,
1933 "Could not add filter %d for %pM\n",
1934 I40E_VLAN_ANY, f->macaddr);
1935 return -ENOMEM;
1936 }
1937 }
1938 }
1939
80f6428f
ASJ		 1940 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1941 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1942 return 0;
1943
41c445ff
JB		 1944 return i40e_sync_vsi_filters(vsi);
1945}
1946
1947/**
1948 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1949 * @netdev: network interface to be adjusted
1950 * @vid: vlan id to be added
078b5876
JB		 1951 *
1952 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1953 **/
1954static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1955 __always_unused __be16 proto, u16 vid)
1956{
1957 struct i40e_netdev_priv *np = netdev_priv(netdev);
1958 struct i40e_vsi *vsi = np->vsi;
078b5876 1959 int ret = 0;
41c445ff
JB		 1960
1961 if (vid > 4095)
078b5876
JB		 1962 return -EINVAL;
1963
1964 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1965
41c445ff
JB		 1966 /* If the network stack called us with vid = 0, we should
1967 * indicate to i40e_vsi_add_vlan() that we want to receive
1968 * any traffic (i.e. with any vlan tag, or untagged)
1969 */
1970 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1971
078b5876
JB		 1972 if (!ret && (vid < VLAN_N_VID))
1973 set_bit(vid, vsi->active_vlans);
41c445ff 1974
078b5876 1975 return ret;
41c445ff
JB		 1976}
1977
1978/**
1979 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1980 * @netdev: network interface to be adjusted
1981 * @vid: vlan id to be removed
078b5876
JB		 1982 *
1983 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1984 **/
1985static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1986 __always_unused __be16 proto, u16 vid)
1987{
1988 struct i40e_netdev_priv *np = netdev_priv(netdev);
1989 struct i40e_vsi *vsi = np->vsi;
1990
078b5876
JB		 1991 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1992
41c445ff
JB		 1993 /* return code is ignored as there is nothing a user
1994 * can do about failure to remove and a log message was
078b5876 1995 * already printed from the other function
41c445ff
JB		 1996 */
1997 i40e_vsi_kill_vlan(vsi, vid);
1998
1999 clear_bit(vid, vsi->active_vlans);
078b5876 2000
41c445ff
JB		 2001 return 0;
2002}
2003
2004/**
2005 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2006 * @vsi: the vsi being brought back up
2007 **/
2008static void i40e_restore_vlan(struct i40e_vsi *vsi)
2009{
2010 u16 vid;
2011
2012 if (!vsi->netdev)
2013 return;
2014
2015 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2016
2017 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2018 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2019 vid);
2020}
2021
2022/**
2023 * i40e_vsi_add_pvid - Add pvid for the VSI
2024 * @vsi: the vsi being adjusted
2025 * @vid: the vlan id to set as a PVID
2026 **/
dcae29be 2027int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2028{
2029 struct i40e_vsi_context ctxt;
dcae29be 2030 i40e_status aq_ret;
41c445ff
JB		 2031
2032 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2033 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2034 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2035 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2036 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2037
2038 ctxt.seid = vsi->seid;
2039 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2040 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2041 if (aq_ret) {
41c445ff
JB		 2042 dev_info(&vsi->back->pdev->dev,
2043 "%s: update vsi failed, aq_err=%d\n",
2044 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2045 return -ENOENT;
41c445ff
JB		 2046 }
2047
dcae29be 2048 return 0;
41c445ff
JB		 2049}
2050
2051/**
2052 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2053 * @vsi: the vsi being adjusted
2054 *
2055 * Just use the vlan_rx_register() service to put it back to normal
2056 **/
2057void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2058{
6c12fcbf
GR		 2059 i40e_vlan_stripping_disable(vsi);
2060
41c445ff 2061 vsi->info.pvid = 0;
41c445ff
JB		 2062}
2063
2064/**
2065 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2066 * @vsi: ptr to the VSI
2067 *
2068 * If this function returns with an error, then it's possible one or
2069 * more of the rings is populated (while the rest are not). It is the
2070 * callers duty to clean those orphaned rings.
2071 *
2072 * Return 0 on success, negative on failure
2073 **/
2074static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2075{
2076 int i, err = 0;
2077
2078 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2079 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2080
2081 return err;
2082}
2083
2084/**
2085 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2086 * @vsi: ptr to the VSI
2087 *
2088 * Free VSI's transmit software resources
2089 **/
2090static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2091{
2092 int i;
2093
8e9dca53
GR		 2094 if (!vsi->tx_rings)
2095 return;
2096
41c445ff 2097 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2098 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2099 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2100}
2101
2102/**
2103 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2104 * @vsi: ptr to the VSI
2105 *
2106 * If this function returns with an error, then it's possible one or
2107 * more of the rings is populated (while the rest are not). It is the
2108 * callers duty to clean those orphaned rings.
2109 *
2110 * Return 0 on success, negative on failure
2111 **/
2112static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2113{
2114 int i, err = 0;
2115
2116 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2117 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2118 return err;
2119}
2120
2121/**
2122 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2123 * @vsi: ptr to the VSI
2124 *
2125 * Free all receive software resources
2126 **/
2127static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2128{
2129 int i;
2130
8e9dca53
GR		 2131 if (!vsi->rx_rings)
2132 return;
2133
41c445ff 2134 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2135 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2136 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2137}
2138
2139/**
2140 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2141 * @ring: The Tx ring to configure
2142 *
2143 * Configure the Tx descriptor ring in the HMC context.
2144 **/
2145static int i40e_configure_tx_ring(struct i40e_ring *ring)
2146{
2147 struct i40e_vsi *vsi = ring->vsi;
2148 u16 pf_q = vsi->base_queue + ring->queue_index;
2149 struct i40e_hw *hw = &vsi->back->hw;
2150 struct i40e_hmc_obj_txq tx_ctx;
2151 i40e_status err = 0;
2152 u32 qtx_ctl = 0;
2153
2154 /* some ATR related tx ring init */
2155 if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
2156 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2157 ring->atr_count = 0;
2158 } else {
2159 ring->atr_sample_rate = 0;
2160 }
2161
2162 /* initialize XPS */
2163 if (ring->q_vector && ring->netdev &&
2164 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2165 netif_set_xps_queue(ring->netdev,
2166 &ring->q_vector->affinity_mask,
2167 ring->queue_index);
2168
2169 /* clear the context structure first */
2170 memset(&tx_ctx, 0, sizeof(tx_ctx));
2171
2172 tx_ctx.new_context = 1;
2173 tx_ctx.base = (ring->dma / 128);
2174 tx_ctx.qlen = ring->count;
2175 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
beb0dff1
JK		 2176 I40E_FLAG_FDIR_ATR_ENABLED));
2177 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
41c445ff
JB		 2178
2179 /* As part of VSI creation/update, FW allocates certain
2180 * Tx arbitration queue sets for each TC enabled for
2181 * the VSI. The FW returns the handles to these queue
2182 * sets as part of the response buffer to Add VSI,
2183 * Update VSI, etc. AQ commands. It is expected that
2184 * these queue set handles be associated with the Tx
2185 * queues by the driver as part of the TX queue context
2186 * initialization. This has to be done regardless of
2187 * DCB as by default everything is mapped to TC0.
2188 */
2189 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2190 tx_ctx.rdylist_act = 0;
2191
2192 /* clear the context in the HMC */
2193 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2194 if (err) {
2195 dev_info(&vsi->back->pdev->dev,
2196 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2197 ring->queue_index, pf_q, err);
2198 return -ENOMEM;
2199 }
2200
2201 /* set the context in the HMC */
2202 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2203 if (err) {
2204 dev_info(&vsi->back->pdev->dev,
2205 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2206 ring->queue_index, pf_q, err);
2207 return -ENOMEM;
2208 }
2209
2210 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2211 if (vsi->type == I40E_VSI_VMDQ2)
2212 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2213 else
2214 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2215 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2216 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2217 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2218 i40e_flush(hw);
2219
2220 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2221
2222 /* cache tail off for easier writes later */
2223 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2224
2225 return 0;
2226}
2227
2228/**
2229 * i40e_configure_rx_ring - Configure a receive ring context
2230 * @ring: The Rx ring to configure
2231 *
2232 * Configure the Rx descriptor ring in the HMC context.
2233 **/
2234static int i40e_configure_rx_ring(struct i40e_ring *ring)
2235{
2236 struct i40e_vsi *vsi = ring->vsi;
2237 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2238 u16 pf_q = vsi->base_queue + ring->queue_index;
2239 struct i40e_hw *hw = &vsi->back->hw;
2240 struct i40e_hmc_obj_rxq rx_ctx;
2241 i40e_status err = 0;
2242
2243 ring->state = 0;
2244
2245 /* clear the context structure first */
2246 memset(&rx_ctx, 0, sizeof(rx_ctx));
2247
2248 ring->rx_buf_len = vsi->rx_buf_len;
2249 ring->rx_hdr_len = vsi->rx_hdr_len;
2250
2251 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2252 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2253
2254 rx_ctx.base = (ring->dma / 128);
2255 rx_ctx.qlen = ring->count;
2256
2257 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2258 set_ring_16byte_desc_enabled(ring);
2259 rx_ctx.dsize = 0;
2260 } else {
2261 rx_ctx.dsize = 1;
2262 }
2263
2264 rx_ctx.dtype = vsi->dtype;
2265 if (vsi->dtype) {
2266 set_ring_ps_enabled(ring);
2267 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2268 I40E_RX_SPLIT_IP |
2269 I40E_RX_SPLIT_TCP_UDP |
2270 I40E_RX_SPLIT_SCTP;
2271 } else {
2272 rx_ctx.hsplit_0 = 0;
2273 }
2274
2275 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2276 (chain_len * ring->rx_buf_len));
2277 rx_ctx.tphrdesc_ena = 1;
2278 rx_ctx.tphwdesc_ena = 1;
2279 rx_ctx.tphdata_ena = 1;
2280 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2281 if (hw->revision_id == 0)
2282 rx_ctx.lrxqthresh = 0;
2283 else
2284 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2285 rx_ctx.crcstrip = 1;
2286 rx_ctx.l2tsel = 1;
2287 rx_ctx.showiv = 1;
2288
2289 /* clear the context in the HMC */
2290 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2291 if (err) {
2292 dev_info(&vsi->back->pdev->dev,
2293 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2294 ring->queue_index, pf_q, err);
2295 return -ENOMEM;
2296 }
2297
2298 /* set the context in the HMC */
2299 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2300 if (err) {
2301 dev_info(&vsi->back->pdev->dev,
2302 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2303 ring->queue_index, pf_q, err);
2304 return -ENOMEM;
2305 }
2306
2307 /* cache tail for quicker writes, and clear the reg before use */
2308 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2309 writel(0, ring->tail);
2310
2311 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2312
2313 return 0;
2314}
2315
2316/**
2317 * i40e_vsi_configure_tx - Configure the VSI for Tx
2318 * @vsi: VSI structure describing this set of rings and resources
2319 *
2320 * Configure the Tx VSI for operation.
2321 **/
2322static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2323{
2324 int err = 0;
2325 u16 i;
2326
9f65e15b
AD		 2327 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2328 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2329
2330 return err;
2331}
2332
2333/**
2334 * i40e_vsi_configure_rx - Configure the VSI for Rx
2335 * @vsi: the VSI being configured
2336 *
2337 * Configure the Rx VSI for operation.
2338 **/
2339static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2340{
2341 int err = 0;
2342 u16 i;
2343
2344 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2345 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2346 + ETH_FCS_LEN + VLAN_HLEN;
2347 else
2348 vsi->max_frame = I40E_RXBUFFER_2048;
2349
2350 /* figure out correct receive buffer length */
2351 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2352 I40E_FLAG_RX_PS_ENABLED)) {
2353 case I40E_FLAG_RX_1BUF_ENABLED:
2354 vsi->rx_hdr_len = 0;
2355 vsi->rx_buf_len = vsi->max_frame;
2356 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2357 break;
2358 case I40E_FLAG_RX_PS_ENABLED:
2359 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2360 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2361 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2362 break;
2363 default:
2364 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2365 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2366 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2367 break;
2368 }
2369
2370 /* round up for the chip's needs */
2371 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2372 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2373 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2374 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2375
2376 /* set up individual rings */
2377 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2378 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2379
2380 return err;
2381}
2382
2383/**
2384 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2385 * @vsi: ptr to the VSI
2386 **/
2387static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2388{
2389 u16 qoffset, qcount;
2390 int i, n;
2391
2392 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2393 return;
2394
2395 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2396 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2397 continue;
2398
2399 qoffset = vsi->tc_config.tc_info[n].qoffset;
2400 qcount = vsi->tc_config.tc_info[n].qcount;
2401 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2402 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2403 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2404 rx_ring->dcb_tc = n;
2405 tx_ring->dcb_tc = n;
2406 }
2407 }
2408}
2409
2410/**
2411 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2412 * @vsi: ptr to the VSI
2413 **/
2414static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2415{
2416 if (vsi->netdev)
2417 i40e_set_rx_mode(vsi->netdev);
2418}
2419
2420/**
2421 * i40e_vsi_configure - Set up the VSI for action
2422 * @vsi: the VSI being configured
2423 **/
2424static int i40e_vsi_configure(struct i40e_vsi *vsi)
2425{
2426 int err;
2427
2428 i40e_set_vsi_rx_mode(vsi);
2429 i40e_restore_vlan(vsi);
2430 i40e_vsi_config_dcb_rings(vsi);
2431 err = i40e_vsi_configure_tx(vsi);
2432 if (!err)
2433 err = i40e_vsi_configure_rx(vsi);
2434
2435 return err;
2436}
2437
2438/**
2439 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2440 * @vsi: the VSI being configured
2441 **/
2442static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2443{
2444 struct i40e_pf *pf = vsi->back;
2445 struct i40e_q_vector *q_vector;
2446 struct i40e_hw *hw = &pf->hw;
2447 u16 vector;
2448 int i, q;
2449 u32 val;
2450 u32 qp;
2451
2452 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2453 * and PFINT_LNKLSTn registers, e.g.:
2454 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2455 */
2456 qp = vsi->base_queue;
2457 vector = vsi->base_vector;
493fb300
AD		 2458 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2459 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2460 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2461 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2462 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2463 q_vector->rx.itr);
2464 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2465 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2466 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2467 q_vector->tx.itr);
2468
2469 /* Linked list for the queuepairs assigned to this vector */
2470 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2471 for (q = 0; q < q_vector->num_ringpairs; q++) {
2472 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2473 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2474 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2475 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2476 (I40E_QUEUE_TYPE_TX
2477 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2478
2479 wr32(hw, I40E_QINT_RQCTL(qp), val);
2480
2481 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2482 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2483 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2484 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2485 (I40E_QUEUE_TYPE_RX
2486 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2487
2488 /* Terminate the linked list */
2489 if (q == (q_vector->num_ringpairs - 1))
2490 val |= (I40E_QUEUE_END_OF_LIST
2491 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2492
2493 wr32(hw, I40E_QINT_TQCTL(qp), val);
2494 qp++;
2495 }
2496 }
2497
2498 i40e_flush(hw);
2499}
2500
2501/**
2502 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2503 * @hw: ptr to the hardware info
2504 **/
2505static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2506{
2507 u32 val;
2508
2509 /* clear things first */
2510 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2511 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2512
2513 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2514 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2515 I40E_PFINT_ICR0_ENA_GRST_MASK |
2516 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2517 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2518 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2519 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2520 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2521 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2522 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2523
2524 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2525
2526 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2527 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2528 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2529
2530 /* OTHER_ITR_IDX = 0 */
2531 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2532}
2533
2534/**
2535 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2536 * @vsi: the VSI being configured
2537 **/
2538static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2539{
493fb300 2540 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2541 struct i40e_pf *pf = vsi->back;
2542 struct i40e_hw *hw = &pf->hw;
2543 u32 val;
2544
2545 /* set the ITR configuration */
2546 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2547 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2548 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2549 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2550 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2551 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2552
2553 i40e_enable_misc_int_causes(hw);
2554
2555 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2556 wr32(hw, I40E_PFINT_LNKLST0, 0);
2557
2558 /* Associate the queue pair to the vector and enable the q int */
2559 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2560 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2561 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2562
2563 wr32(hw, I40E_QINT_RQCTL(0), val);
2564
2565 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2566 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2567 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2568
2569 wr32(hw, I40E_QINT_TQCTL(0), val);
2570 i40e_flush(hw);
2571}
2572
2ef28cfb
MW		 2573/**
2574 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2575 * @pf: board private structure
2576 **/
2577void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2578{
2579 struct i40e_hw *hw = &pf->hw;
2580
2581 wr32(hw, I40E_PFINT_DYN_CTL0,
2582 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2583 i40e_flush(hw);
2584}
2585
41c445ff
JB		 2586/**
2587 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2588 * @pf: board private structure
2589 **/
116a57d4 2590void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2591{
2592 struct i40e_hw *hw = &pf->hw;
2593 u32 val;
2594
2595 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2596 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2597 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2598
2599 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2600 i40e_flush(hw);
2601}
2602
2603/**
2604 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2605 * @vsi: pointer to a vsi
2606 * @vector: enable a particular Hw Interrupt vector
2607 **/
2608void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2609{
2610 struct i40e_pf *pf = vsi->back;
2611 struct i40e_hw *hw = &pf->hw;
2612 u32 val;
2613
2614 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2615 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2616 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2617 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2618 /* skip the flush */
41c445ff
JB		 2619}
2620
2621/**
2622 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2623 * @irq: interrupt number
2624 * @data: pointer to a q_vector
2625 **/
2626static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2627{
2628 struct i40e_q_vector *q_vector = data;
2629
cd0b6fa6 2630 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2631 return IRQ_HANDLED;
2632
2633 napi_schedule(&q_vector->napi);
2634
2635 return IRQ_HANDLED;
2636}
2637
2638/**
2639 * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
2640 * @irq: interrupt number
2641 * @data: pointer to a q_vector
2642 **/
2643static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
2644{
2645 struct i40e_q_vector *q_vector = data;
2646
cd0b6fa6 2647 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2648 return IRQ_HANDLED;
2649
2650 pr_info("fdir ring cleaning needed\n");
2651
2652 return IRQ_HANDLED;
2653}
2654
2655/**
2656 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2657 * @vsi: the VSI being configured
2658 * @basename: name for the vector
2659 *
2660 * Allocates MSI-X vectors and requests interrupts from the kernel.
2661 **/
2662static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2663{
2664 int q_vectors = vsi->num_q_vectors;
2665 struct i40e_pf *pf = vsi->back;
2666 int base = vsi->base_vector;
2667 int rx_int_idx = 0;
2668 int tx_int_idx = 0;
2669 int vector, err;
2670
2671 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2672 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2673
cd0b6fa6 2674 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2675 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2676 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2677 tx_int_idx++;
cd0b6fa6 2678 } else if (q_vector->rx.ring) {
41c445ff
JB		 2679 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2680 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2681 } else if (q_vector->tx.ring) {
41c445ff
JB		 2682 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2683 "%s-%s-%d", basename, "tx", tx_int_idx++);
2684 } else {
2685 /* skip this unused q_vector */
2686 continue;
2687 }
2688 err = request_irq(pf->msix_entries[base + vector].vector,
2689 vsi->irq_handler,
2690 0,
2691 q_vector->name,
2692 q_vector);
2693 if (err) {
2694 dev_info(&pf->pdev->dev,
2695 "%s: request_irq failed, error: %d\n",
2696 __func__, err);
2697 goto free_queue_irqs;
2698 }
2699 /* assign the mask for this irq */
2700 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2701 &q_vector->affinity_mask);
2702 }
2703
2704 return 0;
2705
2706free_queue_irqs:
2707 while (vector) {
2708 vector--;
2709 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2710 NULL);
2711 free_irq(pf->msix_entries[base + vector].vector,
2712 &(vsi->q_vectors[vector]));
2713 }
2714 return err;
2715}
2716
2717/**
2718 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2719 * @vsi: the VSI being un-configured
2720 **/
2721static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2722{
2723 struct i40e_pf *pf = vsi->back;
2724 struct i40e_hw *hw = &pf->hw;
2725 int base = vsi->base_vector;
2726 int i;
2727
2728 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2729 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2730 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2731 }
2732
2733 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2734 for (i = vsi->base_vector;
2735 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2736 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2737
2738 i40e_flush(hw);
2739 for (i = 0; i < vsi->num_q_vectors; i++)
2740 synchronize_irq(pf->msix_entries[i + base].vector);
2741 } else {
2742 /* Legacy and MSI mode - this stops all interrupt handling */
2743 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2744 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2745 i40e_flush(hw);
2746 synchronize_irq(pf->pdev->irq);
2747 }
2748}
2749
2750/**
2751 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2752 * @vsi: the VSI being configured
2753 **/
2754static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2755{
2756 struct i40e_pf *pf = vsi->back;
2757 int i;
2758
2759 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2760 for (i = vsi->base_vector;
2761 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2762 i40e_irq_dynamic_enable(vsi, i);
2763 } else {
2764 i40e_irq_dynamic_enable_icr0(pf);
2765 }
2766
1022cb6c 2767 i40e_flush(&pf->hw);
41c445ff
JB		 2768 return 0;
2769}
2770
2771/**
2772 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2773 * @pf: board private structure
2774 **/
2775static void i40e_stop_misc_vector(struct i40e_pf *pf)
2776{
2777 /* Disable ICR 0 */
2778 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2779 i40e_flush(&pf->hw);
2780}
2781
2782/**
2783 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2784 * @irq: interrupt number
2785 * @data: pointer to a q_vector
2786 *
2787 * This is the handler used for all MSI/Legacy interrupts, and deals
2788 * with both queue and non-queue interrupts. This is also used in
2789 * MSIX mode to handle the non-queue interrupts.
2790 **/
2791static irqreturn_t i40e_intr(int irq, void *data)
2792{
2793 struct i40e_pf *pf = (struct i40e_pf *)data;
2794 struct i40e_hw *hw = &pf->hw;
5e823066 2795 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2796 u32 icr0, icr0_remaining;
2797 u32 val, ena_mask;
2798
2799 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2800 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2801
116a57d4
SN		 2802 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2803 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2804 goto enable_intr;
41c445ff 2805
cd92e72f
SN		 2806 /* if interrupt but no bits showing, must be SWINT */
2807 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2808 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2809 pf->sw_int_count++;
2810
41c445ff
JB		 2811 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2812 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2813
2814 /* temporarily disable queue cause for NAPI processing */
2815 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2816 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2817 wr32(hw, I40E_QINT_RQCTL(0), qval);
2818
2819 qval = rd32(hw, I40E_QINT_TQCTL(0));
2820 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2821 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2822
2823 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2824 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2825 }
2826
2827 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2828 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2829 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2830 }
2831
2832 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2833 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2834 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2835 }
2836
2837 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2838 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2839 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2840 }
2841
2842 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2843 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2844 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2845 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2846 val = rd32(hw, I40E_GLGEN_RSTAT);
2847 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2848 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2849 if (val == I40E_RESET_CORER)
41c445ff 2850 pf->corer_count++;
d52cf0a9 2851 else if (val == I40E_RESET_GLOBR)
41c445ff 2852 pf->globr_count++;
d52cf0a9 2853 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2854 pf->empr_count++;
2855 }
2856
9c010ee0
ASJ		 2857 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2858 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2859 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2860 }
2861
beb0dff1
JK		 2862 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2863 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2864
2865 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
2866 ena_mask &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2867 i40e_ptp_tx_hwtstamp(pf);
2868 prttsyn_stat &= ~I40E_PRTTSYN_STAT_0_TXTIME_MASK;
2869 }
2870
2871 wr32(hw, I40E_PRTTSYN_STAT_0, prttsyn_stat);
2872 }
2873
41c445ff
JB		 2874 /* If a critical error is pending we have no choice but to reset the
2875 * device.
2876 * Report and mask out any remaining unexpected interrupts.
2877 */
2878 icr0_remaining = icr0 & ena_mask;
2879 if (icr0_remaining) {
2880 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2881 icr0_remaining);
9c010ee0 2882 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2883 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2884 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2885 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2886 dev_info(&pf->pdev->dev, "device will be reset\n");
2887 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2888 i40e_service_event_schedule(pf);
41c445ff
JB		 2889 }
2890 ena_mask &= ~icr0_remaining;
2891 }
5e823066 2892 ret = IRQ_HANDLED;
41c445ff 2893
5e823066 2894enable_intr:
41c445ff
JB		 2895 /* re-enable interrupt causes */
2896 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2897 if (!test_bit(__I40E_DOWN, &pf->state)) {
2898 i40e_service_event_schedule(pf);
2899 i40e_irq_dynamic_enable_icr0(pf);
2900 }
2901
5e823066 2902 return ret;
41c445ff
JB		 2903}
2904
2905/**
cd0b6fa6 2906 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2907 * @vsi: the VSI being configured
2908 * @v_idx: vector index
cd0b6fa6 2909 * @qp_idx: queue pair index
41c445ff 2910 **/
cd0b6fa6 2911static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2912{
493fb300 2913 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2914 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2915 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2916
2917 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2918 tx_ring->next = q_vector->tx.ring;
2919 q_vector->tx.ring = tx_ring;
41c445ff 2920 q_vector->tx.count++;
cd0b6fa6
AD		 2921
2922 rx_ring->q_vector = q_vector;
2923 rx_ring->next = q_vector->rx.ring;
2924 q_vector->rx.ring = rx_ring;
2925 q_vector->rx.count++;
41c445ff
JB		 2926}
2927
2928/**
2929 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
2930 * @vsi: the VSI being configured
2931 *
2932 * This function maps descriptor rings to the queue-specific vectors
2933 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2934 * one vector per queue pair, but on a constrained vector budget, we
2935 * group the queue pairs as "efficiently" as possible.
2936 **/
2937static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
2938{
2939 int qp_remaining = vsi->num_queue_pairs;
2940 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 2941 int num_ringpairs;
41c445ff
JB		 2942 int v_start = 0;
2943 int qp_idx = 0;
2944
2945 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2946 * group them so there are multiple queues per vector.
2947 */
2948 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 2949 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
2950
2951 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
2952
2953 q_vector->num_ringpairs = num_ringpairs;
2954
2955 q_vector->rx.count = 0;
2956 q_vector->tx.count = 0;
2957 q_vector->rx.ring = NULL;
2958 q_vector->tx.ring = NULL;
2959
2960 while (num_ringpairs--) {
2961 map_vector_to_qp(vsi, v_start, qp_idx);
2962 qp_idx++;
2963 qp_remaining--;
41c445ff
JB		 2964 }
2965 }
2966}
2967
2968/**
2969 * i40e_vsi_request_irq - Request IRQ from the OS
2970 * @vsi: the VSI being configured
2971 * @basename: name for the vector
2972 **/
2973static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
2974{
2975 struct i40e_pf *pf = vsi->back;
2976 int err;
2977
2978 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
2979 err = i40e_vsi_request_irq_msix(vsi, basename);
2980 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
2981 err = request_irq(pf->pdev->irq, i40e_intr, 0,
2982 pf->misc_int_name, pf);
2983 else
2984 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
2985 pf->misc_int_name, pf);
2986
2987 if (err)
2988 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
2989
2990 return err;
2991}
2992
2993#ifdef CONFIG_NET_POLL_CONTROLLER
2994/**
2995 * i40e_netpoll - A Polling 'interrupt'handler
2996 * @netdev: network interface device structure
2997 *
2998 * This is used by netconsole to send skbs without having to re-enable
2999 * interrupts. It's not called while the normal interrupt routine is executing.
3000 **/
3001static void i40e_netpoll(struct net_device *netdev)
3002{
3003 struct i40e_netdev_priv *np = netdev_priv(netdev);
3004 struct i40e_vsi *vsi = np->vsi;
3005 struct i40e_pf *pf = vsi->back;
3006 int i;
3007
3008 /* if interface is down do nothing */
3009 if (test_bit(__I40E_DOWN, &vsi->state))
3010 return;
3011
3012 pf->flags |= I40E_FLAG_IN_NETPOLL;
3013 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3014 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3015 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3016 } else {
3017 i40e_intr(pf->pdev->irq, netdev);
3018 }
3019 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3020}
3021#endif
3022
3023/**
3024 * i40e_vsi_control_tx - Start or stop a VSI's rings
3025 * @vsi: the VSI being configured
3026 * @enable: start or stop the rings
3027 **/
3028static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3029{
3030 struct i40e_pf *pf = vsi->back;
3031 struct i40e_hw *hw = &pf->hw;
3032 int i, j, pf_q;
3033 u32 tx_reg;
3034
3035 pf_q = vsi->base_queue;
3036 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3037 j = 1000;
3038 do {
3039 usleep_range(1000, 2000);
3040 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3041 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
3042 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
3043
fda972f6
MW		 3044 /* Skip if the queue is already in the requested state */
3045 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3046 continue;
3047 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3048 continue;
41c445ff
JB		 3049
3050 /* turn on/off the queue */
c5c9eb9e
SN		 3051 if (enable) {
3052 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
41c445ff
JB		 3053 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
3054 I40E_QTX_ENA_QENA_STAT_MASK;
c5c9eb9e 3055 } else {
41c445ff 3056 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3057 }
41c445ff
JB		 3058
3059 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3060
3061 /* wait for the change to finish */
3062 for (j = 0; j < 10; j++) {
3063 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3064 if (enable) {
3065 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3066 break;
3067 } else {
3068 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3069 break;
3070 }
3071
3072 udelay(10);
3073 }
3074 if (j >= 10) {
3075 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3076 pf_q, (enable ? "en" : "dis"));
3077 return -ETIMEDOUT;
3078 }
3079 }
3080
7134f9ce
JB		 3081 if (hw->revision_id == 0)
3082 mdelay(50);
3083
41c445ff
JB		 3084 return 0;
3085}
3086
3087/**
3088 * i40e_vsi_control_rx - Start or stop a VSI's rings
3089 * @vsi: the VSI being configured
3090 * @enable: start or stop the rings
3091 **/
3092static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3093{
3094 struct i40e_pf *pf = vsi->back;
3095 struct i40e_hw *hw = &pf->hw;
3096 int i, j, pf_q;
3097 u32 rx_reg;
3098
3099 pf_q = vsi->base_queue;
3100 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3101 j = 1000;
3102 do {
3103 usleep_range(1000, 2000);
3104 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3105 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3106 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3107
3108 if (enable) {
3109 /* is STAT set ? */
3110 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3111 continue;
3112 } else {
3113 /* is !STAT set ? */
3114 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3115 continue;
3116 }
3117
3118 /* turn on/off the queue */
3119 if (enable)
3120 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3121 I40E_QRX_ENA_QENA_STAT_MASK;
3122 else
3123 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3124 I40E_QRX_ENA_QENA_STAT_MASK);
3125 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3126
3127 /* wait for the change to finish */
3128 for (j = 0; j < 10; j++) {
3129 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3130
3131 if (enable) {
3132 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3133 break;
3134 } else {
3135 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3136 break;
3137 }
3138
3139 udelay(10);
3140 }
3141 if (j >= 10) {
3142 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3143 pf_q, (enable ? "en" : "dis"));
3144 return -ETIMEDOUT;
3145 }
3146 }
3147
3148 return 0;
3149}
3150
3151/**
3152 * i40e_vsi_control_rings - Start or stop a VSI's rings
3153 * @vsi: the VSI being configured
3154 * @enable: start or stop the rings
3155 **/
fc18eaa0 3156int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3157{
3b867b28 3158 int ret = 0;
41c445ff
JB		 3159
3160 /* do rx first for enable and last for disable */
3161 if (request) {
3162 ret = i40e_vsi_control_rx(vsi, request);
3163 if (ret)
3164 return ret;
3165 ret = i40e_vsi_control_tx(vsi, request);
3166 } else {
3b867b28
ASJ		 3167 /* Ignore return value, we need to shutdown whatever we can */
3168 i40e_vsi_control_tx(vsi, request);
3169 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3170 }
3171
3172 return ret;
3173}
3174
3175/**
3176 * i40e_vsi_free_irq - Free the irq association with the OS
3177 * @vsi: the VSI being configured
3178 **/
3179static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3180{
3181 struct i40e_pf *pf = vsi->back;
3182 struct i40e_hw *hw = &pf->hw;
3183 int base = vsi->base_vector;
3184 u32 val, qp;
3185 int i;
3186
3187 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3188 if (!vsi->q_vectors)
3189 return;
3190
3191 for (i = 0; i < vsi->num_q_vectors; i++) {
3192 u16 vector = i + base;
3193
3194 /* free only the irqs that were actually requested */
78681b1f
SN		 3195 if (!vsi->q_vectors[i] ||
3196 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3197 continue;
3198
3199 /* clear the affinity_mask in the IRQ descriptor */
3200 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3201 NULL);
3202 free_irq(pf->msix_entries[vector].vector,
493fb300 3203 vsi->q_vectors[i]);
41c445ff
JB		 3204
3205 /* Tear down the interrupt queue link list
3206 *
3207 * We know that they come in pairs and always
3208 * the Rx first, then the Tx. To clear the
3209 * link list, stick the EOL value into the
3210 * next_q field of the registers.
3211 */
3212 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3213 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3214 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3215 val |= I40E_QUEUE_END_OF_LIST
3216 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3217 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3218
3219 while (qp != I40E_QUEUE_END_OF_LIST) {
3220 u32 next;
3221
3222 val = rd32(hw, I40E_QINT_RQCTL(qp));
3223
3224 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3225 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3226 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3227 I40E_QINT_RQCTL_INTEVENT_MASK);
3228
3229 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3230 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3231
3232 wr32(hw, I40E_QINT_RQCTL(qp), val);
3233
3234 val = rd32(hw, I40E_QINT_TQCTL(qp));
3235
3236 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3237 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3238
3239 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3240 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3241 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3242 I40E_QINT_TQCTL_INTEVENT_MASK);
3243
3244 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3245 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3246
3247 wr32(hw, I40E_QINT_TQCTL(qp), val);
3248 qp = next;
3249 }
3250 }
3251 } else {
3252 free_irq(pf->pdev->irq, pf);
3253
3254 val = rd32(hw, I40E_PFINT_LNKLST0);
3255 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3256 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3257 val |= I40E_QUEUE_END_OF_LIST
3258 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3259 wr32(hw, I40E_PFINT_LNKLST0, val);
3260
3261 val = rd32(hw, I40E_QINT_RQCTL(qp));
3262 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3263 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3264 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3265 I40E_QINT_RQCTL_INTEVENT_MASK);
3266
3267 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3268 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3269
3270 wr32(hw, I40E_QINT_RQCTL(qp), val);
3271
3272 val = rd32(hw, I40E_QINT_TQCTL(qp));
3273
3274 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3275 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3276 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3277 I40E_QINT_TQCTL_INTEVENT_MASK);
3278
3279 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3280 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3281
3282 wr32(hw, I40E_QINT_TQCTL(qp), val);
3283 }
3284}
3285
493fb300
AD		 3286/**
3287 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3288 * @vsi: the VSI being configured
3289 * @v_idx: Index of vector to be freed
3290 *
3291 * This function frees the memory allocated to the q_vector. In addition if
3292 * NAPI is enabled it will delete any references to the NAPI struct prior
3293 * to freeing the q_vector.
3294 **/
3295static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3296{
3297 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3298 struct i40e_ring *ring;
493fb300
AD		 3299
3300 if (!q_vector)
3301 return;
3302
3303 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3304 i40e_for_each_ring(ring, q_vector->tx)
3305 ring->q_vector = NULL;
3306
3307 i40e_for_each_ring(ring, q_vector->rx)
3308 ring->q_vector = NULL;
493fb300
AD		 3309
3310 /* only VSI w/ an associated netdev is set up w/ NAPI */
3311 if (vsi->netdev)
3312 netif_napi_del(&q_vector->napi);
3313
3314 vsi->q_vectors[v_idx] = NULL;
3315
3316 kfree_rcu(q_vector, rcu);
3317}
3318
41c445ff
JB		 3319/**
3320 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3321 * @vsi: the VSI being un-configured
3322 *
3323 * This frees the memory allocated to the q_vectors and
3324 * deletes references to the NAPI struct.
3325 **/
3326static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3327{
3328 int v_idx;
3329
493fb300
AD		 3330 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3331 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3332}
3333
3334/**
3335 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3336 * @pf: board private structure
3337 **/
3338static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3339{
3340 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3341 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3342 pci_disable_msix(pf->pdev);
3343 kfree(pf->msix_entries);
3344 pf->msix_entries = NULL;
3345 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3346 pci_disable_msi(pf->pdev);
3347 }
3348 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3349}
3350
3351/**
3352 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3353 * @pf: board private structure
3354 *
3355 * We go through and clear interrupt specific resources and reset the structure
3356 * to pre-load conditions
3357 **/
3358static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3359{
3360 int i;
3361
3362 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3363 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3364 if (pf->vsi[i])
3365 i40e_vsi_free_q_vectors(pf->vsi[i]);
3366 i40e_reset_interrupt_capability(pf);
3367}
3368
3369/**
3370 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3371 * @vsi: the VSI being configured
3372 **/
3373static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3374{
3375 int q_idx;
3376
3377 if (!vsi->netdev)
3378 return;
3379
3380 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3381 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3382}
3383
3384/**
3385 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3386 * @vsi: the VSI being configured
3387 **/
3388static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3389{
3390 int q_idx;
3391
3392 if (!vsi->netdev)
3393 return;
3394
3395 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3396 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3397}
3398
3399/**
3400 * i40e_quiesce_vsi - Pause a given VSI
3401 * @vsi: the VSI being paused
3402 **/
3403static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3404{
3405 if (test_bit(__I40E_DOWN, &vsi->state))
3406 return;
3407
3408 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3409 if (vsi->netdev && netif_running(vsi->netdev)) {
3410 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3411 } else {
3412 set_bit(__I40E_DOWN, &vsi->state);
3413 i40e_down(vsi);
3414 }
3415}
3416
3417/**
3418 * i40e_unquiesce_vsi - Resume a given VSI
3419 * @vsi: the VSI being resumed
3420 **/
3421static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3422{
3423 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3424 return;
3425
3426 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3427 if (vsi->netdev && netif_running(vsi->netdev))
3428 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3429 else
3430 i40e_up(vsi); /* this clears the DOWN bit */
3431}
3432
3433/**
3434 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3435 * @pf: the PF
3436 **/
3437static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3438{
3439 int v;
3440
3441 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3442 if (pf->vsi[v])
3443 i40e_quiesce_vsi(pf->vsi[v]);
3444 }
3445}
3446
3447/**
3448 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3449 * @pf: the PF
3450 **/
3451static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3452{
3453 int v;
3454
3455 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3456 if (pf->vsi[v])
3457 i40e_unquiesce_vsi(pf->vsi[v]);
3458 }
3459}
3460
3461/**
3462 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3463 * @dcbcfg: the corresponding DCBx configuration structure
3464 *
3465 * Return the number of TCs from given DCBx configuration
3466 **/
3467static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3468{
078b5876
JB		 3469 u8 num_tc = 0;
3470 int i;
41c445ff
JB		 3471
3472 /* Scan the ETS Config Priority Table to find
3473 * traffic class enabled for a given priority
3474 * and use the traffic class index to get the
3475 * number of traffic classes enabled
3476 */
3477 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3478 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3479 num_tc = dcbcfg->etscfg.prioritytable[i];
3480 }
3481
3482 /* Traffic class index starts from zero so
3483 * increment to return the actual count
3484 */
078b5876 3485 return num_tc + 1;
41c445ff
JB		 3486}
3487
3488/**
3489 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3490 * @dcbcfg: the corresponding DCBx configuration structure
3491 *
3492 * Query the current DCB configuration and return the number of
3493 * traffic classes enabled from the given DCBX config
3494 **/
3495static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3496{
3497 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3498 u8 enabled_tc = 1;
3499 u8 i;
3500
3501 for (i = 0; i < num_tc; i++)
3502 enabled_tc |= 1 << i;
3503
3504 return enabled_tc;
3505}
3506
3507/**
3508 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3509 * @pf: PF being queried
3510 *
3511 * Return number of traffic classes enabled for the given PF
3512 **/
3513static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3514{
3515 struct i40e_hw *hw = &pf->hw;
3516 u8 i, enabled_tc;
3517 u8 num_tc = 0;
3518 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3519
3520 /* If DCB is not enabled then always in single TC */
3521 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3522 return 1;
3523
3524 /* MFP mode return count of enabled TCs for this PF */
3525 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3526 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3527 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3528 if (enabled_tc & (1 << i))
3529 num_tc++;
3530 }
3531 return num_tc;
3532 }
3533
3534 /* SFP mode will be enabled for all TCs on port */
3535 return i40e_dcb_get_num_tc(dcbcfg);
3536}
3537
3538/**
3539 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3540 * @pf: PF being queried
3541 *
3542 * Return a bitmap for first enabled traffic class for this PF.
3543 **/
3544static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3545{
3546 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3547 u8 i = 0;
3548
3549 if (!enabled_tc)
3550 return 0x1; /* TC0 */
3551
3552 /* Find the first enabled TC */
3553 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3554 if (enabled_tc & (1 << i))
3555 break;
3556 }
3557
3558 return 1 << i;
3559}
3560
3561/**
3562 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3563 * @pf: PF being queried
3564 *
3565 * Return a bitmap for enabled traffic classes for this PF.
3566 **/
3567static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3568{
3569 /* If DCB is not enabled for this PF then just return default TC */
3570 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3571 return i40e_pf_get_default_tc(pf);
3572
3573 /* MFP mode will have enabled TCs set by FW */
3574 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3575 return pf->hw.func_caps.enabled_tcmap;
3576
3577 /* SFP mode we want PF to be enabled for all TCs */
3578 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3579}
3580
3581/**
3582 * i40e_vsi_get_bw_info - Query VSI BW Information
3583 * @vsi: the VSI being queried
3584 *
3585 * Returns 0 on success, negative value on failure
3586 **/
3587static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3588{
3589 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3590 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3591 struct i40e_pf *pf = vsi->back;
3592 struct i40e_hw *hw = &pf->hw;
dcae29be 3593 i40e_status aq_ret;
41c445ff 3594 u32 tc_bw_max;
41c445ff
JB		 3595 int i;
3596
3597 /* Get the VSI level BW configuration */
dcae29be
JB		 3598 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3599 if (aq_ret) {
41c445ff
JB		 3600 dev_info(&pf->pdev->dev,
3601 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3602 aq_ret, pf->hw.aq.asq_last_status);
3603 return -EINVAL;
41c445ff
JB		 3604 }
3605
3606 /* Get the VSI level BW configuration per TC */
dcae29be 3607 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3608 NULL);
dcae29be 3609 if (aq_ret) {
41c445ff
JB		 3610 dev_info(&pf->pdev->dev,
3611 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3612 aq_ret, pf->hw.aq.asq_last_status);
3613 return -EINVAL;
41c445ff
JB		 3614 }
3615
3616 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3617 dev_info(&pf->pdev->dev,
3618 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3619 bw_config.tc_valid_bits,
3620 bw_ets_config.tc_valid_bits);
3621 /* Still continuing */
3622 }
3623
3624 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3625 vsi->bw_max_quanta = bw_config.max_bw;
3626 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3627 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3628 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3629 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3630 vsi->bw_ets_limit_credits[i] =
3631 le16_to_cpu(bw_ets_config.credits[i]);
3632 /* 3 bits out of 4 for each TC */
3633 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3634 }
078b5876 3635
dcae29be 3636 return 0;
41c445ff
JB		 3637}
3638
3639/**
3640 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3641 * @vsi: the VSI being configured
3642 * @enabled_tc: TC bitmap
3643 * @bw_credits: BW shared credits per TC
3644 *
3645 * Returns 0 on success, negative value on failure
3646 **/
dcae29be 3647static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3648 u8 *bw_share)
3649{
3650 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3651 i40e_status aq_ret;
3652 int i;
41c445ff
JB		 3653
3654 bw_data.tc_valid_bits = enabled_tc;
3655 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3656 bw_data.tc_bw_credits[i] = bw_share[i];
3657
dcae29be
JB		 3658 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3659 NULL);
3660 if (aq_ret) {
41c445ff
JB		 3661 dev_info(&vsi->back->pdev->dev,
3662 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3663 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3664 return -EINVAL;
41c445ff
JB		 3665 }
3666
3667 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3668 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3669
dcae29be 3670 return 0;
41c445ff
JB		 3671}
3672
3673/**
3674 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3675 * @vsi: the VSI being configured
3676 * @enabled_tc: TC map to be enabled
3677 *
3678 **/
3679static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3680{
3681 struct net_device *netdev = vsi->netdev;
3682 struct i40e_pf *pf = vsi->back;
3683 struct i40e_hw *hw = &pf->hw;
3684 u8 netdev_tc = 0;
3685 int i;
3686 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3687
3688 if (!netdev)
3689 return;
3690
3691 if (!enabled_tc) {
3692 netdev_reset_tc(netdev);
3693 return;
3694 }
3695
3696 /* Set up actual enabled TCs on the VSI */
3697 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3698 return;
3699
3700 /* set per TC queues for the VSI */
3701 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3702 /* Only set TC queues for enabled tcs
3703 *
3704 * e.g. For a VSI that has TC0 and TC3 enabled the
3705 * enabled_tc bitmap would be 0x00001001; the driver
3706 * will set the numtc for netdev as 2 that will be
3707 * referenced by the netdev layer as TC 0 and 1.
3708 */
3709 if (vsi->tc_config.enabled_tc & (1 << i))
3710 netdev_set_tc_queue(netdev,
3711 vsi->tc_config.tc_info[i].netdev_tc,
3712 vsi->tc_config.tc_info[i].qcount,
3713 vsi->tc_config.tc_info[i].qoffset);
3714 }
3715
3716 /* Assign UP2TC map for the VSI */
3717 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3718 /* Get the actual TC# for the UP */
3719 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3720 /* Get the mapped netdev TC# for the UP */
3721 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3722 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3723 }
3724}
3725
3726/**
3727 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3728 * @vsi: the VSI being configured
3729 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3730 **/
3731static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3732 struct i40e_vsi_context *ctxt)
3733{
3734 /* copy just the sections touched not the entire info
3735 * since not all sections are valid as returned by
3736 * update vsi params
3737 */
3738 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3739 memcpy(&vsi->info.queue_mapping,
3740 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3741 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3742 sizeof(vsi->info.tc_mapping));
3743}
3744
3745/**
3746 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3747 * @vsi: VSI to be configured
3748 * @enabled_tc: TC bitmap
3749 *
3750 * This configures a particular VSI for TCs that are mapped to the
3751 * given TC bitmap. It uses default bandwidth share for TCs across
3752 * VSIs to configure TC for a particular VSI.
3753 *
3754 * NOTE:
3755 * It is expected that the VSI queues have been quisced before calling
3756 * this function.
3757 **/
3758static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3759{
3760 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3761 struct i40e_vsi_context ctxt;
3762 int ret = 0;
3763 int i;
3764
3765 /* Check if enabled_tc is same as existing or new TCs */
3766 if (vsi->tc_config.enabled_tc == enabled_tc)
3767 return ret;
3768
3769 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3770 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3771 if (enabled_tc & (1 << i))
3772 bw_share[i] = 1;
3773 }
3774
3775 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3776 if (ret) {
3777 dev_info(&vsi->back->pdev->dev,
3778 "Failed configuring TC map %d for VSI %d\n",
3779 enabled_tc, vsi->seid);
3780 goto out;
3781 }
3782
3783 /* Update Queue Pairs Mapping for currently enabled UPs */
3784 ctxt.seid = vsi->seid;
3785 ctxt.pf_num = vsi->back->hw.pf_id;
3786 ctxt.vf_num = 0;
3787 ctxt.uplink_seid = vsi->uplink_seid;
3788 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3789 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3790
3791 /* Update the VSI after updating the VSI queue-mapping information */
3792 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3793 if (ret) {
3794 dev_info(&vsi->back->pdev->dev,
3795 "update vsi failed, aq_err=%d\n",
3796 vsi->back->hw.aq.asq_last_status);
3797 goto out;
3798 }
3799 /* update the local VSI info with updated queue map */
3800 i40e_vsi_update_queue_map(vsi, &ctxt);
3801 vsi->info.valid_sections = 0;
3802
3803 /* Update current VSI BW information */
3804 ret = i40e_vsi_get_bw_info(vsi);
3805 if (ret) {
3806 dev_info(&vsi->back->pdev->dev,
3807 "Failed updating vsi bw info, aq_err=%d\n",
3808 vsi->back->hw.aq.asq_last_status);
3809 goto out;
3810 }
3811
3812 /* Update the netdev TC setup */
3813 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3814out:
3815 return ret;
3816}
3817
3818/**
3819 * i40e_up_complete - Finish the last steps of bringing up a connection
3820 * @vsi: the VSI being configured
3821 **/
3822static int i40e_up_complete(struct i40e_vsi *vsi)
3823{
3824 struct i40e_pf *pf = vsi->back;
3825 int err;
3826
3827 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3828 i40e_vsi_configure_msix(vsi);
3829 else
3830 i40e_configure_msi_and_legacy(vsi);
3831
3832 /* start rings */
3833 err = i40e_vsi_control_rings(vsi, true);
3834 if (err)
3835 return err;
3836
3837 clear_bit(__I40E_DOWN, &vsi->state);
3838 i40e_napi_enable_all(vsi);
3839 i40e_vsi_enable_irq(vsi);
3840
3841 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
3842 (vsi->netdev)) {
6d779b41 3843 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 3844 netif_tx_start_all_queues(vsi->netdev);
3845 netif_carrier_on(vsi->netdev);
6d779b41
AS		 3846 } else if (vsi->netdev) {
3847 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 3848 }
3849 i40e_service_event_schedule(pf);
3850
3851 return 0;
3852}
3853
3854/**
3855 * i40e_vsi_reinit_locked - Reset the VSI
3856 * @vsi: the VSI being configured
3857 *
3858 * Rebuild the ring structs after some configuration
3859 * has changed, e.g. MTU size.
3860 **/
3861static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
3862{
3863 struct i40e_pf *pf = vsi->back;
3864
3865 WARN_ON(in_interrupt());
3866 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
3867 usleep_range(1000, 2000);
3868 i40e_down(vsi);
3869
3870 /* Give a VF some time to respond to the reset. The
3871 * two second wait is based upon the watchdog cycle in
3872 * the VF driver.
3873 */
3874 if (vsi->type == I40E_VSI_SRIOV)
3875 msleep(2000);
3876 i40e_up(vsi);
3877 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
3878}
3879
3880/**
3881 * i40e_up - Bring the connection back up after being down
3882 * @vsi: the VSI being configured
3883 **/
3884int i40e_up(struct i40e_vsi *vsi)
3885{
3886 int err;
3887
3888 err = i40e_vsi_configure(vsi);
3889 if (!err)
3890 err = i40e_up_complete(vsi);
3891
3892 return err;
3893}
3894
3895/**
3896 * i40e_down - Shutdown the connection processing
3897 * @vsi: the VSI being stopped
3898 **/
3899void i40e_down(struct i40e_vsi *vsi)
3900{
3901 int i;
3902
3903 /* It is assumed that the caller of this function
3904 * sets the vsi->state __I40E_DOWN bit.
3905 */
3906 if (vsi->netdev) {
3907 netif_carrier_off(vsi->netdev);
3908 netif_tx_disable(vsi->netdev);
3909 }
3910 i40e_vsi_disable_irq(vsi);
3911 i40e_vsi_control_rings(vsi, false);
3912 i40e_napi_disable_all(vsi);
3913
3914 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3915 i40e_clean_tx_ring(vsi->tx_rings[i]);
3916 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3917 }
3918}
3919
3920/**
3921 * i40e_setup_tc - configure multiple traffic classes
3922 * @netdev: net device to configure
3923 * @tc: number of traffic classes to enable
3924 **/
3925static int i40e_setup_tc(struct net_device *netdev, u8 tc)
3926{
3927 struct i40e_netdev_priv *np = netdev_priv(netdev);
3928 struct i40e_vsi *vsi = np->vsi;
3929 struct i40e_pf *pf = vsi->back;
3930 u8 enabled_tc = 0;
3931 int ret = -EINVAL;
3932 int i;
3933
3934 /* Check if DCB enabled to continue */
3935 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
3936 netdev_info(netdev, "DCB is not enabled for adapter\n");
3937 goto exit;
3938 }
3939
3940 /* Check if MFP enabled */
3941 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3942 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
3943 goto exit;
3944 }
3945
3946 /* Check whether tc count is within enabled limit */
3947 if (tc > i40e_pf_get_num_tc(pf)) {
3948 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
3949 goto exit;
3950 }
3951
3952 /* Generate TC map for number of tc requested */
3953 for (i = 0; i < tc; i++)
3954 enabled_tc |= (1 << i);
3955
3956 /* Requesting same TC configuration as already enabled */
3957 if (enabled_tc == vsi->tc_config.enabled_tc)
3958 return 0;
3959
3960 /* Quiesce VSI queues */
3961 i40e_quiesce_vsi(vsi);
3962
3963 /* Configure VSI for enabled TCs */
3964 ret = i40e_vsi_config_tc(vsi, enabled_tc);
3965 if (ret) {
3966 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
3967 vsi->seid);
3968 goto exit;
3969 }
3970
3971 /* Unquiesce VSI */
3972 i40e_unquiesce_vsi(vsi);
3973
3974exit:
3975 return ret;
3976}
3977
3978/**
3979 * i40e_open - Called when a network interface is made active
3980 * @netdev: network interface device structure
3981 *
3982 * The open entry point is called when a network interface is made
3983 * active by the system (IFF_UP). At this point all resources needed
3984 * for transmit and receive operations are allocated, the interrupt
3985 * handler is registered with the OS, the netdev watchdog subtask is
3986 * enabled, and the stack is notified that the interface is ready.
3987 *
3988 * Returns 0 on success, negative value on failure
3989 **/
3990static int i40e_open(struct net_device *netdev)
3991{
3992 struct i40e_netdev_priv *np = netdev_priv(netdev);
3993 struct i40e_vsi *vsi = np->vsi;
3994 struct i40e_pf *pf = vsi->back;
3995 char int_name[IFNAMSIZ];
3996 int err;
3997
3998 /* disallow open during test */
3999 if (test_bit(__I40E_TESTING, &pf->state))
4000 return -EBUSY;
4001
4002 netif_carrier_off(netdev);
4003
4004 /* allocate descriptors */
4005 err = i40e_vsi_setup_tx_resources(vsi);
4006 if (err)
4007 goto err_setup_tx;
4008 err = i40e_vsi_setup_rx_resources(vsi);
4009 if (err)
4010 goto err_setup_rx;
4011
4012 err = i40e_vsi_configure(vsi);
4013 if (err)
4014 goto err_setup_rx;
4015
4016 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4017 dev_driver_string(&pf->pdev->dev), netdev->name);
4018 err = i40e_vsi_request_irq(vsi, int_name);
4019 if (err)
4020 goto err_setup_rx;
4021
25946ddb 4022 /* Notify the stack of the actual queue counts. */
d7397644 4023 err = netif_set_real_num_tx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4024 if (err)
4025 goto err_set_queues;
4026
d7397644 4027 err = netif_set_real_num_rx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4028 if (err)
4029 goto err_set_queues;
4030
41c445ff
JB		 4031 err = i40e_up_complete(vsi);
4032 if (err)
4033 goto err_up_complete;
4034
a1c9a9d9
JK		 4035#ifdef CONFIG_I40E_VXLAN
4036 vxlan_get_rx_port(netdev);
4037#endif
41c445ff
JB		 4038
4039 return 0;
4040
4041err_up_complete:
4042 i40e_down(vsi);
25946ddb 4043err_set_queues:
41c445ff
JB		 4044 i40e_vsi_free_irq(vsi);
4045err_setup_rx:
4046 i40e_vsi_free_rx_resources(vsi);
4047err_setup_tx:
4048 i40e_vsi_free_tx_resources(vsi);
4049 if (vsi == pf->vsi[pf->lan_vsi])
4050 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4051
4052 return err;
4053}
4054
4055/**
4056 * i40e_close - Disables a network interface
4057 * @netdev: network interface device structure
4058 *
4059 * The close entry point is called when an interface is de-activated
4060 * by the OS. The hardware is still under the driver's control, but
4061 * this netdev interface is disabled.
4062 *
4063 * Returns 0, this is not allowed to fail
4064 **/
4065static int i40e_close(struct net_device *netdev)
4066{
4067 struct i40e_netdev_priv *np = netdev_priv(netdev);
4068 struct i40e_vsi *vsi = np->vsi;
4069
4070 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4071 return 0;
4072
4073 i40e_down(vsi);
4074 i40e_vsi_free_irq(vsi);
4075
4076 i40e_vsi_free_tx_resources(vsi);
4077 i40e_vsi_free_rx_resources(vsi);
4078
4079 return 0;
4080}
4081
4082/**
4083 * i40e_do_reset - Start a PF or Core Reset sequence
4084 * @pf: board private structure
4085 * @reset_flags: which reset is requested
4086 *
4087 * The essential difference in resets is that the PF Reset
4088 * doesn't clear the packet buffers, doesn't reset the PE
4089 * firmware, and doesn't bother the other PFs on the chip.
4090 **/
4091void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4092{
4093 u32 val;
4094
4095 WARN_ON(in_interrupt());
4096
4097 /* do the biggest reset indicated */
4098 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4099
4100 /* Request a Global Reset
4101 *
4102 * This will start the chip's countdown to the actual full
4103 * chip reset event, and a warning interrupt to be sent
4104 * to all PFs, including the requestor. Our handler
4105 * for the warning interrupt will deal with the shutdown
4106 * and recovery of the switch setup.
4107 */
4108 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4109 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4110 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4111 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4112
4113 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4114
4115 /* Request a Core Reset
4116 *
4117 * Same as Global Reset, except does *not* include the MAC/PHY
4118 */
4119 dev_info(&pf->pdev->dev, "CoreR requested\n");
4120 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4121 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4122 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4123 i40e_flush(&pf->hw);
4124
7823fe34
SN		 4125 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4126
4127 /* Request a Firmware Reset
4128 *
4129 * Same as Global reset, plus restarting the
4130 * embedded firmware engine.
4131 */
4132 /* enable EMP Reset */
4133 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4134 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4135 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4136
4137 /* force the reset */
4138 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4139 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4140 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4141 i40e_flush(&pf->hw);
4142
41c445ff
JB		 4143 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4144
4145 /* Request a PF Reset
4146 *
4147 * Resets only the PF-specific registers
4148 *
4149 * This goes directly to the tear-down and rebuild of
4150 * the switch, since we need to do all the recovery as
4151 * for the Core Reset.
4152 */
4153 dev_info(&pf->pdev->dev, "PFR requested\n");
4154 i40e_handle_reset_warning(pf);
4155
4156 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4157 int v;
4158
4159 /* Find the VSI(s) that requested a re-init */
4160 dev_info(&pf->pdev->dev,
4161 "VSI reinit requested\n");
4162 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4163 struct i40e_vsi *vsi = pf->vsi[v];
4164 if (vsi != NULL &&
4165 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4166 i40e_vsi_reinit_locked(pf->vsi[v]);
4167 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4168 }
4169 }
4170
4171 /* no further action needed, so return now */
4172 return;
4173 } else {
4174 dev_info(&pf->pdev->dev,
4175 "bad reset request 0x%08x\n", reset_flags);
4176 return;
4177 }
4178}
4179
23326186
ASJ		 4180/**
4181 * i40e_do_reset_safe - Protected reset path for userland calls.
4182 * @pf: board private structure
4183 * @reset_flags: which reset is requested
4184 *
4185 **/
4186void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4187{
4188 rtnl_lock();
4189 i40e_do_reset(pf, reset_flags);
4190 rtnl_unlock();
4191}
4192
41c445ff
JB		 4193/**
4194 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4195 * @pf: board private structure
4196 * @e: event info posted on ARQ
4197 *
4198 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4199 * and VF queues
4200 **/
4201static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4202 struct i40e_arq_event_info *e)
4203{
4204 struct i40e_aqc_lan_overflow *data =
4205 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4206 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4207 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4208 struct i40e_hw *hw = &pf->hw;
4209 struct i40e_vf *vf;
4210 u16 vf_id;
4211
4212 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4213 __func__, queue, qtx_ctl);
4214
4215 /* Queue belongs to VF, find the VF and issue VF reset */
4216 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4217 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4218 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4219 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4220 vf_id -= hw->func_caps.vf_base_id;
4221 vf = &pf->vf[vf_id];
4222 i40e_vc_notify_vf_reset(vf);
4223 /* Allow VF to process pending reset notification */
4224 msleep(20);
4225 i40e_reset_vf(vf, false);
4226 }
4227}
4228
4229/**
4230 * i40e_service_event_complete - Finish up the service event
4231 * @pf: board private structure
4232 **/
4233static void i40e_service_event_complete(struct i40e_pf *pf)
4234{
4235 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4236
4237 /* flush memory to make sure state is correct before next watchog */
4238 smp_mb__before_clear_bit();
4239 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4240}
4241
4242/**
4243 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4244 * @pf: board private structure
4245 **/
4246static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4247{
4248 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4249 return;
4250
4251 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4252
4253 /* if interface is down do nothing */
4254 if (test_bit(__I40E_DOWN, &pf->state))
4255 return;
4256}
4257
4258/**
4259 * i40e_vsi_link_event - notify VSI of a link event
4260 * @vsi: vsi to be notified
4261 * @link_up: link up or down
4262 **/
4263static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4264{
4265 if (!vsi)
4266 return;
4267
4268 switch (vsi->type) {
4269 case I40E_VSI_MAIN:
4270 if (!vsi->netdev || !vsi->netdev_registered)
4271 break;
4272
4273 if (link_up) {
4274 netif_carrier_on(vsi->netdev);
4275 netif_tx_wake_all_queues(vsi->netdev);
4276 } else {
4277 netif_carrier_off(vsi->netdev);
4278 netif_tx_stop_all_queues(vsi->netdev);
4279 }
4280 break;
4281
4282 case I40E_VSI_SRIOV:
4283 break;
4284
4285 case I40E_VSI_VMDQ2:
4286 case I40E_VSI_CTRL:
4287 case I40E_VSI_MIRROR:
4288 default:
4289 /* there is no notification for other VSIs */
4290 break;
4291 }
4292}
4293
4294/**
4295 * i40e_veb_link_event - notify elements on the veb of a link event
4296 * @veb: veb to be notified
4297 * @link_up: link up or down
4298 **/
4299static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4300{
4301 struct i40e_pf *pf;
4302 int i;
4303
4304 if (!veb || !veb->pf)
4305 return;
4306 pf = veb->pf;
4307
4308 /* depth first... */
4309 for (i = 0; i < I40E_MAX_VEB; i++)
4310 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4311 i40e_veb_link_event(pf->veb[i], link_up);
4312
4313 /* ... now the local VSIs */
4314 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4315 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4316 i40e_vsi_link_event(pf->vsi[i], link_up);
4317}
4318
4319/**
4320 * i40e_link_event - Update netif_carrier status
4321 * @pf: board private structure
4322 **/
4323static void i40e_link_event(struct i40e_pf *pf)
4324{
4325 bool new_link, old_link;
4326
4327 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4328 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4329
4330 if (new_link == old_link)
4331 return;
4332
6d779b41
AS		 4333 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4334 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4335 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4336
4337 /* Notify the base of the switch tree connected to
4338 * the link. Floating VEBs are not notified.
4339 */
4340 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4341 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4342 else
4343 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4344
4345 if (pf->vf)
4346 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4347
4348 if (pf->flags & I40E_FLAG_PTP)
4349 i40e_ptp_set_increment(pf);
41c445ff
JB		 4350}
4351
4352/**
4353 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4354 * @pf: board private structure
4355 *
4356 * Set the per-queue flags to request a check for stuck queues in the irq
4357 * clean functions, then force interrupts to be sure the irq clean is called.
4358 **/
4359static void i40e_check_hang_subtask(struct i40e_pf *pf)
4360{
4361 int i, v;
4362
4363 /* If we're down or resetting, just bail */
4364 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4365 return;
4366
4367 /* for each VSI/netdev
4368 * for each Tx queue
4369 * set the check flag
4370 * for each q_vector
4371 * force an interrupt
4372 */
4373 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4374 struct i40e_vsi *vsi = pf->vsi[v];
4375 int armed = 0;
4376
4377 if (!pf->vsi[v] ||
4378 test_bit(__I40E_DOWN, &vsi->state) ||
4379 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4380 continue;
4381
4382 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4383 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4384 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4385 &vsi->tx_rings[i]->state))
41c445ff
JB		 4386 armed++;
4387 }
4388
4389 if (armed) {
4390 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4391 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4392 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4393 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4394 } else {
4395 u16 vec = vsi->base_vector - 1;
4396 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4397 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4398 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4399 wr32(&vsi->back->hw,
4400 I40E_PFINT_DYN_CTLN(vec), val);
4401 }
4402 i40e_flush(&vsi->back->hw);
4403 }
4404 }
4405}
4406
4407/**
4408 * i40e_watchdog_subtask - Check and bring link up
4409 * @pf: board private structure
4410 **/
4411static void i40e_watchdog_subtask(struct i40e_pf *pf)
4412{
4413 int i;
4414
4415 /* if interface is down do nothing */
4416 if (test_bit(__I40E_DOWN, &pf->state) ||
4417 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4418 return;
4419
4420 /* Update the stats for active netdevs so the network stack
4421 * can look at updated numbers whenever it cares to
4422 */
4423 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4424 if (pf->vsi[i] && pf->vsi[i]->netdev)
4425 i40e_update_stats(pf->vsi[i]);
4426
4427 /* Update the stats for the active switching components */
4428 for (i = 0; i < I40E_MAX_VEB; i++)
4429 if (pf->veb[i])
4430 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4431
4432 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4433}
4434
4435/**
4436 * i40e_reset_subtask - Set up for resetting the device and driver
4437 * @pf: board private structure
4438 **/
4439static void i40e_reset_subtask(struct i40e_pf *pf)
4440{
4441 u32 reset_flags = 0;
4442
23326186 4443 rtnl_lock();
41c445ff
JB		 4444 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4445 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4446 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4447 }
4448 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4449 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4450 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4451 }
4452 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4453 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4454 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4455 }
4456 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4457 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4458 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4459 }
4460
4461 /* If there's a recovery already waiting, it takes
4462 * precedence before starting a new reset sequence.
4463 */
4464 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4465 i40e_handle_reset_warning(pf);
23326186 4466 goto unlock;
41c445ff
JB		 4467 }
4468
4469 /* If we're already down or resetting, just bail */
4470 if (reset_flags &&
4471 !test_bit(__I40E_DOWN, &pf->state) &&
4472 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4473 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4474
4475unlock:
4476 rtnl_unlock();
41c445ff
JB		 4477}
4478
4479/**
4480 * i40e_handle_link_event - Handle link event
4481 * @pf: board private structure
4482 * @e: event info posted on ARQ
4483 **/
4484static void i40e_handle_link_event(struct i40e_pf *pf,
4485 struct i40e_arq_event_info *e)
4486{
4487 struct i40e_hw *hw = &pf->hw;
4488 struct i40e_aqc_get_link_status *status =
4489 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4490 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4491
4492 /* save off old link status information */
4493 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4494 sizeof(pf->hw.phy.link_info_old));
4495
4496 /* update link status */
4497 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4498 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4499 hw_link_info->link_info = status->link_info;
4500 hw_link_info->an_info = status->an_info;
4501 hw_link_info->ext_info = status->ext_info;
4502 hw_link_info->lse_enable =
4503 le16_to_cpu(status->command_flags) &
4504 I40E_AQ_LSE_ENABLE;
4505
4506 /* process the event */
4507 i40e_link_event(pf);
4508
4509 /* Do a new status request to re-enable LSE reporting
4510 * and load new status information into the hw struct,
4511 * then see if the status changed while processing the
4512 * initial event.
4513 */
4514 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4515 i40e_link_event(pf);
4516}
4517
4518/**
4519 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4520 * @pf: board private structure
4521 **/
4522static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4523{
4524 struct i40e_arq_event_info event;
4525 struct i40e_hw *hw = &pf->hw;
4526 u16 pending, i = 0;
4527 i40e_status ret;
4528 u16 opcode;
4529 u32 val;
4530
4531 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4532 return;
4533
3197ce22 4534 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 4535 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4536 if (!event.msg_buf)
4537 return;
4538
4539 do {
2f019123 4540 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 4541 ret = i40e_clean_arq_element(hw, &event, &pending);
4542 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4543 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4544 break;
4545 } else if (ret) {
4546 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4547 break;
4548 }
4549
4550 opcode = le16_to_cpu(event.desc.opcode);
4551 switch (opcode) {
4552
4553 case i40e_aqc_opc_get_link_status:
4554 i40e_handle_link_event(pf, &event);
4555 break;
4556 case i40e_aqc_opc_send_msg_to_pf:
4557 ret = i40e_vc_process_vf_msg(pf,
4558 le16_to_cpu(event.desc.retval),
4559 le32_to_cpu(event.desc.cookie_high),
4560 le32_to_cpu(event.desc.cookie_low),
4561 event.msg_buf,
4562 event.msg_size);
4563 break;
4564 case i40e_aqc_opc_lldp_update_mib:
4565 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4566 break;
4567 case i40e_aqc_opc_event_lan_overflow:
4568 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4569 i40e_handle_lan_overflow_event(pf, &event);
4570 break;
0467bc91
SN		 4571 case i40e_aqc_opc_send_msg_to_peer:
4572 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
4573 break;
41c445ff
JB		 4574 default:
4575 dev_info(&pf->pdev->dev,
0467bc91
SN		 4576 "ARQ Error: Unknown event 0x%04x received\n",
4577 opcode);
41c445ff
JB		 4578 break;
4579 }
4580 } while (pending && (i++ < pf->adminq_work_limit));
4581
4582 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4583 /* re-enable Admin queue interrupt cause */
4584 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4585 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4586 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4587 i40e_flush(hw);
4588
4589 kfree(event.msg_buf);
4590}
4591
4592/**
4593 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4594 * @veb: pointer to the VEB instance
4595 *
4596 * This is a recursive function that first builds the attached VSIs then
4597 * recurses in to build the next layer of VEB. We track the connections
4598 * through our own index numbers because the seid's from the HW could
4599 * change across the reset.
4600 **/
4601static int i40e_reconstitute_veb(struct i40e_veb *veb)
4602{
4603 struct i40e_vsi *ctl_vsi = NULL;
4604 struct i40e_pf *pf = veb->pf;
4605 int v, veb_idx;
4606 int ret;
4607
4608 /* build VSI that owns this VEB, temporarily attached to base VEB */
4609 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4610 if (pf->vsi[v] &&
4611 pf->vsi[v]->veb_idx == veb->idx &&
4612 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4613 ctl_vsi = pf->vsi[v];
4614 break;
4615 }
4616 }
4617 if (!ctl_vsi) {
4618 dev_info(&pf->pdev->dev,
4619 "missing owner VSI for veb_idx %d\n", veb->idx);
4620 ret = -ENOENT;
4621 goto end_reconstitute;
4622 }
4623 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4624 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4625 ret = i40e_add_vsi(ctl_vsi);
4626 if (ret) {
4627 dev_info(&pf->pdev->dev,
4628 "rebuild of owner VSI failed: %d\n", ret);
4629 goto end_reconstitute;
4630 }
4631 i40e_vsi_reset_stats(ctl_vsi);
4632
4633 /* create the VEB in the switch and move the VSI onto the VEB */
4634 ret = i40e_add_veb(veb, ctl_vsi);
4635 if (ret)
4636 goto end_reconstitute;
4637
4638 /* create the remaining VSIs attached to this VEB */
4639 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4640 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4641 continue;
4642
4643 if (pf->vsi[v]->veb_idx == veb->idx) {
4644 struct i40e_vsi *vsi = pf->vsi[v];
4645 vsi->uplink_seid = veb->seid;
4646 ret = i40e_add_vsi(vsi);
4647 if (ret) {
4648 dev_info(&pf->pdev->dev,
4649 "rebuild of vsi_idx %d failed: %d\n",
4650 v, ret);
4651 goto end_reconstitute;
4652 }
4653 i40e_vsi_reset_stats(vsi);
4654 }
4655 }
4656
4657 /* create any VEBs attached to this VEB - RECURSION */
4658 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
4659 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
4660 pf->veb[veb_idx]->uplink_seid = veb->seid;
4661 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
4662 if (ret)
4663 break;
4664 }
4665 }
4666
4667end_reconstitute:
4668 return ret;
4669}
4670
4671/**
4672 * i40e_get_capabilities - get info about the HW
4673 * @pf: the PF struct
4674 **/
4675static int i40e_get_capabilities(struct i40e_pf *pf)
4676{
4677 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
4678 u16 data_size;
4679 int buf_len;
4680 int err;
4681
4682 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
4683 do {
4684 cap_buf = kzalloc(buf_len, GFP_KERNEL);
4685 if (!cap_buf)
4686 return -ENOMEM;
4687
4688 /* this loads the data into the hw struct for us */
4689 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
4690 &data_size,
4691 i40e_aqc_opc_list_func_capabilities,
4692 NULL);
4693 /* data loaded, buffer no longer needed */
4694 kfree(cap_buf);
4695
4696 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
4697 /* retry with a larger buffer */
4698 buf_len = data_size;
4699 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
4700 dev_info(&pf->pdev->dev,
4701 "capability discovery failed: aq=%d\n",
4702 pf->hw.aq.asq_last_status);
4703 return -ENODEV;
4704 }
4705 } while (err);
4706
2050bc65 4707 if (pf->hw.revision_id == 0 && (pf->flags & I40E_FLAG_MFP_ENABLED)) {
7134f9ce
JB		 4708 pf->hw.func_caps.num_msix_vectors += 1;
4709 pf->hw.func_caps.num_tx_qp =
4710 min_t(int, pf->hw.func_caps.num_tx_qp,
4711 I40E_MAX_NPAR_QPS);
4712 }
4713
41c445ff
JB		 4714 if (pf->hw.debug_mask & I40E_DEBUG_USER)
4715 dev_info(&pf->pdev->dev,
4716 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
4717 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
4718 pf->hw.func_caps.num_msix_vectors,
4719 pf->hw.func_caps.num_msix_vectors_vf,
4720 pf->hw.func_caps.fd_filters_guaranteed,
4721 pf->hw.func_caps.fd_filters_best_effort,
4722 pf->hw.func_caps.num_tx_qp,
4723 pf->hw.func_caps.num_vsis);
4724
7134f9ce
JB		 4725#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
4726 + pf->hw.func_caps.num_vfs)
4727 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
4728 dev_info(&pf->pdev->dev,
4729 "got num_vsis %d, setting num_vsis to %d\n",
4730 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
4731 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
4732 }
4733
41c445ff
JB		 4734 return 0;
4735}
4736
4737/**
4738 * i40e_fdir_setup - initialize the Flow Director resources
4739 * @pf: board private structure
4740 **/
4741static void i40e_fdir_setup(struct i40e_pf *pf)
4742{
4743 struct i40e_vsi *vsi;
4744 bool new_vsi = false;
4745 int err, i;
4746
958a3e3b
SN		 4747 if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED |
4748 I40E_FLAG_FDIR_ATR_ENABLED)))
41c445ff
JB		 4749 return;
4750
4751 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
4752
4753 /* find existing or make new FDIR VSI */
4754 vsi = NULL;
4755 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4756 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
4757 vsi = pf->vsi[i];
4758 if (!vsi) {
4759 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
4760 if (!vsi) {
4761 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
4762 pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
4763 return;
4764 }
4765 new_vsi = true;
4766 }
4767 WARN_ON(vsi->base_queue != I40E_FDIR_RING);
4768 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
4769
4770 err = i40e_vsi_setup_tx_resources(vsi);
4771 if (!err)
4772 err = i40e_vsi_setup_rx_resources(vsi);
4773 if (!err)
4774 err = i40e_vsi_configure(vsi);
4775 if (!err && new_vsi) {
4776 char int_name[IFNAMSIZ + 9];
4777 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4778 dev_driver_string(&pf->pdev->dev));
4779 err = i40e_vsi_request_irq(vsi, int_name);
4780 }
4781 if (!err)
4782 err = i40e_up_complete(vsi);
4783
4784 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4785}
4786
4787/**
4788 * i40e_fdir_teardown - release the Flow Director resources
4789 * @pf: board private structure
4790 **/
4791static void i40e_fdir_teardown(struct i40e_pf *pf)
4792{
4793 int i;
4794
4795 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
4796 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
4797 i40e_vsi_release(pf->vsi[i]);
4798 break;
4799 }
4800 }
4801}
4802
4803/**
f650a38b 4804 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 4805 * @pf: board private structure
4806 *
f650a38b
ASJ		 4807 * Close up the VFs and other things in prep for pf Reset.
4808 **/
4809static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 4810{
41c445ff
JB		 4811 struct i40e_hw *hw = &pf->hw;
4812 i40e_status ret;
4813 u32 v;
4814
4815 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
4816 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 4817 return 0;
41c445ff
JB		 4818
4819 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
4820
37f0be6d
ASJ		 4821 if (i40e_check_asq_alive(hw))
4822 i40e_vc_notify_reset(pf);
41c445ff
JB		 4823
4824 /* quiesce the VSIs and their queues that are not already DOWN */
4825 i40e_pf_quiesce_all_vsi(pf);
4826
4827 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4828 if (pf->vsi[v])
4829 pf->vsi[v]->seid = 0;
4830 }
4831
4832 i40e_shutdown_adminq(&pf->hw);
4833
f650a38b
ASJ		 4834 /* call shutdown HMC */
4835 ret = i40e_shutdown_lan_hmc(hw);
4836 if (ret) {
4837 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
4838 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4839 }
4840 return ret;
4841}
4842
4843/**
4dda12e6 4844 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 4845 * @pf: board private structure
bc7d338f 4846 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 4847 **/
bc7d338f 4848static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 4849{
4850 struct i40e_driver_version dv;
4851 struct i40e_hw *hw = &pf->hw;
4852 i40e_status ret;
4853 u32 v;
4854
41c445ff
JB		 4855 /* Now we wait for GRST to settle out.
4856 * We don't have to delete the VEBs or VSIs from the hw switch
4857 * because the reset will make them disappear.
4858 */
4859 ret = i40e_pf_reset(hw);
4860 if (ret)
4861 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
4862 pf->pfr_count++;
4863
4864 if (test_bit(__I40E_DOWN, &pf->state))
4865 goto end_core_reset;
4866 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
4867
4868 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
4869 ret = i40e_init_adminq(&pf->hw);
4870 if (ret) {
4871 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
4872 goto end_core_reset;
4873 }
4874
4875 ret = i40e_get_capabilities(pf);
4876 if (ret) {
4877 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
4878 ret);
4879 goto end_core_reset;
4880 }
4881
41c445ff
JB		 4882 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
4883 hw->func_caps.num_rx_qp,
4884 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
4885 if (ret) {
4886 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
4887 goto end_core_reset;
4888 }
4889 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
4890 if (ret) {
4891 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
4892 goto end_core_reset;
4893 }
4894
4895 /* do basic switch setup */
bc7d338f 4896 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 4897 if (ret)
4898 goto end_core_reset;
4899
4900 /* Rebuild the VSIs and VEBs that existed before reset.
4901 * They are still in our local switch element arrays, so only
4902 * need to rebuild the switch model in the HW.
4903 *
4904 * If there were VEBs but the reconstitution failed, we'll try
4905 * try to recover minimal use by getting the basic PF VSI working.
4906 */
4907 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
4908 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
4909 /* find the one VEB connected to the MAC, and find orphans */
4910 for (v = 0; v < I40E_MAX_VEB; v++) {
4911 if (!pf->veb[v])
4912 continue;
4913
4914 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
4915 pf->veb[v]->uplink_seid == 0) {
4916 ret = i40e_reconstitute_veb(pf->veb[v]);
4917
4918 if (!ret)
4919 continue;
4920
4921 /* If Main VEB failed, we're in deep doodoo,
4922 * so give up rebuilding the switch and set up
4923 * for minimal rebuild of PF VSI.
4924 * If orphan failed, we'll report the error
4925 * but try to keep going.
4926 */
4927 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
4928 dev_info(&pf->pdev->dev,
4929 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
4930 ret);
4931 pf->vsi[pf->lan_vsi]->uplink_seid
4932 = pf->mac_seid;
4933 break;
4934 } else if (pf->veb[v]->uplink_seid == 0) {
4935 dev_info(&pf->pdev->dev,
4936 "rebuild of orphan VEB failed: %d\n",
4937 ret);
4938 }
4939 }
4940 }
4941 }
4942
4943 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
4944 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
4945 /* no VEB, so rebuild only the Main VSI */
4946 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
4947 if (ret) {
4948 dev_info(&pf->pdev->dev,
4949 "rebuild of Main VSI failed: %d\n", ret);
4950 goto end_core_reset;
4951 }
4952 }
4953
4954 /* reinit the misc interrupt */
4955 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4956 ret = i40e_setup_misc_vector(pf);
4957
4958 /* restart the VSIs that were rebuilt and running before the reset */
4959 i40e_pf_unquiesce_all_vsi(pf);
4960
4961 /* tell the firmware that we're starting */
4962 dv.major_version = DRV_VERSION_MAJOR;
4963 dv.minor_version = DRV_VERSION_MINOR;
4964 dv.build_version = DRV_VERSION_BUILD;
4965 dv.subbuild_version = 0;
4966 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
4967
4968 dev_info(&pf->pdev->dev, "PF reset done\n");
4969
4970end_core_reset:
4971 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4972}
4973
f650a38b
ASJ		 4974/**
4975 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
4976 * @pf: board private structure
4977 *
4978 * Close up the VFs and other things in prep for a Core Reset,
4979 * then get ready to rebuild the world.
4980 **/
4981static void i40e_handle_reset_warning(struct i40e_pf *pf)
4982{
4983 i40e_status ret;
4984
4985 ret = i40e_prep_for_reset(pf);
4986 if (!ret)
bc7d338f 4987 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 4988}
4989
41c445ff
JB		 4990/**
4991 * i40e_handle_mdd_event
4992 * @pf: pointer to the pf structure
4993 *
4994 * Called from the MDD irq handler to identify possibly malicious vfs
4995 **/
4996static void i40e_handle_mdd_event(struct i40e_pf *pf)
4997{
4998 struct i40e_hw *hw = &pf->hw;
4999 bool mdd_detected = false;
5000 struct i40e_vf *vf;
5001 u32 reg;
5002 int i;
5003
5004 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5005 return;
5006
5007 /* find what triggered the MDD event */
5008 reg = rd32(hw, I40E_GL_MDET_TX);
5009 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5010 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5011 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5012 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5013 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5014 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5015 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5016 dev_info(&pf->pdev->dev,
5017 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
5018 event, queue, func);
5019 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5020 mdd_detected = true;
5021 }
5022 reg = rd32(hw, I40E_GL_MDET_RX);
5023 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5024 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5025 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5026 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5027 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5028 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5029 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5030 dev_info(&pf->pdev->dev,
5031 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
5032 event, queue, func);
5033 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5034 mdd_detected = true;
5035 }
5036
5037 /* see if one of the VFs needs its hand slapped */
5038 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5039 vf = &(pf->vf[i]);
5040 reg = rd32(hw, I40E_VP_MDET_TX(i));
5041 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5042 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5043 vf->num_mdd_events++;
5044 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5045 }
5046
5047 reg = rd32(hw, I40E_VP_MDET_RX(i));
5048 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5049 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5050 vf->num_mdd_events++;
5051 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5052 }
5053
5054 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5055 dev_info(&pf->pdev->dev,
5056 "Too many MDD events on VF %d, disabled\n", i);
5057 dev_info(&pf->pdev->dev,
5058 "Use PF Control I/F to re-enable the VF\n");
5059 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5060 }
5061 }
5062
5063 /* re-enable mdd interrupt cause */
5064 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5065 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5066 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5067 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5068 i40e_flush(hw);
5069}
5070
a1c9a9d9
JK		 5071#ifdef CONFIG_I40E_VXLAN
5072/**
5073 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5074 * @pf: board private structure
5075 **/
5076static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5077{
5078 const int vxlan_hdr_qwords = 4;
5079 struct i40e_hw *hw = &pf->hw;
5080 i40e_status ret;
5081 u8 filter_index;
5082 __be16 port;
5083 int i;
5084
5085 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5086 return;
5087
5088 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5089
5090 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5091 if (pf->pending_vxlan_bitmap & (1 << i)) {
5092 pf->pending_vxlan_bitmap &= ~(1 << i);
5093 port = pf->vxlan_ports[i];
5094 ret = port ?
5095 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5096 vxlan_hdr_qwords,
5097 I40E_AQC_TUNNEL_TYPE_VXLAN,
5098 &filter_index, NULL)
5099 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5100
5101 if (ret) {
5102 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5103 port ? "adding" : "deleting",
5104 ntohs(port), port ? i : i);
5105
5106 pf->vxlan_ports[i] = 0;
5107 } else {
5108 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5109 port ? "Added" : "Deleted",
5110 ntohs(port), port ? i : filter_index);
5111 }
5112 }
5113 }
5114}
5115
5116#endif
41c445ff
JB		 5117/**
5118 * i40e_service_task - Run the driver's async subtasks
5119 * @work: pointer to work_struct containing our data
5120 **/
5121static void i40e_service_task(struct work_struct *work)
5122{
5123 struct i40e_pf *pf = container_of(work,
5124 struct i40e_pf,
5125 service_task);
5126 unsigned long start_time = jiffies;
5127
5128 i40e_reset_subtask(pf);
5129 i40e_handle_mdd_event(pf);
5130 i40e_vc_process_vflr_event(pf);
5131 i40e_watchdog_subtask(pf);
5132 i40e_fdir_reinit_subtask(pf);
5133 i40e_check_hang_subtask(pf);
5134 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5135#ifdef CONFIG_I40E_VXLAN
5136 i40e_sync_vxlan_filters_subtask(pf);
5137#endif
41c445ff
JB		 5138 i40e_clean_adminq_subtask(pf);
5139
5140 i40e_service_event_complete(pf);
5141
5142 /* If the tasks have taken longer than one timer cycle or there
5143 * is more work to be done, reschedule the service task now
5144 * rather than wait for the timer to tick again.
5145 */
5146 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5147 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5148 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5149 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5150 i40e_service_event_schedule(pf);
5151}
5152
5153/**
5154 * i40e_service_timer - timer callback
5155 * @data: pointer to PF struct
5156 **/
5157static void i40e_service_timer(unsigned long data)
5158{
5159 struct i40e_pf *pf = (struct i40e_pf *)data;
5160
5161 mod_timer(&pf->service_timer,
5162 round_jiffies(jiffies + pf->service_timer_period));
5163 i40e_service_event_schedule(pf);
5164}
5165
5166/**
5167 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5168 * @vsi: the VSI being configured
5169 **/
5170static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5171{
5172 struct i40e_pf *pf = vsi->back;
5173
5174 switch (vsi->type) {
5175 case I40E_VSI_MAIN:
5176 vsi->alloc_queue_pairs = pf->num_lan_qps;
5177 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5178 I40E_REQ_DESCRIPTOR_MULTIPLE);
5179 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5180 vsi->num_q_vectors = pf->num_lan_msix;
5181 else
5182 vsi->num_q_vectors = 1;
5183
5184 break;
5185
5186 case I40E_VSI_FDIR:
5187 vsi->alloc_queue_pairs = 1;
5188 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5189 I40E_REQ_DESCRIPTOR_MULTIPLE);
5190 vsi->num_q_vectors = 1;
5191 break;
5192
5193 case I40E_VSI_VMDQ2:
5194 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5195 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5196 I40E_REQ_DESCRIPTOR_MULTIPLE);
5197 vsi->num_q_vectors = pf->num_vmdq_msix;
5198 break;
5199
5200 case I40E_VSI_SRIOV:
5201 vsi->alloc_queue_pairs = pf->num_vf_qps;
5202 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5203 I40E_REQ_DESCRIPTOR_MULTIPLE);
5204 break;
5205
5206 default:
5207 WARN_ON(1);
5208 return -ENODATA;
5209 }
5210
5211 return 0;
5212}
5213
f650a38b
ASJ		 5214/**
5215 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5216 * @type: VSI pointer
bc7d338f 5217 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5218 *
5219 * On error: returns error code (negative)
5220 * On success: returns 0
5221 **/
bc7d338f 5222static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5223{
5224 int size;
5225 int ret = 0;
5226
ac6c5e3d 5227 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5228 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5229 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5230 if (!vsi->tx_rings)
5231 return -ENOMEM;
f650a38b
ASJ		 5232 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5233
bc7d338f
ASJ		 5234 if (alloc_qvectors) {
5235 /* allocate memory for q_vector pointers */
5236 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5237 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5238 if (!vsi->q_vectors) {
5239 ret = -ENOMEM;
5240 goto err_vectors;
5241 }
f650a38b
ASJ		 5242 }
5243 return ret;
5244
5245err_vectors:
5246 kfree(vsi->tx_rings);
5247 return ret;
5248}
5249
41c445ff
JB		 5250/**
5251 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5252 * @pf: board private structure
5253 * @type: type of VSI
5254 *
5255 * On error: returns error code (negative)
5256 * On success: returns vsi index in PF (positive)
5257 **/
5258static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5259{
5260 int ret = -ENODEV;
5261 struct i40e_vsi *vsi;
5262 int vsi_idx;
5263 int i;
5264
5265 /* Need to protect the allocation of the VSIs at the PF level */
5266 mutex_lock(&pf->switch_mutex);
5267
5268 /* VSI list may be fragmented if VSI creation/destruction has
5269 * been happening. We can afford to do a quick scan to look
5270 * for any free VSIs in the list.
5271 *
5272 * find next empty vsi slot, looping back around if necessary
5273 */
5274 i = pf->next_vsi;
5275 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5276 i++;
5277 if (i >= pf->hw.func_caps.num_vsis) {
5278 i = 0;
5279 while (i < pf->next_vsi && pf->vsi[i])
5280 i++;
5281 }
5282
5283 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5284 vsi_idx = i; /* Found one! */
5285 } else {
5286 ret = -ENODEV;
493fb300 5287 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5288 }
5289 pf->next_vsi = ++i;
5290
5291 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5292 if (!vsi) {
5293 ret = -ENOMEM;
493fb300 5294 goto unlock_pf;
41c445ff
JB		 5295 }
5296 vsi->type = type;
5297 vsi->back = pf;
5298 set_bit(__I40E_DOWN, &vsi->state);
5299 vsi->flags = 0;
5300 vsi->idx = vsi_idx;
5301 vsi->rx_itr_setting = pf->rx_itr_default;
5302 vsi->tx_itr_setting = pf->tx_itr_default;
5303 vsi->netdev_registered = false;
5304 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5305 INIT_LIST_HEAD(&vsi->mac_filter_list);
5306
9f65e15b
AD		 5307 ret = i40e_set_num_rings_in_vsi(vsi);
5308 if (ret)
5309 goto err_rings;
5310
bc7d338f 5311 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5312 if (ret)
9f65e15b 5313 goto err_rings;
493fb300 5314
41c445ff
JB		 5315 /* Setup default MSIX irq handler for VSI */
5316 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5317
5318 pf->vsi[vsi_idx] = vsi;
5319 ret = vsi_idx;
493fb300
AD		 5320 goto unlock_pf;
5321
9f65e15b 5322err_rings:
493fb300
AD		 5323 pf->next_vsi = i - 1;
5324 kfree(vsi);
5325unlock_pf:
41c445ff
JB		 5326 mutex_unlock(&pf->switch_mutex);
5327 return ret;
5328}
5329
f650a38b
ASJ		 5330/**
5331 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5332 * @type: VSI pointer
bc7d338f 5333 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5334 *
5335 * On error: returns error code (negative)
5336 * On success: returns 0
5337 **/
bc7d338f 5338static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5339{
5340 /* free the ring and vector containers */
bc7d338f
ASJ		 5341 if (free_qvectors) {
5342 kfree(vsi->q_vectors);
5343 vsi->q_vectors = NULL;
5344 }
f650a38b
ASJ		 5345 kfree(vsi->tx_rings);
5346 vsi->tx_rings = NULL;
5347 vsi->rx_rings = NULL;
5348}
5349
41c445ff
JB		 5350/**
5351 * i40e_vsi_clear - Deallocate the VSI provided
5352 * @vsi: the VSI being un-configured
5353 **/
5354static int i40e_vsi_clear(struct i40e_vsi *vsi)
5355{
5356 struct i40e_pf *pf;
5357
5358 if (!vsi)
5359 return 0;
5360
5361 if (!vsi->back)
5362 goto free_vsi;
5363 pf = vsi->back;
5364
5365 mutex_lock(&pf->switch_mutex);
5366 if (!pf->vsi[vsi->idx]) {
5367 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5368 vsi->idx, vsi->idx, vsi, vsi->type);
5369 goto unlock_vsi;
5370 }
5371
5372 if (pf->vsi[vsi->idx] != vsi) {
5373 dev_err(&pf->pdev->dev,
5374 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5375 pf->vsi[vsi->idx]->idx,
5376 pf->vsi[vsi->idx],
5377 pf->vsi[vsi->idx]->type,
5378 vsi->idx, vsi, vsi->type);
5379 goto unlock_vsi;
5380 }
5381
5382 /* updates the pf for this cleared vsi */
5383 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5384 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5385
bc7d338f 5386 i40e_vsi_free_arrays(vsi, true);
493fb300 5387
41c445ff
JB		 5388 pf->vsi[vsi->idx] = NULL;
5389 if (vsi->idx < pf->next_vsi)
5390 pf->next_vsi = vsi->idx;
5391
5392unlock_vsi:
5393 mutex_unlock(&pf->switch_mutex);
5394free_vsi:
5395 kfree(vsi);
5396
5397 return 0;
5398}
5399
9f65e15b
AD		 5400/**
5401 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5402 * @vsi: the VSI being cleaned
5403 **/
be1d5eea 5404static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5405{
5406 int i;
5407
8e9dca53 5408 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5409 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5410 kfree_rcu(vsi->tx_rings[i], rcu);
5411 vsi->tx_rings[i] = NULL;
5412 vsi->rx_rings[i] = NULL;
5413 }
be1d5eea 5414 }
9f65e15b
AD		 5415}
5416
41c445ff
JB		 5417/**
5418 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5419 * @vsi: the VSI being configured
5420 **/
5421static int i40e_alloc_rings(struct i40e_vsi *vsi)
5422{
5423 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5424 int i;
5425
41c445ff 5426 /* Set basic values in the rings to be used later during open() */
d7397644 5427 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5428 struct i40e_ring *tx_ring;
5429 struct i40e_ring *rx_ring;
5430
ac6c5e3d 5431 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5432 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5433 if (!tx_ring)
5434 goto err_out;
41c445ff
JB		 5435
5436 tx_ring->queue_index = i;
5437 tx_ring->reg_idx = vsi->base_queue + i;
5438 tx_ring->ring_active = false;
5439 tx_ring->vsi = vsi;
5440 tx_ring->netdev = vsi->netdev;
5441 tx_ring->dev = &pf->pdev->dev;
5442 tx_ring->count = vsi->num_desc;
5443 tx_ring->size = 0;
5444 tx_ring->dcb_tc = 0;
9f65e15b 5445 vsi->tx_rings[i] = tx_ring;
41c445ff 5446
9f65e15b 5447 rx_ring = &tx_ring[1];
41c445ff
JB		 5448 rx_ring->queue_index = i;
5449 rx_ring->reg_idx = vsi->base_queue + i;
5450 rx_ring->ring_active = false;
5451 rx_ring->vsi = vsi;
5452 rx_ring->netdev = vsi->netdev;
5453 rx_ring->dev = &pf->pdev->dev;
5454 rx_ring->count = vsi->num_desc;
5455 rx_ring->size = 0;
5456 rx_ring->dcb_tc = 0;
5457 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5458 set_ring_16byte_desc_enabled(rx_ring);
5459 else
5460 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5461 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5462 }
5463
5464 return 0;
9f65e15b
AD		 5465
5466err_out:
5467 i40e_vsi_clear_rings(vsi);
5468 return -ENOMEM;
41c445ff
JB		 5469}
5470
5471/**
5472 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5473 * @pf: board private structure
5474 * @vectors: the number of MSI-X vectors to request
5475 *
5476 * Returns the number of vectors reserved, or error
5477 **/
5478static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5479{
5480 int err = 0;
5481
5482 pf->num_msix_entries = 0;
5483 while (vectors >= I40E_MIN_MSIX) {
5484 err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
5485 if (err == 0) {
5486 /* good to go */
5487 pf->num_msix_entries = vectors;
5488 break;
5489 } else if (err < 0) {
5490 /* total failure */
5491 dev_info(&pf->pdev->dev,
5492 "MSI-X vector reservation failed: %d\n", err);
5493 vectors = 0;
5494 break;
5495 } else {
5496 /* err > 0 is the hint for retry */
5497 dev_info(&pf->pdev->dev,
5498 "MSI-X vectors wanted %d, retrying with %d\n",
5499 vectors, err);
5500 vectors = err;
5501 }
5502 }
5503
5504 if (vectors > 0 && vectors < I40E_MIN_MSIX) {
5505 dev_info(&pf->pdev->dev,
5506 "Couldn't get enough vectors, only %d available\n",
5507 vectors);
5508 vectors = 0;
5509 }
5510
5511 return vectors;
5512}
5513
5514/**
5515 * i40e_init_msix - Setup the MSIX capability
5516 * @pf: board private structure
5517 *
5518 * Work with the OS to set up the MSIX vectors needed.
5519 *
5520 * Returns 0 on success, negative on failure
5521 **/
5522static int i40e_init_msix(struct i40e_pf *pf)
5523{
5524 i40e_status err = 0;
5525 struct i40e_hw *hw = &pf->hw;
5526 int v_budget, i;
5527 int vec;
5528
5529 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5530 return -ENODEV;
5531
5532 /* The number of vectors we'll request will be comprised of:
5533 * - Add 1 for "other" cause for Admin Queue events, etc.
5534 * - The number of LAN queue pairs
f8ff1464
ASJ		 5535 * - Queues being used for RSS.
5536 * We don't need as many as max_rss_size vectors.
5537 * use rss_size instead in the calculation since that
5538 * is governed by number of cpus in the system.
5539 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5540 * - The number of VMDq pairs
5541 * Once we count this up, try the request.
5542 *
5543 * If we can't get what we want, we'll simplify to nearly nothing
5544 * and try again. If that still fails, we punt.
5545 */
f8ff1464 5546 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5547 pf->num_vmdq_msix = pf->num_vmdq_qps;
5548 v_budget = 1 + pf->num_lan_msix;
5549 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
5550 if (pf->flags & I40E_FLAG_FDIR_ENABLED)
5551 v_budget++;
5552
5553 /* Scale down if necessary, and the rings will share vectors */
5554 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5555
5556 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5557 GFP_KERNEL);
5558 if (!pf->msix_entries)
5559 return -ENOMEM;
5560
5561 for (i = 0; i < v_budget; i++)
5562 pf->msix_entries[i].entry = i;
5563 vec = i40e_reserve_msix_vectors(pf, v_budget);
5564 if (vec < I40E_MIN_MSIX) {
5565 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5566 kfree(pf->msix_entries);
5567 pf->msix_entries = NULL;
5568 return -ENODEV;
5569
5570 } else if (vec == I40E_MIN_MSIX) {
5571 /* Adjust for minimal MSIX use */
5572 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5573 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5574 pf->num_vmdq_vsis = 0;
5575 pf->num_vmdq_qps = 0;
5576 pf->num_vmdq_msix = 0;
5577 pf->num_lan_qps = 1;
5578 pf->num_lan_msix = 1;
5579
5580 } else if (vec != v_budget) {
5581 /* Scale vector usage down */
5582 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5583 vec--; /* reserve the misc vector */
5584
5585 /* partition out the remaining vectors */
5586 switch (vec) {
5587 case 2:
5588 pf->num_vmdq_vsis = 1;
5589 pf->num_lan_msix = 1;
5590 break;
5591 case 3:
5592 pf->num_vmdq_vsis = 1;
5593 pf->num_lan_msix = 2;
5594 break;
5595 default:
5596 pf->num_lan_msix = min_t(int, (vec / 2),
5597 pf->num_lan_qps);
5598 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5599 I40E_DEFAULT_NUM_VMDQ_VSI);
5600 break;
5601 }
5602 }
5603
5604 return err;
5605}
5606
493fb300
AD		 5607/**
5608 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5609 * @vsi: the VSI being configured
5610 * @v_idx: index of the vector in the vsi struct
5611 *
5612 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5613 **/
5614static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5615{
5616 struct i40e_q_vector *q_vector;
5617
5618 /* allocate q_vector */
5619 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5620 if (!q_vector)
5621 return -ENOMEM;
5622
5623 q_vector->vsi = vsi;
5624 q_vector->v_idx = v_idx;
5625 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5626 if (vsi->netdev)
5627 netif_napi_add(vsi->netdev, &q_vector->napi,
5628 i40e_napi_poll, vsi->work_limit);
5629
cd0b6fa6
AD		 5630 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5631 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5632
493fb300
AD		 5633 /* tie q_vector and vsi together */
5634 vsi->q_vectors[v_idx] = q_vector;
5635
5636 return 0;
5637}
5638
41c445ff
JB		 5639/**
5640 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5641 * @vsi: the VSI being configured
5642 *
5643 * We allocate one q_vector per queue interrupt. If allocation fails we
5644 * return -ENOMEM.
5645 **/
5646static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
5647{
5648 struct i40e_pf *pf = vsi->back;
5649 int v_idx, num_q_vectors;
493fb300 5650 int err;
41c445ff
JB		 5651
5652 /* if not MSIX, give the one vector only to the LAN VSI */
5653 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5654 num_q_vectors = vsi->num_q_vectors;
5655 else if (vsi == pf->vsi[pf->lan_vsi])
5656 num_q_vectors = 1;
5657 else
5658 return -EINVAL;
5659
41c445ff 5660 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 5661 err = i40e_alloc_q_vector(vsi, v_idx);
5662 if (err)
5663 goto err_out;
41c445ff
JB		 5664 }
5665
5666 return 0;
493fb300
AD		 5667
5668err_out:
5669 while (v_idx--)
5670 i40e_free_q_vector(vsi, v_idx);
5671
5672 return err;
41c445ff
JB		 5673}
5674
5675/**
5676 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
5677 * @pf: board private structure to initialize
5678 **/
5679static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
5680{
5681 int err = 0;
5682
5683 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
5684 err = i40e_init_msix(pf);
5685 if (err) {
958a3e3b
SN		 5686 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
5687 I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 5688 I40E_FLAG_DCB_ENABLED |
5689 I40E_FLAG_SRIOV_ENABLED |
5690 I40E_FLAG_FDIR_ENABLED |
5691 I40E_FLAG_FDIR_ATR_ENABLED |
5692 I40E_FLAG_VMDQ_ENABLED);
5693
5694 /* rework the queue expectations without MSIX */
5695 i40e_determine_queue_usage(pf);
5696 }
5697 }
5698
5699 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
5700 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 5701 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 5702 err = pci_enable_msi(pf->pdev);
5703 if (err) {
958a3e3b 5704 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 5705 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
5706 }
5707 }
5708
958a3e3b
SN		 5709 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
5710 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
5711
41c445ff
JB		 5712 /* track first vector for misc interrupts */
5713 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
5714}
5715
5716/**
5717 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
5718 * @pf: board private structure
5719 *
5720 * This sets up the handler for MSIX 0, which is used to manage the
5721 * non-queue interrupts, e.g. AdminQ and errors. This is not used
5722 * when in MSI or Legacy interrupt mode.
5723 **/
5724static int i40e_setup_misc_vector(struct i40e_pf *pf)
5725{
5726 struct i40e_hw *hw = &pf->hw;
5727 int err = 0;
5728
5729 /* Only request the irq if this is the first time through, and
5730 * not when we're rebuilding after a Reset
5731 */
5732 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5733 err = request_irq(pf->msix_entries[0].vector,
5734 i40e_intr, 0, pf->misc_int_name, pf);
5735 if (err) {
5736 dev_info(&pf->pdev->dev,
5737 "request_irq for msix_misc failed: %d\n", err);
5738 return -EFAULT;
5739 }
5740 }
5741
5742 i40e_enable_misc_int_causes(hw);
5743
5744 /* associate no queues to the misc vector */
5745 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
5746 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
5747
5748 i40e_flush(hw);
5749
5750 i40e_irq_dynamic_enable_icr0(pf);
5751
5752 return err;
5753}
5754
5755/**
5756 * i40e_config_rss - Prepare for RSS if used
5757 * @pf: board private structure
5758 **/
5759static int i40e_config_rss(struct i40e_pf *pf)
5760{
41c445ff
JB		 5761 /* Set of random keys generated using kernel random number generator */
5762 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
5763 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
5764 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
5765 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 5766 struct i40e_hw *hw = &pf->hw;
5767 u32 lut = 0;
5768 int i, j;
5769 u64 hena;
41c445ff
JB		 5770
5771 /* Fill out hash function seed */
5772 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5773 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
5774
5775 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
5776 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
5777 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 5778 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 5779 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
5780 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
5781
5782 /* Populate the LUT with max no. of queues in round robin fashion */
5783 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
5784
5785 /* The assumption is that lan qp count will be the highest
5786 * qp count for any PF VSI that needs RSS.
5787 * If multiple VSIs need RSS support, all the qp counts
5788 * for those VSIs should be a power of 2 for RSS to work.
5789 * If LAN VSI is the only consumer for RSS then this requirement
5790 * is not necessary.
5791 */
5792 if (j == pf->rss_size)
5793 j = 0;
5794 /* lut = 4-byte sliding window of 4 lut entries */
5795 lut = (lut << 8) | (j &
5796 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
5797 /* On i = 3, we have 4 entries in lut; write to the register */
5798 if ((i & 3) == 3)
5799 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
5800 }
5801 i40e_flush(hw);
5802
5803 return 0;
5804}
5805
f8ff1464
ASJ		 5806/**
5807 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
5808 * @pf: board private structure
5809 * @queue_count: the requested queue count for rss.
5810 *
5811 * returns 0 if rss is not enabled, if enabled returns the final rss queue
5812 * count which may be different from the requested queue count.
5813 **/
5814int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
5815{
5816 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
5817 return 0;
5818
5819 queue_count = min_t(int, queue_count, pf->rss_size_max);
5820 queue_count = rounddown_pow_of_two(queue_count);
5821
5822 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 5823 i40e_prep_for_reset(pf);
5824
f8ff1464
ASJ		 5825 pf->rss_size = queue_count;
5826
5827 i40e_reset_and_rebuild(pf, true);
5828 i40e_config_rss(pf);
5829 }
5830 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
5831 return pf->rss_size;
5832}
5833
41c445ff
JB		 5834/**
5835 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
5836 * @pf: board private structure to initialize
5837 *
5838 * i40e_sw_init initializes the Adapter private data structure.
5839 * Fields are initialized based on PCI device information and
5840 * OS network device settings (MTU size).
5841 **/
5842static int i40e_sw_init(struct i40e_pf *pf)
5843{
5844 int err = 0;
5845 int size;
5846
5847 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
5848 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 5849 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 5850 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
5851 if (I40E_DEBUG_USER & debug)
5852 pf->hw.debug_mask = debug;
5853 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
5854 I40E_DEFAULT_MSG_ENABLE);
5855 }
5856
5857 /* Set default capability flags */
5858 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
5859 I40E_FLAG_MSI_ENABLED |
5860 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 5861 I40E_FLAG_RX_1BUF_ENABLED;
5862
7134f9ce
JB		 5863 /* Depending on PF configurations, it is possible that the RSS
5864 * maximum might end up larger than the available queues
5865 */
41c445ff 5866 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 5867 pf->rss_size_max = min_t(int, pf->rss_size_max,
5868 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 5869 if (pf->hw.func_caps.rss) {
5870 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 5871 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 5872 } else {
5873 pf->rss_size = 1;
5874 }
5875
2050bc65
CS		 5876 /* MFP mode enabled */
5877 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
5878 pf->flags |= I40E_FLAG_MFP_ENABLED;
5879 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
5880 }
5881
41c445ff
JB		 5882 if (pf->hw.func_caps.dcb)
5883 pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
5884 else
5885 pf->num_tc_qps = 0;
5886
5887 if (pf->hw.func_caps.fd) {
5888 /* FW/NVM is not yet fixed in this regard */
5889 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
5890 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
5891 pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
5892 dev_info(&pf->pdev->dev,
5893 "Flow Director ATR mode Enabled\n");
5894 pf->flags |= I40E_FLAG_FDIR_ENABLED;
5895 dev_info(&pf->pdev->dev,
5896 "Flow Director Side Band mode Enabled\n");
5897 pf->fdir_pf_filter_count =
5898 pf->hw.func_caps.fd_filters_guaranteed;
5899 }
5900 } else {
5901 pf->fdir_pf_filter_count = 0;
5902 }
5903
5904 if (pf->hw.func_caps.vmdq) {
5905 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
5906 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
5907 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
5908 }
5909
41c445ff
JB		 5910#ifdef CONFIG_PCI_IOV
5911 if (pf->hw.func_caps.num_vfs) {
5912 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
5913 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
5914 pf->num_req_vfs = min_t(int,
5915 pf->hw.func_caps.num_vfs,
5916 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 5917 dev_info(&pf->pdev->dev,
5918 "Number of VFs being requested for PF[%d] = %d\n",
5919 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 5920 }
5921#endif /* CONFIG_PCI_IOV */
5922 pf->eeprom_version = 0xDEAD;
5923 pf->lan_veb = I40E_NO_VEB;
5924 pf->lan_vsi = I40E_NO_VSI;
5925
5926 /* set up queue assignment tracking */
5927 size = sizeof(struct i40e_lump_tracking)
5928 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
5929 pf->qp_pile = kzalloc(size, GFP_KERNEL);
5930 if (!pf->qp_pile) {
5931 err = -ENOMEM;
5932 goto sw_init_done;
5933 }
5934 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
5935 pf->qp_pile->search_hint = 0;
5936
5937 /* set up vector assignment tracking */
5938 size = sizeof(struct i40e_lump_tracking)
5939 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
5940 pf->irq_pile = kzalloc(size, GFP_KERNEL);
5941 if (!pf->irq_pile) {
5942 kfree(pf->qp_pile);
5943 err = -ENOMEM;
5944 goto sw_init_done;
5945 }
5946 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
5947 pf->irq_pile->search_hint = 0;
5948
5949 mutex_init(&pf->switch_mutex);
5950
5951sw_init_done:
5952 return err;
5953}
5954
5955/**
5956 * i40e_set_features - set the netdev feature flags
5957 * @netdev: ptr to the netdev being adjusted
5958 * @features: the feature set that the stack is suggesting
5959 **/
5960static int i40e_set_features(struct net_device *netdev,
5961 netdev_features_t features)
5962{
5963 struct i40e_netdev_priv *np = netdev_priv(netdev);
5964 struct i40e_vsi *vsi = np->vsi;
5965
5966 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5967 i40e_vlan_stripping_enable(vsi);
5968 else
5969 i40e_vlan_stripping_disable(vsi);
5970
5971 return 0;
5972}
5973
a1c9a9d9
JK		 5974#ifdef CONFIG_I40E_VXLAN
5975/**
5976 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
5977 * @pf: board private structure
5978 * @port: The UDP port to look up
5979 *
5980 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
5981 **/
5982static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
5983{
5984 u8 i;
5985
5986 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5987 if (pf->vxlan_ports[i] == port)
5988 return i;
5989 }
5990
5991 return i;
5992}
5993
5994/**
5995 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
5996 * @netdev: This physical port's netdev
5997 * @sa_family: Socket Family that VXLAN is notifying us about
5998 * @port: New UDP port number that VXLAN started listening to
5999 **/
6000static void i40e_add_vxlan_port(struct net_device *netdev,
6001 sa_family_t sa_family, __be16 port)
6002{
6003 struct i40e_netdev_priv *np = netdev_priv(netdev);
6004 struct i40e_vsi *vsi = np->vsi;
6005 struct i40e_pf *pf = vsi->back;
6006 u8 next_idx;
6007 u8 idx;
6008
6009 if (sa_family == AF_INET6)
6010 return;
6011
6012 idx = i40e_get_vxlan_port_idx(pf, port);
6013
6014 /* Check if port already exists */
6015 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6016 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6017 return;
6018 }
6019
6020 /* Now check if there is space to add the new port */
6021 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6022
6023 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6024 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6025 ntohs(port));
6026 return;
6027 }
6028
6029 /* New port: add it and mark its index in the bitmap */
6030 pf->vxlan_ports[next_idx] = port;
6031 pf->pending_vxlan_bitmap |= (1 << next_idx);
6032
6033 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6034}
6035
6036/**
6037 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6038 * @netdev: This physical port's netdev
6039 * @sa_family: Socket Family that VXLAN is notifying us about
6040 * @port: UDP port number that VXLAN stopped listening to
6041 **/
6042static void i40e_del_vxlan_port(struct net_device *netdev,
6043 sa_family_t sa_family, __be16 port)
6044{
6045 struct i40e_netdev_priv *np = netdev_priv(netdev);
6046 struct i40e_vsi *vsi = np->vsi;
6047 struct i40e_pf *pf = vsi->back;
6048 u8 idx;
6049
6050 if (sa_family == AF_INET6)
6051 return;
6052
6053 idx = i40e_get_vxlan_port_idx(pf, port);
6054
6055 /* Check if port already exists */
6056 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6057 /* if port exists, set it to 0 (mark for deletion)
6058 * and make it pending
6059 */
6060 pf->vxlan_ports[idx] = 0;
6061
6062 pf->pending_vxlan_bitmap |= (1 << idx);
6063
6064 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6065 } else {
6066 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6067 ntohs(port));
6068 }
6069}
6070
6071#endif
41c445ff
JB		 6072static const struct net_device_ops i40e_netdev_ops = {
6073 .ndo_open = i40e_open,
6074 .ndo_stop = i40e_close,
6075 .ndo_start_xmit = i40e_lan_xmit_frame,
6076 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6077 .ndo_set_rx_mode = i40e_set_rx_mode,
6078 .ndo_validate_addr = eth_validate_addr,
6079 .ndo_set_mac_address = i40e_set_mac,
6080 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6081 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6082 .ndo_tx_timeout = i40e_tx_timeout,
6083 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6084 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6085#ifdef CONFIG_NET_POLL_CONTROLLER
6086 .ndo_poll_controller = i40e_netpoll,
6087#endif
6088 .ndo_setup_tc = i40e_setup_tc,
6089 .ndo_set_features = i40e_set_features,
6090 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6091 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6092 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6093 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6094#ifdef CONFIG_I40E_VXLAN
6095 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6096 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6097#endif
41c445ff
JB		 6098};
6099
6100/**
6101 * i40e_config_netdev - Setup the netdev flags
6102 * @vsi: the VSI being configured
6103 *
6104 * Returns 0 on success, negative value on failure
6105 **/
6106static int i40e_config_netdev(struct i40e_vsi *vsi)
6107{
1a10370a 6108 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6109 struct i40e_pf *pf = vsi->back;
6110 struct i40e_hw *hw = &pf->hw;
6111 struct i40e_netdev_priv *np;
6112 struct net_device *netdev;
6113 u8 mac_addr[ETH_ALEN];
6114 int etherdev_size;
6115
6116 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6117 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6118 if (!netdev)
6119 return -ENOMEM;
6120
6121 vsi->netdev = netdev;
6122 np = netdev_priv(netdev);
6123 np->vsi = vsi;
6124
6125 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6126 NETIF_F_GSO_UDP_TUNNEL |
6127 NETIF_F_TSO |
6128 NETIF_F_SG;
6129
6130 netdev->features = NETIF_F_SG |
6131 NETIF_F_IP_CSUM |
6132 NETIF_F_SCTP_CSUM |
6133 NETIF_F_HIGHDMA |
6134 NETIF_F_GSO_UDP_TUNNEL |
6135 NETIF_F_HW_VLAN_CTAG_TX |
6136 NETIF_F_HW_VLAN_CTAG_RX |
6137 NETIF_F_HW_VLAN_CTAG_FILTER |
6138 NETIF_F_IPV6_CSUM |
6139 NETIF_F_TSO |
6140 NETIF_F_TSO6 |
6141 NETIF_F_RXCSUM |
6142 NETIF_F_RXHASH |
6143 0;
6144
6145 /* copy netdev features into list of user selectable features */
6146 netdev->hw_features |= netdev->features;
6147
6148 if (vsi->type == I40E_VSI_MAIN) {
6149 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6150 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6151 } else {
6152 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6153 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6154 pf->vsi[pf->lan_vsi]->netdev->name);
6155 random_ether_addr(mac_addr);
6156 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6157 }
1a10370a 6158 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6159
6160 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6161 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6162 /* vlan gets same features (except vlan offload)
6163 * after any tweaks for specific VSI types
6164 */
6165 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6166 NETIF_F_HW_VLAN_CTAG_RX |
6167 NETIF_F_HW_VLAN_CTAG_FILTER);
6168 netdev->priv_flags |= IFF_UNICAST_FLT;
6169 netdev->priv_flags |= IFF_SUPP_NOFCS;
6170 /* Setup netdev TC information */
6171 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6172
6173 netdev->netdev_ops = &i40e_netdev_ops;
6174 netdev->watchdog_timeo = 5 * HZ;
6175 i40e_set_ethtool_ops(netdev);
6176
6177 return 0;
6178}
6179
6180/**
6181 * i40e_vsi_delete - Delete a VSI from the switch
6182 * @vsi: the VSI being removed
6183 *
6184 * Returns 0 on success, negative value on failure
6185 **/
6186static void i40e_vsi_delete(struct i40e_vsi *vsi)
6187{
6188 /* remove default VSI is not allowed */
6189 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6190 return;
6191
6192 /* there is no HW VSI for FDIR */
6193 if (vsi->type == I40E_VSI_FDIR)
6194 return;
6195
6196 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6197 return;
6198}
6199
6200/**
6201 * i40e_add_vsi - Add a VSI to the switch
6202 * @vsi: the VSI being configured
6203 *
6204 * This initializes a VSI context depending on the VSI type to be added and
6205 * passes it down to the add_vsi aq command.
6206 **/
6207static int i40e_add_vsi(struct i40e_vsi *vsi)
6208{
6209 int ret = -ENODEV;
6210 struct i40e_mac_filter *f, *ftmp;
6211 struct i40e_pf *pf = vsi->back;
6212 struct i40e_hw *hw = &pf->hw;
6213 struct i40e_vsi_context ctxt;
6214 u8 enabled_tc = 0x1; /* TC0 enabled */
6215 int f_count = 0;
6216
6217 memset(&ctxt, 0, sizeof(ctxt));
6218 switch (vsi->type) {
6219 case I40E_VSI_MAIN:
6220 /* The PF's main VSI is already setup as part of the
6221 * device initialization, so we'll not bother with
6222 * the add_vsi call, but we will retrieve the current
6223 * VSI context.
6224 */
6225 ctxt.seid = pf->main_vsi_seid;
6226 ctxt.pf_num = pf->hw.pf_id;
6227 ctxt.vf_num = 0;
6228 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6229 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6230 if (ret) {
6231 dev_info(&pf->pdev->dev,
6232 "couldn't get pf vsi config, err %d, aq_err %d\n",
6233 ret, pf->hw.aq.asq_last_status);
6234 return -ENOENT;
6235 }
6236 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6237 vsi->info.valid_sections = 0;
6238
6239 vsi->seid = ctxt.seid;
6240 vsi->id = ctxt.vsi_number;
6241
6242 enabled_tc = i40e_pf_get_tc_map(pf);
6243
6244 /* MFP mode setup queue map and update VSI */
6245 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6246 memset(&ctxt, 0, sizeof(ctxt));
6247 ctxt.seid = pf->main_vsi_seid;
6248 ctxt.pf_num = pf->hw.pf_id;
6249 ctxt.vf_num = 0;
6250 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6251 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6252 if (ret) {
6253 dev_info(&pf->pdev->dev,
6254 "update vsi failed, aq_err=%d\n",
6255 pf->hw.aq.asq_last_status);
6256 ret = -ENOENT;
6257 goto err;
6258 }
6259 /* update the local VSI info queue map */
6260 i40e_vsi_update_queue_map(vsi, &ctxt);
6261 vsi->info.valid_sections = 0;
6262 } else {
6263 /* Default/Main VSI is only enabled for TC0
6264 * reconfigure it to enable all TCs that are
6265 * available on the port in SFP mode.
6266 */
6267 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6268 if (ret) {
6269 dev_info(&pf->pdev->dev,
6270 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6271 enabled_tc, ret,
6272 pf->hw.aq.asq_last_status);
6273 ret = -ENOENT;
6274 }
6275 }
6276 break;
6277
6278 case I40E_VSI_FDIR:
6279 /* no queue mapping or actual HW VSI needed */
6280 vsi->info.valid_sections = 0;
6281 vsi->seid = 0;
6282 vsi->id = 0;
6283 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6284 return 0;
6285 break;
6286
6287 case I40E_VSI_VMDQ2:
6288 ctxt.pf_num = hw->pf_id;
6289 ctxt.vf_num = 0;
6290 ctxt.uplink_seid = vsi->uplink_seid;
6291 ctxt.connection_type = 0x1; /* regular data port */
6292 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6293
6294 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6295
6296 /* This VSI is connected to VEB so the switch_id
6297 * should be set to zero by default.
6298 */
6299 ctxt.info.switch_id = 0;
6300 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6301 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6302
6303 /* Setup the VSI tx/rx queue map for TC0 only for now */
6304 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6305 break;
6306
6307 case I40E_VSI_SRIOV:
6308 ctxt.pf_num = hw->pf_id;
6309 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6310 ctxt.uplink_seid = vsi->uplink_seid;
6311 ctxt.connection_type = 0x1; /* regular data port */
6312 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6313
6314 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6315
6316 /* This VSI is connected to VEB so the switch_id
6317 * should be set to zero by default.
6318 */
6319 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6320
6321 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6322 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6323 /* Setup the VSI tx/rx queue map for TC0 only for now */
6324 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6325 break;
6326
6327 default:
6328 return -ENODEV;
6329 }
6330
6331 if (vsi->type != I40E_VSI_MAIN) {
6332 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6333 if (ret) {
6334 dev_info(&vsi->back->pdev->dev,
6335 "add vsi failed, aq_err=%d\n",
6336 vsi->back->hw.aq.asq_last_status);
6337 ret = -ENOENT;
6338 goto err;
6339 }
6340 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6341 vsi->info.valid_sections = 0;
6342 vsi->seid = ctxt.seid;
6343 vsi->id = ctxt.vsi_number;
6344 }
6345
6346 /* If macvlan filters already exist, force them to get loaded */
6347 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6348 f->changed = true;
6349 f_count++;
6350 }
6351 if (f_count) {
6352 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6353 pf->flags |= I40E_FLAG_FILTER_SYNC;
6354 }
6355
6356 /* Update VSI BW information */
6357 ret = i40e_vsi_get_bw_info(vsi);
6358 if (ret) {
6359 dev_info(&pf->pdev->dev,
6360 "couldn't get vsi bw info, err %d, aq_err %d\n",
6361 ret, pf->hw.aq.asq_last_status);
6362 /* VSI is already added so not tearing that up */
6363 ret = 0;
6364 }
6365
6366err:
6367 return ret;
6368}
6369
6370/**
6371 * i40e_vsi_release - Delete a VSI and free its resources
6372 * @vsi: the VSI being removed
6373 *
6374 * Returns 0 on success or < 0 on error
6375 **/
6376int i40e_vsi_release(struct i40e_vsi *vsi)
6377{
6378 struct i40e_mac_filter *f, *ftmp;
6379 struct i40e_veb *veb = NULL;
6380 struct i40e_pf *pf;
6381 u16 uplink_seid;
6382 int i, n;
6383
6384 pf = vsi->back;
6385
6386 /* release of a VEB-owner or last VSI is not allowed */
6387 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6388 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6389 vsi->seid, vsi->uplink_seid);
6390 return -ENODEV;
6391 }
6392 if (vsi == pf->vsi[pf->lan_vsi] &&
6393 !test_bit(__I40E_DOWN, &pf->state)) {
6394 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6395 return -ENODEV;
6396 }
6397
6398 uplink_seid = vsi->uplink_seid;
6399 if (vsi->type != I40E_VSI_SRIOV) {
6400 if (vsi->netdev_registered) {
6401 vsi->netdev_registered = false;
6402 if (vsi->netdev) {
6403 /* results in a call to i40e_close() */
6404 unregister_netdev(vsi->netdev);
6405 free_netdev(vsi->netdev);
6406 vsi->netdev = NULL;
6407 }
6408 } else {
6409 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6410 i40e_down(vsi);
6411 i40e_vsi_free_irq(vsi);
6412 i40e_vsi_free_tx_resources(vsi);
6413 i40e_vsi_free_rx_resources(vsi);
6414 }
6415 i40e_vsi_disable_irq(vsi);
6416 }
6417
6418 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6419 i40e_del_filter(vsi, f->macaddr, f->vlan,
6420 f->is_vf, f->is_netdev);
6421 i40e_sync_vsi_filters(vsi);
6422
6423 i40e_vsi_delete(vsi);
6424 i40e_vsi_free_q_vectors(vsi);
6425 i40e_vsi_clear_rings(vsi);
6426 i40e_vsi_clear(vsi);
6427
6428 /* If this was the last thing on the VEB, except for the
6429 * controlling VSI, remove the VEB, which puts the controlling
6430 * VSI onto the next level down in the switch.
6431 *
6432 * Well, okay, there's one more exception here: don't remove
6433 * the orphan VEBs yet. We'll wait for an explicit remove request
6434 * from up the network stack.
6435 */
6436 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6437 if (pf->vsi[i] &&
6438 pf->vsi[i]->uplink_seid == uplink_seid &&
6439 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6440 n++; /* count the VSIs */
6441 }
6442 }
6443 for (i = 0; i < I40E_MAX_VEB; i++) {
6444 if (!pf->veb[i])
6445 continue;
6446 if (pf->veb[i]->uplink_seid == uplink_seid)
6447 n++; /* count the VEBs */
6448 if (pf->veb[i]->seid == uplink_seid)
6449 veb = pf->veb[i];
6450 }
6451 if (n == 0 && veb && veb->uplink_seid != 0)
6452 i40e_veb_release(veb);
6453
6454 return 0;
6455}
6456
6457/**
6458 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6459 * @vsi: ptr to the VSI
6460 *
6461 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6462 * corresponding SW VSI structure and initializes num_queue_pairs for the
6463 * newly allocated VSI.
6464 *
6465 * Returns 0 on success or negative on failure
6466 **/
6467static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6468{
6469 int ret = -ENOENT;
6470 struct i40e_pf *pf = vsi->back;
6471
493fb300 6472 if (vsi->q_vectors[0]) {
41c445ff
JB		 6473 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6474 vsi->seid);
6475 return -EEXIST;
6476 }
6477
6478 if (vsi->base_vector) {
6479 dev_info(&pf->pdev->dev,
6480 "VSI %d has non-zero base vector %d\n",
6481 vsi->seid, vsi->base_vector);
6482 return -EEXIST;
6483 }
6484
6485 ret = i40e_alloc_q_vectors(vsi);
6486 if (ret) {
6487 dev_info(&pf->pdev->dev,
6488 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6489 vsi->num_q_vectors, vsi->seid, ret);
6490 vsi->num_q_vectors = 0;
6491 goto vector_setup_out;
6492 }
6493
958a3e3b
SN		 6494 if (vsi->num_q_vectors)
6495 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6496 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6497 if (vsi->base_vector < 0) {
6498 dev_info(&pf->pdev->dev,
6499 "failed to get q tracking for VSI %d, err=%d\n",
6500 vsi->seid, vsi->base_vector);
6501 i40e_vsi_free_q_vectors(vsi);
6502 ret = -ENOENT;
6503 goto vector_setup_out;
6504 }
6505
6506vector_setup_out:
6507 return ret;
6508}
6509
bc7d338f
ASJ		 6510/**
6511 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6512 * @vsi: pointer to the vsi.
6513 *
6514 * This re-allocates a vsi's queue resources.
6515 *
6516 * Returns pointer to the successfully allocated and configured VSI sw struct
6517 * on success, otherwise returns NULL on failure.
6518 **/
6519static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6520{
6521 struct i40e_pf *pf = vsi->back;
6522 u8 enabled_tc;
6523 int ret;
6524
6525 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6526 i40e_vsi_clear_rings(vsi);
6527
6528 i40e_vsi_free_arrays(vsi, false);
6529 i40e_set_num_rings_in_vsi(vsi);
6530 ret = i40e_vsi_alloc_arrays(vsi, false);
6531 if (ret)
6532 goto err_vsi;
6533
6534 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6535 if (ret < 0) {
6536 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6537 vsi->seid, ret);
6538 goto err_vsi;
6539 }
6540 vsi->base_queue = ret;
6541
6542 /* Update the FW view of the VSI. Force a reset of TC and queue
6543 * layout configurations.
6544 */
6545 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6546 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6547 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6548 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6549
6550 /* assign it some queues */
6551 ret = i40e_alloc_rings(vsi);
6552 if (ret)
6553 goto err_rings;
6554
6555 /* map all of the rings to the q_vectors */
6556 i40e_vsi_map_rings_to_vectors(vsi);
6557 return vsi;
6558
6559err_rings:
6560 i40e_vsi_free_q_vectors(vsi);
6561 if (vsi->netdev_registered) {
6562 vsi->netdev_registered = false;
6563 unregister_netdev(vsi->netdev);
6564 free_netdev(vsi->netdev);
6565 vsi->netdev = NULL;
6566 }
6567 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6568err_vsi:
6569 i40e_vsi_clear(vsi);
6570 return NULL;
6571}
6572
41c445ff
JB		 6573/**
6574 * i40e_vsi_setup - Set up a VSI by a given type
6575 * @pf: board private structure
6576 * @type: VSI type
6577 * @uplink_seid: the switch element to link to
6578 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6579 *
6580 * This allocates the sw VSI structure and its queue resources, then add a VSI
6581 * to the identified VEB.
6582 *
6583 * Returns pointer to the successfully allocated and configure VSI sw struct on
6584 * success, otherwise returns NULL on failure.
6585 **/
6586struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6587 u16 uplink_seid, u32 param1)
6588{
6589 struct i40e_vsi *vsi = NULL;
6590 struct i40e_veb *veb = NULL;
6591 int ret, i;
6592 int v_idx;
6593
6594 /* The requested uplink_seid must be either
6595 * - the PF's port seid
6596 * no VEB is needed because this is the PF
6597 * or this is a Flow Director special case VSI
6598 * - seid of an existing VEB
6599 * - seid of a VSI that owns an existing VEB
6600 * - seid of a VSI that doesn't own a VEB
6601 * a new VEB is created and the VSI becomes the owner
6602 * - seid of the PF VSI, which is what creates the first VEB
6603 * this is a special case of the previous
6604 *
6605 * Find which uplink_seid we were given and create a new VEB if needed
6606 */
6607 for (i = 0; i < I40E_MAX_VEB; i++) {
6608 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6609 veb = pf->veb[i];
6610 break;
6611 }
6612 }
6613
6614 if (!veb && uplink_seid != pf->mac_seid) {
6615
6616 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6617 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6618 vsi = pf->vsi[i];
6619 break;
6620 }
6621 }
6622 if (!vsi) {
6623 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6624 uplink_seid);
6625 return NULL;
6626 }
6627
6628 if (vsi->uplink_seid == pf->mac_seid)
6629 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6630 vsi->tc_config.enabled_tc);
6631 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6632 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6633 vsi->tc_config.enabled_tc);
6634
6635 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6636 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6637 veb = pf->veb[i];
6638 }
6639 if (!veb) {
6640 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6641 return NULL;
6642 }
6643
6644 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6645 uplink_seid = veb->seid;
6646 }
6647
6648 /* get vsi sw struct */
6649 v_idx = i40e_vsi_mem_alloc(pf, type);
6650 if (v_idx < 0)
6651 goto err_alloc;
6652 vsi = pf->vsi[v_idx];
6653 vsi->type = type;
6654 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
6655
6656 if (type == I40E_VSI_MAIN)
6657 pf->lan_vsi = v_idx;
6658 else if (type == I40E_VSI_SRIOV)
6659 vsi->vf_id = param1;
6660 /* assign it some queues */
6661 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6662 if (ret < 0) {
6663 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6664 vsi->seid, ret);
6665 goto err_vsi;
6666 }
6667 vsi->base_queue = ret;
6668
6669 /* get a VSI from the hardware */
6670 vsi->uplink_seid = uplink_seid;
6671 ret = i40e_add_vsi(vsi);
6672 if (ret)
6673 goto err_vsi;
6674
6675 switch (vsi->type) {
6676 /* setup the netdev if needed */
6677 case I40E_VSI_MAIN:
6678 case I40E_VSI_VMDQ2:
6679 ret = i40e_config_netdev(vsi);
6680 if (ret)
6681 goto err_netdev;
6682 ret = register_netdev(vsi->netdev);
6683 if (ret)
6684 goto err_netdev;
6685 vsi->netdev_registered = true;
6686 netif_carrier_off(vsi->netdev);
6687 /* fall through */
6688
6689 case I40E_VSI_FDIR:
6690 /* set up vectors and rings if needed */
6691 ret = i40e_vsi_setup_vectors(vsi);
6692 if (ret)
6693 goto err_msix;
6694
6695 ret = i40e_alloc_rings(vsi);
6696 if (ret)
6697 goto err_rings;
6698
6699 /* map all of the rings to the q_vectors */
6700 i40e_vsi_map_rings_to_vectors(vsi);
6701
6702 i40e_vsi_reset_stats(vsi);
6703 break;
6704
6705 default:
6706 /* no netdev or rings for the other VSI types */
6707 break;
6708 }
6709
6710 return vsi;
6711
6712err_rings:
6713 i40e_vsi_free_q_vectors(vsi);
6714err_msix:
6715 if (vsi->netdev_registered) {
6716 vsi->netdev_registered = false;
6717 unregister_netdev(vsi->netdev);
6718 free_netdev(vsi->netdev);
6719 vsi->netdev = NULL;
6720 }
6721err_netdev:
6722 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6723err_vsi:
6724 i40e_vsi_clear(vsi);
6725err_alloc:
6726 return NULL;
6727}
6728
6729/**
6730 * i40e_veb_get_bw_info - Query VEB BW information
6731 * @veb: the veb to query
6732 *
6733 * Query the Tx scheduler BW configuration data for given VEB
6734 **/
6735static int i40e_veb_get_bw_info(struct i40e_veb *veb)
6736{
6737 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
6738 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
6739 struct i40e_pf *pf = veb->pf;
6740 struct i40e_hw *hw = &pf->hw;
6741 u32 tc_bw_max;
6742 int ret = 0;
6743 int i;
6744
6745 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
6746 &bw_data, NULL);
6747 if (ret) {
6748 dev_info(&pf->pdev->dev,
6749 "query veb bw config failed, aq_err=%d\n",
6750 hw->aq.asq_last_status);
6751 goto out;
6752 }
6753
6754 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
6755 &ets_data, NULL);
6756 if (ret) {
6757 dev_info(&pf->pdev->dev,
6758 "query veb bw ets config failed, aq_err=%d\n",
6759 hw->aq.asq_last_status);
6760 goto out;
6761 }
6762
6763 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
6764 veb->bw_max_quanta = ets_data.tc_bw_max;
6765 veb->is_abs_credits = bw_data.absolute_credits_enable;
6766 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
6767 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
6768 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6769 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
6770 veb->bw_tc_limit_credits[i] =
6771 le16_to_cpu(bw_data.tc_bw_limits[i]);
6772 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
6773 }
6774
6775out:
6776 return ret;
6777}
6778
6779/**
6780 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
6781 * @pf: board private structure
6782 *
6783 * On error: returns error code (negative)
6784 * On success: returns vsi index in PF (positive)
6785 **/
6786static int i40e_veb_mem_alloc(struct i40e_pf *pf)
6787{
6788 int ret = -ENOENT;
6789 struct i40e_veb *veb;
6790 int i;
6791
6792 /* Need to protect the allocation of switch elements at the PF level */
6793 mutex_lock(&pf->switch_mutex);
6794
6795 /* VEB list may be fragmented if VEB creation/destruction has
6796 * been happening. We can afford to do a quick scan to look
6797 * for any free slots in the list.
6798 *
6799 * find next empty veb slot, looping back around if necessary
6800 */
6801 i = 0;
6802 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
6803 i++;
6804 if (i >= I40E_MAX_VEB) {
6805 ret = -ENOMEM;
6806 goto err_alloc_veb; /* out of VEB slots! */
6807 }
6808
6809 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
6810 if (!veb) {
6811 ret = -ENOMEM;
6812 goto err_alloc_veb;
6813 }
6814 veb->pf = pf;
6815 veb->idx = i;
6816 veb->enabled_tc = 1;
6817
6818 pf->veb[i] = veb;
6819 ret = i;
6820err_alloc_veb:
6821 mutex_unlock(&pf->switch_mutex);
6822 return ret;
6823}
6824
6825/**
6826 * i40e_switch_branch_release - Delete a branch of the switch tree
6827 * @branch: where to start deleting
6828 *
6829 * This uses recursion to find the tips of the branch to be
6830 * removed, deleting until we get back to and can delete this VEB.
6831 **/
6832static void i40e_switch_branch_release(struct i40e_veb *branch)
6833{
6834 struct i40e_pf *pf = branch->pf;
6835 u16 branch_seid = branch->seid;
6836 u16 veb_idx = branch->idx;
6837 int i;
6838
6839 /* release any VEBs on this VEB - RECURSION */
6840 for (i = 0; i < I40E_MAX_VEB; i++) {
6841 if (!pf->veb[i])
6842 continue;
6843 if (pf->veb[i]->uplink_seid == branch->seid)
6844 i40e_switch_branch_release(pf->veb[i]);
6845 }
6846
6847 /* Release the VSIs on this VEB, but not the owner VSI.
6848 *
6849 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
6850 * the VEB itself, so don't use (*branch) after this loop.
6851 */
6852 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6853 if (!pf->vsi[i])
6854 continue;
6855 if (pf->vsi[i]->uplink_seid == branch_seid &&
6856 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6857 i40e_vsi_release(pf->vsi[i]);
6858 }
6859 }
6860
6861 /* There's one corner case where the VEB might not have been
6862 * removed, so double check it here and remove it if needed.
6863 * This case happens if the veb was created from the debugfs
6864 * commands and no VSIs were added to it.
6865 */
6866 if (pf->veb[veb_idx])
6867 i40e_veb_release(pf->veb[veb_idx]);
6868}
6869
6870/**
6871 * i40e_veb_clear - remove veb struct
6872 * @veb: the veb to remove
6873 **/
6874static void i40e_veb_clear(struct i40e_veb *veb)
6875{
6876 if (!veb)
6877 return;
6878
6879 if (veb->pf) {
6880 struct i40e_pf *pf = veb->pf;
6881
6882 mutex_lock(&pf->switch_mutex);
6883 if (pf->veb[veb->idx] == veb)
6884 pf->veb[veb->idx] = NULL;
6885 mutex_unlock(&pf->switch_mutex);
6886 }
6887
6888 kfree(veb);
6889}
6890
6891/**
6892 * i40e_veb_release - Delete a VEB and free its resources
6893 * @veb: the VEB being removed
6894 **/
6895void i40e_veb_release(struct i40e_veb *veb)
6896{
6897 struct i40e_vsi *vsi = NULL;
6898 struct i40e_pf *pf;
6899 int i, n = 0;
6900
6901 pf = veb->pf;
6902
6903 /* find the remaining VSI and check for extras */
6904 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6905 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
6906 n++;
6907 vsi = pf->vsi[i];
6908 }
6909 }
6910 if (n != 1) {
6911 dev_info(&pf->pdev->dev,
6912 "can't remove VEB %d with %d VSIs left\n",
6913 veb->seid, n);
6914 return;
6915 }
6916
6917 /* move the remaining VSI to uplink veb */
6918 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
6919 if (veb->uplink_seid) {
6920 vsi->uplink_seid = veb->uplink_seid;
6921 if (veb->uplink_seid == pf->mac_seid)
6922 vsi->veb_idx = I40E_NO_VEB;
6923 else
6924 vsi->veb_idx = veb->veb_idx;
6925 } else {
6926 /* floating VEB */
6927 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6928 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
6929 }
6930
6931 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
6932 i40e_veb_clear(veb);
6933
6934 return;
6935}
6936
6937/**
6938 * i40e_add_veb - create the VEB in the switch
6939 * @veb: the VEB to be instantiated
6940 * @vsi: the controlling VSI
6941 **/
6942static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
6943{
56747264 6944 bool is_default = false;
e1c51b95 6945 bool is_cloud = false;
41c445ff
JB		 6946 int ret;
6947
6948 /* get a VEB from the hardware */
6949 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 6950 veb->enabled_tc, is_default,
6951 is_cloud, &veb->seid, NULL);
41c445ff
JB		 6952 if (ret) {
6953 dev_info(&veb->pf->pdev->dev,
6954 "couldn't add VEB, err %d, aq_err %d\n",
6955 ret, veb->pf->hw.aq.asq_last_status);
6956 return -EPERM;
6957 }
6958
6959 /* get statistics counter */
6960 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
6961 &veb->stats_idx, NULL, NULL, NULL);
6962 if (ret) {
6963 dev_info(&veb->pf->pdev->dev,
6964 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
6965 ret, veb->pf->hw.aq.asq_last_status);
6966 return -EPERM;
6967 }
6968 ret = i40e_veb_get_bw_info(veb);
6969 if (ret) {
6970 dev_info(&veb->pf->pdev->dev,
6971 "couldn't get VEB bw info, err %d, aq_err %d\n",
6972 ret, veb->pf->hw.aq.asq_last_status);
6973 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
6974 return -ENOENT;
6975 }
6976
6977 vsi->uplink_seid = veb->seid;
6978 vsi->veb_idx = veb->idx;
6979 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6980
6981 return 0;
6982}
6983
6984/**
6985 * i40e_veb_setup - Set up a VEB
6986 * @pf: board private structure
6987 * @flags: VEB setup flags
6988 * @uplink_seid: the switch element to link to
6989 * @vsi_seid: the initial VSI seid
6990 * @enabled_tc: Enabled TC bit-map
6991 *
6992 * This allocates the sw VEB structure and links it into the switch
6993 * It is possible and legal for this to be a duplicate of an already
6994 * existing VEB. It is also possible for both uplink and vsi seids
6995 * to be zero, in order to create a floating VEB.
6996 *
6997 * Returns pointer to the successfully allocated VEB sw struct on
6998 * success, otherwise returns NULL on failure.
6999 **/
7000struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7001 u16 uplink_seid, u16 vsi_seid,
7002 u8 enabled_tc)
7003{
7004 struct i40e_veb *veb, *uplink_veb = NULL;
7005 int vsi_idx, veb_idx;
7006 int ret;
7007
7008 /* if one seid is 0, the other must be 0 to create a floating relay */
7009 if ((uplink_seid == 0 || vsi_seid == 0) &&
7010 (uplink_seid + vsi_seid != 0)) {
7011 dev_info(&pf->pdev->dev,
7012 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7013 uplink_seid, vsi_seid);
7014 return NULL;
7015 }
7016
7017 /* make sure there is such a vsi and uplink */
7018 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7019 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7020 break;
7021 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7022 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7023 vsi_seid);
7024 return NULL;
7025 }
7026
7027 if (uplink_seid && uplink_seid != pf->mac_seid) {
7028 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7029 if (pf->veb[veb_idx] &&
7030 pf->veb[veb_idx]->seid == uplink_seid) {
7031 uplink_veb = pf->veb[veb_idx];
7032 break;
7033 }
7034 }
7035 if (!uplink_veb) {
7036 dev_info(&pf->pdev->dev,
7037 "uplink seid %d not found\n", uplink_seid);
7038 return NULL;
7039 }
7040 }
7041
7042 /* get veb sw struct */
7043 veb_idx = i40e_veb_mem_alloc(pf);
7044 if (veb_idx < 0)
7045 goto err_alloc;
7046 veb = pf->veb[veb_idx];
7047 veb->flags = flags;
7048 veb->uplink_seid = uplink_seid;
7049 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7050 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7051
7052 /* create the VEB in the switch */
7053 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7054 if (ret)
7055 goto err_veb;
7056
7057 return veb;
7058
7059err_veb:
7060 i40e_veb_clear(veb);
7061err_alloc:
7062 return NULL;
7063}
7064
7065/**
7066 * i40e_setup_pf_switch_element - set pf vars based on switch type
7067 * @pf: board private structure
7068 * @ele: element we are building info from
7069 * @num_reported: total number of elements
7070 * @printconfig: should we print the contents
7071 *
7072 * helper function to assist in extracting a few useful SEID values.
7073 **/
7074static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7075 struct i40e_aqc_switch_config_element_resp *ele,
7076 u16 num_reported, bool printconfig)
7077{
7078 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7079 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7080 u8 element_type = ele->element_type;
7081 u16 seid = le16_to_cpu(ele->seid);
7082
7083 if (printconfig)
7084 dev_info(&pf->pdev->dev,
7085 "type=%d seid=%d uplink=%d downlink=%d\n",
7086 element_type, seid, uplink_seid, downlink_seid);
7087
7088 switch (element_type) {
7089 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7090 pf->mac_seid = seid;
7091 break;
7092 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7093 /* Main VEB? */
7094 if (uplink_seid != pf->mac_seid)
7095 break;
7096 if (pf->lan_veb == I40E_NO_VEB) {
7097 int v;
7098
7099 /* find existing or else empty VEB */
7100 for (v = 0; v < I40E_MAX_VEB; v++) {
7101 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7102 pf->lan_veb = v;
7103 break;
7104 }
7105 }
7106 if (pf->lan_veb == I40E_NO_VEB) {
7107 v = i40e_veb_mem_alloc(pf);
7108 if (v < 0)
7109 break;
7110 pf->lan_veb = v;
7111 }
7112 }
7113
7114 pf->veb[pf->lan_veb]->seid = seid;
7115 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7116 pf->veb[pf->lan_veb]->pf = pf;
7117 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7118 break;
7119 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7120 if (num_reported != 1)
7121 break;
7122 /* This is immediately after a reset so we can assume this is
7123 * the PF's VSI
7124 */
7125 pf->mac_seid = uplink_seid;
7126 pf->pf_seid = downlink_seid;
7127 pf->main_vsi_seid = seid;
7128 if (printconfig)
7129 dev_info(&pf->pdev->dev,
7130 "pf_seid=%d main_vsi_seid=%d\n",
7131 pf->pf_seid, pf->main_vsi_seid);
7132 break;
7133 case I40E_SWITCH_ELEMENT_TYPE_PF:
7134 case I40E_SWITCH_ELEMENT_TYPE_VF:
7135 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7136 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7137 case I40E_SWITCH_ELEMENT_TYPE_PE:
7138 case I40E_SWITCH_ELEMENT_TYPE_PA:
7139 /* ignore these for now */
7140 break;
7141 default:
7142 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7143 element_type, seid);
7144 break;
7145 }
7146}
7147
7148/**
7149 * i40e_fetch_switch_configuration - Get switch config from firmware
7150 * @pf: board private structure
7151 * @printconfig: should we print the contents
7152 *
7153 * Get the current switch configuration from the device and
7154 * extract a few useful SEID values.
7155 **/
7156int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7157{
7158 struct i40e_aqc_get_switch_config_resp *sw_config;
7159 u16 next_seid = 0;
7160 int ret = 0;
7161 u8 *aq_buf;
7162 int i;
7163
7164 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7165 if (!aq_buf)
7166 return -ENOMEM;
7167
7168 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7169 do {
7170 u16 num_reported, num_total;
7171
7172 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7173 I40E_AQ_LARGE_BUF,
7174 &next_seid, NULL);
7175 if (ret) {
7176 dev_info(&pf->pdev->dev,
7177 "get switch config failed %d aq_err=%x\n",
7178 ret, pf->hw.aq.asq_last_status);
7179 kfree(aq_buf);
7180 return -ENOENT;
7181 }
7182
7183 num_reported = le16_to_cpu(sw_config->header.num_reported);
7184 num_total = le16_to_cpu(sw_config->header.num_total);
7185
7186 if (printconfig)
7187 dev_info(&pf->pdev->dev,
7188 "header: %d reported %d total\n",
7189 num_reported, num_total);
7190
7191 if (num_reported) {
7192 int sz = sizeof(*sw_config) * num_reported;
7193
7194 kfree(pf->sw_config);
7195 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7196 if (pf->sw_config)
7197 memcpy(pf->sw_config, sw_config, sz);
7198 }
7199
7200 for (i = 0; i < num_reported; i++) {
7201 struct i40e_aqc_switch_config_element_resp *ele =
7202 &sw_config->element[i];
7203
7204 i40e_setup_pf_switch_element(pf, ele, num_reported,
7205 printconfig);
7206 }
7207 } while (next_seid != 0);
7208
7209 kfree(aq_buf);
7210 return ret;
7211}
7212
7213/**
7214 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7215 * @pf: board private structure
bc7d338f 7216 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7217 *
7218 * Returns 0 on success, negative value on failure
7219 **/
bc7d338f 7220static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7221{
895106a5 7222 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7223 int ret;
7224
7225 /* find out what's out there already */
7226 ret = i40e_fetch_switch_configuration(pf, false);
7227 if (ret) {
7228 dev_info(&pf->pdev->dev,
7229 "couldn't fetch switch config, err %d, aq_err %d\n",
7230 ret, pf->hw.aq.asq_last_status);
7231 return ret;
7232 }
7233 i40e_pf_reset_stats(pf);
7234
7235 /* fdir VSI must happen first to be sure it gets queue 0, but only
7236 * if there is enough room for the fdir VSI
7237 */
7238 if (pf->num_lan_qps > 1)
7239 i40e_fdir_setup(pf);
7240
7241 /* first time setup */
bc7d338f 7242 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7243 struct i40e_vsi *vsi = NULL;
7244 u16 uplink_seid;
7245
7246 /* Set up the PF VSI associated with the PF's main VSI
7247 * that is already in the HW switch
7248 */
7249 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7250 uplink_seid = pf->veb[pf->lan_veb]->seid;
7251 else
7252 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7253 if (pf->lan_vsi == I40E_NO_VSI)
7254 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7255 else if (reinit)
7256 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7257 if (!vsi) {
7258 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7259 i40e_fdir_teardown(pf);
7260 return -EAGAIN;
7261 }
41c445ff
JB		 7262 } else {
7263 /* force a reset of TC and queue layout configurations */
7264 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7265 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7266 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7267 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7268 }
7269 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7270
7271 /* Setup static PF queue filter control settings */
7272 ret = i40e_setup_pf_filter_control(pf);
7273 if (ret) {
7274 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7275 ret);
7276 /* Failure here should not stop continuing other steps */
7277 }
7278
7279 /* enable RSS in the HW, even for only one queue, as the stack can use
7280 * the hash
7281 */
7282 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7283 i40e_config_rss(pf);
7284
7285 /* fill in link information and enable LSE reporting */
7286 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7287 i40e_link_event(pf);
7288
d52c20b7 7289 /* Initialize user-specific link properties */
41c445ff
JB		 7290 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7291 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7292 /* requested_mode is set in probe or by ethtool */
7293 if (!pf->fc_autoneg_status)
7294 goto no_autoneg;
7295
7296 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7297 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7298 pf->hw.fc.current_mode = I40E_FC_FULL;
7299 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7300 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7301 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7302 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7303 else
d52c20b7
JB		 7304 pf->hw.fc.current_mode = I40E_FC_NONE;
7305
7306 /* sync the flow control settings with the auto-neg values */
7307 switch (pf->hw.fc.current_mode) {
7308 case I40E_FC_FULL:
7309 txfc = 1;
7310 rxfc = 1;
7311 break;
7312 case I40E_FC_TX_PAUSE:
7313 txfc = 1;
7314 rxfc = 0;
7315 break;
7316 case I40E_FC_RX_PAUSE:
7317 txfc = 0;
7318 rxfc = 1;
7319 break;
7320 case I40E_FC_NONE:
7321 case I40E_FC_DEFAULT:
7322 txfc = 0;
7323 rxfc = 0;
7324 break;
7325 case I40E_FC_PFC:
7326 /* TBD */
7327 break;
7328 /* no default case, we have to handle all possibilities here */
7329 }
7330
7331 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7332
7333 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7334 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7335 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7336
7337 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7338
d52c20b7
JB		 7339 goto fc_complete;
7340
7341no_autoneg:
7342 /* disable L2 flow control, user can turn it on if they wish */
7343 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7344 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7345 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7346
7347fc_complete:
beb0dff1
JK		 7348 i40e_ptp_init(pf);
7349
41c445ff
JB		 7350 return ret;
7351}
7352
7353/**
7354 * i40e_set_rss_size - helper to set rss_size
7355 * @pf: board private structure
7356 * @queues_left: how many queues
7357 */
7358static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
7359{
7360 int num_tc0;
7361
7362 num_tc0 = min_t(int, queues_left, pf->rss_size_max);
bf051a3b 7363 num_tc0 = min_t(int, num_tc0, num_online_cpus());
41c445ff
JB		 7364 num_tc0 = rounddown_pow_of_two(num_tc0);
7365
7366 return num_tc0;
7367}
7368
7369/**
7370 * i40e_determine_queue_usage - Work out queue distribution
7371 * @pf: board private structure
7372 **/
7373static void i40e_determine_queue_usage(struct i40e_pf *pf)
7374{
7375 int accum_tc_size;
7376 int queues_left;
7377
7378 pf->num_lan_qps = 0;
7379 pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
7380 accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
7381
7382 /* Find the max queues to be put into basic use. We'll always be
7383 * using TC0, whether or not DCB is running, and TC0 will get the
7384 * big RSS set.
7385 */
7386 queues_left = pf->hw.func_caps.num_tx_qp;
7387
9f52987b 7388 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
41c445ff
JB		 7389 !(pf->flags & (I40E_FLAG_RSS_ENABLED |
7390 I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
7391 (queues_left == 1)) {
7392
7393 /* one qp for PF, no queues for anything else */
7394 queues_left = 0;
7395 pf->rss_size = pf->num_lan_qps = 1;
7396
7397 /* make sure all the fancies are disabled */
7398 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 7399 I40E_FLAG_FDIR_ENABLED |
7400 I40E_FLAG_FDIR_ATR_ENABLED |
7401 I40E_FLAG_DCB_ENABLED |
7402 I40E_FLAG_SRIOV_ENABLED |
7403 I40E_FLAG_VMDQ_ENABLED);
7404
7405 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7406 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7407 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7408
7409 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7410
7411 queues_left -= pf->rss_size;
f8ff1464 7412 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7413
7414 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7415 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7416 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7417
7418 /* save num_tc_qps queues for TCs 1 thru 7 and the rest
7419 * are set up for RSS in TC0
7420 */
7421 queues_left -= accum_tc_size;
7422
7423 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7424
7425 queues_left -= pf->rss_size;
7426 if (queues_left < 0) {
7427 dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
7428 return;
7429 }
7430
f8ff1464 7431 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7432
7433 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7434 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7435 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7436
7437 queues_left -= 1; /* save 1 queue for FD */
7438
7439 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7440
7441 queues_left -= pf->rss_size;
7442 if (queues_left < 0) {
7443 dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
7444 return;
7445 }
7446
f8ff1464 7447 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7448
7449 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7450 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7451 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7452
7453 /* save 1 queue for TCs 1 thru 7,
7454 * 1 queue for flow director,
7455 * and the rest are set up for RSS in TC0
7456 */
7457 queues_left -= 1;
7458 queues_left -= accum_tc_size;
7459
7460 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7461 queues_left -= pf->rss_size;
7462 if (queues_left < 0) {
7463 dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
7464 return;
7465 }
7466
f8ff1464 7467 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7468
7469 } else {
7470 dev_info(&pf->pdev->dev,
7471 "Invalid configuration, flags=0x%08llx\n", pf->flags);
7472 return;
7473 }
7474
7475 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7476 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
7477 pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
7478 pf->num_vf_qps));
7479 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7480 }
7481
7482 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7483 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7484 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7485 (queues_left / pf->num_vmdq_qps));
7486 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7487 }
7488
f8ff1464 7489 pf->queues_left = queues_left;
41c445ff
JB		 7490 return;
7491}
7492
7493/**
7494 * i40e_setup_pf_filter_control - Setup PF static filter control
7495 * @pf: PF to be setup
7496 *
7497 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7498 * settings. If PE/FCoE are enabled then it will also set the per PF
7499 * based filter sizes required for them. It also enables Flow director,
7500 * ethertype and macvlan type filter settings for the pf.
7501 *
7502 * Returns 0 on success, negative on failure
7503 **/
7504static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7505{
7506 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7507
7508 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7509
7510 /* Flow Director is enabled */
7511 if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
7512 settings->enable_fdir = true;
7513
7514 /* Ethtype and MACVLAN filters enabled for PF */
7515 settings->enable_ethtype = true;
7516 settings->enable_macvlan = true;
7517
7518 if (i40e_set_filter_control(&pf->hw, settings))
7519 return -ENOENT;
7520
7521 return 0;
7522}
7523
7524/**
7525 * i40e_probe - Device initialization routine
7526 * @pdev: PCI device information struct
7527 * @ent: entry in i40e_pci_tbl
7528 *
7529 * i40e_probe initializes a pf identified by a pci_dev structure.
7530 * The OS initialization, configuring of the pf private structure,
7531 * and a hardware reset occur.
7532 *
7533 * Returns 0 on success, negative on failure
7534 **/
7535static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7536{
7537 struct i40e_driver_version dv;
7538 struct i40e_pf *pf;
7539 struct i40e_hw *hw;
93cd765b 7540 static u16 pfs_found;
d4dfb81a 7541 u16 link_status;
41c445ff
JB		 7542 int err = 0;
7543 u32 len;
7544
7545 err = pci_enable_device_mem(pdev);
7546 if (err)
7547 return err;
7548
7549 /* set up for high or low dma */
7550 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7551 /* coherent mask for the same size will always succeed if
7552 * dma_set_mask does
7553 */
7554 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7555 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7556 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7557 } else {
7558 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7559 err = -EIO;
7560 goto err_dma;
7561 }
7562
7563 /* set up pci connections */
7564 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7565 IORESOURCE_MEM), i40e_driver_name);
7566 if (err) {
7567 dev_info(&pdev->dev,
7568 "pci_request_selected_regions failed %d\n", err);
7569 goto err_pci_reg;
7570 }
7571
7572 pci_enable_pcie_error_reporting(pdev);
7573 pci_set_master(pdev);
7574
7575 /* Now that we have a PCI connection, we need to do the
7576 * low level device setup. This is primarily setting up
7577 * the Admin Queue structures and then querying for the
7578 * device's current profile information.
7579 */
7580 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7581 if (!pf) {
7582 err = -ENOMEM;
7583 goto err_pf_alloc;
7584 }
7585 pf->next_vsi = 0;
7586 pf->pdev = pdev;
7587 set_bit(__I40E_DOWN, &pf->state);
7588
7589 hw = &pf->hw;
7590 hw->back = pf;
7591 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7592 pci_resource_len(pdev, 0));
7593 if (!hw->hw_addr) {
7594 err = -EIO;
7595 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7596 (unsigned int)pci_resource_start(pdev, 0),
7597 (unsigned int)pci_resource_len(pdev, 0), err);
7598 goto err_ioremap;
7599 }
7600 hw->vendor_id = pdev->vendor;
7601 hw->device_id = pdev->device;
7602 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7603 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7604 hw->subsystem_device_id = pdev->subsystem_device;
7605 hw->bus.device = PCI_SLOT(pdev->devfn);
7606 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7607 pf->instance = pfs_found;
41c445ff 7608
7134f9ce
JB		 7609 /* do a special CORER for clearing PXE mode once at init */
7610 if (hw->revision_id == 0 &&
7611 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7612 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7613 i40e_flush(hw);
7614 msleep(200);
7615 pf->corer_count++;
7616
7617 i40e_clear_pxe_mode(hw);
7618 }
7619
41c445ff
JB		 7620 /* Reset here to make sure all is clean and to define PF 'n' */
7621 err = i40e_pf_reset(hw);
7622 if (err) {
7623 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7624 goto err_pf_reset;
7625 }
7626 pf->pfr_count++;
7627
7628 hw->aq.num_arq_entries = I40E_AQ_LEN;
7629 hw->aq.num_asq_entries = I40E_AQ_LEN;
7630 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7631 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7632 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7633 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7634 "%s-pf%d:misc",
7635 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7636
7637 err = i40e_init_shared_code(hw);
7638 if (err) {
7639 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7640 goto err_pf_reset;
7641 }
7642
d52c20b7
JB		 7643 /* set up a default setting for link flow control */
7644 pf->hw.fc.requested_mode = I40E_FC_NONE;
7645
41c445ff
JB		 7646 err = i40e_init_adminq(hw);
7647 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7648 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7649 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7650 dev_info(&pdev->dev,
7651 "warning: NVM version not supported, supported version: %02x.%02x\n",
7652 I40E_CURRENT_NVM_VERSION_HI,
7653 I40E_CURRENT_NVM_VERSION_LO);
7654 }
41c445ff
JB		 7655 if (err) {
7656 dev_info(&pdev->dev,
7657 "init_adminq failed: %d expecting API %02x.%02x\n",
7658 err,
7659 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7660 goto err_pf_reset;
7661 }
7662
6ff4ef86 7663 i40e_clear_pxe_mode(hw);
41c445ff
JB		 7664 err = i40e_get_capabilities(pf);
7665 if (err)
7666 goto err_adminq_setup;
7667
7668 err = i40e_sw_init(pf);
7669 if (err) {
7670 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7671 goto err_sw_init;
7672 }
7673
7674 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7675 hw->func_caps.num_rx_qp,
7676 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7677 if (err) {
7678 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7679 goto err_init_lan_hmc;
7680 }
7681
7682 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7683 if (err) {
7684 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7685 err = -ENOENT;
7686 goto err_configure_lan_hmc;
7687 }
7688
7689 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 7690 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 7691 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7692 err = -EIO;
7693 goto err_mac_addr;
7694 }
7695 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7696 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7697
7698 pci_set_drvdata(pdev, pf);
7699 pci_save_state(pdev);
7700
7701 /* set up periodic task facility */
7702 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7703 pf->service_timer_period = HZ;
7704
7705 INIT_WORK(&pf->service_task, i40e_service_task);
7706 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
7707 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
7708 pf->link_check_timeout = jiffies;
7709
8e2773ae
SN		 7710 /* WoL defaults to disabled */
7711 pf->wol_en = false;
7712 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
7713
41c445ff
JB		 7714 /* set up the main switch operations */
7715 i40e_determine_queue_usage(pf);
7716 i40e_init_interrupt_scheme(pf);
7717
7718 /* Set up the *vsi struct based on the number of VSIs in the HW,
7719 * and set up our local tracking of the MAIN PF vsi.
7720 */
7721 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
7722 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 7723 if (!pf->vsi) {
7724 err = -ENOMEM;
41c445ff 7725 goto err_switch_setup;
ed87ac09 7726 }
41c445ff 7727
bc7d338f 7728 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 7729 if (err) {
7730 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
7731 goto err_vsis;
7732 }
7733
7734 /* The main driver is (mostly) up and happy. We need to set this state
7735 * before setting up the misc vector or we get a race and the vector
7736 * ends up disabled forever.
7737 */
7738 clear_bit(__I40E_DOWN, &pf->state);
7739
7740 /* In case of MSIX we are going to setup the misc vector right here
7741 * to handle admin queue events etc. In case of legacy and MSI
7742 * the misc functionality and queue processing is combined in
7743 * the same vector and that gets setup at open.
7744 */
7745 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7746 err = i40e_setup_misc_vector(pf);
7747 if (err) {
7748 dev_info(&pdev->dev,
7749 "setup of misc vector failed: %d\n", err);
7750 goto err_vsis;
7751 }
7752 }
7753
7754 /* prep for VF support */
7755 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7756 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
7757 u32 val;
7758
7759 /* disable link interrupts for VFs */
7760 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
7761 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
7762 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
7763 i40e_flush(hw);
7764 }
7765
93cd765b
ASJ		 7766 pfs_found++;
7767
41c445ff
JB		 7768 i40e_dbg_pf_init(pf);
7769
7770 /* tell the firmware that we're starting */
7771 dv.major_version = DRV_VERSION_MAJOR;
7772 dv.minor_version = DRV_VERSION_MINOR;
7773 dv.build_version = DRV_VERSION_BUILD;
7774 dv.subbuild_version = 0;
7775 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
7776
7777 /* since everything's happy, start the service_task timer */
7778 mod_timer(&pf->service_timer,
7779 round_jiffies(jiffies + pf->service_timer_period));
7780
d4dfb81a
CS		 7781 /* Get the negotiated link width and speed from PCI config space */
7782 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
7783
7784 i40e_set_pci_config_data(hw, link_status);
7785
7786 dev_info(&pdev->dev, "PCI Express: %s %s\n",
7787 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
7788 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
7789 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
7790 "Unknown"),
7791 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
7792 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
7793 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
7794 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
7795 "Unknown"));
7796
7797 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
7798 hw->bus.speed < i40e_bus_speed_8000) {
7799 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
7800 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
7801 }
7802
41c445ff
JB		 7803 return 0;
7804
7805 /* Unwind what we've done if something failed in the setup */
7806err_vsis:
7807 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 7808 i40e_clear_interrupt_scheme(pf);
7809 kfree(pf->vsi);
04b03013
SN		 7810err_switch_setup:
7811 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 7812 del_timer_sync(&pf->service_timer);
7813err_mac_addr:
7814err_configure_lan_hmc:
7815 (void)i40e_shutdown_lan_hmc(hw);
7816err_init_lan_hmc:
7817 kfree(pf->qp_pile);
7818 kfree(pf->irq_pile);
7819err_sw_init:
7820err_adminq_setup:
7821 (void)i40e_shutdown_adminq(hw);
7822err_pf_reset:
7823 iounmap(hw->hw_addr);
7824err_ioremap:
7825 kfree(pf);
7826err_pf_alloc:
7827 pci_disable_pcie_error_reporting(pdev);
7828 pci_release_selected_regions(pdev,
7829 pci_select_bars(pdev, IORESOURCE_MEM));
7830err_pci_reg:
7831err_dma:
7832 pci_disable_device(pdev);
7833 return err;
7834}
7835
7836/**
7837 * i40e_remove - Device removal routine
7838 * @pdev: PCI device information struct
7839 *
7840 * i40e_remove is called by the PCI subsystem to alert the driver
7841 * that is should release a PCI device. This could be caused by a
7842 * Hot-Plug event, or because the driver is going to be removed from
7843 * memory.
7844 **/
7845static void i40e_remove(struct pci_dev *pdev)
7846{
7847 struct i40e_pf *pf = pci_get_drvdata(pdev);
7848 i40e_status ret_code;
7849 u32 reg;
7850 int i;
7851
7852 i40e_dbg_pf_exit(pf);
7853
beb0dff1
JK		 7854 i40e_ptp_stop(pf);
7855
41c445ff
JB		 7856 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7857 i40e_free_vfs(pf);
7858 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
7859 }
7860
7861 /* no more scheduling of any task */
7862 set_bit(__I40E_DOWN, &pf->state);
7863 del_timer_sync(&pf->service_timer);
7864 cancel_work_sync(&pf->service_task);
7865
7866 i40e_fdir_teardown(pf);
7867
7868 /* If there is a switch structure or any orphans, remove them.
7869 * This will leave only the PF's VSI remaining.
7870 */
7871 for (i = 0; i < I40E_MAX_VEB; i++) {
7872 if (!pf->veb[i])
7873 continue;
7874
7875 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
7876 pf->veb[i]->uplink_seid == 0)
7877 i40e_switch_branch_release(pf->veb[i]);
7878 }
7879
7880 /* Now we can shutdown the PF's VSI, just before we kill
7881 * adminq and hmc.
7882 */
7883 if (pf->vsi[pf->lan_vsi])
7884 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
7885
7886 i40e_stop_misc_vector(pf);
7887 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7888 synchronize_irq(pf->msix_entries[0].vector);
7889 free_irq(pf->msix_entries[0].vector, pf);
7890 }
7891
7892 /* shutdown and destroy the HMC */
7893 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
7894 if (ret_code)
7895 dev_warn(&pdev->dev,
7896 "Failed to destroy the HMC resources: %d\n", ret_code);
7897
7898 /* shutdown the adminq */
41c445ff
JB		 7899 ret_code = i40e_shutdown_adminq(&pf->hw);
7900 if (ret_code)
7901 dev_warn(&pdev->dev,
7902 "Failed to destroy the Admin Queue resources: %d\n",
7903 ret_code);
7904
7905 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
7906 i40e_clear_interrupt_scheme(pf);
7907 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7908 if (pf->vsi[i]) {
7909 i40e_vsi_clear_rings(pf->vsi[i]);
7910 i40e_vsi_clear(pf->vsi[i]);
7911 pf->vsi[i] = NULL;
7912 }
7913 }
7914
7915 for (i = 0; i < I40E_MAX_VEB; i++) {
7916 kfree(pf->veb[i]);
7917 pf->veb[i] = NULL;
7918 }
7919
7920 kfree(pf->qp_pile);
7921 kfree(pf->irq_pile);
7922 kfree(pf->sw_config);
7923 kfree(pf->vsi);
7924
7925 /* force a PF reset to clean anything leftover */
7926 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
7927 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7928 i40e_flush(&pf->hw);
7929
7930 iounmap(pf->hw.hw_addr);
7931 kfree(pf);
7932 pci_release_selected_regions(pdev,
7933 pci_select_bars(pdev, IORESOURCE_MEM));
7934
7935 pci_disable_pcie_error_reporting(pdev);
7936 pci_disable_device(pdev);
7937}
7938
7939/**
7940 * i40e_pci_error_detected - warning that something funky happened in PCI land
7941 * @pdev: PCI device information struct
7942 *
7943 * Called to warn that something happened and the error handling steps
7944 * are in progress. Allows the driver to quiesce things, be ready for
7945 * remediation.
7946 **/
7947static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
7948 enum pci_channel_state error)
7949{
7950 struct i40e_pf *pf = pci_get_drvdata(pdev);
7951
7952 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
7953
7954 /* shutdown all operations */
9007bccd
SN		 7955 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
7956 rtnl_lock();
7957 i40e_prep_for_reset(pf);
7958 rtnl_unlock();
7959 }
41c445ff
JB		 7960
7961 /* Request a slot reset */
7962 return PCI_ERS_RESULT_NEED_RESET;
7963}
7964
7965/**
7966 * i40e_pci_error_slot_reset - a PCI slot reset just happened
7967 * @pdev: PCI device information struct
7968 *
7969 * Called to find if the driver can work with the device now that
7970 * the pci slot has been reset. If a basic connection seems good
7971 * (registers are readable and have sane content) then return a
7972 * happy little PCI_ERS_RESULT_xxx.
7973 **/
7974static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
7975{
7976 struct i40e_pf *pf = pci_get_drvdata(pdev);
7977 pci_ers_result_t result;
7978 int err;
7979 u32 reg;
7980
7981 dev_info(&pdev->dev, "%s\n", __func__);
7982 if (pci_enable_device_mem(pdev)) {
7983 dev_info(&pdev->dev,
7984 "Cannot re-enable PCI device after reset.\n");
7985 result = PCI_ERS_RESULT_DISCONNECT;
7986 } else {
7987 pci_set_master(pdev);
7988 pci_restore_state(pdev);
7989 pci_save_state(pdev);
7990 pci_wake_from_d3(pdev, false);
7991
7992 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7993 if (reg == 0)
7994 result = PCI_ERS_RESULT_RECOVERED;
7995 else
7996 result = PCI_ERS_RESULT_DISCONNECT;
7997 }
7998
7999 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8000 if (err) {
8001 dev_info(&pdev->dev,
8002 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8003 err);
8004 /* non-fatal, continue */
8005 }
8006
8007 return result;
8008}
8009
8010/**
8011 * i40e_pci_error_resume - restart operations after PCI error recovery
8012 * @pdev: PCI device information struct
8013 *
8014 * Called to allow the driver to bring things back up after PCI error
8015 * and/or reset recovery has finished.
8016 **/
8017static void i40e_pci_error_resume(struct pci_dev *pdev)
8018{
8019 struct i40e_pf *pf = pci_get_drvdata(pdev);
8020
8021 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8022 if (test_bit(__I40E_SUSPENDED, &pf->state))
8023 return;
8024
8025 rtnl_lock();
41c445ff 8026 i40e_handle_reset_warning(pf);
9007bccd
SN		 8027 rtnl_lock();
8028}
8029
8030/**
8031 * i40e_shutdown - PCI callback for shutting down
8032 * @pdev: PCI device information struct
8033 **/
8034static void i40e_shutdown(struct pci_dev *pdev)
8035{
8036 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8037 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8038
8039 set_bit(__I40E_SUSPENDED, &pf->state);
8040 set_bit(__I40E_DOWN, &pf->state);
8041 rtnl_lock();
8042 i40e_prep_for_reset(pf);
8043 rtnl_unlock();
8044
8e2773ae
SN		 8045 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8046 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8047
9007bccd 8048 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8049 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8050 pci_set_power_state(pdev, PCI_D3hot);
8051 }
8052}
8053
8054#ifdef CONFIG_PM
8055/**
8056 * i40e_suspend - PCI callback for moving to D3
8057 * @pdev: PCI device information struct
8058 **/
8059static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8060{
8061 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8062 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8063
8064 set_bit(__I40E_SUSPENDED, &pf->state);
8065 set_bit(__I40E_DOWN, &pf->state);
8066 rtnl_lock();
8067 i40e_prep_for_reset(pf);
8068 rtnl_unlock();
8069
8e2773ae
SN		 8070 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8071 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8072
8073 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8074 pci_set_power_state(pdev, PCI_D3hot);
8075
8076 return 0;
41c445ff
JB		 8077}
8078
9007bccd
SN		 8079/**
8080 * i40e_resume - PCI callback for waking up from D3
8081 * @pdev: PCI device information struct
8082 **/
8083static int i40e_resume(struct pci_dev *pdev)
8084{
8085 struct i40e_pf *pf = pci_get_drvdata(pdev);
8086 u32 err;
8087
8088 pci_set_power_state(pdev, PCI_D0);
8089 pci_restore_state(pdev);
8090 /* pci_restore_state() clears dev->state_saves, so
8091 * call pci_save_state() again to restore it.
8092 */
8093 pci_save_state(pdev);
8094
8095 err = pci_enable_device_mem(pdev);
8096 if (err) {
8097 dev_err(&pdev->dev,
8098 "%s: Cannot enable PCI device from suspend\n",
8099 __func__);
8100 return err;
8101 }
8102 pci_set_master(pdev);
8103
8104 /* no wakeup events while running */
8105 pci_wake_from_d3(pdev, false);
8106
8107 /* handling the reset will rebuild the device state */
8108 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8109 clear_bit(__I40E_DOWN, &pf->state);
8110 rtnl_lock();
8111 i40e_reset_and_rebuild(pf, false);
8112 rtnl_unlock();
8113 }
8114
8115 return 0;
8116}
8117
8118#endif
41c445ff
JB		 8119static const struct pci_error_handlers i40e_err_handler = {
8120 .error_detected = i40e_pci_error_detected,
8121 .slot_reset = i40e_pci_error_slot_reset,
8122 .resume = i40e_pci_error_resume,
8123};
8124
8125static struct pci_driver i40e_driver = {
8126 .name = i40e_driver_name,
8127 .id_table = i40e_pci_tbl,
8128 .probe = i40e_probe,
8129 .remove = i40e_remove,
9007bccd
SN		 8130#ifdef CONFIG_PM
8131 .suspend = i40e_suspend,
8132 .resume = i40e_resume,
8133#endif
8134 .shutdown = i40e_shutdown,
41c445ff
JB		 8135 .err_handler = &i40e_err_handler,
8136 .sriov_configure = i40e_pci_sriov_configure,
8137};
8138
8139/**
8140 * i40e_init_module - Driver registration routine
8141 *
8142 * i40e_init_module is the first routine called when the driver is
8143 * loaded. All it does is register with the PCI subsystem.
8144 **/
8145static int __init i40e_init_module(void)
8146{
8147 pr_info("%s: %s - version %s\n", i40e_driver_name,
8148 i40e_driver_string, i40e_driver_version_str);
8149 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8150 i40e_dbg_init();
8151 return pci_register_driver(&i40e_driver);
8152}
8153module_init(i40e_init_module);
8154
8155/**
8156 * i40e_exit_module - Driver exit cleanup routine
8157 *
8158 * i40e_exit_module is called just before the driver is removed
8159 * from memory.
8160 **/
8161static void __exit i40e_exit_module(void)
8162{
8163 pci_unregister_driver(&i40e_driver);
8164 i40e_dbg_exit();
8165}
8166module_exit(i40e_exit_module);
Linux kernel - Deliverables
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