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i40e: Admin queue shutdown fixes
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28/* Local includes */
29#include "i40e.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 3
582a74e5 42#define DRV_VERSION_BUILD 14
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
47static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
58
59/* i40e_pci_tbl - PCI Device ID Table
60 *
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
67 {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
68 {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
69 {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
70 {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
71 {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
72 {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
73 {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
74 {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
75 {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
76 {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
272static void i40e_tx_timeout(struct net_device *netdev)
273{
274 struct i40e_netdev_priv *np = netdev_priv(netdev);
275 struct i40e_vsi *vsi = np->vsi;
276 struct i40e_pf *pf = vsi->back;
277
278 pf->tx_timeout_count++;
279
280 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
281 pf->tx_timeout_recovery_level = 0;
282 pf->tx_timeout_last_recovery = jiffies;
283 netdev_info(netdev, "tx_timeout recovery level %d\n",
284 pf->tx_timeout_recovery_level);
285
286 switch (pf->tx_timeout_recovery_level) {
287 case 0:
288 /* disable and re-enable queues for the VSI */
289 if (in_interrupt()) {
290 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
291 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
292 } else {
293 i40e_vsi_reinit_locked(vsi);
294 }
295 break;
296 case 1:
297 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
298 break;
299 case 2:
300 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
301 break;
302 case 3:
303 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
304 break;
305 default:
306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
307 i40e_down(vsi);
308 break;
309 }
310 i40e_service_event_schedule(pf);
311 pf->tx_timeout_recovery_level++;
312}
313
314/**
315 * i40e_release_rx_desc - Store the new tail and head values
316 * @rx_ring: ring to bump
317 * @val: new head index
318 **/
319static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
320{
321 rx_ring->next_to_use = val;
322
323 /* Force memory writes to complete before letting h/w
324 * know there are new descriptors to fetch. (Only
325 * applicable for weak-ordered memory model archs,
326 * such as IA-64).
327 */
328 wmb();
329 writel(val, rx_ring->tail);
330}
331
332/**
333 * i40e_get_vsi_stats_struct - Get System Network Statistics
334 * @vsi: the VSI we care about
335 *
336 * Returns the address of the device statistics structure.
337 * The statistics are actually updated from the service task.
338 **/
339struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
340{
341 return &vsi->net_stats;
342}
343
344/**
345 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
346 * @netdev: network interface device structure
347 *
348 * Returns the address of the device statistics structure.
349 * The statistics are actually updated from the service task.
350 **/
351static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
352 struct net_device *netdev,
980e9b11 353 struct rtnl_link_stats64 *stats)
41c445ff
JB		 354{
355 struct i40e_netdev_priv *np = netdev_priv(netdev);
356 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 357 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
358 int i;
359
143c9054 360
bc7d338f
ASJ		 361 if (test_bit(__I40E_DOWN, &vsi->state))
362 return stats;
363
3c325ced
JB		 364 if (!vsi->tx_rings)
365 return stats;
366
980e9b11
AD		 367 rcu_read_lock();
368 for (i = 0; i < vsi->num_queue_pairs; i++) {
369 struct i40e_ring *tx_ring, *rx_ring;
370 u64 bytes, packets;
371 unsigned int start;
372
373 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
374 if (!tx_ring)
375 continue;
376
377 do {
378 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
379 packets = tx_ring->stats.packets;
380 bytes = tx_ring->stats.bytes;
381 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
382
383 stats->tx_packets += packets;
384 stats->tx_bytes += bytes;
385 rx_ring = &tx_ring[1];
386
387 do {
388 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
389 packets = rx_ring->stats.packets;
390 bytes = rx_ring->stats.bytes;
391 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 392
980e9b11
AD		 393 stats->rx_packets += packets;
394 stats->rx_bytes += bytes;
395 }
396 rcu_read_unlock();
397
398 /* following stats updated by ixgbe_watchdog_task() */
399 stats->multicast = vsi_stats->multicast;
400 stats->tx_errors = vsi_stats->tx_errors;
401 stats->tx_dropped = vsi_stats->tx_dropped;
402 stats->rx_errors = vsi_stats->rx_errors;
403 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
404 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 405
980e9b11 406 return stats;
41c445ff
JB		 407}
408
409/**
410 * i40e_vsi_reset_stats - Resets all stats of the given vsi
411 * @vsi: the VSI to have its stats reset
412 **/
413void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
414{
415 struct rtnl_link_stats64 *ns;
416 int i;
417
418 if (!vsi)
419 return;
420
421 ns = i40e_get_vsi_stats_struct(vsi);
422 memset(ns, 0, sizeof(*ns));
423 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
424 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
425 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
426 if (vsi->rx_rings)
427 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 428 memset(&vsi->rx_rings[i]->stats, 0 ,
429 sizeof(vsi->rx_rings[i]->stats));
430 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
431 sizeof(vsi->rx_rings[i]->rx_stats));
432 memset(&vsi->tx_rings[i]->stats, 0 ,
433 sizeof(vsi->tx_rings[i]->stats));
434 memset(&vsi->tx_rings[i]->tx_stats, 0,
435 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff
JB		 436 }
437 vsi->stat_offsets_loaded = false;
438}
439
440/**
441 * i40e_pf_reset_stats - Reset all of the stats for the given pf
442 * @pf: the PF to be reset
443 **/
444void i40e_pf_reset_stats(struct i40e_pf *pf)
445{
446 memset(&pf->stats, 0, sizeof(pf->stats));
447 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
448 pf->stat_offsets_loaded = false;
449}
450
451/**
452 * i40e_stat_update48 - read and update a 48 bit stat from the chip
453 * @hw: ptr to the hardware info
454 * @hireg: the high 32 bit reg to read
455 * @loreg: the low 32 bit reg to read
456 * @offset_loaded: has the initial offset been loaded yet
457 * @offset: ptr to current offset value
458 * @stat: ptr to the stat
459 *
460 * Since the device stats are not reset at PFReset, they likely will not
461 * be zeroed when the driver starts. We'll save the first values read
462 * and use them as offsets to be subtracted from the raw values in order
463 * to report stats that count from zero. In the process, we also manage
464 * the potential roll-over.
465 **/
466static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
467 bool offset_loaded, u64 *offset, u64 *stat)
468{
469 u64 new_data;
470
471 if (hw->device_id == I40E_QEMU_DEVICE_ID) {
472 new_data = rd32(hw, loreg);
473 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
474 } else {
475 new_data = rd64(hw, loreg);
476 }
477 if (!offset_loaded)
478 *offset = new_data;
479 if (likely(new_data >= *offset))
480 *stat = new_data - *offset;
481 else
482 *stat = (new_data + ((u64)1 << 48)) - *offset;
483 *stat &= 0xFFFFFFFFFFFFULL;
484}
485
486/**
487 * i40e_stat_update32 - read and update a 32 bit stat from the chip
488 * @hw: ptr to the hardware info
489 * @reg: the hw reg to read
490 * @offset_loaded: has the initial offset been loaded yet
491 * @offset: ptr to current offset value
492 * @stat: ptr to the stat
493 **/
494static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
495 bool offset_loaded, u64 *offset, u64 *stat)
496{
497 u32 new_data;
498
499 new_data = rd32(hw, reg);
500 if (!offset_loaded)
501 *offset = new_data;
502 if (likely(new_data >= *offset))
503 *stat = (u32)(new_data - *offset);
504 else
505 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
506}
507
508/**
509 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
510 * @vsi: the VSI to be updated
511 **/
512void i40e_update_eth_stats(struct i40e_vsi *vsi)
513{
514 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
515 struct i40e_pf *pf = vsi->back;
516 struct i40e_hw *hw = &pf->hw;
517 struct i40e_eth_stats *oes;
518 struct i40e_eth_stats *es; /* device's eth stats */
519
520 es = &vsi->eth_stats;
521 oes = &vsi->eth_stats_offsets;
522
523 /* Gather up the stats that the hw collects */
524 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
525 vsi->stat_offsets_loaded,
526 &oes->tx_errors, &es->tx_errors);
527 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->rx_discards, &es->rx_discards);
530
531 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
532 I40E_GLV_GORCL(stat_idx),
533 vsi->stat_offsets_loaded,
534 &oes->rx_bytes, &es->rx_bytes);
535 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
536 I40E_GLV_UPRCL(stat_idx),
537 vsi->stat_offsets_loaded,
538 &oes->rx_unicast, &es->rx_unicast);
539 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
540 I40E_GLV_MPRCL(stat_idx),
541 vsi->stat_offsets_loaded,
542 &oes->rx_multicast, &es->rx_multicast);
543 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
544 I40E_GLV_BPRCL(stat_idx),
545 vsi->stat_offsets_loaded,
546 &oes->rx_broadcast, &es->rx_broadcast);
547
548 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
549 I40E_GLV_GOTCL(stat_idx),
550 vsi->stat_offsets_loaded,
551 &oes->tx_bytes, &es->tx_bytes);
552 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
553 I40E_GLV_UPTCL(stat_idx),
554 vsi->stat_offsets_loaded,
555 &oes->tx_unicast, &es->tx_unicast);
556 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
557 I40E_GLV_MPTCL(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_multicast, &es->tx_multicast);
560 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
561 I40E_GLV_BPTCL(stat_idx),
562 vsi->stat_offsets_loaded,
563 &oes->tx_broadcast, &es->tx_broadcast);
564 vsi->stat_offsets_loaded = true;
565}
566
567/**
568 * i40e_update_veb_stats - Update Switch component statistics
569 * @veb: the VEB being updated
570 **/
571static void i40e_update_veb_stats(struct i40e_veb *veb)
572{
573 struct i40e_pf *pf = veb->pf;
574 struct i40e_hw *hw = &pf->hw;
575 struct i40e_eth_stats *oes;
576 struct i40e_eth_stats *es; /* device's eth stats */
577 int idx = 0;
578
579 idx = veb->stats_idx;
580 es = &veb->stats;
581 oes = &veb->stats_offsets;
582
583 /* Gather up the stats that the hw collects */
584 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
585 veb->stat_offsets_loaded,
586 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 587 if (hw->revision_id > 0)
588 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
589 veb->stat_offsets_loaded,
590 &oes->rx_unknown_protocol,
591 &es->rx_unknown_protocol);
41c445ff
JB		 592 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
593 veb->stat_offsets_loaded,
594 &oes->rx_bytes, &es->rx_bytes);
595 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_unicast, &es->rx_unicast);
598 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_multicast, &es->rx_multicast);
601 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_broadcast, &es->rx_broadcast);
604
605 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
606 veb->stat_offsets_loaded,
607 &oes->tx_bytes, &es->tx_bytes);
608 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_unicast, &es->tx_unicast);
611 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_multicast, &es->tx_multicast);
614 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_broadcast, &es->tx_broadcast);
617 veb->stat_offsets_loaded = true;
618}
619
620/**
621 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
622 * @pf: the corresponding PF
623 *
624 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
625 **/
626static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
627{
628 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
629 struct i40e_hw_port_stats *nsd = &pf->stats;
630 struct i40e_hw *hw = &pf->hw;
631 u64 xoff = 0;
632 u16 i, v;
633
634 if ((hw->fc.current_mode != I40E_FC_FULL) &&
635 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
636 return;
637
638 xoff = nsd->link_xoff_rx;
639 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
640 pf->stat_offsets_loaded,
641 &osd->link_xoff_rx, &nsd->link_xoff_rx);
642
643 /* No new LFC xoff rx */
644 if (!(nsd->link_xoff_rx - xoff))
645 return;
646
647 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
648 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
649 struct i40e_vsi *vsi = pf->vsi[v];
650
651 if (!vsi)
652 continue;
653
654 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 655 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 656 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
657 }
658 }
659}
660
661/**
662 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
663 * @pf: the corresponding PF
664 *
665 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
666 **/
667static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
668{
669 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
670 struct i40e_hw_port_stats *nsd = &pf->stats;
671 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
672 struct i40e_dcbx_config *dcb_cfg;
673 struct i40e_hw *hw = &pf->hw;
674 u16 i, v;
675 u8 tc;
676
677 dcb_cfg = &hw->local_dcbx_config;
678
679 /* See if DCB enabled with PFC TC */
680 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
681 !(dcb_cfg->pfc.pfcenable)) {
682 i40e_update_link_xoff_rx(pf);
683 return;
684 }
685
686 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
687 u64 prio_xoff = nsd->priority_xoff_rx[i];
688 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
689 pf->stat_offsets_loaded,
690 &osd->priority_xoff_rx[i],
691 &nsd->priority_xoff_rx[i]);
692
693 /* No new PFC xoff rx */
694 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
695 continue;
696 /* Get the TC for given priority */
697 tc = dcb_cfg->etscfg.prioritytable[i];
698 xoff[tc] = true;
699 }
700
701 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
702 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
703 struct i40e_vsi *vsi = pf->vsi[v];
704
705 if (!vsi)
706 continue;
707
708 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 709 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 710
711 tc = ring->dcb_tc;
712 if (xoff[tc])
713 clear_bit(__I40E_HANG_CHECK_ARMED,
714 &ring->state);
715 }
716 }
717}
718
719/**
720 * i40e_update_stats - Update the board statistics counters.
721 * @vsi: the VSI to be updated
722 *
723 * There are a few instances where we store the same stat in a
724 * couple of different structs. This is partly because we have
725 * the netdev stats that need to be filled out, which is slightly
726 * different from the "eth_stats" defined by the chip and used in
727 * VF communications. We sort it all out here in a central place.
728 **/
729void i40e_update_stats(struct i40e_vsi *vsi)
730{
731 struct i40e_pf *pf = vsi->back;
732 struct i40e_hw *hw = &pf->hw;
733 struct rtnl_link_stats64 *ons;
734 struct rtnl_link_stats64 *ns; /* netdev stats */
735 struct i40e_eth_stats *oes;
736 struct i40e_eth_stats *es; /* device's eth stats */
737 u32 tx_restart, tx_busy;
738 u32 rx_page, rx_buf;
739 u64 rx_p, rx_b;
740 u64 tx_p, tx_b;
741 int i;
742 u16 q;
743
744 if (test_bit(__I40E_DOWN, &vsi->state) ||
745 test_bit(__I40E_CONFIG_BUSY, &pf->state))
746 return;
747
748 ns = i40e_get_vsi_stats_struct(vsi);
749 ons = &vsi->net_stats_offsets;
750 es = &vsi->eth_stats;
751 oes = &vsi->eth_stats_offsets;
752
753 /* Gather up the netdev and vsi stats that the driver collects
754 * on the fly during packet processing
755 */
756 rx_b = rx_p = 0;
757 tx_b = tx_p = 0;
758 tx_restart = tx_busy = 0;
759 rx_page = 0;
760 rx_buf = 0;
980e9b11 761 rcu_read_lock();
41c445ff
JB		 762 for (q = 0; q < vsi->num_queue_pairs; q++) {
763 struct i40e_ring *p;
980e9b11
AD		 764 u64 bytes, packets;
765 unsigned int start;
766
767 /* locate Tx ring */
768 p = ACCESS_ONCE(vsi->tx_rings[q]);
769
770 do {
771 start = u64_stats_fetch_begin_bh(&p->syncp);
772 packets = p->stats.packets;
773 bytes = p->stats.bytes;
774 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
775 tx_b += bytes;
776 tx_p += packets;
777 tx_restart += p->tx_stats.restart_queue;
778 tx_busy += p->tx_stats.tx_busy;
41c445ff 779
980e9b11
AD		 780 /* Rx queue is part of the same block as Tx queue */
781 p = &p[1];
782 do {
783 start = u64_stats_fetch_begin_bh(&p->syncp);
784 packets = p->stats.packets;
785 bytes = p->stats.bytes;
786 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
787 rx_b += bytes;
788 rx_p += packets;
41c445ff
JB		 789 rx_buf += p->rx_stats.alloc_rx_buff_failed;
790 rx_page += p->rx_stats.alloc_rx_page_failed;
41c445ff 791 }
980e9b11 792 rcu_read_unlock();
41c445ff
JB		 793 vsi->tx_restart = tx_restart;
794 vsi->tx_busy = tx_busy;
795 vsi->rx_page_failed = rx_page;
796 vsi->rx_buf_failed = rx_buf;
797
798 ns->rx_packets = rx_p;
799 ns->rx_bytes = rx_b;
800 ns->tx_packets = tx_p;
801 ns->tx_bytes = tx_b;
802
803 i40e_update_eth_stats(vsi);
804 /* update netdev stats from eth stats */
805 ons->rx_errors = oes->rx_errors;
806 ns->rx_errors = es->rx_errors;
807 ons->tx_errors = oes->tx_errors;
808 ns->tx_errors = es->tx_errors;
809 ons->multicast = oes->rx_multicast;
810 ns->multicast = es->rx_multicast;
811 ons->tx_dropped = oes->tx_discards;
812 ns->tx_dropped = es->tx_discards;
813
814 /* Get the port data only if this is the main PF VSI */
815 if (vsi == pf->vsi[pf->lan_vsi]) {
816 struct i40e_hw_port_stats *nsd = &pf->stats;
817 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
818
819 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
820 I40E_GLPRT_GORCL(hw->port),
821 pf->stat_offsets_loaded,
822 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
823 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
824 I40E_GLPRT_GOTCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
827 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
828 pf->stat_offsets_loaded,
829 &osd->eth.rx_discards,
830 &nsd->eth.rx_discards);
831 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.tx_discards,
834 &nsd->eth.tx_discards);
835 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
836 I40E_GLPRT_MPRCL(hw->port),
837 pf->stat_offsets_loaded,
838 &osd->eth.rx_multicast,
839 &nsd->eth.rx_multicast);
840
841 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
842 pf->stat_offsets_loaded,
843 &osd->tx_dropped_link_down,
844 &nsd->tx_dropped_link_down);
845
846 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
847 pf->stat_offsets_loaded,
848 &osd->crc_errors, &nsd->crc_errors);
849 ns->rx_crc_errors = nsd->crc_errors;
850
851 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
852 pf->stat_offsets_loaded,
853 &osd->illegal_bytes, &nsd->illegal_bytes);
854 ns->rx_errors = nsd->crc_errors
855 + nsd->illegal_bytes;
856
857 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
858 pf->stat_offsets_loaded,
859 &osd->mac_local_faults,
860 &nsd->mac_local_faults);
861 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_remote_faults,
864 &nsd->mac_remote_faults);
865
866 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
867 pf->stat_offsets_loaded,
868 &osd->rx_length_errors,
869 &nsd->rx_length_errors);
870 ns->rx_length_errors = nsd->rx_length_errors;
871
872 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->link_xon_rx, &nsd->link_xon_rx);
875 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
876 pf->stat_offsets_loaded,
877 &osd->link_xon_tx, &nsd->link_xon_tx);
878 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
879 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xoff_tx, &nsd->link_xoff_tx);
882
883 for (i = 0; i < 8; i++) {
884 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
885 pf->stat_offsets_loaded,
886 &osd->priority_xon_rx[i],
887 &nsd->priority_xon_rx[i]);
888 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_tx[i],
891 &nsd->priority_xon_tx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xoff_tx[i],
895 &nsd->priority_xoff_tx[i]);
896 i40e_stat_update32(hw,
897 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
898 pf->stat_offsets_loaded,
899 &osd->priority_xon_2_xoff[i],
900 &nsd->priority_xon_2_xoff[i]);
901 }
902
903 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
904 I40E_GLPRT_PRC64L(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->rx_size_64, &nsd->rx_size_64);
907 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
908 I40E_GLPRT_PRC127L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_127, &nsd->rx_size_127);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
912 I40E_GLPRT_PRC255L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_255, &nsd->rx_size_255);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
916 I40E_GLPRT_PRC511L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_511, &nsd->rx_size_511);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
920 I40E_GLPRT_PRC1023L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_1023, &nsd->rx_size_1023);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
924 I40E_GLPRT_PRC1522L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1522, &nsd->rx_size_1522);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
928 I40E_GLPRT_PRC9522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_big, &nsd->rx_size_big);
931
932 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
933 I40E_GLPRT_PTC64L(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->tx_size_64, &nsd->tx_size_64);
936 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
937 I40E_GLPRT_PTC127L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_127, &nsd->tx_size_127);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
941 I40E_GLPRT_PTC255L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_255, &nsd->tx_size_255);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
945 I40E_GLPRT_PTC511L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_511, &nsd->tx_size_511);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
949 I40E_GLPRT_PTC1023L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_1023, &nsd->tx_size_1023);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
953 I40E_GLPRT_PTC1522L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1522, &nsd->tx_size_1522);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
957 I40E_GLPRT_PTC9522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_big, &nsd->tx_size_big);
960
961 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->rx_undersize, &nsd->rx_undersize);
964 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->rx_fragments, &nsd->rx_fragments);
967 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->rx_oversize, &nsd->rx_oversize);
970 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_jabber, &nsd->rx_jabber);
973 }
974
975 pf->stat_offsets_loaded = true;
976}
977
978/**
979 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
980 * @vsi: the VSI to be searched
981 * @macaddr: the MAC address
982 * @vlan: the vlan
983 * @is_vf: make sure its a vf filter, else doesn't matter
984 * @is_netdev: make sure its a netdev filter, else doesn't matter
985 *
986 * Returns ptr to the filter object or NULL
987 **/
988static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
989 u8 *macaddr, s16 vlan,
990 bool is_vf, bool is_netdev)
991{
992 struct i40e_mac_filter *f;
993
994 if (!vsi || !macaddr)
995 return NULL;
996
997 list_for_each_entry(f, &vsi->mac_filter_list, list) {
998 if ((ether_addr_equal(macaddr, f->macaddr)) &&
999 (vlan == f->vlan) &&
1000 (!is_vf || f->is_vf) &&
1001 (!is_netdev || f->is_netdev))
1002 return f;
1003 }
1004 return NULL;
1005}
1006
1007/**
1008 * i40e_find_mac - Find a mac addr in the macvlan filters list
1009 * @vsi: the VSI to be searched
1010 * @macaddr: the MAC address we are searching for
1011 * @is_vf: make sure its a vf filter, else doesn't matter
1012 * @is_netdev: make sure its a netdev filter, else doesn't matter
1013 *
1014 * Returns the first filter with the provided MAC address or NULL if
1015 * MAC address was not found
1016 **/
1017struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1018 bool is_vf, bool is_netdev)
1019{
1020 struct i40e_mac_filter *f;
1021
1022 if (!vsi || !macaddr)
1023 return NULL;
1024
1025 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1026 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1027 (!is_vf || f->is_vf) &&
1028 (!is_netdev || f->is_netdev))
1029 return f;
1030 }
1031 return NULL;
1032}
1033
1034/**
1035 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1036 * @vsi: the VSI to be searched
1037 *
1038 * Returns true if VSI is in vlan mode or false otherwise
1039 **/
1040bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1041{
1042 struct i40e_mac_filter *f;
1043
1044 /* Only -1 for all the filters denotes not in vlan mode
1045 * so we have to go through all the list in order to make sure
1046 */
1047 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1048 if (f->vlan >= 0)
1049 return true;
1050 }
1051
1052 return false;
1053}
1054
1055/**
1056 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1057 * @vsi: the VSI to be searched
1058 * @macaddr: the mac address to be filtered
1059 * @is_vf: true if it is a vf
1060 * @is_netdev: true if it is a netdev
1061 *
1062 * Goes through all the macvlan filters and adds a
1063 * macvlan filter for each unique vlan that already exists
1064 *
1065 * Returns first filter found on success, else NULL
1066 **/
1067struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1068 bool is_vf, bool is_netdev)
1069{
1070 struct i40e_mac_filter *f;
1071
1072 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1073 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1074 is_vf, is_netdev)) {
1075 if (!i40e_add_filter(vsi, macaddr, f->vlan,
1076 is_vf, is_netdev))
1077 return NULL;
1078 }
1079 }
1080
1081 return list_first_entry_or_null(&vsi->mac_filter_list,
1082 struct i40e_mac_filter, list);
1083}
1084
1085/**
1086 * i40e_add_filter - Add a mac/vlan filter to the VSI
1087 * @vsi: the VSI to be searched
1088 * @macaddr: the MAC address
1089 * @vlan: the vlan
1090 * @is_vf: make sure its a vf filter, else doesn't matter
1091 * @is_netdev: make sure its a netdev filter, else doesn't matter
1092 *
1093 * Returns ptr to the filter object or NULL when no memory available.
1094 **/
1095struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1096 u8 *macaddr, s16 vlan,
1097 bool is_vf, bool is_netdev)
1098{
1099 struct i40e_mac_filter *f;
1100
1101 if (!vsi || !macaddr)
1102 return NULL;
1103
1104 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1105 if (!f) {
1106 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1107 if (!f)
1108 goto add_filter_out;
1109
1110 memcpy(f->macaddr, macaddr, ETH_ALEN);
1111 f->vlan = vlan;
1112 f->changed = true;
1113
1114 INIT_LIST_HEAD(&f->list);
1115 list_add(&f->list, &vsi->mac_filter_list);
1116 }
1117
1118 /* increment counter and add a new flag if needed */
1119 if (is_vf) {
1120 if (!f->is_vf) {
1121 f->is_vf = true;
1122 f->counter++;
1123 }
1124 } else if (is_netdev) {
1125 if (!f->is_netdev) {
1126 f->is_netdev = true;
1127 f->counter++;
1128 }
1129 } else {
1130 f->counter++;
1131 }
1132
1133 /* changed tells sync_filters_subtask to
1134 * push the filter down to the firmware
1135 */
1136 if (f->changed) {
1137 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1138 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1139 }
1140
1141add_filter_out:
1142 return f;
1143}
1144
1145/**
1146 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1147 * @vsi: the VSI to be searched
1148 * @macaddr: the MAC address
1149 * @vlan: the vlan
1150 * @is_vf: make sure it's a vf filter, else doesn't matter
1151 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1152 **/
1153void i40e_del_filter(struct i40e_vsi *vsi,
1154 u8 *macaddr, s16 vlan,
1155 bool is_vf, bool is_netdev)
1156{
1157 struct i40e_mac_filter *f;
1158
1159 if (!vsi || !macaddr)
1160 return;
1161
1162 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1163 if (!f || f->counter == 0)
1164 return;
1165
1166 if (is_vf) {
1167 if (f->is_vf) {
1168 f->is_vf = false;
1169 f->counter--;
1170 }
1171 } else if (is_netdev) {
1172 if (f->is_netdev) {
1173 f->is_netdev = false;
1174 f->counter--;
1175 }
1176 } else {
1177 /* make sure we don't remove a filter in use by vf or netdev */
1178 int min_f = 0;
1179 min_f += (f->is_vf ? 1 : 0);
1180 min_f += (f->is_netdev ? 1 : 0);
1181
1182 if (f->counter > min_f)
1183 f->counter--;
1184 }
1185
1186 /* counter == 0 tells sync_filters_subtask to
1187 * remove the filter from the firmware's list
1188 */
1189 if (f->counter == 0) {
1190 f->changed = true;
1191 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1192 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1193 }
1194}
1195
1196/**
1197 * i40e_set_mac - NDO callback to set mac address
1198 * @netdev: network interface device structure
1199 * @p: pointer to an address structure
1200 *
1201 * Returns 0 on success, negative on failure
1202 **/
1203static int i40e_set_mac(struct net_device *netdev, void *p)
1204{
1205 struct i40e_netdev_priv *np = netdev_priv(netdev);
1206 struct i40e_vsi *vsi = np->vsi;
1207 struct sockaddr *addr = p;
1208 struct i40e_mac_filter *f;
1209
1210 if (!is_valid_ether_addr(addr->sa_data))
1211 return -EADDRNOTAVAIL;
1212
1213 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1214
1215 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1216 return 0;
1217
1218 if (vsi->type == I40E_VSI_MAIN) {
1219 i40e_status ret;
1220 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1221 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1222 addr->sa_data, NULL);
1223 if (ret) {
1224 netdev_info(netdev,
1225 "Addr change for Main VSI failed: %d\n",
1226 ret);
1227 return -EADDRNOTAVAIL;
1228 }
1229
1230 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1231 }
1232
1233 /* In order to be sure to not drop any packets, add the new address
1234 * then delete the old one.
1235 */
1236 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1237 if (!f)
1238 return -ENOMEM;
1239
1240 i40e_sync_vsi_filters(vsi);
1241 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1242 i40e_sync_vsi_filters(vsi);
1243
1244 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1245
1246 return 0;
1247}
1248
1249/**
1250 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1251 * @vsi: the VSI being setup
1252 * @ctxt: VSI context structure
1253 * @enabled_tc: Enabled TCs bitmap
1254 * @is_add: True if called before Add VSI
1255 *
1256 * Setup VSI queue mapping for enabled traffic classes.
1257 **/
1258static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1259 struct i40e_vsi_context *ctxt,
1260 u8 enabled_tc,
1261 bool is_add)
1262{
1263 struct i40e_pf *pf = vsi->back;
1264 u16 sections = 0;
1265 u8 netdev_tc = 0;
1266 u16 numtc = 0;
1267 u16 qcount;
1268 u8 offset;
1269 u16 qmap;
1270 int i;
1271
1272 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1273 offset = 0;
1274
1275 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1276 /* Find numtc from enabled TC bitmap */
1277 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1278 if (enabled_tc & (1 << i)) /* TC is enabled */
1279 numtc++;
1280 }
1281 if (!numtc) {
1282 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1283 numtc = 1;
1284 }
1285 } else {
1286 /* At least TC0 is enabled in case of non-DCB case */
1287 numtc = 1;
1288 }
1289
1290 vsi->tc_config.numtc = numtc;
1291 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1292
1293 /* Setup queue offset/count for all TCs for given VSI */
1294 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1295 /* See if the given TC is enabled for the given VSI */
1296 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1297 int pow, num_qps;
1298
1299 vsi->tc_config.tc_info[i].qoffset = offset;
1300 switch (vsi->type) {
1301 case I40E_VSI_MAIN:
1302 if (i == 0)
1303 qcount = pf->rss_size;
1304 else
1305 qcount = pf->num_tc_qps;
1306 vsi->tc_config.tc_info[i].qcount = qcount;
1307 break;
1308 case I40E_VSI_FDIR:
1309 case I40E_VSI_SRIOV:
1310 case I40E_VSI_VMDQ2:
1311 default:
1312 qcount = vsi->alloc_queue_pairs;
1313 vsi->tc_config.tc_info[i].qcount = qcount;
1314 WARN_ON(i != 0);
1315 break;
1316 }
1317
1318 /* find the power-of-2 of the number of queue pairs */
1319 num_qps = vsi->tc_config.tc_info[i].qcount;
1320 pow = 0;
1321 while (num_qps &&
1322 ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
1323 pow++;
1324 num_qps >>= 1;
1325 }
1326
1327 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1328 qmap =
1329 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1330 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1331
1332 offset += vsi->tc_config.tc_info[i].qcount;
1333 } else {
1334 /* TC is not enabled so set the offset to
1335 * default queue and allocate one queue
1336 * for the given TC.
1337 */
1338 vsi->tc_config.tc_info[i].qoffset = 0;
1339 vsi->tc_config.tc_info[i].qcount = 1;
1340 vsi->tc_config.tc_info[i].netdev_tc = 0;
1341
1342 qmap = 0;
1343 }
1344 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1345 }
1346
1347 /* Set actual Tx/Rx queue pairs */
1348 vsi->num_queue_pairs = offset;
1349
1350 /* Scheduler section valid can only be set for ADD VSI */
1351 if (is_add) {
1352 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1353
1354 ctxt->info.up_enable_bits = enabled_tc;
1355 }
1356 if (vsi->type == I40E_VSI_SRIOV) {
1357 ctxt->info.mapping_flags |=
1358 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1359 for (i = 0; i < vsi->num_queue_pairs; i++)
1360 ctxt->info.queue_mapping[i] =
1361 cpu_to_le16(vsi->base_queue + i);
1362 } else {
1363 ctxt->info.mapping_flags |=
1364 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1365 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1366 }
1367 ctxt->info.valid_sections |= cpu_to_le16(sections);
1368}
1369
1370/**
1371 * i40e_set_rx_mode - NDO callback to set the netdev filters
1372 * @netdev: network interface device structure
1373 **/
1374static void i40e_set_rx_mode(struct net_device *netdev)
1375{
1376 struct i40e_netdev_priv *np = netdev_priv(netdev);
1377 struct i40e_mac_filter *f, *ftmp;
1378 struct i40e_vsi *vsi = np->vsi;
1379 struct netdev_hw_addr *uca;
1380 struct netdev_hw_addr *mca;
1381 struct netdev_hw_addr *ha;
1382
1383 /* add addr if not already in the filter list */
1384 netdev_for_each_uc_addr(uca, netdev) {
1385 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1386 if (i40e_is_vsi_in_vlan(vsi))
1387 i40e_put_mac_in_vlan(vsi, uca->addr,
1388 false, true);
1389 else
1390 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1391 false, true);
1392 }
1393 }
1394
1395 netdev_for_each_mc_addr(mca, netdev) {
1396 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1397 if (i40e_is_vsi_in_vlan(vsi))
1398 i40e_put_mac_in_vlan(vsi, mca->addr,
1399 false, true);
1400 else
1401 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1402 false, true);
1403 }
1404 }
1405
1406 /* remove filter if not in netdev list */
1407 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1408 bool found = false;
1409
1410 if (!f->is_netdev)
1411 continue;
1412
1413 if (is_multicast_ether_addr(f->macaddr)) {
1414 netdev_for_each_mc_addr(mca, netdev) {
1415 if (ether_addr_equal(mca->addr, f->macaddr)) {
1416 found = true;
1417 break;
1418 }
1419 }
1420 } else {
1421 netdev_for_each_uc_addr(uca, netdev) {
1422 if (ether_addr_equal(uca->addr, f->macaddr)) {
1423 found = true;
1424 break;
1425 }
1426 }
1427
1428 for_each_dev_addr(netdev, ha) {
1429 if (ether_addr_equal(ha->addr, f->macaddr)) {
1430 found = true;
1431 break;
1432 }
1433 }
1434 }
1435 if (!found)
1436 i40e_del_filter(
1437 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1438 }
1439
1440 /* check for other flag changes */
1441 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1442 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1443 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1444 }
1445}
1446
1447/**
1448 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1449 * @vsi: ptr to the VSI
1450 *
1451 * Push any outstanding VSI filter changes through the AdminQ.
1452 *
1453 * Returns 0 or error value
1454 **/
1455int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1456{
1457 struct i40e_mac_filter *f, *ftmp;
1458 bool promisc_forced_on = false;
1459 bool add_happened = false;
1460 int filter_list_len = 0;
1461 u32 changed_flags = 0;
dcae29be 1462 i40e_status aq_ret = 0;
41c445ff
JB		 1463 struct i40e_pf *pf;
1464 int num_add = 0;
1465 int num_del = 0;
1466 u16 cmd_flags;
1467
1468 /* empty array typed pointers, kcalloc later */
1469 struct i40e_aqc_add_macvlan_element_data *add_list;
1470 struct i40e_aqc_remove_macvlan_element_data *del_list;
1471
1472 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1473 usleep_range(1000, 2000);
1474 pf = vsi->back;
1475
1476 if (vsi->netdev) {
1477 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1478 vsi->current_netdev_flags = vsi->netdev->flags;
1479 }
1480
1481 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1482 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1483
1484 filter_list_len = pf->hw.aq.asq_buf_size /
1485 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1486 del_list = kcalloc(filter_list_len,
1487 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1488 GFP_KERNEL);
1489 if (!del_list)
1490 return -ENOMEM;
1491
1492 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1493 if (!f->changed)
1494 continue;
1495
1496 if (f->counter != 0)
1497 continue;
1498 f->changed = false;
1499 cmd_flags = 0;
1500
1501 /* add to delete list */
1502 memcpy(del_list[num_del].mac_addr,
1503 f->macaddr, ETH_ALEN);
1504 del_list[num_del].vlan_tag =
1505 cpu_to_le16((u16)(f->vlan ==
1506 I40E_VLAN_ANY ? 0 : f->vlan));
1507
1508 /* vlan0 as wild card to allow packets from all vlans */
1509 if (f->vlan == I40E_VLAN_ANY ||
1510 (vsi->netdev && !(vsi->netdev->features &
1511 NETIF_F_HW_VLAN_CTAG_FILTER)))
1512 cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1513 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1514 del_list[num_del].flags = cmd_flags;
1515 num_del++;
1516
1517 /* unlink from filter list */
1518 list_del(&f->list);
1519 kfree(f);
1520
1521 /* flush a full buffer */
1522 if (num_del == filter_list_len) {
dcae29be 1523 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1524 vsi->seid, del_list, num_del,
1525 NULL);
1526 num_del = 0;
1527 memset(del_list, 0, sizeof(*del_list));
1528
dcae29be 1529 if (aq_ret)
41c445ff
JB		 1530 dev_info(&pf->pdev->dev,
1531 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1532 aq_ret,
41c445ff
JB		 1533 pf->hw.aq.asq_last_status);
1534 }
1535 }
1536 if (num_del) {
dcae29be 1537 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1538 del_list, num_del, NULL);
1539 num_del = 0;
1540
dcae29be 1541 if (aq_ret)
41c445ff
JB		 1542 dev_info(&pf->pdev->dev,
1543 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1544 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1545 }
1546
1547 kfree(del_list);
1548 del_list = NULL;
1549
1550 /* do all the adds now */
1551 filter_list_len = pf->hw.aq.asq_buf_size /
1552 sizeof(struct i40e_aqc_add_macvlan_element_data),
1553 add_list = kcalloc(filter_list_len,
1554 sizeof(struct i40e_aqc_add_macvlan_element_data),
1555 GFP_KERNEL);
1556 if (!add_list)
1557 return -ENOMEM;
1558
1559 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1560 if (!f->changed)
1561 continue;
1562
1563 if (f->counter == 0)
1564 continue;
1565 f->changed = false;
1566 add_happened = true;
1567 cmd_flags = 0;
1568
1569 /* add to add array */
1570 memcpy(add_list[num_add].mac_addr,
1571 f->macaddr, ETH_ALEN);
1572 add_list[num_add].vlan_tag =
1573 cpu_to_le16(
1574 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1575 add_list[num_add].queue_number = 0;
1576
1577 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
1578
1579 /* vlan0 as wild card to allow packets from all vlans */
1580 if (f->vlan == I40E_VLAN_ANY || (vsi->netdev &&
1581 !(vsi->netdev->features &
1582 NETIF_F_HW_VLAN_CTAG_FILTER)))
1583 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
1584 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1585 num_add++;
1586
1587 /* flush a full buffer */
1588 if (num_add == filter_list_len) {
dcae29be
JB		 1589 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1590 add_list, num_add,
1591 NULL);
41c445ff
JB		 1592 num_add = 0;
1593
dcae29be 1594 if (aq_ret)
41c445ff
JB		 1595 break;
1596 memset(add_list, 0, sizeof(*add_list));
1597 }
1598 }
1599 if (num_add) {
dcae29be
JB		 1600 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1601 add_list, num_add, NULL);
41c445ff
JB		 1602 num_add = 0;
1603 }
1604 kfree(add_list);
1605 add_list = NULL;
1606
dcae29be 1607 if (add_happened && (!aq_ret)) {
41c445ff 1608 /* do nothing */;
dcae29be 1609 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1610 dev_info(&pf->pdev->dev,
1611 "add filter failed, err %d, aq_err %d\n",
dcae29be 1612 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1613 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1614 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1615 &vsi->state)) {
1616 promisc_forced_on = true;
1617 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1618 &vsi->state);
1619 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1620 }
1621 }
1622 }
1623
1624 /* check for changes in promiscuous modes */
1625 if (changed_flags & IFF_ALLMULTI) {
1626 bool cur_multipromisc;
1627 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1628 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1629 vsi->seid,
1630 cur_multipromisc,
1631 NULL);
1632 if (aq_ret)
41c445ff
JB		 1633 dev_info(&pf->pdev->dev,
1634 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1635 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1636 }
1637 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1638 bool cur_promisc;
1639 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1640 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1641 &vsi->state));
dcae29be
JB		 1642 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1643 vsi->seid,
1644 cur_promisc, NULL);
1645 if (aq_ret)
41c445ff
JB		 1646 dev_info(&pf->pdev->dev,
1647 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1648 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1649 }
1650
1651 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1652 return 0;
1653}
1654
1655/**
1656 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1657 * @pf: board private structure
1658 **/
1659static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1660{
1661 int v;
1662
1663 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1664 return;
1665 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1666
1667 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1668 if (pf->vsi[v] &&
1669 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1670 i40e_sync_vsi_filters(pf->vsi[v]);
1671 }
1672}
1673
1674/**
1675 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1676 * @netdev: network interface device structure
1677 * @new_mtu: new value for maximum frame size
1678 *
1679 * Returns 0 on success, negative on failure
1680 **/
1681static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1682{
1683 struct i40e_netdev_priv *np = netdev_priv(netdev);
1684 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1685 struct i40e_vsi *vsi = np->vsi;
1686
1687 /* MTU < 68 is an error and causes problems on some kernels */
1688 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1689 return -EINVAL;
1690
1691 netdev_info(netdev, "changing MTU from %d to %d\n",
1692 netdev->mtu, new_mtu);
1693 netdev->mtu = new_mtu;
1694 if (netif_running(netdev))
1695 i40e_vsi_reinit_locked(vsi);
1696
1697 return 0;
1698}
1699
1700/**
1701 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1702 * @vsi: the vsi being adjusted
1703 **/
1704void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1705{
1706 struct i40e_vsi_context ctxt;
1707 i40e_status ret;
1708
1709 if ((vsi->info.valid_sections &
1710 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1711 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1712 return; /* already enabled */
1713
1714 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1715 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1716 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1717
1718 ctxt.seid = vsi->seid;
1719 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1720 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1721 if (ret) {
1722 dev_info(&vsi->back->pdev->dev,
1723 "%s: update vsi failed, aq_err=%d\n",
1724 __func__, vsi->back->hw.aq.asq_last_status);
1725 }
1726}
1727
1728/**
1729 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1730 * @vsi: the vsi being adjusted
1731 **/
1732void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1733{
1734 struct i40e_vsi_context ctxt;
1735 i40e_status ret;
1736
1737 if ((vsi->info.valid_sections &
1738 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1739 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1740 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1741 return; /* already disabled */
1742
1743 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1744 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1745 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1746
1747 ctxt.seid = vsi->seid;
1748 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1749 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1750 if (ret) {
1751 dev_info(&vsi->back->pdev->dev,
1752 "%s: update vsi failed, aq_err=%d\n",
1753 __func__, vsi->back->hw.aq.asq_last_status);
1754 }
1755}
1756
1757/**
1758 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1759 * @netdev: network interface to be adjusted
1760 * @features: netdev features to test if VLAN offload is enabled or not
1761 **/
1762static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1763{
1764 struct i40e_netdev_priv *np = netdev_priv(netdev);
1765 struct i40e_vsi *vsi = np->vsi;
1766
1767 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1768 i40e_vlan_stripping_enable(vsi);
1769 else
1770 i40e_vlan_stripping_disable(vsi);
1771}
1772
1773/**
1774 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1775 * @vsi: the vsi being configured
1776 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1777 **/
1778int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1779{
1780 struct i40e_mac_filter *f, *add_f;
1781 bool is_netdev, is_vf;
1782 int ret;
1783
1784 is_vf = (vsi->type == I40E_VSI_SRIOV);
1785 is_netdev = !!(vsi->netdev);
1786
1787 if (is_netdev) {
1788 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1789 is_vf, is_netdev);
1790 if (!add_f) {
1791 dev_info(&vsi->back->pdev->dev,
1792 "Could not add vlan filter %d for %pM\n",
1793 vid, vsi->netdev->dev_addr);
1794 return -ENOMEM;
1795 }
1796 }
1797
1798 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1799 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1800 if (!add_f) {
1801 dev_info(&vsi->back->pdev->dev,
1802 "Could not add vlan filter %d for %pM\n",
1803 vid, f->macaddr);
1804 return -ENOMEM;
1805 }
1806 }
1807
1808 ret = i40e_sync_vsi_filters(vsi);
1809 if (ret) {
1810 dev_info(&vsi->back->pdev->dev,
1811 "Could not sync filters for vid %d\n", vid);
1812 return ret;
1813 }
1814
1815 /* Now if we add a vlan tag, make sure to check if it is the first
1816 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1817 * with 0, so we now accept untagged and specified tagged traffic
1818 * (and not any taged and untagged)
1819 */
1820 if (vid > 0) {
1821 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1822 I40E_VLAN_ANY,
1823 is_vf, is_netdev)) {
1824 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1825 I40E_VLAN_ANY, is_vf, is_netdev);
1826 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1827 is_vf, is_netdev);
1828 if (!add_f) {
1829 dev_info(&vsi->back->pdev->dev,
1830 "Could not add filter 0 for %pM\n",
1831 vsi->netdev->dev_addr);
1832 return -ENOMEM;
1833 }
1834 }
1835
1836 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1837 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1838 is_vf, is_netdev)) {
1839 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1840 is_vf, is_netdev);
1841 add_f = i40e_add_filter(vsi, f->macaddr,
1842 0, is_vf, is_netdev);
1843 if (!add_f) {
1844 dev_info(&vsi->back->pdev->dev,
1845 "Could not add filter 0 for %pM\n",
1846 f->macaddr);
1847 return -ENOMEM;
1848 }
1849 }
1850 }
1851 ret = i40e_sync_vsi_filters(vsi);
1852 }
1853
1854 return ret;
1855}
1856
1857/**
1858 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1859 * @vsi: the vsi being configured
1860 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1861 *
1862 * Return: 0 on success or negative otherwise
41c445ff
JB		 1863 **/
1864int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1865{
1866 struct net_device *netdev = vsi->netdev;
1867 struct i40e_mac_filter *f, *add_f;
1868 bool is_vf, is_netdev;
1869 int filter_count = 0;
1870 int ret;
1871
1872 is_vf = (vsi->type == I40E_VSI_SRIOV);
1873 is_netdev = !!(netdev);
1874
1875 if (is_netdev)
1876 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1877
1878 list_for_each_entry(f, &vsi->mac_filter_list, list)
1879 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1880
1881 ret = i40e_sync_vsi_filters(vsi);
1882 if (ret) {
1883 dev_info(&vsi->back->pdev->dev, "Could not sync filters\n");
1884 return ret;
1885 }
1886
1887 /* go through all the filters for this VSI and if there is only
1888 * vid == 0 it means there are no other filters, so vid 0 must
1889 * be replaced with -1. This signifies that we should from now
1890 * on accept any traffic (with any tag present, or untagged)
1891 */
1892 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1893 if (is_netdev) {
1894 if (f->vlan &&
1895 ether_addr_equal(netdev->dev_addr, f->macaddr))
1896 filter_count++;
1897 }
1898
1899 if (f->vlan)
1900 filter_count++;
1901 }
1902
1903 if (!filter_count && is_netdev) {
1904 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1905 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1906 is_vf, is_netdev);
1907 if (!f) {
1908 dev_info(&vsi->back->pdev->dev,
1909 "Could not add filter %d for %pM\n",
1910 I40E_VLAN_ANY, netdev->dev_addr);
1911 return -ENOMEM;
1912 }
1913 }
1914
1915 if (!filter_count) {
1916 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1917 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1918 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1919 is_vf, is_netdev);
1920 if (!add_f) {
1921 dev_info(&vsi->back->pdev->dev,
1922 "Could not add filter %d for %pM\n",
1923 I40E_VLAN_ANY, f->macaddr);
1924 return -ENOMEM;
1925 }
1926 }
1927 }
1928
1929 return i40e_sync_vsi_filters(vsi);
1930}
1931
1932/**
1933 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1934 * @netdev: network interface to be adjusted
1935 * @vid: vlan id to be added
078b5876
JB		 1936 *
1937 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1938 **/
1939static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1940 __always_unused __be16 proto, u16 vid)
1941{
1942 struct i40e_netdev_priv *np = netdev_priv(netdev);
1943 struct i40e_vsi *vsi = np->vsi;
078b5876 1944 int ret = 0;
41c445ff
JB		 1945
1946 if (vid > 4095)
078b5876
JB		 1947 return -EINVAL;
1948
1949 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1950
41c445ff
JB		 1951 /* If the network stack called us with vid = 0, we should
1952 * indicate to i40e_vsi_add_vlan() that we want to receive
1953 * any traffic (i.e. with any vlan tag, or untagged)
1954 */
1955 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1956
078b5876
JB		 1957 if (!ret && (vid < VLAN_N_VID))
1958 set_bit(vid, vsi->active_vlans);
41c445ff 1959
078b5876 1960 return ret;
41c445ff
JB		 1961}
1962
1963/**
1964 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1965 * @netdev: network interface to be adjusted
1966 * @vid: vlan id to be removed
078b5876
JB		 1967 *
1968 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1969 **/
1970static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1971 __always_unused __be16 proto, u16 vid)
1972{
1973 struct i40e_netdev_priv *np = netdev_priv(netdev);
1974 struct i40e_vsi *vsi = np->vsi;
1975
078b5876
JB		 1976 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1977
41c445ff
JB		 1978 /* return code is ignored as there is nothing a user
1979 * can do about failure to remove and a log message was
078b5876 1980 * already printed from the other function
41c445ff
JB		 1981 */
1982 i40e_vsi_kill_vlan(vsi, vid);
1983
1984 clear_bit(vid, vsi->active_vlans);
078b5876 1985
41c445ff
JB		 1986 return 0;
1987}
1988
1989/**
1990 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
1991 * @vsi: the vsi being brought back up
1992 **/
1993static void i40e_restore_vlan(struct i40e_vsi *vsi)
1994{
1995 u16 vid;
1996
1997 if (!vsi->netdev)
1998 return;
1999
2000 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2001
2002 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2003 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2004 vid);
2005}
2006
2007/**
2008 * i40e_vsi_add_pvid - Add pvid for the VSI
2009 * @vsi: the vsi being adjusted
2010 * @vid: the vlan id to set as a PVID
2011 **/
dcae29be 2012int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2013{
2014 struct i40e_vsi_context ctxt;
dcae29be 2015 i40e_status aq_ret;
41c445ff
JB		 2016
2017 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2018 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2019 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2020 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2021 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2022
2023 ctxt.seid = vsi->seid;
2024 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2025 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2026 if (aq_ret) {
41c445ff
JB		 2027 dev_info(&vsi->back->pdev->dev,
2028 "%s: update vsi failed, aq_err=%d\n",
2029 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2030 return -ENOENT;
41c445ff
JB		 2031 }
2032
dcae29be 2033 return 0;
41c445ff
JB		 2034}
2035
2036/**
2037 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2038 * @vsi: the vsi being adjusted
2039 *
2040 * Just use the vlan_rx_register() service to put it back to normal
2041 **/
2042void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2043{
6c12fcbf
GR		 2044 i40e_vlan_stripping_disable(vsi);
2045
41c445ff 2046 vsi->info.pvid = 0;
41c445ff
JB		 2047}
2048
2049/**
2050 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2051 * @vsi: ptr to the VSI
2052 *
2053 * If this function returns with an error, then it's possible one or
2054 * more of the rings is populated (while the rest are not). It is the
2055 * callers duty to clean those orphaned rings.
2056 *
2057 * Return 0 on success, negative on failure
2058 **/
2059static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2060{
2061 int i, err = 0;
2062
2063 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2064 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2065
2066 return err;
2067}
2068
2069/**
2070 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2071 * @vsi: ptr to the VSI
2072 *
2073 * Free VSI's transmit software resources
2074 **/
2075static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2076{
2077 int i;
2078
2079 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2080 if (vsi->tx_rings[i]->desc)
2081 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2082}
2083
2084/**
2085 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2086 * @vsi: ptr to the VSI
2087 *
2088 * If this function returns with an error, then it's possible one or
2089 * more of the rings is populated (while the rest are not). It is the
2090 * callers duty to clean those orphaned rings.
2091 *
2092 * Return 0 on success, negative on failure
2093 **/
2094static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2095{
2096 int i, err = 0;
2097
2098 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2099 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2100 return err;
2101}
2102
2103/**
2104 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2105 * @vsi: ptr to the VSI
2106 *
2107 * Free all receive software resources
2108 **/
2109static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2110{
2111 int i;
2112
2113 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2114 if (vsi->rx_rings[i]->desc)
2115 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2116}
2117
2118/**
2119 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2120 * @ring: The Tx ring to configure
2121 *
2122 * Configure the Tx descriptor ring in the HMC context.
2123 **/
2124static int i40e_configure_tx_ring(struct i40e_ring *ring)
2125{
2126 struct i40e_vsi *vsi = ring->vsi;
2127 u16 pf_q = vsi->base_queue + ring->queue_index;
2128 struct i40e_hw *hw = &vsi->back->hw;
2129 struct i40e_hmc_obj_txq tx_ctx;
2130 i40e_status err = 0;
2131 u32 qtx_ctl = 0;
2132
2133 /* some ATR related tx ring init */
2134 if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
2135 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2136 ring->atr_count = 0;
2137 } else {
2138 ring->atr_sample_rate = 0;
2139 }
2140
2141 /* initialize XPS */
2142 if (ring->q_vector && ring->netdev &&
2143 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2144 netif_set_xps_queue(ring->netdev,
2145 &ring->q_vector->affinity_mask,
2146 ring->queue_index);
2147
2148 /* clear the context structure first */
2149 memset(&tx_ctx, 0, sizeof(tx_ctx));
2150
2151 tx_ctx.new_context = 1;
2152 tx_ctx.base = (ring->dma / 128);
2153 tx_ctx.qlen = ring->count;
2154 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
2155 I40E_FLAG_FDIR_ATR_ENABLED));
2156
2157 /* As part of VSI creation/update, FW allocates certain
2158 * Tx arbitration queue sets for each TC enabled for
2159 * the VSI. The FW returns the handles to these queue
2160 * sets as part of the response buffer to Add VSI,
2161 * Update VSI, etc. AQ commands. It is expected that
2162 * these queue set handles be associated with the Tx
2163 * queues by the driver as part of the TX queue context
2164 * initialization. This has to be done regardless of
2165 * DCB as by default everything is mapped to TC0.
2166 */
2167 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2168 tx_ctx.rdylist_act = 0;
2169
2170 /* clear the context in the HMC */
2171 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2172 if (err) {
2173 dev_info(&vsi->back->pdev->dev,
2174 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2175 ring->queue_index, pf_q, err);
2176 return -ENOMEM;
2177 }
2178
2179 /* set the context in the HMC */
2180 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2181 if (err) {
2182 dev_info(&vsi->back->pdev->dev,
2183 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2184 ring->queue_index, pf_q, err);
2185 return -ENOMEM;
2186 }
2187
2188 /* Now associate this queue with this PCI function */
2189 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2190 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2191 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2192 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2193 i40e_flush(hw);
2194
2195 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2196
2197 /* cache tail off for easier writes later */
2198 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2199
2200 return 0;
2201}
2202
2203/**
2204 * i40e_configure_rx_ring - Configure a receive ring context
2205 * @ring: The Rx ring to configure
2206 *
2207 * Configure the Rx descriptor ring in the HMC context.
2208 **/
2209static int i40e_configure_rx_ring(struct i40e_ring *ring)
2210{
2211 struct i40e_vsi *vsi = ring->vsi;
2212 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2213 u16 pf_q = vsi->base_queue + ring->queue_index;
2214 struct i40e_hw *hw = &vsi->back->hw;
2215 struct i40e_hmc_obj_rxq rx_ctx;
2216 i40e_status err = 0;
2217
2218 ring->state = 0;
2219
2220 /* clear the context structure first */
2221 memset(&rx_ctx, 0, sizeof(rx_ctx));
2222
2223 ring->rx_buf_len = vsi->rx_buf_len;
2224 ring->rx_hdr_len = vsi->rx_hdr_len;
2225
2226 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2227 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2228
2229 rx_ctx.base = (ring->dma / 128);
2230 rx_ctx.qlen = ring->count;
2231
2232 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2233 set_ring_16byte_desc_enabled(ring);
2234 rx_ctx.dsize = 0;
2235 } else {
2236 rx_ctx.dsize = 1;
2237 }
2238
2239 rx_ctx.dtype = vsi->dtype;
2240 if (vsi->dtype) {
2241 set_ring_ps_enabled(ring);
2242 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2243 I40E_RX_SPLIT_IP |
2244 I40E_RX_SPLIT_TCP_UDP |
2245 I40E_RX_SPLIT_SCTP;
2246 } else {
2247 rx_ctx.hsplit_0 = 0;
2248 }
2249
2250 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2251 (chain_len * ring->rx_buf_len));
2252 rx_ctx.tphrdesc_ena = 1;
2253 rx_ctx.tphwdesc_ena = 1;
2254 rx_ctx.tphdata_ena = 1;
2255 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2256 if (hw->revision_id == 0)
2257 rx_ctx.lrxqthresh = 0;
2258 else
2259 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2260 rx_ctx.crcstrip = 1;
2261 rx_ctx.l2tsel = 1;
2262 rx_ctx.showiv = 1;
2263
2264 /* clear the context in the HMC */
2265 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2266 if (err) {
2267 dev_info(&vsi->back->pdev->dev,
2268 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2269 ring->queue_index, pf_q, err);
2270 return -ENOMEM;
2271 }
2272
2273 /* set the context in the HMC */
2274 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2275 if (err) {
2276 dev_info(&vsi->back->pdev->dev,
2277 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2278 ring->queue_index, pf_q, err);
2279 return -ENOMEM;
2280 }
2281
2282 /* cache tail for quicker writes, and clear the reg before use */
2283 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2284 writel(0, ring->tail);
2285
2286 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2287
2288 return 0;
2289}
2290
2291/**
2292 * i40e_vsi_configure_tx - Configure the VSI for Tx
2293 * @vsi: VSI structure describing this set of rings and resources
2294 *
2295 * Configure the Tx VSI for operation.
2296 **/
2297static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2298{
2299 int err = 0;
2300 u16 i;
2301
9f65e15b
AD		 2302 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2303 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2304
2305 return err;
2306}
2307
2308/**
2309 * i40e_vsi_configure_rx - Configure the VSI for Rx
2310 * @vsi: the VSI being configured
2311 *
2312 * Configure the Rx VSI for operation.
2313 **/
2314static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2315{
2316 int err = 0;
2317 u16 i;
2318
2319 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2320 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2321 + ETH_FCS_LEN + VLAN_HLEN;
2322 else
2323 vsi->max_frame = I40E_RXBUFFER_2048;
2324
2325 /* figure out correct receive buffer length */
2326 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2327 I40E_FLAG_RX_PS_ENABLED)) {
2328 case I40E_FLAG_RX_1BUF_ENABLED:
2329 vsi->rx_hdr_len = 0;
2330 vsi->rx_buf_len = vsi->max_frame;
2331 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2332 break;
2333 case I40E_FLAG_RX_PS_ENABLED:
2334 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2335 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2336 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2337 break;
2338 default:
2339 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2340 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2341 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2342 break;
2343 }
2344
2345 /* round up for the chip's needs */
2346 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2347 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2348 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2349 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2350
2351 /* set up individual rings */
2352 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2353 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2354
2355 return err;
2356}
2357
2358/**
2359 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2360 * @vsi: ptr to the VSI
2361 **/
2362static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2363{
2364 u16 qoffset, qcount;
2365 int i, n;
2366
2367 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2368 return;
2369
2370 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2371 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2372 continue;
2373
2374 qoffset = vsi->tc_config.tc_info[n].qoffset;
2375 qcount = vsi->tc_config.tc_info[n].qcount;
2376 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2377 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2378 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2379 rx_ring->dcb_tc = n;
2380 tx_ring->dcb_tc = n;
2381 }
2382 }
2383}
2384
2385/**
2386 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2387 * @vsi: ptr to the VSI
2388 **/
2389static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2390{
2391 if (vsi->netdev)
2392 i40e_set_rx_mode(vsi->netdev);
2393}
2394
2395/**
2396 * i40e_vsi_configure - Set up the VSI for action
2397 * @vsi: the VSI being configured
2398 **/
2399static int i40e_vsi_configure(struct i40e_vsi *vsi)
2400{
2401 int err;
2402
2403 i40e_set_vsi_rx_mode(vsi);
2404 i40e_restore_vlan(vsi);
2405 i40e_vsi_config_dcb_rings(vsi);
2406 err = i40e_vsi_configure_tx(vsi);
2407 if (!err)
2408 err = i40e_vsi_configure_rx(vsi);
2409
2410 return err;
2411}
2412
2413/**
2414 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2415 * @vsi: the VSI being configured
2416 **/
2417static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2418{
2419 struct i40e_pf *pf = vsi->back;
2420 struct i40e_q_vector *q_vector;
2421 struct i40e_hw *hw = &pf->hw;
2422 u16 vector;
2423 int i, q;
2424 u32 val;
2425 u32 qp;
2426
2427 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2428 * and PFINT_LNKLSTn registers, e.g.:
2429 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2430 */
2431 qp = vsi->base_queue;
2432 vector = vsi->base_vector;
493fb300
AD		 2433 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2434 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2435 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2436 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2437 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2438 q_vector->rx.itr);
2439 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2440 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2441 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2442 q_vector->tx.itr);
2443
2444 /* Linked list for the queuepairs assigned to this vector */
2445 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2446 for (q = 0; q < q_vector->num_ringpairs; q++) {
2447 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2448 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2449 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2450 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2451 (I40E_QUEUE_TYPE_TX
2452 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2453
2454 wr32(hw, I40E_QINT_RQCTL(qp), val);
2455
2456 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2457 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2458 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2459 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2460 (I40E_QUEUE_TYPE_RX
2461 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2462
2463 /* Terminate the linked list */
2464 if (q == (q_vector->num_ringpairs - 1))
2465 val |= (I40E_QUEUE_END_OF_LIST
2466 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2467
2468 wr32(hw, I40E_QINT_TQCTL(qp), val);
2469 qp++;
2470 }
2471 }
2472
2473 i40e_flush(hw);
2474}
2475
2476/**
2477 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2478 * @hw: ptr to the hardware info
2479 **/
2480static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2481{
2482 u32 val;
2483
2484 /* clear things first */
2485 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2486 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2487
2488 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2489 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2490 I40E_PFINT_ICR0_ENA_GRST_MASK |
2491 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2492 I40E_PFINT_ICR0_ENA_GPIO_MASK |
2493 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2494 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2495 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2496 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2497
2498 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2499
2500 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2501 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2502 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2503
2504 /* OTHER_ITR_IDX = 0 */
2505 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2506}
2507
2508/**
2509 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2510 * @vsi: the VSI being configured
2511 **/
2512static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2513{
493fb300 2514 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2515 struct i40e_pf *pf = vsi->back;
2516 struct i40e_hw *hw = &pf->hw;
2517 u32 val;
2518
2519 /* set the ITR configuration */
2520 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2521 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2522 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2523 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2524 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2525 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2526
2527 i40e_enable_misc_int_causes(hw);
2528
2529 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2530 wr32(hw, I40E_PFINT_LNKLST0, 0);
2531
2532 /* Associate the queue pair to the vector and enable the q int */
2533 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2534 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2535 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2536
2537 wr32(hw, I40E_QINT_RQCTL(0), val);
2538
2539 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2540 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2541 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2542
2543 wr32(hw, I40E_QINT_TQCTL(0), val);
2544 i40e_flush(hw);
2545}
2546
2ef28cfb
MW		 2547/**
2548 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2549 * @pf: board private structure
2550 **/
2551void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2552{
2553 struct i40e_hw *hw = &pf->hw;
2554
2555 wr32(hw, I40E_PFINT_DYN_CTL0,
2556 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2557 i40e_flush(hw);
2558}
2559
41c445ff
JB		 2560/**
2561 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2562 * @pf: board private structure
2563 **/
116a57d4 2564void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2565{
2566 struct i40e_hw *hw = &pf->hw;
2567 u32 val;
2568
2569 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2570 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2571 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2572
2573 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2574 i40e_flush(hw);
2575}
2576
2577/**
2578 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2579 * @vsi: pointer to a vsi
2580 * @vector: enable a particular Hw Interrupt vector
2581 **/
2582void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2583{
2584 struct i40e_pf *pf = vsi->back;
2585 struct i40e_hw *hw = &pf->hw;
2586 u32 val;
2587
2588 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2589 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2590 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2591 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2592 /* skip the flush */
41c445ff
JB		 2593}
2594
2595/**
2596 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2597 * @irq: interrupt number
2598 * @data: pointer to a q_vector
2599 **/
2600static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2601{
2602 struct i40e_q_vector *q_vector = data;
2603
cd0b6fa6 2604 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2605 return IRQ_HANDLED;
2606
2607 napi_schedule(&q_vector->napi);
2608
2609 return IRQ_HANDLED;
2610}
2611
2612/**
2613 * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
2614 * @irq: interrupt number
2615 * @data: pointer to a q_vector
2616 **/
2617static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
2618{
2619 struct i40e_q_vector *q_vector = data;
2620
cd0b6fa6 2621 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2622 return IRQ_HANDLED;
2623
2624 pr_info("fdir ring cleaning needed\n");
2625
2626 return IRQ_HANDLED;
2627}
2628
2629/**
2630 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2631 * @vsi: the VSI being configured
2632 * @basename: name for the vector
2633 *
2634 * Allocates MSI-X vectors and requests interrupts from the kernel.
2635 **/
2636static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2637{
2638 int q_vectors = vsi->num_q_vectors;
2639 struct i40e_pf *pf = vsi->back;
2640 int base = vsi->base_vector;
2641 int rx_int_idx = 0;
2642 int tx_int_idx = 0;
2643 int vector, err;
2644
2645 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2646 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2647
cd0b6fa6 2648 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2649 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2650 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2651 tx_int_idx++;
cd0b6fa6 2652 } else if (q_vector->rx.ring) {
41c445ff
JB		 2653 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2654 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2655 } else if (q_vector->tx.ring) {
41c445ff
JB		 2656 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2657 "%s-%s-%d", basename, "tx", tx_int_idx++);
2658 } else {
2659 /* skip this unused q_vector */
2660 continue;
2661 }
2662 err = request_irq(pf->msix_entries[base + vector].vector,
2663 vsi->irq_handler,
2664 0,
2665 q_vector->name,
2666 q_vector);
2667 if (err) {
2668 dev_info(&pf->pdev->dev,
2669 "%s: request_irq failed, error: %d\n",
2670 __func__, err);
2671 goto free_queue_irqs;
2672 }
2673 /* assign the mask for this irq */
2674 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2675 &q_vector->affinity_mask);
2676 }
2677
2678 return 0;
2679
2680free_queue_irqs:
2681 while (vector) {
2682 vector--;
2683 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2684 NULL);
2685 free_irq(pf->msix_entries[base + vector].vector,
2686 &(vsi->q_vectors[vector]));
2687 }
2688 return err;
2689}
2690
2691/**
2692 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2693 * @vsi: the VSI being un-configured
2694 **/
2695static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2696{
2697 struct i40e_pf *pf = vsi->back;
2698 struct i40e_hw *hw = &pf->hw;
2699 int base = vsi->base_vector;
2700 int i;
2701
2702 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2703 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2704 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2705 }
2706
2707 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2708 for (i = vsi->base_vector;
2709 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2710 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2711
2712 i40e_flush(hw);
2713 for (i = 0; i < vsi->num_q_vectors; i++)
2714 synchronize_irq(pf->msix_entries[i + base].vector);
2715 } else {
2716 /* Legacy and MSI mode - this stops all interrupt handling */
2717 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2718 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2719 i40e_flush(hw);
2720 synchronize_irq(pf->pdev->irq);
2721 }
2722}
2723
2724/**
2725 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2726 * @vsi: the VSI being configured
2727 **/
2728static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2729{
2730 struct i40e_pf *pf = vsi->back;
2731 int i;
2732
2733 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2734 for (i = vsi->base_vector;
2735 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2736 i40e_irq_dynamic_enable(vsi, i);
2737 } else {
2738 i40e_irq_dynamic_enable_icr0(pf);
2739 }
2740
1022cb6c 2741 i40e_flush(&pf->hw);
41c445ff
JB		 2742 return 0;
2743}
2744
2745/**
2746 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2747 * @pf: board private structure
2748 **/
2749static void i40e_stop_misc_vector(struct i40e_pf *pf)
2750{
2751 /* Disable ICR 0 */
2752 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2753 i40e_flush(&pf->hw);
2754}
2755
2756/**
2757 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2758 * @irq: interrupt number
2759 * @data: pointer to a q_vector
2760 *
2761 * This is the handler used for all MSI/Legacy interrupts, and deals
2762 * with both queue and non-queue interrupts. This is also used in
2763 * MSIX mode to handle the non-queue interrupts.
2764 **/
2765static irqreturn_t i40e_intr(int irq, void *data)
2766{
2767 struct i40e_pf *pf = (struct i40e_pf *)data;
2768 struct i40e_hw *hw = &pf->hw;
2769 u32 icr0, icr0_remaining;
2770 u32 val, ena_mask;
2771
2772 icr0 = rd32(hw, I40E_PFINT_ICR0);
2773
116a57d4
SN		 2774 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2775 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
2776 return IRQ_NONE;
2777
41c445ff
JB		 2778 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
2779
cd92e72f
SN		 2780 /* if interrupt but no bits showing, must be SWINT */
2781 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2782 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2783 pf->sw_int_count++;
2784
41c445ff
JB		 2785 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2786 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2787
2788 /* temporarily disable queue cause for NAPI processing */
2789 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2790 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2791 wr32(hw, I40E_QINT_RQCTL(0), qval);
2792
2793 qval = rd32(hw, I40E_QINT_TQCTL(0));
2794 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2795 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2796
2797 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2798 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2799 }
2800
2801 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2802 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2803 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2804 }
2805
2806 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2807 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2808 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2809 }
2810
2811 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2812 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2813 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2814 }
2815
2816 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2817 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2818 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2819 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2820 val = rd32(hw, I40E_GLGEN_RSTAT);
2821 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2822 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2823 if (val == I40E_RESET_CORER)
41c445ff 2824 pf->corer_count++;
d52cf0a9 2825 else if (val == I40E_RESET_GLOBR)
41c445ff 2826 pf->globr_count++;
d52cf0a9 2827 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2828 pf->empr_count++;
2829 }
2830
9c010ee0
ASJ		 2831 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2832 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2833 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2834 }
2835
41c445ff
JB		 2836 /* If a critical error is pending we have no choice but to reset the
2837 * device.
2838 * Report and mask out any remaining unexpected interrupts.
2839 */
2840 icr0_remaining = icr0 & ena_mask;
2841 if (icr0_remaining) {
2842 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2843 icr0_remaining);
9c010ee0 2844 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2845 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2846 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2847 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2848 dev_info(&pf->pdev->dev, "device will be reset\n");
2849 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2850 i40e_service_event_schedule(pf);
41c445ff
JB		 2851 }
2852 ena_mask &= ~icr0_remaining;
2853 }
2854
2855 /* re-enable interrupt causes */
2856 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2857 if (!test_bit(__I40E_DOWN, &pf->state)) {
2858 i40e_service_event_schedule(pf);
2859 i40e_irq_dynamic_enable_icr0(pf);
2860 }
2861
2862 return IRQ_HANDLED;
2863}
2864
2865/**
cd0b6fa6 2866 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2867 * @vsi: the VSI being configured
2868 * @v_idx: vector index
cd0b6fa6 2869 * @qp_idx: queue pair index
41c445ff 2870 **/
cd0b6fa6 2871static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2872{
493fb300 2873 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2874 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2875 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2876
2877 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2878 tx_ring->next = q_vector->tx.ring;
2879 q_vector->tx.ring = tx_ring;
41c445ff 2880 q_vector->tx.count++;
cd0b6fa6
AD		 2881
2882 rx_ring->q_vector = q_vector;
2883 rx_ring->next = q_vector->rx.ring;
2884 q_vector->rx.ring = rx_ring;
2885 q_vector->rx.count++;
41c445ff
JB		 2886}
2887
2888/**
2889 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
2890 * @vsi: the VSI being configured
2891 *
2892 * This function maps descriptor rings to the queue-specific vectors
2893 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2894 * one vector per queue pair, but on a constrained vector budget, we
2895 * group the queue pairs as "efficiently" as possible.
2896 **/
2897static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
2898{
2899 int qp_remaining = vsi->num_queue_pairs;
2900 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 2901 int num_ringpairs;
41c445ff
JB		 2902 int v_start = 0;
2903 int qp_idx = 0;
2904
2905 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2906 * group them so there are multiple queues per vector.
2907 */
2908 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 2909 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
2910
2911 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
2912
2913 q_vector->num_ringpairs = num_ringpairs;
2914
2915 q_vector->rx.count = 0;
2916 q_vector->tx.count = 0;
2917 q_vector->rx.ring = NULL;
2918 q_vector->tx.ring = NULL;
2919
2920 while (num_ringpairs--) {
2921 map_vector_to_qp(vsi, v_start, qp_idx);
2922 qp_idx++;
2923 qp_remaining--;
41c445ff
JB		 2924 }
2925 }
2926}
2927
2928/**
2929 * i40e_vsi_request_irq - Request IRQ from the OS
2930 * @vsi: the VSI being configured
2931 * @basename: name for the vector
2932 **/
2933static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
2934{
2935 struct i40e_pf *pf = vsi->back;
2936 int err;
2937
2938 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
2939 err = i40e_vsi_request_irq_msix(vsi, basename);
2940 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
2941 err = request_irq(pf->pdev->irq, i40e_intr, 0,
2942 pf->misc_int_name, pf);
2943 else
2944 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
2945 pf->misc_int_name, pf);
2946
2947 if (err)
2948 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
2949
2950 return err;
2951}
2952
2953#ifdef CONFIG_NET_POLL_CONTROLLER
2954/**
2955 * i40e_netpoll - A Polling 'interrupt'handler
2956 * @netdev: network interface device structure
2957 *
2958 * This is used by netconsole to send skbs without having to re-enable
2959 * interrupts. It's not called while the normal interrupt routine is executing.
2960 **/
2961static void i40e_netpoll(struct net_device *netdev)
2962{
2963 struct i40e_netdev_priv *np = netdev_priv(netdev);
2964 struct i40e_vsi *vsi = np->vsi;
2965 struct i40e_pf *pf = vsi->back;
2966 int i;
2967
2968 /* if interface is down do nothing */
2969 if (test_bit(__I40E_DOWN, &vsi->state))
2970 return;
2971
2972 pf->flags |= I40E_FLAG_IN_NETPOLL;
2973 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2974 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 2975 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 2976 } else {
2977 i40e_intr(pf->pdev->irq, netdev);
2978 }
2979 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
2980}
2981#endif
2982
2983/**
2984 * i40e_vsi_control_tx - Start or stop a VSI's rings
2985 * @vsi: the VSI being configured
2986 * @enable: start or stop the rings
2987 **/
2988static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
2989{
2990 struct i40e_pf *pf = vsi->back;
2991 struct i40e_hw *hw = &pf->hw;
2992 int i, j, pf_q;
2993 u32 tx_reg;
2994
2995 pf_q = vsi->base_queue;
2996 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
2997 j = 1000;
2998 do {
2999 usleep_range(1000, 2000);
3000 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3001 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
3002 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
3003
fda972f6
MW		 3004 /* Skip if the queue is already in the requested state */
3005 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3006 continue;
3007 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3008 continue;
41c445ff
JB		 3009
3010 /* turn on/off the queue */
3011 if (enable)
3012 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
3013 I40E_QTX_ENA_QENA_STAT_MASK;
3014 else
3015 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3016
3017 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3018
3019 /* wait for the change to finish */
3020 for (j = 0; j < 10; j++) {
3021 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3022 if (enable) {
3023 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3024 break;
3025 } else {
3026 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3027 break;
3028 }
3029
3030 udelay(10);
3031 }
3032 if (j >= 10) {
3033 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3034 pf_q, (enable ? "en" : "dis"));
3035 return -ETIMEDOUT;
3036 }
3037 }
3038
7134f9ce
JB		 3039 if (hw->revision_id == 0)
3040 mdelay(50);
3041
41c445ff
JB		 3042 return 0;
3043}
3044
3045/**
3046 * i40e_vsi_control_rx - Start or stop a VSI's rings
3047 * @vsi: the VSI being configured
3048 * @enable: start or stop the rings
3049 **/
3050static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3051{
3052 struct i40e_pf *pf = vsi->back;
3053 struct i40e_hw *hw = &pf->hw;
3054 int i, j, pf_q;
3055 u32 rx_reg;
3056
3057 pf_q = vsi->base_queue;
3058 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3059 j = 1000;
3060 do {
3061 usleep_range(1000, 2000);
3062 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3063 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3064 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3065
3066 if (enable) {
3067 /* is STAT set ? */
3068 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3069 continue;
3070 } else {
3071 /* is !STAT set ? */
3072 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3073 continue;
3074 }
3075
3076 /* turn on/off the queue */
3077 if (enable)
3078 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3079 I40E_QRX_ENA_QENA_STAT_MASK;
3080 else
3081 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3082 I40E_QRX_ENA_QENA_STAT_MASK);
3083 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3084
3085 /* wait for the change to finish */
3086 for (j = 0; j < 10; j++) {
3087 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3088
3089 if (enable) {
3090 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3091 break;
3092 } else {
3093 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3094 break;
3095 }
3096
3097 udelay(10);
3098 }
3099 if (j >= 10) {
3100 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3101 pf_q, (enable ? "en" : "dis"));
3102 return -ETIMEDOUT;
3103 }
3104 }
3105
3106 return 0;
3107}
3108
3109/**
3110 * i40e_vsi_control_rings - Start or stop a VSI's rings
3111 * @vsi: the VSI being configured
3112 * @enable: start or stop the rings
3113 **/
fc18eaa0 3114int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff
JB		 3115{
3116 int ret;
3117
3118 /* do rx first for enable and last for disable */
3119 if (request) {
3120 ret = i40e_vsi_control_rx(vsi, request);
3121 if (ret)
3122 return ret;
3123 ret = i40e_vsi_control_tx(vsi, request);
3124 } else {
3125 ret = i40e_vsi_control_tx(vsi, request);
3126 if (ret)
3127 return ret;
3128 ret = i40e_vsi_control_rx(vsi, request);
3129 }
3130
3131 return ret;
3132}
3133
3134/**
3135 * i40e_vsi_free_irq - Free the irq association with the OS
3136 * @vsi: the VSI being configured
3137 **/
3138static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3139{
3140 struct i40e_pf *pf = vsi->back;
3141 struct i40e_hw *hw = &pf->hw;
3142 int base = vsi->base_vector;
3143 u32 val, qp;
3144 int i;
3145
3146 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3147 if (!vsi->q_vectors)
3148 return;
3149
3150 for (i = 0; i < vsi->num_q_vectors; i++) {
3151 u16 vector = i + base;
3152
3153 /* free only the irqs that were actually requested */
78681b1f
SN		 3154 if (!vsi->q_vectors[i] ||
3155 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3156 continue;
3157
3158 /* clear the affinity_mask in the IRQ descriptor */
3159 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3160 NULL);
3161 free_irq(pf->msix_entries[vector].vector,
493fb300 3162 vsi->q_vectors[i]);
41c445ff
JB		 3163
3164 /* Tear down the interrupt queue link list
3165 *
3166 * We know that they come in pairs and always
3167 * the Rx first, then the Tx. To clear the
3168 * link list, stick the EOL value into the
3169 * next_q field of the registers.
3170 */
3171 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3172 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3173 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3174 val |= I40E_QUEUE_END_OF_LIST
3175 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3176 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3177
3178 while (qp != I40E_QUEUE_END_OF_LIST) {
3179 u32 next;
3180
3181 val = rd32(hw, I40E_QINT_RQCTL(qp));
3182
3183 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3184 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3185 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3186 I40E_QINT_RQCTL_INTEVENT_MASK);
3187
3188 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3189 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3190
3191 wr32(hw, I40E_QINT_RQCTL(qp), val);
3192
3193 val = rd32(hw, I40E_QINT_TQCTL(qp));
3194
3195 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3196 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3197
3198 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3199 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3200 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3201 I40E_QINT_TQCTL_INTEVENT_MASK);
3202
3203 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3204 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3205
3206 wr32(hw, I40E_QINT_TQCTL(qp), val);
3207 qp = next;
3208 }
3209 }
3210 } else {
3211 free_irq(pf->pdev->irq, pf);
3212
3213 val = rd32(hw, I40E_PFINT_LNKLST0);
3214 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3215 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3216 val |= I40E_QUEUE_END_OF_LIST
3217 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3218 wr32(hw, I40E_PFINT_LNKLST0, val);
3219
3220 val = rd32(hw, I40E_QINT_RQCTL(qp));
3221 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3222 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3223 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3224 I40E_QINT_RQCTL_INTEVENT_MASK);
3225
3226 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3227 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3228
3229 wr32(hw, I40E_QINT_RQCTL(qp), val);
3230
3231 val = rd32(hw, I40E_QINT_TQCTL(qp));
3232
3233 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3234 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3235 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3236 I40E_QINT_TQCTL_INTEVENT_MASK);
3237
3238 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3239 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3240
3241 wr32(hw, I40E_QINT_TQCTL(qp), val);
3242 }
3243}
3244
493fb300
AD		 3245/**
3246 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3247 * @vsi: the VSI being configured
3248 * @v_idx: Index of vector to be freed
3249 *
3250 * This function frees the memory allocated to the q_vector. In addition if
3251 * NAPI is enabled it will delete any references to the NAPI struct prior
3252 * to freeing the q_vector.
3253 **/
3254static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3255{
3256 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3257 struct i40e_ring *ring;
493fb300
AD		 3258
3259 if (!q_vector)
3260 return;
3261
3262 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3263 i40e_for_each_ring(ring, q_vector->tx)
3264 ring->q_vector = NULL;
3265
3266 i40e_for_each_ring(ring, q_vector->rx)
3267 ring->q_vector = NULL;
493fb300
AD		 3268
3269 /* only VSI w/ an associated netdev is set up w/ NAPI */
3270 if (vsi->netdev)
3271 netif_napi_del(&q_vector->napi);
3272
3273 vsi->q_vectors[v_idx] = NULL;
3274
3275 kfree_rcu(q_vector, rcu);
3276}
3277
41c445ff
JB		 3278/**
3279 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3280 * @vsi: the VSI being un-configured
3281 *
3282 * This frees the memory allocated to the q_vectors and
3283 * deletes references to the NAPI struct.
3284 **/
3285static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3286{
3287 int v_idx;
3288
493fb300
AD		 3289 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3290 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3291}
3292
3293/**
3294 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3295 * @pf: board private structure
3296 **/
3297static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3298{
3299 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3300 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3301 pci_disable_msix(pf->pdev);
3302 kfree(pf->msix_entries);
3303 pf->msix_entries = NULL;
3304 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3305 pci_disable_msi(pf->pdev);
3306 }
3307 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3308}
3309
3310/**
3311 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3312 * @pf: board private structure
3313 *
3314 * We go through and clear interrupt specific resources and reset the structure
3315 * to pre-load conditions
3316 **/
3317static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3318{
3319 int i;
3320
3321 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3322 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3323 if (pf->vsi[i])
3324 i40e_vsi_free_q_vectors(pf->vsi[i]);
3325 i40e_reset_interrupt_capability(pf);
3326}
3327
3328/**
3329 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3330 * @vsi: the VSI being configured
3331 **/
3332static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3333{
3334 int q_idx;
3335
3336 if (!vsi->netdev)
3337 return;
3338
3339 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3340 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3341}
3342
3343/**
3344 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3345 * @vsi: the VSI being configured
3346 **/
3347static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3348{
3349 int q_idx;
3350
3351 if (!vsi->netdev)
3352 return;
3353
3354 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3355 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3356}
3357
3358/**
3359 * i40e_quiesce_vsi - Pause a given VSI
3360 * @vsi: the VSI being paused
3361 **/
3362static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3363{
3364 if (test_bit(__I40E_DOWN, &vsi->state))
3365 return;
3366
3367 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3368 if (vsi->netdev && netif_running(vsi->netdev)) {
3369 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3370 } else {
3371 set_bit(__I40E_DOWN, &vsi->state);
3372 i40e_down(vsi);
3373 }
3374}
3375
3376/**
3377 * i40e_unquiesce_vsi - Resume a given VSI
3378 * @vsi: the VSI being resumed
3379 **/
3380static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3381{
3382 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3383 return;
3384
3385 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3386 if (vsi->netdev && netif_running(vsi->netdev))
3387 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3388 else
3389 i40e_up(vsi); /* this clears the DOWN bit */
3390}
3391
3392/**
3393 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3394 * @pf: the PF
3395 **/
3396static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3397{
3398 int v;
3399
3400 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3401 if (pf->vsi[v])
3402 i40e_quiesce_vsi(pf->vsi[v]);
3403 }
3404}
3405
3406/**
3407 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3408 * @pf: the PF
3409 **/
3410static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3411{
3412 int v;
3413
3414 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3415 if (pf->vsi[v])
3416 i40e_unquiesce_vsi(pf->vsi[v]);
3417 }
3418}
3419
3420/**
3421 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3422 * @dcbcfg: the corresponding DCBx configuration structure
3423 *
3424 * Return the number of TCs from given DCBx configuration
3425 **/
3426static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3427{
078b5876
JB		 3428 u8 num_tc = 0;
3429 int i;
41c445ff
JB		 3430
3431 /* Scan the ETS Config Priority Table to find
3432 * traffic class enabled for a given priority
3433 * and use the traffic class index to get the
3434 * number of traffic classes enabled
3435 */
3436 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3437 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3438 num_tc = dcbcfg->etscfg.prioritytable[i];
3439 }
3440
3441 /* Traffic class index starts from zero so
3442 * increment to return the actual count
3443 */
078b5876 3444 return num_tc + 1;
41c445ff
JB		 3445}
3446
3447/**
3448 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3449 * @dcbcfg: the corresponding DCBx configuration structure
3450 *
3451 * Query the current DCB configuration and return the number of
3452 * traffic classes enabled from the given DCBX config
3453 **/
3454static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3455{
3456 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3457 u8 enabled_tc = 1;
3458 u8 i;
3459
3460 for (i = 0; i < num_tc; i++)
3461 enabled_tc |= 1 << i;
3462
3463 return enabled_tc;
3464}
3465
3466/**
3467 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3468 * @pf: PF being queried
3469 *
3470 * Return number of traffic classes enabled for the given PF
3471 **/
3472static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3473{
3474 struct i40e_hw *hw = &pf->hw;
3475 u8 i, enabled_tc;
3476 u8 num_tc = 0;
3477 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3478
3479 /* If DCB is not enabled then always in single TC */
3480 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3481 return 1;
3482
3483 /* MFP mode return count of enabled TCs for this PF */
3484 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3485 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3486 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3487 if (enabled_tc & (1 << i))
3488 num_tc++;
3489 }
3490 return num_tc;
3491 }
3492
3493 /* SFP mode will be enabled for all TCs on port */
3494 return i40e_dcb_get_num_tc(dcbcfg);
3495}
3496
3497/**
3498 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3499 * @pf: PF being queried
3500 *
3501 * Return a bitmap for first enabled traffic class for this PF.
3502 **/
3503static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3504{
3505 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3506 u8 i = 0;
3507
3508 if (!enabled_tc)
3509 return 0x1; /* TC0 */
3510
3511 /* Find the first enabled TC */
3512 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3513 if (enabled_tc & (1 << i))
3514 break;
3515 }
3516
3517 return 1 << i;
3518}
3519
3520/**
3521 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3522 * @pf: PF being queried
3523 *
3524 * Return a bitmap for enabled traffic classes for this PF.
3525 **/
3526static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3527{
3528 /* If DCB is not enabled for this PF then just return default TC */
3529 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3530 return i40e_pf_get_default_tc(pf);
3531
3532 /* MFP mode will have enabled TCs set by FW */
3533 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3534 return pf->hw.func_caps.enabled_tcmap;
3535
3536 /* SFP mode we want PF to be enabled for all TCs */
3537 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3538}
3539
3540/**
3541 * i40e_vsi_get_bw_info - Query VSI BW Information
3542 * @vsi: the VSI being queried
3543 *
3544 * Returns 0 on success, negative value on failure
3545 **/
3546static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3547{
3548 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3549 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3550 struct i40e_pf *pf = vsi->back;
3551 struct i40e_hw *hw = &pf->hw;
dcae29be 3552 i40e_status aq_ret;
41c445ff 3553 u32 tc_bw_max;
41c445ff
JB		 3554 int i;
3555
3556 /* Get the VSI level BW configuration */
dcae29be
JB		 3557 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3558 if (aq_ret) {
41c445ff
JB		 3559 dev_info(&pf->pdev->dev,
3560 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3561 aq_ret, pf->hw.aq.asq_last_status);
3562 return -EINVAL;
41c445ff
JB		 3563 }
3564
3565 /* Get the VSI level BW configuration per TC */
dcae29be
JB		 3566 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
3567 NULL);
3568 if (aq_ret) {
41c445ff
JB		 3569 dev_info(&pf->pdev->dev,
3570 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3571 aq_ret, pf->hw.aq.asq_last_status);
3572 return -EINVAL;
41c445ff
JB		 3573 }
3574
3575 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3576 dev_info(&pf->pdev->dev,
3577 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3578 bw_config.tc_valid_bits,
3579 bw_ets_config.tc_valid_bits);
3580 /* Still continuing */
3581 }
3582
3583 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3584 vsi->bw_max_quanta = bw_config.max_bw;
3585 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3586 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3587 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3588 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3589 vsi->bw_ets_limit_credits[i] =
3590 le16_to_cpu(bw_ets_config.credits[i]);
3591 /* 3 bits out of 4 for each TC */
3592 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3593 }
078b5876 3594
dcae29be 3595 return 0;
41c445ff
JB		 3596}
3597
3598/**
3599 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3600 * @vsi: the VSI being configured
3601 * @enabled_tc: TC bitmap
3602 * @bw_credits: BW shared credits per TC
3603 *
3604 * Returns 0 on success, negative value on failure
3605 **/
dcae29be 3606static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3607 u8 *bw_share)
3608{
3609 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3610 i40e_status aq_ret;
3611 int i;
41c445ff
JB		 3612
3613 bw_data.tc_valid_bits = enabled_tc;
3614 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3615 bw_data.tc_bw_credits[i] = bw_share[i];
3616
dcae29be
JB		 3617 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3618 NULL);
3619 if (aq_ret) {
41c445ff
JB		 3620 dev_info(&vsi->back->pdev->dev,
3621 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3622 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3623 return -EINVAL;
41c445ff
JB		 3624 }
3625
3626 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3627 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3628
dcae29be 3629 return 0;
41c445ff
JB		 3630}
3631
3632/**
3633 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3634 * @vsi: the VSI being configured
3635 * @enabled_tc: TC map to be enabled
3636 *
3637 **/
3638static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3639{
3640 struct net_device *netdev = vsi->netdev;
3641 struct i40e_pf *pf = vsi->back;
3642 struct i40e_hw *hw = &pf->hw;
3643 u8 netdev_tc = 0;
3644 int i;
3645 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3646
3647 if (!netdev)
3648 return;
3649
3650 if (!enabled_tc) {
3651 netdev_reset_tc(netdev);
3652 return;
3653 }
3654
3655 /* Set up actual enabled TCs on the VSI */
3656 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3657 return;
3658
3659 /* set per TC queues for the VSI */
3660 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3661 /* Only set TC queues for enabled tcs
3662 *
3663 * e.g. For a VSI that has TC0 and TC3 enabled the
3664 * enabled_tc bitmap would be 0x00001001; the driver
3665 * will set the numtc for netdev as 2 that will be
3666 * referenced by the netdev layer as TC 0 and 1.
3667 */
3668 if (vsi->tc_config.enabled_tc & (1 << i))
3669 netdev_set_tc_queue(netdev,
3670 vsi->tc_config.tc_info[i].netdev_tc,
3671 vsi->tc_config.tc_info[i].qcount,
3672 vsi->tc_config.tc_info[i].qoffset);
3673 }
3674
3675 /* Assign UP2TC map for the VSI */
3676 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3677 /* Get the actual TC# for the UP */
3678 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3679 /* Get the mapped netdev TC# for the UP */
3680 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3681 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3682 }
3683}
3684
3685/**
3686 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3687 * @vsi: the VSI being configured
3688 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3689 **/
3690static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3691 struct i40e_vsi_context *ctxt)
3692{
3693 /* copy just the sections touched not the entire info
3694 * since not all sections are valid as returned by
3695 * update vsi params
3696 */
3697 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3698 memcpy(&vsi->info.queue_mapping,
3699 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3700 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3701 sizeof(vsi->info.tc_mapping));
3702}
3703
3704/**
3705 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3706 * @vsi: VSI to be configured
3707 * @enabled_tc: TC bitmap
3708 *
3709 * This configures a particular VSI for TCs that are mapped to the
3710 * given TC bitmap. It uses default bandwidth share for TCs across
3711 * VSIs to configure TC for a particular VSI.
3712 *
3713 * NOTE:
3714 * It is expected that the VSI queues have been quisced before calling
3715 * this function.
3716 **/
3717static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3718{
3719 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3720 struct i40e_vsi_context ctxt;
3721 int ret = 0;
3722 int i;
3723
3724 /* Check if enabled_tc is same as existing or new TCs */
3725 if (vsi->tc_config.enabled_tc == enabled_tc)
3726 return ret;
3727
3728 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3729 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3730 if (enabled_tc & (1 << i))
3731 bw_share[i] = 1;
3732 }
3733
3734 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3735 if (ret) {
3736 dev_info(&vsi->back->pdev->dev,
3737 "Failed configuring TC map %d for VSI %d\n",
3738 enabled_tc, vsi->seid);
3739 goto out;
3740 }
3741
3742 /* Update Queue Pairs Mapping for currently enabled UPs */
3743 ctxt.seid = vsi->seid;
3744 ctxt.pf_num = vsi->back->hw.pf_id;
3745 ctxt.vf_num = 0;
3746 ctxt.uplink_seid = vsi->uplink_seid;
3747 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3748 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3749
3750 /* Update the VSI after updating the VSI queue-mapping information */
3751 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3752 if (ret) {
3753 dev_info(&vsi->back->pdev->dev,
3754 "update vsi failed, aq_err=%d\n",
3755 vsi->back->hw.aq.asq_last_status);
3756 goto out;
3757 }
3758 /* update the local VSI info with updated queue map */
3759 i40e_vsi_update_queue_map(vsi, &ctxt);
3760 vsi->info.valid_sections = 0;
3761
3762 /* Update current VSI BW information */
3763 ret = i40e_vsi_get_bw_info(vsi);
3764 if (ret) {
3765 dev_info(&vsi->back->pdev->dev,
3766 "Failed updating vsi bw info, aq_err=%d\n",
3767 vsi->back->hw.aq.asq_last_status);
3768 goto out;
3769 }
3770
3771 /* Update the netdev TC setup */
3772 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3773out:
3774 return ret;
3775}
3776
3777/**
3778 * i40e_up_complete - Finish the last steps of bringing up a connection
3779 * @vsi: the VSI being configured
3780 **/
3781static int i40e_up_complete(struct i40e_vsi *vsi)
3782{
3783 struct i40e_pf *pf = vsi->back;
3784 int err;
3785
3786 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3787 i40e_vsi_configure_msix(vsi);
3788 else
3789 i40e_configure_msi_and_legacy(vsi);
3790
3791 /* start rings */
3792 err = i40e_vsi_control_rings(vsi, true);
3793 if (err)
3794 return err;
3795
3796 clear_bit(__I40E_DOWN, &vsi->state);
3797 i40e_napi_enable_all(vsi);
3798 i40e_vsi_enable_irq(vsi);
3799
3800 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
3801 (vsi->netdev)) {
6d779b41 3802 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 3803 netif_tx_start_all_queues(vsi->netdev);
3804 netif_carrier_on(vsi->netdev);
6d779b41
AS		 3805 } else if (vsi->netdev) {
3806 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 3807 }
3808 i40e_service_event_schedule(pf);
3809
3810 return 0;
3811}
3812
3813/**
3814 * i40e_vsi_reinit_locked - Reset the VSI
3815 * @vsi: the VSI being configured
3816 *
3817 * Rebuild the ring structs after some configuration
3818 * has changed, e.g. MTU size.
3819 **/
3820static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
3821{
3822 struct i40e_pf *pf = vsi->back;
3823
3824 WARN_ON(in_interrupt());
3825 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
3826 usleep_range(1000, 2000);
3827 i40e_down(vsi);
3828
3829 /* Give a VF some time to respond to the reset. The
3830 * two second wait is based upon the watchdog cycle in
3831 * the VF driver.
3832 */
3833 if (vsi->type == I40E_VSI_SRIOV)
3834 msleep(2000);
3835 i40e_up(vsi);
3836 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
3837}
3838
3839/**
3840 * i40e_up - Bring the connection back up after being down
3841 * @vsi: the VSI being configured
3842 **/
3843int i40e_up(struct i40e_vsi *vsi)
3844{
3845 int err;
3846
3847 err = i40e_vsi_configure(vsi);
3848 if (!err)
3849 err = i40e_up_complete(vsi);
3850
3851 return err;
3852}
3853
3854/**
3855 * i40e_down - Shutdown the connection processing
3856 * @vsi: the VSI being stopped
3857 **/
3858void i40e_down(struct i40e_vsi *vsi)
3859{
3860 int i;
3861
3862 /* It is assumed that the caller of this function
3863 * sets the vsi->state __I40E_DOWN bit.
3864 */
3865 if (vsi->netdev) {
3866 netif_carrier_off(vsi->netdev);
3867 netif_tx_disable(vsi->netdev);
3868 }
3869 i40e_vsi_disable_irq(vsi);
3870 i40e_vsi_control_rings(vsi, false);
3871 i40e_napi_disable_all(vsi);
3872
3873 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3874 i40e_clean_tx_ring(vsi->tx_rings[i]);
3875 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3876 }
3877}
3878
3879/**
3880 * i40e_setup_tc - configure multiple traffic classes
3881 * @netdev: net device to configure
3882 * @tc: number of traffic classes to enable
3883 **/
3884static int i40e_setup_tc(struct net_device *netdev, u8 tc)
3885{
3886 struct i40e_netdev_priv *np = netdev_priv(netdev);
3887 struct i40e_vsi *vsi = np->vsi;
3888 struct i40e_pf *pf = vsi->back;
3889 u8 enabled_tc = 0;
3890 int ret = -EINVAL;
3891 int i;
3892
3893 /* Check if DCB enabled to continue */
3894 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
3895 netdev_info(netdev, "DCB is not enabled for adapter\n");
3896 goto exit;
3897 }
3898
3899 /* Check if MFP enabled */
3900 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3901 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
3902 goto exit;
3903 }
3904
3905 /* Check whether tc count is within enabled limit */
3906 if (tc > i40e_pf_get_num_tc(pf)) {
3907 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
3908 goto exit;
3909 }
3910
3911 /* Generate TC map for number of tc requested */
3912 for (i = 0; i < tc; i++)
3913 enabled_tc |= (1 << i);
3914
3915 /* Requesting same TC configuration as already enabled */
3916 if (enabled_tc == vsi->tc_config.enabled_tc)
3917 return 0;
3918
3919 /* Quiesce VSI queues */
3920 i40e_quiesce_vsi(vsi);
3921
3922 /* Configure VSI for enabled TCs */
3923 ret = i40e_vsi_config_tc(vsi, enabled_tc);
3924 if (ret) {
3925 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
3926 vsi->seid);
3927 goto exit;
3928 }
3929
3930 /* Unquiesce VSI */
3931 i40e_unquiesce_vsi(vsi);
3932
3933exit:
3934 return ret;
3935}
3936
3937/**
3938 * i40e_open - Called when a network interface is made active
3939 * @netdev: network interface device structure
3940 *
3941 * The open entry point is called when a network interface is made
3942 * active by the system (IFF_UP). At this point all resources needed
3943 * for transmit and receive operations are allocated, the interrupt
3944 * handler is registered with the OS, the netdev watchdog subtask is
3945 * enabled, and the stack is notified that the interface is ready.
3946 *
3947 * Returns 0 on success, negative value on failure
3948 **/
3949static int i40e_open(struct net_device *netdev)
3950{
3951 struct i40e_netdev_priv *np = netdev_priv(netdev);
3952 struct i40e_vsi *vsi = np->vsi;
3953 struct i40e_pf *pf = vsi->back;
3954 char int_name[IFNAMSIZ];
3955 int err;
3956
3957 /* disallow open during test */
3958 if (test_bit(__I40E_TESTING, &pf->state))
3959 return -EBUSY;
3960
3961 netif_carrier_off(netdev);
3962
3963 /* allocate descriptors */
3964 err = i40e_vsi_setup_tx_resources(vsi);
3965 if (err)
3966 goto err_setup_tx;
3967 err = i40e_vsi_setup_rx_resources(vsi);
3968 if (err)
3969 goto err_setup_rx;
3970
3971 err = i40e_vsi_configure(vsi);
3972 if (err)
3973 goto err_setup_rx;
3974
3975 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
3976 dev_driver_string(&pf->pdev->dev), netdev->name);
3977 err = i40e_vsi_request_irq(vsi, int_name);
3978 if (err)
3979 goto err_setup_rx;
3980
25946ddb 3981 /* Notify the stack of the actual queue counts. */
d7397644 3982 err = netif_set_real_num_tx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3983 if (err)
3984 goto err_set_queues;
3985
d7397644 3986 err = netif_set_real_num_rx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3987 if (err)
3988 goto err_set_queues;
3989
41c445ff
JB		 3990 err = i40e_up_complete(vsi);
3991 if (err)
3992 goto err_up_complete;
3993
3994 if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
3995 err = i40e_aq_set_vsi_broadcast(&pf->hw, vsi->seid, true, NULL);
3996 if (err)
3997 netdev_info(netdev,
3998 "couldn't set broadcast err %d aq_err %d\n",
3999 err, pf->hw.aq.asq_last_status);
4000 }
a1c9a9d9
JK		 4001#ifdef CONFIG_I40E_VXLAN
4002 vxlan_get_rx_port(netdev);
4003#endif
41c445ff
JB		 4004
4005 return 0;
4006
4007err_up_complete:
4008 i40e_down(vsi);
25946ddb 4009err_set_queues:
41c445ff
JB		 4010 i40e_vsi_free_irq(vsi);
4011err_setup_rx:
4012 i40e_vsi_free_rx_resources(vsi);
4013err_setup_tx:
4014 i40e_vsi_free_tx_resources(vsi);
4015 if (vsi == pf->vsi[pf->lan_vsi])
4016 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4017
4018 return err;
4019}
4020
4021/**
4022 * i40e_close - Disables a network interface
4023 * @netdev: network interface device structure
4024 *
4025 * The close entry point is called when an interface is de-activated
4026 * by the OS. The hardware is still under the driver's control, but
4027 * this netdev interface is disabled.
4028 *
4029 * Returns 0, this is not allowed to fail
4030 **/
4031static int i40e_close(struct net_device *netdev)
4032{
4033 struct i40e_netdev_priv *np = netdev_priv(netdev);
4034 struct i40e_vsi *vsi = np->vsi;
4035
4036 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4037 return 0;
4038
4039 i40e_down(vsi);
4040 i40e_vsi_free_irq(vsi);
4041
4042 i40e_vsi_free_tx_resources(vsi);
4043 i40e_vsi_free_rx_resources(vsi);
4044
4045 return 0;
4046}
4047
4048/**
4049 * i40e_do_reset - Start a PF or Core Reset sequence
4050 * @pf: board private structure
4051 * @reset_flags: which reset is requested
4052 *
4053 * The essential difference in resets is that the PF Reset
4054 * doesn't clear the packet buffers, doesn't reset the PE
4055 * firmware, and doesn't bother the other PFs on the chip.
4056 **/
4057void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4058{
4059 u32 val;
4060
4061 WARN_ON(in_interrupt());
4062
4063 /* do the biggest reset indicated */
4064 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4065
4066 /* Request a Global Reset
4067 *
4068 * This will start the chip's countdown to the actual full
4069 * chip reset event, and a warning interrupt to be sent
4070 * to all PFs, including the requestor. Our handler
4071 * for the warning interrupt will deal with the shutdown
4072 * and recovery of the switch setup.
4073 */
4074 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4075 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4076 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4077 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4078
4079 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4080
4081 /* Request a Core Reset
4082 *
4083 * Same as Global Reset, except does *not* include the MAC/PHY
4084 */
4085 dev_info(&pf->pdev->dev, "CoreR requested\n");
4086 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4087 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4088 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4089 i40e_flush(&pf->hw);
4090
7823fe34
SN		 4091 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4092
4093 /* Request a Firmware Reset
4094 *
4095 * Same as Global reset, plus restarting the
4096 * embedded firmware engine.
4097 */
4098 /* enable EMP Reset */
4099 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4100 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4101 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4102
4103 /* force the reset */
4104 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4105 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4106 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4107 i40e_flush(&pf->hw);
4108
41c445ff
JB		 4109 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4110
4111 /* Request a PF Reset
4112 *
4113 * Resets only the PF-specific registers
4114 *
4115 * This goes directly to the tear-down and rebuild of
4116 * the switch, since we need to do all the recovery as
4117 * for the Core Reset.
4118 */
4119 dev_info(&pf->pdev->dev, "PFR requested\n");
4120 i40e_handle_reset_warning(pf);
4121
4122 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4123 int v;
4124
4125 /* Find the VSI(s) that requested a re-init */
4126 dev_info(&pf->pdev->dev,
4127 "VSI reinit requested\n");
4128 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4129 struct i40e_vsi *vsi = pf->vsi[v];
4130 if (vsi != NULL &&
4131 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4132 i40e_vsi_reinit_locked(pf->vsi[v]);
4133 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4134 }
4135 }
4136
4137 /* no further action needed, so return now */
4138 return;
4139 } else {
4140 dev_info(&pf->pdev->dev,
4141 "bad reset request 0x%08x\n", reset_flags);
4142 return;
4143 }
4144}
4145
23326186
ASJ		 4146/**
4147 * i40e_do_reset_safe - Protected reset path for userland calls.
4148 * @pf: board private structure
4149 * @reset_flags: which reset is requested
4150 *
4151 **/
4152void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4153{
4154 rtnl_lock();
4155 i40e_do_reset(pf, reset_flags);
4156 rtnl_unlock();
4157}
4158
41c445ff
JB		 4159/**
4160 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4161 * @pf: board private structure
4162 * @e: event info posted on ARQ
4163 *
4164 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4165 * and VF queues
4166 **/
4167static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4168 struct i40e_arq_event_info *e)
4169{
4170 struct i40e_aqc_lan_overflow *data =
4171 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4172 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4173 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4174 struct i40e_hw *hw = &pf->hw;
4175 struct i40e_vf *vf;
4176 u16 vf_id;
4177
4178 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4179 __func__, queue, qtx_ctl);
4180
4181 /* Queue belongs to VF, find the VF and issue VF reset */
4182 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4183 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4184 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4185 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4186 vf_id -= hw->func_caps.vf_base_id;
4187 vf = &pf->vf[vf_id];
4188 i40e_vc_notify_vf_reset(vf);
4189 /* Allow VF to process pending reset notification */
4190 msleep(20);
4191 i40e_reset_vf(vf, false);
4192 }
4193}
4194
4195/**
4196 * i40e_service_event_complete - Finish up the service event
4197 * @pf: board private structure
4198 **/
4199static void i40e_service_event_complete(struct i40e_pf *pf)
4200{
4201 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4202
4203 /* flush memory to make sure state is correct before next watchog */
4204 smp_mb__before_clear_bit();
4205 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4206}
4207
4208/**
4209 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4210 * @pf: board private structure
4211 **/
4212static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4213{
4214 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4215 return;
4216
4217 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4218
4219 /* if interface is down do nothing */
4220 if (test_bit(__I40E_DOWN, &pf->state))
4221 return;
4222}
4223
4224/**
4225 * i40e_vsi_link_event - notify VSI of a link event
4226 * @vsi: vsi to be notified
4227 * @link_up: link up or down
4228 **/
4229static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4230{
4231 if (!vsi)
4232 return;
4233
4234 switch (vsi->type) {
4235 case I40E_VSI_MAIN:
4236 if (!vsi->netdev || !vsi->netdev_registered)
4237 break;
4238
4239 if (link_up) {
4240 netif_carrier_on(vsi->netdev);
4241 netif_tx_wake_all_queues(vsi->netdev);
4242 } else {
4243 netif_carrier_off(vsi->netdev);
4244 netif_tx_stop_all_queues(vsi->netdev);
4245 }
4246 break;
4247
4248 case I40E_VSI_SRIOV:
4249 break;
4250
4251 case I40E_VSI_VMDQ2:
4252 case I40E_VSI_CTRL:
4253 case I40E_VSI_MIRROR:
4254 default:
4255 /* there is no notification for other VSIs */
4256 break;
4257 }
4258}
4259
4260/**
4261 * i40e_veb_link_event - notify elements on the veb of a link event
4262 * @veb: veb to be notified
4263 * @link_up: link up or down
4264 **/
4265static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4266{
4267 struct i40e_pf *pf;
4268 int i;
4269
4270 if (!veb || !veb->pf)
4271 return;
4272 pf = veb->pf;
4273
4274 /* depth first... */
4275 for (i = 0; i < I40E_MAX_VEB; i++)
4276 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4277 i40e_veb_link_event(pf->veb[i], link_up);
4278
4279 /* ... now the local VSIs */
4280 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4281 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4282 i40e_vsi_link_event(pf->vsi[i], link_up);
4283}
4284
4285/**
4286 * i40e_link_event - Update netif_carrier status
4287 * @pf: board private structure
4288 **/
4289static void i40e_link_event(struct i40e_pf *pf)
4290{
4291 bool new_link, old_link;
4292
4293 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4294 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4295
4296 if (new_link == old_link)
4297 return;
4298
6d779b41
AS		 4299 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4300 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4301 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4302
4303 /* Notify the base of the switch tree connected to
4304 * the link. Floating VEBs are not notified.
4305 */
4306 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4307 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4308 else
4309 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4310
4311 if (pf->vf)
4312 i40e_vc_notify_link_state(pf);
4313}
4314
4315/**
4316 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4317 * @pf: board private structure
4318 *
4319 * Set the per-queue flags to request a check for stuck queues in the irq
4320 * clean functions, then force interrupts to be sure the irq clean is called.
4321 **/
4322static void i40e_check_hang_subtask(struct i40e_pf *pf)
4323{
4324 int i, v;
4325
4326 /* If we're down or resetting, just bail */
4327 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4328 return;
4329
4330 /* for each VSI/netdev
4331 * for each Tx queue
4332 * set the check flag
4333 * for each q_vector
4334 * force an interrupt
4335 */
4336 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4337 struct i40e_vsi *vsi = pf->vsi[v];
4338 int armed = 0;
4339
4340 if (!pf->vsi[v] ||
4341 test_bit(__I40E_DOWN, &vsi->state) ||
4342 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4343 continue;
4344
4345 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4346 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4347 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4348 &vsi->tx_rings[i]->state))
41c445ff
JB		 4349 armed++;
4350 }
4351
4352 if (armed) {
4353 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4354 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4355 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4356 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4357 } else {
4358 u16 vec = vsi->base_vector - 1;
4359 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4360 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4361 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4362 wr32(&vsi->back->hw,
4363 I40E_PFINT_DYN_CTLN(vec), val);
4364 }
4365 i40e_flush(&vsi->back->hw);
4366 }
4367 }
4368}
4369
4370/**
4371 * i40e_watchdog_subtask - Check and bring link up
4372 * @pf: board private structure
4373 **/
4374static void i40e_watchdog_subtask(struct i40e_pf *pf)
4375{
4376 int i;
4377
4378 /* if interface is down do nothing */
4379 if (test_bit(__I40E_DOWN, &pf->state) ||
4380 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4381 return;
4382
4383 /* Update the stats for active netdevs so the network stack
4384 * can look at updated numbers whenever it cares to
4385 */
4386 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4387 if (pf->vsi[i] && pf->vsi[i]->netdev)
4388 i40e_update_stats(pf->vsi[i]);
4389
4390 /* Update the stats for the active switching components */
4391 for (i = 0; i < I40E_MAX_VEB; i++)
4392 if (pf->veb[i])
4393 i40e_update_veb_stats(pf->veb[i]);
4394}
4395
4396/**
4397 * i40e_reset_subtask - Set up for resetting the device and driver
4398 * @pf: board private structure
4399 **/
4400static void i40e_reset_subtask(struct i40e_pf *pf)
4401{
4402 u32 reset_flags = 0;
4403
23326186 4404 rtnl_lock();
41c445ff
JB		 4405 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4406 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4407 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4408 }
4409 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4410 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4411 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4412 }
4413 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4414 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4415 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4416 }
4417 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4418 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4419 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4420 }
4421
4422 /* If there's a recovery already waiting, it takes
4423 * precedence before starting a new reset sequence.
4424 */
4425 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4426 i40e_handle_reset_warning(pf);
23326186 4427 goto unlock;
41c445ff
JB		 4428 }
4429
4430 /* If we're already down or resetting, just bail */
4431 if (reset_flags &&
4432 !test_bit(__I40E_DOWN, &pf->state) &&
4433 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4434 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4435
4436unlock:
4437 rtnl_unlock();
41c445ff
JB		 4438}
4439
4440/**
4441 * i40e_handle_link_event - Handle link event
4442 * @pf: board private structure
4443 * @e: event info posted on ARQ
4444 **/
4445static void i40e_handle_link_event(struct i40e_pf *pf,
4446 struct i40e_arq_event_info *e)
4447{
4448 struct i40e_hw *hw = &pf->hw;
4449 struct i40e_aqc_get_link_status *status =
4450 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4451 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4452
4453 /* save off old link status information */
4454 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4455 sizeof(pf->hw.phy.link_info_old));
4456
4457 /* update link status */
4458 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4459 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4460 hw_link_info->link_info = status->link_info;
4461 hw_link_info->an_info = status->an_info;
4462 hw_link_info->ext_info = status->ext_info;
4463 hw_link_info->lse_enable =
4464 le16_to_cpu(status->command_flags) &
4465 I40E_AQ_LSE_ENABLE;
4466
4467 /* process the event */
4468 i40e_link_event(pf);
4469
4470 /* Do a new status request to re-enable LSE reporting
4471 * and load new status information into the hw struct,
4472 * then see if the status changed while processing the
4473 * initial event.
4474 */
4475 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4476 i40e_link_event(pf);
4477}
4478
4479/**
4480 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4481 * @pf: board private structure
4482 **/
4483static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4484{
4485 struct i40e_arq_event_info event;
4486 struct i40e_hw *hw = &pf->hw;
4487 u16 pending, i = 0;
4488 i40e_status ret;
4489 u16 opcode;
4490 u32 val;
4491
4492 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4493 return;
4494
3197ce22 4495 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 4496 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4497 if (!event.msg_buf)
4498 return;
4499
4500 do {
2f019123 4501 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 4502 ret = i40e_clean_arq_element(hw, &event, &pending);
4503 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4504 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4505 break;
4506 } else if (ret) {
4507 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4508 break;
4509 }
4510
4511 opcode = le16_to_cpu(event.desc.opcode);
4512 switch (opcode) {
4513
4514 case i40e_aqc_opc_get_link_status:
4515 i40e_handle_link_event(pf, &event);
4516 break;
4517 case i40e_aqc_opc_send_msg_to_pf:
4518 ret = i40e_vc_process_vf_msg(pf,
4519 le16_to_cpu(event.desc.retval),
4520 le32_to_cpu(event.desc.cookie_high),
4521 le32_to_cpu(event.desc.cookie_low),
4522 event.msg_buf,
4523 event.msg_size);
4524 break;
4525 case i40e_aqc_opc_lldp_update_mib:
4526 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4527 break;
4528 case i40e_aqc_opc_event_lan_overflow:
4529 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4530 i40e_handle_lan_overflow_event(pf, &event);
4531 break;
4532 default:
4533 dev_info(&pf->pdev->dev,
4534 "ARQ Error: Unknown event %d received\n",
4535 event.desc.opcode);
4536 break;
4537 }
4538 } while (pending && (i++ < pf->adminq_work_limit));
4539
4540 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4541 /* re-enable Admin queue interrupt cause */
4542 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4543 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4544 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4545 i40e_flush(hw);
4546
4547 kfree(event.msg_buf);
4548}
4549
4550/**
4551 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4552 * @veb: pointer to the VEB instance
4553 *
4554 * This is a recursive function that first builds the attached VSIs then
4555 * recurses in to build the next layer of VEB. We track the connections
4556 * through our own index numbers because the seid's from the HW could
4557 * change across the reset.
4558 **/
4559static int i40e_reconstitute_veb(struct i40e_veb *veb)
4560{
4561 struct i40e_vsi *ctl_vsi = NULL;
4562 struct i40e_pf *pf = veb->pf;
4563 int v, veb_idx;
4564 int ret;
4565
4566 /* build VSI that owns this VEB, temporarily attached to base VEB */
4567 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4568 if (pf->vsi[v] &&
4569 pf->vsi[v]->veb_idx == veb->idx &&
4570 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4571 ctl_vsi = pf->vsi[v];
4572 break;
4573 }
4574 }
4575 if (!ctl_vsi) {
4576 dev_info(&pf->pdev->dev,
4577 "missing owner VSI for veb_idx %d\n", veb->idx);
4578 ret = -ENOENT;
4579 goto end_reconstitute;
4580 }
4581 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4582 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4583 ret = i40e_add_vsi(ctl_vsi);
4584 if (ret) {
4585 dev_info(&pf->pdev->dev,
4586 "rebuild of owner VSI failed: %d\n", ret);
4587 goto end_reconstitute;
4588 }
4589 i40e_vsi_reset_stats(ctl_vsi);
4590
4591 /* create the VEB in the switch and move the VSI onto the VEB */
4592 ret = i40e_add_veb(veb, ctl_vsi);
4593 if (ret)
4594 goto end_reconstitute;
4595
4596 /* create the remaining VSIs attached to this VEB */
4597 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4598 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4599 continue;
4600
4601 if (pf->vsi[v]->veb_idx == veb->idx) {
4602 struct i40e_vsi *vsi = pf->vsi[v];
4603 vsi->uplink_seid = veb->seid;
4604 ret = i40e_add_vsi(vsi);
4605 if (ret) {
4606 dev_info(&pf->pdev->dev,
4607 "rebuild of vsi_idx %d failed: %d\n",
4608 v, ret);
4609 goto end_reconstitute;
4610 }
4611 i40e_vsi_reset_stats(vsi);
4612 }
4613 }
4614
4615 /* create any VEBs attached to this VEB - RECURSION */
4616 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
4617 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
4618 pf->veb[veb_idx]->uplink_seid = veb->seid;
4619 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
4620 if (ret)
4621 break;
4622 }
4623 }
4624
4625end_reconstitute:
4626 return ret;
4627}
4628
4629/**
4630 * i40e_get_capabilities - get info about the HW
4631 * @pf: the PF struct
4632 **/
4633static int i40e_get_capabilities(struct i40e_pf *pf)
4634{
4635 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
4636 u16 data_size;
4637 int buf_len;
4638 int err;
4639
4640 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
4641 do {
4642 cap_buf = kzalloc(buf_len, GFP_KERNEL);
4643 if (!cap_buf)
4644 return -ENOMEM;
4645
4646 /* this loads the data into the hw struct for us */
4647 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
4648 &data_size,
4649 i40e_aqc_opc_list_func_capabilities,
4650 NULL);
4651 /* data loaded, buffer no longer needed */
4652 kfree(cap_buf);
4653
4654 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
4655 /* retry with a larger buffer */
4656 buf_len = data_size;
4657 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
4658 dev_info(&pf->pdev->dev,
4659 "capability discovery failed: aq=%d\n",
4660 pf->hw.aq.asq_last_status);
4661 return -ENODEV;
4662 }
4663 } while (err);
4664
7134f9ce
JB		 4665 if (pf->hw.revision_id == 0 && pf->hw.func_caps.npar_enable) {
4666 pf->hw.func_caps.num_msix_vectors += 1;
4667 pf->hw.func_caps.num_tx_qp =
4668 min_t(int, pf->hw.func_caps.num_tx_qp,
4669 I40E_MAX_NPAR_QPS);
4670 }
4671
41c445ff
JB		 4672 if (pf->hw.debug_mask & I40E_DEBUG_USER)
4673 dev_info(&pf->pdev->dev,
4674 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
4675 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
4676 pf->hw.func_caps.num_msix_vectors,
4677 pf->hw.func_caps.num_msix_vectors_vf,
4678 pf->hw.func_caps.fd_filters_guaranteed,
4679 pf->hw.func_caps.fd_filters_best_effort,
4680 pf->hw.func_caps.num_tx_qp,
4681 pf->hw.func_caps.num_vsis);
4682
7134f9ce
JB		 4683#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
4684 + pf->hw.func_caps.num_vfs)
4685 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
4686 dev_info(&pf->pdev->dev,
4687 "got num_vsis %d, setting num_vsis to %d\n",
4688 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
4689 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
4690 }
4691
41c445ff
JB		 4692 return 0;
4693}
4694
4695/**
4696 * i40e_fdir_setup - initialize the Flow Director resources
4697 * @pf: board private structure
4698 **/
4699static void i40e_fdir_setup(struct i40e_pf *pf)
4700{
4701 struct i40e_vsi *vsi;
4702 bool new_vsi = false;
4703 int err, i;
4704
958a3e3b
SN		 4705 if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED |
4706 I40E_FLAG_FDIR_ATR_ENABLED)))
41c445ff
JB		 4707 return;
4708
4709 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
4710
4711 /* find existing or make new FDIR VSI */
4712 vsi = NULL;
4713 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4714 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
4715 vsi = pf->vsi[i];
4716 if (!vsi) {
4717 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
4718 if (!vsi) {
4719 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
4720 pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
4721 return;
4722 }
4723 new_vsi = true;
4724 }
4725 WARN_ON(vsi->base_queue != I40E_FDIR_RING);
4726 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
4727
4728 err = i40e_vsi_setup_tx_resources(vsi);
4729 if (!err)
4730 err = i40e_vsi_setup_rx_resources(vsi);
4731 if (!err)
4732 err = i40e_vsi_configure(vsi);
4733 if (!err && new_vsi) {
4734 char int_name[IFNAMSIZ + 9];
4735 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4736 dev_driver_string(&pf->pdev->dev));
4737 err = i40e_vsi_request_irq(vsi, int_name);
4738 }
4739 if (!err)
4740 err = i40e_up_complete(vsi);
4741
4742 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4743}
4744
4745/**
4746 * i40e_fdir_teardown - release the Flow Director resources
4747 * @pf: board private structure
4748 **/
4749static void i40e_fdir_teardown(struct i40e_pf *pf)
4750{
4751 int i;
4752
4753 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
4754 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
4755 i40e_vsi_release(pf->vsi[i]);
4756 break;
4757 }
4758 }
4759}
4760
4761/**
f650a38b 4762 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 4763 * @pf: board private structure
4764 *
f650a38b
ASJ		 4765 * Close up the VFs and other things in prep for pf Reset.
4766 **/
4767static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 4768{
41c445ff
JB		 4769 struct i40e_hw *hw = &pf->hw;
4770 i40e_status ret;
4771 u32 v;
4772
4773 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
4774 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 4775 return 0;
41c445ff
JB		 4776
4777 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
4778
4779 i40e_vc_notify_reset(pf);
4780
4781 /* quiesce the VSIs and their queues that are not already DOWN */
4782 i40e_pf_quiesce_all_vsi(pf);
4783
4784 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4785 if (pf->vsi[v])
4786 pf->vsi[v]->seid = 0;
4787 }
4788
4789 i40e_shutdown_adminq(&pf->hw);
4790
f650a38b
ASJ		 4791 /* call shutdown HMC */
4792 ret = i40e_shutdown_lan_hmc(hw);
4793 if (ret) {
4794 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
4795 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4796 }
4797 return ret;
4798}
4799
4800/**
4801 * i40e_reset_and_rebuild - reset and rebuid using a saved config
4802 * @pf: board private structure
bc7d338f 4803 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 4804 **/
bc7d338f 4805static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 4806{
4807 struct i40e_driver_version dv;
4808 struct i40e_hw *hw = &pf->hw;
4809 i40e_status ret;
4810 u32 v;
4811
41c445ff
JB		 4812 /* Now we wait for GRST to settle out.
4813 * We don't have to delete the VEBs or VSIs from the hw switch
4814 * because the reset will make them disappear.
4815 */
4816 ret = i40e_pf_reset(hw);
4817 if (ret)
4818 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
4819 pf->pfr_count++;
4820
4821 if (test_bit(__I40E_DOWN, &pf->state))
4822 goto end_core_reset;
4823 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
4824
4825 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
4826 ret = i40e_init_adminq(&pf->hw);
4827 if (ret) {
4828 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
4829 goto end_core_reset;
4830 }
4831
4832 ret = i40e_get_capabilities(pf);
4833 if (ret) {
4834 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
4835 ret);
4836 goto end_core_reset;
4837 }
4838
41c445ff
JB		 4839 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
4840 hw->func_caps.num_rx_qp,
4841 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
4842 if (ret) {
4843 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
4844 goto end_core_reset;
4845 }
4846 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
4847 if (ret) {
4848 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
4849 goto end_core_reset;
4850 }
4851
4852 /* do basic switch setup */
bc7d338f 4853 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 4854 if (ret)
4855 goto end_core_reset;
4856
4857 /* Rebuild the VSIs and VEBs that existed before reset.
4858 * They are still in our local switch element arrays, so only
4859 * need to rebuild the switch model in the HW.
4860 *
4861 * If there were VEBs but the reconstitution failed, we'll try
4862 * try to recover minimal use by getting the basic PF VSI working.
4863 */
4864 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
4865 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
4866 /* find the one VEB connected to the MAC, and find orphans */
4867 for (v = 0; v < I40E_MAX_VEB; v++) {
4868 if (!pf->veb[v])
4869 continue;
4870
4871 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
4872 pf->veb[v]->uplink_seid == 0) {
4873 ret = i40e_reconstitute_veb(pf->veb[v]);
4874
4875 if (!ret)
4876 continue;
4877
4878 /* If Main VEB failed, we're in deep doodoo,
4879 * so give up rebuilding the switch and set up
4880 * for minimal rebuild of PF VSI.
4881 * If orphan failed, we'll report the error
4882 * but try to keep going.
4883 */
4884 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
4885 dev_info(&pf->pdev->dev,
4886 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
4887 ret);
4888 pf->vsi[pf->lan_vsi]->uplink_seid
4889 = pf->mac_seid;
4890 break;
4891 } else if (pf->veb[v]->uplink_seid == 0) {
4892 dev_info(&pf->pdev->dev,
4893 "rebuild of orphan VEB failed: %d\n",
4894 ret);
4895 }
4896 }
4897 }
4898 }
4899
4900 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
4901 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
4902 /* no VEB, so rebuild only the Main VSI */
4903 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
4904 if (ret) {
4905 dev_info(&pf->pdev->dev,
4906 "rebuild of Main VSI failed: %d\n", ret);
4907 goto end_core_reset;
4908 }
4909 }
4910
4911 /* reinit the misc interrupt */
4912 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4913 ret = i40e_setup_misc_vector(pf);
4914
4915 /* restart the VSIs that were rebuilt and running before the reset */
4916 i40e_pf_unquiesce_all_vsi(pf);
4917
4918 /* tell the firmware that we're starting */
4919 dv.major_version = DRV_VERSION_MAJOR;
4920 dv.minor_version = DRV_VERSION_MINOR;
4921 dv.build_version = DRV_VERSION_BUILD;
4922 dv.subbuild_version = 0;
4923 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
4924
4925 dev_info(&pf->pdev->dev, "PF reset done\n");
4926
4927end_core_reset:
4928 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4929}
4930
f650a38b
ASJ		 4931/**
4932 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
4933 * @pf: board private structure
4934 *
4935 * Close up the VFs and other things in prep for a Core Reset,
4936 * then get ready to rebuild the world.
4937 **/
4938static void i40e_handle_reset_warning(struct i40e_pf *pf)
4939{
4940 i40e_status ret;
4941
4942 ret = i40e_prep_for_reset(pf);
4943 if (!ret)
bc7d338f 4944 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 4945}
4946
41c445ff
JB		 4947/**
4948 * i40e_handle_mdd_event
4949 * @pf: pointer to the pf structure
4950 *
4951 * Called from the MDD irq handler to identify possibly malicious vfs
4952 **/
4953static void i40e_handle_mdd_event(struct i40e_pf *pf)
4954{
4955 struct i40e_hw *hw = &pf->hw;
4956 bool mdd_detected = false;
4957 struct i40e_vf *vf;
4958 u32 reg;
4959 int i;
4960
4961 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
4962 return;
4963
4964 /* find what triggered the MDD event */
4965 reg = rd32(hw, I40E_GL_MDET_TX);
4966 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4967 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
4968 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
4969 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
4970 >> I40E_GL_MDET_TX_EVENT_SHIFT;
4971 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
4972 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
4973 dev_info(&pf->pdev->dev,
4974 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
4975 event, queue, func);
4976 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
4977 mdd_detected = true;
4978 }
4979 reg = rd32(hw, I40E_GL_MDET_RX);
4980 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4981 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
4982 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
4983 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
4984 >> I40E_GL_MDET_RX_EVENT_SHIFT;
4985 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
4986 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
4987 dev_info(&pf->pdev->dev,
4988 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
4989 event, queue, func);
4990 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
4991 mdd_detected = true;
4992 }
4993
4994 /* see if one of the VFs needs its hand slapped */
4995 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
4996 vf = &(pf->vf[i]);
4997 reg = rd32(hw, I40E_VP_MDET_TX(i));
4998 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
4999 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5000 vf->num_mdd_events++;
5001 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5002 }
5003
5004 reg = rd32(hw, I40E_VP_MDET_RX(i));
5005 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5006 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5007 vf->num_mdd_events++;
5008 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5009 }
5010
5011 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5012 dev_info(&pf->pdev->dev,
5013 "Too many MDD events on VF %d, disabled\n", i);
5014 dev_info(&pf->pdev->dev,
5015 "Use PF Control I/F to re-enable the VF\n");
5016 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5017 }
5018 }
5019
5020 /* re-enable mdd interrupt cause */
5021 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5022 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5023 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5024 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5025 i40e_flush(hw);
5026}
5027
a1c9a9d9
JK		 5028#ifdef CONFIG_I40E_VXLAN
5029/**
5030 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5031 * @pf: board private structure
5032 **/
5033static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5034{
5035 const int vxlan_hdr_qwords = 4;
5036 struct i40e_hw *hw = &pf->hw;
5037 i40e_status ret;
5038 u8 filter_index;
5039 __be16 port;
5040 int i;
5041
5042 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5043 return;
5044
5045 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5046
5047 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5048 if (pf->pending_vxlan_bitmap & (1 << i)) {
5049 pf->pending_vxlan_bitmap &= ~(1 << i);
5050 port = pf->vxlan_ports[i];
5051 ret = port ?
5052 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5053 vxlan_hdr_qwords,
5054 I40E_AQC_TUNNEL_TYPE_VXLAN,
5055 &filter_index, NULL)
5056 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5057
5058 if (ret) {
5059 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5060 port ? "adding" : "deleting",
5061 ntohs(port), port ? i : i);
5062
5063 pf->vxlan_ports[i] = 0;
5064 } else {
5065 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5066 port ? "Added" : "Deleted",
5067 ntohs(port), port ? i : filter_index);
5068 }
5069 }
5070 }
5071}
5072
5073#endif
41c445ff
JB		 5074/**
5075 * i40e_service_task - Run the driver's async subtasks
5076 * @work: pointer to work_struct containing our data
5077 **/
5078static void i40e_service_task(struct work_struct *work)
5079{
5080 struct i40e_pf *pf = container_of(work,
5081 struct i40e_pf,
5082 service_task);
5083 unsigned long start_time = jiffies;
5084
5085 i40e_reset_subtask(pf);
5086 i40e_handle_mdd_event(pf);
5087 i40e_vc_process_vflr_event(pf);
5088 i40e_watchdog_subtask(pf);
5089 i40e_fdir_reinit_subtask(pf);
5090 i40e_check_hang_subtask(pf);
5091 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5092#ifdef CONFIG_I40E_VXLAN
5093 i40e_sync_vxlan_filters_subtask(pf);
5094#endif
41c445ff
JB		 5095 i40e_clean_adminq_subtask(pf);
5096
5097 i40e_service_event_complete(pf);
5098
5099 /* If the tasks have taken longer than one timer cycle or there
5100 * is more work to be done, reschedule the service task now
5101 * rather than wait for the timer to tick again.
5102 */
5103 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5104 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5105 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5106 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5107 i40e_service_event_schedule(pf);
5108}
5109
5110/**
5111 * i40e_service_timer - timer callback
5112 * @data: pointer to PF struct
5113 **/
5114static void i40e_service_timer(unsigned long data)
5115{
5116 struct i40e_pf *pf = (struct i40e_pf *)data;
5117
5118 mod_timer(&pf->service_timer,
5119 round_jiffies(jiffies + pf->service_timer_period));
5120 i40e_service_event_schedule(pf);
5121}
5122
5123/**
5124 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5125 * @vsi: the VSI being configured
5126 **/
5127static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5128{
5129 struct i40e_pf *pf = vsi->back;
5130
5131 switch (vsi->type) {
5132 case I40E_VSI_MAIN:
5133 vsi->alloc_queue_pairs = pf->num_lan_qps;
5134 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5135 I40E_REQ_DESCRIPTOR_MULTIPLE);
5136 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5137 vsi->num_q_vectors = pf->num_lan_msix;
5138 else
5139 vsi->num_q_vectors = 1;
5140
5141 break;
5142
5143 case I40E_VSI_FDIR:
5144 vsi->alloc_queue_pairs = 1;
5145 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5146 I40E_REQ_DESCRIPTOR_MULTIPLE);
5147 vsi->num_q_vectors = 1;
5148 break;
5149
5150 case I40E_VSI_VMDQ2:
5151 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5152 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5153 I40E_REQ_DESCRIPTOR_MULTIPLE);
5154 vsi->num_q_vectors = pf->num_vmdq_msix;
5155 break;
5156
5157 case I40E_VSI_SRIOV:
5158 vsi->alloc_queue_pairs = pf->num_vf_qps;
5159 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5160 I40E_REQ_DESCRIPTOR_MULTIPLE);
5161 break;
5162
5163 default:
5164 WARN_ON(1);
5165 return -ENODATA;
5166 }
5167
5168 return 0;
5169}
5170
f650a38b
ASJ		 5171/**
5172 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5173 * @type: VSI pointer
bc7d338f 5174 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5175 *
5176 * On error: returns error code (negative)
5177 * On success: returns 0
5178 **/
bc7d338f 5179static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5180{
5181 int size;
5182 int ret = 0;
5183
ac6c5e3d 5184 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5185 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5186 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5187 if (!vsi->tx_rings)
5188 return -ENOMEM;
f650a38b
ASJ		 5189 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5190
bc7d338f
ASJ		 5191 if (alloc_qvectors) {
5192 /* allocate memory for q_vector pointers */
5193 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5194 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5195 if (!vsi->q_vectors) {
5196 ret = -ENOMEM;
5197 goto err_vectors;
5198 }
f650a38b
ASJ		 5199 }
5200 return ret;
5201
5202err_vectors:
5203 kfree(vsi->tx_rings);
5204 return ret;
5205}
5206
41c445ff
JB		 5207/**
5208 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5209 * @pf: board private structure
5210 * @type: type of VSI
5211 *
5212 * On error: returns error code (negative)
5213 * On success: returns vsi index in PF (positive)
5214 **/
5215static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5216{
5217 int ret = -ENODEV;
5218 struct i40e_vsi *vsi;
5219 int vsi_idx;
5220 int i;
5221
5222 /* Need to protect the allocation of the VSIs at the PF level */
5223 mutex_lock(&pf->switch_mutex);
5224
5225 /* VSI list may be fragmented if VSI creation/destruction has
5226 * been happening. We can afford to do a quick scan to look
5227 * for any free VSIs in the list.
5228 *
5229 * find next empty vsi slot, looping back around if necessary
5230 */
5231 i = pf->next_vsi;
5232 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5233 i++;
5234 if (i >= pf->hw.func_caps.num_vsis) {
5235 i = 0;
5236 while (i < pf->next_vsi && pf->vsi[i])
5237 i++;
5238 }
5239
5240 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5241 vsi_idx = i; /* Found one! */
5242 } else {
5243 ret = -ENODEV;
493fb300 5244 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5245 }
5246 pf->next_vsi = ++i;
5247
5248 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5249 if (!vsi) {
5250 ret = -ENOMEM;
493fb300 5251 goto unlock_pf;
41c445ff
JB		 5252 }
5253 vsi->type = type;
5254 vsi->back = pf;
5255 set_bit(__I40E_DOWN, &vsi->state);
5256 vsi->flags = 0;
5257 vsi->idx = vsi_idx;
5258 vsi->rx_itr_setting = pf->rx_itr_default;
5259 vsi->tx_itr_setting = pf->tx_itr_default;
5260 vsi->netdev_registered = false;
5261 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5262 INIT_LIST_HEAD(&vsi->mac_filter_list);
5263
9f65e15b
AD		 5264 ret = i40e_set_num_rings_in_vsi(vsi);
5265 if (ret)
5266 goto err_rings;
5267
bc7d338f 5268 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5269 if (ret)
9f65e15b 5270 goto err_rings;
493fb300 5271
41c445ff
JB		 5272 /* Setup default MSIX irq handler for VSI */
5273 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5274
5275 pf->vsi[vsi_idx] = vsi;
5276 ret = vsi_idx;
493fb300
AD		 5277 goto unlock_pf;
5278
9f65e15b 5279err_rings:
493fb300
AD		 5280 pf->next_vsi = i - 1;
5281 kfree(vsi);
5282unlock_pf:
41c445ff
JB		 5283 mutex_unlock(&pf->switch_mutex);
5284 return ret;
5285}
5286
f650a38b
ASJ		 5287/**
5288 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5289 * @type: VSI pointer
bc7d338f 5290 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5291 *
5292 * On error: returns error code (negative)
5293 * On success: returns 0
5294 **/
bc7d338f 5295static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5296{
5297 /* free the ring and vector containers */
bc7d338f
ASJ		 5298 if (free_qvectors) {
5299 kfree(vsi->q_vectors);
5300 vsi->q_vectors = NULL;
5301 }
f650a38b
ASJ		 5302 kfree(vsi->tx_rings);
5303 vsi->tx_rings = NULL;
5304 vsi->rx_rings = NULL;
5305}
5306
41c445ff
JB		 5307/**
5308 * i40e_vsi_clear - Deallocate the VSI provided
5309 * @vsi: the VSI being un-configured
5310 **/
5311static int i40e_vsi_clear(struct i40e_vsi *vsi)
5312{
5313 struct i40e_pf *pf;
5314
5315 if (!vsi)
5316 return 0;
5317
5318 if (!vsi->back)
5319 goto free_vsi;
5320 pf = vsi->back;
5321
5322 mutex_lock(&pf->switch_mutex);
5323 if (!pf->vsi[vsi->idx]) {
5324 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5325 vsi->idx, vsi->idx, vsi, vsi->type);
5326 goto unlock_vsi;
5327 }
5328
5329 if (pf->vsi[vsi->idx] != vsi) {
5330 dev_err(&pf->pdev->dev,
5331 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5332 pf->vsi[vsi->idx]->idx,
5333 pf->vsi[vsi->idx],
5334 pf->vsi[vsi->idx]->type,
5335 vsi->idx, vsi, vsi->type);
5336 goto unlock_vsi;
5337 }
5338
5339 /* updates the pf for this cleared vsi */
5340 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5341 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5342
bc7d338f 5343 i40e_vsi_free_arrays(vsi, true);
493fb300 5344
41c445ff
JB		 5345 pf->vsi[vsi->idx] = NULL;
5346 if (vsi->idx < pf->next_vsi)
5347 pf->next_vsi = vsi->idx;
5348
5349unlock_vsi:
5350 mutex_unlock(&pf->switch_mutex);
5351free_vsi:
5352 kfree(vsi);
5353
5354 return 0;
5355}
5356
9f65e15b
AD		 5357/**
5358 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5359 * @vsi: the VSI being cleaned
5360 **/
be1d5eea 5361static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5362{
5363 int i;
5364
be1d5eea 5365 if (vsi->tx_rings[0]) {
d7397644 5366 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5367 kfree_rcu(vsi->tx_rings[i], rcu);
5368 vsi->tx_rings[i] = NULL;
5369 vsi->rx_rings[i] = NULL;
5370 }
be1d5eea 5371 }
9f65e15b
AD		 5372}
5373
41c445ff
JB		 5374/**
5375 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5376 * @vsi: the VSI being configured
5377 **/
5378static int i40e_alloc_rings(struct i40e_vsi *vsi)
5379{
5380 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5381 int i;
5382
41c445ff 5383 /* Set basic values in the rings to be used later during open() */
d7397644 5384 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5385 struct i40e_ring *tx_ring;
5386 struct i40e_ring *rx_ring;
5387
ac6c5e3d 5388 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5389 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5390 if (!tx_ring)
5391 goto err_out;
41c445ff
JB		 5392
5393 tx_ring->queue_index = i;
5394 tx_ring->reg_idx = vsi->base_queue + i;
5395 tx_ring->ring_active = false;
5396 tx_ring->vsi = vsi;
5397 tx_ring->netdev = vsi->netdev;
5398 tx_ring->dev = &pf->pdev->dev;
5399 tx_ring->count = vsi->num_desc;
5400 tx_ring->size = 0;
5401 tx_ring->dcb_tc = 0;
9f65e15b 5402 vsi->tx_rings[i] = tx_ring;
41c445ff 5403
9f65e15b 5404 rx_ring = &tx_ring[1];
41c445ff
JB		 5405 rx_ring->queue_index = i;
5406 rx_ring->reg_idx = vsi->base_queue + i;
5407 rx_ring->ring_active = false;
5408 rx_ring->vsi = vsi;
5409 rx_ring->netdev = vsi->netdev;
5410 rx_ring->dev = &pf->pdev->dev;
5411 rx_ring->count = vsi->num_desc;
5412 rx_ring->size = 0;
5413 rx_ring->dcb_tc = 0;
5414 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5415 set_ring_16byte_desc_enabled(rx_ring);
5416 else
5417 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5418 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5419 }
5420
5421 return 0;
9f65e15b
AD		 5422
5423err_out:
5424 i40e_vsi_clear_rings(vsi);
5425 return -ENOMEM;
41c445ff
JB		 5426}
5427
5428/**
5429 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5430 * @pf: board private structure
5431 * @vectors: the number of MSI-X vectors to request
5432 *
5433 * Returns the number of vectors reserved, or error
5434 **/
5435static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5436{
5437 int err = 0;
5438
5439 pf->num_msix_entries = 0;
5440 while (vectors >= I40E_MIN_MSIX) {
5441 err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
5442 if (err == 0) {
5443 /* good to go */
5444 pf->num_msix_entries = vectors;
5445 break;
5446 } else if (err < 0) {
5447 /* total failure */
5448 dev_info(&pf->pdev->dev,
5449 "MSI-X vector reservation failed: %d\n", err);
5450 vectors = 0;
5451 break;
5452 } else {
5453 /* err > 0 is the hint for retry */
5454 dev_info(&pf->pdev->dev,
5455 "MSI-X vectors wanted %d, retrying with %d\n",
5456 vectors, err);
5457 vectors = err;
5458 }
5459 }
5460
5461 if (vectors > 0 && vectors < I40E_MIN_MSIX) {
5462 dev_info(&pf->pdev->dev,
5463 "Couldn't get enough vectors, only %d available\n",
5464 vectors);
5465 vectors = 0;
5466 }
5467
5468 return vectors;
5469}
5470
5471/**
5472 * i40e_init_msix - Setup the MSIX capability
5473 * @pf: board private structure
5474 *
5475 * Work with the OS to set up the MSIX vectors needed.
5476 *
5477 * Returns 0 on success, negative on failure
5478 **/
5479static int i40e_init_msix(struct i40e_pf *pf)
5480{
5481 i40e_status err = 0;
5482 struct i40e_hw *hw = &pf->hw;
5483 int v_budget, i;
5484 int vec;
5485
5486 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5487 return -ENODEV;
5488
5489 /* The number of vectors we'll request will be comprised of:
5490 * - Add 1 for "other" cause for Admin Queue events, etc.
5491 * - The number of LAN queue pairs
f8ff1464
ASJ		 5492 * - Queues being used for RSS.
5493 * We don't need as many as max_rss_size vectors.
5494 * use rss_size instead in the calculation since that
5495 * is governed by number of cpus in the system.
5496 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5497 * - The number of VMDq pairs
5498 * Once we count this up, try the request.
5499 *
5500 * If we can't get what we want, we'll simplify to nearly nothing
5501 * and try again. If that still fails, we punt.
5502 */
f8ff1464 5503 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5504 pf->num_vmdq_msix = pf->num_vmdq_qps;
5505 v_budget = 1 + pf->num_lan_msix;
5506 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
5507 if (pf->flags & I40E_FLAG_FDIR_ENABLED)
5508 v_budget++;
5509
5510 /* Scale down if necessary, and the rings will share vectors */
5511 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5512
5513 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5514 GFP_KERNEL);
5515 if (!pf->msix_entries)
5516 return -ENOMEM;
5517
5518 for (i = 0; i < v_budget; i++)
5519 pf->msix_entries[i].entry = i;
5520 vec = i40e_reserve_msix_vectors(pf, v_budget);
5521 if (vec < I40E_MIN_MSIX) {
5522 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5523 kfree(pf->msix_entries);
5524 pf->msix_entries = NULL;
5525 return -ENODEV;
5526
5527 } else if (vec == I40E_MIN_MSIX) {
5528 /* Adjust for minimal MSIX use */
5529 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5530 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5531 pf->num_vmdq_vsis = 0;
5532 pf->num_vmdq_qps = 0;
5533 pf->num_vmdq_msix = 0;
5534 pf->num_lan_qps = 1;
5535 pf->num_lan_msix = 1;
5536
5537 } else if (vec != v_budget) {
5538 /* Scale vector usage down */
5539 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5540 vec--; /* reserve the misc vector */
5541
5542 /* partition out the remaining vectors */
5543 switch (vec) {
5544 case 2:
5545 pf->num_vmdq_vsis = 1;
5546 pf->num_lan_msix = 1;
5547 break;
5548 case 3:
5549 pf->num_vmdq_vsis = 1;
5550 pf->num_lan_msix = 2;
5551 break;
5552 default:
5553 pf->num_lan_msix = min_t(int, (vec / 2),
5554 pf->num_lan_qps);
5555 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5556 I40E_DEFAULT_NUM_VMDQ_VSI);
5557 break;
5558 }
5559 }
5560
5561 return err;
5562}
5563
493fb300
AD		 5564/**
5565 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5566 * @vsi: the VSI being configured
5567 * @v_idx: index of the vector in the vsi struct
5568 *
5569 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5570 **/
5571static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5572{
5573 struct i40e_q_vector *q_vector;
5574
5575 /* allocate q_vector */
5576 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5577 if (!q_vector)
5578 return -ENOMEM;
5579
5580 q_vector->vsi = vsi;
5581 q_vector->v_idx = v_idx;
5582 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5583 if (vsi->netdev)
5584 netif_napi_add(vsi->netdev, &q_vector->napi,
5585 i40e_napi_poll, vsi->work_limit);
5586
cd0b6fa6
AD		 5587 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5588 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5589
493fb300
AD		 5590 /* tie q_vector and vsi together */
5591 vsi->q_vectors[v_idx] = q_vector;
5592
5593 return 0;
5594}
5595
41c445ff
JB		 5596/**
5597 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5598 * @vsi: the VSI being configured
5599 *
5600 * We allocate one q_vector per queue interrupt. If allocation fails we
5601 * return -ENOMEM.
5602 **/
5603static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
5604{
5605 struct i40e_pf *pf = vsi->back;
5606 int v_idx, num_q_vectors;
493fb300 5607 int err;
41c445ff
JB		 5608
5609 /* if not MSIX, give the one vector only to the LAN VSI */
5610 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5611 num_q_vectors = vsi->num_q_vectors;
5612 else if (vsi == pf->vsi[pf->lan_vsi])
5613 num_q_vectors = 1;
5614 else
5615 return -EINVAL;
5616
41c445ff 5617 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 5618 err = i40e_alloc_q_vector(vsi, v_idx);
5619 if (err)
5620 goto err_out;
41c445ff
JB		 5621 }
5622
5623 return 0;
493fb300
AD		 5624
5625err_out:
5626 while (v_idx--)
5627 i40e_free_q_vector(vsi, v_idx);
5628
5629 return err;
41c445ff
JB		 5630}
5631
5632/**
5633 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
5634 * @pf: board private structure to initialize
5635 **/
5636static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
5637{
5638 int err = 0;
5639
5640 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
5641 err = i40e_init_msix(pf);
5642 if (err) {
958a3e3b
SN		 5643 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
5644 I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 5645 I40E_FLAG_DCB_ENABLED |
5646 I40E_FLAG_SRIOV_ENABLED |
5647 I40E_FLAG_FDIR_ENABLED |
5648 I40E_FLAG_FDIR_ATR_ENABLED |
5649 I40E_FLAG_VMDQ_ENABLED);
5650
5651 /* rework the queue expectations without MSIX */
5652 i40e_determine_queue_usage(pf);
5653 }
5654 }
5655
5656 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
5657 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 5658 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 5659 err = pci_enable_msi(pf->pdev);
5660 if (err) {
958a3e3b 5661 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 5662 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
5663 }
5664 }
5665
958a3e3b
SN		 5666 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
5667 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
5668
41c445ff
JB		 5669 /* track first vector for misc interrupts */
5670 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
5671}
5672
5673/**
5674 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
5675 * @pf: board private structure
5676 *
5677 * This sets up the handler for MSIX 0, which is used to manage the
5678 * non-queue interrupts, e.g. AdminQ and errors. This is not used
5679 * when in MSI or Legacy interrupt mode.
5680 **/
5681static int i40e_setup_misc_vector(struct i40e_pf *pf)
5682{
5683 struct i40e_hw *hw = &pf->hw;
5684 int err = 0;
5685
5686 /* Only request the irq if this is the first time through, and
5687 * not when we're rebuilding after a Reset
5688 */
5689 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5690 err = request_irq(pf->msix_entries[0].vector,
5691 i40e_intr, 0, pf->misc_int_name, pf);
5692 if (err) {
5693 dev_info(&pf->pdev->dev,
5694 "request_irq for msix_misc failed: %d\n", err);
5695 return -EFAULT;
5696 }
5697 }
5698
5699 i40e_enable_misc_int_causes(hw);
5700
5701 /* associate no queues to the misc vector */
5702 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
5703 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
5704
5705 i40e_flush(hw);
5706
5707 i40e_irq_dynamic_enable_icr0(pf);
5708
5709 return err;
5710}
5711
5712/**
5713 * i40e_config_rss - Prepare for RSS if used
5714 * @pf: board private structure
5715 **/
5716static int i40e_config_rss(struct i40e_pf *pf)
5717{
41c445ff
JB		 5718 /* Set of random keys generated using kernel random number generator */
5719 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
5720 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
5721 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
5722 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 5723 struct i40e_hw *hw = &pf->hw;
5724 u32 lut = 0;
5725 int i, j;
5726 u64 hena;
41c445ff
JB		 5727
5728 /* Fill out hash function seed */
5729 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5730 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
5731
5732 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
5733 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
5734 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 5735 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 5736 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
5737 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
5738
5739 /* Populate the LUT with max no. of queues in round robin fashion */
5740 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
5741
5742 /* The assumption is that lan qp count will be the highest
5743 * qp count for any PF VSI that needs RSS.
5744 * If multiple VSIs need RSS support, all the qp counts
5745 * for those VSIs should be a power of 2 for RSS to work.
5746 * If LAN VSI is the only consumer for RSS then this requirement
5747 * is not necessary.
5748 */
5749 if (j == pf->rss_size)
5750 j = 0;
5751 /* lut = 4-byte sliding window of 4 lut entries */
5752 lut = (lut << 8) | (j &
5753 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
5754 /* On i = 3, we have 4 entries in lut; write to the register */
5755 if ((i & 3) == 3)
5756 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
5757 }
5758 i40e_flush(hw);
5759
5760 return 0;
5761}
5762
f8ff1464
ASJ		 5763/**
5764 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
5765 * @pf: board private structure
5766 * @queue_count: the requested queue count for rss.
5767 *
5768 * returns 0 if rss is not enabled, if enabled returns the final rss queue
5769 * count which may be different from the requested queue count.
5770 **/
5771int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
5772{
5773 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
5774 return 0;
5775
5776 queue_count = min_t(int, queue_count, pf->rss_size_max);
5777 queue_count = rounddown_pow_of_two(queue_count);
5778
5779 if (queue_count != pf->rss_size) {
5780 if (pf->queues_left < (queue_count - pf->rss_size)) {
5781 dev_info(&pf->pdev->dev,
5782 "Not enough queues to do RSS on %d queues: remaining queues %d\n",
5783 queue_count, pf->queues_left);
5784 return pf->rss_size;
5785 }
5786 i40e_prep_for_reset(pf);
5787
5788 pf->num_lan_qps += (queue_count - pf->rss_size);
5789 pf->queues_left -= (queue_count - pf->rss_size);
5790 pf->rss_size = queue_count;
5791
5792 i40e_reset_and_rebuild(pf, true);
5793 i40e_config_rss(pf);
5794 }
5795 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
5796 return pf->rss_size;
5797}
5798
41c445ff
JB		 5799/**
5800 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
5801 * @pf: board private structure to initialize
5802 *
5803 * i40e_sw_init initializes the Adapter private data structure.
5804 * Fields are initialized based on PCI device information and
5805 * OS network device settings (MTU size).
5806 **/
5807static int i40e_sw_init(struct i40e_pf *pf)
5808{
5809 int err = 0;
5810 int size;
5811
5812 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
5813 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 5814 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 5815 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
5816 if (I40E_DEBUG_USER & debug)
5817 pf->hw.debug_mask = debug;
5818 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
5819 I40E_DEFAULT_MSG_ENABLE);
5820 }
5821
5822 /* Set default capability flags */
5823 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
5824 I40E_FLAG_MSI_ENABLED |
5825 I40E_FLAG_MSIX_ENABLED |
5826 I40E_FLAG_RX_PS_ENABLED |
41c445ff
JB		 5827 I40E_FLAG_RX_1BUF_ENABLED;
5828
7134f9ce
JB		 5829 /* Depending on PF configurations, it is possible that the RSS
5830 * maximum might end up larger than the available queues
5831 */
41c445ff 5832 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 5833 pf->rss_size_max = min_t(int, pf->rss_size_max,
5834 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 5835 if (pf->hw.func_caps.rss) {
5836 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 5837 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 5838 } else {
5839 pf->rss_size = 1;
5840 }
5841
5842 if (pf->hw.func_caps.dcb)
5843 pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
5844 else
5845 pf->num_tc_qps = 0;
5846
5847 if (pf->hw.func_caps.fd) {
5848 /* FW/NVM is not yet fixed in this regard */
5849 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
5850 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
5851 pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
5852 dev_info(&pf->pdev->dev,
5853 "Flow Director ATR mode Enabled\n");
5854 pf->flags |= I40E_FLAG_FDIR_ENABLED;
5855 dev_info(&pf->pdev->dev,
5856 "Flow Director Side Band mode Enabled\n");
5857 pf->fdir_pf_filter_count =
5858 pf->hw.func_caps.fd_filters_guaranteed;
5859 }
5860 } else {
5861 pf->fdir_pf_filter_count = 0;
5862 }
5863
5864 if (pf->hw.func_caps.vmdq) {
5865 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
5866 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
5867 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
5868 }
5869
5870 /* MFP mode enabled */
5871 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
5872 pf->flags |= I40E_FLAG_MFP_ENABLED;
5873 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
5874 }
5875
5876#ifdef CONFIG_PCI_IOV
5877 if (pf->hw.func_caps.num_vfs) {
5878 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
5879 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
5880 pf->num_req_vfs = min_t(int,
5881 pf->hw.func_caps.num_vfs,
5882 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 5883 dev_info(&pf->pdev->dev,
5884 "Number of VFs being requested for PF[%d] = %d\n",
5885 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 5886 }
5887#endif /* CONFIG_PCI_IOV */
5888 pf->eeprom_version = 0xDEAD;
5889 pf->lan_veb = I40E_NO_VEB;
5890 pf->lan_vsi = I40E_NO_VSI;
5891
5892 /* set up queue assignment tracking */
5893 size = sizeof(struct i40e_lump_tracking)
5894 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
5895 pf->qp_pile = kzalloc(size, GFP_KERNEL);
5896 if (!pf->qp_pile) {
5897 err = -ENOMEM;
5898 goto sw_init_done;
5899 }
5900 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
5901 pf->qp_pile->search_hint = 0;
5902
5903 /* set up vector assignment tracking */
5904 size = sizeof(struct i40e_lump_tracking)
5905 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
5906 pf->irq_pile = kzalloc(size, GFP_KERNEL);
5907 if (!pf->irq_pile) {
5908 kfree(pf->qp_pile);
5909 err = -ENOMEM;
5910 goto sw_init_done;
5911 }
5912 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
5913 pf->irq_pile->search_hint = 0;
5914
5915 mutex_init(&pf->switch_mutex);
5916
5917sw_init_done:
5918 return err;
5919}
5920
5921/**
5922 * i40e_set_features - set the netdev feature flags
5923 * @netdev: ptr to the netdev being adjusted
5924 * @features: the feature set that the stack is suggesting
5925 **/
5926static int i40e_set_features(struct net_device *netdev,
5927 netdev_features_t features)
5928{
5929 struct i40e_netdev_priv *np = netdev_priv(netdev);
5930 struct i40e_vsi *vsi = np->vsi;
5931
5932 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5933 i40e_vlan_stripping_enable(vsi);
5934 else
5935 i40e_vlan_stripping_disable(vsi);
5936
5937 return 0;
5938}
5939
a1c9a9d9
JK		 5940#ifdef CONFIG_I40E_VXLAN
5941/**
5942 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
5943 * @pf: board private structure
5944 * @port: The UDP port to look up
5945 *
5946 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
5947 **/
5948static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
5949{
5950 u8 i;
5951
5952 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5953 if (pf->vxlan_ports[i] == port)
5954 return i;
5955 }
5956
5957 return i;
5958}
5959
5960/**
5961 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
5962 * @netdev: This physical port's netdev
5963 * @sa_family: Socket Family that VXLAN is notifying us about
5964 * @port: New UDP port number that VXLAN started listening to
5965 **/
5966static void i40e_add_vxlan_port(struct net_device *netdev,
5967 sa_family_t sa_family, __be16 port)
5968{
5969 struct i40e_netdev_priv *np = netdev_priv(netdev);
5970 struct i40e_vsi *vsi = np->vsi;
5971 struct i40e_pf *pf = vsi->back;
5972 u8 next_idx;
5973 u8 idx;
5974
5975 if (sa_family == AF_INET6)
5976 return;
5977
5978 idx = i40e_get_vxlan_port_idx(pf, port);
5979
5980 /* Check if port already exists */
5981 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5982 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
5983 return;
5984 }
5985
5986 /* Now check if there is space to add the new port */
5987 next_idx = i40e_get_vxlan_port_idx(pf, 0);
5988
5989 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5990 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
5991 ntohs(port));
5992 return;
5993 }
5994
5995 /* New port: add it and mark its index in the bitmap */
5996 pf->vxlan_ports[next_idx] = port;
5997 pf->pending_vxlan_bitmap |= (1 << next_idx);
5998
5999 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6000}
6001
6002/**
6003 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6004 * @netdev: This physical port's netdev
6005 * @sa_family: Socket Family that VXLAN is notifying us about
6006 * @port: UDP port number that VXLAN stopped listening to
6007 **/
6008static void i40e_del_vxlan_port(struct net_device *netdev,
6009 sa_family_t sa_family, __be16 port)
6010{
6011 struct i40e_netdev_priv *np = netdev_priv(netdev);
6012 struct i40e_vsi *vsi = np->vsi;
6013 struct i40e_pf *pf = vsi->back;
6014 u8 idx;
6015
6016 if (sa_family == AF_INET6)
6017 return;
6018
6019 idx = i40e_get_vxlan_port_idx(pf, port);
6020
6021 /* Check if port already exists */
6022 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6023 /* if port exists, set it to 0 (mark for deletion)
6024 * and make it pending
6025 */
6026 pf->vxlan_ports[idx] = 0;
6027
6028 pf->pending_vxlan_bitmap |= (1 << idx);
6029
6030 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6031 } else {
6032 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6033 ntohs(port));
6034 }
6035}
6036
6037#endif
41c445ff
JB		 6038static const struct net_device_ops i40e_netdev_ops = {
6039 .ndo_open = i40e_open,
6040 .ndo_stop = i40e_close,
6041 .ndo_start_xmit = i40e_lan_xmit_frame,
6042 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6043 .ndo_set_rx_mode = i40e_set_rx_mode,
6044 .ndo_validate_addr = eth_validate_addr,
6045 .ndo_set_mac_address = i40e_set_mac,
6046 .ndo_change_mtu = i40e_change_mtu,
6047 .ndo_tx_timeout = i40e_tx_timeout,
6048 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6049 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6050#ifdef CONFIG_NET_POLL_CONTROLLER
6051 .ndo_poll_controller = i40e_netpoll,
6052#endif
6053 .ndo_setup_tc = i40e_setup_tc,
6054 .ndo_set_features = i40e_set_features,
6055 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6056 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6057 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6058 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6059#ifdef CONFIG_I40E_VXLAN
6060 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6061 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6062#endif
41c445ff
JB		 6063};
6064
6065/**
6066 * i40e_config_netdev - Setup the netdev flags
6067 * @vsi: the VSI being configured
6068 *
6069 * Returns 0 on success, negative value on failure
6070 **/
6071static int i40e_config_netdev(struct i40e_vsi *vsi)
6072{
6073 struct i40e_pf *pf = vsi->back;
6074 struct i40e_hw *hw = &pf->hw;
6075 struct i40e_netdev_priv *np;
6076 struct net_device *netdev;
6077 u8 mac_addr[ETH_ALEN];
6078 int etherdev_size;
6079
6080 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6081 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6082 if (!netdev)
6083 return -ENOMEM;
6084
6085 vsi->netdev = netdev;
6086 np = netdev_priv(netdev);
6087 np->vsi = vsi;
6088
6089 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6090 NETIF_F_GSO_UDP_TUNNEL |
6091 NETIF_F_TSO |
6092 NETIF_F_SG;
6093
6094 netdev->features = NETIF_F_SG |
6095 NETIF_F_IP_CSUM |
6096 NETIF_F_SCTP_CSUM |
6097 NETIF_F_HIGHDMA |
6098 NETIF_F_GSO_UDP_TUNNEL |
6099 NETIF_F_HW_VLAN_CTAG_TX |
6100 NETIF_F_HW_VLAN_CTAG_RX |
6101 NETIF_F_HW_VLAN_CTAG_FILTER |
6102 NETIF_F_IPV6_CSUM |
6103 NETIF_F_TSO |
6104 NETIF_F_TSO6 |
6105 NETIF_F_RXCSUM |
6106 NETIF_F_RXHASH |
6107 0;
6108
6109 /* copy netdev features into list of user selectable features */
6110 netdev->hw_features |= netdev->features;
6111
6112 if (vsi->type == I40E_VSI_MAIN) {
6113 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6114 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6115 } else {
6116 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6117 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6118 pf->vsi[pf->lan_vsi]->netdev->name);
6119 random_ether_addr(mac_addr);
6120 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6121 }
6122
6123 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6124 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6125 /* vlan gets same features (except vlan offload)
6126 * after any tweaks for specific VSI types
6127 */
6128 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6129 NETIF_F_HW_VLAN_CTAG_RX |
6130 NETIF_F_HW_VLAN_CTAG_FILTER);
6131 netdev->priv_flags |= IFF_UNICAST_FLT;
6132 netdev->priv_flags |= IFF_SUPP_NOFCS;
6133 /* Setup netdev TC information */
6134 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6135
6136 netdev->netdev_ops = &i40e_netdev_ops;
6137 netdev->watchdog_timeo = 5 * HZ;
6138 i40e_set_ethtool_ops(netdev);
6139
6140 return 0;
6141}
6142
6143/**
6144 * i40e_vsi_delete - Delete a VSI from the switch
6145 * @vsi: the VSI being removed
6146 *
6147 * Returns 0 on success, negative value on failure
6148 **/
6149static void i40e_vsi_delete(struct i40e_vsi *vsi)
6150{
6151 /* remove default VSI is not allowed */
6152 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6153 return;
6154
6155 /* there is no HW VSI for FDIR */
6156 if (vsi->type == I40E_VSI_FDIR)
6157 return;
6158
6159 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6160 return;
6161}
6162
6163/**
6164 * i40e_add_vsi - Add a VSI to the switch
6165 * @vsi: the VSI being configured
6166 *
6167 * This initializes a VSI context depending on the VSI type to be added and
6168 * passes it down to the add_vsi aq command.
6169 **/
6170static int i40e_add_vsi(struct i40e_vsi *vsi)
6171{
6172 int ret = -ENODEV;
6173 struct i40e_mac_filter *f, *ftmp;
6174 struct i40e_pf *pf = vsi->back;
6175 struct i40e_hw *hw = &pf->hw;
6176 struct i40e_vsi_context ctxt;
6177 u8 enabled_tc = 0x1; /* TC0 enabled */
6178 int f_count = 0;
6179
6180 memset(&ctxt, 0, sizeof(ctxt));
6181 switch (vsi->type) {
6182 case I40E_VSI_MAIN:
6183 /* The PF's main VSI is already setup as part of the
6184 * device initialization, so we'll not bother with
6185 * the add_vsi call, but we will retrieve the current
6186 * VSI context.
6187 */
6188 ctxt.seid = pf->main_vsi_seid;
6189 ctxt.pf_num = pf->hw.pf_id;
6190 ctxt.vf_num = 0;
6191 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6192 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6193 if (ret) {
6194 dev_info(&pf->pdev->dev,
6195 "couldn't get pf vsi config, err %d, aq_err %d\n",
6196 ret, pf->hw.aq.asq_last_status);
6197 return -ENOENT;
6198 }
6199 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6200 vsi->info.valid_sections = 0;
6201
6202 vsi->seid = ctxt.seid;
6203 vsi->id = ctxt.vsi_number;
6204
6205 enabled_tc = i40e_pf_get_tc_map(pf);
6206
6207 /* MFP mode setup queue map and update VSI */
6208 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6209 memset(&ctxt, 0, sizeof(ctxt));
6210 ctxt.seid = pf->main_vsi_seid;
6211 ctxt.pf_num = pf->hw.pf_id;
6212 ctxt.vf_num = 0;
6213 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6214 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6215 if (ret) {
6216 dev_info(&pf->pdev->dev,
6217 "update vsi failed, aq_err=%d\n",
6218 pf->hw.aq.asq_last_status);
6219 ret = -ENOENT;
6220 goto err;
6221 }
6222 /* update the local VSI info queue map */
6223 i40e_vsi_update_queue_map(vsi, &ctxt);
6224 vsi->info.valid_sections = 0;
6225 } else {
6226 /* Default/Main VSI is only enabled for TC0
6227 * reconfigure it to enable all TCs that are
6228 * available on the port in SFP mode.
6229 */
6230 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6231 if (ret) {
6232 dev_info(&pf->pdev->dev,
6233 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6234 enabled_tc, ret,
6235 pf->hw.aq.asq_last_status);
6236 ret = -ENOENT;
6237 }
6238 }
6239 break;
6240
6241 case I40E_VSI_FDIR:
6242 /* no queue mapping or actual HW VSI needed */
6243 vsi->info.valid_sections = 0;
6244 vsi->seid = 0;
6245 vsi->id = 0;
6246 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6247 return 0;
6248 break;
6249
6250 case I40E_VSI_VMDQ2:
6251 ctxt.pf_num = hw->pf_id;
6252 ctxt.vf_num = 0;
6253 ctxt.uplink_seid = vsi->uplink_seid;
6254 ctxt.connection_type = 0x1; /* regular data port */
6255 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6256
6257 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6258
6259 /* This VSI is connected to VEB so the switch_id
6260 * should be set to zero by default.
6261 */
6262 ctxt.info.switch_id = 0;
6263 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6264 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6265
6266 /* Setup the VSI tx/rx queue map for TC0 only for now */
6267 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6268 break;
6269
6270 case I40E_VSI_SRIOV:
6271 ctxt.pf_num = hw->pf_id;
6272 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6273 ctxt.uplink_seid = vsi->uplink_seid;
6274 ctxt.connection_type = 0x1; /* regular data port */
6275 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6276
6277 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6278
6279 /* This VSI is connected to VEB so the switch_id
6280 * should be set to zero by default.
6281 */
6282 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6283
6284 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6285 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6286 /* Setup the VSI tx/rx queue map for TC0 only for now */
6287 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6288 break;
6289
6290 default:
6291 return -ENODEV;
6292 }
6293
6294 if (vsi->type != I40E_VSI_MAIN) {
6295 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6296 if (ret) {
6297 dev_info(&vsi->back->pdev->dev,
6298 "add vsi failed, aq_err=%d\n",
6299 vsi->back->hw.aq.asq_last_status);
6300 ret = -ENOENT;
6301 goto err;
6302 }
6303 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6304 vsi->info.valid_sections = 0;
6305 vsi->seid = ctxt.seid;
6306 vsi->id = ctxt.vsi_number;
6307 }
6308
6309 /* If macvlan filters already exist, force them to get loaded */
6310 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6311 f->changed = true;
6312 f_count++;
6313 }
6314 if (f_count) {
6315 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6316 pf->flags |= I40E_FLAG_FILTER_SYNC;
6317 }
6318
6319 /* Update VSI BW information */
6320 ret = i40e_vsi_get_bw_info(vsi);
6321 if (ret) {
6322 dev_info(&pf->pdev->dev,
6323 "couldn't get vsi bw info, err %d, aq_err %d\n",
6324 ret, pf->hw.aq.asq_last_status);
6325 /* VSI is already added so not tearing that up */
6326 ret = 0;
6327 }
6328
6329err:
6330 return ret;
6331}
6332
6333/**
6334 * i40e_vsi_release - Delete a VSI and free its resources
6335 * @vsi: the VSI being removed
6336 *
6337 * Returns 0 on success or < 0 on error
6338 **/
6339int i40e_vsi_release(struct i40e_vsi *vsi)
6340{
6341 struct i40e_mac_filter *f, *ftmp;
6342 struct i40e_veb *veb = NULL;
6343 struct i40e_pf *pf;
6344 u16 uplink_seid;
6345 int i, n;
6346
6347 pf = vsi->back;
6348
6349 /* release of a VEB-owner or last VSI is not allowed */
6350 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6351 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6352 vsi->seid, vsi->uplink_seid);
6353 return -ENODEV;
6354 }
6355 if (vsi == pf->vsi[pf->lan_vsi] &&
6356 !test_bit(__I40E_DOWN, &pf->state)) {
6357 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6358 return -ENODEV;
6359 }
6360
6361 uplink_seid = vsi->uplink_seid;
6362 if (vsi->type != I40E_VSI_SRIOV) {
6363 if (vsi->netdev_registered) {
6364 vsi->netdev_registered = false;
6365 if (vsi->netdev) {
6366 /* results in a call to i40e_close() */
6367 unregister_netdev(vsi->netdev);
6368 free_netdev(vsi->netdev);
6369 vsi->netdev = NULL;
6370 }
6371 } else {
6372 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6373 i40e_down(vsi);
6374 i40e_vsi_free_irq(vsi);
6375 i40e_vsi_free_tx_resources(vsi);
6376 i40e_vsi_free_rx_resources(vsi);
6377 }
6378 i40e_vsi_disable_irq(vsi);
6379 }
6380
6381 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6382 i40e_del_filter(vsi, f->macaddr, f->vlan,
6383 f->is_vf, f->is_netdev);
6384 i40e_sync_vsi_filters(vsi);
6385
6386 i40e_vsi_delete(vsi);
6387 i40e_vsi_free_q_vectors(vsi);
6388 i40e_vsi_clear_rings(vsi);
6389 i40e_vsi_clear(vsi);
6390
6391 /* If this was the last thing on the VEB, except for the
6392 * controlling VSI, remove the VEB, which puts the controlling
6393 * VSI onto the next level down in the switch.
6394 *
6395 * Well, okay, there's one more exception here: don't remove
6396 * the orphan VEBs yet. We'll wait for an explicit remove request
6397 * from up the network stack.
6398 */
6399 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6400 if (pf->vsi[i] &&
6401 pf->vsi[i]->uplink_seid == uplink_seid &&
6402 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6403 n++; /* count the VSIs */
6404 }
6405 }
6406 for (i = 0; i < I40E_MAX_VEB; i++) {
6407 if (!pf->veb[i])
6408 continue;
6409 if (pf->veb[i]->uplink_seid == uplink_seid)
6410 n++; /* count the VEBs */
6411 if (pf->veb[i]->seid == uplink_seid)
6412 veb = pf->veb[i];
6413 }
6414 if (n == 0 && veb && veb->uplink_seid != 0)
6415 i40e_veb_release(veb);
6416
6417 return 0;
6418}
6419
6420/**
6421 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6422 * @vsi: ptr to the VSI
6423 *
6424 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6425 * corresponding SW VSI structure and initializes num_queue_pairs for the
6426 * newly allocated VSI.
6427 *
6428 * Returns 0 on success or negative on failure
6429 **/
6430static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6431{
6432 int ret = -ENOENT;
6433 struct i40e_pf *pf = vsi->back;
6434
493fb300 6435 if (vsi->q_vectors[0]) {
41c445ff
JB		 6436 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6437 vsi->seid);
6438 return -EEXIST;
6439 }
6440
6441 if (vsi->base_vector) {
6442 dev_info(&pf->pdev->dev,
6443 "VSI %d has non-zero base vector %d\n",
6444 vsi->seid, vsi->base_vector);
6445 return -EEXIST;
6446 }
6447
6448 ret = i40e_alloc_q_vectors(vsi);
6449 if (ret) {
6450 dev_info(&pf->pdev->dev,
6451 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6452 vsi->num_q_vectors, vsi->seid, ret);
6453 vsi->num_q_vectors = 0;
6454 goto vector_setup_out;
6455 }
6456
958a3e3b
SN		 6457 if (vsi->num_q_vectors)
6458 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6459 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6460 if (vsi->base_vector < 0) {
6461 dev_info(&pf->pdev->dev,
6462 "failed to get q tracking for VSI %d, err=%d\n",
6463 vsi->seid, vsi->base_vector);
6464 i40e_vsi_free_q_vectors(vsi);
6465 ret = -ENOENT;
6466 goto vector_setup_out;
6467 }
6468
6469vector_setup_out:
6470 return ret;
6471}
6472
bc7d338f
ASJ		 6473/**
6474 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6475 * @vsi: pointer to the vsi.
6476 *
6477 * This re-allocates a vsi's queue resources.
6478 *
6479 * Returns pointer to the successfully allocated and configured VSI sw struct
6480 * on success, otherwise returns NULL on failure.
6481 **/
6482static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6483{
6484 struct i40e_pf *pf = vsi->back;
6485 u8 enabled_tc;
6486 int ret;
6487
6488 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6489 i40e_vsi_clear_rings(vsi);
6490
6491 i40e_vsi_free_arrays(vsi, false);
6492 i40e_set_num_rings_in_vsi(vsi);
6493 ret = i40e_vsi_alloc_arrays(vsi, false);
6494 if (ret)
6495 goto err_vsi;
6496
6497 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6498 if (ret < 0) {
6499 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6500 vsi->seid, ret);
6501 goto err_vsi;
6502 }
6503 vsi->base_queue = ret;
6504
6505 /* Update the FW view of the VSI. Force a reset of TC and queue
6506 * layout configurations.
6507 */
6508 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6509 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6510 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6511 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6512
6513 /* assign it some queues */
6514 ret = i40e_alloc_rings(vsi);
6515 if (ret)
6516 goto err_rings;
6517
6518 /* map all of the rings to the q_vectors */
6519 i40e_vsi_map_rings_to_vectors(vsi);
6520 return vsi;
6521
6522err_rings:
6523 i40e_vsi_free_q_vectors(vsi);
6524 if (vsi->netdev_registered) {
6525 vsi->netdev_registered = false;
6526 unregister_netdev(vsi->netdev);
6527 free_netdev(vsi->netdev);
6528 vsi->netdev = NULL;
6529 }
6530 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6531err_vsi:
6532 i40e_vsi_clear(vsi);
6533 return NULL;
6534}
6535
41c445ff
JB		 6536/**
6537 * i40e_vsi_setup - Set up a VSI by a given type
6538 * @pf: board private structure
6539 * @type: VSI type
6540 * @uplink_seid: the switch element to link to
6541 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6542 *
6543 * This allocates the sw VSI structure and its queue resources, then add a VSI
6544 * to the identified VEB.
6545 *
6546 * Returns pointer to the successfully allocated and configure VSI sw struct on
6547 * success, otherwise returns NULL on failure.
6548 **/
6549struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6550 u16 uplink_seid, u32 param1)
6551{
6552 struct i40e_vsi *vsi = NULL;
6553 struct i40e_veb *veb = NULL;
6554 int ret, i;
6555 int v_idx;
6556
6557 /* The requested uplink_seid must be either
6558 * - the PF's port seid
6559 * no VEB is needed because this is the PF
6560 * or this is a Flow Director special case VSI
6561 * - seid of an existing VEB
6562 * - seid of a VSI that owns an existing VEB
6563 * - seid of a VSI that doesn't own a VEB
6564 * a new VEB is created and the VSI becomes the owner
6565 * - seid of the PF VSI, which is what creates the first VEB
6566 * this is a special case of the previous
6567 *
6568 * Find which uplink_seid we were given and create a new VEB if needed
6569 */
6570 for (i = 0; i < I40E_MAX_VEB; i++) {
6571 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6572 veb = pf->veb[i];
6573 break;
6574 }
6575 }
6576
6577 if (!veb && uplink_seid != pf->mac_seid) {
6578
6579 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6580 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6581 vsi = pf->vsi[i];
6582 break;
6583 }
6584 }
6585 if (!vsi) {
6586 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6587 uplink_seid);
6588 return NULL;
6589 }
6590
6591 if (vsi->uplink_seid == pf->mac_seid)
6592 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6593 vsi->tc_config.enabled_tc);
6594 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6595 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6596 vsi->tc_config.enabled_tc);
6597
6598 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6599 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6600 veb = pf->veb[i];
6601 }
6602 if (!veb) {
6603 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6604 return NULL;
6605 }
6606
6607 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6608 uplink_seid = veb->seid;
6609 }
6610
6611 /* get vsi sw struct */
6612 v_idx = i40e_vsi_mem_alloc(pf, type);
6613 if (v_idx < 0)
6614 goto err_alloc;
6615 vsi = pf->vsi[v_idx];
6616 vsi->type = type;
6617 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
6618
6619 if (type == I40E_VSI_MAIN)
6620 pf->lan_vsi = v_idx;
6621 else if (type == I40E_VSI_SRIOV)
6622 vsi->vf_id = param1;
6623 /* assign it some queues */
6624 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6625 if (ret < 0) {
6626 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6627 vsi->seid, ret);
6628 goto err_vsi;
6629 }
6630 vsi->base_queue = ret;
6631
6632 /* get a VSI from the hardware */
6633 vsi->uplink_seid = uplink_seid;
6634 ret = i40e_add_vsi(vsi);
6635 if (ret)
6636 goto err_vsi;
6637
6638 switch (vsi->type) {
6639 /* setup the netdev if needed */
6640 case I40E_VSI_MAIN:
6641 case I40E_VSI_VMDQ2:
6642 ret = i40e_config_netdev(vsi);
6643 if (ret)
6644 goto err_netdev;
6645 ret = register_netdev(vsi->netdev);
6646 if (ret)
6647 goto err_netdev;
6648 vsi->netdev_registered = true;
6649 netif_carrier_off(vsi->netdev);
6650 /* fall through */
6651
6652 case I40E_VSI_FDIR:
6653 /* set up vectors and rings if needed */
6654 ret = i40e_vsi_setup_vectors(vsi);
6655 if (ret)
6656 goto err_msix;
6657
6658 ret = i40e_alloc_rings(vsi);
6659 if (ret)
6660 goto err_rings;
6661
6662 /* map all of the rings to the q_vectors */
6663 i40e_vsi_map_rings_to_vectors(vsi);
6664
6665 i40e_vsi_reset_stats(vsi);
6666 break;
6667
6668 default:
6669 /* no netdev or rings for the other VSI types */
6670 break;
6671 }
6672
6673 return vsi;
6674
6675err_rings:
6676 i40e_vsi_free_q_vectors(vsi);
6677err_msix:
6678 if (vsi->netdev_registered) {
6679 vsi->netdev_registered = false;
6680 unregister_netdev(vsi->netdev);
6681 free_netdev(vsi->netdev);
6682 vsi->netdev = NULL;
6683 }
6684err_netdev:
6685 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6686err_vsi:
6687 i40e_vsi_clear(vsi);
6688err_alloc:
6689 return NULL;
6690}
6691
6692/**
6693 * i40e_veb_get_bw_info - Query VEB BW information
6694 * @veb: the veb to query
6695 *
6696 * Query the Tx scheduler BW configuration data for given VEB
6697 **/
6698static int i40e_veb_get_bw_info(struct i40e_veb *veb)
6699{
6700 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
6701 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
6702 struct i40e_pf *pf = veb->pf;
6703 struct i40e_hw *hw = &pf->hw;
6704 u32 tc_bw_max;
6705 int ret = 0;
6706 int i;
6707
6708 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
6709 &bw_data, NULL);
6710 if (ret) {
6711 dev_info(&pf->pdev->dev,
6712 "query veb bw config failed, aq_err=%d\n",
6713 hw->aq.asq_last_status);
6714 goto out;
6715 }
6716
6717 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
6718 &ets_data, NULL);
6719 if (ret) {
6720 dev_info(&pf->pdev->dev,
6721 "query veb bw ets config failed, aq_err=%d\n",
6722 hw->aq.asq_last_status);
6723 goto out;
6724 }
6725
6726 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
6727 veb->bw_max_quanta = ets_data.tc_bw_max;
6728 veb->is_abs_credits = bw_data.absolute_credits_enable;
6729 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
6730 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
6731 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6732 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
6733 veb->bw_tc_limit_credits[i] =
6734 le16_to_cpu(bw_data.tc_bw_limits[i]);
6735 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
6736 }
6737
6738out:
6739 return ret;
6740}
6741
6742/**
6743 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
6744 * @pf: board private structure
6745 *
6746 * On error: returns error code (negative)
6747 * On success: returns vsi index in PF (positive)
6748 **/
6749static int i40e_veb_mem_alloc(struct i40e_pf *pf)
6750{
6751 int ret = -ENOENT;
6752 struct i40e_veb *veb;
6753 int i;
6754
6755 /* Need to protect the allocation of switch elements at the PF level */
6756 mutex_lock(&pf->switch_mutex);
6757
6758 /* VEB list may be fragmented if VEB creation/destruction has
6759 * been happening. We can afford to do a quick scan to look
6760 * for any free slots in the list.
6761 *
6762 * find next empty veb slot, looping back around if necessary
6763 */
6764 i = 0;
6765 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
6766 i++;
6767 if (i >= I40E_MAX_VEB) {
6768 ret = -ENOMEM;
6769 goto err_alloc_veb; /* out of VEB slots! */
6770 }
6771
6772 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
6773 if (!veb) {
6774 ret = -ENOMEM;
6775 goto err_alloc_veb;
6776 }
6777 veb->pf = pf;
6778 veb->idx = i;
6779 veb->enabled_tc = 1;
6780
6781 pf->veb[i] = veb;
6782 ret = i;
6783err_alloc_veb:
6784 mutex_unlock(&pf->switch_mutex);
6785 return ret;
6786}
6787
6788/**
6789 * i40e_switch_branch_release - Delete a branch of the switch tree
6790 * @branch: where to start deleting
6791 *
6792 * This uses recursion to find the tips of the branch to be
6793 * removed, deleting until we get back to and can delete this VEB.
6794 **/
6795static void i40e_switch_branch_release(struct i40e_veb *branch)
6796{
6797 struct i40e_pf *pf = branch->pf;
6798 u16 branch_seid = branch->seid;
6799 u16 veb_idx = branch->idx;
6800 int i;
6801
6802 /* release any VEBs on this VEB - RECURSION */
6803 for (i = 0; i < I40E_MAX_VEB; i++) {
6804 if (!pf->veb[i])
6805 continue;
6806 if (pf->veb[i]->uplink_seid == branch->seid)
6807 i40e_switch_branch_release(pf->veb[i]);
6808 }
6809
6810 /* Release the VSIs on this VEB, but not the owner VSI.
6811 *
6812 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
6813 * the VEB itself, so don't use (*branch) after this loop.
6814 */
6815 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6816 if (!pf->vsi[i])
6817 continue;
6818 if (pf->vsi[i]->uplink_seid == branch_seid &&
6819 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6820 i40e_vsi_release(pf->vsi[i]);
6821 }
6822 }
6823
6824 /* There's one corner case where the VEB might not have been
6825 * removed, so double check it here and remove it if needed.
6826 * This case happens if the veb was created from the debugfs
6827 * commands and no VSIs were added to it.
6828 */
6829 if (pf->veb[veb_idx])
6830 i40e_veb_release(pf->veb[veb_idx]);
6831}
6832
6833/**
6834 * i40e_veb_clear - remove veb struct
6835 * @veb: the veb to remove
6836 **/
6837static void i40e_veb_clear(struct i40e_veb *veb)
6838{
6839 if (!veb)
6840 return;
6841
6842 if (veb->pf) {
6843 struct i40e_pf *pf = veb->pf;
6844
6845 mutex_lock(&pf->switch_mutex);
6846 if (pf->veb[veb->idx] == veb)
6847 pf->veb[veb->idx] = NULL;
6848 mutex_unlock(&pf->switch_mutex);
6849 }
6850
6851 kfree(veb);
6852}
6853
6854/**
6855 * i40e_veb_release - Delete a VEB and free its resources
6856 * @veb: the VEB being removed
6857 **/
6858void i40e_veb_release(struct i40e_veb *veb)
6859{
6860 struct i40e_vsi *vsi = NULL;
6861 struct i40e_pf *pf;
6862 int i, n = 0;
6863
6864 pf = veb->pf;
6865
6866 /* find the remaining VSI and check for extras */
6867 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6868 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
6869 n++;
6870 vsi = pf->vsi[i];
6871 }
6872 }
6873 if (n != 1) {
6874 dev_info(&pf->pdev->dev,
6875 "can't remove VEB %d with %d VSIs left\n",
6876 veb->seid, n);
6877 return;
6878 }
6879
6880 /* move the remaining VSI to uplink veb */
6881 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
6882 if (veb->uplink_seid) {
6883 vsi->uplink_seid = veb->uplink_seid;
6884 if (veb->uplink_seid == pf->mac_seid)
6885 vsi->veb_idx = I40E_NO_VEB;
6886 else
6887 vsi->veb_idx = veb->veb_idx;
6888 } else {
6889 /* floating VEB */
6890 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6891 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
6892 }
6893
6894 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
6895 i40e_veb_clear(veb);
6896
6897 return;
6898}
6899
6900/**
6901 * i40e_add_veb - create the VEB in the switch
6902 * @veb: the VEB to be instantiated
6903 * @vsi: the controlling VSI
6904 **/
6905static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
6906{
56747264 6907 bool is_default = false;
e1c51b95 6908 bool is_cloud = false;
41c445ff
JB		 6909 int ret;
6910
6911 /* get a VEB from the hardware */
6912 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 6913 veb->enabled_tc, is_default,
6914 is_cloud, &veb->seid, NULL);
41c445ff
JB		 6915 if (ret) {
6916 dev_info(&veb->pf->pdev->dev,
6917 "couldn't add VEB, err %d, aq_err %d\n",
6918 ret, veb->pf->hw.aq.asq_last_status);
6919 return -EPERM;
6920 }
6921
6922 /* get statistics counter */
6923 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
6924 &veb->stats_idx, NULL, NULL, NULL);
6925 if (ret) {
6926 dev_info(&veb->pf->pdev->dev,
6927 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
6928 ret, veb->pf->hw.aq.asq_last_status);
6929 return -EPERM;
6930 }
6931 ret = i40e_veb_get_bw_info(veb);
6932 if (ret) {
6933 dev_info(&veb->pf->pdev->dev,
6934 "couldn't get VEB bw info, err %d, aq_err %d\n",
6935 ret, veb->pf->hw.aq.asq_last_status);
6936 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
6937 return -ENOENT;
6938 }
6939
6940 vsi->uplink_seid = veb->seid;
6941 vsi->veb_idx = veb->idx;
6942 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6943
6944 return 0;
6945}
6946
6947/**
6948 * i40e_veb_setup - Set up a VEB
6949 * @pf: board private structure
6950 * @flags: VEB setup flags
6951 * @uplink_seid: the switch element to link to
6952 * @vsi_seid: the initial VSI seid
6953 * @enabled_tc: Enabled TC bit-map
6954 *
6955 * This allocates the sw VEB structure and links it into the switch
6956 * It is possible and legal for this to be a duplicate of an already
6957 * existing VEB. It is also possible for both uplink and vsi seids
6958 * to be zero, in order to create a floating VEB.
6959 *
6960 * Returns pointer to the successfully allocated VEB sw struct on
6961 * success, otherwise returns NULL on failure.
6962 **/
6963struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
6964 u16 uplink_seid, u16 vsi_seid,
6965 u8 enabled_tc)
6966{
6967 struct i40e_veb *veb, *uplink_veb = NULL;
6968 int vsi_idx, veb_idx;
6969 int ret;
6970
6971 /* if one seid is 0, the other must be 0 to create a floating relay */
6972 if ((uplink_seid == 0 || vsi_seid == 0) &&
6973 (uplink_seid + vsi_seid != 0)) {
6974 dev_info(&pf->pdev->dev,
6975 "one, not both seid's are 0: uplink=%d vsi=%d\n",
6976 uplink_seid, vsi_seid);
6977 return NULL;
6978 }
6979
6980 /* make sure there is such a vsi and uplink */
6981 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
6982 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
6983 break;
6984 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
6985 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
6986 vsi_seid);
6987 return NULL;
6988 }
6989
6990 if (uplink_seid && uplink_seid != pf->mac_seid) {
6991 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6992 if (pf->veb[veb_idx] &&
6993 pf->veb[veb_idx]->seid == uplink_seid) {
6994 uplink_veb = pf->veb[veb_idx];
6995 break;
6996 }
6997 }
6998 if (!uplink_veb) {
6999 dev_info(&pf->pdev->dev,
7000 "uplink seid %d not found\n", uplink_seid);
7001 return NULL;
7002 }
7003 }
7004
7005 /* get veb sw struct */
7006 veb_idx = i40e_veb_mem_alloc(pf);
7007 if (veb_idx < 0)
7008 goto err_alloc;
7009 veb = pf->veb[veb_idx];
7010 veb->flags = flags;
7011 veb->uplink_seid = uplink_seid;
7012 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7013 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7014
7015 /* create the VEB in the switch */
7016 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7017 if (ret)
7018 goto err_veb;
7019
7020 return veb;
7021
7022err_veb:
7023 i40e_veb_clear(veb);
7024err_alloc:
7025 return NULL;
7026}
7027
7028/**
7029 * i40e_setup_pf_switch_element - set pf vars based on switch type
7030 * @pf: board private structure
7031 * @ele: element we are building info from
7032 * @num_reported: total number of elements
7033 * @printconfig: should we print the contents
7034 *
7035 * helper function to assist in extracting a few useful SEID values.
7036 **/
7037static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7038 struct i40e_aqc_switch_config_element_resp *ele,
7039 u16 num_reported, bool printconfig)
7040{
7041 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7042 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7043 u8 element_type = ele->element_type;
7044 u16 seid = le16_to_cpu(ele->seid);
7045
7046 if (printconfig)
7047 dev_info(&pf->pdev->dev,
7048 "type=%d seid=%d uplink=%d downlink=%d\n",
7049 element_type, seid, uplink_seid, downlink_seid);
7050
7051 switch (element_type) {
7052 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7053 pf->mac_seid = seid;
7054 break;
7055 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7056 /* Main VEB? */
7057 if (uplink_seid != pf->mac_seid)
7058 break;
7059 if (pf->lan_veb == I40E_NO_VEB) {
7060 int v;
7061
7062 /* find existing or else empty VEB */
7063 for (v = 0; v < I40E_MAX_VEB; v++) {
7064 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7065 pf->lan_veb = v;
7066 break;
7067 }
7068 }
7069 if (pf->lan_veb == I40E_NO_VEB) {
7070 v = i40e_veb_mem_alloc(pf);
7071 if (v < 0)
7072 break;
7073 pf->lan_veb = v;
7074 }
7075 }
7076
7077 pf->veb[pf->lan_veb]->seid = seid;
7078 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7079 pf->veb[pf->lan_veb]->pf = pf;
7080 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7081 break;
7082 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7083 if (num_reported != 1)
7084 break;
7085 /* This is immediately after a reset so we can assume this is
7086 * the PF's VSI
7087 */
7088 pf->mac_seid = uplink_seid;
7089 pf->pf_seid = downlink_seid;
7090 pf->main_vsi_seid = seid;
7091 if (printconfig)
7092 dev_info(&pf->pdev->dev,
7093 "pf_seid=%d main_vsi_seid=%d\n",
7094 pf->pf_seid, pf->main_vsi_seid);
7095 break;
7096 case I40E_SWITCH_ELEMENT_TYPE_PF:
7097 case I40E_SWITCH_ELEMENT_TYPE_VF:
7098 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7099 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7100 case I40E_SWITCH_ELEMENT_TYPE_PE:
7101 case I40E_SWITCH_ELEMENT_TYPE_PA:
7102 /* ignore these for now */
7103 break;
7104 default:
7105 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7106 element_type, seid);
7107 break;
7108 }
7109}
7110
7111/**
7112 * i40e_fetch_switch_configuration - Get switch config from firmware
7113 * @pf: board private structure
7114 * @printconfig: should we print the contents
7115 *
7116 * Get the current switch configuration from the device and
7117 * extract a few useful SEID values.
7118 **/
7119int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7120{
7121 struct i40e_aqc_get_switch_config_resp *sw_config;
7122 u16 next_seid = 0;
7123 int ret = 0;
7124 u8 *aq_buf;
7125 int i;
7126
7127 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7128 if (!aq_buf)
7129 return -ENOMEM;
7130
7131 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7132 do {
7133 u16 num_reported, num_total;
7134
7135 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7136 I40E_AQ_LARGE_BUF,
7137 &next_seid, NULL);
7138 if (ret) {
7139 dev_info(&pf->pdev->dev,
7140 "get switch config failed %d aq_err=%x\n",
7141 ret, pf->hw.aq.asq_last_status);
7142 kfree(aq_buf);
7143 return -ENOENT;
7144 }
7145
7146 num_reported = le16_to_cpu(sw_config->header.num_reported);
7147 num_total = le16_to_cpu(sw_config->header.num_total);
7148
7149 if (printconfig)
7150 dev_info(&pf->pdev->dev,
7151 "header: %d reported %d total\n",
7152 num_reported, num_total);
7153
7154 if (num_reported) {
7155 int sz = sizeof(*sw_config) * num_reported;
7156
7157 kfree(pf->sw_config);
7158 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7159 if (pf->sw_config)
7160 memcpy(pf->sw_config, sw_config, sz);
7161 }
7162
7163 for (i = 0; i < num_reported; i++) {
7164 struct i40e_aqc_switch_config_element_resp *ele =
7165 &sw_config->element[i];
7166
7167 i40e_setup_pf_switch_element(pf, ele, num_reported,
7168 printconfig);
7169 }
7170 } while (next_seid != 0);
7171
7172 kfree(aq_buf);
7173 return ret;
7174}
7175
7176/**
7177 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7178 * @pf: board private structure
bc7d338f 7179 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7180 *
7181 * Returns 0 on success, negative value on failure
7182 **/
bc7d338f 7183static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7184{
895106a5 7185 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7186 int ret;
7187
7188 /* find out what's out there already */
7189 ret = i40e_fetch_switch_configuration(pf, false);
7190 if (ret) {
7191 dev_info(&pf->pdev->dev,
7192 "couldn't fetch switch config, err %d, aq_err %d\n",
7193 ret, pf->hw.aq.asq_last_status);
7194 return ret;
7195 }
7196 i40e_pf_reset_stats(pf);
7197
7198 /* fdir VSI must happen first to be sure it gets queue 0, but only
7199 * if there is enough room for the fdir VSI
7200 */
7201 if (pf->num_lan_qps > 1)
7202 i40e_fdir_setup(pf);
7203
7204 /* first time setup */
bc7d338f 7205 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7206 struct i40e_vsi *vsi = NULL;
7207 u16 uplink_seid;
7208
7209 /* Set up the PF VSI associated with the PF's main VSI
7210 * that is already in the HW switch
7211 */
7212 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7213 uplink_seid = pf->veb[pf->lan_veb]->seid;
7214 else
7215 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7216 if (pf->lan_vsi == I40E_NO_VSI)
7217 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7218 else if (reinit)
7219 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7220 if (!vsi) {
7221 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7222 i40e_fdir_teardown(pf);
7223 return -EAGAIN;
7224 }
41c445ff
JB		 7225 } else {
7226 /* force a reset of TC and queue layout configurations */
7227 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7228 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7229 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7230 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7231 }
7232 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7233
7234 /* Setup static PF queue filter control settings */
7235 ret = i40e_setup_pf_filter_control(pf);
7236 if (ret) {
7237 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7238 ret);
7239 /* Failure here should not stop continuing other steps */
7240 }
7241
7242 /* enable RSS in the HW, even for only one queue, as the stack can use
7243 * the hash
7244 */
7245 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7246 i40e_config_rss(pf);
7247
7248 /* fill in link information and enable LSE reporting */
7249 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7250 i40e_link_event(pf);
7251
d52c20b7 7252 /* Initialize user-specific link properties */
41c445ff
JB		 7253 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7254 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7255 /* requested_mode is set in probe or by ethtool */
7256 if (!pf->fc_autoneg_status)
7257 goto no_autoneg;
7258
7259 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7260 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7261 pf->hw.fc.current_mode = I40E_FC_FULL;
7262 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7263 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7264 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7265 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7266 else
d52c20b7
JB		 7267 pf->hw.fc.current_mode = I40E_FC_NONE;
7268
7269 /* sync the flow control settings with the auto-neg values */
7270 switch (pf->hw.fc.current_mode) {
7271 case I40E_FC_FULL:
7272 txfc = 1;
7273 rxfc = 1;
7274 break;
7275 case I40E_FC_TX_PAUSE:
7276 txfc = 1;
7277 rxfc = 0;
7278 break;
7279 case I40E_FC_RX_PAUSE:
7280 txfc = 0;
7281 rxfc = 1;
7282 break;
7283 case I40E_FC_NONE:
7284 case I40E_FC_DEFAULT:
7285 txfc = 0;
7286 rxfc = 0;
7287 break;
7288 case I40E_FC_PFC:
7289 /* TBD */
7290 break;
7291 /* no default case, we have to handle all possibilities here */
7292 }
7293
7294 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7295
7296 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7297 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7298 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7299
7300 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7301
d52c20b7
JB		 7302 goto fc_complete;
7303
7304no_autoneg:
7305 /* disable L2 flow control, user can turn it on if they wish */
7306 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7307 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7308 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7309
7310fc_complete:
41c445ff
JB		 7311 return ret;
7312}
7313
7314/**
7315 * i40e_set_rss_size - helper to set rss_size
7316 * @pf: board private structure
7317 * @queues_left: how many queues
7318 */
7319static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
7320{
7321 int num_tc0;
7322
7323 num_tc0 = min_t(int, queues_left, pf->rss_size_max);
bf051a3b 7324 num_tc0 = min_t(int, num_tc0, num_online_cpus());
41c445ff
JB		 7325 num_tc0 = rounddown_pow_of_two(num_tc0);
7326
7327 return num_tc0;
7328}
7329
7330/**
7331 * i40e_determine_queue_usage - Work out queue distribution
7332 * @pf: board private structure
7333 **/
7334static void i40e_determine_queue_usage(struct i40e_pf *pf)
7335{
7336 int accum_tc_size;
7337 int queues_left;
7338
7339 pf->num_lan_qps = 0;
7340 pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
7341 accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
7342
7343 /* Find the max queues to be put into basic use. We'll always be
7344 * using TC0, whether or not DCB is running, and TC0 will get the
7345 * big RSS set.
7346 */
7347 queues_left = pf->hw.func_caps.num_tx_qp;
7348
9f52987b 7349 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
41c445ff
JB		 7350 !(pf->flags & (I40E_FLAG_RSS_ENABLED |
7351 I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
7352 (queues_left == 1)) {
7353
7354 /* one qp for PF, no queues for anything else */
7355 queues_left = 0;
7356 pf->rss_size = pf->num_lan_qps = 1;
7357
7358 /* make sure all the fancies are disabled */
7359 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 7360 I40E_FLAG_FDIR_ENABLED |
7361 I40E_FLAG_FDIR_ATR_ENABLED |
7362 I40E_FLAG_DCB_ENABLED |
7363 I40E_FLAG_SRIOV_ENABLED |
7364 I40E_FLAG_VMDQ_ENABLED);
7365
7366 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7367 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7368 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7369
7370 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7371
7372 queues_left -= pf->rss_size;
f8ff1464 7373 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7374
7375 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7376 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7377 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7378
7379 /* save num_tc_qps queues for TCs 1 thru 7 and the rest
7380 * are set up for RSS in TC0
7381 */
7382 queues_left -= accum_tc_size;
7383
7384 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7385
7386 queues_left -= pf->rss_size;
7387 if (queues_left < 0) {
7388 dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
7389 return;
7390 }
7391
f8ff1464 7392 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7393
7394 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7395 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7396 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7397
7398 queues_left -= 1; /* save 1 queue for FD */
7399
7400 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7401
7402 queues_left -= pf->rss_size;
7403 if (queues_left < 0) {
7404 dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
7405 return;
7406 }
7407
f8ff1464 7408 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7409
7410 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7411 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7412 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7413
7414 /* save 1 queue for TCs 1 thru 7,
7415 * 1 queue for flow director,
7416 * and the rest are set up for RSS in TC0
7417 */
7418 queues_left -= 1;
7419 queues_left -= accum_tc_size;
7420
7421 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7422 queues_left -= pf->rss_size;
7423 if (queues_left < 0) {
7424 dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
7425 return;
7426 }
7427
f8ff1464 7428 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7429
7430 } else {
7431 dev_info(&pf->pdev->dev,
7432 "Invalid configuration, flags=0x%08llx\n", pf->flags);
7433 return;
7434 }
7435
7436 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7437 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
7438 pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
7439 pf->num_vf_qps));
7440 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7441 }
7442
7443 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7444 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7445 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7446 (queues_left / pf->num_vmdq_qps));
7447 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7448 }
7449
f8ff1464 7450 pf->queues_left = queues_left;
41c445ff
JB		 7451 return;
7452}
7453
7454/**
7455 * i40e_setup_pf_filter_control - Setup PF static filter control
7456 * @pf: PF to be setup
7457 *
7458 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7459 * settings. If PE/FCoE are enabled then it will also set the per PF
7460 * based filter sizes required for them. It also enables Flow director,
7461 * ethertype and macvlan type filter settings for the pf.
7462 *
7463 * Returns 0 on success, negative on failure
7464 **/
7465static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7466{
7467 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7468
7469 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7470
7471 /* Flow Director is enabled */
7472 if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
7473 settings->enable_fdir = true;
7474
7475 /* Ethtype and MACVLAN filters enabled for PF */
7476 settings->enable_ethtype = true;
7477 settings->enable_macvlan = true;
7478
7479 if (i40e_set_filter_control(&pf->hw, settings))
7480 return -ENOENT;
7481
7482 return 0;
7483}
7484
7485/**
7486 * i40e_probe - Device initialization routine
7487 * @pdev: PCI device information struct
7488 * @ent: entry in i40e_pci_tbl
7489 *
7490 * i40e_probe initializes a pf identified by a pci_dev structure.
7491 * The OS initialization, configuring of the pf private structure,
7492 * and a hardware reset occur.
7493 *
7494 * Returns 0 on success, negative on failure
7495 **/
7496static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7497{
7498 struct i40e_driver_version dv;
7499 struct i40e_pf *pf;
7500 struct i40e_hw *hw;
93cd765b 7501 static u16 pfs_found;
d4dfb81a 7502 u16 link_status;
41c445ff
JB		 7503 int err = 0;
7504 u32 len;
7505
7506 err = pci_enable_device_mem(pdev);
7507 if (err)
7508 return err;
7509
7510 /* set up for high or low dma */
7511 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7512 /* coherent mask for the same size will always succeed if
7513 * dma_set_mask does
7514 */
7515 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7516 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7517 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7518 } else {
7519 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7520 err = -EIO;
7521 goto err_dma;
7522 }
7523
7524 /* set up pci connections */
7525 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7526 IORESOURCE_MEM), i40e_driver_name);
7527 if (err) {
7528 dev_info(&pdev->dev,
7529 "pci_request_selected_regions failed %d\n", err);
7530 goto err_pci_reg;
7531 }
7532
7533 pci_enable_pcie_error_reporting(pdev);
7534 pci_set_master(pdev);
7535
7536 /* Now that we have a PCI connection, we need to do the
7537 * low level device setup. This is primarily setting up
7538 * the Admin Queue structures and then querying for the
7539 * device's current profile information.
7540 */
7541 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7542 if (!pf) {
7543 err = -ENOMEM;
7544 goto err_pf_alloc;
7545 }
7546 pf->next_vsi = 0;
7547 pf->pdev = pdev;
7548 set_bit(__I40E_DOWN, &pf->state);
7549
7550 hw = &pf->hw;
7551 hw->back = pf;
7552 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7553 pci_resource_len(pdev, 0));
7554 if (!hw->hw_addr) {
7555 err = -EIO;
7556 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7557 (unsigned int)pci_resource_start(pdev, 0),
7558 (unsigned int)pci_resource_len(pdev, 0), err);
7559 goto err_ioremap;
7560 }
7561 hw->vendor_id = pdev->vendor;
7562 hw->device_id = pdev->device;
7563 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7564 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7565 hw->subsystem_device_id = pdev->subsystem_device;
7566 hw->bus.device = PCI_SLOT(pdev->devfn);
7567 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7568 pf->instance = pfs_found;
41c445ff 7569
7134f9ce
JB		 7570 /* do a special CORER for clearing PXE mode once at init */
7571 if (hw->revision_id == 0 &&
7572 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7573 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7574 i40e_flush(hw);
7575 msleep(200);
7576 pf->corer_count++;
7577
7578 i40e_clear_pxe_mode(hw);
7579 }
7580
41c445ff
JB		 7581 /* Reset here to make sure all is clean and to define PF 'n' */
7582 err = i40e_pf_reset(hw);
7583 if (err) {
7584 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7585 goto err_pf_reset;
7586 }
7587 pf->pfr_count++;
7588
7589 hw->aq.num_arq_entries = I40E_AQ_LEN;
7590 hw->aq.num_asq_entries = I40E_AQ_LEN;
7591 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7592 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7593 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7594 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7595 "%s-pf%d:misc",
7596 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7597
7598 err = i40e_init_shared_code(hw);
7599 if (err) {
7600 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7601 goto err_pf_reset;
7602 }
7603
d52c20b7
JB		 7604 /* set up a default setting for link flow control */
7605 pf->hw.fc.requested_mode = I40E_FC_NONE;
7606
41c445ff
JB		 7607 err = i40e_init_adminq(hw);
7608 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7609 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7610 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7611 dev_info(&pdev->dev,
7612 "warning: NVM version not supported, supported version: %02x.%02x\n",
7613 I40E_CURRENT_NVM_VERSION_HI,
7614 I40E_CURRENT_NVM_VERSION_LO);
7615 }
41c445ff
JB		 7616 if (err) {
7617 dev_info(&pdev->dev,
7618 "init_adminq failed: %d expecting API %02x.%02x\n",
7619 err,
7620 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7621 goto err_pf_reset;
7622 }
7623
7624 err = i40e_get_capabilities(pf);
7625 if (err)
7626 goto err_adminq_setup;
7627
7628 err = i40e_sw_init(pf);
7629 if (err) {
7630 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7631 goto err_sw_init;
7632 }
7633
7634 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7635 hw->func_caps.num_rx_qp,
7636 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7637 if (err) {
7638 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7639 goto err_init_lan_hmc;
7640 }
7641
7642 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7643 if (err) {
7644 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7645 err = -ENOENT;
7646 goto err_configure_lan_hmc;
7647 }
7648
7649 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 7650 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 7651 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7652 err = -EIO;
7653 goto err_mac_addr;
7654 }
7655 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7656 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7657
7658 pci_set_drvdata(pdev, pf);
7659 pci_save_state(pdev);
7660
7661 /* set up periodic task facility */
7662 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7663 pf->service_timer_period = HZ;
7664
7665 INIT_WORK(&pf->service_task, i40e_service_task);
7666 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
7667 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
7668 pf->link_check_timeout = jiffies;
7669
8e2773ae
SN		 7670 /* WoL defaults to disabled */
7671 pf->wol_en = false;
7672 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
7673
41c445ff
JB		 7674 /* set up the main switch operations */
7675 i40e_determine_queue_usage(pf);
7676 i40e_init_interrupt_scheme(pf);
7677
7678 /* Set up the *vsi struct based on the number of VSIs in the HW,
7679 * and set up our local tracking of the MAIN PF vsi.
7680 */
7681 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
7682 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 7683 if (!pf->vsi) {
7684 err = -ENOMEM;
41c445ff 7685 goto err_switch_setup;
ed87ac09 7686 }
41c445ff 7687
bc7d338f 7688 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 7689 if (err) {
7690 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
7691 goto err_vsis;
7692 }
7693
7694 /* The main driver is (mostly) up and happy. We need to set this state
7695 * before setting up the misc vector or we get a race and the vector
7696 * ends up disabled forever.
7697 */
7698 clear_bit(__I40E_DOWN, &pf->state);
7699
7700 /* In case of MSIX we are going to setup the misc vector right here
7701 * to handle admin queue events etc. In case of legacy and MSI
7702 * the misc functionality and queue processing is combined in
7703 * the same vector and that gets setup at open.
7704 */
7705 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7706 err = i40e_setup_misc_vector(pf);
7707 if (err) {
7708 dev_info(&pdev->dev,
7709 "setup of misc vector failed: %d\n", err);
7710 goto err_vsis;
7711 }
7712 }
7713
7714 /* prep for VF support */
7715 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7716 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
7717 u32 val;
7718
7719 /* disable link interrupts for VFs */
7720 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
7721 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
7722 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
7723 i40e_flush(hw);
7724 }
7725
93cd765b
ASJ		 7726 pfs_found++;
7727
41c445ff
JB		 7728 i40e_dbg_pf_init(pf);
7729
7730 /* tell the firmware that we're starting */
7731 dv.major_version = DRV_VERSION_MAJOR;
7732 dv.minor_version = DRV_VERSION_MINOR;
7733 dv.build_version = DRV_VERSION_BUILD;
7734 dv.subbuild_version = 0;
7735 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
7736
7737 /* since everything's happy, start the service_task timer */
7738 mod_timer(&pf->service_timer,
7739 round_jiffies(jiffies + pf->service_timer_period));
7740
d4dfb81a
CS		 7741 /* Get the negotiated link width and speed from PCI config space */
7742 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
7743
7744 i40e_set_pci_config_data(hw, link_status);
7745
7746 dev_info(&pdev->dev, "PCI Express: %s %s\n",
7747 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
7748 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
7749 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
7750 "Unknown"),
7751 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
7752 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
7753 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
7754 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
7755 "Unknown"));
7756
7757 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
7758 hw->bus.speed < i40e_bus_speed_8000) {
7759 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
7760 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
7761 }
7762
41c445ff
JB		 7763 return 0;
7764
7765 /* Unwind what we've done if something failed in the setup */
7766err_vsis:
7767 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 7768 i40e_clear_interrupt_scheme(pf);
7769 kfree(pf->vsi);
04b03013
SN		 7770err_switch_setup:
7771 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 7772 del_timer_sync(&pf->service_timer);
7773err_mac_addr:
7774err_configure_lan_hmc:
7775 (void)i40e_shutdown_lan_hmc(hw);
7776err_init_lan_hmc:
7777 kfree(pf->qp_pile);
7778 kfree(pf->irq_pile);
7779err_sw_init:
7780err_adminq_setup:
7781 (void)i40e_shutdown_adminq(hw);
7782err_pf_reset:
7783 iounmap(hw->hw_addr);
7784err_ioremap:
7785 kfree(pf);
7786err_pf_alloc:
7787 pci_disable_pcie_error_reporting(pdev);
7788 pci_release_selected_regions(pdev,
7789 pci_select_bars(pdev, IORESOURCE_MEM));
7790err_pci_reg:
7791err_dma:
7792 pci_disable_device(pdev);
7793 return err;
7794}
7795
7796/**
7797 * i40e_remove - Device removal routine
7798 * @pdev: PCI device information struct
7799 *
7800 * i40e_remove is called by the PCI subsystem to alert the driver
7801 * that is should release a PCI device. This could be caused by a
7802 * Hot-Plug event, or because the driver is going to be removed from
7803 * memory.
7804 **/
7805static void i40e_remove(struct pci_dev *pdev)
7806{
7807 struct i40e_pf *pf = pci_get_drvdata(pdev);
7808 i40e_status ret_code;
7809 u32 reg;
7810 int i;
7811
7812 i40e_dbg_pf_exit(pf);
7813
7814 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7815 i40e_free_vfs(pf);
7816 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
7817 }
7818
7819 /* no more scheduling of any task */
7820 set_bit(__I40E_DOWN, &pf->state);
7821 del_timer_sync(&pf->service_timer);
7822 cancel_work_sync(&pf->service_task);
7823
7824 i40e_fdir_teardown(pf);
7825
7826 /* If there is a switch structure or any orphans, remove them.
7827 * This will leave only the PF's VSI remaining.
7828 */
7829 for (i = 0; i < I40E_MAX_VEB; i++) {
7830 if (!pf->veb[i])
7831 continue;
7832
7833 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
7834 pf->veb[i]->uplink_seid == 0)
7835 i40e_switch_branch_release(pf->veb[i]);
7836 }
7837
7838 /* Now we can shutdown the PF's VSI, just before we kill
7839 * adminq and hmc.
7840 */
7841 if (pf->vsi[pf->lan_vsi])
7842 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
7843
7844 i40e_stop_misc_vector(pf);
7845 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7846 synchronize_irq(pf->msix_entries[0].vector);
7847 free_irq(pf->msix_entries[0].vector, pf);
7848 }
7849
7850 /* shutdown and destroy the HMC */
7851 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
7852 if (ret_code)
7853 dev_warn(&pdev->dev,
7854 "Failed to destroy the HMC resources: %d\n", ret_code);
7855
7856 /* shutdown the adminq */
41c445ff
JB		 7857 ret_code = i40e_shutdown_adminq(&pf->hw);
7858 if (ret_code)
7859 dev_warn(&pdev->dev,
7860 "Failed to destroy the Admin Queue resources: %d\n",
7861 ret_code);
7862
7863 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
7864 i40e_clear_interrupt_scheme(pf);
7865 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7866 if (pf->vsi[i]) {
7867 i40e_vsi_clear_rings(pf->vsi[i]);
7868 i40e_vsi_clear(pf->vsi[i]);
7869 pf->vsi[i] = NULL;
7870 }
7871 }
7872
7873 for (i = 0; i < I40E_MAX_VEB; i++) {
7874 kfree(pf->veb[i]);
7875 pf->veb[i] = NULL;
7876 }
7877
7878 kfree(pf->qp_pile);
7879 kfree(pf->irq_pile);
7880 kfree(pf->sw_config);
7881 kfree(pf->vsi);
7882
7883 /* force a PF reset to clean anything leftover */
7884 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
7885 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7886 i40e_flush(&pf->hw);
7887
7888 iounmap(pf->hw.hw_addr);
7889 kfree(pf);
7890 pci_release_selected_regions(pdev,
7891 pci_select_bars(pdev, IORESOURCE_MEM));
7892
7893 pci_disable_pcie_error_reporting(pdev);
7894 pci_disable_device(pdev);
7895}
7896
7897/**
7898 * i40e_pci_error_detected - warning that something funky happened in PCI land
7899 * @pdev: PCI device information struct
7900 *
7901 * Called to warn that something happened and the error handling steps
7902 * are in progress. Allows the driver to quiesce things, be ready for
7903 * remediation.
7904 **/
7905static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
7906 enum pci_channel_state error)
7907{
7908 struct i40e_pf *pf = pci_get_drvdata(pdev);
7909
7910 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
7911
7912 /* shutdown all operations */
9007bccd
SN		 7913 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
7914 rtnl_lock();
7915 i40e_prep_for_reset(pf);
7916 rtnl_unlock();
7917 }
41c445ff
JB		 7918
7919 /* Request a slot reset */
7920 return PCI_ERS_RESULT_NEED_RESET;
7921}
7922
7923/**
7924 * i40e_pci_error_slot_reset - a PCI slot reset just happened
7925 * @pdev: PCI device information struct
7926 *
7927 * Called to find if the driver can work with the device now that
7928 * the pci slot has been reset. If a basic connection seems good
7929 * (registers are readable and have sane content) then return a
7930 * happy little PCI_ERS_RESULT_xxx.
7931 **/
7932static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
7933{
7934 struct i40e_pf *pf = pci_get_drvdata(pdev);
7935 pci_ers_result_t result;
7936 int err;
7937 u32 reg;
7938
7939 dev_info(&pdev->dev, "%s\n", __func__);
7940 if (pci_enable_device_mem(pdev)) {
7941 dev_info(&pdev->dev,
7942 "Cannot re-enable PCI device after reset.\n");
7943 result = PCI_ERS_RESULT_DISCONNECT;
7944 } else {
7945 pci_set_master(pdev);
7946 pci_restore_state(pdev);
7947 pci_save_state(pdev);
7948 pci_wake_from_d3(pdev, false);
7949
7950 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7951 if (reg == 0)
7952 result = PCI_ERS_RESULT_RECOVERED;
7953 else
7954 result = PCI_ERS_RESULT_DISCONNECT;
7955 }
7956
7957 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7958 if (err) {
7959 dev_info(&pdev->dev,
7960 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7961 err);
7962 /* non-fatal, continue */
7963 }
7964
7965 return result;
7966}
7967
7968/**
7969 * i40e_pci_error_resume - restart operations after PCI error recovery
7970 * @pdev: PCI device information struct
7971 *
7972 * Called to allow the driver to bring things back up after PCI error
7973 * and/or reset recovery has finished.
7974 **/
7975static void i40e_pci_error_resume(struct pci_dev *pdev)
7976{
7977 struct i40e_pf *pf = pci_get_drvdata(pdev);
7978
7979 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 7980 if (test_bit(__I40E_SUSPENDED, &pf->state))
7981 return;
7982
7983 rtnl_lock();
41c445ff 7984 i40e_handle_reset_warning(pf);
9007bccd
SN		 7985 rtnl_lock();
7986}
7987
7988/**
7989 * i40e_shutdown - PCI callback for shutting down
7990 * @pdev: PCI device information struct
7991 **/
7992static void i40e_shutdown(struct pci_dev *pdev)
7993{
7994 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 7995 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 7996
7997 set_bit(__I40E_SUSPENDED, &pf->state);
7998 set_bit(__I40E_DOWN, &pf->state);
7999 rtnl_lock();
8000 i40e_prep_for_reset(pf);
8001 rtnl_unlock();
8002
8e2773ae
SN		 8003 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8004 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8005
9007bccd 8006 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8007 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8008 pci_set_power_state(pdev, PCI_D3hot);
8009 }
8010}
8011
8012#ifdef CONFIG_PM
8013/**
8014 * i40e_suspend - PCI callback for moving to D3
8015 * @pdev: PCI device information struct
8016 **/
8017static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8018{
8019 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8020 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8021
8022 set_bit(__I40E_SUSPENDED, &pf->state);
8023 set_bit(__I40E_DOWN, &pf->state);
8024 rtnl_lock();
8025 i40e_prep_for_reset(pf);
8026 rtnl_unlock();
8027
8e2773ae
SN		 8028 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8029 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8030
8031 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8032 pci_set_power_state(pdev, PCI_D3hot);
8033
8034 return 0;
41c445ff
JB		 8035}
8036
9007bccd
SN		 8037/**
8038 * i40e_resume - PCI callback for waking up from D3
8039 * @pdev: PCI device information struct
8040 **/
8041static int i40e_resume(struct pci_dev *pdev)
8042{
8043 struct i40e_pf *pf = pci_get_drvdata(pdev);
8044 u32 err;
8045
8046 pci_set_power_state(pdev, PCI_D0);
8047 pci_restore_state(pdev);
8048 /* pci_restore_state() clears dev->state_saves, so
8049 * call pci_save_state() again to restore it.
8050 */
8051 pci_save_state(pdev);
8052
8053 err = pci_enable_device_mem(pdev);
8054 if (err) {
8055 dev_err(&pdev->dev,
8056 "%s: Cannot enable PCI device from suspend\n",
8057 __func__);
8058 return err;
8059 }
8060 pci_set_master(pdev);
8061
8062 /* no wakeup events while running */
8063 pci_wake_from_d3(pdev, false);
8064
8065 /* handling the reset will rebuild the device state */
8066 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8067 clear_bit(__I40E_DOWN, &pf->state);
8068 rtnl_lock();
8069 i40e_reset_and_rebuild(pf, false);
8070 rtnl_unlock();
8071 }
8072
8073 return 0;
8074}
8075
8076#endif
41c445ff
JB		 8077static const struct pci_error_handlers i40e_err_handler = {
8078 .error_detected = i40e_pci_error_detected,
8079 .slot_reset = i40e_pci_error_slot_reset,
8080 .resume = i40e_pci_error_resume,
8081};
8082
8083static struct pci_driver i40e_driver = {
8084 .name = i40e_driver_name,
8085 .id_table = i40e_pci_tbl,
8086 .probe = i40e_probe,
8087 .remove = i40e_remove,
9007bccd
SN		 8088#ifdef CONFIG_PM
8089 .suspend = i40e_suspend,
8090 .resume = i40e_resume,
8091#endif
8092 .shutdown = i40e_shutdown,
41c445ff
JB		 8093 .err_handler = &i40e_err_handler,
8094 .sriov_configure = i40e_pci_sriov_configure,
8095};
8096
8097/**
8098 * i40e_init_module - Driver registration routine
8099 *
8100 * i40e_init_module is the first routine called when the driver is
8101 * loaded. All it does is register with the PCI subsystem.
8102 **/
8103static int __init i40e_init_module(void)
8104{
8105 pr_info("%s: %s - version %s\n", i40e_driver_name,
8106 i40e_driver_string, i40e_driver_version_str);
8107 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8108 i40e_dbg_init();
8109 return pci_register_driver(&i40e_driver);
8110}
8111module_init(i40e_init_module);
8112
8113/**
8114 * i40e_exit_module - Driver exit cleanup routine
8115 *
8116 * i40e_exit_module is called just before the driver is removed
8117 * from memory.
8118 **/
8119static void __exit i40e_exit_module(void)
8120{
8121 pci_unregister_driver(&i40e_driver);
8122 i40e_dbg_exit();
8123}
8124module_exit(i40e_exit_module);
Linux kernel - Deliverables
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