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i40e: Add flag for L2 VEB filtering
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28/* Local includes */
29#include "i40e.h"
30
31const char i40e_driver_name[] = "i40e";
32static const char i40e_driver_string[] =
33 "Intel(R) Ethernet Connection XL710 Network Driver";
34
35#define DRV_KERN "-k"
36
37#define DRV_VERSION_MAJOR 0
38#define DRV_VERSION_MINOR 3
1de046b9 39#define DRV_VERSION_BUILD 11
41c445ff
JB		 40#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
41 __stringify(DRV_VERSION_MINOR) "." \
42 __stringify(DRV_VERSION_BUILD) DRV_KERN
43const char i40e_driver_version_str[] = DRV_VERSION;
44static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
45
46/* a bit of forward declarations */
47static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
48static void i40e_handle_reset_warning(struct i40e_pf *pf);
49static int i40e_add_vsi(struct i40e_vsi *vsi);
50static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
51static int i40e_setup_pf_switch(struct i40e_pf *pf);
52static int i40e_setup_misc_vector(struct i40e_pf *pf);
53static void i40e_determine_queue_usage(struct i40e_pf *pf);
54static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
55
56/* i40e_pci_tbl - PCI Device ID Table
57 *
58 * Last entry must be all 0s
59 *
60 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
61 * Class, Class Mask, private data (not used) }
62 */
63static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
64 {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
65 {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
66 {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
67 {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
68 {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
69 {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
70 {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
71 {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
72 {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
73 {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
74 /* required last entry */
75 {0, }
76};
77MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
78
79#define I40E_MAX_VF_COUNT 128
80static int debug = -1;
81module_param(debug, int, 0);
82MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
83
84MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
85MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
86MODULE_LICENSE("GPL");
87MODULE_VERSION(DRV_VERSION);
88
89/**
90 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
91 * @hw: pointer to the HW structure
92 * @mem: ptr to mem struct to fill out
93 * @size: size of memory requested
94 * @alignment: what to align the allocation to
95 **/
96int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
97 u64 size, u32 alignment)
98{
99 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
100
101 mem->size = ALIGN(size, alignment);
102 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
103 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 104 if (!mem->va)
105 return -ENOMEM;
41c445ff 106
93bc73b8 107 return 0;
41c445ff
JB		 108}
109
110/**
111 * i40e_free_dma_mem_d - OS specific memory free for shared code
112 * @hw: pointer to the HW structure
113 * @mem: ptr to mem struct to free
114 **/
115int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
116{
117 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
118
119 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
120 mem->va = NULL;
121 mem->pa = 0;
122 mem->size = 0;
123
124 return 0;
125}
126
127/**
128 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
129 * @hw: pointer to the HW structure
130 * @mem: ptr to mem struct to fill out
131 * @size: size of memory requested
132 **/
133int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
134 u32 size)
135{
136 mem->size = size;
137 mem->va = kzalloc(size, GFP_KERNEL);
138
93bc73b8
JB		 139 if (!mem->va)
140 return -ENOMEM;
41c445ff 141
93bc73b8 142 return 0;
41c445ff
JB		 143}
144
145/**
146 * i40e_free_virt_mem_d - OS specific memory free for shared code
147 * @hw: pointer to the HW structure
148 * @mem: ptr to mem struct to free
149 **/
150int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
151{
152 /* it's ok to kfree a NULL pointer */
153 kfree(mem->va);
154 mem->va = NULL;
155 mem->size = 0;
156
157 return 0;
158}
159
160/**
161 * i40e_get_lump - find a lump of free generic resource
162 * @pf: board private structure
163 * @pile: the pile of resource to search
164 * @needed: the number of items needed
165 * @id: an owner id to stick on the items assigned
166 *
167 * Returns the base item index of the lump, or negative for error
168 *
169 * The search_hint trick and lack of advanced fit-finding only work
170 * because we're highly likely to have all the same size lump requests.
171 * Linear search time and any fragmentation should be minimal.
172 **/
173static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
174 u16 needed, u16 id)
175{
176 int ret = -ENOMEM;
ddf434ac 177 int i, j;
41c445ff
JB		 178
179 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
180 dev_info(&pf->pdev->dev,
181 "param err: pile=%p needed=%d id=0x%04x\n",
182 pile, needed, id);
183 return -EINVAL;
184 }
185
186 /* start the linear search with an imperfect hint */
187 i = pile->search_hint;
ddf434ac 188 while (i < pile->num_entries) {
41c445ff
JB		 189 /* skip already allocated entries */
190 if (pile->list[i] & I40E_PILE_VALID_BIT) {
191 i++;
192 continue;
193 }
194
195 /* do we have enough in this lump? */
196 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
197 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
198 break;
199 }
200
201 if (j == needed) {
202 /* there was enough, so assign it to the requestor */
203 for (j = 0; j < needed; j++)
204 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
205 ret = i;
206 pile->search_hint = i + j;
ddf434ac 207 break;
41c445ff
JB		 208 } else {
209 /* not enough, so skip over it and continue looking */
210 i += j;
211 }
212 }
213
214 return ret;
215}
216
217/**
218 * i40e_put_lump - return a lump of generic resource
219 * @pile: the pile of resource to search
220 * @index: the base item index
221 * @id: the owner id of the items assigned
222 *
223 * Returns the count of items in the lump
224 **/
225static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
226{
227 int valid_id = (id | I40E_PILE_VALID_BIT);
228 int count = 0;
229 int i;
230
231 if (!pile || index >= pile->num_entries)
232 return -EINVAL;
233
234 for (i = index;
235 i < pile->num_entries && pile->list[i] == valid_id;
236 i++) {
237 pile->list[i] = 0;
238 count++;
239 }
240
241 if (count && index < pile->search_hint)
242 pile->search_hint = index;
243
244 return count;
245}
246
247/**
248 * i40e_service_event_schedule - Schedule the service task to wake up
249 * @pf: board private structure
250 *
251 * If not already scheduled, this puts the task into the work queue
252 **/
253static void i40e_service_event_schedule(struct i40e_pf *pf)
254{
255 if (!test_bit(__I40E_DOWN, &pf->state) &&
256 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
257 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
258 schedule_work(&pf->service_task);
259}
260
261/**
262 * i40e_tx_timeout - Respond to a Tx Hang
263 * @netdev: network interface device structure
264 *
265 * If any port has noticed a Tx timeout, it is likely that the whole
266 * device is munged, not just the one netdev port, so go for the full
267 * reset.
268 **/
269static void i40e_tx_timeout(struct net_device *netdev)
270{
271 struct i40e_netdev_priv *np = netdev_priv(netdev);
272 struct i40e_vsi *vsi = np->vsi;
273 struct i40e_pf *pf = vsi->back;
274
275 pf->tx_timeout_count++;
276
277 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
278 pf->tx_timeout_recovery_level = 0;
279 pf->tx_timeout_last_recovery = jiffies;
280 netdev_info(netdev, "tx_timeout recovery level %d\n",
281 pf->tx_timeout_recovery_level);
282
283 switch (pf->tx_timeout_recovery_level) {
284 case 0:
285 /* disable and re-enable queues for the VSI */
286 if (in_interrupt()) {
287 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
288 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
289 } else {
290 i40e_vsi_reinit_locked(vsi);
291 }
292 break;
293 case 1:
294 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
295 break;
296 case 2:
297 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
298 break;
299 case 3:
300 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
301 break;
302 default:
303 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
304 i40e_down(vsi);
305 break;
306 }
307 i40e_service_event_schedule(pf);
308 pf->tx_timeout_recovery_level++;
309}
310
311/**
312 * i40e_release_rx_desc - Store the new tail and head values
313 * @rx_ring: ring to bump
314 * @val: new head index
315 **/
316static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
317{
318 rx_ring->next_to_use = val;
319
320 /* Force memory writes to complete before letting h/w
321 * know there are new descriptors to fetch. (Only
322 * applicable for weak-ordered memory model archs,
323 * such as IA-64).
324 */
325 wmb();
326 writel(val, rx_ring->tail);
327}
328
329/**
330 * i40e_get_vsi_stats_struct - Get System Network Statistics
331 * @vsi: the VSI we care about
332 *
333 * Returns the address of the device statistics structure.
334 * The statistics are actually updated from the service task.
335 **/
336struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
337{
338 return &vsi->net_stats;
339}
340
341/**
342 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
343 * @netdev: network interface device structure
344 *
345 * Returns the address of the device statistics structure.
346 * The statistics are actually updated from the service task.
347 **/
348static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
349 struct net_device *netdev,
980e9b11 350 struct rtnl_link_stats64 *stats)
41c445ff
JB		 351{
352 struct i40e_netdev_priv *np = netdev_priv(netdev);
353 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 354 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
355 int i;
356
357 rcu_read_lock();
358 for (i = 0; i < vsi->num_queue_pairs; i++) {
359 struct i40e_ring *tx_ring, *rx_ring;
360 u64 bytes, packets;
361 unsigned int start;
362
363 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
364 if (!tx_ring)
365 continue;
366
367 do {
368 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
369 packets = tx_ring->stats.packets;
370 bytes = tx_ring->stats.bytes;
371 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
372
373 stats->tx_packets += packets;
374 stats->tx_bytes += bytes;
375 rx_ring = &tx_ring[1];
376
377 do {
378 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
379 packets = rx_ring->stats.packets;
380 bytes = rx_ring->stats.bytes;
381 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 382
980e9b11
AD		 383 stats->rx_packets += packets;
384 stats->rx_bytes += bytes;
385 }
386 rcu_read_unlock();
387
388 /* following stats updated by ixgbe_watchdog_task() */
389 stats->multicast = vsi_stats->multicast;
390 stats->tx_errors = vsi_stats->tx_errors;
391 stats->tx_dropped = vsi_stats->tx_dropped;
392 stats->rx_errors = vsi_stats->rx_errors;
393 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
394 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 395
980e9b11 396 return stats;
41c445ff
JB		 397}
398
399/**
400 * i40e_vsi_reset_stats - Resets all stats of the given vsi
401 * @vsi: the VSI to have its stats reset
402 **/
403void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
404{
405 struct rtnl_link_stats64 *ns;
406 int i;
407
408 if (!vsi)
409 return;
410
411 ns = i40e_get_vsi_stats_struct(vsi);
412 memset(ns, 0, sizeof(*ns));
413 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
414 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
415 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
416 if (vsi->rx_rings)
417 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 418 memset(&vsi->rx_rings[i]->stats, 0 ,
419 sizeof(vsi->rx_rings[i]->stats));
420 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
421 sizeof(vsi->rx_rings[i]->rx_stats));
422 memset(&vsi->tx_rings[i]->stats, 0 ,
423 sizeof(vsi->tx_rings[i]->stats));
424 memset(&vsi->tx_rings[i]->tx_stats, 0,
425 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff
JB		 426 }
427 vsi->stat_offsets_loaded = false;
428}
429
430/**
431 * i40e_pf_reset_stats - Reset all of the stats for the given pf
432 * @pf: the PF to be reset
433 **/
434void i40e_pf_reset_stats(struct i40e_pf *pf)
435{
436 memset(&pf->stats, 0, sizeof(pf->stats));
437 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
438 pf->stat_offsets_loaded = false;
439}
440
441/**
442 * i40e_stat_update48 - read and update a 48 bit stat from the chip
443 * @hw: ptr to the hardware info
444 * @hireg: the high 32 bit reg to read
445 * @loreg: the low 32 bit reg to read
446 * @offset_loaded: has the initial offset been loaded yet
447 * @offset: ptr to current offset value
448 * @stat: ptr to the stat
449 *
450 * Since the device stats are not reset at PFReset, they likely will not
451 * be zeroed when the driver starts. We'll save the first values read
452 * and use them as offsets to be subtracted from the raw values in order
453 * to report stats that count from zero. In the process, we also manage
454 * the potential roll-over.
455 **/
456static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
457 bool offset_loaded, u64 *offset, u64 *stat)
458{
459 u64 new_data;
460
461 if (hw->device_id == I40E_QEMU_DEVICE_ID) {
462 new_data = rd32(hw, loreg);
463 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
464 } else {
465 new_data = rd64(hw, loreg);
466 }
467 if (!offset_loaded)
468 *offset = new_data;
469 if (likely(new_data >= *offset))
470 *stat = new_data - *offset;
471 else
472 *stat = (new_data + ((u64)1 << 48)) - *offset;
473 *stat &= 0xFFFFFFFFFFFFULL;
474}
475
476/**
477 * i40e_stat_update32 - read and update a 32 bit stat from the chip
478 * @hw: ptr to the hardware info
479 * @reg: the hw reg to read
480 * @offset_loaded: has the initial offset been loaded yet
481 * @offset: ptr to current offset value
482 * @stat: ptr to the stat
483 **/
484static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
485 bool offset_loaded, u64 *offset, u64 *stat)
486{
487 u32 new_data;
488
489 new_data = rd32(hw, reg);
490 if (!offset_loaded)
491 *offset = new_data;
492 if (likely(new_data >= *offset))
493 *stat = (u32)(new_data - *offset);
494 else
495 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
496}
497
498/**
499 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
500 * @vsi: the VSI to be updated
501 **/
502void i40e_update_eth_stats(struct i40e_vsi *vsi)
503{
504 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
505 struct i40e_pf *pf = vsi->back;
506 struct i40e_hw *hw = &pf->hw;
507 struct i40e_eth_stats *oes;
508 struct i40e_eth_stats *es; /* device's eth stats */
509
510 es = &vsi->eth_stats;
511 oes = &vsi->eth_stats_offsets;
512
513 /* Gather up the stats that the hw collects */
514 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
515 vsi->stat_offsets_loaded,
516 &oes->tx_errors, &es->tx_errors);
517 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
518 vsi->stat_offsets_loaded,
519 &oes->rx_discards, &es->rx_discards);
520
521 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
522 I40E_GLV_GORCL(stat_idx),
523 vsi->stat_offsets_loaded,
524 &oes->rx_bytes, &es->rx_bytes);
525 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
526 I40E_GLV_UPRCL(stat_idx),
527 vsi->stat_offsets_loaded,
528 &oes->rx_unicast, &es->rx_unicast);
529 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
530 I40E_GLV_MPRCL(stat_idx),
531 vsi->stat_offsets_loaded,
532 &oes->rx_multicast, &es->rx_multicast);
533 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
534 I40E_GLV_BPRCL(stat_idx),
535 vsi->stat_offsets_loaded,
536 &oes->rx_broadcast, &es->rx_broadcast);
537
538 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
539 I40E_GLV_GOTCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->tx_bytes, &es->tx_bytes);
542 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
543 I40E_GLV_UPTCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->tx_unicast, &es->tx_unicast);
546 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
547 I40E_GLV_MPTCL(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->tx_multicast, &es->tx_multicast);
550 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
551 I40E_GLV_BPTCL(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->tx_broadcast, &es->tx_broadcast);
554 vsi->stat_offsets_loaded = true;
555}
556
557/**
558 * i40e_update_veb_stats - Update Switch component statistics
559 * @veb: the VEB being updated
560 **/
561static void i40e_update_veb_stats(struct i40e_veb *veb)
562{
563 struct i40e_pf *pf = veb->pf;
564 struct i40e_hw *hw = &pf->hw;
565 struct i40e_eth_stats *oes;
566 struct i40e_eth_stats *es; /* device's eth stats */
567 int idx = 0;
568
569 idx = veb->stats_idx;
570 es = &veb->stats;
571 oes = &veb->stats_offsets;
572
573 /* Gather up the stats that the hw collects */
574 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
575 veb->stat_offsets_loaded,
576 &oes->tx_discards, &es->tx_discards);
577 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
578 veb->stat_offsets_loaded,
579 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
580
581 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
582 veb->stat_offsets_loaded,
583 &oes->rx_bytes, &es->rx_bytes);
584 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
585 veb->stat_offsets_loaded,
586 &oes->rx_unicast, &es->rx_unicast);
587 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
588 veb->stat_offsets_loaded,
589 &oes->rx_multicast, &es->rx_multicast);
590 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
591 veb->stat_offsets_loaded,
592 &oes->rx_broadcast, &es->rx_broadcast);
593
594 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
595 veb->stat_offsets_loaded,
596 &oes->tx_bytes, &es->tx_bytes);
597 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
598 veb->stat_offsets_loaded,
599 &oes->tx_unicast, &es->tx_unicast);
600 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
601 veb->stat_offsets_loaded,
602 &oes->tx_multicast, &es->tx_multicast);
603 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
604 veb->stat_offsets_loaded,
605 &oes->tx_broadcast, &es->tx_broadcast);
606 veb->stat_offsets_loaded = true;
607}
608
609/**
610 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
611 * @pf: the corresponding PF
612 *
613 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
614 **/
615static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
616{
617 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
618 struct i40e_hw_port_stats *nsd = &pf->stats;
619 struct i40e_hw *hw = &pf->hw;
620 u64 xoff = 0;
621 u16 i, v;
622
623 if ((hw->fc.current_mode != I40E_FC_FULL) &&
624 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
625 return;
626
627 xoff = nsd->link_xoff_rx;
628 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
629 pf->stat_offsets_loaded,
630 &osd->link_xoff_rx, &nsd->link_xoff_rx);
631
632 /* No new LFC xoff rx */
633 if (!(nsd->link_xoff_rx - xoff))
634 return;
635
636 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
637 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
638 struct i40e_vsi *vsi = pf->vsi[v];
639
640 if (!vsi)
641 continue;
642
643 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 644 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 645 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
646 }
647 }
648}
649
650/**
651 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
652 * @pf: the corresponding PF
653 *
654 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
655 **/
656static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
657{
658 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
659 struct i40e_hw_port_stats *nsd = &pf->stats;
660 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
661 struct i40e_dcbx_config *dcb_cfg;
662 struct i40e_hw *hw = &pf->hw;
663 u16 i, v;
664 u8 tc;
665
666 dcb_cfg = &hw->local_dcbx_config;
667
668 /* See if DCB enabled with PFC TC */
669 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
670 !(dcb_cfg->pfc.pfcenable)) {
671 i40e_update_link_xoff_rx(pf);
672 return;
673 }
674
675 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
676 u64 prio_xoff = nsd->priority_xoff_rx[i];
677 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
678 pf->stat_offsets_loaded,
679 &osd->priority_xoff_rx[i],
680 &nsd->priority_xoff_rx[i]);
681
682 /* No new PFC xoff rx */
683 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
684 continue;
685 /* Get the TC for given priority */
686 tc = dcb_cfg->etscfg.prioritytable[i];
687 xoff[tc] = true;
688 }
689
690 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
691 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
692 struct i40e_vsi *vsi = pf->vsi[v];
693
694 if (!vsi)
695 continue;
696
697 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 698 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 699
700 tc = ring->dcb_tc;
701 if (xoff[tc])
702 clear_bit(__I40E_HANG_CHECK_ARMED,
703 &ring->state);
704 }
705 }
706}
707
708/**
709 * i40e_update_stats - Update the board statistics counters.
710 * @vsi: the VSI to be updated
711 *
712 * There are a few instances where we store the same stat in a
713 * couple of different structs. This is partly because we have
714 * the netdev stats that need to be filled out, which is slightly
715 * different from the "eth_stats" defined by the chip and used in
716 * VF communications. We sort it all out here in a central place.
717 **/
718void i40e_update_stats(struct i40e_vsi *vsi)
719{
720 struct i40e_pf *pf = vsi->back;
721 struct i40e_hw *hw = &pf->hw;
722 struct rtnl_link_stats64 *ons;
723 struct rtnl_link_stats64 *ns; /* netdev stats */
724 struct i40e_eth_stats *oes;
725 struct i40e_eth_stats *es; /* device's eth stats */
726 u32 tx_restart, tx_busy;
727 u32 rx_page, rx_buf;
728 u64 rx_p, rx_b;
729 u64 tx_p, tx_b;
730 int i;
731 u16 q;
732
733 if (test_bit(__I40E_DOWN, &vsi->state) ||
734 test_bit(__I40E_CONFIG_BUSY, &pf->state))
735 return;
736
737 ns = i40e_get_vsi_stats_struct(vsi);
738 ons = &vsi->net_stats_offsets;
739 es = &vsi->eth_stats;
740 oes = &vsi->eth_stats_offsets;
741
742 /* Gather up the netdev and vsi stats that the driver collects
743 * on the fly during packet processing
744 */
745 rx_b = rx_p = 0;
746 tx_b = tx_p = 0;
747 tx_restart = tx_busy = 0;
748 rx_page = 0;
749 rx_buf = 0;
980e9b11 750 rcu_read_lock();
41c445ff
JB		 751 for (q = 0; q < vsi->num_queue_pairs; q++) {
752 struct i40e_ring *p;
980e9b11
AD		 753 u64 bytes, packets;
754 unsigned int start;
755
756 /* locate Tx ring */
757 p = ACCESS_ONCE(vsi->tx_rings[q]);
758
759 do {
760 start = u64_stats_fetch_begin_bh(&p->syncp);
761 packets = p->stats.packets;
762 bytes = p->stats.bytes;
763 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
764 tx_b += bytes;
765 tx_p += packets;
766 tx_restart += p->tx_stats.restart_queue;
767 tx_busy += p->tx_stats.tx_busy;
41c445ff 768
980e9b11
AD		 769 /* Rx queue is part of the same block as Tx queue */
770 p = &p[1];
771 do {
772 start = u64_stats_fetch_begin_bh(&p->syncp);
773 packets = p->stats.packets;
774 bytes = p->stats.bytes;
775 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
776 rx_b += bytes;
777 rx_p += packets;
41c445ff
JB		 778 rx_buf += p->rx_stats.alloc_rx_buff_failed;
779 rx_page += p->rx_stats.alloc_rx_page_failed;
41c445ff 780 }
980e9b11 781 rcu_read_unlock();
41c445ff
JB		 782 vsi->tx_restart = tx_restart;
783 vsi->tx_busy = tx_busy;
784 vsi->rx_page_failed = rx_page;
785 vsi->rx_buf_failed = rx_buf;
786
787 ns->rx_packets = rx_p;
788 ns->rx_bytes = rx_b;
789 ns->tx_packets = tx_p;
790 ns->tx_bytes = tx_b;
791
792 i40e_update_eth_stats(vsi);
793 /* update netdev stats from eth stats */
794 ons->rx_errors = oes->rx_errors;
795 ns->rx_errors = es->rx_errors;
796 ons->tx_errors = oes->tx_errors;
797 ns->tx_errors = es->tx_errors;
798 ons->multicast = oes->rx_multicast;
799 ns->multicast = es->rx_multicast;
800 ons->tx_dropped = oes->tx_discards;
801 ns->tx_dropped = es->tx_discards;
802
803 /* Get the port data only if this is the main PF VSI */
804 if (vsi == pf->vsi[pf->lan_vsi]) {
805 struct i40e_hw_port_stats *nsd = &pf->stats;
806 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
807
808 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
809 I40E_GLPRT_GORCL(hw->port),
810 pf->stat_offsets_loaded,
811 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
812 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
813 I40E_GLPRT_GOTCL(hw->port),
814 pf->stat_offsets_loaded,
815 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
816 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
817 pf->stat_offsets_loaded,
818 &osd->eth.rx_discards,
819 &nsd->eth.rx_discards);
820 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
821 pf->stat_offsets_loaded,
822 &osd->eth.tx_discards,
823 &nsd->eth.tx_discards);
824 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
825 I40E_GLPRT_MPRCL(hw->port),
826 pf->stat_offsets_loaded,
827 &osd->eth.rx_multicast,
828 &nsd->eth.rx_multicast);
829
830 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
831 pf->stat_offsets_loaded,
832 &osd->tx_dropped_link_down,
833 &nsd->tx_dropped_link_down);
834
835 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
836 pf->stat_offsets_loaded,
837 &osd->crc_errors, &nsd->crc_errors);
838 ns->rx_crc_errors = nsd->crc_errors;
839
840 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->illegal_bytes, &nsd->illegal_bytes);
843 ns->rx_errors = nsd->crc_errors
844 + nsd->illegal_bytes;
845
846 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
847 pf->stat_offsets_loaded,
848 &osd->mac_local_faults,
849 &nsd->mac_local_faults);
850 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
851 pf->stat_offsets_loaded,
852 &osd->mac_remote_faults,
853 &nsd->mac_remote_faults);
854
855 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
856 pf->stat_offsets_loaded,
857 &osd->rx_length_errors,
858 &nsd->rx_length_errors);
859 ns->rx_length_errors = nsd->rx_length_errors;
860
861 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->link_xon_rx, &nsd->link_xon_rx);
864 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
865 pf->stat_offsets_loaded,
866 &osd->link_xon_tx, &nsd->link_xon_tx);
867 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
868 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
869 pf->stat_offsets_loaded,
870 &osd->link_xoff_tx, &nsd->link_xoff_tx);
871
872 for (i = 0; i < 8; i++) {
873 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
874 pf->stat_offsets_loaded,
875 &osd->priority_xon_rx[i],
876 &nsd->priority_xon_rx[i]);
877 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
878 pf->stat_offsets_loaded,
879 &osd->priority_xon_tx[i],
880 &nsd->priority_xon_tx[i]);
881 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
882 pf->stat_offsets_loaded,
883 &osd->priority_xoff_tx[i],
884 &nsd->priority_xoff_tx[i]);
885 i40e_stat_update32(hw,
886 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
887 pf->stat_offsets_loaded,
888 &osd->priority_xon_2_xoff[i],
889 &nsd->priority_xon_2_xoff[i]);
890 }
891
892 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
893 I40E_GLPRT_PRC64L(hw->port),
894 pf->stat_offsets_loaded,
895 &osd->rx_size_64, &nsd->rx_size_64);
896 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
897 I40E_GLPRT_PRC127L(hw->port),
898 pf->stat_offsets_loaded,
899 &osd->rx_size_127, &nsd->rx_size_127);
900 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
901 I40E_GLPRT_PRC255L(hw->port),
902 pf->stat_offsets_loaded,
903 &osd->rx_size_255, &nsd->rx_size_255);
904 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
905 I40E_GLPRT_PRC511L(hw->port),
906 pf->stat_offsets_loaded,
907 &osd->rx_size_511, &nsd->rx_size_511);
908 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
909 I40E_GLPRT_PRC1023L(hw->port),
910 pf->stat_offsets_loaded,
911 &osd->rx_size_1023, &nsd->rx_size_1023);
912 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
913 I40E_GLPRT_PRC1522L(hw->port),
914 pf->stat_offsets_loaded,
915 &osd->rx_size_1522, &nsd->rx_size_1522);
916 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
917 I40E_GLPRT_PRC9522L(hw->port),
918 pf->stat_offsets_loaded,
919 &osd->rx_size_big, &nsd->rx_size_big);
920
921 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
922 I40E_GLPRT_PTC64L(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->tx_size_64, &nsd->tx_size_64);
925 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
926 I40E_GLPRT_PTC127L(hw->port),
927 pf->stat_offsets_loaded,
928 &osd->tx_size_127, &nsd->tx_size_127);
929 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
930 I40E_GLPRT_PTC255L(hw->port),
931 pf->stat_offsets_loaded,
932 &osd->tx_size_255, &nsd->tx_size_255);
933 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
934 I40E_GLPRT_PTC511L(hw->port),
935 pf->stat_offsets_loaded,
936 &osd->tx_size_511, &nsd->tx_size_511);
937 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
938 I40E_GLPRT_PTC1023L(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->tx_size_1023, &nsd->tx_size_1023);
941 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
942 I40E_GLPRT_PTC1522L(hw->port),
943 pf->stat_offsets_loaded,
944 &osd->tx_size_1522, &nsd->tx_size_1522);
945 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
946 I40E_GLPRT_PTC9522L(hw->port),
947 pf->stat_offsets_loaded,
948 &osd->tx_size_big, &nsd->tx_size_big);
949
950 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->rx_undersize, &nsd->rx_undersize);
953 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->rx_fragments, &nsd->rx_fragments);
956 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
957 pf->stat_offsets_loaded,
958 &osd->rx_oversize, &nsd->rx_oversize);
959 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
960 pf->stat_offsets_loaded,
961 &osd->rx_jabber, &nsd->rx_jabber);
962 }
963
964 pf->stat_offsets_loaded = true;
965}
966
967/**
968 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
969 * @vsi: the VSI to be searched
970 * @macaddr: the MAC address
971 * @vlan: the vlan
972 * @is_vf: make sure its a vf filter, else doesn't matter
973 * @is_netdev: make sure its a netdev filter, else doesn't matter
974 *
975 * Returns ptr to the filter object or NULL
976 **/
977static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
978 u8 *macaddr, s16 vlan,
979 bool is_vf, bool is_netdev)
980{
981 struct i40e_mac_filter *f;
982
983 if (!vsi || !macaddr)
984 return NULL;
985
986 list_for_each_entry(f, &vsi->mac_filter_list, list) {
987 if ((ether_addr_equal(macaddr, f->macaddr)) &&
988 (vlan == f->vlan) &&
989 (!is_vf || f->is_vf) &&
990 (!is_netdev || f->is_netdev))
991 return f;
992 }
993 return NULL;
994}
995
996/**
997 * i40e_find_mac - Find a mac addr in the macvlan filters list
998 * @vsi: the VSI to be searched
999 * @macaddr: the MAC address we are searching for
1000 * @is_vf: make sure its a vf filter, else doesn't matter
1001 * @is_netdev: make sure its a netdev filter, else doesn't matter
1002 *
1003 * Returns the first filter with the provided MAC address or NULL if
1004 * MAC address was not found
1005 **/
1006struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1007 bool is_vf, bool is_netdev)
1008{
1009 struct i40e_mac_filter *f;
1010
1011 if (!vsi || !macaddr)
1012 return NULL;
1013
1014 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1015 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1016 (!is_vf || f->is_vf) &&
1017 (!is_netdev || f->is_netdev))
1018 return f;
1019 }
1020 return NULL;
1021}
1022
1023/**
1024 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1025 * @vsi: the VSI to be searched
1026 *
1027 * Returns true if VSI is in vlan mode or false otherwise
1028 **/
1029bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1030{
1031 struct i40e_mac_filter *f;
1032
1033 /* Only -1 for all the filters denotes not in vlan mode
1034 * so we have to go through all the list in order to make sure
1035 */
1036 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1037 if (f->vlan >= 0)
1038 return true;
1039 }
1040
1041 return false;
1042}
1043
1044/**
1045 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1046 * @vsi: the VSI to be searched
1047 * @macaddr: the mac address to be filtered
1048 * @is_vf: true if it is a vf
1049 * @is_netdev: true if it is a netdev
1050 *
1051 * Goes through all the macvlan filters and adds a
1052 * macvlan filter for each unique vlan that already exists
1053 *
1054 * Returns first filter found on success, else NULL
1055 **/
1056struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1057 bool is_vf, bool is_netdev)
1058{
1059 struct i40e_mac_filter *f;
1060
1061 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1062 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1063 is_vf, is_netdev)) {
1064 if (!i40e_add_filter(vsi, macaddr, f->vlan,
1065 is_vf, is_netdev))
1066 return NULL;
1067 }
1068 }
1069
1070 return list_first_entry_or_null(&vsi->mac_filter_list,
1071 struct i40e_mac_filter, list);
1072}
1073
1074/**
1075 * i40e_add_filter - Add a mac/vlan filter to the VSI
1076 * @vsi: the VSI to be searched
1077 * @macaddr: the MAC address
1078 * @vlan: the vlan
1079 * @is_vf: make sure its a vf filter, else doesn't matter
1080 * @is_netdev: make sure its a netdev filter, else doesn't matter
1081 *
1082 * Returns ptr to the filter object or NULL when no memory available.
1083 **/
1084struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1085 u8 *macaddr, s16 vlan,
1086 bool is_vf, bool is_netdev)
1087{
1088 struct i40e_mac_filter *f;
1089
1090 if (!vsi || !macaddr)
1091 return NULL;
1092
1093 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1094 if (!f) {
1095 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1096 if (!f)
1097 goto add_filter_out;
1098
1099 memcpy(f->macaddr, macaddr, ETH_ALEN);
1100 f->vlan = vlan;
1101 f->changed = true;
1102
1103 INIT_LIST_HEAD(&f->list);
1104 list_add(&f->list, &vsi->mac_filter_list);
1105 }
1106
1107 /* increment counter and add a new flag if needed */
1108 if (is_vf) {
1109 if (!f->is_vf) {
1110 f->is_vf = true;
1111 f->counter++;
1112 }
1113 } else if (is_netdev) {
1114 if (!f->is_netdev) {
1115 f->is_netdev = true;
1116 f->counter++;
1117 }
1118 } else {
1119 f->counter++;
1120 }
1121
1122 /* changed tells sync_filters_subtask to
1123 * push the filter down to the firmware
1124 */
1125 if (f->changed) {
1126 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1127 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1128 }
1129
1130add_filter_out:
1131 return f;
1132}
1133
1134/**
1135 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1136 * @vsi: the VSI to be searched
1137 * @macaddr: the MAC address
1138 * @vlan: the vlan
1139 * @is_vf: make sure it's a vf filter, else doesn't matter
1140 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1141 **/
1142void i40e_del_filter(struct i40e_vsi *vsi,
1143 u8 *macaddr, s16 vlan,
1144 bool is_vf, bool is_netdev)
1145{
1146 struct i40e_mac_filter *f;
1147
1148 if (!vsi || !macaddr)
1149 return;
1150
1151 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1152 if (!f || f->counter == 0)
1153 return;
1154
1155 if (is_vf) {
1156 if (f->is_vf) {
1157 f->is_vf = false;
1158 f->counter--;
1159 }
1160 } else if (is_netdev) {
1161 if (f->is_netdev) {
1162 f->is_netdev = false;
1163 f->counter--;
1164 }
1165 } else {
1166 /* make sure we don't remove a filter in use by vf or netdev */
1167 int min_f = 0;
1168 min_f += (f->is_vf ? 1 : 0);
1169 min_f += (f->is_netdev ? 1 : 0);
1170
1171 if (f->counter > min_f)
1172 f->counter--;
1173 }
1174
1175 /* counter == 0 tells sync_filters_subtask to
1176 * remove the filter from the firmware's list
1177 */
1178 if (f->counter == 0) {
1179 f->changed = true;
1180 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1181 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1182 }
1183}
1184
1185/**
1186 * i40e_set_mac - NDO callback to set mac address
1187 * @netdev: network interface device structure
1188 * @p: pointer to an address structure
1189 *
1190 * Returns 0 on success, negative on failure
1191 **/
1192static int i40e_set_mac(struct net_device *netdev, void *p)
1193{
1194 struct i40e_netdev_priv *np = netdev_priv(netdev);
1195 struct i40e_vsi *vsi = np->vsi;
1196 struct sockaddr *addr = p;
1197 struct i40e_mac_filter *f;
1198
1199 if (!is_valid_ether_addr(addr->sa_data))
1200 return -EADDRNOTAVAIL;
1201
1202 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1203
1204 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1205 return 0;
1206
1207 if (vsi->type == I40E_VSI_MAIN) {
1208 i40e_status ret;
1209 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1210 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1211 addr->sa_data, NULL);
1212 if (ret) {
1213 netdev_info(netdev,
1214 "Addr change for Main VSI failed: %d\n",
1215 ret);
1216 return -EADDRNOTAVAIL;
1217 }
1218
1219 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1220 }
1221
1222 /* In order to be sure to not drop any packets, add the new address
1223 * then delete the old one.
1224 */
1225 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1226 if (!f)
1227 return -ENOMEM;
1228
1229 i40e_sync_vsi_filters(vsi);
1230 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1231 i40e_sync_vsi_filters(vsi);
1232
1233 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1234
1235 return 0;
1236}
1237
1238/**
1239 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1240 * @vsi: the VSI being setup
1241 * @ctxt: VSI context structure
1242 * @enabled_tc: Enabled TCs bitmap
1243 * @is_add: True if called before Add VSI
1244 *
1245 * Setup VSI queue mapping for enabled traffic classes.
1246 **/
1247static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1248 struct i40e_vsi_context *ctxt,
1249 u8 enabled_tc,
1250 bool is_add)
1251{
1252 struct i40e_pf *pf = vsi->back;
1253 u16 sections = 0;
1254 u8 netdev_tc = 0;
1255 u16 numtc = 0;
1256 u16 qcount;
1257 u8 offset;
1258 u16 qmap;
1259 int i;
1260
1261 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1262 offset = 0;
1263
1264 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1265 /* Find numtc from enabled TC bitmap */
1266 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1267 if (enabled_tc & (1 << i)) /* TC is enabled */
1268 numtc++;
1269 }
1270 if (!numtc) {
1271 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1272 numtc = 1;
1273 }
1274 } else {
1275 /* At least TC0 is enabled in case of non-DCB case */
1276 numtc = 1;
1277 }
1278
1279 vsi->tc_config.numtc = numtc;
1280 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1281
1282 /* Setup queue offset/count for all TCs for given VSI */
1283 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1284 /* See if the given TC is enabled for the given VSI */
1285 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1286 int pow, num_qps;
1287
1288 vsi->tc_config.tc_info[i].qoffset = offset;
1289 switch (vsi->type) {
1290 case I40E_VSI_MAIN:
1291 if (i == 0)
1292 qcount = pf->rss_size;
1293 else
1294 qcount = pf->num_tc_qps;
1295 vsi->tc_config.tc_info[i].qcount = qcount;
1296 break;
1297 case I40E_VSI_FDIR:
1298 case I40E_VSI_SRIOV:
1299 case I40E_VSI_VMDQ2:
1300 default:
1301 qcount = vsi->alloc_queue_pairs;
1302 vsi->tc_config.tc_info[i].qcount = qcount;
1303 WARN_ON(i != 0);
1304 break;
1305 }
1306
1307 /* find the power-of-2 of the number of queue pairs */
1308 num_qps = vsi->tc_config.tc_info[i].qcount;
1309 pow = 0;
1310 while (num_qps &&
1311 ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
1312 pow++;
1313 num_qps >>= 1;
1314 }
1315
1316 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1317 qmap =
1318 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1319 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1320
1321 offset += vsi->tc_config.tc_info[i].qcount;
1322 } else {
1323 /* TC is not enabled so set the offset to
1324 * default queue and allocate one queue
1325 * for the given TC.
1326 */
1327 vsi->tc_config.tc_info[i].qoffset = 0;
1328 vsi->tc_config.tc_info[i].qcount = 1;
1329 vsi->tc_config.tc_info[i].netdev_tc = 0;
1330
1331 qmap = 0;
1332 }
1333 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1334 }
1335
1336 /* Set actual Tx/Rx queue pairs */
1337 vsi->num_queue_pairs = offset;
1338
1339 /* Scheduler section valid can only be set for ADD VSI */
1340 if (is_add) {
1341 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1342
1343 ctxt->info.up_enable_bits = enabled_tc;
1344 }
1345 if (vsi->type == I40E_VSI_SRIOV) {
1346 ctxt->info.mapping_flags |=
1347 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1348 for (i = 0; i < vsi->num_queue_pairs; i++)
1349 ctxt->info.queue_mapping[i] =
1350 cpu_to_le16(vsi->base_queue + i);
1351 } else {
1352 ctxt->info.mapping_flags |=
1353 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1354 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1355 }
1356 ctxt->info.valid_sections |= cpu_to_le16(sections);
1357}
1358
1359/**
1360 * i40e_set_rx_mode - NDO callback to set the netdev filters
1361 * @netdev: network interface device structure
1362 **/
1363static void i40e_set_rx_mode(struct net_device *netdev)
1364{
1365 struct i40e_netdev_priv *np = netdev_priv(netdev);
1366 struct i40e_mac_filter *f, *ftmp;
1367 struct i40e_vsi *vsi = np->vsi;
1368 struct netdev_hw_addr *uca;
1369 struct netdev_hw_addr *mca;
1370 struct netdev_hw_addr *ha;
1371
1372 /* add addr if not already in the filter list */
1373 netdev_for_each_uc_addr(uca, netdev) {
1374 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1375 if (i40e_is_vsi_in_vlan(vsi))
1376 i40e_put_mac_in_vlan(vsi, uca->addr,
1377 false, true);
1378 else
1379 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1380 false, true);
1381 }
1382 }
1383
1384 netdev_for_each_mc_addr(mca, netdev) {
1385 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1386 if (i40e_is_vsi_in_vlan(vsi))
1387 i40e_put_mac_in_vlan(vsi, mca->addr,
1388 false, true);
1389 else
1390 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1391 false, true);
1392 }
1393 }
1394
1395 /* remove filter if not in netdev list */
1396 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1397 bool found = false;
1398
1399 if (!f->is_netdev)
1400 continue;
1401
1402 if (is_multicast_ether_addr(f->macaddr)) {
1403 netdev_for_each_mc_addr(mca, netdev) {
1404 if (ether_addr_equal(mca->addr, f->macaddr)) {
1405 found = true;
1406 break;
1407 }
1408 }
1409 } else {
1410 netdev_for_each_uc_addr(uca, netdev) {
1411 if (ether_addr_equal(uca->addr, f->macaddr)) {
1412 found = true;
1413 break;
1414 }
1415 }
1416
1417 for_each_dev_addr(netdev, ha) {
1418 if (ether_addr_equal(ha->addr, f->macaddr)) {
1419 found = true;
1420 break;
1421 }
1422 }
1423 }
1424 if (!found)
1425 i40e_del_filter(
1426 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1427 }
1428
1429 /* check for other flag changes */
1430 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1431 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1432 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1433 }
1434}
1435
1436/**
1437 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1438 * @vsi: ptr to the VSI
1439 *
1440 * Push any outstanding VSI filter changes through the AdminQ.
1441 *
1442 * Returns 0 or error value
1443 **/
1444int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1445{
1446 struct i40e_mac_filter *f, *ftmp;
1447 bool promisc_forced_on = false;
1448 bool add_happened = false;
1449 int filter_list_len = 0;
1450 u32 changed_flags = 0;
dcae29be 1451 i40e_status aq_ret = 0;
41c445ff
JB		 1452 struct i40e_pf *pf;
1453 int num_add = 0;
1454 int num_del = 0;
1455 u16 cmd_flags;
1456
1457 /* empty array typed pointers, kcalloc later */
1458 struct i40e_aqc_add_macvlan_element_data *add_list;
1459 struct i40e_aqc_remove_macvlan_element_data *del_list;
1460
1461 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1462 usleep_range(1000, 2000);
1463 pf = vsi->back;
1464
1465 if (vsi->netdev) {
1466 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1467 vsi->current_netdev_flags = vsi->netdev->flags;
1468 }
1469
1470 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1471 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1472
1473 filter_list_len = pf->hw.aq.asq_buf_size /
1474 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1475 del_list = kcalloc(filter_list_len,
1476 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1477 GFP_KERNEL);
1478 if (!del_list)
1479 return -ENOMEM;
1480
1481 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1482 if (!f->changed)
1483 continue;
1484
1485 if (f->counter != 0)
1486 continue;
1487 f->changed = false;
1488 cmd_flags = 0;
1489
1490 /* add to delete list */
1491 memcpy(del_list[num_del].mac_addr,
1492 f->macaddr, ETH_ALEN);
1493 del_list[num_del].vlan_tag =
1494 cpu_to_le16((u16)(f->vlan ==
1495 I40E_VLAN_ANY ? 0 : f->vlan));
1496
1497 /* vlan0 as wild card to allow packets from all vlans */
1498 if (f->vlan == I40E_VLAN_ANY ||
1499 (vsi->netdev && !(vsi->netdev->features &
1500 NETIF_F_HW_VLAN_CTAG_FILTER)))
1501 cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1502 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1503 del_list[num_del].flags = cmd_flags;
1504 num_del++;
1505
1506 /* unlink from filter list */
1507 list_del(&f->list);
1508 kfree(f);
1509
1510 /* flush a full buffer */
1511 if (num_del == filter_list_len) {
dcae29be 1512 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1513 vsi->seid, del_list, num_del,
1514 NULL);
1515 num_del = 0;
1516 memset(del_list, 0, sizeof(*del_list));
1517
dcae29be 1518 if (aq_ret)
41c445ff
JB		 1519 dev_info(&pf->pdev->dev,
1520 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1521 aq_ret,
41c445ff
JB		 1522 pf->hw.aq.asq_last_status);
1523 }
1524 }
1525 if (num_del) {
dcae29be 1526 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1527 del_list, num_del, NULL);
1528 num_del = 0;
1529
dcae29be 1530 if (aq_ret)
41c445ff
JB		 1531 dev_info(&pf->pdev->dev,
1532 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1533 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1534 }
1535
1536 kfree(del_list);
1537 del_list = NULL;
1538
1539 /* do all the adds now */
1540 filter_list_len = pf->hw.aq.asq_buf_size /
1541 sizeof(struct i40e_aqc_add_macvlan_element_data),
1542 add_list = kcalloc(filter_list_len,
1543 sizeof(struct i40e_aqc_add_macvlan_element_data),
1544 GFP_KERNEL);
1545 if (!add_list)
1546 return -ENOMEM;
1547
1548 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1549 if (!f->changed)
1550 continue;
1551
1552 if (f->counter == 0)
1553 continue;
1554 f->changed = false;
1555 add_happened = true;
1556 cmd_flags = 0;
1557
1558 /* add to add array */
1559 memcpy(add_list[num_add].mac_addr,
1560 f->macaddr, ETH_ALEN);
1561 add_list[num_add].vlan_tag =
1562 cpu_to_le16(
1563 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1564 add_list[num_add].queue_number = 0;
1565
1566 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
1567
1568 /* vlan0 as wild card to allow packets from all vlans */
1569 if (f->vlan == I40E_VLAN_ANY || (vsi->netdev &&
1570 !(vsi->netdev->features &
1571 NETIF_F_HW_VLAN_CTAG_FILTER)))
1572 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
1573 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1574 num_add++;
1575
1576 /* flush a full buffer */
1577 if (num_add == filter_list_len) {
dcae29be
JB		 1578 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1579 add_list, num_add,
1580 NULL);
41c445ff
JB		 1581 num_add = 0;
1582
dcae29be 1583 if (aq_ret)
41c445ff
JB		 1584 break;
1585 memset(add_list, 0, sizeof(*add_list));
1586 }
1587 }
1588 if (num_add) {
dcae29be
JB		 1589 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1590 add_list, num_add, NULL);
41c445ff
JB		 1591 num_add = 0;
1592 }
1593 kfree(add_list);
1594 add_list = NULL;
1595
dcae29be 1596 if (add_happened && (!aq_ret)) {
41c445ff 1597 /* do nothing */;
dcae29be 1598 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1599 dev_info(&pf->pdev->dev,
1600 "add filter failed, err %d, aq_err %d\n",
dcae29be 1601 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1602 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1603 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1604 &vsi->state)) {
1605 promisc_forced_on = true;
1606 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1607 &vsi->state);
1608 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1609 }
1610 }
1611 }
1612
1613 /* check for changes in promiscuous modes */
1614 if (changed_flags & IFF_ALLMULTI) {
1615 bool cur_multipromisc;
1616 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1617 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1618 vsi->seid,
1619 cur_multipromisc,
1620 NULL);
1621 if (aq_ret)
41c445ff
JB		 1622 dev_info(&pf->pdev->dev,
1623 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1624 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1625 }
1626 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1627 bool cur_promisc;
1628 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1629 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1630 &vsi->state));
dcae29be
JB		 1631 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1632 vsi->seid,
1633 cur_promisc, NULL);
1634 if (aq_ret)
41c445ff
JB		 1635 dev_info(&pf->pdev->dev,
1636 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1637 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1638 }
1639
1640 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1641 return 0;
1642}
1643
1644/**
1645 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1646 * @pf: board private structure
1647 **/
1648static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1649{
1650 int v;
1651
1652 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1653 return;
1654 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1655
1656 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1657 if (pf->vsi[v] &&
1658 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1659 i40e_sync_vsi_filters(pf->vsi[v]);
1660 }
1661}
1662
1663/**
1664 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1665 * @netdev: network interface device structure
1666 * @new_mtu: new value for maximum frame size
1667 *
1668 * Returns 0 on success, negative on failure
1669 **/
1670static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1671{
1672 struct i40e_netdev_priv *np = netdev_priv(netdev);
1673 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1674 struct i40e_vsi *vsi = np->vsi;
1675
1676 /* MTU < 68 is an error and causes problems on some kernels */
1677 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1678 return -EINVAL;
1679
1680 netdev_info(netdev, "changing MTU from %d to %d\n",
1681 netdev->mtu, new_mtu);
1682 netdev->mtu = new_mtu;
1683 if (netif_running(netdev))
1684 i40e_vsi_reinit_locked(vsi);
1685
1686 return 0;
1687}
1688
1689/**
1690 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1691 * @vsi: the vsi being adjusted
1692 **/
1693void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1694{
1695 struct i40e_vsi_context ctxt;
1696 i40e_status ret;
1697
1698 if ((vsi->info.valid_sections &
1699 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1700 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1701 return; /* already enabled */
1702
1703 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1704 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1705 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1706
1707 ctxt.seid = vsi->seid;
1708 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1709 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1710 if (ret) {
1711 dev_info(&vsi->back->pdev->dev,
1712 "%s: update vsi failed, aq_err=%d\n",
1713 __func__, vsi->back->hw.aq.asq_last_status);
1714 }
1715}
1716
1717/**
1718 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1719 * @vsi: the vsi being adjusted
1720 **/
1721void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1722{
1723 struct i40e_vsi_context ctxt;
1724 i40e_status ret;
1725
1726 if ((vsi->info.valid_sections &
1727 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1728 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1729 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1730 return; /* already disabled */
1731
1732 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1733 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1734 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1735
1736 ctxt.seid = vsi->seid;
1737 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1738 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1739 if (ret) {
1740 dev_info(&vsi->back->pdev->dev,
1741 "%s: update vsi failed, aq_err=%d\n",
1742 __func__, vsi->back->hw.aq.asq_last_status);
1743 }
1744}
1745
1746/**
1747 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1748 * @netdev: network interface to be adjusted
1749 * @features: netdev features to test if VLAN offload is enabled or not
1750 **/
1751static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1752{
1753 struct i40e_netdev_priv *np = netdev_priv(netdev);
1754 struct i40e_vsi *vsi = np->vsi;
1755
1756 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1757 i40e_vlan_stripping_enable(vsi);
1758 else
1759 i40e_vlan_stripping_disable(vsi);
1760}
1761
1762/**
1763 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1764 * @vsi: the vsi being configured
1765 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1766 **/
1767int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1768{
1769 struct i40e_mac_filter *f, *add_f;
1770 bool is_netdev, is_vf;
1771 int ret;
1772
1773 is_vf = (vsi->type == I40E_VSI_SRIOV);
1774 is_netdev = !!(vsi->netdev);
1775
1776 if (is_netdev) {
1777 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1778 is_vf, is_netdev);
1779 if (!add_f) {
1780 dev_info(&vsi->back->pdev->dev,
1781 "Could not add vlan filter %d for %pM\n",
1782 vid, vsi->netdev->dev_addr);
1783 return -ENOMEM;
1784 }
1785 }
1786
1787 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1788 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1789 if (!add_f) {
1790 dev_info(&vsi->back->pdev->dev,
1791 "Could not add vlan filter %d for %pM\n",
1792 vid, f->macaddr);
1793 return -ENOMEM;
1794 }
1795 }
1796
1797 ret = i40e_sync_vsi_filters(vsi);
1798 if (ret) {
1799 dev_info(&vsi->back->pdev->dev,
1800 "Could not sync filters for vid %d\n", vid);
1801 return ret;
1802 }
1803
1804 /* Now if we add a vlan tag, make sure to check if it is the first
1805 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1806 * with 0, so we now accept untagged and specified tagged traffic
1807 * (and not any taged and untagged)
1808 */
1809 if (vid > 0) {
1810 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1811 I40E_VLAN_ANY,
1812 is_vf, is_netdev)) {
1813 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1814 I40E_VLAN_ANY, is_vf, is_netdev);
1815 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1816 is_vf, is_netdev);
1817 if (!add_f) {
1818 dev_info(&vsi->back->pdev->dev,
1819 "Could not add filter 0 for %pM\n",
1820 vsi->netdev->dev_addr);
1821 return -ENOMEM;
1822 }
1823 }
1824
1825 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1826 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1827 is_vf, is_netdev)) {
1828 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1829 is_vf, is_netdev);
1830 add_f = i40e_add_filter(vsi, f->macaddr,
1831 0, is_vf, is_netdev);
1832 if (!add_f) {
1833 dev_info(&vsi->back->pdev->dev,
1834 "Could not add filter 0 for %pM\n",
1835 f->macaddr);
1836 return -ENOMEM;
1837 }
1838 }
1839 }
1840 ret = i40e_sync_vsi_filters(vsi);
1841 }
1842
1843 return ret;
1844}
1845
1846/**
1847 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1848 * @vsi: the vsi being configured
1849 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1850 *
1851 * Return: 0 on success or negative otherwise
41c445ff
JB		 1852 **/
1853int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1854{
1855 struct net_device *netdev = vsi->netdev;
1856 struct i40e_mac_filter *f, *add_f;
1857 bool is_vf, is_netdev;
1858 int filter_count = 0;
1859 int ret;
1860
1861 is_vf = (vsi->type == I40E_VSI_SRIOV);
1862 is_netdev = !!(netdev);
1863
1864 if (is_netdev)
1865 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1866
1867 list_for_each_entry(f, &vsi->mac_filter_list, list)
1868 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1869
1870 ret = i40e_sync_vsi_filters(vsi);
1871 if (ret) {
1872 dev_info(&vsi->back->pdev->dev, "Could not sync filters\n");
1873 return ret;
1874 }
1875
1876 /* go through all the filters for this VSI and if there is only
1877 * vid == 0 it means there are no other filters, so vid 0 must
1878 * be replaced with -1. This signifies that we should from now
1879 * on accept any traffic (with any tag present, or untagged)
1880 */
1881 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1882 if (is_netdev) {
1883 if (f->vlan &&
1884 ether_addr_equal(netdev->dev_addr, f->macaddr))
1885 filter_count++;
1886 }
1887
1888 if (f->vlan)
1889 filter_count++;
1890 }
1891
1892 if (!filter_count && is_netdev) {
1893 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1894 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1895 is_vf, is_netdev);
1896 if (!f) {
1897 dev_info(&vsi->back->pdev->dev,
1898 "Could not add filter %d for %pM\n",
1899 I40E_VLAN_ANY, netdev->dev_addr);
1900 return -ENOMEM;
1901 }
1902 }
1903
1904 if (!filter_count) {
1905 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1906 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1907 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1908 is_vf, is_netdev);
1909 if (!add_f) {
1910 dev_info(&vsi->back->pdev->dev,
1911 "Could not add filter %d for %pM\n",
1912 I40E_VLAN_ANY, f->macaddr);
1913 return -ENOMEM;
1914 }
1915 }
1916 }
1917
1918 return i40e_sync_vsi_filters(vsi);
1919}
1920
1921/**
1922 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1923 * @netdev: network interface to be adjusted
1924 * @vid: vlan id to be added
078b5876
JB		 1925 *
1926 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1927 **/
1928static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1929 __always_unused __be16 proto, u16 vid)
1930{
1931 struct i40e_netdev_priv *np = netdev_priv(netdev);
1932 struct i40e_vsi *vsi = np->vsi;
078b5876 1933 int ret = 0;
41c445ff
JB		 1934
1935 if (vid > 4095)
078b5876
JB		 1936 return -EINVAL;
1937
1938 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1939
41c445ff
JB		 1940 /* If the network stack called us with vid = 0, we should
1941 * indicate to i40e_vsi_add_vlan() that we want to receive
1942 * any traffic (i.e. with any vlan tag, or untagged)
1943 */
1944 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1945
078b5876
JB		 1946 if (!ret && (vid < VLAN_N_VID))
1947 set_bit(vid, vsi->active_vlans);
41c445ff 1948
078b5876 1949 return ret;
41c445ff
JB		 1950}
1951
1952/**
1953 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1954 * @netdev: network interface to be adjusted
1955 * @vid: vlan id to be removed
078b5876
JB		 1956 *
1957 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1958 **/
1959static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1960 __always_unused __be16 proto, u16 vid)
1961{
1962 struct i40e_netdev_priv *np = netdev_priv(netdev);
1963 struct i40e_vsi *vsi = np->vsi;
1964
078b5876
JB		 1965 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1966
41c445ff
JB		 1967 /* return code is ignored as there is nothing a user
1968 * can do about failure to remove and a log message was
078b5876 1969 * already printed from the other function
41c445ff
JB		 1970 */
1971 i40e_vsi_kill_vlan(vsi, vid);
1972
1973 clear_bit(vid, vsi->active_vlans);
078b5876 1974
41c445ff
JB		 1975 return 0;
1976}
1977
1978/**
1979 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
1980 * @vsi: the vsi being brought back up
1981 **/
1982static void i40e_restore_vlan(struct i40e_vsi *vsi)
1983{
1984 u16 vid;
1985
1986 if (!vsi->netdev)
1987 return;
1988
1989 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
1990
1991 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
1992 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
1993 vid);
1994}
1995
1996/**
1997 * i40e_vsi_add_pvid - Add pvid for the VSI
1998 * @vsi: the vsi being adjusted
1999 * @vid: the vlan id to set as a PVID
2000 **/
dcae29be 2001int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2002{
2003 struct i40e_vsi_context ctxt;
dcae29be 2004 i40e_status aq_ret;
41c445ff
JB		 2005
2006 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2007 vsi->info.pvid = cpu_to_le16(vid);
2008 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
2009 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2010
2011 ctxt.seid = vsi->seid;
2012 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2013 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2014 if (aq_ret) {
41c445ff
JB		 2015 dev_info(&vsi->back->pdev->dev,
2016 "%s: update vsi failed, aq_err=%d\n",
2017 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2018 return -ENOENT;
41c445ff
JB		 2019 }
2020
dcae29be 2021 return 0;
41c445ff
JB		 2022}
2023
2024/**
2025 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2026 * @vsi: the vsi being adjusted
2027 *
2028 * Just use the vlan_rx_register() service to put it back to normal
2029 **/
2030void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2031{
2032 vsi->info.pvid = 0;
2033 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2034}
2035
2036/**
2037 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2038 * @vsi: ptr to the VSI
2039 *
2040 * If this function returns with an error, then it's possible one or
2041 * more of the rings is populated (while the rest are not). It is the
2042 * callers duty to clean those orphaned rings.
2043 *
2044 * Return 0 on success, negative on failure
2045 **/
2046static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2047{
2048 int i, err = 0;
2049
2050 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2051 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2052
2053 return err;
2054}
2055
2056/**
2057 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2058 * @vsi: ptr to the VSI
2059 *
2060 * Free VSI's transmit software resources
2061 **/
2062static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2063{
2064 int i;
2065
2066 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2067 if (vsi->tx_rings[i]->desc)
2068 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2069}
2070
2071/**
2072 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2073 * @vsi: ptr to the VSI
2074 *
2075 * If this function returns with an error, then it's possible one or
2076 * more of the rings is populated (while the rest are not). It is the
2077 * callers duty to clean those orphaned rings.
2078 *
2079 * Return 0 on success, negative on failure
2080 **/
2081static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2082{
2083 int i, err = 0;
2084
2085 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2086 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2087 return err;
2088}
2089
2090/**
2091 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2092 * @vsi: ptr to the VSI
2093 *
2094 * Free all receive software resources
2095 **/
2096static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2097{
2098 int i;
2099
2100 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2101 if (vsi->rx_rings[i]->desc)
2102 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2103}
2104
2105/**
2106 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2107 * @ring: The Tx ring to configure
2108 *
2109 * Configure the Tx descriptor ring in the HMC context.
2110 **/
2111static int i40e_configure_tx_ring(struct i40e_ring *ring)
2112{
2113 struct i40e_vsi *vsi = ring->vsi;
2114 u16 pf_q = vsi->base_queue + ring->queue_index;
2115 struct i40e_hw *hw = &vsi->back->hw;
2116 struct i40e_hmc_obj_txq tx_ctx;
2117 i40e_status err = 0;
2118 u32 qtx_ctl = 0;
2119
2120 /* some ATR related tx ring init */
2121 if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
2122 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2123 ring->atr_count = 0;
2124 } else {
2125 ring->atr_sample_rate = 0;
2126 }
2127
2128 /* initialize XPS */
2129 if (ring->q_vector && ring->netdev &&
2130 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2131 netif_set_xps_queue(ring->netdev,
2132 &ring->q_vector->affinity_mask,
2133 ring->queue_index);
2134
2135 /* clear the context structure first */
2136 memset(&tx_ctx, 0, sizeof(tx_ctx));
2137
2138 tx_ctx.new_context = 1;
2139 tx_ctx.base = (ring->dma / 128);
2140 tx_ctx.qlen = ring->count;
2141 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
2142 I40E_FLAG_FDIR_ATR_ENABLED));
2143
2144 /* As part of VSI creation/update, FW allocates certain
2145 * Tx arbitration queue sets for each TC enabled for
2146 * the VSI. The FW returns the handles to these queue
2147 * sets as part of the response buffer to Add VSI,
2148 * Update VSI, etc. AQ commands. It is expected that
2149 * these queue set handles be associated with the Tx
2150 * queues by the driver as part of the TX queue context
2151 * initialization. This has to be done regardless of
2152 * DCB as by default everything is mapped to TC0.
2153 */
2154 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2155 tx_ctx.rdylist_act = 0;
2156
2157 /* clear the context in the HMC */
2158 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2159 if (err) {
2160 dev_info(&vsi->back->pdev->dev,
2161 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2162 ring->queue_index, pf_q, err);
2163 return -ENOMEM;
2164 }
2165
2166 /* set the context in the HMC */
2167 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2168 if (err) {
2169 dev_info(&vsi->back->pdev->dev,
2170 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2171 ring->queue_index, pf_q, err);
2172 return -ENOMEM;
2173 }
2174
2175 /* Now associate this queue with this PCI function */
2176 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2177 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2178 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2179 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2180 i40e_flush(hw);
2181
2182 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2183
2184 /* cache tail off for easier writes later */
2185 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2186
2187 return 0;
2188}
2189
2190/**
2191 * i40e_configure_rx_ring - Configure a receive ring context
2192 * @ring: The Rx ring to configure
2193 *
2194 * Configure the Rx descriptor ring in the HMC context.
2195 **/
2196static int i40e_configure_rx_ring(struct i40e_ring *ring)
2197{
2198 struct i40e_vsi *vsi = ring->vsi;
2199 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2200 u16 pf_q = vsi->base_queue + ring->queue_index;
2201 struct i40e_hw *hw = &vsi->back->hw;
2202 struct i40e_hmc_obj_rxq rx_ctx;
2203 i40e_status err = 0;
2204
2205 ring->state = 0;
2206
2207 /* clear the context structure first */
2208 memset(&rx_ctx, 0, sizeof(rx_ctx));
2209
2210 ring->rx_buf_len = vsi->rx_buf_len;
2211 ring->rx_hdr_len = vsi->rx_hdr_len;
2212
2213 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2214 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2215
2216 rx_ctx.base = (ring->dma / 128);
2217 rx_ctx.qlen = ring->count;
2218
2219 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2220 set_ring_16byte_desc_enabled(ring);
2221 rx_ctx.dsize = 0;
2222 } else {
2223 rx_ctx.dsize = 1;
2224 }
2225
2226 rx_ctx.dtype = vsi->dtype;
2227 if (vsi->dtype) {
2228 set_ring_ps_enabled(ring);
2229 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2230 I40E_RX_SPLIT_IP |
2231 I40E_RX_SPLIT_TCP_UDP |
2232 I40E_RX_SPLIT_SCTP;
2233 } else {
2234 rx_ctx.hsplit_0 = 0;
2235 }
2236
2237 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2238 (chain_len * ring->rx_buf_len));
2239 rx_ctx.tphrdesc_ena = 1;
2240 rx_ctx.tphwdesc_ena = 1;
2241 rx_ctx.tphdata_ena = 1;
2242 rx_ctx.tphhead_ena = 1;
2243 rx_ctx.lrxqthresh = 2;
2244 rx_ctx.crcstrip = 1;
2245 rx_ctx.l2tsel = 1;
2246 rx_ctx.showiv = 1;
2247
2248 /* clear the context in the HMC */
2249 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2250 if (err) {
2251 dev_info(&vsi->back->pdev->dev,
2252 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2253 ring->queue_index, pf_q, err);
2254 return -ENOMEM;
2255 }
2256
2257 /* set the context in the HMC */
2258 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2259 if (err) {
2260 dev_info(&vsi->back->pdev->dev,
2261 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2262 ring->queue_index, pf_q, err);
2263 return -ENOMEM;
2264 }
2265
2266 /* cache tail for quicker writes, and clear the reg before use */
2267 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2268 writel(0, ring->tail);
2269
2270 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2271
2272 return 0;
2273}
2274
2275/**
2276 * i40e_vsi_configure_tx - Configure the VSI for Tx
2277 * @vsi: VSI structure describing this set of rings and resources
2278 *
2279 * Configure the Tx VSI for operation.
2280 **/
2281static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2282{
2283 int err = 0;
2284 u16 i;
2285
9f65e15b
AD		 2286 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2287 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2288
2289 return err;
2290}
2291
2292/**
2293 * i40e_vsi_configure_rx - Configure the VSI for Rx
2294 * @vsi: the VSI being configured
2295 *
2296 * Configure the Rx VSI for operation.
2297 **/
2298static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2299{
2300 int err = 0;
2301 u16 i;
2302
2303 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2304 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2305 + ETH_FCS_LEN + VLAN_HLEN;
2306 else
2307 vsi->max_frame = I40E_RXBUFFER_2048;
2308
2309 /* figure out correct receive buffer length */
2310 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2311 I40E_FLAG_RX_PS_ENABLED)) {
2312 case I40E_FLAG_RX_1BUF_ENABLED:
2313 vsi->rx_hdr_len = 0;
2314 vsi->rx_buf_len = vsi->max_frame;
2315 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2316 break;
2317 case I40E_FLAG_RX_PS_ENABLED:
2318 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2319 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2320 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2321 break;
2322 default:
2323 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2324 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2325 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2326 break;
2327 }
2328
2329 /* round up for the chip's needs */
2330 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2331 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2332 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2333 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2334
2335 /* set up individual rings */
2336 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2337 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2338
2339 return err;
2340}
2341
2342/**
2343 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2344 * @vsi: ptr to the VSI
2345 **/
2346static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2347{
2348 u16 qoffset, qcount;
2349 int i, n;
2350
2351 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2352 return;
2353
2354 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2355 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2356 continue;
2357
2358 qoffset = vsi->tc_config.tc_info[n].qoffset;
2359 qcount = vsi->tc_config.tc_info[n].qcount;
2360 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2361 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2362 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2363 rx_ring->dcb_tc = n;
2364 tx_ring->dcb_tc = n;
2365 }
2366 }
2367}
2368
2369/**
2370 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2371 * @vsi: ptr to the VSI
2372 **/
2373static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2374{
2375 if (vsi->netdev)
2376 i40e_set_rx_mode(vsi->netdev);
2377}
2378
2379/**
2380 * i40e_vsi_configure - Set up the VSI for action
2381 * @vsi: the VSI being configured
2382 **/
2383static int i40e_vsi_configure(struct i40e_vsi *vsi)
2384{
2385 int err;
2386
2387 i40e_set_vsi_rx_mode(vsi);
2388 i40e_restore_vlan(vsi);
2389 i40e_vsi_config_dcb_rings(vsi);
2390 err = i40e_vsi_configure_tx(vsi);
2391 if (!err)
2392 err = i40e_vsi_configure_rx(vsi);
2393
2394 return err;
2395}
2396
2397/**
2398 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2399 * @vsi: the VSI being configured
2400 **/
2401static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2402{
2403 struct i40e_pf *pf = vsi->back;
2404 struct i40e_q_vector *q_vector;
2405 struct i40e_hw *hw = &pf->hw;
2406 u16 vector;
2407 int i, q;
2408 u32 val;
2409 u32 qp;
2410
2411 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2412 * and PFINT_LNKLSTn registers, e.g.:
2413 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2414 */
2415 qp = vsi->base_queue;
2416 vector = vsi->base_vector;
493fb300
AD		 2417 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2418 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2419 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2420 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2421 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2422 q_vector->rx.itr);
2423 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2424 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2425 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2426 q_vector->tx.itr);
2427
2428 /* Linked list for the queuepairs assigned to this vector */
2429 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2430 for (q = 0; q < q_vector->num_ringpairs; q++) {
2431 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2432 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2433 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2434 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2435 (I40E_QUEUE_TYPE_TX
2436 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2437
2438 wr32(hw, I40E_QINT_RQCTL(qp), val);
2439
2440 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2441 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2442 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2443 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2444 (I40E_QUEUE_TYPE_RX
2445 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2446
2447 /* Terminate the linked list */
2448 if (q == (q_vector->num_ringpairs - 1))
2449 val |= (I40E_QUEUE_END_OF_LIST
2450 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2451
2452 wr32(hw, I40E_QINT_TQCTL(qp), val);
2453 qp++;
2454 }
2455 }
2456
2457 i40e_flush(hw);
2458}
2459
2460/**
2461 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2462 * @hw: ptr to the hardware info
2463 **/
2464static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2465{
2466 u32 val;
2467
2468 /* clear things first */
2469 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2470 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2471
2472 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2473 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2474 I40E_PFINT_ICR0_ENA_GRST_MASK |
2475 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2476 I40E_PFINT_ICR0_ENA_GPIO_MASK |
2477 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2478 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2479 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2480 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2481
2482 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2483
2484 /* SW_ITR_IDX = 0, but don't change INTENA */
2485 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK |
2486 I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK);
2487
2488 /* OTHER_ITR_IDX = 0 */
2489 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2490}
2491
2492/**
2493 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2494 * @vsi: the VSI being configured
2495 **/
2496static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2497{
493fb300 2498 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2499 struct i40e_pf *pf = vsi->back;
2500 struct i40e_hw *hw = &pf->hw;
2501 u32 val;
2502
2503 /* set the ITR configuration */
2504 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2505 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2506 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2507 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2508 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2509 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2510
2511 i40e_enable_misc_int_causes(hw);
2512
2513 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2514 wr32(hw, I40E_PFINT_LNKLST0, 0);
2515
2516 /* Associate the queue pair to the vector and enable the q int */
2517 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2518 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2519 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2520
2521 wr32(hw, I40E_QINT_RQCTL(0), val);
2522
2523 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2524 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2525 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2526
2527 wr32(hw, I40E_QINT_TQCTL(0), val);
2528 i40e_flush(hw);
2529}
2530
2531/**
2532 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2533 * @pf: board private structure
2534 **/
116a57d4 2535void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2536{
2537 struct i40e_hw *hw = &pf->hw;
2538 u32 val;
2539
2540 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2541 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2542 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2543
2544 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2545 i40e_flush(hw);
2546}
2547
2548/**
2549 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2550 * @vsi: pointer to a vsi
2551 * @vector: enable a particular Hw Interrupt vector
2552 **/
2553void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2554{
2555 struct i40e_pf *pf = vsi->back;
2556 struct i40e_hw *hw = &pf->hw;
2557 u32 val;
2558
2559 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2560 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2561 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2562 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2563 /* skip the flush */
41c445ff
JB		 2564}
2565
2566/**
2567 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2568 * @irq: interrupt number
2569 * @data: pointer to a q_vector
2570 **/
2571static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2572{
2573 struct i40e_q_vector *q_vector = data;
2574
cd0b6fa6 2575 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2576 return IRQ_HANDLED;
2577
2578 napi_schedule(&q_vector->napi);
2579
2580 return IRQ_HANDLED;
2581}
2582
2583/**
2584 * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
2585 * @irq: interrupt number
2586 * @data: pointer to a q_vector
2587 **/
2588static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
2589{
2590 struct i40e_q_vector *q_vector = data;
2591
cd0b6fa6 2592 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2593 return IRQ_HANDLED;
2594
2595 pr_info("fdir ring cleaning needed\n");
2596
2597 return IRQ_HANDLED;
2598}
2599
2600/**
2601 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2602 * @vsi: the VSI being configured
2603 * @basename: name for the vector
2604 *
2605 * Allocates MSI-X vectors and requests interrupts from the kernel.
2606 **/
2607static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2608{
2609 int q_vectors = vsi->num_q_vectors;
2610 struct i40e_pf *pf = vsi->back;
2611 int base = vsi->base_vector;
2612 int rx_int_idx = 0;
2613 int tx_int_idx = 0;
2614 int vector, err;
2615
2616 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2617 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2618
cd0b6fa6 2619 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2620 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2621 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2622 tx_int_idx++;
cd0b6fa6 2623 } else if (q_vector->rx.ring) {
41c445ff
JB		 2624 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2625 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2626 } else if (q_vector->tx.ring) {
41c445ff
JB		 2627 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2628 "%s-%s-%d", basename, "tx", tx_int_idx++);
2629 } else {
2630 /* skip this unused q_vector */
2631 continue;
2632 }
2633 err = request_irq(pf->msix_entries[base + vector].vector,
2634 vsi->irq_handler,
2635 0,
2636 q_vector->name,
2637 q_vector);
2638 if (err) {
2639 dev_info(&pf->pdev->dev,
2640 "%s: request_irq failed, error: %d\n",
2641 __func__, err);
2642 goto free_queue_irqs;
2643 }
2644 /* assign the mask for this irq */
2645 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2646 &q_vector->affinity_mask);
2647 }
2648
2649 return 0;
2650
2651free_queue_irqs:
2652 while (vector) {
2653 vector--;
2654 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2655 NULL);
2656 free_irq(pf->msix_entries[base + vector].vector,
2657 &(vsi->q_vectors[vector]));
2658 }
2659 return err;
2660}
2661
2662/**
2663 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2664 * @vsi: the VSI being un-configured
2665 **/
2666static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2667{
2668 struct i40e_pf *pf = vsi->back;
2669 struct i40e_hw *hw = &pf->hw;
2670 int base = vsi->base_vector;
2671 int i;
2672
2673 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2674 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2675 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2676 }
2677
2678 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2679 for (i = vsi->base_vector;
2680 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2681 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2682
2683 i40e_flush(hw);
2684 for (i = 0; i < vsi->num_q_vectors; i++)
2685 synchronize_irq(pf->msix_entries[i + base].vector);
2686 } else {
2687 /* Legacy and MSI mode - this stops all interrupt handling */
2688 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2689 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2690 i40e_flush(hw);
2691 synchronize_irq(pf->pdev->irq);
2692 }
2693}
2694
2695/**
2696 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2697 * @vsi: the VSI being configured
2698 **/
2699static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2700{
2701 struct i40e_pf *pf = vsi->back;
2702 int i;
2703
2704 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2705 for (i = vsi->base_vector;
2706 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2707 i40e_irq_dynamic_enable(vsi, i);
2708 } else {
2709 i40e_irq_dynamic_enable_icr0(pf);
2710 }
2711
1022cb6c 2712 i40e_flush(&pf->hw);
41c445ff
JB		 2713 return 0;
2714}
2715
2716/**
2717 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2718 * @pf: board private structure
2719 **/
2720static void i40e_stop_misc_vector(struct i40e_pf *pf)
2721{
2722 /* Disable ICR 0 */
2723 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2724 i40e_flush(&pf->hw);
2725}
2726
2727/**
2728 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2729 * @irq: interrupt number
2730 * @data: pointer to a q_vector
2731 *
2732 * This is the handler used for all MSI/Legacy interrupts, and deals
2733 * with both queue and non-queue interrupts. This is also used in
2734 * MSIX mode to handle the non-queue interrupts.
2735 **/
2736static irqreturn_t i40e_intr(int irq, void *data)
2737{
2738 struct i40e_pf *pf = (struct i40e_pf *)data;
2739 struct i40e_hw *hw = &pf->hw;
2740 u32 icr0, icr0_remaining;
2741 u32 val, ena_mask;
2742
2743 icr0 = rd32(hw, I40E_PFINT_ICR0);
2744
41c445ff
JB		 2745 val = rd32(hw, I40E_PFINT_DYN_CTL0);
2746 val = val | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK;
2747 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2748
116a57d4
SN		 2749 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2750 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
2751 return IRQ_NONE;
2752
41c445ff
JB		 2753 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
2754
cd92e72f
SN		 2755 /* if interrupt but no bits showing, must be SWINT */
2756 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2757 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2758 pf->sw_int_count++;
2759
41c445ff
JB		 2760 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2761 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2762
2763 /* temporarily disable queue cause for NAPI processing */
2764 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2765 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2766 wr32(hw, I40E_QINT_RQCTL(0), qval);
2767
2768 qval = rd32(hw, I40E_QINT_TQCTL(0));
2769 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2770 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2771
2772 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2773 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2774 }
2775
2776 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2777 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2778 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2779 }
2780
2781 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2782 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2783 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2784 }
2785
2786 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2787 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2788 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2789 }
2790
2791 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2792 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2793 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2794 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2795 val = rd32(hw, I40E_GLGEN_RSTAT);
2796 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2797 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2798 if (val == I40E_RESET_CORER)
41c445ff 2799 pf->corer_count++;
d52cf0a9 2800 else if (val == I40E_RESET_GLOBR)
41c445ff 2801 pf->globr_count++;
d52cf0a9 2802 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2803 pf->empr_count++;
2804 }
2805
2806 /* If a critical error is pending we have no choice but to reset the
2807 * device.
2808 * Report and mask out any remaining unexpected interrupts.
2809 */
2810 icr0_remaining = icr0 & ena_mask;
2811 if (icr0_remaining) {
2812 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2813 icr0_remaining);
2814 if ((icr0_remaining & I40E_PFINT_ICR0_HMC_ERR_MASK) ||
2815 (icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
2816 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2817 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2818 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
2819 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2820 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2821 } else {
2822 dev_info(&pf->pdev->dev, "device will be reset\n");
2823 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2824 i40e_service_event_schedule(pf);
2825 }
2826 }
2827 ena_mask &= ~icr0_remaining;
2828 }
2829
2830 /* re-enable interrupt causes */
2831 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2832 if (!test_bit(__I40E_DOWN, &pf->state)) {
2833 i40e_service_event_schedule(pf);
2834 i40e_irq_dynamic_enable_icr0(pf);
2835 }
2836
2837 return IRQ_HANDLED;
2838}
2839
2840/**
cd0b6fa6 2841 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2842 * @vsi: the VSI being configured
2843 * @v_idx: vector index
cd0b6fa6 2844 * @qp_idx: queue pair index
41c445ff 2845 **/
cd0b6fa6 2846static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2847{
493fb300 2848 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2849 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2850 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2851
2852 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2853 tx_ring->next = q_vector->tx.ring;
2854 q_vector->tx.ring = tx_ring;
41c445ff 2855 q_vector->tx.count++;
cd0b6fa6
AD		 2856
2857 rx_ring->q_vector = q_vector;
2858 rx_ring->next = q_vector->rx.ring;
2859 q_vector->rx.ring = rx_ring;
2860 q_vector->rx.count++;
41c445ff
JB		 2861}
2862
2863/**
2864 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
2865 * @vsi: the VSI being configured
2866 *
2867 * This function maps descriptor rings to the queue-specific vectors
2868 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2869 * one vector per queue pair, but on a constrained vector budget, we
2870 * group the queue pairs as "efficiently" as possible.
2871 **/
2872static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
2873{
2874 int qp_remaining = vsi->num_queue_pairs;
2875 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 2876 int num_ringpairs;
41c445ff
JB		 2877 int v_start = 0;
2878 int qp_idx = 0;
2879
2880 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2881 * group them so there are multiple queues per vector.
2882 */
2883 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 2884 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
2885
2886 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
2887
2888 q_vector->num_ringpairs = num_ringpairs;
2889
2890 q_vector->rx.count = 0;
2891 q_vector->tx.count = 0;
2892 q_vector->rx.ring = NULL;
2893 q_vector->tx.ring = NULL;
2894
2895 while (num_ringpairs--) {
2896 map_vector_to_qp(vsi, v_start, qp_idx);
2897 qp_idx++;
2898 qp_remaining--;
41c445ff
JB		 2899 }
2900 }
2901}
2902
2903/**
2904 * i40e_vsi_request_irq - Request IRQ from the OS
2905 * @vsi: the VSI being configured
2906 * @basename: name for the vector
2907 **/
2908static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
2909{
2910 struct i40e_pf *pf = vsi->back;
2911 int err;
2912
2913 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
2914 err = i40e_vsi_request_irq_msix(vsi, basename);
2915 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
2916 err = request_irq(pf->pdev->irq, i40e_intr, 0,
2917 pf->misc_int_name, pf);
2918 else
2919 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
2920 pf->misc_int_name, pf);
2921
2922 if (err)
2923 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
2924
2925 return err;
2926}
2927
2928#ifdef CONFIG_NET_POLL_CONTROLLER
2929/**
2930 * i40e_netpoll - A Polling 'interrupt'handler
2931 * @netdev: network interface device structure
2932 *
2933 * This is used by netconsole to send skbs without having to re-enable
2934 * interrupts. It's not called while the normal interrupt routine is executing.
2935 **/
2936static void i40e_netpoll(struct net_device *netdev)
2937{
2938 struct i40e_netdev_priv *np = netdev_priv(netdev);
2939 struct i40e_vsi *vsi = np->vsi;
2940 struct i40e_pf *pf = vsi->back;
2941 int i;
2942
2943 /* if interface is down do nothing */
2944 if (test_bit(__I40E_DOWN, &vsi->state))
2945 return;
2946
2947 pf->flags |= I40E_FLAG_IN_NETPOLL;
2948 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2949 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 2950 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 2951 } else {
2952 i40e_intr(pf->pdev->irq, netdev);
2953 }
2954 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
2955}
2956#endif
2957
2958/**
2959 * i40e_vsi_control_tx - Start or stop a VSI's rings
2960 * @vsi: the VSI being configured
2961 * @enable: start or stop the rings
2962 **/
2963static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
2964{
2965 struct i40e_pf *pf = vsi->back;
2966 struct i40e_hw *hw = &pf->hw;
2967 int i, j, pf_q;
2968 u32 tx_reg;
2969
2970 pf_q = vsi->base_queue;
2971 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
2972 j = 1000;
2973 do {
2974 usleep_range(1000, 2000);
2975 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
2976 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
2977 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
2978
2979 if (enable) {
2980 /* is STAT set ? */
2981 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) {
2982 dev_info(&pf->pdev->dev,
2983 "Tx %d already enabled\n", i);
2984 continue;
2985 }
2986 } else {
2987 /* is !STAT set ? */
2988 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) {
2989 dev_info(&pf->pdev->dev,
2990 "Tx %d already disabled\n", i);
2991 continue;
2992 }
2993 }
2994
2995 /* turn on/off the queue */
2996 if (enable)
2997 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
2998 I40E_QTX_ENA_QENA_STAT_MASK;
2999 else
3000 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3001
3002 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3003
3004 /* wait for the change to finish */
3005 for (j = 0; j < 10; j++) {
3006 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3007 if (enable) {
3008 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3009 break;
3010 } else {
3011 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3012 break;
3013 }
3014
3015 udelay(10);
3016 }
3017 if (j >= 10) {
3018 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3019 pf_q, (enable ? "en" : "dis"));
3020 return -ETIMEDOUT;
3021 }
3022 }
3023
3024 return 0;
3025}
3026
3027/**
3028 * i40e_vsi_control_rx - Start or stop a VSI's rings
3029 * @vsi: the VSI being configured
3030 * @enable: start or stop the rings
3031 **/
3032static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3033{
3034 struct i40e_pf *pf = vsi->back;
3035 struct i40e_hw *hw = &pf->hw;
3036 int i, j, pf_q;
3037 u32 rx_reg;
3038
3039 pf_q = vsi->base_queue;
3040 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3041 j = 1000;
3042 do {
3043 usleep_range(1000, 2000);
3044 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3045 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3046 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3047
3048 if (enable) {
3049 /* is STAT set ? */
3050 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3051 continue;
3052 } else {
3053 /* is !STAT set ? */
3054 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3055 continue;
3056 }
3057
3058 /* turn on/off the queue */
3059 if (enable)
3060 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3061 I40E_QRX_ENA_QENA_STAT_MASK;
3062 else
3063 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3064 I40E_QRX_ENA_QENA_STAT_MASK);
3065 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3066
3067 /* wait for the change to finish */
3068 for (j = 0; j < 10; j++) {
3069 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3070
3071 if (enable) {
3072 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3073 break;
3074 } else {
3075 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3076 break;
3077 }
3078
3079 udelay(10);
3080 }
3081 if (j >= 10) {
3082 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3083 pf_q, (enable ? "en" : "dis"));
3084 return -ETIMEDOUT;
3085 }
3086 }
3087
3088 return 0;
3089}
3090
3091/**
3092 * i40e_vsi_control_rings - Start or stop a VSI's rings
3093 * @vsi: the VSI being configured
3094 * @enable: start or stop the rings
3095 **/
3096static int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
3097{
3098 int ret;
3099
3100 /* do rx first for enable and last for disable */
3101 if (request) {
3102 ret = i40e_vsi_control_rx(vsi, request);
3103 if (ret)
3104 return ret;
3105 ret = i40e_vsi_control_tx(vsi, request);
3106 } else {
3107 ret = i40e_vsi_control_tx(vsi, request);
3108 if (ret)
3109 return ret;
3110 ret = i40e_vsi_control_rx(vsi, request);
3111 }
3112
3113 return ret;
3114}
3115
3116/**
3117 * i40e_vsi_free_irq - Free the irq association with the OS
3118 * @vsi: the VSI being configured
3119 **/
3120static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3121{
3122 struct i40e_pf *pf = vsi->back;
3123 struct i40e_hw *hw = &pf->hw;
3124 int base = vsi->base_vector;
3125 u32 val, qp;
3126 int i;
3127
3128 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3129 if (!vsi->q_vectors)
3130 return;
3131
3132 for (i = 0; i < vsi->num_q_vectors; i++) {
3133 u16 vector = i + base;
3134
3135 /* free only the irqs that were actually requested */
493fb300 3136 if (vsi->q_vectors[i]->num_ringpairs == 0)
41c445ff
JB		 3137 continue;
3138
3139 /* clear the affinity_mask in the IRQ descriptor */
3140 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3141 NULL);
3142 free_irq(pf->msix_entries[vector].vector,
493fb300 3143 vsi->q_vectors[i]);
41c445ff
JB		 3144
3145 /* Tear down the interrupt queue link list
3146 *
3147 * We know that they come in pairs and always
3148 * the Rx first, then the Tx. To clear the
3149 * link list, stick the EOL value into the
3150 * next_q field of the registers.
3151 */
3152 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3153 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3154 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3155 val |= I40E_QUEUE_END_OF_LIST
3156 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3157 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3158
3159 while (qp != I40E_QUEUE_END_OF_LIST) {
3160 u32 next;
3161
3162 val = rd32(hw, I40E_QINT_RQCTL(qp));
3163
3164 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3165 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3166 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3167 I40E_QINT_RQCTL_INTEVENT_MASK);
3168
3169 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3170 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3171
3172 wr32(hw, I40E_QINT_RQCTL(qp), val);
3173
3174 val = rd32(hw, I40E_QINT_TQCTL(qp));
3175
3176 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3177 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3178
3179 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3180 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3181 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3182 I40E_QINT_TQCTL_INTEVENT_MASK);
3183
3184 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3185 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3186
3187 wr32(hw, I40E_QINT_TQCTL(qp), val);
3188 qp = next;
3189 }
3190 }
3191 } else {
3192 free_irq(pf->pdev->irq, pf);
3193
3194 val = rd32(hw, I40E_PFINT_LNKLST0);
3195 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3196 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3197 val |= I40E_QUEUE_END_OF_LIST
3198 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3199 wr32(hw, I40E_PFINT_LNKLST0, val);
3200
3201 val = rd32(hw, I40E_QINT_RQCTL(qp));
3202 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3203 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3204 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3205 I40E_QINT_RQCTL_INTEVENT_MASK);
3206
3207 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3208 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3209
3210 wr32(hw, I40E_QINT_RQCTL(qp), val);
3211
3212 val = rd32(hw, I40E_QINT_TQCTL(qp));
3213
3214 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3215 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3216 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3217 I40E_QINT_TQCTL_INTEVENT_MASK);
3218
3219 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3220 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3221
3222 wr32(hw, I40E_QINT_TQCTL(qp), val);
3223 }
3224}
3225
493fb300
AD		 3226/**
3227 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3228 * @vsi: the VSI being configured
3229 * @v_idx: Index of vector to be freed
3230 *
3231 * This function frees the memory allocated to the q_vector. In addition if
3232 * NAPI is enabled it will delete any references to the NAPI struct prior
3233 * to freeing the q_vector.
3234 **/
3235static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3236{
3237 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3238 struct i40e_ring *ring;
493fb300
AD		 3239
3240 if (!q_vector)
3241 return;
3242
3243 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3244 i40e_for_each_ring(ring, q_vector->tx)
3245 ring->q_vector = NULL;
3246
3247 i40e_for_each_ring(ring, q_vector->rx)
3248 ring->q_vector = NULL;
493fb300
AD		 3249
3250 /* only VSI w/ an associated netdev is set up w/ NAPI */
3251 if (vsi->netdev)
3252 netif_napi_del(&q_vector->napi);
3253
3254 vsi->q_vectors[v_idx] = NULL;
3255
3256 kfree_rcu(q_vector, rcu);
3257}
3258
41c445ff
JB		 3259/**
3260 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3261 * @vsi: the VSI being un-configured
3262 *
3263 * This frees the memory allocated to the q_vectors and
3264 * deletes references to the NAPI struct.
3265 **/
3266static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3267{
3268 int v_idx;
3269
493fb300
AD		 3270 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3271 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3272}
3273
3274/**
3275 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3276 * @pf: board private structure
3277 **/
3278static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3279{
3280 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3281 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3282 pci_disable_msix(pf->pdev);
3283 kfree(pf->msix_entries);
3284 pf->msix_entries = NULL;
3285 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3286 pci_disable_msi(pf->pdev);
3287 }
3288 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3289}
3290
3291/**
3292 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3293 * @pf: board private structure
3294 *
3295 * We go through and clear interrupt specific resources and reset the structure
3296 * to pre-load conditions
3297 **/
3298static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3299{
3300 int i;
3301
3302 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3303 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3304 if (pf->vsi[i])
3305 i40e_vsi_free_q_vectors(pf->vsi[i]);
3306 i40e_reset_interrupt_capability(pf);
3307}
3308
3309/**
3310 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3311 * @vsi: the VSI being configured
3312 **/
3313static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3314{
3315 int q_idx;
3316
3317 if (!vsi->netdev)
3318 return;
3319
3320 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3321 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3322}
3323
3324/**
3325 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3326 * @vsi: the VSI being configured
3327 **/
3328static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3329{
3330 int q_idx;
3331
3332 if (!vsi->netdev)
3333 return;
3334
3335 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3336 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3337}
3338
3339/**
3340 * i40e_quiesce_vsi - Pause a given VSI
3341 * @vsi: the VSI being paused
3342 **/
3343static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3344{
3345 if (test_bit(__I40E_DOWN, &vsi->state))
3346 return;
3347
3348 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3349 if (vsi->netdev && netif_running(vsi->netdev)) {
3350 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3351 } else {
3352 set_bit(__I40E_DOWN, &vsi->state);
3353 i40e_down(vsi);
3354 }
3355}
3356
3357/**
3358 * i40e_unquiesce_vsi - Resume a given VSI
3359 * @vsi: the VSI being resumed
3360 **/
3361static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3362{
3363 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3364 return;
3365
3366 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3367 if (vsi->netdev && netif_running(vsi->netdev))
3368 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3369 else
3370 i40e_up(vsi); /* this clears the DOWN bit */
3371}
3372
3373/**
3374 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3375 * @pf: the PF
3376 **/
3377static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3378{
3379 int v;
3380
3381 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3382 if (pf->vsi[v])
3383 i40e_quiesce_vsi(pf->vsi[v]);
3384 }
3385}
3386
3387/**
3388 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3389 * @pf: the PF
3390 **/
3391static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3392{
3393 int v;
3394
3395 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3396 if (pf->vsi[v])
3397 i40e_unquiesce_vsi(pf->vsi[v]);
3398 }
3399}
3400
3401/**
3402 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3403 * @dcbcfg: the corresponding DCBx configuration structure
3404 *
3405 * Return the number of TCs from given DCBx configuration
3406 **/
3407static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3408{
078b5876
JB		 3409 u8 num_tc = 0;
3410 int i;
41c445ff
JB		 3411
3412 /* Scan the ETS Config Priority Table to find
3413 * traffic class enabled for a given priority
3414 * and use the traffic class index to get the
3415 * number of traffic classes enabled
3416 */
3417 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3418 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3419 num_tc = dcbcfg->etscfg.prioritytable[i];
3420 }
3421
3422 /* Traffic class index starts from zero so
3423 * increment to return the actual count
3424 */
078b5876 3425 return num_tc + 1;
41c445ff
JB		 3426}
3427
3428/**
3429 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3430 * @dcbcfg: the corresponding DCBx configuration structure
3431 *
3432 * Query the current DCB configuration and return the number of
3433 * traffic classes enabled from the given DCBX config
3434 **/
3435static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3436{
3437 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3438 u8 enabled_tc = 1;
3439 u8 i;
3440
3441 for (i = 0; i < num_tc; i++)
3442 enabled_tc |= 1 << i;
3443
3444 return enabled_tc;
3445}
3446
3447/**
3448 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3449 * @pf: PF being queried
3450 *
3451 * Return number of traffic classes enabled for the given PF
3452 **/
3453static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3454{
3455 struct i40e_hw *hw = &pf->hw;
3456 u8 i, enabled_tc;
3457 u8 num_tc = 0;
3458 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3459
3460 /* If DCB is not enabled then always in single TC */
3461 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3462 return 1;
3463
3464 /* MFP mode return count of enabled TCs for this PF */
3465 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3466 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3467 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3468 if (enabled_tc & (1 << i))
3469 num_tc++;
3470 }
3471 return num_tc;
3472 }
3473
3474 /* SFP mode will be enabled for all TCs on port */
3475 return i40e_dcb_get_num_tc(dcbcfg);
3476}
3477
3478/**
3479 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3480 * @pf: PF being queried
3481 *
3482 * Return a bitmap for first enabled traffic class for this PF.
3483 **/
3484static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3485{
3486 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3487 u8 i = 0;
3488
3489 if (!enabled_tc)
3490 return 0x1; /* TC0 */
3491
3492 /* Find the first enabled TC */
3493 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3494 if (enabled_tc & (1 << i))
3495 break;
3496 }
3497
3498 return 1 << i;
3499}
3500
3501/**
3502 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3503 * @pf: PF being queried
3504 *
3505 * Return a bitmap for enabled traffic classes for this PF.
3506 **/
3507static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3508{
3509 /* If DCB is not enabled for this PF then just return default TC */
3510 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3511 return i40e_pf_get_default_tc(pf);
3512
3513 /* MFP mode will have enabled TCs set by FW */
3514 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3515 return pf->hw.func_caps.enabled_tcmap;
3516
3517 /* SFP mode we want PF to be enabled for all TCs */
3518 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3519}
3520
3521/**
3522 * i40e_vsi_get_bw_info - Query VSI BW Information
3523 * @vsi: the VSI being queried
3524 *
3525 * Returns 0 on success, negative value on failure
3526 **/
3527static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3528{
3529 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3530 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3531 struct i40e_pf *pf = vsi->back;
3532 struct i40e_hw *hw = &pf->hw;
dcae29be 3533 i40e_status aq_ret;
41c445ff 3534 u32 tc_bw_max;
41c445ff
JB		 3535 int i;
3536
3537 /* Get the VSI level BW configuration */
dcae29be
JB		 3538 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3539 if (aq_ret) {
41c445ff
JB		 3540 dev_info(&pf->pdev->dev,
3541 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3542 aq_ret, pf->hw.aq.asq_last_status);
3543 return -EINVAL;
41c445ff
JB		 3544 }
3545
3546 /* Get the VSI level BW configuration per TC */
dcae29be
JB		 3547 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
3548 NULL);
3549 if (aq_ret) {
41c445ff
JB		 3550 dev_info(&pf->pdev->dev,
3551 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3552 aq_ret, pf->hw.aq.asq_last_status);
3553 return -EINVAL;
41c445ff
JB		 3554 }
3555
3556 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3557 dev_info(&pf->pdev->dev,
3558 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3559 bw_config.tc_valid_bits,
3560 bw_ets_config.tc_valid_bits);
3561 /* Still continuing */
3562 }
3563
3564 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3565 vsi->bw_max_quanta = bw_config.max_bw;
3566 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3567 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3568 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3569 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3570 vsi->bw_ets_limit_credits[i] =
3571 le16_to_cpu(bw_ets_config.credits[i]);
3572 /* 3 bits out of 4 for each TC */
3573 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3574 }
078b5876 3575
dcae29be 3576 return 0;
41c445ff
JB		 3577}
3578
3579/**
3580 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3581 * @vsi: the VSI being configured
3582 * @enabled_tc: TC bitmap
3583 * @bw_credits: BW shared credits per TC
3584 *
3585 * Returns 0 on success, negative value on failure
3586 **/
dcae29be 3587static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3588 u8 *bw_share)
3589{
3590 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3591 i40e_status aq_ret;
3592 int i;
41c445ff
JB		 3593
3594 bw_data.tc_valid_bits = enabled_tc;
3595 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3596 bw_data.tc_bw_credits[i] = bw_share[i];
3597
dcae29be
JB		 3598 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3599 NULL);
3600 if (aq_ret) {
41c445ff
JB		 3601 dev_info(&vsi->back->pdev->dev,
3602 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3603 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3604 return -EINVAL;
41c445ff
JB		 3605 }
3606
3607 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3608 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3609
dcae29be 3610 return 0;
41c445ff
JB		 3611}
3612
3613/**
3614 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3615 * @vsi: the VSI being configured
3616 * @enabled_tc: TC map to be enabled
3617 *
3618 **/
3619static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3620{
3621 struct net_device *netdev = vsi->netdev;
3622 struct i40e_pf *pf = vsi->back;
3623 struct i40e_hw *hw = &pf->hw;
3624 u8 netdev_tc = 0;
3625 int i;
3626 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3627
3628 if (!netdev)
3629 return;
3630
3631 if (!enabled_tc) {
3632 netdev_reset_tc(netdev);
3633 return;
3634 }
3635
3636 /* Set up actual enabled TCs on the VSI */
3637 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3638 return;
3639
3640 /* set per TC queues for the VSI */
3641 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3642 /* Only set TC queues for enabled tcs
3643 *
3644 * e.g. For a VSI that has TC0 and TC3 enabled the
3645 * enabled_tc bitmap would be 0x00001001; the driver
3646 * will set the numtc for netdev as 2 that will be
3647 * referenced by the netdev layer as TC 0 and 1.
3648 */
3649 if (vsi->tc_config.enabled_tc & (1 << i))
3650 netdev_set_tc_queue(netdev,
3651 vsi->tc_config.tc_info[i].netdev_tc,
3652 vsi->tc_config.tc_info[i].qcount,
3653 vsi->tc_config.tc_info[i].qoffset);
3654 }
3655
3656 /* Assign UP2TC map for the VSI */
3657 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3658 /* Get the actual TC# for the UP */
3659 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3660 /* Get the mapped netdev TC# for the UP */
3661 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3662 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3663 }
3664}
3665
3666/**
3667 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3668 * @vsi: the VSI being configured
3669 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3670 **/
3671static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3672 struct i40e_vsi_context *ctxt)
3673{
3674 /* copy just the sections touched not the entire info
3675 * since not all sections are valid as returned by
3676 * update vsi params
3677 */
3678 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3679 memcpy(&vsi->info.queue_mapping,
3680 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3681 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3682 sizeof(vsi->info.tc_mapping));
3683}
3684
3685/**
3686 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3687 * @vsi: VSI to be configured
3688 * @enabled_tc: TC bitmap
3689 *
3690 * This configures a particular VSI for TCs that are mapped to the
3691 * given TC bitmap. It uses default bandwidth share for TCs across
3692 * VSIs to configure TC for a particular VSI.
3693 *
3694 * NOTE:
3695 * It is expected that the VSI queues have been quisced before calling
3696 * this function.
3697 **/
3698static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3699{
3700 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3701 struct i40e_vsi_context ctxt;
3702 int ret = 0;
3703 int i;
3704
3705 /* Check if enabled_tc is same as existing or new TCs */
3706 if (vsi->tc_config.enabled_tc == enabled_tc)
3707 return ret;
3708
3709 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3710 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3711 if (enabled_tc & (1 << i))
3712 bw_share[i] = 1;
3713 }
3714
3715 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3716 if (ret) {
3717 dev_info(&vsi->back->pdev->dev,
3718 "Failed configuring TC map %d for VSI %d\n",
3719 enabled_tc, vsi->seid);
3720 goto out;
3721 }
3722
3723 /* Update Queue Pairs Mapping for currently enabled UPs */
3724 ctxt.seid = vsi->seid;
3725 ctxt.pf_num = vsi->back->hw.pf_id;
3726 ctxt.vf_num = 0;
3727 ctxt.uplink_seid = vsi->uplink_seid;
3728 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3729 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3730
3731 /* Update the VSI after updating the VSI queue-mapping information */
3732 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3733 if (ret) {
3734 dev_info(&vsi->back->pdev->dev,
3735 "update vsi failed, aq_err=%d\n",
3736 vsi->back->hw.aq.asq_last_status);
3737 goto out;
3738 }
3739 /* update the local VSI info with updated queue map */
3740 i40e_vsi_update_queue_map(vsi, &ctxt);
3741 vsi->info.valid_sections = 0;
3742
3743 /* Update current VSI BW information */
3744 ret = i40e_vsi_get_bw_info(vsi);
3745 if (ret) {
3746 dev_info(&vsi->back->pdev->dev,
3747 "Failed updating vsi bw info, aq_err=%d\n",
3748 vsi->back->hw.aq.asq_last_status);
3749 goto out;
3750 }
3751
3752 /* Update the netdev TC setup */
3753 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3754out:
3755 return ret;
3756}
3757
3758/**
3759 * i40e_up_complete - Finish the last steps of bringing up a connection
3760 * @vsi: the VSI being configured
3761 **/
3762static int i40e_up_complete(struct i40e_vsi *vsi)
3763{
3764 struct i40e_pf *pf = vsi->back;
3765 int err;
3766
3767 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3768 i40e_vsi_configure_msix(vsi);
3769 else
3770 i40e_configure_msi_and_legacy(vsi);
3771
3772 /* start rings */
3773 err = i40e_vsi_control_rings(vsi, true);
3774 if (err)
3775 return err;
3776
3777 clear_bit(__I40E_DOWN, &vsi->state);
3778 i40e_napi_enable_all(vsi);
3779 i40e_vsi_enable_irq(vsi);
3780
3781 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
3782 (vsi->netdev)) {
6d779b41 3783 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 3784 netif_tx_start_all_queues(vsi->netdev);
3785 netif_carrier_on(vsi->netdev);
6d779b41
AS		 3786 } else if (vsi->netdev) {
3787 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 3788 }
3789 i40e_service_event_schedule(pf);
3790
3791 return 0;
3792}
3793
3794/**
3795 * i40e_vsi_reinit_locked - Reset the VSI
3796 * @vsi: the VSI being configured
3797 *
3798 * Rebuild the ring structs after some configuration
3799 * has changed, e.g. MTU size.
3800 **/
3801static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
3802{
3803 struct i40e_pf *pf = vsi->back;
3804
3805 WARN_ON(in_interrupt());
3806 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
3807 usleep_range(1000, 2000);
3808 i40e_down(vsi);
3809
3810 /* Give a VF some time to respond to the reset. The
3811 * two second wait is based upon the watchdog cycle in
3812 * the VF driver.
3813 */
3814 if (vsi->type == I40E_VSI_SRIOV)
3815 msleep(2000);
3816 i40e_up(vsi);
3817 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
3818}
3819
3820/**
3821 * i40e_up - Bring the connection back up after being down
3822 * @vsi: the VSI being configured
3823 **/
3824int i40e_up(struct i40e_vsi *vsi)
3825{
3826 int err;
3827
3828 err = i40e_vsi_configure(vsi);
3829 if (!err)
3830 err = i40e_up_complete(vsi);
3831
3832 return err;
3833}
3834
3835/**
3836 * i40e_down - Shutdown the connection processing
3837 * @vsi: the VSI being stopped
3838 **/
3839void i40e_down(struct i40e_vsi *vsi)
3840{
3841 int i;
3842
3843 /* It is assumed that the caller of this function
3844 * sets the vsi->state __I40E_DOWN bit.
3845 */
3846 if (vsi->netdev) {
3847 netif_carrier_off(vsi->netdev);
3848 netif_tx_disable(vsi->netdev);
3849 }
3850 i40e_vsi_disable_irq(vsi);
3851 i40e_vsi_control_rings(vsi, false);
3852 i40e_napi_disable_all(vsi);
3853
3854 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3855 i40e_clean_tx_ring(vsi->tx_rings[i]);
3856 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3857 }
3858}
3859
3860/**
3861 * i40e_setup_tc - configure multiple traffic classes
3862 * @netdev: net device to configure
3863 * @tc: number of traffic classes to enable
3864 **/
3865static int i40e_setup_tc(struct net_device *netdev, u8 tc)
3866{
3867 struct i40e_netdev_priv *np = netdev_priv(netdev);
3868 struct i40e_vsi *vsi = np->vsi;
3869 struct i40e_pf *pf = vsi->back;
3870 u8 enabled_tc = 0;
3871 int ret = -EINVAL;
3872 int i;
3873
3874 /* Check if DCB enabled to continue */
3875 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
3876 netdev_info(netdev, "DCB is not enabled for adapter\n");
3877 goto exit;
3878 }
3879
3880 /* Check if MFP enabled */
3881 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3882 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
3883 goto exit;
3884 }
3885
3886 /* Check whether tc count is within enabled limit */
3887 if (tc > i40e_pf_get_num_tc(pf)) {
3888 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
3889 goto exit;
3890 }
3891
3892 /* Generate TC map for number of tc requested */
3893 for (i = 0; i < tc; i++)
3894 enabled_tc |= (1 << i);
3895
3896 /* Requesting same TC configuration as already enabled */
3897 if (enabled_tc == vsi->tc_config.enabled_tc)
3898 return 0;
3899
3900 /* Quiesce VSI queues */
3901 i40e_quiesce_vsi(vsi);
3902
3903 /* Configure VSI for enabled TCs */
3904 ret = i40e_vsi_config_tc(vsi, enabled_tc);
3905 if (ret) {
3906 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
3907 vsi->seid);
3908 goto exit;
3909 }
3910
3911 /* Unquiesce VSI */
3912 i40e_unquiesce_vsi(vsi);
3913
3914exit:
3915 return ret;
3916}
3917
3918/**
3919 * i40e_open - Called when a network interface is made active
3920 * @netdev: network interface device structure
3921 *
3922 * The open entry point is called when a network interface is made
3923 * active by the system (IFF_UP). At this point all resources needed
3924 * for transmit and receive operations are allocated, the interrupt
3925 * handler is registered with the OS, the netdev watchdog subtask is
3926 * enabled, and the stack is notified that the interface is ready.
3927 *
3928 * Returns 0 on success, negative value on failure
3929 **/
3930static int i40e_open(struct net_device *netdev)
3931{
3932 struct i40e_netdev_priv *np = netdev_priv(netdev);
3933 struct i40e_vsi *vsi = np->vsi;
3934 struct i40e_pf *pf = vsi->back;
3935 char int_name[IFNAMSIZ];
3936 int err;
3937
3938 /* disallow open during test */
3939 if (test_bit(__I40E_TESTING, &pf->state))
3940 return -EBUSY;
3941
3942 netif_carrier_off(netdev);
3943
3944 /* allocate descriptors */
3945 err = i40e_vsi_setup_tx_resources(vsi);
3946 if (err)
3947 goto err_setup_tx;
3948 err = i40e_vsi_setup_rx_resources(vsi);
3949 if (err)
3950 goto err_setup_rx;
3951
3952 err = i40e_vsi_configure(vsi);
3953 if (err)
3954 goto err_setup_rx;
3955
3956 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
3957 dev_driver_string(&pf->pdev->dev), netdev->name);
3958 err = i40e_vsi_request_irq(vsi, int_name);
3959 if (err)
3960 goto err_setup_rx;
3961
3962 err = i40e_up_complete(vsi);
3963 if (err)
3964 goto err_up_complete;
3965
3966 if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
3967 err = i40e_aq_set_vsi_broadcast(&pf->hw, vsi->seid, true, NULL);
3968 if (err)
3969 netdev_info(netdev,
3970 "couldn't set broadcast err %d aq_err %d\n",
3971 err, pf->hw.aq.asq_last_status);
3972 }
3973
3974 return 0;
3975
3976err_up_complete:
3977 i40e_down(vsi);
3978 i40e_vsi_free_irq(vsi);
3979err_setup_rx:
3980 i40e_vsi_free_rx_resources(vsi);
3981err_setup_tx:
3982 i40e_vsi_free_tx_resources(vsi);
3983 if (vsi == pf->vsi[pf->lan_vsi])
3984 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
3985
3986 return err;
3987}
3988
3989/**
3990 * i40e_close - Disables a network interface
3991 * @netdev: network interface device structure
3992 *
3993 * The close entry point is called when an interface is de-activated
3994 * by the OS. The hardware is still under the driver's control, but
3995 * this netdev interface is disabled.
3996 *
3997 * Returns 0, this is not allowed to fail
3998 **/
3999static int i40e_close(struct net_device *netdev)
4000{
4001 struct i40e_netdev_priv *np = netdev_priv(netdev);
4002 struct i40e_vsi *vsi = np->vsi;
4003
4004 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4005 return 0;
4006
4007 i40e_down(vsi);
4008 i40e_vsi_free_irq(vsi);
4009
4010 i40e_vsi_free_tx_resources(vsi);
4011 i40e_vsi_free_rx_resources(vsi);
4012
4013 return 0;
4014}
4015
4016/**
4017 * i40e_do_reset - Start a PF or Core Reset sequence
4018 * @pf: board private structure
4019 * @reset_flags: which reset is requested
4020 *
4021 * The essential difference in resets is that the PF Reset
4022 * doesn't clear the packet buffers, doesn't reset the PE
4023 * firmware, and doesn't bother the other PFs on the chip.
4024 **/
4025void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4026{
4027 u32 val;
4028
4029 WARN_ON(in_interrupt());
4030
4031 /* do the biggest reset indicated */
4032 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4033
4034 /* Request a Global Reset
4035 *
4036 * This will start the chip's countdown to the actual full
4037 * chip reset event, and a warning interrupt to be sent
4038 * to all PFs, including the requestor. Our handler
4039 * for the warning interrupt will deal with the shutdown
4040 * and recovery of the switch setup.
4041 */
4042 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4043 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4044 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4045 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4046
4047 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4048
4049 /* Request a Core Reset
4050 *
4051 * Same as Global Reset, except does *not* include the MAC/PHY
4052 */
4053 dev_info(&pf->pdev->dev, "CoreR requested\n");
4054 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4055 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4056 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4057 i40e_flush(&pf->hw);
4058
7823fe34
SN		 4059 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4060
4061 /* Request a Firmware Reset
4062 *
4063 * Same as Global reset, plus restarting the
4064 * embedded firmware engine.
4065 */
4066 /* enable EMP Reset */
4067 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4068 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4069 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4070
4071 /* force the reset */
4072 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4073 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4074 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4075 i40e_flush(&pf->hw);
4076
41c445ff
JB		 4077 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4078
4079 /* Request a PF Reset
4080 *
4081 * Resets only the PF-specific registers
4082 *
4083 * This goes directly to the tear-down and rebuild of
4084 * the switch, since we need to do all the recovery as
4085 * for the Core Reset.
4086 */
4087 dev_info(&pf->pdev->dev, "PFR requested\n");
4088 i40e_handle_reset_warning(pf);
4089
4090 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4091 int v;
4092
4093 /* Find the VSI(s) that requested a re-init */
4094 dev_info(&pf->pdev->dev,
4095 "VSI reinit requested\n");
4096 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4097 struct i40e_vsi *vsi = pf->vsi[v];
4098 if (vsi != NULL &&
4099 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4100 i40e_vsi_reinit_locked(pf->vsi[v]);
4101 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4102 }
4103 }
4104
4105 /* no further action needed, so return now */
4106 return;
4107 } else {
4108 dev_info(&pf->pdev->dev,
4109 "bad reset request 0x%08x\n", reset_flags);
4110 return;
4111 }
4112}
4113
4114/**
4115 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4116 * @pf: board private structure
4117 * @e: event info posted on ARQ
4118 *
4119 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4120 * and VF queues
4121 **/
4122static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4123 struct i40e_arq_event_info *e)
4124{
4125 struct i40e_aqc_lan_overflow *data =
4126 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4127 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4128 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4129 struct i40e_hw *hw = &pf->hw;
4130 struct i40e_vf *vf;
4131 u16 vf_id;
4132
4133 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4134 __func__, queue, qtx_ctl);
4135
4136 /* Queue belongs to VF, find the VF and issue VF reset */
4137 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4138 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4139 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4140 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4141 vf_id -= hw->func_caps.vf_base_id;
4142 vf = &pf->vf[vf_id];
4143 i40e_vc_notify_vf_reset(vf);
4144 /* Allow VF to process pending reset notification */
4145 msleep(20);
4146 i40e_reset_vf(vf, false);
4147 }
4148}
4149
4150/**
4151 * i40e_service_event_complete - Finish up the service event
4152 * @pf: board private structure
4153 **/
4154static void i40e_service_event_complete(struct i40e_pf *pf)
4155{
4156 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4157
4158 /* flush memory to make sure state is correct before next watchog */
4159 smp_mb__before_clear_bit();
4160 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4161}
4162
4163/**
4164 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4165 * @pf: board private structure
4166 **/
4167static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4168{
4169 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4170 return;
4171
4172 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4173
4174 /* if interface is down do nothing */
4175 if (test_bit(__I40E_DOWN, &pf->state))
4176 return;
4177}
4178
4179/**
4180 * i40e_vsi_link_event - notify VSI of a link event
4181 * @vsi: vsi to be notified
4182 * @link_up: link up or down
4183 **/
4184static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4185{
4186 if (!vsi)
4187 return;
4188
4189 switch (vsi->type) {
4190 case I40E_VSI_MAIN:
4191 if (!vsi->netdev || !vsi->netdev_registered)
4192 break;
4193
4194 if (link_up) {
4195 netif_carrier_on(vsi->netdev);
4196 netif_tx_wake_all_queues(vsi->netdev);
4197 } else {
4198 netif_carrier_off(vsi->netdev);
4199 netif_tx_stop_all_queues(vsi->netdev);
4200 }
4201 break;
4202
4203 case I40E_VSI_SRIOV:
4204 break;
4205
4206 case I40E_VSI_VMDQ2:
4207 case I40E_VSI_CTRL:
4208 case I40E_VSI_MIRROR:
4209 default:
4210 /* there is no notification for other VSIs */
4211 break;
4212 }
4213}
4214
4215/**
4216 * i40e_veb_link_event - notify elements on the veb of a link event
4217 * @veb: veb to be notified
4218 * @link_up: link up or down
4219 **/
4220static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4221{
4222 struct i40e_pf *pf;
4223 int i;
4224
4225 if (!veb || !veb->pf)
4226 return;
4227 pf = veb->pf;
4228
4229 /* depth first... */
4230 for (i = 0; i < I40E_MAX_VEB; i++)
4231 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4232 i40e_veb_link_event(pf->veb[i], link_up);
4233
4234 /* ... now the local VSIs */
4235 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4236 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4237 i40e_vsi_link_event(pf->vsi[i], link_up);
4238}
4239
4240/**
4241 * i40e_link_event - Update netif_carrier status
4242 * @pf: board private structure
4243 **/
4244static void i40e_link_event(struct i40e_pf *pf)
4245{
4246 bool new_link, old_link;
4247
4248 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4249 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4250
4251 if (new_link == old_link)
4252 return;
4253
6d779b41
AS		 4254 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4255 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4256 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4257
4258 /* Notify the base of the switch tree connected to
4259 * the link. Floating VEBs are not notified.
4260 */
4261 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4262 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4263 else
4264 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4265
4266 if (pf->vf)
4267 i40e_vc_notify_link_state(pf);
4268}
4269
4270/**
4271 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4272 * @pf: board private structure
4273 *
4274 * Set the per-queue flags to request a check for stuck queues in the irq
4275 * clean functions, then force interrupts to be sure the irq clean is called.
4276 **/
4277static void i40e_check_hang_subtask(struct i40e_pf *pf)
4278{
4279 int i, v;
4280
4281 /* If we're down or resetting, just bail */
4282 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4283 return;
4284
4285 /* for each VSI/netdev
4286 * for each Tx queue
4287 * set the check flag
4288 * for each q_vector
4289 * force an interrupt
4290 */
4291 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4292 struct i40e_vsi *vsi = pf->vsi[v];
4293 int armed = 0;
4294
4295 if (!pf->vsi[v] ||
4296 test_bit(__I40E_DOWN, &vsi->state) ||
4297 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4298 continue;
4299
4300 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4301 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4302 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4303 &vsi->tx_rings[i]->state))
41c445ff
JB		 4304 armed++;
4305 }
4306
4307 if (armed) {
4308 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4309 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4310 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4311 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4312 } else {
4313 u16 vec = vsi->base_vector - 1;
4314 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4315 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4316 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4317 wr32(&vsi->back->hw,
4318 I40E_PFINT_DYN_CTLN(vec), val);
4319 }
4320 i40e_flush(&vsi->back->hw);
4321 }
4322 }
4323}
4324
4325/**
4326 * i40e_watchdog_subtask - Check and bring link up
4327 * @pf: board private structure
4328 **/
4329static void i40e_watchdog_subtask(struct i40e_pf *pf)
4330{
4331 int i;
4332
4333 /* if interface is down do nothing */
4334 if (test_bit(__I40E_DOWN, &pf->state) ||
4335 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4336 return;
4337
4338 /* Update the stats for active netdevs so the network stack
4339 * can look at updated numbers whenever it cares to
4340 */
4341 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4342 if (pf->vsi[i] && pf->vsi[i]->netdev)
4343 i40e_update_stats(pf->vsi[i]);
4344
4345 /* Update the stats for the active switching components */
4346 for (i = 0; i < I40E_MAX_VEB; i++)
4347 if (pf->veb[i])
4348 i40e_update_veb_stats(pf->veb[i]);
4349}
4350
4351/**
4352 * i40e_reset_subtask - Set up for resetting the device and driver
4353 * @pf: board private structure
4354 **/
4355static void i40e_reset_subtask(struct i40e_pf *pf)
4356{
4357 u32 reset_flags = 0;
4358
4359 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4360 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4361 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4362 }
4363 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4364 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4365 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4366 }
4367 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4368 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4369 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4370 }
4371 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4372 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4373 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4374 }
4375
4376 /* If there's a recovery already waiting, it takes
4377 * precedence before starting a new reset sequence.
4378 */
4379 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4380 i40e_handle_reset_warning(pf);
4381 return;
4382 }
4383
4384 /* If we're already down or resetting, just bail */
4385 if (reset_flags &&
4386 !test_bit(__I40E_DOWN, &pf->state) &&
4387 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4388 i40e_do_reset(pf, reset_flags);
4389}
4390
4391/**
4392 * i40e_handle_link_event - Handle link event
4393 * @pf: board private structure
4394 * @e: event info posted on ARQ
4395 **/
4396static void i40e_handle_link_event(struct i40e_pf *pf,
4397 struct i40e_arq_event_info *e)
4398{
4399 struct i40e_hw *hw = &pf->hw;
4400 struct i40e_aqc_get_link_status *status =
4401 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4402 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4403
4404 /* save off old link status information */
4405 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4406 sizeof(pf->hw.phy.link_info_old));
4407
4408 /* update link status */
4409 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4410 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4411 hw_link_info->link_info = status->link_info;
4412 hw_link_info->an_info = status->an_info;
4413 hw_link_info->ext_info = status->ext_info;
4414 hw_link_info->lse_enable =
4415 le16_to_cpu(status->command_flags) &
4416 I40E_AQ_LSE_ENABLE;
4417
4418 /* process the event */
4419 i40e_link_event(pf);
4420
4421 /* Do a new status request to re-enable LSE reporting
4422 * and load new status information into the hw struct,
4423 * then see if the status changed while processing the
4424 * initial event.
4425 */
4426 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4427 i40e_link_event(pf);
4428}
4429
4430/**
4431 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4432 * @pf: board private structure
4433 **/
4434static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4435{
4436 struct i40e_arq_event_info event;
4437 struct i40e_hw *hw = &pf->hw;
4438 u16 pending, i = 0;
4439 i40e_status ret;
4440 u16 opcode;
4441 u32 val;
4442
4443 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4444 return;
4445
4446 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
4447 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4448 if (!event.msg_buf)
4449 return;
4450
4451 do {
4452 ret = i40e_clean_arq_element(hw, &event, &pending);
4453 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4454 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4455 break;
4456 } else if (ret) {
4457 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4458 break;
4459 }
4460
4461 opcode = le16_to_cpu(event.desc.opcode);
4462 switch (opcode) {
4463
4464 case i40e_aqc_opc_get_link_status:
4465 i40e_handle_link_event(pf, &event);
4466 break;
4467 case i40e_aqc_opc_send_msg_to_pf:
4468 ret = i40e_vc_process_vf_msg(pf,
4469 le16_to_cpu(event.desc.retval),
4470 le32_to_cpu(event.desc.cookie_high),
4471 le32_to_cpu(event.desc.cookie_low),
4472 event.msg_buf,
4473 event.msg_size);
4474 break;
4475 case i40e_aqc_opc_lldp_update_mib:
4476 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4477 break;
4478 case i40e_aqc_opc_event_lan_overflow:
4479 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4480 i40e_handle_lan_overflow_event(pf, &event);
4481 break;
4482 default:
4483 dev_info(&pf->pdev->dev,
4484 "ARQ Error: Unknown event %d received\n",
4485 event.desc.opcode);
4486 break;
4487 }
4488 } while (pending && (i++ < pf->adminq_work_limit));
4489
4490 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4491 /* re-enable Admin queue interrupt cause */
4492 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4493 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4494 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4495 i40e_flush(hw);
4496
4497 kfree(event.msg_buf);
4498}
4499
4500/**
4501 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4502 * @veb: pointer to the VEB instance
4503 *
4504 * This is a recursive function that first builds the attached VSIs then
4505 * recurses in to build the next layer of VEB. We track the connections
4506 * through our own index numbers because the seid's from the HW could
4507 * change across the reset.
4508 **/
4509static int i40e_reconstitute_veb(struct i40e_veb *veb)
4510{
4511 struct i40e_vsi *ctl_vsi = NULL;
4512 struct i40e_pf *pf = veb->pf;
4513 int v, veb_idx;
4514 int ret;
4515
4516 /* build VSI that owns this VEB, temporarily attached to base VEB */
4517 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4518 if (pf->vsi[v] &&
4519 pf->vsi[v]->veb_idx == veb->idx &&
4520 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4521 ctl_vsi = pf->vsi[v];
4522 break;
4523 }
4524 }
4525 if (!ctl_vsi) {
4526 dev_info(&pf->pdev->dev,
4527 "missing owner VSI for veb_idx %d\n", veb->idx);
4528 ret = -ENOENT;
4529 goto end_reconstitute;
4530 }
4531 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4532 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4533 ret = i40e_add_vsi(ctl_vsi);
4534 if (ret) {
4535 dev_info(&pf->pdev->dev,
4536 "rebuild of owner VSI failed: %d\n", ret);
4537 goto end_reconstitute;
4538 }
4539 i40e_vsi_reset_stats(ctl_vsi);
4540
4541 /* create the VEB in the switch and move the VSI onto the VEB */
4542 ret = i40e_add_veb(veb, ctl_vsi);
4543 if (ret)
4544 goto end_reconstitute;
4545
4546 /* create the remaining VSIs attached to this VEB */
4547 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4548 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4549 continue;
4550
4551 if (pf->vsi[v]->veb_idx == veb->idx) {
4552 struct i40e_vsi *vsi = pf->vsi[v];
4553 vsi->uplink_seid = veb->seid;
4554 ret = i40e_add_vsi(vsi);
4555 if (ret) {
4556 dev_info(&pf->pdev->dev,
4557 "rebuild of vsi_idx %d failed: %d\n",
4558 v, ret);
4559 goto end_reconstitute;
4560 }
4561 i40e_vsi_reset_stats(vsi);
4562 }
4563 }
4564
4565 /* create any VEBs attached to this VEB - RECURSION */
4566 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
4567 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
4568 pf->veb[veb_idx]->uplink_seid = veb->seid;
4569 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
4570 if (ret)
4571 break;
4572 }
4573 }
4574
4575end_reconstitute:
4576 return ret;
4577}
4578
4579/**
4580 * i40e_get_capabilities - get info about the HW
4581 * @pf: the PF struct
4582 **/
4583static int i40e_get_capabilities(struct i40e_pf *pf)
4584{
4585 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
4586 u16 data_size;
4587 int buf_len;
4588 int err;
4589
4590 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
4591 do {
4592 cap_buf = kzalloc(buf_len, GFP_KERNEL);
4593 if (!cap_buf)
4594 return -ENOMEM;
4595
4596 /* this loads the data into the hw struct for us */
4597 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
4598 &data_size,
4599 i40e_aqc_opc_list_func_capabilities,
4600 NULL);
4601 /* data loaded, buffer no longer needed */
4602 kfree(cap_buf);
4603
4604 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
4605 /* retry with a larger buffer */
4606 buf_len = data_size;
4607 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
4608 dev_info(&pf->pdev->dev,
4609 "capability discovery failed: aq=%d\n",
4610 pf->hw.aq.asq_last_status);
4611 return -ENODEV;
4612 }
4613 } while (err);
4614
4615 if (pf->hw.debug_mask & I40E_DEBUG_USER)
4616 dev_info(&pf->pdev->dev,
4617 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
4618 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
4619 pf->hw.func_caps.num_msix_vectors,
4620 pf->hw.func_caps.num_msix_vectors_vf,
4621 pf->hw.func_caps.fd_filters_guaranteed,
4622 pf->hw.func_caps.fd_filters_best_effort,
4623 pf->hw.func_caps.num_tx_qp,
4624 pf->hw.func_caps.num_vsis);
4625
4626 return 0;
4627}
4628
4629/**
4630 * i40e_fdir_setup - initialize the Flow Director resources
4631 * @pf: board private structure
4632 **/
4633static void i40e_fdir_setup(struct i40e_pf *pf)
4634{
4635 struct i40e_vsi *vsi;
4636 bool new_vsi = false;
4637 int err, i;
4638
958a3e3b
SN		 4639 if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED |
4640 I40E_FLAG_FDIR_ATR_ENABLED)))
41c445ff
JB		 4641 return;
4642
4643 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
4644
4645 /* find existing or make new FDIR VSI */
4646 vsi = NULL;
4647 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4648 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
4649 vsi = pf->vsi[i];
4650 if (!vsi) {
4651 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
4652 if (!vsi) {
4653 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
4654 pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
4655 return;
4656 }
4657 new_vsi = true;
4658 }
4659 WARN_ON(vsi->base_queue != I40E_FDIR_RING);
4660 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
4661
4662 err = i40e_vsi_setup_tx_resources(vsi);
4663 if (!err)
4664 err = i40e_vsi_setup_rx_resources(vsi);
4665 if (!err)
4666 err = i40e_vsi_configure(vsi);
4667 if (!err && new_vsi) {
4668 char int_name[IFNAMSIZ + 9];
4669 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4670 dev_driver_string(&pf->pdev->dev));
4671 err = i40e_vsi_request_irq(vsi, int_name);
4672 }
4673 if (!err)
4674 err = i40e_up_complete(vsi);
4675
4676 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4677}
4678
4679/**
4680 * i40e_fdir_teardown - release the Flow Director resources
4681 * @pf: board private structure
4682 **/
4683static void i40e_fdir_teardown(struct i40e_pf *pf)
4684{
4685 int i;
4686
4687 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
4688 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
4689 i40e_vsi_release(pf->vsi[i]);
4690 break;
4691 }
4692 }
4693}
4694
4695/**
4696 * i40e_handle_reset_warning - prep for the core to reset
4697 * @pf: board private structure
4698 *
4699 * Close up the VFs and other things in prep for a Core Reset,
4700 * then get ready to rebuild the world.
4701 **/
4702static void i40e_handle_reset_warning(struct i40e_pf *pf)
4703{
4704 struct i40e_driver_version dv;
4705 struct i40e_hw *hw = &pf->hw;
4706 i40e_status ret;
4707 u32 v;
4708
4709 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
4710 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
4711 return;
4712
4713 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
4714
4715 i40e_vc_notify_reset(pf);
4716
4717 /* quiesce the VSIs and their queues that are not already DOWN */
4718 i40e_pf_quiesce_all_vsi(pf);
4719
4720 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4721 if (pf->vsi[v])
4722 pf->vsi[v]->seid = 0;
4723 }
4724
4725 i40e_shutdown_adminq(&pf->hw);
4726
4727 /* Now we wait for GRST to settle out.
4728 * We don't have to delete the VEBs or VSIs from the hw switch
4729 * because the reset will make them disappear.
4730 */
4731 ret = i40e_pf_reset(hw);
4732 if (ret)
4733 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
4734 pf->pfr_count++;
4735
4736 if (test_bit(__I40E_DOWN, &pf->state))
4737 goto end_core_reset;
4738 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
4739
4740 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
4741 ret = i40e_init_adminq(&pf->hw);
4742 if (ret) {
4743 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
4744 goto end_core_reset;
4745 }
4746
4747 ret = i40e_get_capabilities(pf);
4748 if (ret) {
4749 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
4750 ret);
4751 goto end_core_reset;
4752 }
4753
4754 /* call shutdown HMC */
4755 ret = i40e_shutdown_lan_hmc(hw);
4756 if (ret) {
4757 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
4758 goto end_core_reset;
4759 }
4760
4761 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
4762 hw->func_caps.num_rx_qp,
4763 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
4764 if (ret) {
4765 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
4766 goto end_core_reset;
4767 }
4768 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
4769 if (ret) {
4770 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
4771 goto end_core_reset;
4772 }
4773
4774 /* do basic switch setup */
4775 ret = i40e_setup_pf_switch(pf);
4776 if (ret)
4777 goto end_core_reset;
4778
4779 /* Rebuild the VSIs and VEBs that existed before reset.
4780 * They are still in our local switch element arrays, so only
4781 * need to rebuild the switch model in the HW.
4782 *
4783 * If there were VEBs but the reconstitution failed, we'll try
4784 * try to recover minimal use by getting the basic PF VSI working.
4785 */
4786 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
4787 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
4788 /* find the one VEB connected to the MAC, and find orphans */
4789 for (v = 0; v < I40E_MAX_VEB; v++) {
4790 if (!pf->veb[v])
4791 continue;
4792
4793 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
4794 pf->veb[v]->uplink_seid == 0) {
4795 ret = i40e_reconstitute_veb(pf->veb[v]);
4796
4797 if (!ret)
4798 continue;
4799
4800 /* If Main VEB failed, we're in deep doodoo,
4801 * so give up rebuilding the switch and set up
4802 * for minimal rebuild of PF VSI.
4803 * If orphan failed, we'll report the error
4804 * but try to keep going.
4805 */
4806 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
4807 dev_info(&pf->pdev->dev,
4808 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
4809 ret);
4810 pf->vsi[pf->lan_vsi]->uplink_seid
4811 = pf->mac_seid;
4812 break;
4813 } else if (pf->veb[v]->uplink_seid == 0) {
4814 dev_info(&pf->pdev->dev,
4815 "rebuild of orphan VEB failed: %d\n",
4816 ret);
4817 }
4818 }
4819 }
4820 }
4821
4822 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
4823 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
4824 /* no VEB, so rebuild only the Main VSI */
4825 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
4826 if (ret) {
4827 dev_info(&pf->pdev->dev,
4828 "rebuild of Main VSI failed: %d\n", ret);
4829 goto end_core_reset;
4830 }
4831 }
4832
4833 /* reinit the misc interrupt */
4834 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4835 ret = i40e_setup_misc_vector(pf);
4836
4837 /* restart the VSIs that were rebuilt and running before the reset */
4838 i40e_pf_unquiesce_all_vsi(pf);
4839
4840 /* tell the firmware that we're starting */
4841 dv.major_version = DRV_VERSION_MAJOR;
4842 dv.minor_version = DRV_VERSION_MINOR;
4843 dv.build_version = DRV_VERSION_BUILD;
4844 dv.subbuild_version = 0;
4845 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
4846
4847 dev_info(&pf->pdev->dev, "PF reset done\n");
4848
4849end_core_reset:
4850 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4851}
4852
4853/**
4854 * i40e_handle_mdd_event
4855 * @pf: pointer to the pf structure
4856 *
4857 * Called from the MDD irq handler to identify possibly malicious vfs
4858 **/
4859static void i40e_handle_mdd_event(struct i40e_pf *pf)
4860{
4861 struct i40e_hw *hw = &pf->hw;
4862 bool mdd_detected = false;
4863 struct i40e_vf *vf;
4864 u32 reg;
4865 int i;
4866
4867 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
4868 return;
4869
4870 /* find what triggered the MDD event */
4871 reg = rd32(hw, I40E_GL_MDET_TX);
4872 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4873 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
4874 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
4875 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
4876 >> I40E_GL_MDET_TX_EVENT_SHIFT;
4877 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
4878 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
4879 dev_info(&pf->pdev->dev,
4880 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
4881 event, queue, func);
4882 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
4883 mdd_detected = true;
4884 }
4885 reg = rd32(hw, I40E_GL_MDET_RX);
4886 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4887 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
4888 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
4889 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
4890 >> I40E_GL_MDET_RX_EVENT_SHIFT;
4891 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
4892 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
4893 dev_info(&pf->pdev->dev,
4894 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
4895 event, queue, func);
4896 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
4897 mdd_detected = true;
4898 }
4899
4900 /* see if one of the VFs needs its hand slapped */
4901 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
4902 vf = &(pf->vf[i]);
4903 reg = rd32(hw, I40E_VP_MDET_TX(i));
4904 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
4905 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
4906 vf->num_mdd_events++;
4907 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
4908 }
4909
4910 reg = rd32(hw, I40E_VP_MDET_RX(i));
4911 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
4912 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
4913 vf->num_mdd_events++;
4914 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
4915 }
4916
4917 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
4918 dev_info(&pf->pdev->dev,
4919 "Too many MDD events on VF %d, disabled\n", i);
4920 dev_info(&pf->pdev->dev,
4921 "Use PF Control I/F to re-enable the VF\n");
4922 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
4923 }
4924 }
4925
4926 /* re-enable mdd interrupt cause */
4927 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
4928 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
4929 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
4930 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
4931 i40e_flush(hw);
4932}
4933
4934/**
4935 * i40e_service_task - Run the driver's async subtasks
4936 * @work: pointer to work_struct containing our data
4937 **/
4938static void i40e_service_task(struct work_struct *work)
4939{
4940 struct i40e_pf *pf = container_of(work,
4941 struct i40e_pf,
4942 service_task);
4943 unsigned long start_time = jiffies;
4944
4945 i40e_reset_subtask(pf);
4946 i40e_handle_mdd_event(pf);
4947 i40e_vc_process_vflr_event(pf);
4948 i40e_watchdog_subtask(pf);
4949 i40e_fdir_reinit_subtask(pf);
4950 i40e_check_hang_subtask(pf);
4951 i40e_sync_filters_subtask(pf);
4952 i40e_clean_adminq_subtask(pf);
4953
4954 i40e_service_event_complete(pf);
4955
4956 /* If the tasks have taken longer than one timer cycle or there
4957 * is more work to be done, reschedule the service task now
4958 * rather than wait for the timer to tick again.
4959 */
4960 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
4961 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
4962 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
4963 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
4964 i40e_service_event_schedule(pf);
4965}
4966
4967/**
4968 * i40e_service_timer - timer callback
4969 * @data: pointer to PF struct
4970 **/
4971static void i40e_service_timer(unsigned long data)
4972{
4973 struct i40e_pf *pf = (struct i40e_pf *)data;
4974
4975 mod_timer(&pf->service_timer,
4976 round_jiffies(jiffies + pf->service_timer_period));
4977 i40e_service_event_schedule(pf);
4978}
4979
4980/**
4981 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
4982 * @vsi: the VSI being configured
4983 **/
4984static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
4985{
4986 struct i40e_pf *pf = vsi->back;
4987
4988 switch (vsi->type) {
4989 case I40E_VSI_MAIN:
4990 vsi->alloc_queue_pairs = pf->num_lan_qps;
4991 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
4992 I40E_REQ_DESCRIPTOR_MULTIPLE);
4993 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4994 vsi->num_q_vectors = pf->num_lan_msix;
4995 else
4996 vsi->num_q_vectors = 1;
4997
4998 break;
4999
5000 case I40E_VSI_FDIR:
5001 vsi->alloc_queue_pairs = 1;
5002 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5003 I40E_REQ_DESCRIPTOR_MULTIPLE);
5004 vsi->num_q_vectors = 1;
5005 break;
5006
5007 case I40E_VSI_VMDQ2:
5008 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5009 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5010 I40E_REQ_DESCRIPTOR_MULTIPLE);
5011 vsi->num_q_vectors = pf->num_vmdq_msix;
5012 break;
5013
5014 case I40E_VSI_SRIOV:
5015 vsi->alloc_queue_pairs = pf->num_vf_qps;
5016 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5017 I40E_REQ_DESCRIPTOR_MULTIPLE);
5018 break;
5019
5020 default:
5021 WARN_ON(1);
5022 return -ENODATA;
5023 }
5024
5025 return 0;
5026}
5027
5028/**
5029 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5030 * @pf: board private structure
5031 * @type: type of VSI
5032 *
5033 * On error: returns error code (negative)
5034 * On success: returns vsi index in PF (positive)
5035 **/
5036static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5037{
5038 int ret = -ENODEV;
5039 struct i40e_vsi *vsi;
493fb300 5040 int sz_vectors;
9f65e15b 5041 int sz_rings;
41c445ff
JB		 5042 int vsi_idx;
5043 int i;
5044
5045 /* Need to protect the allocation of the VSIs at the PF level */
5046 mutex_lock(&pf->switch_mutex);
5047
5048 /* VSI list may be fragmented if VSI creation/destruction has
5049 * been happening. We can afford to do a quick scan to look
5050 * for any free VSIs in the list.
5051 *
5052 * find next empty vsi slot, looping back around if necessary
5053 */
5054 i = pf->next_vsi;
5055 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5056 i++;
5057 if (i >= pf->hw.func_caps.num_vsis) {
5058 i = 0;
5059 while (i < pf->next_vsi && pf->vsi[i])
5060 i++;
5061 }
5062
5063 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5064 vsi_idx = i; /* Found one! */
5065 } else {
5066 ret = -ENODEV;
493fb300 5067 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5068 }
5069 pf->next_vsi = ++i;
5070
5071 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5072 if (!vsi) {
5073 ret = -ENOMEM;
493fb300 5074 goto unlock_pf;
41c445ff
JB		 5075 }
5076 vsi->type = type;
5077 vsi->back = pf;
5078 set_bit(__I40E_DOWN, &vsi->state);
5079 vsi->flags = 0;
5080 vsi->idx = vsi_idx;
5081 vsi->rx_itr_setting = pf->rx_itr_default;
5082 vsi->tx_itr_setting = pf->tx_itr_default;
5083 vsi->netdev_registered = false;
5084 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5085 INIT_LIST_HEAD(&vsi->mac_filter_list);
5086
9f65e15b
AD		 5087 ret = i40e_set_num_rings_in_vsi(vsi);
5088 if (ret)
5089 goto err_rings;
5090
5091 /* allocate memory for ring pointers */
5092 sz_rings = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5093 vsi->tx_rings = kzalloc(sz_rings, GFP_KERNEL);
5094 if (!vsi->tx_rings) {
5095 ret = -ENOMEM;
5096 goto err_rings;
5097 }
5098 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
41c445ff 5099
493fb300
AD		 5100 /* allocate memory for q_vector pointers */
5101 sz_vectors = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5102 vsi->q_vectors = kzalloc(sz_vectors, GFP_KERNEL);
5103 if (!vsi->q_vectors) {
5104 ret = -ENOMEM;
5105 goto err_vectors;
5106 }
5107
41c445ff
JB		 5108 /* Setup default MSIX irq handler for VSI */
5109 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5110
5111 pf->vsi[vsi_idx] = vsi;
5112 ret = vsi_idx;
493fb300
AD		 5113 goto unlock_pf;
5114
5115err_vectors:
9f65e15b
AD		 5116 kfree(vsi->tx_rings);
5117err_rings:
493fb300
AD		 5118 pf->next_vsi = i - 1;
5119 kfree(vsi);
5120unlock_pf:
41c445ff
JB		 5121 mutex_unlock(&pf->switch_mutex);
5122 return ret;
5123}
5124
5125/**
5126 * i40e_vsi_clear - Deallocate the VSI provided
5127 * @vsi: the VSI being un-configured
5128 **/
5129static int i40e_vsi_clear(struct i40e_vsi *vsi)
5130{
5131 struct i40e_pf *pf;
5132
5133 if (!vsi)
5134 return 0;
5135
5136 if (!vsi->back)
5137 goto free_vsi;
5138 pf = vsi->back;
5139
5140 mutex_lock(&pf->switch_mutex);
5141 if (!pf->vsi[vsi->idx]) {
5142 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5143 vsi->idx, vsi->idx, vsi, vsi->type);
5144 goto unlock_vsi;
5145 }
5146
5147 if (pf->vsi[vsi->idx] != vsi) {
5148 dev_err(&pf->pdev->dev,
5149 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5150 pf->vsi[vsi->idx]->idx,
5151 pf->vsi[vsi->idx],
5152 pf->vsi[vsi->idx]->type,
5153 vsi->idx, vsi, vsi->type);
5154 goto unlock_vsi;
5155 }
5156
5157 /* updates the pf for this cleared vsi */
5158 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5159 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5160
493fb300
AD		 5161 /* free the ring and vector containers */
5162 kfree(vsi->q_vectors);
9f65e15b 5163 kfree(vsi->tx_rings);
493fb300 5164
41c445ff
JB		 5165 pf->vsi[vsi->idx] = NULL;
5166 if (vsi->idx < pf->next_vsi)
5167 pf->next_vsi = vsi->idx;
5168
5169unlock_vsi:
5170 mutex_unlock(&pf->switch_mutex);
5171free_vsi:
5172 kfree(vsi);
5173
5174 return 0;
5175}
5176
9f65e15b
AD		 5177/**
5178 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5179 * @vsi: the VSI being cleaned
5180 **/
5181static s32 i40e_vsi_clear_rings(struct i40e_vsi *vsi)
5182{
5183 int i;
5184
00403f04
MW		 5185 if (vsi->tx_rings[0])
5186 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
5187 kfree_rcu(vsi->tx_rings[i], rcu);
5188 vsi->tx_rings[i] = NULL;
5189 vsi->rx_rings[i] = NULL;
5190 }
9f65e15b
AD		 5191
5192 return 0;
5193}
5194
41c445ff
JB		 5195/**
5196 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5197 * @vsi: the VSI being configured
5198 **/
5199static int i40e_alloc_rings(struct i40e_vsi *vsi)
5200{
5201 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5202 int i;
5203
41c445ff
JB		 5204 /* Set basic values in the rings to be used later during open() */
5205 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5206 struct i40e_ring *tx_ring;
5207 struct i40e_ring *rx_ring;
5208
5209 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5210 if (!tx_ring)
5211 goto err_out;
41c445ff
JB		 5212
5213 tx_ring->queue_index = i;
5214 tx_ring->reg_idx = vsi->base_queue + i;
5215 tx_ring->ring_active = false;
5216 tx_ring->vsi = vsi;
5217 tx_ring->netdev = vsi->netdev;
5218 tx_ring->dev = &pf->pdev->dev;
5219 tx_ring->count = vsi->num_desc;
5220 tx_ring->size = 0;
5221 tx_ring->dcb_tc = 0;
9f65e15b 5222 vsi->tx_rings[i] = tx_ring;
41c445ff 5223
9f65e15b 5224 rx_ring = &tx_ring[1];
41c445ff
JB		 5225 rx_ring->queue_index = i;
5226 rx_ring->reg_idx = vsi->base_queue + i;
5227 rx_ring->ring_active = false;
5228 rx_ring->vsi = vsi;
5229 rx_ring->netdev = vsi->netdev;
5230 rx_ring->dev = &pf->pdev->dev;
5231 rx_ring->count = vsi->num_desc;
5232 rx_ring->size = 0;
5233 rx_ring->dcb_tc = 0;
5234 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5235 set_ring_16byte_desc_enabled(rx_ring);
5236 else
5237 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5238 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5239 }
5240
5241 return 0;
9f65e15b
AD		 5242
5243err_out:
5244 i40e_vsi_clear_rings(vsi);
5245 return -ENOMEM;
41c445ff
JB		 5246}
5247
5248/**
5249 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5250 * @pf: board private structure
5251 * @vectors: the number of MSI-X vectors to request
5252 *
5253 * Returns the number of vectors reserved, or error
5254 **/
5255static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5256{
5257 int err = 0;
5258
5259 pf->num_msix_entries = 0;
5260 while (vectors >= I40E_MIN_MSIX) {
5261 err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
5262 if (err == 0) {
5263 /* good to go */
5264 pf->num_msix_entries = vectors;
5265 break;
5266 } else if (err < 0) {
5267 /* total failure */
5268 dev_info(&pf->pdev->dev,
5269 "MSI-X vector reservation failed: %d\n", err);
5270 vectors = 0;
5271 break;
5272 } else {
5273 /* err > 0 is the hint for retry */
5274 dev_info(&pf->pdev->dev,
5275 "MSI-X vectors wanted %d, retrying with %d\n",
5276 vectors, err);
5277 vectors = err;
5278 }
5279 }
5280
5281 if (vectors > 0 && vectors < I40E_MIN_MSIX) {
5282 dev_info(&pf->pdev->dev,
5283 "Couldn't get enough vectors, only %d available\n",
5284 vectors);
5285 vectors = 0;
5286 }
5287
5288 return vectors;
5289}
5290
5291/**
5292 * i40e_init_msix - Setup the MSIX capability
5293 * @pf: board private structure
5294 *
5295 * Work with the OS to set up the MSIX vectors needed.
5296 *
5297 * Returns 0 on success, negative on failure
5298 **/
5299static int i40e_init_msix(struct i40e_pf *pf)
5300{
5301 i40e_status err = 0;
5302 struct i40e_hw *hw = &pf->hw;
5303 int v_budget, i;
5304 int vec;
5305
5306 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5307 return -ENODEV;
5308
5309 /* The number of vectors we'll request will be comprised of:
5310 * - Add 1 for "other" cause for Admin Queue events, etc.
5311 * - The number of LAN queue pairs
5312 * already adjusted for the NUMA node
5313 * assumes symmetric Tx/Rx pairing
5314 * - The number of VMDq pairs
5315 * Once we count this up, try the request.
5316 *
5317 * If we can't get what we want, we'll simplify to nearly nothing
5318 * and try again. If that still fails, we punt.
5319 */
5320 pf->num_lan_msix = pf->num_lan_qps;
5321 pf->num_vmdq_msix = pf->num_vmdq_qps;
5322 v_budget = 1 + pf->num_lan_msix;
5323 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
5324 if (pf->flags & I40E_FLAG_FDIR_ENABLED)
5325 v_budget++;
5326
5327 /* Scale down if necessary, and the rings will share vectors */
5328 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5329
5330 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5331 GFP_KERNEL);
5332 if (!pf->msix_entries)
5333 return -ENOMEM;
5334
5335 for (i = 0; i < v_budget; i++)
5336 pf->msix_entries[i].entry = i;
5337 vec = i40e_reserve_msix_vectors(pf, v_budget);
5338 if (vec < I40E_MIN_MSIX) {
5339 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5340 kfree(pf->msix_entries);
5341 pf->msix_entries = NULL;
5342 return -ENODEV;
5343
5344 } else if (vec == I40E_MIN_MSIX) {
5345 /* Adjust for minimal MSIX use */
5346 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5347 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5348 pf->num_vmdq_vsis = 0;
5349 pf->num_vmdq_qps = 0;
5350 pf->num_vmdq_msix = 0;
5351 pf->num_lan_qps = 1;
5352 pf->num_lan_msix = 1;
5353
5354 } else if (vec != v_budget) {
5355 /* Scale vector usage down */
5356 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5357 vec--; /* reserve the misc vector */
5358
5359 /* partition out the remaining vectors */
5360 switch (vec) {
5361 case 2:
5362 pf->num_vmdq_vsis = 1;
5363 pf->num_lan_msix = 1;
5364 break;
5365 case 3:
5366 pf->num_vmdq_vsis = 1;
5367 pf->num_lan_msix = 2;
5368 break;
5369 default:
5370 pf->num_lan_msix = min_t(int, (vec / 2),
5371 pf->num_lan_qps);
5372 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5373 I40E_DEFAULT_NUM_VMDQ_VSI);
5374 break;
5375 }
5376 }
5377
5378 return err;
5379}
5380
493fb300
AD		 5381/**
5382 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5383 * @vsi: the VSI being configured
5384 * @v_idx: index of the vector in the vsi struct
5385 *
5386 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5387 **/
5388static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5389{
5390 struct i40e_q_vector *q_vector;
5391
5392 /* allocate q_vector */
5393 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5394 if (!q_vector)
5395 return -ENOMEM;
5396
5397 q_vector->vsi = vsi;
5398 q_vector->v_idx = v_idx;
5399 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5400 if (vsi->netdev)
5401 netif_napi_add(vsi->netdev, &q_vector->napi,
5402 i40e_napi_poll, vsi->work_limit);
5403
cd0b6fa6
AD		 5404 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5405 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5406
493fb300
AD		 5407 /* tie q_vector and vsi together */
5408 vsi->q_vectors[v_idx] = q_vector;
5409
5410 return 0;
5411}
5412
41c445ff
JB		 5413/**
5414 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5415 * @vsi: the VSI being configured
5416 *
5417 * We allocate one q_vector per queue interrupt. If allocation fails we
5418 * return -ENOMEM.
5419 **/
5420static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
5421{
5422 struct i40e_pf *pf = vsi->back;
5423 int v_idx, num_q_vectors;
493fb300 5424 int err;
41c445ff
JB		 5425
5426 /* if not MSIX, give the one vector only to the LAN VSI */
5427 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5428 num_q_vectors = vsi->num_q_vectors;
5429 else if (vsi == pf->vsi[pf->lan_vsi])
5430 num_q_vectors = 1;
5431 else
5432 return -EINVAL;
5433
41c445ff 5434 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 5435 err = i40e_alloc_q_vector(vsi, v_idx);
5436 if (err)
5437 goto err_out;
41c445ff
JB		 5438 }
5439
5440 return 0;
493fb300
AD		 5441
5442err_out:
5443 while (v_idx--)
5444 i40e_free_q_vector(vsi, v_idx);
5445
5446 return err;
41c445ff
JB		 5447}
5448
5449/**
5450 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
5451 * @pf: board private structure to initialize
5452 **/
5453static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
5454{
5455 int err = 0;
5456
5457 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
5458 err = i40e_init_msix(pf);
5459 if (err) {
958a3e3b
SN		 5460 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
5461 I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 5462 I40E_FLAG_MQ_ENABLED |
5463 I40E_FLAG_DCB_ENABLED |
5464 I40E_FLAG_SRIOV_ENABLED |
5465 I40E_FLAG_FDIR_ENABLED |
5466 I40E_FLAG_FDIR_ATR_ENABLED |
5467 I40E_FLAG_VMDQ_ENABLED);
5468
5469 /* rework the queue expectations without MSIX */
5470 i40e_determine_queue_usage(pf);
5471 }
5472 }
5473
5474 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
5475 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 5476 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 5477 err = pci_enable_msi(pf->pdev);
5478 if (err) {
958a3e3b 5479 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 5480 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
5481 }
5482 }
5483
958a3e3b
SN		 5484 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
5485 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
5486
41c445ff
JB		 5487 /* track first vector for misc interrupts */
5488 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
5489}
5490
5491/**
5492 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
5493 * @pf: board private structure
5494 *
5495 * This sets up the handler for MSIX 0, which is used to manage the
5496 * non-queue interrupts, e.g. AdminQ and errors. This is not used
5497 * when in MSI or Legacy interrupt mode.
5498 **/
5499static int i40e_setup_misc_vector(struct i40e_pf *pf)
5500{
5501 struct i40e_hw *hw = &pf->hw;
5502 int err = 0;
5503
5504 /* Only request the irq if this is the first time through, and
5505 * not when we're rebuilding after a Reset
5506 */
5507 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5508 err = request_irq(pf->msix_entries[0].vector,
5509 i40e_intr, 0, pf->misc_int_name, pf);
5510 if (err) {
5511 dev_info(&pf->pdev->dev,
5512 "request_irq for msix_misc failed: %d\n", err);
5513 return -EFAULT;
5514 }
5515 }
5516
5517 i40e_enable_misc_int_causes(hw);
5518
5519 /* associate no queues to the misc vector */
5520 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
5521 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
5522
5523 i40e_flush(hw);
5524
5525 i40e_irq_dynamic_enable_icr0(pf);
5526
5527 return err;
5528}
5529
5530/**
5531 * i40e_config_rss - Prepare for RSS if used
5532 * @pf: board private structure
5533 **/
5534static int i40e_config_rss(struct i40e_pf *pf)
5535{
5536 struct i40e_hw *hw = &pf->hw;
5537 u32 lut = 0;
5538 int i, j;
5539 u64 hena;
5540 /* Set of random keys generated using kernel random number generator */
5541 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
5542 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
5543 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
5544 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
5545
5546 /* Fill out hash function seed */
5547 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5548 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
5549
5550 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
5551 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
5552 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
5553 hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
5554 ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
5555 ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) |
5556 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
5557 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
5558 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
5559 ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
5560 ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) |
5561 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4)|
5562 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6);
5563 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
5564 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
5565
5566 /* Populate the LUT with max no. of queues in round robin fashion */
5567 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
5568
5569 /* The assumption is that lan qp count will be the highest
5570 * qp count for any PF VSI that needs RSS.
5571 * If multiple VSIs need RSS support, all the qp counts
5572 * for those VSIs should be a power of 2 for RSS to work.
5573 * If LAN VSI is the only consumer for RSS then this requirement
5574 * is not necessary.
5575 */
5576 if (j == pf->rss_size)
5577 j = 0;
5578 /* lut = 4-byte sliding window of 4 lut entries */
5579 lut = (lut << 8) | (j &
5580 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
5581 /* On i = 3, we have 4 entries in lut; write to the register */
5582 if ((i & 3) == 3)
5583 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
5584 }
5585 i40e_flush(hw);
5586
5587 return 0;
5588}
5589
5590/**
5591 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
5592 * @pf: board private structure to initialize
5593 *
5594 * i40e_sw_init initializes the Adapter private data structure.
5595 * Fields are initialized based on PCI device information and
5596 * OS network device settings (MTU size).
5597 **/
5598static int i40e_sw_init(struct i40e_pf *pf)
5599{
5600 int err = 0;
5601 int size;
5602
5603 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
5604 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 5605 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 5606 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
5607 if (I40E_DEBUG_USER & debug)
5608 pf->hw.debug_mask = debug;
5609 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
5610 I40E_DEFAULT_MSG_ENABLE);
5611 }
5612
5613 /* Set default capability flags */
5614 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
5615 I40E_FLAG_MSI_ENABLED |
5616 I40E_FLAG_MSIX_ENABLED |
5617 I40E_FLAG_RX_PS_ENABLED |
5618 I40E_FLAG_MQ_ENABLED |
5619 I40E_FLAG_RX_1BUF_ENABLED;
5620
5621 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
5622 if (pf->hw.func_caps.rss) {
5623 pf->flags |= I40E_FLAG_RSS_ENABLED;
5624 pf->rss_size = min_t(int, pf->rss_size_max,
5625 nr_cpus_node(numa_node_id()));
5626 } else {
5627 pf->rss_size = 1;
5628 }
5629
5630 if (pf->hw.func_caps.dcb)
5631 pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
5632 else
5633 pf->num_tc_qps = 0;
5634
5635 if (pf->hw.func_caps.fd) {
5636 /* FW/NVM is not yet fixed in this regard */
5637 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
5638 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
5639 pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
5640 dev_info(&pf->pdev->dev,
5641 "Flow Director ATR mode Enabled\n");
5642 pf->flags |= I40E_FLAG_FDIR_ENABLED;
5643 dev_info(&pf->pdev->dev,
5644 "Flow Director Side Band mode Enabled\n");
5645 pf->fdir_pf_filter_count =
5646 pf->hw.func_caps.fd_filters_guaranteed;
5647 }
5648 } else {
5649 pf->fdir_pf_filter_count = 0;
5650 }
5651
5652 if (pf->hw.func_caps.vmdq) {
5653 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
5654 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
5655 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
5656 }
5657
5658 /* MFP mode enabled */
5659 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
5660 pf->flags |= I40E_FLAG_MFP_ENABLED;
5661 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
5662 }
5663
5664#ifdef CONFIG_PCI_IOV
5665 if (pf->hw.func_caps.num_vfs) {
5666 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
5667 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
5668 pf->num_req_vfs = min_t(int,
5669 pf->hw.func_caps.num_vfs,
5670 I40E_MAX_VF_COUNT);
5671 }
5672#endif /* CONFIG_PCI_IOV */
5673 pf->eeprom_version = 0xDEAD;
5674 pf->lan_veb = I40E_NO_VEB;
5675 pf->lan_vsi = I40E_NO_VSI;
5676
5677 /* set up queue assignment tracking */
5678 size = sizeof(struct i40e_lump_tracking)
5679 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
5680 pf->qp_pile = kzalloc(size, GFP_KERNEL);
5681 if (!pf->qp_pile) {
5682 err = -ENOMEM;
5683 goto sw_init_done;
5684 }
5685 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
5686 pf->qp_pile->search_hint = 0;
5687
5688 /* set up vector assignment tracking */
5689 size = sizeof(struct i40e_lump_tracking)
5690 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
5691 pf->irq_pile = kzalloc(size, GFP_KERNEL);
5692 if (!pf->irq_pile) {
5693 kfree(pf->qp_pile);
5694 err = -ENOMEM;
5695 goto sw_init_done;
5696 }
5697 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
5698 pf->irq_pile->search_hint = 0;
5699
5700 mutex_init(&pf->switch_mutex);
5701
5702sw_init_done:
5703 return err;
5704}
5705
5706/**
5707 * i40e_set_features - set the netdev feature flags
5708 * @netdev: ptr to the netdev being adjusted
5709 * @features: the feature set that the stack is suggesting
5710 **/
5711static int i40e_set_features(struct net_device *netdev,
5712 netdev_features_t features)
5713{
5714 struct i40e_netdev_priv *np = netdev_priv(netdev);
5715 struct i40e_vsi *vsi = np->vsi;
5716
5717 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5718 i40e_vlan_stripping_enable(vsi);
5719 else
5720 i40e_vlan_stripping_disable(vsi);
5721
5722 return 0;
5723}
5724
5725static const struct net_device_ops i40e_netdev_ops = {
5726 .ndo_open = i40e_open,
5727 .ndo_stop = i40e_close,
5728 .ndo_start_xmit = i40e_lan_xmit_frame,
5729 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
5730 .ndo_set_rx_mode = i40e_set_rx_mode,
5731 .ndo_validate_addr = eth_validate_addr,
5732 .ndo_set_mac_address = i40e_set_mac,
5733 .ndo_change_mtu = i40e_change_mtu,
5734 .ndo_tx_timeout = i40e_tx_timeout,
5735 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
5736 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
5737#ifdef CONFIG_NET_POLL_CONTROLLER
5738 .ndo_poll_controller = i40e_netpoll,
5739#endif
5740 .ndo_setup_tc = i40e_setup_tc,
5741 .ndo_set_features = i40e_set_features,
5742 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
5743 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
5744 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
5745 .ndo_get_vf_config = i40e_ndo_get_vf_config,
5746};
5747
5748/**
5749 * i40e_config_netdev - Setup the netdev flags
5750 * @vsi: the VSI being configured
5751 *
5752 * Returns 0 on success, negative value on failure
5753 **/
5754static int i40e_config_netdev(struct i40e_vsi *vsi)
5755{
5756 struct i40e_pf *pf = vsi->back;
5757 struct i40e_hw *hw = &pf->hw;
5758 struct i40e_netdev_priv *np;
5759 struct net_device *netdev;
5760 u8 mac_addr[ETH_ALEN];
5761 int etherdev_size;
5762
5763 etherdev_size = sizeof(struct i40e_netdev_priv);
5764 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
5765 if (!netdev)
5766 return -ENOMEM;
5767
5768 vsi->netdev = netdev;
5769 np = netdev_priv(netdev);
5770 np->vsi = vsi;
5771
5772 netdev->hw_enc_features = NETIF_F_IP_CSUM |
5773 NETIF_F_GSO_UDP_TUNNEL |
5774 NETIF_F_TSO |
5775 NETIF_F_SG;
5776
5777 netdev->features = NETIF_F_SG |
5778 NETIF_F_IP_CSUM |
5779 NETIF_F_SCTP_CSUM |
5780 NETIF_F_HIGHDMA |
5781 NETIF_F_GSO_UDP_TUNNEL |
5782 NETIF_F_HW_VLAN_CTAG_TX |
5783 NETIF_F_HW_VLAN_CTAG_RX |
5784 NETIF_F_HW_VLAN_CTAG_FILTER |
5785 NETIF_F_IPV6_CSUM |
5786 NETIF_F_TSO |
5787 NETIF_F_TSO6 |
5788 NETIF_F_RXCSUM |
5789 NETIF_F_RXHASH |
5790 0;
5791
5792 /* copy netdev features into list of user selectable features */
5793 netdev->hw_features |= netdev->features;
5794
5795 if (vsi->type == I40E_VSI_MAIN) {
5796 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
5797 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
5798 } else {
5799 /* relate the VSI_VMDQ name to the VSI_MAIN name */
5800 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
5801 pf->vsi[pf->lan_vsi]->netdev->name);
5802 random_ether_addr(mac_addr);
5803 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
5804 }
5805
5806 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
5807 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
5808 /* vlan gets same features (except vlan offload)
5809 * after any tweaks for specific VSI types
5810 */
5811 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
5812 NETIF_F_HW_VLAN_CTAG_RX |
5813 NETIF_F_HW_VLAN_CTAG_FILTER);
5814 netdev->priv_flags |= IFF_UNICAST_FLT;
5815 netdev->priv_flags |= IFF_SUPP_NOFCS;
5816 /* Setup netdev TC information */
5817 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
5818
5819 netdev->netdev_ops = &i40e_netdev_ops;
5820 netdev->watchdog_timeo = 5 * HZ;
5821 i40e_set_ethtool_ops(netdev);
5822
5823 return 0;
5824}
5825
5826/**
5827 * i40e_vsi_delete - Delete a VSI from the switch
5828 * @vsi: the VSI being removed
5829 *
5830 * Returns 0 on success, negative value on failure
5831 **/
5832static void i40e_vsi_delete(struct i40e_vsi *vsi)
5833{
5834 /* remove default VSI is not allowed */
5835 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
5836 return;
5837
5838 /* there is no HW VSI for FDIR */
5839 if (vsi->type == I40E_VSI_FDIR)
5840 return;
5841
5842 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
5843 return;
5844}
5845
5846/**
5847 * i40e_add_vsi - Add a VSI to the switch
5848 * @vsi: the VSI being configured
5849 *
5850 * This initializes a VSI context depending on the VSI type to be added and
5851 * passes it down to the add_vsi aq command.
5852 **/
5853static int i40e_add_vsi(struct i40e_vsi *vsi)
5854{
5855 int ret = -ENODEV;
5856 struct i40e_mac_filter *f, *ftmp;
5857 struct i40e_pf *pf = vsi->back;
5858 struct i40e_hw *hw = &pf->hw;
5859 struct i40e_vsi_context ctxt;
5860 u8 enabled_tc = 0x1; /* TC0 enabled */
5861 int f_count = 0;
5862
5863 memset(&ctxt, 0, sizeof(ctxt));
5864 switch (vsi->type) {
5865 case I40E_VSI_MAIN:
5866 /* The PF's main VSI is already setup as part of the
5867 * device initialization, so we'll not bother with
5868 * the add_vsi call, but we will retrieve the current
5869 * VSI context.
5870 */
5871 ctxt.seid = pf->main_vsi_seid;
5872 ctxt.pf_num = pf->hw.pf_id;
5873 ctxt.vf_num = 0;
5874 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
5875 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5876 if (ret) {
5877 dev_info(&pf->pdev->dev,
5878 "couldn't get pf vsi config, err %d, aq_err %d\n",
5879 ret, pf->hw.aq.asq_last_status);
5880 return -ENOENT;
5881 }
5882 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5883 vsi->info.valid_sections = 0;
5884
5885 vsi->seid = ctxt.seid;
5886 vsi->id = ctxt.vsi_number;
5887
5888 enabled_tc = i40e_pf_get_tc_map(pf);
5889
5890 /* MFP mode setup queue map and update VSI */
5891 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5892 memset(&ctxt, 0, sizeof(ctxt));
5893 ctxt.seid = pf->main_vsi_seid;
5894 ctxt.pf_num = pf->hw.pf_id;
5895 ctxt.vf_num = 0;
5896 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
5897 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5898 if (ret) {
5899 dev_info(&pf->pdev->dev,
5900 "update vsi failed, aq_err=%d\n",
5901 pf->hw.aq.asq_last_status);
5902 ret = -ENOENT;
5903 goto err;
5904 }
5905 /* update the local VSI info queue map */
5906 i40e_vsi_update_queue_map(vsi, &ctxt);
5907 vsi->info.valid_sections = 0;
5908 } else {
5909 /* Default/Main VSI is only enabled for TC0
5910 * reconfigure it to enable all TCs that are
5911 * available on the port in SFP mode.
5912 */
5913 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5914 if (ret) {
5915 dev_info(&pf->pdev->dev,
5916 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
5917 enabled_tc, ret,
5918 pf->hw.aq.asq_last_status);
5919 ret = -ENOENT;
5920 }
5921 }
5922 break;
5923
5924 case I40E_VSI_FDIR:
5925 /* no queue mapping or actual HW VSI needed */
5926 vsi->info.valid_sections = 0;
5927 vsi->seid = 0;
5928 vsi->id = 0;
5929 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
5930 return 0;
5931 break;
5932
5933 case I40E_VSI_VMDQ2:
5934 ctxt.pf_num = hw->pf_id;
5935 ctxt.vf_num = 0;
5936 ctxt.uplink_seid = vsi->uplink_seid;
5937 ctxt.connection_type = 0x1; /* regular data port */
5938 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5939
5940 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5941
5942 /* This VSI is connected to VEB so the switch_id
5943 * should be set to zero by default.
5944 */
5945 ctxt.info.switch_id = 0;
5946 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5947 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5948
5949 /* Setup the VSI tx/rx queue map for TC0 only for now */
5950 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
5951 break;
5952
5953 case I40E_VSI_SRIOV:
5954 ctxt.pf_num = hw->pf_id;
5955 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
5956 ctxt.uplink_seid = vsi->uplink_seid;
5957 ctxt.connection_type = 0x1; /* regular data port */
5958 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5959
5960 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5961
5962 /* This VSI is connected to VEB so the switch_id
5963 * should be set to zero by default.
5964 */
5965 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5966
5967 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
5968 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5969 /* Setup the VSI tx/rx queue map for TC0 only for now */
5970 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
5971 break;
5972
5973 default:
5974 return -ENODEV;
5975 }
5976
5977 if (vsi->type != I40E_VSI_MAIN) {
5978 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5979 if (ret) {
5980 dev_info(&vsi->back->pdev->dev,
5981 "add vsi failed, aq_err=%d\n",
5982 vsi->back->hw.aq.asq_last_status);
5983 ret = -ENOENT;
5984 goto err;
5985 }
5986 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5987 vsi->info.valid_sections = 0;
5988 vsi->seid = ctxt.seid;
5989 vsi->id = ctxt.vsi_number;
5990 }
5991
5992 /* If macvlan filters already exist, force them to get loaded */
5993 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
5994 f->changed = true;
5995 f_count++;
5996 }
5997 if (f_count) {
5998 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
5999 pf->flags |= I40E_FLAG_FILTER_SYNC;
6000 }
6001
6002 /* Update VSI BW information */
6003 ret = i40e_vsi_get_bw_info(vsi);
6004 if (ret) {
6005 dev_info(&pf->pdev->dev,
6006 "couldn't get vsi bw info, err %d, aq_err %d\n",
6007 ret, pf->hw.aq.asq_last_status);
6008 /* VSI is already added so not tearing that up */
6009 ret = 0;
6010 }
6011
6012err:
6013 return ret;
6014}
6015
6016/**
6017 * i40e_vsi_release - Delete a VSI and free its resources
6018 * @vsi: the VSI being removed
6019 *
6020 * Returns 0 on success or < 0 on error
6021 **/
6022int i40e_vsi_release(struct i40e_vsi *vsi)
6023{
6024 struct i40e_mac_filter *f, *ftmp;
6025 struct i40e_veb *veb = NULL;
6026 struct i40e_pf *pf;
6027 u16 uplink_seid;
6028 int i, n;
6029
6030 pf = vsi->back;
6031
6032 /* release of a VEB-owner or last VSI is not allowed */
6033 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6034 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6035 vsi->seid, vsi->uplink_seid);
6036 return -ENODEV;
6037 }
6038 if (vsi == pf->vsi[pf->lan_vsi] &&
6039 !test_bit(__I40E_DOWN, &pf->state)) {
6040 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6041 return -ENODEV;
6042 }
6043
6044 uplink_seid = vsi->uplink_seid;
6045 if (vsi->type != I40E_VSI_SRIOV) {
6046 if (vsi->netdev_registered) {
6047 vsi->netdev_registered = false;
6048 if (vsi->netdev) {
6049 /* results in a call to i40e_close() */
6050 unregister_netdev(vsi->netdev);
6051 free_netdev(vsi->netdev);
6052 vsi->netdev = NULL;
6053 }
6054 } else {
6055 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6056 i40e_down(vsi);
6057 i40e_vsi_free_irq(vsi);
6058 i40e_vsi_free_tx_resources(vsi);
6059 i40e_vsi_free_rx_resources(vsi);
6060 }
6061 i40e_vsi_disable_irq(vsi);
6062 }
6063
6064 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6065 i40e_del_filter(vsi, f->macaddr, f->vlan,
6066 f->is_vf, f->is_netdev);
6067 i40e_sync_vsi_filters(vsi);
6068
6069 i40e_vsi_delete(vsi);
6070 i40e_vsi_free_q_vectors(vsi);
6071 i40e_vsi_clear_rings(vsi);
6072 i40e_vsi_clear(vsi);
6073
6074 /* If this was the last thing on the VEB, except for the
6075 * controlling VSI, remove the VEB, which puts the controlling
6076 * VSI onto the next level down in the switch.
6077 *
6078 * Well, okay, there's one more exception here: don't remove
6079 * the orphan VEBs yet. We'll wait for an explicit remove request
6080 * from up the network stack.
6081 */
6082 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6083 if (pf->vsi[i] &&
6084 pf->vsi[i]->uplink_seid == uplink_seid &&
6085 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6086 n++; /* count the VSIs */
6087 }
6088 }
6089 for (i = 0; i < I40E_MAX_VEB; i++) {
6090 if (!pf->veb[i])
6091 continue;
6092 if (pf->veb[i]->uplink_seid == uplink_seid)
6093 n++; /* count the VEBs */
6094 if (pf->veb[i]->seid == uplink_seid)
6095 veb = pf->veb[i];
6096 }
6097 if (n == 0 && veb && veb->uplink_seid != 0)
6098 i40e_veb_release(veb);
6099
6100 return 0;
6101}
6102
6103/**
6104 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6105 * @vsi: ptr to the VSI
6106 *
6107 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6108 * corresponding SW VSI structure and initializes num_queue_pairs for the
6109 * newly allocated VSI.
6110 *
6111 * Returns 0 on success or negative on failure
6112 **/
6113static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6114{
6115 int ret = -ENOENT;
6116 struct i40e_pf *pf = vsi->back;
6117
493fb300 6118 if (vsi->q_vectors[0]) {
41c445ff
JB		 6119 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6120 vsi->seid);
6121 return -EEXIST;
6122 }
6123
6124 if (vsi->base_vector) {
6125 dev_info(&pf->pdev->dev,
6126 "VSI %d has non-zero base vector %d\n",
6127 vsi->seid, vsi->base_vector);
6128 return -EEXIST;
6129 }
6130
6131 ret = i40e_alloc_q_vectors(vsi);
6132 if (ret) {
6133 dev_info(&pf->pdev->dev,
6134 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6135 vsi->num_q_vectors, vsi->seid, ret);
6136 vsi->num_q_vectors = 0;
6137 goto vector_setup_out;
6138 }
6139
958a3e3b
SN		 6140 if (vsi->num_q_vectors)
6141 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6142 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6143 if (vsi->base_vector < 0) {
6144 dev_info(&pf->pdev->dev,
6145 "failed to get q tracking for VSI %d, err=%d\n",
6146 vsi->seid, vsi->base_vector);
6147 i40e_vsi_free_q_vectors(vsi);
6148 ret = -ENOENT;
6149 goto vector_setup_out;
6150 }
6151
6152vector_setup_out:
6153 return ret;
6154}
6155
6156/**
6157 * i40e_vsi_setup - Set up a VSI by a given type
6158 * @pf: board private structure
6159 * @type: VSI type
6160 * @uplink_seid: the switch element to link to
6161 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6162 *
6163 * This allocates the sw VSI structure and its queue resources, then add a VSI
6164 * to the identified VEB.
6165 *
6166 * Returns pointer to the successfully allocated and configure VSI sw struct on
6167 * success, otherwise returns NULL on failure.
6168 **/
6169struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6170 u16 uplink_seid, u32 param1)
6171{
6172 struct i40e_vsi *vsi = NULL;
6173 struct i40e_veb *veb = NULL;
6174 int ret, i;
6175 int v_idx;
6176
6177 /* The requested uplink_seid must be either
6178 * - the PF's port seid
6179 * no VEB is needed because this is the PF
6180 * or this is a Flow Director special case VSI
6181 * - seid of an existing VEB
6182 * - seid of a VSI that owns an existing VEB
6183 * - seid of a VSI that doesn't own a VEB
6184 * a new VEB is created and the VSI becomes the owner
6185 * - seid of the PF VSI, which is what creates the first VEB
6186 * this is a special case of the previous
6187 *
6188 * Find which uplink_seid we were given and create a new VEB if needed
6189 */
6190 for (i = 0; i < I40E_MAX_VEB; i++) {
6191 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6192 veb = pf->veb[i];
6193 break;
6194 }
6195 }
6196
6197 if (!veb && uplink_seid != pf->mac_seid) {
6198
6199 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6200 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6201 vsi = pf->vsi[i];
6202 break;
6203 }
6204 }
6205 if (!vsi) {
6206 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6207 uplink_seid);
6208 return NULL;
6209 }
6210
6211 if (vsi->uplink_seid == pf->mac_seid)
6212 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6213 vsi->tc_config.enabled_tc);
6214 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6215 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6216 vsi->tc_config.enabled_tc);
6217
6218 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6219 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6220 veb = pf->veb[i];
6221 }
6222 if (!veb) {
6223 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6224 return NULL;
6225 }
6226
6227 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6228 uplink_seid = veb->seid;
6229 }
6230
6231 /* get vsi sw struct */
6232 v_idx = i40e_vsi_mem_alloc(pf, type);
6233 if (v_idx < 0)
6234 goto err_alloc;
6235 vsi = pf->vsi[v_idx];
6236 vsi->type = type;
6237 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
6238
6239 if (type == I40E_VSI_MAIN)
6240 pf->lan_vsi = v_idx;
6241 else if (type == I40E_VSI_SRIOV)
6242 vsi->vf_id = param1;
6243 /* assign it some queues */
6244 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6245 if (ret < 0) {
6246 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6247 vsi->seid, ret);
6248 goto err_vsi;
6249 }
6250 vsi->base_queue = ret;
6251
6252 /* get a VSI from the hardware */
6253 vsi->uplink_seid = uplink_seid;
6254 ret = i40e_add_vsi(vsi);
6255 if (ret)
6256 goto err_vsi;
6257
6258 switch (vsi->type) {
6259 /* setup the netdev if needed */
6260 case I40E_VSI_MAIN:
6261 case I40E_VSI_VMDQ2:
6262 ret = i40e_config_netdev(vsi);
6263 if (ret)
6264 goto err_netdev;
6265 ret = register_netdev(vsi->netdev);
6266 if (ret)
6267 goto err_netdev;
6268 vsi->netdev_registered = true;
6269 netif_carrier_off(vsi->netdev);
6270 /* fall through */
6271
6272 case I40E_VSI_FDIR:
6273 /* set up vectors and rings if needed */
6274 ret = i40e_vsi_setup_vectors(vsi);
6275 if (ret)
6276 goto err_msix;
6277
6278 ret = i40e_alloc_rings(vsi);
6279 if (ret)
6280 goto err_rings;
6281
6282 /* map all of the rings to the q_vectors */
6283 i40e_vsi_map_rings_to_vectors(vsi);
6284
6285 i40e_vsi_reset_stats(vsi);
6286 break;
6287
6288 default:
6289 /* no netdev or rings for the other VSI types */
6290 break;
6291 }
6292
6293 return vsi;
6294
6295err_rings:
6296 i40e_vsi_free_q_vectors(vsi);
6297err_msix:
6298 if (vsi->netdev_registered) {
6299 vsi->netdev_registered = false;
6300 unregister_netdev(vsi->netdev);
6301 free_netdev(vsi->netdev);
6302 vsi->netdev = NULL;
6303 }
6304err_netdev:
6305 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6306err_vsi:
6307 i40e_vsi_clear(vsi);
6308err_alloc:
6309 return NULL;
6310}
6311
6312/**
6313 * i40e_veb_get_bw_info - Query VEB BW information
6314 * @veb: the veb to query
6315 *
6316 * Query the Tx scheduler BW configuration data for given VEB
6317 **/
6318static int i40e_veb_get_bw_info(struct i40e_veb *veb)
6319{
6320 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
6321 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
6322 struct i40e_pf *pf = veb->pf;
6323 struct i40e_hw *hw = &pf->hw;
6324 u32 tc_bw_max;
6325 int ret = 0;
6326 int i;
6327
6328 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
6329 &bw_data, NULL);
6330 if (ret) {
6331 dev_info(&pf->pdev->dev,
6332 "query veb bw config failed, aq_err=%d\n",
6333 hw->aq.asq_last_status);
6334 goto out;
6335 }
6336
6337 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
6338 &ets_data, NULL);
6339 if (ret) {
6340 dev_info(&pf->pdev->dev,
6341 "query veb bw ets config failed, aq_err=%d\n",
6342 hw->aq.asq_last_status);
6343 goto out;
6344 }
6345
6346 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
6347 veb->bw_max_quanta = ets_data.tc_bw_max;
6348 veb->is_abs_credits = bw_data.absolute_credits_enable;
6349 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
6350 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
6351 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6352 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
6353 veb->bw_tc_limit_credits[i] =
6354 le16_to_cpu(bw_data.tc_bw_limits[i]);
6355 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
6356 }
6357
6358out:
6359 return ret;
6360}
6361
6362/**
6363 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
6364 * @pf: board private structure
6365 *
6366 * On error: returns error code (negative)
6367 * On success: returns vsi index in PF (positive)
6368 **/
6369static int i40e_veb_mem_alloc(struct i40e_pf *pf)
6370{
6371 int ret = -ENOENT;
6372 struct i40e_veb *veb;
6373 int i;
6374
6375 /* Need to protect the allocation of switch elements at the PF level */
6376 mutex_lock(&pf->switch_mutex);
6377
6378 /* VEB list may be fragmented if VEB creation/destruction has
6379 * been happening. We can afford to do a quick scan to look
6380 * for any free slots in the list.
6381 *
6382 * find next empty veb slot, looping back around if necessary
6383 */
6384 i = 0;
6385 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
6386 i++;
6387 if (i >= I40E_MAX_VEB) {
6388 ret = -ENOMEM;
6389 goto err_alloc_veb; /* out of VEB slots! */
6390 }
6391
6392 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
6393 if (!veb) {
6394 ret = -ENOMEM;
6395 goto err_alloc_veb;
6396 }
6397 veb->pf = pf;
6398 veb->idx = i;
6399 veb->enabled_tc = 1;
6400
6401 pf->veb[i] = veb;
6402 ret = i;
6403err_alloc_veb:
6404 mutex_unlock(&pf->switch_mutex);
6405 return ret;
6406}
6407
6408/**
6409 * i40e_switch_branch_release - Delete a branch of the switch tree
6410 * @branch: where to start deleting
6411 *
6412 * This uses recursion to find the tips of the branch to be
6413 * removed, deleting until we get back to and can delete this VEB.
6414 **/
6415static void i40e_switch_branch_release(struct i40e_veb *branch)
6416{
6417 struct i40e_pf *pf = branch->pf;
6418 u16 branch_seid = branch->seid;
6419 u16 veb_idx = branch->idx;
6420 int i;
6421
6422 /* release any VEBs on this VEB - RECURSION */
6423 for (i = 0; i < I40E_MAX_VEB; i++) {
6424 if (!pf->veb[i])
6425 continue;
6426 if (pf->veb[i]->uplink_seid == branch->seid)
6427 i40e_switch_branch_release(pf->veb[i]);
6428 }
6429
6430 /* Release the VSIs on this VEB, but not the owner VSI.
6431 *
6432 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
6433 * the VEB itself, so don't use (*branch) after this loop.
6434 */
6435 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6436 if (!pf->vsi[i])
6437 continue;
6438 if (pf->vsi[i]->uplink_seid == branch_seid &&
6439 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6440 i40e_vsi_release(pf->vsi[i]);
6441 }
6442 }
6443
6444 /* There's one corner case where the VEB might not have been
6445 * removed, so double check it here and remove it if needed.
6446 * This case happens if the veb was created from the debugfs
6447 * commands and no VSIs were added to it.
6448 */
6449 if (pf->veb[veb_idx])
6450 i40e_veb_release(pf->veb[veb_idx]);
6451}
6452
6453/**
6454 * i40e_veb_clear - remove veb struct
6455 * @veb: the veb to remove
6456 **/
6457static void i40e_veb_clear(struct i40e_veb *veb)
6458{
6459 if (!veb)
6460 return;
6461
6462 if (veb->pf) {
6463 struct i40e_pf *pf = veb->pf;
6464
6465 mutex_lock(&pf->switch_mutex);
6466 if (pf->veb[veb->idx] == veb)
6467 pf->veb[veb->idx] = NULL;
6468 mutex_unlock(&pf->switch_mutex);
6469 }
6470
6471 kfree(veb);
6472}
6473
6474/**
6475 * i40e_veb_release - Delete a VEB and free its resources
6476 * @veb: the VEB being removed
6477 **/
6478void i40e_veb_release(struct i40e_veb *veb)
6479{
6480 struct i40e_vsi *vsi = NULL;
6481 struct i40e_pf *pf;
6482 int i, n = 0;
6483
6484 pf = veb->pf;
6485
6486 /* find the remaining VSI and check for extras */
6487 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6488 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
6489 n++;
6490 vsi = pf->vsi[i];
6491 }
6492 }
6493 if (n != 1) {
6494 dev_info(&pf->pdev->dev,
6495 "can't remove VEB %d with %d VSIs left\n",
6496 veb->seid, n);
6497 return;
6498 }
6499
6500 /* move the remaining VSI to uplink veb */
6501 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
6502 if (veb->uplink_seid) {
6503 vsi->uplink_seid = veb->uplink_seid;
6504 if (veb->uplink_seid == pf->mac_seid)
6505 vsi->veb_idx = I40E_NO_VEB;
6506 else
6507 vsi->veb_idx = veb->veb_idx;
6508 } else {
6509 /* floating VEB */
6510 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6511 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
6512 }
6513
6514 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
6515 i40e_veb_clear(veb);
6516
6517 return;
6518}
6519
6520/**
6521 * i40e_add_veb - create the VEB in the switch
6522 * @veb: the VEB to be instantiated
6523 * @vsi: the controlling VSI
6524 **/
6525static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
6526{
6527 bool is_default = (vsi->idx == vsi->back->lan_vsi);
e1c51b95 6528 bool is_cloud = false;
41c445ff
JB		 6529 int ret;
6530
6531 /* get a VEB from the hardware */
6532 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 6533 veb->enabled_tc, is_default,
6534 is_cloud, &veb->seid, NULL);
41c445ff
JB		 6535 if (ret) {
6536 dev_info(&veb->pf->pdev->dev,
6537 "couldn't add VEB, err %d, aq_err %d\n",
6538 ret, veb->pf->hw.aq.asq_last_status);
6539 return -EPERM;
6540 }
6541
6542 /* get statistics counter */
6543 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
6544 &veb->stats_idx, NULL, NULL, NULL);
6545 if (ret) {
6546 dev_info(&veb->pf->pdev->dev,
6547 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
6548 ret, veb->pf->hw.aq.asq_last_status);
6549 return -EPERM;
6550 }
6551 ret = i40e_veb_get_bw_info(veb);
6552 if (ret) {
6553 dev_info(&veb->pf->pdev->dev,
6554 "couldn't get VEB bw info, err %d, aq_err %d\n",
6555 ret, veb->pf->hw.aq.asq_last_status);
6556 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
6557 return -ENOENT;
6558 }
6559
6560 vsi->uplink_seid = veb->seid;
6561 vsi->veb_idx = veb->idx;
6562 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6563
6564 return 0;
6565}
6566
6567/**
6568 * i40e_veb_setup - Set up a VEB
6569 * @pf: board private structure
6570 * @flags: VEB setup flags
6571 * @uplink_seid: the switch element to link to
6572 * @vsi_seid: the initial VSI seid
6573 * @enabled_tc: Enabled TC bit-map
6574 *
6575 * This allocates the sw VEB structure and links it into the switch
6576 * It is possible and legal for this to be a duplicate of an already
6577 * existing VEB. It is also possible for both uplink and vsi seids
6578 * to be zero, in order to create a floating VEB.
6579 *
6580 * Returns pointer to the successfully allocated VEB sw struct on
6581 * success, otherwise returns NULL on failure.
6582 **/
6583struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
6584 u16 uplink_seid, u16 vsi_seid,
6585 u8 enabled_tc)
6586{
6587 struct i40e_veb *veb, *uplink_veb = NULL;
6588 int vsi_idx, veb_idx;
6589 int ret;
6590
6591 /* if one seid is 0, the other must be 0 to create a floating relay */
6592 if ((uplink_seid == 0 || vsi_seid == 0) &&
6593 (uplink_seid + vsi_seid != 0)) {
6594 dev_info(&pf->pdev->dev,
6595 "one, not both seid's are 0: uplink=%d vsi=%d\n",
6596 uplink_seid, vsi_seid);
6597 return NULL;
6598 }
6599
6600 /* make sure there is such a vsi and uplink */
6601 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
6602 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
6603 break;
6604 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
6605 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
6606 vsi_seid);
6607 return NULL;
6608 }
6609
6610 if (uplink_seid && uplink_seid != pf->mac_seid) {
6611 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6612 if (pf->veb[veb_idx] &&
6613 pf->veb[veb_idx]->seid == uplink_seid) {
6614 uplink_veb = pf->veb[veb_idx];
6615 break;
6616 }
6617 }
6618 if (!uplink_veb) {
6619 dev_info(&pf->pdev->dev,
6620 "uplink seid %d not found\n", uplink_seid);
6621 return NULL;
6622 }
6623 }
6624
6625 /* get veb sw struct */
6626 veb_idx = i40e_veb_mem_alloc(pf);
6627 if (veb_idx < 0)
6628 goto err_alloc;
6629 veb = pf->veb[veb_idx];
6630 veb->flags = flags;
6631 veb->uplink_seid = uplink_seid;
6632 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
6633 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
6634
6635 /* create the VEB in the switch */
6636 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
6637 if (ret)
6638 goto err_veb;
6639
6640 return veb;
6641
6642err_veb:
6643 i40e_veb_clear(veb);
6644err_alloc:
6645 return NULL;
6646}
6647
6648/**
6649 * i40e_setup_pf_switch_element - set pf vars based on switch type
6650 * @pf: board private structure
6651 * @ele: element we are building info from
6652 * @num_reported: total number of elements
6653 * @printconfig: should we print the contents
6654 *
6655 * helper function to assist in extracting a few useful SEID values.
6656 **/
6657static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
6658 struct i40e_aqc_switch_config_element_resp *ele,
6659 u16 num_reported, bool printconfig)
6660{
6661 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
6662 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
6663 u8 element_type = ele->element_type;
6664 u16 seid = le16_to_cpu(ele->seid);
6665
6666 if (printconfig)
6667 dev_info(&pf->pdev->dev,
6668 "type=%d seid=%d uplink=%d downlink=%d\n",
6669 element_type, seid, uplink_seid, downlink_seid);
6670
6671 switch (element_type) {
6672 case I40E_SWITCH_ELEMENT_TYPE_MAC:
6673 pf->mac_seid = seid;
6674 break;
6675 case I40E_SWITCH_ELEMENT_TYPE_VEB:
6676 /* Main VEB? */
6677 if (uplink_seid != pf->mac_seid)
6678 break;
6679 if (pf->lan_veb == I40E_NO_VEB) {
6680 int v;
6681
6682 /* find existing or else empty VEB */
6683 for (v = 0; v < I40E_MAX_VEB; v++) {
6684 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
6685 pf->lan_veb = v;
6686 break;
6687 }
6688 }
6689 if (pf->lan_veb == I40E_NO_VEB) {
6690 v = i40e_veb_mem_alloc(pf);
6691 if (v < 0)
6692 break;
6693 pf->lan_veb = v;
6694 }
6695 }
6696
6697 pf->veb[pf->lan_veb]->seid = seid;
6698 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
6699 pf->veb[pf->lan_veb]->pf = pf;
6700 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
6701 break;
6702 case I40E_SWITCH_ELEMENT_TYPE_VSI:
6703 if (num_reported != 1)
6704 break;
6705 /* This is immediately after a reset so we can assume this is
6706 * the PF's VSI
6707 */
6708 pf->mac_seid = uplink_seid;
6709 pf->pf_seid = downlink_seid;
6710 pf->main_vsi_seid = seid;
6711 if (printconfig)
6712 dev_info(&pf->pdev->dev,
6713 "pf_seid=%d main_vsi_seid=%d\n",
6714 pf->pf_seid, pf->main_vsi_seid);
6715 break;
6716 case I40E_SWITCH_ELEMENT_TYPE_PF:
6717 case I40E_SWITCH_ELEMENT_TYPE_VF:
6718 case I40E_SWITCH_ELEMENT_TYPE_EMP:
6719 case I40E_SWITCH_ELEMENT_TYPE_BMC:
6720 case I40E_SWITCH_ELEMENT_TYPE_PE:
6721 case I40E_SWITCH_ELEMENT_TYPE_PA:
6722 /* ignore these for now */
6723 break;
6724 default:
6725 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
6726 element_type, seid);
6727 break;
6728 }
6729}
6730
6731/**
6732 * i40e_fetch_switch_configuration - Get switch config from firmware
6733 * @pf: board private structure
6734 * @printconfig: should we print the contents
6735 *
6736 * Get the current switch configuration from the device and
6737 * extract a few useful SEID values.
6738 **/
6739int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
6740{
6741 struct i40e_aqc_get_switch_config_resp *sw_config;
6742 u16 next_seid = 0;
6743 int ret = 0;
6744 u8 *aq_buf;
6745 int i;
6746
6747 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
6748 if (!aq_buf)
6749 return -ENOMEM;
6750
6751 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
6752 do {
6753 u16 num_reported, num_total;
6754
6755 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
6756 I40E_AQ_LARGE_BUF,
6757 &next_seid, NULL);
6758 if (ret) {
6759 dev_info(&pf->pdev->dev,
6760 "get switch config failed %d aq_err=%x\n",
6761 ret, pf->hw.aq.asq_last_status);
6762 kfree(aq_buf);
6763 return -ENOENT;
6764 }
6765
6766 num_reported = le16_to_cpu(sw_config->header.num_reported);
6767 num_total = le16_to_cpu(sw_config->header.num_total);
6768
6769 if (printconfig)
6770 dev_info(&pf->pdev->dev,
6771 "header: %d reported %d total\n",
6772 num_reported, num_total);
6773
6774 if (num_reported) {
6775 int sz = sizeof(*sw_config) * num_reported;
6776
6777 kfree(pf->sw_config);
6778 pf->sw_config = kzalloc(sz, GFP_KERNEL);
6779 if (pf->sw_config)
6780 memcpy(pf->sw_config, sw_config, sz);
6781 }
6782
6783 for (i = 0; i < num_reported; i++) {
6784 struct i40e_aqc_switch_config_element_resp *ele =
6785 &sw_config->element[i];
6786
6787 i40e_setup_pf_switch_element(pf, ele, num_reported,
6788 printconfig);
6789 }
6790 } while (next_seid != 0);
6791
6792 kfree(aq_buf);
6793 return ret;
6794}
6795
6796/**
6797 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
6798 * @pf: board private structure
6799 *
6800 * Returns 0 on success, negative value on failure
6801 **/
6802static int i40e_setup_pf_switch(struct i40e_pf *pf)
6803{
6804 int ret;
6805
6806 /* find out what's out there already */
6807 ret = i40e_fetch_switch_configuration(pf, false);
6808 if (ret) {
6809 dev_info(&pf->pdev->dev,
6810 "couldn't fetch switch config, err %d, aq_err %d\n",
6811 ret, pf->hw.aq.asq_last_status);
6812 return ret;
6813 }
6814 i40e_pf_reset_stats(pf);
6815
6816 /* fdir VSI must happen first to be sure it gets queue 0, but only
6817 * if there is enough room for the fdir VSI
6818 */
6819 if (pf->num_lan_qps > 1)
6820 i40e_fdir_setup(pf);
6821
6822 /* first time setup */
6823 if (pf->lan_vsi == I40E_NO_VSI) {
6824 struct i40e_vsi *vsi = NULL;
6825 u16 uplink_seid;
6826
6827 /* Set up the PF VSI associated with the PF's main VSI
6828 * that is already in the HW switch
6829 */
6830 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6831 uplink_seid = pf->veb[pf->lan_veb]->seid;
6832 else
6833 uplink_seid = pf->mac_seid;
6834
6835 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
6836 if (!vsi) {
6837 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
6838 i40e_fdir_teardown(pf);
6839 return -EAGAIN;
6840 }
6841 /* accommodate kcompat by copying the main VSI queue count
6842 * into the pf, since this newer code pushes the pf queue
6843 * info down a level into a VSI
6844 */
6845 pf->num_rx_queues = vsi->alloc_queue_pairs;
6846 pf->num_tx_queues = vsi->alloc_queue_pairs;
6847 } else {
6848 /* force a reset of TC and queue layout configurations */
6849 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6850 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6851 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6852 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6853 }
6854 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
6855
6856 /* Setup static PF queue filter control settings */
6857 ret = i40e_setup_pf_filter_control(pf);
6858 if (ret) {
6859 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
6860 ret);
6861 /* Failure here should not stop continuing other steps */
6862 }
6863
6864 /* enable RSS in the HW, even for only one queue, as the stack can use
6865 * the hash
6866 */
6867 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
6868 i40e_config_rss(pf);
6869
6870 /* fill in link information and enable LSE reporting */
6871 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
6872 i40e_link_event(pf);
6873
6874 /* Initialize user-specifics link properties */
6875 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
6876 I40E_AQ_AN_COMPLETED) ? true : false);
6877 pf->hw.fc.requested_mode = I40E_FC_DEFAULT;
6878 if (pf->hw.phy.link_info.an_info &
6879 (I40E_AQ_LINK_PAUSE_TX | I40E_AQ_LINK_PAUSE_RX))
6880 pf->hw.fc.current_mode = I40E_FC_FULL;
6881 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
6882 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
6883 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
6884 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
6885 else
6886 pf->hw.fc.current_mode = I40E_FC_DEFAULT;
6887
6888 return ret;
6889}
6890
6891/**
6892 * i40e_set_rss_size - helper to set rss_size
6893 * @pf: board private structure
6894 * @queues_left: how many queues
6895 */
6896static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
6897{
6898 int num_tc0;
6899
6900 num_tc0 = min_t(int, queues_left, pf->rss_size_max);
6901 num_tc0 = min_t(int, num_tc0, nr_cpus_node(numa_node_id()));
6902 num_tc0 = rounddown_pow_of_two(num_tc0);
6903
6904 return num_tc0;
6905}
6906
6907/**
6908 * i40e_determine_queue_usage - Work out queue distribution
6909 * @pf: board private structure
6910 **/
6911static void i40e_determine_queue_usage(struct i40e_pf *pf)
6912{
6913 int accum_tc_size;
6914 int queues_left;
6915
6916 pf->num_lan_qps = 0;
6917 pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
6918 accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
6919
6920 /* Find the max queues to be put into basic use. We'll always be
6921 * using TC0, whether or not DCB is running, and TC0 will get the
6922 * big RSS set.
6923 */
6924 queues_left = pf->hw.func_caps.num_tx_qp;
6925
6926 if (!((pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6927 (pf->flags & I40E_FLAG_MQ_ENABLED)) ||
6928 !(pf->flags & (I40E_FLAG_RSS_ENABLED |
6929 I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
6930 (queues_left == 1)) {
6931
6932 /* one qp for PF, no queues for anything else */
6933 queues_left = 0;
6934 pf->rss_size = pf->num_lan_qps = 1;
6935
6936 /* make sure all the fancies are disabled */
6937 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
6938 I40E_FLAG_MQ_ENABLED |
6939 I40E_FLAG_FDIR_ENABLED |
6940 I40E_FLAG_FDIR_ATR_ENABLED |
6941 I40E_FLAG_DCB_ENABLED |
6942 I40E_FLAG_SRIOV_ENABLED |
6943 I40E_FLAG_VMDQ_ENABLED);
6944
6945 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
6946 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
6947 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
6948
6949 pf->rss_size = i40e_set_rss_size(pf, queues_left);
6950
6951 queues_left -= pf->rss_size;
6952 pf->num_lan_qps = pf->rss_size;
6953
6954 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
6955 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
6956 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
6957
6958 /* save num_tc_qps queues for TCs 1 thru 7 and the rest
6959 * are set up for RSS in TC0
6960 */
6961 queues_left -= accum_tc_size;
6962
6963 pf->rss_size = i40e_set_rss_size(pf, queues_left);
6964
6965 queues_left -= pf->rss_size;
6966 if (queues_left < 0) {
6967 dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
6968 return;
6969 }
6970
6971 pf->num_lan_qps = pf->rss_size + accum_tc_size;
6972
6973 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
6974 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
6975 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
6976
6977 queues_left -= 1; /* save 1 queue for FD */
6978
6979 pf->rss_size = i40e_set_rss_size(pf, queues_left);
6980
6981 queues_left -= pf->rss_size;
6982 if (queues_left < 0) {
6983 dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
6984 return;
6985 }
6986
6987 pf->num_lan_qps = pf->rss_size;
6988
6989 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
6990 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
6991 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
6992
6993 /* save 1 queue for TCs 1 thru 7,
6994 * 1 queue for flow director,
6995 * and the rest are set up for RSS in TC0
6996 */
6997 queues_left -= 1;
6998 queues_left -= accum_tc_size;
6999
7000 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7001 queues_left -= pf->rss_size;
7002 if (queues_left < 0) {
7003 dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
7004 return;
7005 }
7006
7007 pf->num_lan_qps = pf->rss_size + accum_tc_size;
7008
7009 } else {
7010 dev_info(&pf->pdev->dev,
7011 "Invalid configuration, flags=0x%08llx\n", pf->flags);
7012 return;
7013 }
7014
7015 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7016 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
7017 pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
7018 pf->num_vf_qps));
7019 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7020 }
7021
7022 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7023 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7024 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7025 (queues_left / pf->num_vmdq_qps));
7026 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7027 }
7028
7029 return;
7030}
7031
7032/**
7033 * i40e_setup_pf_filter_control - Setup PF static filter control
7034 * @pf: PF to be setup
7035 *
7036 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7037 * settings. If PE/FCoE are enabled then it will also set the per PF
7038 * based filter sizes required for them. It also enables Flow director,
7039 * ethertype and macvlan type filter settings for the pf.
7040 *
7041 * Returns 0 on success, negative on failure
7042 **/
7043static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7044{
7045 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7046
7047 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7048
7049 /* Flow Director is enabled */
7050 if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
7051 settings->enable_fdir = true;
7052
7053 /* Ethtype and MACVLAN filters enabled for PF */
7054 settings->enable_ethtype = true;
7055 settings->enable_macvlan = true;
7056
7057 if (i40e_set_filter_control(&pf->hw, settings))
7058 return -ENOENT;
7059
7060 return 0;
7061}
7062
7063/**
7064 * i40e_probe - Device initialization routine
7065 * @pdev: PCI device information struct
7066 * @ent: entry in i40e_pci_tbl
7067 *
7068 * i40e_probe initializes a pf identified by a pci_dev structure.
7069 * The OS initialization, configuring of the pf private structure,
7070 * and a hardware reset occur.
7071 *
7072 * Returns 0 on success, negative on failure
7073 **/
7074static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7075{
7076 struct i40e_driver_version dv;
7077 struct i40e_pf *pf;
7078 struct i40e_hw *hw;
7079 int err = 0;
7080 u32 len;
7081
7082 err = pci_enable_device_mem(pdev);
7083 if (err)
7084 return err;
7085
7086 /* set up for high or low dma */
7087 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7088 /* coherent mask for the same size will always succeed if
7089 * dma_set_mask does
7090 */
7091 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7092 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7093 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7094 } else {
7095 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7096 err = -EIO;
7097 goto err_dma;
7098 }
7099
7100 /* set up pci connections */
7101 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7102 IORESOURCE_MEM), i40e_driver_name);
7103 if (err) {
7104 dev_info(&pdev->dev,
7105 "pci_request_selected_regions failed %d\n", err);
7106 goto err_pci_reg;
7107 }
7108
7109 pci_enable_pcie_error_reporting(pdev);
7110 pci_set_master(pdev);
7111
7112 /* Now that we have a PCI connection, we need to do the
7113 * low level device setup. This is primarily setting up
7114 * the Admin Queue structures and then querying for the
7115 * device's current profile information.
7116 */
7117 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7118 if (!pf) {
7119 err = -ENOMEM;
7120 goto err_pf_alloc;
7121 }
7122 pf->next_vsi = 0;
7123 pf->pdev = pdev;
7124 set_bit(__I40E_DOWN, &pf->state);
7125
7126 hw = &pf->hw;
7127 hw->back = pf;
7128 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7129 pci_resource_len(pdev, 0));
7130 if (!hw->hw_addr) {
7131 err = -EIO;
7132 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7133 (unsigned int)pci_resource_start(pdev, 0),
7134 (unsigned int)pci_resource_len(pdev, 0), err);
7135 goto err_ioremap;
7136 }
7137 hw->vendor_id = pdev->vendor;
7138 hw->device_id = pdev->device;
7139 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7140 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7141 hw->subsystem_device_id = pdev->subsystem_device;
7142 hw->bus.device = PCI_SLOT(pdev->devfn);
7143 hw->bus.func = PCI_FUNC(pdev->devfn);
7144
7145 /* Reset here to make sure all is clean and to define PF 'n' */
7146 err = i40e_pf_reset(hw);
7147 if (err) {
7148 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7149 goto err_pf_reset;
7150 }
7151 pf->pfr_count++;
7152
7153 hw->aq.num_arq_entries = I40E_AQ_LEN;
7154 hw->aq.num_asq_entries = I40E_AQ_LEN;
7155 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7156 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7157 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7158 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7159 "%s-pf%d:misc",
7160 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7161
7162 err = i40e_init_shared_code(hw);
7163 if (err) {
7164 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7165 goto err_pf_reset;
7166 }
7167
7168 err = i40e_init_adminq(hw);
7169 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7170 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7171 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7172 dev_info(&pdev->dev,
7173 "warning: NVM version not supported, supported version: %02x.%02x\n",
7174 I40E_CURRENT_NVM_VERSION_HI,
7175 I40E_CURRENT_NVM_VERSION_LO);
7176 }
41c445ff
JB		 7177 if (err) {
7178 dev_info(&pdev->dev,
7179 "init_adminq failed: %d expecting API %02x.%02x\n",
7180 err,
7181 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7182 goto err_pf_reset;
7183 }
7184
7185 err = i40e_get_capabilities(pf);
7186 if (err)
7187 goto err_adminq_setup;
7188
7189 err = i40e_sw_init(pf);
7190 if (err) {
7191 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7192 goto err_sw_init;
7193 }
7194
7195 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7196 hw->func_caps.num_rx_qp,
7197 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7198 if (err) {
7199 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7200 goto err_init_lan_hmc;
7201 }
7202
7203 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7204 if (err) {
7205 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7206 err = -ENOENT;
7207 goto err_configure_lan_hmc;
7208 }
7209
7210 i40e_get_mac_addr(hw, hw->mac.addr);
7211 if (i40e_validate_mac_addr(hw->mac.addr)) {
7212 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7213 err = -EIO;
7214 goto err_mac_addr;
7215 }
7216 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7217 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7218
7219 pci_set_drvdata(pdev, pf);
7220 pci_save_state(pdev);
7221
7222 /* set up periodic task facility */
7223 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7224 pf->service_timer_period = HZ;
7225
7226 INIT_WORK(&pf->service_task, i40e_service_task);
7227 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
7228 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
7229 pf->link_check_timeout = jiffies;
7230
7231 /* set up the main switch operations */
7232 i40e_determine_queue_usage(pf);
7233 i40e_init_interrupt_scheme(pf);
7234
7235 /* Set up the *vsi struct based on the number of VSIs in the HW,
7236 * and set up our local tracking of the MAIN PF vsi.
7237 */
7238 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
7239 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 7240 if (!pf->vsi) {
7241 err = -ENOMEM;
41c445ff 7242 goto err_switch_setup;
ed87ac09 7243 }
41c445ff
JB		 7244
7245 err = i40e_setup_pf_switch(pf);
7246 if (err) {
7247 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
7248 goto err_vsis;
7249 }
7250
7251 /* The main driver is (mostly) up and happy. We need to set this state
7252 * before setting up the misc vector or we get a race and the vector
7253 * ends up disabled forever.
7254 */
7255 clear_bit(__I40E_DOWN, &pf->state);
7256
7257 /* In case of MSIX we are going to setup the misc vector right here
7258 * to handle admin queue events etc. In case of legacy and MSI
7259 * the misc functionality and queue processing is combined in
7260 * the same vector and that gets setup at open.
7261 */
7262 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7263 err = i40e_setup_misc_vector(pf);
7264 if (err) {
7265 dev_info(&pdev->dev,
7266 "setup of misc vector failed: %d\n", err);
7267 goto err_vsis;
7268 }
7269 }
7270
7271 /* prep for VF support */
7272 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7273 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
7274 u32 val;
7275
7276 /* disable link interrupts for VFs */
7277 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
7278 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
7279 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
7280 i40e_flush(hw);
7281 }
7282
7283 i40e_dbg_pf_init(pf);
7284
7285 /* tell the firmware that we're starting */
7286 dv.major_version = DRV_VERSION_MAJOR;
7287 dv.minor_version = DRV_VERSION_MINOR;
7288 dv.build_version = DRV_VERSION_BUILD;
7289 dv.subbuild_version = 0;
7290 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
7291
7292 /* since everything's happy, start the service_task timer */
7293 mod_timer(&pf->service_timer,
7294 round_jiffies(jiffies + pf->service_timer_period));
7295
7296 return 0;
7297
7298 /* Unwind what we've done if something failed in the setup */
7299err_vsis:
7300 set_bit(__I40E_DOWN, &pf->state);
7301err_switch_setup:
7302 i40e_clear_interrupt_scheme(pf);
7303 kfree(pf->vsi);
7304 del_timer_sync(&pf->service_timer);
7305err_mac_addr:
7306err_configure_lan_hmc:
7307 (void)i40e_shutdown_lan_hmc(hw);
7308err_init_lan_hmc:
7309 kfree(pf->qp_pile);
7310 kfree(pf->irq_pile);
7311err_sw_init:
7312err_adminq_setup:
7313 (void)i40e_shutdown_adminq(hw);
7314err_pf_reset:
7315 iounmap(hw->hw_addr);
7316err_ioremap:
7317 kfree(pf);
7318err_pf_alloc:
7319 pci_disable_pcie_error_reporting(pdev);
7320 pci_release_selected_regions(pdev,
7321 pci_select_bars(pdev, IORESOURCE_MEM));
7322err_pci_reg:
7323err_dma:
7324 pci_disable_device(pdev);
7325 return err;
7326}
7327
7328/**
7329 * i40e_remove - Device removal routine
7330 * @pdev: PCI device information struct
7331 *
7332 * i40e_remove is called by the PCI subsystem to alert the driver
7333 * that is should release a PCI device. This could be caused by a
7334 * Hot-Plug event, or because the driver is going to be removed from
7335 * memory.
7336 **/
7337static void i40e_remove(struct pci_dev *pdev)
7338{
7339 struct i40e_pf *pf = pci_get_drvdata(pdev);
7340 i40e_status ret_code;
7341 u32 reg;
7342 int i;
7343
7344 i40e_dbg_pf_exit(pf);
7345
7346 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7347 i40e_free_vfs(pf);
7348 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
7349 }
7350
7351 /* no more scheduling of any task */
7352 set_bit(__I40E_DOWN, &pf->state);
7353 del_timer_sync(&pf->service_timer);
7354 cancel_work_sync(&pf->service_task);
7355
7356 i40e_fdir_teardown(pf);
7357
7358 /* If there is a switch structure or any orphans, remove them.
7359 * This will leave only the PF's VSI remaining.
7360 */
7361 for (i = 0; i < I40E_MAX_VEB; i++) {
7362 if (!pf->veb[i])
7363 continue;
7364
7365 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
7366 pf->veb[i]->uplink_seid == 0)
7367 i40e_switch_branch_release(pf->veb[i]);
7368 }
7369
7370 /* Now we can shutdown the PF's VSI, just before we kill
7371 * adminq and hmc.
7372 */
7373 if (pf->vsi[pf->lan_vsi])
7374 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
7375
7376 i40e_stop_misc_vector(pf);
7377 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7378 synchronize_irq(pf->msix_entries[0].vector);
7379 free_irq(pf->msix_entries[0].vector, pf);
7380 }
7381
7382 /* shutdown and destroy the HMC */
7383 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
7384 if (ret_code)
7385 dev_warn(&pdev->dev,
7386 "Failed to destroy the HMC resources: %d\n", ret_code);
7387
7388 /* shutdown the adminq */
7389 i40e_aq_queue_shutdown(&pf->hw, true);
7390 ret_code = i40e_shutdown_adminq(&pf->hw);
7391 if (ret_code)
7392 dev_warn(&pdev->dev,
7393 "Failed to destroy the Admin Queue resources: %d\n",
7394 ret_code);
7395
7396 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
7397 i40e_clear_interrupt_scheme(pf);
7398 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7399 if (pf->vsi[i]) {
7400 i40e_vsi_clear_rings(pf->vsi[i]);
7401 i40e_vsi_clear(pf->vsi[i]);
7402 pf->vsi[i] = NULL;
7403 }
7404 }
7405
7406 for (i = 0; i < I40E_MAX_VEB; i++) {
7407 kfree(pf->veb[i]);
7408 pf->veb[i] = NULL;
7409 }
7410
7411 kfree(pf->qp_pile);
7412 kfree(pf->irq_pile);
7413 kfree(pf->sw_config);
7414 kfree(pf->vsi);
7415
7416 /* force a PF reset to clean anything leftover */
7417 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
7418 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7419 i40e_flush(&pf->hw);
7420
7421 iounmap(pf->hw.hw_addr);
7422 kfree(pf);
7423 pci_release_selected_regions(pdev,
7424 pci_select_bars(pdev, IORESOURCE_MEM));
7425
7426 pci_disable_pcie_error_reporting(pdev);
7427 pci_disable_device(pdev);
7428}
7429
7430/**
7431 * i40e_pci_error_detected - warning that something funky happened in PCI land
7432 * @pdev: PCI device information struct
7433 *
7434 * Called to warn that something happened and the error handling steps
7435 * are in progress. Allows the driver to quiesce things, be ready for
7436 * remediation.
7437 **/
7438static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
7439 enum pci_channel_state error)
7440{
7441 struct i40e_pf *pf = pci_get_drvdata(pdev);
7442
7443 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
7444
7445 /* shutdown all operations */
7446 i40e_pf_quiesce_all_vsi(pf);
7447
7448 /* Request a slot reset */
7449 return PCI_ERS_RESULT_NEED_RESET;
7450}
7451
7452/**
7453 * i40e_pci_error_slot_reset - a PCI slot reset just happened
7454 * @pdev: PCI device information struct
7455 *
7456 * Called to find if the driver can work with the device now that
7457 * the pci slot has been reset. If a basic connection seems good
7458 * (registers are readable and have sane content) then return a
7459 * happy little PCI_ERS_RESULT_xxx.
7460 **/
7461static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
7462{
7463 struct i40e_pf *pf = pci_get_drvdata(pdev);
7464 pci_ers_result_t result;
7465 int err;
7466 u32 reg;
7467
7468 dev_info(&pdev->dev, "%s\n", __func__);
7469 if (pci_enable_device_mem(pdev)) {
7470 dev_info(&pdev->dev,
7471 "Cannot re-enable PCI device after reset.\n");
7472 result = PCI_ERS_RESULT_DISCONNECT;
7473 } else {
7474 pci_set_master(pdev);
7475 pci_restore_state(pdev);
7476 pci_save_state(pdev);
7477 pci_wake_from_d3(pdev, false);
7478
7479 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7480 if (reg == 0)
7481 result = PCI_ERS_RESULT_RECOVERED;
7482 else
7483 result = PCI_ERS_RESULT_DISCONNECT;
7484 }
7485
7486 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7487 if (err) {
7488 dev_info(&pdev->dev,
7489 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7490 err);
7491 /* non-fatal, continue */
7492 }
7493
7494 return result;
7495}
7496
7497/**
7498 * i40e_pci_error_resume - restart operations after PCI error recovery
7499 * @pdev: PCI device information struct
7500 *
7501 * Called to allow the driver to bring things back up after PCI error
7502 * and/or reset recovery has finished.
7503 **/
7504static void i40e_pci_error_resume(struct pci_dev *pdev)
7505{
7506 struct i40e_pf *pf = pci_get_drvdata(pdev);
7507
7508 dev_info(&pdev->dev, "%s\n", __func__);
7509 i40e_handle_reset_warning(pf);
7510}
7511
7512static const struct pci_error_handlers i40e_err_handler = {
7513 .error_detected = i40e_pci_error_detected,
7514 .slot_reset = i40e_pci_error_slot_reset,
7515 .resume = i40e_pci_error_resume,
7516};
7517
7518static struct pci_driver i40e_driver = {
7519 .name = i40e_driver_name,
7520 .id_table = i40e_pci_tbl,
7521 .probe = i40e_probe,
7522 .remove = i40e_remove,
7523 .err_handler = &i40e_err_handler,
7524 .sriov_configure = i40e_pci_sriov_configure,
7525};
7526
7527/**
7528 * i40e_init_module - Driver registration routine
7529 *
7530 * i40e_init_module is the first routine called when the driver is
7531 * loaded. All it does is register with the PCI subsystem.
7532 **/
7533static int __init i40e_init_module(void)
7534{
7535 pr_info("%s: %s - version %s\n", i40e_driver_name,
7536 i40e_driver_string, i40e_driver_version_str);
7537 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
7538 i40e_dbg_init();
7539 return pci_register_driver(&i40e_driver);
7540}
7541module_init(i40e_init_module);
7542
7543/**
7544 * i40e_exit_module - Driver exit cleanup routine
7545 *
7546 * i40e_exit_module is called just before the driver is removed
7547 * from memory.
7548 **/
7549static void __exit i40e_exit_module(void)
7550{
7551 pci_unregister_driver(&i40e_driver);
7552 i40e_dbg_exit();
7553}
7554module_exit(i40e_exit_module);
Linux kernel - Deliverables
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