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i40e: Implement the API function for aq_set_switch_config
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
2818ccd9 4 * Copyright(c) 2013 - 2016 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
b499ffb0
SV		 27#include <linux/etherdevice.h>
28#include <linux/of_net.h>
29#include <linux/pci.h>
30
41c445ff
JB		 31/* Local includes */
32#include "i40e.h"
4eb3f768 33#include "i40e_diag.h"
6a899024 34#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 35#include <net/vxlan.h>
36#endif
6a899024
SA		 37#if IS_ENABLED(CONFIG_GENEVE)
38#include <net/geneve.h>
39#endif
41c445ff
JB		 40
41const char i40e_driver_name[] = "i40e";
42static const char i40e_driver_string[] =
43 "Intel(R) Ethernet Connection XL710 Network Driver";
44
45#define DRV_KERN "-k"
46
e8e724db 47#define DRV_VERSION_MAJOR 1
50f26a50 48#define DRV_VERSION_MINOR 5
5a6fc256 49#define DRV_VERSION_BUILD 10
41c445ff
JB		 50#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
51 __stringify(DRV_VERSION_MINOR) "." \
52 __stringify(DRV_VERSION_BUILD) DRV_KERN
53const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 54static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 55
56/* a bit of forward declarations */
57static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
58static void i40e_handle_reset_warning(struct i40e_pf *pf);
59static int i40e_add_vsi(struct i40e_vsi *vsi);
60static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 61static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 62static int i40e_setup_misc_vector(struct i40e_pf *pf);
63static void i40e_determine_queue_usage(struct i40e_pf *pf);
64static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 65static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
66 u16 rss_table_size, u16 rss_size);
cbf61325 67static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 68static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 69
70/* i40e_pci_tbl - PCI Device ID Table
71 *
72 * Last entry must be all 0s
73 *
74 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
75 * Class, Class Mask, private data (not used) }
76 */
9baa3c34 77static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
ab60085e
SN		 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
35dae51d
ASJ		 88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
87e6c1d7
ASJ		 90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
91 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
92 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
d6bf58c2 93 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},
a3aa5036 94 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_I_X722), 0},
48a3b512
SN		 95 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
96 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 97 /* required last entry */
98 {0, }
99};
100MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
101
102#define I40E_MAX_VF_COUNT 128
103static int debug = -1;
104module_param(debug, int, 0);
105MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
106
107MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
108MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
109MODULE_LICENSE("GPL");
110MODULE_VERSION(DRV_VERSION);
111
2803b16c
JB		 112static struct workqueue_struct *i40e_wq;
113
41c445ff
JB		 114/**
115 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to fill out
118 * @size: size of memory requested
119 * @alignment: what to align the allocation to
120 **/
121int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
122 u64 size, u32 alignment)
123{
124 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
125
126 mem->size = ALIGN(size, alignment);
127 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
128 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 129 if (!mem->va)
130 return -ENOMEM;
41c445ff 131
93bc73b8 132 return 0;
41c445ff
JB		 133}
134
135/**
136 * i40e_free_dma_mem_d - OS specific memory free for shared code
137 * @hw: pointer to the HW structure
138 * @mem: ptr to mem struct to free
139 **/
140int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
141{
142 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
143
144 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
145 mem->va = NULL;
146 mem->pa = 0;
147 mem->size = 0;
148
149 return 0;
150}
151
152/**
153 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
154 * @hw: pointer to the HW structure
155 * @mem: ptr to mem struct to fill out
156 * @size: size of memory requested
157 **/
158int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
159 u32 size)
160{
161 mem->size = size;
162 mem->va = kzalloc(size, GFP_KERNEL);
163
93bc73b8
JB		 164 if (!mem->va)
165 return -ENOMEM;
41c445ff 166
93bc73b8 167 return 0;
41c445ff
JB		 168}
169
170/**
171 * i40e_free_virt_mem_d - OS specific memory free for shared code
172 * @hw: pointer to the HW structure
173 * @mem: ptr to mem struct to free
174 **/
175int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
176{
177 /* it's ok to kfree a NULL pointer */
178 kfree(mem->va);
179 mem->va = NULL;
180 mem->size = 0;
181
182 return 0;
183}
184
185/**
186 * i40e_get_lump - find a lump of free generic resource
187 * @pf: board private structure
188 * @pile: the pile of resource to search
189 * @needed: the number of items needed
190 * @id: an owner id to stick on the items assigned
191 *
192 * Returns the base item index of the lump, or negative for error
193 *
194 * The search_hint trick and lack of advanced fit-finding only work
195 * because we're highly likely to have all the same size lump requests.
196 * Linear search time and any fragmentation should be minimal.
197 **/
198static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
199 u16 needed, u16 id)
200{
201 int ret = -ENOMEM;
ddf434ac 202 int i, j;
41c445ff
JB		 203
204 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
205 dev_info(&pf->pdev->dev,
206 "param err: pile=%p needed=%d id=0x%04x\n",
207 pile, needed, id);
208 return -EINVAL;
209 }
210
211 /* start the linear search with an imperfect hint */
212 i = pile->search_hint;
ddf434ac 213 while (i < pile->num_entries) {
41c445ff
JB		 214 /* skip already allocated entries */
215 if (pile->list[i] & I40E_PILE_VALID_BIT) {
216 i++;
217 continue;
218 }
219
220 /* do we have enough in this lump? */
221 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
222 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
223 break;
224 }
225
226 if (j == needed) {
227 /* there was enough, so assign it to the requestor */
228 for (j = 0; j < needed; j++)
229 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
230 ret = i;
231 pile->search_hint = i + j;
ddf434ac 232 break;
41c445ff 233 }
6995b36c
JB		 234
235 /* not enough, so skip over it and continue looking */
236 i += j;
41c445ff
JB		 237 }
238
239 return ret;
240}
241
242/**
243 * i40e_put_lump - return a lump of generic resource
244 * @pile: the pile of resource to search
245 * @index: the base item index
246 * @id: the owner id of the items assigned
247 *
248 * Returns the count of items in the lump
249 **/
250static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
251{
252 int valid_id = (id | I40E_PILE_VALID_BIT);
253 int count = 0;
254 int i;
255
256 if (!pile || index >= pile->num_entries)
257 return -EINVAL;
258
259 for (i = index;
260 i < pile->num_entries && pile->list[i] == valid_id;
261 i++) {
262 pile->list[i] = 0;
263 count++;
264 }
265
266 if (count && index < pile->search_hint)
267 pile->search_hint = index;
268
269 return count;
270}
271
fdf0e0bf
ASJ		 272/**
273 * i40e_find_vsi_from_id - searches for the vsi with the given id
274 * @pf - the pf structure to search for the vsi
275 * @id - id of the vsi it is searching for
276 **/
277struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
278{
279 int i;
280
281 for (i = 0; i < pf->num_alloc_vsi; i++)
282 if (pf->vsi[i] && (pf->vsi[i]->id == id))
283 return pf->vsi[i];
284
285 return NULL;
286}
287
41c445ff
JB		 288/**
289 * i40e_service_event_schedule - Schedule the service task to wake up
290 * @pf: board private structure
291 *
292 * If not already scheduled, this puts the task into the work queue
293 **/
e3219ce6 294void i40e_service_event_schedule(struct i40e_pf *pf)
41c445ff
JB		 295{
296 if (!test_bit(__I40E_DOWN, &pf->state) &&
297 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
298 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
2803b16c 299 queue_work(i40e_wq, &pf->service_task);
41c445ff
JB		 300}
301
302/**
303 * i40e_tx_timeout - Respond to a Tx Hang
304 * @netdev: network interface device structure
305 *
306 * If any port has noticed a Tx timeout, it is likely that the whole
307 * device is munged, not just the one netdev port, so go for the full
308 * reset.
309 **/
38e00438
VD		 310#ifdef I40E_FCOE
311void i40e_tx_timeout(struct net_device *netdev)
312#else
41c445ff 313static void i40e_tx_timeout(struct net_device *netdev)
38e00438 314#endif
41c445ff
JB		 315{
316 struct i40e_netdev_priv *np = netdev_priv(netdev);
317 struct i40e_vsi *vsi = np->vsi;
318 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 319 struct i40e_ring *tx_ring = NULL;
320 unsigned int i, hung_queue = 0;
321 u32 head, val;
41c445ff
JB		 322
323 pf->tx_timeout_count++;
324
b03a8c1f
KP		 325 /* find the stopped queue the same way the stack does */
326 for (i = 0; i < netdev->num_tx_queues; i++) {
327 struct netdev_queue *q;
328 unsigned long trans_start;
329
330 q = netdev_get_tx_queue(netdev, i);
9b36627a 331 trans_start = q->trans_start;
b03a8c1f
KP		 332 if (netif_xmit_stopped(q) &&
333 time_after(jiffies,
334 (trans_start + netdev->watchdog_timeo))) {
335 hung_queue = i;
336 break;
337 }
338 }
339
340 if (i == netdev->num_tx_queues) {
341 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
342 } else {
343 /* now that we have an index, find the tx_ring struct */
344 for (i = 0; i < vsi->num_queue_pairs; i++) {
345 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
346 if (hung_queue ==
347 vsi->tx_rings[i]->queue_index) {
348 tx_ring = vsi->tx_rings[i];
349 break;
350 }
351 }
352 }
353 }
354
41c445ff 355 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 356 pf->tx_timeout_recovery_level = 1; /* reset after some time */
357 else if (time_before(jiffies,
358 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
359 return; /* don't do any new action before the next timeout */
360
361 if (tx_ring) {
362 head = i40e_get_head(tx_ring);
363 /* Read interrupt register */
364 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
365 val = rd32(&pf->hw,
366 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
367 tx_ring->vsi->base_vector - 1));
368 else
369 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
370
371 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
372 vsi->seid, hung_queue, tx_ring->next_to_clean,
373 head, tx_ring->next_to_use,
374 readl(tx_ring->tail), val);
375 }
376
41c445ff 377 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 378 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
379 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 380
381 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 382 case 1:
383 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
384 break;
385 case 2:
386 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
387 break;
388 case 3:
389 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
390 break;
391 default:
392 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 393 break;
394 }
b03a8c1f 395
41c445ff
JB		 396 i40e_service_event_schedule(pf);
397 pf->tx_timeout_recovery_level++;
398}
399
41c445ff
JB		 400/**
401 * i40e_get_vsi_stats_struct - Get System Network Statistics
402 * @vsi: the VSI we care about
403 *
404 * Returns the address of the device statistics structure.
405 * The statistics are actually updated from the service task.
406 **/
407struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
408{
409 return &vsi->net_stats;
410}
411
412/**
413 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
414 * @netdev: network interface device structure
415 *
416 * Returns the address of the device statistics structure.
417 * The statistics are actually updated from the service task.
418 **/
38e00438
VD		 419#ifdef I40E_FCOE
420struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
421 struct net_device *netdev,
422 struct rtnl_link_stats64 *stats)
423#else
41c445ff
JB		 424static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
425 struct net_device *netdev,
980e9b11 426 struct rtnl_link_stats64 *stats)
38e00438 427#endif
41c445ff
JB		 428{
429 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 430 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 431 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 432 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
433 int i;
434
bc7d338f
ASJ		 435 if (test_bit(__I40E_DOWN, &vsi->state))
436 return stats;
437
3c325ced
JB		 438 if (!vsi->tx_rings)
439 return stats;
440
980e9b11
AD		 441 rcu_read_lock();
442 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 443 u64 bytes, packets;
444 unsigned int start;
445
446 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
447 if (!tx_ring)
448 continue;
449
450 do {
57a7744e 451 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 452 packets = tx_ring->stats.packets;
453 bytes = tx_ring->stats.bytes;
57a7744e 454 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 455
456 stats->tx_packets += packets;
457 stats->tx_bytes += bytes;
458 rx_ring = &tx_ring[1];
459
460 do {
57a7744e 461 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 462 packets = rx_ring->stats.packets;
463 bytes = rx_ring->stats.bytes;
57a7744e 464 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 465
980e9b11
AD		 466 stats->rx_packets += packets;
467 stats->rx_bytes += bytes;
468 }
469 rcu_read_unlock();
470
a5282f44 471 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 472 stats->multicast = vsi_stats->multicast;
473 stats->tx_errors = vsi_stats->tx_errors;
474 stats->tx_dropped = vsi_stats->tx_dropped;
475 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 476 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 477 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
478 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 479
980e9b11 480 return stats;
41c445ff
JB		 481}
482
483/**
484 * i40e_vsi_reset_stats - Resets all stats of the given vsi
485 * @vsi: the VSI to have its stats reset
486 **/
487void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
488{
489 struct rtnl_link_stats64 *ns;
490 int i;
491
492 if (!vsi)
493 return;
494
495 ns = i40e_get_vsi_stats_struct(vsi);
496 memset(ns, 0, sizeof(*ns));
497 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
498 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
499 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 500 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 501 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 502 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 503 sizeof(vsi->rx_rings[i]->stats));
6995b36c 504 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 505 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 506 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 507 sizeof(vsi->tx_rings[i]->stats));
508 memset(&vsi->tx_rings[i]->tx_stats, 0,
509 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 510 }
8e9dca53 511 }
41c445ff
JB		 512 vsi->stat_offsets_loaded = false;
513}
514
515/**
b40c82e6 516 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 517 * @pf: the PF to be reset
518 **/
519void i40e_pf_reset_stats(struct i40e_pf *pf)
520{
e91fdf76
SN		 521 int i;
522
41c445ff
JB		 523 memset(&pf->stats, 0, sizeof(pf->stats));
524 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
525 pf->stat_offsets_loaded = false;
e91fdf76
SN		 526
527 for (i = 0; i < I40E_MAX_VEB; i++) {
528 if (pf->veb[i]) {
529 memset(&pf->veb[i]->stats, 0,
530 sizeof(pf->veb[i]->stats));
531 memset(&pf->veb[i]->stats_offsets, 0,
532 sizeof(pf->veb[i]->stats_offsets));
533 pf->veb[i]->stat_offsets_loaded = false;
534 }
535 }
41c445ff
JB		 536}
537
538/**
539 * i40e_stat_update48 - read and update a 48 bit stat from the chip
540 * @hw: ptr to the hardware info
541 * @hireg: the high 32 bit reg to read
542 * @loreg: the low 32 bit reg to read
543 * @offset_loaded: has the initial offset been loaded yet
544 * @offset: ptr to current offset value
545 * @stat: ptr to the stat
546 *
547 * Since the device stats are not reset at PFReset, they likely will not
548 * be zeroed when the driver starts. We'll save the first values read
549 * and use them as offsets to be subtracted from the raw values in order
550 * to report stats that count from zero. In the process, we also manage
551 * the potential roll-over.
552 **/
553static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
554 bool offset_loaded, u64 *offset, u64 *stat)
555{
556 u64 new_data;
557
ab60085e 558 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 559 new_data = rd32(hw, loreg);
560 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
561 } else {
562 new_data = rd64(hw, loreg);
563 }
564 if (!offset_loaded)
565 *offset = new_data;
566 if (likely(new_data >= *offset))
567 *stat = new_data - *offset;
568 else
41a1d04b 569 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 570 *stat &= 0xFFFFFFFFFFFFULL;
571}
572
573/**
574 * i40e_stat_update32 - read and update a 32 bit stat from the chip
575 * @hw: ptr to the hardware info
576 * @reg: the hw reg to read
577 * @offset_loaded: has the initial offset been loaded yet
578 * @offset: ptr to current offset value
579 * @stat: ptr to the stat
580 **/
581static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
582 bool offset_loaded, u64 *offset, u64 *stat)
583{
584 u32 new_data;
585
586 new_data = rd32(hw, reg);
587 if (!offset_loaded)
588 *offset = new_data;
589 if (likely(new_data >= *offset))
590 *stat = (u32)(new_data - *offset);
591 else
41a1d04b 592 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 593}
594
595/**
596 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
597 * @vsi: the VSI to be updated
598 **/
599void i40e_update_eth_stats(struct i40e_vsi *vsi)
600{
601 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
602 struct i40e_pf *pf = vsi->back;
603 struct i40e_hw *hw = &pf->hw;
604 struct i40e_eth_stats *oes;
605 struct i40e_eth_stats *es; /* device's eth stats */
606
607 es = &vsi->eth_stats;
608 oes = &vsi->eth_stats_offsets;
609
610 /* Gather up the stats that the hw collects */
611 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
612 vsi->stat_offsets_loaded,
613 &oes->tx_errors, &es->tx_errors);
614 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
615 vsi->stat_offsets_loaded,
616 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 617 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
618 vsi->stat_offsets_loaded,
619 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
620 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 623
624 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
625 I40E_GLV_GORCL(stat_idx),
626 vsi->stat_offsets_loaded,
627 &oes->rx_bytes, &es->rx_bytes);
628 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
629 I40E_GLV_UPRCL(stat_idx),
630 vsi->stat_offsets_loaded,
631 &oes->rx_unicast, &es->rx_unicast);
632 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
633 I40E_GLV_MPRCL(stat_idx),
634 vsi->stat_offsets_loaded,
635 &oes->rx_multicast, &es->rx_multicast);
636 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
637 I40E_GLV_BPRCL(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->rx_broadcast, &es->rx_broadcast);
640
641 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
642 I40E_GLV_GOTCL(stat_idx),
643 vsi->stat_offsets_loaded,
644 &oes->tx_bytes, &es->tx_bytes);
645 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
646 I40E_GLV_UPTCL(stat_idx),
647 vsi->stat_offsets_loaded,
648 &oes->tx_unicast, &es->tx_unicast);
649 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
650 I40E_GLV_MPTCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->tx_multicast, &es->tx_multicast);
653 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
654 I40E_GLV_BPTCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->tx_broadcast, &es->tx_broadcast);
657 vsi->stat_offsets_loaded = true;
658}
659
660/**
661 * i40e_update_veb_stats - Update Switch component statistics
662 * @veb: the VEB being updated
663 **/
664static void i40e_update_veb_stats(struct i40e_veb *veb)
665{
666 struct i40e_pf *pf = veb->pf;
667 struct i40e_hw *hw = &pf->hw;
668 struct i40e_eth_stats *oes;
669 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 670 struct i40e_veb_tc_stats *veb_oes;
671 struct i40e_veb_tc_stats *veb_es;
672 int i, idx = 0;
41c445ff
JB		 673
674 idx = veb->stats_idx;
675 es = &veb->stats;
676 oes = &veb->stats_offsets;
fe860afb
NP		 677 veb_es = &veb->tc_stats;
678 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 679
680 /* Gather up the stats that the hw collects */
681 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
682 veb->stat_offsets_loaded,
683 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 684 if (hw->revision_id > 0)
685 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
686 veb->stat_offsets_loaded,
687 &oes->rx_unknown_protocol,
688 &es->rx_unknown_protocol);
41c445ff
JB		 689 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
690 veb->stat_offsets_loaded,
691 &oes->rx_bytes, &es->rx_bytes);
692 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
693 veb->stat_offsets_loaded,
694 &oes->rx_unicast, &es->rx_unicast);
695 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
696 veb->stat_offsets_loaded,
697 &oes->rx_multicast, &es->rx_multicast);
698 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
699 veb->stat_offsets_loaded,
700 &oes->rx_broadcast, &es->rx_broadcast);
701
702 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
703 veb->stat_offsets_loaded,
704 &oes->tx_bytes, &es->tx_bytes);
705 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
706 veb->stat_offsets_loaded,
707 &oes->tx_unicast, &es->tx_unicast);
708 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
709 veb->stat_offsets_loaded,
710 &oes->tx_multicast, &es->tx_multicast);
711 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
712 veb->stat_offsets_loaded,
713 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 714 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
715 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
716 I40E_GLVEBTC_RPCL(i, idx),
717 veb->stat_offsets_loaded,
718 &veb_oes->tc_rx_packets[i],
719 &veb_es->tc_rx_packets[i]);
720 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
721 I40E_GLVEBTC_RBCL(i, idx),
722 veb->stat_offsets_loaded,
723 &veb_oes->tc_rx_bytes[i],
724 &veb_es->tc_rx_bytes[i]);
725 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
726 I40E_GLVEBTC_TPCL(i, idx),
727 veb->stat_offsets_loaded,
728 &veb_oes->tc_tx_packets[i],
729 &veb_es->tc_tx_packets[i]);
730 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
731 I40E_GLVEBTC_TBCL(i, idx),
732 veb->stat_offsets_loaded,
733 &veb_oes->tc_tx_bytes[i],
734 &veb_es->tc_tx_bytes[i]);
735 }
41c445ff
JB		 736 veb->stat_offsets_loaded = true;
737}
738
38e00438
VD		 739#ifdef I40E_FCOE
740/**
741 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
742 * @vsi: the VSI that is capable of doing FCoE
743 **/
744static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
745{
746 struct i40e_pf *pf = vsi->back;
747 struct i40e_hw *hw = &pf->hw;
748 struct i40e_fcoe_stats *ofs;
749 struct i40e_fcoe_stats *fs; /* device's eth stats */
750 int idx;
751
752 if (vsi->type != I40E_VSI_FCOE)
753 return;
754
4147e2c5 755 idx = hw->pf_id + I40E_FCOE_PF_STAT_OFFSET;
38e00438
VD		 756 fs = &vsi->fcoe_stats;
757 ofs = &vsi->fcoe_stats_offsets;
758
759 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
760 vsi->fcoe_stat_offsets_loaded,
761 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
762 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
763 vsi->fcoe_stat_offsets_loaded,
764 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
765 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
766 vsi->fcoe_stat_offsets_loaded,
767 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
768 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
769 vsi->fcoe_stat_offsets_loaded,
770 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
771 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
772 vsi->fcoe_stat_offsets_loaded,
773 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
774 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
775 vsi->fcoe_stat_offsets_loaded,
776 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
777 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
778 vsi->fcoe_stat_offsets_loaded,
779 &ofs->fcoe_last_error, &fs->fcoe_last_error);
780 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
781 vsi->fcoe_stat_offsets_loaded,
782 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
783
784 vsi->fcoe_stat_offsets_loaded = true;
785}
786
787#endif
41c445ff 788/**
7812fddc 789 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 790 * @vsi: the VSI to be updated
791 *
792 * There are a few instances where we store the same stat in a
793 * couple of different structs. This is partly because we have
794 * the netdev stats that need to be filled out, which is slightly
795 * different from the "eth_stats" defined by the chip and used in
7812fddc 796 * VF communications. We sort it out here.
41c445ff 797 **/
7812fddc 798static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 799{
800 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 801 struct rtnl_link_stats64 *ons;
802 struct rtnl_link_stats64 *ns; /* netdev stats */
803 struct i40e_eth_stats *oes;
804 struct i40e_eth_stats *es; /* device's eth stats */
805 u32 tx_restart, tx_busy;
dd353109 806 u64 tx_lost_interrupt;
bf00b376 807 struct i40e_ring *p;
41c445ff 808 u32 rx_page, rx_buf;
bf00b376
AA		 809 u64 bytes, packets;
810 unsigned int start;
2fc3d715 811 u64 tx_linearize;
164c9f54 812 u64 tx_force_wb;
41c445ff
JB		 813 u64 rx_p, rx_b;
814 u64 tx_p, tx_b;
41c445ff
JB		 815 u16 q;
816
817 if (test_bit(__I40E_DOWN, &vsi->state) ||
818 test_bit(__I40E_CONFIG_BUSY, &pf->state))
819 return;
820
821 ns = i40e_get_vsi_stats_struct(vsi);
822 ons = &vsi->net_stats_offsets;
823 es = &vsi->eth_stats;
824 oes = &vsi->eth_stats_offsets;
825
826 /* Gather up the netdev and vsi stats that the driver collects
827 * on the fly during packet processing
828 */
829 rx_b = rx_p = 0;
830 tx_b = tx_p = 0;
164c9f54 831 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
dd353109 832 tx_lost_interrupt = 0;
41c445ff
JB		 833 rx_page = 0;
834 rx_buf = 0;
980e9b11 835 rcu_read_lock();
41c445ff 836 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 837 /* locate Tx ring */
838 p = ACCESS_ONCE(vsi->tx_rings[q]);
839
840 do {
57a7744e 841 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 842 packets = p->stats.packets;
843 bytes = p->stats.bytes;
57a7744e 844 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 845 tx_b += bytes;
846 tx_p += packets;
847 tx_restart += p->tx_stats.restart_queue;
848 tx_busy += p->tx_stats.tx_busy;
2fc3d715 849 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 850 tx_force_wb += p->tx_stats.tx_force_wb;
dd353109 851 tx_lost_interrupt += p->tx_stats.tx_lost_interrupt;
41c445ff 852
980e9b11
AD		 853 /* Rx queue is part of the same block as Tx queue */
854 p = &p[1];
855 do {
57a7744e 856 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 857 packets = p->stats.packets;
858 bytes = p->stats.bytes;
57a7744e 859 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 860 rx_b += bytes;
861 rx_p += packets;
420136cc
MW		 862 rx_buf += p->rx_stats.alloc_buff_failed;
863 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 864 }
980e9b11 865 rcu_read_unlock();
41c445ff
JB		 866 vsi->tx_restart = tx_restart;
867 vsi->tx_busy = tx_busy;
2fc3d715 868 vsi->tx_linearize = tx_linearize;
164c9f54 869 vsi->tx_force_wb = tx_force_wb;
dd353109 870 vsi->tx_lost_interrupt = tx_lost_interrupt;
41c445ff
JB		 871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc 898/**
b40c82e6 899 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
532d283d
SN		 922 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
923 I40E_GLPRT_UPRCL(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_unicast,
926 &nsd->eth.rx_unicast);
7812fddc
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
928 I40E_GLPRT_MPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_multicast,
931 &nsd->eth.rx_multicast);
532d283d
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
933 I40E_GLPRT_BPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_broadcast,
936 &nsd->eth.rx_broadcast);
937 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
938 I40E_GLPRT_UPTCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.tx_unicast,
941 &nsd->eth.tx_unicast);
942 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
943 I40E_GLPRT_MPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_multicast,
946 &nsd->eth.tx_multicast);
947 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
948 I40E_GLPRT_BPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_broadcast,
951 &nsd->eth.tx_broadcast);
41c445ff 952
7812fddc
SN		 953 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_dropped_link_down,
956 &nsd->tx_dropped_link_down);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->crc_errors, &nsd->crc_errors);
41c445ff 961
7812fddc
SN		 962 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 965
7812fddc
SN		 966 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->mac_local_faults,
969 &nsd->mac_local_faults);
970 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->mac_remote_faults,
973 &nsd->mac_remote_faults);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->rx_length_errors,
978 &nsd->rx_length_errors);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->link_xon_rx, &nsd->link_xon_rx);
983 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 986 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
987 pf->stat_offsets_loaded,
988 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 989 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
990 pf->stat_offsets_loaded,
991 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 992
7812fddc 993 for (i = 0; i < 8; i++) {
95db239f
NP		 994 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
995 pf->stat_offsets_loaded,
996 &osd->priority_xoff_rx[i],
997 &nsd->priority_xoff_rx[i]);
7812fddc 998 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 999 pf->stat_offsets_loaded,
7812fddc
SN		 1000 &osd->priority_xon_rx[i],
1001 &nsd->priority_xon_rx[i]);
1002 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1003 pf->stat_offsets_loaded,
7812fddc
SN		 1004 &osd->priority_xon_tx[i],
1005 &nsd->priority_xon_tx[i]);
1006 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1007 pf->stat_offsets_loaded,
7812fddc
SN		 1008 &osd->priority_xoff_tx[i],
1009 &nsd->priority_xoff_tx[i]);
1010 i40e_stat_update32(hw,
1011 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1012 pf->stat_offsets_loaded,
7812fddc
SN		 1013 &osd->priority_xon_2_xoff[i],
1014 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1015 }
1016
7812fddc
SN		 1017 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1018 I40E_GLPRT_PRC64L(hw->port),
1019 pf->stat_offsets_loaded,
1020 &osd->rx_size_64, &nsd->rx_size_64);
1021 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1022 I40E_GLPRT_PRC127L(hw->port),
1023 pf->stat_offsets_loaded,
1024 &osd->rx_size_127, &nsd->rx_size_127);
1025 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1026 I40E_GLPRT_PRC255L(hw->port),
1027 pf->stat_offsets_loaded,
1028 &osd->rx_size_255, &nsd->rx_size_255);
1029 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1030 I40E_GLPRT_PRC511L(hw->port),
1031 pf->stat_offsets_loaded,
1032 &osd->rx_size_511, &nsd->rx_size_511);
1033 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1034 I40E_GLPRT_PRC1023L(hw->port),
1035 pf->stat_offsets_loaded,
1036 &osd->rx_size_1023, &nsd->rx_size_1023);
1037 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1038 I40E_GLPRT_PRC1522L(hw->port),
1039 pf->stat_offsets_loaded,
1040 &osd->rx_size_1522, &nsd->rx_size_1522);
1041 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1042 I40E_GLPRT_PRC9522L(hw->port),
1043 pf->stat_offsets_loaded,
1044 &osd->rx_size_big, &nsd->rx_size_big);
1045
1046 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1047 I40E_GLPRT_PTC64L(hw->port),
1048 pf->stat_offsets_loaded,
1049 &osd->tx_size_64, &nsd->tx_size_64);
1050 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1051 I40E_GLPRT_PTC127L(hw->port),
1052 pf->stat_offsets_loaded,
1053 &osd->tx_size_127, &nsd->tx_size_127);
1054 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1055 I40E_GLPRT_PTC255L(hw->port),
1056 pf->stat_offsets_loaded,
1057 &osd->tx_size_255, &nsd->tx_size_255);
1058 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1059 I40E_GLPRT_PTC511L(hw->port),
1060 pf->stat_offsets_loaded,
1061 &osd->tx_size_511, &nsd->tx_size_511);
1062 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1063 I40E_GLPRT_PTC1023L(hw->port),
1064 pf->stat_offsets_loaded,
1065 &osd->tx_size_1023, &nsd->tx_size_1023);
1066 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1067 I40E_GLPRT_PTC1522L(hw->port),
1068 pf->stat_offsets_loaded,
1069 &osd->tx_size_1522, &nsd->tx_size_1522);
1070 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1071 I40E_GLPRT_PTC9522L(hw->port),
1072 pf->stat_offsets_loaded,
1073 &osd->tx_size_big, &nsd->tx_size_big);
1074
1075 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1076 pf->stat_offsets_loaded,
1077 &osd->rx_undersize, &nsd->rx_undersize);
1078 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_fragments, &nsd->rx_fragments);
1081 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1082 pf->stat_offsets_loaded,
1083 &osd->rx_oversize, &nsd->rx_oversize);
1084 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1085 pf->stat_offsets_loaded,
1086 &osd->rx_jabber, &nsd->rx_jabber);
1087
433c47de 1088 /* FDIR stats */
0bf4b1b0
ASJ		 1089 i40e_stat_update32(hw,
1090 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1091 pf->stat_offsets_loaded,
1092 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1093 i40e_stat_update32(hw,
1094 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1095 pf->stat_offsets_loaded,
1096 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1097 i40e_stat_update32(hw,
1098 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1099 pf->stat_offsets_loaded,
1100 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1101
7812fddc
SN		 1102 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1103 nsd->tx_lpi_status =
1104 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1105 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1106 nsd->rx_lpi_status =
1107 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1108 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1109 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1110 pf->stat_offsets_loaded,
1111 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1112 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1113 pf->stat_offsets_loaded,
1114 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1115
d0389e51
ASJ		 1116 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1117 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1118 nsd->fd_sb_status = true;
1119 else
1120 nsd->fd_sb_status = false;
1121
1122 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1123 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1124 nsd->fd_atr_status = true;
1125 else
1126 nsd->fd_atr_status = false;
1127
41c445ff
JB		 1128 pf->stat_offsets_loaded = true;
1129}
1130
7812fddc
SN		 1131/**
1132 * i40e_update_stats - Update the various statistics counters.
1133 * @vsi: the VSI to be updated
1134 *
1135 * Update the various stats for this VSI and its related entities.
1136 **/
1137void i40e_update_stats(struct i40e_vsi *vsi)
1138{
1139 struct i40e_pf *pf = vsi->back;
1140
1141 if (vsi == pf->vsi[pf->lan_vsi])
1142 i40e_update_pf_stats(pf);
1143
1144 i40e_update_vsi_stats(vsi);
38e00438
VD		 1145#ifdef I40E_FCOE
1146 i40e_update_fcoe_stats(vsi);
1147#endif
7812fddc
SN		 1148}
1149
41c445ff
JB		 1150/**
1151 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1152 * @vsi: the VSI to be searched
1153 * @macaddr: the MAC address
1154 * @vlan: the vlan
b40c82e6 1155 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1156 * @is_netdev: make sure its a netdev filter, else doesn't matter
1157 *
1158 * Returns ptr to the filter object or NULL
1159 **/
1160static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1161 u8 *macaddr, s16 vlan,
1162 bool is_vf, bool is_netdev)
1163{
1164 struct i40e_mac_filter *f;
1165
1166 if (!vsi || !macaddr)
1167 return NULL;
1168
1169 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1170 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1171 (vlan == f->vlan) &&
1172 (!is_vf || f->is_vf) &&
1173 (!is_netdev || f->is_netdev))
1174 return f;
1175 }
1176 return NULL;
1177}
1178
1179/**
1180 * i40e_find_mac - Find a mac addr in the macvlan filters list
1181 * @vsi: the VSI to be searched
1182 * @macaddr: the MAC address we are searching for
b40c82e6 1183 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1184 * @is_netdev: make sure its a netdev filter, else doesn't matter
1185 *
1186 * Returns the first filter with the provided MAC address or NULL if
1187 * MAC address was not found
1188 **/
1189struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1190 bool is_vf, bool is_netdev)
1191{
1192 struct i40e_mac_filter *f;
1193
1194 if (!vsi || !macaddr)
1195 return NULL;
1196
1197 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1198 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1199 (!is_vf || f->is_vf) &&
1200 (!is_netdev || f->is_netdev))
1201 return f;
1202 }
1203 return NULL;
1204}
1205
1206/**
1207 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1208 * @vsi: the VSI to be searched
1209 *
1210 * Returns true if VSI is in vlan mode or false otherwise
1211 **/
1212bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1213{
1214 struct i40e_mac_filter *f;
1215
1216 /* Only -1 for all the filters denotes not in vlan mode
1217 * so we have to go through all the list in order to make sure
1218 */
1219 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1220 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1221 return true;
1222 }
1223
1224 return false;
1225}
1226
1227/**
1228 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1229 * @vsi: the VSI to be searched
1230 * @macaddr: the mac address to be filtered
b40c82e6 1231 * @is_vf: true if it is a VF
41c445ff
JB		 1232 * @is_netdev: true if it is a netdev
1233 *
1234 * Goes through all the macvlan filters and adds a
1235 * macvlan filter for each unique vlan that already exists
1236 *
1237 * Returns first filter found on success, else NULL
1238 **/
1239struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1240 bool is_vf, bool is_netdev)
1241{
1242 struct i40e_mac_filter *f;
1243
1244 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1245 if (vsi->info.pvid)
1246 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1247 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1248 is_vf, is_netdev)) {
1249 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1250 is_vf, is_netdev))
41c445ff
JB		 1251 return NULL;
1252 }
1253 }
1254
1255 return list_first_entry_or_null(&vsi->mac_filter_list,
1256 struct i40e_mac_filter, list);
1257}
1258
b36e9ab5
MW		 1259/**
1260 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1261 * @vsi: the VSI to be searched
1262 * @macaddr: the mac address to be removed
1263 * @is_vf: true if it is a VF
1264 * @is_netdev: true if it is a netdev
1265 *
1266 * Removes a given MAC address from a VSI, regardless of VLAN
1267 *
1268 * Returns 0 for success, or error
1269 **/
1270int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1271 bool is_vf, bool is_netdev)
1272{
1273 struct i40e_mac_filter *f = NULL;
1274 int changed = 0;
1275
1276 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1277 "Missing mac_filter_list_lock\n");
1278 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1279 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1280 (is_vf == f->is_vf) &&
1281 (is_netdev == f->is_netdev)) {
1282 f->counter--;
1283 f->changed = true;
1284 changed = 1;
1285 }
1286 }
1287 if (changed) {
1288 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1289 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1290 return 0;
1291 }
1292 return -ENOENT;
1293}
1294
8c27d42e
GR		 1295/**
1296 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1297 * @vsi: the PF Main VSI - inappropriate for any other VSI
1298 * @macaddr: the MAC address
30650cc5
SN		 1299 *
1300 * Some older firmware configurations set up a default promiscuous VLAN
1301 * filter that needs to be removed.
8c27d42e 1302 **/
30650cc5 1303static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1304{
1305 struct i40e_aqc_remove_macvlan_element_data element;
1306 struct i40e_pf *pf = vsi->back;
f1c7e72e 1307 i40e_status ret;
8c27d42e
GR		 1308
1309 /* Only appropriate for the PF main VSI */
1310 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1311 return -EINVAL;
8c27d42e 1312
30650cc5 1313 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1314 ether_addr_copy(element.mac_addr, macaddr);
1315 element.vlan_tag = 0;
1316 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1317 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1318 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1319 if (ret)
30650cc5
SN		 1320 return -ENOENT;
1321
1322 return 0;
8c27d42e
GR		 1323}
1324
41c445ff
JB		 1325/**
1326 * i40e_add_filter - Add a mac/vlan filter to the VSI
1327 * @vsi: the VSI to be searched
1328 * @macaddr: the MAC address
1329 * @vlan: the vlan
b40c82e6 1330 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1331 * @is_netdev: make sure its a netdev filter, else doesn't matter
1332 *
1333 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1334 *
1335 * NOTE: This function is expected to be called with mac_filter_list_lock
1336 * being held.
41c445ff
JB		 1337 **/
1338struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1339 u8 *macaddr, s16 vlan,
1340 bool is_vf, bool is_netdev)
1341{
1342 struct i40e_mac_filter *f;
1343
1344 if (!vsi || !macaddr)
1345 return NULL;
1346
1347 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1348 if (!f) {
1349 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1350 if (!f)
1351 goto add_filter_out;
1352
9a173901 1353 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1354 f->vlan = vlan;
1355 f->changed = true;
1356
1357 INIT_LIST_HEAD(&f->list);
04d5a21d 1358 list_add_tail(&f->list, &vsi->mac_filter_list);
41c445ff
JB		 1359 }
1360
1361 /* increment counter and add a new flag if needed */
1362 if (is_vf) {
1363 if (!f->is_vf) {
1364 f->is_vf = true;
1365 f->counter++;
1366 }
1367 } else if (is_netdev) {
1368 if (!f->is_netdev) {
1369 f->is_netdev = true;
1370 f->counter++;
1371 }
1372 } else {
1373 f->counter++;
1374 }
1375
1376 /* changed tells sync_filters_subtask to
1377 * push the filter down to the firmware
1378 */
1379 if (f->changed) {
1380 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1381 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1382 }
1383
1384add_filter_out:
1385 return f;
1386}
1387
1388/**
1389 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1390 * @vsi: the VSI to be searched
1391 * @macaddr: the MAC address
1392 * @vlan: the vlan
b40c82e6 1393 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1394 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1395 *
1396 * NOTE: This function is expected to be called with mac_filter_list_lock
1397 * being held.
41c445ff
JB		 1398 **/
1399void i40e_del_filter(struct i40e_vsi *vsi,
1400 u8 *macaddr, s16 vlan,
1401 bool is_vf, bool is_netdev)
1402{
1403 struct i40e_mac_filter *f;
1404
1405 if (!vsi || !macaddr)
1406 return;
1407
1408 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1409 if (!f || f->counter == 0)
1410 return;
1411
1412 if (is_vf) {
1413 if (f->is_vf) {
1414 f->is_vf = false;
1415 f->counter--;
1416 }
1417 } else if (is_netdev) {
1418 if (f->is_netdev) {
1419 f->is_netdev = false;
1420 f->counter--;
1421 }
1422 } else {
b40c82e6 1423 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1424 int min_f = 0;
6995b36c 1425
41c445ff
JB		 1426 min_f += (f->is_vf ? 1 : 0);
1427 min_f += (f->is_netdev ? 1 : 0);
1428
1429 if (f->counter > min_f)
1430 f->counter--;
1431 }
1432
1433 /* counter == 0 tells sync_filters_subtask to
1434 * remove the filter from the firmware's list
1435 */
1436 if (f->counter == 0) {
1437 f->changed = true;
1438 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1439 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1440 }
1441}
1442
1443/**
1444 * i40e_set_mac - NDO callback to set mac address
1445 * @netdev: network interface device structure
1446 * @p: pointer to an address structure
1447 *
1448 * Returns 0 on success, negative on failure
1449 **/
38e00438
VD		 1450#ifdef I40E_FCOE
1451int i40e_set_mac(struct net_device *netdev, void *p)
1452#else
41c445ff 1453static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1454#endif
41c445ff
JB		 1455{
1456 struct i40e_netdev_priv *np = netdev_priv(netdev);
1457 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1458 struct i40e_pf *pf = vsi->back;
1459 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1460 struct sockaddr *addr = p;
1461 struct i40e_mac_filter *f;
1462
1463 if (!is_valid_ether_addr(addr->sa_data))
1464 return -EADDRNOTAVAIL;
1465
30650cc5
SN		 1466 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1467 netdev_info(netdev, "already using mac address %pM\n",
1468 addr->sa_data);
1469 return 0;
1470 }
41c445ff 1471
80f6428f
ASJ		 1472 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1473 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1474 return -EADDRNOTAVAIL;
1475
30650cc5
SN		 1476 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1477 netdev_info(netdev, "returning to hw mac address %pM\n",
1478 hw->mac.addr);
1479 else
1480 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1481
41c445ff
JB		 1482 if (vsi->type == I40E_VSI_MAIN) {
1483 i40e_status ret;
6995b36c 1484
41c445ff 1485 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1486 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1487 addr->sa_data, NULL);
1488 if (ret) {
1489 netdev_info(netdev,
1490 "Addr change for Main VSI failed: %d\n",
1491 ret);
1492 return -EADDRNOTAVAIL;
1493 }
41c445ff
JB		 1494 }
1495
30650cc5
SN		 1496 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1497 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1498
30650cc5
SN		 1499 memset(&element, 0, sizeof(element));
1500 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1501 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1502 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1503 } else {
21659035 1504 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1505 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1506 false, false);
21659035 1507 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1508 }
41c445ff 1509
30650cc5
SN		 1510 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1511 struct i40e_aqc_add_macvlan_element_data element;
1512
1513 memset(&element, 0, sizeof(element));
1514 ether_addr_copy(element.mac_addr, hw->mac.addr);
1515 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1516 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1517 } else {
21659035 1518 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1519 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1520 false, false);
1521 if (f)
1522 f->is_laa = true;
21659035 1523 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1524 }
1525
30650cc5 1526 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b 1527
c53934c6
JB		 1528 /* schedule our worker thread which will take care of
1529 * applying the new filter changes
1530 */
1531 i40e_service_event_schedule(vsi->back);
1532 return 0;
41c445ff
JB		 1533}
1534
1535/**
1536 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1537 * @vsi: the VSI being setup
1538 * @ctxt: VSI context structure
1539 * @enabled_tc: Enabled TCs bitmap
1540 * @is_add: True if called before Add VSI
1541 *
1542 * Setup VSI queue mapping for enabled traffic classes.
1543 **/
38e00438
VD		 1544#ifdef I40E_FCOE
1545void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1546 struct i40e_vsi_context *ctxt,
1547 u8 enabled_tc,
1548 bool is_add)
1549#else
41c445ff
JB		 1550static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1551 struct i40e_vsi_context *ctxt,
1552 u8 enabled_tc,
1553 bool is_add)
38e00438 1554#endif
41c445ff
JB		 1555{
1556 struct i40e_pf *pf = vsi->back;
1557 u16 sections = 0;
1558 u8 netdev_tc = 0;
1559 u16 numtc = 0;
1560 u16 qcount;
1561 u8 offset;
1562 u16 qmap;
1563 int i;
4e3b35b0 1564 u16 num_tc_qps = 0;
41c445ff
JB		 1565
1566 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1567 offset = 0;
1568
1569 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1570 /* Find numtc from enabled TC bitmap */
1571 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1572 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1573 numtc++;
1574 }
1575 if (!numtc) {
1576 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1577 numtc = 1;
1578 }
1579 } else {
1580 /* At least TC0 is enabled in case of non-DCB case */
1581 numtc = 1;
1582 }
1583
1584 vsi->tc_config.numtc = numtc;
1585 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1586 /* Number of queues per enabled TC */
7f9ff476
AS		 1587 /* In MFP case we can have a much lower count of MSIx
1588 * vectors available and so we need to lower the used
1589 * q count.
1590 */
26cdc443
ASJ		 1591 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1592 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1593 else
1594 qcount = vsi->alloc_queue_pairs;
7f9ff476 1595 num_tc_qps = qcount / numtc;
e25d00b8 1596 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1597
1598 /* Setup queue offset/count for all TCs for given VSI */
1599 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1600 /* See if the given TC is enabled for the given VSI */
75f5cea9 1601 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1602 /* TC is enabled */
41c445ff
JB		 1603 int pow, num_qps;
1604
41c445ff
JB		 1605 switch (vsi->type) {
1606 case I40E_VSI_MAIN:
acd65448
HZ		 1607 qcount = min_t(int, pf->alloc_rss_size,
1608 num_tc_qps);
41c445ff 1609 break;
38e00438
VD		 1610#ifdef I40E_FCOE
1611 case I40E_VSI_FCOE:
1612 qcount = num_tc_qps;
1613 break;
1614#endif
41c445ff
JB		 1615 case I40E_VSI_FDIR:
1616 case I40E_VSI_SRIOV:
1617 case I40E_VSI_VMDQ2:
1618 default:
4e3b35b0 1619 qcount = num_tc_qps;
41c445ff
JB		 1620 WARN_ON(i != 0);
1621 break;
1622 }
4e3b35b0
NP		 1623 vsi->tc_config.tc_info[i].qoffset = offset;
1624 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1625
1e200e4a 1626 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1627 num_qps = qcount;
41c445ff 1628 pow = 0;
41a1d04b 1629 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1630 pow++;
1631 num_qps >>= 1;
1632 }
1633
1634 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1635 qmap =
1636 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1637 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1638
4e3b35b0 1639 offset += qcount;
41c445ff
JB		 1640 } else {
1641 /* TC is not enabled so set the offset to
1642 * default queue and allocate one queue
1643 * for the given TC.
1644 */
1645 vsi->tc_config.tc_info[i].qoffset = 0;
1646 vsi->tc_config.tc_info[i].qcount = 1;
1647 vsi->tc_config.tc_info[i].netdev_tc = 0;
1648
1649 qmap = 0;
1650 }
1651 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1652 }
1653
1654 /* Set actual Tx/Rx queue pairs */
1655 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1656 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1657 if (vsi->req_queue_pairs > 0)
1658 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1659 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1660 vsi->num_queue_pairs = pf->num_lan_msix;
1661 }
41c445ff
JB		 1662
1663 /* Scheduler section valid can only be set for ADD VSI */
1664 if (is_add) {
1665 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1666
1667 ctxt->info.up_enable_bits = enabled_tc;
1668 }
1669 if (vsi->type == I40E_VSI_SRIOV) {
1670 ctxt->info.mapping_flags |=
1671 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1672 for (i = 0; i < vsi->num_queue_pairs; i++)
1673 ctxt->info.queue_mapping[i] =
1674 cpu_to_le16(vsi->base_queue + i);
1675 } else {
1676 ctxt->info.mapping_flags |=
1677 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1678 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1679 }
1680 ctxt->info.valid_sections |= cpu_to_le16(sections);
1681}
1682
1683/**
1684 * i40e_set_rx_mode - NDO callback to set the netdev filters
1685 * @netdev: network interface device structure
1686 **/
38e00438
VD		 1687#ifdef I40E_FCOE
1688void i40e_set_rx_mode(struct net_device *netdev)
1689#else
41c445ff 1690static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1691#endif
41c445ff
JB		 1692{
1693 struct i40e_netdev_priv *np = netdev_priv(netdev);
1694 struct i40e_mac_filter *f, *ftmp;
1695 struct i40e_vsi *vsi = np->vsi;
1696 struct netdev_hw_addr *uca;
1697 struct netdev_hw_addr *mca;
1698 struct netdev_hw_addr *ha;
1699
21659035
KP		 1700 spin_lock_bh(&vsi->mac_filter_list_lock);
1701
41c445ff
JB		 1702 /* add addr if not already in the filter list */
1703 netdev_for_each_uc_addr(uca, netdev) {
1704 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1705 if (i40e_is_vsi_in_vlan(vsi))
1706 i40e_put_mac_in_vlan(vsi, uca->addr,
1707 false, true);
1708 else
1709 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1710 false, true);
1711 }
1712 }
1713
1714 netdev_for_each_mc_addr(mca, netdev) {
1715 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1716 if (i40e_is_vsi_in_vlan(vsi))
1717 i40e_put_mac_in_vlan(vsi, mca->addr,
1718 false, true);
1719 else
1720 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1721 false, true);
1722 }
1723 }
1724
1725 /* remove filter if not in netdev list */
1726 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1727
1728 if (!f->is_netdev)
1729 continue;
1730
2f41f335
SN		 1731 netdev_for_each_mc_addr(mca, netdev)
1732 if (ether_addr_equal(mca->addr, f->macaddr))
1733 goto bottom_of_search_loop;
41c445ff 1734
2f41f335
SN		 1735 netdev_for_each_uc_addr(uca, netdev)
1736 if (ether_addr_equal(uca->addr, f->macaddr))
1737 goto bottom_of_search_loop;
1738
1739 for_each_dev_addr(netdev, ha)
1740 if (ether_addr_equal(ha->addr, f->macaddr))
1741 goto bottom_of_search_loop;
1742
1743 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1744 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1745
1746bottom_of_search_loop:
1747 continue;
41c445ff 1748 }
21659035 1749 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1750
1751 /* check for other flag changes */
1752 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1753 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1754 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1755 }
c53934c6
JB		 1756
1757 /* schedule our worker thread which will take care of
1758 * applying the new filter changes
1759 */
1760 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1761}
1762
21659035
KP		 1763/**
1764 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1765 * @src: source MAC filter entry to be clones
1766 *
1767 * Returns the pointer to newly cloned MAC filter entry or NULL
1768 * in case of error
1769 **/
1770static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1771 struct i40e_mac_filter *src)
1772{
1773 struct i40e_mac_filter *f;
1774
1775 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1776 if (!f)
1777 return NULL;
1778 *f = *src;
1779
1780 INIT_LIST_HEAD(&f->list);
1781
1782 return f;
1783}
1784
1785/**
1786 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1787 * @vsi: pointer to vsi struct
1788 * @from: Pointer to list which contains MAC filter entries - changes to
1789 * those entries needs to be undone.
1790 *
1791 * MAC filter entries from list were slated to be removed from device.
1792 **/
1793static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1794 struct list_head *from)
1795{
1796 struct i40e_mac_filter *f, *ftmp;
1797
1798 list_for_each_entry_safe(f, ftmp, from, list) {
1799 f->changed = true;
1800 /* Move the element back into MAC filter list*/
1801 list_move_tail(&f->list, &vsi->mac_filter_list);
1802 }
1803}
1804
1805/**
1806 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1807 * @vsi: pointer to vsi struct
1808 *
1809 * MAC filter entries from list were slated to be added from device.
1810 **/
1811static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1812{
1813 struct i40e_mac_filter *f, *ftmp;
1814
1815 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1816 if (!f->changed && f->counter)
1817 f->changed = true;
1818 }
1819}
1820
1821/**
1822 * i40e_cleanup_add_list - Deletes the element from add list and release
1823 * memory
1824 * @add_list: Pointer to list which contains MAC filter entries
1825 **/
1826static void i40e_cleanup_add_list(struct list_head *add_list)
1827{
1828 struct i40e_mac_filter *f, *ftmp;
1829
1830 list_for_each_entry_safe(f, ftmp, add_list, list) {
1831 list_del(&f->list);
1832 kfree(f);
1833 }
1834}
1835
41c445ff
JB		 1836/**
1837 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1838 * @vsi: ptr to the VSI
1839 *
1840 * Push any outstanding VSI filter changes through the AdminQ.
1841 *
1842 * Returns 0 or error value
1843 **/
17652c63 1844int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1845{
21659035
KP		 1846 struct list_head tmp_del_list, tmp_add_list;
1847 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1848 bool promisc_forced_on = false;
1849 bool add_happened = false;
1850 int filter_list_len = 0;
1851 u32 changed_flags = 0;
ea02e90b 1852 i40e_status aq_ret = 0;
21659035 1853 bool err_cond = false;
ea02e90b 1854 int retval = 0;
41c445ff
JB		 1855 struct i40e_pf *pf;
1856 int num_add = 0;
1857 int num_del = 0;
f1c7e72e 1858 int aq_err = 0;
41c445ff
JB		 1859 u16 cmd_flags;
1860
1861 /* empty array typed pointers, kcalloc later */
1862 struct i40e_aqc_add_macvlan_element_data *add_list;
1863 struct i40e_aqc_remove_macvlan_element_data *del_list;
1864
1865 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1866 usleep_range(1000, 2000);
1867 pf = vsi->back;
1868
1869 if (vsi->netdev) {
1870 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1871 vsi->current_netdev_flags = vsi->netdev->flags;
1872 }
1873
21659035
KP		 1874 INIT_LIST_HEAD(&tmp_del_list);
1875 INIT_LIST_HEAD(&tmp_add_list);
1876
41c445ff
JB		 1877 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1878 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1879
21659035 1880 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1881 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1882 if (!f->changed)
1883 continue;
1884
1885 if (f->counter != 0)
1886 continue;
1887 f->changed = false;
21659035
KP		 1888
1889 /* Move the element into temporary del_list */
1890 list_move_tail(&f->list, &tmp_del_list);
1891 }
1892
1893 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1894 if (!f->changed)
1895 continue;
1896
1897 if (f->counter == 0)
1898 continue;
1899 f->changed = false;
1900
1901 /* Clone MAC filter entry and add into temporary list */
1902 fclone = i40e_mac_filter_entry_clone(f);
1903 if (!fclone) {
1904 err_cond = true;
1905 break;
1906 }
1907 list_add_tail(&fclone->list, &tmp_add_list);
1908 }
1909
1910 /* if failed to clone MAC filter entry - undo */
1911 if (err_cond) {
1912 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1913 i40e_undo_add_filter_entries(vsi);
1914 }
1915 spin_unlock_bh(&vsi->mac_filter_list_lock);
1916
ea02e90b 1917 if (err_cond) {
21659035 1918 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1919 retval = -ENOMEM;
1920 goto out;
1921 }
21659035
KP		 1922 }
1923
1924 /* Now process 'del_list' outside the lock */
1925 if (!list_empty(&tmp_del_list)) {
f1199998
SN		 1926 int del_list_size;
1927
21659035
KP		 1928 filter_list_len = pf->hw.aq.asq_buf_size /
1929 sizeof(struct i40e_aqc_remove_macvlan_element_data);
f1199998
SN		 1930 del_list_size = filter_list_len *
1931 sizeof(struct i40e_aqc_remove_macvlan_element_data);
38c3cec7 1932 del_list = kzalloc(del_list_size, GFP_ATOMIC);
21659035
KP		 1933 if (!del_list) {
1934 i40e_cleanup_add_list(&tmp_add_list);
1935
1936 /* Undo VSI's MAC filter entry element updates */
1937 spin_lock_bh(&vsi->mac_filter_list_lock);
1938 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1939 i40e_undo_add_filter_entries(vsi);
1940 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1941 retval = -ENOMEM;
1942 goto out;
21659035
KP		 1943 }
1944
1945 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1946 cmd_flags = 0;
1947
1948 /* add to delete list */
9a173901 1949 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1950 del_list[num_del].vlan_tag =
1951 cpu_to_le16((u16)(f->vlan ==
1952 I40E_VLAN_ANY ? 0 : f->vlan));
1953
41c445ff
JB		 1954 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1955 del_list[num_del].flags = cmd_flags;
1956 num_del++;
1957
41c445ff
JB		 1958 /* flush a full buffer */
1959 if (num_del == filter_list_len) {
ea02e90b
MW		 1960 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1961 vsi->seid,
1962 del_list,
1963 num_del,
1964 NULL);
f1c7e72e 1965 aq_err = pf->hw.aq.asq_last_status;
41c445ff 1966 num_del = 0;
f1199998 1967 memset(del_list, 0, del_list_size);
41c445ff 1968
ea02e90b
MW		 1969 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1970 retval = -EIO;
21659035
KP		 1971 dev_err(&pf->pdev->dev,
1972 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
ea02e90b 1973 i40e_stat_str(&pf->hw, aq_ret),
21659035 1974 i40e_aq_str(&pf->hw, aq_err));
ea02e90b 1975 }
41c445ff 1976 }
21659035
KP		 1977 /* Release memory for MAC filter entries which were
1978 * synced up with HW.
1979 */
1980 list_del(&f->list);
1981 kfree(f);
41c445ff 1982 }
21659035 1983
41c445ff 1984 if (num_del) {
ea02e90b
MW		 1985 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
1986 del_list, num_del,
1987 NULL);
f1c7e72e 1988 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1989 num_del = 0;
1990
ea02e90b 1991 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1992 dev_info(&pf->pdev->dev,
f1c7e72e 1993 "ignoring delete macvlan error, err %s aq_err %s\n",
ea02e90b 1994 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 1995 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1996 }
1997
1998 kfree(del_list);
1999 del_list = NULL;
21659035
KP		 2000 }
2001
2002 if (!list_empty(&tmp_add_list)) {
f1199998 2003 int add_list_size;
41c445ff
JB		 2004
2005 /* do all the adds now */
2006 filter_list_len = pf->hw.aq.asq_buf_size /
2007 sizeof(struct i40e_aqc_add_macvlan_element_data),
f1199998
SN		 2008 add_list_size = filter_list_len *
2009 sizeof(struct i40e_aqc_add_macvlan_element_data);
38c3cec7 2010 add_list = kzalloc(add_list_size, GFP_ATOMIC);
21659035
KP		 2011 if (!add_list) {
2012 /* Purge element from temporary lists */
2013 i40e_cleanup_add_list(&tmp_add_list);
2014
2015 /* Undo add filter entries from VSI MAC filter list */
2016 spin_lock_bh(&vsi->mac_filter_list_lock);
2017 i40e_undo_add_filter_entries(vsi);
2018 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2019 retval = -ENOMEM;
2020 goto out;
21659035 2021 }
41c445ff 2022
21659035 2023 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2024
41c445ff
JB		 2025 add_happened = true;
2026 cmd_flags = 0;
2027
2028 /* add to add array */
9a173901 2029 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2030 add_list[num_add].vlan_tag =
2031 cpu_to_le16(
2032 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2033 add_list[num_add].queue_number = 0;
2034
2035 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2036 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2037 num_add++;
2038
2039 /* flush a full buffer */
2040 if (num_add == filter_list_len) {
ea02e90b
MW		 2041 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2042 add_list, num_add,
2043 NULL);
f1c7e72e 2044 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2045 num_add = 0;
2046
ea02e90b 2047 if (aq_ret)
41c445ff 2048 break;
f1199998 2049 memset(add_list, 0, add_list_size);
41c445ff 2050 }
21659035
KP		 2051 /* Entries from tmp_add_list were cloned from MAC
2052 * filter list, hence clean those cloned entries
2053 */
2054 list_del(&f->list);
2055 kfree(f);
41c445ff 2056 }
21659035 2057
41c445ff 2058 if (num_add) {
ea02e90b
MW		 2059 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2060 add_list, num_add, NULL);
f1c7e72e 2061 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2062 num_add = 0;
2063 }
2064 kfree(add_list);
2065 add_list = NULL;
2066
ea02e90b
MW		 2067 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2068 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2069 dev_info(&pf->pdev->dev,
f1c7e72e 2070 "add filter failed, err %s aq_err %s\n",
ea02e90b 2071 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2072 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2073 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2074 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2075 &vsi->state)) {
2076 promisc_forced_on = true;
2077 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2078 &vsi->state);
2079 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2080 }
2081 }
2082 }
2083
a856b5cb
ASJ		 2084 /* if the VF is not trusted do not do promisc */
2085 if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) {
2086 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state);
2087 goto out;
2088 }
2089
41c445ff
JB		 2090 /* check for changes in promiscuous modes */
2091 if (changed_flags & IFF_ALLMULTI) {
2092 bool cur_multipromisc;
6995b36c 2093
41c445ff 2094 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2095 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2096 vsi->seid,
2097 cur_multipromisc,
2098 NULL);
2099 if (aq_ret) {
2100 retval = i40e_aq_rc_to_posix(aq_ret,
2101 pf->hw.aq.asq_last_status);
41c445ff 2102 dev_info(&pf->pdev->dev,
f1c7e72e 2103 "set multi promisc failed, err %s aq_err %s\n",
ea02e90b 2104 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2105 i40e_aq_str(&pf->hw,
2106 pf->hw.aq.asq_last_status));
ea02e90b 2107 }
41c445ff
JB		 2108 }
2109 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2110 bool cur_promisc;
6995b36c 2111
41c445ff
JB		 2112 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2113 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2114 &vsi->state));
6784ed5a
ASJ		 2115 if ((vsi->type == I40E_VSI_MAIN) &&
2116 (pf->lan_veb != I40E_NO_VEB) &&
2117 !(pf->flags & I40E_FLAG_MFP_ENABLED)) {
92faef85
ASJ		 2118 /* set defport ON for Main VSI instead of true promisc
2119 * this way we will get all unicast/multicast and VLAN
2120 * promisc behavior but will not get VF or VMDq traffic
2121 * replicated on the Main VSI.
2122 */
2123 if (pf->cur_promisc != cur_promisc) {
2124 pf->cur_promisc = cur_promisc;
0e4425ed 2125 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2126 }
2127 } else {
ea02e90b 2128 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
92faef85 2129 &vsi->back->hw,
f1c7e72e
SN		 2130 vsi->seid,
2131 cur_promisc, NULL);
ea02e90b
MW		 2132 if (aq_ret) {
2133 retval =
2134 i40e_aq_rc_to_posix(aq_ret,
2135 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2136 dev_info(&pf->pdev->dev,
2137 "set unicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2138 aq_ret, pf->hw.aq.asq_last_status);
2139 }
2140 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
92faef85
ASJ		 2141 &vsi->back->hw,
2142 vsi->seid,
2143 cur_promisc, NULL);
ea02e90b
MW		 2144 if (aq_ret) {
2145 retval =
2146 i40e_aq_rc_to_posix(aq_ret,
2147 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2148 dev_info(&pf->pdev->dev,
2149 "set multicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2150 aq_ret, pf->hw.aq.asq_last_status);
2151 }
92faef85 2152 }
ea02e90b
MW		 2153 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2154 vsi->seid,
2155 cur_promisc, NULL);
2156 if (aq_ret) {
2157 retval = i40e_aq_rc_to_posix(aq_ret,
2158 pf->hw.aq.asq_last_status);
1a10370a 2159 dev_info(&pf->pdev->dev,
f1c7e72e 2160 "set brdcast promisc failed, err %s, aq_err %s\n",
ea02e90b 2161 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2162 i40e_aq_str(&pf->hw,
2163 pf->hw.aq.asq_last_status));
ea02e90b 2164 }
41c445ff 2165 }
ea02e90b 2166out:
2818ccd9
JB		 2167 /* if something went wrong then set the changed flag so we try again */
2168 if (retval)
2169 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2170
41c445ff 2171 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2172 return retval;
41c445ff
JB		 2173}
2174
2175/**
2176 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2177 * @pf: board private structure
2178 **/
2179static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2180{
2181 int v;
2182
2183 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2184 return;
2185 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2186
505682cd 2187 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2188 if (pf->vsi[v] &&
17652c63
JB		 2189 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2190 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2191
2192 if (ret) {
2193 /* come back and try again later */
2194 pf->flags |= I40E_FLAG_FILTER_SYNC;
2195 break;
2196 }
2197 }
41c445ff
JB		 2198 }
2199}
2200
2201/**
2202 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2203 * @netdev: network interface device structure
2204 * @new_mtu: new value for maximum frame size
2205 *
2206 * Returns 0 on success, negative on failure
2207 **/
2208static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2209{
2210 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2211 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2212 struct i40e_vsi *vsi = np->vsi;
2213
2214 /* MTU < 68 is an error and causes problems on some kernels */
2215 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2216 return -EINVAL;
2217
2218 netdev_info(netdev, "changing MTU from %d to %d\n",
2219 netdev->mtu, new_mtu);
2220 netdev->mtu = new_mtu;
2221 if (netif_running(netdev))
2222 i40e_vsi_reinit_locked(vsi);
e3219ce6 2223 i40e_notify_client_of_l2_param_changes(vsi);
41c445ff
JB		 2224 return 0;
2225}
2226
beb0dff1
JK		 2227/**
2228 * i40e_ioctl - Access the hwtstamp interface
2229 * @netdev: network interface device structure
2230 * @ifr: interface request data
2231 * @cmd: ioctl command
2232 **/
2233int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2234{
2235 struct i40e_netdev_priv *np = netdev_priv(netdev);
2236 struct i40e_pf *pf = np->vsi->back;
2237
2238 switch (cmd) {
2239 case SIOCGHWTSTAMP:
2240 return i40e_ptp_get_ts_config(pf, ifr);
2241 case SIOCSHWTSTAMP:
2242 return i40e_ptp_set_ts_config(pf, ifr);
2243 default:
2244 return -EOPNOTSUPP;
2245 }
2246}
2247
41c445ff
JB		 2248/**
2249 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2250 * @vsi: the vsi being adjusted
2251 **/
2252void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2253{
2254 struct i40e_vsi_context ctxt;
2255 i40e_status ret;
2256
2257 if ((vsi->info.valid_sections &
2258 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2259 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2260 return; /* already enabled */
2261
2262 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2263 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2264 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2265
2266 ctxt.seid = vsi->seid;
1a2f6248 2267 ctxt.info = vsi->info;
41c445ff
JB		 2268 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2269 if (ret) {
2270 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2271 "update vlan stripping failed, err %s aq_err %s\n",
2272 i40e_stat_str(&vsi->back->hw, ret),
2273 i40e_aq_str(&vsi->back->hw,
2274 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2275 }
2276}
2277
2278/**
2279 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2280 * @vsi: the vsi being adjusted
2281 **/
2282void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2283{
2284 struct i40e_vsi_context ctxt;
2285 i40e_status ret;
2286
2287 if ((vsi->info.valid_sections &
2288 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2289 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2290 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2291 return; /* already disabled */
2292
2293 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2294 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2295 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2296
2297 ctxt.seid = vsi->seid;
1a2f6248 2298 ctxt.info = vsi->info;
41c445ff
JB		 2299 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2300 if (ret) {
2301 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2302 "update vlan stripping failed, err %s aq_err %s\n",
2303 i40e_stat_str(&vsi->back->hw, ret),
2304 i40e_aq_str(&vsi->back->hw,
2305 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2306 }
2307}
2308
2309/**
2310 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2311 * @netdev: network interface to be adjusted
2312 * @features: netdev features to test if VLAN offload is enabled or not
2313 **/
2314static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2315{
2316 struct i40e_netdev_priv *np = netdev_priv(netdev);
2317 struct i40e_vsi *vsi = np->vsi;
2318
2319 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2320 i40e_vlan_stripping_enable(vsi);
2321 else
2322 i40e_vlan_stripping_disable(vsi);
2323}
2324
2325/**
2326 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2327 * @vsi: the vsi being configured
2328 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2329 **/
2330int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2331{
2332 struct i40e_mac_filter *f, *add_f;
2333 bool is_netdev, is_vf;
41c445ff
JB		 2334
2335 is_vf = (vsi->type == I40E_VSI_SRIOV);
2336 is_netdev = !!(vsi->netdev);
2337
21659035
KP		 2338 /* Locked once because all functions invoked below iterates list*/
2339 spin_lock_bh(&vsi->mac_filter_list_lock);
2340
41c445ff
JB		 2341 if (is_netdev) {
2342 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2343 is_vf, is_netdev);
2344 if (!add_f) {
2345 dev_info(&vsi->back->pdev->dev,
2346 "Could not add vlan filter %d for %pM\n",
2347 vid, vsi->netdev->dev_addr);
21659035 2348 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2349 return -ENOMEM;
2350 }
2351 }
2352
2353 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2354 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2355 if (!add_f) {
2356 dev_info(&vsi->back->pdev->dev,
2357 "Could not add vlan filter %d for %pM\n",
2358 vid, f->macaddr);
21659035 2359 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2360 return -ENOMEM;
2361 }
2362 }
2363
41c445ff
JB		 2364 /* Now if we add a vlan tag, make sure to check if it is the first
2365 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2366 * with 0, so we now accept untagged and specified tagged traffic
2367 * (and not any taged and untagged)
2368 */
2369 if (vid > 0) {
2370 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2371 I40E_VLAN_ANY,
2372 is_vf, is_netdev)) {
2373 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2374 I40E_VLAN_ANY, is_vf, is_netdev);
2375 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2376 is_vf, is_netdev);
2377 if (!add_f) {
2378 dev_info(&vsi->back->pdev->dev,
2379 "Could not add filter 0 for %pM\n",
2380 vsi->netdev->dev_addr);
21659035 2381 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2382 return -ENOMEM;
2383 }
2384 }
8d82a7c5 2385 }
41c445ff 2386
8d82a7c5
GR		 2387 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2388 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2389 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2390 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2391 is_vf, is_netdev))
2392 continue;
2393 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2394 is_vf, is_netdev);
2395 add_f = i40e_add_filter(vsi, f->macaddr,
2396 0, is_vf, is_netdev);
2397 if (!add_f) {
2398 dev_info(&vsi->back->pdev->dev,
2399 "Could not add filter 0 for %pM\n",
2400 f->macaddr);
2401 spin_unlock_bh(&vsi->mac_filter_list_lock);
2402 return -ENOMEM;
41c445ff
JB		 2403 }
2404 }
41c445ff
JB		 2405 }
2406
21659035
KP		 2407 spin_unlock_bh(&vsi->mac_filter_list_lock);
2408
0e4425ed
JB		 2409 /* schedule our worker thread which will take care of
2410 * applying the new filter changes
2411 */
2412 i40e_service_event_schedule(vsi->back);
2413 return 0;
41c445ff
JB		 2414}
2415
2416/**
2417 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2418 * @vsi: the vsi being configured
2419 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2420 *
2421 * Return: 0 on success or negative otherwise
41c445ff
JB		 2422 **/
2423int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2424{
2425 struct net_device *netdev = vsi->netdev;
2426 struct i40e_mac_filter *f, *add_f;
2427 bool is_vf, is_netdev;
2428 int filter_count = 0;
41c445ff
JB		 2429
2430 is_vf = (vsi->type == I40E_VSI_SRIOV);
2431 is_netdev = !!(netdev);
2432
21659035
KP		 2433 /* Locked once because all functions invoked below iterates list */
2434 spin_lock_bh(&vsi->mac_filter_list_lock);
2435
41c445ff
JB		 2436 if (is_netdev)
2437 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2438
2439 list_for_each_entry(f, &vsi->mac_filter_list, list)
2440 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2441
41c445ff
JB		 2442 /* go through all the filters for this VSI and if there is only
2443 * vid == 0 it means there are no other filters, so vid 0 must
2444 * be replaced with -1. This signifies that we should from now
2445 * on accept any traffic (with any tag present, or untagged)
2446 */
2447 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2448 if (is_netdev) {
2449 if (f->vlan &&
2450 ether_addr_equal(netdev->dev_addr, f->macaddr))
2451 filter_count++;
2452 }
2453
2454 if (f->vlan)
2455 filter_count++;
2456 }
2457
2458 if (!filter_count && is_netdev) {
2459 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2460 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2461 is_vf, is_netdev);
2462 if (!f) {
2463 dev_info(&vsi->back->pdev->dev,
2464 "Could not add filter %d for %pM\n",
2465 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2466 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2467 return -ENOMEM;
2468 }
2469 }
2470
2471 if (!filter_count) {
2472 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2473 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2474 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2475 is_vf, is_netdev);
41c445ff
JB		 2476 if (!add_f) {
2477 dev_info(&vsi->back->pdev->dev,
2478 "Could not add filter %d for %pM\n",
2479 I40E_VLAN_ANY, f->macaddr);
21659035 2480 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2481 return -ENOMEM;
2482 }
2483 }
2484 }
2485
21659035
KP		 2486 spin_unlock_bh(&vsi->mac_filter_list_lock);
2487
0e4425ed
JB		 2488 /* schedule our worker thread which will take care of
2489 * applying the new filter changes
2490 */
2491 i40e_service_event_schedule(vsi->back);
2492 return 0;
41c445ff
JB		 2493}
2494
2495/**
2496 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2497 * @netdev: network interface to be adjusted
2498 * @vid: vlan id to be added
078b5876
JB		 2499 *
2500 * net_device_ops implementation for adding vlan ids
41c445ff 2501 **/
38e00438
VD		 2502#ifdef I40E_FCOE
2503int i40e_vlan_rx_add_vid(struct net_device *netdev,
2504 __always_unused __be16 proto, u16 vid)
2505#else
41c445ff
JB		 2506static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2507 __always_unused __be16 proto, u16 vid)
38e00438 2508#endif
41c445ff
JB		 2509{
2510 struct i40e_netdev_priv *np = netdev_priv(netdev);
2511 struct i40e_vsi *vsi = np->vsi;
078b5876 2512 int ret = 0;
41c445ff
JB		 2513
2514 if (vid > 4095)
078b5876
JB		 2515 return -EINVAL;
2516
2517 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2518
6982d429
ASJ		 2519 /* If the network stack called us with vid = 0 then
2520 * it is asking to receive priority tagged packets with
2521 * vlan id 0. Our HW receives them by default when configured
2522 * to receive untagged packets so there is no need to add an
2523 * extra filter for vlan 0 tagged packets.
41c445ff 2524 */
6982d429
ASJ		 2525 if (vid)
2526 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2527
078b5876
JB		 2528 if (!ret && (vid < VLAN_N_VID))
2529 set_bit(vid, vsi->active_vlans);
41c445ff 2530
078b5876 2531 return ret;
41c445ff
JB		 2532}
2533
2534/**
2535 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2536 * @netdev: network interface to be adjusted
2537 * @vid: vlan id to be removed
078b5876 2538 *
fdfd943e 2539 * net_device_ops implementation for removing vlan ids
41c445ff 2540 **/
38e00438
VD		 2541#ifdef I40E_FCOE
2542int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2543 __always_unused __be16 proto, u16 vid)
2544#else
41c445ff
JB		 2545static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2546 __always_unused __be16 proto, u16 vid)
38e00438 2547#endif
41c445ff
JB		 2548{
2549 struct i40e_netdev_priv *np = netdev_priv(netdev);
2550 struct i40e_vsi *vsi = np->vsi;
2551
078b5876
JB		 2552 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2553
41c445ff
JB		 2554 /* return code is ignored as there is nothing a user
2555 * can do about failure to remove and a log message was
078b5876 2556 * already printed from the other function
41c445ff
JB		 2557 */
2558 i40e_vsi_kill_vlan(vsi, vid);
2559
2560 clear_bit(vid, vsi->active_vlans);
078b5876 2561
41c445ff
JB		 2562 return 0;
2563}
2564
2565/**
2566 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2567 * @vsi: the vsi being brought back up
2568 **/
2569static void i40e_restore_vlan(struct i40e_vsi *vsi)
2570{
2571 u16 vid;
2572
2573 if (!vsi->netdev)
2574 return;
2575
2576 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2577
2578 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2579 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2580 vid);
2581}
2582
2583/**
2584 * i40e_vsi_add_pvid - Add pvid for the VSI
2585 * @vsi: the vsi being adjusted
2586 * @vid: the vlan id to set as a PVID
2587 **/
dcae29be 2588int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2589{
2590 struct i40e_vsi_context ctxt;
f1c7e72e 2591 i40e_status ret;
41c445ff
JB		 2592
2593 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2594 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2595 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2596 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2597 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2598
2599 ctxt.seid = vsi->seid;
1a2f6248 2600 ctxt.info = vsi->info;
f1c7e72e
SN		 2601 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2602 if (ret) {
41c445ff 2603 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2604 "add pvid failed, err %s aq_err %s\n",
2605 i40e_stat_str(&vsi->back->hw, ret),
2606 i40e_aq_str(&vsi->back->hw,
2607 vsi->back->hw.aq.asq_last_status));
dcae29be 2608 return -ENOENT;
41c445ff
JB		 2609 }
2610
dcae29be 2611 return 0;
41c445ff
JB		 2612}
2613
2614/**
2615 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2616 * @vsi: the vsi being adjusted
2617 *
2618 * Just use the vlan_rx_register() service to put it back to normal
2619 **/
2620void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2621{
6c12fcbf
GR		 2622 i40e_vlan_stripping_disable(vsi);
2623
41c445ff 2624 vsi->info.pvid = 0;
41c445ff
JB		 2625}
2626
2627/**
2628 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2629 * @vsi: ptr to the VSI
2630 *
2631 * If this function returns with an error, then it's possible one or
2632 * more of the rings is populated (while the rest are not). It is the
2633 * callers duty to clean those orphaned rings.
2634 *
2635 * Return 0 on success, negative on failure
2636 **/
2637static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2638{
2639 int i, err = 0;
2640
2641 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2642 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2643
2644 return err;
2645}
2646
2647/**
2648 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2649 * @vsi: ptr to the VSI
2650 *
2651 * Free VSI's transmit software resources
2652 **/
2653static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2654{
2655 int i;
2656
8e9dca53
GR		 2657 if (!vsi->tx_rings)
2658 return;
2659
41c445ff 2660 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2661 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2662 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2663}
2664
2665/**
2666 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2667 * @vsi: ptr to the VSI
2668 *
2669 * If this function returns with an error, then it's possible one or
2670 * more of the rings is populated (while the rest are not). It is the
2671 * callers duty to clean those orphaned rings.
2672 *
2673 * Return 0 on success, negative on failure
2674 **/
2675static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2676{
2677 int i, err = 0;
2678
2679 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2680 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2681#ifdef I40E_FCOE
2682 i40e_fcoe_setup_ddp_resources(vsi);
2683#endif
41c445ff
JB		 2684 return err;
2685}
2686
2687/**
2688 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2689 * @vsi: ptr to the VSI
2690 *
2691 * Free all receive software resources
2692 **/
2693static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2694{
2695 int i;
2696
8e9dca53
GR		 2697 if (!vsi->rx_rings)
2698 return;
2699
41c445ff 2700 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2701 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2702 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2703#ifdef I40E_FCOE
2704 i40e_fcoe_free_ddp_resources(vsi);
2705#endif
41c445ff
JB		 2706}
2707
3ffa037d
NP		 2708/**
2709 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2710 * @ring: The Tx ring to configure
2711 *
2712 * This enables/disables XPS for a given Tx descriptor ring
2713 * based on the TCs enabled for the VSI that ring belongs to.
2714 **/
2715static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2716{
2717 struct i40e_vsi *vsi = ring->vsi;
2718 cpumask_var_t mask;
2719
9a660eea
JB		 2720 if (!ring->q_vector || !ring->netdev)
2721 return;
2722
2723 /* Single TC mode enable XPS */
2724 if (vsi->tc_config.numtc <= 1) {
2725 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2726 netif_set_xps_queue(ring->netdev,
2727 &ring->q_vector->affinity_mask,
2728 ring->queue_index);
9a660eea
JB		 2729 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2730 /* Disable XPS to allow selection based on TC */
2731 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2732 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2733 free_cpumask_var(mask);
3ffa037d 2734 }
0e4425ed
JB		 2735
2736 /* schedule our worker thread which will take care of
2737 * applying the new filter changes
2738 */
2739 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2740}
2741
41c445ff
JB		 2742/**
2743 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2744 * @ring: The Tx ring to configure
2745 *
2746 * Configure the Tx descriptor ring in the HMC context.
2747 **/
2748static int i40e_configure_tx_ring(struct i40e_ring *ring)
2749{
2750 struct i40e_vsi *vsi = ring->vsi;
2751 u16 pf_q = vsi->base_queue + ring->queue_index;
2752 struct i40e_hw *hw = &vsi->back->hw;
2753 struct i40e_hmc_obj_txq tx_ctx;
2754 i40e_status err = 0;
2755 u32 qtx_ctl = 0;
2756
2757 /* some ATR related tx ring init */
60ea5f83 2758 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2759 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2760 ring->atr_count = 0;
2761 } else {
2762 ring->atr_sample_rate = 0;
2763 }
2764
3ffa037d
NP		 2765 /* configure XPS */
2766 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2767
2768 /* clear the context structure first */
2769 memset(&tx_ctx, 0, sizeof(tx_ctx));
2770
2771 tx_ctx.new_context = 1;
2772 tx_ctx.base = (ring->dma / 128);
2773 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2774 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2775 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2776#ifdef I40E_FCOE
2777 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2778#endif
beb0dff1 2779 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2780 /* FDIR VSI tx ring can still use RS bit and writebacks */
2781 if (vsi->type != I40E_VSI_FDIR)
2782 tx_ctx.head_wb_ena = 1;
2783 tx_ctx.head_wb_addr = ring->dma +
2784 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2785
2786 /* As part of VSI creation/update, FW allocates certain
2787 * Tx arbitration queue sets for each TC enabled for
2788 * the VSI. The FW returns the handles to these queue
2789 * sets as part of the response buffer to Add VSI,
2790 * Update VSI, etc. AQ commands. It is expected that
2791 * these queue set handles be associated with the Tx
2792 * queues by the driver as part of the TX queue context
2793 * initialization. This has to be done regardless of
2794 * DCB as by default everything is mapped to TC0.
2795 */
2796 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2797 tx_ctx.rdylist_act = 0;
2798
2799 /* clear the context in the HMC */
2800 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2801 if (err) {
2802 dev_info(&vsi->back->pdev->dev,
2803 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2804 ring->queue_index, pf_q, err);
2805 return -ENOMEM;
2806 }
2807
2808 /* set the context in the HMC */
2809 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2810 if (err) {
2811 dev_info(&vsi->back->pdev->dev,
2812 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2813 ring->queue_index, pf_q, err);
2814 return -ENOMEM;
2815 }
2816
2817 /* Now associate this queue with this PCI function */
7a28d885 2818 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2819 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2820 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2821 I40E_QTX_CTL_VFVM_INDX_MASK;
2822 } else {
9d8bf547 2823 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2824 }
2825
13fd9774
SN		 2826 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2827 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2828 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2829 i40e_flush(hw);
2830
41c445ff
JB		 2831 /* cache tail off for easier writes later */
2832 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2833
2834 return 0;
2835}
2836
2837/**
2838 * i40e_configure_rx_ring - Configure a receive ring context
2839 * @ring: The Rx ring to configure
2840 *
2841 * Configure the Rx descriptor ring in the HMC context.
2842 **/
2843static int i40e_configure_rx_ring(struct i40e_ring *ring)
2844{
2845 struct i40e_vsi *vsi = ring->vsi;
2846 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2847 u16 pf_q = vsi->base_queue + ring->queue_index;
2848 struct i40e_hw *hw = &vsi->back->hw;
2849 struct i40e_hmc_obj_rxq rx_ctx;
2850 i40e_status err = 0;
2851
2852 ring->state = 0;
2853
2854 /* clear the context structure first */
2855 memset(&rx_ctx, 0, sizeof(rx_ctx));
2856
2857 ring->rx_buf_len = vsi->rx_buf_len;
41c445ff
JB		 2858
2859 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
41c445ff
JB		 2860
2861 rx_ctx.base = (ring->dma / 128);
2862 rx_ctx.qlen = ring->count;
2863
bec60fc4
JB		 2864 /* use 32 byte descriptors */
2865 rx_ctx.dsize = 1;
41c445ff 2866
bec60fc4
JB		 2867 /* descriptor type is always zero
2868 * rx_ctx.dtype = 0;
2869 */
b32bfa17 2870 rx_ctx.hsplit_0 = 0;
41c445ff 2871
b32bfa17 2872 rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len);
7134f9ce
JB		 2873 if (hw->revision_id == 0)
2874 rx_ctx.lrxqthresh = 0;
2875 else
2876 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2877 rx_ctx.crcstrip = 1;
2878 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2879 /* this controls whether VLAN is stripped from inner headers */
2880 rx_ctx.showiv = 0;
38e00438
VD		 2881#ifdef I40E_FCOE
2882 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2883#endif
acb3676b
CS		 2884 /* set the prefena field to 1 because the manual says to */
2885 rx_ctx.prefena = 1;
41c445ff
JB		 2886
2887 /* clear the context in the HMC */
2888 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2889 if (err) {
2890 dev_info(&vsi->back->pdev->dev,
2891 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2892 ring->queue_index, pf_q, err);
2893 return -ENOMEM;
2894 }
2895
2896 /* set the context in the HMC */
2897 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2898 if (err) {
2899 dev_info(&vsi->back->pdev->dev,
2900 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2901 ring->queue_index, pf_q, err);
2902 return -ENOMEM;
2903 }
2904
2905 /* cache tail for quicker writes, and clear the reg before use */
2906 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2907 writel(0, ring->tail);
2908
1a557afc 2909 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
41c445ff
JB		 2910
2911 return 0;
2912}
2913
2914/**
2915 * i40e_vsi_configure_tx - Configure the VSI for Tx
2916 * @vsi: VSI structure describing this set of rings and resources
2917 *
2918 * Configure the Tx VSI for operation.
2919 **/
2920static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2921{
2922 int err = 0;
2923 u16 i;
2924
9f65e15b
AD		 2925 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2926 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2927
2928 return err;
2929}
2930
2931/**
2932 * i40e_vsi_configure_rx - Configure the VSI for Rx
2933 * @vsi: the VSI being configured
2934 *
2935 * Configure the Rx VSI for operation.
2936 **/
2937static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2938{
2939 int err = 0;
2940 u16 i;
2941
2942 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2943 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2944 + ETH_FCS_LEN + VLAN_HLEN;
2945 else
2946 vsi->max_frame = I40E_RXBUFFER_2048;
2947
1a557afc 2948 vsi->rx_buf_len = I40E_RXBUFFER_2048;
41c445ff 2949
38e00438
VD		 2950#ifdef I40E_FCOE
2951 /* setup rx buffer for FCoE */
2952 if ((vsi->type == I40E_VSI_FCOE) &&
2953 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
38e00438
VD		 2954 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2955 vsi->max_frame = I40E_RXBUFFER_3072;
38e00438
VD		 2956 }
2957
2958#endif /* I40E_FCOE */
41c445ff 2959 /* round up for the chip's needs */
41c445ff 2960 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2961 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2962
2963 /* set up individual rings */
2964 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2965 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2966
2967 return err;
2968}
2969
2970/**
2971 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2972 * @vsi: ptr to the VSI
2973 **/
2974static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2975{
e7046ee1 2976 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2977 u16 qoffset, qcount;
2978 int i, n;
2979
cd238a3e
PN		 2980 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2981 /* Reset the TC information */
2982 for (i = 0; i < vsi->num_queue_pairs; i++) {
2983 rx_ring = vsi->rx_rings[i];
2984 tx_ring = vsi->tx_rings[i];
2985 rx_ring->dcb_tc = 0;
2986 tx_ring->dcb_tc = 0;
2987 }
2988 }
41c445ff
JB		 2989
2990 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2991 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2992 continue;
2993
2994 qoffset = vsi->tc_config.tc_info[n].qoffset;
2995 qcount = vsi->tc_config.tc_info[n].qcount;
2996 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2997 rx_ring = vsi->rx_rings[i];
2998 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2999 rx_ring->dcb_tc = n;
3000 tx_ring->dcb_tc = n;
3001 }
3002 }
3003}
3004
3005/**
3006 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3007 * @vsi: ptr to the VSI
3008 **/
3009static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3010{
3011 if (vsi->netdev)
3012 i40e_set_rx_mode(vsi->netdev);
3013}
3014
17a73f6b
JG		 3015/**
3016 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3017 * @vsi: Pointer to the targeted VSI
3018 *
3019 * This function replays the hlist on the hw where all the SB Flow Director
3020 * filters were saved.
3021 **/
3022static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3023{
3024 struct i40e_fdir_filter *filter;
3025 struct i40e_pf *pf = vsi->back;
3026 struct hlist_node *node;
3027
55a5e60b
ASJ		 3028 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3029 return;
3030
17a73f6b
JG		 3031 hlist_for_each_entry_safe(filter, node,
3032 &pf->fdir_filter_list, fdir_node) {
3033 i40e_add_del_fdir(vsi, filter, true);
3034 }
3035}
3036
41c445ff
JB		 3037/**
3038 * i40e_vsi_configure - Set up the VSI for action
3039 * @vsi: the VSI being configured
3040 **/
3041static int i40e_vsi_configure(struct i40e_vsi *vsi)
3042{
3043 int err;
3044
3045 i40e_set_vsi_rx_mode(vsi);
3046 i40e_restore_vlan(vsi);
3047 i40e_vsi_config_dcb_rings(vsi);
3048 err = i40e_vsi_configure_tx(vsi);
3049 if (!err)
3050 err = i40e_vsi_configure_rx(vsi);
3051
3052 return err;
3053}
3054
3055/**
3056 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3057 * @vsi: the VSI being configured
3058 **/
3059static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3060{
3061 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3062 struct i40e_hw *hw = &pf->hw;
3063 u16 vector;
3064 int i, q;
41c445ff
JB		 3065 u32 qp;
3066
3067 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3068 * and PFINT_LNKLSTn registers, e.g.:
3069 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3070 */
3071 qp = vsi->base_queue;
3072 vector = vsi->base_vector;
493fb300 3073 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3074 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3075
ee2319cf 3076 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3077 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting);
41c445ff
JB		 3078 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3079 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3080 q_vector->rx.itr);
a75e8005 3081 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting);
41c445ff
JB		 3082 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3083 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3084 q_vector->tx.itr);
ac26fc13
JB		 3085 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3086 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3087
3088 /* Linked list for the queuepairs assigned to this vector */
3089 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3090 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3091 u32 val;
3092
41c445ff
JB		 3093 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3094 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3095 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3096 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3097 (I40E_QUEUE_TYPE_TX
3098 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3099
3100 wr32(hw, I40E_QINT_RQCTL(qp), val);
3101
3102 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3103 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3104 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3105 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3106 (I40E_QUEUE_TYPE_RX
3107 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3108
3109 /* Terminate the linked list */
3110 if (q == (q_vector->num_ringpairs - 1))
3111 val |= (I40E_QUEUE_END_OF_LIST
3112 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3113
3114 wr32(hw, I40E_QINT_TQCTL(qp), val);
3115 qp++;
3116 }
3117 }
3118
3119 i40e_flush(hw);
3120}
3121
3122/**
3123 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3124 * @hw: ptr to the hardware info
3125 **/
ab437b5a 3126static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3127{
ab437b5a 3128 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3129 u32 val;
3130
3131 /* clear things first */
3132 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3133 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3134
3135 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3136 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3137 I40E_PFINT_ICR0_ENA_GRST_MASK |
3138 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3139 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3140 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3141 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3142 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3143
0d8e1439
ASJ		 3144 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3145 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3146
ab437b5a
JK		 3147 if (pf->flags & I40E_FLAG_PTP)
3148 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3149
41c445ff
JB		 3150 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3151
3152 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3153 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3154 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3155
3156 /* OTHER_ITR_IDX = 0 */
3157 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3158}
3159
3160/**
3161 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3162 * @vsi: the VSI being configured
3163 **/
3164static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3165{
493fb300 3166 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3167 struct i40e_pf *pf = vsi->back;
3168 struct i40e_hw *hw = &pf->hw;
3169 u32 val;
3170
3171 /* set the ITR configuration */
ee2319cf 3172 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3173 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting);
41c445ff
JB		 3174 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3175 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
a75e8005 3176 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting);
41c445ff
JB		 3177 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3178 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3179
ab437b5a 3180 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3181
3182 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3183 wr32(hw, I40E_PFINT_LNKLST0, 0);
3184
f29eaa3d 3185 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3186 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3187 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3188 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3189
3190 wr32(hw, I40E_QINT_RQCTL(0), val);
3191
3192 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3193 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3194 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3195
3196 wr32(hw, I40E_QINT_TQCTL(0), val);
3197 i40e_flush(hw);
3198}
3199
2ef28cfb
MW		 3200/**
3201 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3202 * @pf: board private structure
3203 **/
3204void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3205{
3206 struct i40e_hw *hw = &pf->hw;
3207
3208 wr32(hw, I40E_PFINT_DYN_CTL0,
3209 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3210 i40e_flush(hw);
3211}
3212
41c445ff
JB		 3213/**
3214 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3215 * @pf: board private structure
40d72a50 3216 * @clearpba: true when all pending interrupt events should be cleared
41c445ff 3217 **/
40d72a50 3218void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba)
41c445ff
JB		 3219{
3220 struct i40e_hw *hw = &pf->hw;
3221 u32 val;
3222
3223 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
40d72a50 3224 (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) |
41c445ff
JB		 3225 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3226
3227 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3228 i40e_flush(hw);
3229}
3230
41c445ff
JB		 3231/**
3232 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3233 * @irq: interrupt number
3234 * @data: pointer to a q_vector
3235 **/
3236static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3237{
3238 struct i40e_q_vector *q_vector = data;
3239
cd0b6fa6 3240 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3241 return IRQ_HANDLED;
3242
5d3465a1 3243 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3244
3245 return IRQ_HANDLED;
3246}
3247
41c445ff
JB		 3248/**
3249 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3250 * @vsi: the VSI being configured
3251 * @basename: name for the vector
3252 *
3253 * Allocates MSI-X vectors and requests interrupts from the kernel.
3254 **/
3255static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3256{
3257 int q_vectors = vsi->num_q_vectors;
3258 struct i40e_pf *pf = vsi->back;
3259 int base = vsi->base_vector;
3260 int rx_int_idx = 0;
3261 int tx_int_idx = 0;
3262 int vector, err;
3263
3264 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3265 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3266
cd0b6fa6 3267 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3268 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3269 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3270 tx_int_idx++;
cd0b6fa6 3271 } else if (q_vector->rx.ring) {
41c445ff
JB		 3272 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3273 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3274 } else if (q_vector->tx.ring) {
41c445ff
JB		 3275 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3276 "%s-%s-%d", basename, "tx", tx_int_idx++);
3277 } else {
3278 /* skip this unused q_vector */
3279 continue;
3280 }
3281 err = request_irq(pf->msix_entries[base + vector].vector,
3282 vsi->irq_handler,
3283 0,
3284 q_vector->name,
3285 q_vector);
3286 if (err) {
3287 dev_info(&pf->pdev->dev,
fb43201f 3288 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3289 goto free_queue_irqs;
3290 }
3291 /* assign the mask for this irq */
3292 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3293 &q_vector->affinity_mask);
3294 }
3295
63741846 3296 vsi->irqs_ready = true;
41c445ff
JB		 3297 return 0;
3298
3299free_queue_irqs:
3300 while (vector) {
3301 vector--;
3302 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3303 NULL);
3304 free_irq(pf->msix_entries[base + vector].vector,
3305 &(vsi->q_vectors[vector]));
3306 }
3307 return err;
3308}
3309
3310/**
3311 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3312 * @vsi: the VSI being un-configured
3313 **/
3314static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3315{
3316 struct i40e_pf *pf = vsi->back;
3317 struct i40e_hw *hw = &pf->hw;
3318 int base = vsi->base_vector;
3319 int i;
3320
3321 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3322 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3323 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3324 }
3325
3326 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3327 for (i = vsi->base_vector;
3328 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3329 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3330
3331 i40e_flush(hw);
3332 for (i = 0; i < vsi->num_q_vectors; i++)
3333 synchronize_irq(pf->msix_entries[i + base].vector);
3334 } else {
3335 /* Legacy and MSI mode - this stops all interrupt handling */
3336 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3337 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3338 i40e_flush(hw);
3339 synchronize_irq(pf->pdev->irq);
3340 }
3341}
3342
3343/**
3344 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3345 * @vsi: the VSI being configured
3346 **/
3347static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3348{
3349 struct i40e_pf *pf = vsi->back;
3350 int i;
3351
3352 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3353 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3354 i40e_irq_dynamic_enable(vsi, i);
3355 } else {
40d72a50 3356 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 3357 }
3358
1022cb6c 3359 i40e_flush(&pf->hw);
41c445ff
JB		 3360 return 0;
3361}
3362
3363/**
3364 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3365 * @pf: board private structure
3366 **/
3367static void i40e_stop_misc_vector(struct i40e_pf *pf)
3368{
3369 /* Disable ICR 0 */
3370 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3371 i40e_flush(&pf->hw);
3372}
3373
3374/**
3375 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3376 * @irq: interrupt number
3377 * @data: pointer to a q_vector
3378 *
3379 * This is the handler used for all MSI/Legacy interrupts, and deals
3380 * with both queue and non-queue interrupts. This is also used in
3381 * MSIX mode to handle the non-queue interrupts.
3382 **/
3383static irqreturn_t i40e_intr(int irq, void *data)
3384{
3385 struct i40e_pf *pf = (struct i40e_pf *)data;
3386 struct i40e_hw *hw = &pf->hw;
5e823066 3387 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3388 u32 icr0, icr0_remaining;
3389 u32 val, ena_mask;
3390
3391 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3392 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3393
116a57d4
SN		 3394 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3395 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3396 goto enable_intr;
41c445ff 3397
cd92e72f
SN		 3398 /* if interrupt but no bits showing, must be SWINT */
3399 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3400 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3401 pf->sw_int_count++;
3402
0d8e1439
ASJ		 3403 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3404 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3405 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3406 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3407 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3408 }
3409
41c445ff
JB		 3410 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3411 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3412 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3413 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff 3414
a16ae2d5
ASJ		 3415 /* We do not have a way to disarm Queue causes while leaving
3416 * interrupt enabled for all other causes, ideally
3417 * interrupt should be disabled while we are in NAPI but
3418 * this is not a performance path and napi_schedule()
3419 * can deal with rescheduling.
3420 */
41c445ff 3421 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3422 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3423 }
3424
3425 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3426 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3427 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6e93d0c9 3428 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n");
41c445ff
JB		 3429 }
3430
3431 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3432 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3433 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3434 }
3435
3436 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3437 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3438 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3439 }
3440
3441 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3442 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3443 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3444 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3445 val = rd32(hw, I40E_GLGEN_RSTAT);
3446 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3447 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3448 if (val == I40E_RESET_CORER) {
41c445ff 3449 pf->corer_count++;
4eb3f768 3450 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3451 pf->globr_count++;
4eb3f768 3452 } else if (val == I40E_RESET_EMPR) {
41c445ff 3453 pf->empr_count++;
9df42d1a 3454 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3455 }
41c445ff
JB		 3456 }
3457
9c010ee0
ASJ		 3458 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3459 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3460 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3461 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3462 rd32(hw, I40E_PFHMC_ERRORINFO),
3463 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3464 }
3465
beb0dff1
JK		 3466 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3467 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3468
3469 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3470 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3471 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3472 }
beb0dff1
JK		 3473 }
3474
41c445ff
JB		 3475 /* If a critical error is pending we have no choice but to reset the
3476 * device.
3477 * Report and mask out any remaining unexpected interrupts.
3478 */
3479 icr0_remaining = icr0 & ena_mask;
3480 if (icr0_remaining) {
3481 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3482 icr0_remaining);
9c010ee0 3483 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3484 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3485 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3486 dev_info(&pf->pdev->dev, "device will be reset\n");
3487 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3488 i40e_service_event_schedule(pf);
41c445ff
JB		 3489 }
3490 ena_mask &= ~icr0_remaining;
3491 }
5e823066 3492 ret = IRQ_HANDLED;
41c445ff 3493
5e823066 3494enable_intr:
41c445ff
JB		 3495 /* re-enable interrupt causes */
3496 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3497 if (!test_bit(__I40E_DOWN, &pf->state)) {
3498 i40e_service_event_schedule(pf);
40d72a50 3499 i40e_irq_dynamic_enable_icr0(pf, false);
41c445ff
JB		 3500 }
3501
5e823066 3502 return ret;
41c445ff
JB		 3503}
3504
cbf61325
ASJ		 3505/**
3506 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3507 * @tx_ring: tx ring to clean
3508 * @budget: how many cleans we're allowed
3509 *
3510 * Returns true if there's any budget left (e.g. the clean is finished)
3511 **/
3512static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3513{
3514 struct i40e_vsi *vsi = tx_ring->vsi;
3515 u16 i = tx_ring->next_to_clean;
3516 struct i40e_tx_buffer *tx_buf;
3517 struct i40e_tx_desc *tx_desc;
3518
3519 tx_buf = &tx_ring->tx_bi[i];
3520 tx_desc = I40E_TX_DESC(tx_ring, i);
3521 i -= tx_ring->count;
3522
3523 do {
3524 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3525
3526 /* if next_to_watch is not set then there is no work pending */
3527 if (!eop_desc)
3528 break;
3529
3530 /* prevent any other reads prior to eop_desc */
3531 read_barrier_depends();
3532
3533 /* if the descriptor isn't done, no work yet to do */
3534 if (!(eop_desc->cmd_type_offset_bsz &
3535 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3536 break;
3537
3538 /* clear next_to_watch to prevent false hangs */
3539 tx_buf->next_to_watch = NULL;
3540
49d7d933
ASJ		 3541 tx_desc->buffer_addr = 0;
3542 tx_desc->cmd_type_offset_bsz = 0;
3543 /* move past filter desc */
3544 tx_buf++;
3545 tx_desc++;
3546 i++;
3547 if (unlikely(!i)) {
3548 i -= tx_ring->count;
3549 tx_buf = tx_ring->tx_bi;
3550 tx_desc = I40E_TX_DESC(tx_ring, 0);
3551 }
cbf61325
ASJ		 3552 /* unmap skb header data */
3553 dma_unmap_single(tx_ring->dev,
3554 dma_unmap_addr(tx_buf, dma),
3555 dma_unmap_len(tx_buf, len),
3556 DMA_TO_DEVICE);
49d7d933
ASJ		 3557 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3558 kfree(tx_buf->raw_buf);
cbf61325 3559
49d7d933
ASJ		 3560 tx_buf->raw_buf = NULL;
3561 tx_buf->tx_flags = 0;
3562 tx_buf->next_to_watch = NULL;
cbf61325 3563 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3564 tx_desc->buffer_addr = 0;
3565 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3566
49d7d933 3567 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3568 tx_buf++;
3569 tx_desc++;
3570 i++;
3571 if (unlikely(!i)) {
3572 i -= tx_ring->count;
3573 tx_buf = tx_ring->tx_bi;
3574 tx_desc = I40E_TX_DESC(tx_ring, 0);
3575 }
3576
3577 /* update budget accounting */
3578 budget--;
3579 } while (likely(budget));
3580
3581 i += tx_ring->count;
3582 tx_ring->next_to_clean = i;
3583
6995b36c 3584 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3585 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3586
cbf61325
ASJ		 3587 return budget > 0;
3588}
3589
3590/**
3591 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3592 * @irq: interrupt number
3593 * @data: pointer to a q_vector
3594 **/
3595static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3596{
3597 struct i40e_q_vector *q_vector = data;
3598 struct i40e_vsi *vsi;
3599
3600 if (!q_vector->tx.ring)
3601 return IRQ_HANDLED;
3602
3603 vsi = q_vector->tx.ring->vsi;
3604 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3605
3606 return IRQ_HANDLED;
3607}
3608
41c445ff 3609/**
cd0b6fa6 3610 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3611 * @vsi: the VSI being configured
3612 * @v_idx: vector index
cd0b6fa6 3613 * @qp_idx: queue pair index
41c445ff 3614 **/
26cdc443 3615static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3616{
493fb300 3617 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3618 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3619 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3620
3621 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3622 tx_ring->next = q_vector->tx.ring;
3623 q_vector->tx.ring = tx_ring;
41c445ff 3624 q_vector->tx.count++;
cd0b6fa6
AD		 3625
3626 rx_ring->q_vector = q_vector;
3627 rx_ring->next = q_vector->rx.ring;
3628 q_vector->rx.ring = rx_ring;
3629 q_vector->rx.count++;
41c445ff
JB		 3630}
3631
3632/**
3633 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3634 * @vsi: the VSI being configured
3635 *
3636 * This function maps descriptor rings to the queue-specific vectors
3637 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3638 * one vector per queue pair, but on a constrained vector budget, we
3639 * group the queue pairs as "efficiently" as possible.
3640 **/
3641static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3642{
3643 int qp_remaining = vsi->num_queue_pairs;
3644 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3645 int num_ringpairs;
41c445ff
JB		 3646 int v_start = 0;
3647 int qp_idx = 0;
3648
3649 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3650 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3651 * It is also important to go through all the vectors available to be
3652 * sure that if we don't use all the vectors, that the remaining vectors
3653 * are cleared. This is especially important when decreasing the
3654 * number of queues in use.
41c445ff 3655 */
70114ec4 3656 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3657 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3658
3659 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3660
3661 q_vector->num_ringpairs = num_ringpairs;
3662
3663 q_vector->rx.count = 0;
3664 q_vector->tx.count = 0;
3665 q_vector->rx.ring = NULL;
3666 q_vector->tx.ring = NULL;
3667
3668 while (num_ringpairs--) {
26cdc443 3669 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3670 qp_idx++;
3671 qp_remaining--;
41c445ff
JB		 3672 }
3673 }
3674}
3675
3676/**
3677 * i40e_vsi_request_irq - Request IRQ from the OS
3678 * @vsi: the VSI being configured
3679 * @basename: name for the vector
3680 **/
3681static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3682{
3683 struct i40e_pf *pf = vsi->back;
3684 int err;
3685
3686 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3687 err = i40e_vsi_request_irq_msix(vsi, basename);
3688 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3689 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3690 pf->int_name, pf);
41c445ff
JB		 3691 else
3692 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3693 pf->int_name, pf);
41c445ff
JB		 3694
3695 if (err)
3696 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3697
3698 return err;
3699}
3700
3701#ifdef CONFIG_NET_POLL_CONTROLLER
3702/**
d89d967f 3703 * i40e_netpoll - A Polling 'interrupt' handler
41c445ff
JB		 3704 * @netdev: network interface device structure
3705 *
3706 * This is used by netconsole to send skbs without having to re-enable
3707 * interrupts. It's not called while the normal interrupt routine is executing.
3708 **/
38e00438
VD		 3709#ifdef I40E_FCOE
3710void i40e_netpoll(struct net_device *netdev)
3711#else
41c445ff 3712static void i40e_netpoll(struct net_device *netdev)
38e00438 3713#endif
41c445ff
JB		 3714{
3715 struct i40e_netdev_priv *np = netdev_priv(netdev);
3716 struct i40e_vsi *vsi = np->vsi;
3717 struct i40e_pf *pf = vsi->back;
3718 int i;
3719
3720 /* if interface is down do nothing */
3721 if (test_bit(__I40E_DOWN, &vsi->state))
3722 return;
3723
41c445ff
JB		 3724 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3725 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3726 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3727 } else {
3728 i40e_intr(pf->pdev->irq, netdev);
3729 }
41c445ff
JB		 3730}
3731#endif
3732
23527308
NP		 3733/**
3734 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3735 * @pf: the PF being configured
3736 * @pf_q: the PF queue
3737 * @enable: enable or disable state of the queue
3738 *
3739 * This routine will wait for the given Tx queue of the PF to reach the
3740 * enabled or disabled state.
3741 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3742 * multiple retries; else will return 0 in case of success.
3743 **/
3744static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3745{
3746 int i;
3747 u32 tx_reg;
3748
3749 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3750 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3751 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3752 break;
3753
f98a2006 3754 usleep_range(10, 20);
23527308
NP		 3755 }
3756 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3757 return -ETIMEDOUT;
3758
3759 return 0;
3760}
3761
41c445ff
JB		 3762/**
3763 * i40e_vsi_control_tx - Start or stop a VSI's rings
3764 * @vsi: the VSI being configured
3765 * @enable: start or stop the rings
3766 **/
3767static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3768{
3769 struct i40e_pf *pf = vsi->back;
3770 struct i40e_hw *hw = &pf->hw;
23527308 3771 int i, j, pf_q, ret = 0;
41c445ff
JB		 3772 u32 tx_reg;
3773
3774 pf_q = vsi->base_queue;
3775 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3776
3777 /* warn the TX unit of coming changes */
3778 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3779 if (!enable)
f98a2006 3780 usleep_range(10, 20);
351499ab 3781
6c5ef620 3782 for (j = 0; j < 50; j++) {
41c445ff 3783 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3784 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3785 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3786 break;
3787 usleep_range(1000, 2000);
3788 }
fda972f6 3789 /* Skip if the queue is already in the requested state */
7c122007 3790 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3791 continue;
41c445ff
JB		 3792
3793 /* turn on/off the queue */
c5c9eb9e
SN		 3794 if (enable) {
3795 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3796 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3797 } else {
41c445ff 3798 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3799 }
41c445ff
JB		 3800
3801 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3802 /* No waiting for the Tx queue to disable */
3803 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3804 continue;
41c445ff
JB		 3805
3806 /* wait for the change to finish */
23527308
NP		 3807 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3808 if (ret) {
3809 dev_info(&pf->pdev->dev,
fb43201f
SN		 3810 "VSI seid %d Tx ring %d %sable timeout\n",
3811 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3812 break;
41c445ff
JB		 3813 }
3814 }
3815
7134f9ce
JB		 3816 if (hw->revision_id == 0)
3817 mdelay(50);
23527308
NP		 3818 return ret;
3819}
3820
3821/**
3822 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3823 * @pf: the PF being configured
3824 * @pf_q: the PF queue
3825 * @enable: enable or disable state of the queue
3826 *
3827 * This routine will wait for the given Rx queue of the PF to reach the
3828 * enabled or disabled state.
3829 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3830 * multiple retries; else will return 0 in case of success.
3831 **/
3832static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3833{
3834 int i;
3835 u32 rx_reg;
3836
3837 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3838 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3839 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3840 break;
3841
f98a2006 3842 usleep_range(10, 20);
23527308
NP		 3843 }
3844 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3845 return -ETIMEDOUT;
7134f9ce 3846
41c445ff
JB		 3847 return 0;
3848}
3849
3850/**
3851 * i40e_vsi_control_rx - Start or stop a VSI's rings
3852 * @vsi: the VSI being configured
3853 * @enable: start or stop the rings
3854 **/
3855static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3856{
3857 struct i40e_pf *pf = vsi->back;
3858 struct i40e_hw *hw = &pf->hw;
23527308 3859 int i, j, pf_q, ret = 0;
41c445ff
JB		 3860 u32 rx_reg;
3861
3862 pf_q = vsi->base_queue;
3863 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3864 for (j = 0; j < 50; j++) {
41c445ff 3865 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3866 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3867 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3868 break;
3869 usleep_range(1000, 2000);
3870 }
41c445ff 3871
7c122007
CS		 3872 /* Skip if the queue is already in the requested state */
3873 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3874 continue;
41c445ff
JB		 3875
3876 /* turn on/off the queue */
3877 if (enable)
6c5ef620 3878 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3879 else
6c5ef620 3880 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3881 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3fe06f41
NP		 3882 /* No waiting for the Tx queue to disable */
3883 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3884 continue;
41c445ff
JB		 3885
3886 /* wait for the change to finish */
23527308
NP		 3887 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3888 if (ret) {
3889 dev_info(&pf->pdev->dev,
fb43201f
SN		 3890 "VSI seid %d Rx ring %d %sable timeout\n",
3891 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3892 break;
41c445ff
JB		 3893 }
3894 }
3895
23527308 3896 return ret;
41c445ff
JB		 3897}
3898
3899/**
3900 * i40e_vsi_control_rings - Start or stop a VSI's rings
3901 * @vsi: the VSI being configured
3902 * @enable: start or stop the rings
3903 **/
fc18eaa0 3904int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3905{
3b867b28 3906 int ret = 0;
41c445ff
JB		 3907
3908 /* do rx first for enable and last for disable */
3909 if (request) {
3910 ret = i40e_vsi_control_rx(vsi, request);
3911 if (ret)
3912 return ret;
3913 ret = i40e_vsi_control_tx(vsi, request);
3914 } else {
3b867b28
ASJ		 3915 /* Ignore return value, we need to shutdown whatever we can */
3916 i40e_vsi_control_tx(vsi, request);
3917 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3918 }
3919
3920 return ret;
3921}
3922
3923/**
3924 * i40e_vsi_free_irq - Free the irq association with the OS
3925 * @vsi: the VSI being configured
3926 **/
3927static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3928{
3929 struct i40e_pf *pf = vsi->back;
3930 struct i40e_hw *hw = &pf->hw;
3931 int base = vsi->base_vector;
3932 u32 val, qp;
3933 int i;
3934
3935 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3936 if (!vsi->q_vectors)
3937 return;
3938
63741846
SN		 3939 if (!vsi->irqs_ready)
3940 return;
3941
3942 vsi->irqs_ready = false;
41c445ff
JB		 3943 for (i = 0; i < vsi->num_q_vectors; i++) {
3944 u16 vector = i + base;
3945
3946 /* free only the irqs that were actually requested */
78681b1f
SN		 3947 if (!vsi->q_vectors[i] ||
3948 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3949 continue;
3950
3951 /* clear the affinity_mask in the IRQ descriptor */
3952 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3953 NULL);
3954 free_irq(pf->msix_entries[vector].vector,
493fb300 3955 vsi->q_vectors[i]);
41c445ff
JB		 3956
3957 /* Tear down the interrupt queue link list
3958 *
3959 * We know that they come in pairs and always
3960 * the Rx first, then the Tx. To clear the
3961 * link list, stick the EOL value into the
3962 * next_q field of the registers.
3963 */
3964 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3965 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3966 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3967 val |= I40E_QUEUE_END_OF_LIST
3968 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3969 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3970
3971 while (qp != I40E_QUEUE_END_OF_LIST) {
3972 u32 next;
3973
3974 val = rd32(hw, I40E_QINT_RQCTL(qp));
3975
3976 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3977 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3978 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3979 I40E_QINT_RQCTL_INTEVENT_MASK);
3980
3981 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3982 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3983
3984 wr32(hw, I40E_QINT_RQCTL(qp), val);
3985
3986 val = rd32(hw, I40E_QINT_TQCTL(qp));
3987
3988 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3989 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3990
3991 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3992 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3993 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3994 I40E_QINT_TQCTL_INTEVENT_MASK);
3995
3996 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3997 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3998
3999 wr32(hw, I40E_QINT_TQCTL(qp), val);
4000 qp = next;
4001 }
4002 }
4003 } else {
4004 free_irq(pf->pdev->irq, pf);
4005
4006 val = rd32(hw, I40E_PFINT_LNKLST0);
4007 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4008 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4009 val |= I40E_QUEUE_END_OF_LIST
4010 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4011 wr32(hw, I40E_PFINT_LNKLST0, val);
4012
4013 val = rd32(hw, I40E_QINT_RQCTL(qp));
4014 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4015 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4016 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4017 I40E_QINT_RQCTL_INTEVENT_MASK);
4018
4019 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4020 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4021
4022 wr32(hw, I40E_QINT_RQCTL(qp), val);
4023
4024 val = rd32(hw, I40E_QINT_TQCTL(qp));
4025
4026 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4027 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4028 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4029 I40E_QINT_TQCTL_INTEVENT_MASK);
4030
4031 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4032 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4033
4034 wr32(hw, I40E_QINT_TQCTL(qp), val);
4035 }
4036}
4037
493fb300
AD		 4038/**
4039 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4040 * @vsi: the VSI being configured
4041 * @v_idx: Index of vector to be freed
4042 *
4043 * This function frees the memory allocated to the q_vector. In addition if
4044 * NAPI is enabled it will delete any references to the NAPI struct prior
4045 * to freeing the q_vector.
4046 **/
4047static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4048{
4049 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4050 struct i40e_ring *ring;
493fb300
AD		 4051
4052 if (!q_vector)
4053 return;
4054
4055 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4056 i40e_for_each_ring(ring, q_vector->tx)
4057 ring->q_vector = NULL;
4058
4059 i40e_for_each_ring(ring, q_vector->rx)
4060 ring->q_vector = NULL;
493fb300
AD		 4061
4062 /* only VSI w/ an associated netdev is set up w/ NAPI */
4063 if (vsi->netdev)
4064 netif_napi_del(&q_vector->napi);
4065
4066 vsi->q_vectors[v_idx] = NULL;
4067
4068 kfree_rcu(q_vector, rcu);
4069}
4070
41c445ff
JB		 4071/**
4072 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4073 * @vsi: the VSI being un-configured
4074 *
4075 * This frees the memory allocated to the q_vectors and
4076 * deletes references to the NAPI struct.
4077 **/
4078static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4079{
4080 int v_idx;
4081
493fb300
AD		 4082 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4083 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4084}
4085
4086/**
4087 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4088 * @pf: board private structure
4089 **/
4090static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4091{
4092 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4093 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4094 pci_disable_msix(pf->pdev);
4095 kfree(pf->msix_entries);
4096 pf->msix_entries = NULL;
3b444399
SN		 4097 kfree(pf->irq_pile);
4098 pf->irq_pile = NULL;
41c445ff
JB		 4099 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4100 pci_disable_msi(pf->pdev);
4101 }
4102 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4103}
4104
4105/**
4106 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4107 * @pf: board private structure
4108 *
4109 * We go through and clear interrupt specific resources and reset the structure
4110 * to pre-load conditions
4111 **/
4112static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4113{
4114 int i;
4115
e147758d 4116 i40e_stop_misc_vector(pf);
69278398 4117 if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) {
e147758d
SN		 4118 synchronize_irq(pf->msix_entries[0].vector);
4119 free_irq(pf->msix_entries[0].vector, pf);
4120 }
4121
e3219ce6
ASJ		 4122 i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector,
4123 I40E_IWARP_IRQ_PILE_ID);
4124
41c445ff 4125 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4126 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4127 if (pf->vsi[i])
4128 i40e_vsi_free_q_vectors(pf->vsi[i]);
4129 i40e_reset_interrupt_capability(pf);
4130}
4131
4132/**
4133 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4134 * @vsi: the VSI being configured
4135 **/
4136static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4137{
4138 int q_idx;
4139
4140 if (!vsi->netdev)
4141 return;
4142
4143 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4144 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4145}
4146
4147/**
4148 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4149 * @vsi: the VSI being configured
4150 **/
4151static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4152{
4153 int q_idx;
4154
4155 if (!vsi->netdev)
4156 return;
4157
4158 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4159 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4160}
4161
90ef8d47
SN		 4162/**
4163 * i40e_vsi_close - Shut down a VSI
4164 * @vsi: the vsi to be quelled
4165 **/
4166static void i40e_vsi_close(struct i40e_vsi *vsi)
4167{
e3219ce6
ASJ		 4168 bool reset = false;
4169
90ef8d47
SN		 4170 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4171 i40e_down(vsi);
4172 i40e_vsi_free_irq(vsi);
4173 i40e_vsi_free_tx_resources(vsi);
4174 i40e_vsi_free_rx_resources(vsi);
92faef85 4175 vsi->current_netdev_flags = 0;
e3219ce6
ASJ		 4176 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4177 reset = true;
4178 i40e_notify_client_of_netdev_close(vsi, reset);
90ef8d47
SN		 4179}
4180
41c445ff
JB		 4181/**
4182 * i40e_quiesce_vsi - Pause a given VSI
4183 * @vsi: the VSI being paused
4184 **/
4185static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4186{
4187 if (test_bit(__I40E_DOWN, &vsi->state))
4188 return;
4189
d341b7a5
NP		 4190 /* No need to disable FCoE VSI when Tx suspended */
4191 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4192 vsi->type == I40E_VSI_FCOE) {
4193 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4194 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4195 return;
4196 }
4197
41c445ff 4198 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4199 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4200 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4201 else
90ef8d47 4202 i40e_vsi_close(vsi);
41c445ff
JB		 4203}
4204
4205/**
4206 * i40e_unquiesce_vsi - Resume a given VSI
4207 * @vsi: the VSI being resumed
4208 **/
4209static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4210{
4211 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4212 return;
4213
4214 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4215 if (vsi->netdev && netif_running(vsi->netdev))
4216 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4217 else
8276f757 4218 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4219}
4220
4221/**
4222 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4223 * @pf: the PF
4224 **/
4225static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4226{
4227 int v;
4228
505682cd 4229 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4230 if (pf->vsi[v])
4231 i40e_quiesce_vsi(pf->vsi[v]);
4232 }
4233}
4234
4235/**
4236 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4237 * @pf: the PF
4238 **/
4239static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4240{
4241 int v;
4242
505682cd 4243 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4244 if (pf->vsi[v])
4245 i40e_unquiesce_vsi(pf->vsi[v]);
4246 }
4247}
4248
69129dc3
NP		 4249#ifdef CONFIG_I40E_DCB
4250/**
3fe06f41 4251 * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled
69129dc3
NP		 4252 * @vsi: the VSI being configured
4253 *
3fe06f41 4254 * This function waits for the given VSI's queues to be disabled.
69129dc3 4255 **/
3fe06f41 4256static int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi)
69129dc3
NP		 4257{
4258 struct i40e_pf *pf = vsi->back;
4259 int i, pf_q, ret;
4260
4261 pf_q = vsi->base_queue;
4262 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4263 /* Check and wait for the disable status of the queue */
4264 ret = i40e_pf_txq_wait(pf, pf_q, false);
4265 if (ret) {
4266 dev_info(&pf->pdev->dev,
fb43201f
SN		 4267 "VSI seid %d Tx ring %d disable timeout\n",
4268 vsi->seid, pf_q);
69129dc3
NP		 4269 return ret;
4270 }
4271 }
4272
3fe06f41
NP		 4273 pf_q = vsi->base_queue;
4274 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4275 /* Check and wait for the disable status of the queue */
4276 ret = i40e_pf_rxq_wait(pf, pf_q, false);
4277 if (ret) {
4278 dev_info(&pf->pdev->dev,
4279 "VSI seid %d Rx ring %d disable timeout\n",
4280 vsi->seid, pf_q);
4281 return ret;
4282 }
4283 }
4284
69129dc3
NP		 4285 return 0;
4286}
4287
4288/**
3fe06f41 4289 * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled
69129dc3
NP		 4290 * @pf: the PF
4291 *
3fe06f41 4292 * This function waits for the queues to be in disabled state for all the
69129dc3
NP		 4293 * VSIs that are managed by this PF.
4294 **/
3fe06f41 4295static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf)
69129dc3
NP		 4296{
4297 int v, ret = 0;
4298
4299 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4300 /* No need to wait for FCoE VSI queues */
4301 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
3fe06f41 4302 ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]);
69129dc3
NP		 4303 if (ret)
4304 break;
4305 }
4306 }
4307
4308 return ret;
4309}
4310
4311#endif
b03a8c1f
KP		 4312
4313/**
4314 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4315 * @q_idx: TX queue number
4316 * @vsi: Pointer to VSI struct
4317 *
4318 * This function checks specified queue for given VSI. Detects hung condition.
4319 * Sets hung bit since it is two step process. Before next run of service task
4320 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4321 * hung condition remain unchanged and during subsequent run, this function
4322 * issues SW interrupt to recover from hung condition.
4323 **/
4324static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4325{
4326 struct i40e_ring *tx_ring = NULL;
4327 struct i40e_pf *pf;
dd353109 4328 u32 head, val, tx_pending_hw;
b03a8c1f
KP		 4329 int i;
4330
4331 pf = vsi->back;
4332
4333 /* now that we have an index, find the tx_ring struct */
4334 for (i = 0; i < vsi->num_queue_pairs; i++) {
4335 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4336 if (q_idx == vsi->tx_rings[i]->queue_index) {
4337 tx_ring = vsi->tx_rings[i];
4338 break;
4339 }
4340 }
4341 }
4342
4343 if (!tx_ring)
4344 return;
4345
4346 /* Read interrupt register */
4347 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4348 val = rd32(&pf->hw,
4349 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4350 tx_ring->vsi->base_vector - 1));
4351 else
4352 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4353
4354 head = i40e_get_head(tx_ring);
4355
dd353109 4356 tx_pending_hw = i40e_get_tx_pending(tx_ring, false);
b03a8c1f 4357
9c6c1259
KP		 4358 /* HW is done executing descriptors, updated HEAD write back,
4359 * but SW hasn't processed those descriptors. If interrupt is
4360 * not generated from this point ON, it could result into
4361 * dev_watchdog detecting timeout on those netdev_queue,
4362 * hence proactively trigger SW interrupt.
b03a8c1f 4363 */
dd353109 4364 if (tx_pending_hw && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
9c6c1259
KP		 4365 /* NAPI Poll didn't run and clear since it was set */
4366 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4367 &tx_ring->q_vector->hung_detected)) {
dd353109
ASJ		 4368 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending_hw: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4369 vsi->seid, q_idx, tx_pending_hw,
9c6c1259
KP		 4370 tx_ring->next_to_clean, head,
4371 tx_ring->next_to_use,
4372 readl(tx_ring->tail));
4373 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4374 vsi->seid, q_idx, val);
4375 i40e_force_wb(vsi, tx_ring->q_vector);
4376 } else {
4377 /* First Chance - detected possible hung */
4378 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4379 &tx_ring->q_vector->hung_detected);
4380 }
4381 }
dd353109
ASJ		 4382
4383 /* This is the case where we have interrupts missing,
4384 * so the tx_pending in HW will most likely be 0, but we
4385 * will have tx_pending in SW since the WB happened but the
4386 * interrupt got lost.
4387 */
4388 if ((!tx_pending_hw) && i40e_get_tx_pending(tx_ring, true) &&
4389 (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
4390 if (napi_reschedule(&tx_ring->q_vector->napi))
4391 tx_ring->tx_stats.tx_lost_interrupt++;
4392 }
b03a8c1f
KP		 4393}
4394
4395/**
4396 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4397 * @pf: pointer to PF struct
4398 *
4399 * LAN VSI has netdev and netdev has TX queues. This function is to check
4400 * each of those TX queues if they are hung, trigger recovery by issuing
4401 * SW interrupt.
4402 **/
4403static void i40e_detect_recover_hung(struct i40e_pf *pf)
4404{
4405 struct net_device *netdev;
4406 struct i40e_vsi *vsi;
4407 int i;
4408
4409 /* Only for LAN VSI */
4410 vsi = pf->vsi[pf->lan_vsi];
4411
4412 if (!vsi)
4413 return;
4414
4415 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4416 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4417 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4418 return;
4419
4420 /* Make sure type is MAIN VSI */
4421 if (vsi->type != I40E_VSI_MAIN)
4422 return;
4423
4424 netdev = vsi->netdev;
4425 if (!netdev)
4426 return;
4427
4428 /* Bail out if netif_carrier is not OK */
4429 if (!netif_carrier_ok(netdev))
4430 return;
4431
4432 /* Go thru' TX queues for netdev */
4433 for (i = 0; i < netdev->num_tx_queues; i++) {
4434 struct netdev_queue *q;
4435
4436 q = netdev_get_tx_queue(netdev, i);
4437 if (q)
4438 i40e_detect_recover_hung_queue(i, vsi);
4439 }
4440}
4441
63d7e5a4
NP		 4442/**
4443 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4444 * @pf: pointer to PF
63d7e5a4
NP		 4445 *
4446 * Get TC map for ISCSI PF type that will include iSCSI TC
4447 * and LAN TC.
4448 **/
4449static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4450{
4451 struct i40e_dcb_app_priority_table app;
4452 struct i40e_hw *hw = &pf->hw;
4453 u8 enabled_tc = 1; /* TC0 is always enabled */
4454 u8 tc, i;
4455 /* Get the iSCSI APP TLV */
4456 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4457
4458 for (i = 0; i < dcbcfg->numapps; i++) {
4459 app = dcbcfg->app[i];
4460 if (app.selector == I40E_APP_SEL_TCPIP &&
4461 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4462 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4463 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4464 break;
4465 }
4466 }
4467
4468 return enabled_tc;
4469}
4470
41c445ff
JB		 4471/**
4472 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4473 * @dcbcfg: the corresponding DCBx configuration structure
4474 *
4475 * Return the number of TCs from given DCBx configuration
4476 **/
4477static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4478{
078b5876
JB		 4479 u8 num_tc = 0;
4480 int i;
41c445ff
JB		 4481
4482 /* Scan the ETS Config Priority Table to find
4483 * traffic class enabled for a given priority
4484 * and use the traffic class index to get the
4485 * number of traffic classes enabled
4486 */
4487 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4488 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4489 num_tc = dcbcfg->etscfg.prioritytable[i];
4490 }
4491
4492 /* Traffic class index starts from zero so
4493 * increment to return the actual count
4494 */
078b5876 4495 return num_tc + 1;
41c445ff
JB		 4496}
4497
4498/**
4499 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4500 * @dcbcfg: the corresponding DCBx configuration structure
4501 *
4502 * Query the current DCB configuration and return the number of
4503 * traffic classes enabled from the given DCBX config
4504 **/
4505static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4506{
4507 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4508 u8 enabled_tc = 1;
4509 u8 i;
4510
4511 for (i = 0; i < num_tc; i++)
41a1d04b 4512 enabled_tc |= BIT(i);
41c445ff
JB		 4513
4514 return enabled_tc;
4515}
4516
4517/**
4518 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4519 * @pf: PF being queried
4520 *
4521 * Return number of traffic classes enabled for the given PF
4522 **/
4523static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4524{
4525 struct i40e_hw *hw = &pf->hw;
4526 u8 i, enabled_tc;
4527 u8 num_tc = 0;
4528 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4529
4530 /* If DCB is not enabled then always in single TC */
4531 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4532 return 1;
4533
63d7e5a4
NP		 4534 /* SFP mode will be enabled for all TCs on port */
4535 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4536 return i40e_dcb_get_num_tc(dcbcfg);
4537
41c445ff 4538 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4539 if (pf->hw.func_caps.iscsi)
4540 enabled_tc = i40e_get_iscsi_tc_map(pf);
4541 else
fc51de96 4542 return 1; /* Only TC0 */
41c445ff 4543
63d7e5a4
NP		 4544 /* At least have TC0 */
4545 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4546 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4547 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4548 num_tc++;
4549 }
4550 return num_tc;
41c445ff
JB		 4551}
4552
4553/**
4554 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4555 * @pf: PF being queried
4556 *
4557 * Return a bitmap for first enabled traffic class for this PF.
4558 **/
4559static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4560{
4561 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4562 u8 i = 0;
4563
4564 if (!enabled_tc)
4565 return 0x1; /* TC0 */
4566
4567 /* Find the first enabled TC */
4568 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4569 if (enabled_tc & BIT(i))
41c445ff
JB		 4570 break;
4571 }
4572
41a1d04b 4573 return BIT(i);
41c445ff
JB		 4574}
4575
4576/**
4577 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4578 * @pf: PF being queried
4579 *
4580 * Return a bitmap for enabled traffic classes for this PF.
4581 **/
4582static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4583{
4584 /* If DCB is not enabled for this PF then just return default TC */
4585 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4586 return i40e_pf_get_default_tc(pf);
4587
41c445ff 4588 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4589 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4590 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4591
fc51de96 4592 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4593 if (pf->hw.func_caps.iscsi)
4594 return i40e_get_iscsi_tc_map(pf);
4595 else
fc51de96 4596 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4597}
4598
4599/**
4600 * i40e_vsi_get_bw_info - Query VSI BW Information
4601 * @vsi: the VSI being queried
4602 *
4603 * Returns 0 on success, negative value on failure
4604 **/
4605static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4606{
4607 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4608 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4609 struct i40e_pf *pf = vsi->back;
4610 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4611 i40e_status ret;
41c445ff 4612 u32 tc_bw_max;
41c445ff
JB		 4613 int i;
4614
4615 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4616 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4617 if (ret) {
41c445ff 4618 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4619 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4620 i40e_stat_str(&pf->hw, ret),
4621 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4622 return -EINVAL;
41c445ff
JB		 4623 }
4624
4625 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4626 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4627 NULL);
4628 if (ret) {
41c445ff 4629 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4630 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4631 i40e_stat_str(&pf->hw, ret),
4632 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4633 return -EINVAL;
41c445ff
JB		 4634 }
4635
4636 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4637 dev_info(&pf->pdev->dev,
4638 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4639 bw_config.tc_valid_bits,
4640 bw_ets_config.tc_valid_bits);
4641 /* Still continuing */
4642 }
4643
4644 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4645 vsi->bw_max_quanta = bw_config.max_bw;
4646 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4647 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4648 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4649 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4650 vsi->bw_ets_limit_credits[i] =
4651 le16_to_cpu(bw_ets_config.credits[i]);
4652 /* 3 bits out of 4 for each TC */
4653 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4654 }
078b5876 4655
dcae29be 4656 return 0;
41c445ff
JB		 4657}
4658
4659/**
4660 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4661 * @vsi: the VSI being configured
4662 * @enabled_tc: TC bitmap
4663 * @bw_credits: BW shared credits per TC
4664 *
4665 * Returns 0 on success, negative value on failure
4666 **/
dcae29be 4667static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4668 u8 *bw_share)
4669{
4670 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4671 i40e_status ret;
dcae29be 4672 int i;
41c445ff
JB		 4673
4674 bw_data.tc_valid_bits = enabled_tc;
4675 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4676 bw_data.tc_bw_credits[i] = bw_share[i];
4677
f1c7e72e
SN		 4678 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4679 NULL);
4680 if (ret) {
41c445ff 4681 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4682 "AQ command Config VSI BW allocation per TC failed = %d\n",
4683 vsi->back->hw.aq.asq_last_status);
dcae29be 4684 return -EINVAL;
41c445ff
JB		 4685 }
4686
4687 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4688 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4689
dcae29be 4690 return 0;
41c445ff
JB		 4691}
4692
4693/**
4694 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4695 * @vsi: the VSI being configured
4696 * @enabled_tc: TC map to be enabled
4697 *
4698 **/
4699static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4700{
4701 struct net_device *netdev = vsi->netdev;
4702 struct i40e_pf *pf = vsi->back;
4703 struct i40e_hw *hw = &pf->hw;
4704 u8 netdev_tc = 0;
4705 int i;
4706 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4707
4708 if (!netdev)
4709 return;
4710
4711 if (!enabled_tc) {
4712 netdev_reset_tc(netdev);
4713 return;
4714 }
4715
4716 /* Set up actual enabled TCs on the VSI */
4717 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4718 return;
4719
4720 /* set per TC queues for the VSI */
4721 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4722 /* Only set TC queues for enabled tcs
4723 *
4724 * e.g. For a VSI that has TC0 and TC3 enabled the
4725 * enabled_tc bitmap would be 0x00001001; the driver
4726 * will set the numtc for netdev as 2 that will be
4727 * referenced by the netdev layer as TC 0 and 1.
4728 */
75f5cea9 4729 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4730 netdev_set_tc_queue(netdev,
4731 vsi->tc_config.tc_info[i].netdev_tc,
4732 vsi->tc_config.tc_info[i].qcount,
4733 vsi->tc_config.tc_info[i].qoffset);
4734 }
4735
4736 /* Assign UP2TC map for the VSI */
4737 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4738 /* Get the actual TC# for the UP */
4739 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4740 /* Get the mapped netdev TC# for the UP */
4741 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4742 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4743 }
4744}
4745
4746/**
4747 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4748 * @vsi: the VSI being configured
4749 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4750 **/
4751static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4752 struct i40e_vsi_context *ctxt)
4753{
4754 /* copy just the sections touched not the entire info
4755 * since not all sections are valid as returned by
4756 * update vsi params
4757 */
4758 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4759 memcpy(&vsi->info.queue_mapping,
4760 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4761 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4762 sizeof(vsi->info.tc_mapping));
4763}
4764
4765/**
4766 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4767 * @vsi: VSI to be configured
4768 * @enabled_tc: TC bitmap
4769 *
4770 * This configures a particular VSI for TCs that are mapped to the
4771 * given TC bitmap. It uses default bandwidth share for TCs across
4772 * VSIs to configure TC for a particular VSI.
4773 *
4774 * NOTE:
4775 * It is expected that the VSI queues have been quisced before calling
4776 * this function.
4777 **/
4778static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4779{
4780 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4781 struct i40e_vsi_context ctxt;
4782 int ret = 0;
4783 int i;
4784
4785 /* Check if enabled_tc is same as existing or new TCs */
4786 if (vsi->tc_config.enabled_tc == enabled_tc)
4787 return ret;
4788
4789 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4790 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4791 if (enabled_tc & BIT(i))
41c445ff
JB		 4792 bw_share[i] = 1;
4793 }
4794
4795 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4796 if (ret) {
4797 dev_info(&vsi->back->pdev->dev,
4798 "Failed configuring TC map %d for VSI %d\n",
4799 enabled_tc, vsi->seid);
4800 goto out;
4801 }
4802
4803 /* Update Queue Pairs Mapping for currently enabled UPs */
4804 ctxt.seid = vsi->seid;
4805 ctxt.pf_num = vsi->back->hw.pf_id;
4806 ctxt.vf_num = 0;
4807 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4808 ctxt.info = vsi->info;
41c445ff
JB		 4809 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4810
e3219ce6
ASJ		 4811 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
4812 ctxt.info.valid_sections |=
4813 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
4814 ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
4815 }
4816
41c445ff
JB		 4817 /* Update the VSI after updating the VSI queue-mapping information */
4818 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4819 if (ret) {
4820 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4821 "Update vsi tc config failed, err %s aq_err %s\n",
4822 i40e_stat_str(&vsi->back->hw, ret),
4823 i40e_aq_str(&vsi->back->hw,
4824 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4825 goto out;
4826 }
4827 /* update the local VSI info with updated queue map */
4828 i40e_vsi_update_queue_map(vsi, &ctxt);
4829 vsi->info.valid_sections = 0;
4830
4831 /* Update current VSI BW information */
4832 ret = i40e_vsi_get_bw_info(vsi);
4833 if (ret) {
4834 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4835 "Failed updating vsi bw info, err %s aq_err %s\n",
4836 i40e_stat_str(&vsi->back->hw, ret),
4837 i40e_aq_str(&vsi->back->hw,
4838 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4839 goto out;
4840 }
4841
4842 /* Update the netdev TC setup */
4843 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4844out:
4845 return ret;
4846}
4847
4e3b35b0
NP		 4848/**
4849 * i40e_veb_config_tc - Configure TCs for given VEB
4850 * @veb: given VEB
4851 * @enabled_tc: TC bitmap
4852 *
4853 * Configures given TC bitmap for VEB (switching) element
4854 **/
4855int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4856{
4857 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4858 struct i40e_pf *pf = veb->pf;
4859 int ret = 0;
4860 int i;
4861
4862 /* No TCs or already enabled TCs just return */
4863 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4864 return ret;
4865
4866 bw_data.tc_valid_bits = enabled_tc;
4867 /* bw_data.absolute_credits is not set (relative) */
4868
4869 /* Enable ETS TCs with equal BW Share for now */
4870 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4871 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4872 bw_data.tc_bw_share_credits[i] = 1;
4873 }
4874
4875 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4876 &bw_data, NULL);
4877 if (ret) {
4878 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4879 "VEB bw config failed, err %s aq_err %s\n",
4880 i40e_stat_str(&pf->hw, ret),
4881 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4882 goto out;
4883 }
4884
4885 /* Update the BW information */
4886 ret = i40e_veb_get_bw_info(veb);
4887 if (ret) {
4888 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4889 "Failed getting veb bw config, err %s aq_err %s\n",
4890 i40e_stat_str(&pf->hw, ret),
4891 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4892 }
4893
4894out:
4895 return ret;
4896}
4897
4898#ifdef CONFIG_I40E_DCB
4899/**
4900 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4901 * @pf: PF struct
4902 *
4903 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4904 * the caller would've quiesce all the VSIs before calling
4905 * this function
4906 **/
4907static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4908{
4909 u8 tc_map = 0;
4910 int ret;
4911 u8 v;
4912
4913 /* Enable the TCs available on PF to all VEBs */
4914 tc_map = i40e_pf_get_tc_map(pf);
4915 for (v = 0; v < I40E_MAX_VEB; v++) {
4916 if (!pf->veb[v])
4917 continue;
4918 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4919 if (ret) {
4920 dev_info(&pf->pdev->dev,
4921 "Failed configuring TC for VEB seid=%d\n",
4922 pf->veb[v]->seid);
4923 /* Will try to configure as many components */
4924 }
4925 }
4926
4927 /* Update each VSI */
505682cd 4928 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4929 if (!pf->vsi[v])
4930 continue;
4931
4932 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4933#ifdef I40E_FCOE
4934 * - For FCoE VSI only enable the TC configured
4935 * as per the APP TLV
4936#endif
4e3b35b0
NP		 4937 * - For all others keep them at TC0 for now
4938 */
4939 if (v == pf->lan_vsi)
4940 tc_map = i40e_pf_get_tc_map(pf);
4941 else
4942 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4943#ifdef I40E_FCOE
4944 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4945 tc_map = i40e_get_fcoe_tc_map(pf);
4946#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4947
4948 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4949 if (ret) {
4950 dev_info(&pf->pdev->dev,
4951 "Failed configuring TC for VSI seid=%d\n",
4952 pf->vsi[v]->seid);
4953 /* Will try to configure as many components */
4954 } else {
0672a091
NP		 4955 /* Re-configure VSI vectors based on updated TC map */
4956 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4957 if (pf->vsi[v]->netdev)
4958 i40e_dcbnl_set_all(pf->vsi[v]);
4959 }
e3219ce6 4960 i40e_notify_client_of_l2_param_changes(pf->vsi[v]);
4e3b35b0
NP		 4961 }
4962}
4963
2fd75f31
NP		 4964/**
4965 * i40e_resume_port_tx - Resume port Tx
4966 * @pf: PF struct
4967 *
4968 * Resume a port's Tx and issue a PF reset in case of failure to
4969 * resume.
4970 **/
4971static int i40e_resume_port_tx(struct i40e_pf *pf)
4972{
4973 struct i40e_hw *hw = &pf->hw;
4974 int ret;
4975
4976 ret = i40e_aq_resume_port_tx(hw, NULL);
4977 if (ret) {
4978 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4979 "Resume Port Tx failed, err %s aq_err %s\n",
4980 i40e_stat_str(&pf->hw, ret),
4981 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4982 /* Schedule PF reset to recover */
4983 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4984 i40e_service_event_schedule(pf);
4985 }
4986
4987 return ret;
4988}
4989
4e3b35b0
NP		 4990/**
4991 * i40e_init_pf_dcb - Initialize DCB configuration
4992 * @pf: PF being configured
4993 *
4994 * Query the current DCB configuration and cache it
4995 * in the hardware structure
4996 **/
4997static int i40e_init_pf_dcb(struct i40e_pf *pf)
4998{
4999 struct i40e_hw *hw = &pf->hw;
5000 int err = 0;
5001
025b4a54 5002 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
f1bbad33 5003 if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT)
025b4a54
ASJ		 5004 goto out;
5005
4e3b35b0
NP		 5006 /* Get the initial DCB configuration */
5007 err = i40e_init_dcb(hw);
5008 if (!err) {
5009 /* Device/Function is not DCBX capable */
5010 if ((!hw->func_caps.dcb) ||
5011 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5012 dev_info(&pf->pdev->dev,
5013 "DCBX offload is not supported or is disabled for this PF.\n");
5014
5015 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5016 goto out;
5017
5018 } else {
5019 /* When status is not DISABLED then DCBX in FW */
5020 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5021 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5022
5023 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5024 /* Enable DCB tagging only when more than one TC */
5025 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5026 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5027 dev_dbg(&pf->pdev->dev,
5028 "DCBX offload is supported for this PF.\n");
4e3b35b0 5029 }
014269ff 5030 } else {
aebfc816 5031 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5032 "Query for DCB configuration failed, err %s aq_err %s\n",
5033 i40e_stat_str(&pf->hw, err),
5034 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5035 }
5036
5037out:
5038 return err;
5039}
5040#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5041#define SPEED_SIZE 14
5042#define FC_SIZE 8
5043/**
5044 * i40e_print_link_message - print link up or down
5045 * @vsi: the VSI for which link needs a message
5046 */
c156f856 5047void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5048{
a9165490
SN		 5049 char *speed = "Unknown";
5050 char *fc = "Unknown";
cf05ed08 5051
c156f856
MJ		 5052 if (vsi->current_isup == isup)
5053 return;
5054 vsi->current_isup = isup;
cf05ed08
JB		 5055 if (!isup) {
5056 netdev_info(vsi->netdev, "NIC Link is Down\n");
5057 return;
5058 }
5059
148c2d80
GR		 5060 /* Warn user if link speed on NPAR enabled partition is not at
5061 * least 10GB
5062 */
5063 if (vsi->back->hw.func_caps.npar_enable &&
5064 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5065 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5066 netdev_warn(vsi->netdev,
5067 "The partition detected link speed that is less than 10Gbps\n");
5068
cf05ed08
JB		 5069 switch (vsi->back->hw.phy.link_info.link_speed) {
5070 case I40E_LINK_SPEED_40GB:
a9165490 5071 speed = "40 G";
cf05ed08 5072 break;
ae24b409 5073 case I40E_LINK_SPEED_20GB:
a9165490 5074 speed = "20 G";
ae24b409 5075 break;
cf05ed08 5076 case I40E_LINK_SPEED_10GB:
a9165490 5077 speed = "10 G";
cf05ed08
JB		 5078 break;
5079 case I40E_LINK_SPEED_1GB:
a9165490 5080 speed = "1000 M";
cf05ed08 5081 break;
5960d33f 5082 case I40E_LINK_SPEED_100MB:
a9165490 5083 speed = "100 M";
5960d33f 5084 break;
cf05ed08
JB		 5085 default:
5086 break;
5087 }
5088
5089 switch (vsi->back->hw.fc.current_mode) {
5090 case I40E_FC_FULL:
a9165490 5091 fc = "RX/TX";
cf05ed08
JB		 5092 break;
5093 case I40E_FC_TX_PAUSE:
a9165490 5094 fc = "TX";
cf05ed08
JB		 5095 break;
5096 case I40E_FC_RX_PAUSE:
a9165490 5097 fc = "RX";
cf05ed08
JB		 5098 break;
5099 default:
a9165490 5100 fc = "None";
cf05ed08
JB		 5101 break;
5102 }
5103
a9165490 5104 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5105 speed, fc);
5106}
4e3b35b0 5107
41c445ff
JB		 5108/**
5109 * i40e_up_complete - Finish the last steps of bringing up a connection
5110 * @vsi: the VSI being configured
5111 **/
5112static int i40e_up_complete(struct i40e_vsi *vsi)
5113{
5114 struct i40e_pf *pf = vsi->back;
5115 int err;
5116
5117 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5118 i40e_vsi_configure_msix(vsi);
5119 else
5120 i40e_configure_msi_and_legacy(vsi);
5121
5122 /* start rings */
5123 err = i40e_vsi_control_rings(vsi, true);
5124 if (err)
5125 return err;
5126
5127 clear_bit(__I40E_DOWN, &vsi->state);
5128 i40e_napi_enable_all(vsi);
5129 i40e_vsi_enable_irq(vsi);
5130
5131 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5132 (vsi->netdev)) {
cf05ed08 5133 i40e_print_link_message(vsi, true);
41c445ff
JB		 5134 netif_tx_start_all_queues(vsi->netdev);
5135 netif_carrier_on(vsi->netdev);
6d779b41 5136 } else if (vsi->netdev) {
cf05ed08 5137 i40e_print_link_message(vsi, false);
7b592f61
CW		 5138 /* need to check for qualified module here*/
5139 if ((pf->hw.phy.link_info.link_info &
5140 I40E_AQ_MEDIA_AVAILABLE) &&
5141 (!(pf->hw.phy.link_info.an_info &
5142 I40E_AQ_QUALIFIED_MODULE)))
5143 netdev_err(vsi->netdev,
5144 "the driver failed to link because an unqualified module was detected.");
41c445ff 5145 }
ca64fa4e
ASJ		 5146
5147 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5148 if (vsi->type == I40E_VSI_FDIR) {
5149 /* reset fd counters */
5150 pf->fd_add_err = pf->fd_atr_cnt = 0;
5151 if (pf->fd_tcp_rule > 0) {
5152 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5153 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5154 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5155 pf->fd_tcp_rule = 0;
5156 }
ca64fa4e 5157 i40e_fdir_filter_restore(vsi);
1e1be8f6 5158 }
e3219ce6
ASJ		 5159
5160 /* On the next run of the service_task, notify any clients of the new
5161 * opened netdev
5162 */
5163 pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED;
41c445ff
JB		 5164 i40e_service_event_schedule(pf);
5165
5166 return 0;
5167}
5168
5169/**
5170 * i40e_vsi_reinit_locked - Reset the VSI
5171 * @vsi: the VSI being configured
5172 *
5173 * Rebuild the ring structs after some configuration
5174 * has changed, e.g. MTU size.
5175 **/
5176static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5177{
5178 struct i40e_pf *pf = vsi->back;
5179
5180 WARN_ON(in_interrupt());
5181 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5182 usleep_range(1000, 2000);
5183 i40e_down(vsi);
5184
5185 /* Give a VF some time to respond to the reset. The
5186 * two second wait is based upon the watchdog cycle in
5187 * the VF driver.
5188 */
5189 if (vsi->type == I40E_VSI_SRIOV)
5190 msleep(2000);
5191 i40e_up(vsi);
5192 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5193}
5194
5195/**
5196 * i40e_up - Bring the connection back up after being down
5197 * @vsi: the VSI being configured
5198 **/
5199int i40e_up(struct i40e_vsi *vsi)
5200{
5201 int err;
5202
5203 err = i40e_vsi_configure(vsi);
5204 if (!err)
5205 err = i40e_up_complete(vsi);
5206
5207 return err;
5208}
5209
5210/**
5211 * i40e_down - Shutdown the connection processing
5212 * @vsi: the VSI being stopped
5213 **/
5214void i40e_down(struct i40e_vsi *vsi)
5215{
5216 int i;
5217
5218 /* It is assumed that the caller of this function
5219 * sets the vsi->state __I40E_DOWN bit.
5220 */
5221 if (vsi->netdev) {
5222 netif_carrier_off(vsi->netdev);
5223 netif_tx_disable(vsi->netdev);
5224 }
5225 i40e_vsi_disable_irq(vsi);
5226 i40e_vsi_control_rings(vsi, false);
5227 i40e_napi_disable_all(vsi);
5228
5229 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5230 i40e_clean_tx_ring(vsi->tx_rings[i]);
5231 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5232 }
5233}
5234
5235/**
5236 * i40e_setup_tc - configure multiple traffic classes
5237 * @netdev: net device to configure
5238 * @tc: number of traffic classes to enable
5239 **/
5240static int i40e_setup_tc(struct net_device *netdev, u8 tc)
5241{
5242 struct i40e_netdev_priv *np = netdev_priv(netdev);
5243 struct i40e_vsi *vsi = np->vsi;
5244 struct i40e_pf *pf = vsi->back;
5245 u8 enabled_tc = 0;
5246 int ret = -EINVAL;
5247 int i;
5248
5249 /* Check if DCB enabled to continue */
5250 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5251 netdev_info(netdev, "DCB is not enabled for adapter\n");
5252 goto exit;
5253 }
5254
5255 /* Check if MFP enabled */
5256 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5257 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5258 goto exit;
5259 }
5260
5261 /* Check whether tc count is within enabled limit */
5262 if (tc > i40e_pf_get_num_tc(pf)) {
5263 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5264 goto exit;
5265 }
5266
5267 /* Generate TC map for number of tc requested */
5268 for (i = 0; i < tc; i++)
75f5cea9 5269 enabled_tc |= BIT(i);
41c445ff
JB		 5270
5271 /* Requesting same TC configuration as already enabled */
5272 if (enabled_tc == vsi->tc_config.enabled_tc)
5273 return 0;
5274
5275 /* Quiesce VSI queues */
5276 i40e_quiesce_vsi(vsi);
5277
5278 /* Configure VSI for enabled TCs */
5279 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5280 if (ret) {
5281 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5282 vsi->seid);
5283 goto exit;
5284 }
5285
5286 /* Unquiesce VSI */
5287 i40e_unquiesce_vsi(vsi);
5288
5289exit:
5290 return ret;
5291}
5292
e4c6734e 5293#ifdef I40E_FCOE
16e5cc64
JF		 5294int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5295 struct tc_to_netdev *tc)
e4c6734e 5296#else
16e5cc64
JF		 5297static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5298 struct tc_to_netdev *tc)
e4c6734e
JF		 5299#endif
5300{
16e5cc64 5301 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
e4c6734e 5302 return -EINVAL;
16e5cc64 5303 return i40e_setup_tc(netdev, tc->tc);
e4c6734e
JF		 5304}
5305
41c445ff
JB		 5306/**
5307 * i40e_open - Called when a network interface is made active
5308 * @netdev: network interface device structure
5309 *
5310 * The open entry point is called when a network interface is made
5311 * active by the system (IFF_UP). At this point all resources needed
5312 * for transmit and receive operations are allocated, the interrupt
5313 * handler is registered with the OS, the netdev watchdog subtask is
5314 * enabled, and the stack is notified that the interface is ready.
5315 *
5316 * Returns 0 on success, negative value on failure
5317 **/
38e00438 5318int i40e_open(struct net_device *netdev)
41c445ff
JB		 5319{
5320 struct i40e_netdev_priv *np = netdev_priv(netdev);
5321 struct i40e_vsi *vsi = np->vsi;
5322 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5323 int err;
5324
4eb3f768
SN		 5325 /* disallow open during test or if eeprom is broken */
5326 if (test_bit(__I40E_TESTING, &pf->state) ||
5327 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5328 return -EBUSY;
5329
5330 netif_carrier_off(netdev);
5331
6c167f58
EK		 5332 err = i40e_vsi_open(vsi);
5333 if (err)
5334 return err;
5335
059dab69
JB		 5336 /* configure global TSO hardware offload settings */
5337 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5338 TCP_FLAG_FIN) >> 16);
5339 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5340 TCP_FLAG_FIN |
5341 TCP_FLAG_CWR) >> 16);
5342 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5343
6633d381 5344#ifdef CONFIG_I40E_VXLAN
6c167f58
EK		 5345 vxlan_get_rx_port(netdev);
5346#endif
cd866606 5347#ifdef CONFIG_I40E_GENEVE
a340c789
AS		 5348 if (pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE)
5349 geneve_get_rx_port(netdev);
cd866606 5350#endif
6c167f58 5351
e3219ce6
ASJ		 5352 i40e_notify_client_of_netdev_open(vsi);
5353
6c167f58
EK		 5354 return 0;
5355}
5356
5357/**
5358 * i40e_vsi_open -
5359 * @vsi: the VSI to open
5360 *
5361 * Finish initialization of the VSI.
5362 *
5363 * Returns 0 on success, negative value on failure
5364 **/
5365int i40e_vsi_open(struct i40e_vsi *vsi)
5366{
5367 struct i40e_pf *pf = vsi->back;
b294ac70 5368 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5369 int err;
5370
41c445ff
JB		 5371 /* allocate descriptors */
5372 err = i40e_vsi_setup_tx_resources(vsi);
5373 if (err)
5374 goto err_setup_tx;
5375 err = i40e_vsi_setup_rx_resources(vsi);
5376 if (err)
5377 goto err_setup_rx;
5378
5379 err = i40e_vsi_configure(vsi);
5380 if (err)
5381 goto err_setup_rx;
5382
c22e3c6c
SN		 5383 if (vsi->netdev) {
5384 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5385 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5386 err = i40e_vsi_request_irq(vsi, int_name);
5387 if (err)
5388 goto err_setup_rx;
41c445ff 5389
c22e3c6c
SN		 5390 /* Notify the stack of the actual queue counts. */
5391 err = netif_set_real_num_tx_queues(vsi->netdev,
5392 vsi->num_queue_pairs);
5393 if (err)
5394 goto err_set_queues;
25946ddb 5395
c22e3c6c
SN		 5396 err = netif_set_real_num_rx_queues(vsi->netdev,
5397 vsi->num_queue_pairs);
5398 if (err)
5399 goto err_set_queues;
8a9eb7d3
SN		 5400
5401 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5402 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5403 dev_driver_string(&pf->pdev->dev),
5404 dev_name(&pf->pdev->dev));
8a9eb7d3 5405 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5406
c22e3c6c 5407 } else {
ce9ccb17 5408 err = -EINVAL;
6c167f58
EK		 5409 goto err_setup_rx;
5410 }
25946ddb 5411
41c445ff
JB		 5412 err = i40e_up_complete(vsi);
5413 if (err)
5414 goto err_up_complete;
5415
41c445ff
JB		 5416 return 0;
5417
5418err_up_complete:
5419 i40e_down(vsi);
25946ddb 5420err_set_queues:
41c445ff
JB		 5421 i40e_vsi_free_irq(vsi);
5422err_setup_rx:
5423 i40e_vsi_free_rx_resources(vsi);
5424err_setup_tx:
5425 i40e_vsi_free_tx_resources(vsi);
5426 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5427 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5428
5429 return err;
5430}
5431
17a73f6b
JG		 5432/**
5433 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5434 * @pf: Pointer to PF
17a73f6b
JG		 5435 *
5436 * This function destroys the hlist where all the Flow Director
5437 * filters were saved.
5438 **/
5439static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5440{
5441 struct i40e_fdir_filter *filter;
5442 struct hlist_node *node2;
5443
5444 hlist_for_each_entry_safe(filter, node2,
5445 &pf->fdir_filter_list, fdir_node) {
5446 hlist_del(&filter->fdir_node);
5447 kfree(filter);
5448 }
5449 pf->fdir_pf_active_filters = 0;
5450}
5451
41c445ff
JB		 5452/**
5453 * i40e_close - Disables a network interface
5454 * @netdev: network interface device structure
5455 *
5456 * The close entry point is called when an interface is de-activated
5457 * by the OS. The hardware is still under the driver's control, but
5458 * this netdev interface is disabled.
5459 *
5460 * Returns 0, this is not allowed to fail
5461 **/
38e00438 5462int i40e_close(struct net_device *netdev)
41c445ff
JB		 5463{
5464 struct i40e_netdev_priv *np = netdev_priv(netdev);
5465 struct i40e_vsi *vsi = np->vsi;
5466
90ef8d47 5467 i40e_vsi_close(vsi);
41c445ff
JB		 5468
5469 return 0;
5470}
5471
5472/**
5473 * i40e_do_reset - Start a PF or Core Reset sequence
5474 * @pf: board private structure
5475 * @reset_flags: which reset is requested
5476 *
5477 * The essential difference in resets is that the PF Reset
5478 * doesn't clear the packet buffers, doesn't reset the PE
5479 * firmware, and doesn't bother the other PFs on the chip.
5480 **/
5481void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5482{
5483 u32 val;
5484
5485 WARN_ON(in_interrupt());
5486
263fc48f 5487
41c445ff 5488 /* do the biggest reset indicated */
41a1d04b 5489 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5490
5491 /* Request a Global Reset
5492 *
5493 * This will start the chip's countdown to the actual full
5494 * chip reset event, and a warning interrupt to be sent
5495 * to all PFs, including the requestor. Our handler
5496 * for the warning interrupt will deal with the shutdown
5497 * and recovery of the switch setup.
5498 */
69bfb110 5499 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5500 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5501 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5502 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5503
41a1d04b 5504 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5505
5506 /* Request a Core Reset
5507 *
5508 * Same as Global Reset, except does *not* include the MAC/PHY
5509 */
69bfb110 5510 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5511 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5512 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5513 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5514 i40e_flush(&pf->hw);
5515
41a1d04b 5516 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5517
5518 /* Request a PF Reset
5519 *
5520 * Resets only the PF-specific registers
5521 *
5522 * This goes directly to the tear-down and rebuild of
5523 * the switch, since we need to do all the recovery as
5524 * for the Core Reset.
5525 */
69bfb110 5526 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5527 i40e_handle_reset_warning(pf);
5528
41a1d04b 5529 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5530 int v;
5531
5532 /* Find the VSI(s) that requested a re-init */
5533 dev_info(&pf->pdev->dev,
5534 "VSI reinit requested\n");
505682cd 5535 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5536 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5537
41c445ff
JB		 5538 if (vsi != NULL &&
5539 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5540 i40e_vsi_reinit_locked(pf->vsi[v]);
5541 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5542 }
5543 }
41a1d04b 5544 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5545 int v;
5546
5547 /* Find the VSI(s) that needs to be brought down */
5548 dev_info(&pf->pdev->dev, "VSI down requested\n");
5549 for (v = 0; v < pf->num_alloc_vsi; v++) {
5550 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5551
b5d06f05
NP		 5552 if (vsi != NULL &&
5553 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5554 set_bit(__I40E_DOWN, &vsi->state);
5555 i40e_down(vsi);
5556 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5557 }
5558 }
41c445ff
JB		 5559 } else {
5560 dev_info(&pf->pdev->dev,
5561 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5562 }
5563}
5564
4e3b35b0
NP		 5565#ifdef CONFIG_I40E_DCB
5566/**
5567 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5568 * @pf: board private structure
5569 * @old_cfg: current DCB config
5570 * @new_cfg: new DCB config
5571 **/
5572bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5573 struct i40e_dcbx_config *old_cfg,
5574 struct i40e_dcbx_config *new_cfg)
5575{
5576 bool need_reconfig = false;
5577
5578 /* Check if ETS configuration has changed */
5579 if (memcmp(&new_cfg->etscfg,
5580 &old_cfg->etscfg,
5581 sizeof(new_cfg->etscfg))) {
5582 /* If Priority Table has changed reconfig is needed */
5583 if (memcmp(&new_cfg->etscfg.prioritytable,
5584 &old_cfg->etscfg.prioritytable,
5585 sizeof(new_cfg->etscfg.prioritytable))) {
5586 need_reconfig = true;
69bfb110 5587 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5588 }
5589
5590 if (memcmp(&new_cfg->etscfg.tcbwtable,
5591 &old_cfg->etscfg.tcbwtable,
5592 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5593 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5594
5595 if (memcmp(&new_cfg->etscfg.tsatable,
5596 &old_cfg->etscfg.tsatable,
5597 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5598 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5599 }
5600
5601 /* Check if PFC configuration has changed */
5602 if (memcmp(&new_cfg->pfc,
5603 &old_cfg->pfc,
5604 sizeof(new_cfg->pfc))) {
5605 need_reconfig = true;
69bfb110 5606 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5607 }
5608
5609 /* Check if APP Table has changed */
5610 if (memcmp(&new_cfg->app,
5611 &old_cfg->app,
3d9667a9 5612 sizeof(new_cfg->app))) {
4e3b35b0 5613 need_reconfig = true;
69bfb110 5614 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5615 }
4e3b35b0 5616
fb43201f 5617 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5618 return need_reconfig;
5619}
5620
5621/**
5622 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5623 * @pf: board private structure
5624 * @e: event info posted on ARQ
5625 **/
5626static int i40e_handle_lldp_event(struct i40e_pf *pf,
5627 struct i40e_arq_event_info *e)
5628{
5629 struct i40e_aqc_lldp_get_mib *mib =
5630 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5631 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5632 struct i40e_dcbx_config tmp_dcbx_cfg;
5633 bool need_reconfig = false;
5634 int ret = 0;
5635 u8 type;
5636
4d9b6043
NP		 5637 /* Not DCB capable or capability disabled */
5638 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5639 return ret;
5640
4e3b35b0
NP		 5641 /* Ignore if event is not for Nearest Bridge */
5642 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5643 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5644 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5645 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5646 return ret;
5647
5648 /* Check MIB Type and return if event for Remote MIB update */
5649 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5650 dev_dbg(&pf->pdev->dev,
fb43201f 5651 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5652 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5653 /* Update the remote cached instance and return */
5654 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5655 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5656 &hw->remote_dcbx_config);
5657 goto exit;
5658 }
5659
9fa61dd2 5660 /* Store the old configuration */
1a2f6248 5661 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5662
750fcbcf
NP		 5663 /* Reset the old DCBx configuration data */
5664 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5665 /* Get updated DCBX data from firmware */
5666 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5667 if (ret) {
f1c7e72e
SN		 5668 dev_info(&pf->pdev->dev,
5669 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5670 i40e_stat_str(&pf->hw, ret),
5671 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5672 goto exit;
5673 }
5674
5675 /* No change detected in DCBX configs */
750fcbcf
NP		 5676 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5677 sizeof(tmp_dcbx_cfg))) {
69bfb110 5678 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5679 goto exit;
5680 }
5681
750fcbcf
NP		 5682 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5683 &hw->local_dcbx_config);
4e3b35b0 5684
750fcbcf 5685 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5686
5687 if (!need_reconfig)
5688 goto exit;
5689
4d9b6043 5690 /* Enable DCB tagging only when more than one TC */
750fcbcf 5691 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5692 pf->flags |= I40E_FLAG_DCB_ENABLED;
5693 else
5694 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5695
69129dc3 5696 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5697 /* Reconfiguration needed quiesce all VSIs */
5698 i40e_pf_quiesce_all_vsi(pf);
5699
5700 /* Changes in configuration update VEB/VSI */
5701 i40e_dcb_reconfigure(pf);
5702
2fd75f31
NP		 5703 ret = i40e_resume_port_tx(pf);
5704
69129dc3 5705 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5706 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5707 if (ret)
5708 goto exit;
5709
3fe06f41
NP		 5710 /* Wait for the PF's queues to be disabled */
5711 ret = i40e_pf_wait_queues_disabled(pf);
11e47708
PN		 5712 if (ret) {
5713 /* Schedule PF reset to recover */
5714 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5715 i40e_service_event_schedule(pf);
5716 } else {
2fd75f31 5717 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5718 }
5719
4e3b35b0
NP		 5720exit:
5721 return ret;
5722}
5723#endif /* CONFIG_I40E_DCB */
5724
23326186
ASJ		 5725/**
5726 * i40e_do_reset_safe - Protected reset path for userland calls.
5727 * @pf: board private structure
5728 * @reset_flags: which reset is requested
5729 *
5730 **/
5731void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5732{
5733 rtnl_lock();
5734 i40e_do_reset(pf, reset_flags);
5735 rtnl_unlock();
5736}
5737
41c445ff
JB		 5738/**
5739 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5740 * @pf: board private structure
5741 * @e: event info posted on ARQ
5742 *
5743 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5744 * and VF queues
5745 **/
5746static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5747 struct i40e_arq_event_info *e)
5748{
5749 struct i40e_aqc_lan_overflow *data =
5750 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5751 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5752 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5753 struct i40e_hw *hw = &pf->hw;
5754 struct i40e_vf *vf;
5755 u16 vf_id;
5756
69bfb110
JB		 5757 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5758 queue, qtx_ctl);
41c445ff
JB		 5759
5760 /* Queue belongs to VF, find the VF and issue VF reset */
5761 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5762 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5763 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5764 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5765 vf_id -= hw->func_caps.vf_base_id;
5766 vf = &pf->vf[vf_id];
5767 i40e_vc_notify_vf_reset(vf);
5768 /* Allow VF to process pending reset notification */
5769 msleep(20);
5770 i40e_reset_vf(vf, false);
5771 }
5772}
5773
5774/**
5775 * i40e_service_event_complete - Finish up the service event
5776 * @pf: board private structure
5777 **/
5778static void i40e_service_event_complete(struct i40e_pf *pf)
5779{
b875f99b 5780 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5781
5782 /* flush memory to make sure state is correct before next watchog */
4e857c58 5783 smp_mb__before_atomic();
41c445ff
JB		 5784 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5785}
5786
55a5e60b 5787/**
12957388
ASJ		 5788 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5789 * @pf: board private structure
5790 **/
04294e38 5791u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5792{
04294e38 5793 u32 val, fcnt_prog;
12957388
ASJ		 5794
5795 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5796 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5797 return fcnt_prog;
5798}
5799
5800/**
04294e38 5801 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5802 * @pf: board private structure
5803 **/
04294e38 5804u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5805{
04294e38
ASJ		 5806 u32 val, fcnt_prog;
5807
55a5e60b
ASJ		 5808 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5809 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5810 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5811 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5812 return fcnt_prog;
5813}
1e1be8f6 5814
04294e38
ASJ		 5815/**
5816 * i40e_get_global_fd_count - Get total FD filters programmed on device
5817 * @pf: board private structure
5818 **/
5819u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5820{
5821 u32 val, fcnt_prog;
5822
5823 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5824 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5825 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5826 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5827 return fcnt_prog;
5828}
5829
55a5e60b
ASJ		 5830/**
5831 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5832 * @pf: board private structure
5833 **/
5834void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5835{
3487b6c3 5836 struct i40e_fdir_filter *filter;
55a5e60b 5837 u32 fcnt_prog, fcnt_avail;
3487b6c3 5838 struct hlist_node *node;
55a5e60b 5839
1e1be8f6
ASJ		 5840 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5841 return;
5842
55a5e60b
ASJ		 5843 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5844 * to re-enable
5845 */
04294e38 5846 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5847 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5848 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5849 (pf->fd_add_err == 0) ||
5850 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5851 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5852 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5853 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5854 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5855 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5856 }
5857 }
5858 /* Wait for some more space to be available to turn on ATR */
5859 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5860 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5861 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5862 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5863 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5864 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5865 }
5866 }
3487b6c3
CW		 5867
5868 /* if hw had a problem adding a filter, delete it */
5869 if (pf->fd_inv > 0) {
5870 hlist_for_each_entry_safe(filter, node,
5871 &pf->fdir_filter_list, fdir_node) {
5872 if (filter->fd_id == pf->fd_inv) {
5873 hlist_del(&filter->fdir_node);
5874 kfree(filter);
5875 pf->fdir_pf_active_filters--;
5876 }
5877 }
5878 }
55a5e60b
ASJ		 5879}
5880
1e1be8f6 5881#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5882#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5883/**
5884 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5885 * @pf: board private structure
5886 **/
5887static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5888{
04294e38 5889 unsigned long min_flush_time;
1e1be8f6 5890 int flush_wait_retry = 50;
04294e38
ASJ		 5891 bool disable_atr = false;
5892 int fd_room;
1e1be8f6
ASJ		 5893 int reg;
5894
1790ed0c
AA		 5895 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5896 return;
5897
a5fdaf34
JB		 5898 if (!time_after(jiffies, pf->fd_flush_timestamp +
5899 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5900 return;
04294e38 5901
a5fdaf34
JB		 5902 /* If the flush is happening too quick and we have mostly SB rules we
5903 * should not re-enable ATR for some time.
5904 */
5905 min_flush_time = pf->fd_flush_timestamp +
5906 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5907 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5908
5909 if (!(time_after(jiffies, min_flush_time)) &&
5910 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5911 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5912 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5913 disable_atr = true;
5914 }
5915
5916 pf->fd_flush_timestamp = jiffies;
5917 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5918 /* flush all filters */
5919 wr32(&pf->hw, I40E_PFQF_CTL_1,
5920 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5921 i40e_flush(&pf->hw);
5922 pf->fd_flush_cnt++;
5923 pf->fd_add_err = 0;
5924 do {
5925 /* Check FD flush status every 5-6msec */
5926 usleep_range(5000, 6000);
5927 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5928 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5929 break;
5930 } while (flush_wait_retry--);
5931 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5932 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5933 } else {
5934 /* replay sideband filters */
5935 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5936 if (!disable_atr)
5937 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5938 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5939 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5940 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5941 }
a5fdaf34 5942
1e1be8f6
ASJ		 5943}
5944
5945/**
5946 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5947 * @pf: board private structure
5948 **/
04294e38 5949u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5950{
5951 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5952}
5953
5954/* We can see up to 256 filter programming desc in transit if the filters are
5955 * being applied really fast; before we see the first
5956 * filter miss error on Rx queue 0. Accumulating enough error messages before
5957 * reacting will make sure we don't cause flush too often.
5958 */
5959#define I40E_MAX_FD_PROGRAM_ERROR 256
5960
41c445ff
JB		 5961/**
5962 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5963 * @pf: board private structure
5964 **/
5965static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5966{
41c445ff 5967
41c445ff
JB		 5968 /* if interface is down do nothing */
5969 if (test_bit(__I40E_DOWN, &pf->state))
5970 return;
1e1be8f6 5971
1790ed0c
AA		 5972 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5973 return;
5974
04294e38 5975 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5976 i40e_fdir_flush_and_replay(pf);
5977
55a5e60b
ASJ		 5978 i40e_fdir_check_and_reenable(pf);
5979
41c445ff
JB		 5980}
5981
5982/**
5983 * i40e_vsi_link_event - notify VSI of a link event
5984 * @vsi: vsi to be notified
5985 * @link_up: link up or down
5986 **/
5987static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5988{
32b5b811 5989 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5990 return;
5991
5992 switch (vsi->type) {
5993 case I40E_VSI_MAIN:
38e00438
VD		 5994#ifdef I40E_FCOE
5995 case I40E_VSI_FCOE:
5996#endif
41c445ff
JB		 5997 if (!vsi->netdev || !vsi->netdev_registered)
5998 break;
5999
6000 if (link_up) {
6001 netif_carrier_on(vsi->netdev);
6002 netif_tx_wake_all_queues(vsi->netdev);
6003 } else {
6004 netif_carrier_off(vsi->netdev);
6005 netif_tx_stop_all_queues(vsi->netdev);
6006 }
6007 break;
6008
6009 case I40E_VSI_SRIOV:
41c445ff
JB		 6010 case I40E_VSI_VMDQ2:
6011 case I40E_VSI_CTRL:
e3219ce6 6012 case I40E_VSI_IWARP:
41c445ff
JB		 6013 case I40E_VSI_MIRROR:
6014 default:
6015 /* there is no notification for other VSIs */
6016 break;
6017 }
6018}
6019
6020/**
6021 * i40e_veb_link_event - notify elements on the veb of a link event
6022 * @veb: veb to be notified
6023 * @link_up: link up or down
6024 **/
6025static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6026{
6027 struct i40e_pf *pf;
6028 int i;
6029
6030 if (!veb || !veb->pf)
6031 return;
6032 pf = veb->pf;
6033
6034 /* depth first... */
6035 for (i = 0; i < I40E_MAX_VEB; i++)
6036 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6037 i40e_veb_link_event(pf->veb[i], link_up);
6038
6039 /* ... now the local VSIs */
505682cd 6040 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6041 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6042 i40e_vsi_link_event(pf->vsi[i], link_up);
6043}
6044
6045/**
6046 * i40e_link_event - Update netif_carrier status
6047 * @pf: board private structure
6048 **/
6049static void i40e_link_event(struct i40e_pf *pf)
6050{
320684cd 6051 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6052 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6053 i40e_status status;
6054 bool new_link, old_link;
41c445ff 6055
1f9610e4
CS		 6056 /* save off old link status information */
6057 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6058
1e701e09
JB		 6059 /* set this to force the get_link_status call to refresh state */
6060 pf->hw.phy.get_link_info = true;
6061
41c445ff 6062 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6063
6064 status = i40e_get_link_status(&pf->hw, &new_link);
6065 if (status) {
6066 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6067 status);
6068 return;
6069 }
6070
fef59ddf
CS		 6071 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6072 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6073
1e701e09 6074 if (new_link == old_link &&
fef59ddf 6075 new_link_speed == old_link_speed &&
320684cd
MW		 6076 (test_bit(__I40E_DOWN, &vsi->state) ||
6077 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6078 return;
320684cd
MW		 6079
6080 if (!test_bit(__I40E_DOWN, &vsi->state))
6081 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6082
6083 /* Notify the base of the switch tree connected to
6084 * the link. Floating VEBs are not notified.
6085 */
6086 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6087 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6088 else
320684cd 6089 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6090
6091 if (pf->vf)
6092 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6093
6094 if (pf->flags & I40E_FLAG_PTP)
6095 i40e_ptp_set_increment(pf);
41c445ff
JB		 6096}
6097
41c445ff 6098/**
21536717 6099 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6100 * @pf: board private structure
6101 **/
6102static void i40e_watchdog_subtask(struct i40e_pf *pf)
6103{
6104 int i;
6105
6106 /* if interface is down do nothing */
6107 if (test_bit(__I40E_DOWN, &pf->state) ||
6108 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6109 return;
6110
21536717
SN		 6111 /* make sure we don't do these things too often */
6112 if (time_before(jiffies, (pf->service_timer_previous +
6113 pf->service_timer_period)))
6114 return;
6115 pf->service_timer_previous = jiffies;
6116
9ac77266
SN		 6117 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6118 i40e_link_event(pf);
21536717 6119
41c445ff
JB		 6120 /* Update the stats for active netdevs so the network stack
6121 * can look at updated numbers whenever it cares to
6122 */
505682cd 6123 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6124 if (pf->vsi[i] && pf->vsi[i]->netdev)
6125 i40e_update_stats(pf->vsi[i]);
6126
d1a8d275
ASJ		 6127 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6128 /* Update the stats for the active switching components */
6129 for (i = 0; i < I40E_MAX_VEB; i++)
6130 if (pf->veb[i])
6131 i40e_update_veb_stats(pf->veb[i]);
6132 }
beb0dff1
JK		 6133
6134 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6135}
6136
6137/**
6138 * i40e_reset_subtask - Set up for resetting the device and driver
6139 * @pf: board private structure
6140 **/
6141static void i40e_reset_subtask(struct i40e_pf *pf)
6142{
6143 u32 reset_flags = 0;
6144
23326186 6145 rtnl_lock();
41c445ff 6146 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6147 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6148 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6149 }
6150 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6151 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6152 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6153 }
6154 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6155 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6156 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6157 }
6158 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6159 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6160 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6161 }
b5d06f05 6162 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6163 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6164 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6165 }
41c445ff
JB		 6166
6167 /* If there's a recovery already waiting, it takes
6168 * precedence before starting a new reset sequence.
6169 */
6170 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6171 i40e_handle_reset_warning(pf);
23326186 6172 goto unlock;
41c445ff
JB		 6173 }
6174
6175 /* If we're already down or resetting, just bail */
6176 if (reset_flags &&
6177 !test_bit(__I40E_DOWN, &pf->state) &&
6178 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6179 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6180
6181unlock:
6182 rtnl_unlock();
41c445ff
JB		 6183}
6184
6185/**
6186 * i40e_handle_link_event - Handle link event
6187 * @pf: board private structure
6188 * @e: event info posted on ARQ
6189 **/
6190static void i40e_handle_link_event(struct i40e_pf *pf,
6191 struct i40e_arq_event_info *e)
6192{
41c445ff
JB		 6193 struct i40e_aqc_get_link_status *status =
6194 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6195
1e701e09
JB		 6196 /* Do a new status request to re-enable LSE reporting
6197 * and load new status information into the hw struct
6198 * This completely ignores any state information
6199 * in the ARQ event info, instead choosing to always
6200 * issue the AQ update link status command.
6201 */
6202 i40e_link_event(pf);
6203
7b592f61
CW		 6204 /* check for unqualified module, if link is down */
6205 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6206 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6207 (!(status->link_info & I40E_AQ_LINK_UP)))
6208 dev_err(&pf->pdev->dev,
6209 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6210}
6211
6212/**
6213 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6214 * @pf: board private structure
6215 **/
6216static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6217{
6218 struct i40e_arq_event_info event;
6219 struct i40e_hw *hw = &pf->hw;
6220 u16 pending, i = 0;
6221 i40e_status ret;
6222 u16 opcode;
86df242b 6223 u32 oldval;
41c445ff
JB		 6224 u32 val;
6225
a316f651
ASJ		 6226 /* Do not run clean AQ when PF reset fails */
6227 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6228 return;
6229
86df242b
SN		 6230 /* check for error indications */
6231 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6232 oldval = val;
6233 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6234 if (hw->debug_mask & I40E_DEBUG_AQ)
6235 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6236 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6237 }
6238 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6239 if (hw->debug_mask & I40E_DEBUG_AQ)
6240 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b 6241 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
1d0a4ada 6242 pf->arq_overflows++;
86df242b
SN		 6243 }
6244 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6245 if (hw->debug_mask & I40E_DEBUG_AQ)
6246 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6247 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6248 }
6249 if (oldval != val)
6250 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6251
6252 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6253 oldval = val;
6254 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6255 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6256 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6257 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6258 }
6259 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6260 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6261 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6262 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6263 }
6264 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6265 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6266 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6267 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6268 }
6269 if (oldval != val)
6270 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6271
1001dc37
MW		 6272 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6273 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6274 if (!event.msg_buf)
6275 return;
6276
6277 do {
6278 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6279 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6280 break;
56497978 6281 else if (ret) {
41c445ff
JB		 6282 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6283 break;
6284 }
6285
6286 opcode = le16_to_cpu(event.desc.opcode);
6287 switch (opcode) {
6288
6289 case i40e_aqc_opc_get_link_status:
6290 i40e_handle_link_event(pf, &event);
6291 break;
6292 case i40e_aqc_opc_send_msg_to_pf:
6293 ret = i40e_vc_process_vf_msg(pf,
6294 le16_to_cpu(event.desc.retval),
6295 le32_to_cpu(event.desc.cookie_high),
6296 le32_to_cpu(event.desc.cookie_low),
6297 event.msg_buf,
1001dc37 6298 event.msg_len);
41c445ff
JB		 6299 break;
6300 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6301 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6302#ifdef CONFIG_I40E_DCB
6303 rtnl_lock();
6304 ret = i40e_handle_lldp_event(pf, &event);
6305 rtnl_unlock();
6306#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6307 break;
6308 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6309 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6310 i40e_handle_lan_overflow_event(pf, &event);
6311 break;
0467bc91
SN		 6312 case i40e_aqc_opc_send_msg_to_peer:
6313 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6314 break;
91a0f930
SN		 6315 case i40e_aqc_opc_nvm_erase:
6316 case i40e_aqc_opc_nvm_update:
00ada50d 6317 case i40e_aqc_opc_oem_post_update:
6e93d0c9
SN		 6318 i40e_debug(&pf->hw, I40E_DEBUG_NVM,
6319 "ARQ NVM operation 0x%04x completed\n",
6320 opcode);
91a0f930 6321 break;
41c445ff
JB		 6322 default:
6323 dev_info(&pf->pdev->dev,
56e5ca68 6324 "ARQ: Unknown event 0x%04x ignored\n",
0467bc91 6325 opcode);
41c445ff
JB		 6326 break;
6327 }
6328 } while (pending && (i++ < pf->adminq_work_limit));
6329
6330 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6331 /* re-enable Admin queue interrupt cause */
6332 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6333 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6334 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6335 i40e_flush(hw);
6336
6337 kfree(event.msg_buf);
6338}
6339
4eb3f768
SN		 6340/**
6341 * i40e_verify_eeprom - make sure eeprom is good to use
6342 * @pf: board private structure
6343 **/
6344static void i40e_verify_eeprom(struct i40e_pf *pf)
6345{
6346 int err;
6347
6348 err = i40e_diag_eeprom_test(&pf->hw);
6349 if (err) {
6350 /* retry in case of garbage read */
6351 err = i40e_diag_eeprom_test(&pf->hw);
6352 if (err) {
6353 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6354 err);
6355 set_bit(__I40E_BAD_EEPROM, &pf->state);
6356 }
6357 }
6358
6359 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6360 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6361 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6362 }
6363}
6364
386a0afa
AA		 6365/**
6366 * i40e_enable_pf_switch_lb
b40c82e6 6367 * @pf: pointer to the PF structure
386a0afa
AA		 6368 *
6369 * enable switch loop back or die - no point in a return value
6370 **/
6371static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6372{
6373 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6374 struct i40e_vsi_context ctxt;
f1c7e72e 6375 int ret;
386a0afa
AA		 6376
6377 ctxt.seid = pf->main_vsi_seid;
6378 ctxt.pf_num = pf->hw.pf_id;
6379 ctxt.vf_num = 0;
f1c7e72e
SN		 6380 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6381 if (ret) {
386a0afa 6382 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6383 "couldn't get PF vsi config, err %s aq_err %s\n",
6384 i40e_stat_str(&pf->hw, ret),
6385 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6386 return;
6387 }
6388 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6389 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6390 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6391
f1c7e72e
SN		 6392 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6393 if (ret) {
386a0afa 6394 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6395 "update vsi switch failed, err %s aq_err %s\n",
6396 i40e_stat_str(&pf->hw, ret),
6397 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6398 }
6399}
6400
6401/**
6402 * i40e_disable_pf_switch_lb
b40c82e6 6403 * @pf: pointer to the PF structure
386a0afa
AA		 6404 *
6405 * disable switch loop back or die - no point in a return value
6406 **/
6407static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6408{
6409 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6410 struct i40e_vsi_context ctxt;
f1c7e72e 6411 int ret;
386a0afa
AA		 6412
6413 ctxt.seid = pf->main_vsi_seid;
6414 ctxt.pf_num = pf->hw.pf_id;
6415 ctxt.vf_num = 0;
f1c7e72e
SN		 6416 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6417 if (ret) {
386a0afa 6418 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6419 "couldn't get PF vsi config, err %s aq_err %s\n",
6420 i40e_stat_str(&pf->hw, ret),
6421 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6422 return;
6423 }
6424 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6425 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6426 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6427
f1c7e72e
SN		 6428 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6429 if (ret) {
386a0afa 6430 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6431 "update vsi switch failed, err %s aq_err %s\n",
6432 i40e_stat_str(&pf->hw, ret),
6433 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6434 }
6435}
6436
51616018
NP		 6437/**
6438 * i40e_config_bridge_mode - Configure the HW bridge mode
6439 * @veb: pointer to the bridge instance
6440 *
6441 * Configure the loop back mode for the LAN VSI that is downlink to the
6442 * specified HW bridge instance. It is expected this function is called
6443 * when a new HW bridge is instantiated.
6444 **/
6445static void i40e_config_bridge_mode(struct i40e_veb *veb)
6446{
6447 struct i40e_pf *pf = veb->pf;
6448
6dec1017
SN		 6449 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6450 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6451 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6452 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6453 i40e_disable_pf_switch_lb(pf);
6454 else
6455 i40e_enable_pf_switch_lb(pf);
6456}
6457
41c445ff
JB		 6458/**
6459 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6460 * @veb: pointer to the VEB instance
6461 *
6462 * This is a recursive function that first builds the attached VSIs then
6463 * recurses in to build the next layer of VEB. We track the connections
6464 * through our own index numbers because the seid's from the HW could
6465 * change across the reset.
6466 **/
6467static int i40e_reconstitute_veb(struct i40e_veb *veb)
6468{
6469 struct i40e_vsi *ctl_vsi = NULL;
6470 struct i40e_pf *pf = veb->pf;
6471 int v, veb_idx;
6472 int ret;
6473
6474 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6475 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6476 if (pf->vsi[v] &&
6477 pf->vsi[v]->veb_idx == veb->idx &&
6478 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6479 ctl_vsi = pf->vsi[v];
6480 break;
6481 }
6482 }
6483 if (!ctl_vsi) {
6484 dev_info(&pf->pdev->dev,
6485 "missing owner VSI for veb_idx %d\n", veb->idx);
6486 ret = -ENOENT;
6487 goto end_reconstitute;
6488 }
6489 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6490 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6491 ret = i40e_add_vsi(ctl_vsi);
6492 if (ret) {
6493 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6494 "rebuild of veb_idx %d owner VSI failed: %d\n",
6495 veb->idx, ret);
41c445ff
JB		 6496 goto end_reconstitute;
6497 }
6498 i40e_vsi_reset_stats(ctl_vsi);
6499
6500 /* create the VEB in the switch and move the VSI onto the VEB */
6501 ret = i40e_add_veb(veb, ctl_vsi);
6502 if (ret)
6503 goto end_reconstitute;
6504
fc60861e
ASJ		 6505 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6506 veb->bridge_mode = BRIDGE_MODE_VEB;
6507 else
6508 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6509 i40e_config_bridge_mode(veb);
b64ba084 6510
41c445ff 6511 /* create the remaining VSIs attached to this VEB */
505682cd 6512 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6513 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6514 continue;
6515
6516 if (pf->vsi[v]->veb_idx == veb->idx) {
6517 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6518
41c445ff
JB		 6519 vsi->uplink_seid = veb->seid;
6520 ret = i40e_add_vsi(vsi);
6521 if (ret) {
6522 dev_info(&pf->pdev->dev,
6523 "rebuild of vsi_idx %d failed: %d\n",
6524 v, ret);
6525 goto end_reconstitute;
6526 }
6527 i40e_vsi_reset_stats(vsi);
6528 }
6529 }
6530
6531 /* create any VEBs attached to this VEB - RECURSION */
6532 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6533 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6534 pf->veb[veb_idx]->uplink_seid = veb->seid;
6535 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6536 if (ret)
6537 break;
6538 }
6539 }
6540
6541end_reconstitute:
6542 return ret;
6543}
6544
6545/**
6546 * i40e_get_capabilities - get info about the HW
6547 * @pf: the PF struct
6548 **/
6549static int i40e_get_capabilities(struct i40e_pf *pf)
6550{
6551 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6552 u16 data_size;
6553 int buf_len;
6554 int err;
6555
6556 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6557 do {
6558 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6559 if (!cap_buf)
6560 return -ENOMEM;
6561
6562 /* this loads the data into the hw struct for us */
6563 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6564 &data_size,
6565 i40e_aqc_opc_list_func_capabilities,
6566 NULL);
6567 /* data loaded, buffer no longer needed */
6568 kfree(cap_buf);
6569
6570 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6571 /* retry with a larger buffer */
6572 buf_len = data_size;
6573 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6574 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6575 "capability discovery failed, err %s aq_err %s\n",
6576 i40e_stat_str(&pf->hw, err),
6577 i40e_aq_str(&pf->hw,
6578 pf->hw.aq.asq_last_status));
41c445ff
JB		 6579 return -ENODEV;
6580 }
6581 } while (err);
6582
6583 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6584 dev_info(&pf->pdev->dev,
6585 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6586 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6587 pf->hw.func_caps.num_msix_vectors,
6588 pf->hw.func_caps.num_msix_vectors_vf,
6589 pf->hw.func_caps.fd_filters_guaranteed,
6590 pf->hw.func_caps.fd_filters_best_effort,
6591 pf->hw.func_caps.num_tx_qp,
6592 pf->hw.func_caps.num_vsis);
6593
7134f9ce
JB		 6594#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6595 + pf->hw.func_caps.num_vfs)
6596 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6597 dev_info(&pf->pdev->dev,
6598 "got num_vsis %d, setting num_vsis to %d\n",
6599 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6600 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6601 }
6602
41c445ff
JB		 6603 return 0;
6604}
6605
cbf61325
ASJ		 6606static int i40e_vsi_clear(struct i40e_vsi *vsi);
6607
41c445ff 6608/**
cbf61325 6609 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6610 * @pf: board private structure
6611 **/
cbf61325 6612static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6613{
6614 struct i40e_vsi *vsi;
8a9eb7d3 6615 int i;
41c445ff 6616
407e063c
JB		 6617 /* quick workaround for an NVM issue that leaves a critical register
6618 * uninitialized
6619 */
6620 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6621 static const u32 hkey[] = {
6622 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6623 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6624 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6625 0x95b3a76d};
6626
6627 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6628 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6629 }
6630
cbf61325 6631 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6632 return;
6633
cbf61325 6634 /* find existing VSI and see if it needs configuring */
41c445ff 6635 vsi = NULL;
505682cd 6636 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6637 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6638 vsi = pf->vsi[i];
cbf61325
ASJ		 6639 break;
6640 }
6641 }
6642
6643 /* create a new VSI if none exists */
41c445ff 6644 if (!vsi) {
cbf61325
ASJ		 6645 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6646 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6647 if (!vsi) {
6648 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6649 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6650 return;
41c445ff 6651 }
cbf61325 6652 }
41c445ff 6653
8a9eb7d3 6654 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6655}
6656
6657/**
6658 * i40e_fdir_teardown - release the Flow Director resources
6659 * @pf: board private structure
6660 **/
6661static void i40e_fdir_teardown(struct i40e_pf *pf)
6662{
6663 int i;
6664
17a73f6b 6665 i40e_fdir_filter_exit(pf);
505682cd 6666 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6667 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6668 i40e_vsi_release(pf->vsi[i]);
6669 break;
6670 }
6671 }
6672}
6673
6674/**
f650a38b 6675 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6676 * @pf: board private structure
6677 *
b40c82e6 6678 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6679 **/
23cfbe07 6680static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6681{
41c445ff 6682 struct i40e_hw *hw = &pf->hw;
60442dea 6683 i40e_status ret = 0;
41c445ff
JB		 6684 u32 v;
6685
6686 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6687 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6688 return;
d3ce5734
MW		 6689 if (i40e_check_asq_alive(&pf->hw))
6690 i40e_vc_notify_reset(pf);
41c445ff 6691
69bfb110 6692 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6693
41c445ff
JB		 6694 /* quiesce the VSIs and their queues that are not already DOWN */
6695 i40e_pf_quiesce_all_vsi(pf);
6696
505682cd 6697 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6698 if (pf->vsi[v])
6699 pf->vsi[v]->seid = 0;
6700 }
6701
6702 i40e_shutdown_adminq(&pf->hw);
6703
f650a38b 6704 /* call shutdown HMC */
60442dea
SN		 6705 if (hw->hmc.hmc_obj) {
6706 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6707 if (ret)
60442dea
SN		 6708 dev_warn(&pf->pdev->dev,
6709 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6710 }
f650a38b
ASJ		 6711}
6712
44033fac
JB		 6713/**
6714 * i40e_send_version - update firmware with driver version
6715 * @pf: PF struct
6716 */
6717static void i40e_send_version(struct i40e_pf *pf)
6718{
6719 struct i40e_driver_version dv;
6720
6721 dv.major_version = DRV_VERSION_MAJOR;
6722 dv.minor_version = DRV_VERSION_MINOR;
6723 dv.build_version = DRV_VERSION_BUILD;
6724 dv.subbuild_version = 0;
35a7d804 6725 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6726 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6727}
6728
f650a38b 6729/**
4dda12e6 6730 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6731 * @pf: board private structure
bc7d338f 6732 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6733 **/
bc7d338f 6734static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6735{
f650a38b 6736 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6737 u8 set_fc_aq_fail = 0;
f650a38b 6738 i40e_status ret;
4f2f017c 6739 u32 val;
f650a38b
ASJ		 6740 u32 v;
6741
41c445ff
JB		 6742 /* Now we wait for GRST to settle out.
6743 * We don't have to delete the VEBs or VSIs from the hw switch
6744 * because the reset will make them disappear.
6745 */
6746 ret = i40e_pf_reset(hw);
b5565400 6747 if (ret) {
41c445ff 6748 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6749 set_bit(__I40E_RESET_FAILED, &pf->state);
6750 goto clear_recovery;
b5565400 6751 }
41c445ff
JB		 6752 pf->pfr_count++;
6753
6754 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6755 goto clear_recovery;
69bfb110 6756 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6757
6758 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6759 ret = i40e_init_adminq(&pf->hw);
6760 if (ret) {
f1c7e72e
SN		 6761 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6762 i40e_stat_str(&pf->hw, ret),
6763 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6764 goto clear_recovery;
41c445ff
JB		 6765 }
6766
4eb3f768 6767 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6768 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6769 i40e_verify_eeprom(pf);
4eb3f768 6770
e78ac4bf 6771 i40e_clear_pxe_mode(hw);
41c445ff 6772 ret = i40e_get_capabilities(pf);
f1c7e72e 6773 if (ret)
41c445ff 6774 goto end_core_reset;
41c445ff 6775
41c445ff
JB		 6776 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6777 hw->func_caps.num_rx_qp,
6778 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6779 if (ret) {
6780 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6781 goto end_core_reset;
6782 }
6783 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6784 if (ret) {
6785 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6786 goto end_core_reset;
6787 }
6788
4e3b35b0
NP		 6789#ifdef CONFIG_I40E_DCB
6790 ret = i40e_init_pf_dcb(pf);
6791 if (ret) {
aebfc816
SN		 6792 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6793 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6794 /* Continue without DCB enabled */
4e3b35b0
NP		 6795 }
6796#endif /* CONFIG_I40E_DCB */
38e00438 6797#ifdef I40E_FCOE
21364bcf 6798 i40e_init_pf_fcoe(pf);
4e3b35b0 6799
38e00438 6800#endif
41c445ff 6801 /* do basic switch setup */
bc7d338f 6802 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6803 if (ret)
6804 goto end_core_reset;
6805
2f0aff41
SN		 6806 /* The driver only wants link up/down and module qualification
6807 * reports from firmware. Note the negative logic.
7e2453fe
JB		 6808 */
6809 ret = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 6810 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 6811 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 6812 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 6813 if (ret)
f1c7e72e
SN		 6814 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6815 i40e_stat_str(&pf->hw, ret),
6816 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6817
cafa2ee6
ASJ		 6818 /* make sure our flow control settings are restored */
6819 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6820 if (ret)
8279e495
NP		 6821 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6822 i40e_stat_str(&pf->hw, ret),
6823 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6824
41c445ff
JB		 6825 /* Rebuild the VSIs and VEBs that existed before reset.
6826 * They are still in our local switch element arrays, so only
6827 * need to rebuild the switch model in the HW.
6828 *
6829 * If there were VEBs but the reconstitution failed, we'll try
6830 * try to recover minimal use by getting the basic PF VSI working.
6831 */
6832 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6833 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6834 /* find the one VEB connected to the MAC, and find orphans */
6835 for (v = 0; v < I40E_MAX_VEB; v++) {
6836 if (!pf->veb[v])
6837 continue;
6838
6839 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6840 pf->veb[v]->uplink_seid == 0) {
6841 ret = i40e_reconstitute_veb(pf->veb[v]);
6842
6843 if (!ret)
6844 continue;
6845
6846 /* If Main VEB failed, we're in deep doodoo,
6847 * so give up rebuilding the switch and set up
6848 * for minimal rebuild of PF VSI.
6849 * If orphan failed, we'll report the error
6850 * but try to keep going.
6851 */
6852 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6853 dev_info(&pf->pdev->dev,
6854 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6855 ret);
6856 pf->vsi[pf->lan_vsi]->uplink_seid
6857 = pf->mac_seid;
6858 break;
6859 } else if (pf->veb[v]->uplink_seid == 0) {
6860 dev_info(&pf->pdev->dev,
6861 "rebuild of orphan VEB failed: %d\n",
6862 ret);
6863 }
6864 }
6865 }
6866 }
6867
6868 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6869 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6870 /* no VEB, so rebuild only the Main VSI */
6871 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6872 if (ret) {
6873 dev_info(&pf->pdev->dev,
6874 "rebuild of Main VSI failed: %d\n", ret);
6875 goto end_core_reset;
6876 }
6877 }
6878
4f2f017c
ASJ		 6879 /* Reconfigure hardware for allowing smaller MSS in the case
6880 * of TSO, so that we avoid the MDD being fired and causing
6881 * a reset in the case of small MSS+TSO.
6882 */
6883#define I40E_REG_MSS 0x000E64DC
6884#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6885#define I40E_64BYTE_MSS 0x400000
6886 val = rd32(hw, I40E_REG_MSS);
6887 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6888 val &= ~I40E_REG_MSS_MIN_MASK;
6889 val |= I40E_64BYTE_MSS;
6890 wr32(hw, I40E_REG_MSS, val);
6891 }
6892
8eed76fa 6893 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 6894 msleep(75);
6895 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6896 if (ret)
f1c7e72e
SN		 6897 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6898 i40e_stat_str(&pf->hw, ret),
6899 i40e_aq_str(&pf->hw,
6900 pf->hw.aq.asq_last_status));
cafa2ee6 6901 }
41c445ff
JB		 6902 /* reinit the misc interrupt */
6903 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6904 ret = i40e_setup_misc_vector(pf);
6905
e7358f54
ASJ		 6906 /* Add a filter to drop all Flow control frames from any VSI from being
6907 * transmitted. By doing so we stop a malicious VF from sending out
6908 * PAUSE or PFC frames and potentially controlling traffic for other
6909 * PF/VF VSIs.
6910 * The FW can still send Flow control frames if enabled.
6911 */
6912 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6913 pf->main_vsi_seid);
6914
41c445ff
JB		 6915 /* restart the VSIs that were rebuilt and running before the reset */
6916 i40e_pf_unquiesce_all_vsi(pf);
6917
69f64b2b
MW		 6918 if (pf->num_alloc_vfs) {
6919 for (v = 0; v < pf->num_alloc_vfs; v++)
6920 i40e_reset_vf(&pf->vf[v], true);
6921 }
6922
41c445ff 6923 /* tell the firmware that we're starting */
44033fac 6924 i40e_send_version(pf);
41c445ff
JB		 6925
6926end_core_reset:
a316f651
ASJ		 6927 clear_bit(__I40E_RESET_FAILED, &pf->state);
6928clear_recovery:
41c445ff
JB		 6929 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6930}
6931
f650a38b 6932/**
b40c82e6 6933 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6934 * @pf: board private structure
6935 *
6936 * Close up the VFs and other things in prep for a Core Reset,
6937 * then get ready to rebuild the world.
6938 **/
6939static void i40e_handle_reset_warning(struct i40e_pf *pf)
6940{
23cfbe07
SN		 6941 i40e_prep_for_reset(pf);
6942 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6943}
6944
41c445ff
JB		 6945/**
6946 * i40e_handle_mdd_event
b40c82e6 6947 * @pf: pointer to the PF structure
41c445ff
JB		 6948 *
6949 * Called from the MDD irq handler to identify possibly malicious vfs
6950 **/
6951static void i40e_handle_mdd_event(struct i40e_pf *pf)
6952{
6953 struct i40e_hw *hw = &pf->hw;
6954 bool mdd_detected = false;
df430b12 6955 bool pf_mdd_detected = false;
41c445ff
JB		 6956 struct i40e_vf *vf;
6957 u32 reg;
6958 int i;
6959
6960 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6961 return;
6962
6963 /* find what triggered the MDD event */
6964 reg = rd32(hw, I40E_GL_MDET_TX);
6965 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6966 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6967 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6968 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6969 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6970 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6971 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6972 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6973 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6974 pf->hw.func_caps.base_queue;
faf32978 6975 if (netif_msg_tx_err(pf))
b40c82e6 6976 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6977 event, queue, pf_num, vf_num);
41c445ff
JB		 6978 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6979 mdd_detected = true;
6980 }
6981 reg = rd32(hw, I40E_GL_MDET_RX);
6982 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6983 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6984 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6985 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6986 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6987 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6988 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6989 pf->hw.func_caps.base_queue;
faf32978
JB		 6990 if (netif_msg_rx_err(pf))
6991 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6992 event, queue, func);
41c445ff
JB		 6993 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6994 mdd_detected = true;
6995 }
6996
df430b12
NP		 6997 if (mdd_detected) {
6998 reg = rd32(hw, I40E_PF_MDET_TX);
6999 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
7000 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 7001 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 7002 pf_mdd_detected = true;
7003 }
7004 reg = rd32(hw, I40E_PF_MDET_RX);
7005 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
7006 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 7007 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 7008 pf_mdd_detected = true;
7009 }
7010 /* Queue belongs to the PF, initiate a reset */
7011 if (pf_mdd_detected) {
7012 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7013 i40e_service_event_schedule(pf);
7014 }
7015 }
7016
41c445ff
JB		 7017 /* see if one of the VFs needs its hand slapped */
7018 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7019 vf = &(pf->vf[i]);
7020 reg = rd32(hw, I40E_VP_MDET_TX(i));
7021 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7022 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7023 vf->num_mdd_events++;
faf32978
JB		 7024 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7025 i);
41c445ff
JB		 7026 }
7027
7028 reg = rd32(hw, I40E_VP_MDET_RX(i));
7029 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7030 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7031 vf->num_mdd_events++;
faf32978
JB		 7032 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7033 i);
41c445ff
JB		 7034 }
7035
7036 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7037 dev_info(&pf->pdev->dev,
7038 "Too many MDD events on VF %d, disabled\n", i);
7039 dev_info(&pf->pdev->dev,
7040 "Use PF Control I/F to re-enable the VF\n");
7041 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7042 }
7043 }
7044
7045 /* re-enable mdd interrupt cause */
7046 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7047 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7048 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7049 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7050 i40e_flush(hw);
7051}
7052
a1c9a9d9 7053/**
6a899024 7054 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7055 * @pf: board private structure
7056 **/
6a899024 7057static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7058{
6a899024 7059#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9
JK		 7060 struct i40e_hw *hw = &pf->hw;
7061 i40e_status ret;
a1c9a9d9
JK		 7062 __be16 port;
7063 int i;
7064
6a899024 7065 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7066 return;
7067
6a899024 7068 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7069
7070 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7071 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7072 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7073 port = pf->udp_ports[i].index;
c22c06c8
SN		 7074 if (port)
7075 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7076 pf->udp_ports[i].type,
c22c06c8
SN		 7077 NULL, NULL);
7078 else
7079 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7080
7081 if (ret) {
730a8f87
CW		 7082 dev_dbg(&pf->pdev->dev,
7083 "%s %s port %d, index %d failed, err %s aq_err %s\n",
7084 pf->udp_ports[i].type ? "vxlan" : "geneve",
7085 port ? "add" : "delete",
7086 ntohs(port), i,
7087 i40e_stat_str(&pf->hw, ret),
7088 i40e_aq_str(&pf->hw,
f1c7e72e 7089 pf->hw.aq.asq_last_status));
6a899024 7090 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7091 }
7092 }
7093 }
6a899024 7094#endif
a1c9a9d9
JK		 7095}
7096
41c445ff
JB		 7097/**
7098 * i40e_service_task - Run the driver's async subtasks
7099 * @work: pointer to work_struct containing our data
7100 **/
7101static void i40e_service_task(struct work_struct *work)
7102{
7103 struct i40e_pf *pf = container_of(work,
7104 struct i40e_pf,
7105 service_task);
7106 unsigned long start_time = jiffies;
7107
e57a2fea
SN		 7108 /* don't bother with service tasks if a reset is in progress */
7109 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7110 i40e_service_event_complete(pf);
7111 return;
7112 }
7113
b03a8c1f 7114 i40e_detect_recover_hung(pf);
2818ccd9 7115 i40e_sync_filters_subtask(pf);
41c445ff
JB		 7116 i40e_reset_subtask(pf);
7117 i40e_handle_mdd_event(pf);
7118 i40e_vc_process_vflr_event(pf);
7119 i40e_watchdog_subtask(pf);
7120 i40e_fdir_reinit_subtask(pf);
e3219ce6 7121 i40e_client_subtask(pf);
41c445ff 7122 i40e_sync_filters_subtask(pf);
6a899024 7123 i40e_sync_udp_filters_subtask(pf);
41c445ff
JB		 7124 i40e_clean_adminq_subtask(pf);
7125
7126 i40e_service_event_complete(pf);
7127
7128 /* If the tasks have taken longer than one timer cycle or there
7129 * is more work to be done, reschedule the service task now
7130 * rather than wait for the timer to tick again.
7131 */
7132 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7133 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7134 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7135 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7136 i40e_service_event_schedule(pf);
7137}
7138
7139/**
7140 * i40e_service_timer - timer callback
7141 * @data: pointer to PF struct
7142 **/
7143static void i40e_service_timer(unsigned long data)
7144{
7145 struct i40e_pf *pf = (struct i40e_pf *)data;
7146
7147 mod_timer(&pf->service_timer,
7148 round_jiffies(jiffies + pf->service_timer_period));
7149 i40e_service_event_schedule(pf);
7150}
7151
7152/**
7153 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7154 * @vsi: the VSI being configured
7155 **/
7156static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7157{
7158 struct i40e_pf *pf = vsi->back;
7159
7160 switch (vsi->type) {
7161 case I40E_VSI_MAIN:
7162 vsi->alloc_queue_pairs = pf->num_lan_qps;
7163 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7164 I40E_REQ_DESCRIPTOR_MULTIPLE);
7165 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7166 vsi->num_q_vectors = pf->num_lan_msix;
7167 else
7168 vsi->num_q_vectors = 1;
7169
7170 break;
7171
7172 case I40E_VSI_FDIR:
7173 vsi->alloc_queue_pairs = 1;
7174 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7175 I40E_REQ_DESCRIPTOR_MULTIPLE);
7176 vsi->num_q_vectors = 1;
7177 break;
7178
7179 case I40E_VSI_VMDQ2:
7180 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7181 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7182 I40E_REQ_DESCRIPTOR_MULTIPLE);
7183 vsi->num_q_vectors = pf->num_vmdq_msix;
7184 break;
7185
7186 case I40E_VSI_SRIOV:
7187 vsi->alloc_queue_pairs = pf->num_vf_qps;
7188 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7189 I40E_REQ_DESCRIPTOR_MULTIPLE);
7190 break;
7191
38e00438
VD		 7192#ifdef I40E_FCOE
7193 case I40E_VSI_FCOE:
7194 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7195 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7196 I40E_REQ_DESCRIPTOR_MULTIPLE);
7197 vsi->num_q_vectors = pf->num_fcoe_msix;
7198 break;
7199
7200#endif /* I40E_FCOE */
41c445ff
JB		 7201 default:
7202 WARN_ON(1);
7203 return -ENODATA;
7204 }
7205
7206 return 0;
7207}
7208
f650a38b
ASJ		 7209/**
7210 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7211 * @type: VSI pointer
bc7d338f 7212 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7213 *
7214 * On error: returns error code (negative)
7215 * On success: returns 0
7216 **/
bc7d338f 7217static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7218{
7219 int size;
7220 int ret = 0;
7221
ac6c5e3d 7222 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7223 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7224 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7225 if (!vsi->tx_rings)
7226 return -ENOMEM;
f650a38b
ASJ		 7227 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7228
bc7d338f
ASJ		 7229 if (alloc_qvectors) {
7230 /* allocate memory for q_vector pointers */
f57e4fbd 7231 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7232 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7233 if (!vsi->q_vectors) {
7234 ret = -ENOMEM;
7235 goto err_vectors;
7236 }
f650a38b
ASJ		 7237 }
7238 return ret;
7239
7240err_vectors:
7241 kfree(vsi->tx_rings);
7242 return ret;
7243}
7244
41c445ff
JB		 7245/**
7246 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7247 * @pf: board private structure
7248 * @type: type of VSI
7249 *
7250 * On error: returns error code (negative)
7251 * On success: returns vsi index in PF (positive)
7252 **/
7253static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7254{
7255 int ret = -ENODEV;
7256 struct i40e_vsi *vsi;
7257 int vsi_idx;
7258 int i;
7259
7260 /* Need to protect the allocation of the VSIs at the PF level */
7261 mutex_lock(&pf->switch_mutex);
7262
7263 /* VSI list may be fragmented if VSI creation/destruction has
7264 * been happening. We can afford to do a quick scan to look
7265 * for any free VSIs in the list.
7266 *
7267 * find next empty vsi slot, looping back around if necessary
7268 */
7269 i = pf->next_vsi;
505682cd 7270 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7271 i++;
505682cd 7272 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7273 i = 0;
7274 while (i < pf->next_vsi && pf->vsi[i])
7275 i++;
7276 }
7277
505682cd 7278 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7279 vsi_idx = i; /* Found one! */
7280 } else {
7281 ret = -ENODEV;
493fb300 7282 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7283 }
7284 pf->next_vsi = ++i;
7285
7286 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7287 if (!vsi) {
7288 ret = -ENOMEM;
493fb300 7289 goto unlock_pf;
41c445ff
JB		 7290 }
7291 vsi->type = type;
7292 vsi->back = pf;
7293 set_bit(__I40E_DOWN, &vsi->state);
7294 vsi->flags = 0;
7295 vsi->idx = vsi_idx;
ac26fc13 7296 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7297 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7298 pf->rss_table_size : 64;
41c445ff
JB		 7299 vsi->netdev_registered = false;
7300 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7301 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7302 vsi->irqs_ready = false;
41c445ff 7303
9f65e15b
AD		 7304 ret = i40e_set_num_rings_in_vsi(vsi);
7305 if (ret)
7306 goto err_rings;
7307
bc7d338f 7308 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7309 if (ret)
9f65e15b 7310 goto err_rings;
493fb300 7311
41c445ff
JB		 7312 /* Setup default MSIX irq handler for VSI */
7313 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7314
21659035
KP		 7315 /* Initialize VSI lock */
7316 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7317 pf->vsi[vsi_idx] = vsi;
7318 ret = vsi_idx;
493fb300
AD		 7319 goto unlock_pf;
7320
9f65e15b 7321err_rings:
493fb300
AD		 7322 pf->next_vsi = i - 1;
7323 kfree(vsi);
7324unlock_pf:
41c445ff
JB		 7325 mutex_unlock(&pf->switch_mutex);
7326 return ret;
7327}
7328
f650a38b
ASJ		 7329/**
7330 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7331 * @type: VSI pointer
bc7d338f 7332 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7333 *
7334 * On error: returns error code (negative)
7335 * On success: returns 0
7336 **/
bc7d338f 7337static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7338{
7339 /* free the ring and vector containers */
bc7d338f
ASJ		 7340 if (free_qvectors) {
7341 kfree(vsi->q_vectors);
7342 vsi->q_vectors = NULL;
7343 }
f650a38b
ASJ		 7344 kfree(vsi->tx_rings);
7345 vsi->tx_rings = NULL;
7346 vsi->rx_rings = NULL;
7347}
7348
28c5869f
HZ		 7349/**
7350 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7351 * and lookup table
7352 * @vsi: Pointer to VSI structure
7353 */
7354static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7355{
7356 if (!vsi)
7357 return;
7358
7359 kfree(vsi->rss_hkey_user);
7360 vsi->rss_hkey_user = NULL;
7361
7362 kfree(vsi->rss_lut_user);
7363 vsi->rss_lut_user = NULL;
7364}
7365
41c445ff
JB		 7366/**
7367 * i40e_vsi_clear - Deallocate the VSI provided
7368 * @vsi: the VSI being un-configured
7369 **/
7370static int i40e_vsi_clear(struct i40e_vsi *vsi)
7371{
7372 struct i40e_pf *pf;
7373
7374 if (!vsi)
7375 return 0;
7376
7377 if (!vsi->back)
7378 goto free_vsi;
7379 pf = vsi->back;
7380
7381 mutex_lock(&pf->switch_mutex);
7382 if (!pf->vsi[vsi->idx]) {
7383 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7384 vsi->idx, vsi->idx, vsi, vsi->type);
7385 goto unlock_vsi;
7386 }
7387
7388 if (pf->vsi[vsi->idx] != vsi) {
7389 dev_err(&pf->pdev->dev,
7390 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7391 pf->vsi[vsi->idx]->idx,
7392 pf->vsi[vsi->idx],
7393 pf->vsi[vsi->idx]->type,
7394 vsi->idx, vsi, vsi->type);
7395 goto unlock_vsi;
7396 }
7397
b40c82e6 7398 /* updates the PF for this cleared vsi */
41c445ff
JB		 7399 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7400 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7401
bc7d338f 7402 i40e_vsi_free_arrays(vsi, true);
28c5869f 7403 i40e_clear_rss_config_user(vsi);
493fb300 7404
41c445ff
JB		 7405 pf->vsi[vsi->idx] = NULL;
7406 if (vsi->idx < pf->next_vsi)
7407 pf->next_vsi = vsi->idx;
7408
7409unlock_vsi:
7410 mutex_unlock(&pf->switch_mutex);
7411free_vsi:
7412 kfree(vsi);
7413
7414 return 0;
7415}
7416
9f65e15b
AD		 7417/**
7418 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7419 * @vsi: the VSI being cleaned
7420 **/
be1d5eea 7421static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7422{
7423 int i;
7424
8e9dca53 7425 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7426 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7427 kfree_rcu(vsi->tx_rings[i], rcu);
7428 vsi->tx_rings[i] = NULL;
7429 vsi->rx_rings[i] = NULL;
7430 }
be1d5eea 7431 }
9f65e15b
AD		 7432}
7433
41c445ff
JB		 7434/**
7435 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7436 * @vsi: the VSI being configured
7437 **/
7438static int i40e_alloc_rings(struct i40e_vsi *vsi)
7439{
e7046ee1 7440 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7441 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7442 int i;
7443
41c445ff 7444 /* Set basic values in the rings to be used later during open() */
d7397644 7445 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7446 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7447 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7448 if (!tx_ring)
7449 goto err_out;
41c445ff
JB		 7450
7451 tx_ring->queue_index = i;
7452 tx_ring->reg_idx = vsi->base_queue + i;
7453 tx_ring->ring_active = false;
7454 tx_ring->vsi = vsi;
7455 tx_ring->netdev = vsi->netdev;
7456 tx_ring->dev = &pf->pdev->dev;
7457 tx_ring->count = vsi->num_desc;
7458 tx_ring->size = 0;
7459 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7460 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7461 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
a75e8005 7462 tx_ring->tx_itr_setting = pf->tx_itr_default;
9f65e15b 7463 vsi->tx_rings[i] = tx_ring;
41c445ff 7464
9f65e15b 7465 rx_ring = &tx_ring[1];
41c445ff
JB		 7466 rx_ring->queue_index = i;
7467 rx_ring->reg_idx = vsi->base_queue + i;
7468 rx_ring->ring_active = false;
7469 rx_ring->vsi = vsi;
7470 rx_ring->netdev = vsi->netdev;
7471 rx_ring->dev = &pf->pdev->dev;
7472 rx_ring->count = vsi->num_desc;
7473 rx_ring->size = 0;
7474 rx_ring->dcb_tc = 0;
a75e8005 7475 rx_ring->rx_itr_setting = pf->rx_itr_default;
9f65e15b 7476 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7477 }
7478
7479 return 0;
9f65e15b
AD		 7480
7481err_out:
7482 i40e_vsi_clear_rings(vsi);
7483 return -ENOMEM;
41c445ff
JB		 7484}
7485
7486/**
7487 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7488 * @pf: board private structure
7489 * @vectors: the number of MSI-X vectors to request
7490 *
7491 * Returns the number of vectors reserved, or error
7492 **/
7493static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7494{
7b37f376
AG		 7495 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7496 I40E_MIN_MSIX, vectors);
7497 if (vectors < 0) {
41c445ff 7498 dev_info(&pf->pdev->dev,
7b37f376 7499 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7500 vectors = 0;
7501 }
7502
7503 return vectors;
7504}
7505
7506/**
7507 * i40e_init_msix - Setup the MSIX capability
7508 * @pf: board private structure
7509 *
7510 * Work with the OS to set up the MSIX vectors needed.
7511 *
3b444399 7512 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7513 **/
7514static int i40e_init_msix(struct i40e_pf *pf)
7515{
41c445ff 7516 struct i40e_hw *hw = &pf->hw;
1e200e4a 7517 int vectors_left;
41c445ff 7518 int v_budget, i;
3b444399 7519 int v_actual;
e3219ce6 7520 int iwarp_requested = 0;
41c445ff
JB		 7521
7522 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7523 return -ENODEV;
7524
7525 /* The number of vectors we'll request will be comprised of:
7526 * - Add 1 for "other" cause for Admin Queue events, etc.
7527 * - The number of LAN queue pairs
f8ff1464
ASJ		 7528 * - Queues being used for RSS.
7529 * We don't need as many as max_rss_size vectors.
7530 * use rss_size instead in the calculation since that
7531 * is governed by number of cpus in the system.
7532 * - assumes symmetric Tx/Rx pairing
41c445ff 7533 * - The number of VMDq pairs
e3219ce6 7534 * - The CPU count within the NUMA node if iWARP is enabled
38e00438
VD		 7535#ifdef I40E_FCOE
7536 * - The number of FCOE qps.
7537#endif
41c445ff
JB		 7538 * Once we count this up, try the request.
7539 *
7540 * If we can't get what we want, we'll simplify to nearly nothing
7541 * and try again. If that still fails, we punt.
7542 */
1e200e4a
SN		 7543 vectors_left = hw->func_caps.num_msix_vectors;
7544 v_budget = 0;
7545
7546 /* reserve one vector for miscellaneous handler */
7547 if (vectors_left) {
7548 v_budget++;
7549 vectors_left--;
7550 }
7551
7552 /* reserve vectors for the main PF traffic queues */
7553 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7554 vectors_left -= pf->num_lan_msix;
7555 v_budget += pf->num_lan_msix;
7556
7557 /* reserve one vector for sideband flow director */
7558 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7559 if (vectors_left) {
7560 v_budget++;
7561 vectors_left--;
7562 } else {
7563 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7564 }
7565 }
83840e4b 7566
38e00438 7567#ifdef I40E_FCOE
1e200e4a 7568 /* can we reserve enough for FCoE? */
38e00438 7569 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7570 if (!vectors_left)
7571 pf->num_fcoe_msix = 0;
7572 else if (vectors_left >= pf->num_fcoe_qps)
7573 pf->num_fcoe_msix = pf->num_fcoe_qps;
7574 else
7575 pf->num_fcoe_msix = 1;
38e00438 7576 v_budget += pf->num_fcoe_msix;
1e200e4a 7577 vectors_left -= pf->num_fcoe_msix;
38e00438 7578 }
1e200e4a 7579
38e00438 7580#endif
e3219ce6
ASJ		 7581 /* can we reserve enough for iWARP? */
7582 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7583 if (!vectors_left)
7584 pf->num_iwarp_msix = 0;
7585 else if (vectors_left < pf->num_iwarp_msix)
7586 pf->num_iwarp_msix = 1;
7587 v_budget += pf->num_iwarp_msix;
7588 vectors_left -= pf->num_iwarp_msix;
7589 }
7590
1e200e4a
SN		 7591 /* any vectors left over go for VMDq support */
7592 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7593 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7594 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7595
7596 /* if we're short on vectors for what's desired, we limit
7597 * the queues per vmdq. If this is still more than are
7598 * available, the user will need to change the number of
7599 * queues/vectors used by the PF later with the ethtool
7600 * channels command
7601 */
7602 if (vmdq_vecs < vmdq_vecs_wanted)
7603 pf->num_vmdq_qps = 1;
7604 pf->num_vmdq_msix = pf->num_vmdq_qps;
7605
7606 v_budget += vmdq_vecs;
7607 vectors_left -= vmdq_vecs;
7608 }
41c445ff
JB		 7609
7610 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7611 GFP_KERNEL);
7612 if (!pf->msix_entries)
7613 return -ENOMEM;
7614
7615 for (i = 0; i < v_budget; i++)
7616 pf->msix_entries[i].entry = i;
3b444399 7617 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7618
3b444399 7619 if (v_actual != v_budget) {
a34977ba
ASJ		 7620 /* If we have limited resources, we will start with no vectors
7621 * for the special features and then allocate vectors to some
7622 * of these features based on the policy and at the end disable
7623 * the features that did not get any vectors.
7624 */
e3219ce6
ASJ		 7625 iwarp_requested = pf->num_iwarp_msix;
7626 pf->num_iwarp_msix = 0;
38e00438
VD		 7627#ifdef I40E_FCOE
7628 pf->num_fcoe_qps = 0;
7629 pf->num_fcoe_msix = 0;
7630#endif
a34977ba
ASJ		 7631 pf->num_vmdq_msix = 0;
7632 }
7633
3b444399 7634 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7635 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7636 kfree(pf->msix_entries);
7637 pf->msix_entries = NULL;
7638 return -ENODEV;
7639
3b444399 7640 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7641 /* Adjust for minimal MSIX use */
41c445ff
JB		 7642 pf->num_vmdq_vsis = 0;
7643 pf->num_vmdq_qps = 0;
41c445ff
JB		 7644 pf->num_lan_qps = 1;
7645 pf->num_lan_msix = 1;
7646
3b444399
SN		 7647 } else if (v_actual != v_budget) {
7648 int vec;
7649
a34977ba 7650 /* reserve the misc vector */
3b444399 7651 vec = v_actual - 1;
a34977ba 7652
41c445ff
JB		 7653 /* Scale vector usage down */
7654 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7655 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7656 pf->num_vmdq_qps = 1;
7657 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7658
7659 /* partition out the remaining vectors */
7660 switch (vec) {
7661 case 2:
41c445ff
JB		 7662 pf->num_lan_msix = 1;
7663 break;
7664 case 3:
e3219ce6
ASJ		 7665 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7666 pf->num_lan_msix = 1;
7667 pf->num_iwarp_msix = 1;
7668 } else {
7669 pf->num_lan_msix = 2;
7670 }
38e00438
VD		 7671#ifdef I40E_FCOE
7672 /* give one vector to FCoE */
7673 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7674 pf->num_lan_msix = 1;
7675 pf->num_fcoe_msix = 1;
7676 }
38e00438 7677#endif
41c445ff
JB		 7678 break;
7679 default:
e3219ce6
ASJ		 7680 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7681 pf->num_iwarp_msix = min_t(int, (vec / 3),
7682 iwarp_requested);
7683 pf->num_vmdq_vsis = min_t(int, (vec / 3),
7684 I40E_DEFAULT_NUM_VMDQ_VSI);
7685 } else {
7686 pf->num_vmdq_vsis = min_t(int, (vec / 2),
7687 I40E_DEFAULT_NUM_VMDQ_VSI);
7688 }
7689 pf->num_lan_msix = min_t(int,
7690 (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)),
7691 pf->num_lan_msix);
38e00438
VD		 7692#ifdef I40E_FCOE
7693 /* give one vector to FCoE */
7694 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7695 pf->num_fcoe_msix = 1;
7696 vec--;
7697 }
7698#endif
41c445ff
JB		 7699 break;
7700 }
7701 }
7702
a34977ba
ASJ		 7703 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7704 (pf->num_vmdq_msix == 0)) {
7705 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7706 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7707 }
e3219ce6
ASJ		 7708
7709 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
7710 (pf->num_iwarp_msix == 0)) {
7711 dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n");
7712 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
7713 }
38e00438
VD		 7714#ifdef I40E_FCOE
7715
7716 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7717 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7718 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7719 }
7720#endif
3b444399 7721 return v_actual;
41c445ff
JB		 7722}
7723
493fb300 7724/**
90e04070 7725 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7726 * @vsi: the VSI being configured
7727 * @v_idx: index of the vector in the vsi struct
7728 *
7729 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7730 **/
90e04070 7731static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7732{
7733 struct i40e_q_vector *q_vector;
7734
7735 /* allocate q_vector */
7736 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7737 if (!q_vector)
7738 return -ENOMEM;
7739
7740 q_vector->vsi = vsi;
7741 q_vector->v_idx = v_idx;
7742 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7743 if (vsi->netdev)
7744 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7745 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7746
cd0b6fa6
AD		 7747 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7748 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7749
493fb300
AD		 7750 /* tie q_vector and vsi together */
7751 vsi->q_vectors[v_idx] = q_vector;
7752
7753 return 0;
7754}
7755
41c445ff 7756/**
90e04070 7757 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7758 * @vsi: the VSI being configured
7759 *
7760 * We allocate one q_vector per queue interrupt. If allocation fails we
7761 * return -ENOMEM.
7762 **/
90e04070 7763static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7764{
7765 struct i40e_pf *pf = vsi->back;
7766 int v_idx, num_q_vectors;
493fb300 7767 int err;
41c445ff
JB		 7768
7769 /* if not MSIX, give the one vector only to the LAN VSI */
7770 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7771 num_q_vectors = vsi->num_q_vectors;
7772 else if (vsi == pf->vsi[pf->lan_vsi])
7773 num_q_vectors = 1;
7774 else
7775 return -EINVAL;
7776
41c445ff 7777 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7778 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7779 if (err)
7780 goto err_out;
41c445ff
JB		 7781 }
7782
7783 return 0;
493fb300
AD		 7784
7785err_out:
7786 while (v_idx--)
7787 i40e_free_q_vector(vsi, v_idx);
7788
7789 return err;
41c445ff
JB		 7790}
7791
7792/**
7793 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7794 * @pf: board private structure to initialize
7795 **/
c1147280 7796static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7797{
3b444399
SN		 7798 int vectors = 0;
7799 ssize_t size;
41c445ff
JB		 7800
7801 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7802 vectors = i40e_init_msix(pf);
7803 if (vectors < 0) {
60ea5f83 7804 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
e3219ce6 7805 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 7806#ifdef I40E_FCOE
7807 I40E_FLAG_FCOE_ENABLED |
7808#endif
60ea5f83 7809 I40E_FLAG_RSS_ENABLED |
4d9b6043 7810 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7811 I40E_FLAG_SRIOV_ENABLED |
7812 I40E_FLAG_FD_SB_ENABLED |
7813 I40E_FLAG_FD_ATR_ENABLED |
7814 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7815
7816 /* rework the queue expectations without MSIX */
7817 i40e_determine_queue_usage(pf);
7818 }
7819 }
7820
7821 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7822 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7823 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7824 vectors = pci_enable_msi(pf->pdev);
7825 if (vectors < 0) {
7826 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7827 vectors);
41c445ff
JB		 7828 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7829 }
3b444399 7830 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7831 }
7832
958a3e3b 7833 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7834 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7835
3b444399
SN		 7836 /* set up vector assignment tracking */
7837 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7838 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7839 if (!pf->irq_pile) {
7840 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7841 return -ENOMEM;
7842 }
3b444399
SN		 7843 pf->irq_pile->num_entries = vectors;
7844 pf->irq_pile->search_hint = 0;
7845
c1147280 7846 /* track first vector for misc interrupts, ignore return */
3b444399 7847 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7848
7849 return 0;
41c445ff
JB		 7850}
7851
7852/**
7853 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7854 * @pf: board private structure
7855 *
7856 * This sets up the handler for MSIX 0, which is used to manage the
7857 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7858 * when in MSI or Legacy interrupt mode.
7859 **/
7860static int i40e_setup_misc_vector(struct i40e_pf *pf)
7861{
7862 struct i40e_hw *hw = &pf->hw;
7863 int err = 0;
7864
7865 /* Only request the irq if this is the first time through, and
7866 * not when we're rebuilding after a Reset
7867 */
7868 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7869 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7870 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7871 if (err) {
7872 dev_info(&pf->pdev->dev,
77fa28be 7873 "request_irq for %s failed: %d\n",
b294ac70 7874 pf->int_name, err);
41c445ff
JB		 7875 return -EFAULT;
7876 }
7877 }
7878
ab437b5a 7879 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7880
7881 /* associate no queues to the misc vector */
7882 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7883 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7884
7885 i40e_flush(hw);
7886
40d72a50 7887 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 7888
7889 return err;
7890}
7891
7892/**
e25d00b8
ASJ		 7893 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7894 * @vsi: vsi structure
7895 * @seed: RSS hash seed
7896 **/
e69ff813
HZ		 7897static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7898 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7899{
7900 struct i40e_aqc_get_set_rss_key_data rss_key;
7901 struct i40e_pf *pf = vsi->back;
7902 struct i40e_hw *hw = &pf->hw;
7903 bool pf_lut = false;
7904 u8 *rss_lut;
7905 int ret, i;
7906
7907 memset(&rss_key, 0, sizeof(rss_key));
7908 memcpy(&rss_key, seed, sizeof(rss_key));
7909
7910 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7911 if (!rss_lut)
7912 return -ENOMEM;
7913
7914 /* Populate the LUT with max no. of queues in round robin fashion */
7915 for (i = 0; i < vsi->rss_table_size; i++)
7916 rss_lut[i] = i % vsi->rss_size;
7917
7918 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7919 if (ret) {
7920 dev_info(&pf->pdev->dev,
7921 "Cannot set RSS key, err %s aq_err %s\n",
7922 i40e_stat_str(&pf->hw, ret),
7923 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7924 goto config_rss_aq_out;
e25d00b8
ASJ		 7925 }
7926
7927 if (vsi->type == I40E_VSI_MAIN)
7928 pf_lut = true;
7929
7930 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7931 vsi->rss_table_size);
7932 if (ret)
7933 dev_info(&pf->pdev->dev,
7934 "Cannot set RSS lut, err %s aq_err %s\n",
7935 i40e_stat_str(&pf->hw, ret),
7936 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7937
126b63d9
AS		 7938config_rss_aq_out:
7939 kfree(rss_lut);
e25d00b8
ASJ		 7940 return ret;
7941}
7942
7943/**
7944 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7945 * @vsi: VSI structure
7946 **/
7947static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7948{
7949 u8 seed[I40E_HKEY_ARRAY_SIZE];
7950 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7951 u8 *lut;
7952 int ret;
7953
7954 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7955 return 0;
7956
7957 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7958 if (!lut)
7959 return -ENOMEM;
e25d00b8 7960
e69ff813 7961 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7962 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7963 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7964 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7965 kfree(lut);
e25d00b8 7966
e69ff813 7967 return ret;
e25d00b8
ASJ		 7968}
7969
95a73780
ASJ		 7970/**
7971 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
7972 * @vsi: Pointer to vsi structure
7973 * @seed: Buffter to store the hash keys
7974 * @lut: Buffer to store the lookup table entries
7975 * @lut_size: Size of buffer to store the lookup table entries
7976 *
7977 * Return 0 on success, negative on failure
7978 */
7979static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7980 u8 *lut, u16 lut_size)
7981{
7982 struct i40e_pf *pf = vsi->back;
7983 struct i40e_hw *hw = &pf->hw;
7984 int ret = 0;
7985
7986 if (seed) {
7987 ret = i40e_aq_get_rss_key(hw, vsi->id,
7988 (struct i40e_aqc_get_set_rss_key_data *)seed);
7989 if (ret) {
7990 dev_info(&pf->pdev->dev,
7991 "Cannot get RSS key, err %s aq_err %s\n",
7992 i40e_stat_str(&pf->hw, ret),
7993 i40e_aq_str(&pf->hw,
7994 pf->hw.aq.asq_last_status));
7995 return ret;
7996 }
7997 }
7998
7999 if (lut) {
8000 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
8001
8002 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
8003 if (ret) {
8004 dev_info(&pf->pdev->dev,
8005 "Cannot get RSS lut, err %s aq_err %s\n",
8006 i40e_stat_str(&pf->hw, ret),
8007 i40e_aq_str(&pf->hw,
8008 pf->hw.aq.asq_last_status));
8009 return ret;
8010 }
8011 }
8012
8013 return ret;
8014}
8015
e25d00b8 8016/**
043dd650 8017 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 8018 * @vsi: Pointer to vsi structure
e25d00b8 8019 * @seed: RSS hash seed
e69ff813
HZ		 8020 * @lut: Lookup table
8021 * @lut_size: Lookup table size
8022 *
8023 * Returns 0 on success, negative on failure
41c445ff 8024 **/
e69ff813
HZ		 8025static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
8026 const u8 *lut, u16 lut_size)
41c445ff 8027{
e69ff813 8028 struct i40e_pf *pf = vsi->back;
4617e8c0 8029 struct i40e_hw *hw = &pf->hw;
c4e1868c 8030 u16 vf_id = vsi->vf_id;
e69ff813 8031 u8 i;
41c445ff 8032
e25d00b8 8033 /* Fill out hash function seed */
e69ff813
HZ		 8034 if (seed) {
8035 u32 *seed_dw = (u32 *)seed;
8036
c4e1868c
MW		 8037 if (vsi->type == I40E_VSI_MAIN) {
8038 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8039 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i),
8040 seed_dw[i]);
8041 } else if (vsi->type == I40E_VSI_SRIOV) {
8042 for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++)
8043 i40e_write_rx_ctl(hw,
8044 I40E_VFQF_HKEY1(i, vf_id),
8045 seed_dw[i]);
8046 } else {
8047 dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n");
8048 }
e69ff813
HZ		 8049 }
8050
8051 if (lut) {
8052 u32 *lut_dw = (u32 *)lut;
8053
c4e1868c
MW		 8054 if (vsi->type == I40E_VSI_MAIN) {
8055 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8056 return -EINVAL;
8057 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8058 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
8059 } else if (vsi->type == I40E_VSI_SRIOV) {
8060 if (lut_size != I40E_VF_HLUT_ARRAY_SIZE)
8061 return -EINVAL;
8062 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++)
8063 i40e_write_rx_ctl(hw,
8064 I40E_VFQF_HLUT1(i, vf_id),
8065 lut_dw[i]);
8066 } else {
8067 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n");
8068 }
e25d00b8
ASJ		 8069 }
8070 i40e_flush(hw);
8071
8072 return 0;
8073}
8074
043dd650
HZ		 8075/**
8076 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
8077 * @vsi: Pointer to VSI structure
8078 * @seed: Buffer to store the keys
8079 * @lut: Buffer to store the lookup table entries
8080 * @lut_size: Size of buffer to store the lookup table entries
8081 *
8082 * Returns 0 on success, negative on failure
8083 */
8084static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
8085 u8 *lut, u16 lut_size)
8086{
8087 struct i40e_pf *pf = vsi->back;
8088 struct i40e_hw *hw = &pf->hw;
8089 u16 i;
8090
8091 if (seed) {
8092 u32 *seed_dw = (u32 *)seed;
8093
8094 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
272cdaf2 8095 seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
043dd650
HZ		 8096 }
8097 if (lut) {
8098 u32 *lut_dw = (u32 *)lut;
8099
8100 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8101 return -EINVAL;
8102 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8103 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
8104 }
8105
8106 return 0;
8107}
8108
8109/**
8110 * i40e_config_rss - Configure RSS keys and lut
8111 * @vsi: Pointer to VSI structure
8112 * @seed: RSS hash seed
8113 * @lut: Lookup table
8114 * @lut_size: Lookup table size
8115 *
8116 * Returns 0 on success, negative on failure
8117 */
8118int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8119{
8120 struct i40e_pf *pf = vsi->back;
8121
8122 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8123 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8124 else
8125 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8126}
8127
8128/**
8129 * i40e_get_rss - Get RSS keys and lut
8130 * @vsi: Pointer to VSI structure
8131 * @seed: Buffer to store the keys
8132 * @lut: Buffer to store the lookup table entries
8133 * lut_size: Size of buffer to store the lookup table entries
8134 *
8135 * Returns 0 on success, negative on failure
8136 */
8137int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8138{
95a73780
ASJ		 8139 struct i40e_pf *pf = vsi->back;
8140
8141 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8142 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
8143 else
8144 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
043dd650
HZ		 8145}
8146
e69ff813
HZ		 8147/**
8148 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8149 * @pf: Pointer to board private structure
8150 * @lut: Lookup table
8151 * @rss_table_size: Lookup table size
8152 * @rss_size: Range of queue number for hashing
8153 */
8154static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8155 u16 rss_table_size, u16 rss_size)
8156{
8157 u16 i;
8158
8159 for (i = 0; i < rss_table_size; i++)
8160 lut[i] = i % rss_size;
8161}
8162
e25d00b8 8163/**
043dd650 8164 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8165 * @pf: board private structure
8166 **/
043dd650 8167static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8168{
8169 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8170 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8171 u8 *lut;
e25d00b8
ASJ		 8172 struct i40e_hw *hw = &pf->hw;
8173 u32 reg_val;
8174 u64 hena;
e69ff813 8175 int ret;
e25d00b8 8176
41c445ff 8177 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
272cdaf2
SN		 8178 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
8179 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8180 hena |= i40e_pf_get_default_rss_hena(pf);
8181
272cdaf2
SN		 8182 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
8183 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
41c445ff 8184
e25d00b8 8185 /* Determine the RSS table size based on the hardware capabilities */
272cdaf2 8186 reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8187 reg_val = (pf->rss_table_size == 512) ?
8188 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8189 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
272cdaf2 8190 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
e157ea30 8191
28c5869f
HZ		 8192 /* Determine the RSS size of the VSI */
8193 if (!vsi->rss_size)
acd65448
HZ		 8194 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8195 vsi->num_queue_pairs);
28c5869f 8196
e69ff813
HZ		 8197 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8198 if (!lut)
8199 return -ENOMEM;
8200
28c5869f
HZ		 8201 /* Use user configured lut if there is one, otherwise use default */
8202 if (vsi->rss_lut_user)
8203 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8204 else
8205 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8206
28c5869f
HZ		 8207 /* Use user configured hash key if there is one, otherwise
8208 * use default.
8209 */
8210 if (vsi->rss_hkey_user)
8211 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8212 else
8213 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8214 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8215 kfree(lut);
8216
8217 return ret;
41c445ff
JB		 8218}
8219
f8ff1464
ASJ		 8220/**
8221 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8222 * @pf: board private structure
8223 * @queue_count: the requested queue count for rss.
8224 *
8225 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8226 * count which may be different from the requested queue count.
8227 **/
8228int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8229{
9a3bd2f1
ASJ		 8230 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8231 int new_rss_size;
8232
f8ff1464
ASJ		 8233 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8234 return 0;
8235
9a3bd2f1 8236 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8237
9a3bd2f1
ASJ		 8238 if (queue_count != vsi->num_queue_pairs) {
8239 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8240 i40e_prep_for_reset(pf);
8241
acd65448 8242 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8243
8244 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8245
8246 /* Discard the user configured hash keys and lut, if less
8247 * queues are enabled.
8248 */
8249 if (queue_count < vsi->rss_size) {
8250 i40e_clear_rss_config_user(vsi);
8251 dev_dbg(&pf->pdev->dev,
8252 "discard user configured hash keys and lut\n");
8253 }
8254
8255 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8256 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8257 vsi->num_queue_pairs);
28c5869f 8258
043dd650 8259 i40e_pf_config_rss(pf);
f8ff1464 8260 }
e36b0b11
HZ		 8261 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8262 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8263 return pf->alloc_rss_size;
f8ff1464
ASJ		 8264}
8265
f4492db1
GR		 8266/**
8267 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8268 * @pf: board private structure
8269 **/
8270i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8271{
8272 i40e_status status;
8273 bool min_valid, max_valid;
8274 u32 max_bw, min_bw;
8275
8276 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8277 &min_valid, &max_valid);
8278
8279 if (!status) {
8280 if (min_valid)
8281 pf->npar_min_bw = min_bw;
8282 if (max_valid)
8283 pf->npar_max_bw = max_bw;
8284 }
8285
8286 return status;
8287}
8288
8289/**
8290 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8291 * @pf: board private structure
8292 **/
8293i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8294{
8295 struct i40e_aqc_configure_partition_bw_data bw_data;
8296 i40e_status status;
8297
b40c82e6 8298 /* Set the valid bit for this PF */
41a1d04b 8299 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8300 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8301 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8302
8303 /* Set the new bandwidths */
8304 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8305
8306 return status;
8307}
8308
8309/**
8310 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8311 * @pf: board private structure
8312 **/
8313i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8314{
8315 /* Commit temporary BW setting to permanent NVM image */
8316 enum i40e_admin_queue_err last_aq_status;
8317 i40e_status ret;
8318 u16 nvm_word;
8319
8320 if (pf->hw.partition_id != 1) {
8321 dev_info(&pf->pdev->dev,
8322 "Commit BW only works on partition 1! This is partition %d",
8323 pf->hw.partition_id);
8324 ret = I40E_NOT_SUPPORTED;
8325 goto bw_commit_out;
8326 }
8327
8328 /* Acquire NVM for read access */
8329 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8330 last_aq_status = pf->hw.aq.asq_last_status;
8331 if (ret) {
8332 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8333 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8334 i40e_stat_str(&pf->hw, ret),
8335 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8336 goto bw_commit_out;
8337 }
8338
8339 /* Read word 0x10 of NVM - SW compatibility word 1 */
8340 ret = i40e_aq_read_nvm(&pf->hw,
8341 I40E_SR_NVM_CONTROL_WORD,
8342 0x10, sizeof(nvm_word), &nvm_word,
8343 false, NULL);
8344 /* Save off last admin queue command status before releasing
8345 * the NVM
8346 */
8347 last_aq_status = pf->hw.aq.asq_last_status;
8348 i40e_release_nvm(&pf->hw);
8349 if (ret) {
f1c7e72e
SN		 8350 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8351 i40e_stat_str(&pf->hw, ret),
8352 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8353 goto bw_commit_out;
8354 }
8355
8356 /* Wait a bit for NVM release to complete */
8357 msleep(50);
8358
8359 /* Acquire NVM for write access */
8360 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8361 last_aq_status = pf->hw.aq.asq_last_status;
8362 if (ret) {
8363 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8364 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8365 i40e_stat_str(&pf->hw, ret),
8366 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8367 goto bw_commit_out;
8368 }
8369 /* Write it back out unchanged to initiate update NVM,
8370 * which will force a write of the shadow (alt) RAM to
8371 * the NVM - thus storing the bandwidth values permanently.
8372 */
8373 ret = i40e_aq_update_nvm(&pf->hw,
8374 I40E_SR_NVM_CONTROL_WORD,
8375 0x10, sizeof(nvm_word),
8376 &nvm_word, true, NULL);
8377 /* Save off last admin queue command status before releasing
8378 * the NVM
8379 */
8380 last_aq_status = pf->hw.aq.asq_last_status;
8381 i40e_release_nvm(&pf->hw);
8382 if (ret)
8383 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8384 "BW settings NOT SAVED, err %s aq_err %s\n",
8385 i40e_stat_str(&pf->hw, ret),
8386 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8387bw_commit_out:
8388
8389 return ret;
8390}
8391
41c445ff
JB		 8392/**
8393 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8394 * @pf: board private structure to initialize
8395 *
8396 * i40e_sw_init initializes the Adapter private data structure.
8397 * Fields are initialized based on PCI device information and
8398 * OS network device settings (MTU size).
8399 **/
8400static int i40e_sw_init(struct i40e_pf *pf)
8401{
8402 int err = 0;
8403 int size;
8404
8405 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8406 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
8407 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8408 if (I40E_DEBUG_USER & debug)
8409 pf->hw.debug_mask = debug;
8410 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8411 I40E_DEFAULT_MSG_ENABLE);
8412 }
8413
8414 /* Set default capability flags */
8415 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8416 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 8417 I40E_FLAG_MSIX_ENABLED;
8418
ca99eb99
MW		 8419 /* Set default ITR */
8420 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8421 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8422
7134f9ce
JB		 8423 /* Depending on PF configurations, it is possible that the RSS
8424 * maximum might end up larger than the available queues
8425 */
41a1d04b 8426 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8427 pf->alloc_rss_size = 1;
5db4cb59 8428 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8429 pf->rss_size_max = min_t(int, pf->rss_size_max,
8430 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8431 if (pf->hw.func_caps.rss) {
8432 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8433 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8434 num_online_cpus());
41c445ff
JB		 8435 }
8436
2050bc65 8437 /* MFP mode enabled */
c78b953e 8438 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8439 pf->flags |= I40E_FLAG_MFP_ENABLED;
8440 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8441 if (i40e_get_npar_bw_setting(pf))
8442 dev_warn(&pf->pdev->dev,
8443 "Could not get NPAR bw settings\n");
8444 else
8445 dev_info(&pf->pdev->dev,
8446 "Min BW = %8.8x, Max BW = %8.8x\n",
8447 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8448 }
8449
cbf61325
ASJ		 8450 /* FW/NVM is not yet fixed in this regard */
8451 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8452 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8453 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8454 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8455 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8456 pf->hw.num_partitions > 1)
cbf61325 8457 dev_info(&pf->pdev->dev,
0b67584f 8458 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8459 else
8460 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8461 pf->fdir_pf_filter_count =
8462 pf->hw.func_caps.fd_filters_guaranteed;
8463 pf->hw.fdir_shared_filter_count =
8464 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8465 }
8466
f1bbad33 8467 if (i40e_is_mac_710(&pf->hw) &&
8eed76fa 8468 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
f1bbad33 8469 (pf->hw.aq.fw_maj_ver < 4))) {
8eed76fa 8470 pf->flags |= I40E_FLAG_RESTART_AUTONEG;
f1bbad33
NP		 8471 /* No DCB support for FW < v4.33 */
8472 pf->flags |= I40E_FLAG_NO_DCB_SUPPORT;
8473 }
8474
8475 /* Disable FW LLDP if FW < v4.3 */
8476 if (i40e_is_mac_710(&pf->hw) &&
8477 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
8478 (pf->hw.aq.fw_maj_ver < 4)))
8479 pf->flags |= I40E_FLAG_STOP_FW_LLDP;
8480
8481 /* Use the FW Set LLDP MIB API if FW > v4.40 */
8482 if (i40e_is_mac_710(&pf->hw) &&
8483 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
8484 (pf->hw.aq.fw_maj_ver >= 5)))
8485 pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB;
8eed76fa 8486
41c445ff 8487 if (pf->hw.func_caps.vmdq) {
41c445ff 8488 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8489 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8490 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8491 }
8492
e3219ce6
ASJ		 8493 if (pf->hw.func_caps.iwarp) {
8494 pf->flags |= I40E_FLAG_IWARP_ENABLED;
8495 /* IWARP needs one extra vector for CQP just like MISC.*/
8496 pf->num_iwarp_msix = (int)num_online_cpus() + 1;
8497 }
8498
38e00438 8499#ifdef I40E_FCOE
21364bcf 8500 i40e_init_pf_fcoe(pf);
38e00438
VD		 8501
8502#endif /* I40E_FCOE */
41c445ff 8503#ifdef CONFIG_PCI_IOV
ba252f13 8504 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8505 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8506 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8507 pf->num_req_vfs = min_t(int,
8508 pf->hw.func_caps.num_vfs,
8509 I40E_MAX_VF_COUNT);
8510 }
8511#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8512 if (pf->hw.mac.type == I40E_MAC_X722) {
8513 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8514 I40E_FLAG_128_QP_RSS_CAPABLE |
8515 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8516 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8517 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024 8518 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
8e2cc0e6 8519 I40E_FLAG_NO_PCI_LINK_CHECK |
f8db54cc 8520 I40E_FLAG_100M_SGMII_CAPABLE |
f1bbad33 8521 I40E_FLAG_USE_SET_LLDP_MIB |
6a899024 8522 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
a340c789
AS		 8523 } else if ((pf->hw.aq.api_maj_ver > 1) ||
8524 ((pf->hw.aq.api_maj_ver == 1) &&
8525 (pf->hw.aq.api_min_ver > 4))) {
8526 /* Supported in FW API version higher than 1.4 */
8527 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
72b74869
ASJ		 8528 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
8529 } else {
8530 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
d502ce01 8531 }
a340c789 8532
41c445ff
JB		 8533 pf->eeprom_version = 0xDEAD;
8534 pf->lan_veb = I40E_NO_VEB;
8535 pf->lan_vsi = I40E_NO_VSI;
8536
d1a8d275
ASJ		 8537 /* By default FW has this off for performance reasons */
8538 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8539
41c445ff
JB		 8540 /* set up queue assignment tracking */
8541 size = sizeof(struct i40e_lump_tracking)
8542 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8543 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8544 if (!pf->qp_pile) {
8545 err = -ENOMEM;
8546 goto sw_init_done;
8547 }
8548 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8549 pf->qp_pile->search_hint = 0;
8550
327fe04b
ASJ		 8551 pf->tx_timeout_recovery_level = 1;
8552
41c445ff
JB		 8553 mutex_init(&pf->switch_mutex);
8554
c668a12c
GR		 8555 /* If NPAR is enabled nudge the Tx scheduler */
8556 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8557 i40e_set_npar_bw_setting(pf);
8558
41c445ff
JB		 8559sw_init_done:
8560 return err;
8561}
8562
7c3c288b
ASJ		 8563/**
8564 * i40e_set_ntuple - set the ntuple feature flag and take action
8565 * @pf: board private structure to initialize
8566 * @features: the feature set that the stack is suggesting
8567 *
8568 * returns a bool to indicate if reset needs to happen
8569 **/
8570bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8571{
8572 bool need_reset = false;
8573
8574 /* Check if Flow Director n-tuple support was enabled or disabled. If
8575 * the state changed, we need to reset.
8576 */
8577 if (features & NETIF_F_NTUPLE) {
8578 /* Enable filters and mark for reset */
8579 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8580 need_reset = true;
8581 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8582 } else {
8583 /* turn off filters, mark for reset and clear SW filter list */
8584 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8585 need_reset = true;
8586 i40e_fdir_filter_exit(pf);
8587 }
8588 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8589 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8590 /* reset fd counters */
8591 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8592 pf->fdir_pf_active_filters = 0;
8593 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8594 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8595 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8596 /* if ATR was auto disabled it can be re-enabled. */
8597 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8598 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8599 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8600 }
8601 return need_reset;
8602}
8603
41c445ff
JB		 8604/**
8605 * i40e_set_features - set the netdev feature flags
8606 * @netdev: ptr to the netdev being adjusted
8607 * @features: the feature set that the stack is suggesting
8608 **/
8609static int i40e_set_features(struct net_device *netdev,
8610 netdev_features_t features)
8611{
8612 struct i40e_netdev_priv *np = netdev_priv(netdev);
8613 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8614 struct i40e_pf *pf = vsi->back;
8615 bool need_reset;
41c445ff
JB		 8616
8617 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8618 i40e_vlan_stripping_enable(vsi);
8619 else
8620 i40e_vlan_stripping_disable(vsi);
8621
7c3c288b
ASJ		 8622 need_reset = i40e_set_ntuple(pf, features);
8623
8624 if (need_reset)
41a1d04b 8625 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8626
41c445ff
JB		 8627 return 0;
8628}
8629
6a899024 8630#if IS_ENABLED(CONFIG_VXLAN) || IS_ENABLED(CONFIG_GENEVE)
a1c9a9d9 8631/**
6a899024 8632 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8633 * @pf: board private structure
8634 * @port: The UDP port to look up
8635 *
8636 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8637 **/
6a899024 8638static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8639{
8640 u8 i;
8641
8642 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8643 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8644 return i;
8645 }
8646
8647 return i;
8648}
8649
6a899024 8650#endif
5cae7615
ED		 8651
8652#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 8653/**
8654 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8655 * @netdev: This physical port's netdev
8656 * @sa_family: Socket Family that VXLAN is notifying us about
8657 * @port: New UDP port number that VXLAN started listening to
8658 **/
8659static void i40e_add_vxlan_port(struct net_device *netdev,
8660 sa_family_t sa_family, __be16 port)
8661{
8662 struct i40e_netdev_priv *np = netdev_priv(netdev);
8663 struct i40e_vsi *vsi = np->vsi;
8664 struct i40e_pf *pf = vsi->back;
8665 u8 next_idx;
8666 u8 idx;
8667
6a899024 8668 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8669
8670 /* Check if port already exists */
8671 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8672 netdev_info(netdev, "vxlan port %d already offloaded\n",
8673 ntohs(port));
a1c9a9d9
JK		 8674 return;
8675 }
8676
8677 /* Now check if there is space to add the new port */
6a899024 8678 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8679
8680 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8681 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8682 ntohs(port));
8683 return;
8684 }
8685
8686 /* New port: add it and mark its index in the bitmap */
6a899024
SA		 8687 pf->udp_ports[next_idx].index = port;
8688 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8689 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8690 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 8691}
8692
8693/**
8694 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8695 * @netdev: This physical port's netdev
8696 * @sa_family: Socket Family that VXLAN is notifying us about
8697 * @port: UDP port number that VXLAN stopped listening to
8698 **/
8699static void i40e_del_vxlan_port(struct net_device *netdev,
8700 sa_family_t sa_family, __be16 port)
8701{
8702 struct i40e_netdev_priv *np = netdev_priv(netdev);
8703 struct i40e_vsi *vsi = np->vsi;
8704 struct i40e_pf *pf = vsi->back;
8705 u8 idx;
8706
6a899024 8707 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8708
8709 /* Check if port already exists */
8710 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8711 /* if port exists, set it to 0 (mark for deletion)
8712 * and make it pending
8713 */
6a899024
SA		 8714 pf->udp_ports[idx].index = 0;
8715 pf->pending_udp_bitmap |= BIT_ULL(idx);
8716 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9 8717 } else {
c22c06c8 8718 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8719 ntohs(port));
8720 }
6a899024 8721}
5cae7615 8722#endif
6a899024 8723
5cae7615 8724#if IS_ENABLED(CONFIG_GENEVE)
6a899024
SA		 8725/**
8726 * i40e_add_geneve_port - Get notifications about GENEVE ports that come up
8727 * @netdev: This physical port's netdev
8728 * @sa_family: Socket Family that GENEVE is notifying us about
8729 * @port: New UDP port number that GENEVE started listening to
8730 **/
8731static void i40e_add_geneve_port(struct net_device *netdev,
8732 sa_family_t sa_family, __be16 port)
8733{
6a899024
SA		 8734 struct i40e_netdev_priv *np = netdev_priv(netdev);
8735 struct i40e_vsi *vsi = np->vsi;
8736 struct i40e_pf *pf = vsi->back;
8737 u8 next_idx;
8738 u8 idx;
8739
a340c789
AS		 8740 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8741 return;
8742
6a899024
SA		 8743 idx = i40e_get_udp_port_idx(pf, port);
8744
8745 /* Check if port already exists */
8746 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8747 netdev_info(netdev, "udp port %d already offloaded\n",
8748 ntohs(port));
8749 return;
8750 }
8751
8752 /* Now check if there is space to add the new port */
8753 next_idx = i40e_get_udp_port_idx(pf, 0);
8754
8755 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8756 netdev_info(netdev, "maximum number of UDP ports reached, not adding port %d\n",
8757 ntohs(port));
8758 return;
8759 }
8760
8761 /* New port: add it and mark its index in the bitmap */
8762 pf->udp_ports[next_idx].index = port;
8763 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8764 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8765 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8766
8767 dev_info(&pf->pdev->dev, "adding geneve port %d\n", ntohs(port));
a1c9a9d9
JK		 8768}
8769
6a899024
SA		 8770/**
8771 * i40e_del_geneve_port - Get notifications about GENEVE ports that go away
8772 * @netdev: This physical port's netdev
8773 * @sa_family: Socket Family that GENEVE is notifying us about
8774 * @port: UDP port number that GENEVE stopped listening to
8775 **/
8776static void i40e_del_geneve_port(struct net_device *netdev,
8777 sa_family_t sa_family, __be16 port)
8778{
6a899024
SA		 8779 struct i40e_netdev_priv *np = netdev_priv(netdev);
8780 struct i40e_vsi *vsi = np->vsi;
8781 struct i40e_pf *pf = vsi->back;
8782 u8 idx;
8783
a340c789
AS		 8784 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8785 return;
8786
6a899024
SA		 8787 idx = i40e_get_udp_port_idx(pf, port);
8788
8789 /* Check if port already exists */
8790 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8791 /* if port exists, set it to 0 (mark for deletion)
8792 * and make it pending
8793 */
8794 pf->udp_ports[idx].index = 0;
8795 pf->pending_udp_bitmap |= BIT_ULL(idx);
8796 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8797
8798 dev_info(&pf->pdev->dev, "deleting geneve port %d\n",
8799 ntohs(port));
8800 } else {
8801 netdev_warn(netdev, "geneve port %d was not found, not deleting\n",
8802 ntohs(port));
8803 }
6a899024 8804}
5cae7615 8805#endif
6a899024 8806
1f224ad2 8807static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8808 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8809{
8810 struct i40e_netdev_priv *np = netdev_priv(netdev);
8811 struct i40e_pf *pf = np->vsi->back;
8812 struct i40e_hw *hw = &pf->hw;
8813
8814 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8815 return -EOPNOTSUPP;
8816
8817 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8818 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8819
8820 return 0;
8821}
8822
2f90ade6
JB		 8823/**
8824 * i40e_ndo_fdb_add - add an entry to the hardware database
8825 * @ndm: the input from the stack
8826 * @tb: pointer to array of nladdr (unused)
8827 * @dev: the net device pointer
8828 * @addr: the MAC address entry being added
8829 * @flags: instructions from stack about fdb operation
8830 */
4ba0dea5
GR		 8831static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8832 struct net_device *dev,
f6f6424b 8833 const unsigned char *addr, u16 vid,
4ba0dea5 8834 u16 flags)
4ba0dea5
GR		 8835{
8836 struct i40e_netdev_priv *np = netdev_priv(dev);
8837 struct i40e_pf *pf = np->vsi->back;
8838 int err = 0;
8839
8840 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8841 return -EOPNOTSUPP;
8842
65891fea
OG		 8843 if (vid) {
8844 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8845 return -EINVAL;
8846 }
8847
4ba0dea5
GR		 8848 /* Hardware does not support aging addresses so if a
8849 * ndm_state is given only allow permanent addresses
8850 */
8851 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8852 netdev_info(dev, "FDB only supports static addresses\n");
8853 return -EINVAL;
8854 }
8855
8856 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8857 err = dev_uc_add_excl(dev, addr);
8858 else if (is_multicast_ether_addr(addr))
8859 err = dev_mc_add_excl(dev, addr);
8860 else
8861 err = -EINVAL;
8862
8863 /* Only return duplicate errors if NLM_F_EXCL is set */
8864 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8865 err = 0;
8866
8867 return err;
8868}
8869
51616018
NP		 8870/**
8871 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8872 * @dev: the netdev being configured
8873 * @nlh: RTNL message
8874 *
8875 * Inserts a new hardware bridge if not already created and
8876 * enables the bridging mode requested (VEB or VEPA). If the
8877 * hardware bridge has already been inserted and the request
8878 * is to change the mode then that requires a PF reset to
8879 * allow rebuild of the components with required hardware
8880 * bridge mode enabled.
8881 **/
8882static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8883 struct nlmsghdr *nlh,
8884 u16 flags)
51616018
NP		 8885{
8886 struct i40e_netdev_priv *np = netdev_priv(dev);
8887 struct i40e_vsi *vsi = np->vsi;
8888 struct i40e_pf *pf = vsi->back;
8889 struct i40e_veb *veb = NULL;
8890 struct nlattr *attr, *br_spec;
8891 int i, rem;
8892
8893 /* Only for PF VSI for now */
8894 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8895 return -EOPNOTSUPP;
8896
8897 /* Find the HW bridge for PF VSI */
8898 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8899 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8900 veb = pf->veb[i];
8901 }
8902
8903 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8904
8905 nla_for_each_nested(attr, br_spec, rem) {
8906 __u16 mode;
8907
8908 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8909 continue;
8910
8911 mode = nla_get_u16(attr);
8912 if ((mode != BRIDGE_MODE_VEPA) &&
8913 (mode != BRIDGE_MODE_VEB))
8914 return -EINVAL;
8915
8916 /* Insert a new HW bridge */
8917 if (!veb) {
8918 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8919 vsi->tc_config.enabled_tc);
8920 if (veb) {
8921 veb->bridge_mode = mode;
8922 i40e_config_bridge_mode(veb);
8923 } else {
8924 /* No Bridge HW offload available */
8925 return -ENOENT;
8926 }
8927 break;
8928 } else if (mode != veb->bridge_mode) {
8929 /* Existing HW bridge but different mode needs reset */
8930 veb->bridge_mode = mode;
fc60861e
ASJ		 8931 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8932 if (mode == BRIDGE_MODE_VEB)
8933 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8934 else
8935 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8936 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8937 break;
8938 }
8939 }
8940
8941 return 0;
8942}
8943
8944/**
8945 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8946 * @skb: skb buff
8947 * @pid: process id
8948 * @seq: RTNL message seq #
8949 * @dev: the netdev being configured
8950 * @filter_mask: unused
d4b2f9fe 8951 * @nlflags: netlink flags passed in
51616018
NP		 8952 *
8953 * Return the mode in which the hardware bridge is operating in
8954 * i.e VEB or VEPA.
8955 **/
51616018
NP		 8956static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8957 struct net_device *dev,
9f4ffc44
CW		 8958 u32 __always_unused filter_mask,
8959 int nlflags)
51616018
NP		 8960{
8961 struct i40e_netdev_priv *np = netdev_priv(dev);
8962 struct i40e_vsi *vsi = np->vsi;
8963 struct i40e_pf *pf = vsi->back;
8964 struct i40e_veb *veb = NULL;
8965 int i;
8966
8967 /* Only for PF VSI for now */
8968 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8969 return -EOPNOTSUPP;
8970
8971 /* Find the HW bridge for the PF VSI */
8972 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8973 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8974 veb = pf->veb[i];
8975 }
8976
8977 if (!veb)
8978 return 0;
8979
46c264da 8980 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8981 nlflags, 0, 0, filter_mask, NULL);
51616018 8982}
51616018 8983
6a899024
SA		 8984/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
8985 * inner mac plus all inner ethertypes.
8986 */
8987#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 8988/**
8989 * i40e_features_check - Validate encapsulated packet conforms to limits
8990 * @skb: skb buff
2bc11c63 8991 * @dev: This physical port's netdev
f44a75e2
JS		 8992 * @features: Offload features that the stack believes apply
8993 **/
8994static netdev_features_t i40e_features_check(struct sk_buff *skb,
8995 struct net_device *dev,
8996 netdev_features_t features)
8997{
8998 if (skb->encapsulation &&
6a899024 8999 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 9000 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 9001 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 9002
9003 return features;
9004}
9005
37a2973a 9006static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 9007 .ndo_open = i40e_open,
9008 .ndo_stop = i40e_close,
9009 .ndo_start_xmit = i40e_lan_xmit_frame,
9010 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
9011 .ndo_set_rx_mode = i40e_set_rx_mode,
9012 .ndo_validate_addr = eth_validate_addr,
9013 .ndo_set_mac_address = i40e_set_mac,
9014 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 9015 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 9016 .ndo_tx_timeout = i40e_tx_timeout,
9017 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
9018 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
9019#ifdef CONFIG_NET_POLL_CONTROLLER
9020 .ndo_poll_controller = i40e_netpoll,
9021#endif
e4c6734e 9022 .ndo_setup_tc = __i40e_setup_tc,
38e00438
VD		 9023#ifdef I40E_FCOE
9024 .ndo_fcoe_enable = i40e_fcoe_enable,
9025 .ndo_fcoe_disable = i40e_fcoe_disable,
9026#endif
41c445ff
JB		 9027 .ndo_set_features = i40e_set_features,
9028 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
9029 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 9030 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 9031 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 9032 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 9033 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
c3bbbd20 9034 .ndo_set_vf_trust = i40e_ndo_set_vf_trust,
6a899024 9035#if IS_ENABLED(CONFIG_VXLAN)
a1c9a9d9
JK		 9036 .ndo_add_vxlan_port = i40e_add_vxlan_port,
9037 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6a899024
SA		 9038#endif
9039#if IS_ENABLED(CONFIG_GENEVE)
9040 .ndo_add_geneve_port = i40e_add_geneve_port,
9041 .ndo_del_geneve_port = i40e_del_geneve_port,
a1c9a9d9 9042#endif
1f224ad2 9043 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 9044 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 9045 .ndo_features_check = i40e_features_check,
51616018
NP		 9046 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
9047 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 9048};
9049
9050/**
9051 * i40e_config_netdev - Setup the netdev flags
9052 * @vsi: the VSI being configured
9053 *
9054 * Returns 0 on success, negative value on failure
9055 **/
9056static int i40e_config_netdev(struct i40e_vsi *vsi)
9057{
1a10370a 9058 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 9059 struct i40e_pf *pf = vsi->back;
9060 struct i40e_hw *hw = &pf->hw;
9061 struct i40e_netdev_priv *np;
9062 struct net_device *netdev;
9063 u8 mac_addr[ETH_ALEN];
9064 int etherdev_size;
9065
9066 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 9067 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 9068 if (!netdev)
9069 return -ENOMEM;
9070
9071 vsi->netdev = netdev;
9072 np = netdev_priv(netdev);
9073 np->vsi = vsi;
9074
b0fe3306
AD		 9075 netdev->hw_enc_features |= NETIF_F_SG |
9076 NETIF_F_IP_CSUM |
9077 NETIF_F_IPV6_CSUM |
9078 NETIF_F_HIGHDMA |
9079 NETIF_F_SOFT_FEATURES |
9080 NETIF_F_TSO |
9081 NETIF_F_TSO_ECN |
9082 NETIF_F_TSO6 |
9083 NETIF_F_GSO_GRE |
1c7b4a23 9084 NETIF_F_GSO_GRE_CSUM |
577389a5
AD		 9085 NETIF_F_GSO_IPIP |
9086 NETIF_F_GSO_SIT |
b0fe3306
AD		 9087 NETIF_F_GSO_UDP_TUNNEL |
9088 NETIF_F_GSO_UDP_TUNNEL_CSUM |
1c7b4a23 9089 NETIF_F_GSO_PARTIAL |
b0fe3306
AD		 9090 NETIF_F_SCTP_CRC |
9091 NETIF_F_RXHASH |
9092 NETIF_F_RXCSUM |
5afdaaa0 9093 0;
41c445ff 9094
b0fe3306 9095 if (!(pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE))
1c7b4a23
AD		 9096 netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
9097
9098 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
b0fe3306
AD		 9099
9100 /* record features VLANs can make use of */
1c7b4a23
AD		 9101 netdev->vlan_features |= netdev->hw_enc_features |
9102 NETIF_F_TSO_MANGLEID;
41c445ff 9103
2e86a0b6 9104 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
b0fe3306
AD		 9105 netdev->hw_features |= NETIF_F_NTUPLE;
9106
9107 netdev->hw_features |= netdev->hw_enc_features |
9108 NETIF_F_HW_VLAN_CTAG_TX |
9109 NETIF_F_HW_VLAN_CTAG_RX;
2e86a0b6 9110
b0fe3306 9111 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
1c7b4a23 9112 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
41c445ff
JB		 9113
9114 if (vsi->type == I40E_VSI_MAIN) {
9115 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 9116 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 9117 /* The following steps are necessary to prevent reception
9118 * of tagged packets - some older NVM configurations load a
9119 * default a MAC-VLAN filter that accepts any tagged packet
9120 * which must be replaced by a normal filter.
8c27d42e 9121 */
21659035
KP		 9122 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
9123 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 9124 i40e_add_filter(vsi, mac_addr,
9125 I40E_VLAN_ANY, false, true);
21659035
KP		 9126 spin_unlock_bh(&vsi->mac_filter_list_lock);
9127 }
3845ccea
ASJ		 9128 } else if ((pf->hw.aq.api_maj_ver > 1) ||
9129 ((pf->hw.aq.api_maj_ver == 1) &&
9130 (pf->hw.aq.api_min_ver > 4))) {
9131 /* Supported in FW API version higher than 1.4 */
9132 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
9133 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
41c445ff
JB		 9134 } else {
9135 /* relate the VSI_VMDQ name to the VSI_MAIN name */
9136 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
9137 pf->vsi[pf->lan_vsi]->netdev->name);
9138 random_ether_addr(mac_addr);
21659035
KP		 9139
9140 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 9141 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 9142 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9143 }
21659035
KP		 9144
9145 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 9146 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 9147 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9148
9a173901
GR		 9149 ether_addr_copy(netdev->dev_addr, mac_addr);
9150 ether_addr_copy(netdev->perm_addr, mac_addr);
b0fe3306 9151
41c445ff
JB		 9152 netdev->priv_flags |= IFF_UNICAST_FLT;
9153 netdev->priv_flags |= IFF_SUPP_NOFCS;
9154 /* Setup netdev TC information */
9155 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9156
9157 netdev->netdev_ops = &i40e_netdev_ops;
9158 netdev->watchdog_timeo = 5 * HZ;
9159 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9160#ifdef I40E_FCOE
9161 i40e_fcoe_config_netdev(netdev, vsi);
9162#endif
41c445ff
JB		 9163
9164 return 0;
9165}
9166
9167/**
9168 * i40e_vsi_delete - Delete a VSI from the switch
9169 * @vsi: the VSI being removed
9170 *
9171 * Returns 0 on success, negative value on failure
9172 **/
9173static void i40e_vsi_delete(struct i40e_vsi *vsi)
9174{
9175 /* remove default VSI is not allowed */
9176 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9177 return;
9178
41c445ff 9179 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9180}
9181
51616018
NP		 9182/**
9183 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9184 * @vsi: the VSI being queried
9185 *
9186 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9187 **/
9188int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9189{
9190 struct i40e_veb *veb;
9191 struct i40e_pf *pf = vsi->back;
9192
9193 /* Uplink is not a bridge so default to VEB */
9194 if (vsi->veb_idx == I40E_NO_VEB)
9195 return 1;
9196
9197 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9198 if (!veb) {
9199 dev_info(&pf->pdev->dev,
9200 "There is no veb associated with the bridge\n");
9201 return -ENOENT;
9202 }
9203
51616018 9204 /* Uplink is a bridge in VEPA mode */
09603eaa 9205 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9206 return 0;
09603eaa
AA		 9207 } else {
9208 /* Uplink is a bridge in VEB mode */
9209 return 1;
9210 }
51616018 9211
09603eaa
AA		 9212 /* VEPA is now default bridge, so return 0 */
9213 return 0;
51616018
NP		 9214}
9215
41c445ff
JB		 9216/**
9217 * i40e_add_vsi - Add a VSI to the switch
9218 * @vsi: the VSI being configured
9219 *
9220 * This initializes a VSI context depending on the VSI type to be added and
9221 * passes it down to the add_vsi aq command.
9222 **/
9223static int i40e_add_vsi(struct i40e_vsi *vsi)
9224{
9225 int ret = -ENODEV;
21659035
KP		 9226 u8 laa_macaddr[ETH_ALEN];
9227 bool found_laa_mac_filter = false;
41c445ff
JB		 9228 struct i40e_pf *pf = vsi->back;
9229 struct i40e_hw *hw = &pf->hw;
9230 struct i40e_vsi_context ctxt;
21659035
KP		 9231 struct i40e_mac_filter *f, *ftmp;
9232
41c445ff
JB		 9233 u8 enabled_tc = 0x1; /* TC0 enabled */
9234 int f_count = 0;
9235
9236 memset(&ctxt, 0, sizeof(ctxt));
9237 switch (vsi->type) {
9238 case I40E_VSI_MAIN:
9239 /* The PF's main VSI is already setup as part of the
9240 * device initialization, so we'll not bother with
9241 * the add_vsi call, but we will retrieve the current
9242 * VSI context.
9243 */
9244 ctxt.seid = pf->main_vsi_seid;
9245 ctxt.pf_num = pf->hw.pf_id;
9246 ctxt.vf_num = 0;
9247 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9248 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9249 if (ret) {
9250 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9251 "couldn't get PF vsi config, err %s aq_err %s\n",
9252 i40e_stat_str(&pf->hw, ret),
9253 i40e_aq_str(&pf->hw,
9254 pf->hw.aq.asq_last_status));
41c445ff
JB		 9255 return -ENOENT;
9256 }
1a2f6248 9257 vsi->info = ctxt.info;
41c445ff
JB		 9258 vsi->info.valid_sections = 0;
9259
9260 vsi->seid = ctxt.seid;
9261 vsi->id = ctxt.vsi_number;
9262
9263 enabled_tc = i40e_pf_get_tc_map(pf);
9264
9265 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9266 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9267 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9268 memset(&ctxt, 0, sizeof(ctxt));
9269 ctxt.seid = pf->main_vsi_seid;
9270 ctxt.pf_num = pf->hw.pf_id;
9271 ctxt.vf_num = 0;
9272 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9273 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9274 if (ret) {
9275 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9276 "update vsi failed, err %s aq_err %s\n",
9277 i40e_stat_str(&pf->hw, ret),
9278 i40e_aq_str(&pf->hw,
9279 pf->hw.aq.asq_last_status));
41c445ff
JB		 9280 ret = -ENOENT;
9281 goto err;
9282 }
9283 /* update the local VSI info queue map */
9284 i40e_vsi_update_queue_map(vsi, &ctxt);
9285 vsi->info.valid_sections = 0;
9286 } else {
9287 /* Default/Main VSI is only enabled for TC0
9288 * reconfigure it to enable all TCs that are
9289 * available on the port in SFP mode.
63d7e5a4
NP		 9290 * For MFP case the iSCSI PF would use this
9291 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9292 */
9293 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9294 if (ret) {
9295 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9296 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9297 enabled_tc,
9298 i40e_stat_str(&pf->hw, ret),
9299 i40e_aq_str(&pf->hw,
9300 pf->hw.aq.asq_last_status));
41c445ff
JB		 9301 ret = -ENOENT;
9302 }
9303 }
9304 break;
9305
9306 case I40E_VSI_FDIR:
cbf61325
ASJ		 9307 ctxt.pf_num = hw->pf_id;
9308 ctxt.vf_num = 0;
9309 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9310 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9311 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9312 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9313 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9314 ctxt.info.valid_sections |=
fc60861e 9315 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9316 ctxt.info.switch_id =
fc60861e 9317 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9318 }
41c445ff 9319 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9320 break;
9321
9322 case I40E_VSI_VMDQ2:
9323 ctxt.pf_num = hw->pf_id;
9324 ctxt.vf_num = 0;
9325 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9326 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9327 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9328
41c445ff
JB		 9329 /* This VSI is connected to VEB so the switch_id
9330 * should be set to zero by default.
9331 */
51616018
NP		 9332 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9333 ctxt.info.valid_sections |=
9334 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9335 ctxt.info.switch_id =
9336 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9337 }
41c445ff
JB		 9338
9339 /* Setup the VSI tx/rx queue map for TC0 only for now */
9340 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9341 break;
9342
9343 case I40E_VSI_SRIOV:
9344 ctxt.pf_num = hw->pf_id;
9345 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9346 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9347 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9348 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9349
41c445ff
JB		 9350 /* This VSI is connected to VEB so the switch_id
9351 * should be set to zero by default.
9352 */
51616018
NP		 9353 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9354 ctxt.info.valid_sections |=
9355 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9356 ctxt.info.switch_id =
9357 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9358 }
41c445ff 9359
e3219ce6
ASJ		 9360 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
9361 ctxt.info.valid_sections |=
9362 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
9363 ctxt.info.queueing_opt_flags |=
9364 I40E_AQ_VSI_QUE_OPT_TCP_ENA;
9365 }
9366
41c445ff
JB		 9367 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9368 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9369 if (pf->vf[vsi->vf_id].spoofchk) {
9370 ctxt.info.valid_sections |=
9371 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9372 ctxt.info.sec_flags |=
9373 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9374 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9375 }
41c445ff
JB		 9376 /* Setup the VSI tx/rx queue map for TC0 only for now */
9377 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9378 break;
9379
38e00438
VD		 9380#ifdef I40E_FCOE
9381 case I40E_VSI_FCOE:
9382 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9383 if (ret) {
9384 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9385 return ret;
9386 }
9387 break;
9388
9389#endif /* I40E_FCOE */
e3219ce6
ASJ		 9390 case I40E_VSI_IWARP:
9391 /* send down message to iWARP */
9392 break;
9393
41c445ff
JB		 9394 default:
9395 return -ENODEV;
9396 }
9397
9398 if (vsi->type != I40E_VSI_MAIN) {
9399 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9400 if (ret) {
9401 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9402 "add vsi failed, err %s aq_err %s\n",
9403 i40e_stat_str(&pf->hw, ret),
9404 i40e_aq_str(&pf->hw,
9405 pf->hw.aq.asq_last_status));
41c445ff
JB		 9406 ret = -ENOENT;
9407 goto err;
9408 }
1a2f6248 9409 vsi->info = ctxt.info;
41c445ff
JB		 9410 vsi->info.valid_sections = 0;
9411 vsi->seid = ctxt.seid;
9412 vsi->id = ctxt.vsi_number;
9413 }
9414
21659035 9415 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9416 /* If macvlan filters already exist, force them to get loaded */
9417 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9418 f->changed = true;
9419 f_count++;
6252c7e4 9420
21659035 9421 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9422 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9423 ether_addr_copy(laa_macaddr, f->macaddr);
9424 found_laa_mac_filter = true;
9425 }
9426 }
9427 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9428
21659035
KP		 9429 if (found_laa_mac_filter) {
9430 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9431
21659035
KP		 9432 memset(&element, 0, sizeof(element));
9433 ether_addr_copy(element.mac_addr, laa_macaddr);
9434 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9435 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9436 &element, 1, NULL);
9437 if (ret) {
9438 /* some older FW has a different default */
9439 element.flags |=
9440 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9441 i40e_aq_remove_macvlan(hw, vsi->seid,
9442 &element, 1, NULL);
6252c7e4 9443 }
21659035
KP		 9444
9445 i40e_aq_mac_address_write(hw,
9446 I40E_AQC_WRITE_TYPE_LAA_WOL,
9447 laa_macaddr, NULL);
41c445ff 9448 }
21659035 9449
41c445ff
JB		 9450 if (f_count) {
9451 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9452 pf->flags |= I40E_FLAG_FILTER_SYNC;
9453 }
9454
9455 /* Update VSI BW information */
9456 ret = i40e_vsi_get_bw_info(vsi);
9457 if (ret) {
9458 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9459 "couldn't get vsi bw info, err %s aq_err %s\n",
9460 i40e_stat_str(&pf->hw, ret),
9461 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9462 /* VSI is already added so not tearing that up */
9463 ret = 0;
9464 }
9465
9466err:
9467 return ret;
9468}
9469
9470/**
9471 * i40e_vsi_release - Delete a VSI and free its resources
9472 * @vsi: the VSI being removed
9473 *
9474 * Returns 0 on success or < 0 on error
9475 **/
9476int i40e_vsi_release(struct i40e_vsi *vsi)
9477{
9478 struct i40e_mac_filter *f, *ftmp;
9479 struct i40e_veb *veb = NULL;
9480 struct i40e_pf *pf;
9481 u16 uplink_seid;
9482 int i, n;
9483
9484 pf = vsi->back;
9485
9486 /* release of a VEB-owner or last VSI is not allowed */
9487 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9488 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9489 vsi->seid, vsi->uplink_seid);
9490 return -ENODEV;
9491 }
9492 if (vsi == pf->vsi[pf->lan_vsi] &&
9493 !test_bit(__I40E_DOWN, &pf->state)) {
9494 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9495 return -ENODEV;
9496 }
9497
9498 uplink_seid = vsi->uplink_seid;
9499 if (vsi->type != I40E_VSI_SRIOV) {
9500 if (vsi->netdev_registered) {
9501 vsi->netdev_registered = false;
9502 if (vsi->netdev) {
9503 /* results in a call to i40e_close() */
9504 unregister_netdev(vsi->netdev);
41c445ff
JB		 9505 }
9506 } else {
90ef8d47 9507 i40e_vsi_close(vsi);
41c445ff
JB		 9508 }
9509 i40e_vsi_disable_irq(vsi);
9510 }
9511
21659035 9512 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9513 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9514 i40e_del_filter(vsi, f->macaddr, f->vlan,
9515 f->is_vf, f->is_netdev);
21659035
KP		 9516 spin_unlock_bh(&vsi->mac_filter_list_lock);
9517
17652c63 9518 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9519
9520 i40e_vsi_delete(vsi);
9521 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9522 if (vsi->netdev) {
9523 free_netdev(vsi->netdev);
9524 vsi->netdev = NULL;
9525 }
41c445ff
JB		 9526 i40e_vsi_clear_rings(vsi);
9527 i40e_vsi_clear(vsi);
9528
9529 /* If this was the last thing on the VEB, except for the
9530 * controlling VSI, remove the VEB, which puts the controlling
9531 * VSI onto the next level down in the switch.
9532 *
9533 * Well, okay, there's one more exception here: don't remove
9534 * the orphan VEBs yet. We'll wait for an explicit remove request
9535 * from up the network stack.
9536 */
505682cd 9537 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9538 if (pf->vsi[i] &&
9539 pf->vsi[i]->uplink_seid == uplink_seid &&
9540 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9541 n++; /* count the VSIs */
9542 }
9543 }
9544 for (i = 0; i < I40E_MAX_VEB; i++) {
9545 if (!pf->veb[i])
9546 continue;
9547 if (pf->veb[i]->uplink_seid == uplink_seid)
9548 n++; /* count the VEBs */
9549 if (pf->veb[i]->seid == uplink_seid)
9550 veb = pf->veb[i];
9551 }
9552 if (n == 0 && veb && veb->uplink_seid != 0)
9553 i40e_veb_release(veb);
9554
9555 return 0;
9556}
9557
9558/**
9559 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9560 * @vsi: ptr to the VSI
9561 *
9562 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9563 * corresponding SW VSI structure and initializes num_queue_pairs for the
9564 * newly allocated VSI.
9565 *
9566 * Returns 0 on success or negative on failure
9567 **/
9568static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9569{
9570 int ret = -ENOENT;
9571 struct i40e_pf *pf = vsi->back;
9572
493fb300 9573 if (vsi->q_vectors[0]) {
41c445ff
JB		 9574 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9575 vsi->seid);
9576 return -EEXIST;
9577 }
9578
9579 if (vsi->base_vector) {
f29eaa3d 9580 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9581 vsi->seid, vsi->base_vector);
9582 return -EEXIST;
9583 }
9584
90e04070 9585 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9586 if (ret) {
9587 dev_info(&pf->pdev->dev,
9588 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9589 vsi->num_q_vectors, vsi->seid, ret);
9590 vsi->num_q_vectors = 0;
9591 goto vector_setup_out;
9592 }
9593
26cdc443
ASJ		 9594 /* In Legacy mode, we do not have to get any other vector since we
9595 * piggyback on the misc/ICR0 for queue interrupts.
9596 */
9597 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9598 return ret;
958a3e3b
SN		 9599 if (vsi->num_q_vectors)
9600 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9601 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9602 if (vsi->base_vector < 0) {
9603 dev_info(&pf->pdev->dev,
049a2be8
SN		 9604 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9605 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9606 i40e_vsi_free_q_vectors(vsi);
9607 ret = -ENOENT;
9608 goto vector_setup_out;
9609 }
9610
9611vector_setup_out:
9612 return ret;
9613}
9614
bc7d338f
ASJ		 9615/**
9616 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9617 * @vsi: pointer to the vsi.
9618 *
9619 * This re-allocates a vsi's queue resources.
9620 *
9621 * Returns pointer to the successfully allocated and configured VSI sw struct
9622 * on success, otherwise returns NULL on failure.
9623 **/
9624static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9625{
f534039d 9626 struct i40e_pf *pf;
bc7d338f
ASJ		 9627 u8 enabled_tc;
9628 int ret;
9629
f534039d
JU		 9630 if (!vsi)
9631 return NULL;
9632
9633 pf = vsi->back;
9634
bc7d338f
ASJ		 9635 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9636 i40e_vsi_clear_rings(vsi);
9637
9638 i40e_vsi_free_arrays(vsi, false);
9639 i40e_set_num_rings_in_vsi(vsi);
9640 ret = i40e_vsi_alloc_arrays(vsi, false);
9641 if (ret)
9642 goto err_vsi;
9643
9644 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9645 if (ret < 0) {
049a2be8 9646 dev_info(&pf->pdev->dev,
f1c7e72e 9647 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9648 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9649 goto err_vsi;
9650 }
9651 vsi->base_queue = ret;
9652
9653 /* Update the FW view of the VSI. Force a reset of TC and queue
9654 * layout configurations.
9655 */
9656 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9657 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9658 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9659 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9660
9661 /* assign it some queues */
9662 ret = i40e_alloc_rings(vsi);
9663 if (ret)
9664 goto err_rings;
9665
9666 /* map all of the rings to the q_vectors */
9667 i40e_vsi_map_rings_to_vectors(vsi);
9668 return vsi;
9669
9670err_rings:
9671 i40e_vsi_free_q_vectors(vsi);
9672 if (vsi->netdev_registered) {
9673 vsi->netdev_registered = false;
9674 unregister_netdev(vsi->netdev);
9675 free_netdev(vsi->netdev);
9676 vsi->netdev = NULL;
9677 }
9678 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9679err_vsi:
9680 i40e_vsi_clear(vsi);
9681 return NULL;
9682}
9683
b499ffb0
SV		 9684/**
9685 * i40e_macaddr_init - explicitly write the mac address filters.
9686 *
9687 * @vsi: pointer to the vsi.
9688 * @macaddr: the MAC address
9689 *
9690 * This is needed when the macaddr has been obtained by other
9691 * means than the default, e.g., from Open Firmware or IDPROM.
9692 * Returns 0 on success, negative on failure
9693 **/
9694static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr)
9695{
9696 int ret;
9697 struct i40e_aqc_add_macvlan_element_data element;
9698
9699 ret = i40e_aq_mac_address_write(&vsi->back->hw,
9700 I40E_AQC_WRITE_TYPE_LAA_WOL,
9701 macaddr, NULL);
9702 if (ret) {
9703 dev_info(&vsi->back->pdev->dev,
9704 "Addr change for VSI failed: %d\n", ret);
9705 return -EADDRNOTAVAIL;
9706 }
9707
9708 memset(&element, 0, sizeof(element));
9709 ether_addr_copy(element.mac_addr, macaddr);
9710 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
9711 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL);
9712 if (ret) {
9713 dev_info(&vsi->back->pdev->dev,
9714 "add filter failed err %s aq_err %s\n",
9715 i40e_stat_str(&vsi->back->hw, ret),
9716 i40e_aq_str(&vsi->back->hw,
9717 vsi->back->hw.aq.asq_last_status));
9718 }
9719 return ret;
9720}
9721
41c445ff
JB		 9722/**
9723 * i40e_vsi_setup - Set up a VSI by a given type
9724 * @pf: board private structure
9725 * @type: VSI type
9726 * @uplink_seid: the switch element to link to
9727 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9728 *
9729 * This allocates the sw VSI structure and its queue resources, then add a VSI
9730 * to the identified VEB.
9731 *
9732 * Returns pointer to the successfully allocated and configure VSI sw struct on
9733 * success, otherwise returns NULL on failure.
9734 **/
9735struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9736 u16 uplink_seid, u32 param1)
9737{
9738 struct i40e_vsi *vsi = NULL;
9739 struct i40e_veb *veb = NULL;
9740 int ret, i;
9741 int v_idx;
9742
9743 /* The requested uplink_seid must be either
9744 * - the PF's port seid
9745 * no VEB is needed because this is the PF
9746 * or this is a Flow Director special case VSI
9747 * - seid of an existing VEB
9748 * - seid of a VSI that owns an existing VEB
9749 * - seid of a VSI that doesn't own a VEB
9750 * a new VEB is created and the VSI becomes the owner
9751 * - seid of the PF VSI, which is what creates the first VEB
9752 * this is a special case of the previous
9753 *
9754 * Find which uplink_seid we were given and create a new VEB if needed
9755 */
9756 for (i = 0; i < I40E_MAX_VEB; i++) {
9757 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9758 veb = pf->veb[i];
9759 break;
9760 }
9761 }
9762
9763 if (!veb && uplink_seid != pf->mac_seid) {
9764
505682cd 9765 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9766 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9767 vsi = pf->vsi[i];
9768 break;
9769 }
9770 }
9771 if (!vsi) {
9772 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9773 uplink_seid);
9774 return NULL;
9775 }
9776
9777 if (vsi->uplink_seid == pf->mac_seid)
9778 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9779 vsi->tc_config.enabled_tc);
9780 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9781 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9782 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9783 if (veb) {
9784 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9785 dev_info(&vsi->back->pdev->dev,
fb43201f 9786 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9787 return NULL;
9788 }
fa11cb3d
ASJ		 9789 /* We come up by default in VEPA mode if SRIOV is not
9790 * already enabled, in which case we can't force VEPA
9791 * mode.
9792 */
9793 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9794 veb->bridge_mode = BRIDGE_MODE_VEPA;
9795 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9796 }
51616018 9797 i40e_config_bridge_mode(veb);
79c21a82 9798 }
41c445ff
JB		 9799 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9800 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9801 veb = pf->veb[i];
9802 }
9803 if (!veb) {
9804 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9805 return NULL;
9806 }
9807
9808 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9809 uplink_seid = veb->seid;
9810 }
9811
9812 /* get vsi sw struct */
9813 v_idx = i40e_vsi_mem_alloc(pf, type);
9814 if (v_idx < 0)
9815 goto err_alloc;
9816 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9817 if (!vsi)
9818 goto err_alloc;
41c445ff
JB		 9819 vsi->type = type;
9820 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9821
9822 if (type == I40E_VSI_MAIN)
9823 pf->lan_vsi = v_idx;
9824 else if (type == I40E_VSI_SRIOV)
9825 vsi->vf_id = param1;
9826 /* assign it some queues */
cbf61325
ASJ		 9827 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9828 vsi->idx);
41c445ff 9829 if (ret < 0) {
049a2be8
SN		 9830 dev_info(&pf->pdev->dev,
9831 "failed to get tracking for %d queues for VSI %d err=%d\n",
9832 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9833 goto err_vsi;
9834 }
9835 vsi->base_queue = ret;
9836
9837 /* get a VSI from the hardware */
9838 vsi->uplink_seid = uplink_seid;
9839 ret = i40e_add_vsi(vsi);
9840 if (ret)
9841 goto err_vsi;
9842
9843 switch (vsi->type) {
9844 /* setup the netdev if needed */
9845 case I40E_VSI_MAIN:
b499ffb0
SV		 9846 /* Apply relevant filters if a platform-specific mac
9847 * address was selected.
9848 */
9849 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
9850 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr);
9851 if (ret) {
9852 dev_warn(&pf->pdev->dev,
9853 "could not set up macaddr; err %d\n",
9854 ret);
9855 }
9856 }
41c445ff 9857 case I40E_VSI_VMDQ2:
38e00438 9858 case I40E_VSI_FCOE:
41c445ff
JB		 9859 ret = i40e_config_netdev(vsi);
9860 if (ret)
9861 goto err_netdev;
9862 ret = register_netdev(vsi->netdev);
9863 if (ret)
9864 goto err_netdev;
9865 vsi->netdev_registered = true;
9866 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9867#ifdef CONFIG_I40E_DCB
9868 /* Setup DCB netlink interface */
9869 i40e_dcbnl_setup(vsi);
9870#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9871 /* fall through */
9872
9873 case I40E_VSI_FDIR:
9874 /* set up vectors and rings if needed */
9875 ret = i40e_vsi_setup_vectors(vsi);
9876 if (ret)
9877 goto err_msix;
9878
9879 ret = i40e_alloc_rings(vsi);
9880 if (ret)
9881 goto err_rings;
9882
9883 /* map all of the rings to the q_vectors */
9884 i40e_vsi_map_rings_to_vectors(vsi);
9885
9886 i40e_vsi_reset_stats(vsi);
9887 break;
9888
9889 default:
9890 /* no netdev or rings for the other VSI types */
9891 break;
9892 }
9893
e25d00b8
ASJ		 9894 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9895 (vsi->type == I40E_VSI_VMDQ2)) {
9896 ret = i40e_vsi_config_rss(vsi);
9897 }
41c445ff
JB		 9898 return vsi;
9899
9900err_rings:
9901 i40e_vsi_free_q_vectors(vsi);
9902err_msix:
9903 if (vsi->netdev_registered) {
9904 vsi->netdev_registered = false;
9905 unregister_netdev(vsi->netdev);
9906 free_netdev(vsi->netdev);
9907 vsi->netdev = NULL;
9908 }
9909err_netdev:
9910 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9911err_vsi:
9912 i40e_vsi_clear(vsi);
9913err_alloc:
9914 return NULL;
9915}
9916
9917/**
9918 * i40e_veb_get_bw_info - Query VEB BW information
9919 * @veb: the veb to query
9920 *
9921 * Query the Tx scheduler BW configuration data for given VEB
9922 **/
9923static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9924{
9925 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9926 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9927 struct i40e_pf *pf = veb->pf;
9928 struct i40e_hw *hw = &pf->hw;
9929 u32 tc_bw_max;
9930 int ret = 0;
9931 int i;
9932
9933 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9934 &bw_data, NULL);
9935 if (ret) {
9936 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9937 "query veb bw config failed, err %s aq_err %s\n",
9938 i40e_stat_str(&pf->hw, ret),
9939 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9940 goto out;
9941 }
9942
9943 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9944 &ets_data, NULL);
9945 if (ret) {
9946 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9947 "query veb bw ets config failed, err %s aq_err %s\n",
9948 i40e_stat_str(&pf->hw, ret),
9949 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9950 goto out;
9951 }
9952
9953 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9954 veb->bw_max_quanta = ets_data.tc_bw_max;
9955 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9956 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9957 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9958 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9959 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9960 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9961 veb->bw_tc_limit_credits[i] =
9962 le16_to_cpu(bw_data.tc_bw_limits[i]);
9963 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9964 }
9965
9966out:
9967 return ret;
9968}
9969
9970/**
9971 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9972 * @pf: board private structure
9973 *
9974 * On error: returns error code (negative)
9975 * On success: returns vsi index in PF (positive)
9976 **/
9977static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9978{
9979 int ret = -ENOENT;
9980 struct i40e_veb *veb;
9981 int i;
9982
9983 /* Need to protect the allocation of switch elements at the PF level */
9984 mutex_lock(&pf->switch_mutex);
9985
9986 /* VEB list may be fragmented if VEB creation/destruction has
9987 * been happening. We can afford to do a quick scan to look
9988 * for any free slots in the list.
9989 *
9990 * find next empty veb slot, looping back around if necessary
9991 */
9992 i = 0;
9993 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9994 i++;
9995 if (i >= I40E_MAX_VEB) {
9996 ret = -ENOMEM;
9997 goto err_alloc_veb; /* out of VEB slots! */
9998 }
9999
10000 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
10001 if (!veb) {
10002 ret = -ENOMEM;
10003 goto err_alloc_veb;
10004 }
10005 veb->pf = pf;
10006 veb->idx = i;
10007 veb->enabled_tc = 1;
10008
10009 pf->veb[i] = veb;
10010 ret = i;
10011err_alloc_veb:
10012 mutex_unlock(&pf->switch_mutex);
10013 return ret;
10014}
10015
10016/**
10017 * i40e_switch_branch_release - Delete a branch of the switch tree
10018 * @branch: where to start deleting
10019 *
10020 * This uses recursion to find the tips of the branch to be
10021 * removed, deleting until we get back to and can delete this VEB.
10022 **/
10023static void i40e_switch_branch_release(struct i40e_veb *branch)
10024{
10025 struct i40e_pf *pf = branch->pf;
10026 u16 branch_seid = branch->seid;
10027 u16 veb_idx = branch->idx;
10028 int i;
10029
10030 /* release any VEBs on this VEB - RECURSION */
10031 for (i = 0; i < I40E_MAX_VEB; i++) {
10032 if (!pf->veb[i])
10033 continue;
10034 if (pf->veb[i]->uplink_seid == branch->seid)
10035 i40e_switch_branch_release(pf->veb[i]);
10036 }
10037
10038 /* Release the VSIs on this VEB, but not the owner VSI.
10039 *
10040 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
10041 * the VEB itself, so don't use (*branch) after this loop.
10042 */
505682cd 10043 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10044 if (!pf->vsi[i])
10045 continue;
10046 if (pf->vsi[i]->uplink_seid == branch_seid &&
10047 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
10048 i40e_vsi_release(pf->vsi[i]);
10049 }
10050 }
10051
10052 /* There's one corner case where the VEB might not have been
10053 * removed, so double check it here and remove it if needed.
10054 * This case happens if the veb was created from the debugfs
10055 * commands and no VSIs were added to it.
10056 */
10057 if (pf->veb[veb_idx])
10058 i40e_veb_release(pf->veb[veb_idx]);
10059}
10060
10061/**
10062 * i40e_veb_clear - remove veb struct
10063 * @veb: the veb to remove
10064 **/
10065static void i40e_veb_clear(struct i40e_veb *veb)
10066{
10067 if (!veb)
10068 return;
10069
10070 if (veb->pf) {
10071 struct i40e_pf *pf = veb->pf;
10072
10073 mutex_lock(&pf->switch_mutex);
10074 if (pf->veb[veb->idx] == veb)
10075 pf->veb[veb->idx] = NULL;
10076 mutex_unlock(&pf->switch_mutex);
10077 }
10078
10079 kfree(veb);
10080}
10081
10082/**
10083 * i40e_veb_release - Delete a VEB and free its resources
10084 * @veb: the VEB being removed
10085 **/
10086void i40e_veb_release(struct i40e_veb *veb)
10087{
10088 struct i40e_vsi *vsi = NULL;
10089 struct i40e_pf *pf;
10090 int i, n = 0;
10091
10092 pf = veb->pf;
10093
10094 /* find the remaining VSI and check for extras */
505682cd 10095 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10096 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
10097 n++;
10098 vsi = pf->vsi[i];
10099 }
10100 }
10101 if (n != 1) {
10102 dev_info(&pf->pdev->dev,
10103 "can't remove VEB %d with %d VSIs left\n",
10104 veb->seid, n);
10105 return;
10106 }
10107
10108 /* move the remaining VSI to uplink veb */
10109 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
10110 if (veb->uplink_seid) {
10111 vsi->uplink_seid = veb->uplink_seid;
10112 if (veb->uplink_seid == pf->mac_seid)
10113 vsi->veb_idx = I40E_NO_VEB;
10114 else
10115 vsi->veb_idx = veb->veb_idx;
10116 } else {
10117 /* floating VEB */
10118 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10119 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
10120 }
10121
10122 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
10123 i40e_veb_clear(veb);
41c445ff
JB		 10124}
10125
10126/**
10127 * i40e_add_veb - create the VEB in the switch
10128 * @veb: the VEB to be instantiated
10129 * @vsi: the controlling VSI
10130 **/
10131static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
10132{
f1c7e72e 10133 struct i40e_pf *pf = veb->pf;
92faef85 10134 bool is_default = veb->pf->cur_promisc;
66fc360a 10135 bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED);
41c445ff
JB		 10136 int ret;
10137
10138 /* get a VEB from the hardware */
f1c7e72e 10139 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95 10140 veb->enabled_tc, is_default,
66fc360a 10141 &veb->seid, enable_stats, NULL);
41c445ff 10142 if (ret) {
f1c7e72e
SN		 10143 dev_info(&pf->pdev->dev,
10144 "couldn't add VEB, err %s aq_err %s\n",
10145 i40e_stat_str(&pf->hw, ret),
10146 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10147 return -EPERM;
10148 }
10149
10150 /* get statistics counter */
f1c7e72e 10151 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 10152 &veb->stats_idx, NULL, NULL, NULL);
10153 if (ret) {
f1c7e72e
SN		 10154 dev_info(&pf->pdev->dev,
10155 "couldn't get VEB statistics idx, err %s aq_err %s\n",
10156 i40e_stat_str(&pf->hw, ret),
10157 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10158 return -EPERM;
10159 }
10160 ret = i40e_veb_get_bw_info(veb);
10161 if (ret) {
f1c7e72e
SN		 10162 dev_info(&pf->pdev->dev,
10163 "couldn't get VEB bw info, err %s aq_err %s\n",
10164 i40e_stat_str(&pf->hw, ret),
10165 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10166 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 10167 return -ENOENT;
10168 }
10169
10170 vsi->uplink_seid = veb->seid;
10171 vsi->veb_idx = veb->idx;
10172 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
10173
10174 return 0;
10175}
10176
10177/**
10178 * i40e_veb_setup - Set up a VEB
10179 * @pf: board private structure
10180 * @flags: VEB setup flags
10181 * @uplink_seid: the switch element to link to
10182 * @vsi_seid: the initial VSI seid
10183 * @enabled_tc: Enabled TC bit-map
10184 *
10185 * This allocates the sw VEB structure and links it into the switch
10186 * It is possible and legal for this to be a duplicate of an already
10187 * existing VEB. It is also possible for both uplink and vsi seids
10188 * to be zero, in order to create a floating VEB.
10189 *
10190 * Returns pointer to the successfully allocated VEB sw struct on
10191 * success, otherwise returns NULL on failure.
10192 **/
10193struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
10194 u16 uplink_seid, u16 vsi_seid,
10195 u8 enabled_tc)
10196{
10197 struct i40e_veb *veb, *uplink_veb = NULL;
10198 int vsi_idx, veb_idx;
10199 int ret;
10200
10201 /* if one seid is 0, the other must be 0 to create a floating relay */
10202 if ((uplink_seid == 0 || vsi_seid == 0) &&
10203 (uplink_seid + vsi_seid != 0)) {
10204 dev_info(&pf->pdev->dev,
10205 "one, not both seid's are 0: uplink=%d vsi=%d\n",
10206 uplink_seid, vsi_seid);
10207 return NULL;
10208 }
10209
10210 /* make sure there is such a vsi and uplink */
505682cd 10211 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10212 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10213 break;
505682cd 10214 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10215 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10216 vsi_seid);
10217 return NULL;
10218 }
10219
10220 if (uplink_seid && uplink_seid != pf->mac_seid) {
10221 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10222 if (pf->veb[veb_idx] &&
10223 pf->veb[veb_idx]->seid == uplink_seid) {
10224 uplink_veb = pf->veb[veb_idx];
10225 break;
10226 }
10227 }
10228 if (!uplink_veb) {
10229 dev_info(&pf->pdev->dev,
10230 "uplink seid %d not found\n", uplink_seid);
10231 return NULL;
10232 }
10233 }
10234
10235 /* get veb sw struct */
10236 veb_idx = i40e_veb_mem_alloc(pf);
10237 if (veb_idx < 0)
10238 goto err_alloc;
10239 veb = pf->veb[veb_idx];
10240 veb->flags = flags;
10241 veb->uplink_seid = uplink_seid;
10242 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10243 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10244
10245 /* create the VEB in the switch */
10246 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10247 if (ret)
10248 goto err_veb;
1bb8b935
SN		 10249 if (vsi_idx == pf->lan_vsi)
10250 pf->lan_veb = veb->idx;
41c445ff
JB		 10251
10252 return veb;
10253
10254err_veb:
10255 i40e_veb_clear(veb);
10256err_alloc:
10257 return NULL;
10258}
10259
10260/**
b40c82e6 10261 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10262 * @pf: board private structure
10263 * @ele: element we are building info from
10264 * @num_reported: total number of elements
10265 * @printconfig: should we print the contents
10266 *
10267 * helper function to assist in extracting a few useful SEID values.
10268 **/
10269static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10270 struct i40e_aqc_switch_config_element_resp *ele,
10271 u16 num_reported, bool printconfig)
10272{
10273 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10274 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10275 u8 element_type = ele->element_type;
10276 u16 seid = le16_to_cpu(ele->seid);
10277
10278 if (printconfig)
10279 dev_info(&pf->pdev->dev,
10280 "type=%d seid=%d uplink=%d downlink=%d\n",
10281 element_type, seid, uplink_seid, downlink_seid);
10282
10283 switch (element_type) {
10284 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10285 pf->mac_seid = seid;
10286 break;
10287 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10288 /* Main VEB? */
10289 if (uplink_seid != pf->mac_seid)
10290 break;
10291 if (pf->lan_veb == I40E_NO_VEB) {
10292 int v;
10293
10294 /* find existing or else empty VEB */
10295 for (v = 0; v < I40E_MAX_VEB; v++) {
10296 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10297 pf->lan_veb = v;
10298 break;
10299 }
10300 }
10301 if (pf->lan_veb == I40E_NO_VEB) {
10302 v = i40e_veb_mem_alloc(pf);
10303 if (v < 0)
10304 break;
10305 pf->lan_veb = v;
10306 }
10307 }
10308
10309 pf->veb[pf->lan_veb]->seid = seid;
10310 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10311 pf->veb[pf->lan_veb]->pf = pf;
10312 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10313 break;
10314 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10315 if (num_reported != 1)
10316 break;
10317 /* This is immediately after a reset so we can assume this is
10318 * the PF's VSI
10319 */
10320 pf->mac_seid = uplink_seid;
10321 pf->pf_seid = downlink_seid;
10322 pf->main_vsi_seid = seid;
10323 if (printconfig)
10324 dev_info(&pf->pdev->dev,
10325 "pf_seid=%d main_vsi_seid=%d\n",
10326 pf->pf_seid, pf->main_vsi_seid);
10327 break;
10328 case I40E_SWITCH_ELEMENT_TYPE_PF:
10329 case I40E_SWITCH_ELEMENT_TYPE_VF:
10330 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10331 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10332 case I40E_SWITCH_ELEMENT_TYPE_PE:
10333 case I40E_SWITCH_ELEMENT_TYPE_PA:
10334 /* ignore these for now */
10335 break;
10336 default:
10337 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10338 element_type, seid);
10339 break;
10340 }
10341}
10342
10343/**
10344 * i40e_fetch_switch_configuration - Get switch config from firmware
10345 * @pf: board private structure
10346 * @printconfig: should we print the contents
10347 *
10348 * Get the current switch configuration from the device and
10349 * extract a few useful SEID values.
10350 **/
10351int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10352{
10353 struct i40e_aqc_get_switch_config_resp *sw_config;
10354 u16 next_seid = 0;
10355 int ret = 0;
10356 u8 *aq_buf;
10357 int i;
10358
10359 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10360 if (!aq_buf)
10361 return -ENOMEM;
10362
10363 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10364 do {
10365 u16 num_reported, num_total;
10366
10367 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10368 I40E_AQ_LARGE_BUF,
10369 &next_seid, NULL);
10370 if (ret) {
10371 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10372 "get switch config failed err %s aq_err %s\n",
10373 i40e_stat_str(&pf->hw, ret),
10374 i40e_aq_str(&pf->hw,
10375 pf->hw.aq.asq_last_status));
41c445ff
JB		 10376 kfree(aq_buf);
10377 return -ENOENT;
10378 }
10379
10380 num_reported = le16_to_cpu(sw_config->header.num_reported);
10381 num_total = le16_to_cpu(sw_config->header.num_total);
10382
10383 if (printconfig)
10384 dev_info(&pf->pdev->dev,
10385 "header: %d reported %d total\n",
10386 num_reported, num_total);
10387
41c445ff
JB		 10388 for (i = 0; i < num_reported; i++) {
10389 struct i40e_aqc_switch_config_element_resp *ele =
10390 &sw_config->element[i];
10391
10392 i40e_setup_pf_switch_element(pf, ele, num_reported,
10393 printconfig);
10394 }
10395 } while (next_seid != 0);
10396
10397 kfree(aq_buf);
10398 return ret;
10399}
10400
10401/**
10402 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10403 * @pf: board private structure
bc7d338f 10404 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10405 *
10406 * Returns 0 on success, negative value on failure
10407 **/
bc7d338f 10408static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10409{
10410 int ret;
10411
10412 /* find out what's out there already */
10413 ret = i40e_fetch_switch_configuration(pf, false);
10414 if (ret) {
10415 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10416 "couldn't fetch switch config, err %s aq_err %s\n",
10417 i40e_stat_str(&pf->hw, ret),
10418 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10419 return ret;
10420 }
10421 i40e_pf_reset_stats(pf);
10422
41c445ff 10423 /* first time setup */
bc7d338f 10424 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10425 struct i40e_vsi *vsi = NULL;
10426 u16 uplink_seid;
10427
10428 /* Set up the PF VSI associated with the PF's main VSI
10429 * that is already in the HW switch
10430 */
10431 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10432 uplink_seid = pf->veb[pf->lan_veb]->seid;
10433 else
10434 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10435 if (pf->lan_vsi == I40E_NO_VSI)
10436 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10437 else if (reinit)
10438 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10439 if (!vsi) {
10440 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10441 i40e_fdir_teardown(pf);
10442 return -EAGAIN;
10443 }
41c445ff
JB		 10444 } else {
10445 /* force a reset of TC and queue layout configurations */
10446 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10447
41c445ff
JB		 10448 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10449 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10450 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10451 }
10452 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10453
cbf61325
ASJ		 10454 i40e_fdir_sb_setup(pf);
10455
41c445ff
JB		 10456 /* Setup static PF queue filter control settings */
10457 ret = i40e_setup_pf_filter_control(pf);
10458 if (ret) {
10459 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10460 ret);
10461 /* Failure here should not stop continuing other steps */
10462 }
10463
10464 /* enable RSS in the HW, even for only one queue, as the stack can use
10465 * the hash
10466 */
10467 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10468 i40e_pf_config_rss(pf);
41c445ff
JB		 10469
10470 /* fill in link information and enable LSE reporting */
0a862b43 10471 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10472 i40e_link_event(pf);
10473
d52c20b7 10474 /* Initialize user-specific link properties */
41c445ff
JB		 10475 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10476 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10477
beb0dff1
JK		 10478 i40e_ptp_init(pf);
10479
41c445ff
JB		 10480 return ret;
10481}
10482
41c445ff
JB		 10483/**
10484 * i40e_determine_queue_usage - Work out queue distribution
10485 * @pf: board private structure
10486 **/
10487static void i40e_determine_queue_usage(struct i40e_pf *pf)
10488{
41c445ff
JB		 10489 int queues_left;
10490
10491 pf->num_lan_qps = 0;
38e00438
VD		 10492#ifdef I40E_FCOE
10493 pf->num_fcoe_qps = 0;
10494#endif
41c445ff
JB		 10495
10496 /* Find the max queues to be put into basic use. We'll always be
10497 * using TC0, whether or not DCB is running, and TC0 will get the
10498 * big RSS set.
10499 */
10500 queues_left = pf->hw.func_caps.num_tx_qp;
10501
cbf61325 10502 if ((queues_left == 1) ||
9aa7e935 10503 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10504 /* one qp for PF, no queues for anything else */
10505 queues_left = 0;
acd65448 10506 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10507
10508 /* make sure all the fancies are disabled */
60ea5f83 10509 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10510 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10511#ifdef I40E_FCOE
10512 I40E_FLAG_FCOE_ENABLED |
10513#endif
60ea5f83
JB		 10514 I40E_FLAG_FD_SB_ENABLED |
10515 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10516 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10517 I40E_FLAG_SRIOV_ENABLED |
10518 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10519 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10520 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10521 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10522 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10523 /* one qp for PF */
acd65448 10524 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10525 queues_left -= pf->num_lan_qps;
10526
10527 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10528 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10529#ifdef I40E_FCOE
10530 I40E_FLAG_FCOE_ENABLED |
10531#endif
9aa7e935
FZ		 10532 I40E_FLAG_FD_SB_ENABLED |
10533 I40E_FLAG_FD_ATR_ENABLED |
10534 I40E_FLAG_DCB_ENABLED |
10535 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10536 } else {
cbf61325 10537 /* Not enough queues for all TCs */
4d9b6043 10538 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10539 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10540 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10541 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10542 }
9a3bd2f1
ASJ		 10543 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10544 num_online_cpus());
10545 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10546 pf->hw.func_caps.num_tx_qp);
10547
cbf61325
ASJ		 10548 queues_left -= pf->num_lan_qps;
10549 }
10550
38e00438
VD		 10551#ifdef I40E_FCOE
10552 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10553 if (I40E_DEFAULT_FCOE <= queues_left) {
10554 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10555 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10556 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10557 } else {
10558 pf->num_fcoe_qps = 0;
10559 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10560 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10561 }
10562
10563 queues_left -= pf->num_fcoe_qps;
10564 }
10565
10566#endif
cbf61325
ASJ		 10567 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10568 if (queues_left > 1) {
10569 queues_left -= 1; /* save 1 queue for FD */
10570 } else {
10571 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10572 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10573 }
41c445ff
JB		 10574 }
10575
10576 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10577 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10578 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10579 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10580 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10581 }
10582
10583 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10584 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10585 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10586 (queues_left / pf->num_vmdq_qps));
10587 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10588 }
10589
f8ff1464 10590 pf->queues_left = queues_left;
8279e495
NP		 10591 dev_dbg(&pf->pdev->dev,
10592 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10593 pf->hw.func_caps.num_tx_qp,
10594 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10595 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10596 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10597 queues_left);
38e00438 10598#ifdef I40E_FCOE
8279e495 10599 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10600#endif
41c445ff
JB		 10601}
10602
10603/**
10604 * i40e_setup_pf_filter_control - Setup PF static filter control
10605 * @pf: PF to be setup
10606 *
b40c82e6 10607 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10608 * settings. If PE/FCoE are enabled then it will also set the per PF
10609 * based filter sizes required for them. It also enables Flow director,
10610 * ethertype and macvlan type filter settings for the pf.
10611 *
10612 * Returns 0 on success, negative on failure
10613 **/
10614static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10615{
10616 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10617
10618 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10619
10620 /* Flow Director is enabled */
60ea5f83 10621 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10622 settings->enable_fdir = true;
10623
10624 /* Ethtype and MACVLAN filters enabled for PF */
10625 settings->enable_ethtype = true;
10626 settings->enable_macvlan = true;
10627
10628 if (i40e_set_filter_control(&pf->hw, settings))
10629 return -ENOENT;
10630
10631 return 0;
10632}
10633
0c22b3dd 10634#define INFO_STRING_LEN 255
7fd89545 10635#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10636static void i40e_print_features(struct i40e_pf *pf)
10637{
10638 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10639 char *buf;
10640 int i;
0c22b3dd 10641
3b195843
JP		 10642 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10643 if (!buf)
0c22b3dd 10644 return;
0c22b3dd 10645
3b195843 10646 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10647#ifdef CONFIG_PCI_IOV
3b195843 10648 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10649#endif
1a557afc 10650 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d",
7fd89545 10651 pf->hw.func_caps.num_vsis,
1a557afc 10652 pf->vsi[pf->lan_vsi]->num_queue_pairs);
0c22b3dd 10653 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10654 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10655 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10656 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10657 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10658 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10659 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10660 }
4d9b6043 10661 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10662 i += snprintf(&buf[i], REMAIN(i), " DCB");
ce6fcb3f 10663#if IS_ENABLED(CONFIG_VXLAN)
3b195843 10664 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024
SA		 10665#endif
10666#if IS_ENABLED(CONFIG_GENEVE)
10667 i += snprintf(&buf[i], REMAIN(i), " Geneve");
ce6fcb3f 10668#endif
0c22b3dd 10669 if (pf->flags & I40E_FLAG_PTP)
3b195843 10670 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10671#ifdef I40E_FCOE
10672 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10673 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10674#endif
6dec1017 10675 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10676 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10677 else
3b195843 10678 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10679
3b195843
JP		 10680 dev_info(&pf->pdev->dev, "%s\n", buf);
10681 kfree(buf);
7fd89545 10682 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10683}
10684
b499ffb0
SV		 10685/**
10686 * i40e_get_platform_mac_addr - get platform-specific MAC address
10687 *
10688 * @pdev: PCI device information struct
10689 * @pf: board private structure
10690 *
10691 * Look up the MAC address in Open Firmware on systems that support it,
10692 * and use IDPROM on SPARC if no OF address is found. On return, the
10693 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value
10694 * has been selected.
10695 **/
10696static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
10697{
b499ffb0 10698 pf->flags &= ~I40E_FLAG_PF_MAC;
ba94272d 10699 if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr))
b499ffb0 10700 pf->flags |= I40E_FLAG_PF_MAC;
b499ffb0
SV		 10701}
10702
41c445ff
JB		 10703/**
10704 * i40e_probe - Device initialization routine
10705 * @pdev: PCI device information struct
10706 * @ent: entry in i40e_pci_tbl
10707 *
b40c82e6
JK		 10708 * i40e_probe initializes a PF identified by a pci_dev structure.
10709 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10710 * and a hardware reset occur.
10711 *
10712 * Returns 0 on success, negative on failure
10713 **/
10714static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10715{
e827845c 10716 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10717 struct i40e_pf *pf;
10718 struct i40e_hw *hw;
93cd765b 10719 static u16 pfs_found;
1d5109d1 10720 u16 wol_nvm_bits;
d4dfb81a 10721 u16 link_status;
6f66a484 10722 int err;
4f2f017c 10723 u32 val;
8a9eb7d3 10724 u32 i;
58fc3267 10725 u8 set_fc_aq_fail;
41c445ff
JB		 10726
10727 err = pci_enable_device_mem(pdev);
10728 if (err)
10729 return err;
10730
10731 /* set up for high or low dma */
6494294f 10732 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10733 if (err) {
e3e3bfdd
JS		 10734 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10735 if (err) {
10736 dev_err(&pdev->dev,
10737 "DMA configuration failed: 0x%x\n", err);
10738 goto err_dma;
10739 }
41c445ff
JB		 10740 }
10741
10742 /* set up pci connections */
10743 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10744 IORESOURCE_MEM), i40e_driver_name);
10745 if (err) {
10746 dev_info(&pdev->dev,
10747 "pci_request_selected_regions failed %d\n", err);
10748 goto err_pci_reg;
10749 }
10750
10751 pci_enable_pcie_error_reporting(pdev);
10752 pci_set_master(pdev);
10753
10754 /* Now that we have a PCI connection, we need to do the
10755 * low level device setup. This is primarily setting up
10756 * the Admin Queue structures and then querying for the
10757 * device's current profile information.
10758 */
10759 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10760 if (!pf) {
10761 err = -ENOMEM;
10762 goto err_pf_alloc;
10763 }
10764 pf->next_vsi = 0;
10765 pf->pdev = pdev;
10766 set_bit(__I40E_DOWN, &pf->state);
10767
10768 hw = &pf->hw;
10769 hw->back = pf;
232f4706 10770
2ac8b675
SN		 10771 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10772 I40E_MAX_CSR_SPACE);
232f4706 10773
2ac8b675 10774 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10775 if (!hw->hw_addr) {
10776 err = -EIO;
10777 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10778 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10779 pf->ioremap_len, err);
41c445ff
JB		 10780 goto err_ioremap;
10781 }
10782 hw->vendor_id = pdev->vendor;
10783 hw->device_id = pdev->device;
10784 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10785 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10786 hw->subsystem_device_id = pdev->subsystem_device;
10787 hw->bus.device = PCI_SLOT(pdev->devfn);
10788 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10789 pf->instance = pfs_found;
41c445ff 10790
de03d2b0
SN		 10791 /* set up the locks for the AQ, do this only once in probe
10792 * and destroy them only once in remove
10793 */
10794 mutex_init(&hw->aq.asq_mutex);
10795 mutex_init(&hw->aq.arq_mutex);
10796
5b5faa43
SN		 10797 if (debug != -1) {
10798 pf->msg_enable = pf->hw.debug_mask;
10799 pf->msg_enable = debug;
10800 }
10801
7134f9ce
JB		 10802 /* do a special CORER for clearing PXE mode once at init */
10803 if (hw->revision_id == 0 &&
10804 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10805 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10806 i40e_flush(hw);
10807 msleep(200);
10808 pf->corer_count++;
10809
10810 i40e_clear_pxe_mode(hw);
10811 }
10812
41c445ff 10813 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10814 i40e_clear_hw(hw);
41c445ff
JB		 10815 err = i40e_pf_reset(hw);
10816 if (err) {
10817 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10818 goto err_pf_reset;
10819 }
10820 pf->pfr_count++;
10821
10822 hw->aq.num_arq_entries = I40E_AQ_LEN;
10823 hw->aq.num_asq_entries = I40E_AQ_LEN;
10824 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10825 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10826 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10827
b294ac70 10828 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10829 "%s-%s:misc",
10830 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10831
10832 err = i40e_init_shared_code(hw);
10833 if (err) {
b2a75c58
ASJ		 10834 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10835 err);
41c445ff
JB		 10836 goto err_pf_reset;
10837 }
10838
d52c20b7
JB		 10839 /* set up a default setting for link flow control */
10840 pf->hw.fc.requested_mode = I40E_FC_NONE;
10841
41c445ff 10842 err = i40e_init_adminq(hw);
2b2426a7
CW		 10843 if (err) {
10844 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10845 dev_info(&pdev->dev,
10846 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10847 else
10848 dev_info(&pdev->dev,
10849 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10850
10851 goto err_pf_reset;
10852 }
f0b44440 10853
6dec1017
SN		 10854 /* provide nvm, fw, api versions */
10855 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10856 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10857 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10858 i40e_nvm_version_str(hw));
f0b44440 10859
7aa67613
CS		 10860 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10861 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10862 dev_info(&pdev->dev,
7aa67613
CS		 10863 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10864 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10865 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10866 dev_info(&pdev->dev,
7aa67613 10867 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10868
4eb3f768
SN		 10869 i40e_verify_eeprom(pf);
10870
2c5fe33b
JB		 10871 /* Rev 0 hardware was never productized */
10872 if (hw->revision_id < 1)
10873 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10874
6ff4ef86 10875 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10876 err = i40e_get_capabilities(pf);
10877 if (err)
10878 goto err_adminq_setup;
10879
10880 err = i40e_sw_init(pf);
10881 if (err) {
10882 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10883 goto err_sw_init;
10884 }
10885
10886 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10887 hw->func_caps.num_rx_qp,
10888 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10889 if (err) {
10890 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10891 goto err_init_lan_hmc;
10892 }
10893
10894 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10895 if (err) {
10896 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10897 err = -ENOENT;
10898 goto err_configure_lan_hmc;
10899 }
10900
b686ece5
NP		 10901 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10902 * Ignore error return codes because if it was already disabled via
10903 * hardware settings this will fail
10904 */
f1bbad33 10905 if (pf->flags & I40E_FLAG_STOP_FW_LLDP) {
b686ece5
NP		 10906 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10907 i40e_aq_stop_lldp(hw, true, NULL);
10908 }
10909
41c445ff 10910 i40e_get_mac_addr(hw, hw->mac.addr);
b499ffb0
SV		 10911 /* allow a platform config to override the HW addr */
10912 i40e_get_platform_mac_addr(pdev, pf);
f62b5060 10913 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10914 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10915 err = -EIO;
10916 goto err_mac_addr;
10917 }
10918 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10919 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10920 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10921 if (is_valid_ether_addr(hw->mac.port_addr))
10922 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10923#ifdef I40E_FCOE
10924 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10925 if (err)
10926 dev_info(&pdev->dev,
10927 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10928 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10929 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10930 hw->mac.san_addr);
10931 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10932 }
10933 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10934#endif /* I40E_FCOE */
41c445ff
JB		 10935
10936 pci_set_drvdata(pdev, pf);
10937 pci_save_state(pdev);
4e3b35b0
NP		 10938#ifdef CONFIG_I40E_DCB
10939 err = i40e_init_pf_dcb(pf);
10940 if (err) {
aebfc816 10941 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10942 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10943 /* Continue without DCB enabled */
4e3b35b0
NP		 10944 }
10945#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10946
10947 /* set up periodic task facility */
10948 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10949 pf->service_timer_period = HZ;
10950
10951 INIT_WORK(&pf->service_task, i40e_service_task);
10952 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10953 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10954
1d5109d1
SN		 10955 /* NVM bit on means WoL disabled for the port */
10956 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10957 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10958 pf->wol_en = false;
10959 else
10960 pf->wol_en = true;
8e2773ae
SN		 10961 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10962
41c445ff
JB		 10963 /* set up the main switch operations */
10964 i40e_determine_queue_usage(pf);
c1147280
JB		 10965 err = i40e_init_interrupt_scheme(pf);
10966 if (err)
10967 goto err_switch_setup;
41c445ff 10968
505682cd
MW		 10969 /* The number of VSIs reported by the FW is the minimum guaranteed
10970 * to us; HW supports far more and we share the remaining pool with
10971 * the other PFs. We allocate space for more than the guarantee with
10972 * the understanding that we might not get them all later.
41c445ff 10973 */
505682cd
MW		 10974 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10975 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10976 else
10977 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10978
10979 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
d17038d6
JB		 10980 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
10981 GFP_KERNEL);
ed87ac09
WY		 10982 if (!pf->vsi) {
10983 err = -ENOMEM;
41c445ff 10984 goto err_switch_setup;
ed87ac09 10985 }
41c445ff 10986
fa11cb3d
ASJ		 10987#ifdef CONFIG_PCI_IOV
10988 /* prep for VF support */
10989 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10990 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10991 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10992 if (pci_num_vf(pdev))
10993 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10994 }
10995#endif
bc7d338f 10996 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10997 if (err) {
10998 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10999 goto err_vsis;
11000 }
58fc3267
HZ		 11001
11002 /* Make sure flow control is set according to current settings */
11003 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
11004 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
11005 dev_dbg(&pf->pdev->dev,
11006 "Set fc with err %s aq_err %s on get_phy_cap\n",
11007 i40e_stat_str(hw, err),
11008 i40e_aq_str(hw, hw->aq.asq_last_status));
11009 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
11010 dev_dbg(&pf->pdev->dev,
11011 "Set fc with err %s aq_err %s on set_phy_config\n",
11012 i40e_stat_str(hw, err),
11013 i40e_aq_str(hw, hw->aq.asq_last_status));
11014 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
11015 dev_dbg(&pf->pdev->dev,
11016 "Set fc with err %s aq_err %s on get_link_info\n",
11017 i40e_stat_str(hw, err),
11018 i40e_aq_str(hw, hw->aq.asq_last_status));
11019
8a9eb7d3 11020 /* if FDIR VSI was set up, start it now */
505682cd 11021 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 11022 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
11023 i40e_vsi_open(pf->vsi[i]);
11024 break;
11025 }
11026 }
41c445ff 11027
2f0aff41
SN		 11028 /* The driver only wants link up/down and module qualification
11029 * reports from firmware. Note the negative logic.
7e2453fe
JB		 11030 */
11031 err = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 11032 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 11033 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 11034 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 11035 if (err)
f1c7e72e
SN		 11036 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
11037 i40e_stat_str(&pf->hw, err),
11038 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 11039
4f2f017c
ASJ		 11040 /* Reconfigure hardware for allowing smaller MSS in the case
11041 * of TSO, so that we avoid the MDD being fired and causing
11042 * a reset in the case of small MSS+TSO.
11043 */
11044 val = rd32(hw, I40E_REG_MSS);
11045 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
11046 val &= ~I40E_REG_MSS_MIN_MASK;
11047 val |= I40E_64BYTE_MSS;
11048 wr32(hw, I40E_REG_MSS, val);
11049 }
11050
8eed76fa 11051 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 11052 msleep(75);
11053 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
11054 if (err)
f1c7e72e
SN		 11055 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
11056 i40e_stat_str(&pf->hw, err),
11057 i40e_aq_str(&pf->hw,
11058 pf->hw.aq.asq_last_status));
cafa2ee6 11059 }
41c445ff
JB		 11060 /* The main driver is (mostly) up and happy. We need to set this state
11061 * before setting up the misc vector or we get a race and the vector
11062 * ends up disabled forever.
11063 */
11064 clear_bit(__I40E_DOWN, &pf->state);
11065
11066 /* In case of MSIX we are going to setup the misc vector right here
11067 * to handle admin queue events etc. In case of legacy and MSI
11068 * the misc functionality and queue processing is combined in
11069 * the same vector and that gets setup at open.
11070 */
11071 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
11072 err = i40e_setup_misc_vector(pf);
11073 if (err) {
11074 dev_info(&pdev->dev,
11075 "setup of misc vector failed: %d\n", err);
11076 goto err_vsis;
11077 }
11078 }
11079
df805f62 11080#ifdef CONFIG_PCI_IOV
41c445ff
JB		 11081 /* prep for VF support */
11082 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 11083 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11084 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 11085 /* disable link interrupts for VFs */
11086 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
11087 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
11088 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
11089 i40e_flush(hw);
4aeec010
MW		 11090
11091 if (pci_num_vf(pdev)) {
11092 dev_info(&pdev->dev,
11093 "Active VFs found, allocating resources.\n");
11094 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
11095 if (err)
11096 dev_info(&pdev->dev,
11097 "Error %d allocating resources for existing VFs\n",
11098 err);
11099 }
41c445ff 11100 }
df805f62 11101#endif /* CONFIG_PCI_IOV */
41c445ff 11102
e3219ce6
ASJ		 11103 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
11104 pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile,
11105 pf->num_iwarp_msix,
11106 I40E_IWARP_IRQ_PILE_ID);
11107 if (pf->iwarp_base_vector < 0) {
11108 dev_info(&pdev->dev,
11109 "failed to get tracking for %d vectors for IWARP err=%d\n",
11110 pf->num_iwarp_msix, pf->iwarp_base_vector);
11111 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
11112 }
11113 }
93cd765b 11114
41c445ff
JB		 11115 i40e_dbg_pf_init(pf);
11116
11117 /* tell the firmware that we're starting */
44033fac 11118 i40e_send_version(pf);
41c445ff
JB		 11119
11120 /* since everything's happy, start the service_task timer */
11121 mod_timer(&pf->service_timer,
11122 round_jiffies(jiffies + pf->service_timer_period));
11123
e3219ce6
ASJ		 11124 /* add this PF to client device list and launch a client service task */
11125 err = i40e_lan_add_device(pf);
11126 if (err)
11127 dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n",
11128 err);
11129
38e00438
VD		 11130#ifdef I40E_FCOE
11131 /* create FCoE interface */
11132 i40e_fcoe_vsi_setup(pf);
11133
11134#endif
3fced535
ASJ		 11135#define PCI_SPEED_SIZE 8
11136#define PCI_WIDTH_SIZE 8
11137 /* Devices on the IOSF bus do not have this information
11138 * and will report PCI Gen 1 x 1 by default so don't bother
11139 * checking them.
11140 */
11141 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
11142 char speed[PCI_SPEED_SIZE] = "Unknown";
11143 char width[PCI_WIDTH_SIZE] = "Unknown";
11144
11145 /* Get the negotiated link width and speed from PCI config
11146 * space
11147 */
11148 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
11149 &link_status);
11150
11151 i40e_set_pci_config_data(hw, link_status);
11152
11153 switch (hw->bus.speed) {
11154 case i40e_bus_speed_8000:
11155 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
11156 case i40e_bus_speed_5000:
11157 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
11158 case i40e_bus_speed_2500:
11159 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
11160 default:
11161 break;
11162 }
11163 switch (hw->bus.width) {
11164 case i40e_bus_width_pcie_x8:
11165 strncpy(width, "8", PCI_WIDTH_SIZE); break;
11166 case i40e_bus_width_pcie_x4:
11167 strncpy(width, "4", PCI_WIDTH_SIZE); break;
11168 case i40e_bus_width_pcie_x2:
11169 strncpy(width, "2", PCI_WIDTH_SIZE); break;
11170 case i40e_bus_width_pcie_x1:
11171 strncpy(width, "1", PCI_WIDTH_SIZE); break;
11172 default:
11173 break;
11174 }
11175
11176 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
11177 speed, width);
11178
11179 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
11180 hw->bus.speed < i40e_bus_speed_8000) {
11181 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
11182 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
11183 }
d4dfb81a
CS		 11184 }
11185
e827845c
CS		 11186 /* get the requested speeds from the fw */
11187 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
11188 if (err)
8279e495
NP		 11189 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
11190 i40e_stat_str(&pf->hw, err),
11191 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 11192 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
11193
fc72dbce
CS		 11194 /* get the supported phy types from the fw */
11195 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
11196 if (err)
11197 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
11198 i40e_stat_str(&pf->hw, err),
11199 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11200 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
11201
e7358f54
ASJ		 11202 /* Add a filter to drop all Flow control frames from any VSI from being
11203 * transmitted. By doing so we stop a malicious VF from sending out
11204 * PAUSE or PFC frames and potentially controlling traffic for other
11205 * PF/VF VSIs.
11206 * The FW can still send Flow control frames if enabled.
11207 */
11208 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11209 pf->main_vsi_seid);
11210
31b606d0
CW		 11211 if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
11212 (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
11213 pf->flags |= I40E_FLAG_HAVE_10GBASET_PHY;
11214
0c22b3dd
JB		 11215 /* print a string summarizing features */
11216 i40e_print_features(pf);
11217
41c445ff
JB		 11218 return 0;
11219
11220 /* Unwind what we've done if something failed in the setup */
11221err_vsis:
11222 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 11223 i40e_clear_interrupt_scheme(pf);
11224 kfree(pf->vsi);
04b03013
SN		 11225err_switch_setup:
11226 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 11227 del_timer_sync(&pf->service_timer);
11228err_mac_addr:
11229err_configure_lan_hmc:
11230 (void)i40e_shutdown_lan_hmc(hw);
11231err_init_lan_hmc:
11232 kfree(pf->qp_pile);
41c445ff
JB		 11233err_sw_init:
11234err_adminq_setup:
41c445ff
JB		 11235err_pf_reset:
11236 iounmap(hw->hw_addr);
11237err_ioremap:
11238 kfree(pf);
11239err_pf_alloc:
11240 pci_disable_pcie_error_reporting(pdev);
11241 pci_release_selected_regions(pdev,
11242 pci_select_bars(pdev, IORESOURCE_MEM));
11243err_pci_reg:
11244err_dma:
11245 pci_disable_device(pdev);
11246 return err;
11247}
11248
11249/**
11250 * i40e_remove - Device removal routine
11251 * @pdev: PCI device information struct
11252 *
11253 * i40e_remove is called by the PCI subsystem to alert the driver
11254 * that is should release a PCI device. This could be caused by a
11255 * Hot-Plug event, or because the driver is going to be removed from
11256 * memory.
11257 **/
11258static void i40e_remove(struct pci_dev *pdev)
11259{
11260 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11261 struct i40e_hw *hw = &pf->hw;
41c445ff 11262 i40e_status ret_code;
41c445ff
JB		 11263 int i;
11264
11265 i40e_dbg_pf_exit(pf);
11266
beb0dff1
JK		 11267 i40e_ptp_stop(pf);
11268
bcab2db9 11269 /* Disable RSS in hw */
272cdaf2
SN		 11270 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
11271 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
bcab2db9 11272
41c445ff 11273 /* no more scheduling of any task */
a4618ec8 11274 set_bit(__I40E_SUSPENDED, &pf->state);
41c445ff 11275 set_bit(__I40E_DOWN, &pf->state);
c99abb4c
SN		 11276 if (pf->service_timer.data)
11277 del_timer_sync(&pf->service_timer);
11278 if (pf->service_task.func)
11279 cancel_work_sync(&pf->service_task);
41c445ff 11280
eb2d80bc
MW		 11281 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11282 i40e_free_vfs(pf);
11283 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11284 }
11285
41c445ff
JB		 11286 i40e_fdir_teardown(pf);
11287
11288 /* If there is a switch structure or any orphans, remove them.
11289 * This will leave only the PF's VSI remaining.
11290 */
11291 for (i = 0; i < I40E_MAX_VEB; i++) {
11292 if (!pf->veb[i])
11293 continue;
11294
11295 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11296 pf->veb[i]->uplink_seid == 0)
11297 i40e_switch_branch_release(pf->veb[i]);
11298 }
11299
11300 /* Now we can shutdown the PF's VSI, just before we kill
11301 * adminq and hmc.
11302 */
11303 if (pf->vsi[pf->lan_vsi])
11304 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11305
e3219ce6
ASJ		 11306 /* remove attached clients */
11307 ret_code = i40e_lan_del_device(pf);
11308 if (ret_code) {
11309 dev_warn(&pdev->dev, "Failed to delete client device: %d\n",
11310 ret_code);
11311 }
11312
41c445ff 11313 /* shutdown and destroy the HMC */
f734dfff
JB		 11314 if (hw->hmc.hmc_obj) {
11315 ret_code = i40e_shutdown_lan_hmc(hw);
60442dea
SN		 11316 if (ret_code)
11317 dev_warn(&pdev->dev,
11318 "Failed to destroy the HMC resources: %d\n",
11319 ret_code);
11320 }
41c445ff
JB		 11321
11322 /* shutdown the adminq */
f734dfff 11323 ret_code = i40e_shutdown_adminq(hw);
41c445ff
JB		 11324 if (ret_code)
11325 dev_warn(&pdev->dev,
11326 "Failed to destroy the Admin Queue resources: %d\n",
11327 ret_code);
11328
8ddb3326
JB		 11329 /* destroy the locks only once, here */
11330 mutex_destroy(&hw->aq.arq_mutex);
11331 mutex_destroy(&hw->aq.asq_mutex);
11332
41c445ff
JB		 11333 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11334 i40e_clear_interrupt_scheme(pf);
505682cd 11335 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11336 if (pf->vsi[i]) {
11337 i40e_vsi_clear_rings(pf->vsi[i]);
11338 i40e_vsi_clear(pf->vsi[i]);
11339 pf->vsi[i] = NULL;
11340 }
11341 }
11342
11343 for (i = 0; i < I40E_MAX_VEB; i++) {
11344 kfree(pf->veb[i]);
11345 pf->veb[i] = NULL;
11346 }
11347
11348 kfree(pf->qp_pile);
41c445ff
JB		 11349 kfree(pf->vsi);
11350
f734dfff 11351 iounmap(hw->hw_addr);
41c445ff
JB		 11352 kfree(pf);
11353 pci_release_selected_regions(pdev,
11354 pci_select_bars(pdev, IORESOURCE_MEM));
11355
11356 pci_disable_pcie_error_reporting(pdev);
11357 pci_disable_device(pdev);
11358}
11359
11360/**
11361 * i40e_pci_error_detected - warning that something funky happened in PCI land
11362 * @pdev: PCI device information struct
11363 *
11364 * Called to warn that something happened and the error handling steps
11365 * are in progress. Allows the driver to quiesce things, be ready for
11366 * remediation.
11367 **/
11368static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11369 enum pci_channel_state error)
11370{
11371 struct i40e_pf *pf = pci_get_drvdata(pdev);
11372
11373 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11374
11375 /* shutdown all operations */
9007bccd
SN		 11376 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11377 rtnl_lock();
11378 i40e_prep_for_reset(pf);
11379 rtnl_unlock();
11380 }
41c445ff
JB		 11381
11382 /* Request a slot reset */
11383 return PCI_ERS_RESULT_NEED_RESET;
11384}
11385
11386/**
11387 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11388 * @pdev: PCI device information struct
11389 *
11390 * Called to find if the driver can work with the device now that
11391 * the pci slot has been reset. If a basic connection seems good
11392 * (registers are readable and have sane content) then return a
11393 * happy little PCI_ERS_RESULT_xxx.
11394 **/
11395static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11396{
11397 struct i40e_pf *pf = pci_get_drvdata(pdev);
11398 pci_ers_result_t result;
11399 int err;
11400 u32 reg;
11401
fb43201f 11402 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11403 if (pci_enable_device_mem(pdev)) {
11404 dev_info(&pdev->dev,
11405 "Cannot re-enable PCI device after reset.\n");
11406 result = PCI_ERS_RESULT_DISCONNECT;
11407 } else {
11408 pci_set_master(pdev);
11409 pci_restore_state(pdev);
11410 pci_save_state(pdev);
11411 pci_wake_from_d3(pdev, false);
11412
11413 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11414 if (reg == 0)
11415 result = PCI_ERS_RESULT_RECOVERED;
11416 else
11417 result = PCI_ERS_RESULT_DISCONNECT;
11418 }
11419
11420 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11421 if (err) {
11422 dev_info(&pdev->dev,
11423 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11424 err);
11425 /* non-fatal, continue */
11426 }
11427
11428 return result;
11429}
11430
11431/**
11432 * i40e_pci_error_resume - restart operations after PCI error recovery
11433 * @pdev: PCI device information struct
11434 *
11435 * Called to allow the driver to bring things back up after PCI error
11436 * and/or reset recovery has finished.
11437 **/
11438static void i40e_pci_error_resume(struct pci_dev *pdev)
11439{
11440 struct i40e_pf *pf = pci_get_drvdata(pdev);
11441
fb43201f 11442 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11443 if (test_bit(__I40E_SUSPENDED, &pf->state))
11444 return;
11445
11446 rtnl_lock();
41c445ff 11447 i40e_handle_reset_warning(pf);
4c4935a9 11448 rtnl_unlock();
9007bccd
SN		 11449}
11450
11451/**
11452 * i40e_shutdown - PCI callback for shutting down
11453 * @pdev: PCI device information struct
11454 **/
11455static void i40e_shutdown(struct pci_dev *pdev)
11456{
11457 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11458 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11459
11460 set_bit(__I40E_SUSPENDED, &pf->state);
11461 set_bit(__I40E_DOWN, &pf->state);
11462 rtnl_lock();
11463 i40e_prep_for_reset(pf);
11464 rtnl_unlock();
11465
8e2773ae
SN		 11466 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11467 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11468
02b42498
CS		 11469 del_timer_sync(&pf->service_timer);
11470 cancel_work_sync(&pf->service_task);
11471 i40e_fdir_teardown(pf);
11472
11473 rtnl_lock();
11474 i40e_prep_for_reset(pf);
11475 rtnl_unlock();
11476
11477 wr32(hw, I40E_PFPM_APM,
11478 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11479 wr32(hw, I40E_PFPM_WUFC,
11480 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11481
e147758d
SN		 11482 i40e_clear_interrupt_scheme(pf);
11483
9007bccd 11484 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11485 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11486 pci_set_power_state(pdev, PCI_D3hot);
11487 }
11488}
11489
11490#ifdef CONFIG_PM
11491/**
11492 * i40e_suspend - PCI callback for moving to D3
11493 * @pdev: PCI device information struct
11494 **/
11495static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11496{
11497 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11498 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11499
11500 set_bit(__I40E_SUSPENDED, &pf->state);
11501 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11502
9007bccd
SN		 11503 rtnl_lock();
11504 i40e_prep_for_reset(pf);
11505 rtnl_unlock();
11506
8e2773ae
SN		 11507 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11508 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11509
11510 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11511 pci_set_power_state(pdev, PCI_D3hot);
11512
11513 return 0;
41c445ff
JB		 11514}
11515
9007bccd
SN		 11516/**
11517 * i40e_resume - PCI callback for waking up from D3
11518 * @pdev: PCI device information struct
11519 **/
11520static int i40e_resume(struct pci_dev *pdev)
11521{
11522 struct i40e_pf *pf = pci_get_drvdata(pdev);
11523 u32 err;
11524
11525 pci_set_power_state(pdev, PCI_D0);
11526 pci_restore_state(pdev);
11527 /* pci_restore_state() clears dev->state_saves, so
11528 * call pci_save_state() again to restore it.
11529 */
11530 pci_save_state(pdev);
11531
11532 err = pci_enable_device_mem(pdev);
11533 if (err) {
fb43201f 11534 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11535 return err;
11536 }
11537 pci_set_master(pdev);
11538
11539 /* no wakeup events while running */
11540 pci_wake_from_d3(pdev, false);
11541
11542 /* handling the reset will rebuild the device state */
11543 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11544 clear_bit(__I40E_DOWN, &pf->state);
11545 rtnl_lock();
11546 i40e_reset_and_rebuild(pf, false);
11547 rtnl_unlock();
11548 }
11549
11550 return 0;
11551}
11552
11553#endif
41c445ff
JB		 11554static const struct pci_error_handlers i40e_err_handler = {
11555 .error_detected = i40e_pci_error_detected,
11556 .slot_reset = i40e_pci_error_slot_reset,
11557 .resume = i40e_pci_error_resume,
11558};
11559
11560static struct pci_driver i40e_driver = {
11561 .name = i40e_driver_name,
11562 .id_table = i40e_pci_tbl,
11563 .probe = i40e_probe,
11564 .remove = i40e_remove,
9007bccd
SN		 11565#ifdef CONFIG_PM
11566 .suspend = i40e_suspend,
11567 .resume = i40e_resume,
11568#endif
11569 .shutdown = i40e_shutdown,
41c445ff
JB		 11570 .err_handler = &i40e_err_handler,
11571 .sriov_configure = i40e_pci_sriov_configure,
11572};
11573
11574/**
11575 * i40e_init_module - Driver registration routine
11576 *
11577 * i40e_init_module is the first routine called when the driver is
11578 * loaded. All it does is register with the PCI subsystem.
11579 **/
11580static int __init i40e_init_module(void)
11581{
11582 pr_info("%s: %s - version %s\n", i40e_driver_name,
11583 i40e_driver_string, i40e_driver_version_str);
11584 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11585
2803b16c
JB		 11586 /* we will see if single thread per module is enough for now,
11587 * it can't be any worse than using the system workqueue which
11588 * was already single threaded
11589 */
11590 i40e_wq = create_singlethread_workqueue(i40e_driver_name);
11591 if (!i40e_wq) {
11592 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
11593 return -ENOMEM;
11594 }
11595
41c445ff
JB		 11596 i40e_dbg_init();
11597 return pci_register_driver(&i40e_driver);
11598}
11599module_init(i40e_init_module);
11600
11601/**
11602 * i40e_exit_module - Driver exit cleanup routine
11603 *
11604 * i40e_exit_module is called just before the driver is removed
11605 * from memory.
11606 **/
11607static void __exit i40e_exit_module(void)
11608{
11609 pci_unregister_driver(&i40e_driver);
2803b16c 11610 destroy_workqueue(i40e_wq);
41c445ff
JB		 11611 i40e_dbg_exit();
11612}
11613module_exit(i40e_exit_module);
Linux kernel - Deliverables
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