projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i40e: add functions to control default VSI
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
2818ccd9 4 * Copyright(c) 2013 - 2016 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
b499ffb0
SV		 27#include <linux/etherdevice.h>
28#include <linux/of_net.h>
29#include <linux/pci.h>
30
41c445ff
JB		 31/* Local includes */
32#include "i40e.h"
4eb3f768 33#include "i40e_diag.h"
06a5f7f1 34#include <net/udp_tunnel.h>
41c445ff
JB		 35
36const char i40e_driver_name[] = "i40e";
37static const char i40e_driver_string[] =
38 "Intel(R) Ethernet Connection XL710 Network Driver";
39
40#define DRV_KERN "-k"
41
e8e724db 42#define DRV_VERSION_MAJOR 1
50f26a50 43#define DRV_VERSION_MINOR 5
c74dff1a 44#define DRV_VERSION_BUILD 16
41c445ff
JB		 45#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
46 __stringify(DRV_VERSION_MINOR) "." \
47 __stringify(DRV_VERSION_BUILD) DRV_KERN
48const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 49static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 50
51/* a bit of forward declarations */
52static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
53static void i40e_handle_reset_warning(struct i40e_pf *pf);
54static int i40e_add_vsi(struct i40e_vsi *vsi);
55static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 56static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 57static int i40e_setup_misc_vector(struct i40e_pf *pf);
58static void i40e_determine_queue_usage(struct i40e_pf *pf);
59static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 60static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
61 u16 rss_table_size, u16 rss_size);
cbf61325 62static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 63static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 64
65/* i40e_pci_tbl - PCI Device ID Table
66 *
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
9baa3c34 72static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
ab60085e
SN		 75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
35dae51d
ASJ		 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
87e6c1d7
ASJ		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
d6bf58c2 88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},
a3aa5036 89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_I_X722), 0},
48a3b512
SN		 90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
91 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 92 /* required last entry */
93 {0, }
94};
95MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
96
97#define I40E_MAX_VF_COUNT 128
98static int debug = -1;
99module_param(debug, int, 0);
100MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
101
102MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
103MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
104MODULE_LICENSE("GPL");
105MODULE_VERSION(DRV_VERSION);
106
2803b16c
JB		 107static struct workqueue_struct *i40e_wq;
108
41c445ff
JB		 109/**
110 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
111 * @hw: pointer to the HW structure
112 * @mem: ptr to mem struct to fill out
113 * @size: size of memory requested
114 * @alignment: what to align the allocation to
115 **/
116int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
117 u64 size, u32 alignment)
118{
119 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
120
121 mem->size = ALIGN(size, alignment);
122 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
123 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 124 if (!mem->va)
125 return -ENOMEM;
41c445ff 126
93bc73b8 127 return 0;
41c445ff
JB		 128}
129
130/**
131 * i40e_free_dma_mem_d - OS specific memory free for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to free
134 **/
135int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
136{
137 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
138
139 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
140 mem->va = NULL;
141 mem->pa = 0;
142 mem->size = 0;
143
144 return 0;
145}
146
147/**
148 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
149 * @hw: pointer to the HW structure
150 * @mem: ptr to mem struct to fill out
151 * @size: size of memory requested
152 **/
153int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
154 u32 size)
155{
156 mem->size = size;
157 mem->va = kzalloc(size, GFP_KERNEL);
158
93bc73b8
JB		 159 if (!mem->va)
160 return -ENOMEM;
41c445ff 161
93bc73b8 162 return 0;
41c445ff
JB		 163}
164
165/**
166 * i40e_free_virt_mem_d - OS specific memory free for shared code
167 * @hw: pointer to the HW structure
168 * @mem: ptr to mem struct to free
169 **/
170int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
171{
172 /* it's ok to kfree a NULL pointer */
173 kfree(mem->va);
174 mem->va = NULL;
175 mem->size = 0;
176
177 return 0;
178}
179
180/**
181 * i40e_get_lump - find a lump of free generic resource
182 * @pf: board private structure
183 * @pile: the pile of resource to search
184 * @needed: the number of items needed
185 * @id: an owner id to stick on the items assigned
186 *
187 * Returns the base item index of the lump, or negative for error
188 *
189 * The search_hint trick and lack of advanced fit-finding only work
190 * because we're highly likely to have all the same size lump requests.
191 * Linear search time and any fragmentation should be minimal.
192 **/
193static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
194 u16 needed, u16 id)
195{
196 int ret = -ENOMEM;
ddf434ac 197 int i, j;
41c445ff
JB		 198
199 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
200 dev_info(&pf->pdev->dev,
201 "param err: pile=%p needed=%d id=0x%04x\n",
202 pile, needed, id);
203 return -EINVAL;
204 }
205
206 /* start the linear search with an imperfect hint */
207 i = pile->search_hint;
ddf434ac 208 while (i < pile->num_entries) {
41c445ff
JB		 209 /* skip already allocated entries */
210 if (pile->list[i] & I40E_PILE_VALID_BIT) {
211 i++;
212 continue;
213 }
214
215 /* do we have enough in this lump? */
216 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
217 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
218 break;
219 }
220
221 if (j == needed) {
222 /* there was enough, so assign it to the requestor */
223 for (j = 0; j < needed; j++)
224 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
225 ret = i;
226 pile->search_hint = i + j;
ddf434ac 227 break;
41c445ff 228 }
6995b36c
JB		 229
230 /* not enough, so skip over it and continue looking */
231 i += j;
41c445ff
JB		 232 }
233
234 return ret;
235}
236
237/**
238 * i40e_put_lump - return a lump of generic resource
239 * @pile: the pile of resource to search
240 * @index: the base item index
241 * @id: the owner id of the items assigned
242 *
243 * Returns the count of items in the lump
244 **/
245static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
246{
247 int valid_id = (id | I40E_PILE_VALID_BIT);
248 int count = 0;
249 int i;
250
251 if (!pile || index >= pile->num_entries)
252 return -EINVAL;
253
254 for (i = index;
255 i < pile->num_entries && pile->list[i] == valid_id;
256 i++) {
257 pile->list[i] = 0;
258 count++;
259 }
260
261 if (count && index < pile->search_hint)
262 pile->search_hint = index;
263
264 return count;
265}
266
fdf0e0bf
ASJ		 267/**
268 * i40e_find_vsi_from_id - searches for the vsi with the given id
269 * @pf - the pf structure to search for the vsi
270 * @id - id of the vsi it is searching for
271 **/
272struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
273{
274 int i;
275
276 for (i = 0; i < pf->num_alloc_vsi; i++)
277 if (pf->vsi[i] && (pf->vsi[i]->id == id))
278 return pf->vsi[i];
279
280 return NULL;
281}
282
41c445ff
JB		 283/**
284 * i40e_service_event_schedule - Schedule the service task to wake up
285 * @pf: board private structure
286 *
287 * If not already scheduled, this puts the task into the work queue
288 **/
e3219ce6 289void i40e_service_event_schedule(struct i40e_pf *pf)
41c445ff
JB		 290{
291 if (!test_bit(__I40E_DOWN, &pf->state) &&
292 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
293 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
2803b16c 294 queue_work(i40e_wq, &pf->service_task);
41c445ff
JB		 295}
296
297/**
298 * i40e_tx_timeout - Respond to a Tx Hang
299 * @netdev: network interface device structure
300 *
301 * If any port has noticed a Tx timeout, it is likely that the whole
302 * device is munged, not just the one netdev port, so go for the full
303 * reset.
304 **/
38e00438
VD		 305#ifdef I40E_FCOE
306void i40e_tx_timeout(struct net_device *netdev)
307#else
41c445ff 308static void i40e_tx_timeout(struct net_device *netdev)
38e00438 309#endif
41c445ff
JB		 310{
311 struct i40e_netdev_priv *np = netdev_priv(netdev);
312 struct i40e_vsi *vsi = np->vsi;
313 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 314 struct i40e_ring *tx_ring = NULL;
315 unsigned int i, hung_queue = 0;
316 u32 head, val;
41c445ff
JB		 317
318 pf->tx_timeout_count++;
319
b03a8c1f
KP		 320 /* find the stopped queue the same way the stack does */
321 for (i = 0; i < netdev->num_tx_queues; i++) {
322 struct netdev_queue *q;
323 unsigned long trans_start;
324
325 q = netdev_get_tx_queue(netdev, i);
9b36627a 326 trans_start = q->trans_start;
b03a8c1f
KP		 327 if (netif_xmit_stopped(q) &&
328 time_after(jiffies,
329 (trans_start + netdev->watchdog_timeo))) {
330 hung_queue = i;
331 break;
332 }
333 }
334
335 if (i == netdev->num_tx_queues) {
336 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
337 } else {
338 /* now that we have an index, find the tx_ring struct */
339 for (i = 0; i < vsi->num_queue_pairs; i++) {
340 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
341 if (hung_queue ==
342 vsi->tx_rings[i]->queue_index) {
343 tx_ring = vsi->tx_rings[i];
344 break;
345 }
346 }
347 }
348 }
349
41c445ff 350 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 351 pf->tx_timeout_recovery_level = 1; /* reset after some time */
352 else if (time_before(jiffies,
353 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
354 return; /* don't do any new action before the next timeout */
355
356 if (tx_ring) {
357 head = i40e_get_head(tx_ring);
358 /* Read interrupt register */
359 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
360 val = rd32(&pf->hw,
361 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
362 tx_ring->vsi->base_vector - 1));
363 else
364 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
365
366 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
367 vsi->seid, hung_queue, tx_ring->next_to_clean,
368 head, tx_ring->next_to_use,
369 readl(tx_ring->tail), val);
370 }
371
41c445ff 372 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 373 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
374 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 375
376 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 377 case 1:
378 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
379 break;
380 case 2:
381 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
382 break;
383 case 3:
384 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
385 break;
386 default:
387 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 388 break;
389 }
b03a8c1f 390
41c445ff
JB		 391 i40e_service_event_schedule(pf);
392 pf->tx_timeout_recovery_level++;
393}
394
41c445ff
JB		 395/**
396 * i40e_get_vsi_stats_struct - Get System Network Statistics
397 * @vsi: the VSI we care about
398 *
399 * Returns the address of the device statistics structure.
400 * The statistics are actually updated from the service task.
401 **/
402struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
403{
404 return &vsi->net_stats;
405}
406
407/**
408 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
409 * @netdev: network interface device structure
410 *
411 * Returns the address of the device statistics structure.
412 * The statistics are actually updated from the service task.
413 **/
38e00438
VD		 414#ifdef I40E_FCOE
415struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
416 struct net_device *netdev,
417 struct rtnl_link_stats64 *stats)
418#else
41c445ff
JB		 419static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
420 struct net_device *netdev,
980e9b11 421 struct rtnl_link_stats64 *stats)
38e00438 422#endif
41c445ff
JB		 423{
424 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 425 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 426 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 427 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
428 int i;
429
bc7d338f
ASJ		 430 if (test_bit(__I40E_DOWN, &vsi->state))
431 return stats;
432
3c325ced
JB		 433 if (!vsi->tx_rings)
434 return stats;
435
980e9b11
AD		 436 rcu_read_lock();
437 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 438 u64 bytes, packets;
439 unsigned int start;
440
441 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
442 if (!tx_ring)
443 continue;
444
445 do {
57a7744e 446 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 447 packets = tx_ring->stats.packets;
448 bytes = tx_ring->stats.bytes;
57a7744e 449 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 450
451 stats->tx_packets += packets;
452 stats->tx_bytes += bytes;
453 rx_ring = &tx_ring[1];
454
455 do {
57a7744e 456 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 457 packets = rx_ring->stats.packets;
458 bytes = rx_ring->stats.bytes;
57a7744e 459 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 460
980e9b11
AD		 461 stats->rx_packets += packets;
462 stats->rx_bytes += bytes;
463 }
464 rcu_read_unlock();
465
a5282f44 466 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 467 stats->multicast = vsi_stats->multicast;
468 stats->tx_errors = vsi_stats->tx_errors;
469 stats->tx_dropped = vsi_stats->tx_dropped;
470 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 471 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 472 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
473 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 474
980e9b11 475 return stats;
41c445ff
JB		 476}
477
478/**
479 * i40e_vsi_reset_stats - Resets all stats of the given vsi
480 * @vsi: the VSI to have its stats reset
481 **/
482void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
483{
484 struct rtnl_link_stats64 *ns;
485 int i;
486
487 if (!vsi)
488 return;
489
490 ns = i40e_get_vsi_stats_struct(vsi);
491 memset(ns, 0, sizeof(*ns));
492 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
493 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
494 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 495 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 496 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 497 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 498 sizeof(vsi->rx_rings[i]->stats));
6995b36c 499 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 500 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 501 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 502 sizeof(vsi->tx_rings[i]->stats));
503 memset(&vsi->tx_rings[i]->tx_stats, 0,
504 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 505 }
8e9dca53 506 }
41c445ff
JB		 507 vsi->stat_offsets_loaded = false;
508}
509
510/**
b40c82e6 511 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 512 * @pf: the PF to be reset
513 **/
514void i40e_pf_reset_stats(struct i40e_pf *pf)
515{
e91fdf76
SN		 516 int i;
517
41c445ff
JB		 518 memset(&pf->stats, 0, sizeof(pf->stats));
519 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
520 pf->stat_offsets_loaded = false;
e91fdf76
SN		 521
522 for (i = 0; i < I40E_MAX_VEB; i++) {
523 if (pf->veb[i]) {
524 memset(&pf->veb[i]->stats, 0,
525 sizeof(pf->veb[i]->stats));
526 memset(&pf->veb[i]->stats_offsets, 0,
527 sizeof(pf->veb[i]->stats_offsets));
528 pf->veb[i]->stat_offsets_loaded = false;
529 }
530 }
41c445ff
JB		 531}
532
533/**
534 * i40e_stat_update48 - read and update a 48 bit stat from the chip
535 * @hw: ptr to the hardware info
536 * @hireg: the high 32 bit reg to read
537 * @loreg: the low 32 bit reg to read
538 * @offset_loaded: has the initial offset been loaded yet
539 * @offset: ptr to current offset value
540 * @stat: ptr to the stat
541 *
542 * Since the device stats are not reset at PFReset, they likely will not
543 * be zeroed when the driver starts. We'll save the first values read
544 * and use them as offsets to be subtracted from the raw values in order
545 * to report stats that count from zero. In the process, we also manage
546 * the potential roll-over.
547 **/
548static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
549 bool offset_loaded, u64 *offset, u64 *stat)
550{
551 u64 new_data;
552
ab60085e 553 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 554 new_data = rd32(hw, loreg);
555 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
556 } else {
557 new_data = rd64(hw, loreg);
558 }
559 if (!offset_loaded)
560 *offset = new_data;
561 if (likely(new_data >= *offset))
562 *stat = new_data - *offset;
563 else
41a1d04b 564 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 565 *stat &= 0xFFFFFFFFFFFFULL;
566}
567
568/**
569 * i40e_stat_update32 - read and update a 32 bit stat from the chip
570 * @hw: ptr to the hardware info
571 * @reg: the hw reg to read
572 * @offset_loaded: has the initial offset been loaded yet
573 * @offset: ptr to current offset value
574 * @stat: ptr to the stat
575 **/
576static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
577 bool offset_loaded, u64 *offset, u64 *stat)
578{
579 u32 new_data;
580
581 new_data = rd32(hw, reg);
582 if (!offset_loaded)
583 *offset = new_data;
584 if (likely(new_data >= *offset))
585 *stat = (u32)(new_data - *offset);
586 else
41a1d04b 587 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 588}
589
590/**
591 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
592 * @vsi: the VSI to be updated
593 **/
594void i40e_update_eth_stats(struct i40e_vsi *vsi)
595{
596 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
597 struct i40e_pf *pf = vsi->back;
598 struct i40e_hw *hw = &pf->hw;
599 struct i40e_eth_stats *oes;
600 struct i40e_eth_stats *es; /* device's eth stats */
601
602 es = &vsi->eth_stats;
603 oes = &vsi->eth_stats_offsets;
604
605 /* Gather up the stats that the hw collects */
606 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
607 vsi->stat_offsets_loaded,
608 &oes->tx_errors, &es->tx_errors);
609 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
610 vsi->stat_offsets_loaded,
611 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 612 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
613 vsi->stat_offsets_loaded,
614 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
615 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
616 vsi->stat_offsets_loaded,
617 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 618
619 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
620 I40E_GLV_GORCL(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->rx_bytes, &es->rx_bytes);
623 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
624 I40E_GLV_UPRCL(stat_idx),
625 vsi->stat_offsets_loaded,
626 &oes->rx_unicast, &es->rx_unicast);
627 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
628 I40E_GLV_MPRCL(stat_idx),
629 vsi->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
632 I40E_GLV_BPRCL(stat_idx),
633 vsi->stat_offsets_loaded,
634 &oes->rx_broadcast, &es->rx_broadcast);
635
636 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
637 I40E_GLV_GOTCL(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->tx_bytes, &es->tx_bytes);
640 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
641 I40E_GLV_UPTCL(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->tx_unicast, &es->tx_unicast);
644 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
645 I40E_GLV_MPTCL(stat_idx),
646 vsi->stat_offsets_loaded,
647 &oes->tx_multicast, &es->tx_multicast);
648 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
649 I40E_GLV_BPTCL(stat_idx),
650 vsi->stat_offsets_loaded,
651 &oes->tx_broadcast, &es->tx_broadcast);
652 vsi->stat_offsets_loaded = true;
653}
654
655/**
656 * i40e_update_veb_stats - Update Switch component statistics
657 * @veb: the VEB being updated
658 **/
659static void i40e_update_veb_stats(struct i40e_veb *veb)
660{
661 struct i40e_pf *pf = veb->pf;
662 struct i40e_hw *hw = &pf->hw;
663 struct i40e_eth_stats *oes;
664 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 665 struct i40e_veb_tc_stats *veb_oes;
666 struct i40e_veb_tc_stats *veb_es;
667 int i, idx = 0;
41c445ff
JB		 668
669 idx = veb->stats_idx;
670 es = &veb->stats;
671 oes = &veb->stats_offsets;
fe860afb
NP		 672 veb_es = &veb->tc_stats;
673 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 674
675 /* Gather up the stats that the hw collects */
676 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
677 veb->stat_offsets_loaded,
678 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 679 if (hw->revision_id > 0)
680 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
681 veb->stat_offsets_loaded,
682 &oes->rx_unknown_protocol,
683 &es->rx_unknown_protocol);
41c445ff
JB		 684 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
685 veb->stat_offsets_loaded,
686 &oes->rx_bytes, &es->rx_bytes);
687 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
688 veb->stat_offsets_loaded,
689 &oes->rx_unicast, &es->rx_unicast);
690 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
691 veb->stat_offsets_loaded,
692 &oes->rx_multicast, &es->rx_multicast);
693 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
694 veb->stat_offsets_loaded,
695 &oes->rx_broadcast, &es->rx_broadcast);
696
697 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
698 veb->stat_offsets_loaded,
699 &oes->tx_bytes, &es->tx_bytes);
700 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
701 veb->stat_offsets_loaded,
702 &oes->tx_unicast, &es->tx_unicast);
703 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
704 veb->stat_offsets_loaded,
705 &oes->tx_multicast, &es->tx_multicast);
706 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 709 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
710 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
711 I40E_GLVEBTC_RPCL(i, idx),
712 veb->stat_offsets_loaded,
713 &veb_oes->tc_rx_packets[i],
714 &veb_es->tc_rx_packets[i]);
715 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
716 I40E_GLVEBTC_RBCL(i, idx),
717 veb->stat_offsets_loaded,
718 &veb_oes->tc_rx_bytes[i],
719 &veb_es->tc_rx_bytes[i]);
720 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
721 I40E_GLVEBTC_TPCL(i, idx),
722 veb->stat_offsets_loaded,
723 &veb_oes->tc_tx_packets[i],
724 &veb_es->tc_tx_packets[i]);
725 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
726 I40E_GLVEBTC_TBCL(i, idx),
727 veb->stat_offsets_loaded,
728 &veb_oes->tc_tx_bytes[i],
729 &veb_es->tc_tx_bytes[i]);
730 }
41c445ff
JB		 731 veb->stat_offsets_loaded = true;
732}
733
38e00438
VD		 734#ifdef I40E_FCOE
735/**
736 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
737 * @vsi: the VSI that is capable of doing FCoE
738 **/
739static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
740{
741 struct i40e_pf *pf = vsi->back;
742 struct i40e_hw *hw = &pf->hw;
743 struct i40e_fcoe_stats *ofs;
744 struct i40e_fcoe_stats *fs; /* device's eth stats */
745 int idx;
746
747 if (vsi->type != I40E_VSI_FCOE)
748 return;
749
4147e2c5 750 idx = hw->pf_id + I40E_FCOE_PF_STAT_OFFSET;
38e00438
VD		 751 fs = &vsi->fcoe_stats;
752 ofs = &vsi->fcoe_stats_offsets;
753
754 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
755 vsi->fcoe_stat_offsets_loaded,
756 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
757 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
758 vsi->fcoe_stat_offsets_loaded,
759 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
760 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
761 vsi->fcoe_stat_offsets_loaded,
762 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
763 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
764 vsi->fcoe_stat_offsets_loaded,
765 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
766 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
767 vsi->fcoe_stat_offsets_loaded,
768 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
769 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
770 vsi->fcoe_stat_offsets_loaded,
771 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
772 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
773 vsi->fcoe_stat_offsets_loaded,
774 &ofs->fcoe_last_error, &fs->fcoe_last_error);
775 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
778
779 vsi->fcoe_stat_offsets_loaded = true;
780}
781
782#endif
41c445ff 783/**
7812fddc 784 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 785 * @vsi: the VSI to be updated
786 *
787 * There are a few instances where we store the same stat in a
788 * couple of different structs. This is partly because we have
789 * the netdev stats that need to be filled out, which is slightly
790 * different from the "eth_stats" defined by the chip and used in
7812fddc 791 * VF communications. We sort it out here.
41c445ff 792 **/
7812fddc 793static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 794{
795 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 796 struct rtnl_link_stats64 *ons;
797 struct rtnl_link_stats64 *ns; /* netdev stats */
798 struct i40e_eth_stats *oes;
799 struct i40e_eth_stats *es; /* device's eth stats */
800 u32 tx_restart, tx_busy;
dd353109 801 u64 tx_lost_interrupt;
bf00b376 802 struct i40e_ring *p;
41c445ff 803 u32 rx_page, rx_buf;
bf00b376
AA		 804 u64 bytes, packets;
805 unsigned int start;
2fc3d715 806 u64 tx_linearize;
164c9f54 807 u64 tx_force_wb;
41c445ff
JB		 808 u64 rx_p, rx_b;
809 u64 tx_p, tx_b;
41c445ff
JB		 810 u16 q;
811
812 if (test_bit(__I40E_DOWN, &vsi->state) ||
813 test_bit(__I40E_CONFIG_BUSY, &pf->state))
814 return;
815
816 ns = i40e_get_vsi_stats_struct(vsi);
817 ons = &vsi->net_stats_offsets;
818 es = &vsi->eth_stats;
819 oes = &vsi->eth_stats_offsets;
820
821 /* Gather up the netdev and vsi stats that the driver collects
822 * on the fly during packet processing
823 */
824 rx_b = rx_p = 0;
825 tx_b = tx_p = 0;
164c9f54 826 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
dd353109 827 tx_lost_interrupt = 0;
41c445ff
JB		 828 rx_page = 0;
829 rx_buf = 0;
980e9b11 830 rcu_read_lock();
41c445ff 831 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 832 /* locate Tx ring */
833 p = ACCESS_ONCE(vsi->tx_rings[q]);
834
835 do {
57a7744e 836 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 837 packets = p->stats.packets;
838 bytes = p->stats.bytes;
57a7744e 839 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 840 tx_b += bytes;
841 tx_p += packets;
842 tx_restart += p->tx_stats.restart_queue;
843 tx_busy += p->tx_stats.tx_busy;
2fc3d715 844 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 845 tx_force_wb += p->tx_stats.tx_force_wb;
dd353109 846 tx_lost_interrupt += p->tx_stats.tx_lost_interrupt;
41c445ff 847
980e9b11
AD		 848 /* Rx queue is part of the same block as Tx queue */
849 p = &p[1];
850 do {
57a7744e 851 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 852 packets = p->stats.packets;
853 bytes = p->stats.bytes;
57a7744e 854 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 855 rx_b += bytes;
856 rx_p += packets;
420136cc
MW		 857 rx_buf += p->rx_stats.alloc_buff_failed;
858 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 859 }
980e9b11 860 rcu_read_unlock();
41c445ff
JB		 861 vsi->tx_restart = tx_restart;
862 vsi->tx_busy = tx_busy;
2fc3d715 863 vsi->tx_linearize = tx_linearize;
164c9f54 864 vsi->tx_force_wb = tx_force_wb;
dd353109 865 vsi->tx_lost_interrupt = tx_lost_interrupt;
41c445ff
JB		 866 vsi->rx_page_failed = rx_page;
867 vsi->rx_buf_failed = rx_buf;
868
869 ns->rx_packets = rx_p;
870 ns->rx_bytes = rx_b;
871 ns->tx_packets = tx_p;
872 ns->tx_bytes = tx_b;
873
41c445ff 874 /* update netdev stats from eth stats */
7812fddc 875 i40e_update_eth_stats(vsi);
41c445ff
JB		 876 ons->tx_errors = oes->tx_errors;
877 ns->tx_errors = es->tx_errors;
878 ons->multicast = oes->rx_multicast;
879 ns->multicast = es->rx_multicast;
41a9e55c
SN		 880 ons->rx_dropped = oes->rx_discards;
881 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 882 ons->tx_dropped = oes->tx_discards;
883 ns->tx_dropped = es->tx_discards;
884
7812fddc 885 /* pull in a couple PF stats if this is the main vsi */
41c445ff 886 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 887 ns->rx_crc_errors = pf->stats.crc_errors;
888 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
889 ns->rx_length_errors = pf->stats.rx_length_errors;
890 }
891}
41c445ff 892
7812fddc 893/**
b40c82e6 894 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 895 * @pf: the PF to be updated
896 **/
897static void i40e_update_pf_stats(struct i40e_pf *pf)
898{
899 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
900 struct i40e_hw_port_stats *nsd = &pf->stats;
901 struct i40e_hw *hw = &pf->hw;
902 u32 val;
903 int i;
41c445ff 904
7812fddc
SN		 905 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
906 I40E_GLPRT_GORCL(hw->port),
907 pf->stat_offsets_loaded,
908 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
909 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
910 I40E_GLPRT_GOTCL(hw->port),
911 pf->stat_offsets_loaded,
912 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
913 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
914 pf->stat_offsets_loaded,
915 &osd->eth.rx_discards,
916 &nsd->eth.rx_discards);
532d283d
SN		 917 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
918 I40E_GLPRT_UPRCL(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_unicast,
921 &nsd->eth.rx_unicast);
7812fddc
SN		 922 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
923 I40E_GLPRT_MPRCL(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_multicast,
926 &nsd->eth.rx_multicast);
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
928 I40E_GLPRT_BPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_broadcast,
931 &nsd->eth.rx_broadcast);
932 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
933 I40E_GLPRT_UPTCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.tx_unicast,
936 &nsd->eth.tx_unicast);
937 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
938 I40E_GLPRT_MPTCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.tx_multicast,
941 &nsd->eth.tx_multicast);
942 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
943 I40E_GLPRT_BPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_broadcast,
946 &nsd->eth.tx_broadcast);
41c445ff 947
7812fddc
SN		 948 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->tx_dropped_link_down,
951 &nsd->tx_dropped_link_down);
41c445ff 952
7812fddc
SN		 953 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->crc_errors, &nsd->crc_errors);
41c445ff 956
7812fddc
SN		 957 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 960
7812fddc
SN		 961 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->mac_local_faults,
964 &nsd->mac_local_faults);
965 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->mac_remote_faults,
968 &nsd->mac_remote_faults);
41c445ff 969
7812fddc
SN		 970 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_length_errors,
973 &nsd->rx_length_errors);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->link_xon_rx, &nsd->link_xon_rx);
978 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
979 pf->stat_offsets_loaded,
980 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 981 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
982 pf->stat_offsets_loaded,
983 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 984 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
985 pf->stat_offsets_loaded,
986 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 987
7812fddc 988 for (i = 0; i < 8; i++) {
95db239f
NP		 989 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
990 pf->stat_offsets_loaded,
991 &osd->priority_xoff_rx[i],
992 &nsd->priority_xoff_rx[i]);
7812fddc 993 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 994 pf->stat_offsets_loaded,
7812fddc
SN		 995 &osd->priority_xon_rx[i],
996 &nsd->priority_xon_rx[i]);
997 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_tx[i],
1000 &nsd->priority_xon_tx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xoff_tx[i],
1004 &nsd->priority_xoff_tx[i]);
1005 i40e_stat_update32(hw,
1006 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1007 pf->stat_offsets_loaded,
7812fddc
SN		 1008 &osd->priority_xon_2_xoff[i],
1009 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1010 }
1011
7812fddc
SN		 1012 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1013 I40E_GLPRT_PRC64L(hw->port),
1014 pf->stat_offsets_loaded,
1015 &osd->rx_size_64, &nsd->rx_size_64);
1016 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1017 I40E_GLPRT_PRC127L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_127, &nsd->rx_size_127);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1021 I40E_GLPRT_PRC255L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_255, &nsd->rx_size_255);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1025 I40E_GLPRT_PRC511L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_511, &nsd->rx_size_511);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1029 I40E_GLPRT_PRC1023L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_1023, &nsd->rx_size_1023);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1033 I40E_GLPRT_PRC1522L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1522, &nsd->rx_size_1522);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1037 I40E_GLPRT_PRC9522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_big, &nsd->rx_size_big);
1040
1041 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1042 I40E_GLPRT_PTC64L(hw->port),
1043 pf->stat_offsets_loaded,
1044 &osd->tx_size_64, &nsd->tx_size_64);
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1046 I40E_GLPRT_PTC127L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_127, &nsd->tx_size_127);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1050 I40E_GLPRT_PTC255L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_255, &nsd->tx_size_255);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1054 I40E_GLPRT_PTC511L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_511, &nsd->tx_size_511);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1058 I40E_GLPRT_PTC1023L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_1023, &nsd->tx_size_1023);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1062 I40E_GLPRT_PTC1522L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1522, &nsd->tx_size_1522);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1066 I40E_GLPRT_PTC9522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_big, &nsd->tx_size_big);
1069
1070 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->rx_undersize, &nsd->rx_undersize);
1073 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1074 pf->stat_offsets_loaded,
1075 &osd->rx_fragments, &nsd->rx_fragments);
1076 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1077 pf->stat_offsets_loaded,
1078 &osd->rx_oversize, &nsd->rx_oversize);
1079 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1080 pf->stat_offsets_loaded,
1081 &osd->rx_jabber, &nsd->rx_jabber);
1082
433c47de 1083 /* FDIR stats */
0bf4b1b0
ASJ		 1084 i40e_stat_update32(hw,
1085 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1086 pf->stat_offsets_loaded,
1087 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1088 i40e_stat_update32(hw,
1089 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1090 pf->stat_offsets_loaded,
1091 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1092 i40e_stat_update32(hw,
1093 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1094 pf->stat_offsets_loaded,
1095 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1096
7812fddc
SN		 1097 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1098 nsd->tx_lpi_status =
1099 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1100 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1101 nsd->rx_lpi_status =
1102 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1103 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1104 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1105 pf->stat_offsets_loaded,
1106 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1107 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1108 pf->stat_offsets_loaded,
1109 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1110
d0389e51
ASJ		 1111 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1112 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1113 nsd->fd_sb_status = true;
1114 else
1115 nsd->fd_sb_status = false;
1116
1117 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1118 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1119 nsd->fd_atr_status = true;
1120 else
1121 nsd->fd_atr_status = false;
1122
41c445ff
JB		 1123 pf->stat_offsets_loaded = true;
1124}
1125
7812fddc
SN		 1126/**
1127 * i40e_update_stats - Update the various statistics counters.
1128 * @vsi: the VSI to be updated
1129 *
1130 * Update the various stats for this VSI and its related entities.
1131 **/
1132void i40e_update_stats(struct i40e_vsi *vsi)
1133{
1134 struct i40e_pf *pf = vsi->back;
1135
1136 if (vsi == pf->vsi[pf->lan_vsi])
1137 i40e_update_pf_stats(pf);
1138
1139 i40e_update_vsi_stats(vsi);
38e00438
VD		 1140#ifdef I40E_FCOE
1141 i40e_update_fcoe_stats(vsi);
1142#endif
7812fddc
SN		 1143}
1144
41c445ff
JB		 1145/**
1146 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1147 * @vsi: the VSI to be searched
1148 * @macaddr: the MAC address
1149 * @vlan: the vlan
b40c82e6 1150 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1151 * @is_netdev: make sure its a netdev filter, else doesn't matter
1152 *
1153 * Returns ptr to the filter object or NULL
1154 **/
1155static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1156 u8 *macaddr, s16 vlan,
1157 bool is_vf, bool is_netdev)
1158{
1159 struct i40e_mac_filter *f;
1160
1161 if (!vsi || !macaddr)
1162 return NULL;
1163
1164 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1165 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1166 (vlan == f->vlan) &&
1167 (!is_vf || f->is_vf) &&
1168 (!is_netdev || f->is_netdev))
1169 return f;
1170 }
1171 return NULL;
1172}
1173
1174/**
1175 * i40e_find_mac - Find a mac addr in the macvlan filters list
1176 * @vsi: the VSI to be searched
1177 * @macaddr: the MAC address we are searching for
b40c82e6 1178 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1179 * @is_netdev: make sure its a netdev filter, else doesn't matter
1180 *
1181 * Returns the first filter with the provided MAC address or NULL if
1182 * MAC address was not found
1183 **/
1184struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1185 bool is_vf, bool is_netdev)
1186{
1187 struct i40e_mac_filter *f;
1188
1189 if (!vsi || !macaddr)
1190 return NULL;
1191
1192 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1193 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1194 (!is_vf || f->is_vf) &&
1195 (!is_netdev || f->is_netdev))
1196 return f;
1197 }
1198 return NULL;
1199}
1200
1201/**
1202 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1203 * @vsi: the VSI to be searched
1204 *
1205 * Returns true if VSI is in vlan mode or false otherwise
1206 **/
1207bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1208{
1209 struct i40e_mac_filter *f;
1210
1211 /* Only -1 for all the filters denotes not in vlan mode
1212 * so we have to go through all the list in order to make sure
1213 */
1214 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1215 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1216 return true;
1217 }
1218
1219 return false;
1220}
1221
1222/**
1223 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1224 * @vsi: the VSI to be searched
1225 * @macaddr: the mac address to be filtered
b40c82e6 1226 * @is_vf: true if it is a VF
41c445ff
JB		 1227 * @is_netdev: true if it is a netdev
1228 *
1229 * Goes through all the macvlan filters and adds a
1230 * macvlan filter for each unique vlan that already exists
1231 *
1232 * Returns first filter found on success, else NULL
1233 **/
1234struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1235 bool is_vf, bool is_netdev)
1236{
1237 struct i40e_mac_filter *f;
1238
1239 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1240 if (vsi->info.pvid)
1241 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1242 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1243 is_vf, is_netdev)) {
1244 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1245 is_vf, is_netdev))
41c445ff
JB		 1246 return NULL;
1247 }
1248 }
1249
1250 return list_first_entry_or_null(&vsi->mac_filter_list,
1251 struct i40e_mac_filter, list);
1252}
1253
b36e9ab5
MW		 1254/**
1255 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1256 * @vsi: the VSI to be searched
1257 * @macaddr: the mac address to be removed
1258 * @is_vf: true if it is a VF
1259 * @is_netdev: true if it is a netdev
1260 *
1261 * Removes a given MAC address from a VSI, regardless of VLAN
1262 *
1263 * Returns 0 for success, or error
1264 **/
1265int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1266 bool is_vf, bool is_netdev)
1267{
1268 struct i40e_mac_filter *f = NULL;
1269 int changed = 0;
1270
1271 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1272 "Missing mac_filter_list_lock\n");
1273 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1274 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1275 (is_vf == f->is_vf) &&
1276 (is_netdev == f->is_netdev)) {
1277 f->counter--;
1278 f->changed = true;
1279 changed = 1;
1280 }
1281 }
1282 if (changed) {
1283 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1284 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1285 return 0;
1286 }
1287 return -ENOENT;
1288}
1289
8c27d42e
GR		 1290/**
1291 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1292 * @vsi: the PF Main VSI - inappropriate for any other VSI
1293 * @macaddr: the MAC address
30650cc5
SN		 1294 *
1295 * Some older firmware configurations set up a default promiscuous VLAN
1296 * filter that needs to be removed.
8c27d42e 1297 **/
30650cc5 1298static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1299{
1300 struct i40e_aqc_remove_macvlan_element_data element;
1301 struct i40e_pf *pf = vsi->back;
f1c7e72e 1302 i40e_status ret;
8c27d42e
GR		 1303
1304 /* Only appropriate for the PF main VSI */
1305 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1306 return -EINVAL;
8c27d42e 1307
30650cc5 1308 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1309 ether_addr_copy(element.mac_addr, macaddr);
1310 element.vlan_tag = 0;
1311 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1312 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1313 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1314 if (ret)
30650cc5
SN		 1315 return -ENOENT;
1316
1317 return 0;
8c27d42e
GR		 1318}
1319
41c445ff
JB		 1320/**
1321 * i40e_add_filter - Add a mac/vlan filter to the VSI
1322 * @vsi: the VSI to be searched
1323 * @macaddr: the MAC address
1324 * @vlan: the vlan
b40c82e6 1325 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1326 * @is_netdev: make sure its a netdev filter, else doesn't matter
1327 *
1328 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1329 *
1330 * NOTE: This function is expected to be called with mac_filter_list_lock
1331 * being held.
41c445ff
JB		 1332 **/
1333struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1334 u8 *macaddr, s16 vlan,
1335 bool is_vf, bool is_netdev)
1336{
1337 struct i40e_mac_filter *f;
1338
1339 if (!vsi || !macaddr)
1340 return NULL;
1341
1342 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1343 if (!f) {
1344 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1345 if (!f)
1346 goto add_filter_out;
1347
9a173901 1348 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1349 f->vlan = vlan;
1350 f->changed = true;
1351
1352 INIT_LIST_HEAD(&f->list);
04d5a21d 1353 list_add_tail(&f->list, &vsi->mac_filter_list);
41c445ff
JB		 1354 }
1355
1356 /* increment counter and add a new flag if needed */
1357 if (is_vf) {
1358 if (!f->is_vf) {
1359 f->is_vf = true;
1360 f->counter++;
1361 }
1362 } else if (is_netdev) {
1363 if (!f->is_netdev) {
1364 f->is_netdev = true;
1365 f->counter++;
1366 }
1367 } else {
1368 f->counter++;
1369 }
1370
1371 /* changed tells sync_filters_subtask to
1372 * push the filter down to the firmware
1373 */
1374 if (f->changed) {
1375 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1376 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1377 }
1378
1379add_filter_out:
1380 return f;
1381}
1382
1383/**
1384 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1385 * @vsi: the VSI to be searched
1386 * @macaddr: the MAC address
1387 * @vlan: the vlan
b40c82e6 1388 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1389 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1390 *
1391 * NOTE: This function is expected to be called with mac_filter_list_lock
1392 * being held.
41c445ff
JB		 1393 **/
1394void i40e_del_filter(struct i40e_vsi *vsi,
1395 u8 *macaddr, s16 vlan,
1396 bool is_vf, bool is_netdev)
1397{
1398 struct i40e_mac_filter *f;
1399
1400 if (!vsi || !macaddr)
1401 return;
1402
1403 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1404 if (!f || f->counter == 0)
1405 return;
1406
1407 if (is_vf) {
1408 if (f->is_vf) {
1409 f->is_vf = false;
1410 f->counter--;
1411 }
1412 } else if (is_netdev) {
1413 if (f->is_netdev) {
1414 f->is_netdev = false;
1415 f->counter--;
1416 }
1417 } else {
b40c82e6 1418 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1419 int min_f = 0;
6995b36c 1420
41c445ff
JB		 1421 min_f += (f->is_vf ? 1 : 0);
1422 min_f += (f->is_netdev ? 1 : 0);
1423
1424 if (f->counter > min_f)
1425 f->counter--;
1426 }
1427
1428 /* counter == 0 tells sync_filters_subtask to
1429 * remove the filter from the firmware's list
1430 */
1431 if (f->counter == 0) {
1432 f->changed = true;
1433 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1434 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1435 }
1436}
1437
1438/**
1439 * i40e_set_mac - NDO callback to set mac address
1440 * @netdev: network interface device structure
1441 * @p: pointer to an address structure
1442 *
1443 * Returns 0 on success, negative on failure
1444 **/
38e00438
VD		 1445#ifdef I40E_FCOE
1446int i40e_set_mac(struct net_device *netdev, void *p)
1447#else
41c445ff 1448static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1449#endif
41c445ff
JB		 1450{
1451 struct i40e_netdev_priv *np = netdev_priv(netdev);
1452 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1453 struct i40e_pf *pf = vsi->back;
1454 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1455 struct sockaddr *addr = p;
1456 struct i40e_mac_filter *f;
1457
1458 if (!is_valid_ether_addr(addr->sa_data))
1459 return -EADDRNOTAVAIL;
1460
30650cc5
SN		 1461 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1462 netdev_info(netdev, "already using mac address %pM\n",
1463 addr->sa_data);
1464 return 0;
1465 }
41c445ff 1466
80f6428f
ASJ		 1467 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1468 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1469 return -EADDRNOTAVAIL;
1470
30650cc5
SN		 1471 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1472 netdev_info(netdev, "returning to hw mac address %pM\n",
1473 hw->mac.addr);
1474 else
1475 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1476
41c445ff
JB		 1477 if (vsi->type == I40E_VSI_MAIN) {
1478 i40e_status ret;
6995b36c 1479
41c445ff 1480 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1481 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1482 addr->sa_data, NULL);
1483 if (ret) {
1484 netdev_info(netdev,
1485 "Addr change for Main VSI failed: %d\n",
1486 ret);
1487 return -EADDRNOTAVAIL;
1488 }
41c445ff
JB		 1489 }
1490
30650cc5
SN		 1491 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1492 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1493
30650cc5
SN		 1494 memset(&element, 0, sizeof(element));
1495 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1496 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1497 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1498 } else {
21659035 1499 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1500 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1501 false, false);
21659035 1502 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1503 }
41c445ff 1504
30650cc5
SN		 1505 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1506 struct i40e_aqc_add_macvlan_element_data element;
1507
1508 memset(&element, 0, sizeof(element));
1509 ether_addr_copy(element.mac_addr, hw->mac.addr);
1510 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1511 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1512 } else {
21659035 1513 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1514 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1515 false, false);
1516 if (f)
1517 f->is_laa = true;
21659035 1518 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1519 }
1520
30650cc5 1521 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b 1522
c53934c6
JB		 1523 /* schedule our worker thread which will take care of
1524 * applying the new filter changes
1525 */
1526 i40e_service_event_schedule(vsi->back);
1527 return 0;
41c445ff
JB		 1528}
1529
1530/**
1531 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1532 * @vsi: the VSI being setup
1533 * @ctxt: VSI context structure
1534 * @enabled_tc: Enabled TCs bitmap
1535 * @is_add: True if called before Add VSI
1536 *
1537 * Setup VSI queue mapping for enabled traffic classes.
1538 **/
38e00438
VD		 1539#ifdef I40E_FCOE
1540void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1541 struct i40e_vsi_context *ctxt,
1542 u8 enabled_tc,
1543 bool is_add)
1544#else
41c445ff
JB		 1545static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1546 struct i40e_vsi_context *ctxt,
1547 u8 enabled_tc,
1548 bool is_add)
38e00438 1549#endif
41c445ff
JB		 1550{
1551 struct i40e_pf *pf = vsi->back;
1552 u16 sections = 0;
1553 u8 netdev_tc = 0;
1554 u16 numtc = 0;
1555 u16 qcount;
1556 u8 offset;
1557 u16 qmap;
1558 int i;
4e3b35b0 1559 u16 num_tc_qps = 0;
41c445ff
JB		 1560
1561 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1562 offset = 0;
1563
1564 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1565 /* Find numtc from enabled TC bitmap */
1566 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1567 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1568 numtc++;
1569 }
1570 if (!numtc) {
1571 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1572 numtc = 1;
1573 }
1574 } else {
1575 /* At least TC0 is enabled in case of non-DCB case */
1576 numtc = 1;
1577 }
1578
1579 vsi->tc_config.numtc = numtc;
1580 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1581 /* Number of queues per enabled TC */
7f9ff476
AS		 1582 /* In MFP case we can have a much lower count of MSIx
1583 * vectors available and so we need to lower the used
1584 * q count.
1585 */
26cdc443
ASJ		 1586 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1587 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1588 else
1589 qcount = vsi->alloc_queue_pairs;
7f9ff476 1590 num_tc_qps = qcount / numtc;
e25d00b8 1591 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1592
1593 /* Setup queue offset/count for all TCs for given VSI */
1594 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1595 /* See if the given TC is enabled for the given VSI */
75f5cea9 1596 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1597 /* TC is enabled */
41c445ff
JB		 1598 int pow, num_qps;
1599
41c445ff
JB		 1600 switch (vsi->type) {
1601 case I40E_VSI_MAIN:
acd65448
HZ		 1602 qcount = min_t(int, pf->alloc_rss_size,
1603 num_tc_qps);
41c445ff 1604 break;
38e00438
VD		 1605#ifdef I40E_FCOE
1606 case I40E_VSI_FCOE:
1607 qcount = num_tc_qps;
1608 break;
1609#endif
41c445ff
JB		 1610 case I40E_VSI_FDIR:
1611 case I40E_VSI_SRIOV:
1612 case I40E_VSI_VMDQ2:
1613 default:
4e3b35b0 1614 qcount = num_tc_qps;
41c445ff
JB		 1615 WARN_ON(i != 0);
1616 break;
1617 }
4e3b35b0
NP		 1618 vsi->tc_config.tc_info[i].qoffset = offset;
1619 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1620
1e200e4a 1621 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1622 num_qps = qcount;
41c445ff 1623 pow = 0;
41a1d04b 1624 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1625 pow++;
1626 num_qps >>= 1;
1627 }
1628
1629 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1630 qmap =
1631 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1632 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1633
4e3b35b0 1634 offset += qcount;
41c445ff
JB		 1635 } else {
1636 /* TC is not enabled so set the offset to
1637 * default queue and allocate one queue
1638 * for the given TC.
1639 */
1640 vsi->tc_config.tc_info[i].qoffset = 0;
1641 vsi->tc_config.tc_info[i].qcount = 1;
1642 vsi->tc_config.tc_info[i].netdev_tc = 0;
1643
1644 qmap = 0;
1645 }
1646 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1647 }
1648
1649 /* Set actual Tx/Rx queue pairs */
1650 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1651 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1652 if (vsi->req_queue_pairs > 0)
1653 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1654 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1655 vsi->num_queue_pairs = pf->num_lan_msix;
1656 }
41c445ff
JB		 1657
1658 /* Scheduler section valid can only be set for ADD VSI */
1659 if (is_add) {
1660 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1661
1662 ctxt->info.up_enable_bits = enabled_tc;
1663 }
1664 if (vsi->type == I40E_VSI_SRIOV) {
1665 ctxt->info.mapping_flags |=
1666 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1667 for (i = 0; i < vsi->num_queue_pairs; i++)
1668 ctxt->info.queue_mapping[i] =
1669 cpu_to_le16(vsi->base_queue + i);
1670 } else {
1671 ctxt->info.mapping_flags |=
1672 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1673 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1674 }
1675 ctxt->info.valid_sections |= cpu_to_le16(sections);
1676}
1677
1678/**
1679 * i40e_set_rx_mode - NDO callback to set the netdev filters
1680 * @netdev: network interface device structure
1681 **/
38e00438
VD		 1682#ifdef I40E_FCOE
1683void i40e_set_rx_mode(struct net_device *netdev)
1684#else
41c445ff 1685static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1686#endif
41c445ff
JB		 1687{
1688 struct i40e_netdev_priv *np = netdev_priv(netdev);
1689 struct i40e_mac_filter *f, *ftmp;
1690 struct i40e_vsi *vsi = np->vsi;
1691 struct netdev_hw_addr *uca;
1692 struct netdev_hw_addr *mca;
1693 struct netdev_hw_addr *ha;
1694
21659035
KP		 1695 spin_lock_bh(&vsi->mac_filter_list_lock);
1696
41c445ff
JB		 1697 /* add addr if not already in the filter list */
1698 netdev_for_each_uc_addr(uca, netdev) {
1699 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1700 if (i40e_is_vsi_in_vlan(vsi))
1701 i40e_put_mac_in_vlan(vsi, uca->addr,
1702 false, true);
1703 else
1704 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1705 false, true);
1706 }
1707 }
1708
1709 netdev_for_each_mc_addr(mca, netdev) {
1710 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1711 if (i40e_is_vsi_in_vlan(vsi))
1712 i40e_put_mac_in_vlan(vsi, mca->addr,
1713 false, true);
1714 else
1715 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1716 false, true);
1717 }
1718 }
1719
1720 /* remove filter if not in netdev list */
1721 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1722
1723 if (!f->is_netdev)
1724 continue;
1725
2f41f335
SN		 1726 netdev_for_each_mc_addr(mca, netdev)
1727 if (ether_addr_equal(mca->addr, f->macaddr))
1728 goto bottom_of_search_loop;
41c445ff 1729
2f41f335
SN		 1730 netdev_for_each_uc_addr(uca, netdev)
1731 if (ether_addr_equal(uca->addr, f->macaddr))
1732 goto bottom_of_search_loop;
1733
1734 for_each_dev_addr(netdev, ha)
1735 if (ether_addr_equal(ha->addr, f->macaddr))
1736 goto bottom_of_search_loop;
1737
1738 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1739 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1740
1741bottom_of_search_loop:
1742 continue;
41c445ff 1743 }
21659035 1744 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1745
1746 /* check for other flag changes */
1747 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1748 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1749 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1750 }
c53934c6
JB		 1751
1752 /* schedule our worker thread which will take care of
1753 * applying the new filter changes
1754 */
1755 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1756}
1757
21659035
KP		 1758/**
1759 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1760 * @src: source MAC filter entry to be clones
1761 *
1762 * Returns the pointer to newly cloned MAC filter entry or NULL
1763 * in case of error
1764 **/
1765static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1766 struct i40e_mac_filter *src)
1767{
1768 struct i40e_mac_filter *f;
1769
1770 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1771 if (!f)
1772 return NULL;
1773 *f = *src;
1774
1775 INIT_LIST_HEAD(&f->list);
1776
1777 return f;
1778}
1779
1780/**
1781 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1782 * @vsi: pointer to vsi struct
1783 * @from: Pointer to list which contains MAC filter entries - changes to
1784 * those entries needs to be undone.
1785 *
1786 * MAC filter entries from list were slated to be removed from device.
1787 **/
1788static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1789 struct list_head *from)
1790{
1791 struct i40e_mac_filter *f, *ftmp;
1792
1793 list_for_each_entry_safe(f, ftmp, from, list) {
1794 f->changed = true;
1795 /* Move the element back into MAC filter list*/
1796 list_move_tail(&f->list, &vsi->mac_filter_list);
1797 }
1798}
1799
1800/**
1801 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1802 * @vsi: pointer to vsi struct
1803 *
1804 * MAC filter entries from list were slated to be added from device.
1805 **/
1806static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1807{
1808 struct i40e_mac_filter *f, *ftmp;
1809
1810 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1811 if (!f->changed && f->counter)
1812 f->changed = true;
1813 }
1814}
1815
1816/**
1817 * i40e_cleanup_add_list - Deletes the element from add list and release
1818 * memory
1819 * @add_list: Pointer to list which contains MAC filter entries
1820 **/
1821static void i40e_cleanup_add_list(struct list_head *add_list)
1822{
1823 struct i40e_mac_filter *f, *ftmp;
1824
1825 list_for_each_entry_safe(f, ftmp, add_list, list) {
1826 list_del(&f->list);
1827 kfree(f);
1828 }
1829}
1830
41c445ff
JB		 1831/**
1832 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1833 * @vsi: ptr to the VSI
1834 *
1835 * Push any outstanding VSI filter changes through the AdminQ.
1836 *
1837 * Returns 0 or error value
1838 **/
17652c63 1839int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1840{
21659035
KP		 1841 struct list_head tmp_del_list, tmp_add_list;
1842 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1843 bool promisc_forced_on = false;
1844 bool add_happened = false;
1845 int filter_list_len = 0;
1846 u32 changed_flags = 0;
ea02e90b 1847 i40e_status aq_ret = 0;
21659035 1848 bool err_cond = false;
ea02e90b 1849 int retval = 0;
41c445ff
JB		 1850 struct i40e_pf *pf;
1851 int num_add = 0;
1852 int num_del = 0;
f1c7e72e 1853 int aq_err = 0;
41c445ff
JB		 1854 u16 cmd_flags;
1855
1856 /* empty array typed pointers, kcalloc later */
1857 struct i40e_aqc_add_macvlan_element_data *add_list;
1858 struct i40e_aqc_remove_macvlan_element_data *del_list;
1859
1860 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1861 usleep_range(1000, 2000);
1862 pf = vsi->back;
1863
1864 if (vsi->netdev) {
1865 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1866 vsi->current_netdev_flags = vsi->netdev->flags;
1867 }
1868
21659035
KP		 1869 INIT_LIST_HEAD(&tmp_del_list);
1870 INIT_LIST_HEAD(&tmp_add_list);
1871
41c445ff
JB		 1872 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1873 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1874
21659035 1875 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1876 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1877 if (!f->changed)
1878 continue;
1879
1880 if (f->counter != 0)
1881 continue;
1882 f->changed = false;
21659035
KP		 1883
1884 /* Move the element into temporary del_list */
1885 list_move_tail(&f->list, &tmp_del_list);
1886 }
1887
1888 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1889 if (!f->changed)
1890 continue;
1891
1892 if (f->counter == 0)
1893 continue;
1894 f->changed = false;
1895
1896 /* Clone MAC filter entry and add into temporary list */
1897 fclone = i40e_mac_filter_entry_clone(f);
1898 if (!fclone) {
1899 err_cond = true;
1900 break;
1901 }
1902 list_add_tail(&fclone->list, &tmp_add_list);
1903 }
1904
1905 /* if failed to clone MAC filter entry - undo */
1906 if (err_cond) {
1907 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1908 i40e_undo_add_filter_entries(vsi);
1909 }
1910 spin_unlock_bh(&vsi->mac_filter_list_lock);
1911
ea02e90b 1912 if (err_cond) {
21659035 1913 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1914 retval = -ENOMEM;
1915 goto out;
1916 }
21659035
KP		 1917 }
1918
1919 /* Now process 'del_list' outside the lock */
1920 if (!list_empty(&tmp_del_list)) {
f1199998
SN		 1921 int del_list_size;
1922
21659035
KP		 1923 filter_list_len = pf->hw.aq.asq_buf_size /
1924 sizeof(struct i40e_aqc_remove_macvlan_element_data);
f1199998
SN		 1925 del_list_size = filter_list_len *
1926 sizeof(struct i40e_aqc_remove_macvlan_element_data);
38c3cec7 1927 del_list = kzalloc(del_list_size, GFP_ATOMIC);
21659035
KP		 1928 if (!del_list) {
1929 i40e_cleanup_add_list(&tmp_add_list);
1930
1931 /* Undo VSI's MAC filter entry element updates */
1932 spin_lock_bh(&vsi->mac_filter_list_lock);
1933 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1934 i40e_undo_add_filter_entries(vsi);
1935 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1936 retval = -ENOMEM;
1937 goto out;
21659035
KP		 1938 }
1939
1940 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1941 cmd_flags = 0;
1942
1943 /* add to delete list */
9a173901 1944 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1945 del_list[num_del].vlan_tag =
1946 cpu_to_le16((u16)(f->vlan ==
1947 I40E_VLAN_ANY ? 0 : f->vlan));
1948
41c445ff
JB		 1949 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1950 del_list[num_del].flags = cmd_flags;
1951 num_del++;
1952
41c445ff
JB		 1953 /* flush a full buffer */
1954 if (num_del == filter_list_len) {
ea02e90b
MW		 1955 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1956 vsi->seid,
1957 del_list,
1958 num_del,
1959 NULL);
f1c7e72e 1960 aq_err = pf->hw.aq.asq_last_status;
41c445ff 1961 num_del = 0;
f1199998 1962 memset(del_list, 0, del_list_size);
41c445ff 1963
ea02e90b
MW		 1964 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1965 retval = -EIO;
21659035
KP		 1966 dev_err(&pf->pdev->dev,
1967 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
ea02e90b 1968 i40e_stat_str(&pf->hw, aq_ret),
21659035 1969 i40e_aq_str(&pf->hw, aq_err));
ea02e90b 1970 }
41c445ff 1971 }
21659035
KP		 1972 /* Release memory for MAC filter entries which were
1973 * synced up with HW.
1974 */
1975 list_del(&f->list);
1976 kfree(f);
41c445ff 1977 }
21659035 1978
41c445ff 1979 if (num_del) {
ea02e90b
MW		 1980 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
1981 del_list, num_del,
1982 NULL);
f1c7e72e 1983 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1984 num_del = 0;
1985
ea02e90b 1986 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1987 dev_info(&pf->pdev->dev,
f1c7e72e 1988 "ignoring delete macvlan error, err %s aq_err %s\n",
ea02e90b 1989 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 1990 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1991 }
1992
1993 kfree(del_list);
1994 del_list = NULL;
21659035
KP		 1995 }
1996
1997 if (!list_empty(&tmp_add_list)) {
f1199998 1998 int add_list_size;
41c445ff
JB		 1999
2000 /* do all the adds now */
2001 filter_list_len = pf->hw.aq.asq_buf_size /
2002 sizeof(struct i40e_aqc_add_macvlan_element_data),
f1199998
SN		 2003 add_list_size = filter_list_len *
2004 sizeof(struct i40e_aqc_add_macvlan_element_data);
38c3cec7 2005 add_list = kzalloc(add_list_size, GFP_ATOMIC);
21659035
KP		 2006 if (!add_list) {
2007 /* Purge element from temporary lists */
2008 i40e_cleanup_add_list(&tmp_add_list);
2009
2010 /* Undo add filter entries from VSI MAC filter list */
2011 spin_lock_bh(&vsi->mac_filter_list_lock);
2012 i40e_undo_add_filter_entries(vsi);
2013 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2014 retval = -ENOMEM;
2015 goto out;
21659035 2016 }
41c445ff 2017
21659035 2018 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2019
41c445ff
JB		 2020 add_happened = true;
2021 cmd_flags = 0;
2022
2023 /* add to add array */
9a173901 2024 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2025 add_list[num_add].vlan_tag =
2026 cpu_to_le16(
2027 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2028 add_list[num_add].queue_number = 0;
2029
2030 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2031 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2032 num_add++;
2033
2034 /* flush a full buffer */
2035 if (num_add == filter_list_len) {
ea02e90b
MW		 2036 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2037 add_list, num_add,
2038 NULL);
f1c7e72e 2039 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2040 num_add = 0;
2041
ea02e90b 2042 if (aq_ret)
41c445ff 2043 break;
f1199998 2044 memset(add_list, 0, add_list_size);
41c445ff 2045 }
21659035
KP		 2046 /* Entries from tmp_add_list were cloned from MAC
2047 * filter list, hence clean those cloned entries
2048 */
2049 list_del(&f->list);
2050 kfree(f);
41c445ff 2051 }
21659035 2052
41c445ff 2053 if (num_add) {
ea02e90b
MW		 2054 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2055 add_list, num_add, NULL);
f1c7e72e 2056 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2057 num_add = 0;
2058 }
2059 kfree(add_list);
2060 add_list = NULL;
2061
ea02e90b
MW		 2062 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2063 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2064 dev_info(&pf->pdev->dev,
f1c7e72e 2065 "add filter failed, err %s aq_err %s\n",
ea02e90b 2066 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2067 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2068 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2069 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2070 &vsi->state)) {
2071 promisc_forced_on = true;
2072 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2073 &vsi->state);
2074 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2075 }
2076 }
2077 }
2078
a856b5cb
ASJ		 2079 /* if the VF is not trusted do not do promisc */
2080 if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) {
2081 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state);
2082 goto out;
2083 }
2084
41c445ff
JB		 2085 /* check for changes in promiscuous modes */
2086 if (changed_flags & IFF_ALLMULTI) {
2087 bool cur_multipromisc;
6995b36c 2088
41c445ff 2089 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2090 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2091 vsi->seid,
2092 cur_multipromisc,
2093 NULL);
2094 if (aq_ret) {
2095 retval = i40e_aq_rc_to_posix(aq_ret,
2096 pf->hw.aq.asq_last_status);
41c445ff 2097 dev_info(&pf->pdev->dev,
f1c7e72e 2098 "set multi promisc failed, err %s aq_err %s\n",
ea02e90b 2099 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2100 i40e_aq_str(&pf->hw,
2101 pf->hw.aq.asq_last_status));
ea02e90b 2102 }
41c445ff
JB		 2103 }
2104 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2105 bool cur_promisc;
6995b36c 2106
41c445ff
JB		 2107 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2108 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2109 &vsi->state));
6784ed5a
ASJ		 2110 if ((vsi->type == I40E_VSI_MAIN) &&
2111 (pf->lan_veb != I40E_NO_VEB) &&
2112 !(pf->flags & I40E_FLAG_MFP_ENABLED)) {
92faef85
ASJ		 2113 /* set defport ON for Main VSI instead of true promisc
2114 * this way we will get all unicast/multicast and VLAN
2115 * promisc behavior but will not get VF or VMDq traffic
2116 * replicated on the Main VSI.
2117 */
2118 if (pf->cur_promisc != cur_promisc) {
2119 pf->cur_promisc = cur_promisc;
0e4425ed 2120 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2121 }
2122 } else {
ea02e90b 2123 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
92faef85 2124 &vsi->back->hw,
f1c7e72e 2125 vsi->seid,
b5569892
ASJ		 2126 cur_promisc, NULL,
2127 true);
ea02e90b
MW		 2128 if (aq_ret) {
2129 retval =
2130 i40e_aq_rc_to_posix(aq_ret,
2131 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2132 dev_info(&pf->pdev->dev,
2133 "set unicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2134 aq_ret, pf->hw.aq.asq_last_status);
2135 }
2136 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
92faef85
ASJ		 2137 &vsi->back->hw,
2138 vsi->seid,
2139 cur_promisc, NULL);
ea02e90b
MW		 2140 if (aq_ret) {
2141 retval =
2142 i40e_aq_rc_to_posix(aq_ret,
2143 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2144 dev_info(&pf->pdev->dev,
2145 "set multicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2146 aq_ret, pf->hw.aq.asq_last_status);
2147 }
92faef85 2148 }
ea02e90b
MW		 2149 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2150 vsi->seid,
2151 cur_promisc, NULL);
2152 if (aq_ret) {
2153 retval = i40e_aq_rc_to_posix(aq_ret,
2154 pf->hw.aq.asq_last_status);
1a10370a 2155 dev_info(&pf->pdev->dev,
f1c7e72e 2156 "set brdcast promisc failed, err %s, aq_err %s\n",
ea02e90b 2157 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2158 i40e_aq_str(&pf->hw,
2159 pf->hw.aq.asq_last_status));
ea02e90b 2160 }
41c445ff 2161 }
ea02e90b 2162out:
2818ccd9
JB		 2163 /* if something went wrong then set the changed flag so we try again */
2164 if (retval)
2165 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2166
41c445ff 2167 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2168 return retval;
41c445ff
JB		 2169}
2170
2171/**
2172 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2173 * @pf: board private structure
2174 **/
2175static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2176{
2177 int v;
2178
2179 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2180 return;
2181 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2182
505682cd 2183 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2184 if (pf->vsi[v] &&
17652c63
JB		 2185 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2186 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2187
2188 if (ret) {
2189 /* come back and try again later */
2190 pf->flags |= I40E_FLAG_FILTER_SYNC;
2191 break;
2192 }
2193 }
41c445ff
JB		 2194 }
2195}
2196
2197/**
2198 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2199 * @netdev: network interface device structure
2200 * @new_mtu: new value for maximum frame size
2201 *
2202 * Returns 0 on success, negative on failure
2203 **/
2204static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2205{
2206 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2207 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2208 struct i40e_vsi *vsi = np->vsi;
2209
2210 /* MTU < 68 is an error and causes problems on some kernels */
2211 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2212 return -EINVAL;
2213
2214 netdev_info(netdev, "changing MTU from %d to %d\n",
2215 netdev->mtu, new_mtu);
2216 netdev->mtu = new_mtu;
2217 if (netif_running(netdev))
2218 i40e_vsi_reinit_locked(vsi);
e3219ce6 2219 i40e_notify_client_of_l2_param_changes(vsi);
41c445ff
JB		 2220 return 0;
2221}
2222
beb0dff1
JK		 2223/**
2224 * i40e_ioctl - Access the hwtstamp interface
2225 * @netdev: network interface device structure
2226 * @ifr: interface request data
2227 * @cmd: ioctl command
2228 **/
2229int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2230{
2231 struct i40e_netdev_priv *np = netdev_priv(netdev);
2232 struct i40e_pf *pf = np->vsi->back;
2233
2234 switch (cmd) {
2235 case SIOCGHWTSTAMP:
2236 return i40e_ptp_get_ts_config(pf, ifr);
2237 case SIOCSHWTSTAMP:
2238 return i40e_ptp_set_ts_config(pf, ifr);
2239 default:
2240 return -EOPNOTSUPP;
2241 }
2242}
2243
41c445ff
JB		 2244/**
2245 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2246 * @vsi: the vsi being adjusted
2247 **/
2248void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2249{
2250 struct i40e_vsi_context ctxt;
2251 i40e_status ret;
2252
2253 if ((vsi->info.valid_sections &
2254 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2255 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2256 return; /* already enabled */
2257
2258 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2259 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2260 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2261
2262 ctxt.seid = vsi->seid;
1a2f6248 2263 ctxt.info = vsi->info;
41c445ff
JB		 2264 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2265 if (ret) {
2266 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2267 "update vlan stripping failed, err %s aq_err %s\n",
2268 i40e_stat_str(&vsi->back->hw, ret),
2269 i40e_aq_str(&vsi->back->hw,
2270 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2271 }
2272}
2273
2274/**
2275 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2276 * @vsi: the vsi being adjusted
2277 **/
2278void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2279{
2280 struct i40e_vsi_context ctxt;
2281 i40e_status ret;
2282
2283 if ((vsi->info.valid_sections &
2284 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2285 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2286 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2287 return; /* already disabled */
2288
2289 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2290 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2291 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2292
2293 ctxt.seid = vsi->seid;
1a2f6248 2294 ctxt.info = vsi->info;
41c445ff
JB		 2295 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2296 if (ret) {
2297 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2298 "update vlan stripping failed, err %s aq_err %s\n",
2299 i40e_stat_str(&vsi->back->hw, ret),
2300 i40e_aq_str(&vsi->back->hw,
2301 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2302 }
2303}
2304
2305/**
2306 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2307 * @netdev: network interface to be adjusted
2308 * @features: netdev features to test if VLAN offload is enabled or not
2309 **/
2310static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2311{
2312 struct i40e_netdev_priv *np = netdev_priv(netdev);
2313 struct i40e_vsi *vsi = np->vsi;
2314
2315 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2316 i40e_vlan_stripping_enable(vsi);
2317 else
2318 i40e_vlan_stripping_disable(vsi);
2319}
2320
2321/**
2322 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2323 * @vsi: the vsi being configured
2324 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2325 **/
2326int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2327{
2328 struct i40e_mac_filter *f, *add_f;
2329 bool is_netdev, is_vf;
41c445ff
JB		 2330
2331 is_vf = (vsi->type == I40E_VSI_SRIOV);
2332 is_netdev = !!(vsi->netdev);
2333
21659035
KP		 2334 /* Locked once because all functions invoked below iterates list*/
2335 spin_lock_bh(&vsi->mac_filter_list_lock);
2336
41c445ff
JB		 2337 if (is_netdev) {
2338 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2339 is_vf, is_netdev);
2340 if (!add_f) {
2341 dev_info(&vsi->back->pdev->dev,
2342 "Could not add vlan filter %d for %pM\n",
2343 vid, vsi->netdev->dev_addr);
21659035 2344 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2345 return -ENOMEM;
2346 }
2347 }
2348
2349 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2350 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2351 if (!add_f) {
2352 dev_info(&vsi->back->pdev->dev,
2353 "Could not add vlan filter %d for %pM\n",
2354 vid, f->macaddr);
21659035 2355 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2356 return -ENOMEM;
2357 }
2358 }
2359
41c445ff
JB		 2360 /* Now if we add a vlan tag, make sure to check if it is the first
2361 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2362 * with 0, so we now accept untagged and specified tagged traffic
2363 * (and not any taged and untagged)
2364 */
2365 if (vid > 0) {
2366 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2367 I40E_VLAN_ANY,
2368 is_vf, is_netdev)) {
2369 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2370 I40E_VLAN_ANY, is_vf, is_netdev);
2371 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2372 is_vf, is_netdev);
2373 if (!add_f) {
2374 dev_info(&vsi->back->pdev->dev,
2375 "Could not add filter 0 for %pM\n",
2376 vsi->netdev->dev_addr);
21659035 2377 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2378 return -ENOMEM;
2379 }
2380 }
8d82a7c5 2381 }
41c445ff 2382
8d82a7c5
GR		 2383 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2384 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2385 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2386 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2387 is_vf, is_netdev))
2388 continue;
2389 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2390 is_vf, is_netdev);
2391 add_f = i40e_add_filter(vsi, f->macaddr,
2392 0, is_vf, is_netdev);
2393 if (!add_f) {
2394 dev_info(&vsi->back->pdev->dev,
2395 "Could not add filter 0 for %pM\n",
2396 f->macaddr);
2397 spin_unlock_bh(&vsi->mac_filter_list_lock);
2398 return -ENOMEM;
41c445ff
JB		 2399 }
2400 }
41c445ff
JB		 2401 }
2402
21659035
KP		 2403 spin_unlock_bh(&vsi->mac_filter_list_lock);
2404
0e4425ed
JB		 2405 /* schedule our worker thread which will take care of
2406 * applying the new filter changes
2407 */
2408 i40e_service_event_schedule(vsi->back);
2409 return 0;
41c445ff
JB		 2410}
2411
2412/**
2413 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2414 * @vsi: the vsi being configured
2415 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2416 *
2417 * Return: 0 on success or negative otherwise
41c445ff
JB		 2418 **/
2419int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2420{
2421 struct net_device *netdev = vsi->netdev;
2422 struct i40e_mac_filter *f, *add_f;
2423 bool is_vf, is_netdev;
2424 int filter_count = 0;
41c445ff
JB		 2425
2426 is_vf = (vsi->type == I40E_VSI_SRIOV);
2427 is_netdev = !!(netdev);
2428
21659035
KP		 2429 /* Locked once because all functions invoked below iterates list */
2430 spin_lock_bh(&vsi->mac_filter_list_lock);
2431
41c445ff
JB		 2432 if (is_netdev)
2433 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2434
2435 list_for_each_entry(f, &vsi->mac_filter_list, list)
2436 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2437
41c445ff
JB		 2438 /* go through all the filters for this VSI and if there is only
2439 * vid == 0 it means there are no other filters, so vid 0 must
2440 * be replaced with -1. This signifies that we should from now
2441 * on accept any traffic (with any tag present, or untagged)
2442 */
2443 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2444 if (is_netdev) {
2445 if (f->vlan &&
2446 ether_addr_equal(netdev->dev_addr, f->macaddr))
2447 filter_count++;
2448 }
2449
2450 if (f->vlan)
2451 filter_count++;
2452 }
2453
2454 if (!filter_count && is_netdev) {
2455 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2456 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2457 is_vf, is_netdev);
2458 if (!f) {
2459 dev_info(&vsi->back->pdev->dev,
2460 "Could not add filter %d for %pM\n",
2461 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2462 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2463 return -ENOMEM;
2464 }
2465 }
2466
2467 if (!filter_count) {
2468 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2469 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2470 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2471 is_vf, is_netdev);
41c445ff
JB		 2472 if (!add_f) {
2473 dev_info(&vsi->back->pdev->dev,
2474 "Could not add filter %d for %pM\n",
2475 I40E_VLAN_ANY, f->macaddr);
21659035 2476 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2477 return -ENOMEM;
2478 }
2479 }
2480 }
2481
21659035
KP		 2482 spin_unlock_bh(&vsi->mac_filter_list_lock);
2483
0e4425ed
JB		 2484 /* schedule our worker thread which will take care of
2485 * applying the new filter changes
2486 */
2487 i40e_service_event_schedule(vsi->back);
2488 return 0;
41c445ff
JB		 2489}
2490
2491/**
2492 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2493 * @netdev: network interface to be adjusted
2494 * @vid: vlan id to be added
078b5876
JB		 2495 *
2496 * net_device_ops implementation for adding vlan ids
41c445ff 2497 **/
38e00438
VD		 2498#ifdef I40E_FCOE
2499int i40e_vlan_rx_add_vid(struct net_device *netdev,
2500 __always_unused __be16 proto, u16 vid)
2501#else
41c445ff
JB		 2502static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2503 __always_unused __be16 proto, u16 vid)
38e00438 2504#endif
41c445ff
JB		 2505{
2506 struct i40e_netdev_priv *np = netdev_priv(netdev);
2507 struct i40e_vsi *vsi = np->vsi;
078b5876 2508 int ret = 0;
41c445ff
JB		 2509
2510 if (vid > 4095)
078b5876
JB		 2511 return -EINVAL;
2512
2513 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2514
6982d429
ASJ		 2515 /* If the network stack called us with vid = 0 then
2516 * it is asking to receive priority tagged packets with
2517 * vlan id 0. Our HW receives them by default when configured
2518 * to receive untagged packets so there is no need to add an
2519 * extra filter for vlan 0 tagged packets.
41c445ff 2520 */
6982d429
ASJ		 2521 if (vid)
2522 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2523
078b5876
JB		 2524 if (!ret && (vid < VLAN_N_VID))
2525 set_bit(vid, vsi->active_vlans);
41c445ff 2526
078b5876 2527 return ret;
41c445ff
JB		 2528}
2529
2530/**
2531 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2532 * @netdev: network interface to be adjusted
2533 * @vid: vlan id to be removed
078b5876 2534 *
fdfd943e 2535 * net_device_ops implementation for removing vlan ids
41c445ff 2536 **/
38e00438
VD		 2537#ifdef I40E_FCOE
2538int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2539 __always_unused __be16 proto, u16 vid)
2540#else
41c445ff
JB		 2541static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2542 __always_unused __be16 proto, u16 vid)
38e00438 2543#endif
41c445ff
JB		 2544{
2545 struct i40e_netdev_priv *np = netdev_priv(netdev);
2546 struct i40e_vsi *vsi = np->vsi;
2547
078b5876
JB		 2548 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2549
41c445ff
JB		 2550 /* return code is ignored as there is nothing a user
2551 * can do about failure to remove and a log message was
078b5876 2552 * already printed from the other function
41c445ff
JB		 2553 */
2554 i40e_vsi_kill_vlan(vsi, vid);
2555
2556 clear_bit(vid, vsi->active_vlans);
078b5876 2557
41c445ff
JB		 2558 return 0;
2559}
2560
2561/**
2562 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2563 * @vsi: the vsi being brought back up
2564 **/
2565static void i40e_restore_vlan(struct i40e_vsi *vsi)
2566{
2567 u16 vid;
2568
2569 if (!vsi->netdev)
2570 return;
2571
2572 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2573
2574 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2575 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2576 vid);
2577}
2578
2579/**
2580 * i40e_vsi_add_pvid - Add pvid for the VSI
2581 * @vsi: the vsi being adjusted
2582 * @vid: the vlan id to set as a PVID
2583 **/
dcae29be 2584int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2585{
2586 struct i40e_vsi_context ctxt;
f1c7e72e 2587 i40e_status ret;
41c445ff
JB		 2588
2589 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2590 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2591 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2592 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2593 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2594
2595 ctxt.seid = vsi->seid;
1a2f6248 2596 ctxt.info = vsi->info;
f1c7e72e
SN		 2597 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2598 if (ret) {
41c445ff 2599 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2600 "add pvid failed, err %s aq_err %s\n",
2601 i40e_stat_str(&vsi->back->hw, ret),
2602 i40e_aq_str(&vsi->back->hw,
2603 vsi->back->hw.aq.asq_last_status));
dcae29be 2604 return -ENOENT;
41c445ff
JB		 2605 }
2606
dcae29be 2607 return 0;
41c445ff
JB		 2608}
2609
2610/**
2611 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2612 * @vsi: the vsi being adjusted
2613 *
2614 * Just use the vlan_rx_register() service to put it back to normal
2615 **/
2616void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2617{
6c12fcbf
GR		 2618 i40e_vlan_stripping_disable(vsi);
2619
41c445ff 2620 vsi->info.pvid = 0;
41c445ff
JB		 2621}
2622
2623/**
2624 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2625 * @vsi: ptr to the VSI
2626 *
2627 * If this function returns with an error, then it's possible one or
2628 * more of the rings is populated (while the rest are not). It is the
2629 * callers duty to clean those orphaned rings.
2630 *
2631 * Return 0 on success, negative on failure
2632 **/
2633static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2634{
2635 int i, err = 0;
2636
2637 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2638 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2639
2640 return err;
2641}
2642
2643/**
2644 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2645 * @vsi: ptr to the VSI
2646 *
2647 * Free VSI's transmit software resources
2648 **/
2649static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2650{
2651 int i;
2652
8e9dca53
GR		 2653 if (!vsi->tx_rings)
2654 return;
2655
41c445ff 2656 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2657 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2658 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2659}
2660
2661/**
2662 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2663 * @vsi: ptr to the VSI
2664 *
2665 * If this function returns with an error, then it's possible one or
2666 * more of the rings is populated (while the rest are not). It is the
2667 * callers duty to clean those orphaned rings.
2668 *
2669 * Return 0 on success, negative on failure
2670 **/
2671static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2672{
2673 int i, err = 0;
2674
2675 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2676 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2677#ifdef I40E_FCOE
2678 i40e_fcoe_setup_ddp_resources(vsi);
2679#endif
41c445ff
JB		 2680 return err;
2681}
2682
2683/**
2684 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2685 * @vsi: ptr to the VSI
2686 *
2687 * Free all receive software resources
2688 **/
2689static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2690{
2691 int i;
2692
8e9dca53
GR		 2693 if (!vsi->rx_rings)
2694 return;
2695
41c445ff 2696 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2697 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2698 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2699#ifdef I40E_FCOE
2700 i40e_fcoe_free_ddp_resources(vsi);
2701#endif
41c445ff
JB		 2702}
2703
3ffa037d
NP		 2704/**
2705 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2706 * @ring: The Tx ring to configure
2707 *
2708 * This enables/disables XPS for a given Tx descriptor ring
2709 * based on the TCs enabled for the VSI that ring belongs to.
2710 **/
2711static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2712{
2713 struct i40e_vsi *vsi = ring->vsi;
2714 cpumask_var_t mask;
2715
9a660eea
JB		 2716 if (!ring->q_vector || !ring->netdev)
2717 return;
2718
2719 /* Single TC mode enable XPS */
2720 if (vsi->tc_config.numtc <= 1) {
2721 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2722 netif_set_xps_queue(ring->netdev,
2723 &ring->q_vector->affinity_mask,
2724 ring->queue_index);
9a660eea
JB		 2725 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2726 /* Disable XPS to allow selection based on TC */
2727 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2728 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2729 free_cpumask_var(mask);
3ffa037d 2730 }
0e4425ed
JB		 2731
2732 /* schedule our worker thread which will take care of
2733 * applying the new filter changes
2734 */
2735 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2736}
2737
41c445ff
JB		 2738/**
2739 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2740 * @ring: The Tx ring to configure
2741 *
2742 * Configure the Tx descriptor ring in the HMC context.
2743 **/
2744static int i40e_configure_tx_ring(struct i40e_ring *ring)
2745{
2746 struct i40e_vsi *vsi = ring->vsi;
2747 u16 pf_q = vsi->base_queue + ring->queue_index;
2748 struct i40e_hw *hw = &vsi->back->hw;
2749 struct i40e_hmc_obj_txq tx_ctx;
2750 i40e_status err = 0;
2751 u32 qtx_ctl = 0;
2752
2753 /* some ATR related tx ring init */
60ea5f83 2754 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2755 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2756 ring->atr_count = 0;
2757 } else {
2758 ring->atr_sample_rate = 0;
2759 }
2760
3ffa037d
NP		 2761 /* configure XPS */
2762 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2763
2764 /* clear the context structure first */
2765 memset(&tx_ctx, 0, sizeof(tx_ctx));
2766
2767 tx_ctx.new_context = 1;
2768 tx_ctx.base = (ring->dma / 128);
2769 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2770 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2771 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2772#ifdef I40E_FCOE
2773 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2774#endif
beb0dff1 2775 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2776 /* FDIR VSI tx ring can still use RS bit and writebacks */
2777 if (vsi->type != I40E_VSI_FDIR)
2778 tx_ctx.head_wb_ena = 1;
2779 tx_ctx.head_wb_addr = ring->dma +
2780 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2781
2782 /* As part of VSI creation/update, FW allocates certain
2783 * Tx arbitration queue sets for each TC enabled for
2784 * the VSI. The FW returns the handles to these queue
2785 * sets as part of the response buffer to Add VSI,
2786 * Update VSI, etc. AQ commands. It is expected that
2787 * these queue set handles be associated with the Tx
2788 * queues by the driver as part of the TX queue context
2789 * initialization. This has to be done regardless of
2790 * DCB as by default everything is mapped to TC0.
2791 */
2792 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2793 tx_ctx.rdylist_act = 0;
2794
2795 /* clear the context in the HMC */
2796 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2797 if (err) {
2798 dev_info(&vsi->back->pdev->dev,
2799 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2800 ring->queue_index, pf_q, err);
2801 return -ENOMEM;
2802 }
2803
2804 /* set the context in the HMC */
2805 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2806 if (err) {
2807 dev_info(&vsi->back->pdev->dev,
2808 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2809 ring->queue_index, pf_q, err);
2810 return -ENOMEM;
2811 }
2812
2813 /* Now associate this queue with this PCI function */
7a28d885 2814 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2815 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2816 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2817 I40E_QTX_CTL_VFVM_INDX_MASK;
2818 } else {
9d8bf547 2819 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2820 }
2821
13fd9774
SN		 2822 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2823 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2824 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2825 i40e_flush(hw);
2826
41c445ff
JB		 2827 /* cache tail off for easier writes later */
2828 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2829
2830 return 0;
2831}
2832
2833/**
2834 * i40e_configure_rx_ring - Configure a receive ring context
2835 * @ring: The Rx ring to configure
2836 *
2837 * Configure the Rx descriptor ring in the HMC context.
2838 **/
2839static int i40e_configure_rx_ring(struct i40e_ring *ring)
2840{
2841 struct i40e_vsi *vsi = ring->vsi;
2842 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2843 u16 pf_q = vsi->base_queue + ring->queue_index;
2844 struct i40e_hw *hw = &vsi->back->hw;
2845 struct i40e_hmc_obj_rxq rx_ctx;
2846 i40e_status err = 0;
2847
2848 ring->state = 0;
2849
2850 /* clear the context structure first */
2851 memset(&rx_ctx, 0, sizeof(rx_ctx));
2852
2853 ring->rx_buf_len = vsi->rx_buf_len;
41c445ff
JB		 2854
2855 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
41c445ff
JB		 2856
2857 rx_ctx.base = (ring->dma / 128);
2858 rx_ctx.qlen = ring->count;
2859
bec60fc4
JB		 2860 /* use 32 byte descriptors */
2861 rx_ctx.dsize = 1;
41c445ff 2862
bec60fc4
JB		 2863 /* descriptor type is always zero
2864 * rx_ctx.dtype = 0;
2865 */
b32bfa17 2866 rx_ctx.hsplit_0 = 0;
41c445ff 2867
b32bfa17 2868 rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len);
7134f9ce
JB		 2869 if (hw->revision_id == 0)
2870 rx_ctx.lrxqthresh = 0;
2871 else
2872 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2873 rx_ctx.crcstrip = 1;
2874 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2875 /* this controls whether VLAN is stripped from inner headers */
2876 rx_ctx.showiv = 0;
38e00438
VD		 2877#ifdef I40E_FCOE
2878 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2879#endif
acb3676b
CS		 2880 /* set the prefena field to 1 because the manual says to */
2881 rx_ctx.prefena = 1;
41c445ff
JB		 2882
2883 /* clear the context in the HMC */
2884 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2885 if (err) {
2886 dev_info(&vsi->back->pdev->dev,
2887 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2888 ring->queue_index, pf_q, err);
2889 return -ENOMEM;
2890 }
2891
2892 /* set the context in the HMC */
2893 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2894 if (err) {
2895 dev_info(&vsi->back->pdev->dev,
2896 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2897 ring->queue_index, pf_q, err);
2898 return -ENOMEM;
2899 }
2900
2901 /* cache tail for quicker writes, and clear the reg before use */
2902 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2903 writel(0, ring->tail);
2904
1a557afc 2905 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
41c445ff
JB		 2906
2907 return 0;
2908}
2909
2910/**
2911 * i40e_vsi_configure_tx - Configure the VSI for Tx
2912 * @vsi: VSI structure describing this set of rings and resources
2913 *
2914 * Configure the Tx VSI for operation.
2915 **/
2916static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2917{
2918 int err = 0;
2919 u16 i;
2920
9f65e15b
AD		 2921 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2922 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2923
2924 return err;
2925}
2926
2927/**
2928 * i40e_vsi_configure_rx - Configure the VSI for Rx
2929 * @vsi: the VSI being configured
2930 *
2931 * Configure the Rx VSI for operation.
2932 **/
2933static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2934{
2935 int err = 0;
2936 u16 i;
2937
2938 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2939 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2940 + ETH_FCS_LEN + VLAN_HLEN;
2941 else
2942 vsi->max_frame = I40E_RXBUFFER_2048;
2943
1a557afc 2944 vsi->rx_buf_len = I40E_RXBUFFER_2048;
41c445ff 2945
38e00438
VD		 2946#ifdef I40E_FCOE
2947 /* setup rx buffer for FCoE */
2948 if ((vsi->type == I40E_VSI_FCOE) &&
2949 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
38e00438
VD		 2950 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2951 vsi->max_frame = I40E_RXBUFFER_3072;
38e00438
VD		 2952 }
2953
2954#endif /* I40E_FCOE */
41c445ff 2955 /* round up for the chip's needs */
41c445ff 2956 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2957 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2958
2959 /* set up individual rings */
2960 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2961 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2962
2963 return err;
2964}
2965
2966/**
2967 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2968 * @vsi: ptr to the VSI
2969 **/
2970static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2971{
e7046ee1 2972 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2973 u16 qoffset, qcount;
2974 int i, n;
2975
cd238a3e
PN		 2976 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2977 /* Reset the TC information */
2978 for (i = 0; i < vsi->num_queue_pairs; i++) {
2979 rx_ring = vsi->rx_rings[i];
2980 tx_ring = vsi->tx_rings[i];
2981 rx_ring->dcb_tc = 0;
2982 tx_ring->dcb_tc = 0;
2983 }
2984 }
41c445ff
JB		 2985
2986 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2987 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2988 continue;
2989
2990 qoffset = vsi->tc_config.tc_info[n].qoffset;
2991 qcount = vsi->tc_config.tc_info[n].qcount;
2992 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2993 rx_ring = vsi->rx_rings[i];
2994 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2995 rx_ring->dcb_tc = n;
2996 tx_ring->dcb_tc = n;
2997 }
2998 }
2999}
3000
3001/**
3002 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3003 * @vsi: ptr to the VSI
3004 **/
3005static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3006{
3007 if (vsi->netdev)
3008 i40e_set_rx_mode(vsi->netdev);
3009}
3010
17a73f6b
JG		 3011/**
3012 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3013 * @vsi: Pointer to the targeted VSI
3014 *
3015 * This function replays the hlist on the hw where all the SB Flow Director
3016 * filters were saved.
3017 **/
3018static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3019{
3020 struct i40e_fdir_filter *filter;
3021 struct i40e_pf *pf = vsi->back;
3022 struct hlist_node *node;
3023
55a5e60b
ASJ		 3024 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3025 return;
3026
17a73f6b
JG		 3027 hlist_for_each_entry_safe(filter, node,
3028 &pf->fdir_filter_list, fdir_node) {
3029 i40e_add_del_fdir(vsi, filter, true);
3030 }
3031}
3032
41c445ff
JB		 3033/**
3034 * i40e_vsi_configure - Set up the VSI for action
3035 * @vsi: the VSI being configured
3036 **/
3037static int i40e_vsi_configure(struct i40e_vsi *vsi)
3038{
3039 int err;
3040
3041 i40e_set_vsi_rx_mode(vsi);
3042 i40e_restore_vlan(vsi);
3043 i40e_vsi_config_dcb_rings(vsi);
3044 err = i40e_vsi_configure_tx(vsi);
3045 if (!err)
3046 err = i40e_vsi_configure_rx(vsi);
3047
3048 return err;
3049}
3050
3051/**
3052 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3053 * @vsi: the VSI being configured
3054 **/
3055static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3056{
3057 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3058 struct i40e_hw *hw = &pf->hw;
3059 u16 vector;
3060 int i, q;
41c445ff
JB		 3061 u32 qp;
3062
3063 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3064 * and PFINT_LNKLSTn registers, e.g.:
3065 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3066 */
3067 qp = vsi->base_queue;
3068 vector = vsi->base_vector;
493fb300 3069 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3070 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3071
ee2319cf 3072 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3073 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting);
41c445ff
JB		 3074 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3075 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3076 q_vector->rx.itr);
a75e8005 3077 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting);
41c445ff
JB		 3078 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3079 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3080 q_vector->tx.itr);
ac26fc13
JB		 3081 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3082 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3083
3084 /* Linked list for the queuepairs assigned to this vector */
3085 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3086 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3087 u32 val;
3088
41c445ff
JB		 3089 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3090 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3091 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3092 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3093 (I40E_QUEUE_TYPE_TX
3094 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3095
3096 wr32(hw, I40E_QINT_RQCTL(qp), val);
3097
3098 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3099 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3100 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3101 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3102 (I40E_QUEUE_TYPE_RX
3103 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3104
3105 /* Terminate the linked list */
3106 if (q == (q_vector->num_ringpairs - 1))
3107 val |= (I40E_QUEUE_END_OF_LIST
3108 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3109
3110 wr32(hw, I40E_QINT_TQCTL(qp), val);
3111 qp++;
3112 }
3113 }
3114
3115 i40e_flush(hw);
3116}
3117
3118/**
3119 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3120 * @hw: ptr to the hardware info
3121 **/
ab437b5a 3122static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3123{
ab437b5a 3124 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3125 u32 val;
3126
3127 /* clear things first */
3128 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3129 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3130
3131 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3132 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3133 I40E_PFINT_ICR0_ENA_GRST_MASK |
3134 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3135 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3136 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3137 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3138 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3139
0d8e1439
ASJ		 3140 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3141 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3142
ab437b5a
JK		 3143 if (pf->flags & I40E_FLAG_PTP)
3144 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3145
41c445ff
JB		 3146 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3147
3148 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3149 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3150 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3151
3152 /* OTHER_ITR_IDX = 0 */
3153 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3154}
3155
3156/**
3157 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3158 * @vsi: the VSI being configured
3159 **/
3160static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3161{
493fb300 3162 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3163 struct i40e_pf *pf = vsi->back;
3164 struct i40e_hw *hw = &pf->hw;
3165 u32 val;
3166
3167 /* set the ITR configuration */
ee2319cf 3168 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3169 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting);
41c445ff
JB		 3170 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3171 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
a75e8005 3172 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting);
41c445ff
JB		 3173 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3174 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3175
ab437b5a 3176 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3177
3178 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3179 wr32(hw, I40E_PFINT_LNKLST0, 0);
3180
f29eaa3d 3181 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3182 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3183 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3184 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3185
3186 wr32(hw, I40E_QINT_RQCTL(0), val);
3187
3188 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3189 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3190 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3191
3192 wr32(hw, I40E_QINT_TQCTL(0), val);
3193 i40e_flush(hw);
3194}
3195
2ef28cfb
MW		 3196/**
3197 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3198 * @pf: board private structure
3199 **/
3200void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3201{
3202 struct i40e_hw *hw = &pf->hw;
3203
3204 wr32(hw, I40E_PFINT_DYN_CTL0,
3205 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3206 i40e_flush(hw);
3207}
3208
41c445ff
JB		 3209/**
3210 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3211 * @pf: board private structure
40d72a50 3212 * @clearpba: true when all pending interrupt events should be cleared
41c445ff 3213 **/
40d72a50 3214void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba)
41c445ff
JB		 3215{
3216 struct i40e_hw *hw = &pf->hw;
3217 u32 val;
3218
3219 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
40d72a50 3220 (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) |
41c445ff
JB		 3221 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3222
3223 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3224 i40e_flush(hw);
3225}
3226
41c445ff
JB		 3227/**
3228 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3229 * @irq: interrupt number
3230 * @data: pointer to a q_vector
3231 **/
3232static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3233{
3234 struct i40e_q_vector *q_vector = data;
3235
cd0b6fa6 3236 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3237 return IRQ_HANDLED;
3238
5d3465a1 3239 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3240
3241 return IRQ_HANDLED;
3242}
3243
41c445ff
JB		 3244/**
3245 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3246 * @vsi: the VSI being configured
3247 * @basename: name for the vector
3248 *
3249 * Allocates MSI-X vectors and requests interrupts from the kernel.
3250 **/
3251static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3252{
3253 int q_vectors = vsi->num_q_vectors;
3254 struct i40e_pf *pf = vsi->back;
3255 int base = vsi->base_vector;
3256 int rx_int_idx = 0;
3257 int tx_int_idx = 0;
3258 int vector, err;
3259
3260 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3261 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3262
cd0b6fa6 3263 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3264 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3265 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3266 tx_int_idx++;
cd0b6fa6 3267 } else if (q_vector->rx.ring) {
41c445ff
JB		 3268 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3269 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3270 } else if (q_vector->tx.ring) {
41c445ff
JB		 3271 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3272 "%s-%s-%d", basename, "tx", tx_int_idx++);
3273 } else {
3274 /* skip this unused q_vector */
3275 continue;
3276 }
3277 err = request_irq(pf->msix_entries[base + vector].vector,
3278 vsi->irq_handler,
3279 0,
3280 q_vector->name,
3281 q_vector);
3282 if (err) {
3283 dev_info(&pf->pdev->dev,
fb43201f 3284 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3285 goto free_queue_irqs;
3286 }
3287 /* assign the mask for this irq */
3288 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3289 &q_vector->affinity_mask);
3290 }
3291
63741846 3292 vsi->irqs_ready = true;
41c445ff
JB		 3293 return 0;
3294
3295free_queue_irqs:
3296 while (vector) {
3297 vector--;
3298 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3299 NULL);
3300 free_irq(pf->msix_entries[base + vector].vector,
3301 &(vsi->q_vectors[vector]));
3302 }
3303 return err;
3304}
3305
3306/**
3307 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3308 * @vsi: the VSI being un-configured
3309 **/
3310static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3311{
3312 struct i40e_pf *pf = vsi->back;
3313 struct i40e_hw *hw = &pf->hw;
3314 int base = vsi->base_vector;
3315 int i;
3316
3317 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3318 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3319 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3320 }
3321
3322 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3323 for (i = vsi->base_vector;
3324 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3325 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3326
3327 i40e_flush(hw);
3328 for (i = 0; i < vsi->num_q_vectors; i++)
3329 synchronize_irq(pf->msix_entries[i + base].vector);
3330 } else {
3331 /* Legacy and MSI mode - this stops all interrupt handling */
3332 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3333 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3334 i40e_flush(hw);
3335 synchronize_irq(pf->pdev->irq);
3336 }
3337}
3338
3339/**
3340 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3341 * @vsi: the VSI being configured
3342 **/
3343static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3344{
3345 struct i40e_pf *pf = vsi->back;
3346 int i;
3347
3348 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3349 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3350 i40e_irq_dynamic_enable(vsi, i);
3351 } else {
40d72a50 3352 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 3353 }
3354
1022cb6c 3355 i40e_flush(&pf->hw);
41c445ff
JB		 3356 return 0;
3357}
3358
3359/**
3360 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3361 * @pf: board private structure
3362 **/
3363static void i40e_stop_misc_vector(struct i40e_pf *pf)
3364{
3365 /* Disable ICR 0 */
3366 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3367 i40e_flush(&pf->hw);
3368}
3369
3370/**
3371 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3372 * @irq: interrupt number
3373 * @data: pointer to a q_vector
3374 *
3375 * This is the handler used for all MSI/Legacy interrupts, and deals
3376 * with both queue and non-queue interrupts. This is also used in
3377 * MSIX mode to handle the non-queue interrupts.
3378 **/
3379static irqreturn_t i40e_intr(int irq, void *data)
3380{
3381 struct i40e_pf *pf = (struct i40e_pf *)data;
3382 struct i40e_hw *hw = &pf->hw;
5e823066 3383 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3384 u32 icr0, icr0_remaining;
3385 u32 val, ena_mask;
3386
3387 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3388 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3389
116a57d4
SN		 3390 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3391 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3392 goto enable_intr;
41c445ff 3393
cd92e72f
SN		 3394 /* if interrupt but no bits showing, must be SWINT */
3395 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3396 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3397 pf->sw_int_count++;
3398
0d8e1439
ASJ		 3399 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3400 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3401 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3402 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3403 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3404 }
3405
41c445ff
JB		 3406 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3407 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3408 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3409 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff 3410
a16ae2d5
ASJ		 3411 /* We do not have a way to disarm Queue causes while leaving
3412 * interrupt enabled for all other causes, ideally
3413 * interrupt should be disabled while we are in NAPI but
3414 * this is not a performance path and napi_schedule()
3415 * can deal with rescheduling.
3416 */
41c445ff 3417 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3418 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3419 }
3420
3421 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3422 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3423 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6e93d0c9 3424 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n");
41c445ff
JB		 3425 }
3426
3427 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3428 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3429 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3430 }
3431
3432 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3433 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3434 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3435 }
3436
3437 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3438 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3439 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3440 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3441 val = rd32(hw, I40E_GLGEN_RSTAT);
3442 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3443 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3444 if (val == I40E_RESET_CORER) {
41c445ff 3445 pf->corer_count++;
4eb3f768 3446 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3447 pf->globr_count++;
4eb3f768 3448 } else if (val == I40E_RESET_EMPR) {
41c445ff 3449 pf->empr_count++;
9df42d1a 3450 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3451 }
41c445ff
JB		 3452 }
3453
9c010ee0
ASJ		 3454 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3455 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3456 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3457 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3458 rd32(hw, I40E_PFHMC_ERRORINFO),
3459 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3460 }
3461
beb0dff1
JK		 3462 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3463 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3464
3465 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3466 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3467 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3468 }
beb0dff1
JK		 3469 }
3470
41c445ff
JB		 3471 /* If a critical error is pending we have no choice but to reset the
3472 * device.
3473 * Report and mask out any remaining unexpected interrupts.
3474 */
3475 icr0_remaining = icr0 & ena_mask;
3476 if (icr0_remaining) {
3477 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3478 icr0_remaining);
9c010ee0 3479 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3480 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3481 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3482 dev_info(&pf->pdev->dev, "device will be reset\n");
3483 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3484 i40e_service_event_schedule(pf);
41c445ff
JB		 3485 }
3486 ena_mask &= ~icr0_remaining;
3487 }
5e823066 3488 ret = IRQ_HANDLED;
41c445ff 3489
5e823066 3490enable_intr:
41c445ff
JB		 3491 /* re-enable interrupt causes */
3492 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3493 if (!test_bit(__I40E_DOWN, &pf->state)) {
3494 i40e_service_event_schedule(pf);
40d72a50 3495 i40e_irq_dynamic_enable_icr0(pf, false);
41c445ff
JB		 3496 }
3497
5e823066 3498 return ret;
41c445ff
JB		 3499}
3500
cbf61325
ASJ		 3501/**
3502 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3503 * @tx_ring: tx ring to clean
3504 * @budget: how many cleans we're allowed
3505 *
3506 * Returns true if there's any budget left (e.g. the clean is finished)
3507 **/
3508static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3509{
3510 struct i40e_vsi *vsi = tx_ring->vsi;
3511 u16 i = tx_ring->next_to_clean;
3512 struct i40e_tx_buffer *tx_buf;
3513 struct i40e_tx_desc *tx_desc;
3514
3515 tx_buf = &tx_ring->tx_bi[i];
3516 tx_desc = I40E_TX_DESC(tx_ring, i);
3517 i -= tx_ring->count;
3518
3519 do {
3520 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3521
3522 /* if next_to_watch is not set then there is no work pending */
3523 if (!eop_desc)
3524 break;
3525
3526 /* prevent any other reads prior to eop_desc */
3527 read_barrier_depends();
3528
3529 /* if the descriptor isn't done, no work yet to do */
3530 if (!(eop_desc->cmd_type_offset_bsz &
3531 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3532 break;
3533
3534 /* clear next_to_watch to prevent false hangs */
3535 tx_buf->next_to_watch = NULL;
3536
49d7d933
ASJ		 3537 tx_desc->buffer_addr = 0;
3538 tx_desc->cmd_type_offset_bsz = 0;
3539 /* move past filter desc */
3540 tx_buf++;
3541 tx_desc++;
3542 i++;
3543 if (unlikely(!i)) {
3544 i -= tx_ring->count;
3545 tx_buf = tx_ring->tx_bi;
3546 tx_desc = I40E_TX_DESC(tx_ring, 0);
3547 }
cbf61325
ASJ		 3548 /* unmap skb header data */
3549 dma_unmap_single(tx_ring->dev,
3550 dma_unmap_addr(tx_buf, dma),
3551 dma_unmap_len(tx_buf, len),
3552 DMA_TO_DEVICE);
49d7d933
ASJ		 3553 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3554 kfree(tx_buf->raw_buf);
cbf61325 3555
49d7d933
ASJ		 3556 tx_buf->raw_buf = NULL;
3557 tx_buf->tx_flags = 0;
3558 tx_buf->next_to_watch = NULL;
cbf61325 3559 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3560 tx_desc->buffer_addr = 0;
3561 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3562
49d7d933 3563 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3564 tx_buf++;
3565 tx_desc++;
3566 i++;
3567 if (unlikely(!i)) {
3568 i -= tx_ring->count;
3569 tx_buf = tx_ring->tx_bi;
3570 tx_desc = I40E_TX_DESC(tx_ring, 0);
3571 }
3572
3573 /* update budget accounting */
3574 budget--;
3575 } while (likely(budget));
3576
3577 i += tx_ring->count;
3578 tx_ring->next_to_clean = i;
3579
6995b36c 3580 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3581 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3582
cbf61325
ASJ		 3583 return budget > 0;
3584}
3585
3586/**
3587 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3588 * @irq: interrupt number
3589 * @data: pointer to a q_vector
3590 **/
3591static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3592{
3593 struct i40e_q_vector *q_vector = data;
3594 struct i40e_vsi *vsi;
3595
3596 if (!q_vector->tx.ring)
3597 return IRQ_HANDLED;
3598
3599 vsi = q_vector->tx.ring->vsi;
3600 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3601
3602 return IRQ_HANDLED;
3603}
3604
41c445ff 3605/**
cd0b6fa6 3606 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3607 * @vsi: the VSI being configured
3608 * @v_idx: vector index
cd0b6fa6 3609 * @qp_idx: queue pair index
41c445ff 3610 **/
26cdc443 3611static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3612{
493fb300 3613 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3614 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3615 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3616
3617 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3618 tx_ring->next = q_vector->tx.ring;
3619 q_vector->tx.ring = tx_ring;
41c445ff 3620 q_vector->tx.count++;
cd0b6fa6
AD		 3621
3622 rx_ring->q_vector = q_vector;
3623 rx_ring->next = q_vector->rx.ring;
3624 q_vector->rx.ring = rx_ring;
3625 q_vector->rx.count++;
41c445ff
JB		 3626}
3627
3628/**
3629 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3630 * @vsi: the VSI being configured
3631 *
3632 * This function maps descriptor rings to the queue-specific vectors
3633 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3634 * one vector per queue pair, but on a constrained vector budget, we
3635 * group the queue pairs as "efficiently" as possible.
3636 **/
3637static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3638{
3639 int qp_remaining = vsi->num_queue_pairs;
3640 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3641 int num_ringpairs;
41c445ff
JB		 3642 int v_start = 0;
3643 int qp_idx = 0;
3644
3645 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3646 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3647 * It is also important to go through all the vectors available to be
3648 * sure that if we don't use all the vectors, that the remaining vectors
3649 * are cleared. This is especially important when decreasing the
3650 * number of queues in use.
41c445ff 3651 */
70114ec4 3652 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3653 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3654
3655 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3656
3657 q_vector->num_ringpairs = num_ringpairs;
3658
3659 q_vector->rx.count = 0;
3660 q_vector->tx.count = 0;
3661 q_vector->rx.ring = NULL;
3662 q_vector->tx.ring = NULL;
3663
3664 while (num_ringpairs--) {
26cdc443 3665 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3666 qp_idx++;
3667 qp_remaining--;
41c445ff
JB		 3668 }
3669 }
3670}
3671
3672/**
3673 * i40e_vsi_request_irq - Request IRQ from the OS
3674 * @vsi: the VSI being configured
3675 * @basename: name for the vector
3676 **/
3677static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3678{
3679 struct i40e_pf *pf = vsi->back;
3680 int err;
3681
3682 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3683 err = i40e_vsi_request_irq_msix(vsi, basename);
3684 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3685 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3686 pf->int_name, pf);
41c445ff
JB		 3687 else
3688 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3689 pf->int_name, pf);
41c445ff
JB		 3690
3691 if (err)
3692 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3693
3694 return err;
3695}
3696
3697#ifdef CONFIG_NET_POLL_CONTROLLER
3698/**
d89d967f 3699 * i40e_netpoll - A Polling 'interrupt' handler
41c445ff
JB		 3700 * @netdev: network interface device structure
3701 *
3702 * This is used by netconsole to send skbs without having to re-enable
3703 * interrupts. It's not called while the normal interrupt routine is executing.
3704 **/
38e00438
VD		 3705#ifdef I40E_FCOE
3706void i40e_netpoll(struct net_device *netdev)
3707#else
41c445ff 3708static void i40e_netpoll(struct net_device *netdev)
38e00438 3709#endif
41c445ff
JB		 3710{
3711 struct i40e_netdev_priv *np = netdev_priv(netdev);
3712 struct i40e_vsi *vsi = np->vsi;
3713 struct i40e_pf *pf = vsi->back;
3714 int i;
3715
3716 /* if interface is down do nothing */
3717 if (test_bit(__I40E_DOWN, &vsi->state))
3718 return;
3719
41c445ff
JB		 3720 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3721 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3722 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3723 } else {
3724 i40e_intr(pf->pdev->irq, netdev);
3725 }
41c445ff
JB		 3726}
3727#endif
3728
23527308
NP		 3729/**
3730 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3731 * @pf: the PF being configured
3732 * @pf_q: the PF queue
3733 * @enable: enable or disable state of the queue
3734 *
3735 * This routine will wait for the given Tx queue of the PF to reach the
3736 * enabled or disabled state.
3737 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3738 * multiple retries; else will return 0 in case of success.
3739 **/
3740static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3741{
3742 int i;
3743 u32 tx_reg;
3744
3745 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3746 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3747 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3748 break;
3749
f98a2006 3750 usleep_range(10, 20);
23527308
NP		 3751 }
3752 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3753 return -ETIMEDOUT;
3754
3755 return 0;
3756}
3757
41c445ff
JB		 3758/**
3759 * i40e_vsi_control_tx - Start or stop a VSI's rings
3760 * @vsi: the VSI being configured
3761 * @enable: start or stop the rings
3762 **/
3763static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3764{
3765 struct i40e_pf *pf = vsi->back;
3766 struct i40e_hw *hw = &pf->hw;
23527308 3767 int i, j, pf_q, ret = 0;
41c445ff
JB		 3768 u32 tx_reg;
3769
3770 pf_q = vsi->base_queue;
3771 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3772
3773 /* warn the TX unit of coming changes */
3774 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3775 if (!enable)
f98a2006 3776 usleep_range(10, 20);
351499ab 3777
6c5ef620 3778 for (j = 0; j < 50; j++) {
41c445ff 3779 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3780 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3781 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3782 break;
3783 usleep_range(1000, 2000);
3784 }
fda972f6 3785 /* Skip if the queue is already in the requested state */
7c122007 3786 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3787 continue;
41c445ff
JB		 3788
3789 /* turn on/off the queue */
c5c9eb9e
SN		 3790 if (enable) {
3791 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3792 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3793 } else {
41c445ff 3794 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3795 }
41c445ff
JB		 3796
3797 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3798 /* No waiting for the Tx queue to disable */
3799 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3800 continue;
41c445ff
JB		 3801
3802 /* wait for the change to finish */
23527308
NP		 3803 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3804 if (ret) {
3805 dev_info(&pf->pdev->dev,
fb43201f
SN		 3806 "VSI seid %d Tx ring %d %sable timeout\n",
3807 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3808 break;
41c445ff
JB		 3809 }
3810 }
3811
7134f9ce
JB		 3812 if (hw->revision_id == 0)
3813 mdelay(50);
23527308
NP		 3814 return ret;
3815}
3816
3817/**
3818 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3819 * @pf: the PF being configured
3820 * @pf_q: the PF queue
3821 * @enable: enable or disable state of the queue
3822 *
3823 * This routine will wait for the given Rx queue of the PF to reach the
3824 * enabled or disabled state.
3825 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3826 * multiple retries; else will return 0 in case of success.
3827 **/
3828static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3829{
3830 int i;
3831 u32 rx_reg;
3832
3833 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3834 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3835 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3836 break;
3837
f98a2006 3838 usleep_range(10, 20);
23527308
NP		 3839 }
3840 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3841 return -ETIMEDOUT;
7134f9ce 3842
41c445ff
JB		 3843 return 0;
3844}
3845
3846/**
3847 * i40e_vsi_control_rx - Start or stop a VSI's rings
3848 * @vsi: the VSI being configured
3849 * @enable: start or stop the rings
3850 **/
3851static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3852{
3853 struct i40e_pf *pf = vsi->back;
3854 struct i40e_hw *hw = &pf->hw;
23527308 3855 int i, j, pf_q, ret = 0;
41c445ff
JB		 3856 u32 rx_reg;
3857
3858 pf_q = vsi->base_queue;
3859 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3860 for (j = 0; j < 50; j++) {
41c445ff 3861 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3862 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3863 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3864 break;
3865 usleep_range(1000, 2000);
3866 }
41c445ff 3867
7c122007
CS		 3868 /* Skip if the queue is already in the requested state */
3869 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3870 continue;
41c445ff
JB		 3871
3872 /* turn on/off the queue */
3873 if (enable)
6c5ef620 3874 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3875 else
6c5ef620 3876 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3877 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3fe06f41
NP		 3878 /* No waiting for the Tx queue to disable */
3879 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3880 continue;
41c445ff
JB		 3881
3882 /* wait for the change to finish */
23527308
NP		 3883 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3884 if (ret) {
3885 dev_info(&pf->pdev->dev,
fb43201f
SN		 3886 "VSI seid %d Rx ring %d %sable timeout\n",
3887 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3888 break;
41c445ff
JB		 3889 }
3890 }
3891
23527308 3892 return ret;
41c445ff
JB		 3893}
3894
3895/**
3896 * i40e_vsi_control_rings - Start or stop a VSI's rings
3897 * @vsi: the VSI being configured
3898 * @enable: start or stop the rings
3899 **/
fc18eaa0 3900int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3901{
3b867b28 3902 int ret = 0;
41c445ff
JB		 3903
3904 /* do rx first for enable and last for disable */
3905 if (request) {
3906 ret = i40e_vsi_control_rx(vsi, request);
3907 if (ret)
3908 return ret;
3909 ret = i40e_vsi_control_tx(vsi, request);
3910 } else {
3b867b28
ASJ		 3911 /* Ignore return value, we need to shutdown whatever we can */
3912 i40e_vsi_control_tx(vsi, request);
3913 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3914 }
3915
3916 return ret;
3917}
3918
3919/**
3920 * i40e_vsi_free_irq - Free the irq association with the OS
3921 * @vsi: the VSI being configured
3922 **/
3923static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3924{
3925 struct i40e_pf *pf = vsi->back;
3926 struct i40e_hw *hw = &pf->hw;
3927 int base = vsi->base_vector;
3928 u32 val, qp;
3929 int i;
3930
3931 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3932 if (!vsi->q_vectors)
3933 return;
3934
63741846
SN		 3935 if (!vsi->irqs_ready)
3936 return;
3937
3938 vsi->irqs_ready = false;
41c445ff
JB		 3939 for (i = 0; i < vsi->num_q_vectors; i++) {
3940 u16 vector = i + base;
3941
3942 /* free only the irqs that were actually requested */
78681b1f
SN		 3943 if (!vsi->q_vectors[i] ||
3944 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3945 continue;
3946
3947 /* clear the affinity_mask in the IRQ descriptor */
3948 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3949 NULL);
3950 free_irq(pf->msix_entries[vector].vector,
493fb300 3951 vsi->q_vectors[i]);
41c445ff
JB		 3952
3953 /* Tear down the interrupt queue link list
3954 *
3955 * We know that they come in pairs and always
3956 * the Rx first, then the Tx. To clear the
3957 * link list, stick the EOL value into the
3958 * next_q field of the registers.
3959 */
3960 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3961 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3962 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3963 val |= I40E_QUEUE_END_OF_LIST
3964 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3965 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3966
3967 while (qp != I40E_QUEUE_END_OF_LIST) {
3968 u32 next;
3969
3970 val = rd32(hw, I40E_QINT_RQCTL(qp));
3971
3972 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3973 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3974 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3975 I40E_QINT_RQCTL_INTEVENT_MASK);
3976
3977 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3978 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3979
3980 wr32(hw, I40E_QINT_RQCTL(qp), val);
3981
3982 val = rd32(hw, I40E_QINT_TQCTL(qp));
3983
3984 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3985 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3986
3987 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3988 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3989 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3990 I40E_QINT_TQCTL_INTEVENT_MASK);
3991
3992 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3993 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3994
3995 wr32(hw, I40E_QINT_TQCTL(qp), val);
3996 qp = next;
3997 }
3998 }
3999 } else {
4000 free_irq(pf->pdev->irq, pf);
4001
4002 val = rd32(hw, I40E_PFINT_LNKLST0);
4003 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4004 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4005 val |= I40E_QUEUE_END_OF_LIST
4006 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4007 wr32(hw, I40E_PFINT_LNKLST0, val);
4008
4009 val = rd32(hw, I40E_QINT_RQCTL(qp));
4010 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4011 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4012 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4013 I40E_QINT_RQCTL_INTEVENT_MASK);
4014
4015 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4016 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4017
4018 wr32(hw, I40E_QINT_RQCTL(qp), val);
4019
4020 val = rd32(hw, I40E_QINT_TQCTL(qp));
4021
4022 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4023 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4024 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4025 I40E_QINT_TQCTL_INTEVENT_MASK);
4026
4027 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4028 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4029
4030 wr32(hw, I40E_QINT_TQCTL(qp), val);
4031 }
4032}
4033
493fb300
AD		 4034/**
4035 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4036 * @vsi: the VSI being configured
4037 * @v_idx: Index of vector to be freed
4038 *
4039 * This function frees the memory allocated to the q_vector. In addition if
4040 * NAPI is enabled it will delete any references to the NAPI struct prior
4041 * to freeing the q_vector.
4042 **/
4043static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4044{
4045 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4046 struct i40e_ring *ring;
493fb300
AD		 4047
4048 if (!q_vector)
4049 return;
4050
4051 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4052 i40e_for_each_ring(ring, q_vector->tx)
4053 ring->q_vector = NULL;
4054
4055 i40e_for_each_ring(ring, q_vector->rx)
4056 ring->q_vector = NULL;
493fb300
AD		 4057
4058 /* only VSI w/ an associated netdev is set up w/ NAPI */
4059 if (vsi->netdev)
4060 netif_napi_del(&q_vector->napi);
4061
4062 vsi->q_vectors[v_idx] = NULL;
4063
4064 kfree_rcu(q_vector, rcu);
4065}
4066
41c445ff
JB		 4067/**
4068 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4069 * @vsi: the VSI being un-configured
4070 *
4071 * This frees the memory allocated to the q_vectors and
4072 * deletes references to the NAPI struct.
4073 **/
4074static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4075{
4076 int v_idx;
4077
493fb300
AD		 4078 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4079 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4080}
4081
4082/**
4083 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4084 * @pf: board private structure
4085 **/
4086static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4087{
4088 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4089 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4090 pci_disable_msix(pf->pdev);
4091 kfree(pf->msix_entries);
4092 pf->msix_entries = NULL;
3b444399
SN		 4093 kfree(pf->irq_pile);
4094 pf->irq_pile = NULL;
41c445ff
JB		 4095 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4096 pci_disable_msi(pf->pdev);
4097 }
4098 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4099}
4100
4101/**
4102 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4103 * @pf: board private structure
4104 *
4105 * We go through and clear interrupt specific resources and reset the structure
4106 * to pre-load conditions
4107 **/
4108static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4109{
4110 int i;
4111
e147758d 4112 i40e_stop_misc_vector(pf);
69278398 4113 if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) {
e147758d
SN		 4114 synchronize_irq(pf->msix_entries[0].vector);
4115 free_irq(pf->msix_entries[0].vector, pf);
4116 }
4117
e3219ce6
ASJ		 4118 i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector,
4119 I40E_IWARP_IRQ_PILE_ID);
4120
41c445ff 4121 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4122 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4123 if (pf->vsi[i])
4124 i40e_vsi_free_q_vectors(pf->vsi[i]);
4125 i40e_reset_interrupt_capability(pf);
4126}
4127
4128/**
4129 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4130 * @vsi: the VSI being configured
4131 **/
4132static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4133{
4134 int q_idx;
4135
4136 if (!vsi->netdev)
4137 return;
4138
4139 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4140 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4141}
4142
4143/**
4144 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4145 * @vsi: the VSI being configured
4146 **/
4147static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4148{
4149 int q_idx;
4150
4151 if (!vsi->netdev)
4152 return;
4153
4154 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4155 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4156}
4157
90ef8d47
SN		 4158/**
4159 * i40e_vsi_close - Shut down a VSI
4160 * @vsi: the vsi to be quelled
4161 **/
4162static void i40e_vsi_close(struct i40e_vsi *vsi)
4163{
e3219ce6
ASJ		 4164 bool reset = false;
4165
90ef8d47
SN		 4166 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4167 i40e_down(vsi);
4168 i40e_vsi_free_irq(vsi);
4169 i40e_vsi_free_tx_resources(vsi);
4170 i40e_vsi_free_rx_resources(vsi);
92faef85 4171 vsi->current_netdev_flags = 0;
e3219ce6
ASJ		 4172 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4173 reset = true;
4174 i40e_notify_client_of_netdev_close(vsi, reset);
90ef8d47
SN		 4175}
4176
41c445ff
JB		 4177/**
4178 * i40e_quiesce_vsi - Pause a given VSI
4179 * @vsi: the VSI being paused
4180 **/
4181static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4182{
4183 if (test_bit(__I40E_DOWN, &vsi->state))
4184 return;
4185
d341b7a5
NP		 4186 /* No need to disable FCoE VSI when Tx suspended */
4187 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4188 vsi->type == I40E_VSI_FCOE) {
4189 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4190 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4191 return;
4192 }
4193
41c445ff 4194 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4195 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4196 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4197 else
90ef8d47 4198 i40e_vsi_close(vsi);
41c445ff
JB		 4199}
4200
4201/**
4202 * i40e_unquiesce_vsi - Resume a given VSI
4203 * @vsi: the VSI being resumed
4204 **/
4205static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4206{
4207 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4208 return;
4209
4210 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4211 if (vsi->netdev && netif_running(vsi->netdev))
4212 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4213 else
8276f757 4214 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4215}
4216
4217/**
4218 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4219 * @pf: the PF
4220 **/
4221static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4222{
4223 int v;
4224
505682cd 4225 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4226 if (pf->vsi[v])
4227 i40e_quiesce_vsi(pf->vsi[v]);
4228 }
4229}
4230
4231/**
4232 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4233 * @pf: the PF
4234 **/
4235static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4236{
4237 int v;
4238
505682cd 4239 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4240 if (pf->vsi[v])
4241 i40e_unquiesce_vsi(pf->vsi[v]);
4242 }
4243}
4244
69129dc3
NP		 4245#ifdef CONFIG_I40E_DCB
4246/**
3fe06f41 4247 * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled
69129dc3
NP		 4248 * @vsi: the VSI being configured
4249 *
3fe06f41 4250 * This function waits for the given VSI's queues to be disabled.
69129dc3 4251 **/
3fe06f41 4252static int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi)
69129dc3
NP		 4253{
4254 struct i40e_pf *pf = vsi->back;
4255 int i, pf_q, ret;
4256
4257 pf_q = vsi->base_queue;
4258 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4259 /* Check and wait for the disable status of the queue */
4260 ret = i40e_pf_txq_wait(pf, pf_q, false);
4261 if (ret) {
4262 dev_info(&pf->pdev->dev,
fb43201f
SN		 4263 "VSI seid %d Tx ring %d disable timeout\n",
4264 vsi->seid, pf_q);
69129dc3
NP		 4265 return ret;
4266 }
4267 }
4268
3fe06f41
NP		 4269 pf_q = vsi->base_queue;
4270 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4271 /* Check and wait for the disable status of the queue */
4272 ret = i40e_pf_rxq_wait(pf, pf_q, false);
4273 if (ret) {
4274 dev_info(&pf->pdev->dev,
4275 "VSI seid %d Rx ring %d disable timeout\n",
4276 vsi->seid, pf_q);
4277 return ret;
4278 }
4279 }
4280
69129dc3
NP		 4281 return 0;
4282}
4283
4284/**
3fe06f41 4285 * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled
69129dc3
NP		 4286 * @pf: the PF
4287 *
3fe06f41 4288 * This function waits for the queues to be in disabled state for all the
69129dc3
NP		 4289 * VSIs that are managed by this PF.
4290 **/
3fe06f41 4291static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf)
69129dc3
NP		 4292{
4293 int v, ret = 0;
4294
4295 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4296 /* No need to wait for FCoE VSI queues */
4297 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
3fe06f41 4298 ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]);
69129dc3
NP		 4299 if (ret)
4300 break;
4301 }
4302 }
4303
4304 return ret;
4305}
4306
4307#endif
b03a8c1f
KP		 4308
4309/**
4310 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4311 * @q_idx: TX queue number
4312 * @vsi: Pointer to VSI struct
4313 *
4314 * This function checks specified queue for given VSI. Detects hung condition.
4315 * Sets hung bit since it is two step process. Before next run of service task
4316 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4317 * hung condition remain unchanged and during subsequent run, this function
4318 * issues SW interrupt to recover from hung condition.
4319 **/
4320static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4321{
4322 struct i40e_ring *tx_ring = NULL;
4323 struct i40e_pf *pf;
dd353109 4324 u32 head, val, tx_pending_hw;
b03a8c1f
KP		 4325 int i;
4326
4327 pf = vsi->back;
4328
4329 /* now that we have an index, find the tx_ring struct */
4330 for (i = 0; i < vsi->num_queue_pairs; i++) {
4331 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4332 if (q_idx == vsi->tx_rings[i]->queue_index) {
4333 tx_ring = vsi->tx_rings[i];
4334 break;
4335 }
4336 }
4337 }
4338
4339 if (!tx_ring)
4340 return;
4341
4342 /* Read interrupt register */
4343 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4344 val = rd32(&pf->hw,
4345 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4346 tx_ring->vsi->base_vector - 1));
4347 else
4348 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4349
4350 head = i40e_get_head(tx_ring);
4351
dd353109 4352 tx_pending_hw = i40e_get_tx_pending(tx_ring, false);
b03a8c1f 4353
9c6c1259
KP		 4354 /* HW is done executing descriptors, updated HEAD write back,
4355 * but SW hasn't processed those descriptors. If interrupt is
4356 * not generated from this point ON, it could result into
4357 * dev_watchdog detecting timeout on those netdev_queue,
4358 * hence proactively trigger SW interrupt.
b03a8c1f 4359 */
dd353109 4360 if (tx_pending_hw && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
9c6c1259
KP		 4361 /* NAPI Poll didn't run and clear since it was set */
4362 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4363 &tx_ring->q_vector->hung_detected)) {
dd353109
ASJ		 4364 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending_hw: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4365 vsi->seid, q_idx, tx_pending_hw,
9c6c1259
KP		 4366 tx_ring->next_to_clean, head,
4367 tx_ring->next_to_use,
4368 readl(tx_ring->tail));
4369 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4370 vsi->seid, q_idx, val);
4371 i40e_force_wb(vsi, tx_ring->q_vector);
4372 } else {
4373 /* First Chance - detected possible hung */
4374 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4375 &tx_ring->q_vector->hung_detected);
4376 }
4377 }
dd353109
ASJ		 4378
4379 /* This is the case where we have interrupts missing,
4380 * so the tx_pending in HW will most likely be 0, but we
4381 * will have tx_pending in SW since the WB happened but the
4382 * interrupt got lost.
4383 */
4384 if ((!tx_pending_hw) && i40e_get_tx_pending(tx_ring, true) &&
4385 (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
4386 if (napi_reschedule(&tx_ring->q_vector->napi))
4387 tx_ring->tx_stats.tx_lost_interrupt++;
4388 }
b03a8c1f
KP		 4389}
4390
4391/**
4392 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4393 * @pf: pointer to PF struct
4394 *
4395 * LAN VSI has netdev and netdev has TX queues. This function is to check
4396 * each of those TX queues if they are hung, trigger recovery by issuing
4397 * SW interrupt.
4398 **/
4399static void i40e_detect_recover_hung(struct i40e_pf *pf)
4400{
4401 struct net_device *netdev;
4402 struct i40e_vsi *vsi;
4403 int i;
4404
4405 /* Only for LAN VSI */
4406 vsi = pf->vsi[pf->lan_vsi];
4407
4408 if (!vsi)
4409 return;
4410
4411 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4412 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4413 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4414 return;
4415
4416 /* Make sure type is MAIN VSI */
4417 if (vsi->type != I40E_VSI_MAIN)
4418 return;
4419
4420 netdev = vsi->netdev;
4421 if (!netdev)
4422 return;
4423
4424 /* Bail out if netif_carrier is not OK */
4425 if (!netif_carrier_ok(netdev))
4426 return;
4427
4428 /* Go thru' TX queues for netdev */
4429 for (i = 0; i < netdev->num_tx_queues; i++) {
4430 struct netdev_queue *q;
4431
4432 q = netdev_get_tx_queue(netdev, i);
4433 if (q)
4434 i40e_detect_recover_hung_queue(i, vsi);
4435 }
4436}
4437
63d7e5a4
NP		 4438/**
4439 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4440 * @pf: pointer to PF
63d7e5a4
NP		 4441 *
4442 * Get TC map for ISCSI PF type that will include iSCSI TC
4443 * and LAN TC.
4444 **/
4445static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4446{
4447 struct i40e_dcb_app_priority_table app;
4448 struct i40e_hw *hw = &pf->hw;
4449 u8 enabled_tc = 1; /* TC0 is always enabled */
4450 u8 tc, i;
4451 /* Get the iSCSI APP TLV */
4452 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4453
4454 for (i = 0; i < dcbcfg->numapps; i++) {
4455 app = dcbcfg->app[i];
4456 if (app.selector == I40E_APP_SEL_TCPIP &&
4457 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4458 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4459 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4460 break;
4461 }
4462 }
4463
4464 return enabled_tc;
4465}
4466
41c445ff
JB		 4467/**
4468 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4469 * @dcbcfg: the corresponding DCBx configuration structure
4470 *
4471 * Return the number of TCs from given DCBx configuration
4472 **/
4473static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4474{
078b5876
JB		 4475 u8 num_tc = 0;
4476 int i;
41c445ff
JB		 4477
4478 /* Scan the ETS Config Priority Table to find
4479 * traffic class enabled for a given priority
4480 * and use the traffic class index to get the
4481 * number of traffic classes enabled
4482 */
4483 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4484 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4485 num_tc = dcbcfg->etscfg.prioritytable[i];
4486 }
4487
4488 /* Traffic class index starts from zero so
4489 * increment to return the actual count
4490 */
078b5876 4491 return num_tc + 1;
41c445ff
JB		 4492}
4493
4494/**
4495 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4496 * @dcbcfg: the corresponding DCBx configuration structure
4497 *
4498 * Query the current DCB configuration and return the number of
4499 * traffic classes enabled from the given DCBX config
4500 **/
4501static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4502{
4503 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4504 u8 enabled_tc = 1;
4505 u8 i;
4506
4507 for (i = 0; i < num_tc; i++)
41a1d04b 4508 enabled_tc |= BIT(i);
41c445ff
JB		 4509
4510 return enabled_tc;
4511}
4512
4513/**
4514 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4515 * @pf: PF being queried
4516 *
4517 * Return number of traffic classes enabled for the given PF
4518 **/
4519static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4520{
4521 struct i40e_hw *hw = &pf->hw;
4522 u8 i, enabled_tc;
4523 u8 num_tc = 0;
4524 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4525
4526 /* If DCB is not enabled then always in single TC */
4527 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4528 return 1;
4529
63d7e5a4
NP		 4530 /* SFP mode will be enabled for all TCs on port */
4531 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4532 return i40e_dcb_get_num_tc(dcbcfg);
4533
41c445ff 4534 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4535 if (pf->hw.func_caps.iscsi)
4536 enabled_tc = i40e_get_iscsi_tc_map(pf);
4537 else
fc51de96 4538 return 1; /* Only TC0 */
41c445ff 4539
63d7e5a4
NP		 4540 /* At least have TC0 */
4541 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4542 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4543 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4544 num_tc++;
4545 }
4546 return num_tc;
41c445ff
JB		 4547}
4548
4549/**
4550 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4551 * @pf: PF being queried
4552 *
4553 * Return a bitmap for first enabled traffic class for this PF.
4554 **/
4555static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4556{
4557 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4558 u8 i = 0;
4559
4560 if (!enabled_tc)
4561 return 0x1; /* TC0 */
4562
4563 /* Find the first enabled TC */
4564 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4565 if (enabled_tc & BIT(i))
41c445ff
JB		 4566 break;
4567 }
4568
41a1d04b 4569 return BIT(i);
41c445ff
JB		 4570}
4571
4572/**
4573 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4574 * @pf: PF being queried
4575 *
4576 * Return a bitmap for enabled traffic classes for this PF.
4577 **/
4578static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4579{
4580 /* If DCB is not enabled for this PF then just return default TC */
4581 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4582 return i40e_pf_get_default_tc(pf);
4583
41c445ff 4584 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4585 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4586 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4587
fc51de96 4588 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4589 if (pf->hw.func_caps.iscsi)
4590 return i40e_get_iscsi_tc_map(pf);
4591 else
fc51de96 4592 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4593}
4594
4595/**
4596 * i40e_vsi_get_bw_info - Query VSI BW Information
4597 * @vsi: the VSI being queried
4598 *
4599 * Returns 0 on success, negative value on failure
4600 **/
4601static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4602{
4603 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4604 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4605 struct i40e_pf *pf = vsi->back;
4606 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4607 i40e_status ret;
41c445ff 4608 u32 tc_bw_max;
41c445ff
JB		 4609 int i;
4610
4611 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4612 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4613 if (ret) {
41c445ff 4614 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4615 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4616 i40e_stat_str(&pf->hw, ret),
4617 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4618 return -EINVAL;
41c445ff
JB		 4619 }
4620
4621 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4622 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4623 NULL);
4624 if (ret) {
41c445ff 4625 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4626 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4627 i40e_stat_str(&pf->hw, ret),
4628 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4629 return -EINVAL;
41c445ff
JB		 4630 }
4631
4632 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4633 dev_info(&pf->pdev->dev,
4634 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4635 bw_config.tc_valid_bits,
4636 bw_ets_config.tc_valid_bits);
4637 /* Still continuing */
4638 }
4639
4640 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4641 vsi->bw_max_quanta = bw_config.max_bw;
4642 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4643 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4644 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4645 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4646 vsi->bw_ets_limit_credits[i] =
4647 le16_to_cpu(bw_ets_config.credits[i]);
4648 /* 3 bits out of 4 for each TC */
4649 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4650 }
078b5876 4651
dcae29be 4652 return 0;
41c445ff
JB		 4653}
4654
4655/**
4656 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4657 * @vsi: the VSI being configured
4658 * @enabled_tc: TC bitmap
4659 * @bw_credits: BW shared credits per TC
4660 *
4661 * Returns 0 on success, negative value on failure
4662 **/
dcae29be 4663static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4664 u8 *bw_share)
4665{
4666 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4667 i40e_status ret;
dcae29be 4668 int i;
41c445ff
JB		 4669
4670 bw_data.tc_valid_bits = enabled_tc;
4671 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4672 bw_data.tc_bw_credits[i] = bw_share[i];
4673
f1c7e72e
SN		 4674 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4675 NULL);
4676 if (ret) {
41c445ff 4677 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4678 "AQ command Config VSI BW allocation per TC failed = %d\n",
4679 vsi->back->hw.aq.asq_last_status);
dcae29be 4680 return -EINVAL;
41c445ff
JB		 4681 }
4682
4683 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4684 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4685
dcae29be 4686 return 0;
41c445ff
JB		 4687}
4688
4689/**
4690 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4691 * @vsi: the VSI being configured
4692 * @enabled_tc: TC map to be enabled
4693 *
4694 **/
4695static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4696{
4697 struct net_device *netdev = vsi->netdev;
4698 struct i40e_pf *pf = vsi->back;
4699 struct i40e_hw *hw = &pf->hw;
4700 u8 netdev_tc = 0;
4701 int i;
4702 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4703
4704 if (!netdev)
4705 return;
4706
4707 if (!enabled_tc) {
4708 netdev_reset_tc(netdev);
4709 return;
4710 }
4711
4712 /* Set up actual enabled TCs on the VSI */
4713 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4714 return;
4715
4716 /* set per TC queues for the VSI */
4717 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4718 /* Only set TC queues for enabled tcs
4719 *
4720 * e.g. For a VSI that has TC0 and TC3 enabled the
4721 * enabled_tc bitmap would be 0x00001001; the driver
4722 * will set the numtc for netdev as 2 that will be
4723 * referenced by the netdev layer as TC 0 and 1.
4724 */
75f5cea9 4725 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4726 netdev_set_tc_queue(netdev,
4727 vsi->tc_config.tc_info[i].netdev_tc,
4728 vsi->tc_config.tc_info[i].qcount,
4729 vsi->tc_config.tc_info[i].qoffset);
4730 }
4731
4732 /* Assign UP2TC map for the VSI */
4733 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4734 /* Get the actual TC# for the UP */
4735 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4736 /* Get the mapped netdev TC# for the UP */
4737 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4738 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4739 }
4740}
4741
4742/**
4743 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4744 * @vsi: the VSI being configured
4745 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4746 **/
4747static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4748 struct i40e_vsi_context *ctxt)
4749{
4750 /* copy just the sections touched not the entire info
4751 * since not all sections are valid as returned by
4752 * update vsi params
4753 */
4754 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4755 memcpy(&vsi->info.queue_mapping,
4756 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4757 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4758 sizeof(vsi->info.tc_mapping));
4759}
4760
4761/**
4762 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4763 * @vsi: VSI to be configured
4764 * @enabled_tc: TC bitmap
4765 *
4766 * This configures a particular VSI for TCs that are mapped to the
4767 * given TC bitmap. It uses default bandwidth share for TCs across
4768 * VSIs to configure TC for a particular VSI.
4769 *
4770 * NOTE:
4771 * It is expected that the VSI queues have been quisced before calling
4772 * this function.
4773 **/
4774static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4775{
4776 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4777 struct i40e_vsi_context ctxt;
4778 int ret = 0;
4779 int i;
4780
4781 /* Check if enabled_tc is same as existing or new TCs */
4782 if (vsi->tc_config.enabled_tc == enabled_tc)
4783 return ret;
4784
4785 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4786 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4787 if (enabled_tc & BIT(i))
41c445ff
JB		 4788 bw_share[i] = 1;
4789 }
4790
4791 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4792 if (ret) {
4793 dev_info(&vsi->back->pdev->dev,
4794 "Failed configuring TC map %d for VSI %d\n",
4795 enabled_tc, vsi->seid);
4796 goto out;
4797 }
4798
4799 /* Update Queue Pairs Mapping for currently enabled UPs */
4800 ctxt.seid = vsi->seid;
4801 ctxt.pf_num = vsi->back->hw.pf_id;
4802 ctxt.vf_num = 0;
4803 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4804 ctxt.info = vsi->info;
41c445ff
JB		 4805 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4806
e3219ce6
ASJ		 4807 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
4808 ctxt.info.valid_sections |=
4809 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
4810 ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
4811 }
4812
41c445ff
JB		 4813 /* Update the VSI after updating the VSI queue-mapping information */
4814 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4815 if (ret) {
4816 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4817 "Update vsi tc config failed, err %s aq_err %s\n",
4818 i40e_stat_str(&vsi->back->hw, ret),
4819 i40e_aq_str(&vsi->back->hw,
4820 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4821 goto out;
4822 }
4823 /* update the local VSI info with updated queue map */
4824 i40e_vsi_update_queue_map(vsi, &ctxt);
4825 vsi->info.valid_sections = 0;
4826
4827 /* Update current VSI BW information */
4828 ret = i40e_vsi_get_bw_info(vsi);
4829 if (ret) {
4830 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4831 "Failed updating vsi bw info, err %s aq_err %s\n",
4832 i40e_stat_str(&vsi->back->hw, ret),
4833 i40e_aq_str(&vsi->back->hw,
4834 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4835 goto out;
4836 }
4837
4838 /* Update the netdev TC setup */
4839 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4840out:
4841 return ret;
4842}
4843
4e3b35b0
NP		 4844/**
4845 * i40e_veb_config_tc - Configure TCs for given VEB
4846 * @veb: given VEB
4847 * @enabled_tc: TC bitmap
4848 *
4849 * Configures given TC bitmap for VEB (switching) element
4850 **/
4851int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4852{
4853 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4854 struct i40e_pf *pf = veb->pf;
4855 int ret = 0;
4856 int i;
4857
4858 /* No TCs or already enabled TCs just return */
4859 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4860 return ret;
4861
4862 bw_data.tc_valid_bits = enabled_tc;
4863 /* bw_data.absolute_credits is not set (relative) */
4864
4865 /* Enable ETS TCs with equal BW Share for now */
4866 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4867 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4868 bw_data.tc_bw_share_credits[i] = 1;
4869 }
4870
4871 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4872 &bw_data, NULL);
4873 if (ret) {
4874 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4875 "VEB bw config failed, err %s aq_err %s\n",
4876 i40e_stat_str(&pf->hw, ret),
4877 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4878 goto out;
4879 }
4880
4881 /* Update the BW information */
4882 ret = i40e_veb_get_bw_info(veb);
4883 if (ret) {
4884 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4885 "Failed getting veb bw config, err %s aq_err %s\n",
4886 i40e_stat_str(&pf->hw, ret),
4887 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4888 }
4889
4890out:
4891 return ret;
4892}
4893
4894#ifdef CONFIG_I40E_DCB
4895/**
4896 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4897 * @pf: PF struct
4898 *
4899 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4900 * the caller would've quiesce all the VSIs before calling
4901 * this function
4902 **/
4903static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4904{
4905 u8 tc_map = 0;
4906 int ret;
4907 u8 v;
4908
4909 /* Enable the TCs available on PF to all VEBs */
4910 tc_map = i40e_pf_get_tc_map(pf);
4911 for (v = 0; v < I40E_MAX_VEB; v++) {
4912 if (!pf->veb[v])
4913 continue;
4914 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4915 if (ret) {
4916 dev_info(&pf->pdev->dev,
4917 "Failed configuring TC for VEB seid=%d\n",
4918 pf->veb[v]->seid);
4919 /* Will try to configure as many components */
4920 }
4921 }
4922
4923 /* Update each VSI */
505682cd 4924 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4925 if (!pf->vsi[v])
4926 continue;
4927
4928 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4929#ifdef I40E_FCOE
4930 * - For FCoE VSI only enable the TC configured
4931 * as per the APP TLV
4932#endif
4e3b35b0
NP		 4933 * - For all others keep them at TC0 for now
4934 */
4935 if (v == pf->lan_vsi)
4936 tc_map = i40e_pf_get_tc_map(pf);
4937 else
4938 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4939#ifdef I40E_FCOE
4940 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4941 tc_map = i40e_get_fcoe_tc_map(pf);
4942#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4943
4944 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4945 if (ret) {
4946 dev_info(&pf->pdev->dev,
4947 "Failed configuring TC for VSI seid=%d\n",
4948 pf->vsi[v]->seid);
4949 /* Will try to configure as many components */
4950 } else {
0672a091
NP		 4951 /* Re-configure VSI vectors based on updated TC map */
4952 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4953 if (pf->vsi[v]->netdev)
4954 i40e_dcbnl_set_all(pf->vsi[v]);
4955 }
e3219ce6 4956 i40e_notify_client_of_l2_param_changes(pf->vsi[v]);
4e3b35b0
NP		 4957 }
4958}
4959
2fd75f31
NP		 4960/**
4961 * i40e_resume_port_tx - Resume port Tx
4962 * @pf: PF struct
4963 *
4964 * Resume a port's Tx and issue a PF reset in case of failure to
4965 * resume.
4966 **/
4967static int i40e_resume_port_tx(struct i40e_pf *pf)
4968{
4969 struct i40e_hw *hw = &pf->hw;
4970 int ret;
4971
4972 ret = i40e_aq_resume_port_tx(hw, NULL);
4973 if (ret) {
4974 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4975 "Resume Port Tx failed, err %s aq_err %s\n",
4976 i40e_stat_str(&pf->hw, ret),
4977 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4978 /* Schedule PF reset to recover */
4979 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4980 i40e_service_event_schedule(pf);
4981 }
4982
4983 return ret;
4984}
4985
4e3b35b0
NP		 4986/**
4987 * i40e_init_pf_dcb - Initialize DCB configuration
4988 * @pf: PF being configured
4989 *
4990 * Query the current DCB configuration and cache it
4991 * in the hardware structure
4992 **/
4993static int i40e_init_pf_dcb(struct i40e_pf *pf)
4994{
4995 struct i40e_hw *hw = &pf->hw;
4996 int err = 0;
4997
025b4a54 4998 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
f1bbad33 4999 if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT)
025b4a54
ASJ		 5000 goto out;
5001
4e3b35b0
NP		 5002 /* Get the initial DCB configuration */
5003 err = i40e_init_dcb(hw);
5004 if (!err) {
5005 /* Device/Function is not DCBX capable */
5006 if ((!hw->func_caps.dcb) ||
5007 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5008 dev_info(&pf->pdev->dev,
5009 "DCBX offload is not supported or is disabled for this PF.\n");
5010
5011 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5012 goto out;
5013
5014 } else {
5015 /* When status is not DISABLED then DCBX in FW */
5016 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5017 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5018
5019 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5020 /* Enable DCB tagging only when more than one TC */
5021 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5022 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5023 dev_dbg(&pf->pdev->dev,
5024 "DCBX offload is supported for this PF.\n");
4e3b35b0 5025 }
014269ff 5026 } else {
aebfc816 5027 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5028 "Query for DCB configuration failed, err %s aq_err %s\n",
5029 i40e_stat_str(&pf->hw, err),
5030 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5031 }
5032
5033out:
5034 return err;
5035}
5036#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5037#define SPEED_SIZE 14
5038#define FC_SIZE 8
5039/**
5040 * i40e_print_link_message - print link up or down
5041 * @vsi: the VSI for which link needs a message
5042 */
c156f856 5043void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5044{
a9165490
SN		 5045 char *speed = "Unknown";
5046 char *fc = "Unknown";
cf05ed08 5047
c156f856
MJ		 5048 if (vsi->current_isup == isup)
5049 return;
5050 vsi->current_isup = isup;
cf05ed08
JB		 5051 if (!isup) {
5052 netdev_info(vsi->netdev, "NIC Link is Down\n");
5053 return;
5054 }
5055
148c2d80
GR		 5056 /* Warn user if link speed on NPAR enabled partition is not at
5057 * least 10GB
5058 */
5059 if (vsi->back->hw.func_caps.npar_enable &&
5060 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5061 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5062 netdev_warn(vsi->netdev,
5063 "The partition detected link speed that is less than 10Gbps\n");
5064
cf05ed08
JB		 5065 switch (vsi->back->hw.phy.link_info.link_speed) {
5066 case I40E_LINK_SPEED_40GB:
a9165490 5067 speed = "40 G";
cf05ed08 5068 break;
ae24b409 5069 case I40E_LINK_SPEED_20GB:
a9165490 5070 speed = "20 G";
ae24b409 5071 break;
cf05ed08 5072 case I40E_LINK_SPEED_10GB:
a9165490 5073 speed = "10 G";
cf05ed08
JB		 5074 break;
5075 case I40E_LINK_SPEED_1GB:
a9165490 5076 speed = "1000 M";
cf05ed08 5077 break;
5960d33f 5078 case I40E_LINK_SPEED_100MB:
a9165490 5079 speed = "100 M";
5960d33f 5080 break;
cf05ed08
JB		 5081 default:
5082 break;
5083 }
5084
5085 switch (vsi->back->hw.fc.current_mode) {
5086 case I40E_FC_FULL:
a9165490 5087 fc = "RX/TX";
cf05ed08
JB		 5088 break;
5089 case I40E_FC_TX_PAUSE:
a9165490 5090 fc = "TX";
cf05ed08
JB		 5091 break;
5092 case I40E_FC_RX_PAUSE:
a9165490 5093 fc = "RX";
cf05ed08
JB		 5094 break;
5095 default:
a9165490 5096 fc = "None";
cf05ed08
JB		 5097 break;
5098 }
5099
a9165490 5100 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5101 speed, fc);
5102}
4e3b35b0 5103
41c445ff
JB		 5104/**
5105 * i40e_up_complete - Finish the last steps of bringing up a connection
5106 * @vsi: the VSI being configured
5107 **/
5108static int i40e_up_complete(struct i40e_vsi *vsi)
5109{
5110 struct i40e_pf *pf = vsi->back;
5111 int err;
5112
5113 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5114 i40e_vsi_configure_msix(vsi);
5115 else
5116 i40e_configure_msi_and_legacy(vsi);
5117
5118 /* start rings */
5119 err = i40e_vsi_control_rings(vsi, true);
5120 if (err)
5121 return err;
5122
5123 clear_bit(__I40E_DOWN, &vsi->state);
5124 i40e_napi_enable_all(vsi);
5125 i40e_vsi_enable_irq(vsi);
5126
5127 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5128 (vsi->netdev)) {
cf05ed08 5129 i40e_print_link_message(vsi, true);
41c445ff
JB		 5130 netif_tx_start_all_queues(vsi->netdev);
5131 netif_carrier_on(vsi->netdev);
6d779b41 5132 } else if (vsi->netdev) {
cf05ed08 5133 i40e_print_link_message(vsi, false);
7b592f61
CW		 5134 /* need to check for qualified module here*/
5135 if ((pf->hw.phy.link_info.link_info &
5136 I40E_AQ_MEDIA_AVAILABLE) &&
5137 (!(pf->hw.phy.link_info.an_info &
5138 I40E_AQ_QUALIFIED_MODULE)))
5139 netdev_err(vsi->netdev,
5140 "the driver failed to link because an unqualified module was detected.");
41c445ff 5141 }
ca64fa4e
ASJ		 5142
5143 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5144 if (vsi->type == I40E_VSI_FDIR) {
5145 /* reset fd counters */
5146 pf->fd_add_err = pf->fd_atr_cnt = 0;
5147 if (pf->fd_tcp_rule > 0) {
5148 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5149 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5150 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5151 pf->fd_tcp_rule = 0;
5152 }
ca64fa4e 5153 i40e_fdir_filter_restore(vsi);
1e1be8f6 5154 }
e3219ce6
ASJ		 5155
5156 /* On the next run of the service_task, notify any clients of the new
5157 * opened netdev
5158 */
5159 pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED;
41c445ff
JB		 5160 i40e_service_event_schedule(pf);
5161
5162 return 0;
5163}
5164
5165/**
5166 * i40e_vsi_reinit_locked - Reset the VSI
5167 * @vsi: the VSI being configured
5168 *
5169 * Rebuild the ring structs after some configuration
5170 * has changed, e.g. MTU size.
5171 **/
5172static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5173{
5174 struct i40e_pf *pf = vsi->back;
5175
5176 WARN_ON(in_interrupt());
5177 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5178 usleep_range(1000, 2000);
5179 i40e_down(vsi);
5180
5181 /* Give a VF some time to respond to the reset. The
5182 * two second wait is based upon the watchdog cycle in
5183 * the VF driver.
5184 */
5185 if (vsi->type == I40E_VSI_SRIOV)
5186 msleep(2000);
5187 i40e_up(vsi);
5188 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5189}
5190
5191/**
5192 * i40e_up - Bring the connection back up after being down
5193 * @vsi: the VSI being configured
5194 **/
5195int i40e_up(struct i40e_vsi *vsi)
5196{
5197 int err;
5198
5199 err = i40e_vsi_configure(vsi);
5200 if (!err)
5201 err = i40e_up_complete(vsi);
5202
5203 return err;
5204}
5205
5206/**
5207 * i40e_down - Shutdown the connection processing
5208 * @vsi: the VSI being stopped
5209 **/
5210void i40e_down(struct i40e_vsi *vsi)
5211{
5212 int i;
5213
5214 /* It is assumed that the caller of this function
5215 * sets the vsi->state __I40E_DOWN bit.
5216 */
5217 if (vsi->netdev) {
5218 netif_carrier_off(vsi->netdev);
5219 netif_tx_disable(vsi->netdev);
5220 }
5221 i40e_vsi_disable_irq(vsi);
5222 i40e_vsi_control_rings(vsi, false);
5223 i40e_napi_disable_all(vsi);
5224
5225 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5226 i40e_clean_tx_ring(vsi->tx_rings[i]);
5227 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5228 }
5229}
5230
5231/**
5232 * i40e_setup_tc - configure multiple traffic classes
5233 * @netdev: net device to configure
5234 * @tc: number of traffic classes to enable
5235 **/
5236static int i40e_setup_tc(struct net_device *netdev, u8 tc)
5237{
5238 struct i40e_netdev_priv *np = netdev_priv(netdev);
5239 struct i40e_vsi *vsi = np->vsi;
5240 struct i40e_pf *pf = vsi->back;
5241 u8 enabled_tc = 0;
5242 int ret = -EINVAL;
5243 int i;
5244
5245 /* Check if DCB enabled to continue */
5246 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5247 netdev_info(netdev, "DCB is not enabled for adapter\n");
5248 goto exit;
5249 }
5250
5251 /* Check if MFP enabled */
5252 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5253 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5254 goto exit;
5255 }
5256
5257 /* Check whether tc count is within enabled limit */
5258 if (tc > i40e_pf_get_num_tc(pf)) {
5259 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5260 goto exit;
5261 }
5262
5263 /* Generate TC map for number of tc requested */
5264 for (i = 0; i < tc; i++)
75f5cea9 5265 enabled_tc |= BIT(i);
41c445ff
JB		 5266
5267 /* Requesting same TC configuration as already enabled */
5268 if (enabled_tc == vsi->tc_config.enabled_tc)
5269 return 0;
5270
5271 /* Quiesce VSI queues */
5272 i40e_quiesce_vsi(vsi);
5273
5274 /* Configure VSI for enabled TCs */
5275 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5276 if (ret) {
5277 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5278 vsi->seid);
5279 goto exit;
5280 }
5281
5282 /* Unquiesce VSI */
5283 i40e_unquiesce_vsi(vsi);
5284
5285exit:
5286 return ret;
5287}
5288
e4c6734e 5289#ifdef I40E_FCOE
16e5cc64
JF		 5290int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5291 struct tc_to_netdev *tc)
e4c6734e 5292#else
16e5cc64
JF		 5293static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5294 struct tc_to_netdev *tc)
e4c6734e
JF		 5295#endif
5296{
16e5cc64 5297 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
e4c6734e 5298 return -EINVAL;
16e5cc64 5299 return i40e_setup_tc(netdev, tc->tc);
e4c6734e
JF		 5300}
5301
41c445ff
JB		 5302/**
5303 * i40e_open - Called when a network interface is made active
5304 * @netdev: network interface device structure
5305 *
5306 * The open entry point is called when a network interface is made
5307 * active by the system (IFF_UP). At this point all resources needed
5308 * for transmit and receive operations are allocated, the interrupt
5309 * handler is registered with the OS, the netdev watchdog subtask is
5310 * enabled, and the stack is notified that the interface is ready.
5311 *
5312 * Returns 0 on success, negative value on failure
5313 **/
38e00438 5314int i40e_open(struct net_device *netdev)
41c445ff
JB		 5315{
5316 struct i40e_netdev_priv *np = netdev_priv(netdev);
5317 struct i40e_vsi *vsi = np->vsi;
5318 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5319 int err;
5320
4eb3f768
SN		 5321 /* disallow open during test or if eeprom is broken */
5322 if (test_bit(__I40E_TESTING, &pf->state) ||
5323 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5324 return -EBUSY;
5325
5326 netif_carrier_off(netdev);
5327
6c167f58
EK		 5328 err = i40e_vsi_open(vsi);
5329 if (err)
5330 return err;
5331
059dab69
JB		 5332 /* configure global TSO hardware offload settings */
5333 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5334 TCP_FLAG_FIN) >> 16);
5335 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5336 TCP_FLAG_FIN |
5337 TCP_FLAG_CWR) >> 16);
5338 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5339
06a5f7f1 5340 udp_tunnel_get_rx_info(netdev);
e3219ce6
ASJ		 5341 i40e_notify_client_of_netdev_open(vsi);
5342
6c167f58
EK		 5343 return 0;
5344}
5345
5346/**
5347 * i40e_vsi_open -
5348 * @vsi: the VSI to open
5349 *
5350 * Finish initialization of the VSI.
5351 *
5352 * Returns 0 on success, negative value on failure
5353 **/
5354int i40e_vsi_open(struct i40e_vsi *vsi)
5355{
5356 struct i40e_pf *pf = vsi->back;
b294ac70 5357 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5358 int err;
5359
41c445ff
JB		 5360 /* allocate descriptors */
5361 err = i40e_vsi_setup_tx_resources(vsi);
5362 if (err)
5363 goto err_setup_tx;
5364 err = i40e_vsi_setup_rx_resources(vsi);
5365 if (err)
5366 goto err_setup_rx;
5367
5368 err = i40e_vsi_configure(vsi);
5369 if (err)
5370 goto err_setup_rx;
5371
c22e3c6c
SN		 5372 if (vsi->netdev) {
5373 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5374 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5375 err = i40e_vsi_request_irq(vsi, int_name);
5376 if (err)
5377 goto err_setup_rx;
41c445ff 5378
c22e3c6c
SN		 5379 /* Notify the stack of the actual queue counts. */
5380 err = netif_set_real_num_tx_queues(vsi->netdev,
5381 vsi->num_queue_pairs);
5382 if (err)
5383 goto err_set_queues;
25946ddb 5384
c22e3c6c
SN		 5385 err = netif_set_real_num_rx_queues(vsi->netdev,
5386 vsi->num_queue_pairs);
5387 if (err)
5388 goto err_set_queues;
8a9eb7d3
SN		 5389
5390 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5391 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5392 dev_driver_string(&pf->pdev->dev),
5393 dev_name(&pf->pdev->dev));
8a9eb7d3 5394 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5395
c22e3c6c 5396 } else {
ce9ccb17 5397 err = -EINVAL;
6c167f58
EK		 5398 goto err_setup_rx;
5399 }
25946ddb 5400
41c445ff
JB		 5401 err = i40e_up_complete(vsi);
5402 if (err)
5403 goto err_up_complete;
5404
41c445ff
JB		 5405 return 0;
5406
5407err_up_complete:
5408 i40e_down(vsi);
25946ddb 5409err_set_queues:
41c445ff
JB		 5410 i40e_vsi_free_irq(vsi);
5411err_setup_rx:
5412 i40e_vsi_free_rx_resources(vsi);
5413err_setup_tx:
5414 i40e_vsi_free_tx_resources(vsi);
5415 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5416 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5417
5418 return err;
5419}
5420
17a73f6b
JG		 5421/**
5422 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5423 * @pf: Pointer to PF
17a73f6b
JG		 5424 *
5425 * This function destroys the hlist where all the Flow Director
5426 * filters were saved.
5427 **/
5428static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5429{
5430 struct i40e_fdir_filter *filter;
5431 struct hlist_node *node2;
5432
5433 hlist_for_each_entry_safe(filter, node2,
5434 &pf->fdir_filter_list, fdir_node) {
5435 hlist_del(&filter->fdir_node);
5436 kfree(filter);
5437 }
5438 pf->fdir_pf_active_filters = 0;
5439}
5440
41c445ff
JB		 5441/**
5442 * i40e_close - Disables a network interface
5443 * @netdev: network interface device structure
5444 *
5445 * The close entry point is called when an interface is de-activated
5446 * by the OS. The hardware is still under the driver's control, but
5447 * this netdev interface is disabled.
5448 *
5449 * Returns 0, this is not allowed to fail
5450 **/
38e00438 5451int i40e_close(struct net_device *netdev)
41c445ff
JB		 5452{
5453 struct i40e_netdev_priv *np = netdev_priv(netdev);
5454 struct i40e_vsi *vsi = np->vsi;
5455
90ef8d47 5456 i40e_vsi_close(vsi);
41c445ff
JB		 5457
5458 return 0;
5459}
5460
5461/**
5462 * i40e_do_reset - Start a PF or Core Reset sequence
5463 * @pf: board private structure
5464 * @reset_flags: which reset is requested
5465 *
5466 * The essential difference in resets is that the PF Reset
5467 * doesn't clear the packet buffers, doesn't reset the PE
5468 * firmware, and doesn't bother the other PFs on the chip.
5469 **/
5470void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5471{
5472 u32 val;
5473
5474 WARN_ON(in_interrupt());
5475
263fc48f 5476
41c445ff 5477 /* do the biggest reset indicated */
41a1d04b 5478 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5479
5480 /* Request a Global Reset
5481 *
5482 * This will start the chip's countdown to the actual full
5483 * chip reset event, and a warning interrupt to be sent
5484 * to all PFs, including the requestor. Our handler
5485 * for the warning interrupt will deal with the shutdown
5486 * and recovery of the switch setup.
5487 */
69bfb110 5488 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5489 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5490 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5491 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5492
41a1d04b 5493 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5494
5495 /* Request a Core Reset
5496 *
5497 * Same as Global Reset, except does *not* include the MAC/PHY
5498 */
69bfb110 5499 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5500 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5501 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5502 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5503 i40e_flush(&pf->hw);
5504
41a1d04b 5505 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5506
5507 /* Request a PF Reset
5508 *
5509 * Resets only the PF-specific registers
5510 *
5511 * This goes directly to the tear-down and rebuild of
5512 * the switch, since we need to do all the recovery as
5513 * for the Core Reset.
5514 */
69bfb110 5515 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5516 i40e_handle_reset_warning(pf);
5517
41a1d04b 5518 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5519 int v;
5520
5521 /* Find the VSI(s) that requested a re-init */
5522 dev_info(&pf->pdev->dev,
5523 "VSI reinit requested\n");
505682cd 5524 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5525 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5526
41c445ff
JB		 5527 if (vsi != NULL &&
5528 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5529 i40e_vsi_reinit_locked(pf->vsi[v]);
5530 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5531 }
5532 }
41a1d04b 5533 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5534 int v;
5535
5536 /* Find the VSI(s) that needs to be brought down */
5537 dev_info(&pf->pdev->dev, "VSI down requested\n");
5538 for (v = 0; v < pf->num_alloc_vsi; v++) {
5539 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5540
b5d06f05
NP		 5541 if (vsi != NULL &&
5542 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5543 set_bit(__I40E_DOWN, &vsi->state);
5544 i40e_down(vsi);
5545 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5546 }
5547 }
41c445ff
JB		 5548 } else {
5549 dev_info(&pf->pdev->dev,
5550 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5551 }
5552}
5553
4e3b35b0
NP		 5554#ifdef CONFIG_I40E_DCB
5555/**
5556 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5557 * @pf: board private structure
5558 * @old_cfg: current DCB config
5559 * @new_cfg: new DCB config
5560 **/
5561bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5562 struct i40e_dcbx_config *old_cfg,
5563 struct i40e_dcbx_config *new_cfg)
5564{
5565 bool need_reconfig = false;
5566
5567 /* Check if ETS configuration has changed */
5568 if (memcmp(&new_cfg->etscfg,
5569 &old_cfg->etscfg,
5570 sizeof(new_cfg->etscfg))) {
5571 /* If Priority Table has changed reconfig is needed */
5572 if (memcmp(&new_cfg->etscfg.prioritytable,
5573 &old_cfg->etscfg.prioritytable,
5574 sizeof(new_cfg->etscfg.prioritytable))) {
5575 need_reconfig = true;
69bfb110 5576 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5577 }
5578
5579 if (memcmp(&new_cfg->etscfg.tcbwtable,
5580 &old_cfg->etscfg.tcbwtable,
5581 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5582 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5583
5584 if (memcmp(&new_cfg->etscfg.tsatable,
5585 &old_cfg->etscfg.tsatable,
5586 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5587 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5588 }
5589
5590 /* Check if PFC configuration has changed */
5591 if (memcmp(&new_cfg->pfc,
5592 &old_cfg->pfc,
5593 sizeof(new_cfg->pfc))) {
5594 need_reconfig = true;
69bfb110 5595 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5596 }
5597
5598 /* Check if APP Table has changed */
5599 if (memcmp(&new_cfg->app,
5600 &old_cfg->app,
3d9667a9 5601 sizeof(new_cfg->app))) {
4e3b35b0 5602 need_reconfig = true;
69bfb110 5603 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5604 }
4e3b35b0 5605
fb43201f 5606 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5607 return need_reconfig;
5608}
5609
5610/**
5611 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5612 * @pf: board private structure
5613 * @e: event info posted on ARQ
5614 **/
5615static int i40e_handle_lldp_event(struct i40e_pf *pf,
5616 struct i40e_arq_event_info *e)
5617{
5618 struct i40e_aqc_lldp_get_mib *mib =
5619 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5620 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5621 struct i40e_dcbx_config tmp_dcbx_cfg;
5622 bool need_reconfig = false;
5623 int ret = 0;
5624 u8 type;
5625
4d9b6043
NP		 5626 /* Not DCB capable or capability disabled */
5627 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5628 return ret;
5629
4e3b35b0
NP		 5630 /* Ignore if event is not for Nearest Bridge */
5631 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5632 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5633 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5634 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5635 return ret;
5636
5637 /* Check MIB Type and return if event for Remote MIB update */
5638 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5639 dev_dbg(&pf->pdev->dev,
fb43201f 5640 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5641 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5642 /* Update the remote cached instance and return */
5643 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5644 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5645 &hw->remote_dcbx_config);
5646 goto exit;
5647 }
5648
9fa61dd2 5649 /* Store the old configuration */
1a2f6248 5650 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5651
750fcbcf
NP		 5652 /* Reset the old DCBx configuration data */
5653 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5654 /* Get updated DCBX data from firmware */
5655 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5656 if (ret) {
f1c7e72e
SN		 5657 dev_info(&pf->pdev->dev,
5658 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5659 i40e_stat_str(&pf->hw, ret),
5660 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5661 goto exit;
5662 }
5663
5664 /* No change detected in DCBX configs */
750fcbcf
NP		 5665 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5666 sizeof(tmp_dcbx_cfg))) {
69bfb110 5667 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5668 goto exit;
5669 }
5670
750fcbcf
NP		 5671 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5672 &hw->local_dcbx_config);
4e3b35b0 5673
750fcbcf 5674 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5675
5676 if (!need_reconfig)
5677 goto exit;
5678
4d9b6043 5679 /* Enable DCB tagging only when more than one TC */
750fcbcf 5680 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5681 pf->flags |= I40E_FLAG_DCB_ENABLED;
5682 else
5683 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5684
69129dc3 5685 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5686 /* Reconfiguration needed quiesce all VSIs */
5687 i40e_pf_quiesce_all_vsi(pf);
5688
5689 /* Changes in configuration update VEB/VSI */
5690 i40e_dcb_reconfigure(pf);
5691
2fd75f31
NP		 5692 ret = i40e_resume_port_tx(pf);
5693
69129dc3 5694 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5695 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5696 if (ret)
5697 goto exit;
5698
3fe06f41
NP		 5699 /* Wait for the PF's queues to be disabled */
5700 ret = i40e_pf_wait_queues_disabled(pf);
11e47708
PN		 5701 if (ret) {
5702 /* Schedule PF reset to recover */
5703 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5704 i40e_service_event_schedule(pf);
5705 } else {
2fd75f31 5706 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5707 }
5708
4e3b35b0
NP		 5709exit:
5710 return ret;
5711}
5712#endif /* CONFIG_I40E_DCB */
5713
23326186
ASJ		 5714/**
5715 * i40e_do_reset_safe - Protected reset path for userland calls.
5716 * @pf: board private structure
5717 * @reset_flags: which reset is requested
5718 *
5719 **/
5720void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5721{
5722 rtnl_lock();
5723 i40e_do_reset(pf, reset_flags);
5724 rtnl_unlock();
5725}
5726
41c445ff
JB		 5727/**
5728 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5729 * @pf: board private structure
5730 * @e: event info posted on ARQ
5731 *
5732 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5733 * and VF queues
5734 **/
5735static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5736 struct i40e_arq_event_info *e)
5737{
5738 struct i40e_aqc_lan_overflow *data =
5739 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5740 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5741 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5742 struct i40e_hw *hw = &pf->hw;
5743 struct i40e_vf *vf;
5744 u16 vf_id;
5745
69bfb110
JB		 5746 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5747 queue, qtx_ctl);
41c445ff
JB		 5748
5749 /* Queue belongs to VF, find the VF and issue VF reset */
5750 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5751 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5752 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5753 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5754 vf_id -= hw->func_caps.vf_base_id;
5755 vf = &pf->vf[vf_id];
5756 i40e_vc_notify_vf_reset(vf);
5757 /* Allow VF to process pending reset notification */
5758 msleep(20);
5759 i40e_reset_vf(vf, false);
5760 }
5761}
5762
5763/**
5764 * i40e_service_event_complete - Finish up the service event
5765 * @pf: board private structure
5766 **/
5767static void i40e_service_event_complete(struct i40e_pf *pf)
5768{
b875f99b 5769 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5770
5771 /* flush memory to make sure state is correct before next watchog */
4e857c58 5772 smp_mb__before_atomic();
41c445ff
JB		 5773 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5774}
5775
55a5e60b 5776/**
12957388
ASJ		 5777 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5778 * @pf: board private structure
5779 **/
04294e38 5780u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5781{
04294e38 5782 u32 val, fcnt_prog;
12957388
ASJ		 5783
5784 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5785 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5786 return fcnt_prog;
5787}
5788
5789/**
04294e38 5790 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5791 * @pf: board private structure
5792 **/
04294e38 5793u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5794{
04294e38
ASJ		 5795 u32 val, fcnt_prog;
5796
55a5e60b
ASJ		 5797 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5798 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5799 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5800 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5801 return fcnt_prog;
5802}
1e1be8f6 5803
04294e38
ASJ		 5804/**
5805 * i40e_get_global_fd_count - Get total FD filters programmed on device
5806 * @pf: board private structure
5807 **/
5808u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5809{
5810 u32 val, fcnt_prog;
5811
5812 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5813 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5814 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5815 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5816 return fcnt_prog;
5817}
5818
55a5e60b
ASJ		 5819/**
5820 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5821 * @pf: board private structure
5822 **/
5823void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5824{
3487b6c3 5825 struct i40e_fdir_filter *filter;
55a5e60b 5826 u32 fcnt_prog, fcnt_avail;
3487b6c3 5827 struct hlist_node *node;
55a5e60b 5828
1e1be8f6
ASJ		 5829 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5830 return;
5831
55a5e60b
ASJ		 5832 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5833 * to re-enable
5834 */
04294e38 5835 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5836 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5837 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5838 (pf->fd_add_err == 0) ||
5839 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5840 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5841 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5842 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5843 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5844 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5845 }
5846 }
5847 /* Wait for some more space to be available to turn on ATR */
5848 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5849 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5850 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5851 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5852 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5853 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5854 }
5855 }
3487b6c3
CW		 5856
5857 /* if hw had a problem adding a filter, delete it */
5858 if (pf->fd_inv > 0) {
5859 hlist_for_each_entry_safe(filter, node,
5860 &pf->fdir_filter_list, fdir_node) {
5861 if (filter->fd_id == pf->fd_inv) {
5862 hlist_del(&filter->fdir_node);
5863 kfree(filter);
5864 pf->fdir_pf_active_filters--;
5865 }
5866 }
5867 }
55a5e60b
ASJ		 5868}
5869
1e1be8f6 5870#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5871#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5872/**
5873 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5874 * @pf: board private structure
5875 **/
5876static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5877{
04294e38 5878 unsigned long min_flush_time;
1e1be8f6 5879 int flush_wait_retry = 50;
04294e38
ASJ		 5880 bool disable_atr = false;
5881 int fd_room;
1e1be8f6
ASJ		 5882 int reg;
5883
1790ed0c
AA		 5884 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5885 return;
5886
a5fdaf34
JB		 5887 if (!time_after(jiffies, pf->fd_flush_timestamp +
5888 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5889 return;
04294e38 5890
a5fdaf34
JB		 5891 /* If the flush is happening too quick and we have mostly SB rules we
5892 * should not re-enable ATR for some time.
5893 */
5894 min_flush_time = pf->fd_flush_timestamp +
5895 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5896 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5897
5898 if (!(time_after(jiffies, min_flush_time)) &&
5899 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5900 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5901 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5902 disable_atr = true;
5903 }
5904
5905 pf->fd_flush_timestamp = jiffies;
5906 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5907 /* flush all filters */
5908 wr32(&pf->hw, I40E_PFQF_CTL_1,
5909 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5910 i40e_flush(&pf->hw);
5911 pf->fd_flush_cnt++;
5912 pf->fd_add_err = 0;
5913 do {
5914 /* Check FD flush status every 5-6msec */
5915 usleep_range(5000, 6000);
5916 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5917 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5918 break;
5919 } while (flush_wait_retry--);
5920 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5921 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5922 } else {
5923 /* replay sideband filters */
5924 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5925 if (!disable_atr)
5926 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5927 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5928 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5929 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5930 }
a5fdaf34 5931
1e1be8f6
ASJ		 5932}
5933
5934/**
5935 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5936 * @pf: board private structure
5937 **/
04294e38 5938u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5939{
5940 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5941}
5942
5943/* We can see up to 256 filter programming desc in transit if the filters are
5944 * being applied really fast; before we see the first
5945 * filter miss error on Rx queue 0. Accumulating enough error messages before
5946 * reacting will make sure we don't cause flush too often.
5947 */
5948#define I40E_MAX_FD_PROGRAM_ERROR 256
5949
41c445ff
JB		 5950/**
5951 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5952 * @pf: board private structure
5953 **/
5954static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5955{
41c445ff 5956
41c445ff
JB		 5957 /* if interface is down do nothing */
5958 if (test_bit(__I40E_DOWN, &pf->state))
5959 return;
1e1be8f6 5960
1790ed0c
AA		 5961 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5962 return;
5963
04294e38 5964 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5965 i40e_fdir_flush_and_replay(pf);
5966
55a5e60b
ASJ		 5967 i40e_fdir_check_and_reenable(pf);
5968
41c445ff
JB		 5969}
5970
5971/**
5972 * i40e_vsi_link_event - notify VSI of a link event
5973 * @vsi: vsi to be notified
5974 * @link_up: link up or down
5975 **/
5976static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5977{
32b5b811 5978 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5979 return;
5980
5981 switch (vsi->type) {
5982 case I40E_VSI_MAIN:
38e00438
VD		 5983#ifdef I40E_FCOE
5984 case I40E_VSI_FCOE:
5985#endif
41c445ff
JB		 5986 if (!vsi->netdev || !vsi->netdev_registered)
5987 break;
5988
5989 if (link_up) {
5990 netif_carrier_on(vsi->netdev);
5991 netif_tx_wake_all_queues(vsi->netdev);
5992 } else {
5993 netif_carrier_off(vsi->netdev);
5994 netif_tx_stop_all_queues(vsi->netdev);
5995 }
5996 break;
5997
5998 case I40E_VSI_SRIOV:
41c445ff
JB		 5999 case I40E_VSI_VMDQ2:
6000 case I40E_VSI_CTRL:
e3219ce6 6001 case I40E_VSI_IWARP:
41c445ff
JB		 6002 case I40E_VSI_MIRROR:
6003 default:
6004 /* there is no notification for other VSIs */
6005 break;
6006 }
6007}
6008
6009/**
6010 * i40e_veb_link_event - notify elements on the veb of a link event
6011 * @veb: veb to be notified
6012 * @link_up: link up or down
6013 **/
6014static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6015{
6016 struct i40e_pf *pf;
6017 int i;
6018
6019 if (!veb || !veb->pf)
6020 return;
6021 pf = veb->pf;
6022
6023 /* depth first... */
6024 for (i = 0; i < I40E_MAX_VEB; i++)
6025 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6026 i40e_veb_link_event(pf->veb[i], link_up);
6027
6028 /* ... now the local VSIs */
505682cd 6029 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6030 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6031 i40e_vsi_link_event(pf->vsi[i], link_up);
6032}
6033
6034/**
6035 * i40e_link_event - Update netif_carrier status
6036 * @pf: board private structure
6037 **/
6038static void i40e_link_event(struct i40e_pf *pf)
6039{
320684cd 6040 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6041 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6042 i40e_status status;
6043 bool new_link, old_link;
41c445ff 6044
1f9610e4
CS		 6045 /* save off old link status information */
6046 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6047
1e701e09
JB		 6048 /* set this to force the get_link_status call to refresh state */
6049 pf->hw.phy.get_link_info = true;
6050
41c445ff 6051 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6052
6053 status = i40e_get_link_status(&pf->hw, &new_link);
6054 if (status) {
6055 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6056 status);
6057 return;
6058 }
6059
fef59ddf
CS		 6060 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6061 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6062
1e701e09 6063 if (new_link == old_link &&
fef59ddf 6064 new_link_speed == old_link_speed &&
320684cd
MW		 6065 (test_bit(__I40E_DOWN, &vsi->state) ||
6066 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6067 return;
320684cd
MW		 6068
6069 if (!test_bit(__I40E_DOWN, &vsi->state))
6070 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6071
6072 /* Notify the base of the switch tree connected to
6073 * the link. Floating VEBs are not notified.
6074 */
6075 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6076 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6077 else
320684cd 6078 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6079
6080 if (pf->vf)
6081 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6082
6083 if (pf->flags & I40E_FLAG_PTP)
6084 i40e_ptp_set_increment(pf);
41c445ff
JB		 6085}
6086
41c445ff 6087/**
21536717 6088 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6089 * @pf: board private structure
6090 **/
6091static void i40e_watchdog_subtask(struct i40e_pf *pf)
6092{
6093 int i;
6094
6095 /* if interface is down do nothing */
6096 if (test_bit(__I40E_DOWN, &pf->state) ||
6097 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6098 return;
6099
21536717
SN		 6100 /* make sure we don't do these things too often */
6101 if (time_before(jiffies, (pf->service_timer_previous +
6102 pf->service_timer_period)))
6103 return;
6104 pf->service_timer_previous = jiffies;
6105
9ac77266
SN		 6106 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6107 i40e_link_event(pf);
21536717 6108
41c445ff
JB		 6109 /* Update the stats for active netdevs so the network stack
6110 * can look at updated numbers whenever it cares to
6111 */
505682cd 6112 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6113 if (pf->vsi[i] && pf->vsi[i]->netdev)
6114 i40e_update_stats(pf->vsi[i]);
6115
d1a8d275
ASJ		 6116 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6117 /* Update the stats for the active switching components */
6118 for (i = 0; i < I40E_MAX_VEB; i++)
6119 if (pf->veb[i])
6120 i40e_update_veb_stats(pf->veb[i]);
6121 }
beb0dff1
JK		 6122
6123 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6124}
6125
6126/**
6127 * i40e_reset_subtask - Set up for resetting the device and driver
6128 * @pf: board private structure
6129 **/
6130static void i40e_reset_subtask(struct i40e_pf *pf)
6131{
6132 u32 reset_flags = 0;
6133
23326186 6134 rtnl_lock();
41c445ff 6135 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6136 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6137 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6138 }
6139 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6140 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6141 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6142 }
6143 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6144 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6145 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6146 }
6147 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6148 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6149 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6150 }
b5d06f05 6151 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6152 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6153 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6154 }
41c445ff
JB		 6155
6156 /* If there's a recovery already waiting, it takes
6157 * precedence before starting a new reset sequence.
6158 */
6159 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6160 i40e_handle_reset_warning(pf);
23326186 6161 goto unlock;
41c445ff
JB		 6162 }
6163
6164 /* If we're already down or resetting, just bail */
6165 if (reset_flags &&
6166 !test_bit(__I40E_DOWN, &pf->state) &&
6167 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6168 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6169
6170unlock:
6171 rtnl_unlock();
41c445ff
JB		 6172}
6173
6174/**
6175 * i40e_handle_link_event - Handle link event
6176 * @pf: board private structure
6177 * @e: event info posted on ARQ
6178 **/
6179static void i40e_handle_link_event(struct i40e_pf *pf,
6180 struct i40e_arq_event_info *e)
6181{
41c445ff
JB		 6182 struct i40e_aqc_get_link_status *status =
6183 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6184
1e701e09
JB		 6185 /* Do a new status request to re-enable LSE reporting
6186 * and load new status information into the hw struct
6187 * This completely ignores any state information
6188 * in the ARQ event info, instead choosing to always
6189 * issue the AQ update link status command.
6190 */
6191 i40e_link_event(pf);
6192
7b592f61
CW		 6193 /* check for unqualified module, if link is down */
6194 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6195 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6196 (!(status->link_info & I40E_AQ_LINK_UP)))
6197 dev_err(&pf->pdev->dev,
6198 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6199}
6200
6201/**
6202 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6203 * @pf: board private structure
6204 **/
6205static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6206{
6207 struct i40e_arq_event_info event;
6208 struct i40e_hw *hw = &pf->hw;
6209 u16 pending, i = 0;
6210 i40e_status ret;
6211 u16 opcode;
86df242b 6212 u32 oldval;
41c445ff
JB		 6213 u32 val;
6214
a316f651
ASJ		 6215 /* Do not run clean AQ when PF reset fails */
6216 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6217 return;
6218
86df242b
SN		 6219 /* check for error indications */
6220 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6221 oldval = val;
6222 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6223 if (hw->debug_mask & I40E_DEBUG_AQ)
6224 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6225 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6226 }
6227 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6228 if (hw->debug_mask & I40E_DEBUG_AQ)
6229 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b 6230 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
1d0a4ada 6231 pf->arq_overflows++;
86df242b
SN		 6232 }
6233 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6234 if (hw->debug_mask & I40E_DEBUG_AQ)
6235 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6236 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6237 }
6238 if (oldval != val)
6239 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6240
6241 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6242 oldval = val;
6243 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6244 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6245 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6246 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6247 }
6248 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6249 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6250 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6251 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6252 }
6253 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6254 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6255 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6256 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6257 }
6258 if (oldval != val)
6259 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6260
1001dc37
MW		 6261 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6262 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6263 if (!event.msg_buf)
6264 return;
6265
6266 do {
6267 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6268 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6269 break;
56497978 6270 else if (ret) {
41c445ff
JB		 6271 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6272 break;
6273 }
6274
6275 opcode = le16_to_cpu(event.desc.opcode);
6276 switch (opcode) {
6277
6278 case i40e_aqc_opc_get_link_status:
6279 i40e_handle_link_event(pf, &event);
6280 break;
6281 case i40e_aqc_opc_send_msg_to_pf:
6282 ret = i40e_vc_process_vf_msg(pf,
6283 le16_to_cpu(event.desc.retval),
6284 le32_to_cpu(event.desc.cookie_high),
6285 le32_to_cpu(event.desc.cookie_low),
6286 event.msg_buf,
1001dc37 6287 event.msg_len);
41c445ff
JB		 6288 break;
6289 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6290 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6291#ifdef CONFIG_I40E_DCB
6292 rtnl_lock();
6293 ret = i40e_handle_lldp_event(pf, &event);
6294 rtnl_unlock();
6295#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6296 break;
6297 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6298 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6299 i40e_handle_lan_overflow_event(pf, &event);
6300 break;
0467bc91
SN		 6301 case i40e_aqc_opc_send_msg_to_peer:
6302 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6303 break;
91a0f930
SN		 6304 case i40e_aqc_opc_nvm_erase:
6305 case i40e_aqc_opc_nvm_update:
00ada50d 6306 case i40e_aqc_opc_oem_post_update:
6e93d0c9
SN		 6307 i40e_debug(&pf->hw, I40E_DEBUG_NVM,
6308 "ARQ NVM operation 0x%04x completed\n",
6309 opcode);
91a0f930 6310 break;
41c445ff
JB		 6311 default:
6312 dev_info(&pf->pdev->dev,
56e5ca68 6313 "ARQ: Unknown event 0x%04x ignored\n",
0467bc91 6314 opcode);
41c445ff
JB		 6315 break;
6316 }
6317 } while (pending && (i++ < pf->adminq_work_limit));
6318
6319 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6320 /* re-enable Admin queue interrupt cause */
6321 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6322 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6323 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6324 i40e_flush(hw);
6325
6326 kfree(event.msg_buf);
6327}
6328
4eb3f768
SN		 6329/**
6330 * i40e_verify_eeprom - make sure eeprom is good to use
6331 * @pf: board private structure
6332 **/
6333static void i40e_verify_eeprom(struct i40e_pf *pf)
6334{
6335 int err;
6336
6337 err = i40e_diag_eeprom_test(&pf->hw);
6338 if (err) {
6339 /* retry in case of garbage read */
6340 err = i40e_diag_eeprom_test(&pf->hw);
6341 if (err) {
6342 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6343 err);
6344 set_bit(__I40E_BAD_EEPROM, &pf->state);
6345 }
6346 }
6347
6348 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6349 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6350 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6351 }
6352}
6353
386a0afa
AA		 6354/**
6355 * i40e_enable_pf_switch_lb
b40c82e6 6356 * @pf: pointer to the PF structure
386a0afa
AA		 6357 *
6358 * enable switch loop back or die - no point in a return value
6359 **/
6360static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6361{
6362 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6363 struct i40e_vsi_context ctxt;
f1c7e72e 6364 int ret;
386a0afa
AA		 6365
6366 ctxt.seid = pf->main_vsi_seid;
6367 ctxt.pf_num = pf->hw.pf_id;
6368 ctxt.vf_num = 0;
f1c7e72e
SN		 6369 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6370 if (ret) {
386a0afa 6371 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6372 "couldn't get PF vsi config, err %s aq_err %s\n",
6373 i40e_stat_str(&pf->hw, ret),
6374 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6375 return;
6376 }
6377 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6378 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6379 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6380
f1c7e72e
SN		 6381 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6382 if (ret) {
386a0afa 6383 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6384 "update vsi switch failed, err %s aq_err %s\n",
6385 i40e_stat_str(&pf->hw, ret),
6386 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6387 }
6388}
6389
6390/**
6391 * i40e_disable_pf_switch_lb
b40c82e6 6392 * @pf: pointer to the PF structure
386a0afa
AA		 6393 *
6394 * disable switch loop back or die - no point in a return value
6395 **/
6396static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6397{
6398 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6399 struct i40e_vsi_context ctxt;
f1c7e72e 6400 int ret;
386a0afa
AA		 6401
6402 ctxt.seid = pf->main_vsi_seid;
6403 ctxt.pf_num = pf->hw.pf_id;
6404 ctxt.vf_num = 0;
f1c7e72e
SN		 6405 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6406 if (ret) {
386a0afa 6407 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6408 "couldn't get PF vsi config, err %s aq_err %s\n",
6409 i40e_stat_str(&pf->hw, ret),
6410 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6411 return;
6412 }
6413 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6414 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6415 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6416
f1c7e72e
SN		 6417 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6418 if (ret) {
386a0afa 6419 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6420 "update vsi switch failed, err %s aq_err %s\n",
6421 i40e_stat_str(&pf->hw, ret),
6422 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6423 }
6424}
6425
51616018
NP		 6426/**
6427 * i40e_config_bridge_mode - Configure the HW bridge mode
6428 * @veb: pointer to the bridge instance
6429 *
6430 * Configure the loop back mode for the LAN VSI that is downlink to the
6431 * specified HW bridge instance. It is expected this function is called
6432 * when a new HW bridge is instantiated.
6433 **/
6434static void i40e_config_bridge_mode(struct i40e_veb *veb)
6435{
6436 struct i40e_pf *pf = veb->pf;
6437
6dec1017
SN		 6438 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6439 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6440 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6441 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6442 i40e_disable_pf_switch_lb(pf);
6443 else
6444 i40e_enable_pf_switch_lb(pf);
6445}
6446
41c445ff
JB		 6447/**
6448 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6449 * @veb: pointer to the VEB instance
6450 *
6451 * This is a recursive function that first builds the attached VSIs then
6452 * recurses in to build the next layer of VEB. We track the connections
6453 * through our own index numbers because the seid's from the HW could
6454 * change across the reset.
6455 **/
6456static int i40e_reconstitute_veb(struct i40e_veb *veb)
6457{
6458 struct i40e_vsi *ctl_vsi = NULL;
6459 struct i40e_pf *pf = veb->pf;
6460 int v, veb_idx;
6461 int ret;
6462
6463 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6464 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6465 if (pf->vsi[v] &&
6466 pf->vsi[v]->veb_idx == veb->idx &&
6467 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6468 ctl_vsi = pf->vsi[v];
6469 break;
6470 }
6471 }
6472 if (!ctl_vsi) {
6473 dev_info(&pf->pdev->dev,
6474 "missing owner VSI for veb_idx %d\n", veb->idx);
6475 ret = -ENOENT;
6476 goto end_reconstitute;
6477 }
6478 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6479 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6480 ret = i40e_add_vsi(ctl_vsi);
6481 if (ret) {
6482 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6483 "rebuild of veb_idx %d owner VSI failed: %d\n",
6484 veb->idx, ret);
41c445ff
JB		 6485 goto end_reconstitute;
6486 }
6487 i40e_vsi_reset_stats(ctl_vsi);
6488
6489 /* create the VEB in the switch and move the VSI onto the VEB */
6490 ret = i40e_add_veb(veb, ctl_vsi);
6491 if (ret)
6492 goto end_reconstitute;
6493
fc60861e
ASJ		 6494 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6495 veb->bridge_mode = BRIDGE_MODE_VEB;
6496 else
6497 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6498 i40e_config_bridge_mode(veb);
b64ba084 6499
41c445ff 6500 /* create the remaining VSIs attached to this VEB */
505682cd 6501 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6502 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6503 continue;
6504
6505 if (pf->vsi[v]->veb_idx == veb->idx) {
6506 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6507
41c445ff
JB		 6508 vsi->uplink_seid = veb->seid;
6509 ret = i40e_add_vsi(vsi);
6510 if (ret) {
6511 dev_info(&pf->pdev->dev,
6512 "rebuild of vsi_idx %d failed: %d\n",
6513 v, ret);
6514 goto end_reconstitute;
6515 }
6516 i40e_vsi_reset_stats(vsi);
6517 }
6518 }
6519
6520 /* create any VEBs attached to this VEB - RECURSION */
6521 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6522 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6523 pf->veb[veb_idx]->uplink_seid = veb->seid;
6524 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6525 if (ret)
6526 break;
6527 }
6528 }
6529
6530end_reconstitute:
6531 return ret;
6532}
6533
6534/**
6535 * i40e_get_capabilities - get info about the HW
6536 * @pf: the PF struct
6537 **/
6538static int i40e_get_capabilities(struct i40e_pf *pf)
6539{
6540 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6541 u16 data_size;
6542 int buf_len;
6543 int err;
6544
6545 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6546 do {
6547 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6548 if (!cap_buf)
6549 return -ENOMEM;
6550
6551 /* this loads the data into the hw struct for us */
6552 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6553 &data_size,
6554 i40e_aqc_opc_list_func_capabilities,
6555 NULL);
6556 /* data loaded, buffer no longer needed */
6557 kfree(cap_buf);
6558
6559 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6560 /* retry with a larger buffer */
6561 buf_len = data_size;
6562 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6563 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6564 "capability discovery failed, err %s aq_err %s\n",
6565 i40e_stat_str(&pf->hw, err),
6566 i40e_aq_str(&pf->hw,
6567 pf->hw.aq.asq_last_status));
41c445ff
JB		 6568 return -ENODEV;
6569 }
6570 } while (err);
6571
6572 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6573 dev_info(&pf->pdev->dev,
6574 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6575 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6576 pf->hw.func_caps.num_msix_vectors,
6577 pf->hw.func_caps.num_msix_vectors_vf,
6578 pf->hw.func_caps.fd_filters_guaranteed,
6579 pf->hw.func_caps.fd_filters_best_effort,
6580 pf->hw.func_caps.num_tx_qp,
6581 pf->hw.func_caps.num_vsis);
6582
7134f9ce
JB		 6583#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6584 + pf->hw.func_caps.num_vfs)
6585 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6586 dev_info(&pf->pdev->dev,
6587 "got num_vsis %d, setting num_vsis to %d\n",
6588 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6589 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6590 }
6591
41c445ff
JB		 6592 return 0;
6593}
6594
cbf61325
ASJ		 6595static int i40e_vsi_clear(struct i40e_vsi *vsi);
6596
41c445ff 6597/**
cbf61325 6598 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6599 * @pf: board private structure
6600 **/
cbf61325 6601static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6602{
6603 struct i40e_vsi *vsi;
8a9eb7d3 6604 int i;
41c445ff 6605
407e063c
JB		 6606 /* quick workaround for an NVM issue that leaves a critical register
6607 * uninitialized
6608 */
6609 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6610 static const u32 hkey[] = {
6611 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6612 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6613 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6614 0x95b3a76d};
6615
6616 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6617 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6618 }
6619
cbf61325 6620 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6621 return;
6622
cbf61325 6623 /* find existing VSI and see if it needs configuring */
41c445ff 6624 vsi = NULL;
505682cd 6625 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6626 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6627 vsi = pf->vsi[i];
cbf61325
ASJ		 6628 break;
6629 }
6630 }
6631
6632 /* create a new VSI if none exists */
41c445ff 6633 if (!vsi) {
cbf61325
ASJ		 6634 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6635 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6636 if (!vsi) {
6637 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6638 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6639 return;
41c445ff 6640 }
cbf61325 6641 }
41c445ff 6642
8a9eb7d3 6643 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6644}
6645
6646/**
6647 * i40e_fdir_teardown - release the Flow Director resources
6648 * @pf: board private structure
6649 **/
6650static void i40e_fdir_teardown(struct i40e_pf *pf)
6651{
6652 int i;
6653
17a73f6b 6654 i40e_fdir_filter_exit(pf);
505682cd 6655 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6656 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6657 i40e_vsi_release(pf->vsi[i]);
6658 break;
6659 }
6660 }
6661}
6662
6663/**
f650a38b 6664 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6665 * @pf: board private structure
6666 *
b40c82e6 6667 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6668 **/
23cfbe07 6669static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6670{
41c445ff 6671 struct i40e_hw *hw = &pf->hw;
60442dea 6672 i40e_status ret = 0;
41c445ff
JB		 6673 u32 v;
6674
6675 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6676 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6677 return;
d3ce5734
MW		 6678 if (i40e_check_asq_alive(&pf->hw))
6679 i40e_vc_notify_reset(pf);
41c445ff 6680
69bfb110 6681 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6682
41c445ff
JB		 6683 /* quiesce the VSIs and their queues that are not already DOWN */
6684 i40e_pf_quiesce_all_vsi(pf);
6685
505682cd 6686 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6687 if (pf->vsi[v])
6688 pf->vsi[v]->seid = 0;
6689 }
6690
6691 i40e_shutdown_adminq(&pf->hw);
6692
f650a38b 6693 /* call shutdown HMC */
60442dea
SN		 6694 if (hw->hmc.hmc_obj) {
6695 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6696 if (ret)
60442dea
SN		 6697 dev_warn(&pf->pdev->dev,
6698 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6699 }
f650a38b
ASJ		 6700}
6701
44033fac
JB		 6702/**
6703 * i40e_send_version - update firmware with driver version
6704 * @pf: PF struct
6705 */
6706static void i40e_send_version(struct i40e_pf *pf)
6707{
6708 struct i40e_driver_version dv;
6709
6710 dv.major_version = DRV_VERSION_MAJOR;
6711 dv.minor_version = DRV_VERSION_MINOR;
6712 dv.build_version = DRV_VERSION_BUILD;
6713 dv.subbuild_version = 0;
35a7d804 6714 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6715 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6716}
6717
f650a38b 6718/**
4dda12e6 6719 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6720 * @pf: board private structure
bc7d338f 6721 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6722 **/
bc7d338f 6723static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6724{
f650a38b 6725 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6726 u8 set_fc_aq_fail = 0;
f650a38b 6727 i40e_status ret;
4f2f017c 6728 u32 val;
f650a38b
ASJ		 6729 u32 v;
6730
41c445ff
JB		 6731 /* Now we wait for GRST to settle out.
6732 * We don't have to delete the VEBs or VSIs from the hw switch
6733 * because the reset will make them disappear.
6734 */
6735 ret = i40e_pf_reset(hw);
b5565400 6736 if (ret) {
41c445ff 6737 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6738 set_bit(__I40E_RESET_FAILED, &pf->state);
6739 goto clear_recovery;
b5565400 6740 }
41c445ff
JB		 6741 pf->pfr_count++;
6742
6743 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6744 goto clear_recovery;
69bfb110 6745 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6746
6747 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6748 ret = i40e_init_adminq(&pf->hw);
6749 if (ret) {
f1c7e72e
SN		 6750 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6751 i40e_stat_str(&pf->hw, ret),
6752 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6753 goto clear_recovery;
41c445ff
JB		 6754 }
6755
4eb3f768 6756 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6757 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6758 i40e_verify_eeprom(pf);
4eb3f768 6759
e78ac4bf 6760 i40e_clear_pxe_mode(hw);
41c445ff 6761 ret = i40e_get_capabilities(pf);
f1c7e72e 6762 if (ret)
41c445ff 6763 goto end_core_reset;
41c445ff 6764
41c445ff
JB		 6765 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6766 hw->func_caps.num_rx_qp,
6767 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6768 if (ret) {
6769 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6770 goto end_core_reset;
6771 }
6772 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6773 if (ret) {
6774 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6775 goto end_core_reset;
6776 }
6777
4e3b35b0
NP		 6778#ifdef CONFIG_I40E_DCB
6779 ret = i40e_init_pf_dcb(pf);
6780 if (ret) {
aebfc816
SN		 6781 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6782 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6783 /* Continue without DCB enabled */
4e3b35b0
NP		 6784 }
6785#endif /* CONFIG_I40E_DCB */
38e00438 6786#ifdef I40E_FCOE
21364bcf 6787 i40e_init_pf_fcoe(pf);
4e3b35b0 6788
38e00438 6789#endif
41c445ff 6790 /* do basic switch setup */
bc7d338f 6791 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6792 if (ret)
6793 goto end_core_reset;
6794
2f0aff41
SN		 6795 /* The driver only wants link up/down and module qualification
6796 * reports from firmware. Note the negative logic.
7e2453fe
JB		 6797 */
6798 ret = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 6799 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 6800 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 6801 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 6802 if (ret)
f1c7e72e
SN		 6803 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6804 i40e_stat_str(&pf->hw, ret),
6805 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6806
cafa2ee6
ASJ		 6807 /* make sure our flow control settings are restored */
6808 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6809 if (ret)
8279e495
NP		 6810 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6811 i40e_stat_str(&pf->hw, ret),
6812 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6813
41c445ff
JB		 6814 /* Rebuild the VSIs and VEBs that existed before reset.
6815 * They are still in our local switch element arrays, so only
6816 * need to rebuild the switch model in the HW.
6817 *
6818 * If there were VEBs but the reconstitution failed, we'll try
6819 * try to recover minimal use by getting the basic PF VSI working.
6820 */
6821 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6822 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6823 /* find the one VEB connected to the MAC, and find orphans */
6824 for (v = 0; v < I40E_MAX_VEB; v++) {
6825 if (!pf->veb[v])
6826 continue;
6827
6828 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6829 pf->veb[v]->uplink_seid == 0) {
6830 ret = i40e_reconstitute_veb(pf->veb[v]);
6831
6832 if (!ret)
6833 continue;
6834
6835 /* If Main VEB failed, we're in deep doodoo,
6836 * so give up rebuilding the switch and set up
6837 * for minimal rebuild of PF VSI.
6838 * If orphan failed, we'll report the error
6839 * but try to keep going.
6840 */
6841 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6842 dev_info(&pf->pdev->dev,
6843 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6844 ret);
6845 pf->vsi[pf->lan_vsi]->uplink_seid
6846 = pf->mac_seid;
6847 break;
6848 } else if (pf->veb[v]->uplink_seid == 0) {
6849 dev_info(&pf->pdev->dev,
6850 "rebuild of orphan VEB failed: %d\n",
6851 ret);
6852 }
6853 }
6854 }
6855 }
6856
6857 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6858 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6859 /* no VEB, so rebuild only the Main VSI */
6860 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6861 if (ret) {
6862 dev_info(&pf->pdev->dev,
6863 "rebuild of Main VSI failed: %d\n", ret);
6864 goto end_core_reset;
6865 }
6866 }
6867
4f2f017c
ASJ		 6868 /* Reconfigure hardware for allowing smaller MSS in the case
6869 * of TSO, so that we avoid the MDD being fired and causing
6870 * a reset in the case of small MSS+TSO.
6871 */
6872#define I40E_REG_MSS 0x000E64DC
6873#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6874#define I40E_64BYTE_MSS 0x400000
6875 val = rd32(hw, I40E_REG_MSS);
6876 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6877 val &= ~I40E_REG_MSS_MIN_MASK;
6878 val |= I40E_64BYTE_MSS;
6879 wr32(hw, I40E_REG_MSS, val);
6880 }
6881
8eed76fa 6882 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 6883 msleep(75);
6884 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6885 if (ret)
f1c7e72e
SN		 6886 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6887 i40e_stat_str(&pf->hw, ret),
6888 i40e_aq_str(&pf->hw,
6889 pf->hw.aq.asq_last_status));
cafa2ee6 6890 }
41c445ff
JB		 6891 /* reinit the misc interrupt */
6892 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6893 ret = i40e_setup_misc_vector(pf);
6894
e7358f54
ASJ		 6895 /* Add a filter to drop all Flow control frames from any VSI from being
6896 * transmitted. By doing so we stop a malicious VF from sending out
6897 * PAUSE or PFC frames and potentially controlling traffic for other
6898 * PF/VF VSIs.
6899 * The FW can still send Flow control frames if enabled.
6900 */
6901 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6902 pf->main_vsi_seid);
6903
41c445ff
JB		 6904 /* restart the VSIs that were rebuilt and running before the reset */
6905 i40e_pf_unquiesce_all_vsi(pf);
6906
69f64b2b
MW		 6907 if (pf->num_alloc_vfs) {
6908 for (v = 0; v < pf->num_alloc_vfs; v++)
6909 i40e_reset_vf(&pf->vf[v], true);
6910 }
6911
41c445ff 6912 /* tell the firmware that we're starting */
44033fac 6913 i40e_send_version(pf);
41c445ff
JB		 6914
6915end_core_reset:
a316f651
ASJ		 6916 clear_bit(__I40E_RESET_FAILED, &pf->state);
6917clear_recovery:
41c445ff
JB		 6918 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6919}
6920
f650a38b 6921/**
b40c82e6 6922 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6923 * @pf: board private structure
6924 *
6925 * Close up the VFs and other things in prep for a Core Reset,
6926 * then get ready to rebuild the world.
6927 **/
6928static void i40e_handle_reset_warning(struct i40e_pf *pf)
6929{
23cfbe07
SN		 6930 i40e_prep_for_reset(pf);
6931 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6932}
6933
41c445ff
JB		 6934/**
6935 * i40e_handle_mdd_event
b40c82e6 6936 * @pf: pointer to the PF structure
41c445ff
JB		 6937 *
6938 * Called from the MDD irq handler to identify possibly malicious vfs
6939 **/
6940static void i40e_handle_mdd_event(struct i40e_pf *pf)
6941{
6942 struct i40e_hw *hw = &pf->hw;
6943 bool mdd_detected = false;
df430b12 6944 bool pf_mdd_detected = false;
41c445ff
JB		 6945 struct i40e_vf *vf;
6946 u32 reg;
6947 int i;
6948
6949 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6950 return;
6951
6952 /* find what triggered the MDD event */
6953 reg = rd32(hw, I40E_GL_MDET_TX);
6954 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6955 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6956 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6957 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6958 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6959 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6960 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6961 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6962 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6963 pf->hw.func_caps.base_queue;
faf32978 6964 if (netif_msg_tx_err(pf))
b40c82e6 6965 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6966 event, queue, pf_num, vf_num);
41c445ff
JB		 6967 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6968 mdd_detected = true;
6969 }
6970 reg = rd32(hw, I40E_GL_MDET_RX);
6971 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6972 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6973 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6974 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6975 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6976 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6977 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6978 pf->hw.func_caps.base_queue;
faf32978
JB		 6979 if (netif_msg_rx_err(pf))
6980 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6981 event, queue, func);
41c445ff
JB		 6982 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6983 mdd_detected = true;
6984 }
6985
df430b12
NP		 6986 if (mdd_detected) {
6987 reg = rd32(hw, I40E_PF_MDET_TX);
6988 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6989 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6990 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6991 pf_mdd_detected = true;
6992 }
6993 reg = rd32(hw, I40E_PF_MDET_RX);
6994 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6995 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6996 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6997 pf_mdd_detected = true;
6998 }
6999 /* Queue belongs to the PF, initiate a reset */
7000 if (pf_mdd_detected) {
7001 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7002 i40e_service_event_schedule(pf);
7003 }
7004 }
7005
41c445ff
JB		 7006 /* see if one of the VFs needs its hand slapped */
7007 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7008 vf = &(pf->vf[i]);
7009 reg = rd32(hw, I40E_VP_MDET_TX(i));
7010 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7011 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7012 vf->num_mdd_events++;
faf32978
JB		 7013 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7014 i);
41c445ff
JB		 7015 }
7016
7017 reg = rd32(hw, I40E_VP_MDET_RX(i));
7018 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7019 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7020 vf->num_mdd_events++;
faf32978
JB		 7021 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7022 i);
41c445ff
JB		 7023 }
7024
7025 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7026 dev_info(&pf->pdev->dev,
7027 "Too many MDD events on VF %d, disabled\n", i);
7028 dev_info(&pf->pdev->dev,
7029 "Use PF Control I/F to re-enable the VF\n");
7030 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7031 }
7032 }
7033
7034 /* re-enable mdd interrupt cause */
7035 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7036 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7037 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7038 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7039 i40e_flush(hw);
7040}
7041
a1c9a9d9 7042/**
6a899024 7043 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7044 * @pf: board private structure
7045 **/
6a899024 7046static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7047{
a1c9a9d9
JK		 7048 struct i40e_hw *hw = &pf->hw;
7049 i40e_status ret;
a1c9a9d9
JK		 7050 __be16 port;
7051 int i;
7052
6a899024 7053 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7054 return;
7055
6a899024 7056 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7057
7058 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7059 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7060 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7061 port = pf->udp_ports[i].index;
c22c06c8
SN		 7062 if (port)
7063 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7064 pf->udp_ports[i].type,
c22c06c8
SN		 7065 NULL, NULL);
7066 else
7067 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7068
7069 if (ret) {
730a8f87
CW		 7070 dev_dbg(&pf->pdev->dev,
7071 "%s %s port %d, index %d failed, err %s aq_err %s\n",
7072 pf->udp_ports[i].type ? "vxlan" : "geneve",
7073 port ? "add" : "delete",
7074 ntohs(port), i,
7075 i40e_stat_str(&pf->hw, ret),
7076 i40e_aq_str(&pf->hw,
f1c7e72e 7077 pf->hw.aq.asq_last_status));
6a899024 7078 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7079 }
7080 }
7081 }
7082}
7083
41c445ff
JB		 7084/**
7085 * i40e_service_task - Run the driver's async subtasks
7086 * @work: pointer to work_struct containing our data
7087 **/
7088static void i40e_service_task(struct work_struct *work)
7089{
7090 struct i40e_pf *pf = container_of(work,
7091 struct i40e_pf,
7092 service_task);
7093 unsigned long start_time = jiffies;
7094
e57a2fea
SN		 7095 /* don't bother with service tasks if a reset is in progress */
7096 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7097 i40e_service_event_complete(pf);
7098 return;
7099 }
7100
b03a8c1f 7101 i40e_detect_recover_hung(pf);
2818ccd9 7102 i40e_sync_filters_subtask(pf);
41c445ff
JB		 7103 i40e_reset_subtask(pf);
7104 i40e_handle_mdd_event(pf);
7105 i40e_vc_process_vflr_event(pf);
7106 i40e_watchdog_subtask(pf);
7107 i40e_fdir_reinit_subtask(pf);
e3219ce6 7108 i40e_client_subtask(pf);
41c445ff 7109 i40e_sync_filters_subtask(pf);
6a899024 7110 i40e_sync_udp_filters_subtask(pf);
41c445ff
JB		 7111 i40e_clean_adminq_subtask(pf);
7112
7113 i40e_service_event_complete(pf);
7114
7115 /* If the tasks have taken longer than one timer cycle or there
7116 * is more work to be done, reschedule the service task now
7117 * rather than wait for the timer to tick again.
7118 */
7119 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7120 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7121 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7122 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7123 i40e_service_event_schedule(pf);
7124}
7125
7126/**
7127 * i40e_service_timer - timer callback
7128 * @data: pointer to PF struct
7129 **/
7130static void i40e_service_timer(unsigned long data)
7131{
7132 struct i40e_pf *pf = (struct i40e_pf *)data;
7133
7134 mod_timer(&pf->service_timer,
7135 round_jiffies(jiffies + pf->service_timer_period));
7136 i40e_service_event_schedule(pf);
7137}
7138
7139/**
7140 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7141 * @vsi: the VSI being configured
7142 **/
7143static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7144{
7145 struct i40e_pf *pf = vsi->back;
7146
7147 switch (vsi->type) {
7148 case I40E_VSI_MAIN:
7149 vsi->alloc_queue_pairs = pf->num_lan_qps;
7150 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7151 I40E_REQ_DESCRIPTOR_MULTIPLE);
7152 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7153 vsi->num_q_vectors = pf->num_lan_msix;
7154 else
7155 vsi->num_q_vectors = 1;
7156
7157 break;
7158
7159 case I40E_VSI_FDIR:
7160 vsi->alloc_queue_pairs = 1;
7161 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7162 I40E_REQ_DESCRIPTOR_MULTIPLE);
7163 vsi->num_q_vectors = 1;
7164 break;
7165
7166 case I40E_VSI_VMDQ2:
7167 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7168 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7169 I40E_REQ_DESCRIPTOR_MULTIPLE);
7170 vsi->num_q_vectors = pf->num_vmdq_msix;
7171 break;
7172
7173 case I40E_VSI_SRIOV:
7174 vsi->alloc_queue_pairs = pf->num_vf_qps;
7175 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7176 I40E_REQ_DESCRIPTOR_MULTIPLE);
7177 break;
7178
38e00438
VD		 7179#ifdef I40E_FCOE
7180 case I40E_VSI_FCOE:
7181 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7182 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7183 I40E_REQ_DESCRIPTOR_MULTIPLE);
7184 vsi->num_q_vectors = pf->num_fcoe_msix;
7185 break;
7186
7187#endif /* I40E_FCOE */
41c445ff
JB		 7188 default:
7189 WARN_ON(1);
7190 return -ENODATA;
7191 }
7192
7193 return 0;
7194}
7195
f650a38b
ASJ		 7196/**
7197 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7198 * @type: VSI pointer
bc7d338f 7199 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7200 *
7201 * On error: returns error code (negative)
7202 * On success: returns 0
7203 **/
bc7d338f 7204static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7205{
7206 int size;
7207 int ret = 0;
7208
ac6c5e3d 7209 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7210 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7211 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7212 if (!vsi->tx_rings)
7213 return -ENOMEM;
f650a38b
ASJ		 7214 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7215
bc7d338f
ASJ		 7216 if (alloc_qvectors) {
7217 /* allocate memory for q_vector pointers */
f57e4fbd 7218 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7219 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7220 if (!vsi->q_vectors) {
7221 ret = -ENOMEM;
7222 goto err_vectors;
7223 }
f650a38b
ASJ		 7224 }
7225 return ret;
7226
7227err_vectors:
7228 kfree(vsi->tx_rings);
7229 return ret;
7230}
7231
41c445ff
JB		 7232/**
7233 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7234 * @pf: board private structure
7235 * @type: type of VSI
7236 *
7237 * On error: returns error code (negative)
7238 * On success: returns vsi index in PF (positive)
7239 **/
7240static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7241{
7242 int ret = -ENODEV;
7243 struct i40e_vsi *vsi;
7244 int vsi_idx;
7245 int i;
7246
7247 /* Need to protect the allocation of the VSIs at the PF level */
7248 mutex_lock(&pf->switch_mutex);
7249
7250 /* VSI list may be fragmented if VSI creation/destruction has
7251 * been happening. We can afford to do a quick scan to look
7252 * for any free VSIs in the list.
7253 *
7254 * find next empty vsi slot, looping back around if necessary
7255 */
7256 i = pf->next_vsi;
505682cd 7257 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7258 i++;
505682cd 7259 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7260 i = 0;
7261 while (i < pf->next_vsi && pf->vsi[i])
7262 i++;
7263 }
7264
505682cd 7265 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7266 vsi_idx = i; /* Found one! */
7267 } else {
7268 ret = -ENODEV;
493fb300 7269 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7270 }
7271 pf->next_vsi = ++i;
7272
7273 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7274 if (!vsi) {
7275 ret = -ENOMEM;
493fb300 7276 goto unlock_pf;
41c445ff
JB		 7277 }
7278 vsi->type = type;
7279 vsi->back = pf;
7280 set_bit(__I40E_DOWN, &vsi->state);
7281 vsi->flags = 0;
7282 vsi->idx = vsi_idx;
ac26fc13 7283 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7284 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7285 pf->rss_table_size : 64;
41c445ff
JB		 7286 vsi->netdev_registered = false;
7287 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7288 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7289 vsi->irqs_ready = false;
41c445ff 7290
9f65e15b
AD		 7291 ret = i40e_set_num_rings_in_vsi(vsi);
7292 if (ret)
7293 goto err_rings;
7294
bc7d338f 7295 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7296 if (ret)
9f65e15b 7297 goto err_rings;
493fb300 7298
41c445ff
JB		 7299 /* Setup default MSIX irq handler for VSI */
7300 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7301
21659035
KP		 7302 /* Initialize VSI lock */
7303 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7304 pf->vsi[vsi_idx] = vsi;
7305 ret = vsi_idx;
493fb300
AD		 7306 goto unlock_pf;
7307
9f65e15b 7308err_rings:
493fb300
AD		 7309 pf->next_vsi = i - 1;
7310 kfree(vsi);
7311unlock_pf:
41c445ff
JB		 7312 mutex_unlock(&pf->switch_mutex);
7313 return ret;
7314}
7315
f650a38b
ASJ		 7316/**
7317 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7318 * @type: VSI pointer
bc7d338f 7319 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7320 *
7321 * On error: returns error code (negative)
7322 * On success: returns 0
7323 **/
bc7d338f 7324static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7325{
7326 /* free the ring and vector containers */
bc7d338f
ASJ		 7327 if (free_qvectors) {
7328 kfree(vsi->q_vectors);
7329 vsi->q_vectors = NULL;
7330 }
f650a38b
ASJ		 7331 kfree(vsi->tx_rings);
7332 vsi->tx_rings = NULL;
7333 vsi->rx_rings = NULL;
7334}
7335
28c5869f
HZ		 7336/**
7337 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7338 * and lookup table
7339 * @vsi: Pointer to VSI structure
7340 */
7341static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7342{
7343 if (!vsi)
7344 return;
7345
7346 kfree(vsi->rss_hkey_user);
7347 vsi->rss_hkey_user = NULL;
7348
7349 kfree(vsi->rss_lut_user);
7350 vsi->rss_lut_user = NULL;
7351}
7352
41c445ff
JB		 7353/**
7354 * i40e_vsi_clear - Deallocate the VSI provided
7355 * @vsi: the VSI being un-configured
7356 **/
7357static int i40e_vsi_clear(struct i40e_vsi *vsi)
7358{
7359 struct i40e_pf *pf;
7360
7361 if (!vsi)
7362 return 0;
7363
7364 if (!vsi->back)
7365 goto free_vsi;
7366 pf = vsi->back;
7367
7368 mutex_lock(&pf->switch_mutex);
7369 if (!pf->vsi[vsi->idx]) {
7370 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7371 vsi->idx, vsi->idx, vsi, vsi->type);
7372 goto unlock_vsi;
7373 }
7374
7375 if (pf->vsi[vsi->idx] != vsi) {
7376 dev_err(&pf->pdev->dev,
7377 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7378 pf->vsi[vsi->idx]->idx,
7379 pf->vsi[vsi->idx],
7380 pf->vsi[vsi->idx]->type,
7381 vsi->idx, vsi, vsi->type);
7382 goto unlock_vsi;
7383 }
7384
b40c82e6 7385 /* updates the PF for this cleared vsi */
41c445ff
JB		 7386 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7387 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7388
bc7d338f 7389 i40e_vsi_free_arrays(vsi, true);
28c5869f 7390 i40e_clear_rss_config_user(vsi);
493fb300 7391
41c445ff
JB		 7392 pf->vsi[vsi->idx] = NULL;
7393 if (vsi->idx < pf->next_vsi)
7394 pf->next_vsi = vsi->idx;
7395
7396unlock_vsi:
7397 mutex_unlock(&pf->switch_mutex);
7398free_vsi:
7399 kfree(vsi);
7400
7401 return 0;
7402}
7403
9f65e15b
AD		 7404/**
7405 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7406 * @vsi: the VSI being cleaned
7407 **/
be1d5eea 7408static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7409{
7410 int i;
7411
8e9dca53 7412 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7413 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7414 kfree_rcu(vsi->tx_rings[i], rcu);
7415 vsi->tx_rings[i] = NULL;
7416 vsi->rx_rings[i] = NULL;
7417 }
be1d5eea 7418 }
9f65e15b
AD		 7419}
7420
41c445ff
JB		 7421/**
7422 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7423 * @vsi: the VSI being configured
7424 **/
7425static int i40e_alloc_rings(struct i40e_vsi *vsi)
7426{
e7046ee1 7427 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7428 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7429 int i;
7430
41c445ff 7431 /* Set basic values in the rings to be used later during open() */
d7397644 7432 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7433 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7434 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7435 if (!tx_ring)
7436 goto err_out;
41c445ff
JB		 7437
7438 tx_ring->queue_index = i;
7439 tx_ring->reg_idx = vsi->base_queue + i;
7440 tx_ring->ring_active = false;
7441 tx_ring->vsi = vsi;
7442 tx_ring->netdev = vsi->netdev;
7443 tx_ring->dev = &pf->pdev->dev;
7444 tx_ring->count = vsi->num_desc;
7445 tx_ring->size = 0;
7446 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7447 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7448 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
a75e8005 7449 tx_ring->tx_itr_setting = pf->tx_itr_default;
9f65e15b 7450 vsi->tx_rings[i] = tx_ring;
41c445ff 7451
9f65e15b 7452 rx_ring = &tx_ring[1];
41c445ff
JB		 7453 rx_ring->queue_index = i;
7454 rx_ring->reg_idx = vsi->base_queue + i;
7455 rx_ring->ring_active = false;
7456 rx_ring->vsi = vsi;
7457 rx_ring->netdev = vsi->netdev;
7458 rx_ring->dev = &pf->pdev->dev;
7459 rx_ring->count = vsi->num_desc;
7460 rx_ring->size = 0;
7461 rx_ring->dcb_tc = 0;
a75e8005 7462 rx_ring->rx_itr_setting = pf->rx_itr_default;
9f65e15b 7463 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7464 }
7465
7466 return 0;
9f65e15b
AD		 7467
7468err_out:
7469 i40e_vsi_clear_rings(vsi);
7470 return -ENOMEM;
41c445ff
JB		 7471}
7472
7473/**
7474 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7475 * @pf: board private structure
7476 * @vectors: the number of MSI-X vectors to request
7477 *
7478 * Returns the number of vectors reserved, or error
7479 **/
7480static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7481{
7b37f376
AG		 7482 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7483 I40E_MIN_MSIX, vectors);
7484 if (vectors < 0) {
41c445ff 7485 dev_info(&pf->pdev->dev,
7b37f376 7486 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7487 vectors = 0;
7488 }
7489
7490 return vectors;
7491}
7492
7493/**
7494 * i40e_init_msix - Setup the MSIX capability
7495 * @pf: board private structure
7496 *
7497 * Work with the OS to set up the MSIX vectors needed.
7498 *
3b444399 7499 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7500 **/
7501static int i40e_init_msix(struct i40e_pf *pf)
7502{
41c445ff 7503 struct i40e_hw *hw = &pf->hw;
1e200e4a 7504 int vectors_left;
41c445ff 7505 int v_budget, i;
3b444399 7506 int v_actual;
e3219ce6 7507 int iwarp_requested = 0;
41c445ff
JB		 7508
7509 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7510 return -ENODEV;
7511
7512 /* The number of vectors we'll request will be comprised of:
7513 * - Add 1 for "other" cause for Admin Queue events, etc.
7514 * - The number of LAN queue pairs
f8ff1464
ASJ		 7515 * - Queues being used for RSS.
7516 * We don't need as many as max_rss_size vectors.
7517 * use rss_size instead in the calculation since that
7518 * is governed by number of cpus in the system.
7519 * - assumes symmetric Tx/Rx pairing
41c445ff 7520 * - The number of VMDq pairs
e3219ce6 7521 * - The CPU count within the NUMA node if iWARP is enabled
38e00438
VD		 7522#ifdef I40E_FCOE
7523 * - The number of FCOE qps.
7524#endif
41c445ff
JB		 7525 * Once we count this up, try the request.
7526 *
7527 * If we can't get what we want, we'll simplify to nearly nothing
7528 * and try again. If that still fails, we punt.
7529 */
1e200e4a
SN		 7530 vectors_left = hw->func_caps.num_msix_vectors;
7531 v_budget = 0;
7532
7533 /* reserve one vector for miscellaneous handler */
7534 if (vectors_left) {
7535 v_budget++;
7536 vectors_left--;
7537 }
7538
7539 /* reserve vectors for the main PF traffic queues */
7540 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7541 vectors_left -= pf->num_lan_msix;
7542 v_budget += pf->num_lan_msix;
7543
7544 /* reserve one vector for sideband flow director */
7545 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7546 if (vectors_left) {
7547 v_budget++;
7548 vectors_left--;
7549 } else {
7550 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7551 }
7552 }
83840e4b 7553
38e00438 7554#ifdef I40E_FCOE
1e200e4a 7555 /* can we reserve enough for FCoE? */
38e00438 7556 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7557 if (!vectors_left)
7558 pf->num_fcoe_msix = 0;
7559 else if (vectors_left >= pf->num_fcoe_qps)
7560 pf->num_fcoe_msix = pf->num_fcoe_qps;
7561 else
7562 pf->num_fcoe_msix = 1;
38e00438 7563 v_budget += pf->num_fcoe_msix;
1e200e4a 7564 vectors_left -= pf->num_fcoe_msix;
38e00438 7565 }
1e200e4a 7566
38e00438 7567#endif
e3219ce6
ASJ		 7568 /* can we reserve enough for iWARP? */
7569 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7570 if (!vectors_left)
7571 pf->num_iwarp_msix = 0;
7572 else if (vectors_left < pf->num_iwarp_msix)
7573 pf->num_iwarp_msix = 1;
7574 v_budget += pf->num_iwarp_msix;
7575 vectors_left -= pf->num_iwarp_msix;
7576 }
7577
1e200e4a
SN		 7578 /* any vectors left over go for VMDq support */
7579 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7580 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7581 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7582
7583 /* if we're short on vectors for what's desired, we limit
7584 * the queues per vmdq. If this is still more than are
7585 * available, the user will need to change the number of
7586 * queues/vectors used by the PF later with the ethtool
7587 * channels command
7588 */
7589 if (vmdq_vecs < vmdq_vecs_wanted)
7590 pf->num_vmdq_qps = 1;
7591 pf->num_vmdq_msix = pf->num_vmdq_qps;
7592
7593 v_budget += vmdq_vecs;
7594 vectors_left -= vmdq_vecs;
7595 }
41c445ff
JB		 7596
7597 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7598 GFP_KERNEL);
7599 if (!pf->msix_entries)
7600 return -ENOMEM;
7601
7602 for (i = 0; i < v_budget; i++)
7603 pf->msix_entries[i].entry = i;
3b444399 7604 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7605
3b444399 7606 if (v_actual != v_budget) {
a34977ba
ASJ		 7607 /* If we have limited resources, we will start with no vectors
7608 * for the special features and then allocate vectors to some
7609 * of these features based on the policy and at the end disable
7610 * the features that did not get any vectors.
7611 */
e3219ce6
ASJ		 7612 iwarp_requested = pf->num_iwarp_msix;
7613 pf->num_iwarp_msix = 0;
38e00438
VD		 7614#ifdef I40E_FCOE
7615 pf->num_fcoe_qps = 0;
7616 pf->num_fcoe_msix = 0;
7617#endif
a34977ba
ASJ		 7618 pf->num_vmdq_msix = 0;
7619 }
7620
3b444399 7621 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7622 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7623 kfree(pf->msix_entries);
7624 pf->msix_entries = NULL;
7625 return -ENODEV;
7626
3b444399 7627 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7628 /* Adjust for minimal MSIX use */
41c445ff
JB		 7629 pf->num_vmdq_vsis = 0;
7630 pf->num_vmdq_qps = 0;
41c445ff
JB		 7631 pf->num_lan_qps = 1;
7632 pf->num_lan_msix = 1;
7633
3b444399
SN		 7634 } else if (v_actual != v_budget) {
7635 int vec;
7636
a34977ba 7637 /* reserve the misc vector */
3b444399 7638 vec = v_actual - 1;
a34977ba 7639
41c445ff
JB		 7640 /* Scale vector usage down */
7641 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7642 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7643 pf->num_vmdq_qps = 1;
7644 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7645
7646 /* partition out the remaining vectors */
7647 switch (vec) {
7648 case 2:
41c445ff
JB		 7649 pf->num_lan_msix = 1;
7650 break;
7651 case 3:
e3219ce6
ASJ		 7652 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7653 pf->num_lan_msix = 1;
7654 pf->num_iwarp_msix = 1;
7655 } else {
7656 pf->num_lan_msix = 2;
7657 }
38e00438
VD		 7658#ifdef I40E_FCOE
7659 /* give one vector to FCoE */
7660 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7661 pf->num_lan_msix = 1;
7662 pf->num_fcoe_msix = 1;
7663 }
38e00438 7664#endif
41c445ff
JB		 7665 break;
7666 default:
e3219ce6
ASJ		 7667 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7668 pf->num_iwarp_msix = min_t(int, (vec / 3),
7669 iwarp_requested);
7670 pf->num_vmdq_vsis = min_t(int, (vec / 3),
7671 I40E_DEFAULT_NUM_VMDQ_VSI);
7672 } else {
7673 pf->num_vmdq_vsis = min_t(int, (vec / 2),
7674 I40E_DEFAULT_NUM_VMDQ_VSI);
7675 }
7676 pf->num_lan_msix = min_t(int,
7677 (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)),
7678 pf->num_lan_msix);
38e00438
VD		 7679#ifdef I40E_FCOE
7680 /* give one vector to FCoE */
7681 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7682 pf->num_fcoe_msix = 1;
7683 vec--;
7684 }
7685#endif
41c445ff
JB		 7686 break;
7687 }
7688 }
7689
a34977ba
ASJ		 7690 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7691 (pf->num_vmdq_msix == 0)) {
7692 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7693 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7694 }
e3219ce6
ASJ		 7695
7696 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
7697 (pf->num_iwarp_msix == 0)) {
7698 dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n");
7699 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
7700 }
38e00438
VD		 7701#ifdef I40E_FCOE
7702
7703 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7704 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7705 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7706 }
7707#endif
3b444399 7708 return v_actual;
41c445ff
JB		 7709}
7710
493fb300 7711/**
90e04070 7712 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7713 * @vsi: the VSI being configured
7714 * @v_idx: index of the vector in the vsi struct
7715 *
7716 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7717 **/
90e04070 7718static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7719{
7720 struct i40e_q_vector *q_vector;
7721
7722 /* allocate q_vector */
7723 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7724 if (!q_vector)
7725 return -ENOMEM;
7726
7727 q_vector->vsi = vsi;
7728 q_vector->v_idx = v_idx;
7729 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7730 if (vsi->netdev)
7731 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7732 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7733
cd0b6fa6
AD		 7734 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7735 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7736
493fb300
AD		 7737 /* tie q_vector and vsi together */
7738 vsi->q_vectors[v_idx] = q_vector;
7739
7740 return 0;
7741}
7742
41c445ff 7743/**
90e04070 7744 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7745 * @vsi: the VSI being configured
7746 *
7747 * We allocate one q_vector per queue interrupt. If allocation fails we
7748 * return -ENOMEM.
7749 **/
90e04070 7750static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7751{
7752 struct i40e_pf *pf = vsi->back;
7753 int v_idx, num_q_vectors;
493fb300 7754 int err;
41c445ff
JB		 7755
7756 /* if not MSIX, give the one vector only to the LAN VSI */
7757 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7758 num_q_vectors = vsi->num_q_vectors;
7759 else if (vsi == pf->vsi[pf->lan_vsi])
7760 num_q_vectors = 1;
7761 else
7762 return -EINVAL;
7763
41c445ff 7764 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7765 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7766 if (err)
7767 goto err_out;
41c445ff
JB		 7768 }
7769
7770 return 0;
493fb300
AD		 7771
7772err_out:
7773 while (v_idx--)
7774 i40e_free_q_vector(vsi, v_idx);
7775
7776 return err;
41c445ff
JB		 7777}
7778
7779/**
7780 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7781 * @pf: board private structure to initialize
7782 **/
c1147280 7783static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7784{
3b444399
SN		 7785 int vectors = 0;
7786 ssize_t size;
41c445ff
JB		 7787
7788 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7789 vectors = i40e_init_msix(pf);
7790 if (vectors < 0) {
60ea5f83 7791 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
e3219ce6 7792 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 7793#ifdef I40E_FCOE
7794 I40E_FLAG_FCOE_ENABLED |
7795#endif
60ea5f83 7796 I40E_FLAG_RSS_ENABLED |
4d9b6043 7797 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7798 I40E_FLAG_SRIOV_ENABLED |
7799 I40E_FLAG_FD_SB_ENABLED |
7800 I40E_FLAG_FD_ATR_ENABLED |
7801 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7802
7803 /* rework the queue expectations without MSIX */
7804 i40e_determine_queue_usage(pf);
7805 }
7806 }
7807
7808 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7809 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7810 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7811 vectors = pci_enable_msi(pf->pdev);
7812 if (vectors < 0) {
7813 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7814 vectors);
41c445ff
JB		 7815 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7816 }
3b444399 7817 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7818 }
7819
958a3e3b 7820 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7821 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7822
3b444399
SN		 7823 /* set up vector assignment tracking */
7824 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7825 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7826 if (!pf->irq_pile) {
7827 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7828 return -ENOMEM;
7829 }
3b444399
SN		 7830 pf->irq_pile->num_entries = vectors;
7831 pf->irq_pile->search_hint = 0;
7832
c1147280 7833 /* track first vector for misc interrupts, ignore return */
3b444399 7834 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7835
7836 return 0;
41c445ff
JB		 7837}
7838
7839/**
7840 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7841 * @pf: board private structure
7842 *
7843 * This sets up the handler for MSIX 0, which is used to manage the
7844 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7845 * when in MSI or Legacy interrupt mode.
7846 **/
7847static int i40e_setup_misc_vector(struct i40e_pf *pf)
7848{
7849 struct i40e_hw *hw = &pf->hw;
7850 int err = 0;
7851
7852 /* Only request the irq if this is the first time through, and
7853 * not when we're rebuilding after a Reset
7854 */
7855 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7856 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7857 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7858 if (err) {
7859 dev_info(&pf->pdev->dev,
77fa28be 7860 "request_irq for %s failed: %d\n",
b294ac70 7861 pf->int_name, err);
41c445ff
JB		 7862 return -EFAULT;
7863 }
7864 }
7865
ab437b5a 7866 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7867
7868 /* associate no queues to the misc vector */
7869 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7870 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7871
7872 i40e_flush(hw);
7873
40d72a50 7874 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 7875
7876 return err;
7877}
7878
7879/**
e25d00b8
ASJ		 7880 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7881 * @vsi: vsi structure
7882 * @seed: RSS hash seed
7883 **/
e69ff813
HZ		 7884static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7885 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7886{
7887 struct i40e_aqc_get_set_rss_key_data rss_key;
7888 struct i40e_pf *pf = vsi->back;
7889 struct i40e_hw *hw = &pf->hw;
7890 bool pf_lut = false;
7891 u8 *rss_lut;
7892 int ret, i;
7893
7894 memset(&rss_key, 0, sizeof(rss_key));
7895 memcpy(&rss_key, seed, sizeof(rss_key));
7896
7897 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7898 if (!rss_lut)
7899 return -ENOMEM;
7900
7901 /* Populate the LUT with max no. of queues in round robin fashion */
7902 for (i = 0; i < vsi->rss_table_size; i++)
7903 rss_lut[i] = i % vsi->rss_size;
7904
7905 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7906 if (ret) {
7907 dev_info(&pf->pdev->dev,
7908 "Cannot set RSS key, err %s aq_err %s\n",
7909 i40e_stat_str(&pf->hw, ret),
7910 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7911 goto config_rss_aq_out;
e25d00b8
ASJ		 7912 }
7913
7914 if (vsi->type == I40E_VSI_MAIN)
7915 pf_lut = true;
7916
7917 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7918 vsi->rss_table_size);
7919 if (ret)
7920 dev_info(&pf->pdev->dev,
7921 "Cannot set RSS lut, err %s aq_err %s\n",
7922 i40e_stat_str(&pf->hw, ret),
7923 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7924
126b63d9
AS		 7925config_rss_aq_out:
7926 kfree(rss_lut);
e25d00b8
ASJ		 7927 return ret;
7928}
7929
7930/**
7931 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7932 * @vsi: VSI structure
7933 **/
7934static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7935{
7936 u8 seed[I40E_HKEY_ARRAY_SIZE];
7937 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7938 u8 *lut;
7939 int ret;
7940
7941 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7942 return 0;
7943
7944 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7945 if (!lut)
7946 return -ENOMEM;
e25d00b8 7947
e69ff813 7948 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7949 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7950 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7951 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7952 kfree(lut);
e25d00b8 7953
e69ff813 7954 return ret;
e25d00b8
ASJ		 7955}
7956
95a73780
ASJ		 7957/**
7958 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
7959 * @vsi: Pointer to vsi structure
7960 * @seed: Buffter to store the hash keys
7961 * @lut: Buffer to store the lookup table entries
7962 * @lut_size: Size of buffer to store the lookup table entries
7963 *
7964 * Return 0 on success, negative on failure
7965 */
7966static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7967 u8 *lut, u16 lut_size)
7968{
7969 struct i40e_pf *pf = vsi->back;
7970 struct i40e_hw *hw = &pf->hw;
7971 int ret = 0;
7972
7973 if (seed) {
7974 ret = i40e_aq_get_rss_key(hw, vsi->id,
7975 (struct i40e_aqc_get_set_rss_key_data *)seed);
7976 if (ret) {
7977 dev_info(&pf->pdev->dev,
7978 "Cannot get RSS key, err %s aq_err %s\n",
7979 i40e_stat_str(&pf->hw, ret),
7980 i40e_aq_str(&pf->hw,
7981 pf->hw.aq.asq_last_status));
7982 return ret;
7983 }
7984 }
7985
7986 if (lut) {
7987 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
7988
7989 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
7990 if (ret) {
7991 dev_info(&pf->pdev->dev,
7992 "Cannot get RSS lut, err %s aq_err %s\n",
7993 i40e_stat_str(&pf->hw, ret),
7994 i40e_aq_str(&pf->hw,
7995 pf->hw.aq.asq_last_status));
7996 return ret;
7997 }
7998 }
7999
8000 return ret;
8001}
8002
e25d00b8 8003/**
043dd650 8004 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 8005 * @vsi: Pointer to vsi structure
e25d00b8 8006 * @seed: RSS hash seed
e69ff813
HZ		 8007 * @lut: Lookup table
8008 * @lut_size: Lookup table size
8009 *
8010 * Returns 0 on success, negative on failure
41c445ff 8011 **/
e69ff813
HZ		 8012static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
8013 const u8 *lut, u16 lut_size)
41c445ff 8014{
e69ff813 8015 struct i40e_pf *pf = vsi->back;
4617e8c0 8016 struct i40e_hw *hw = &pf->hw;
c4e1868c 8017 u16 vf_id = vsi->vf_id;
e69ff813 8018 u8 i;
41c445ff 8019
e25d00b8 8020 /* Fill out hash function seed */
e69ff813
HZ		 8021 if (seed) {
8022 u32 *seed_dw = (u32 *)seed;
8023
c4e1868c
MW		 8024 if (vsi->type == I40E_VSI_MAIN) {
8025 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8026 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i),
8027 seed_dw[i]);
8028 } else if (vsi->type == I40E_VSI_SRIOV) {
8029 for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++)
8030 i40e_write_rx_ctl(hw,
8031 I40E_VFQF_HKEY1(i, vf_id),
8032 seed_dw[i]);
8033 } else {
8034 dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n");
8035 }
e69ff813
HZ		 8036 }
8037
8038 if (lut) {
8039 u32 *lut_dw = (u32 *)lut;
8040
c4e1868c
MW		 8041 if (vsi->type == I40E_VSI_MAIN) {
8042 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8043 return -EINVAL;
8044 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8045 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
8046 } else if (vsi->type == I40E_VSI_SRIOV) {
8047 if (lut_size != I40E_VF_HLUT_ARRAY_SIZE)
8048 return -EINVAL;
8049 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++)
8050 i40e_write_rx_ctl(hw,
8051 I40E_VFQF_HLUT1(i, vf_id),
8052 lut_dw[i]);
8053 } else {
8054 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n");
8055 }
e25d00b8
ASJ		 8056 }
8057 i40e_flush(hw);
8058
8059 return 0;
8060}
8061
043dd650
HZ		 8062/**
8063 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
8064 * @vsi: Pointer to VSI structure
8065 * @seed: Buffer to store the keys
8066 * @lut: Buffer to store the lookup table entries
8067 * @lut_size: Size of buffer to store the lookup table entries
8068 *
8069 * Returns 0 on success, negative on failure
8070 */
8071static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
8072 u8 *lut, u16 lut_size)
8073{
8074 struct i40e_pf *pf = vsi->back;
8075 struct i40e_hw *hw = &pf->hw;
8076 u16 i;
8077
8078 if (seed) {
8079 u32 *seed_dw = (u32 *)seed;
8080
8081 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
272cdaf2 8082 seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
043dd650
HZ		 8083 }
8084 if (lut) {
8085 u32 *lut_dw = (u32 *)lut;
8086
8087 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8088 return -EINVAL;
8089 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8090 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
8091 }
8092
8093 return 0;
8094}
8095
8096/**
8097 * i40e_config_rss - Configure RSS keys and lut
8098 * @vsi: Pointer to VSI structure
8099 * @seed: RSS hash seed
8100 * @lut: Lookup table
8101 * @lut_size: Lookup table size
8102 *
8103 * Returns 0 on success, negative on failure
8104 */
8105int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8106{
8107 struct i40e_pf *pf = vsi->back;
8108
8109 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8110 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8111 else
8112 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8113}
8114
8115/**
8116 * i40e_get_rss - Get RSS keys and lut
8117 * @vsi: Pointer to VSI structure
8118 * @seed: Buffer to store the keys
8119 * @lut: Buffer to store the lookup table entries
8120 * lut_size: Size of buffer to store the lookup table entries
8121 *
8122 * Returns 0 on success, negative on failure
8123 */
8124int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8125{
95a73780
ASJ		 8126 struct i40e_pf *pf = vsi->back;
8127
8128 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8129 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
8130 else
8131 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
043dd650
HZ		 8132}
8133
e69ff813
HZ		 8134/**
8135 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8136 * @pf: Pointer to board private structure
8137 * @lut: Lookup table
8138 * @rss_table_size: Lookup table size
8139 * @rss_size: Range of queue number for hashing
8140 */
8141static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8142 u16 rss_table_size, u16 rss_size)
8143{
8144 u16 i;
8145
8146 for (i = 0; i < rss_table_size; i++)
8147 lut[i] = i % rss_size;
8148}
8149
e25d00b8 8150/**
043dd650 8151 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8152 * @pf: board private structure
8153 **/
043dd650 8154static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8155{
8156 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8157 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8158 u8 *lut;
e25d00b8
ASJ		 8159 struct i40e_hw *hw = &pf->hw;
8160 u32 reg_val;
8161 u64 hena;
e69ff813 8162 int ret;
e25d00b8 8163
41c445ff 8164 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
272cdaf2
SN		 8165 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
8166 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8167 hena |= i40e_pf_get_default_rss_hena(pf);
8168
272cdaf2
SN		 8169 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
8170 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
41c445ff 8171
e25d00b8 8172 /* Determine the RSS table size based on the hardware capabilities */
272cdaf2 8173 reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8174 reg_val = (pf->rss_table_size == 512) ?
8175 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8176 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
272cdaf2 8177 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
e157ea30 8178
28c5869f
HZ		 8179 /* Determine the RSS size of the VSI */
8180 if (!vsi->rss_size)
acd65448
HZ		 8181 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8182 vsi->num_queue_pairs);
28c5869f 8183
e69ff813
HZ		 8184 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8185 if (!lut)
8186 return -ENOMEM;
8187
28c5869f
HZ		 8188 /* Use user configured lut if there is one, otherwise use default */
8189 if (vsi->rss_lut_user)
8190 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8191 else
8192 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8193
28c5869f
HZ		 8194 /* Use user configured hash key if there is one, otherwise
8195 * use default.
8196 */
8197 if (vsi->rss_hkey_user)
8198 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8199 else
8200 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8201 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8202 kfree(lut);
8203
8204 return ret;
41c445ff
JB		 8205}
8206
f8ff1464
ASJ		 8207/**
8208 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8209 * @pf: board private structure
8210 * @queue_count: the requested queue count for rss.
8211 *
8212 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8213 * count which may be different from the requested queue count.
8214 **/
8215int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8216{
9a3bd2f1
ASJ		 8217 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8218 int new_rss_size;
8219
f8ff1464
ASJ		 8220 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8221 return 0;
8222
9a3bd2f1 8223 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8224
9a3bd2f1
ASJ		 8225 if (queue_count != vsi->num_queue_pairs) {
8226 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8227 i40e_prep_for_reset(pf);
8228
acd65448 8229 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8230
8231 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8232
8233 /* Discard the user configured hash keys and lut, if less
8234 * queues are enabled.
8235 */
8236 if (queue_count < vsi->rss_size) {
8237 i40e_clear_rss_config_user(vsi);
8238 dev_dbg(&pf->pdev->dev,
8239 "discard user configured hash keys and lut\n");
8240 }
8241
8242 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8243 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8244 vsi->num_queue_pairs);
28c5869f 8245
043dd650 8246 i40e_pf_config_rss(pf);
f8ff1464 8247 }
e36b0b11
HZ		 8248 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8249 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8250 return pf->alloc_rss_size;
f8ff1464
ASJ		 8251}
8252
f4492db1
GR		 8253/**
8254 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8255 * @pf: board private structure
8256 **/
8257i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8258{
8259 i40e_status status;
8260 bool min_valid, max_valid;
8261 u32 max_bw, min_bw;
8262
8263 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8264 &min_valid, &max_valid);
8265
8266 if (!status) {
8267 if (min_valid)
8268 pf->npar_min_bw = min_bw;
8269 if (max_valid)
8270 pf->npar_max_bw = max_bw;
8271 }
8272
8273 return status;
8274}
8275
8276/**
8277 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8278 * @pf: board private structure
8279 **/
8280i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8281{
8282 struct i40e_aqc_configure_partition_bw_data bw_data;
8283 i40e_status status;
8284
b40c82e6 8285 /* Set the valid bit for this PF */
41a1d04b 8286 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8287 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8288 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8289
8290 /* Set the new bandwidths */
8291 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8292
8293 return status;
8294}
8295
8296/**
8297 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8298 * @pf: board private structure
8299 **/
8300i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8301{
8302 /* Commit temporary BW setting to permanent NVM image */
8303 enum i40e_admin_queue_err last_aq_status;
8304 i40e_status ret;
8305 u16 nvm_word;
8306
8307 if (pf->hw.partition_id != 1) {
8308 dev_info(&pf->pdev->dev,
8309 "Commit BW only works on partition 1! This is partition %d",
8310 pf->hw.partition_id);
8311 ret = I40E_NOT_SUPPORTED;
8312 goto bw_commit_out;
8313 }
8314
8315 /* Acquire NVM for read access */
8316 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8317 last_aq_status = pf->hw.aq.asq_last_status;
8318 if (ret) {
8319 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8320 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8321 i40e_stat_str(&pf->hw, ret),
8322 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8323 goto bw_commit_out;
8324 }
8325
8326 /* Read word 0x10 of NVM - SW compatibility word 1 */
8327 ret = i40e_aq_read_nvm(&pf->hw,
8328 I40E_SR_NVM_CONTROL_WORD,
8329 0x10, sizeof(nvm_word), &nvm_word,
8330 false, NULL);
8331 /* Save off last admin queue command status before releasing
8332 * the NVM
8333 */
8334 last_aq_status = pf->hw.aq.asq_last_status;
8335 i40e_release_nvm(&pf->hw);
8336 if (ret) {
f1c7e72e
SN		 8337 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8338 i40e_stat_str(&pf->hw, ret),
8339 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8340 goto bw_commit_out;
8341 }
8342
8343 /* Wait a bit for NVM release to complete */
8344 msleep(50);
8345
8346 /* Acquire NVM for write access */
8347 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8348 last_aq_status = pf->hw.aq.asq_last_status;
8349 if (ret) {
8350 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8351 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8352 i40e_stat_str(&pf->hw, ret),
8353 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8354 goto bw_commit_out;
8355 }
8356 /* Write it back out unchanged to initiate update NVM,
8357 * which will force a write of the shadow (alt) RAM to
8358 * the NVM - thus storing the bandwidth values permanently.
8359 */
8360 ret = i40e_aq_update_nvm(&pf->hw,
8361 I40E_SR_NVM_CONTROL_WORD,
8362 0x10, sizeof(nvm_word),
8363 &nvm_word, true, NULL);
8364 /* Save off last admin queue command status before releasing
8365 * the NVM
8366 */
8367 last_aq_status = pf->hw.aq.asq_last_status;
8368 i40e_release_nvm(&pf->hw);
8369 if (ret)
8370 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8371 "BW settings NOT SAVED, err %s aq_err %s\n",
8372 i40e_stat_str(&pf->hw, ret),
8373 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8374bw_commit_out:
8375
8376 return ret;
8377}
8378
41c445ff
JB		 8379/**
8380 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8381 * @pf: board private structure to initialize
8382 *
8383 * i40e_sw_init initializes the Adapter private data structure.
8384 * Fields are initialized based on PCI device information and
8385 * OS network device settings (MTU size).
8386 **/
8387static int i40e_sw_init(struct i40e_pf *pf)
8388{
8389 int err = 0;
8390 int size;
8391
8392 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8393 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
8394 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8395 if (I40E_DEBUG_USER & debug)
8396 pf->hw.debug_mask = debug;
8397 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8398 I40E_DEFAULT_MSG_ENABLE);
8399 }
8400
8401 /* Set default capability flags */
8402 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8403 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 8404 I40E_FLAG_MSIX_ENABLED;
8405
ca99eb99
MW		 8406 /* Set default ITR */
8407 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8408 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8409
7134f9ce
JB		 8410 /* Depending on PF configurations, it is possible that the RSS
8411 * maximum might end up larger than the available queues
8412 */
41a1d04b 8413 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8414 pf->alloc_rss_size = 1;
5db4cb59 8415 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8416 pf->rss_size_max = min_t(int, pf->rss_size_max,
8417 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8418 if (pf->hw.func_caps.rss) {
8419 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8420 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8421 num_online_cpus());
41c445ff
JB		 8422 }
8423
2050bc65 8424 /* MFP mode enabled */
c78b953e 8425 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8426 pf->flags |= I40E_FLAG_MFP_ENABLED;
8427 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8428 if (i40e_get_npar_bw_setting(pf))
8429 dev_warn(&pf->pdev->dev,
8430 "Could not get NPAR bw settings\n");
8431 else
8432 dev_info(&pf->pdev->dev,
8433 "Min BW = %8.8x, Max BW = %8.8x\n",
8434 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8435 }
8436
cbf61325
ASJ		 8437 /* FW/NVM is not yet fixed in this regard */
8438 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8439 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8440 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8441 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8442 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8443 pf->hw.num_partitions > 1)
cbf61325 8444 dev_info(&pf->pdev->dev,
0b67584f 8445 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8446 else
8447 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8448 pf->fdir_pf_filter_count =
8449 pf->hw.func_caps.fd_filters_guaranteed;
8450 pf->hw.fdir_shared_filter_count =
8451 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8452 }
8453
f1bbad33 8454 if (i40e_is_mac_710(&pf->hw) &&
8eed76fa 8455 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
f1bbad33 8456 (pf->hw.aq.fw_maj_ver < 4))) {
8eed76fa 8457 pf->flags |= I40E_FLAG_RESTART_AUTONEG;
f1bbad33
NP		 8458 /* No DCB support for FW < v4.33 */
8459 pf->flags |= I40E_FLAG_NO_DCB_SUPPORT;
8460 }
8461
8462 /* Disable FW LLDP if FW < v4.3 */
8463 if (i40e_is_mac_710(&pf->hw) &&
8464 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
8465 (pf->hw.aq.fw_maj_ver < 4)))
8466 pf->flags |= I40E_FLAG_STOP_FW_LLDP;
8467
8468 /* Use the FW Set LLDP MIB API if FW > v4.40 */
8469 if (i40e_is_mac_710(&pf->hw) &&
8470 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
8471 (pf->hw.aq.fw_maj_ver >= 5)))
8472 pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB;
8eed76fa 8473
41c445ff 8474 if (pf->hw.func_caps.vmdq) {
41c445ff 8475 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8476 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8477 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8478 }
8479
e3219ce6
ASJ		 8480 if (pf->hw.func_caps.iwarp) {
8481 pf->flags |= I40E_FLAG_IWARP_ENABLED;
8482 /* IWARP needs one extra vector for CQP just like MISC.*/
8483 pf->num_iwarp_msix = (int)num_online_cpus() + 1;
8484 }
8485
38e00438 8486#ifdef I40E_FCOE
21364bcf 8487 i40e_init_pf_fcoe(pf);
38e00438
VD		 8488
8489#endif /* I40E_FCOE */
41c445ff 8490#ifdef CONFIG_PCI_IOV
ba252f13 8491 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8492 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8493 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8494 pf->num_req_vfs = min_t(int,
8495 pf->hw.func_caps.num_vfs,
8496 I40E_MAX_VF_COUNT);
8497 }
8498#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8499 if (pf->hw.mac.type == I40E_MAC_X722) {
8500 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8501 I40E_FLAG_128_QP_RSS_CAPABLE |
8502 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8503 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8504 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024 8505 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
8e2cc0e6 8506 I40E_FLAG_NO_PCI_LINK_CHECK |
f8db54cc 8507 I40E_FLAG_100M_SGMII_CAPABLE |
f1bbad33 8508 I40E_FLAG_USE_SET_LLDP_MIB |
6a899024 8509 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
a340c789
AS		 8510 } else if ((pf->hw.aq.api_maj_ver > 1) ||
8511 ((pf->hw.aq.api_maj_ver == 1) &&
8512 (pf->hw.aq.api_min_ver > 4))) {
8513 /* Supported in FW API version higher than 1.4 */
8514 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
72b74869
ASJ		 8515 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
8516 } else {
8517 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
d502ce01 8518 }
a340c789 8519
41c445ff
JB		 8520 pf->eeprom_version = 0xDEAD;
8521 pf->lan_veb = I40E_NO_VEB;
8522 pf->lan_vsi = I40E_NO_VSI;
8523
d1a8d275
ASJ		 8524 /* By default FW has this off for performance reasons */
8525 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8526
41c445ff
JB		 8527 /* set up queue assignment tracking */
8528 size = sizeof(struct i40e_lump_tracking)
8529 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8530 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8531 if (!pf->qp_pile) {
8532 err = -ENOMEM;
8533 goto sw_init_done;
8534 }
8535 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8536 pf->qp_pile->search_hint = 0;
8537
327fe04b
ASJ		 8538 pf->tx_timeout_recovery_level = 1;
8539
41c445ff
JB		 8540 mutex_init(&pf->switch_mutex);
8541
c668a12c
GR		 8542 /* If NPAR is enabled nudge the Tx scheduler */
8543 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8544 i40e_set_npar_bw_setting(pf);
8545
41c445ff
JB		 8546sw_init_done:
8547 return err;
8548}
8549
7c3c288b
ASJ		 8550/**
8551 * i40e_set_ntuple - set the ntuple feature flag and take action
8552 * @pf: board private structure to initialize
8553 * @features: the feature set that the stack is suggesting
8554 *
8555 * returns a bool to indicate if reset needs to happen
8556 **/
8557bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8558{
8559 bool need_reset = false;
8560
8561 /* Check if Flow Director n-tuple support was enabled or disabled. If
8562 * the state changed, we need to reset.
8563 */
8564 if (features & NETIF_F_NTUPLE) {
8565 /* Enable filters and mark for reset */
8566 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8567 need_reset = true;
8568 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8569 } else {
8570 /* turn off filters, mark for reset and clear SW filter list */
8571 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8572 need_reset = true;
8573 i40e_fdir_filter_exit(pf);
8574 }
8575 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8576 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8577 /* reset fd counters */
8578 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8579 pf->fdir_pf_active_filters = 0;
8580 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8581 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8582 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8583 /* if ATR was auto disabled it can be re-enabled. */
8584 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8585 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8586 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8587 }
8588 return need_reset;
8589}
8590
41c445ff
JB		 8591/**
8592 * i40e_set_features - set the netdev feature flags
8593 * @netdev: ptr to the netdev being adjusted
8594 * @features: the feature set that the stack is suggesting
8595 **/
8596static int i40e_set_features(struct net_device *netdev,
8597 netdev_features_t features)
8598{
8599 struct i40e_netdev_priv *np = netdev_priv(netdev);
8600 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8601 struct i40e_pf *pf = vsi->back;
8602 bool need_reset;
41c445ff
JB		 8603
8604 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8605 i40e_vlan_stripping_enable(vsi);
8606 else
8607 i40e_vlan_stripping_disable(vsi);
8608
7c3c288b
ASJ		 8609 need_reset = i40e_set_ntuple(pf, features);
8610
8611 if (need_reset)
41a1d04b 8612 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8613
41c445ff
JB		 8614 return 0;
8615}
8616
a1c9a9d9 8617/**
6a899024 8618 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8619 * @pf: board private structure
8620 * @port: The UDP port to look up
8621 *
8622 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8623 **/
6a899024 8624static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8625{
8626 u8 i;
8627
8628 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8629 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8630 return i;
8631 }
8632
8633 return i;
8634}
8635
8636/**
06a5f7f1 8637 * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up
a1c9a9d9 8638 * @netdev: This physical port's netdev
06a5f7f1 8639 * @ti: Tunnel endpoint information
a1c9a9d9 8640 **/
06a5f7f1
AD		 8641static void i40e_udp_tunnel_add(struct net_device *netdev,
8642 struct udp_tunnel_info *ti)
a1c9a9d9
JK		 8643{
8644 struct i40e_netdev_priv *np = netdev_priv(netdev);
8645 struct i40e_vsi *vsi = np->vsi;
8646 struct i40e_pf *pf = vsi->back;
06a5f7f1 8647 __be16 port = ti->port;
a1c9a9d9
JK		 8648 u8 next_idx;
8649 u8 idx;
8650
6a899024 8651 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8652
8653 /* Check if port already exists */
8654 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
06a5f7f1 8655 netdev_info(netdev, "port %d already offloaded\n",
c22c06c8 8656 ntohs(port));
a1c9a9d9
JK		 8657 return;
8658 }
8659
8660 /* Now check if there is space to add the new port */
6a899024 8661 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8662
8663 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
06a5f7f1 8664 netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n",
6a899024
SA		 8665 ntohs(port));
8666 return;
8667 }
8668
06a5f7f1
AD		 8669 switch (ti->type) {
8670 case UDP_TUNNEL_TYPE_VXLAN:
8671 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8672 break;
8673 case UDP_TUNNEL_TYPE_GENEVE:
8674 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8675 return;
8676 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8677 break;
8678 default:
6a899024
SA		 8679 return;
8680 }
8681
8682 /* New port: add it and mark its index in the bitmap */
8683 pf->udp_ports[next_idx].index = port;
6a899024
SA		 8684 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8685 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 8686}
8687
6a899024 8688/**
06a5f7f1 8689 * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away
6a899024 8690 * @netdev: This physical port's netdev
06a5f7f1 8691 * @ti: Tunnel endpoint information
6a899024 8692 **/
06a5f7f1
AD		 8693static void i40e_udp_tunnel_del(struct net_device *netdev,
8694 struct udp_tunnel_info *ti)
6a899024 8695{
6a899024
SA		 8696 struct i40e_netdev_priv *np = netdev_priv(netdev);
8697 struct i40e_vsi *vsi = np->vsi;
8698 struct i40e_pf *pf = vsi->back;
06a5f7f1 8699 __be16 port = ti->port;
6a899024
SA		 8700 u8 idx;
8701
6a899024
SA		 8702 idx = i40e_get_udp_port_idx(pf, port);
8703
8704 /* Check if port already exists */
06a5f7f1
AD		 8705 if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS)
8706 goto not_found;
6a899024 8707
06a5f7f1
AD		 8708 switch (ti->type) {
8709 case UDP_TUNNEL_TYPE_VXLAN:
8710 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN)
8711 goto not_found;
8712 break;
8713 case UDP_TUNNEL_TYPE_GENEVE:
8714 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE)
8715 goto not_found;
8716 break;
8717 default:
8718 goto not_found;
6a899024 8719 }
06a5f7f1
AD		 8720
8721 /* if port exists, set it to 0 (mark for deletion)
8722 * and make it pending
8723 */
8724 pf->udp_ports[idx].index = 0;
8725 pf->pending_udp_bitmap |= BIT_ULL(idx);
8726 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8727
8728 return;
8729not_found:
8730 netdev_warn(netdev, "UDP port %d was not found, not deleting\n",
8731 ntohs(port));
6a899024
SA		 8732}
8733
1f224ad2 8734static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8735 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8736{
8737 struct i40e_netdev_priv *np = netdev_priv(netdev);
8738 struct i40e_pf *pf = np->vsi->back;
8739 struct i40e_hw *hw = &pf->hw;
8740
8741 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8742 return -EOPNOTSUPP;
8743
8744 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8745 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8746
8747 return 0;
8748}
8749
2f90ade6
JB		 8750/**
8751 * i40e_ndo_fdb_add - add an entry to the hardware database
8752 * @ndm: the input from the stack
8753 * @tb: pointer to array of nladdr (unused)
8754 * @dev: the net device pointer
8755 * @addr: the MAC address entry being added
8756 * @flags: instructions from stack about fdb operation
8757 */
4ba0dea5
GR		 8758static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8759 struct net_device *dev,
f6f6424b 8760 const unsigned char *addr, u16 vid,
4ba0dea5 8761 u16 flags)
4ba0dea5
GR		 8762{
8763 struct i40e_netdev_priv *np = netdev_priv(dev);
8764 struct i40e_pf *pf = np->vsi->back;
8765 int err = 0;
8766
8767 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8768 return -EOPNOTSUPP;
8769
65891fea
OG		 8770 if (vid) {
8771 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8772 return -EINVAL;
8773 }
8774
4ba0dea5
GR		 8775 /* Hardware does not support aging addresses so if a
8776 * ndm_state is given only allow permanent addresses
8777 */
8778 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8779 netdev_info(dev, "FDB only supports static addresses\n");
8780 return -EINVAL;
8781 }
8782
8783 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8784 err = dev_uc_add_excl(dev, addr);
8785 else if (is_multicast_ether_addr(addr))
8786 err = dev_mc_add_excl(dev, addr);
8787 else
8788 err = -EINVAL;
8789
8790 /* Only return duplicate errors if NLM_F_EXCL is set */
8791 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8792 err = 0;
8793
8794 return err;
8795}
8796
51616018
NP		 8797/**
8798 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8799 * @dev: the netdev being configured
8800 * @nlh: RTNL message
8801 *
8802 * Inserts a new hardware bridge if not already created and
8803 * enables the bridging mode requested (VEB or VEPA). If the
8804 * hardware bridge has already been inserted and the request
8805 * is to change the mode then that requires a PF reset to
8806 * allow rebuild of the components with required hardware
8807 * bridge mode enabled.
8808 **/
8809static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8810 struct nlmsghdr *nlh,
8811 u16 flags)
51616018
NP		 8812{
8813 struct i40e_netdev_priv *np = netdev_priv(dev);
8814 struct i40e_vsi *vsi = np->vsi;
8815 struct i40e_pf *pf = vsi->back;
8816 struct i40e_veb *veb = NULL;
8817 struct nlattr *attr, *br_spec;
8818 int i, rem;
8819
8820 /* Only for PF VSI for now */
8821 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8822 return -EOPNOTSUPP;
8823
8824 /* Find the HW bridge for PF VSI */
8825 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8826 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8827 veb = pf->veb[i];
8828 }
8829
8830 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8831
8832 nla_for_each_nested(attr, br_spec, rem) {
8833 __u16 mode;
8834
8835 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8836 continue;
8837
8838 mode = nla_get_u16(attr);
8839 if ((mode != BRIDGE_MODE_VEPA) &&
8840 (mode != BRIDGE_MODE_VEB))
8841 return -EINVAL;
8842
8843 /* Insert a new HW bridge */
8844 if (!veb) {
8845 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8846 vsi->tc_config.enabled_tc);
8847 if (veb) {
8848 veb->bridge_mode = mode;
8849 i40e_config_bridge_mode(veb);
8850 } else {
8851 /* No Bridge HW offload available */
8852 return -ENOENT;
8853 }
8854 break;
8855 } else if (mode != veb->bridge_mode) {
8856 /* Existing HW bridge but different mode needs reset */
8857 veb->bridge_mode = mode;
fc60861e
ASJ		 8858 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8859 if (mode == BRIDGE_MODE_VEB)
8860 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8861 else
8862 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8863 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8864 break;
8865 }
8866 }
8867
8868 return 0;
8869}
8870
8871/**
8872 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8873 * @skb: skb buff
8874 * @pid: process id
8875 * @seq: RTNL message seq #
8876 * @dev: the netdev being configured
8877 * @filter_mask: unused
d4b2f9fe 8878 * @nlflags: netlink flags passed in
51616018
NP		 8879 *
8880 * Return the mode in which the hardware bridge is operating in
8881 * i.e VEB or VEPA.
8882 **/
51616018
NP		 8883static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8884 struct net_device *dev,
9f4ffc44
CW		 8885 u32 __always_unused filter_mask,
8886 int nlflags)
51616018
NP		 8887{
8888 struct i40e_netdev_priv *np = netdev_priv(dev);
8889 struct i40e_vsi *vsi = np->vsi;
8890 struct i40e_pf *pf = vsi->back;
8891 struct i40e_veb *veb = NULL;
8892 int i;
8893
8894 /* Only for PF VSI for now */
8895 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8896 return -EOPNOTSUPP;
8897
8898 /* Find the HW bridge for the PF VSI */
8899 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8900 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8901 veb = pf->veb[i];
8902 }
8903
8904 if (!veb)
8905 return 0;
8906
46c264da 8907 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8908 nlflags, 0, 0, filter_mask, NULL);
51616018 8909}
51616018 8910
6a899024
SA		 8911/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
8912 * inner mac plus all inner ethertypes.
8913 */
8914#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 8915/**
8916 * i40e_features_check - Validate encapsulated packet conforms to limits
8917 * @skb: skb buff
2bc11c63 8918 * @dev: This physical port's netdev
f44a75e2
JS		 8919 * @features: Offload features that the stack believes apply
8920 **/
8921static netdev_features_t i40e_features_check(struct sk_buff *skb,
8922 struct net_device *dev,
8923 netdev_features_t features)
8924{
8925 if (skb->encapsulation &&
6a899024 8926 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 8927 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 8928 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 8929
8930 return features;
8931}
8932
37a2973a 8933static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8934 .ndo_open = i40e_open,
8935 .ndo_stop = i40e_close,
8936 .ndo_start_xmit = i40e_lan_xmit_frame,
8937 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8938 .ndo_set_rx_mode = i40e_set_rx_mode,
8939 .ndo_validate_addr = eth_validate_addr,
8940 .ndo_set_mac_address = i40e_set_mac,
8941 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8942 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8943 .ndo_tx_timeout = i40e_tx_timeout,
8944 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8945 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8946#ifdef CONFIG_NET_POLL_CONTROLLER
8947 .ndo_poll_controller = i40e_netpoll,
8948#endif
e4c6734e 8949 .ndo_setup_tc = __i40e_setup_tc,
38e00438
VD		 8950#ifdef I40E_FCOE
8951 .ndo_fcoe_enable = i40e_fcoe_enable,
8952 .ndo_fcoe_disable = i40e_fcoe_disable,
8953#endif
41c445ff
JB		 8954 .ndo_set_features = i40e_set_features,
8955 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8956 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8957 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8958 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8959 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8960 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
c3bbbd20 8961 .ndo_set_vf_trust = i40e_ndo_set_vf_trust,
06a5f7f1
AD		 8962 .ndo_udp_tunnel_add = i40e_udp_tunnel_add,
8963 .ndo_udp_tunnel_del = i40e_udp_tunnel_del,
1f224ad2 8964 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8965 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8966 .ndo_features_check = i40e_features_check,
51616018
NP		 8967 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8968 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8969};
8970
8971/**
8972 * i40e_config_netdev - Setup the netdev flags
8973 * @vsi: the VSI being configured
8974 *
8975 * Returns 0 on success, negative value on failure
8976 **/
8977static int i40e_config_netdev(struct i40e_vsi *vsi)
8978{
1a10370a 8979 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8980 struct i40e_pf *pf = vsi->back;
8981 struct i40e_hw *hw = &pf->hw;
8982 struct i40e_netdev_priv *np;
8983 struct net_device *netdev;
8984 u8 mac_addr[ETH_ALEN];
8985 int etherdev_size;
8986
8987 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8988 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8989 if (!netdev)
8990 return -ENOMEM;
8991
8992 vsi->netdev = netdev;
8993 np = netdev_priv(netdev);
8994 np->vsi = vsi;
8995
b0fe3306
AD		 8996 netdev->hw_enc_features |= NETIF_F_SG |
8997 NETIF_F_IP_CSUM |
8998 NETIF_F_IPV6_CSUM |
8999 NETIF_F_HIGHDMA |
9000 NETIF_F_SOFT_FEATURES |
9001 NETIF_F_TSO |
9002 NETIF_F_TSO_ECN |
9003 NETIF_F_TSO6 |
9004 NETIF_F_GSO_GRE |
1c7b4a23 9005 NETIF_F_GSO_GRE_CSUM |
7e13318d 9006 NETIF_F_GSO_IPXIP4 |
bf2d1df3 9007 NETIF_F_GSO_IPXIP6 |
b0fe3306
AD		 9008 NETIF_F_GSO_UDP_TUNNEL |
9009 NETIF_F_GSO_UDP_TUNNEL_CSUM |
1c7b4a23 9010 NETIF_F_GSO_PARTIAL |
b0fe3306
AD		 9011 NETIF_F_SCTP_CRC |
9012 NETIF_F_RXHASH |
9013 NETIF_F_RXCSUM |
5afdaaa0 9014 0;
41c445ff 9015
b0fe3306 9016 if (!(pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE))
1c7b4a23
AD		 9017 netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
9018
9019 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
b0fe3306
AD		 9020
9021 /* record features VLANs can make use of */
1c7b4a23
AD		 9022 netdev->vlan_features |= netdev->hw_enc_features |
9023 NETIF_F_TSO_MANGLEID;
41c445ff 9024
2e86a0b6 9025 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
b0fe3306
AD		 9026 netdev->hw_features |= NETIF_F_NTUPLE;
9027
9028 netdev->hw_features |= netdev->hw_enc_features |
9029 NETIF_F_HW_VLAN_CTAG_TX |
9030 NETIF_F_HW_VLAN_CTAG_RX;
2e86a0b6 9031
b0fe3306 9032 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
1c7b4a23 9033 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
41c445ff
JB		 9034
9035 if (vsi->type == I40E_VSI_MAIN) {
9036 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 9037 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 9038 /* The following steps are necessary to prevent reception
9039 * of tagged packets - some older NVM configurations load a
9040 * default a MAC-VLAN filter that accepts any tagged packet
9041 * which must be replaced by a normal filter.
8c27d42e 9042 */
21659035
KP		 9043 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
9044 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 9045 i40e_add_filter(vsi, mac_addr,
9046 I40E_VLAN_ANY, false, true);
21659035
KP		 9047 spin_unlock_bh(&vsi->mac_filter_list_lock);
9048 }
3845ccea
ASJ		 9049 } else if ((pf->hw.aq.api_maj_ver > 1) ||
9050 ((pf->hw.aq.api_maj_ver == 1) &&
9051 (pf->hw.aq.api_min_ver > 4))) {
9052 /* Supported in FW API version higher than 1.4 */
9053 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
9054 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
41c445ff
JB		 9055 } else {
9056 /* relate the VSI_VMDQ name to the VSI_MAIN name */
9057 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
9058 pf->vsi[pf->lan_vsi]->netdev->name);
9059 random_ether_addr(mac_addr);
21659035
KP		 9060
9061 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 9062 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 9063 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9064 }
21659035
KP		 9065
9066 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 9067 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 9068 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9069
9a173901
GR		 9070 ether_addr_copy(netdev->dev_addr, mac_addr);
9071 ether_addr_copy(netdev->perm_addr, mac_addr);
b0fe3306 9072
41c445ff
JB		 9073 netdev->priv_flags |= IFF_UNICAST_FLT;
9074 netdev->priv_flags |= IFF_SUPP_NOFCS;
9075 /* Setup netdev TC information */
9076 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9077
9078 netdev->netdev_ops = &i40e_netdev_ops;
9079 netdev->watchdog_timeo = 5 * HZ;
9080 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9081#ifdef I40E_FCOE
9082 i40e_fcoe_config_netdev(netdev, vsi);
9083#endif
41c445ff
JB		 9084
9085 return 0;
9086}
9087
9088/**
9089 * i40e_vsi_delete - Delete a VSI from the switch
9090 * @vsi: the VSI being removed
9091 *
9092 * Returns 0 on success, negative value on failure
9093 **/
9094static void i40e_vsi_delete(struct i40e_vsi *vsi)
9095{
9096 /* remove default VSI is not allowed */
9097 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9098 return;
9099
41c445ff 9100 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9101}
9102
51616018
NP		 9103/**
9104 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9105 * @vsi: the VSI being queried
9106 *
9107 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9108 **/
9109int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9110{
9111 struct i40e_veb *veb;
9112 struct i40e_pf *pf = vsi->back;
9113
9114 /* Uplink is not a bridge so default to VEB */
9115 if (vsi->veb_idx == I40E_NO_VEB)
9116 return 1;
9117
9118 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9119 if (!veb) {
9120 dev_info(&pf->pdev->dev,
9121 "There is no veb associated with the bridge\n");
9122 return -ENOENT;
9123 }
9124
51616018 9125 /* Uplink is a bridge in VEPA mode */
09603eaa 9126 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9127 return 0;
09603eaa
AA		 9128 } else {
9129 /* Uplink is a bridge in VEB mode */
9130 return 1;
9131 }
51616018 9132
09603eaa
AA		 9133 /* VEPA is now default bridge, so return 0 */
9134 return 0;
51616018
NP		 9135}
9136
41c445ff
JB		 9137/**
9138 * i40e_add_vsi - Add a VSI to the switch
9139 * @vsi: the VSI being configured
9140 *
9141 * This initializes a VSI context depending on the VSI type to be added and
9142 * passes it down to the add_vsi aq command.
9143 **/
9144static int i40e_add_vsi(struct i40e_vsi *vsi)
9145{
9146 int ret = -ENODEV;
21659035
KP		 9147 u8 laa_macaddr[ETH_ALEN];
9148 bool found_laa_mac_filter = false;
41c445ff
JB		 9149 struct i40e_pf *pf = vsi->back;
9150 struct i40e_hw *hw = &pf->hw;
9151 struct i40e_vsi_context ctxt;
21659035
KP		 9152 struct i40e_mac_filter *f, *ftmp;
9153
41c445ff
JB		 9154 u8 enabled_tc = 0x1; /* TC0 enabled */
9155 int f_count = 0;
9156
9157 memset(&ctxt, 0, sizeof(ctxt));
9158 switch (vsi->type) {
9159 case I40E_VSI_MAIN:
9160 /* The PF's main VSI is already setup as part of the
9161 * device initialization, so we'll not bother with
9162 * the add_vsi call, but we will retrieve the current
9163 * VSI context.
9164 */
9165 ctxt.seid = pf->main_vsi_seid;
9166 ctxt.pf_num = pf->hw.pf_id;
9167 ctxt.vf_num = 0;
9168 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9169 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9170 if (ret) {
9171 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9172 "couldn't get PF vsi config, err %s aq_err %s\n",
9173 i40e_stat_str(&pf->hw, ret),
9174 i40e_aq_str(&pf->hw,
9175 pf->hw.aq.asq_last_status));
41c445ff
JB		 9176 return -ENOENT;
9177 }
1a2f6248 9178 vsi->info = ctxt.info;
41c445ff
JB		 9179 vsi->info.valid_sections = 0;
9180
9181 vsi->seid = ctxt.seid;
9182 vsi->id = ctxt.vsi_number;
9183
9184 enabled_tc = i40e_pf_get_tc_map(pf);
9185
9186 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9187 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9188 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9189 memset(&ctxt, 0, sizeof(ctxt));
9190 ctxt.seid = pf->main_vsi_seid;
9191 ctxt.pf_num = pf->hw.pf_id;
9192 ctxt.vf_num = 0;
9193 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9194 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9195 if (ret) {
9196 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9197 "update vsi failed, err %s aq_err %s\n",
9198 i40e_stat_str(&pf->hw, ret),
9199 i40e_aq_str(&pf->hw,
9200 pf->hw.aq.asq_last_status));
41c445ff
JB		 9201 ret = -ENOENT;
9202 goto err;
9203 }
9204 /* update the local VSI info queue map */
9205 i40e_vsi_update_queue_map(vsi, &ctxt);
9206 vsi->info.valid_sections = 0;
9207 } else {
9208 /* Default/Main VSI is only enabled for TC0
9209 * reconfigure it to enable all TCs that are
9210 * available on the port in SFP mode.
63d7e5a4
NP		 9211 * For MFP case the iSCSI PF would use this
9212 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9213 */
9214 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9215 if (ret) {
9216 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9217 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9218 enabled_tc,
9219 i40e_stat_str(&pf->hw, ret),
9220 i40e_aq_str(&pf->hw,
9221 pf->hw.aq.asq_last_status));
41c445ff
JB		 9222 ret = -ENOENT;
9223 }
9224 }
9225 break;
9226
9227 case I40E_VSI_FDIR:
cbf61325
ASJ		 9228 ctxt.pf_num = hw->pf_id;
9229 ctxt.vf_num = 0;
9230 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9231 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9232 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9233 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9234 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9235 ctxt.info.valid_sections |=
fc60861e 9236 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9237 ctxt.info.switch_id =
fc60861e 9238 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9239 }
41c445ff 9240 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9241 break;
9242
9243 case I40E_VSI_VMDQ2:
9244 ctxt.pf_num = hw->pf_id;
9245 ctxt.vf_num = 0;
9246 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9247 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9248 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9249
41c445ff
JB		 9250 /* This VSI is connected to VEB so the switch_id
9251 * should be set to zero by default.
9252 */
51616018
NP		 9253 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9254 ctxt.info.valid_sections |=
9255 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9256 ctxt.info.switch_id =
9257 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9258 }
41c445ff
JB		 9259
9260 /* Setup the VSI tx/rx queue map for TC0 only for now */
9261 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9262 break;
9263
9264 case I40E_VSI_SRIOV:
9265 ctxt.pf_num = hw->pf_id;
9266 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9267 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9268 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9269 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9270
41c445ff
JB		 9271 /* This VSI is connected to VEB so the switch_id
9272 * should be set to zero by default.
9273 */
51616018
NP		 9274 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9275 ctxt.info.valid_sections |=
9276 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9277 ctxt.info.switch_id =
9278 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9279 }
41c445ff 9280
e3219ce6
ASJ		 9281 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
9282 ctxt.info.valid_sections |=
9283 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
9284 ctxt.info.queueing_opt_flags |=
4b28cdba
AS		 9285 (I40E_AQ_VSI_QUE_OPT_TCP_ENA |
9286 I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI);
e3219ce6
ASJ		 9287 }
9288
41c445ff
JB		 9289 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9290 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9291 if (pf->vf[vsi->vf_id].spoofchk) {
9292 ctxt.info.valid_sections |=
9293 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9294 ctxt.info.sec_flags |=
9295 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9296 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9297 }
41c445ff
JB		 9298 /* Setup the VSI tx/rx queue map for TC0 only for now */
9299 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9300 break;
9301
38e00438
VD		 9302#ifdef I40E_FCOE
9303 case I40E_VSI_FCOE:
9304 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9305 if (ret) {
9306 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9307 return ret;
9308 }
9309 break;
9310
9311#endif /* I40E_FCOE */
e3219ce6
ASJ		 9312 case I40E_VSI_IWARP:
9313 /* send down message to iWARP */
9314 break;
9315
41c445ff
JB		 9316 default:
9317 return -ENODEV;
9318 }
9319
9320 if (vsi->type != I40E_VSI_MAIN) {
9321 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9322 if (ret) {
9323 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9324 "add vsi failed, err %s aq_err %s\n",
9325 i40e_stat_str(&pf->hw, ret),
9326 i40e_aq_str(&pf->hw,
9327 pf->hw.aq.asq_last_status));
41c445ff
JB		 9328 ret = -ENOENT;
9329 goto err;
9330 }
1a2f6248 9331 vsi->info = ctxt.info;
41c445ff
JB		 9332 vsi->info.valid_sections = 0;
9333 vsi->seid = ctxt.seid;
9334 vsi->id = ctxt.vsi_number;
9335 }
9336
21659035 9337 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9338 /* If macvlan filters already exist, force them to get loaded */
9339 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9340 f->changed = true;
9341 f_count++;
6252c7e4 9342
21659035 9343 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9344 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9345 ether_addr_copy(laa_macaddr, f->macaddr);
9346 found_laa_mac_filter = true;
9347 }
9348 }
9349 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9350
21659035
KP		 9351 if (found_laa_mac_filter) {
9352 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9353
21659035
KP		 9354 memset(&element, 0, sizeof(element));
9355 ether_addr_copy(element.mac_addr, laa_macaddr);
9356 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9357 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9358 &element, 1, NULL);
9359 if (ret) {
9360 /* some older FW has a different default */
9361 element.flags |=
9362 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9363 i40e_aq_remove_macvlan(hw, vsi->seid,
9364 &element, 1, NULL);
6252c7e4 9365 }
21659035
KP		 9366
9367 i40e_aq_mac_address_write(hw,
9368 I40E_AQC_WRITE_TYPE_LAA_WOL,
9369 laa_macaddr, NULL);
41c445ff 9370 }
21659035 9371
41c445ff
JB		 9372 if (f_count) {
9373 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9374 pf->flags |= I40E_FLAG_FILTER_SYNC;
9375 }
9376
9377 /* Update VSI BW information */
9378 ret = i40e_vsi_get_bw_info(vsi);
9379 if (ret) {
9380 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9381 "couldn't get vsi bw info, err %s aq_err %s\n",
9382 i40e_stat_str(&pf->hw, ret),
9383 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9384 /* VSI is already added so not tearing that up */
9385 ret = 0;
9386 }
9387
9388err:
9389 return ret;
9390}
9391
9392/**
9393 * i40e_vsi_release - Delete a VSI and free its resources
9394 * @vsi: the VSI being removed
9395 *
9396 * Returns 0 on success or < 0 on error
9397 **/
9398int i40e_vsi_release(struct i40e_vsi *vsi)
9399{
9400 struct i40e_mac_filter *f, *ftmp;
9401 struct i40e_veb *veb = NULL;
9402 struct i40e_pf *pf;
9403 u16 uplink_seid;
9404 int i, n;
9405
9406 pf = vsi->back;
9407
9408 /* release of a VEB-owner or last VSI is not allowed */
9409 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9410 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9411 vsi->seid, vsi->uplink_seid);
9412 return -ENODEV;
9413 }
9414 if (vsi == pf->vsi[pf->lan_vsi] &&
9415 !test_bit(__I40E_DOWN, &pf->state)) {
9416 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9417 return -ENODEV;
9418 }
9419
9420 uplink_seid = vsi->uplink_seid;
9421 if (vsi->type != I40E_VSI_SRIOV) {
9422 if (vsi->netdev_registered) {
9423 vsi->netdev_registered = false;
9424 if (vsi->netdev) {
9425 /* results in a call to i40e_close() */
9426 unregister_netdev(vsi->netdev);
41c445ff
JB		 9427 }
9428 } else {
90ef8d47 9429 i40e_vsi_close(vsi);
41c445ff
JB		 9430 }
9431 i40e_vsi_disable_irq(vsi);
9432 }
9433
21659035 9434 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9435 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9436 i40e_del_filter(vsi, f->macaddr, f->vlan,
9437 f->is_vf, f->is_netdev);
21659035
KP		 9438 spin_unlock_bh(&vsi->mac_filter_list_lock);
9439
17652c63 9440 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9441
9442 i40e_vsi_delete(vsi);
9443 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9444 if (vsi->netdev) {
9445 free_netdev(vsi->netdev);
9446 vsi->netdev = NULL;
9447 }
41c445ff
JB		 9448 i40e_vsi_clear_rings(vsi);
9449 i40e_vsi_clear(vsi);
9450
9451 /* If this was the last thing on the VEB, except for the
9452 * controlling VSI, remove the VEB, which puts the controlling
9453 * VSI onto the next level down in the switch.
9454 *
9455 * Well, okay, there's one more exception here: don't remove
9456 * the orphan VEBs yet. We'll wait for an explicit remove request
9457 * from up the network stack.
9458 */
505682cd 9459 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9460 if (pf->vsi[i] &&
9461 pf->vsi[i]->uplink_seid == uplink_seid &&
9462 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9463 n++; /* count the VSIs */
9464 }
9465 }
9466 for (i = 0; i < I40E_MAX_VEB; i++) {
9467 if (!pf->veb[i])
9468 continue;
9469 if (pf->veb[i]->uplink_seid == uplink_seid)
9470 n++; /* count the VEBs */
9471 if (pf->veb[i]->seid == uplink_seid)
9472 veb = pf->veb[i];
9473 }
9474 if (n == 0 && veb && veb->uplink_seid != 0)
9475 i40e_veb_release(veb);
9476
9477 return 0;
9478}
9479
9480/**
9481 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9482 * @vsi: ptr to the VSI
9483 *
9484 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9485 * corresponding SW VSI structure and initializes num_queue_pairs for the
9486 * newly allocated VSI.
9487 *
9488 * Returns 0 on success or negative on failure
9489 **/
9490static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9491{
9492 int ret = -ENOENT;
9493 struct i40e_pf *pf = vsi->back;
9494
493fb300 9495 if (vsi->q_vectors[0]) {
41c445ff
JB		 9496 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9497 vsi->seid);
9498 return -EEXIST;
9499 }
9500
9501 if (vsi->base_vector) {
f29eaa3d 9502 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9503 vsi->seid, vsi->base_vector);
9504 return -EEXIST;
9505 }
9506
90e04070 9507 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9508 if (ret) {
9509 dev_info(&pf->pdev->dev,
9510 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9511 vsi->num_q_vectors, vsi->seid, ret);
9512 vsi->num_q_vectors = 0;
9513 goto vector_setup_out;
9514 }
9515
26cdc443
ASJ		 9516 /* In Legacy mode, we do not have to get any other vector since we
9517 * piggyback on the misc/ICR0 for queue interrupts.
9518 */
9519 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9520 return ret;
958a3e3b
SN		 9521 if (vsi->num_q_vectors)
9522 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9523 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9524 if (vsi->base_vector < 0) {
9525 dev_info(&pf->pdev->dev,
049a2be8
SN		 9526 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9527 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9528 i40e_vsi_free_q_vectors(vsi);
9529 ret = -ENOENT;
9530 goto vector_setup_out;
9531 }
9532
9533vector_setup_out:
9534 return ret;
9535}
9536
bc7d338f
ASJ		 9537/**
9538 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9539 * @vsi: pointer to the vsi.
9540 *
9541 * This re-allocates a vsi's queue resources.
9542 *
9543 * Returns pointer to the successfully allocated and configured VSI sw struct
9544 * on success, otherwise returns NULL on failure.
9545 **/
9546static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9547{
f534039d 9548 struct i40e_pf *pf;
bc7d338f
ASJ		 9549 u8 enabled_tc;
9550 int ret;
9551
f534039d
JU		 9552 if (!vsi)
9553 return NULL;
9554
9555 pf = vsi->back;
9556
bc7d338f
ASJ		 9557 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9558 i40e_vsi_clear_rings(vsi);
9559
9560 i40e_vsi_free_arrays(vsi, false);
9561 i40e_set_num_rings_in_vsi(vsi);
9562 ret = i40e_vsi_alloc_arrays(vsi, false);
9563 if (ret)
9564 goto err_vsi;
9565
9566 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9567 if (ret < 0) {
049a2be8 9568 dev_info(&pf->pdev->dev,
f1c7e72e 9569 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9570 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9571 goto err_vsi;
9572 }
9573 vsi->base_queue = ret;
9574
9575 /* Update the FW view of the VSI. Force a reset of TC and queue
9576 * layout configurations.
9577 */
9578 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9579 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9580 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9581 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9582
9583 /* assign it some queues */
9584 ret = i40e_alloc_rings(vsi);
9585 if (ret)
9586 goto err_rings;
9587
9588 /* map all of the rings to the q_vectors */
9589 i40e_vsi_map_rings_to_vectors(vsi);
9590 return vsi;
9591
9592err_rings:
9593 i40e_vsi_free_q_vectors(vsi);
9594 if (vsi->netdev_registered) {
9595 vsi->netdev_registered = false;
9596 unregister_netdev(vsi->netdev);
9597 free_netdev(vsi->netdev);
9598 vsi->netdev = NULL;
9599 }
9600 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9601err_vsi:
9602 i40e_vsi_clear(vsi);
9603 return NULL;
9604}
9605
b499ffb0
SV		 9606/**
9607 * i40e_macaddr_init - explicitly write the mac address filters.
9608 *
9609 * @vsi: pointer to the vsi.
9610 * @macaddr: the MAC address
9611 *
9612 * This is needed when the macaddr has been obtained by other
9613 * means than the default, e.g., from Open Firmware or IDPROM.
9614 * Returns 0 on success, negative on failure
9615 **/
9616static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr)
9617{
9618 int ret;
9619 struct i40e_aqc_add_macvlan_element_data element;
9620
9621 ret = i40e_aq_mac_address_write(&vsi->back->hw,
9622 I40E_AQC_WRITE_TYPE_LAA_WOL,
9623 macaddr, NULL);
9624 if (ret) {
9625 dev_info(&vsi->back->pdev->dev,
9626 "Addr change for VSI failed: %d\n", ret);
9627 return -EADDRNOTAVAIL;
9628 }
9629
9630 memset(&element, 0, sizeof(element));
9631 ether_addr_copy(element.mac_addr, macaddr);
9632 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
9633 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL);
9634 if (ret) {
9635 dev_info(&vsi->back->pdev->dev,
9636 "add filter failed err %s aq_err %s\n",
9637 i40e_stat_str(&vsi->back->hw, ret),
9638 i40e_aq_str(&vsi->back->hw,
9639 vsi->back->hw.aq.asq_last_status));
9640 }
9641 return ret;
9642}
9643
41c445ff
JB		 9644/**
9645 * i40e_vsi_setup - Set up a VSI by a given type
9646 * @pf: board private structure
9647 * @type: VSI type
9648 * @uplink_seid: the switch element to link to
9649 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9650 *
9651 * This allocates the sw VSI structure and its queue resources, then add a VSI
9652 * to the identified VEB.
9653 *
9654 * Returns pointer to the successfully allocated and configure VSI sw struct on
9655 * success, otherwise returns NULL on failure.
9656 **/
9657struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9658 u16 uplink_seid, u32 param1)
9659{
9660 struct i40e_vsi *vsi = NULL;
9661 struct i40e_veb *veb = NULL;
9662 int ret, i;
9663 int v_idx;
9664
9665 /* The requested uplink_seid must be either
9666 * - the PF's port seid
9667 * no VEB is needed because this is the PF
9668 * or this is a Flow Director special case VSI
9669 * - seid of an existing VEB
9670 * - seid of a VSI that owns an existing VEB
9671 * - seid of a VSI that doesn't own a VEB
9672 * a new VEB is created and the VSI becomes the owner
9673 * - seid of the PF VSI, which is what creates the first VEB
9674 * this is a special case of the previous
9675 *
9676 * Find which uplink_seid we were given and create a new VEB if needed
9677 */
9678 for (i = 0; i < I40E_MAX_VEB; i++) {
9679 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9680 veb = pf->veb[i];
9681 break;
9682 }
9683 }
9684
9685 if (!veb && uplink_seid != pf->mac_seid) {
9686
505682cd 9687 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9688 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9689 vsi = pf->vsi[i];
9690 break;
9691 }
9692 }
9693 if (!vsi) {
9694 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9695 uplink_seid);
9696 return NULL;
9697 }
9698
9699 if (vsi->uplink_seid == pf->mac_seid)
9700 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9701 vsi->tc_config.enabled_tc);
9702 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9703 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9704 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9705 if (veb) {
9706 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9707 dev_info(&vsi->back->pdev->dev,
fb43201f 9708 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9709 return NULL;
9710 }
fa11cb3d
ASJ		 9711 /* We come up by default in VEPA mode if SRIOV is not
9712 * already enabled, in which case we can't force VEPA
9713 * mode.
9714 */
9715 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9716 veb->bridge_mode = BRIDGE_MODE_VEPA;
9717 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9718 }
51616018 9719 i40e_config_bridge_mode(veb);
79c21a82 9720 }
41c445ff
JB		 9721 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9722 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9723 veb = pf->veb[i];
9724 }
9725 if (!veb) {
9726 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9727 return NULL;
9728 }
9729
9730 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9731 uplink_seid = veb->seid;
9732 }
9733
9734 /* get vsi sw struct */
9735 v_idx = i40e_vsi_mem_alloc(pf, type);
9736 if (v_idx < 0)
9737 goto err_alloc;
9738 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9739 if (!vsi)
9740 goto err_alloc;
41c445ff
JB		 9741 vsi->type = type;
9742 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9743
9744 if (type == I40E_VSI_MAIN)
9745 pf->lan_vsi = v_idx;
9746 else if (type == I40E_VSI_SRIOV)
9747 vsi->vf_id = param1;
9748 /* assign it some queues */
cbf61325
ASJ		 9749 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9750 vsi->idx);
41c445ff 9751 if (ret < 0) {
049a2be8
SN		 9752 dev_info(&pf->pdev->dev,
9753 "failed to get tracking for %d queues for VSI %d err=%d\n",
9754 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9755 goto err_vsi;
9756 }
9757 vsi->base_queue = ret;
9758
9759 /* get a VSI from the hardware */
9760 vsi->uplink_seid = uplink_seid;
9761 ret = i40e_add_vsi(vsi);
9762 if (ret)
9763 goto err_vsi;
9764
9765 switch (vsi->type) {
9766 /* setup the netdev if needed */
9767 case I40E_VSI_MAIN:
b499ffb0
SV		 9768 /* Apply relevant filters if a platform-specific mac
9769 * address was selected.
9770 */
9771 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
9772 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr);
9773 if (ret) {
9774 dev_warn(&pf->pdev->dev,
9775 "could not set up macaddr; err %d\n",
9776 ret);
9777 }
9778 }
41c445ff 9779 case I40E_VSI_VMDQ2:
38e00438 9780 case I40E_VSI_FCOE:
41c445ff
JB		 9781 ret = i40e_config_netdev(vsi);
9782 if (ret)
9783 goto err_netdev;
9784 ret = register_netdev(vsi->netdev);
9785 if (ret)
9786 goto err_netdev;
9787 vsi->netdev_registered = true;
9788 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9789#ifdef CONFIG_I40E_DCB
9790 /* Setup DCB netlink interface */
9791 i40e_dcbnl_setup(vsi);
9792#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9793 /* fall through */
9794
9795 case I40E_VSI_FDIR:
9796 /* set up vectors and rings if needed */
9797 ret = i40e_vsi_setup_vectors(vsi);
9798 if (ret)
9799 goto err_msix;
9800
9801 ret = i40e_alloc_rings(vsi);
9802 if (ret)
9803 goto err_rings;
9804
9805 /* map all of the rings to the q_vectors */
9806 i40e_vsi_map_rings_to_vectors(vsi);
9807
9808 i40e_vsi_reset_stats(vsi);
9809 break;
9810
9811 default:
9812 /* no netdev or rings for the other VSI types */
9813 break;
9814 }
9815
e25d00b8
ASJ		 9816 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9817 (vsi->type == I40E_VSI_VMDQ2)) {
9818 ret = i40e_vsi_config_rss(vsi);
9819 }
41c445ff
JB		 9820 return vsi;
9821
9822err_rings:
9823 i40e_vsi_free_q_vectors(vsi);
9824err_msix:
9825 if (vsi->netdev_registered) {
9826 vsi->netdev_registered = false;
9827 unregister_netdev(vsi->netdev);
9828 free_netdev(vsi->netdev);
9829 vsi->netdev = NULL;
9830 }
9831err_netdev:
9832 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9833err_vsi:
9834 i40e_vsi_clear(vsi);
9835err_alloc:
9836 return NULL;
9837}
9838
9839/**
9840 * i40e_veb_get_bw_info - Query VEB BW information
9841 * @veb: the veb to query
9842 *
9843 * Query the Tx scheduler BW configuration data for given VEB
9844 **/
9845static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9846{
9847 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9848 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9849 struct i40e_pf *pf = veb->pf;
9850 struct i40e_hw *hw = &pf->hw;
9851 u32 tc_bw_max;
9852 int ret = 0;
9853 int i;
9854
9855 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9856 &bw_data, NULL);
9857 if (ret) {
9858 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9859 "query veb bw config failed, err %s aq_err %s\n",
9860 i40e_stat_str(&pf->hw, ret),
9861 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9862 goto out;
9863 }
9864
9865 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9866 &ets_data, NULL);
9867 if (ret) {
9868 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9869 "query veb bw ets config failed, err %s aq_err %s\n",
9870 i40e_stat_str(&pf->hw, ret),
9871 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9872 goto out;
9873 }
9874
9875 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9876 veb->bw_max_quanta = ets_data.tc_bw_max;
9877 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9878 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9879 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9880 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9881 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9882 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9883 veb->bw_tc_limit_credits[i] =
9884 le16_to_cpu(bw_data.tc_bw_limits[i]);
9885 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9886 }
9887
9888out:
9889 return ret;
9890}
9891
9892/**
9893 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9894 * @pf: board private structure
9895 *
9896 * On error: returns error code (negative)
9897 * On success: returns vsi index in PF (positive)
9898 **/
9899static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9900{
9901 int ret = -ENOENT;
9902 struct i40e_veb *veb;
9903 int i;
9904
9905 /* Need to protect the allocation of switch elements at the PF level */
9906 mutex_lock(&pf->switch_mutex);
9907
9908 /* VEB list may be fragmented if VEB creation/destruction has
9909 * been happening. We can afford to do a quick scan to look
9910 * for any free slots in the list.
9911 *
9912 * find next empty veb slot, looping back around if necessary
9913 */
9914 i = 0;
9915 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9916 i++;
9917 if (i >= I40E_MAX_VEB) {
9918 ret = -ENOMEM;
9919 goto err_alloc_veb; /* out of VEB slots! */
9920 }
9921
9922 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9923 if (!veb) {
9924 ret = -ENOMEM;
9925 goto err_alloc_veb;
9926 }
9927 veb->pf = pf;
9928 veb->idx = i;
9929 veb->enabled_tc = 1;
9930
9931 pf->veb[i] = veb;
9932 ret = i;
9933err_alloc_veb:
9934 mutex_unlock(&pf->switch_mutex);
9935 return ret;
9936}
9937
9938/**
9939 * i40e_switch_branch_release - Delete a branch of the switch tree
9940 * @branch: where to start deleting
9941 *
9942 * This uses recursion to find the tips of the branch to be
9943 * removed, deleting until we get back to and can delete this VEB.
9944 **/
9945static void i40e_switch_branch_release(struct i40e_veb *branch)
9946{
9947 struct i40e_pf *pf = branch->pf;
9948 u16 branch_seid = branch->seid;
9949 u16 veb_idx = branch->idx;
9950 int i;
9951
9952 /* release any VEBs on this VEB - RECURSION */
9953 for (i = 0; i < I40E_MAX_VEB; i++) {
9954 if (!pf->veb[i])
9955 continue;
9956 if (pf->veb[i]->uplink_seid == branch->seid)
9957 i40e_switch_branch_release(pf->veb[i]);
9958 }
9959
9960 /* Release the VSIs on this VEB, but not the owner VSI.
9961 *
9962 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9963 * the VEB itself, so don't use (*branch) after this loop.
9964 */
505682cd 9965 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9966 if (!pf->vsi[i])
9967 continue;
9968 if (pf->vsi[i]->uplink_seid == branch_seid &&
9969 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9970 i40e_vsi_release(pf->vsi[i]);
9971 }
9972 }
9973
9974 /* There's one corner case where the VEB might not have been
9975 * removed, so double check it here and remove it if needed.
9976 * This case happens if the veb was created from the debugfs
9977 * commands and no VSIs were added to it.
9978 */
9979 if (pf->veb[veb_idx])
9980 i40e_veb_release(pf->veb[veb_idx]);
9981}
9982
9983/**
9984 * i40e_veb_clear - remove veb struct
9985 * @veb: the veb to remove
9986 **/
9987static void i40e_veb_clear(struct i40e_veb *veb)
9988{
9989 if (!veb)
9990 return;
9991
9992 if (veb->pf) {
9993 struct i40e_pf *pf = veb->pf;
9994
9995 mutex_lock(&pf->switch_mutex);
9996 if (pf->veb[veb->idx] == veb)
9997 pf->veb[veb->idx] = NULL;
9998 mutex_unlock(&pf->switch_mutex);
9999 }
10000
10001 kfree(veb);
10002}
10003
10004/**
10005 * i40e_veb_release - Delete a VEB and free its resources
10006 * @veb: the VEB being removed
10007 **/
10008void i40e_veb_release(struct i40e_veb *veb)
10009{
10010 struct i40e_vsi *vsi = NULL;
10011 struct i40e_pf *pf;
10012 int i, n = 0;
10013
10014 pf = veb->pf;
10015
10016 /* find the remaining VSI and check for extras */
505682cd 10017 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10018 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
10019 n++;
10020 vsi = pf->vsi[i];
10021 }
10022 }
10023 if (n != 1) {
10024 dev_info(&pf->pdev->dev,
10025 "can't remove VEB %d with %d VSIs left\n",
10026 veb->seid, n);
10027 return;
10028 }
10029
10030 /* move the remaining VSI to uplink veb */
10031 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
10032 if (veb->uplink_seid) {
10033 vsi->uplink_seid = veb->uplink_seid;
10034 if (veb->uplink_seid == pf->mac_seid)
10035 vsi->veb_idx = I40E_NO_VEB;
10036 else
10037 vsi->veb_idx = veb->veb_idx;
10038 } else {
10039 /* floating VEB */
10040 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10041 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
10042 }
10043
10044 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
10045 i40e_veb_clear(veb);
41c445ff
JB		 10046}
10047
10048/**
10049 * i40e_add_veb - create the VEB in the switch
10050 * @veb: the VEB to be instantiated
10051 * @vsi: the controlling VSI
10052 **/
10053static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
10054{
f1c7e72e 10055 struct i40e_pf *pf = veb->pf;
92faef85 10056 bool is_default = veb->pf->cur_promisc;
66fc360a 10057 bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED);
41c445ff
JB		 10058 int ret;
10059
10060 /* get a VEB from the hardware */
f1c7e72e 10061 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95 10062 veb->enabled_tc, is_default,
66fc360a 10063 &veb->seid, enable_stats, NULL);
41c445ff 10064 if (ret) {
f1c7e72e
SN		 10065 dev_info(&pf->pdev->dev,
10066 "couldn't add VEB, err %s aq_err %s\n",
10067 i40e_stat_str(&pf->hw, ret),
10068 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10069 return -EPERM;
10070 }
10071
10072 /* get statistics counter */
f1c7e72e 10073 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 10074 &veb->stats_idx, NULL, NULL, NULL);
10075 if (ret) {
f1c7e72e
SN		 10076 dev_info(&pf->pdev->dev,
10077 "couldn't get VEB statistics idx, err %s aq_err %s\n",
10078 i40e_stat_str(&pf->hw, ret),
10079 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10080 return -EPERM;
10081 }
10082 ret = i40e_veb_get_bw_info(veb);
10083 if (ret) {
f1c7e72e
SN		 10084 dev_info(&pf->pdev->dev,
10085 "couldn't get VEB bw info, err %s aq_err %s\n",
10086 i40e_stat_str(&pf->hw, ret),
10087 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10088 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 10089 return -ENOENT;
10090 }
10091
10092 vsi->uplink_seid = veb->seid;
10093 vsi->veb_idx = veb->idx;
10094 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
10095
10096 return 0;
10097}
10098
10099/**
10100 * i40e_veb_setup - Set up a VEB
10101 * @pf: board private structure
10102 * @flags: VEB setup flags
10103 * @uplink_seid: the switch element to link to
10104 * @vsi_seid: the initial VSI seid
10105 * @enabled_tc: Enabled TC bit-map
10106 *
10107 * This allocates the sw VEB structure and links it into the switch
10108 * It is possible and legal for this to be a duplicate of an already
10109 * existing VEB. It is also possible for both uplink and vsi seids
10110 * to be zero, in order to create a floating VEB.
10111 *
10112 * Returns pointer to the successfully allocated VEB sw struct on
10113 * success, otherwise returns NULL on failure.
10114 **/
10115struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
10116 u16 uplink_seid, u16 vsi_seid,
10117 u8 enabled_tc)
10118{
10119 struct i40e_veb *veb, *uplink_veb = NULL;
10120 int vsi_idx, veb_idx;
10121 int ret;
10122
10123 /* if one seid is 0, the other must be 0 to create a floating relay */
10124 if ((uplink_seid == 0 || vsi_seid == 0) &&
10125 (uplink_seid + vsi_seid != 0)) {
10126 dev_info(&pf->pdev->dev,
10127 "one, not both seid's are 0: uplink=%d vsi=%d\n",
10128 uplink_seid, vsi_seid);
10129 return NULL;
10130 }
10131
10132 /* make sure there is such a vsi and uplink */
505682cd 10133 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10134 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10135 break;
505682cd 10136 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10137 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10138 vsi_seid);
10139 return NULL;
10140 }
10141
10142 if (uplink_seid && uplink_seid != pf->mac_seid) {
10143 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10144 if (pf->veb[veb_idx] &&
10145 pf->veb[veb_idx]->seid == uplink_seid) {
10146 uplink_veb = pf->veb[veb_idx];
10147 break;
10148 }
10149 }
10150 if (!uplink_veb) {
10151 dev_info(&pf->pdev->dev,
10152 "uplink seid %d not found\n", uplink_seid);
10153 return NULL;
10154 }
10155 }
10156
10157 /* get veb sw struct */
10158 veb_idx = i40e_veb_mem_alloc(pf);
10159 if (veb_idx < 0)
10160 goto err_alloc;
10161 veb = pf->veb[veb_idx];
10162 veb->flags = flags;
10163 veb->uplink_seid = uplink_seid;
10164 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10165 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10166
10167 /* create the VEB in the switch */
10168 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10169 if (ret)
10170 goto err_veb;
1bb8b935
SN		 10171 if (vsi_idx == pf->lan_vsi)
10172 pf->lan_veb = veb->idx;
41c445ff
JB		 10173
10174 return veb;
10175
10176err_veb:
10177 i40e_veb_clear(veb);
10178err_alloc:
10179 return NULL;
10180}
10181
10182/**
b40c82e6 10183 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10184 * @pf: board private structure
10185 * @ele: element we are building info from
10186 * @num_reported: total number of elements
10187 * @printconfig: should we print the contents
10188 *
10189 * helper function to assist in extracting a few useful SEID values.
10190 **/
10191static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10192 struct i40e_aqc_switch_config_element_resp *ele,
10193 u16 num_reported, bool printconfig)
10194{
10195 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10196 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10197 u8 element_type = ele->element_type;
10198 u16 seid = le16_to_cpu(ele->seid);
10199
10200 if (printconfig)
10201 dev_info(&pf->pdev->dev,
10202 "type=%d seid=%d uplink=%d downlink=%d\n",
10203 element_type, seid, uplink_seid, downlink_seid);
10204
10205 switch (element_type) {
10206 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10207 pf->mac_seid = seid;
10208 break;
10209 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10210 /* Main VEB? */
10211 if (uplink_seid != pf->mac_seid)
10212 break;
10213 if (pf->lan_veb == I40E_NO_VEB) {
10214 int v;
10215
10216 /* find existing or else empty VEB */
10217 for (v = 0; v < I40E_MAX_VEB; v++) {
10218 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10219 pf->lan_veb = v;
10220 break;
10221 }
10222 }
10223 if (pf->lan_veb == I40E_NO_VEB) {
10224 v = i40e_veb_mem_alloc(pf);
10225 if (v < 0)
10226 break;
10227 pf->lan_veb = v;
10228 }
10229 }
10230
10231 pf->veb[pf->lan_veb]->seid = seid;
10232 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10233 pf->veb[pf->lan_veb]->pf = pf;
10234 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10235 break;
10236 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10237 if (num_reported != 1)
10238 break;
10239 /* This is immediately after a reset so we can assume this is
10240 * the PF's VSI
10241 */
10242 pf->mac_seid = uplink_seid;
10243 pf->pf_seid = downlink_seid;
10244 pf->main_vsi_seid = seid;
10245 if (printconfig)
10246 dev_info(&pf->pdev->dev,
10247 "pf_seid=%d main_vsi_seid=%d\n",
10248 pf->pf_seid, pf->main_vsi_seid);
10249 break;
10250 case I40E_SWITCH_ELEMENT_TYPE_PF:
10251 case I40E_SWITCH_ELEMENT_TYPE_VF:
10252 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10253 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10254 case I40E_SWITCH_ELEMENT_TYPE_PE:
10255 case I40E_SWITCH_ELEMENT_TYPE_PA:
10256 /* ignore these for now */
10257 break;
10258 default:
10259 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10260 element_type, seid);
10261 break;
10262 }
10263}
10264
10265/**
10266 * i40e_fetch_switch_configuration - Get switch config from firmware
10267 * @pf: board private structure
10268 * @printconfig: should we print the contents
10269 *
10270 * Get the current switch configuration from the device and
10271 * extract a few useful SEID values.
10272 **/
10273int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10274{
10275 struct i40e_aqc_get_switch_config_resp *sw_config;
10276 u16 next_seid = 0;
10277 int ret = 0;
10278 u8 *aq_buf;
10279 int i;
10280
10281 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10282 if (!aq_buf)
10283 return -ENOMEM;
10284
10285 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10286 do {
10287 u16 num_reported, num_total;
10288
10289 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10290 I40E_AQ_LARGE_BUF,
10291 &next_seid, NULL);
10292 if (ret) {
10293 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10294 "get switch config failed err %s aq_err %s\n",
10295 i40e_stat_str(&pf->hw, ret),
10296 i40e_aq_str(&pf->hw,
10297 pf->hw.aq.asq_last_status));
41c445ff
JB		 10298 kfree(aq_buf);
10299 return -ENOENT;
10300 }
10301
10302 num_reported = le16_to_cpu(sw_config->header.num_reported);
10303 num_total = le16_to_cpu(sw_config->header.num_total);
10304
10305 if (printconfig)
10306 dev_info(&pf->pdev->dev,
10307 "header: %d reported %d total\n",
10308 num_reported, num_total);
10309
41c445ff
JB		 10310 for (i = 0; i < num_reported; i++) {
10311 struct i40e_aqc_switch_config_element_resp *ele =
10312 &sw_config->element[i];
10313
10314 i40e_setup_pf_switch_element(pf, ele, num_reported,
10315 printconfig);
10316 }
10317 } while (next_seid != 0);
10318
10319 kfree(aq_buf);
10320 return ret;
10321}
10322
10323/**
10324 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10325 * @pf: board private structure
bc7d338f 10326 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10327 *
10328 * Returns 0 on success, negative value on failure
10329 **/
bc7d338f 10330static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 10331{
b5569892 10332 u16 flags = 0;
41c445ff
JB		 10333 int ret;
10334
10335 /* find out what's out there already */
10336 ret = i40e_fetch_switch_configuration(pf, false);
10337 if (ret) {
10338 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10339 "couldn't fetch switch config, err %s aq_err %s\n",
10340 i40e_stat_str(&pf->hw, ret),
10341 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10342 return ret;
10343 }
10344 i40e_pf_reset_stats(pf);
10345
b5569892
ASJ		 10346 /* set the switch config bit for the whole device to
10347 * support limited promisc or true promisc
10348 * when user requests promisc. The default is limited
10349 * promisc.
10350 */
10351
10352 if ((pf->hw.pf_id == 0) &&
10353 !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT))
10354 flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
10355
10356 if (pf->hw.pf_id == 0) {
10357 u16 valid_flags;
10358
10359 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
10360 ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags,
10361 NULL);
10362 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
10363 dev_info(&pf->pdev->dev,
10364 "couldn't set switch config bits, err %s aq_err %s\n",
10365 i40e_stat_str(&pf->hw, ret),
10366 i40e_aq_str(&pf->hw,
10367 pf->hw.aq.asq_last_status));
10368 /* not a fatal problem, just keep going */
10369 }
10370 }
10371
41c445ff 10372 /* first time setup */
bc7d338f 10373 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10374 struct i40e_vsi *vsi = NULL;
10375 u16 uplink_seid;
10376
10377 /* Set up the PF VSI associated with the PF's main VSI
10378 * that is already in the HW switch
10379 */
10380 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10381 uplink_seid = pf->veb[pf->lan_veb]->seid;
10382 else
10383 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10384 if (pf->lan_vsi == I40E_NO_VSI)
10385 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10386 else if (reinit)
10387 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10388 if (!vsi) {
10389 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10390 i40e_fdir_teardown(pf);
10391 return -EAGAIN;
10392 }
41c445ff
JB		 10393 } else {
10394 /* force a reset of TC and queue layout configurations */
10395 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10396
41c445ff
JB		 10397 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10398 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10399 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10400 }
10401 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10402
cbf61325
ASJ		 10403 i40e_fdir_sb_setup(pf);
10404
41c445ff
JB		 10405 /* Setup static PF queue filter control settings */
10406 ret = i40e_setup_pf_filter_control(pf);
10407 if (ret) {
10408 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10409 ret);
10410 /* Failure here should not stop continuing other steps */
10411 }
10412
10413 /* enable RSS in the HW, even for only one queue, as the stack can use
10414 * the hash
10415 */
10416 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10417 i40e_pf_config_rss(pf);
41c445ff
JB		 10418
10419 /* fill in link information and enable LSE reporting */
0a862b43 10420 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10421 i40e_link_event(pf);
10422
d52c20b7 10423 /* Initialize user-specific link properties */
41c445ff
JB		 10424 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10425 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10426
beb0dff1
JK		 10427 i40e_ptp_init(pf);
10428
41c445ff
JB		 10429 return ret;
10430}
10431
41c445ff
JB		 10432/**
10433 * i40e_determine_queue_usage - Work out queue distribution
10434 * @pf: board private structure
10435 **/
10436static void i40e_determine_queue_usage(struct i40e_pf *pf)
10437{
41c445ff
JB		 10438 int queues_left;
10439
10440 pf->num_lan_qps = 0;
38e00438
VD		 10441#ifdef I40E_FCOE
10442 pf->num_fcoe_qps = 0;
10443#endif
41c445ff
JB		 10444
10445 /* Find the max queues to be put into basic use. We'll always be
10446 * using TC0, whether or not DCB is running, and TC0 will get the
10447 * big RSS set.
10448 */
10449 queues_left = pf->hw.func_caps.num_tx_qp;
10450
cbf61325 10451 if ((queues_left == 1) ||
9aa7e935 10452 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10453 /* one qp for PF, no queues for anything else */
10454 queues_left = 0;
acd65448 10455 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10456
10457 /* make sure all the fancies are disabled */
60ea5f83 10458 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10459 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10460#ifdef I40E_FCOE
10461 I40E_FLAG_FCOE_ENABLED |
10462#endif
60ea5f83
JB		 10463 I40E_FLAG_FD_SB_ENABLED |
10464 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10465 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10466 I40E_FLAG_SRIOV_ENABLED |
10467 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10468 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10469 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10470 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10471 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10472 /* one qp for PF */
acd65448 10473 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10474 queues_left -= pf->num_lan_qps;
10475
10476 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10477 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10478#ifdef I40E_FCOE
10479 I40E_FLAG_FCOE_ENABLED |
10480#endif
9aa7e935
FZ		 10481 I40E_FLAG_FD_SB_ENABLED |
10482 I40E_FLAG_FD_ATR_ENABLED |
10483 I40E_FLAG_DCB_ENABLED |
10484 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10485 } else {
cbf61325 10486 /* Not enough queues for all TCs */
4d9b6043 10487 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10488 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10489 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10490 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10491 }
9a3bd2f1
ASJ		 10492 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10493 num_online_cpus());
10494 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10495 pf->hw.func_caps.num_tx_qp);
10496
cbf61325
ASJ		 10497 queues_left -= pf->num_lan_qps;
10498 }
10499
38e00438
VD		 10500#ifdef I40E_FCOE
10501 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10502 if (I40E_DEFAULT_FCOE <= queues_left) {
10503 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10504 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10505 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10506 } else {
10507 pf->num_fcoe_qps = 0;
10508 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10509 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10510 }
10511
10512 queues_left -= pf->num_fcoe_qps;
10513 }
10514
10515#endif
cbf61325
ASJ		 10516 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10517 if (queues_left > 1) {
10518 queues_left -= 1; /* save 1 queue for FD */
10519 } else {
10520 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10521 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10522 }
41c445ff
JB		 10523 }
10524
10525 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10526 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10527 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10528 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10529 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10530 }
10531
10532 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10533 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10534 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10535 (queues_left / pf->num_vmdq_qps));
10536 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10537 }
10538
f8ff1464 10539 pf->queues_left = queues_left;
8279e495
NP		 10540 dev_dbg(&pf->pdev->dev,
10541 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10542 pf->hw.func_caps.num_tx_qp,
10543 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10544 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10545 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10546 queues_left);
38e00438 10547#ifdef I40E_FCOE
8279e495 10548 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10549#endif
41c445ff
JB		 10550}
10551
10552/**
10553 * i40e_setup_pf_filter_control - Setup PF static filter control
10554 * @pf: PF to be setup
10555 *
b40c82e6 10556 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10557 * settings. If PE/FCoE are enabled then it will also set the per PF
10558 * based filter sizes required for them. It also enables Flow director,
10559 * ethertype and macvlan type filter settings for the pf.
10560 *
10561 * Returns 0 on success, negative on failure
10562 **/
10563static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10564{
10565 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10566
10567 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10568
10569 /* Flow Director is enabled */
60ea5f83 10570 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10571 settings->enable_fdir = true;
10572
10573 /* Ethtype and MACVLAN filters enabled for PF */
10574 settings->enable_ethtype = true;
10575 settings->enable_macvlan = true;
10576
10577 if (i40e_set_filter_control(&pf->hw, settings))
10578 return -ENOENT;
10579
10580 return 0;
10581}
10582
0c22b3dd 10583#define INFO_STRING_LEN 255
7fd89545 10584#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10585static void i40e_print_features(struct i40e_pf *pf)
10586{
10587 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10588 char *buf;
10589 int i;
0c22b3dd 10590
3b195843
JP		 10591 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10592 if (!buf)
0c22b3dd 10593 return;
0c22b3dd 10594
3b195843 10595 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10596#ifdef CONFIG_PCI_IOV
3b195843 10597 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10598#endif
1a557afc 10599 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d",
7fd89545 10600 pf->hw.func_caps.num_vsis,
1a557afc 10601 pf->vsi[pf->lan_vsi]->num_queue_pairs);
0c22b3dd 10602 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10603 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10604 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10605 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10606 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10607 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10608 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10609 }
4d9b6043 10610 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10611 i += snprintf(&buf[i], REMAIN(i), " DCB");
3b195843 10612 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024 10613 i += snprintf(&buf[i], REMAIN(i), " Geneve");
0c22b3dd 10614 if (pf->flags & I40E_FLAG_PTP)
3b195843 10615 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10616#ifdef I40E_FCOE
10617 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10618 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10619#endif
6dec1017 10620 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10621 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10622 else
3b195843 10623 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10624
3b195843
JP		 10625 dev_info(&pf->pdev->dev, "%s\n", buf);
10626 kfree(buf);
7fd89545 10627 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10628}
10629
b499ffb0
SV		 10630/**
10631 * i40e_get_platform_mac_addr - get platform-specific MAC address
10632 *
10633 * @pdev: PCI device information struct
10634 * @pf: board private structure
10635 *
10636 * Look up the MAC address in Open Firmware on systems that support it,
10637 * and use IDPROM on SPARC if no OF address is found. On return, the
10638 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value
10639 * has been selected.
10640 **/
10641static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
10642{
b499ffb0 10643 pf->flags &= ~I40E_FLAG_PF_MAC;
ba94272d 10644 if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr))
b499ffb0 10645 pf->flags |= I40E_FLAG_PF_MAC;
b499ffb0
SV		 10646}
10647
41c445ff
JB		 10648/**
10649 * i40e_probe - Device initialization routine
10650 * @pdev: PCI device information struct
10651 * @ent: entry in i40e_pci_tbl
10652 *
b40c82e6
JK		 10653 * i40e_probe initializes a PF identified by a pci_dev structure.
10654 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10655 * and a hardware reset occur.
10656 *
10657 * Returns 0 on success, negative on failure
10658 **/
10659static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10660{
e827845c 10661 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10662 struct i40e_pf *pf;
10663 struct i40e_hw *hw;
93cd765b 10664 static u16 pfs_found;
1d5109d1 10665 u16 wol_nvm_bits;
d4dfb81a 10666 u16 link_status;
6f66a484 10667 int err;
4f2f017c 10668 u32 val;
8a9eb7d3 10669 u32 i;
58fc3267 10670 u8 set_fc_aq_fail;
41c445ff
JB		 10671
10672 err = pci_enable_device_mem(pdev);
10673 if (err)
10674 return err;
10675
10676 /* set up for high or low dma */
6494294f 10677 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10678 if (err) {
e3e3bfdd
JS		 10679 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10680 if (err) {
10681 dev_err(&pdev->dev,
10682 "DMA configuration failed: 0x%x\n", err);
10683 goto err_dma;
10684 }
41c445ff
JB		 10685 }
10686
10687 /* set up pci connections */
10688 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10689 IORESOURCE_MEM), i40e_driver_name);
10690 if (err) {
10691 dev_info(&pdev->dev,
10692 "pci_request_selected_regions failed %d\n", err);
10693 goto err_pci_reg;
10694 }
10695
10696 pci_enable_pcie_error_reporting(pdev);
10697 pci_set_master(pdev);
10698
10699 /* Now that we have a PCI connection, we need to do the
10700 * low level device setup. This is primarily setting up
10701 * the Admin Queue structures and then querying for the
10702 * device's current profile information.
10703 */
10704 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10705 if (!pf) {
10706 err = -ENOMEM;
10707 goto err_pf_alloc;
10708 }
10709 pf->next_vsi = 0;
10710 pf->pdev = pdev;
10711 set_bit(__I40E_DOWN, &pf->state);
10712
10713 hw = &pf->hw;
10714 hw->back = pf;
232f4706 10715
2ac8b675
SN		 10716 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10717 I40E_MAX_CSR_SPACE);
232f4706 10718
2ac8b675 10719 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10720 if (!hw->hw_addr) {
10721 err = -EIO;
10722 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10723 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10724 pf->ioremap_len, err);
41c445ff
JB		 10725 goto err_ioremap;
10726 }
10727 hw->vendor_id = pdev->vendor;
10728 hw->device_id = pdev->device;
10729 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10730 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10731 hw->subsystem_device_id = pdev->subsystem_device;
10732 hw->bus.device = PCI_SLOT(pdev->devfn);
10733 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10734 pf->instance = pfs_found;
41c445ff 10735
de03d2b0
SN		 10736 /* set up the locks for the AQ, do this only once in probe
10737 * and destroy them only once in remove
10738 */
10739 mutex_init(&hw->aq.asq_mutex);
10740 mutex_init(&hw->aq.arq_mutex);
10741
5b5faa43
SN		 10742 if (debug != -1) {
10743 pf->msg_enable = pf->hw.debug_mask;
10744 pf->msg_enable = debug;
10745 }
10746
7134f9ce
JB		 10747 /* do a special CORER for clearing PXE mode once at init */
10748 if (hw->revision_id == 0 &&
10749 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10750 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10751 i40e_flush(hw);
10752 msleep(200);
10753 pf->corer_count++;
10754
10755 i40e_clear_pxe_mode(hw);
10756 }
10757
41c445ff 10758 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10759 i40e_clear_hw(hw);
41c445ff
JB		 10760 err = i40e_pf_reset(hw);
10761 if (err) {
10762 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10763 goto err_pf_reset;
10764 }
10765 pf->pfr_count++;
10766
10767 hw->aq.num_arq_entries = I40E_AQ_LEN;
10768 hw->aq.num_asq_entries = I40E_AQ_LEN;
10769 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10770 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10771 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10772
b294ac70 10773 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10774 "%s-%s:misc",
10775 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10776
10777 err = i40e_init_shared_code(hw);
10778 if (err) {
b2a75c58
ASJ		 10779 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10780 err);
41c445ff
JB		 10781 goto err_pf_reset;
10782 }
10783
d52c20b7
JB		 10784 /* set up a default setting for link flow control */
10785 pf->hw.fc.requested_mode = I40E_FC_NONE;
10786
41c445ff 10787 err = i40e_init_adminq(hw);
2b2426a7
CW		 10788 if (err) {
10789 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10790 dev_info(&pdev->dev,
10791 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10792 else
10793 dev_info(&pdev->dev,
10794 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10795
10796 goto err_pf_reset;
10797 }
f0b44440 10798
6dec1017
SN		 10799 /* provide nvm, fw, api versions */
10800 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10801 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10802 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10803 i40e_nvm_version_str(hw));
f0b44440 10804
7aa67613
CS		 10805 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10806 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10807 dev_info(&pdev->dev,
7aa67613
CS		 10808 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10809 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10810 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10811 dev_info(&pdev->dev,
7aa67613 10812 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10813
4eb3f768
SN		 10814 i40e_verify_eeprom(pf);
10815
2c5fe33b
JB		 10816 /* Rev 0 hardware was never productized */
10817 if (hw->revision_id < 1)
10818 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10819
6ff4ef86 10820 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10821 err = i40e_get_capabilities(pf);
10822 if (err)
10823 goto err_adminq_setup;
10824
10825 err = i40e_sw_init(pf);
10826 if (err) {
10827 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10828 goto err_sw_init;
10829 }
10830
10831 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10832 hw->func_caps.num_rx_qp,
10833 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10834 if (err) {
10835 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10836 goto err_init_lan_hmc;
10837 }
10838
10839 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10840 if (err) {
10841 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10842 err = -ENOENT;
10843 goto err_configure_lan_hmc;
10844 }
10845
b686ece5
NP		 10846 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10847 * Ignore error return codes because if it was already disabled via
10848 * hardware settings this will fail
10849 */
f1bbad33 10850 if (pf->flags & I40E_FLAG_STOP_FW_LLDP) {
b686ece5
NP		 10851 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10852 i40e_aq_stop_lldp(hw, true, NULL);
10853 }
10854
41c445ff 10855 i40e_get_mac_addr(hw, hw->mac.addr);
b499ffb0
SV		 10856 /* allow a platform config to override the HW addr */
10857 i40e_get_platform_mac_addr(pdev, pf);
f62b5060 10858 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10859 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10860 err = -EIO;
10861 goto err_mac_addr;
10862 }
10863 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10864 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10865 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10866 if (is_valid_ether_addr(hw->mac.port_addr))
10867 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10868#ifdef I40E_FCOE
10869 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10870 if (err)
10871 dev_info(&pdev->dev,
10872 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10873 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10874 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10875 hw->mac.san_addr);
10876 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10877 }
10878 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10879#endif /* I40E_FCOE */
41c445ff
JB		 10880
10881 pci_set_drvdata(pdev, pf);
10882 pci_save_state(pdev);
4e3b35b0
NP		 10883#ifdef CONFIG_I40E_DCB
10884 err = i40e_init_pf_dcb(pf);
10885 if (err) {
aebfc816 10886 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10887 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10888 /* Continue without DCB enabled */
4e3b35b0
NP		 10889 }
10890#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10891
10892 /* set up periodic task facility */
10893 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10894 pf->service_timer_period = HZ;
10895
10896 INIT_WORK(&pf->service_task, i40e_service_task);
10897 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10898 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10899
1d5109d1
SN		 10900 /* NVM bit on means WoL disabled for the port */
10901 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10902 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10903 pf->wol_en = false;
10904 else
10905 pf->wol_en = true;
8e2773ae
SN		 10906 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10907
41c445ff
JB		 10908 /* set up the main switch operations */
10909 i40e_determine_queue_usage(pf);
c1147280
JB		 10910 err = i40e_init_interrupt_scheme(pf);
10911 if (err)
10912 goto err_switch_setup;
41c445ff 10913
505682cd
MW		 10914 /* The number of VSIs reported by the FW is the minimum guaranteed
10915 * to us; HW supports far more and we share the remaining pool with
10916 * the other PFs. We allocate space for more than the guarantee with
10917 * the understanding that we might not get them all later.
41c445ff 10918 */
505682cd
MW		 10919 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10920 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10921 else
10922 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10923
10924 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
d17038d6
JB		 10925 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
10926 GFP_KERNEL);
ed87ac09
WY		 10927 if (!pf->vsi) {
10928 err = -ENOMEM;
41c445ff 10929 goto err_switch_setup;
ed87ac09 10930 }
41c445ff 10931
fa11cb3d
ASJ		 10932#ifdef CONFIG_PCI_IOV
10933 /* prep for VF support */
10934 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10935 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10936 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10937 if (pci_num_vf(pdev))
10938 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10939 }
10940#endif
bc7d338f 10941 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10942 if (err) {
10943 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10944 goto err_vsis;
10945 }
58fc3267
HZ		 10946
10947 /* Make sure flow control is set according to current settings */
10948 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10949 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10950 dev_dbg(&pf->pdev->dev,
10951 "Set fc with err %s aq_err %s on get_phy_cap\n",
10952 i40e_stat_str(hw, err),
10953 i40e_aq_str(hw, hw->aq.asq_last_status));
10954 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10955 dev_dbg(&pf->pdev->dev,
10956 "Set fc with err %s aq_err %s on set_phy_config\n",
10957 i40e_stat_str(hw, err),
10958 i40e_aq_str(hw, hw->aq.asq_last_status));
10959 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10960 dev_dbg(&pf->pdev->dev,
10961 "Set fc with err %s aq_err %s on get_link_info\n",
10962 i40e_stat_str(hw, err),
10963 i40e_aq_str(hw, hw->aq.asq_last_status));
10964
8a9eb7d3 10965 /* if FDIR VSI was set up, start it now */
505682cd 10966 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10967 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10968 i40e_vsi_open(pf->vsi[i]);
10969 break;
10970 }
10971 }
41c445ff 10972
2f0aff41
SN		 10973 /* The driver only wants link up/down and module qualification
10974 * reports from firmware. Note the negative logic.
7e2453fe
JB		 10975 */
10976 err = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 10977 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 10978 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 10979 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 10980 if (err)
f1c7e72e
SN		 10981 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10982 i40e_stat_str(&pf->hw, err),
10983 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10984
4f2f017c
ASJ		 10985 /* Reconfigure hardware for allowing smaller MSS in the case
10986 * of TSO, so that we avoid the MDD being fired and causing
10987 * a reset in the case of small MSS+TSO.
10988 */
10989 val = rd32(hw, I40E_REG_MSS);
10990 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10991 val &= ~I40E_REG_MSS_MIN_MASK;
10992 val |= I40E_64BYTE_MSS;
10993 wr32(hw, I40E_REG_MSS, val);
10994 }
10995
8eed76fa 10996 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 10997 msleep(75);
10998 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10999 if (err)
f1c7e72e
SN		 11000 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
11001 i40e_stat_str(&pf->hw, err),
11002 i40e_aq_str(&pf->hw,
11003 pf->hw.aq.asq_last_status));
cafa2ee6 11004 }
41c445ff
JB		 11005 /* The main driver is (mostly) up and happy. We need to set this state
11006 * before setting up the misc vector or we get a race and the vector
11007 * ends up disabled forever.
11008 */
11009 clear_bit(__I40E_DOWN, &pf->state);
11010
11011 /* In case of MSIX we are going to setup the misc vector right here
11012 * to handle admin queue events etc. In case of legacy and MSI
11013 * the misc functionality and queue processing is combined in
11014 * the same vector and that gets setup at open.
11015 */
11016 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
11017 err = i40e_setup_misc_vector(pf);
11018 if (err) {
11019 dev_info(&pdev->dev,
11020 "setup of misc vector failed: %d\n", err);
11021 goto err_vsis;
11022 }
11023 }
11024
df805f62 11025#ifdef CONFIG_PCI_IOV
41c445ff
JB		 11026 /* prep for VF support */
11027 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 11028 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11029 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 11030 /* disable link interrupts for VFs */
11031 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
11032 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
11033 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
11034 i40e_flush(hw);
4aeec010
MW		 11035
11036 if (pci_num_vf(pdev)) {
11037 dev_info(&pdev->dev,
11038 "Active VFs found, allocating resources.\n");
11039 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
11040 if (err)
11041 dev_info(&pdev->dev,
11042 "Error %d allocating resources for existing VFs\n",
11043 err);
11044 }
41c445ff 11045 }
df805f62 11046#endif /* CONFIG_PCI_IOV */
41c445ff 11047
e3219ce6
ASJ		 11048 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
11049 pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile,
11050 pf->num_iwarp_msix,
11051 I40E_IWARP_IRQ_PILE_ID);
11052 if (pf->iwarp_base_vector < 0) {
11053 dev_info(&pdev->dev,
11054 "failed to get tracking for %d vectors for IWARP err=%d\n",
11055 pf->num_iwarp_msix, pf->iwarp_base_vector);
11056 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
11057 }
11058 }
93cd765b 11059
41c445ff
JB		 11060 i40e_dbg_pf_init(pf);
11061
11062 /* tell the firmware that we're starting */
44033fac 11063 i40e_send_version(pf);
41c445ff
JB		 11064
11065 /* since everything's happy, start the service_task timer */
11066 mod_timer(&pf->service_timer,
11067 round_jiffies(jiffies + pf->service_timer_period));
11068
e3219ce6
ASJ		 11069 /* add this PF to client device list and launch a client service task */
11070 err = i40e_lan_add_device(pf);
11071 if (err)
11072 dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n",
11073 err);
11074
38e00438
VD		 11075#ifdef I40E_FCOE
11076 /* create FCoE interface */
11077 i40e_fcoe_vsi_setup(pf);
11078
11079#endif
3fced535
ASJ		 11080#define PCI_SPEED_SIZE 8
11081#define PCI_WIDTH_SIZE 8
11082 /* Devices on the IOSF bus do not have this information
11083 * and will report PCI Gen 1 x 1 by default so don't bother
11084 * checking them.
11085 */
11086 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
11087 char speed[PCI_SPEED_SIZE] = "Unknown";
11088 char width[PCI_WIDTH_SIZE] = "Unknown";
11089
11090 /* Get the negotiated link width and speed from PCI config
11091 * space
11092 */
11093 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
11094 &link_status);
11095
11096 i40e_set_pci_config_data(hw, link_status);
11097
11098 switch (hw->bus.speed) {
11099 case i40e_bus_speed_8000:
11100 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
11101 case i40e_bus_speed_5000:
11102 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
11103 case i40e_bus_speed_2500:
11104 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
11105 default:
11106 break;
11107 }
11108 switch (hw->bus.width) {
11109 case i40e_bus_width_pcie_x8:
11110 strncpy(width, "8", PCI_WIDTH_SIZE); break;
11111 case i40e_bus_width_pcie_x4:
11112 strncpy(width, "4", PCI_WIDTH_SIZE); break;
11113 case i40e_bus_width_pcie_x2:
11114 strncpy(width, "2", PCI_WIDTH_SIZE); break;
11115 case i40e_bus_width_pcie_x1:
11116 strncpy(width, "1", PCI_WIDTH_SIZE); break;
11117 default:
11118 break;
11119 }
11120
11121 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
11122 speed, width);
11123
11124 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
11125 hw->bus.speed < i40e_bus_speed_8000) {
11126 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
11127 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
11128 }
d4dfb81a
CS		 11129 }
11130
e827845c
CS		 11131 /* get the requested speeds from the fw */
11132 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
11133 if (err)
8279e495
NP		 11134 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
11135 i40e_stat_str(&pf->hw, err),
11136 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 11137 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
11138
fc72dbce
CS		 11139 /* get the supported phy types from the fw */
11140 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
11141 if (err)
11142 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
11143 i40e_stat_str(&pf->hw, err),
11144 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11145 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
11146
e7358f54
ASJ		 11147 /* Add a filter to drop all Flow control frames from any VSI from being
11148 * transmitted. By doing so we stop a malicious VF from sending out
11149 * PAUSE or PFC frames and potentially controlling traffic for other
11150 * PF/VF VSIs.
11151 * The FW can still send Flow control frames if enabled.
11152 */
11153 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11154 pf->main_vsi_seid);
11155
31b606d0
CW		 11156 if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
11157 (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
11158 pf->flags |= I40E_FLAG_HAVE_10GBASET_PHY;
11159
0c22b3dd
JB		 11160 /* print a string summarizing features */
11161 i40e_print_features(pf);
11162
41c445ff
JB		 11163 return 0;
11164
11165 /* Unwind what we've done if something failed in the setup */
11166err_vsis:
11167 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 11168 i40e_clear_interrupt_scheme(pf);
11169 kfree(pf->vsi);
04b03013
SN		 11170err_switch_setup:
11171 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 11172 del_timer_sync(&pf->service_timer);
11173err_mac_addr:
11174err_configure_lan_hmc:
11175 (void)i40e_shutdown_lan_hmc(hw);
11176err_init_lan_hmc:
11177 kfree(pf->qp_pile);
41c445ff
JB		 11178err_sw_init:
11179err_adminq_setup:
41c445ff
JB		 11180err_pf_reset:
11181 iounmap(hw->hw_addr);
11182err_ioremap:
11183 kfree(pf);
11184err_pf_alloc:
11185 pci_disable_pcie_error_reporting(pdev);
11186 pci_release_selected_regions(pdev,
11187 pci_select_bars(pdev, IORESOURCE_MEM));
11188err_pci_reg:
11189err_dma:
11190 pci_disable_device(pdev);
11191 return err;
11192}
11193
11194/**
11195 * i40e_remove - Device removal routine
11196 * @pdev: PCI device information struct
11197 *
11198 * i40e_remove is called by the PCI subsystem to alert the driver
11199 * that is should release a PCI device. This could be caused by a
11200 * Hot-Plug event, or because the driver is going to be removed from
11201 * memory.
11202 **/
11203static void i40e_remove(struct pci_dev *pdev)
11204{
11205 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11206 struct i40e_hw *hw = &pf->hw;
41c445ff 11207 i40e_status ret_code;
41c445ff
JB		 11208 int i;
11209
11210 i40e_dbg_pf_exit(pf);
11211
beb0dff1
JK		 11212 i40e_ptp_stop(pf);
11213
bcab2db9 11214 /* Disable RSS in hw */
272cdaf2
SN		 11215 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
11216 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
bcab2db9 11217
41c445ff 11218 /* no more scheduling of any task */
a4618ec8 11219 set_bit(__I40E_SUSPENDED, &pf->state);
41c445ff 11220 set_bit(__I40E_DOWN, &pf->state);
c99abb4c
SN		 11221 if (pf->service_timer.data)
11222 del_timer_sync(&pf->service_timer);
11223 if (pf->service_task.func)
11224 cancel_work_sync(&pf->service_task);
41c445ff 11225
eb2d80bc
MW		 11226 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11227 i40e_free_vfs(pf);
11228 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11229 }
11230
41c445ff
JB		 11231 i40e_fdir_teardown(pf);
11232
11233 /* If there is a switch structure or any orphans, remove them.
11234 * This will leave only the PF's VSI remaining.
11235 */
11236 for (i = 0; i < I40E_MAX_VEB; i++) {
11237 if (!pf->veb[i])
11238 continue;
11239
11240 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11241 pf->veb[i]->uplink_seid == 0)
11242 i40e_switch_branch_release(pf->veb[i]);
11243 }
11244
11245 /* Now we can shutdown the PF's VSI, just before we kill
11246 * adminq and hmc.
11247 */
11248 if (pf->vsi[pf->lan_vsi])
11249 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11250
e3219ce6
ASJ		 11251 /* remove attached clients */
11252 ret_code = i40e_lan_del_device(pf);
11253 if (ret_code) {
11254 dev_warn(&pdev->dev, "Failed to delete client device: %d\n",
11255 ret_code);
11256 }
11257
41c445ff 11258 /* shutdown and destroy the HMC */
f734dfff
JB		 11259 if (hw->hmc.hmc_obj) {
11260 ret_code = i40e_shutdown_lan_hmc(hw);
60442dea
SN		 11261 if (ret_code)
11262 dev_warn(&pdev->dev,
11263 "Failed to destroy the HMC resources: %d\n",
11264 ret_code);
11265 }
41c445ff
JB		 11266
11267 /* shutdown the adminq */
f734dfff 11268 ret_code = i40e_shutdown_adminq(hw);
41c445ff
JB		 11269 if (ret_code)
11270 dev_warn(&pdev->dev,
11271 "Failed to destroy the Admin Queue resources: %d\n",
11272 ret_code);
11273
8ddb3326
JB		 11274 /* destroy the locks only once, here */
11275 mutex_destroy(&hw->aq.arq_mutex);
11276 mutex_destroy(&hw->aq.asq_mutex);
11277
41c445ff
JB		 11278 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11279 i40e_clear_interrupt_scheme(pf);
505682cd 11280 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11281 if (pf->vsi[i]) {
11282 i40e_vsi_clear_rings(pf->vsi[i]);
11283 i40e_vsi_clear(pf->vsi[i]);
11284 pf->vsi[i] = NULL;
11285 }
11286 }
11287
11288 for (i = 0; i < I40E_MAX_VEB; i++) {
11289 kfree(pf->veb[i]);
11290 pf->veb[i] = NULL;
11291 }
11292
11293 kfree(pf->qp_pile);
41c445ff
JB		 11294 kfree(pf->vsi);
11295
f734dfff 11296 iounmap(hw->hw_addr);
41c445ff
JB		 11297 kfree(pf);
11298 pci_release_selected_regions(pdev,
11299 pci_select_bars(pdev, IORESOURCE_MEM));
11300
11301 pci_disable_pcie_error_reporting(pdev);
11302 pci_disable_device(pdev);
11303}
11304
11305/**
11306 * i40e_pci_error_detected - warning that something funky happened in PCI land
11307 * @pdev: PCI device information struct
11308 *
11309 * Called to warn that something happened and the error handling steps
11310 * are in progress. Allows the driver to quiesce things, be ready for
11311 * remediation.
11312 **/
11313static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11314 enum pci_channel_state error)
11315{
11316 struct i40e_pf *pf = pci_get_drvdata(pdev);
11317
11318 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11319
11320 /* shutdown all operations */
9007bccd
SN		 11321 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11322 rtnl_lock();
11323 i40e_prep_for_reset(pf);
11324 rtnl_unlock();
11325 }
41c445ff
JB		 11326
11327 /* Request a slot reset */
11328 return PCI_ERS_RESULT_NEED_RESET;
11329}
11330
11331/**
11332 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11333 * @pdev: PCI device information struct
11334 *
11335 * Called to find if the driver can work with the device now that
11336 * the pci slot has been reset. If a basic connection seems good
11337 * (registers are readable and have sane content) then return a
11338 * happy little PCI_ERS_RESULT_xxx.
11339 **/
11340static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11341{
11342 struct i40e_pf *pf = pci_get_drvdata(pdev);
11343 pci_ers_result_t result;
11344 int err;
11345 u32 reg;
11346
fb43201f 11347 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11348 if (pci_enable_device_mem(pdev)) {
11349 dev_info(&pdev->dev,
11350 "Cannot re-enable PCI device after reset.\n");
11351 result = PCI_ERS_RESULT_DISCONNECT;
11352 } else {
11353 pci_set_master(pdev);
11354 pci_restore_state(pdev);
11355 pci_save_state(pdev);
11356 pci_wake_from_d3(pdev, false);
11357
11358 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11359 if (reg == 0)
11360 result = PCI_ERS_RESULT_RECOVERED;
11361 else
11362 result = PCI_ERS_RESULT_DISCONNECT;
11363 }
11364
11365 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11366 if (err) {
11367 dev_info(&pdev->dev,
11368 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11369 err);
11370 /* non-fatal, continue */
11371 }
11372
11373 return result;
11374}
11375
11376/**
11377 * i40e_pci_error_resume - restart operations after PCI error recovery
11378 * @pdev: PCI device information struct
11379 *
11380 * Called to allow the driver to bring things back up after PCI error
11381 * and/or reset recovery has finished.
11382 **/
11383static void i40e_pci_error_resume(struct pci_dev *pdev)
11384{
11385 struct i40e_pf *pf = pci_get_drvdata(pdev);
11386
fb43201f 11387 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11388 if (test_bit(__I40E_SUSPENDED, &pf->state))
11389 return;
11390
11391 rtnl_lock();
41c445ff 11392 i40e_handle_reset_warning(pf);
4c4935a9 11393 rtnl_unlock();
9007bccd
SN		 11394}
11395
11396/**
11397 * i40e_shutdown - PCI callback for shutting down
11398 * @pdev: PCI device information struct
11399 **/
11400static void i40e_shutdown(struct pci_dev *pdev)
11401{
11402 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11403 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11404
11405 set_bit(__I40E_SUSPENDED, &pf->state);
11406 set_bit(__I40E_DOWN, &pf->state);
11407 rtnl_lock();
11408 i40e_prep_for_reset(pf);
11409 rtnl_unlock();
11410
8e2773ae
SN		 11411 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11412 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11413
02b42498
CS		 11414 del_timer_sync(&pf->service_timer);
11415 cancel_work_sync(&pf->service_task);
11416 i40e_fdir_teardown(pf);
11417
11418 rtnl_lock();
11419 i40e_prep_for_reset(pf);
11420 rtnl_unlock();
11421
11422 wr32(hw, I40E_PFPM_APM,
11423 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11424 wr32(hw, I40E_PFPM_WUFC,
11425 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11426
e147758d
SN		 11427 i40e_clear_interrupt_scheme(pf);
11428
9007bccd 11429 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11430 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11431 pci_set_power_state(pdev, PCI_D3hot);
11432 }
11433}
11434
11435#ifdef CONFIG_PM
11436/**
11437 * i40e_suspend - PCI callback for moving to D3
11438 * @pdev: PCI device information struct
11439 **/
11440static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11441{
11442 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11443 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11444
11445 set_bit(__I40E_SUSPENDED, &pf->state);
11446 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11447
9007bccd
SN		 11448 rtnl_lock();
11449 i40e_prep_for_reset(pf);
11450 rtnl_unlock();
11451
8e2773ae
SN		 11452 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11453 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11454
11455 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11456 pci_set_power_state(pdev, PCI_D3hot);
11457
11458 return 0;
41c445ff
JB		 11459}
11460
9007bccd
SN		 11461/**
11462 * i40e_resume - PCI callback for waking up from D3
11463 * @pdev: PCI device information struct
11464 **/
11465static int i40e_resume(struct pci_dev *pdev)
11466{
11467 struct i40e_pf *pf = pci_get_drvdata(pdev);
11468 u32 err;
11469
11470 pci_set_power_state(pdev, PCI_D0);
11471 pci_restore_state(pdev);
11472 /* pci_restore_state() clears dev->state_saves, so
11473 * call pci_save_state() again to restore it.
11474 */
11475 pci_save_state(pdev);
11476
11477 err = pci_enable_device_mem(pdev);
11478 if (err) {
fb43201f 11479 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11480 return err;
11481 }
11482 pci_set_master(pdev);
11483
11484 /* no wakeup events while running */
11485 pci_wake_from_d3(pdev, false);
11486
11487 /* handling the reset will rebuild the device state */
11488 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11489 clear_bit(__I40E_DOWN, &pf->state);
11490 rtnl_lock();
11491 i40e_reset_and_rebuild(pf, false);
11492 rtnl_unlock();
11493 }
11494
11495 return 0;
11496}
11497
11498#endif
41c445ff
JB		 11499static const struct pci_error_handlers i40e_err_handler = {
11500 .error_detected = i40e_pci_error_detected,
11501 .slot_reset = i40e_pci_error_slot_reset,
11502 .resume = i40e_pci_error_resume,
11503};
11504
11505static struct pci_driver i40e_driver = {
11506 .name = i40e_driver_name,
11507 .id_table = i40e_pci_tbl,
11508 .probe = i40e_probe,
11509 .remove = i40e_remove,
9007bccd
SN		 11510#ifdef CONFIG_PM
11511 .suspend = i40e_suspend,
11512 .resume = i40e_resume,
11513#endif
11514 .shutdown = i40e_shutdown,
41c445ff
JB		 11515 .err_handler = &i40e_err_handler,
11516 .sriov_configure = i40e_pci_sriov_configure,
11517};
11518
11519/**
11520 * i40e_init_module - Driver registration routine
11521 *
11522 * i40e_init_module is the first routine called when the driver is
11523 * loaded. All it does is register with the PCI subsystem.
11524 **/
11525static int __init i40e_init_module(void)
11526{
11527 pr_info("%s: %s - version %s\n", i40e_driver_name,
11528 i40e_driver_string, i40e_driver_version_str);
11529 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11530
2803b16c
JB		 11531 /* we will see if single thread per module is enough for now,
11532 * it can't be any worse than using the system workqueue which
11533 * was already single threaded
11534 */
11535 i40e_wq = create_singlethread_workqueue(i40e_driver_name);
11536 if (!i40e_wq) {
11537 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
11538 return -ENOMEM;
11539 }
11540
41c445ff
JB		 11541 i40e_dbg_init();
11542 return pci_register_driver(&i40e_driver);
11543}
11544module_init(i40e_init_module);
11545
11546/**
11547 * i40e_exit_module - Driver exit cleanup routine
11548 *
11549 * i40e_exit_module is called just before the driver is removed
11550 * from memory.
11551 **/
11552static void __exit i40e_exit_module(void)
11553{
11554 pci_unregister_driver(&i40e_driver);
2803b16c 11555 destroy_workqueue(i40e_wq);
41c445ff
JB		 11556 i40e_dbg_exit();
11557}
11558module_exit(i40e_exit_module);
Linux kernel - Deliverables
This page took 1.266935 seconds and 5 git commands to generate.