[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_txrx.h

/*******************************************************************************
 *
 * Intel Ethernet Controller XL710 Family Linux Driver
 * Copyright(c) 2013 - 2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
 *
 * Contact Information:
 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 ******************************************************************************/

#ifndef _I40E_TXRX_H_
#define _I40E_TXRX_H_

/* Interrupt Throttling and Rate Limiting (storm control) Goodies */

#define I40E_MAX_ITR               0x0FF0  /* reg uses 2 usec resolution */
#define I40E_MIN_ITR               0x0004  /* reg uses 2 usec resolution */
#define I40E_MAX_IRATE             0x03F
#define I40E_MIN_IRATE             0x001
#define I40E_IRATE_USEC_RESOLUTION 4
#define I40E_ITR_100K              0x0005
#define I40E_ITR_20K               0x0019
#define I40E_ITR_8K                0x003E
#define I40E_ITR_4K                0x007A
#define I40E_ITR_RX_DEF            I40E_ITR_8K
#define I40E_ITR_TX_DEF            I40E_ITR_4K
#define I40E_ITR_DYNAMIC           0x8000  /* use top bit as a flag */
#define I40E_MIN_INT_RATE          250     /* ~= 1000000 / (I40E_MAX_ITR * 2) */
#define I40E_MAX_INT_RATE          500000  /* == 1000000 / (I40E_MIN_ITR * 2) */
#define I40E_DEFAULT_IRQ_WORK      256
#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)

#define I40E_QUEUE_END_OF_LIST 0x7FF

/* this enum matches hardware bits and is meant to be used by DYN_CTLN
 * registers and QINT registers or more generally anywhere in the manual
 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
 * register but instead is a special value meaning "don't update" ITR0/1/2.
 */
enum i40e_dyn_idx_t {
	I40E_IDX_ITR0 = 0,
	I40E_IDX_ITR1 = 1,
	I40E_IDX_ITR2 = 2,
	I40E_ITR_NONE = 3	/* ITR_NONE must not be used as an index */
};

/* these are indexes into ITRN registers */
#define I40E_RX_ITR    I40E_IDX_ITR0
#define I40E_TX_ITR    I40E_IDX_ITR1
#define I40E_PE_ITR    I40E_IDX_ITR2

/* Supported RSS offloads */
#define I40E_DEFAULT_RSS_HENA ( \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
	((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
	((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
	((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD))

/* Supported Rx Buffer Sizes */
#define I40E_RXBUFFER_512   512    /* Used for packet split */
#define I40E_RXBUFFER_2048  2048
#define I40E_RXBUFFER_3072  3072   /* For FCoE MTU of 2158 */
#define I40E_RXBUFFER_4096  4096
#define I40E_RXBUFFER_8192  8192
#define I40E_MAX_RXBUFFER   9728  /* largest size for single descriptor */

/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
 * this adds up to 512 bytes of extra data meaning the smallest allocation
 * we could have is 1K.
 * i.e. RXBUFFER_512 --> size-1024 slab
 */
#define I40E_RX_HDR_SIZE  I40E_RXBUFFER_512

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define I40E_RX_BUFFER_WRITE	16	/* Must be power of 2 */
#define I40E_RX_NEXT_DESC(r, i, n)		\
	do {					\
		(i)++;				\
		if ((i) == (r)->count)		\
			i = 0;			\
		(n) = I40E_RX_DESC((r), (i));	\
	} while (0)

#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n)		\
	do {						\
		I40E_RX_NEXT_DESC((r), (i), (n));	\
		prefetch((n));				\
	} while (0)

#define i40e_rx_desc i40e_32byte_rx_desc

#define I40E_MIN_TX_LEN		17
#define I40E_MAX_DATA_PER_TXD	16383	/* aka 16kB - 1 */

/* Tx Descriptors needed, worst case */
#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)

#define I40E_TX_FLAGS_CSUM		(u32)(1)
#define I40E_TX_FLAGS_HW_VLAN		(u32)(1 << 1)
#define I40E_TX_FLAGS_SW_VLAN		(u32)(1 << 2)
#define I40E_TX_FLAGS_TSO		(u32)(1 << 3)
#define I40E_TX_FLAGS_IPV4		(u32)(1 << 4)
#define I40E_TX_FLAGS_IPV6		(u32)(1 << 5)
#define I40E_TX_FLAGS_FCCRC		(u32)(1 << 6)
#define I40E_TX_FLAGS_FSO		(u32)(1 << 7)
#define I40E_TX_FLAGS_VLAN_MASK		0xffff0000
#define I40E_TX_FLAGS_VLAN_PRIO_MASK	0xe0000000
#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT	29
#define I40E_TX_FLAGS_VLAN_SHIFT	16

struct i40e_tx_buffer {
	struct i40e_tx_desc *next_to_watch;
	unsigned long time_stamp;
	struct sk_buff *skb;
	unsigned int bytecount;
	unsigned short gso_segs;
	DEFINE_DMA_UNMAP_ADDR(dma);
	DEFINE_DMA_UNMAP_LEN(len);
	u32 tx_flags;
};

struct i40e_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	unsigned int page_offset;
};

struct i40e_queue_stats {
	u64 packets;
	u64 bytes;
};

struct i40e_tx_queue_stats {
	u64 restart_queue;
	u64 tx_busy;
	u64 tx_done_old;
};

struct i40e_rx_queue_stats {
	u64 non_eop_descs;
	u64 alloc_page_failed;
	u64 alloc_buff_failed;
};

enum i40e_ring_state_t {
	__I40E_TX_FDIR_INIT_DONE,
	__I40E_TX_XPS_INIT_DONE,
	__I40E_TX_DETECT_HANG,
	__I40E_HANG_CHECK_ARMED,
	__I40E_RX_PS_ENABLED,
	__I40E_RX_LRO_ENABLED,
	__I40E_RX_16BYTE_DESC_ENABLED,
};

#define ring_is_ps_enabled(ring) \
	test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
#define set_ring_ps_enabled(ring) \
	set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
#define clear_ring_ps_enabled(ring) \
	clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
#define check_for_tx_hang(ring) \
	test_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
#define set_check_for_tx_hang(ring) \
	set_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
#define clear_check_for_tx_hang(ring) \
	clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
#define ring_is_lro_enabled(ring) \
	test_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
#define set_ring_lro_enabled(ring) \
	set_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
#define clear_ring_lro_enabled(ring) \
	clear_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
#define ring_is_16byte_desc_enabled(ring) \
	test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
#define set_ring_16byte_desc_enabled(ring) \
	set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
#define clear_ring_16byte_desc_enabled(ring) \
	clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)

/* struct that defines a descriptor ring, associated with a VSI */
struct i40e_ring {
	struct i40e_ring *next;		/* pointer to next ring in q_vector */
	void *desc;			/* Descriptor ring memory */
	struct device *dev;		/* Used for DMA mapping */
	struct net_device *netdev;	/* netdev ring maps to */
	union {
		struct i40e_tx_buffer *tx_bi;
		struct i40e_rx_buffer *rx_bi;
	};
	unsigned long state;
	u16 queue_index;		/* Queue number of ring */
	u8 dcb_tc;			/* Traffic class of ring */
	u8 __iomem *tail;

	u16 count;			/* Number of descriptors */
	u16 reg_idx;			/* HW register index of the ring */
	u16 rx_hdr_len;
	u16 rx_buf_len;
	u8  dtype;
#define I40E_RX_DTYPE_NO_SPLIT      0
#define I40E_RX_DTYPE_SPLIT_ALWAYS  1
#define I40E_RX_DTYPE_HEADER_SPLIT  2
	u8  hsplit;
#define I40E_RX_SPLIT_L2      0x1
#define I40E_RX_SPLIT_IP      0x2
#define I40E_RX_SPLIT_TCP_UDP 0x4
#define I40E_RX_SPLIT_SCTP    0x8

	/* used in interrupt processing */
	u16 next_to_use;
	u16 next_to_clean;

	u8 atr_sample_rate;
	u8 atr_count;

	bool ring_active;		/* is ring online or not */

	/* stats structs */
	struct i40e_queue_stats	stats;
	struct u64_stats_sync syncp;
	union {
		struct i40e_tx_queue_stats tx_stats;
		struct i40e_rx_queue_stats rx_stats;
	};

	unsigned int size;		/* length of descriptor ring in bytes */
	dma_addr_t dma;			/* physical address of ring */

	struct i40e_vsi *vsi;		/* Backreference to associated VSI */
	struct i40e_q_vector *q_vector;	/* Backreference to associated vector */

	struct rcu_head rcu;		/* to avoid race on free */
} ____cacheline_internodealigned_in_smp;

enum i40e_latency_range {
	I40E_LOWEST_LATENCY = 0,
	I40E_LOW_LATENCY = 1,
	I40E_BULK_LATENCY = 2,
};

struct i40e_ring_container {
	/* array of pointers to rings */
	struct i40e_ring *ring;
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u16 count;
	enum i40e_latency_range latency_range;
	u16 itr;
};

/* iterator for handling rings in ring container */
#define i40e_for_each_ring(pos, head) \
	for (pos = (head).ring; pos != NULL; pos = pos->next)

void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring);
void i40e_free_tx_resources(struct i40e_ring *tx_ring);
void i40e_free_rx_resources(struct i40e_ring *rx_ring);
int i40e_napi_poll(struct napi_struct *napi, int budget);
#endif /* _I40E_TXRX_H_ */
Commit	Line	Data
7daa6bf3 JB	1	/*******************************************************************************
	2	*
	3	* Intel Ethernet Controller XL710 Family Linux Driver
dc641b73	4	* Copyright(c) 2013 - 2014 Intel Corporation.
7daa6bf3 JB	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
dc641b73 GR	15	* You should have received a copy of the GNU General Public License along
dc641b73 GR	16	* with this program. If not, see <http://www.gnu.org/licenses/>.
7daa6bf3 JB	17	*
	18	* The full GNU General Public License is included in this distribution in
	19	* the file called "COPYING".
	20	*
	21	* Contact Information:
	22	* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	23	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	24	*
	25	******************************************************************************/
	26
36fac581 VD	27	#ifndef _I40E_TXRX_H_
	28	#define _I40E_TXRX_H_
	29
7daa6bf3 JB	30	/* Interrupt Throttling and Rate Limiting (storm control) Goodies */
7daa6bf3 JB	31
3126dcb7 SN	32	#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */
3126dcb7 SN	33	#define I40E_MIN_ITR 0x0004 /* reg uses 2 usec resolution */
7daa6bf3 JB	34	#define I40E_MAX_IRATE 0x03F
	35	#define I40E_MIN_IRATE 0x001
	36	#define I40E_IRATE_USEC_RESOLUTION 4
	37	#define I40E_ITR_100K 0x0005
	38	#define I40E_ITR_20K 0x0019
	39	#define I40E_ITR_8K 0x003E
	40	#define I40E_ITR_4K 0x007A
	41	#define I40E_ITR_RX_DEF I40E_ITR_8K
	42	#define I40E_ITR_TX_DEF I40E_ITR_4K
	43	#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
	44	#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */
	45	#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */
	46	#define I40E_DEFAULT_IRQ_WORK 256
	47	#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
	48	#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
	49	#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)
	50
	51	#define I40E_QUEUE_END_OF_LIST 0x7FF
	52
0319577f JB	53	/* this enum matches hardware bits and is meant to be used by DYN_CTLN
	54	* registers and QINT registers or more generally anywhere in the manual
	55	* mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
	56	* register but instead is a special value meaning "don't update" ITR0/1/2.
	57	*/
	58	enum i40e_dyn_idx_t {
	59	I40E_IDX_ITR0 = 0,
	60	I40E_IDX_ITR1 = 1,
	61	I40E_IDX_ITR2 = 2,
	62	I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
	63	};
	64
	65	/* these are indexes into ITRN registers */
	66	#define I40E_RX_ITR I40E_IDX_ITR0
	67	#define I40E_TX_ITR I40E_IDX_ITR1
	68	#define I40E_PE_ITR I40E_IDX_ITR2
	69
12dc4fe3 MW	70	/* Supported RSS offloads */
	71	#define I40E_DEFAULT_RSS_HENA ( \
	72	((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) \| \
	73	((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) \| \
	74	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) \| \
	75	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) \| \
	76	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN) \| \
	77	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) \| \
	78	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) \| \
	79	((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) \| \
	80	((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) \| \
	81	((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) \| \
	82	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) \| \
	83	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN) \| \
	84	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) \| \
	85	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) \| \
	86	((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) \| \
	87	((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) \| \
	88	((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD))
	89
7daa6bf3 JB	90	/* Supported Rx Buffer Sizes */
	91	#define I40E_RXBUFFER_512 512 /* Used for packet split */
	92	#define I40E_RXBUFFER_2048 2048
	93	#define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */
	94	#define I40E_RXBUFFER_4096 4096
	95	#define I40E_RXBUFFER_8192 8192
	96	#define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */
	97
	98	/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
	99	* reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
	100	* this adds up to 512 bytes of extra data meaning the smallest allocation
	101	* we could have is 1K.
	102	* i.e. RXBUFFER_512 --> size-1024 slab
	103	*/
	104	#define I40E_RX_HDR_SIZE I40E_RXBUFFER_512
	105
	106	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	107	#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	108	#define I40E_RX_NEXT_DESC(r, i, n) \
	109	do { \
	110	(i)++; \
	111	if ((i) == (r)->count) \
	112	i = 0; \
	113	(n) = I40E_RX_DESC((r), (i)); \
	114	} while (0)
	115
	116	#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \
	117	do { \
	118	I40E_RX_NEXT_DESC((r), (i), (n)); \
	119	prefetch((n)); \
	120	} while (0)
	121
	122	#define i40e_rx_desc i40e_32byte_rx_desc
	123
	124	#define I40E_MIN_TX_LEN 17
	125	#define I40E_MAX_DATA_PER_TXD 16383 /* aka 16kB - 1 */
	126
	127	/* Tx Descriptors needed, worst case */
	128	#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
	129	#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
	130
	131	#define I40E_TX_FLAGS_CSUM (u32)(1)
	132	#define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1)
	133	#define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2)
	134	#define I40E_TX_FLAGS_TSO (u32)(1 << 3)
	135	#define I40E_TX_FLAGS_IPV4 (u32)(1 << 4)
	136	#define I40E_TX_FLAGS_IPV6 (u32)(1 << 5)
	137	#define I40E_TX_FLAGS_FCCRC (u32)(1 << 6)
	138	#define I40E_TX_FLAGS_FSO (u32)(1 << 7)
7daa6bf3 JB	139	#define I40E_TX_FLAGS_VLAN_MASK 0xffff0000
	140	#define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
	141	#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29
	142	#define I40E_TX_FLAGS_VLAN_SHIFT 16
	143
	144	struct i40e_tx_buffer {
7daa6bf3	145	struct i40e_tx_desc *next_to_watch;
35a1e2ad AD	146	unsigned long time_stamp;
35a1e2ad AD	147	struct sk_buff *skb;
7daa6bf3	148	unsigned int bytecount;
35a1e2ad AD	149	unsigned short gso_segs;
	150	DEFINE_DMA_UNMAP_ADDR(dma);
	151	DEFINE_DMA_UNMAP_LEN(len);
	152	u32 tx_flags;
7daa6bf3 JB	153	};
	154
	155	struct i40e_rx_buffer {
	156	struct sk_buff *skb;
	157	dma_addr_t dma;
	158	struct page *page;
	159	dma_addr_t page_dma;
	160	unsigned int page_offset;
	161	};
	162
a114d0a6	163	struct i40e_queue_stats {
7daa6bf3 JB	164	u64 packets;
7daa6bf3 JB	165	u64 bytes;
a114d0a6 AD	166	};
	167
	168	struct i40e_tx_queue_stats {
7daa6bf3 JB	169	u64 restart_queue;
7daa6bf3 JB	170	u64 tx_busy;
7daa6bf3 JB	171	u64 tx_done_old;
	172	};
	173
	174	struct i40e_rx_queue_stats {
7daa6bf3	175	u64 non_eop_descs;
420136cc MW	176	u64 alloc_page_failed;
420136cc MW	177	u64 alloc_buff_failed;
7daa6bf3 JB	178	};
	179
	180	enum i40e_ring_state_t {
	181	__I40E_TX_FDIR_INIT_DONE,
	182	__I40E_TX_XPS_INIT_DONE,
	183	__I40E_TX_DETECT_HANG,
	184	__I40E_HANG_CHECK_ARMED,
	185	__I40E_RX_PS_ENABLED,
	186	__I40E_RX_LRO_ENABLED,
	187	__I40E_RX_16BYTE_DESC_ENABLED,
	188	};
	189
	190	#define ring_is_ps_enabled(ring) \
	191	test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
	192	#define set_ring_ps_enabled(ring) \
	193	set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
	194	#define clear_ring_ps_enabled(ring) \
	195	clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
	196	#define check_for_tx_hang(ring) \
	197	test_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
	198	#define set_check_for_tx_hang(ring) \
	199	set_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
	200	#define clear_check_for_tx_hang(ring) \
	201	clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
	202	#define ring_is_lro_enabled(ring) \
	203	test_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
	204	#define set_ring_lro_enabled(ring) \
	205	set_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
	206	#define clear_ring_lro_enabled(ring) \
	207	clear_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
	208	#define ring_is_16byte_desc_enabled(ring) \
	209	test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
	210	#define set_ring_16byte_desc_enabled(ring) \
	211	set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
	212	#define clear_ring_16byte_desc_enabled(ring) \
	213	clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
	214
	215	/* struct that defines a descriptor ring, associated with a VSI */
	216	struct i40e_ring {
cd0b6fa6	217	struct i40e_ring next; / pointer to next ring in q_vector */
7daa6bf3 JB	218	void desc; / Descriptor ring memory */
	219	struct device dev; / Used for DMA mapping */
	220	struct net_device netdev; / netdev ring maps to */
	221	union {
	222	struct i40e_tx_buffer *tx_bi;
	223	struct i40e_rx_buffer *rx_bi;
	224	};
	225	unsigned long state;
	226	u16 queue_index; /* Queue number of ring */
	227	u8 dcb_tc; /* Traffic class of ring */
	228	u8 __iomem *tail;
	229
	230	u16 count; /* Number of descriptors */
	231	u16 reg_idx; /* HW register index of the ring */
	232	u16 rx_hdr_len;
	233	u16 rx_buf_len;
	234	u8 dtype;
	235	#define I40E_RX_DTYPE_NO_SPLIT 0
	236	#define I40E_RX_DTYPE_SPLIT_ALWAYS 1
	237	#define I40E_RX_DTYPE_HEADER_SPLIT 2
	238	u8 hsplit;
	239	#define I40E_RX_SPLIT_L2 0x1
	240	#define I40E_RX_SPLIT_IP 0x2
	241	#define I40E_RX_SPLIT_TCP_UDP 0x4
	242	#define I40E_RX_SPLIT_SCTP 0x8
	243
	244	/* used in interrupt processing */
	245	u16 next_to_use;
	246	u16 next_to_clean;
	247
	248	u8 atr_sample_rate;
	249	u8 atr_count;
	250
	251	bool ring_active; /* is ring online or not */
	252
	253	/* stats structs */
a114d0a6	254	struct i40e_queue_stats stats;
980e9b11	255	struct u64_stats_sync syncp;
7daa6bf3 JB	256	union {
	257	struct i40e_tx_queue_stats tx_stats;
	258	struct i40e_rx_queue_stats rx_stats;
	259	};
	260
	261	unsigned int size; /* length of descriptor ring in bytes */
	262	dma_addr_t dma; /* physical address of ring */
	263
	264	struct i40e_vsi vsi; / Backreference to associated VSI */
	265	struct i40e_q_vector q_vector; / Backreference to associated vector */
9f65e15b AD	266
9f65e15b AD	267	struct rcu_head rcu; /* to avoid race on free */
7daa6bf3 JB	268	} ____cacheline_internodealigned_in_smp;
	269
	270	enum i40e_latency_range {
	271	I40E_LOWEST_LATENCY = 0,
	272	I40E_LOW_LATENCY = 1,
	273	I40E_BULK_LATENCY = 2,
	274	};
	275
	276	struct i40e_ring_container {
7daa6bf3	277	/* array of pointers to rings */
cd0b6fa6	278	struct i40e_ring *ring;
7daa6bf3 JB	279	unsigned int total_bytes; /* total bytes processed this int */
	280	unsigned int total_packets; /* total packets processed this int */
	281	u16 count;
	282	enum i40e_latency_range latency_range;
	283	u16 itr;
	284	};
	285
cd0b6fa6 AD	286	/* iterator for handling rings in ring container */
	287	#define i40e_for_each_ring(pos, head) \
	288	for (pos = (head).ring; pos != NULL; pos = pos->next)
	289
7daa6bf3 JB	290	void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
	291	netdev_tx_t i40e_lan_xmit_frame(struct sk_buff skb, struct net_device netdev);
	292	void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
	293	void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
	294	int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
	295	int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring);
	296	void i40e_free_tx_resources(struct i40e_ring *tx_ring);
	297	void i40e_free_rx_resources(struct i40e_ring *rx_ring);
	298	int i40e_napi_poll(struct napi_struct *napi, int budget);
36fac581	299	#endif /* _I40E_TXRX_H_ */