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7daa6bf3 JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
dc641b73 | 4 | * Copyright(c) 2013 - 2014 Intel Corporation. |
7daa6bf3 JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
7daa6bf3 JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
36fac581 VD |
27 | #ifndef _I40E_TXRX_H_ |
28 | #define _I40E_TXRX_H_ | |
29 | ||
aee8087f | 30 | /* Interrupt Throttling and Rate Limiting Goodies */ |
7daa6bf3 | 31 | |
3126dcb7 SN |
32 | #define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ |
33 | #define I40E_MIN_ITR 0x0004 /* reg uses 2 usec resolution */ | |
7daa6bf3 JB |
34 | #define I40E_MAX_IRATE 0x03F |
35 | #define I40E_MIN_IRATE 0x001 | |
36 | #define I40E_IRATE_USEC_RESOLUTION 4 | |
37 | #define I40E_ITR_100K 0x0005 | |
38 | #define I40E_ITR_20K 0x0019 | |
39 | #define I40E_ITR_8K 0x003E | |
40 | #define I40E_ITR_4K 0x007A | |
41 | #define I40E_ITR_RX_DEF I40E_ITR_8K | |
42 | #define I40E_ITR_TX_DEF I40E_ITR_4K | |
43 | #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ | |
44 | #define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ | |
45 | #define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ | |
46 | #define I40E_DEFAULT_IRQ_WORK 256 | |
47 | #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) | |
48 | #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) | |
49 | #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) | |
50 | ||
51 | #define I40E_QUEUE_END_OF_LIST 0x7FF | |
52 | ||
0319577f JB |
53 | /* this enum matches hardware bits and is meant to be used by DYN_CTLN |
54 | * registers and QINT registers or more generally anywhere in the manual | |
55 | * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any | |
56 | * register but instead is a special value meaning "don't update" ITR0/1/2. | |
57 | */ | |
58 | enum i40e_dyn_idx_t { | |
59 | I40E_IDX_ITR0 = 0, | |
60 | I40E_IDX_ITR1 = 1, | |
61 | I40E_IDX_ITR2 = 2, | |
62 | I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ | |
63 | }; | |
64 | ||
65 | /* these are indexes into ITRN registers */ | |
66 | #define I40E_RX_ITR I40E_IDX_ITR0 | |
67 | #define I40E_TX_ITR I40E_IDX_ITR1 | |
68 | #define I40E_PE_ITR I40E_IDX_ITR2 | |
69 | ||
12dc4fe3 MW |
70 | /* Supported RSS offloads */ |
71 | #define I40E_DEFAULT_RSS_HENA ( \ | |
12dc4fe3 MW |
72 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ |
73 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ | |
12dc4fe3 MW |
74 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ |
75 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ | |
76 | ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ | |
12dc4fe3 | 77 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ |
12dc4fe3 MW |
78 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ |
79 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ | |
80 | ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ | |
81 | ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ | |
82 | ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD)) | |
83 | ||
7daa6bf3 JB |
84 | /* Supported Rx Buffer Sizes */ |
85 | #define I40E_RXBUFFER_512 512 /* Used for packet split */ | |
86 | #define I40E_RXBUFFER_2048 2048 | |
87 | #define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */ | |
88 | #define I40E_RXBUFFER_4096 4096 | |
89 | #define I40E_RXBUFFER_8192 8192 | |
90 | #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ | |
91 | ||
92 | /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we | |
93 | * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, | |
94 | * this adds up to 512 bytes of extra data meaning the smallest allocation | |
95 | * we could have is 1K. | |
96 | * i.e. RXBUFFER_512 --> size-1024 slab | |
97 | */ | |
98 | #define I40E_RX_HDR_SIZE I40E_RXBUFFER_512 | |
99 | ||
100 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | |
101 | #define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
102 | #define I40E_RX_NEXT_DESC(r, i, n) \ | |
103 | do { \ | |
104 | (i)++; \ | |
105 | if ((i) == (r)->count) \ | |
106 | i = 0; \ | |
107 | (n) = I40E_RX_DESC((r), (i)); \ | |
108 | } while (0) | |
109 | ||
110 | #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ | |
111 | do { \ | |
112 | I40E_RX_NEXT_DESC((r), (i), (n)); \ | |
113 | prefetch((n)); \ | |
114 | } while (0) | |
115 | ||
116 | #define i40e_rx_desc i40e_32byte_rx_desc | |
117 | ||
118 | #define I40E_MIN_TX_LEN 17 | |
980093eb | 119 | #define I40E_MAX_DATA_PER_TXD 8192 |
7daa6bf3 JB |
120 | |
121 | /* Tx Descriptors needed, worst case */ | |
122 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD) | |
980093eb | 123 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
7daa6bf3 JB |
124 | |
125 | #define I40E_TX_FLAGS_CSUM (u32)(1) | |
126 | #define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1) | |
127 | #define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2) | |
128 | #define I40E_TX_FLAGS_TSO (u32)(1 << 3) | |
129 | #define I40E_TX_FLAGS_IPV4 (u32)(1 << 4) | |
130 | #define I40E_TX_FLAGS_IPV6 (u32)(1 << 5) | |
131 | #define I40E_TX_FLAGS_FCCRC (u32)(1 << 6) | |
132 | #define I40E_TX_FLAGS_FSO (u32)(1 << 7) | |
beb0dff1 | 133 | #define I40E_TX_FLAGS_TSYN (u32)(1 << 8) |
49d7d933 | 134 | #define I40E_TX_FLAGS_FD_SB (u32)(1 << 9) |
7daa6bf3 JB |
135 | #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 |
136 | #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 | |
137 | #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
138 | #define I40E_TX_FLAGS_VLAN_SHIFT 16 | |
139 | ||
140 | struct i40e_tx_buffer { | |
7daa6bf3 | 141 | struct i40e_tx_desc *next_to_watch; |
35a1e2ad | 142 | unsigned long time_stamp; |
49d7d933 ASJ |
143 | union { |
144 | struct sk_buff *skb; | |
145 | void *raw_buf; | |
146 | }; | |
7daa6bf3 | 147 | unsigned int bytecount; |
35a1e2ad AD |
148 | unsigned short gso_segs; |
149 | DEFINE_DMA_UNMAP_ADDR(dma); | |
150 | DEFINE_DMA_UNMAP_LEN(len); | |
151 | u32 tx_flags; | |
7daa6bf3 JB |
152 | }; |
153 | ||
154 | struct i40e_rx_buffer { | |
155 | struct sk_buff *skb; | |
156 | dma_addr_t dma; | |
157 | struct page *page; | |
158 | dma_addr_t page_dma; | |
159 | unsigned int page_offset; | |
160 | }; | |
161 | ||
a114d0a6 | 162 | struct i40e_queue_stats { |
7daa6bf3 JB |
163 | u64 packets; |
164 | u64 bytes; | |
a114d0a6 AD |
165 | }; |
166 | ||
167 | struct i40e_tx_queue_stats { | |
7daa6bf3 JB |
168 | u64 restart_queue; |
169 | u64 tx_busy; | |
7daa6bf3 JB |
170 | u64 tx_done_old; |
171 | }; | |
172 | ||
173 | struct i40e_rx_queue_stats { | |
7daa6bf3 | 174 | u64 non_eop_descs; |
420136cc MW |
175 | u64 alloc_page_failed; |
176 | u64 alloc_buff_failed; | |
7daa6bf3 JB |
177 | }; |
178 | ||
179 | enum i40e_ring_state_t { | |
180 | __I40E_TX_FDIR_INIT_DONE, | |
181 | __I40E_TX_XPS_INIT_DONE, | |
182 | __I40E_TX_DETECT_HANG, | |
183 | __I40E_HANG_CHECK_ARMED, | |
184 | __I40E_RX_PS_ENABLED, | |
7daa6bf3 JB |
185 | __I40E_RX_16BYTE_DESC_ENABLED, |
186 | }; | |
187 | ||
188 | #define ring_is_ps_enabled(ring) \ | |
189 | test_bit(__I40E_RX_PS_ENABLED, &(ring)->state) | |
190 | #define set_ring_ps_enabled(ring) \ | |
191 | set_bit(__I40E_RX_PS_ENABLED, &(ring)->state) | |
192 | #define clear_ring_ps_enabled(ring) \ | |
193 | clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state) | |
194 | #define check_for_tx_hang(ring) \ | |
195 | test_bit(__I40E_TX_DETECT_HANG, &(ring)->state) | |
196 | #define set_check_for_tx_hang(ring) \ | |
197 | set_bit(__I40E_TX_DETECT_HANG, &(ring)->state) | |
198 | #define clear_check_for_tx_hang(ring) \ | |
199 | clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state) | |
7daa6bf3 JB |
200 | #define ring_is_16byte_desc_enabled(ring) \ |
201 | test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) | |
202 | #define set_ring_16byte_desc_enabled(ring) \ | |
203 | set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) | |
204 | #define clear_ring_16byte_desc_enabled(ring) \ | |
205 | clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) | |
206 | ||
207 | /* struct that defines a descriptor ring, associated with a VSI */ | |
208 | struct i40e_ring { | |
cd0b6fa6 | 209 | struct i40e_ring *next; /* pointer to next ring in q_vector */ |
7daa6bf3 JB |
210 | void *desc; /* Descriptor ring memory */ |
211 | struct device *dev; /* Used for DMA mapping */ | |
212 | struct net_device *netdev; /* netdev ring maps to */ | |
213 | union { | |
214 | struct i40e_tx_buffer *tx_bi; | |
215 | struct i40e_rx_buffer *rx_bi; | |
216 | }; | |
217 | unsigned long state; | |
218 | u16 queue_index; /* Queue number of ring */ | |
219 | u8 dcb_tc; /* Traffic class of ring */ | |
220 | u8 __iomem *tail; | |
221 | ||
222 | u16 count; /* Number of descriptors */ | |
223 | u16 reg_idx; /* HW register index of the ring */ | |
224 | u16 rx_hdr_len; | |
225 | u16 rx_buf_len; | |
226 | u8 dtype; | |
227 | #define I40E_RX_DTYPE_NO_SPLIT 0 | |
228 | #define I40E_RX_DTYPE_SPLIT_ALWAYS 1 | |
229 | #define I40E_RX_DTYPE_HEADER_SPLIT 2 | |
230 | u8 hsplit; | |
231 | #define I40E_RX_SPLIT_L2 0x1 | |
232 | #define I40E_RX_SPLIT_IP 0x2 | |
233 | #define I40E_RX_SPLIT_TCP_UDP 0x4 | |
234 | #define I40E_RX_SPLIT_SCTP 0x8 | |
235 | ||
236 | /* used in interrupt processing */ | |
237 | u16 next_to_use; | |
238 | u16 next_to_clean; | |
239 | ||
240 | u8 atr_sample_rate; | |
241 | u8 atr_count; | |
242 | ||
beb0dff1 JK |
243 | unsigned long last_rx_timestamp; |
244 | ||
7daa6bf3 JB |
245 | bool ring_active; /* is ring online or not */ |
246 | ||
247 | /* stats structs */ | |
a114d0a6 | 248 | struct i40e_queue_stats stats; |
980e9b11 | 249 | struct u64_stats_sync syncp; |
7daa6bf3 JB |
250 | union { |
251 | struct i40e_tx_queue_stats tx_stats; | |
252 | struct i40e_rx_queue_stats rx_stats; | |
253 | }; | |
254 | ||
255 | unsigned int size; /* length of descriptor ring in bytes */ | |
256 | dma_addr_t dma; /* physical address of ring */ | |
257 | ||
258 | struct i40e_vsi *vsi; /* Backreference to associated VSI */ | |
259 | struct i40e_q_vector *q_vector; /* Backreference to associated vector */ | |
9f65e15b AD |
260 | |
261 | struct rcu_head rcu; /* to avoid race on free */ | |
7daa6bf3 JB |
262 | } ____cacheline_internodealigned_in_smp; |
263 | ||
264 | enum i40e_latency_range { | |
265 | I40E_LOWEST_LATENCY = 0, | |
266 | I40E_LOW_LATENCY = 1, | |
267 | I40E_BULK_LATENCY = 2, | |
268 | }; | |
269 | ||
270 | struct i40e_ring_container { | |
7daa6bf3 | 271 | /* array of pointers to rings */ |
cd0b6fa6 | 272 | struct i40e_ring *ring; |
7daa6bf3 JB |
273 | unsigned int total_bytes; /* total bytes processed this int */ |
274 | unsigned int total_packets; /* total packets processed this int */ | |
275 | u16 count; | |
276 | enum i40e_latency_range latency_range; | |
277 | u16 itr; | |
278 | }; | |
279 | ||
cd0b6fa6 AD |
280 | /* iterator for handling rings in ring container */ |
281 | #define i40e_for_each_ring(pos, head) \ | |
282 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
283 | ||
7daa6bf3 JB |
284 | void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); |
285 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); | |
286 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring); | |
287 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring); | |
288 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); | |
289 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); | |
290 | void i40e_free_tx_resources(struct i40e_ring *tx_ring); | |
291 | void i40e_free_rx_resources(struct i40e_ring *rx_ring); | |
292 | int i40e_napi_poll(struct napi_struct *napi, int budget); | |
36fac581 | 293 | #endif /* _I40E_TXRX_H_ */ |