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i40e: When in promisc mode apply promisc mode to Tx Traffic as well
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_adminq_cmd.h
CommitLineData
d358aa9a
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
3b120089 4 * Copyright(c) 2013 - 2016 Intel Corporation.
d358aa9a
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
d358aa9a
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_ADMINQ_CMD_H_
28#define _I40E_ADMINQ_CMD_H_
29
30/* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
8c570dcc 36#define I40E_FW_API_VERSION_MAJOR 0x0001
97b884fe 37#define I40E_FW_API_VERSION_MINOR 0x0005
d358aa9a
GR		 38
39struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61};
62
63/* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68/* command flags and offsets*/
8c570dcc
JK		 69#define I40E_AQ_FLAG_DD_SHIFT 0
70#define I40E_AQ_FLAG_CMP_SHIFT 1
71#define I40E_AQ_FLAG_ERR_SHIFT 2
72#define I40E_AQ_FLAG_VFE_SHIFT 3
73#define I40E_AQ_FLAG_LB_SHIFT 9
74#define I40E_AQ_FLAG_RD_SHIFT 10
75#define I40E_AQ_FLAG_VFC_SHIFT 11
76#define I40E_AQ_FLAG_BUF_SHIFT 12
77#define I40E_AQ_FLAG_SI_SHIFT 13
78#define I40E_AQ_FLAG_EI_SHIFT 14
79#define I40E_AQ_FLAG_FE_SHIFT 15
80
81#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
d358aa9a
GR		 92
93/* error codes */
94enum i40e_admin_queue_err {
8c570dcc
JK		 95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
d358aa9a
GR		 118};
119
120/* Admin Queue command opcodes */
121enum i40e_admin_queue_opc {
122 /* aq commands */
8c570dcc
JK		 123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
d358aa9a
GR		 127
128 /* resource ownership */
8c570dcc
JK		 129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
d358aa9a 131
8c570dcc
JK		 132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
d358aa9a 134
d358aa9a 135 /* LAA */
8c570dcc
JK		 136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
d358aa9a
GR		 138
139 /* PXE */
8c570dcc 140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
d358aa9a
GR		 141
142 /* internal switch commands */
8c570dcc
JK		 143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
fa5623a6 148 i40e_aqc_opc_set_switch_config = 0x0205,
8c570dcc
JK		 149
150 i40e_aqc_opc_add_vsi = 0x0210,
151 i40e_aqc_opc_update_vsi_parameters = 0x0211,
152 i40e_aqc_opc_get_vsi_parameters = 0x0212,
153
154 i40e_aqc_opc_add_pv = 0x0220,
155 i40e_aqc_opc_update_pv_parameters = 0x0221,
156 i40e_aqc_opc_get_pv_parameters = 0x0222,
157
158 i40e_aqc_opc_add_veb = 0x0230,
159 i40e_aqc_opc_update_veb_parameters = 0x0231,
160 i40e_aqc_opc_get_veb_parameters = 0x0232,
161
162 i40e_aqc_opc_delete_element = 0x0243,
163
164 i40e_aqc_opc_add_macvlan = 0x0250,
165 i40e_aqc_opc_remove_macvlan = 0x0251,
166 i40e_aqc_opc_add_vlan = 0x0252,
167 i40e_aqc_opc_remove_vlan = 0x0253,
168 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
169 i40e_aqc_opc_add_tag = 0x0255,
170 i40e_aqc_opc_remove_tag = 0x0256,
171 i40e_aqc_opc_add_multicast_etag = 0x0257,
172 i40e_aqc_opc_remove_multicast_etag = 0x0258,
173 i40e_aqc_opc_update_tag = 0x0259,
174 i40e_aqc_opc_add_control_packet_filter = 0x025A,
175 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
176 i40e_aqc_opc_add_cloud_filters = 0x025C,
177 i40e_aqc_opc_remove_cloud_filters = 0x025D,
178
179 i40e_aqc_opc_add_mirror_rule = 0x0260,
180 i40e_aqc_opc_delete_mirror_rule = 0x0261,
d358aa9a 181
d358aa9a 182 /* DCB commands */
8c570dcc
JK		 183 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
184 i40e_aqc_opc_dcb_updated = 0x0302,
d358aa9a
GR		 185
186 /* TX scheduler */
8c570dcc
JK		 187 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
188 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
189 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
190 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
191 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
192 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
193
194 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
195 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
196 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
197 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
198 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
199 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
200 i40e_aqc_opc_query_port_ets_config = 0x0419,
201 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
202 i40e_aqc_opc_suspend_port_tx = 0x041B,
203 i40e_aqc_opc_resume_port_tx = 0x041C,
204 i40e_aqc_opc_configure_partition_bw = 0x041D,
d358aa9a
GR		 205
206 /* hmc */
8c570dcc
JK		 207 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
208 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
d358aa9a
GR		 209
210 /* phy commands*/
8c570dcc
JK		 211 i40e_aqc_opc_get_phy_abilities = 0x0600,
212 i40e_aqc_opc_set_phy_config = 0x0601,
213 i40e_aqc_opc_set_mac_config = 0x0603,
214 i40e_aqc_opc_set_link_restart_an = 0x0605,
215 i40e_aqc_opc_get_link_status = 0x0607,
216 i40e_aqc_opc_set_phy_int_mask = 0x0613,
217 i40e_aqc_opc_get_local_advt_reg = 0x0614,
218 i40e_aqc_opc_set_local_advt_reg = 0x0615,
219 i40e_aqc_opc_get_partner_advt = 0x0616,
220 i40e_aqc_opc_set_lb_modes = 0x0618,
221 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
222 i40e_aqc_opc_set_phy_debug = 0x0622,
223 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
5394f02f 224 i40e_aqc_opc_run_phy_activity = 0x0626,
d358aa9a
GR		 225
226 /* NVM commands */
8c570dcc
JK		 227 i40e_aqc_opc_nvm_read = 0x0701,
228 i40e_aqc_opc_nvm_erase = 0x0702,
229 i40e_aqc_opc_nvm_update = 0x0703,
230 i40e_aqc_opc_nvm_config_read = 0x0704,
231 i40e_aqc_opc_nvm_config_write = 0x0705,
00ada50d 232 i40e_aqc_opc_oem_post_update = 0x0720,
6774faf9 233 i40e_aqc_opc_thermal_sensor = 0x0721,
d358aa9a
GR		 234
235 /* virtualization commands */
8c570dcc
JK		 236 i40e_aqc_opc_send_msg_to_pf = 0x0801,
237 i40e_aqc_opc_send_msg_to_vf = 0x0802,
238 i40e_aqc_opc_send_msg_to_peer = 0x0803,
d358aa9a
GR		 239
240 /* alternate structure */
8c570dcc
JK		 241 i40e_aqc_opc_alternate_write = 0x0900,
242 i40e_aqc_opc_alternate_write_indirect = 0x0901,
243 i40e_aqc_opc_alternate_read = 0x0902,
244 i40e_aqc_opc_alternate_read_indirect = 0x0903,
245 i40e_aqc_opc_alternate_write_done = 0x0904,
246 i40e_aqc_opc_alternate_set_mode = 0x0905,
247 i40e_aqc_opc_alternate_clear_port = 0x0906,
d358aa9a
GR		 248
249 /* LLDP commands */
8c570dcc
JK		 250 i40e_aqc_opc_lldp_get_mib = 0x0A00,
251 i40e_aqc_opc_lldp_update_mib = 0x0A01,
252 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
253 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
254 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
255 i40e_aqc_opc_lldp_stop = 0x0A05,
256 i40e_aqc_opc_lldp_start = 0x0A06,
d358aa9a
GR		 257
258 /* Tunnel commands */
8c570dcc
JK		 259 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
260 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
e50c8d6d
ASJ		 261 i40e_aqc_opc_set_rss_key = 0x0B02,
262 i40e_aqc_opc_set_rss_lut = 0x0B03,
263 i40e_aqc_opc_get_rss_key = 0x0B04,
264 i40e_aqc_opc_get_rss_lut = 0x0B05,
d358aa9a
GR		 265
266 /* Async Events */
8c570dcc 267 i40e_aqc_opc_event_lan_overflow = 0x1001,
d358aa9a
GR		 268
269 /* OEM commands */
8c570dcc
JK		 270 i40e_aqc_opc_oem_parameter_change = 0xFE00,
271 i40e_aqc_opc_oem_device_status_change = 0xFE01,
672415c5
SN		 272 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
273 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
d358aa9a
GR		 274
275 /* debug commands */
8c570dcc
JK		 276 i40e_aqc_opc_debug_read_reg = 0xFF03,
277 i40e_aqc_opc_debug_write_reg = 0xFF04,
278 i40e_aqc_opc_debug_modify_reg = 0xFF07,
279 i40e_aqc_opc_debug_dump_internals = 0xFF08,
d358aa9a
GR		 280};
281
282/* command structures and indirect data structures */
283
284/* Structure naming conventions:
285 * - no suffix for direct command descriptor structures
286 * - _data for indirect sent data
287 * - _resp for indirect return data (data which is both will use _data)
288 * - _completion for direct return data
289 * - _element_ for repeated elements (may also be _data or _resp)
290 *
291 * Command structures are expected to overlay the params.raw member of the basic
292 * descriptor, and as such cannot exceed 16 bytes in length.
293 */
294
295/* This macro is used to generate a compilation error if a structure
296 * is not exactly the correct length. It gives a divide by zero error if the
297 * structure is not of the correct size, otherwise it creates an enum that is
298 * never used.
299 */
300#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
301 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
302
303/* This macro is used extensively to ensure that command structures are 16
304 * bytes in length as they have to map to the raw array of that size.
305 */
8c570dcc 306#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
d358aa9a
GR		 307
308/* internal (0x00XX) commands */
309
310/* Get version (direct 0x0001) */
311struct i40e_aqc_get_version {
312 __le32 rom_ver;
313 __le32 fw_build;
314 __le16 fw_major;
315 __le16 fw_minor;
316 __le16 api_major;
317 __le16 api_minor;
318};
319
320I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
321
322/* Send driver version (indirect 0x0002) */
323struct i40e_aqc_driver_version {
8c570dcc
JK		 324 u8 driver_major_ver;
325 u8 driver_minor_ver;
326 u8 driver_build_ver;
327 u8 driver_subbuild_ver;
328 u8 reserved[4];
329 __le32 address_high;
330 __le32 address_low;
d358aa9a
GR		 331};
332
333I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
334
335/* Queue Shutdown (direct 0x0003) */
336struct i40e_aqc_queue_shutdown {
8c570dcc
JK		 337 __le32 driver_unloading;
338#define I40E_AQ_DRIVER_UNLOADING 0x1
339 u8 reserved[12];
d358aa9a
GR		 340};
341
342I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
343
f94234ee
SN		 344/* Set PF context (0x0004, direct) */
345struct i40e_aqc_set_pf_context {
346 u8 pf_id;
347 u8 reserved[15];
348};
349
350I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
351
d358aa9a
GR		 352/* Request resource ownership (direct 0x0008)
353 * Release resource ownership (direct 0x0009)
354 */
8c570dcc
JK		 355#define I40E_AQ_RESOURCE_NVM 1
356#define I40E_AQ_RESOURCE_SDP 2
357#define I40E_AQ_RESOURCE_ACCESS_READ 1
358#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
359#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
360#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
d358aa9a
GR		 361
362struct i40e_aqc_request_resource {
8c570dcc
JK		 363 __le16 resource_id;
364 __le16 access_type;
365 __le32 timeout;
366 __le32 resource_number;
367 u8 reserved[4];
d358aa9a
GR		 368};
369
370I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
371
372/* Get function capabilities (indirect 0x000A)
373 * Get device capabilities (indirect 0x000B)
374 */
375struct i40e_aqc_list_capabilites {
376 u8 command_flags;
8c570dcc 377#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
d358aa9a
GR		 378 u8 pf_index;
379 u8 reserved[2];
380 __le32 count;
381 __le32 addr_high;
382 __le32 addr_low;
383};
384
385I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
386
387struct i40e_aqc_list_capabilities_element_resp {
8c570dcc
JK		 388 __le16 id;
389 u8 major_rev;
390 u8 minor_rev;
391 __le32 number;
392 __le32 logical_id;
393 __le32 phys_id;
394 u8 reserved[16];
d358aa9a
GR		 395};
396
397/* list of caps */
398
8c570dcc
JK		 399#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
400#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
401#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
402#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
403#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
404#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
4ba40bce 405#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
8c570dcc
JK		 406#define I40E_AQ_CAP_ID_SRIOV 0x0012
407#define I40E_AQ_CAP_ID_VF 0x0013
408#define I40E_AQ_CAP_ID_VMDQ 0x0014
409#define I40E_AQ_CAP_ID_8021QBG 0x0015
410#define I40E_AQ_CAP_ID_8021QBR 0x0016
411#define I40E_AQ_CAP_ID_VSI 0x0017
412#define I40E_AQ_CAP_ID_DCB 0x0018
413#define I40E_AQ_CAP_ID_FCOE 0x0021
35155fe6 414#define I40E_AQ_CAP_ID_ISCSI 0x0022
8c570dcc
JK		 415#define I40E_AQ_CAP_ID_RSS 0x0040
416#define I40E_AQ_CAP_ID_RXQ 0x0041
417#define I40E_AQ_CAP_ID_TXQ 0x0042
418#define I40E_AQ_CAP_ID_MSIX 0x0043
419#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
420#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
421#define I40E_AQ_CAP_ID_1588 0x0046
422#define I40E_AQ_CAP_ID_IWARP 0x0051
423#define I40E_AQ_CAP_ID_LED 0x0061
424#define I40E_AQ_CAP_ID_SDP 0x0062
425#define I40E_AQ_CAP_ID_MDIO 0x0063
406e734a 426#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
8c570dcc
JK		 427#define I40E_AQ_CAP_ID_FLEX10 0x00F1
428#define I40E_AQ_CAP_ID_CEM 0x00F2
d358aa9a
GR		 429
430/* Set CPPM Configuration (direct 0x0103) */
431struct i40e_aqc_cppm_configuration {
8c570dcc
JK		 432 __le16 command_flags;
433#define I40E_AQ_CPPM_EN_LTRC 0x0800
434#define I40E_AQ_CPPM_EN_DMCTH 0x1000
435#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
436#define I40E_AQ_CPPM_EN_HPTC 0x4000
437#define I40E_AQ_CPPM_EN_DMARC 0x8000
438 __le16 ttlx;
439 __le32 dmacr;
440 __le16 dmcth;
441 u8 hptc;
442 u8 reserved;
443 __le32 pfltrc;
d358aa9a
GR		 444};
445
446I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
447
448/* Set ARP Proxy command / response (indirect 0x0104) */
449struct i40e_aqc_arp_proxy_data {
8c570dcc
JK		 450 __le16 command_flags;
451#define I40E_AQ_ARP_INIT_IPV4 0x0008
452#define I40E_AQ_ARP_UNSUP_CTL 0x0010
453#define I40E_AQ_ARP_ENA 0x0020
454#define I40E_AQ_ARP_ADD_IPV4 0x0040
455#define I40E_AQ_ARP_DEL_IPV4 0x0080
456 __le16 table_id;
457 __le32 pfpm_proxyfc;
458 __le32 ip_addr;
459 u8 mac_addr[6];
672415c5 460 u8 reserved[2];
d358aa9a
GR		 461};
462
8d5e33ad
SN		 463I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
464
d358aa9a
GR		 465/* Set NS Proxy Table Entry Command (indirect 0x0105) */
466struct i40e_aqc_ns_proxy_data {
8c570dcc
JK		 467 __le16 table_idx_mac_addr_0;
468 __le16 table_idx_mac_addr_1;
469 __le16 table_idx_ipv6_0;
470 __le16 table_idx_ipv6_1;
471 __le16 control;
472#define I40E_AQ_NS_PROXY_ADD_0 0x0100
473#define I40E_AQ_NS_PROXY_DEL_0 0x0200
474#define I40E_AQ_NS_PROXY_ADD_1 0x0400
475#define I40E_AQ_NS_PROXY_DEL_1 0x0800
476#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
477#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
478#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
479#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
480#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
481#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
482#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
483 u8 mac_addr_0[6];
484 u8 mac_addr_1[6];
485 u8 local_mac_addr[6];
486 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
487 u8 ipv6_addr_1[16];
d358aa9a
GR		 488};
489
8d5e33ad
SN		 490I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
491
d358aa9a
GR		 492/* Manage LAA Command (0x0106) - obsolete */
493struct i40e_aqc_mng_laa {
494 __le16 command_flags;
8c570dcc
JK		 495#define I40E_AQ_LAA_FLAG_WR 0x8000
496 u8 reserved[2];
497 __le32 sal;
498 __le16 sah;
499 u8 reserved2[6];
d358aa9a
GR		 500};
501
8d5e33ad
SN		 502I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
503
d358aa9a
GR		 504/* Manage MAC Address Read Command (indirect 0x0107) */
505struct i40e_aqc_mac_address_read {
506 __le16 command_flags;
8c570dcc
JK		 507#define I40E_AQC_LAN_ADDR_VALID 0x10
508#define I40E_AQC_SAN_ADDR_VALID 0x20
509#define I40E_AQC_PORT_ADDR_VALID 0x40
510#define I40E_AQC_WOL_ADDR_VALID 0x80
cb2f65bc
GR		 511#define I40E_AQC_MC_MAG_EN_VALID 0x100
512#define I40E_AQC_ADDR_VALID_MASK 0x1F0
8c570dcc
JK		 513 u8 reserved[6];
514 __le32 addr_high;
515 __le32 addr_low;
d358aa9a
GR		 516};
517
518I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
519
520struct i40e_aqc_mac_address_read_data {
521 u8 pf_lan_mac[6];
522 u8 pf_san_mac[6];
523 u8 port_mac[6];
524 u8 pf_wol_mac[6];
525};
526
527I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
528
529/* Manage MAC Address Write Command (0x0108) */
530struct i40e_aqc_mac_address_write {
8c570dcc
JK		 531 __le16 command_flags;
532#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
533#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
534#define I40E_AQC_WRITE_TYPE_PORT 0x8000
cb2f65bc
GR		 535#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
536#define I40E_AQC_WRITE_TYPE_MASK 0xC000
537
8c570dcc
JK		 538 __le16 mac_sah;
539 __le32 mac_sal;
540 u8 reserved[8];
d358aa9a
GR		 541};
542
543I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
544
545/* PXE commands (0x011x) */
546
547/* Clear PXE Command and response (direct 0x0110) */
548struct i40e_aqc_clear_pxe {
549 u8 rx_cnt;
550 u8 reserved[15];
551};
552
553I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
554
555/* Switch configuration commands (0x02xx) */
556
557/* Used by many indirect commands that only pass an seid and a buffer in the
558 * command
559 */
560struct i40e_aqc_switch_seid {
8c570dcc
JK		 561 __le16 seid;
562 u8 reserved[6];
563 __le32 addr_high;
564 __le32 addr_low;
d358aa9a
GR		 565};
566
567I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
568
569/* Get Switch Configuration command (indirect 0x0200)
570 * uses i40e_aqc_switch_seid for the descriptor
571 */
572struct i40e_aqc_get_switch_config_header_resp {
8c570dcc
JK		 573 __le16 num_reported;
574 __le16 num_total;
575 u8 reserved[12];
d358aa9a
GR		 576};
577
8d5e33ad
SN		 578I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
579
d358aa9a 580struct i40e_aqc_switch_config_element_resp {
8c570dcc
JK		 581 u8 element_type;
582#define I40E_AQ_SW_ELEM_TYPE_MAC 1
583#define I40E_AQ_SW_ELEM_TYPE_PF 2
584#define I40E_AQ_SW_ELEM_TYPE_VF 3
585#define I40E_AQ_SW_ELEM_TYPE_EMP 4
586#define I40E_AQ_SW_ELEM_TYPE_BMC 5
587#define I40E_AQ_SW_ELEM_TYPE_PV 16
588#define I40E_AQ_SW_ELEM_TYPE_VEB 17
589#define I40E_AQ_SW_ELEM_TYPE_PA 18
590#define I40E_AQ_SW_ELEM_TYPE_VSI 19
591 u8 revision;
592#define I40E_AQ_SW_ELEM_REV_1 1
593 __le16 seid;
594 __le16 uplink_seid;
595 __le16 downlink_seid;
596 u8 reserved[3];
597 u8 connection_type;
598#define I40E_AQ_CONN_TYPE_REGULAR 0x1
599#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
600#define I40E_AQ_CONN_TYPE_CASCADED 0x3
601 __le16 scheduler_id;
602 __le16 element_info;
d358aa9a
GR		 603};
604
8d5e33ad
SN		 605I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
606
d358aa9a
GR		 607/* Get Switch Configuration (indirect 0x0200)
608 * an array of elements are returned in the response buffer
609 * the first in the array is the header, remainder are elements
610 */
611struct i40e_aqc_get_switch_config_resp {
8c570dcc
JK		 612 struct i40e_aqc_get_switch_config_header_resp header;
613 struct i40e_aqc_switch_config_element_resp element[1];
d358aa9a
GR		 614};
615
8d5e33ad
SN		 616I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
617
d358aa9a
GR		 618/* Add Statistics (direct 0x0201)
619 * Remove Statistics (direct 0x0202)
620 */
621struct i40e_aqc_add_remove_statistics {
8c570dcc
JK		 622 __le16 seid;
623 __le16 vlan;
624 __le16 stat_index;
625 u8 reserved[10];
d358aa9a
GR		 626};
627
628I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
629
630/* Set Port Parameters command (direct 0x0203) */
631struct i40e_aqc_set_port_parameters {
8c570dcc
JK		 632 __le16 command_flags;
633#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
634#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
635#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
636 __le16 bad_frame_vsi;
637 __le16 default_seid; /* reserved for command */
638 u8 reserved[10];
d358aa9a
GR		 639};
640
641I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
642
643/* Get Switch Resource Allocation (indirect 0x0204) */
644struct i40e_aqc_get_switch_resource_alloc {
8c570dcc
JK		 645 u8 num_entries; /* reserved for command */
646 u8 reserved[7];
647 __le32 addr_high;
648 __le32 addr_low;
d358aa9a
GR		 649};
650
651I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
652
653/* expect an array of these structs in the response buffer */
654struct i40e_aqc_switch_resource_alloc_element_resp {
8c570dcc
JK		 655 u8 resource_type;
656#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
657#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
658#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
659#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
660#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
661#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
662#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
663#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
664#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
665#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
666#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
667#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
668#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
669#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
670#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
671#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
672#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
673#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
674#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
675 u8 reserved1;
676 __le16 guaranteed;
677 __le16 total;
678 __le16 used;
679 __le16 total_unalloced;
680 u8 reserved2[6];
d358aa9a
GR		 681};
682
8d5e33ad
SN		 683I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
684
fa5623a6
SN		 685/* Set Switch Configuration (direct 0x0205) */
686struct i40e_aqc_set_switch_config {
687 __le16 flags;
688#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
689#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
690 __le16 valid_flags;
691 u8 reserved[12];
692};
693
694I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
695
d358aa9a
GR		 696/* Add VSI (indirect 0x0210)
697 * this indirect command uses struct i40e_aqc_vsi_properties_data
698 * as the indirect buffer (128 bytes)
699 *
700 * Update VSI (indirect 0x211)
701 * uses the same data structure as Add VSI
702 *
703 * Get VSI (indirect 0x0212)
704 * uses the same completion and data structure as Add VSI
705 */
706struct i40e_aqc_add_get_update_vsi {
8c570dcc
JK		 707 __le16 uplink_seid;
708 u8 connection_type;
709#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
710#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
711#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
712 u8 reserved1;
713 u8 vf_id;
714 u8 reserved2;
715 __le16 vsi_flags;
716#define I40E_AQ_VSI_TYPE_SHIFT 0x0
717#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
718#define I40E_AQ_VSI_TYPE_VF 0x0
719#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
720#define I40E_AQ_VSI_TYPE_PF 0x2
721#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
722#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
723 __le32 addr_high;
724 __le32 addr_low;
d358aa9a
GR		 725};
726
727I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
728
729struct i40e_aqc_add_get_update_vsi_completion {
730 __le16 seid;
731 __le16 vsi_number;
732 __le16 vsi_used;
733 __le16 vsi_free;
734 __le32 addr_high;
735 __le32 addr_low;
736};
737
738I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
739
740struct i40e_aqc_vsi_properties_data {
741 /* first 96 byte are written by SW */
8c570dcc
JK		 742 __le16 valid_sections;
743#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
744#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
745#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
746#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
747#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
748#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
749#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
750#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
751#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
752#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
d358aa9a 753 /* switch section */
8c570dcc
JK		 754 __le16 switch_id; /* 12bit id combined with flags below */
755#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
756#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
757#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
758#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
759#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
760 u8 sw_reserved[2];
d358aa9a 761 /* security section */
8c570dcc
JK		 762 u8 sec_flags;
763#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
764#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
765#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
766 u8 sec_reserved;
d358aa9a 767 /* VLAN section */
8c570dcc
JK		 768 __le16 pvid; /* VLANS include priority bits */
769 __le16 fcoe_pvid;
770 u8 port_vlan_flags;
771#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
772#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
773 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
774#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
775#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
776#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
777#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
778#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
779#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
780 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
781#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
782#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
783#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
784#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
785 u8 pvlan_reserved[3];
d358aa9a 786 /* ingress egress up sections */
8c570dcc
JK		 787 __le32 ingress_table; /* bitmap, 3 bits per up */
788#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
789#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
790 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
791#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
792#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
793 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
794#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
795#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
796 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
797#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
798#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
799 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
800#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
801#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
802 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
803#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
804#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
805 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
806#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
807#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
808 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
809#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
810#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
811 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
812 __le32 egress_table; /* same defines as for ingress table */
d358aa9a 813 /* cascaded PV section */
8c570dcc
JK		 814 __le16 cas_pv_tag;
815 u8 cas_pv_flags;
816#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
817#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
818 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
819#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
820#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
821#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
822#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
823#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
824#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
825 u8 cas_pv_reserved;
d358aa9a 826 /* queue mapping section */
8c570dcc
JK		 827 __le16 mapping_flags;
828#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
829#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
830 __le16 queue_mapping[16];
831#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
832#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
833 __le16 tc_mapping[8];
834#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
835#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
836 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
837#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
838#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
839 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
d358aa9a 840 /* queueing option section */
8c570dcc 841 u8 queueing_opt_flags;
e50c8d6d
ASJ		 842#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
843#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
8c570dcc
JK		 844#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
845#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
e50c8d6d
ASJ		 846#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
847#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
8c570dcc 848 u8 queueing_opt_reserved[3];
d358aa9a 849 /* scheduler section */
8c570dcc
JK		 850 u8 up_enable_bits;
851 u8 sched_reserved;
d358aa9a 852 /* outer up section */
8c570dcc
JK		 853 __le32 outer_up_table; /* same structure and defines as ingress tbl */
854 u8 cmd_reserved[8];
d358aa9a 855 /* last 32 bytes are written by FW */
8c570dcc 856 __le16 qs_handle[8];
d358aa9a 857#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
8c570dcc
JK		 858 __le16 stat_counter_idx;
859 __le16 sched_id;
860 u8 resp_reserved[12];
d358aa9a
GR		 861};
862
863I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
864
865/* Add Port Virtualizer (direct 0x0220)
866 * also used for update PV (direct 0x0221) but only flags are used
867 * (IS_CTRL_PORT only works on add PV)
868 */
869struct i40e_aqc_add_update_pv {
8c570dcc
JK		 870 __le16 command_flags;
871#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
872#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
873#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
874#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
875 __le16 uplink_seid;
876 __le16 connected_seid;
877 u8 reserved[10];
d358aa9a
GR		 878};
879
880I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
881
882struct i40e_aqc_add_update_pv_completion {
883 /* reserved for update; for add also encodes error if rc == ENOSPC */
8c570dcc
JK		 884 __le16 pv_seid;
885#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
886#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
887#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
888#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
889 u8 reserved[14];
d358aa9a
GR		 890};
891
892I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
893
894/* Get PV Params (direct 0x0222)
895 * uses i40e_aqc_switch_seid for the descriptor
896 */
897
898struct i40e_aqc_get_pv_params_completion {
8c570dcc
JK		 899 __le16 seid;
900 __le16 default_stag;
901 __le16 pv_flags; /* same flags as add_pv */
902#define I40E_AQC_GET_PV_PV_TYPE 0x1
903#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
904#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
905 u8 reserved[8];
906 __le16 default_port_seid;
d358aa9a
GR		 907};
908
909I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
910
911/* Add VEB (direct 0x0230) */
912struct i40e_aqc_add_veb {
8c570dcc
JK		 913 __le16 uplink_seid;
914 __le16 downlink_seid;
915 __le16 veb_flags;
916#define I40E_AQC_ADD_VEB_FLOATING 0x1
917#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
918#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
d358aa9a 919 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
8c570dcc
JK		 920#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
921#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
fa5623a6
SN		 922#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
923#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
8c570dcc
JK		 924 u8 enable_tcs;
925 u8 reserved[9];
d358aa9a
GR		 926};
927
928I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
929
930struct i40e_aqc_add_veb_completion {
8c570dcc
JK		 931 u8 reserved[6];
932 __le16 switch_seid;
d358aa9a 933 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
8c570dcc
JK		 934 __le16 veb_seid;
935#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
936#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
937#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
938#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
939 __le16 statistic_index;
940 __le16 vebs_used;
941 __le16 vebs_free;
d358aa9a
GR		 942};
943
944I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
945
946/* Get VEB Parameters (direct 0x0232)
947 * uses i40e_aqc_switch_seid for the descriptor
948 */
949struct i40e_aqc_get_veb_parameters_completion {
8c570dcc
JK		 950 __le16 seid;
951 __le16 switch_id;
952 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
953 __le16 statistic_index;
954 __le16 vebs_used;
955 __le16 vebs_free;
956 u8 reserved[4];
d358aa9a
GR		 957};
958
959I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
960
961/* Delete Element (direct 0x0243)
962 * uses the generic i40e_aqc_switch_seid
963 */
964
965/* Add MAC-VLAN (indirect 0x0250) */
966
967/* used for the command for most vlan commands */
968struct i40e_aqc_macvlan {
8c570dcc
JK		 969 __le16 num_addresses;
970 __le16 seid[3];
971#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
972#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 973 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 974#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
975 __le32 addr_high;
976 __le32 addr_low;
d358aa9a
GR		 977};
978
979I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
980
981/* indirect data for command and response */
982struct i40e_aqc_add_macvlan_element_data {
8c570dcc
JK		 983 u8 mac_addr[6];
984 __le16 vlan_tag;
985 __le16 flags;
986#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
987#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
988#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
989#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
90680779 990#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
8c570dcc
JK		 991 __le16 queue_number;
992#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
993#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
d358aa9a
GR		 994 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
995 /* response section */
8c570dcc
JK		 996 u8 match_method;
997#define I40E_AQC_MM_PERFECT_MATCH 0x01
998#define I40E_AQC_MM_HASH_MATCH 0x02
999#define I40E_AQC_MM_ERR_NO_RES 0xFF
1000 u8 reserved1[3];
d358aa9a
GR		 1001};
1002
1003struct i40e_aqc_add_remove_macvlan_completion {
1004 __le16 perfect_mac_used;
1005 __le16 perfect_mac_free;
1006 __le16 unicast_hash_free;
1007 __le16 multicast_hash_free;
1008 __le32 addr_high;
1009 __le32 addr_low;
1010};
1011
1012I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1013
1014/* Remove MAC-VLAN (indirect 0x0251)
1015 * uses i40e_aqc_macvlan for the descriptor
1016 * data points to an array of num_addresses of elements
1017 */
1018
1019struct i40e_aqc_remove_macvlan_element_data {
8c570dcc
JK		 1020 u8 mac_addr[6];
1021 __le16 vlan_tag;
1022 u8 flags;
1023#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1024#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1025#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1026#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1027 u8 reserved[3];
d358aa9a 1028 /* reply section */
8c570dcc
JK		 1029 u8 error_code;
1030#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1031#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1032 u8 reply_reserved[3];
d358aa9a
GR		 1033};
1034
1035/* Add VLAN (indirect 0x0252)
1036 * Remove VLAN (indirect 0x0253)
1037 * use the generic i40e_aqc_macvlan for the command
1038 */
1039struct i40e_aqc_add_remove_vlan_element_data {
8c570dcc
JK		 1040 __le16 vlan_tag;
1041 u8 vlan_flags;
d358aa9a 1042/* flags for add VLAN */
8c570dcc
JK		 1043#define I40E_AQC_ADD_VLAN_LOCAL 0x1
1044#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1045#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1046#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1047#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1048#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1049#define I40E_AQC_VLAN_PTYPE_SHIFT 3
1050#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1051#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1052#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1053#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1054#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
d358aa9a 1055/* flags for remove VLAN */
8c570dcc
JK		 1056#define I40E_AQC_REMOVE_VLAN_ALL 0x1
1057 u8 reserved;
1058 u8 result;
d358aa9a 1059/* flags for add VLAN */
8c570dcc
JK		 1060#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1061#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1062#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
d358aa9a 1063/* flags for remove VLAN */
8c570dcc
JK		 1064#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1065#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1066 u8 reserved1[3];
d358aa9a
GR		 1067};
1068
1069struct i40e_aqc_add_remove_vlan_completion {
8c570dcc
JK		 1070 u8 reserved[4];
1071 __le16 vlans_used;
1072 __le16 vlans_free;
1073 __le32 addr_high;
1074 __le32 addr_low;
d358aa9a
GR		 1075};
1076
1077/* Set VSI Promiscuous Modes (direct 0x0254) */
1078struct i40e_aqc_set_vsi_promiscuous_modes {
8c570dcc
JK		 1079 __le16 promiscuous_flags;
1080 __le16 valid_flags;
d358aa9a 1081/* flags used for both fields above */
8c570dcc
JK		 1082#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1083#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1084#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1085#define I40E_AQC_SET_VSI_DEFAULT 0x08
1086#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
3b120089 1087#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
8c570dcc
JK		 1088 __le16 seid;
1089#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1090 __le16 vlan_tag;
cb2f65bc 1091#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
8c570dcc
JK		 1092#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1093 u8 reserved[8];
d358aa9a
GR		 1094};
1095
1096I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1097
1098/* Add S/E-tag command (direct 0x0255)
1099 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1100 */
1101struct i40e_aqc_add_tag {
8c570dcc
JK		 1102 __le16 flags;
1103#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1104 __le16 seid;
1105#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1106#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1107 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1108 __le16 tag;
1109 __le16 queue_number;
1110 u8 reserved[8];
d358aa9a
GR		 1111};
1112
1113I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1114
1115struct i40e_aqc_add_remove_tag_completion {
8c570dcc
JK		 1116 u8 reserved[12];
1117 __le16 tags_used;
1118 __le16 tags_free;
d358aa9a
GR		 1119};
1120
1121I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1122
1123/* Remove S/E-tag command (direct 0x0256)
1124 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1125 */
1126struct i40e_aqc_remove_tag {
8c570dcc
JK		 1127 __le16 seid;
1128#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1129#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1130 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1131 __le16 tag;
1132 u8 reserved[12];
d358aa9a
GR		 1133};
1134
8d5e33ad
SN		 1135I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1136
d358aa9a
GR		 1137/* Add multicast E-Tag (direct 0x0257)
1138 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1139 * and no external data
1140 */
1141struct i40e_aqc_add_remove_mcast_etag {
8c570dcc
JK		 1142 __le16 pv_seid;
1143 __le16 etag;
1144 u8 num_unicast_etags;
1145 u8 reserved[3];
1146 __le32 addr_high; /* address of array of 2-byte s-tags */
1147 __le32 addr_low;
d358aa9a
GR		 1148};
1149
1150I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1151
1152struct i40e_aqc_add_remove_mcast_etag_completion {
8c570dcc
JK		 1153 u8 reserved[4];
1154 __le16 mcast_etags_used;
1155 __le16 mcast_etags_free;
1156 __le32 addr_high;
1157 __le32 addr_low;
d358aa9a
GR		 1158
1159};
1160
1161I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1162
1163/* Update S/E-Tag (direct 0x0259) */
1164struct i40e_aqc_update_tag {
8c570dcc
JK		 1165 __le16 seid;
1166#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1167#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1168 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1169 __le16 old_tag;
1170 __le16 new_tag;
1171 u8 reserved[10];
d358aa9a
GR		 1172};
1173
1174I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1175
1176struct i40e_aqc_update_tag_completion {
8c570dcc
JK		 1177 u8 reserved[12];
1178 __le16 tags_used;
1179 __le16 tags_free;
d358aa9a
GR		 1180};
1181
1182I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1183
1184/* Add Control Packet filter (direct 0x025A)
1185 * Remove Control Packet filter (direct 0x025B)
1186 * uses the i40e_aqc_add_oveb_cloud,
1187 * and the generic direct completion structure
1188 */
1189struct i40e_aqc_add_remove_control_packet_filter {
8c570dcc
JK		 1190 u8 mac[6];
1191 __le16 etype;
1192 __le16 flags;
1193#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1194#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1195#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1196#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1197#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1198 __le16 seid;
1199#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1200#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1201 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1202 __le16 queue;
1203 u8 reserved[2];
d358aa9a
GR		 1204};
1205
1206I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1207
1208struct i40e_aqc_add_remove_control_packet_filter_completion {
8c570dcc
JK		 1209 __le16 mac_etype_used;
1210 __le16 etype_used;
1211 __le16 mac_etype_free;
1212 __le16 etype_free;
1213 u8 reserved[8];
d358aa9a
GR		 1214};
1215
1216I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1217
1218/* Add Cloud filters (indirect 0x025C)
1219 * Remove Cloud filters (indirect 0x025D)
1220 * uses the i40e_aqc_add_remove_cloud_filters,
1221 * and the generic indirect completion structure
1222 */
1223struct i40e_aqc_add_remove_cloud_filters {
8c570dcc
JK		 1224 u8 num_filters;
1225 u8 reserved;
1226 __le16 seid;
1227#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1228#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1229 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1230 u8 reserved2[4];
1231 __le32 addr_high;
1232 __le32 addr_low;
d358aa9a
GR		 1233};
1234
1235I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1236
1237struct i40e_aqc_add_remove_cloud_filters_element_data {
8c570dcc
JK		 1238 u8 outer_mac[6];
1239 u8 inner_mac[6];
1240 __le16 inner_vlan;
d358aa9a
GR		 1241 union {
1242 struct {
1243 u8 reserved[12];
1244 u8 data[4];
1245 } v4;
1246 struct {
1247 u8 data[16];
1248 } v6;
1249 } ipaddr;
8c570dcc
JK		 1250 __le16 flags;
1251#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
35155fe6 1252#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
d358aa9a
GR		 1253 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1254/* 0x0000 reserved */
8c570dcc 1255#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
d358aa9a 1256/* 0x0002 reserved */
8c570dcc
JK		 1257#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1258#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
d358aa9a 1259/* 0x0005 reserved */
8c570dcc 1260#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
d358aa9a
GR		 1261/* 0x0007 reserved */
1262/* 0x0008 reserved */
8c570dcc
JK		 1263#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1264#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1265#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1266#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1267
1268#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1269#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1270#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1271#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1272#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1273
1274#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1275#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
59264253 1276#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
8c570dcc 1277#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
59264253 1278#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
8c570dcc 1279#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
2fcc1a40
SN		 1280#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1281#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
8c570dcc 1282
90680779
SN		 1283#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1284#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1285#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1286
8c570dcc
JK		 1287 __le32 tenant_id;
1288 u8 reserved[4];
1289 __le16 queue_number;
1290#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
35155fe6 1291#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
8c570dcc
JK		 1292 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1293 u8 reserved2[14];
d358aa9a 1294 /* response section */
8c570dcc
JK		 1295 u8 allocation_result;
1296#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1297#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1298 u8 response_reserved[7];
d358aa9a
GR		 1299};
1300
1301struct i40e_aqc_remove_cloud_filters_completion {
1302 __le16 perfect_ovlan_used;
1303 __le16 perfect_ovlan_free;
1304 __le16 vlan_used;
1305 __le16 vlan_free;
1306 __le32 addr_high;
1307 __le32 addr_low;
1308};
1309
1310I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1311
1312/* Add Mirror Rule (indirect or direct 0x0260)
1313 * Delete Mirror Rule (indirect or direct 0x0261)
1314 * note: some rule types (4,5) do not use an external buffer.
1315 * take care to set the flags correctly.
1316 */
1317struct i40e_aqc_add_delete_mirror_rule {
1318 __le16 seid;
1319 __le16 rule_type;
8c570dcc
JK		 1320#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1321#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
d358aa9a 1322 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
8c570dcc
JK		 1323#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1324#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1325#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1326#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1327#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
d358aa9a
GR		 1328 __le16 num_entries;
1329 __le16 destination; /* VSI for add, rule id for delete */
1330 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1331 __le32 addr_low;
1332};
1333
1334I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1335
1336struct i40e_aqc_add_delete_mirror_rule_completion {
8c570dcc
JK		 1337 u8 reserved[2];
1338 __le16 rule_id; /* only used on add */
1339 __le16 mirror_rules_used;
1340 __le16 mirror_rules_free;
1341 __le32 addr_high;
1342 __le32 addr_low;
d358aa9a
GR		 1343};
1344
1345I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1346
d358aa9a
GR		 1347/* DCB 0x03xx*/
1348
1349/* PFC Ignore (direct 0x0301)
1350 * the command and response use the same descriptor structure
1351 */
1352struct i40e_aqc_pfc_ignore {
8c570dcc
JK		 1353 u8 tc_bitmap;
1354 u8 command_flags; /* unused on response */
1355#define I40E_AQC_PFC_IGNORE_SET 0x80
1356#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1357 u8 reserved[14];
d358aa9a
GR		 1358};
1359
1360I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1361
1362/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1363 * with no parameters
1364 */
1365
1366/* TX scheduler 0x04xx */
1367
1368/* Almost all the indirect commands use
1369 * this generic struct to pass the SEID in param0
1370 */
1371struct i40e_aqc_tx_sched_ind {
8c570dcc
JK		 1372 __le16 vsi_seid;
1373 u8 reserved[6];
1374 __le32 addr_high;
1375 __le32 addr_low;
d358aa9a
GR		 1376};
1377
1378I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1379
1380/* Several commands respond with a set of queue set handles */
1381struct i40e_aqc_qs_handles_resp {
1382 __le16 qs_handles[8];
1383};
1384
1385/* Configure VSI BW limits (direct 0x0400) */
1386struct i40e_aqc_configure_vsi_bw_limit {
8c570dcc
JK		 1387 __le16 vsi_seid;
1388 u8 reserved[2];
1389 __le16 credit;
1390 u8 reserved1[2];
1391 u8 max_credit; /* 0-3, limit = 2^max */
1392 u8 reserved2[7];
d358aa9a
GR		 1393};
1394
1395I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1396
1397/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1398 * responds with i40e_aqc_qs_handles_resp
1399 */
1400struct i40e_aqc_configure_vsi_ets_sla_bw_data {
8c570dcc
JK		 1401 u8 tc_valid_bits;
1402 u8 reserved[15];
1403 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
d358aa9a
GR		 1404
1405 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc
JK		 1406 __le16 tc_bw_max[2];
1407 u8 reserved1[28];
d358aa9a
GR		 1408};
1409
8d5e33ad
SN		 1410I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1411
d358aa9a
GR		 1412/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1413 * responds with i40e_aqc_qs_handles_resp
1414 */
1415struct i40e_aqc_configure_vsi_tc_bw_data {
8c570dcc
JK		 1416 u8 tc_valid_bits;
1417 u8 reserved[3];
1418 u8 tc_bw_credits[8];
1419 u8 reserved1[4];
1420 __le16 qs_handles[8];
d358aa9a
GR		 1421};
1422
8d5e33ad
SN		 1423I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1424
d358aa9a
GR		 1425/* Query vsi bw configuration (indirect 0x0408) */
1426struct i40e_aqc_query_vsi_bw_config_resp {
8c570dcc
JK		 1427 u8 tc_valid_bits;
1428 u8 tc_suspended_bits;
1429 u8 reserved[14];
1430 __le16 qs_handles[8];
1431 u8 reserved1[4];
1432 __le16 port_bw_limit;
1433 u8 reserved2[2];
1434 u8 max_bw; /* 0-3, limit = 2^max */
1435 u8 reserved3[23];
d358aa9a
GR		 1436};
1437
8d5e33ad
SN		 1438I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1439
d358aa9a
GR		 1440/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1441struct i40e_aqc_query_vsi_ets_sla_config_resp {
8c570dcc
JK		 1442 u8 tc_valid_bits;
1443 u8 reserved[3];
1444 u8 share_credits[8];
1445 __le16 credits[8];
d358aa9a
GR		 1446
1447 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc 1448 __le16 tc_bw_max[2];
d358aa9a
GR		 1449};
1450
8d5e33ad
SN		 1451I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1452
d358aa9a
GR		 1453/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1454struct i40e_aqc_configure_switching_comp_bw_limit {
8c570dcc
JK		 1455 __le16 seid;
1456 u8 reserved[2];
1457 __le16 credit;
1458 u8 reserved1[2];
1459 u8 max_bw; /* 0-3, limit = 2^max */
1460 u8 reserved2[7];
d358aa9a
GR		 1461};
1462
1463I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1464
1465/* Enable Physical Port ETS (indirect 0x0413)
1466 * Modify Physical Port ETS (indirect 0x0414)
1467 * Disable Physical Port ETS (indirect 0x0415)
1468 */
1469struct i40e_aqc_configure_switching_comp_ets_data {
8c570dcc
JK		 1470 u8 reserved[4];
1471 u8 tc_valid_bits;
1472 u8 seepage;
1473#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1474 u8 tc_strict_priority_flags;
1475 u8 reserved1[17];
1476 u8 tc_bw_share_credits[8];
1477 u8 reserved2[96];
d358aa9a
GR		 1478};
1479
8d5e33ad
SN		 1480I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1481
d358aa9a
GR		 1482/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1483struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
8c570dcc
JK		 1484 u8 tc_valid_bits;
1485 u8 reserved[15];
1486 __le16 tc_bw_credit[8];
d358aa9a
GR		 1487
1488 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc
JK		 1489 __le16 tc_bw_max[2];
1490 u8 reserved1[28];
d358aa9a
GR		 1491};
1492
8d5e33ad
SN		 1493I40E_CHECK_STRUCT_LEN(0x40,
1494 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1495
d358aa9a
GR		 1496/* Configure Switching Component Bandwidth Allocation per Tc
1497 * (indirect 0x0417)
1498 */
1499struct i40e_aqc_configure_switching_comp_bw_config_data {
8c570dcc
JK		 1500 u8 tc_valid_bits;
1501 u8 reserved[2];
1502 u8 absolute_credits; /* bool */
1503 u8 tc_bw_share_credits[8];
1504 u8 reserved1[20];
d358aa9a
GR		 1505};
1506
8d5e33ad
SN		 1507I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1508
d358aa9a
GR		 1509/* Query Switching Component Configuration (indirect 0x0418) */
1510struct i40e_aqc_query_switching_comp_ets_config_resp {
8c570dcc
JK		 1511 u8 tc_valid_bits;
1512 u8 reserved[35];
1513 __le16 port_bw_limit;
1514 u8 reserved1[2];
1515 u8 tc_bw_max; /* 0-3, limit = 2^max */
1516 u8 reserved2[23];
d358aa9a
GR		 1517};
1518
8d5e33ad
SN		 1519I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1520
d358aa9a
GR		 1521/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1522struct i40e_aqc_query_port_ets_config_resp {
8c570dcc
JK		 1523 u8 reserved[4];
1524 u8 tc_valid_bits;
1525 u8 reserved1;
1526 u8 tc_strict_priority_bits;
1527 u8 reserved2;
1528 u8 tc_bw_share_credits[8];
1529 __le16 tc_bw_limits[8];
d358aa9a
GR		 1530
1531 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
8c570dcc
JK		 1532 __le16 tc_bw_max[2];
1533 u8 reserved3[32];
d358aa9a
GR		 1534};
1535
8d5e33ad
SN		 1536I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1537
d358aa9a
GR		 1538/* Query Switching Component Bandwidth Allocation per Traffic Type
1539 * (indirect 0x041A)
1540 */
1541struct i40e_aqc_query_switching_comp_bw_config_resp {
8c570dcc
JK		 1542 u8 tc_valid_bits;
1543 u8 reserved[2];
1544 u8 absolute_credits_enable; /* bool */
1545 u8 tc_bw_share_credits[8];
1546 __le16 tc_bw_limits[8];
d358aa9a
GR		 1547
1548 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc 1549 __le16 tc_bw_max[2];
d358aa9a
GR		 1550};
1551
8d5e33ad
SN		 1552I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1553
d358aa9a
GR		 1554/* Suspend/resume port TX traffic
1555 * (direct 0x041B and 0x041C) uses the generic SEID struct
1556 */
1557
befc229c
SN		 1558/* Configure partition BW
1559 * (indirect 0x041D)
1560 */
1561struct i40e_aqc_configure_partition_bw_data {
8c570dcc
JK		 1562 __le16 pf_valid_bits;
1563 u8 min_bw[16]; /* guaranteed bandwidth */
1564 u8 max_bw[16]; /* bandwidth limit */
befc229c
SN		 1565};
1566
8d5e33ad
SN		 1567I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1568
d358aa9a
GR		 1569/* Get and set the active HMC resource profile and status.
1570 * (direct 0x0500) and (direct 0x0501)
1571 */
1572struct i40e_aq_get_set_hmc_resource_profile {
8c570dcc
JK		 1573 u8 pm_profile;
1574 u8 pe_vf_enabled;
1575 u8 reserved[14];
d358aa9a
GR		 1576};
1577
1578I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1579
1580enum i40e_aq_hmc_profile {
1581 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
8c570dcc
JK		 1582 I40E_HMC_PROFILE_DEFAULT = 1,
1583 I40E_HMC_PROFILE_FAVOR_VF = 2,
1584 I40E_HMC_PROFILE_EQUAL = 3,
d358aa9a
GR		 1585};
1586
8c570dcc
JK		 1587#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1588#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
d358aa9a
GR		 1589
1590/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1591
1592/* set in param0 for get phy abilities to report qualified modules */
8c570dcc
JK		 1593#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1594#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
d358aa9a
GR		 1595
1596enum i40e_aq_phy_type {
1597 I40E_PHY_TYPE_SGMII = 0x0,
1598 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1599 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1600 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1601 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1602 I40E_PHY_TYPE_XAUI = 0x5,
1603 I40E_PHY_TYPE_XFI = 0x6,
1604 I40E_PHY_TYPE_SFI = 0x7,
1605 I40E_PHY_TYPE_XLAUI = 0x8,
1606 I40E_PHY_TYPE_XLPPI = 0x9,
1607 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1608 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
f94234ee
SN		 1609 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1610 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
d358aa9a
GR		 1611 I40E_PHY_TYPE_100BASE_TX = 0x11,
1612 I40E_PHY_TYPE_1000BASE_T = 0x12,
1613 I40E_PHY_TYPE_10GBASE_T = 0x13,
1614 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1615 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1616 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1617 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1618 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1619 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1620 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
f94234ee
SN		 1621 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1622 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1623 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1624 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
d358aa9a
GR		 1625 I40E_PHY_TYPE_MAX
1626};
1627
1628#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1629#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1630#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1631#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1632#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1633
1634enum i40e_aq_link_speed {
1635 I40E_LINK_SPEED_UNKNOWN = 0,
1636 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1637 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1638 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1639 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1640 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1641};
1642
1643struct i40e_aqc_module_desc {
1644 u8 oui[3];
1645 u8 reserved1;
1646 u8 part_number[16];
1647 u8 revision[4];
1648 u8 reserved2[8];
1649};
1650
8d5e33ad
SN		 1651I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1652
d358aa9a 1653struct i40e_aq_get_phy_abilities_resp {
8c570dcc
JK		 1654 __le32 phy_type; /* bitmap using the above enum for offsets */
1655 u8 link_speed; /* bitmap using the above enum bit patterns */
1656 u8 abilities;
1657#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1658#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1659#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1660#define I40E_AQ_PHY_LINK_ENABLED 0x08
1661#define I40E_AQ_PHY_AN_ENABLED 0x10
1662#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1663 __le16 eee_capability;
1664#define I40E_AQ_EEE_100BASE_TX 0x0002
1665#define I40E_AQ_EEE_1000BASE_T 0x0004
1666#define I40E_AQ_EEE_10GBASE_T 0x0008
1667#define I40E_AQ_EEE_1000BASE_KX 0x0010
1668#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1669#define I40E_AQ_EEE_10GBASE_KR 0x0040
1670 __le32 eeer_val;
1671 u8 d3_lpan;
1672#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1673 u8 reserved[3];
1674 u8 phy_id[4];
1675 u8 module_type[3];
1676 u8 qualified_module_count;
1677#define I40E_AQ_PHY_MAX_QMS 16
1678 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
d358aa9a
GR		 1679};
1680
8d5e33ad
SN		 1681I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1682
d358aa9a
GR		 1683/* Set PHY Config (direct 0x0601) */
1684struct i40e_aq_set_phy_config { /* same bits as above in all */
8c570dcc
JK		 1685 __le32 phy_type;
1686 u8 link_speed;
1687 u8 abilities;
d358aa9a
GR		 1688/* bits 0-2 use the values from get_phy_abilities_resp */
1689#define I40E_AQ_PHY_ENABLE_LINK 0x08
1690#define I40E_AQ_PHY_ENABLE_AN 0x10
1691#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
8c570dcc
JK		 1692 __le16 eee_capability;
1693 __le32 eeer;
1694 u8 low_power_ctrl;
1695 u8 reserved[3];
d358aa9a
GR		 1696};
1697
1698I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1699
1700/* Set MAC Config command data structure (direct 0x0603) */
1701struct i40e_aq_set_mac_config {
8c570dcc
JK		 1702 __le16 max_frame_size;
1703 u8 params;
1704#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1705#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1706#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1707#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1708#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1709#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1710#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1711#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1712#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1713#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1714#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1715#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1716#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1717#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1718 u8 tx_timer_priority; /* bitmap */
1719 __le16 tx_timer_value;
1720 __le16 fc_refresh_threshold;
1721 u8 reserved[8];
d358aa9a
GR		 1722};
1723
1724I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1725
1726/* Restart Auto-Negotiation (direct 0x605) */
1727struct i40e_aqc_set_link_restart_an {
8c570dcc
JK		 1728 u8 command;
1729#define I40E_AQ_PHY_RESTART_AN 0x02
1730#define I40E_AQ_PHY_LINK_ENABLE 0x04
1731 u8 reserved[15];
d358aa9a
GR		 1732};
1733
1734I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1735
1736/* Get Link Status cmd & response data structure (direct 0x0607) */
1737struct i40e_aqc_get_link_status {
8c570dcc
JK		 1738 __le16 command_flags; /* only field set on command */
1739#define I40E_AQ_LSE_MASK 0x3
1740#define I40E_AQ_LSE_NOP 0x0
1741#define I40E_AQ_LSE_DISABLE 0x2
1742#define I40E_AQ_LSE_ENABLE 0x3
d358aa9a 1743/* only response uses this flag */
8c570dcc
JK		 1744#define I40E_AQ_LSE_IS_ENABLED 0x1
1745 u8 phy_type; /* i40e_aq_phy_type */
1746 u8 link_speed; /* i40e_aq_link_speed */
1747 u8 link_info;
1d55aa9c
SN		 1748#define I40E_AQ_LINK_UP 0x01 /* obsolete */
1749#define I40E_AQ_LINK_UP_FUNCTION 0x01
8c570dcc
JK		 1750#define I40E_AQ_LINK_FAULT 0x02
1751#define I40E_AQ_LINK_FAULT_TX 0x04
1752#define I40E_AQ_LINK_FAULT_RX 0x08
1753#define I40E_AQ_LINK_FAULT_REMOTE 0x10
1d55aa9c 1754#define I40E_AQ_LINK_UP_PORT 0x20
8c570dcc
JK		 1755#define I40E_AQ_MEDIA_AVAILABLE 0x40
1756#define I40E_AQ_SIGNAL_DETECT 0x80
1757 u8 an_info;
1758#define I40E_AQ_AN_COMPLETED 0x01
1759#define I40E_AQ_LP_AN_ABILITY 0x02
1760#define I40E_AQ_PD_FAULT 0x04
1761#define I40E_AQ_FEC_EN 0x08
1762#define I40E_AQ_PHY_LOW_POWER 0x10
1763#define I40E_AQ_LINK_PAUSE_TX 0x20
1764#define I40E_AQ_LINK_PAUSE_RX 0x40
1765#define I40E_AQ_QUALIFIED_MODULE 0x80
1766 u8 ext_info;
1767#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1768#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1769#define I40E_AQ_LINK_TX_SHIFT 0x02
1770#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1771#define I40E_AQ_LINK_TX_ACTIVE 0x00
1772#define I40E_AQ_LINK_TX_DRAINED 0x01
1773#define I40E_AQ_LINK_TX_FLUSHED 0x03
1774#define I40E_AQ_LINK_FORCED_40G 0x10
1775 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1776 __le16 max_frame_size;
1777 u8 config;
1778#define I40E_AQ_CONFIG_CRC_ENA 0x04
1779#define I40E_AQ_CONFIG_PACING_MASK 0x78
5eb772f7
SN		 1780 u8 external_power_ability;
1781#define I40E_AQ_LINK_POWER_CLASS_1 0x00
1782#define I40E_AQ_LINK_POWER_CLASS_2 0x01
1783#define I40E_AQ_LINK_POWER_CLASS_3 0x02
1784#define I40E_AQ_LINK_POWER_CLASS_4 0x03
1785 u8 reserved[4];
d358aa9a
GR		 1786};
1787
1788I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1789
1790/* Set event mask command (direct 0x613) */
1791struct i40e_aqc_set_phy_int_mask {
8c570dcc
JK		 1792 u8 reserved[8];
1793 __le16 event_mask;
1794#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1795#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1796#define I40E_AQ_EVENT_LINK_FAULT 0x0008
1797#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1798#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1799#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1800#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1801#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1802#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1803 u8 reserved1[6];
d358aa9a
GR		 1804};
1805
1806I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1807
1808/* Get Local AN advt register (direct 0x0614)
1809 * Set Local AN advt register (direct 0x0615)
1810 * Get Link Partner AN advt register (direct 0x0616)
1811 */
1812struct i40e_aqc_an_advt_reg {
8c570dcc
JK		 1813 __le32 local_an_reg0;
1814 __le16 local_an_reg1;
1815 u8 reserved[10];
d358aa9a
GR		 1816};
1817
1818I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1819
1820/* Set Loopback mode (0x0618) */
1821struct i40e_aqc_set_lb_mode {
8c570dcc
JK		 1822 __le16 lb_mode;
1823#define I40E_AQ_LB_PHY_LOCAL 0x01
1824#define I40E_AQ_LB_PHY_REMOTE 0x02
1825#define I40E_AQ_LB_MAC_LOCAL 0x04
1826 u8 reserved[14];
d358aa9a
GR		 1827};
1828
1829I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1830
f94234ee
SN		 1831/* Set PHY Debug command (0x0622) */
1832struct i40e_aqc_set_phy_debug {
8c570dcc 1833 u8 command_flags;
f94234ee
SN		 1834#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1835#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1836#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1837 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1838#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1839#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1840#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1841#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
8c570dcc 1842 u8 reserved[15];
d358aa9a
GR		 1843};
1844
f94234ee 1845I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
d358aa9a
GR		 1846
1847enum i40e_aq_phy_reg_type {
8c570dcc
JK		 1848 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1849 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1850 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
d358aa9a
GR		 1851};
1852
5394f02f
SN		 1853/* Run PHY Activity (0x0626) */
1854struct i40e_aqc_run_phy_activity {
1855 __le16 activity_id;
1856 u8 flags;
1857 u8 reserved1;
1858 __le32 control;
1859 __le32 data;
1860 u8 reserved2[4];
1861};
1862
1863I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1864
d358aa9a
GR		 1865/* NVM Read command (indirect 0x0701)
1866 * NVM Erase commands (direct 0x0702)
1867 * NVM Update commands (indirect 0x0703)
1868 */
1869struct i40e_aqc_nvm_update {
8c570dcc
JK		 1870 u8 command_flags;
1871#define I40E_AQ_NVM_LAST_CMD 0x01
1872#define I40E_AQ_NVM_FLASH_ONLY 0x80
1873 u8 module_pointer;
1874 __le16 length;
1875 __le32 offset;
1876 __le32 addr_high;
1877 __le32 addr_low;
d358aa9a
GR		 1878};
1879
1880I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1881
f94234ee
SN		 1882/* NVM Config Read (indirect 0x0704) */
1883struct i40e_aqc_nvm_config_read {
8c570dcc 1884 __le16 cmd_flags;
e910ca7c
JK		 1885#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1886#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1887#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
8c570dcc 1888 __le16 element_count;
e910ca7c
JK		 1889 __le16 element_id; /* Feature/field ID */
1890 __le16 element_id_msw; /* MSWord of field ID */
8c570dcc
JK		 1891 __le32 address_high;
1892 __le32 address_low;
f94234ee
SN		 1893};
1894
1895I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1896
1897/* NVM Config Write (indirect 0x0705) */
1898struct i40e_aqc_nvm_config_write {
8c570dcc
JK		 1899 __le16 cmd_flags;
1900 __le16 element_count;
1901 u8 reserved[4];
1902 __le32 address_high;
1903 __le32 address_low;
f94234ee
SN		 1904};
1905
1906I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1907
672415c5
SN		 1908/* Used for 0x0704 as well as for 0x0705 commands */
1909#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1910#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1911 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1912#define I40E_AQ_ANVM_FEATURE 0
1913#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
f94234ee
SN		 1914struct i40e_aqc_nvm_config_data_feature {
1915 __le16 feature_id;
672415c5
SN		 1916#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1917#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1918#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
f94234ee
SN		 1919 __le16 feature_options;
1920 __le16 feature_selection;
1921};
1922
672415c5
SN		 1923I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1924
f94234ee 1925struct i40e_aqc_nvm_config_data_immediate_field {
672415c5
SN		 1926 __le32 field_id;
1927 __le32 field_value;
f94234ee 1928 __le16 field_options;
672415c5 1929 __le16 reserved;
f94234ee
SN		 1930};
1931
672415c5
SN		 1932I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1933
00ada50d
MK		 1934/* OEM Post Update (indirect 0x0720)
1935 * no command data struct used
1936 */
1937 struct i40e_aqc_nvm_oem_post_update {
1938#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1939 u8 sel_data;
1940 u8 reserved[7];
1941};
1942
1943I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1944
1945struct i40e_aqc_nvm_oem_post_update_buffer {
1946 u8 str_len;
1947 u8 dev_addr;
1948 __le16 eeprom_addr;
1949 u8 data[36];
1950};
1951
1952I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1953
6774faf9
SN		 1954/* Thermal Sensor (indirect 0x0721)
1955 * read or set thermal sensor configs and values
1956 * takes a sensor and command specific data buffer, not detailed here
1957 */
1958struct i40e_aqc_thermal_sensor {
1959 u8 sensor_action;
1960#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
1961#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
1962#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
1963 u8 reserved[7];
1964 __le32 addr_high;
1965 __le32 addr_low;
1966};
1967
1968I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1969
d358aa9a
GR		 1970/* Send to PF command (indirect 0x0801) id is only used by PF
1971 * Send to VF command (indirect 0x0802) id is only used by PF
1972 * Send to Peer PF command (indirect 0x0803)
1973 */
1974struct i40e_aqc_pf_vf_message {
8c570dcc
JK		 1975 __le32 id;
1976 u8 reserved[4];
1977 __le32 addr_high;
1978 __le32 addr_low;
d358aa9a
GR		 1979};
1980
1981I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1982
1983/* Alternate structure */
1984
1985/* Direct write (direct 0x0900)
1986 * Direct read (direct 0x0902)
1987 */
1988struct i40e_aqc_alternate_write {
1989 __le32 address0;
1990 __le32 data0;
1991 __le32 address1;
1992 __le32 data1;
1993};
1994
1995I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1996
1997/* Indirect write (indirect 0x0901)
1998 * Indirect read (indirect 0x0903)
1999 */
2000
2001struct i40e_aqc_alternate_ind_write {
2002 __le32 address;
2003 __le32 length;
2004 __le32 addr_high;
2005 __le32 addr_low;
2006};
2007
2008I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2009
2010/* Done alternate write (direct 0x0904)
2011 * uses i40e_aq_desc
2012 */
2013struct i40e_aqc_alternate_write_done {
8c570dcc 2014 __le16 cmd_flags;
d358aa9a
GR		 2015#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2016#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2017#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2018#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
8c570dcc 2019 u8 reserved[14];
d358aa9a
GR		 2020};
2021
2022I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2023
2024/* Set OEM mode (direct 0x0905) */
2025struct i40e_aqc_alternate_set_mode {
8c570dcc 2026 __le32 mode;
d358aa9a
GR		 2027#define I40E_AQ_ALTERNATE_MODE_NONE 0
2028#define I40E_AQ_ALTERNATE_MODE_OEM 1
8c570dcc 2029 u8 reserved[12];
d358aa9a
GR		 2030};
2031
2032I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2033
2034/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2035
2036/* async events 0x10xx */
2037
2038/* Lan Queue Overflow Event (direct, 0x1001) */
2039struct i40e_aqc_lan_overflow {
8c570dcc
JK		 2040 __le32 prtdcb_rupto;
2041 __le32 otx_ctl;
2042 u8 reserved[8];
d358aa9a
GR		 2043};
2044
2045I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2046
2047/* Get LLDP MIB (indirect 0x0A00) */
2048struct i40e_aqc_lldp_get_mib {
8c570dcc
JK		 2049 u8 type;
2050 u8 reserved1;
2051#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2052#define I40E_AQ_LLDP_MIB_LOCAL 0x0
2053#define I40E_AQ_LLDP_MIB_REMOTE 0x1
2054#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2055#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2056#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2057#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2058#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2059#define I40E_AQ_LLDP_TX_SHIFT 0x4
2060#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
d358aa9a 2061/* TX pause flags use I40E_AQ_LINK_TX_* above */
8c570dcc
JK		 2062 __le16 local_len;
2063 __le16 remote_len;
2064 u8 reserved2[2];
2065 __le32 addr_high;
2066 __le32 addr_low;
d358aa9a
GR		 2067};
2068
2069I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2070
2071/* Configure LLDP MIB Change Event (direct 0x0A01)
2072 * also used for the event (with type in the command field)
2073 */
2074struct i40e_aqc_lldp_update_mib {
8c570dcc
JK		 2075 u8 command;
2076#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2077#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2078 u8 reserved[7];
2079 __le32 addr_high;
2080 __le32 addr_low;
d358aa9a
GR		 2081};
2082
2083I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2084
2085/* Add LLDP TLV (indirect 0x0A02)
2086 * Delete LLDP TLV (indirect 0x0A04)
2087 */
2088struct i40e_aqc_lldp_add_tlv {
8c570dcc
JK		 2089 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2090 u8 reserved1[1];
2091 __le16 len;
2092 u8 reserved2[4];
2093 __le32 addr_high;
2094 __le32 addr_low;
d358aa9a
GR		 2095};
2096
2097I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2098
2099/* Update LLDP TLV (indirect 0x0A03) */
2100struct i40e_aqc_lldp_update_tlv {
8c570dcc
JK		 2101 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2102 u8 reserved;
2103 __le16 old_len;
2104 __le16 new_offset;
2105 __le16 new_len;
2106 __le32 addr_high;
2107 __le32 addr_low;
d358aa9a
GR		 2108};
2109
2110I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2111
2112/* Stop LLDP (direct 0x0A05) */
2113struct i40e_aqc_lldp_stop {
8c570dcc
JK		 2114 u8 command;
2115#define I40E_AQ_LLDP_AGENT_STOP 0x0
2116#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2117 u8 reserved[15];
d358aa9a
GR		 2118};
2119
2120I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2121
2122/* Start LLDP (direct 0x0A06) */
2123
2124struct i40e_aqc_lldp_start {
8c570dcc
JK		 2125 u8 command;
2126#define I40E_AQ_LLDP_AGENT_START 0x1
2127 u8 reserved[15];
d358aa9a
GR		 2128};
2129
2130I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2131
2132/* Apply MIB changes (0x0A07)
2133 * uses the generic struc as it contains no data
2134 */
2135
2136/* Add Udp Tunnel command and completion (direct 0x0B00) */
2137struct i40e_aqc_add_udp_tunnel {
8c570dcc
JK		 2138 __le16 udp_port;
2139 u8 reserved0[3];
2140 u8 protocol_type;
9774dd8d
SN		 2141#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2142#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2143#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2fcc1a40 2144#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
8c570dcc 2145 u8 reserved1[10];
d358aa9a
GR		 2146};
2147
2148I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2149
2150struct i40e_aqc_add_udp_tunnel_completion {
2151 __le16 udp_port;
2152 u8 filter_entry_index;
2153 u8 multiple_pfs;
8c570dcc
JK		 2154#define I40E_AQC_SINGLE_PF 0x0
2155#define I40E_AQC_MULTIPLE_PFS 0x1
d358aa9a
GR		 2156 u8 total_filters;
2157 u8 reserved[11];
2158};
2159
2160I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2161
2162/* remove UDP Tunnel command (0x0B01) */
2163struct i40e_aqc_remove_udp_tunnel {
8c570dcc
JK		 2164 u8 reserved[2];
2165 u8 index; /* 0 to 15 */
2166 u8 reserved2[13];
d358aa9a
GR		 2167};
2168
2169I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2170
2171struct i40e_aqc_del_udp_tunnel_completion {
8c570dcc
JK		 2172 __le16 udp_port;
2173 u8 index; /* 0 to 15 */
2174 u8 multiple_pfs;
2175 u8 total_filters_used;
2176 u8 reserved1[11];
d358aa9a
GR		 2177};
2178
2179I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2180
e50c8d6d
ASJ		 2181struct i40e_aqc_get_set_rss_key {
2182#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2183#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2184#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2185 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2186 __le16 vsi_id;
2187 u8 reserved[6];
2188 __le32 addr_high;
2189 __le32 addr_low;
2190};
2191
2192I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2193
2194struct i40e_aqc_get_set_rss_key_data {
2195 u8 standard_rss_key[0x28];
2196 u8 extended_hash_key[0xc];
2197};
2198
2199I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2200
2201struct i40e_aqc_get_set_rss_lut {
2202#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2203#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2204#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2205 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2206 __le16 vsi_id;
2207#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2208#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2209 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2210
2211#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2212#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2213 __le16 flags;
2214 u8 reserved[4];
2215 __le32 addr_high;
2216 __le32 addr_low;
2217};
2218
2219I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2220
d358aa9a
GR		 2221/* tunnel key structure 0x0B10 */
2222
90327e7d
GR		 2223struct i40e_aqc_tunnel_key_structure_A0 {
2224 __le16 key1_off;
2225 __le16 key1_len;
2226 __le16 key2_off;
2227 __le16 key2_len;
2228 __le16 flags;
2229#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2230/* response flags */
2231#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2232#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2233#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2234 u8 resreved[6];
2235};
2236
2237I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2238
d358aa9a
GR		 2239struct i40e_aqc_tunnel_key_structure {
2240 u8 key1_off;
2241 u8 key2_off;
2242 u8 key1_len; /* 0 to 15 */
2243 u8 key2_len; /* 0 to 15 */
2244 u8 flags;
8c570dcc 2245#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
d358aa9a 2246/* response flags */
8c570dcc
JK		 2247#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2248#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2249#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
d358aa9a
GR		 2250 u8 network_key_index;
2251#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2252#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2253#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2254#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2255 u8 reserved[10];
2256};
2257
2258I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2259
2260/* OEM mode commands (direct 0xFE0x) */
2261struct i40e_aqc_oem_param_change {
8c570dcc
JK		 2262 __le32 param_type;
2263#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2264#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2265#define I40E_AQ_OEM_PARAM_MAC 2
2266 __le32 param_value1;
35155fe6
SN		 2267 __le16 param_value2;
2268 u8 reserved[6];
d358aa9a
GR		 2269};
2270
2271I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2272
2273struct i40e_aqc_oem_state_change {
8c570dcc
JK		 2274 __le32 state;
2275#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2276#define I40E_AQ_OEM_STATE_LINK_UP 0x1
2277 u8 reserved[12];
d358aa9a
GR		 2278};
2279
2280I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2281
672415c5
SN		 2282/* Initialize OCSD (0xFE02, direct) */
2283struct i40e_aqc_opc_oem_ocsd_initialize {
2284 u8 type_status;
2285 u8 reserved1[3];
2286 __le32 ocsd_memory_block_addr_high;
2287 __le32 ocsd_memory_block_addr_low;
2288 __le32 requested_update_interval;
2289};
2290
2291I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2292
2293/* Initialize OCBB (0xFE03, direct) */
2294struct i40e_aqc_opc_oem_ocbb_initialize {
2295 u8 type_status;
2296 u8 reserved1[3];
2297 __le32 ocbb_memory_block_addr_high;
2298 __le32 ocbb_memory_block_addr_low;
2299 u8 reserved2[4];
2300};
2301
2302I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2303
d358aa9a
GR		 2304/* debug commands */
2305
2306/* get device id (0xFF00) uses the generic structure */
2307
2308/* set test more (0xFF01, internal) */
2309
2310struct i40e_acq_set_test_mode {
8c570dcc
JK		 2311 u8 mode;
2312#define I40E_AQ_TEST_PARTIAL 0
2313#define I40E_AQ_TEST_FULL 1
2314#define I40E_AQ_TEST_NVM 2
2315 u8 reserved[3];
2316 u8 command;
2317#define I40E_AQ_TEST_OPEN 0
2318#define I40E_AQ_TEST_CLOSE 1
2319#define I40E_AQ_TEST_INC 2
2320 u8 reserved2[3];
2321 __le32 address_high;
2322 __le32 address_low;
d358aa9a
GR		 2323};
2324
2325I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2326
2327/* Debug Read Register command (0xFF03)
2328 * Debug Write Register command (0xFF04)
2329 */
2330struct i40e_aqc_debug_reg_read_write {
2331 __le32 reserved;
2332 __le32 address;
2333 __le32 value_high;
2334 __le32 value_low;
2335};
2336
2337I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2338
2339/* Scatter/gather Reg Read (indirect 0xFF05)
2340 * Scatter/gather Reg Write (indirect 0xFF06)
2341 */
2342
2343/* i40e_aq_desc is used for the command */
2344struct i40e_aqc_debug_reg_sg_element_data {
2345 __le32 address;
2346 __le32 value;
2347};
2348
2349/* Debug Modify register (direct 0xFF07) */
2350struct i40e_aqc_debug_modify_reg {
2351 __le32 address;
2352 __le32 value;
2353 __le32 clear_mask;
2354 __le32 set_mask;
2355};
2356
2357I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2358
2359/* dump internal data (0xFF08, indirect) */
2360
2361#define I40E_AQ_CLUSTER_ID_AUX 0
2362#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2363#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2364#define I40E_AQ_CLUSTER_ID_HMC 3
2365#define I40E_AQ_CLUSTER_ID_MAC0 4
2366#define I40E_AQ_CLUSTER_ID_MAC1 5
2367#define I40E_AQ_CLUSTER_ID_MAC2 6
2368#define I40E_AQ_CLUSTER_ID_MAC3 7
2369#define I40E_AQ_CLUSTER_ID_DCB 8
2370#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2371#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2372#define I40E_AQ_CLUSTER_ID_ALTRAM 11
2373
2374struct i40e_aqc_debug_dump_internals {
8c570dcc
JK		 2375 u8 cluster_id;
2376 u8 table_id;
2377 __le16 data_size;
2378 __le32 idx;
2379 __le32 address_high;
2380 __le32 address_low;
d358aa9a
GR		 2381};
2382
2383I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2384
2385struct i40e_aqc_debug_modify_internals {
8c570dcc
JK		 2386 u8 cluster_id;
2387 u8 cluster_specific_params[7];
2388 __le32 address_high;
2389 __le32 address_low;
d358aa9a
GR		 2390};
2391
2392I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2393
2f175f55 2394#endif /* _I40E_ADMINQ_CMD_H_ */
Linux kernel - Deliverables
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