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i40e: clean event descriptor before use
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_adminq_cmd.h
CommitLineData
d358aa9a
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
b831607d 4 * Copyright(c) 2013 - 2014 Intel Corporation.
d358aa9a
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
d358aa9a
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_ADMINQ_CMD_H_
28#define _I40E_ADMINQ_CMD_H_
29
30/* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
8c570dcc 36#define I40E_FW_API_VERSION_MAJOR 0x0001
97b884fe 37#define I40E_FW_API_VERSION_MINOR 0x0005
d358aa9a
GR		 38
39struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61};
62
63/* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68/* command flags and offsets*/
8c570dcc
JK		 69#define I40E_AQ_FLAG_DD_SHIFT 0
70#define I40E_AQ_FLAG_CMP_SHIFT 1
71#define I40E_AQ_FLAG_ERR_SHIFT 2
72#define I40E_AQ_FLAG_VFE_SHIFT 3
73#define I40E_AQ_FLAG_LB_SHIFT 9
74#define I40E_AQ_FLAG_RD_SHIFT 10
75#define I40E_AQ_FLAG_VFC_SHIFT 11
76#define I40E_AQ_FLAG_BUF_SHIFT 12
77#define I40E_AQ_FLAG_SI_SHIFT 13
78#define I40E_AQ_FLAG_EI_SHIFT 14
79#define I40E_AQ_FLAG_FE_SHIFT 15
80
81#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
d358aa9a
GR		 92
93/* error codes */
94enum i40e_admin_queue_err {
8c570dcc
JK		 95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
d358aa9a
GR		 118};
119
120/* Admin Queue command opcodes */
121enum i40e_admin_queue_opc {
122 /* aq commands */
8c570dcc
JK		 123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
d358aa9a
GR		 127
128 /* resource ownership */
8c570dcc
JK		 129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
d358aa9a 131
8c570dcc
JK		 132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
d358aa9a 134
d358aa9a 135 /* LAA */
8c570dcc
JK		 136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
d358aa9a
GR		 138
139 /* PXE */
8c570dcc 140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
d358aa9a
GR		 141
142 /* internal switch commands */
8c570dcc
JK		 143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
fa5623a6 148 i40e_aqc_opc_set_switch_config = 0x0205,
8c570dcc
JK		 149
150 i40e_aqc_opc_add_vsi = 0x0210,
151 i40e_aqc_opc_update_vsi_parameters = 0x0211,
152 i40e_aqc_opc_get_vsi_parameters = 0x0212,
153
154 i40e_aqc_opc_add_pv = 0x0220,
155 i40e_aqc_opc_update_pv_parameters = 0x0221,
156 i40e_aqc_opc_get_pv_parameters = 0x0222,
157
158 i40e_aqc_opc_add_veb = 0x0230,
159 i40e_aqc_opc_update_veb_parameters = 0x0231,
160 i40e_aqc_opc_get_veb_parameters = 0x0232,
161
162 i40e_aqc_opc_delete_element = 0x0243,
163
164 i40e_aqc_opc_add_macvlan = 0x0250,
165 i40e_aqc_opc_remove_macvlan = 0x0251,
166 i40e_aqc_opc_add_vlan = 0x0252,
167 i40e_aqc_opc_remove_vlan = 0x0253,
168 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
169 i40e_aqc_opc_add_tag = 0x0255,
170 i40e_aqc_opc_remove_tag = 0x0256,
171 i40e_aqc_opc_add_multicast_etag = 0x0257,
172 i40e_aqc_opc_remove_multicast_etag = 0x0258,
173 i40e_aqc_opc_update_tag = 0x0259,
174 i40e_aqc_opc_add_control_packet_filter = 0x025A,
175 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
176 i40e_aqc_opc_add_cloud_filters = 0x025C,
177 i40e_aqc_opc_remove_cloud_filters = 0x025D,
178
179 i40e_aqc_opc_add_mirror_rule = 0x0260,
180 i40e_aqc_opc_delete_mirror_rule = 0x0261,
d358aa9a 181
d358aa9a 182 /* DCB commands */
8c570dcc
JK		 183 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
184 i40e_aqc_opc_dcb_updated = 0x0302,
d358aa9a
GR		 185
186 /* TX scheduler */
8c570dcc
JK		 187 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
188 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
189 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
190 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
191 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
192 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
193
194 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
195 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
196 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
197 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
198 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
199 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
200 i40e_aqc_opc_query_port_ets_config = 0x0419,
201 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
202 i40e_aqc_opc_suspend_port_tx = 0x041B,
203 i40e_aqc_opc_resume_port_tx = 0x041C,
204 i40e_aqc_opc_configure_partition_bw = 0x041D,
d358aa9a
GR		 205
206 /* hmc */
8c570dcc
JK		 207 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
208 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
d358aa9a
GR		 209
210 /* phy commands*/
8c570dcc
JK		 211 i40e_aqc_opc_get_phy_abilities = 0x0600,
212 i40e_aqc_opc_set_phy_config = 0x0601,
213 i40e_aqc_opc_set_mac_config = 0x0603,
214 i40e_aqc_opc_set_link_restart_an = 0x0605,
215 i40e_aqc_opc_get_link_status = 0x0607,
216 i40e_aqc_opc_set_phy_int_mask = 0x0613,
217 i40e_aqc_opc_get_local_advt_reg = 0x0614,
218 i40e_aqc_opc_set_local_advt_reg = 0x0615,
219 i40e_aqc_opc_get_partner_advt = 0x0616,
220 i40e_aqc_opc_set_lb_modes = 0x0618,
221 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
222 i40e_aqc_opc_set_phy_debug = 0x0622,
223 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
5394f02f 224 i40e_aqc_opc_run_phy_activity = 0x0626,
d358aa9a
GR		 225
226 /* NVM commands */
8c570dcc
JK		 227 i40e_aqc_opc_nvm_read = 0x0701,
228 i40e_aqc_opc_nvm_erase = 0x0702,
229 i40e_aqc_opc_nvm_update = 0x0703,
230 i40e_aqc_opc_nvm_config_read = 0x0704,
231 i40e_aqc_opc_nvm_config_write = 0x0705,
00ada50d 232 i40e_aqc_opc_oem_post_update = 0x0720,
6774faf9 233 i40e_aqc_opc_thermal_sensor = 0x0721,
d358aa9a
GR		 234
235 /* virtualization commands */
8c570dcc
JK		 236 i40e_aqc_opc_send_msg_to_pf = 0x0801,
237 i40e_aqc_opc_send_msg_to_vf = 0x0802,
238 i40e_aqc_opc_send_msg_to_peer = 0x0803,
d358aa9a
GR		 239
240 /* alternate structure */
8c570dcc
JK		 241 i40e_aqc_opc_alternate_write = 0x0900,
242 i40e_aqc_opc_alternate_write_indirect = 0x0901,
243 i40e_aqc_opc_alternate_read = 0x0902,
244 i40e_aqc_opc_alternate_read_indirect = 0x0903,
245 i40e_aqc_opc_alternate_write_done = 0x0904,
246 i40e_aqc_opc_alternate_set_mode = 0x0905,
247 i40e_aqc_opc_alternate_clear_port = 0x0906,
d358aa9a
GR		 248
249 /* LLDP commands */
8c570dcc
JK		 250 i40e_aqc_opc_lldp_get_mib = 0x0A00,
251 i40e_aqc_opc_lldp_update_mib = 0x0A01,
252 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
253 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
254 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
255 i40e_aqc_opc_lldp_stop = 0x0A05,
256 i40e_aqc_opc_lldp_start = 0x0A06,
d358aa9a
GR		 257
258 /* Tunnel commands */
8c570dcc
JK		 259 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
260 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
e50c8d6d
ASJ		 261 i40e_aqc_opc_set_rss_key = 0x0B02,
262 i40e_aqc_opc_set_rss_lut = 0x0B03,
263 i40e_aqc_opc_get_rss_key = 0x0B04,
264 i40e_aqc_opc_get_rss_lut = 0x0B05,
d358aa9a
GR		 265
266 /* Async Events */
8c570dcc 267 i40e_aqc_opc_event_lan_overflow = 0x1001,
d358aa9a
GR		 268
269 /* OEM commands */
8c570dcc
JK		 270 i40e_aqc_opc_oem_parameter_change = 0xFE00,
271 i40e_aqc_opc_oem_device_status_change = 0xFE01,
672415c5
SN		 272 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
273 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
d358aa9a
GR		 274
275 /* debug commands */
8c570dcc
JK		 276 i40e_aqc_opc_debug_read_reg = 0xFF03,
277 i40e_aqc_opc_debug_write_reg = 0xFF04,
278 i40e_aqc_opc_debug_modify_reg = 0xFF07,
279 i40e_aqc_opc_debug_dump_internals = 0xFF08,
d358aa9a
GR		 280};
281
282/* command structures and indirect data structures */
283
284/* Structure naming conventions:
285 * - no suffix for direct command descriptor structures
286 * - _data for indirect sent data
287 * - _resp for indirect return data (data which is both will use _data)
288 * - _completion for direct return data
289 * - _element_ for repeated elements (may also be _data or _resp)
290 *
291 * Command structures are expected to overlay the params.raw member of the basic
292 * descriptor, and as such cannot exceed 16 bytes in length.
293 */
294
295/* This macro is used to generate a compilation error if a structure
296 * is not exactly the correct length. It gives a divide by zero error if the
297 * structure is not of the correct size, otherwise it creates an enum that is
298 * never used.
299 */
300#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
301 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
302
303/* This macro is used extensively to ensure that command structures are 16
304 * bytes in length as they have to map to the raw array of that size.
305 */
8c570dcc 306#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
d358aa9a
GR		 307
308/* internal (0x00XX) commands */
309
310/* Get version (direct 0x0001) */
311struct i40e_aqc_get_version {
312 __le32 rom_ver;
313 __le32 fw_build;
314 __le16 fw_major;
315 __le16 fw_minor;
316 __le16 api_major;
317 __le16 api_minor;
318};
319
320I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
321
322/* Send driver version (indirect 0x0002) */
323struct i40e_aqc_driver_version {
8c570dcc
JK		 324 u8 driver_major_ver;
325 u8 driver_minor_ver;
326 u8 driver_build_ver;
327 u8 driver_subbuild_ver;
328 u8 reserved[4];
329 __le32 address_high;
330 __le32 address_low;
d358aa9a
GR		 331};
332
333I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
334
335/* Queue Shutdown (direct 0x0003) */
336struct i40e_aqc_queue_shutdown {
8c570dcc
JK		 337 __le32 driver_unloading;
338#define I40E_AQ_DRIVER_UNLOADING 0x1
339 u8 reserved[12];
d358aa9a
GR		 340};
341
342I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
343
f94234ee
SN		 344/* Set PF context (0x0004, direct) */
345struct i40e_aqc_set_pf_context {
346 u8 pf_id;
347 u8 reserved[15];
348};
349
350I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
351
d358aa9a
GR		 352/* Request resource ownership (direct 0x0008)
353 * Release resource ownership (direct 0x0009)
354 */
8c570dcc
JK		 355#define I40E_AQ_RESOURCE_NVM 1
356#define I40E_AQ_RESOURCE_SDP 2
357#define I40E_AQ_RESOURCE_ACCESS_READ 1
358#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
359#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
360#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
d358aa9a
GR		 361
362struct i40e_aqc_request_resource {
8c570dcc
JK		 363 __le16 resource_id;
364 __le16 access_type;
365 __le32 timeout;
366 __le32 resource_number;
367 u8 reserved[4];
d358aa9a
GR		 368};
369
370I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
371
372/* Get function capabilities (indirect 0x000A)
373 * Get device capabilities (indirect 0x000B)
374 */
375struct i40e_aqc_list_capabilites {
376 u8 command_flags;
8c570dcc 377#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
d358aa9a
GR		 378 u8 pf_index;
379 u8 reserved[2];
380 __le32 count;
381 __le32 addr_high;
382 __le32 addr_low;
383};
384
385I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
386
387struct i40e_aqc_list_capabilities_element_resp {
8c570dcc
JK		 388 __le16 id;
389 u8 major_rev;
390 u8 minor_rev;
391 __le32 number;
392 __le32 logical_id;
393 __le32 phys_id;
394 u8 reserved[16];
d358aa9a
GR		 395};
396
397/* list of caps */
398
8c570dcc
JK		 399#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
400#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
401#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
402#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
403#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
404#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
4ba40bce 405#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
8c570dcc
JK		 406#define I40E_AQ_CAP_ID_SRIOV 0x0012
407#define I40E_AQ_CAP_ID_VF 0x0013
408#define I40E_AQ_CAP_ID_VMDQ 0x0014
409#define I40E_AQ_CAP_ID_8021QBG 0x0015
410#define I40E_AQ_CAP_ID_8021QBR 0x0016
411#define I40E_AQ_CAP_ID_VSI 0x0017
412#define I40E_AQ_CAP_ID_DCB 0x0018
413#define I40E_AQ_CAP_ID_FCOE 0x0021
35155fe6 414#define I40E_AQ_CAP_ID_ISCSI 0x0022
8c570dcc
JK		 415#define I40E_AQ_CAP_ID_RSS 0x0040
416#define I40E_AQ_CAP_ID_RXQ 0x0041
417#define I40E_AQ_CAP_ID_TXQ 0x0042
418#define I40E_AQ_CAP_ID_MSIX 0x0043
419#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
420#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
421#define I40E_AQ_CAP_ID_1588 0x0046
422#define I40E_AQ_CAP_ID_IWARP 0x0051
423#define I40E_AQ_CAP_ID_LED 0x0061
424#define I40E_AQ_CAP_ID_SDP 0x0062
425#define I40E_AQ_CAP_ID_MDIO 0x0063
406e734a 426#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
8c570dcc
JK		 427#define I40E_AQ_CAP_ID_FLEX10 0x00F1
428#define I40E_AQ_CAP_ID_CEM 0x00F2
d358aa9a
GR		 429
430/* Set CPPM Configuration (direct 0x0103) */
431struct i40e_aqc_cppm_configuration {
8c570dcc
JK		 432 __le16 command_flags;
433#define I40E_AQ_CPPM_EN_LTRC 0x0800
434#define I40E_AQ_CPPM_EN_DMCTH 0x1000
435#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
436#define I40E_AQ_CPPM_EN_HPTC 0x4000
437#define I40E_AQ_CPPM_EN_DMARC 0x8000
438 __le16 ttlx;
439 __le32 dmacr;
440 __le16 dmcth;
441 u8 hptc;
442 u8 reserved;
443 __le32 pfltrc;
d358aa9a
GR		 444};
445
446I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
447
448/* Set ARP Proxy command / response (indirect 0x0104) */
449struct i40e_aqc_arp_proxy_data {
8c570dcc
JK		 450 __le16 command_flags;
451#define I40E_AQ_ARP_INIT_IPV4 0x0008
452#define I40E_AQ_ARP_UNSUP_CTL 0x0010
453#define I40E_AQ_ARP_ENA 0x0020
454#define I40E_AQ_ARP_ADD_IPV4 0x0040
455#define I40E_AQ_ARP_DEL_IPV4 0x0080
456 __le16 table_id;
457 __le32 pfpm_proxyfc;
458 __le32 ip_addr;
459 u8 mac_addr[6];
672415c5 460 u8 reserved[2];
d358aa9a
GR		 461};
462
8d5e33ad
SN		 463I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
464
d358aa9a
GR		 465/* Set NS Proxy Table Entry Command (indirect 0x0105) */
466struct i40e_aqc_ns_proxy_data {
8c570dcc
JK		 467 __le16 table_idx_mac_addr_0;
468 __le16 table_idx_mac_addr_1;
469 __le16 table_idx_ipv6_0;
470 __le16 table_idx_ipv6_1;
471 __le16 control;
472#define I40E_AQ_NS_PROXY_ADD_0 0x0100
473#define I40E_AQ_NS_PROXY_DEL_0 0x0200
474#define I40E_AQ_NS_PROXY_ADD_1 0x0400
475#define I40E_AQ_NS_PROXY_DEL_1 0x0800
476#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
477#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
478#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
479#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
480#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
481#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
482#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
483 u8 mac_addr_0[6];
484 u8 mac_addr_1[6];
485 u8 local_mac_addr[6];
486 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
487 u8 ipv6_addr_1[16];
d358aa9a
GR		 488};
489
8d5e33ad
SN		 490I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
491
d358aa9a
GR		 492/* Manage LAA Command (0x0106) - obsolete */
493struct i40e_aqc_mng_laa {
494 __le16 command_flags;
8c570dcc
JK		 495#define I40E_AQ_LAA_FLAG_WR 0x8000
496 u8 reserved[2];
497 __le32 sal;
498 __le16 sah;
499 u8 reserved2[6];
d358aa9a
GR		 500};
501
8d5e33ad
SN		 502I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
503
d358aa9a
GR		 504/* Manage MAC Address Read Command (indirect 0x0107) */
505struct i40e_aqc_mac_address_read {
506 __le16 command_flags;
8c570dcc
JK		 507#define I40E_AQC_LAN_ADDR_VALID 0x10
508#define I40E_AQC_SAN_ADDR_VALID 0x20
509#define I40E_AQC_PORT_ADDR_VALID 0x40
510#define I40E_AQC_WOL_ADDR_VALID 0x80
cb2f65bc
GR		 511#define I40E_AQC_MC_MAG_EN_VALID 0x100
512#define I40E_AQC_ADDR_VALID_MASK 0x1F0
8c570dcc
JK		 513 u8 reserved[6];
514 __le32 addr_high;
515 __le32 addr_low;
d358aa9a
GR		 516};
517
518I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
519
520struct i40e_aqc_mac_address_read_data {
521 u8 pf_lan_mac[6];
522 u8 pf_san_mac[6];
523 u8 port_mac[6];
524 u8 pf_wol_mac[6];
525};
526
527I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
528
529/* Manage MAC Address Write Command (0x0108) */
530struct i40e_aqc_mac_address_write {
8c570dcc
JK		 531 __le16 command_flags;
532#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
533#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
534#define I40E_AQC_WRITE_TYPE_PORT 0x8000
cb2f65bc
GR		 535#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
536#define I40E_AQC_WRITE_TYPE_MASK 0xC000
537
8c570dcc
JK		 538 __le16 mac_sah;
539 __le32 mac_sal;
540 u8 reserved[8];
d358aa9a
GR		 541};
542
543I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
544
545/* PXE commands (0x011x) */
546
547/* Clear PXE Command and response (direct 0x0110) */
548struct i40e_aqc_clear_pxe {
549 u8 rx_cnt;
550 u8 reserved[15];
551};
552
553I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
554
555/* Switch configuration commands (0x02xx) */
556
557/* Used by many indirect commands that only pass an seid and a buffer in the
558 * command
559 */
560struct i40e_aqc_switch_seid {
8c570dcc
JK		 561 __le16 seid;
562 u8 reserved[6];
563 __le32 addr_high;
564 __le32 addr_low;
d358aa9a
GR		 565};
566
567I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
568
569/* Get Switch Configuration command (indirect 0x0200)
570 * uses i40e_aqc_switch_seid for the descriptor
571 */
572struct i40e_aqc_get_switch_config_header_resp {
8c570dcc
JK		 573 __le16 num_reported;
574 __le16 num_total;
575 u8 reserved[12];
d358aa9a
GR		 576};
577
8d5e33ad
SN		 578I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
579
d358aa9a 580struct i40e_aqc_switch_config_element_resp {
8c570dcc
JK		 581 u8 element_type;
582#define I40E_AQ_SW_ELEM_TYPE_MAC 1
583#define I40E_AQ_SW_ELEM_TYPE_PF 2
584#define I40E_AQ_SW_ELEM_TYPE_VF 3
585#define I40E_AQ_SW_ELEM_TYPE_EMP 4
586#define I40E_AQ_SW_ELEM_TYPE_BMC 5
587#define I40E_AQ_SW_ELEM_TYPE_PV 16
588#define I40E_AQ_SW_ELEM_TYPE_VEB 17
589#define I40E_AQ_SW_ELEM_TYPE_PA 18
590#define I40E_AQ_SW_ELEM_TYPE_VSI 19
591 u8 revision;
592#define I40E_AQ_SW_ELEM_REV_1 1
593 __le16 seid;
594 __le16 uplink_seid;
595 __le16 downlink_seid;
596 u8 reserved[3];
597 u8 connection_type;
598#define I40E_AQ_CONN_TYPE_REGULAR 0x1
599#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
600#define I40E_AQ_CONN_TYPE_CASCADED 0x3
601 __le16 scheduler_id;
602 __le16 element_info;
d358aa9a
GR		 603};
604
8d5e33ad
SN		 605I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
606
d358aa9a
GR		 607/* Get Switch Configuration (indirect 0x0200)
608 * an array of elements are returned in the response buffer
609 * the first in the array is the header, remainder are elements
610 */
611struct i40e_aqc_get_switch_config_resp {
8c570dcc
JK		 612 struct i40e_aqc_get_switch_config_header_resp header;
613 struct i40e_aqc_switch_config_element_resp element[1];
d358aa9a
GR		 614};
615
8d5e33ad
SN		 616I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
617
d358aa9a
GR		 618/* Add Statistics (direct 0x0201)
619 * Remove Statistics (direct 0x0202)
620 */
621struct i40e_aqc_add_remove_statistics {
8c570dcc
JK		 622 __le16 seid;
623 __le16 vlan;
624 __le16 stat_index;
625 u8 reserved[10];
d358aa9a
GR		 626};
627
628I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
629
630/* Set Port Parameters command (direct 0x0203) */
631struct i40e_aqc_set_port_parameters {
8c570dcc
JK		 632 __le16 command_flags;
633#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
634#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
635#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
636 __le16 bad_frame_vsi;
637 __le16 default_seid; /* reserved for command */
638 u8 reserved[10];
d358aa9a
GR		 639};
640
641I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
642
643/* Get Switch Resource Allocation (indirect 0x0204) */
644struct i40e_aqc_get_switch_resource_alloc {
8c570dcc
JK		 645 u8 num_entries; /* reserved for command */
646 u8 reserved[7];
647 __le32 addr_high;
648 __le32 addr_low;
d358aa9a
GR		 649};
650
651I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
652
653/* expect an array of these structs in the response buffer */
654struct i40e_aqc_switch_resource_alloc_element_resp {
8c570dcc
JK		 655 u8 resource_type;
656#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
657#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
658#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
659#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
660#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
661#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
662#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
663#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
664#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
665#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
666#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
667#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
668#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
669#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
670#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
671#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
672#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
673#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
674#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
675 u8 reserved1;
676 __le16 guaranteed;
677 __le16 total;
678 __le16 used;
679 __le16 total_unalloced;
680 u8 reserved2[6];
d358aa9a
GR		 681};
682
8d5e33ad
SN		 683I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
684
fa5623a6
SN		 685/* Set Switch Configuration (direct 0x0205) */
686struct i40e_aqc_set_switch_config {
687 __le16 flags;
688#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
689#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
690 __le16 valid_flags;
691 u8 reserved[12];
692};
693
694I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
695
d358aa9a
GR		 696/* Add VSI (indirect 0x0210)
697 * this indirect command uses struct i40e_aqc_vsi_properties_data
698 * as the indirect buffer (128 bytes)
699 *
700 * Update VSI (indirect 0x211)
701 * uses the same data structure as Add VSI
702 *
703 * Get VSI (indirect 0x0212)
704 * uses the same completion and data structure as Add VSI
705 */
706struct i40e_aqc_add_get_update_vsi {
8c570dcc
JK		 707 __le16 uplink_seid;
708 u8 connection_type;
709#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
710#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
711#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
712 u8 reserved1;
713 u8 vf_id;
714 u8 reserved2;
715 __le16 vsi_flags;
716#define I40E_AQ_VSI_TYPE_SHIFT 0x0
717#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
718#define I40E_AQ_VSI_TYPE_VF 0x0
719#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
720#define I40E_AQ_VSI_TYPE_PF 0x2
721#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
722#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
723 __le32 addr_high;
724 __le32 addr_low;
d358aa9a
GR		 725};
726
727I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
728
729struct i40e_aqc_add_get_update_vsi_completion {
730 __le16 seid;
731 __le16 vsi_number;
732 __le16 vsi_used;
733 __le16 vsi_free;
734 __le32 addr_high;
735 __le32 addr_low;
736};
737
738I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
739
740struct i40e_aqc_vsi_properties_data {
741 /* first 96 byte are written by SW */
8c570dcc
JK		 742 __le16 valid_sections;
743#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
744#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
745#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
746#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
747#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
748#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
749#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
750#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
751#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
752#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
d358aa9a 753 /* switch section */
8c570dcc
JK		 754 __le16 switch_id; /* 12bit id combined with flags below */
755#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
756#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
757#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
758#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
759#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
760 u8 sw_reserved[2];
d358aa9a 761 /* security section */
8c570dcc
JK		 762 u8 sec_flags;
763#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
764#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
765#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
766 u8 sec_reserved;
d358aa9a 767 /* VLAN section */
8c570dcc
JK		 768 __le16 pvid; /* VLANS include priority bits */
769 __le16 fcoe_pvid;
770 u8 port_vlan_flags;
771#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
772#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
773 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
774#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
775#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
776#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
777#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
778#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
779#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
780 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
781#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
782#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
783#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
784#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
785 u8 pvlan_reserved[3];
d358aa9a 786 /* ingress egress up sections */
8c570dcc
JK		 787 __le32 ingress_table; /* bitmap, 3 bits per up */
788#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
789#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
790 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
791#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
792#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
793 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
794#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
795#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
796 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
797#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
798#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
799 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
800#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
801#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
802 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
803#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
804#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
805 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
806#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
807#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
808 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
809#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
810#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
811 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
812 __le32 egress_table; /* same defines as for ingress table */
d358aa9a 813 /* cascaded PV section */
8c570dcc
JK		 814 __le16 cas_pv_tag;
815 u8 cas_pv_flags;
816#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
817#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
818 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
819#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
820#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
821#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
822#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
823#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
824#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
825 u8 cas_pv_reserved;
d358aa9a 826 /* queue mapping section */
8c570dcc
JK		 827 __le16 mapping_flags;
828#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
829#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
830 __le16 queue_mapping[16];
831#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
832#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
833 __le16 tc_mapping[8];
834#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
835#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
836 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
837#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
838#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
839 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
d358aa9a 840 /* queueing option section */
8c570dcc 841 u8 queueing_opt_flags;
e50c8d6d
ASJ		 842#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
843#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
8c570dcc
JK		 844#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
845#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
e50c8d6d
ASJ		 846#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
847#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
8c570dcc 848 u8 queueing_opt_reserved[3];
d358aa9a 849 /* scheduler section */
8c570dcc
JK		 850 u8 up_enable_bits;
851 u8 sched_reserved;
d358aa9a 852 /* outer up section */
8c570dcc
JK		 853 __le32 outer_up_table; /* same structure and defines as ingress tbl */
854 u8 cmd_reserved[8];
d358aa9a 855 /* last 32 bytes are written by FW */
8c570dcc 856 __le16 qs_handle[8];
d358aa9a 857#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
8c570dcc
JK		 858 __le16 stat_counter_idx;
859 __le16 sched_id;
860 u8 resp_reserved[12];
d358aa9a
GR		 861};
862
863I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
864
865/* Add Port Virtualizer (direct 0x0220)
866 * also used for update PV (direct 0x0221) but only flags are used
867 * (IS_CTRL_PORT only works on add PV)
868 */
869struct i40e_aqc_add_update_pv {
8c570dcc
JK		 870 __le16 command_flags;
871#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
872#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
873#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
874#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
875 __le16 uplink_seid;
876 __le16 connected_seid;
877 u8 reserved[10];
d358aa9a
GR		 878};
879
880I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
881
882struct i40e_aqc_add_update_pv_completion {
883 /* reserved for update; for add also encodes error if rc == ENOSPC */
8c570dcc
JK		 884 __le16 pv_seid;
885#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
886#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
887#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
888#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
889 u8 reserved[14];
d358aa9a
GR		 890};
891
892I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
893
894/* Get PV Params (direct 0x0222)
895 * uses i40e_aqc_switch_seid for the descriptor
896 */
897
898struct i40e_aqc_get_pv_params_completion {
8c570dcc
JK		 899 __le16 seid;
900 __le16 default_stag;
901 __le16 pv_flags; /* same flags as add_pv */
902#define I40E_AQC_GET_PV_PV_TYPE 0x1
903#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
904#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
905 u8 reserved[8];
906 __le16 default_port_seid;
d358aa9a
GR		 907};
908
909I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
910
911/* Add VEB (direct 0x0230) */
912struct i40e_aqc_add_veb {
8c570dcc
JK		 913 __le16 uplink_seid;
914 __le16 downlink_seid;
915 __le16 veb_flags;
916#define I40E_AQC_ADD_VEB_FLOATING 0x1
917#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
918#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
d358aa9a 919 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
8c570dcc
JK		 920#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
921#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
fa5623a6
SN		 922#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
923#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
8c570dcc
JK		 924 u8 enable_tcs;
925 u8 reserved[9];
d358aa9a
GR		 926};
927
928I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
929
930struct i40e_aqc_add_veb_completion {
8c570dcc
JK		 931 u8 reserved[6];
932 __le16 switch_seid;
d358aa9a 933 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
8c570dcc
JK		 934 __le16 veb_seid;
935#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
936#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
937#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
938#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
939 __le16 statistic_index;
940 __le16 vebs_used;
941 __le16 vebs_free;
d358aa9a
GR		 942};
943
944I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
945
946/* Get VEB Parameters (direct 0x0232)
947 * uses i40e_aqc_switch_seid for the descriptor
948 */
949struct i40e_aqc_get_veb_parameters_completion {
8c570dcc
JK		 950 __le16 seid;
951 __le16 switch_id;
952 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
953 __le16 statistic_index;
954 __le16 vebs_used;
955 __le16 vebs_free;
956 u8 reserved[4];
d358aa9a
GR		 957};
958
959I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
960
961/* Delete Element (direct 0x0243)
962 * uses the generic i40e_aqc_switch_seid
963 */
964
965/* Add MAC-VLAN (indirect 0x0250) */
966
967/* used for the command for most vlan commands */
968struct i40e_aqc_macvlan {
8c570dcc
JK		 969 __le16 num_addresses;
970 __le16 seid[3];
971#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
972#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 973 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 974#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
975 __le32 addr_high;
976 __le32 addr_low;
d358aa9a
GR		 977};
978
979I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
980
981/* indirect data for command and response */
982struct i40e_aqc_add_macvlan_element_data {
8c570dcc
JK		 983 u8 mac_addr[6];
984 __le16 vlan_tag;
985 __le16 flags;
986#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
987#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
988#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
989#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
90680779 990#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
8c570dcc
JK		 991 __le16 queue_number;
992#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
993#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
d358aa9a
GR		 994 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
995 /* response section */
8c570dcc
JK		 996 u8 match_method;
997#define I40E_AQC_MM_PERFECT_MATCH 0x01
998#define I40E_AQC_MM_HASH_MATCH 0x02
999#define I40E_AQC_MM_ERR_NO_RES 0xFF
1000 u8 reserved1[3];
d358aa9a
GR		 1001};
1002
1003struct i40e_aqc_add_remove_macvlan_completion {
1004 __le16 perfect_mac_used;
1005 __le16 perfect_mac_free;
1006 __le16 unicast_hash_free;
1007 __le16 multicast_hash_free;
1008 __le32 addr_high;
1009 __le32 addr_low;
1010};
1011
1012I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1013
1014/* Remove MAC-VLAN (indirect 0x0251)
1015 * uses i40e_aqc_macvlan for the descriptor
1016 * data points to an array of num_addresses of elements
1017 */
1018
1019struct i40e_aqc_remove_macvlan_element_data {
8c570dcc
JK		 1020 u8 mac_addr[6];
1021 __le16 vlan_tag;
1022 u8 flags;
1023#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1024#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1025#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1026#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1027 u8 reserved[3];
d358aa9a 1028 /* reply section */
8c570dcc
JK		 1029 u8 error_code;
1030#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1031#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1032 u8 reply_reserved[3];
d358aa9a
GR		 1033};
1034
1035/* Add VLAN (indirect 0x0252)
1036 * Remove VLAN (indirect 0x0253)
1037 * use the generic i40e_aqc_macvlan for the command
1038 */
1039struct i40e_aqc_add_remove_vlan_element_data {
8c570dcc
JK		 1040 __le16 vlan_tag;
1041 u8 vlan_flags;
d358aa9a 1042/* flags for add VLAN */
8c570dcc
JK		 1043#define I40E_AQC_ADD_VLAN_LOCAL 0x1
1044#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1045#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1046#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1047#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1048#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1049#define I40E_AQC_VLAN_PTYPE_SHIFT 3
1050#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1051#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1052#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1053#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1054#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
d358aa9a 1055/* flags for remove VLAN */
8c570dcc
JK		 1056#define I40E_AQC_REMOVE_VLAN_ALL 0x1
1057 u8 reserved;
1058 u8 result;
d358aa9a 1059/* flags for add VLAN */
8c570dcc
JK		 1060#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1061#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1062#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
d358aa9a 1063/* flags for remove VLAN */
8c570dcc
JK		 1064#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1065#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1066 u8 reserved1[3];
d358aa9a
GR		 1067};
1068
1069struct i40e_aqc_add_remove_vlan_completion {
8c570dcc
JK		 1070 u8 reserved[4];
1071 __le16 vlans_used;
1072 __le16 vlans_free;
1073 __le32 addr_high;
1074 __le32 addr_low;
d358aa9a
GR		 1075};
1076
1077/* Set VSI Promiscuous Modes (direct 0x0254) */
1078struct i40e_aqc_set_vsi_promiscuous_modes {
8c570dcc
JK		 1079 __le16 promiscuous_flags;
1080 __le16 valid_flags;
d358aa9a 1081/* flags used for both fields above */
8c570dcc
JK		 1082#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1083#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1084#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1085#define I40E_AQC_SET_VSI_DEFAULT 0x08
1086#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1087 __le16 seid;
1088#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1089 __le16 vlan_tag;
cb2f65bc 1090#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
8c570dcc
JK		 1091#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1092 u8 reserved[8];
d358aa9a
GR		 1093};
1094
1095I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1096
1097/* Add S/E-tag command (direct 0x0255)
1098 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1099 */
1100struct i40e_aqc_add_tag {
8c570dcc
JK		 1101 __le16 flags;
1102#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1103 __le16 seid;
1104#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1105#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1106 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1107 __le16 tag;
1108 __le16 queue_number;
1109 u8 reserved[8];
d358aa9a
GR		 1110};
1111
1112I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1113
1114struct i40e_aqc_add_remove_tag_completion {
8c570dcc
JK		 1115 u8 reserved[12];
1116 __le16 tags_used;
1117 __le16 tags_free;
d358aa9a
GR		 1118};
1119
1120I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1121
1122/* Remove S/E-tag command (direct 0x0256)
1123 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1124 */
1125struct i40e_aqc_remove_tag {
8c570dcc
JK		 1126 __le16 seid;
1127#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1128#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1129 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1130 __le16 tag;
1131 u8 reserved[12];
d358aa9a
GR		 1132};
1133
8d5e33ad
SN		 1134I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1135
d358aa9a
GR		 1136/* Add multicast E-Tag (direct 0x0257)
1137 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1138 * and no external data
1139 */
1140struct i40e_aqc_add_remove_mcast_etag {
8c570dcc
JK		 1141 __le16 pv_seid;
1142 __le16 etag;
1143 u8 num_unicast_etags;
1144 u8 reserved[3];
1145 __le32 addr_high; /* address of array of 2-byte s-tags */
1146 __le32 addr_low;
d358aa9a
GR		 1147};
1148
1149I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1150
1151struct i40e_aqc_add_remove_mcast_etag_completion {
8c570dcc
JK		 1152 u8 reserved[4];
1153 __le16 mcast_etags_used;
1154 __le16 mcast_etags_free;
1155 __le32 addr_high;
1156 __le32 addr_low;
d358aa9a
GR		 1157
1158};
1159
1160I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1161
1162/* Update S/E-Tag (direct 0x0259) */
1163struct i40e_aqc_update_tag {
8c570dcc
JK		 1164 __le16 seid;
1165#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1166#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1167 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1168 __le16 old_tag;
1169 __le16 new_tag;
1170 u8 reserved[10];
d358aa9a
GR		 1171};
1172
1173I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1174
1175struct i40e_aqc_update_tag_completion {
8c570dcc
JK		 1176 u8 reserved[12];
1177 __le16 tags_used;
1178 __le16 tags_free;
d358aa9a
GR		 1179};
1180
1181I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1182
1183/* Add Control Packet filter (direct 0x025A)
1184 * Remove Control Packet filter (direct 0x025B)
1185 * uses the i40e_aqc_add_oveb_cloud,
1186 * and the generic direct completion structure
1187 */
1188struct i40e_aqc_add_remove_control_packet_filter {
8c570dcc
JK		 1189 u8 mac[6];
1190 __le16 etype;
1191 __le16 flags;
1192#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1193#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1194#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1195#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1196#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1197 __le16 seid;
1198#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1199#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1200 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1201 __le16 queue;
1202 u8 reserved[2];
d358aa9a
GR		 1203};
1204
1205I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1206
1207struct i40e_aqc_add_remove_control_packet_filter_completion {
8c570dcc
JK		 1208 __le16 mac_etype_used;
1209 __le16 etype_used;
1210 __le16 mac_etype_free;
1211 __le16 etype_free;
1212 u8 reserved[8];
d358aa9a
GR		 1213};
1214
1215I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1216
1217/* Add Cloud filters (indirect 0x025C)
1218 * Remove Cloud filters (indirect 0x025D)
1219 * uses the i40e_aqc_add_remove_cloud_filters,
1220 * and the generic indirect completion structure
1221 */
1222struct i40e_aqc_add_remove_cloud_filters {
8c570dcc
JK		 1223 u8 num_filters;
1224 u8 reserved;
1225 __le16 seid;
1226#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1227#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1228 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1229 u8 reserved2[4];
1230 __le32 addr_high;
1231 __le32 addr_low;
d358aa9a
GR		 1232};
1233
1234I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1235
1236struct i40e_aqc_add_remove_cloud_filters_element_data {
8c570dcc
JK		 1237 u8 outer_mac[6];
1238 u8 inner_mac[6];
1239 __le16 inner_vlan;
d358aa9a
GR		 1240 union {
1241 struct {
1242 u8 reserved[12];
1243 u8 data[4];
1244 } v4;
1245 struct {
1246 u8 data[16];
1247 } v6;
1248 } ipaddr;
8c570dcc
JK		 1249 __le16 flags;
1250#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
35155fe6 1251#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
d358aa9a
GR		 1252 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1253/* 0x0000 reserved */
8c570dcc 1254#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
d358aa9a 1255/* 0x0002 reserved */
8c570dcc
JK		 1256#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1257#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
d358aa9a 1258/* 0x0005 reserved */
8c570dcc 1259#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
d358aa9a
GR		 1260/* 0x0007 reserved */
1261/* 0x0008 reserved */
8c570dcc
JK		 1262#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1263#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1264#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1265#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1266
1267#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1268#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1269#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1270#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1271#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1272
1273#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1274#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
59264253 1275#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
8c570dcc 1276#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
59264253 1277#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
8c570dcc 1278#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
2fcc1a40
SN		 1279#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1280#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
8c570dcc 1281
90680779
SN		 1282#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1283#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1284#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1285
8c570dcc
JK		 1286 __le32 tenant_id;
1287 u8 reserved[4];
1288 __le16 queue_number;
1289#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
35155fe6 1290#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
8c570dcc
JK		 1291 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1292 u8 reserved2[14];
d358aa9a 1293 /* response section */
8c570dcc
JK		 1294 u8 allocation_result;
1295#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1296#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1297 u8 response_reserved[7];
d358aa9a
GR		 1298};
1299
1300struct i40e_aqc_remove_cloud_filters_completion {
1301 __le16 perfect_ovlan_used;
1302 __le16 perfect_ovlan_free;
1303 __le16 vlan_used;
1304 __le16 vlan_free;
1305 __le32 addr_high;
1306 __le32 addr_low;
1307};
1308
1309I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1310
1311/* Add Mirror Rule (indirect or direct 0x0260)
1312 * Delete Mirror Rule (indirect or direct 0x0261)
1313 * note: some rule types (4,5) do not use an external buffer.
1314 * take care to set the flags correctly.
1315 */
1316struct i40e_aqc_add_delete_mirror_rule {
1317 __le16 seid;
1318 __le16 rule_type;
8c570dcc
JK		 1319#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1320#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
d358aa9a 1321 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
8c570dcc
JK		 1322#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1323#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1324#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1325#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1326#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
d358aa9a
GR		 1327 __le16 num_entries;
1328 __le16 destination; /* VSI for add, rule id for delete */
1329 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1330 __le32 addr_low;
1331};
1332
1333I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1334
1335struct i40e_aqc_add_delete_mirror_rule_completion {
8c570dcc
JK		 1336 u8 reserved[2];
1337 __le16 rule_id; /* only used on add */
1338 __le16 mirror_rules_used;
1339 __le16 mirror_rules_free;
1340 __le32 addr_high;
1341 __le32 addr_low;
d358aa9a
GR		 1342};
1343
1344I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1345
d358aa9a
GR		 1346/* DCB 0x03xx*/
1347
1348/* PFC Ignore (direct 0x0301)
1349 * the command and response use the same descriptor structure
1350 */
1351struct i40e_aqc_pfc_ignore {
8c570dcc
JK		 1352 u8 tc_bitmap;
1353 u8 command_flags; /* unused on response */
1354#define I40E_AQC_PFC_IGNORE_SET 0x80
1355#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1356 u8 reserved[14];
d358aa9a
GR		 1357};
1358
1359I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1360
1361/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1362 * with no parameters
1363 */
1364
1365/* TX scheduler 0x04xx */
1366
1367/* Almost all the indirect commands use
1368 * this generic struct to pass the SEID in param0
1369 */
1370struct i40e_aqc_tx_sched_ind {
8c570dcc
JK		 1371 __le16 vsi_seid;
1372 u8 reserved[6];
1373 __le32 addr_high;
1374 __le32 addr_low;
d358aa9a
GR		 1375};
1376
1377I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1378
1379/* Several commands respond with a set of queue set handles */
1380struct i40e_aqc_qs_handles_resp {
1381 __le16 qs_handles[8];
1382};
1383
1384/* Configure VSI BW limits (direct 0x0400) */
1385struct i40e_aqc_configure_vsi_bw_limit {
8c570dcc
JK		 1386 __le16 vsi_seid;
1387 u8 reserved[2];
1388 __le16 credit;
1389 u8 reserved1[2];
1390 u8 max_credit; /* 0-3, limit = 2^max */
1391 u8 reserved2[7];
d358aa9a
GR		 1392};
1393
1394I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1395
1396/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1397 * responds with i40e_aqc_qs_handles_resp
1398 */
1399struct i40e_aqc_configure_vsi_ets_sla_bw_data {
8c570dcc
JK		 1400 u8 tc_valid_bits;
1401 u8 reserved[15];
1402 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
d358aa9a
GR		 1403
1404 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc
JK		 1405 __le16 tc_bw_max[2];
1406 u8 reserved1[28];
d358aa9a
GR		 1407};
1408
8d5e33ad
SN		 1409I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1410
d358aa9a
GR		 1411/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1412 * responds with i40e_aqc_qs_handles_resp
1413 */
1414struct i40e_aqc_configure_vsi_tc_bw_data {
8c570dcc
JK		 1415 u8 tc_valid_bits;
1416 u8 reserved[3];
1417 u8 tc_bw_credits[8];
1418 u8 reserved1[4];
1419 __le16 qs_handles[8];
d358aa9a
GR		 1420};
1421
8d5e33ad
SN		 1422I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1423
d358aa9a
GR		 1424/* Query vsi bw configuration (indirect 0x0408) */
1425struct i40e_aqc_query_vsi_bw_config_resp {
8c570dcc
JK		 1426 u8 tc_valid_bits;
1427 u8 tc_suspended_bits;
1428 u8 reserved[14];
1429 __le16 qs_handles[8];
1430 u8 reserved1[4];
1431 __le16 port_bw_limit;
1432 u8 reserved2[2];
1433 u8 max_bw; /* 0-3, limit = 2^max */
1434 u8 reserved3[23];
d358aa9a
GR		 1435};
1436
8d5e33ad
SN		 1437I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1438
d358aa9a
GR		 1439/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1440struct i40e_aqc_query_vsi_ets_sla_config_resp {
8c570dcc
JK		 1441 u8 tc_valid_bits;
1442 u8 reserved[3];
1443 u8 share_credits[8];
1444 __le16 credits[8];
d358aa9a
GR		 1445
1446 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc 1447 __le16 tc_bw_max[2];
d358aa9a
GR		 1448};
1449
8d5e33ad
SN		 1450I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1451
d358aa9a
GR		 1452/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1453struct i40e_aqc_configure_switching_comp_bw_limit {
8c570dcc
JK		 1454 __le16 seid;
1455 u8 reserved[2];
1456 __le16 credit;
1457 u8 reserved1[2];
1458 u8 max_bw; /* 0-3, limit = 2^max */
1459 u8 reserved2[7];
d358aa9a
GR		 1460};
1461
1462I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1463
1464/* Enable Physical Port ETS (indirect 0x0413)
1465 * Modify Physical Port ETS (indirect 0x0414)
1466 * Disable Physical Port ETS (indirect 0x0415)
1467 */
1468struct i40e_aqc_configure_switching_comp_ets_data {
8c570dcc
JK		 1469 u8 reserved[4];
1470 u8 tc_valid_bits;
1471 u8 seepage;
1472#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1473 u8 tc_strict_priority_flags;
1474 u8 reserved1[17];
1475 u8 tc_bw_share_credits[8];
1476 u8 reserved2[96];
d358aa9a
GR		 1477};
1478
8d5e33ad
SN		 1479I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1480
d358aa9a
GR		 1481/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1482struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
8c570dcc
JK		 1483 u8 tc_valid_bits;
1484 u8 reserved[15];
1485 __le16 tc_bw_credit[8];
d358aa9a
GR		 1486
1487 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc
JK		 1488 __le16 tc_bw_max[2];
1489 u8 reserved1[28];
d358aa9a
GR		 1490};
1491
8d5e33ad
SN		 1492I40E_CHECK_STRUCT_LEN(0x40,
1493 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1494
d358aa9a
GR		 1495/* Configure Switching Component Bandwidth Allocation per Tc
1496 * (indirect 0x0417)
1497 */
1498struct i40e_aqc_configure_switching_comp_bw_config_data {
8c570dcc
JK		 1499 u8 tc_valid_bits;
1500 u8 reserved[2];
1501 u8 absolute_credits; /* bool */
1502 u8 tc_bw_share_credits[8];
1503 u8 reserved1[20];
d358aa9a
GR		 1504};
1505
8d5e33ad
SN		 1506I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1507
d358aa9a
GR		 1508/* Query Switching Component Configuration (indirect 0x0418) */
1509struct i40e_aqc_query_switching_comp_ets_config_resp {
8c570dcc
JK		 1510 u8 tc_valid_bits;
1511 u8 reserved[35];
1512 __le16 port_bw_limit;
1513 u8 reserved1[2];
1514 u8 tc_bw_max; /* 0-3, limit = 2^max */
1515 u8 reserved2[23];
d358aa9a
GR		 1516};
1517
8d5e33ad
SN		 1518I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1519
d358aa9a
GR		 1520/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1521struct i40e_aqc_query_port_ets_config_resp {
8c570dcc
JK		 1522 u8 reserved[4];
1523 u8 tc_valid_bits;
1524 u8 reserved1;
1525 u8 tc_strict_priority_bits;
1526 u8 reserved2;
1527 u8 tc_bw_share_credits[8];
1528 __le16 tc_bw_limits[8];
d358aa9a
GR		 1529
1530 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
8c570dcc
JK		 1531 __le16 tc_bw_max[2];
1532 u8 reserved3[32];
d358aa9a
GR		 1533};
1534
8d5e33ad
SN		 1535I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1536
d358aa9a
GR		 1537/* Query Switching Component Bandwidth Allocation per Traffic Type
1538 * (indirect 0x041A)
1539 */
1540struct i40e_aqc_query_switching_comp_bw_config_resp {
8c570dcc
JK		 1541 u8 tc_valid_bits;
1542 u8 reserved[2];
1543 u8 absolute_credits_enable; /* bool */
1544 u8 tc_bw_share_credits[8];
1545 __le16 tc_bw_limits[8];
d358aa9a
GR		 1546
1547 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc 1548 __le16 tc_bw_max[2];
d358aa9a
GR		 1549};
1550
8d5e33ad
SN		 1551I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1552
d358aa9a
GR		 1553/* Suspend/resume port TX traffic
1554 * (direct 0x041B and 0x041C) uses the generic SEID struct
1555 */
1556
befc229c
SN		 1557/* Configure partition BW
1558 * (indirect 0x041D)
1559 */
1560struct i40e_aqc_configure_partition_bw_data {
8c570dcc
JK		 1561 __le16 pf_valid_bits;
1562 u8 min_bw[16]; /* guaranteed bandwidth */
1563 u8 max_bw[16]; /* bandwidth limit */
befc229c
SN		 1564};
1565
8d5e33ad
SN		 1566I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1567
d358aa9a
GR		 1568/* Get and set the active HMC resource profile and status.
1569 * (direct 0x0500) and (direct 0x0501)
1570 */
1571struct i40e_aq_get_set_hmc_resource_profile {
8c570dcc
JK		 1572 u8 pm_profile;
1573 u8 pe_vf_enabled;
1574 u8 reserved[14];
d358aa9a
GR		 1575};
1576
1577I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1578
1579enum i40e_aq_hmc_profile {
1580 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
8c570dcc
JK		 1581 I40E_HMC_PROFILE_DEFAULT = 1,
1582 I40E_HMC_PROFILE_FAVOR_VF = 2,
1583 I40E_HMC_PROFILE_EQUAL = 3,
d358aa9a
GR		 1584};
1585
8c570dcc
JK		 1586#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1587#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
d358aa9a
GR		 1588
1589/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1590
1591/* set in param0 for get phy abilities to report qualified modules */
8c570dcc
JK		 1592#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1593#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
d358aa9a
GR		 1594
1595enum i40e_aq_phy_type {
1596 I40E_PHY_TYPE_SGMII = 0x0,
1597 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1598 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1599 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1600 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1601 I40E_PHY_TYPE_XAUI = 0x5,
1602 I40E_PHY_TYPE_XFI = 0x6,
1603 I40E_PHY_TYPE_SFI = 0x7,
1604 I40E_PHY_TYPE_XLAUI = 0x8,
1605 I40E_PHY_TYPE_XLPPI = 0x9,
1606 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1607 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
f94234ee
SN		 1608 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1609 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
d358aa9a
GR		 1610 I40E_PHY_TYPE_100BASE_TX = 0x11,
1611 I40E_PHY_TYPE_1000BASE_T = 0x12,
1612 I40E_PHY_TYPE_10GBASE_T = 0x13,
1613 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1614 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1615 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1616 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1617 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1618 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1619 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
f94234ee
SN		 1620 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1621 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1622 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1623 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
d358aa9a
GR		 1624 I40E_PHY_TYPE_MAX
1625};
1626
1627#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1628#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1629#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1630#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1631#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1632
1633enum i40e_aq_link_speed {
1634 I40E_LINK_SPEED_UNKNOWN = 0,
1635 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1636 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1637 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1638 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1639 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1640};
1641
1642struct i40e_aqc_module_desc {
1643 u8 oui[3];
1644 u8 reserved1;
1645 u8 part_number[16];
1646 u8 revision[4];
1647 u8 reserved2[8];
1648};
1649
8d5e33ad
SN		 1650I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1651
d358aa9a 1652struct i40e_aq_get_phy_abilities_resp {
8c570dcc
JK		 1653 __le32 phy_type; /* bitmap using the above enum for offsets */
1654 u8 link_speed; /* bitmap using the above enum bit patterns */
1655 u8 abilities;
1656#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1657#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1658#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1659#define I40E_AQ_PHY_LINK_ENABLED 0x08
1660#define I40E_AQ_PHY_AN_ENABLED 0x10
1661#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1662 __le16 eee_capability;
1663#define I40E_AQ_EEE_100BASE_TX 0x0002
1664#define I40E_AQ_EEE_1000BASE_T 0x0004
1665#define I40E_AQ_EEE_10GBASE_T 0x0008
1666#define I40E_AQ_EEE_1000BASE_KX 0x0010
1667#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1668#define I40E_AQ_EEE_10GBASE_KR 0x0040
1669 __le32 eeer_val;
1670 u8 d3_lpan;
1671#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1672 u8 reserved[3];
1673 u8 phy_id[4];
1674 u8 module_type[3];
1675 u8 qualified_module_count;
1676#define I40E_AQ_PHY_MAX_QMS 16
1677 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
d358aa9a
GR		 1678};
1679
8d5e33ad
SN		 1680I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1681
d358aa9a
GR		 1682/* Set PHY Config (direct 0x0601) */
1683struct i40e_aq_set_phy_config { /* same bits as above in all */
8c570dcc
JK		 1684 __le32 phy_type;
1685 u8 link_speed;
1686 u8 abilities;
d358aa9a
GR		 1687/* bits 0-2 use the values from get_phy_abilities_resp */
1688#define I40E_AQ_PHY_ENABLE_LINK 0x08
1689#define I40E_AQ_PHY_ENABLE_AN 0x10
1690#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
8c570dcc
JK		 1691 __le16 eee_capability;
1692 __le32 eeer;
1693 u8 low_power_ctrl;
1694 u8 reserved[3];
d358aa9a
GR		 1695};
1696
1697I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1698
1699/* Set MAC Config command data structure (direct 0x0603) */
1700struct i40e_aq_set_mac_config {
8c570dcc
JK		 1701 __le16 max_frame_size;
1702 u8 params;
1703#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1704#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1705#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1706#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1707#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1708#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1709#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1710#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1711#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1712#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1713#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1714#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1715#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1716#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1717 u8 tx_timer_priority; /* bitmap */
1718 __le16 tx_timer_value;
1719 __le16 fc_refresh_threshold;
1720 u8 reserved[8];
d358aa9a
GR		 1721};
1722
1723I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1724
1725/* Restart Auto-Negotiation (direct 0x605) */
1726struct i40e_aqc_set_link_restart_an {
8c570dcc
JK		 1727 u8 command;
1728#define I40E_AQ_PHY_RESTART_AN 0x02
1729#define I40E_AQ_PHY_LINK_ENABLE 0x04
1730 u8 reserved[15];
d358aa9a
GR		 1731};
1732
1733I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1734
1735/* Get Link Status cmd & response data structure (direct 0x0607) */
1736struct i40e_aqc_get_link_status {
8c570dcc
JK		 1737 __le16 command_flags; /* only field set on command */
1738#define I40E_AQ_LSE_MASK 0x3
1739#define I40E_AQ_LSE_NOP 0x0
1740#define I40E_AQ_LSE_DISABLE 0x2
1741#define I40E_AQ_LSE_ENABLE 0x3
d358aa9a 1742/* only response uses this flag */
8c570dcc
JK		 1743#define I40E_AQ_LSE_IS_ENABLED 0x1
1744 u8 phy_type; /* i40e_aq_phy_type */
1745 u8 link_speed; /* i40e_aq_link_speed */
1746 u8 link_info;
1d55aa9c
SN		 1747#define I40E_AQ_LINK_UP 0x01 /* obsolete */
1748#define I40E_AQ_LINK_UP_FUNCTION 0x01
8c570dcc
JK		 1749#define I40E_AQ_LINK_FAULT 0x02
1750#define I40E_AQ_LINK_FAULT_TX 0x04
1751#define I40E_AQ_LINK_FAULT_RX 0x08
1752#define I40E_AQ_LINK_FAULT_REMOTE 0x10
1d55aa9c 1753#define I40E_AQ_LINK_UP_PORT 0x20
8c570dcc
JK		 1754#define I40E_AQ_MEDIA_AVAILABLE 0x40
1755#define I40E_AQ_SIGNAL_DETECT 0x80
1756 u8 an_info;
1757#define I40E_AQ_AN_COMPLETED 0x01
1758#define I40E_AQ_LP_AN_ABILITY 0x02
1759#define I40E_AQ_PD_FAULT 0x04
1760#define I40E_AQ_FEC_EN 0x08
1761#define I40E_AQ_PHY_LOW_POWER 0x10
1762#define I40E_AQ_LINK_PAUSE_TX 0x20
1763#define I40E_AQ_LINK_PAUSE_RX 0x40
1764#define I40E_AQ_QUALIFIED_MODULE 0x80
1765 u8 ext_info;
1766#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1767#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1768#define I40E_AQ_LINK_TX_SHIFT 0x02
1769#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1770#define I40E_AQ_LINK_TX_ACTIVE 0x00
1771#define I40E_AQ_LINK_TX_DRAINED 0x01
1772#define I40E_AQ_LINK_TX_FLUSHED 0x03
1773#define I40E_AQ_LINK_FORCED_40G 0x10
1774 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1775 __le16 max_frame_size;
1776 u8 config;
1777#define I40E_AQ_CONFIG_CRC_ENA 0x04
1778#define I40E_AQ_CONFIG_PACING_MASK 0x78
5eb772f7
SN		 1779 u8 external_power_ability;
1780#define I40E_AQ_LINK_POWER_CLASS_1 0x00
1781#define I40E_AQ_LINK_POWER_CLASS_2 0x01
1782#define I40E_AQ_LINK_POWER_CLASS_3 0x02
1783#define I40E_AQ_LINK_POWER_CLASS_4 0x03
1784 u8 reserved[4];
d358aa9a
GR		 1785};
1786
1787I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1788
1789/* Set event mask command (direct 0x613) */
1790struct i40e_aqc_set_phy_int_mask {
8c570dcc
JK		 1791 u8 reserved[8];
1792 __le16 event_mask;
1793#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1794#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1795#define I40E_AQ_EVENT_LINK_FAULT 0x0008
1796#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1797#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1798#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1799#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1800#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1801#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1802 u8 reserved1[6];
d358aa9a
GR		 1803};
1804
1805I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1806
1807/* Get Local AN advt register (direct 0x0614)
1808 * Set Local AN advt register (direct 0x0615)
1809 * Get Link Partner AN advt register (direct 0x0616)
1810 */
1811struct i40e_aqc_an_advt_reg {
8c570dcc
JK		 1812 __le32 local_an_reg0;
1813 __le16 local_an_reg1;
1814 u8 reserved[10];
d358aa9a
GR		 1815};
1816
1817I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1818
1819/* Set Loopback mode (0x0618) */
1820struct i40e_aqc_set_lb_mode {
8c570dcc
JK		 1821 __le16 lb_mode;
1822#define I40E_AQ_LB_PHY_LOCAL 0x01
1823#define I40E_AQ_LB_PHY_REMOTE 0x02
1824#define I40E_AQ_LB_MAC_LOCAL 0x04
1825 u8 reserved[14];
d358aa9a
GR		 1826};
1827
1828I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1829
f94234ee
SN		 1830/* Set PHY Debug command (0x0622) */
1831struct i40e_aqc_set_phy_debug {
8c570dcc 1832 u8 command_flags;
f94234ee
SN		 1833#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1834#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1835#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1836 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1837#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1838#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1839#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1840#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
8c570dcc 1841 u8 reserved[15];
d358aa9a
GR		 1842};
1843
f94234ee 1844I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
d358aa9a
GR		 1845
1846enum i40e_aq_phy_reg_type {
8c570dcc
JK		 1847 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1848 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1849 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
d358aa9a
GR		 1850};
1851
5394f02f
SN		 1852/* Run PHY Activity (0x0626) */
1853struct i40e_aqc_run_phy_activity {
1854 __le16 activity_id;
1855 u8 flags;
1856 u8 reserved1;
1857 __le32 control;
1858 __le32 data;
1859 u8 reserved2[4];
1860};
1861
1862I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1863
d358aa9a
GR		 1864/* NVM Read command (indirect 0x0701)
1865 * NVM Erase commands (direct 0x0702)
1866 * NVM Update commands (indirect 0x0703)
1867 */
1868struct i40e_aqc_nvm_update {
8c570dcc
JK		 1869 u8 command_flags;
1870#define I40E_AQ_NVM_LAST_CMD 0x01
1871#define I40E_AQ_NVM_FLASH_ONLY 0x80
1872 u8 module_pointer;
1873 __le16 length;
1874 __le32 offset;
1875 __le32 addr_high;
1876 __le32 addr_low;
d358aa9a
GR		 1877};
1878
1879I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1880
f94234ee
SN		 1881/* NVM Config Read (indirect 0x0704) */
1882struct i40e_aqc_nvm_config_read {
8c570dcc 1883 __le16 cmd_flags;
e910ca7c
JK		 1884#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1885#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1886#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
8c570dcc 1887 __le16 element_count;
e910ca7c
JK		 1888 __le16 element_id; /* Feature/field ID */
1889 __le16 element_id_msw; /* MSWord of field ID */
8c570dcc
JK		 1890 __le32 address_high;
1891 __le32 address_low;
f94234ee
SN		 1892};
1893
1894I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1895
1896/* NVM Config Write (indirect 0x0705) */
1897struct i40e_aqc_nvm_config_write {
8c570dcc
JK		 1898 __le16 cmd_flags;
1899 __le16 element_count;
1900 u8 reserved[4];
1901 __le32 address_high;
1902 __le32 address_low;
f94234ee
SN		 1903};
1904
1905I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1906
672415c5
SN		 1907/* Used for 0x0704 as well as for 0x0705 commands */
1908#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1909#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1910 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1911#define I40E_AQ_ANVM_FEATURE 0
1912#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
f94234ee
SN		 1913struct i40e_aqc_nvm_config_data_feature {
1914 __le16 feature_id;
672415c5
SN		 1915#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1916#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1917#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
f94234ee
SN		 1918 __le16 feature_options;
1919 __le16 feature_selection;
1920};
1921
672415c5
SN		 1922I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1923
f94234ee 1924struct i40e_aqc_nvm_config_data_immediate_field {
672415c5
SN		 1925 __le32 field_id;
1926 __le32 field_value;
f94234ee 1927 __le16 field_options;
672415c5 1928 __le16 reserved;
f94234ee
SN		 1929};
1930
672415c5
SN		 1931I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1932
00ada50d
MK		 1933/* OEM Post Update (indirect 0x0720)
1934 * no command data struct used
1935 */
1936 struct i40e_aqc_nvm_oem_post_update {
1937#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1938 u8 sel_data;
1939 u8 reserved[7];
1940};
1941
1942I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1943
1944struct i40e_aqc_nvm_oem_post_update_buffer {
1945 u8 str_len;
1946 u8 dev_addr;
1947 __le16 eeprom_addr;
1948 u8 data[36];
1949};
1950
1951I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1952
6774faf9
SN		 1953/* Thermal Sensor (indirect 0x0721)
1954 * read or set thermal sensor configs and values
1955 * takes a sensor and command specific data buffer, not detailed here
1956 */
1957struct i40e_aqc_thermal_sensor {
1958 u8 sensor_action;
1959#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
1960#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
1961#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
1962 u8 reserved[7];
1963 __le32 addr_high;
1964 __le32 addr_low;
1965};
1966
1967I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1968
d358aa9a
GR		 1969/* Send to PF command (indirect 0x0801) id is only used by PF
1970 * Send to VF command (indirect 0x0802) id is only used by PF
1971 * Send to Peer PF command (indirect 0x0803)
1972 */
1973struct i40e_aqc_pf_vf_message {
8c570dcc
JK		 1974 __le32 id;
1975 u8 reserved[4];
1976 __le32 addr_high;
1977 __le32 addr_low;
d358aa9a
GR		 1978};
1979
1980I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1981
1982/* Alternate structure */
1983
1984/* Direct write (direct 0x0900)
1985 * Direct read (direct 0x0902)
1986 */
1987struct i40e_aqc_alternate_write {
1988 __le32 address0;
1989 __le32 data0;
1990 __le32 address1;
1991 __le32 data1;
1992};
1993
1994I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1995
1996/* Indirect write (indirect 0x0901)
1997 * Indirect read (indirect 0x0903)
1998 */
1999
2000struct i40e_aqc_alternate_ind_write {
2001 __le32 address;
2002 __le32 length;
2003 __le32 addr_high;
2004 __le32 addr_low;
2005};
2006
2007I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2008
2009/* Done alternate write (direct 0x0904)
2010 * uses i40e_aq_desc
2011 */
2012struct i40e_aqc_alternate_write_done {
8c570dcc 2013 __le16 cmd_flags;
d358aa9a
GR		 2014#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2015#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2016#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2017#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
8c570dcc 2018 u8 reserved[14];
d358aa9a
GR		 2019};
2020
2021I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2022
2023/* Set OEM mode (direct 0x0905) */
2024struct i40e_aqc_alternate_set_mode {
8c570dcc 2025 __le32 mode;
d358aa9a
GR		 2026#define I40E_AQ_ALTERNATE_MODE_NONE 0
2027#define I40E_AQ_ALTERNATE_MODE_OEM 1
8c570dcc 2028 u8 reserved[12];
d358aa9a
GR		 2029};
2030
2031I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2032
2033/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2034
2035/* async events 0x10xx */
2036
2037/* Lan Queue Overflow Event (direct, 0x1001) */
2038struct i40e_aqc_lan_overflow {
8c570dcc
JK		 2039 __le32 prtdcb_rupto;
2040 __le32 otx_ctl;
2041 u8 reserved[8];
d358aa9a
GR		 2042};
2043
2044I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2045
2046/* Get LLDP MIB (indirect 0x0A00) */
2047struct i40e_aqc_lldp_get_mib {
8c570dcc
JK		 2048 u8 type;
2049 u8 reserved1;
2050#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2051#define I40E_AQ_LLDP_MIB_LOCAL 0x0
2052#define I40E_AQ_LLDP_MIB_REMOTE 0x1
2053#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2054#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2055#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2056#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2057#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2058#define I40E_AQ_LLDP_TX_SHIFT 0x4
2059#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
d358aa9a 2060/* TX pause flags use I40E_AQ_LINK_TX_* above */
8c570dcc
JK		 2061 __le16 local_len;
2062 __le16 remote_len;
2063 u8 reserved2[2];
2064 __le32 addr_high;
2065 __le32 addr_low;
d358aa9a
GR		 2066};
2067
2068I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2069
2070/* Configure LLDP MIB Change Event (direct 0x0A01)
2071 * also used for the event (with type in the command field)
2072 */
2073struct i40e_aqc_lldp_update_mib {
8c570dcc
JK		 2074 u8 command;
2075#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2076#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2077 u8 reserved[7];
2078 __le32 addr_high;
2079 __le32 addr_low;
d358aa9a
GR		 2080};
2081
2082I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2083
2084/* Add LLDP TLV (indirect 0x0A02)
2085 * Delete LLDP TLV (indirect 0x0A04)
2086 */
2087struct i40e_aqc_lldp_add_tlv {
8c570dcc
JK		 2088 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2089 u8 reserved1[1];
2090 __le16 len;
2091 u8 reserved2[4];
2092 __le32 addr_high;
2093 __le32 addr_low;
d358aa9a
GR		 2094};
2095
2096I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2097
2098/* Update LLDP TLV (indirect 0x0A03) */
2099struct i40e_aqc_lldp_update_tlv {
8c570dcc
JK		 2100 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2101 u8 reserved;
2102 __le16 old_len;
2103 __le16 new_offset;
2104 __le16 new_len;
2105 __le32 addr_high;
2106 __le32 addr_low;
d358aa9a
GR		 2107};
2108
2109I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2110
2111/* Stop LLDP (direct 0x0A05) */
2112struct i40e_aqc_lldp_stop {
8c570dcc
JK		 2113 u8 command;
2114#define I40E_AQ_LLDP_AGENT_STOP 0x0
2115#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2116 u8 reserved[15];
d358aa9a
GR		 2117};
2118
2119I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2120
2121/* Start LLDP (direct 0x0A06) */
2122
2123struct i40e_aqc_lldp_start {
8c570dcc
JK		 2124 u8 command;
2125#define I40E_AQ_LLDP_AGENT_START 0x1
2126 u8 reserved[15];
d358aa9a
GR		 2127};
2128
2129I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2130
2131/* Apply MIB changes (0x0A07)
2132 * uses the generic struc as it contains no data
2133 */
2134
2135/* Add Udp Tunnel command and completion (direct 0x0B00) */
2136struct i40e_aqc_add_udp_tunnel {
8c570dcc
JK		 2137 __le16 udp_port;
2138 u8 reserved0[3];
2139 u8 protocol_type;
9774dd8d
SN		 2140#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2141#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2142#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2fcc1a40 2143#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
8c570dcc 2144 u8 reserved1[10];
d358aa9a
GR		 2145};
2146
2147I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2148
2149struct i40e_aqc_add_udp_tunnel_completion {
2150 __le16 udp_port;
2151 u8 filter_entry_index;
2152 u8 multiple_pfs;
8c570dcc
JK		 2153#define I40E_AQC_SINGLE_PF 0x0
2154#define I40E_AQC_MULTIPLE_PFS 0x1
d358aa9a
GR		 2155 u8 total_filters;
2156 u8 reserved[11];
2157};
2158
2159I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2160
2161/* remove UDP Tunnel command (0x0B01) */
2162struct i40e_aqc_remove_udp_tunnel {
8c570dcc
JK		 2163 u8 reserved[2];
2164 u8 index; /* 0 to 15 */
2165 u8 reserved2[13];
d358aa9a
GR		 2166};
2167
2168I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2169
2170struct i40e_aqc_del_udp_tunnel_completion {
8c570dcc
JK		 2171 __le16 udp_port;
2172 u8 index; /* 0 to 15 */
2173 u8 multiple_pfs;
2174 u8 total_filters_used;
2175 u8 reserved1[11];
d358aa9a
GR		 2176};
2177
2178I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2179
e50c8d6d
ASJ		 2180struct i40e_aqc_get_set_rss_key {
2181#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2182#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2183#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2184 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2185 __le16 vsi_id;
2186 u8 reserved[6];
2187 __le32 addr_high;
2188 __le32 addr_low;
2189};
2190
2191I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2192
2193struct i40e_aqc_get_set_rss_key_data {
2194 u8 standard_rss_key[0x28];
2195 u8 extended_hash_key[0xc];
2196};
2197
2198I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2199
2200struct i40e_aqc_get_set_rss_lut {
2201#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2202#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2203#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2204 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2205 __le16 vsi_id;
2206#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2207#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2208 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2209
2210#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2211#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2212 __le16 flags;
2213 u8 reserved[4];
2214 __le32 addr_high;
2215 __le32 addr_low;
2216};
2217
2218I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2219
d358aa9a
GR		 2220/* tunnel key structure 0x0B10 */
2221
90327e7d
GR		 2222struct i40e_aqc_tunnel_key_structure_A0 {
2223 __le16 key1_off;
2224 __le16 key1_len;
2225 __le16 key2_off;
2226 __le16 key2_len;
2227 __le16 flags;
2228#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2229/* response flags */
2230#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2231#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2232#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2233 u8 resreved[6];
2234};
2235
2236I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2237
d358aa9a
GR		 2238struct i40e_aqc_tunnel_key_structure {
2239 u8 key1_off;
2240 u8 key2_off;
2241 u8 key1_len; /* 0 to 15 */
2242 u8 key2_len; /* 0 to 15 */
2243 u8 flags;
8c570dcc 2244#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
d358aa9a 2245/* response flags */
8c570dcc
JK		 2246#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2247#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2248#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
d358aa9a
GR		 2249 u8 network_key_index;
2250#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2251#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2252#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2253#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2254 u8 reserved[10];
2255};
2256
2257I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2258
2259/* OEM mode commands (direct 0xFE0x) */
2260struct i40e_aqc_oem_param_change {
8c570dcc
JK		 2261 __le32 param_type;
2262#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2263#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2264#define I40E_AQ_OEM_PARAM_MAC 2
2265 __le32 param_value1;
35155fe6
SN		 2266 __le16 param_value2;
2267 u8 reserved[6];
d358aa9a
GR		 2268};
2269
2270I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2271
2272struct i40e_aqc_oem_state_change {
8c570dcc
JK		 2273 __le32 state;
2274#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2275#define I40E_AQ_OEM_STATE_LINK_UP 0x1
2276 u8 reserved[12];
d358aa9a
GR		 2277};
2278
2279I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2280
672415c5
SN		 2281/* Initialize OCSD (0xFE02, direct) */
2282struct i40e_aqc_opc_oem_ocsd_initialize {
2283 u8 type_status;
2284 u8 reserved1[3];
2285 __le32 ocsd_memory_block_addr_high;
2286 __le32 ocsd_memory_block_addr_low;
2287 __le32 requested_update_interval;
2288};
2289
2290I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2291
2292/* Initialize OCBB (0xFE03, direct) */
2293struct i40e_aqc_opc_oem_ocbb_initialize {
2294 u8 type_status;
2295 u8 reserved1[3];
2296 __le32 ocbb_memory_block_addr_high;
2297 __le32 ocbb_memory_block_addr_low;
2298 u8 reserved2[4];
2299};
2300
2301I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2302
d358aa9a
GR		 2303/* debug commands */
2304
2305/* get device id (0xFF00) uses the generic structure */
2306
2307/* set test more (0xFF01, internal) */
2308
2309struct i40e_acq_set_test_mode {
8c570dcc
JK		 2310 u8 mode;
2311#define I40E_AQ_TEST_PARTIAL 0
2312#define I40E_AQ_TEST_FULL 1
2313#define I40E_AQ_TEST_NVM 2
2314 u8 reserved[3];
2315 u8 command;
2316#define I40E_AQ_TEST_OPEN 0
2317#define I40E_AQ_TEST_CLOSE 1
2318#define I40E_AQ_TEST_INC 2
2319 u8 reserved2[3];
2320 __le32 address_high;
2321 __le32 address_low;
d358aa9a
GR		 2322};
2323
2324I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2325
2326/* Debug Read Register command (0xFF03)
2327 * Debug Write Register command (0xFF04)
2328 */
2329struct i40e_aqc_debug_reg_read_write {
2330 __le32 reserved;
2331 __le32 address;
2332 __le32 value_high;
2333 __le32 value_low;
2334};
2335
2336I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2337
2338/* Scatter/gather Reg Read (indirect 0xFF05)
2339 * Scatter/gather Reg Write (indirect 0xFF06)
2340 */
2341
2342/* i40e_aq_desc is used for the command */
2343struct i40e_aqc_debug_reg_sg_element_data {
2344 __le32 address;
2345 __le32 value;
2346};
2347
2348/* Debug Modify register (direct 0xFF07) */
2349struct i40e_aqc_debug_modify_reg {
2350 __le32 address;
2351 __le32 value;
2352 __le32 clear_mask;
2353 __le32 set_mask;
2354};
2355
2356I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2357
2358/* dump internal data (0xFF08, indirect) */
2359
2360#define I40E_AQ_CLUSTER_ID_AUX 0
2361#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2362#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2363#define I40E_AQ_CLUSTER_ID_HMC 3
2364#define I40E_AQ_CLUSTER_ID_MAC0 4
2365#define I40E_AQ_CLUSTER_ID_MAC1 5
2366#define I40E_AQ_CLUSTER_ID_MAC2 6
2367#define I40E_AQ_CLUSTER_ID_MAC3 7
2368#define I40E_AQ_CLUSTER_ID_DCB 8
2369#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2370#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2371#define I40E_AQ_CLUSTER_ID_ALTRAM 11
2372
2373struct i40e_aqc_debug_dump_internals {
8c570dcc
JK		 2374 u8 cluster_id;
2375 u8 table_id;
2376 __le16 data_size;
2377 __le32 idx;
2378 __le32 address_high;
2379 __le32 address_low;
d358aa9a
GR		 2380};
2381
2382I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2383
2384struct i40e_aqc_debug_modify_internals {
8c570dcc
JK		 2385 u8 cluster_id;
2386 u8 cluster_specific_params[7];
2387 __le32 address_high;
2388 __le32 address_low;
d358aa9a
GR		 2389};
2390
2391I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2392
2f175f55 2393#endif /* _I40E_ADMINQ_CMD_H_ */
Linux kernel - Deliverables
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