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i40e: add more struct size checks
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_adminq_cmd.h
CommitLineData
d358aa9a
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
b831607d 4 * Copyright(c) 2013 - 2014 Intel Corporation.
d358aa9a
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
d358aa9a
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_ADMINQ_CMD_H_
28#define _I40E_ADMINQ_CMD_H_
29
30/* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
8c570dcc
JK		 36#define I40E_FW_API_VERSION_MAJOR 0x0001
37#define I40E_FW_API_VERSION_MINOR 0x0002
90327e7d 38#define I40E_FW_API_VERSION_A0_MINOR 0x0000
d358aa9a
GR		 39
40struct i40e_aq_desc {
41 __le16 flags;
42 __le16 opcode;
43 __le16 datalen;
44 __le16 retval;
45 __le32 cookie_high;
46 __le32 cookie_low;
47 union {
48 struct {
49 __le32 param0;
50 __le32 param1;
51 __le32 param2;
52 __le32 param3;
53 } internal;
54 struct {
55 __le32 param0;
56 __le32 param1;
57 __le32 addr_high;
58 __le32 addr_low;
59 } external;
60 u8 raw[16];
61 } params;
62};
63
64/* Flags sub-structure
65 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
66 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
67 */
68
69/* command flags and offsets*/
8c570dcc
JK		 70#define I40E_AQ_FLAG_DD_SHIFT 0
71#define I40E_AQ_FLAG_CMP_SHIFT 1
72#define I40E_AQ_FLAG_ERR_SHIFT 2
73#define I40E_AQ_FLAG_VFE_SHIFT 3
74#define I40E_AQ_FLAG_LB_SHIFT 9
75#define I40E_AQ_FLAG_RD_SHIFT 10
76#define I40E_AQ_FLAG_VFC_SHIFT 11
77#define I40E_AQ_FLAG_BUF_SHIFT 12
78#define I40E_AQ_FLAG_SI_SHIFT 13
79#define I40E_AQ_FLAG_EI_SHIFT 14
80#define I40E_AQ_FLAG_FE_SHIFT 15
81
82#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
83#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
84#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
85#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
86#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
87#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
88#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
89#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
90#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
91#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
92#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
d358aa9a
GR		 93
94/* error codes */
95enum i40e_admin_queue_err {
8c570dcc
JK		 96 I40E_AQ_RC_OK = 0, /* success */
97 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
98 I40E_AQ_RC_ENOENT = 2, /* No such element */
99 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
100 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
101 I40E_AQ_RC_EIO = 5, /* I/O error */
102 I40E_AQ_RC_ENXIO = 6, /* No such resource */
103 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
104 I40E_AQ_RC_EAGAIN = 8, /* Try again */
105 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
106 I40E_AQ_RC_EACCES = 10, /* Permission denied */
107 I40E_AQ_RC_EFAULT = 11, /* Bad address */
108 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
109 I40E_AQ_RC_EEXIST = 13, /* object already exists */
110 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
111 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
112 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
113 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
114 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
115 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
116 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
117 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
118 I40E_AQ_RC_EFBIG = 22, /* File too large */
d358aa9a
GR		 119};
120
121/* Admin Queue command opcodes */
122enum i40e_admin_queue_opc {
123 /* aq commands */
8c570dcc
JK		 124 i40e_aqc_opc_get_version = 0x0001,
125 i40e_aqc_opc_driver_version = 0x0002,
126 i40e_aqc_opc_queue_shutdown = 0x0003,
127 i40e_aqc_opc_set_pf_context = 0x0004,
d358aa9a
GR		 128
129 /* resource ownership */
8c570dcc
JK		 130 i40e_aqc_opc_request_resource = 0x0008,
131 i40e_aqc_opc_release_resource = 0x0009,
d358aa9a 132
8c570dcc
JK		 133 i40e_aqc_opc_list_func_capabilities = 0x000A,
134 i40e_aqc_opc_list_dev_capabilities = 0x000B,
d358aa9a 135
8c570dcc
JK		 136 i40e_aqc_opc_set_cppm_configuration = 0x0103,
137 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
138 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
d358aa9a
GR		 139
140 /* LAA */
8c570dcc
JK		 141 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
142 i40e_aqc_opc_mac_address_read = 0x0107,
143 i40e_aqc_opc_mac_address_write = 0x0108,
d358aa9a
GR		 144
145 /* PXE */
8c570dcc 146 i40e_aqc_opc_clear_pxe_mode = 0x0110,
d358aa9a
GR		 147
148 /* internal switch commands */
8c570dcc
JK		 149 i40e_aqc_opc_get_switch_config = 0x0200,
150 i40e_aqc_opc_add_statistics = 0x0201,
151 i40e_aqc_opc_remove_statistics = 0x0202,
152 i40e_aqc_opc_set_port_parameters = 0x0203,
153 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
154
155 i40e_aqc_opc_add_vsi = 0x0210,
156 i40e_aqc_opc_update_vsi_parameters = 0x0211,
157 i40e_aqc_opc_get_vsi_parameters = 0x0212,
158
159 i40e_aqc_opc_add_pv = 0x0220,
160 i40e_aqc_opc_update_pv_parameters = 0x0221,
161 i40e_aqc_opc_get_pv_parameters = 0x0222,
162
163 i40e_aqc_opc_add_veb = 0x0230,
164 i40e_aqc_opc_update_veb_parameters = 0x0231,
165 i40e_aqc_opc_get_veb_parameters = 0x0232,
166
167 i40e_aqc_opc_delete_element = 0x0243,
168
169 i40e_aqc_opc_add_macvlan = 0x0250,
170 i40e_aqc_opc_remove_macvlan = 0x0251,
171 i40e_aqc_opc_add_vlan = 0x0252,
172 i40e_aqc_opc_remove_vlan = 0x0253,
173 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
174 i40e_aqc_opc_add_tag = 0x0255,
175 i40e_aqc_opc_remove_tag = 0x0256,
176 i40e_aqc_opc_add_multicast_etag = 0x0257,
177 i40e_aqc_opc_remove_multicast_etag = 0x0258,
178 i40e_aqc_opc_update_tag = 0x0259,
179 i40e_aqc_opc_add_control_packet_filter = 0x025A,
180 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
181 i40e_aqc_opc_add_cloud_filters = 0x025C,
182 i40e_aqc_opc_remove_cloud_filters = 0x025D,
183
184 i40e_aqc_opc_add_mirror_rule = 0x0260,
185 i40e_aqc_opc_delete_mirror_rule = 0x0261,
d358aa9a 186
d358aa9a 187 /* DCB commands */
8c570dcc
JK		 188 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
189 i40e_aqc_opc_dcb_updated = 0x0302,
d358aa9a
GR		 190
191 /* TX scheduler */
8c570dcc
JK		 192 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
193 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
194 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
195 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
196 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
197 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
198
199 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
200 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
201 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
202 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
203 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
204 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
205 i40e_aqc_opc_query_port_ets_config = 0x0419,
206 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
207 i40e_aqc_opc_suspend_port_tx = 0x041B,
208 i40e_aqc_opc_resume_port_tx = 0x041C,
209 i40e_aqc_opc_configure_partition_bw = 0x041D,
d358aa9a
GR		 210
211 /* hmc */
8c570dcc
JK		 212 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
213 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
d358aa9a
GR		 214
215 /* phy commands*/
8c570dcc
JK		 216 i40e_aqc_opc_get_phy_abilities = 0x0600,
217 i40e_aqc_opc_set_phy_config = 0x0601,
218 i40e_aqc_opc_set_mac_config = 0x0603,
219 i40e_aqc_opc_set_link_restart_an = 0x0605,
220 i40e_aqc_opc_get_link_status = 0x0607,
221 i40e_aqc_opc_set_phy_int_mask = 0x0613,
222 i40e_aqc_opc_get_local_advt_reg = 0x0614,
223 i40e_aqc_opc_set_local_advt_reg = 0x0615,
224 i40e_aqc_opc_get_partner_advt = 0x0616,
225 i40e_aqc_opc_set_lb_modes = 0x0618,
226 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
227 i40e_aqc_opc_set_phy_debug = 0x0622,
228 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
d358aa9a
GR		 229
230 /* NVM commands */
8c570dcc
JK		 231 i40e_aqc_opc_nvm_read = 0x0701,
232 i40e_aqc_opc_nvm_erase = 0x0702,
233 i40e_aqc_opc_nvm_update = 0x0703,
234 i40e_aqc_opc_nvm_config_read = 0x0704,
235 i40e_aqc_opc_nvm_config_write = 0x0705,
d358aa9a
GR		 236
237 /* virtualization commands */
8c570dcc
JK		 238 i40e_aqc_opc_send_msg_to_pf = 0x0801,
239 i40e_aqc_opc_send_msg_to_vf = 0x0802,
240 i40e_aqc_opc_send_msg_to_peer = 0x0803,
d358aa9a
GR		 241
242 /* alternate structure */
8c570dcc
JK		 243 i40e_aqc_opc_alternate_write = 0x0900,
244 i40e_aqc_opc_alternate_write_indirect = 0x0901,
245 i40e_aqc_opc_alternate_read = 0x0902,
246 i40e_aqc_opc_alternate_read_indirect = 0x0903,
247 i40e_aqc_opc_alternate_write_done = 0x0904,
248 i40e_aqc_opc_alternate_set_mode = 0x0905,
249 i40e_aqc_opc_alternate_clear_port = 0x0906,
d358aa9a
GR		 250
251 /* LLDP commands */
8c570dcc
JK		 252 i40e_aqc_opc_lldp_get_mib = 0x0A00,
253 i40e_aqc_opc_lldp_update_mib = 0x0A01,
254 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
255 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
256 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
257 i40e_aqc_opc_lldp_stop = 0x0A05,
258 i40e_aqc_opc_lldp_start = 0x0A06,
d358aa9a
GR		 259
260 /* Tunnel commands */
8c570dcc
JK		 261 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
262 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
263 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
d358aa9a
GR		 264
265 /* Async Events */
8c570dcc 266 i40e_aqc_opc_event_lan_overflow = 0x1001,
d358aa9a
GR		 267
268 /* OEM commands */
8c570dcc
JK		 269 i40e_aqc_opc_oem_parameter_change = 0xFE00,
270 i40e_aqc_opc_oem_device_status_change = 0xFE01,
d358aa9a
GR		 271
272 /* debug commands */
8c570dcc
JK		 273 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
274 i40e_aqc_opc_debug_set_mode = 0xFF01,
275 i40e_aqc_opc_debug_read_reg = 0xFF03,
276 i40e_aqc_opc_debug_write_reg = 0xFF04,
277 i40e_aqc_opc_debug_modify_reg = 0xFF07,
278 i40e_aqc_opc_debug_dump_internals = 0xFF08,
d358aa9a
GR		 279};
280
281/* command structures and indirect data structures */
282
283/* Structure naming conventions:
284 * - no suffix for direct command descriptor structures
285 * - _data for indirect sent data
286 * - _resp for indirect return data (data which is both will use _data)
287 * - _completion for direct return data
288 * - _element_ for repeated elements (may also be _data or _resp)
289 *
290 * Command structures are expected to overlay the params.raw member of the basic
291 * descriptor, and as such cannot exceed 16 bytes in length.
292 */
293
294/* This macro is used to generate a compilation error if a structure
295 * is not exactly the correct length. It gives a divide by zero error if the
296 * structure is not of the correct size, otherwise it creates an enum that is
297 * never used.
298 */
299#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
300 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
301
302/* This macro is used extensively to ensure that command structures are 16
303 * bytes in length as they have to map to the raw array of that size.
304 */
8c570dcc 305#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
d358aa9a
GR		 306
307/* internal (0x00XX) commands */
308
309/* Get version (direct 0x0001) */
310struct i40e_aqc_get_version {
311 __le32 rom_ver;
312 __le32 fw_build;
313 __le16 fw_major;
314 __le16 fw_minor;
315 __le16 api_major;
316 __le16 api_minor;
317};
318
319I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
320
321/* Send driver version (indirect 0x0002) */
322struct i40e_aqc_driver_version {
8c570dcc
JK		 323 u8 driver_major_ver;
324 u8 driver_minor_ver;
325 u8 driver_build_ver;
326 u8 driver_subbuild_ver;
327 u8 reserved[4];
328 __le32 address_high;
329 __le32 address_low;
d358aa9a
GR		 330};
331
332I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
333
334/* Queue Shutdown (direct 0x0003) */
335struct i40e_aqc_queue_shutdown {
8c570dcc
JK		 336 __le32 driver_unloading;
337#define I40E_AQ_DRIVER_UNLOADING 0x1
338 u8 reserved[12];
d358aa9a
GR		 339};
340
341I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
342
f94234ee
SN		 343/* Set PF context (0x0004, direct) */
344struct i40e_aqc_set_pf_context {
345 u8 pf_id;
346 u8 reserved[15];
347};
348
349I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
350
d358aa9a
GR		 351/* Request resource ownership (direct 0x0008)
352 * Release resource ownership (direct 0x0009)
353 */
8c570dcc
JK		 354#define I40E_AQ_RESOURCE_NVM 1
355#define I40E_AQ_RESOURCE_SDP 2
356#define I40E_AQ_RESOURCE_ACCESS_READ 1
357#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
358#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
359#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
d358aa9a
GR		 360
361struct i40e_aqc_request_resource {
8c570dcc
JK		 362 __le16 resource_id;
363 __le16 access_type;
364 __le32 timeout;
365 __le32 resource_number;
366 u8 reserved[4];
d358aa9a
GR		 367};
368
369I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
370
371/* Get function capabilities (indirect 0x000A)
372 * Get device capabilities (indirect 0x000B)
373 */
374struct i40e_aqc_list_capabilites {
375 u8 command_flags;
8c570dcc 376#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
d358aa9a
GR		 377 u8 pf_index;
378 u8 reserved[2];
379 __le32 count;
380 __le32 addr_high;
381 __le32 addr_low;
382};
383
384I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
385
386struct i40e_aqc_list_capabilities_element_resp {
8c570dcc
JK		 387 __le16 id;
388 u8 major_rev;
389 u8 minor_rev;
390 __le32 number;
391 __le32 logical_id;
392 __le32 phys_id;
393 u8 reserved[16];
d358aa9a
GR		 394};
395
396/* list of caps */
397
8c570dcc
JK		 398#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
399#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
400#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
401#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
402#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
403#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
404#define I40E_AQ_CAP_ID_SRIOV 0x0012
405#define I40E_AQ_CAP_ID_VF 0x0013
406#define I40E_AQ_CAP_ID_VMDQ 0x0014
407#define I40E_AQ_CAP_ID_8021QBG 0x0015
408#define I40E_AQ_CAP_ID_8021QBR 0x0016
409#define I40E_AQ_CAP_ID_VSI 0x0017
410#define I40E_AQ_CAP_ID_DCB 0x0018
411#define I40E_AQ_CAP_ID_FCOE 0x0021
35155fe6 412#define I40E_AQ_CAP_ID_ISCSI 0x0022
8c570dcc
JK		 413#define I40E_AQ_CAP_ID_RSS 0x0040
414#define I40E_AQ_CAP_ID_RXQ 0x0041
415#define I40E_AQ_CAP_ID_TXQ 0x0042
416#define I40E_AQ_CAP_ID_MSIX 0x0043
417#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
418#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
419#define I40E_AQ_CAP_ID_1588 0x0046
420#define I40E_AQ_CAP_ID_IWARP 0x0051
421#define I40E_AQ_CAP_ID_LED 0x0061
422#define I40E_AQ_CAP_ID_SDP 0x0062
423#define I40E_AQ_CAP_ID_MDIO 0x0063
424#define I40E_AQ_CAP_ID_FLEX10 0x00F1
425#define I40E_AQ_CAP_ID_CEM 0x00F2
d358aa9a
GR		 426
427/* Set CPPM Configuration (direct 0x0103) */
428struct i40e_aqc_cppm_configuration {
8c570dcc
JK		 429 __le16 command_flags;
430#define I40E_AQ_CPPM_EN_LTRC 0x0800
431#define I40E_AQ_CPPM_EN_DMCTH 0x1000
432#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
433#define I40E_AQ_CPPM_EN_HPTC 0x4000
434#define I40E_AQ_CPPM_EN_DMARC 0x8000
435 __le16 ttlx;
436 __le32 dmacr;
437 __le16 dmcth;
438 u8 hptc;
439 u8 reserved;
440 __le32 pfltrc;
d358aa9a
GR		 441};
442
443I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
444
445/* Set ARP Proxy command / response (indirect 0x0104) */
446struct i40e_aqc_arp_proxy_data {
8c570dcc
JK		 447 __le16 command_flags;
448#define I40E_AQ_ARP_INIT_IPV4 0x0008
449#define I40E_AQ_ARP_UNSUP_CTL 0x0010
450#define I40E_AQ_ARP_ENA 0x0020
451#define I40E_AQ_ARP_ADD_IPV4 0x0040
452#define I40E_AQ_ARP_DEL_IPV4 0x0080
453 __le16 table_id;
454 __le32 pfpm_proxyfc;
455 __le32 ip_addr;
456 u8 mac_addr[6];
d358aa9a
GR		 457};
458
8d5e33ad
SN		 459I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
460
d358aa9a
GR		 461/* Set NS Proxy Table Entry Command (indirect 0x0105) */
462struct i40e_aqc_ns_proxy_data {
8c570dcc
JK		 463 __le16 table_idx_mac_addr_0;
464 __le16 table_idx_mac_addr_1;
465 __le16 table_idx_ipv6_0;
466 __le16 table_idx_ipv6_1;
467 __le16 control;
468#define I40E_AQ_NS_PROXY_ADD_0 0x0100
469#define I40E_AQ_NS_PROXY_DEL_0 0x0200
470#define I40E_AQ_NS_PROXY_ADD_1 0x0400
471#define I40E_AQ_NS_PROXY_DEL_1 0x0800
472#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
473#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
474#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
475#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
476#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
477#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
478#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
479 u8 mac_addr_0[6];
480 u8 mac_addr_1[6];
481 u8 local_mac_addr[6];
482 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
483 u8 ipv6_addr_1[16];
d358aa9a
GR		 484};
485
8d5e33ad
SN		 486I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
487
d358aa9a
GR		 488/* Manage LAA Command (0x0106) - obsolete */
489struct i40e_aqc_mng_laa {
490 __le16 command_flags;
8c570dcc
JK		 491#define I40E_AQ_LAA_FLAG_WR 0x8000
492 u8 reserved[2];
493 __le32 sal;
494 __le16 sah;
495 u8 reserved2[6];
d358aa9a
GR		 496};
497
8d5e33ad
SN		 498I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
499
d358aa9a
GR		 500/* Manage MAC Address Read Command (indirect 0x0107) */
501struct i40e_aqc_mac_address_read {
502 __le16 command_flags;
8c570dcc
JK		 503#define I40E_AQC_LAN_ADDR_VALID 0x10
504#define I40E_AQC_SAN_ADDR_VALID 0x20
505#define I40E_AQC_PORT_ADDR_VALID 0x40
506#define I40E_AQC_WOL_ADDR_VALID 0x80
507#define I40E_AQC_ADDR_VALID_MASK 0xf0
508 u8 reserved[6];
509 __le32 addr_high;
510 __le32 addr_low;
d358aa9a
GR		 511};
512
513I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
514
515struct i40e_aqc_mac_address_read_data {
516 u8 pf_lan_mac[6];
517 u8 pf_san_mac[6];
518 u8 port_mac[6];
519 u8 pf_wol_mac[6];
520};
521
522I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
523
524/* Manage MAC Address Write Command (0x0108) */
525struct i40e_aqc_mac_address_write {
8c570dcc
JK		 526 __le16 command_flags;
527#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
528#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
529#define I40E_AQC_WRITE_TYPE_PORT 0x8000
530#define I40E_AQC_WRITE_TYPE_MASK 0xc000
531 __le16 mac_sah;
532 __le32 mac_sal;
533 u8 reserved[8];
d358aa9a
GR		 534};
535
536I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
537
538/* PXE commands (0x011x) */
539
540/* Clear PXE Command and response (direct 0x0110) */
541struct i40e_aqc_clear_pxe {
542 u8 rx_cnt;
543 u8 reserved[15];
544};
545
546I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
547
548/* Switch configuration commands (0x02xx) */
549
550/* Used by many indirect commands that only pass an seid and a buffer in the
551 * command
552 */
553struct i40e_aqc_switch_seid {
8c570dcc
JK		 554 __le16 seid;
555 u8 reserved[6];
556 __le32 addr_high;
557 __le32 addr_low;
d358aa9a
GR		 558};
559
560I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
561
562/* Get Switch Configuration command (indirect 0x0200)
563 * uses i40e_aqc_switch_seid for the descriptor
564 */
565struct i40e_aqc_get_switch_config_header_resp {
8c570dcc
JK		 566 __le16 num_reported;
567 __le16 num_total;
568 u8 reserved[12];
d358aa9a
GR		 569};
570
8d5e33ad
SN		 571I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
572
d358aa9a 573struct i40e_aqc_switch_config_element_resp {
8c570dcc
JK		 574 u8 element_type;
575#define I40E_AQ_SW_ELEM_TYPE_MAC 1
576#define I40E_AQ_SW_ELEM_TYPE_PF 2
577#define I40E_AQ_SW_ELEM_TYPE_VF 3
578#define I40E_AQ_SW_ELEM_TYPE_EMP 4
579#define I40E_AQ_SW_ELEM_TYPE_BMC 5
580#define I40E_AQ_SW_ELEM_TYPE_PV 16
581#define I40E_AQ_SW_ELEM_TYPE_VEB 17
582#define I40E_AQ_SW_ELEM_TYPE_PA 18
583#define I40E_AQ_SW_ELEM_TYPE_VSI 19
584 u8 revision;
585#define I40E_AQ_SW_ELEM_REV_1 1
586 __le16 seid;
587 __le16 uplink_seid;
588 __le16 downlink_seid;
589 u8 reserved[3];
590 u8 connection_type;
591#define I40E_AQ_CONN_TYPE_REGULAR 0x1
592#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
593#define I40E_AQ_CONN_TYPE_CASCADED 0x3
594 __le16 scheduler_id;
595 __le16 element_info;
d358aa9a
GR		 596};
597
8d5e33ad
SN		 598I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
599
d358aa9a
GR		 600/* Get Switch Configuration (indirect 0x0200)
601 * an array of elements are returned in the response buffer
602 * the first in the array is the header, remainder are elements
603 */
604struct i40e_aqc_get_switch_config_resp {
8c570dcc
JK		 605 struct i40e_aqc_get_switch_config_header_resp header;
606 struct i40e_aqc_switch_config_element_resp element[1];
d358aa9a
GR		 607};
608
8d5e33ad
SN		 609I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
610
d358aa9a
GR		 611/* Add Statistics (direct 0x0201)
612 * Remove Statistics (direct 0x0202)
613 */
614struct i40e_aqc_add_remove_statistics {
8c570dcc
JK		 615 __le16 seid;
616 __le16 vlan;
617 __le16 stat_index;
618 u8 reserved[10];
d358aa9a
GR		 619};
620
621I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
622
623/* Set Port Parameters command (direct 0x0203) */
624struct i40e_aqc_set_port_parameters {
8c570dcc
JK		 625 __le16 command_flags;
626#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
627#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
628#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
629 __le16 bad_frame_vsi;
630 __le16 default_seid; /* reserved for command */
631 u8 reserved[10];
d358aa9a
GR		 632};
633
634I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
635
636/* Get Switch Resource Allocation (indirect 0x0204) */
637struct i40e_aqc_get_switch_resource_alloc {
8c570dcc
JK		 638 u8 num_entries; /* reserved for command */
639 u8 reserved[7];
640 __le32 addr_high;
641 __le32 addr_low;
d358aa9a
GR		 642};
643
644I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
645
646/* expect an array of these structs in the response buffer */
647struct i40e_aqc_switch_resource_alloc_element_resp {
8c570dcc
JK		 648 u8 resource_type;
649#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
650#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
651#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
652#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
653#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
654#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
655#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
656#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
657#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
658#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
659#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
660#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
661#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
662#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
663#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
664#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
665#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
666#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
667#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
668 u8 reserved1;
669 __le16 guaranteed;
670 __le16 total;
671 __le16 used;
672 __le16 total_unalloced;
673 u8 reserved2[6];
d358aa9a
GR		 674};
675
8d5e33ad
SN		 676I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
677
d358aa9a
GR		 678/* Add VSI (indirect 0x0210)
679 * this indirect command uses struct i40e_aqc_vsi_properties_data
680 * as the indirect buffer (128 bytes)
681 *
682 * Update VSI (indirect 0x211)
683 * uses the same data structure as Add VSI
684 *
685 * Get VSI (indirect 0x0212)
686 * uses the same completion and data structure as Add VSI
687 */
688struct i40e_aqc_add_get_update_vsi {
8c570dcc
JK		 689 __le16 uplink_seid;
690 u8 connection_type;
691#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
692#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
693#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
694 u8 reserved1;
695 u8 vf_id;
696 u8 reserved2;
697 __le16 vsi_flags;
698#define I40E_AQ_VSI_TYPE_SHIFT 0x0
699#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
700#define I40E_AQ_VSI_TYPE_VF 0x0
701#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
702#define I40E_AQ_VSI_TYPE_PF 0x2
703#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
704#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
705 __le32 addr_high;
706 __le32 addr_low;
d358aa9a
GR		 707};
708
709I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
710
711struct i40e_aqc_add_get_update_vsi_completion {
712 __le16 seid;
713 __le16 vsi_number;
714 __le16 vsi_used;
715 __le16 vsi_free;
716 __le32 addr_high;
717 __le32 addr_low;
718};
719
720I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
721
722struct i40e_aqc_vsi_properties_data {
723 /* first 96 byte are written by SW */
8c570dcc
JK		 724 __le16 valid_sections;
725#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
726#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
727#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
728#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
729#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
730#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
731#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
732#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
733#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
734#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
d358aa9a 735 /* switch section */
8c570dcc
JK		 736 __le16 switch_id; /* 12bit id combined with flags below */
737#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
738#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
739#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
740#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
741#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
742 u8 sw_reserved[2];
d358aa9a 743 /* security section */
8c570dcc
JK		 744 u8 sec_flags;
745#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
746#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
747#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
748 u8 sec_reserved;
d358aa9a 749 /* VLAN section */
8c570dcc
JK		 750 __le16 pvid; /* VLANS include priority bits */
751 __le16 fcoe_pvid;
752 u8 port_vlan_flags;
753#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
754#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
755 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
756#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
757#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
758#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
759#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
760#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
761#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
762 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
763#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
764#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
765#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
766#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
767 u8 pvlan_reserved[3];
d358aa9a 768 /* ingress egress up sections */
8c570dcc
JK		 769 __le32 ingress_table; /* bitmap, 3 bits per up */
770#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
771#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
772 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
773#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
774#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
775 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
776#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
777#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
778 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
779#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
780#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
781 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
782#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
783#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
784 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
785#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
786#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
787 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
788#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
789#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
790 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
791#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
792#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
793 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
794 __le32 egress_table; /* same defines as for ingress table */
d358aa9a 795 /* cascaded PV section */
8c570dcc
JK		 796 __le16 cas_pv_tag;
797 u8 cas_pv_flags;
798#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
799#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
800 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
801#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
802#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
803#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
804#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
805#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
806#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
807 u8 cas_pv_reserved;
d358aa9a 808 /* queue mapping section */
8c570dcc
JK		 809 __le16 mapping_flags;
810#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
811#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
812 __le16 queue_mapping[16];
813#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
814#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
815 __le16 tc_mapping[8];
816#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
817#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
818 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
819#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
820#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
821 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
d358aa9a 822 /* queueing option section */
8c570dcc
JK		 823 u8 queueing_opt_flags;
824#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
825#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
826 u8 queueing_opt_reserved[3];
d358aa9a 827 /* scheduler section */
8c570dcc
JK		 828 u8 up_enable_bits;
829 u8 sched_reserved;
d358aa9a 830 /* outer up section */
8c570dcc
JK		 831 __le32 outer_up_table; /* same structure and defines as ingress tbl */
832 u8 cmd_reserved[8];
d358aa9a 833 /* last 32 bytes are written by FW */
8c570dcc 834 __le16 qs_handle[8];
d358aa9a 835#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
8c570dcc
JK		 836 __le16 stat_counter_idx;
837 __le16 sched_id;
838 u8 resp_reserved[12];
d358aa9a
GR		 839};
840
841I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
842
843/* Add Port Virtualizer (direct 0x0220)
844 * also used for update PV (direct 0x0221) but only flags are used
845 * (IS_CTRL_PORT only works on add PV)
846 */
847struct i40e_aqc_add_update_pv {
8c570dcc
JK		 848 __le16 command_flags;
849#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
850#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
851#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
852#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
853 __le16 uplink_seid;
854 __le16 connected_seid;
855 u8 reserved[10];
d358aa9a
GR		 856};
857
858I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
859
860struct i40e_aqc_add_update_pv_completion {
861 /* reserved for update; for add also encodes error if rc == ENOSPC */
8c570dcc
JK		 862 __le16 pv_seid;
863#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
864#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
865#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
866#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
867 u8 reserved[14];
d358aa9a
GR		 868};
869
870I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
871
872/* Get PV Params (direct 0x0222)
873 * uses i40e_aqc_switch_seid for the descriptor
874 */
875
876struct i40e_aqc_get_pv_params_completion {
8c570dcc
JK		 877 __le16 seid;
878 __le16 default_stag;
879 __le16 pv_flags; /* same flags as add_pv */
880#define I40E_AQC_GET_PV_PV_TYPE 0x1
881#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
882#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
883 u8 reserved[8];
884 __le16 default_port_seid;
d358aa9a
GR		 885};
886
887I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
888
889/* Add VEB (direct 0x0230) */
890struct i40e_aqc_add_veb {
8c570dcc
JK		 891 __le16 uplink_seid;
892 __le16 downlink_seid;
893 __le16 veb_flags;
894#define I40E_AQC_ADD_VEB_FLOATING 0x1
895#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
896#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
d358aa9a 897 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
8c570dcc
JK		 898#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
899#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
900#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
901 u8 enable_tcs;
902 u8 reserved[9];
d358aa9a
GR		 903};
904
905I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
906
907struct i40e_aqc_add_veb_completion {
8c570dcc
JK		 908 u8 reserved[6];
909 __le16 switch_seid;
d358aa9a 910 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
8c570dcc
JK		 911 __le16 veb_seid;
912#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
913#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
914#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
915#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
916 __le16 statistic_index;
917 __le16 vebs_used;
918 __le16 vebs_free;
d358aa9a
GR		 919};
920
921I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
922
923/* Get VEB Parameters (direct 0x0232)
924 * uses i40e_aqc_switch_seid for the descriptor
925 */
926struct i40e_aqc_get_veb_parameters_completion {
8c570dcc
JK		 927 __le16 seid;
928 __le16 switch_id;
929 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
930 __le16 statistic_index;
931 __le16 vebs_used;
932 __le16 vebs_free;
933 u8 reserved[4];
d358aa9a
GR		 934};
935
936I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
937
938/* Delete Element (direct 0x0243)
939 * uses the generic i40e_aqc_switch_seid
940 */
941
942/* Add MAC-VLAN (indirect 0x0250) */
943
944/* used for the command for most vlan commands */
945struct i40e_aqc_macvlan {
8c570dcc
JK		 946 __le16 num_addresses;
947 __le16 seid[3];
948#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
949#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 950 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 951#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
952 __le32 addr_high;
953 __le32 addr_low;
d358aa9a
GR		 954};
955
956I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
957
958/* indirect data for command and response */
959struct i40e_aqc_add_macvlan_element_data {
8c570dcc
JK		 960 u8 mac_addr[6];
961 __le16 vlan_tag;
962 __le16 flags;
963#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
964#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
965#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
966#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
967 __le16 queue_number;
968#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
969#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
d358aa9a
GR		 970 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
971 /* response section */
8c570dcc
JK		 972 u8 match_method;
973#define I40E_AQC_MM_PERFECT_MATCH 0x01
974#define I40E_AQC_MM_HASH_MATCH 0x02
975#define I40E_AQC_MM_ERR_NO_RES 0xFF
976 u8 reserved1[3];
d358aa9a
GR		 977};
978
979struct i40e_aqc_add_remove_macvlan_completion {
980 __le16 perfect_mac_used;
981 __le16 perfect_mac_free;
982 __le16 unicast_hash_free;
983 __le16 multicast_hash_free;
984 __le32 addr_high;
985 __le32 addr_low;
986};
987
988I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
989
990/* Remove MAC-VLAN (indirect 0x0251)
991 * uses i40e_aqc_macvlan for the descriptor
992 * data points to an array of num_addresses of elements
993 */
994
995struct i40e_aqc_remove_macvlan_element_data {
8c570dcc
JK		 996 u8 mac_addr[6];
997 __le16 vlan_tag;
998 u8 flags;
999#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1000#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1001#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1002#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1003 u8 reserved[3];
d358aa9a 1004 /* reply section */
8c570dcc
JK		 1005 u8 error_code;
1006#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1007#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1008 u8 reply_reserved[3];
d358aa9a
GR		 1009};
1010
1011/* Add VLAN (indirect 0x0252)
1012 * Remove VLAN (indirect 0x0253)
1013 * use the generic i40e_aqc_macvlan for the command
1014 */
1015struct i40e_aqc_add_remove_vlan_element_data {
8c570dcc
JK		 1016 __le16 vlan_tag;
1017 u8 vlan_flags;
d358aa9a 1018/* flags for add VLAN */
8c570dcc
JK		 1019#define I40E_AQC_ADD_VLAN_LOCAL 0x1
1020#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1021#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1022#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1023#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1024#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1025#define I40E_AQC_VLAN_PTYPE_SHIFT 3
1026#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1027#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1028#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1029#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1030#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
d358aa9a 1031/* flags for remove VLAN */
8c570dcc
JK		 1032#define I40E_AQC_REMOVE_VLAN_ALL 0x1
1033 u8 reserved;
1034 u8 result;
d358aa9a 1035/* flags for add VLAN */
8c570dcc
JK		 1036#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1037#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1038#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
d358aa9a 1039/* flags for remove VLAN */
8c570dcc
JK		 1040#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1041#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1042 u8 reserved1[3];
d358aa9a
GR		 1043};
1044
1045struct i40e_aqc_add_remove_vlan_completion {
8c570dcc
JK		 1046 u8 reserved[4];
1047 __le16 vlans_used;
1048 __le16 vlans_free;
1049 __le32 addr_high;
1050 __le32 addr_low;
d358aa9a
GR		 1051};
1052
1053/* Set VSI Promiscuous Modes (direct 0x0254) */
1054struct i40e_aqc_set_vsi_promiscuous_modes {
8c570dcc
JK		 1055 __le16 promiscuous_flags;
1056 __le16 valid_flags;
d358aa9a 1057/* flags used for both fields above */
8c570dcc
JK		 1058#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1059#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1060#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1061#define I40E_AQC_SET_VSI_DEFAULT 0x08
1062#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1063 __le16 seid;
1064#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1065 __le16 vlan_tag;
1066#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1067 u8 reserved[8];
d358aa9a
GR		 1068};
1069
1070I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1071
1072/* Add S/E-tag command (direct 0x0255)
1073 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1074 */
1075struct i40e_aqc_add_tag {
8c570dcc
JK		 1076 __le16 flags;
1077#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1078 __le16 seid;
1079#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1080#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1081 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1082 __le16 tag;
1083 __le16 queue_number;
1084 u8 reserved[8];
d358aa9a
GR		 1085};
1086
1087I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1088
1089struct i40e_aqc_add_remove_tag_completion {
8c570dcc
JK		 1090 u8 reserved[12];
1091 __le16 tags_used;
1092 __le16 tags_free;
d358aa9a
GR		 1093};
1094
1095I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1096
1097/* Remove S/E-tag command (direct 0x0256)
1098 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1099 */
1100struct i40e_aqc_remove_tag {
8c570dcc
JK		 1101 __le16 seid;
1102#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1103#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1104 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1105 __le16 tag;
1106 u8 reserved[12];
d358aa9a
GR		 1107};
1108
8d5e33ad
SN		 1109I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1110
d358aa9a
GR		 1111/* Add multicast E-Tag (direct 0x0257)
1112 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1113 * and no external data
1114 */
1115struct i40e_aqc_add_remove_mcast_etag {
8c570dcc
JK		 1116 __le16 pv_seid;
1117 __le16 etag;
1118 u8 num_unicast_etags;
1119 u8 reserved[3];
1120 __le32 addr_high; /* address of array of 2-byte s-tags */
1121 __le32 addr_low;
d358aa9a
GR		 1122};
1123
1124I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1125
1126struct i40e_aqc_add_remove_mcast_etag_completion {
8c570dcc
JK		 1127 u8 reserved[4];
1128 __le16 mcast_etags_used;
1129 __le16 mcast_etags_free;
1130 __le32 addr_high;
1131 __le32 addr_low;
d358aa9a
GR		 1132
1133};
1134
1135I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1136
1137/* Update S/E-Tag (direct 0x0259) */
1138struct i40e_aqc_update_tag {
8c570dcc
JK		 1139 __le16 seid;
1140#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1141#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1142 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1143 __le16 old_tag;
1144 __le16 new_tag;
1145 u8 reserved[10];
d358aa9a
GR		 1146};
1147
1148I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1149
1150struct i40e_aqc_update_tag_completion {
8c570dcc
JK		 1151 u8 reserved[12];
1152 __le16 tags_used;
1153 __le16 tags_free;
d358aa9a
GR		 1154};
1155
1156I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1157
1158/* Add Control Packet filter (direct 0x025A)
1159 * Remove Control Packet filter (direct 0x025B)
1160 * uses the i40e_aqc_add_oveb_cloud,
1161 * and the generic direct completion structure
1162 */
1163struct i40e_aqc_add_remove_control_packet_filter {
8c570dcc
JK		 1164 u8 mac[6];
1165 __le16 etype;
1166 __le16 flags;
1167#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1168#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1169#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1170#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1171#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1172 __le16 seid;
1173#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1174#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1175 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1176 __le16 queue;
1177 u8 reserved[2];
d358aa9a
GR		 1178};
1179
1180I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1181
1182struct i40e_aqc_add_remove_control_packet_filter_completion {
8c570dcc
JK		 1183 __le16 mac_etype_used;
1184 __le16 etype_used;
1185 __le16 mac_etype_free;
1186 __le16 etype_free;
1187 u8 reserved[8];
d358aa9a
GR		 1188};
1189
1190I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1191
1192/* Add Cloud filters (indirect 0x025C)
1193 * Remove Cloud filters (indirect 0x025D)
1194 * uses the i40e_aqc_add_remove_cloud_filters,
1195 * and the generic indirect completion structure
1196 */
1197struct i40e_aqc_add_remove_cloud_filters {
8c570dcc
JK		 1198 u8 num_filters;
1199 u8 reserved;
1200 __le16 seid;
1201#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1202#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
d358aa9a 1203 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1204 u8 reserved2[4];
1205 __le32 addr_high;
1206 __le32 addr_low;
d358aa9a
GR		 1207};
1208
1209I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1210
1211struct i40e_aqc_add_remove_cloud_filters_element_data {
8c570dcc
JK		 1212 u8 outer_mac[6];
1213 u8 inner_mac[6];
1214 __le16 inner_vlan;
d358aa9a
GR		 1215 union {
1216 struct {
1217 u8 reserved[12];
1218 u8 data[4];
1219 } v4;
1220 struct {
1221 u8 data[16];
1222 } v6;
1223 } ipaddr;
8c570dcc
JK		 1224 __le16 flags;
1225#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
35155fe6 1226#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
d358aa9a
GR		 1227 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1228/* 0x0000 reserved */
8c570dcc 1229#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
d358aa9a 1230/* 0x0002 reserved */
8c570dcc
JK		 1231#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1232#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
d358aa9a 1233/* 0x0005 reserved */
8c570dcc 1234#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
d358aa9a
GR		 1235/* 0x0007 reserved */
1236/* 0x0008 reserved */
8c570dcc
JK		 1237#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1238#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1239#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1240#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1241
1242#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1243#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1244#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1245#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1246#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1247
1248#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1249#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1250#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1251#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1252#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1253#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1254
1255 __le32 tenant_id;
1256 u8 reserved[4];
1257 __le16 queue_number;
1258#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
35155fe6 1259#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
8c570dcc
JK		 1260 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1261 u8 reserved2[14];
d358aa9a 1262 /* response section */
8c570dcc
JK		 1263 u8 allocation_result;
1264#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1265#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1266 u8 response_reserved[7];
d358aa9a
GR		 1267};
1268
1269struct i40e_aqc_remove_cloud_filters_completion {
1270 __le16 perfect_ovlan_used;
1271 __le16 perfect_ovlan_free;
1272 __le16 vlan_used;
1273 __le16 vlan_free;
1274 __le32 addr_high;
1275 __le32 addr_low;
1276};
1277
1278I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1279
1280/* Add Mirror Rule (indirect or direct 0x0260)
1281 * Delete Mirror Rule (indirect or direct 0x0261)
1282 * note: some rule types (4,5) do not use an external buffer.
1283 * take care to set the flags correctly.
1284 */
1285struct i40e_aqc_add_delete_mirror_rule {
1286 __le16 seid;
1287 __le16 rule_type;
8c570dcc
JK		 1288#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1289#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
d358aa9a 1290 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
8c570dcc
JK		 1291#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1292#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1293#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1294#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1295#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
d358aa9a
GR		 1296 __le16 num_entries;
1297 __le16 destination; /* VSI for add, rule id for delete */
1298 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1299 __le32 addr_low;
1300};
1301
1302I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1303
1304struct i40e_aqc_add_delete_mirror_rule_completion {
8c570dcc
JK		 1305 u8 reserved[2];
1306 __le16 rule_id; /* only used on add */
1307 __le16 mirror_rules_used;
1308 __le16 mirror_rules_free;
1309 __le32 addr_high;
1310 __le32 addr_low;
d358aa9a
GR		 1311};
1312
1313I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1314
d358aa9a
GR		 1315/* DCB 0x03xx*/
1316
1317/* PFC Ignore (direct 0x0301)
1318 * the command and response use the same descriptor structure
1319 */
1320struct i40e_aqc_pfc_ignore {
8c570dcc
JK		 1321 u8 tc_bitmap;
1322 u8 command_flags; /* unused on response */
1323#define I40E_AQC_PFC_IGNORE_SET 0x80
1324#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1325 u8 reserved[14];
d358aa9a
GR		 1326};
1327
1328I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1329
1330/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1331 * with no parameters
1332 */
1333
1334/* TX scheduler 0x04xx */
1335
1336/* Almost all the indirect commands use
1337 * this generic struct to pass the SEID in param0
1338 */
1339struct i40e_aqc_tx_sched_ind {
8c570dcc
JK		 1340 __le16 vsi_seid;
1341 u8 reserved[6];
1342 __le32 addr_high;
1343 __le32 addr_low;
d358aa9a
GR		 1344};
1345
1346I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1347
1348/* Several commands respond with a set of queue set handles */
1349struct i40e_aqc_qs_handles_resp {
1350 __le16 qs_handles[8];
1351};
1352
1353/* Configure VSI BW limits (direct 0x0400) */
1354struct i40e_aqc_configure_vsi_bw_limit {
8c570dcc
JK		 1355 __le16 vsi_seid;
1356 u8 reserved[2];
1357 __le16 credit;
1358 u8 reserved1[2];
1359 u8 max_credit; /* 0-3, limit = 2^max */
1360 u8 reserved2[7];
d358aa9a
GR		 1361};
1362
1363I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1364
1365/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1366 * responds with i40e_aqc_qs_handles_resp
1367 */
1368struct i40e_aqc_configure_vsi_ets_sla_bw_data {
8c570dcc
JK		 1369 u8 tc_valid_bits;
1370 u8 reserved[15];
1371 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
d358aa9a
GR		 1372
1373 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc
JK		 1374 __le16 tc_bw_max[2];
1375 u8 reserved1[28];
d358aa9a
GR		 1376};
1377
8d5e33ad
SN		 1378I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1379
d358aa9a
GR		 1380/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1381 * responds with i40e_aqc_qs_handles_resp
1382 */
1383struct i40e_aqc_configure_vsi_tc_bw_data {
8c570dcc
JK		 1384 u8 tc_valid_bits;
1385 u8 reserved[3];
1386 u8 tc_bw_credits[8];
1387 u8 reserved1[4];
1388 __le16 qs_handles[8];
d358aa9a
GR		 1389};
1390
8d5e33ad
SN		 1391I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1392
d358aa9a
GR		 1393/* Query vsi bw configuration (indirect 0x0408) */
1394struct i40e_aqc_query_vsi_bw_config_resp {
8c570dcc
JK		 1395 u8 tc_valid_bits;
1396 u8 tc_suspended_bits;
1397 u8 reserved[14];
1398 __le16 qs_handles[8];
1399 u8 reserved1[4];
1400 __le16 port_bw_limit;
1401 u8 reserved2[2];
1402 u8 max_bw; /* 0-3, limit = 2^max */
1403 u8 reserved3[23];
d358aa9a
GR		 1404};
1405
8d5e33ad
SN		 1406I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1407
d358aa9a
GR		 1408/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1409struct i40e_aqc_query_vsi_ets_sla_config_resp {
8c570dcc
JK		 1410 u8 tc_valid_bits;
1411 u8 reserved[3];
1412 u8 share_credits[8];
1413 __le16 credits[8];
d358aa9a
GR		 1414
1415 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc 1416 __le16 tc_bw_max[2];
d358aa9a
GR		 1417};
1418
8d5e33ad
SN		 1419I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1420
d358aa9a
GR		 1421/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1422struct i40e_aqc_configure_switching_comp_bw_limit {
8c570dcc
JK		 1423 __le16 seid;
1424 u8 reserved[2];
1425 __le16 credit;
1426 u8 reserved1[2];
1427 u8 max_bw; /* 0-3, limit = 2^max */
1428 u8 reserved2[7];
d358aa9a
GR		 1429};
1430
1431I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1432
1433/* Enable Physical Port ETS (indirect 0x0413)
1434 * Modify Physical Port ETS (indirect 0x0414)
1435 * Disable Physical Port ETS (indirect 0x0415)
1436 */
1437struct i40e_aqc_configure_switching_comp_ets_data {
8c570dcc
JK		 1438 u8 reserved[4];
1439 u8 tc_valid_bits;
1440 u8 seepage;
1441#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1442 u8 tc_strict_priority_flags;
1443 u8 reserved1[17];
1444 u8 tc_bw_share_credits[8];
1445 u8 reserved2[96];
d358aa9a
GR		 1446};
1447
8d5e33ad
SN		 1448I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1449
d358aa9a
GR		 1450/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1451struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
8c570dcc
JK		 1452 u8 tc_valid_bits;
1453 u8 reserved[15];
1454 __le16 tc_bw_credit[8];
d358aa9a
GR		 1455
1456 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc
JK		 1457 __le16 tc_bw_max[2];
1458 u8 reserved1[28];
d358aa9a
GR		 1459};
1460
8d5e33ad
SN		 1461I40E_CHECK_STRUCT_LEN(0x40,
1462 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1463
d358aa9a
GR		 1464/* Configure Switching Component Bandwidth Allocation per Tc
1465 * (indirect 0x0417)
1466 */
1467struct i40e_aqc_configure_switching_comp_bw_config_data {
8c570dcc
JK		 1468 u8 tc_valid_bits;
1469 u8 reserved[2];
1470 u8 absolute_credits; /* bool */
1471 u8 tc_bw_share_credits[8];
1472 u8 reserved1[20];
d358aa9a
GR		 1473};
1474
8d5e33ad
SN		 1475I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1476
d358aa9a
GR		 1477/* Query Switching Component Configuration (indirect 0x0418) */
1478struct i40e_aqc_query_switching_comp_ets_config_resp {
8c570dcc
JK		 1479 u8 tc_valid_bits;
1480 u8 reserved[35];
1481 __le16 port_bw_limit;
1482 u8 reserved1[2];
1483 u8 tc_bw_max; /* 0-3, limit = 2^max */
1484 u8 reserved2[23];
d358aa9a
GR		 1485};
1486
8d5e33ad
SN		 1487I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1488
d358aa9a
GR		 1489/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1490struct i40e_aqc_query_port_ets_config_resp {
8c570dcc
JK		 1491 u8 reserved[4];
1492 u8 tc_valid_bits;
1493 u8 reserved1;
1494 u8 tc_strict_priority_bits;
1495 u8 reserved2;
1496 u8 tc_bw_share_credits[8];
1497 __le16 tc_bw_limits[8];
d358aa9a
GR		 1498
1499 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
8c570dcc
JK		 1500 __le16 tc_bw_max[2];
1501 u8 reserved3[32];
d358aa9a
GR		 1502};
1503
8d5e33ad
SN		 1504I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1505
d358aa9a
GR		 1506/* Query Switching Component Bandwidth Allocation per Traffic Type
1507 * (indirect 0x041A)
1508 */
1509struct i40e_aqc_query_switching_comp_bw_config_resp {
8c570dcc
JK		 1510 u8 tc_valid_bits;
1511 u8 reserved[2];
1512 u8 absolute_credits_enable; /* bool */
1513 u8 tc_bw_share_credits[8];
1514 __le16 tc_bw_limits[8];
d358aa9a
GR		 1515
1516 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc 1517 __le16 tc_bw_max[2];
d358aa9a
GR		 1518};
1519
8d5e33ad
SN		 1520I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1521
d358aa9a
GR		 1522/* Suspend/resume port TX traffic
1523 * (direct 0x041B and 0x041C) uses the generic SEID struct
1524 */
1525
befc229c
SN		 1526/* Configure partition BW
1527 * (indirect 0x041D)
1528 */
1529struct i40e_aqc_configure_partition_bw_data {
8c570dcc
JK		 1530 __le16 pf_valid_bits;
1531 u8 min_bw[16]; /* guaranteed bandwidth */
1532 u8 max_bw[16]; /* bandwidth limit */
befc229c
SN		 1533};
1534
8d5e33ad
SN		 1535I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1536
d358aa9a
GR		 1537/* Get and set the active HMC resource profile and status.
1538 * (direct 0x0500) and (direct 0x0501)
1539 */
1540struct i40e_aq_get_set_hmc_resource_profile {
8c570dcc
JK		 1541 u8 pm_profile;
1542 u8 pe_vf_enabled;
1543 u8 reserved[14];
d358aa9a
GR		 1544};
1545
1546I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1547
1548enum i40e_aq_hmc_profile {
1549 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
8c570dcc
JK		 1550 I40E_HMC_PROFILE_DEFAULT = 1,
1551 I40E_HMC_PROFILE_FAVOR_VF = 2,
1552 I40E_HMC_PROFILE_EQUAL = 3,
d358aa9a
GR		 1553};
1554
8c570dcc
JK		 1555#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1556#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
d358aa9a
GR		 1557
1558/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1559
1560/* set in param0 for get phy abilities to report qualified modules */
8c570dcc
JK		 1561#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1562#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
d358aa9a
GR		 1563
1564enum i40e_aq_phy_type {
1565 I40E_PHY_TYPE_SGMII = 0x0,
1566 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1567 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1568 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1569 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1570 I40E_PHY_TYPE_XAUI = 0x5,
1571 I40E_PHY_TYPE_XFI = 0x6,
1572 I40E_PHY_TYPE_SFI = 0x7,
1573 I40E_PHY_TYPE_XLAUI = 0x8,
1574 I40E_PHY_TYPE_XLPPI = 0x9,
1575 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1576 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
f94234ee
SN		 1577 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1578 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
d358aa9a
GR		 1579 I40E_PHY_TYPE_100BASE_TX = 0x11,
1580 I40E_PHY_TYPE_1000BASE_T = 0x12,
1581 I40E_PHY_TYPE_10GBASE_T = 0x13,
1582 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1583 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1584 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1585 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1586 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1587 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1588 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
f94234ee
SN		 1589 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1590 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1591 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1592 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
d358aa9a
GR		 1593 I40E_PHY_TYPE_MAX
1594};
1595
1596#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1597#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1598#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1599#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1600#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1601
1602enum i40e_aq_link_speed {
1603 I40E_LINK_SPEED_UNKNOWN = 0,
1604 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1605 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1606 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1607 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1608 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1609};
1610
1611struct i40e_aqc_module_desc {
1612 u8 oui[3];
1613 u8 reserved1;
1614 u8 part_number[16];
1615 u8 revision[4];
1616 u8 reserved2[8];
1617};
1618
8d5e33ad
SN		 1619I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1620
d358aa9a 1621struct i40e_aq_get_phy_abilities_resp {
8c570dcc
JK		 1622 __le32 phy_type; /* bitmap using the above enum for offsets */
1623 u8 link_speed; /* bitmap using the above enum bit patterns */
1624 u8 abilities;
1625#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1626#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1627#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1628#define I40E_AQ_PHY_LINK_ENABLED 0x08
1629#define I40E_AQ_PHY_AN_ENABLED 0x10
1630#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1631 __le16 eee_capability;
1632#define I40E_AQ_EEE_100BASE_TX 0x0002
1633#define I40E_AQ_EEE_1000BASE_T 0x0004
1634#define I40E_AQ_EEE_10GBASE_T 0x0008
1635#define I40E_AQ_EEE_1000BASE_KX 0x0010
1636#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1637#define I40E_AQ_EEE_10GBASE_KR 0x0040
1638 __le32 eeer_val;
1639 u8 d3_lpan;
1640#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1641 u8 reserved[3];
1642 u8 phy_id[4];
1643 u8 module_type[3];
1644 u8 qualified_module_count;
1645#define I40E_AQ_PHY_MAX_QMS 16
1646 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
d358aa9a
GR		 1647};
1648
8d5e33ad
SN		 1649I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1650
d358aa9a
GR		 1651/* Set PHY Config (direct 0x0601) */
1652struct i40e_aq_set_phy_config { /* same bits as above in all */
8c570dcc
JK		 1653 __le32 phy_type;
1654 u8 link_speed;
1655 u8 abilities;
d358aa9a
GR		 1656/* bits 0-2 use the values from get_phy_abilities_resp */
1657#define I40E_AQ_PHY_ENABLE_LINK 0x08
1658#define I40E_AQ_PHY_ENABLE_AN 0x10
1659#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
8c570dcc
JK		 1660 __le16 eee_capability;
1661 __le32 eeer;
1662 u8 low_power_ctrl;
1663 u8 reserved[3];
d358aa9a
GR		 1664};
1665
1666I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1667
1668/* Set MAC Config command data structure (direct 0x0603) */
1669struct i40e_aq_set_mac_config {
8c570dcc
JK		 1670 __le16 max_frame_size;
1671 u8 params;
1672#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1673#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1674#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1675#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1676#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1677#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1678#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1679#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1680#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1681#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1682#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1683#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1684#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1685#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1686 u8 tx_timer_priority; /* bitmap */
1687 __le16 tx_timer_value;
1688 __le16 fc_refresh_threshold;
1689 u8 reserved[8];
d358aa9a
GR		 1690};
1691
1692I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1693
1694/* Restart Auto-Negotiation (direct 0x605) */
1695struct i40e_aqc_set_link_restart_an {
8c570dcc
JK		 1696 u8 command;
1697#define I40E_AQ_PHY_RESTART_AN 0x02
1698#define I40E_AQ_PHY_LINK_ENABLE 0x04
1699 u8 reserved[15];
d358aa9a
GR		 1700};
1701
1702I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1703
1704/* Get Link Status cmd & response data structure (direct 0x0607) */
1705struct i40e_aqc_get_link_status {
8c570dcc
JK		 1706 __le16 command_flags; /* only field set on command */
1707#define I40E_AQ_LSE_MASK 0x3
1708#define I40E_AQ_LSE_NOP 0x0
1709#define I40E_AQ_LSE_DISABLE 0x2
1710#define I40E_AQ_LSE_ENABLE 0x3
d358aa9a 1711/* only response uses this flag */
8c570dcc
JK		 1712#define I40E_AQ_LSE_IS_ENABLED 0x1
1713 u8 phy_type; /* i40e_aq_phy_type */
1714 u8 link_speed; /* i40e_aq_link_speed */
1715 u8 link_info;
1716#define I40E_AQ_LINK_UP 0x01
1717#define I40E_AQ_LINK_FAULT 0x02
1718#define I40E_AQ_LINK_FAULT_TX 0x04
1719#define I40E_AQ_LINK_FAULT_RX 0x08
1720#define I40E_AQ_LINK_FAULT_REMOTE 0x10
1721#define I40E_AQ_MEDIA_AVAILABLE 0x40
1722#define I40E_AQ_SIGNAL_DETECT 0x80
1723 u8 an_info;
1724#define I40E_AQ_AN_COMPLETED 0x01
1725#define I40E_AQ_LP_AN_ABILITY 0x02
1726#define I40E_AQ_PD_FAULT 0x04
1727#define I40E_AQ_FEC_EN 0x08
1728#define I40E_AQ_PHY_LOW_POWER 0x10
1729#define I40E_AQ_LINK_PAUSE_TX 0x20
1730#define I40E_AQ_LINK_PAUSE_RX 0x40
1731#define I40E_AQ_QUALIFIED_MODULE 0x80
1732 u8 ext_info;
1733#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1734#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1735#define I40E_AQ_LINK_TX_SHIFT 0x02
1736#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1737#define I40E_AQ_LINK_TX_ACTIVE 0x00
1738#define I40E_AQ_LINK_TX_DRAINED 0x01
1739#define I40E_AQ_LINK_TX_FLUSHED 0x03
1740#define I40E_AQ_LINK_FORCED_40G 0x10
1741 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1742 __le16 max_frame_size;
1743 u8 config;
1744#define I40E_AQ_CONFIG_CRC_ENA 0x04
1745#define I40E_AQ_CONFIG_PACING_MASK 0x78
1746 u8 reserved[5];
d358aa9a
GR		 1747};
1748
1749I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1750
1751/* Set event mask command (direct 0x613) */
1752struct i40e_aqc_set_phy_int_mask {
8c570dcc
JK		 1753 u8 reserved[8];
1754 __le16 event_mask;
1755#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1756#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1757#define I40E_AQ_EVENT_LINK_FAULT 0x0008
1758#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1759#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1760#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1761#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1762#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1763#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1764 u8 reserved1[6];
d358aa9a
GR		 1765};
1766
1767I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1768
1769/* Get Local AN advt register (direct 0x0614)
1770 * Set Local AN advt register (direct 0x0615)
1771 * Get Link Partner AN advt register (direct 0x0616)
1772 */
1773struct i40e_aqc_an_advt_reg {
8c570dcc
JK		 1774 __le32 local_an_reg0;
1775 __le16 local_an_reg1;
1776 u8 reserved[10];
d358aa9a
GR		 1777};
1778
1779I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1780
1781/* Set Loopback mode (0x0618) */
1782struct i40e_aqc_set_lb_mode {
8c570dcc
JK		 1783 __le16 lb_mode;
1784#define I40E_AQ_LB_PHY_LOCAL 0x01
1785#define I40E_AQ_LB_PHY_REMOTE 0x02
1786#define I40E_AQ_LB_MAC_LOCAL 0x04
1787 u8 reserved[14];
d358aa9a
GR		 1788};
1789
1790I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1791
f94234ee
SN		 1792/* Set PHY Debug command (0x0622) */
1793struct i40e_aqc_set_phy_debug {
8c570dcc 1794 u8 command_flags;
f94234ee
SN		 1795#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1796#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1797#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1798 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1799#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1800#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1801#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1802#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
8c570dcc 1803 u8 reserved[15];
d358aa9a
GR		 1804};
1805
f94234ee 1806I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
d358aa9a
GR		 1807
1808enum i40e_aq_phy_reg_type {
8c570dcc
JK		 1809 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1810 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1811 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
d358aa9a
GR		 1812};
1813
1814/* NVM Read command (indirect 0x0701)
1815 * NVM Erase commands (direct 0x0702)
1816 * NVM Update commands (indirect 0x0703)
1817 */
1818struct i40e_aqc_nvm_update {
8c570dcc
JK		 1819 u8 command_flags;
1820#define I40E_AQ_NVM_LAST_CMD 0x01
1821#define I40E_AQ_NVM_FLASH_ONLY 0x80
1822 u8 module_pointer;
1823 __le16 length;
1824 __le32 offset;
1825 __le32 addr_high;
1826 __le32 addr_low;
d358aa9a
GR		 1827};
1828
1829I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1830
f94234ee
SN		 1831/* NVM Config Read (indirect 0x0704) */
1832struct i40e_aqc_nvm_config_read {
8c570dcc 1833 __le16 cmd_flags;
f94234ee
SN		 1834#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1835#define ANVM_READ_SINGLE_FEATURE 0
1836#define ANVM_READ_MULTIPLE_FEATURES 1
8c570dcc
JK		 1837 __le16 element_count;
1838 __le16 element_id; /* Feature/field ID */
1839 u8 reserved[2];
1840 __le32 address_high;
1841 __le32 address_low;
f94234ee
SN		 1842};
1843
1844I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1845
1846/* NVM Config Write (indirect 0x0705) */
1847struct i40e_aqc_nvm_config_write {
8c570dcc
JK		 1848 __le16 cmd_flags;
1849 __le16 element_count;
1850 u8 reserved[4];
1851 __le32 address_high;
1852 __le32 address_low;
f94234ee
SN		 1853};
1854
1855I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1856
1857struct i40e_aqc_nvm_config_data_feature {
1858 __le16 feature_id;
1859 __le16 instance_id;
1860 __le16 feature_options;
1861 __le16 feature_selection;
1862};
1863
1864struct i40e_aqc_nvm_config_data_immediate_field {
1865#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2
1866 __le16 field_id;
1867 __le16 instance_id;
1868 __le16 field_options;
1869 __le16 field_value;
1870};
1871
d358aa9a
GR		 1872/* Send to PF command (indirect 0x0801) id is only used by PF
1873 * Send to VF command (indirect 0x0802) id is only used by PF
1874 * Send to Peer PF command (indirect 0x0803)
1875 */
1876struct i40e_aqc_pf_vf_message {
8c570dcc
JK		 1877 __le32 id;
1878 u8 reserved[4];
1879 __le32 addr_high;
1880 __le32 addr_low;
d358aa9a
GR		 1881};
1882
1883I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1884
1885/* Alternate structure */
1886
1887/* Direct write (direct 0x0900)
1888 * Direct read (direct 0x0902)
1889 */
1890struct i40e_aqc_alternate_write {
1891 __le32 address0;
1892 __le32 data0;
1893 __le32 address1;
1894 __le32 data1;
1895};
1896
1897I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1898
1899/* Indirect write (indirect 0x0901)
1900 * Indirect read (indirect 0x0903)
1901 */
1902
1903struct i40e_aqc_alternate_ind_write {
1904 __le32 address;
1905 __le32 length;
1906 __le32 addr_high;
1907 __le32 addr_low;
1908};
1909
1910I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1911
1912/* Done alternate write (direct 0x0904)
1913 * uses i40e_aq_desc
1914 */
1915struct i40e_aqc_alternate_write_done {
8c570dcc 1916 __le16 cmd_flags;
d358aa9a
GR		 1917#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1918#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1919#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1920#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
8c570dcc 1921 u8 reserved[14];
d358aa9a
GR		 1922};
1923
1924I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1925
1926/* Set OEM mode (direct 0x0905) */
1927struct i40e_aqc_alternate_set_mode {
8c570dcc 1928 __le32 mode;
d358aa9a
GR		 1929#define I40E_AQ_ALTERNATE_MODE_NONE 0
1930#define I40E_AQ_ALTERNATE_MODE_OEM 1
8c570dcc 1931 u8 reserved[12];
d358aa9a
GR		 1932};
1933
1934I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1935
1936/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1937
1938/* async events 0x10xx */
1939
1940/* Lan Queue Overflow Event (direct, 0x1001) */
1941struct i40e_aqc_lan_overflow {
8c570dcc
JK		 1942 __le32 prtdcb_rupto;
1943 __le32 otx_ctl;
1944 u8 reserved[8];
d358aa9a
GR		 1945};
1946
1947I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1948
1949/* Get LLDP MIB (indirect 0x0A00) */
1950struct i40e_aqc_lldp_get_mib {
8c570dcc
JK		 1951 u8 type;
1952 u8 reserved1;
1953#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1954#define I40E_AQ_LLDP_MIB_LOCAL 0x0
1955#define I40E_AQ_LLDP_MIB_REMOTE 0x1
1956#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1957#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1958#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1959#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1960#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1961#define I40E_AQ_LLDP_TX_SHIFT 0x4
1962#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
d358aa9a 1963/* TX pause flags use I40E_AQ_LINK_TX_* above */
8c570dcc
JK		 1964 __le16 local_len;
1965 __le16 remote_len;
1966 u8 reserved2[2];
1967 __le32 addr_high;
1968 __le32 addr_low;
d358aa9a
GR		 1969};
1970
1971I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1972
1973/* Configure LLDP MIB Change Event (direct 0x0A01)
1974 * also used for the event (with type in the command field)
1975 */
1976struct i40e_aqc_lldp_update_mib {
8c570dcc
JK		 1977 u8 command;
1978#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1979#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1980 u8 reserved[7];
1981 __le32 addr_high;
1982 __le32 addr_low;
d358aa9a
GR		 1983};
1984
1985I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1986
1987/* Add LLDP TLV (indirect 0x0A02)
1988 * Delete LLDP TLV (indirect 0x0A04)
1989 */
1990struct i40e_aqc_lldp_add_tlv {
8c570dcc
JK		 1991 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1992 u8 reserved1[1];
1993 __le16 len;
1994 u8 reserved2[4];
1995 __le32 addr_high;
1996 __le32 addr_low;
d358aa9a
GR		 1997};
1998
1999I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2000
2001/* Update LLDP TLV (indirect 0x0A03) */
2002struct i40e_aqc_lldp_update_tlv {
8c570dcc
JK		 2003 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2004 u8 reserved;
2005 __le16 old_len;
2006 __le16 new_offset;
2007 __le16 new_len;
2008 __le32 addr_high;
2009 __le32 addr_low;
d358aa9a
GR		 2010};
2011
2012I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2013
2014/* Stop LLDP (direct 0x0A05) */
2015struct i40e_aqc_lldp_stop {
8c570dcc
JK		 2016 u8 command;
2017#define I40E_AQ_LLDP_AGENT_STOP 0x0
2018#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2019 u8 reserved[15];
d358aa9a
GR		 2020};
2021
2022I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2023
2024/* Start LLDP (direct 0x0A06) */
2025
2026struct i40e_aqc_lldp_start {
8c570dcc
JK		 2027 u8 command;
2028#define I40E_AQ_LLDP_AGENT_START 0x1
2029 u8 reserved[15];
d358aa9a
GR		 2030};
2031
2032I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2033
2034/* Apply MIB changes (0x0A07)
2035 * uses the generic struc as it contains no data
2036 */
2037
2038/* Add Udp Tunnel command and completion (direct 0x0B00) */
2039struct i40e_aqc_add_udp_tunnel {
8c570dcc
JK		 2040 __le16 udp_port;
2041 u8 reserved0[3];
2042 u8 protocol_type;
9774dd8d
SN		 2043#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2044#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2045#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
8c570dcc 2046 u8 reserved1[10];
d358aa9a
GR		 2047};
2048
2049I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2050
2051struct i40e_aqc_add_udp_tunnel_completion {
2052 __le16 udp_port;
2053 u8 filter_entry_index;
2054 u8 multiple_pfs;
8c570dcc
JK		 2055#define I40E_AQC_SINGLE_PF 0x0
2056#define I40E_AQC_MULTIPLE_PFS 0x1
d358aa9a
GR		 2057 u8 total_filters;
2058 u8 reserved[11];
2059};
2060
2061I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2062
2063/* remove UDP Tunnel command (0x0B01) */
2064struct i40e_aqc_remove_udp_tunnel {
8c570dcc
JK		 2065 u8 reserved[2];
2066 u8 index; /* 0 to 15 */
2067 u8 reserved2[13];
d358aa9a
GR		 2068};
2069
2070I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2071
2072struct i40e_aqc_del_udp_tunnel_completion {
8c570dcc
JK		 2073 __le16 udp_port;
2074 u8 index; /* 0 to 15 */
2075 u8 multiple_pfs;
2076 u8 total_filters_used;
2077 u8 reserved1[11];
d358aa9a
GR		 2078};
2079
2080I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2081
2082/* tunnel key structure 0x0B10 */
2083
90327e7d
GR		 2084struct i40e_aqc_tunnel_key_structure_A0 {
2085 __le16 key1_off;
2086 __le16 key1_len;
2087 __le16 key2_off;
2088 __le16 key2_len;
2089 __le16 flags;
2090#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2091/* response flags */
2092#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2093#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2094#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2095 u8 resreved[6];
2096};
2097
2098I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2099
d358aa9a
GR		 2100struct i40e_aqc_tunnel_key_structure {
2101 u8 key1_off;
2102 u8 key2_off;
2103 u8 key1_len; /* 0 to 15 */
2104 u8 key2_len; /* 0 to 15 */
2105 u8 flags;
8c570dcc 2106#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
d358aa9a 2107/* response flags */
8c570dcc
JK		 2108#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2109#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2110#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
d358aa9a
GR		 2111 u8 network_key_index;
2112#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2113#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2114#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2115#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2116 u8 reserved[10];
2117};
2118
2119I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2120
2121/* OEM mode commands (direct 0xFE0x) */
2122struct i40e_aqc_oem_param_change {
8c570dcc
JK		 2123 __le32 param_type;
2124#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2125#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2126#define I40E_AQ_OEM_PARAM_MAC 2
2127 __le32 param_value1;
35155fe6
SN		 2128 __le16 param_value2;
2129 u8 reserved[6];
d358aa9a
GR		 2130};
2131
2132I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2133
2134struct i40e_aqc_oem_state_change {
8c570dcc
JK		 2135 __le32 state;
2136#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2137#define I40E_AQ_OEM_STATE_LINK_UP 0x1
2138 u8 reserved[12];
d358aa9a
GR		 2139};
2140
2141I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2142
2143/* debug commands */
2144
2145/* get device id (0xFF00) uses the generic structure */
2146
2147/* set test more (0xFF01, internal) */
2148
2149struct i40e_acq_set_test_mode {
8c570dcc
JK		 2150 u8 mode;
2151#define I40E_AQ_TEST_PARTIAL 0
2152#define I40E_AQ_TEST_FULL 1
2153#define I40E_AQ_TEST_NVM 2
2154 u8 reserved[3];
2155 u8 command;
2156#define I40E_AQ_TEST_OPEN 0
2157#define I40E_AQ_TEST_CLOSE 1
2158#define I40E_AQ_TEST_INC 2
2159 u8 reserved2[3];
2160 __le32 address_high;
2161 __le32 address_low;
d358aa9a
GR		 2162};
2163
2164I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2165
2166/* Debug Read Register command (0xFF03)
2167 * Debug Write Register command (0xFF04)
2168 */
2169struct i40e_aqc_debug_reg_read_write {
2170 __le32 reserved;
2171 __le32 address;
2172 __le32 value_high;
2173 __le32 value_low;
2174};
2175
2176I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2177
2178/* Scatter/gather Reg Read (indirect 0xFF05)
2179 * Scatter/gather Reg Write (indirect 0xFF06)
2180 */
2181
2182/* i40e_aq_desc is used for the command */
2183struct i40e_aqc_debug_reg_sg_element_data {
2184 __le32 address;
2185 __le32 value;
2186};
2187
2188/* Debug Modify register (direct 0xFF07) */
2189struct i40e_aqc_debug_modify_reg {
2190 __le32 address;
2191 __le32 value;
2192 __le32 clear_mask;
2193 __le32 set_mask;
2194};
2195
2196I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2197
2198/* dump internal data (0xFF08, indirect) */
2199
2200#define I40E_AQ_CLUSTER_ID_AUX 0
2201#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2202#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2203#define I40E_AQ_CLUSTER_ID_HMC 3
2204#define I40E_AQ_CLUSTER_ID_MAC0 4
2205#define I40E_AQ_CLUSTER_ID_MAC1 5
2206#define I40E_AQ_CLUSTER_ID_MAC2 6
2207#define I40E_AQ_CLUSTER_ID_MAC3 7
2208#define I40E_AQ_CLUSTER_ID_DCB 8
2209#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2210#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2211#define I40E_AQ_CLUSTER_ID_ALTRAM 11
2212
2213struct i40e_aqc_debug_dump_internals {
8c570dcc
JK		 2214 u8 cluster_id;
2215 u8 table_id;
2216 __le16 data_size;
2217 __le32 idx;
2218 __le32 address_high;
2219 __le32 address_low;
d358aa9a
GR		 2220};
2221
2222I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2223
2224struct i40e_aqc_debug_modify_internals {
8c570dcc
JK		 2225 u8 cluster_id;
2226 u8 cluster_specific_params[7];
2227 __le32 address_high;
2228 __le32 address_low;
d358aa9a
GR		 2229};
2230
2231I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2232
2233#endif
Linux kernel - Deliverables
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