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d358aa9a GR |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver | |
b831607d | 4 | * Copyright(c) 2013 - 2014 Intel Corporation. |
d358aa9a GR |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
b831607d JB |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
d358aa9a GR |
18 | * The full GNU General Public License is included in this distribution in |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
27 | #ifndef _I40E_REGISTER_H_ | |
28 | #define _I40E_REGISTER_H_ | |
29 | ||
4c33f83a | 30 | #define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ |
d358aa9a GR |
31 | #define I40E_VFMSIX_PBA1_MAX_INDEX 19 |
32 | #define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0 | |
4c33f83a ASJ |
33 | #define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT) |
34 | #define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ | |
d358aa9a GR |
35 | #define I40E_VFMSIX_TADD1_MAX_INDEX 639 |
36 | #define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0 | |
4c33f83a | 37 | #define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT) |
d358aa9a | 38 | #define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2 |
4c33f83a ASJ |
39 | #define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT) |
40 | #define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ | |
d358aa9a GR |
41 | #define I40E_VFMSIX_TMSG1_MAX_INDEX 639 |
42 | #define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0 | |
4c33f83a ASJ |
43 | #define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT) |
44 | #define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ | |
d358aa9a GR |
45 | #define I40E_VFMSIX_TUADD1_MAX_INDEX 639 |
46 | #define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0 | |
4c33f83a ASJ |
47 | #define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT) |
48 | #define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ | |
d358aa9a GR |
49 | #define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639 |
50 | #define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0 | |
4c33f83a | 51 | #define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT) |
4c33f83a | 52 | #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ |
d358aa9a | 53 | #define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0 |
4c33f83a ASJ |
54 | #define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT) |
55 | #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ | |
d358aa9a | 56 | #define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0 |
4c33f83a ASJ |
57 | #define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT) |
58 | #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ | |
d358aa9a | 59 | #define I40E_VF_ARQH1_ARQH_SHIFT 0 |
4c33f83a ASJ |
60 | #define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT) |
61 | #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ | |
d358aa9a | 62 | #define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0 |
4c33f83a | 63 | #define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) |
d358aa9a | 64 | #define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 |
4c33f83a | 65 | #define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) |
d358aa9a | 66 | #define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 |
4c33f83a | 67 | #define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT) |
d358aa9a | 68 | #define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 |
4c33f83a | 69 | #define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT) |
d358aa9a | 70 | #define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 |
4c33f83a ASJ |
71 | #define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) |
72 | #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ | |
d358aa9a | 73 | #define I40E_VF_ARQT1_ARQT_SHIFT 0 |
4c33f83a ASJ |
74 | #define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) |
75 | #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ | |
d358aa9a | 76 | #define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 |
4c33f83a ASJ |
77 | #define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) |
78 | #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ | |
d358aa9a | 79 | #define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 |
4c33f83a ASJ |
80 | #define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT) |
81 | #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ | |
d358aa9a | 82 | #define I40E_VF_ATQH1_ATQH_SHIFT 0 |
4c33f83a ASJ |
83 | #define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT) |
84 | #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ | |
d358aa9a | 85 | #define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0 |
4c33f83a | 86 | #define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) |
d358aa9a | 87 | #define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 |
4c33f83a | 88 | #define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) |
d358aa9a | 89 | #define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 |
4c33f83a | 90 | #define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT) |
d358aa9a | 91 | #define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 |
4c33f83a | 92 | #define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT) |
d358aa9a | 93 | #define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 |
4c33f83a ASJ |
94 | #define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) |
95 | #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ | |
d358aa9a | 96 | #define I40E_VF_ATQT1_ATQT_SHIFT 0 |
4c33f83a ASJ |
97 | #define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) |
98 | #define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ | |
d358aa9a | 99 | #define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 |
4c33f83a ASJ |
100 | #define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) |
101 | #define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ | |
d358aa9a | 102 | #define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 |
4c33f83a | 103 | #define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT) |
d358aa9a | 104 | #define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1 |
4c33f83a | 105 | #define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT) |
d358aa9a | 106 | #define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 |
4c33f83a | 107 | #define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT) |
d358aa9a | 108 | #define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 |
4c33f83a | 109 | #define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
d358aa9a | 110 | #define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5 |
4c33f83a | 111 | #define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT) |
d358aa9a | 112 | #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 |
4c33f83a | 113 | #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) |
d358aa9a | 114 | #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 |
4c33f83a | 115 | #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) |
d358aa9a | 116 | #define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 |
4c33f83a ASJ |
117 | #define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT) |
118 | #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ | |
d358aa9a GR |
119 | #define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15 |
120 | #define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 | |
4c33f83a | 121 | #define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) |
d358aa9a | 122 | #define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 |
4c33f83a | 123 | #define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT) |
d358aa9a | 124 | #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 |
4c33f83a | 125 | #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) |
d358aa9a | 126 | #define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 |
4c33f83a | 127 | #define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
d358aa9a | 128 | #define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 |
4c33f83a | 129 | #define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT) |
d358aa9a | 130 | #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 |
4c33f83a | 131 | #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) |
d358aa9a | 132 | #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 |
4c33f83a | 133 | #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) |
d358aa9a | 134 | #define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 |
4c33f83a ASJ |
135 | #define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT) |
136 | #define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ | |
d358aa9a | 137 | #define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 |
4c33f83a | 138 | #define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) |
d358aa9a | 139 | #define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 |
4c33f83a | 140 | #define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) |
d358aa9a | 141 | #define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 |
4c33f83a ASJ |
142 | #define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT) |
143 | #define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */ | |
d358aa9a | 144 | #define I40E_VFINT_ICR01_INTEVENT_SHIFT 0 |
4c33f83a | 145 | #define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT) |
d358aa9a | 146 | #define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1 |
4c33f83a | 147 | #define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT) |
d358aa9a | 148 | #define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2 |
4c33f83a | 149 | #define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT) |
d358aa9a | 150 | #define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3 |
4c33f83a | 151 | #define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT) |
d358aa9a | 152 | #define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4 |
4c33f83a | 153 | #define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT) |
d358aa9a | 154 | #define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 |
4c33f83a | 155 | #define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT) |
d358aa9a | 156 | #define I40E_VFINT_ICR01_ADMINQ_SHIFT 30 |
4c33f83a | 157 | #define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT) |
d358aa9a | 158 | #define I40E_VFINT_ICR01_SWINT_SHIFT 31 |
4c33f83a ASJ |
159 | #define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT) |
160 | #define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ | |
d358aa9a GR |
161 | #define I40E_VFINT_ITR01_MAX_INDEX 2 |
162 | #define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 | |
4c33f83a ASJ |
163 | #define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT) |
164 | #define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ | |
d358aa9a GR |
165 | #define I40E_VFINT_ITRN1_MAX_INDEX 2 |
166 | #define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 | |
4c33f83a | 167 | #define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT) |
5098850c | 168 | #define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ |
d358aa9a | 169 | #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 |
4c33f83a ASJ |
170 | #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) |
171 | #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ | |
d358aa9a GR |
172 | #define I40E_QRX_TAIL1_MAX_INDEX 15 |
173 | #define I40E_QRX_TAIL1_TAIL_SHIFT 0 | |
4c33f83a ASJ |
174 | #define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT) |
175 | #define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ | |
d358aa9a GR |
176 | #define I40E_QTX_TAIL1_MAX_INDEX 15 |
177 | #define I40E_QTX_TAIL1_TAIL_SHIFT 0 | |
4c33f83a ASJ |
178 | #define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT) |
179 | #define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */ | |
d358aa9a | 180 | #define I40E_VFMSIX_PBA_PENBIT_SHIFT 0 |
4c33f83a ASJ |
181 | #define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT) |
182 | #define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ | |
d358aa9a GR |
183 | #define I40E_VFMSIX_TADD_MAX_INDEX 16 |
184 | #define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0 | |
4c33f83a | 185 | #define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT) |
d358aa9a | 186 | #define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2 |
4c33f83a ASJ |
187 | #define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT) |
188 | #define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ | |
d358aa9a GR |
189 | #define I40E_VFMSIX_TMSG_MAX_INDEX 16 |
190 | #define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0 | |
4c33f83a ASJ |
191 | #define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT) |
192 | #define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ | |
d358aa9a GR |
193 | #define I40E_VFMSIX_TUADD_MAX_INDEX 16 |
194 | #define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0 | |
4c33f83a ASJ |
195 | #define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT) |
196 | #define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ | |
d358aa9a GR |
197 | #define I40E_VFMSIX_TVCTRL_MAX_INDEX 16 |
198 | #define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0 | |
4c33f83a ASJ |
199 | #define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT) |
200 | #define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */ | |
d358aa9a | 201 | #define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 |
4c33f83a | 202 | #define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT) |
d358aa9a | 203 | #define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 |
4c33f83a | 204 | #define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT) |
d358aa9a | 205 | #define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8 |
4c33f83a ASJ |
206 | #define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT) |
207 | #define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */ | |
d358aa9a | 208 | #define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 |
4c33f83a | 209 | #define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT) |
d358aa9a | 210 | #define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 |
4c33f83a | 211 | #define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT) |
d358aa9a | 212 | #define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 |
4c33f83a | 213 | #define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) |
d358aa9a | 214 | #define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 |
4c33f83a | 215 | #define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) |
d358aa9a | 216 | #define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 |
4c33f83a ASJ |
217 | #define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) |
218 | #define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ | |
d358aa9a GR |
219 | #define I40E_VFQF_HENA_MAX_INDEX 1 |
220 | #define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0 | |
4c33f83a ASJ |
221 | #define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT) |
222 | #define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ | |
d358aa9a GR |
223 | #define I40E_VFQF_HKEY_MAX_INDEX 12 |
224 | #define I40E_VFQF_HKEY_KEY_0_SHIFT 0 | |
4c33f83a | 225 | #define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT) |
d358aa9a | 226 | #define I40E_VFQF_HKEY_KEY_1_SHIFT 8 |
4c33f83a | 227 | #define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT) |
d358aa9a | 228 | #define I40E_VFQF_HKEY_KEY_2_SHIFT 16 |
4c33f83a | 229 | #define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT) |
d358aa9a | 230 | #define I40E_VFQF_HKEY_KEY_3_SHIFT 24 |
4c33f83a ASJ |
231 | #define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT) |
232 | #define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ | |
d358aa9a GR |
233 | #define I40E_VFQF_HLUT_MAX_INDEX 15 |
234 | #define I40E_VFQF_HLUT_LUT0_SHIFT 0 | |
4c33f83a | 235 | #define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT) |
d358aa9a | 236 | #define I40E_VFQF_HLUT_LUT1_SHIFT 8 |
4c33f83a | 237 | #define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT) |
d358aa9a | 238 | #define I40E_VFQF_HLUT_LUT2_SHIFT 16 |
4c33f83a | 239 | #define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT) |
d358aa9a | 240 | #define I40E_VFQF_HLUT_LUT3_SHIFT 24 |
4c33f83a ASJ |
241 | #define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT) |
242 | #define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */ | |
d358aa9a GR |
243 | #define I40E_VFQF_HREGION_MAX_INDEX 7 |
244 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 | |
4c33f83a | 245 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT) |
d358aa9a | 246 | #define I40E_VFQF_HREGION_REGION_0_SHIFT 1 |
4c33f83a | 247 | #define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT) |
d358aa9a | 248 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 |
4c33f83a | 249 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT) |
d358aa9a | 250 | #define I40E_VFQF_HREGION_REGION_1_SHIFT 5 |
4c33f83a | 251 | #define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT) |
d358aa9a | 252 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 |
4c33f83a | 253 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT) |
d358aa9a | 254 | #define I40E_VFQF_HREGION_REGION_2_SHIFT 9 |
4c33f83a | 255 | #define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT) |
d358aa9a | 256 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 |
4c33f83a | 257 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT) |
d358aa9a | 258 | #define I40E_VFQF_HREGION_REGION_3_SHIFT 13 |
4c33f83a | 259 | #define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT) |
d358aa9a | 260 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 |
4c33f83a | 261 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT) |
d358aa9a | 262 | #define I40E_VFQF_HREGION_REGION_4_SHIFT 17 |
4c33f83a | 263 | #define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT) |
d358aa9a | 264 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 |
4c33f83a | 265 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT) |
d358aa9a | 266 | #define I40E_VFQF_HREGION_REGION_5_SHIFT 21 |
4c33f83a | 267 | #define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT) |
d358aa9a | 268 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 |
4c33f83a | 269 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) |
d358aa9a | 270 | #define I40E_VFQF_HREGION_REGION_6_SHIFT 25 |
4c33f83a | 271 | #define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT) |
d358aa9a | 272 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 |
4c33f83a | 273 | #define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) |
d358aa9a | 274 | #define I40E_VFQF_HREGION_REGION_7_SHIFT 29 |
4c33f83a | 275 | #define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT) |
da48c9a2 ASJ |
276 | #define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30 |
277 | #define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT) | |
278 | #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30 | |
279 | #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT) | |
280 | #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ | |
281 | #define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0 | |
282 | #define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT) | |
283 | #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ | |
284 | #define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0 | |
285 | #define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT) | |
286 | #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ | |
287 | #define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0 | |
288 | #define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT) | |
289 | #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ | |
290 | #define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0 | |
291 | #define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT) | |
292 | #define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4 | |
293 | #define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT) | |
294 | #define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16 | |
295 | #define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT) | |
296 | #define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31 | |
297 | #define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT) | |
298 | #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ | |
299 | #define I40E_VFPE_CQACK1_PECQID_SHIFT 0 | |
300 | #define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT) | |
301 | #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ | |
302 | #define I40E_VFPE_CQARM1_PECQID_SHIFT 0 | |
303 | #define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT) | |
304 | #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ | |
305 | #define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0 | |
306 | #define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT) | |
307 | #define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ | |
308 | #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0 | |
309 | #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT) | |
310 | #define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16 | |
311 | #define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT) | |
312 | #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ | |
313 | #define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0 | |
314 | #define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT) | |
315 | #define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31 | |
316 | #define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT) | |
317 | #define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ | |
318 | #define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0 | |
319 | #define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT) | |
320 | #define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16 | |
321 | #define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT) | |
322 | #define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ | |
323 | #define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0 | |
324 | #define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT) | |
325 | #define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ | |
326 | #define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0 | |
327 | #define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT) | |
328 | #define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ | |
329 | #define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0 | |
330 | #define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT) | |
331 | #define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */ | |
332 | #define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0 | |
333 | #define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT) | |
334 | #define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20 | |
335 | #define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT) | |
336 | #endif /* _I40E_REGISTER_H_ */ |