Commit | Line | Data |
---|---|---|
7f12ad74 GR |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver | |
ecc6a239 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
7f12ad74 GR |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
b831607d JB |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
7f12ad74 GR |
18 | * The full GNU General Public License is included in this distribution in |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
7ed3f5f0 | 27 | #include <linux/prefetch.h> |
a132af24 | 28 | #include <net/busy_poll.h> |
7ed3f5f0 | 29 | |
7f12ad74 | 30 | #include "i40evf.h" |
206812b5 | 31 | #include "i40e_prototype.h" |
7f12ad74 GR |
32 | |
33 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
34 | u32 td_tag) | |
35 | { | |
36 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
37 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
38 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
39 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
40 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
41 | } | |
42 | ||
43 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) | |
44 | ||
45 | /** | |
46 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer | |
47 | * @ring: the ring that owns the buffer | |
48 | * @tx_buffer: the buffer to free | |
49 | **/ | |
50 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, | |
51 | struct i40e_tx_buffer *tx_buffer) | |
52 | { | |
53 | if (tx_buffer->skb) { | |
a42e7a36 | 54 | dev_kfree_skb_any(tx_buffer->skb); |
7f12ad74 GR |
55 | if (dma_unmap_len(tx_buffer, len)) |
56 | dma_unmap_single(ring->dev, | |
57 | dma_unmap_addr(tx_buffer, dma), | |
58 | dma_unmap_len(tx_buffer, len), | |
59 | DMA_TO_DEVICE); | |
60 | } else if (dma_unmap_len(tx_buffer, len)) { | |
61 | dma_unmap_page(ring->dev, | |
62 | dma_unmap_addr(tx_buffer, dma), | |
63 | dma_unmap_len(tx_buffer, len), | |
64 | DMA_TO_DEVICE); | |
65 | } | |
a42e7a36 KP |
66 | |
67 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) | |
68 | kfree(tx_buffer->raw_buf); | |
69 | ||
7f12ad74 GR |
70 | tx_buffer->next_to_watch = NULL; |
71 | tx_buffer->skb = NULL; | |
72 | dma_unmap_len_set(tx_buffer, len, 0); | |
73 | /* tx_buffer must be completely set up in the transmit path */ | |
74 | } | |
75 | ||
76 | /** | |
77 | * i40evf_clean_tx_ring - Free any empty Tx buffers | |
78 | * @tx_ring: ring to be cleaned | |
79 | **/ | |
80 | void i40evf_clean_tx_ring(struct i40e_ring *tx_ring) | |
81 | { | |
82 | unsigned long bi_size; | |
83 | u16 i; | |
84 | ||
85 | /* ring already cleared, nothing to do */ | |
86 | if (!tx_ring->tx_bi) | |
87 | return; | |
88 | ||
89 | /* Free all the Tx ring sk_buffs */ | |
90 | for (i = 0; i < tx_ring->count; i++) | |
91 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
92 | ||
93 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
94 | memset(tx_ring->tx_bi, 0, bi_size); | |
95 | ||
96 | /* Zero out the descriptor ring */ | |
97 | memset(tx_ring->desc, 0, tx_ring->size); | |
98 | ||
99 | tx_ring->next_to_use = 0; | |
100 | tx_ring->next_to_clean = 0; | |
101 | ||
102 | if (!tx_ring->netdev) | |
103 | return; | |
104 | ||
105 | /* cleanup Tx queue statistics */ | |
106 | netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, | |
107 | tx_ring->queue_index)); | |
108 | } | |
109 | ||
110 | /** | |
111 | * i40evf_free_tx_resources - Free Tx resources per queue | |
112 | * @tx_ring: Tx descriptor ring for a specific queue | |
113 | * | |
114 | * Free all transmit software resources | |
115 | **/ | |
116 | void i40evf_free_tx_resources(struct i40e_ring *tx_ring) | |
117 | { | |
118 | i40evf_clean_tx_ring(tx_ring); | |
119 | kfree(tx_ring->tx_bi); | |
120 | tx_ring->tx_bi = NULL; | |
121 | ||
122 | if (tx_ring->desc) { | |
123 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
124 | tx_ring->desc, tx_ring->dma); | |
125 | tx_ring->desc = NULL; | |
126 | } | |
127 | } | |
128 | ||
a68de58d | 129 | /** |
9c6c1259 KP |
130 | * i40evf_get_tx_pending - how many Tx descriptors not processed |
131 | * @tx_ring: the ring of descriptors | |
dd353109 | 132 | * @in_sw: is tx_pending being checked in SW or HW |
a68de58d | 133 | * |
9c6c1259 KP |
134 | * Since there is no access to the ring head register |
135 | * in XL710, we need to use our local copies | |
a68de58d | 136 | **/ |
dd353109 | 137 | u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw) |
a68de58d | 138 | { |
9c6c1259 | 139 | u32 head, tail; |
a68de58d | 140 | |
dd353109 ASJ |
141 | if (!in_sw) |
142 | head = i40e_get_head(ring); | |
143 | else | |
144 | head = ring->next_to_clean; | |
9c6c1259 KP |
145 | tail = readl(ring->tail); |
146 | ||
147 | if (head != tail) | |
148 | return (head < tail) ? | |
149 | tail - head : (tail + ring->count - head); | |
150 | ||
151 | return 0; | |
a68de58d JB |
152 | } |
153 | ||
c29af37f ASJ |
154 | #define WB_STRIDE 0x3 |
155 | ||
7f12ad74 GR |
156 | /** |
157 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
a619afe8 AD |
158 | * @vsi: the VSI we care about |
159 | * @tx_ring: Tx ring to clean | |
160 | * @napi_budget: Used to determine if we are in netpoll | |
7f12ad74 GR |
161 | * |
162 | * Returns true if there's any budget left (e.g. the clean is finished) | |
163 | **/ | |
a619afe8 AD |
164 | static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, |
165 | struct i40e_ring *tx_ring, int napi_budget) | |
7f12ad74 GR |
166 | { |
167 | u16 i = tx_ring->next_to_clean; | |
168 | struct i40e_tx_buffer *tx_buf; | |
1943d8ba | 169 | struct i40e_tx_desc *tx_head; |
7f12ad74 | 170 | struct i40e_tx_desc *tx_desc; |
a619afe8 AD |
171 | unsigned int total_bytes = 0, total_packets = 0; |
172 | unsigned int budget = vsi->work_limit; | |
7f12ad74 GR |
173 | |
174 | tx_buf = &tx_ring->tx_bi[i]; | |
175 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
176 | i -= tx_ring->count; | |
177 | ||
1943d8ba JB |
178 | tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); |
179 | ||
7f12ad74 GR |
180 | do { |
181 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
182 | ||
183 | /* if next_to_watch is not set then there is no work pending */ | |
184 | if (!eop_desc) | |
185 | break; | |
186 | ||
187 | /* prevent any other reads prior to eop_desc */ | |
188 | read_barrier_depends(); | |
189 | ||
1943d8ba JB |
190 | /* we have caught up to head, no work left to do */ |
191 | if (tx_head == tx_desc) | |
7f12ad74 GR |
192 | break; |
193 | ||
194 | /* clear next_to_watch to prevent false hangs */ | |
195 | tx_buf->next_to_watch = NULL; | |
196 | ||
197 | /* update the statistics for this packet */ | |
198 | total_bytes += tx_buf->bytecount; | |
199 | total_packets += tx_buf->gso_segs; | |
200 | ||
201 | /* free the skb */ | |
a619afe8 | 202 | napi_consume_skb(tx_buf->skb, napi_budget); |
7f12ad74 GR |
203 | |
204 | /* unmap skb header data */ | |
205 | dma_unmap_single(tx_ring->dev, | |
206 | dma_unmap_addr(tx_buf, dma), | |
207 | dma_unmap_len(tx_buf, len), | |
208 | DMA_TO_DEVICE); | |
209 | ||
210 | /* clear tx_buffer data */ | |
211 | tx_buf->skb = NULL; | |
212 | dma_unmap_len_set(tx_buf, len, 0); | |
213 | ||
214 | /* unmap remaining buffers */ | |
215 | while (tx_desc != eop_desc) { | |
216 | ||
217 | tx_buf++; | |
218 | tx_desc++; | |
219 | i++; | |
220 | if (unlikely(!i)) { | |
221 | i -= tx_ring->count; | |
222 | tx_buf = tx_ring->tx_bi; | |
223 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
224 | } | |
225 | ||
226 | /* unmap any remaining paged data */ | |
227 | if (dma_unmap_len(tx_buf, len)) { | |
228 | dma_unmap_page(tx_ring->dev, | |
229 | dma_unmap_addr(tx_buf, dma), | |
230 | dma_unmap_len(tx_buf, len), | |
231 | DMA_TO_DEVICE); | |
232 | dma_unmap_len_set(tx_buf, len, 0); | |
233 | } | |
234 | } | |
235 | ||
236 | /* move us one more past the eop_desc for start of next pkt */ | |
237 | tx_buf++; | |
238 | tx_desc++; | |
239 | i++; | |
240 | if (unlikely(!i)) { | |
241 | i -= tx_ring->count; | |
242 | tx_buf = tx_ring->tx_bi; | |
243 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
244 | } | |
245 | ||
016890b9 JB |
246 | prefetch(tx_desc); |
247 | ||
7f12ad74 GR |
248 | /* update budget accounting */ |
249 | budget--; | |
250 | } while (likely(budget)); | |
251 | ||
252 | i += tx_ring->count; | |
253 | tx_ring->next_to_clean = i; | |
254 | u64_stats_update_begin(&tx_ring->syncp); | |
255 | tx_ring->stats.bytes += total_bytes; | |
256 | tx_ring->stats.packets += total_packets; | |
257 | u64_stats_update_end(&tx_ring->syncp); | |
258 | tx_ring->q_vector->tx.total_bytes += total_bytes; | |
259 | tx_ring->q_vector->tx.total_packets += total_packets; | |
260 | ||
f6d83d13 ASJ |
261 | if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { |
262 | unsigned int j = 0; | |
263 | /* check to see if there are < 4 descriptors | |
264 | * waiting to be written back, then kick the hardware to force | |
265 | * them to be written back in case we stay in NAPI. | |
266 | * In this mode on X722 we do not enable Interrupt. | |
267 | */ | |
dd353109 | 268 | j = i40evf_get_tx_pending(tx_ring, false); |
f6d83d13 ASJ |
269 | |
270 | if (budget && | |
271 | ((j / (WB_STRIDE + 1)) == 0) && (j > 0) && | |
a619afe8 | 272 | !test_bit(__I40E_DOWN, &vsi->state) && |
f6d83d13 ASJ |
273 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) |
274 | tx_ring->arm_wb = true; | |
275 | } | |
276 | ||
7f12ad74 GR |
277 | netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev, |
278 | tx_ring->queue_index), | |
279 | total_packets, total_bytes); | |
280 | ||
281 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) | |
282 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
283 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
284 | /* Make sure that anybody stopping the queue after this | |
285 | * sees the new next_to_clean. | |
286 | */ | |
287 | smp_mb(); | |
288 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
289 | tx_ring->queue_index) && | |
a619afe8 | 290 | !test_bit(__I40E_DOWN, &vsi->state)) { |
7f12ad74 GR |
291 | netif_wake_subqueue(tx_ring->netdev, |
292 | tx_ring->queue_index); | |
293 | ++tx_ring->tx_stats.restart_queue; | |
294 | } | |
295 | } | |
296 | ||
b03a8c1f | 297 | return !!budget; |
7f12ad74 GR |
298 | } |
299 | ||
c29af37f | 300 | /** |
ecc6a239 | 301 | * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled |
c29af37f | 302 | * @vsi: the VSI we care about |
ecc6a239 | 303 | * @q_vector: the vector on which to enable writeback |
c29af37f ASJ |
304 | * |
305 | **/ | |
ecc6a239 ASJ |
306 | static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, |
307 | struct i40e_q_vector *q_vector) | |
c29af37f | 308 | { |
8e0764b4 | 309 | u16 flags = q_vector->tx.ring[0].flags; |
ecc6a239 | 310 | u32 val; |
8e0764b4 | 311 | |
ecc6a239 ASJ |
312 | if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) |
313 | return; | |
314 | ||
315 | if (q_vector->arm_wb_state) | |
316 | return; | |
317 | ||
318 | val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK | | |
319 | I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */ | |
320 | ||
321 | wr32(&vsi->back->hw, | |
322 | I40E_VFINT_DYN_CTLN1(q_vector->v_idx + | |
323 | vsi->base_vector - 1), val); | |
324 | q_vector->arm_wb_state = true; | |
325 | } | |
326 | ||
327 | /** | |
328 | * i40evf_force_wb - Issue SW Interrupt so HW does a wb | |
329 | * @vsi: the VSI we care about | |
330 | * @q_vector: the vector on which to force writeback | |
331 | * | |
332 | **/ | |
333 | void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
334 | { | |
335 | u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK | | |
336 | I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */ | |
337 | I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK | | |
338 | I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK | |
339 | /* allow 00 to be written to the index */; | |
340 | ||
341 | wr32(&vsi->back->hw, | |
342 | I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1), | |
343 | val); | |
c29af37f ASJ |
344 | } |
345 | ||
7f12ad74 GR |
346 | /** |
347 | * i40e_set_new_dynamic_itr - Find new ITR level | |
348 | * @rc: structure containing ring performance data | |
349 | * | |
8f5e39ce JB |
350 | * Returns true if ITR changed, false if not |
351 | * | |
7f12ad74 GR |
352 | * Stores a new ITR value based on packets and byte counts during |
353 | * the last interrupt. The advantage of per interrupt computation | |
354 | * is faster updates and more accurate ITR for the current traffic | |
355 | * pattern. Constants in this function were computed based on | |
356 | * theoretical maximum wire speed and thresholds were set based on | |
357 | * testing data as well as attempting to minimize response time | |
358 | * while increasing bulk throughput. | |
359 | **/ | |
8f5e39ce | 360 | static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) |
7f12ad74 GR |
361 | { |
362 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
c56625d5 | 363 | struct i40e_q_vector *qv = rc->ring->q_vector; |
7f12ad74 GR |
364 | u32 new_itr = rc->itr; |
365 | int bytes_per_int; | |
51cc6d9f | 366 | int usecs; |
7f12ad74 GR |
367 | |
368 | if (rc->total_packets == 0 || !rc->itr) | |
8f5e39ce | 369 | return false; |
7f12ad74 GR |
370 | |
371 | /* simple throttlerate management | |
c56625d5 | 372 | * 0-10MB/s lowest (50000 ints/s) |
7f12ad74 | 373 | * 10-20MB/s low (20000 ints/s) |
c56625d5 JB |
374 | * 20-1249MB/s bulk (18000 ints/s) |
375 | * > 40000 Rx packets per second (8000 ints/s) | |
51cc6d9f JB |
376 | * |
377 | * The math works out because the divisor is in 10^(-6) which | |
378 | * turns the bytes/us input value into MB/s values, but | |
379 | * make sure to use usecs, as the register values written | |
ee2319cf JB |
380 | * are in 2 usec increments in the ITR registers, and make sure |
381 | * to use the smoothed values that the countdown timer gives us. | |
7f12ad74 | 382 | */ |
ee2319cf | 383 | usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; |
51cc6d9f | 384 | bytes_per_int = rc->total_bytes / usecs; |
ee2319cf | 385 | |
de32e3ef | 386 | switch (new_latency_range) { |
7f12ad74 GR |
387 | case I40E_LOWEST_LATENCY: |
388 | if (bytes_per_int > 10) | |
389 | new_latency_range = I40E_LOW_LATENCY; | |
390 | break; | |
391 | case I40E_LOW_LATENCY: | |
392 | if (bytes_per_int > 20) | |
393 | new_latency_range = I40E_BULK_LATENCY; | |
394 | else if (bytes_per_int <= 10) | |
395 | new_latency_range = I40E_LOWEST_LATENCY; | |
396 | break; | |
397 | case I40E_BULK_LATENCY: | |
c56625d5 | 398 | case I40E_ULTRA_LATENCY: |
de32e3ef CW |
399 | default: |
400 | if (bytes_per_int <= 20) | |
401 | new_latency_range = I40E_LOW_LATENCY; | |
7f12ad74 GR |
402 | break; |
403 | } | |
c56625d5 JB |
404 | |
405 | /* this is to adjust RX more aggressively when streaming small | |
406 | * packets. The value of 40000 was picked as it is just beyond | |
407 | * what the hardware can receive per second if in low latency | |
408 | * mode. | |
409 | */ | |
410 | #define RX_ULTRA_PACKET_RATE 40000 | |
411 | ||
412 | if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && | |
413 | (&qv->rx == rc)) | |
414 | new_latency_range = I40E_ULTRA_LATENCY; | |
415 | ||
de32e3ef | 416 | rc->latency_range = new_latency_range; |
7f12ad74 GR |
417 | |
418 | switch (new_latency_range) { | |
419 | case I40E_LOWEST_LATENCY: | |
c56625d5 | 420 | new_itr = I40E_ITR_50K; |
7f12ad74 GR |
421 | break; |
422 | case I40E_LOW_LATENCY: | |
423 | new_itr = I40E_ITR_20K; | |
424 | break; | |
425 | case I40E_BULK_LATENCY: | |
c56625d5 JB |
426 | new_itr = I40E_ITR_18K; |
427 | break; | |
428 | case I40E_ULTRA_LATENCY: | |
7f12ad74 GR |
429 | new_itr = I40E_ITR_8K; |
430 | break; | |
431 | default: | |
432 | break; | |
433 | } | |
434 | ||
7f12ad74 GR |
435 | rc->total_bytes = 0; |
436 | rc->total_packets = 0; | |
8f5e39ce JB |
437 | |
438 | if (new_itr != rc->itr) { | |
439 | rc->itr = new_itr; | |
440 | return true; | |
441 | } | |
442 | ||
443 | return false; | |
7f12ad74 GR |
444 | } |
445 | ||
4eeb1fff | 446 | /** |
7f12ad74 GR |
447 | * i40evf_setup_tx_descriptors - Allocate the Tx descriptors |
448 | * @tx_ring: the tx ring to set up | |
449 | * | |
450 | * Return 0 on success, negative on error | |
451 | **/ | |
452 | int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
453 | { | |
454 | struct device *dev = tx_ring->dev; | |
455 | int bi_size; | |
456 | ||
457 | if (!dev) | |
458 | return -ENOMEM; | |
459 | ||
67c818a1 MW |
460 | /* warn if we are about to overwrite the pointer */ |
461 | WARN_ON(tx_ring->tx_bi); | |
7f12ad74 GR |
462 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; |
463 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
464 | if (!tx_ring->tx_bi) | |
465 | goto err; | |
466 | ||
467 | /* round up to nearest 4K */ | |
468 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
1943d8ba JB |
469 | /* add u32 for head writeback, align after this takes care of |
470 | * guaranteeing this is at least one cache line in size | |
471 | */ | |
472 | tx_ring->size += sizeof(u32); | |
7f12ad74 GR |
473 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
474 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
475 | &tx_ring->dma, GFP_KERNEL); | |
476 | if (!tx_ring->desc) { | |
477 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
478 | tx_ring->size); | |
479 | goto err; | |
480 | } | |
481 | ||
482 | tx_ring->next_to_use = 0; | |
483 | tx_ring->next_to_clean = 0; | |
484 | return 0; | |
485 | ||
486 | err: | |
487 | kfree(tx_ring->tx_bi); | |
488 | tx_ring->tx_bi = NULL; | |
489 | return -ENOMEM; | |
490 | } | |
491 | ||
492 | /** | |
493 | * i40evf_clean_rx_ring - Free Rx buffers | |
494 | * @rx_ring: ring to be cleaned | |
495 | **/ | |
496 | void i40evf_clean_rx_ring(struct i40e_ring *rx_ring) | |
497 | { | |
498 | struct device *dev = rx_ring->dev; | |
7f12ad74 GR |
499 | unsigned long bi_size; |
500 | u16 i; | |
501 | ||
502 | /* ring already cleared, nothing to do */ | |
503 | if (!rx_ring->rx_bi) | |
504 | return; | |
505 | ||
506 | /* Free all the Rx ring sk_buffs */ | |
507 | for (i = 0; i < rx_ring->count; i++) { | |
ab9ad98e JB |
508 | struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; |
509 | ||
7f12ad74 GR |
510 | if (rx_bi->skb) { |
511 | dev_kfree_skb(rx_bi->skb); | |
512 | rx_bi->skb = NULL; | |
513 | } | |
ab9ad98e JB |
514 | if (!rx_bi->page) |
515 | continue; | |
516 | ||
517 | dma_unmap_page(dev, rx_bi->dma, PAGE_SIZE, DMA_FROM_DEVICE); | |
518 | __free_pages(rx_bi->page, 0); | |
519 | ||
520 | rx_bi->page = NULL; | |
521 | rx_bi->page_offset = 0; | |
7f12ad74 GR |
522 | } |
523 | ||
524 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
525 | memset(rx_ring->rx_bi, 0, bi_size); | |
526 | ||
527 | /* Zero out the descriptor ring */ | |
528 | memset(rx_ring->desc, 0, rx_ring->size); | |
529 | ||
ab9ad98e | 530 | rx_ring->next_to_alloc = 0; |
7f12ad74 GR |
531 | rx_ring->next_to_clean = 0; |
532 | rx_ring->next_to_use = 0; | |
533 | } | |
534 | ||
535 | /** | |
536 | * i40evf_free_rx_resources - Free Rx resources | |
537 | * @rx_ring: ring to clean the resources from | |
538 | * | |
539 | * Free all receive software resources | |
540 | **/ | |
541 | void i40evf_free_rx_resources(struct i40e_ring *rx_ring) | |
542 | { | |
543 | i40evf_clean_rx_ring(rx_ring); | |
544 | kfree(rx_ring->rx_bi); | |
545 | rx_ring->rx_bi = NULL; | |
546 | ||
547 | if (rx_ring->desc) { | |
548 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
549 | rx_ring->desc, rx_ring->dma); | |
550 | rx_ring->desc = NULL; | |
551 | } | |
552 | } | |
553 | ||
554 | /** | |
555 | * i40evf_setup_rx_descriptors - Allocate Rx descriptors | |
556 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
557 | * | |
558 | * Returns 0 on success, negative on failure | |
559 | **/ | |
560 | int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
561 | { | |
562 | struct device *dev = rx_ring->dev; | |
563 | int bi_size; | |
564 | ||
67c818a1 MW |
565 | /* warn if we are about to overwrite the pointer */ |
566 | WARN_ON(rx_ring->rx_bi); | |
7f12ad74 GR |
567 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
568 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
569 | if (!rx_ring->rx_bi) | |
570 | goto err; | |
571 | ||
f217d6ca | 572 | u64_stats_init(&rx_ring->syncp); |
638702bd | 573 | |
7f12ad74 | 574 | /* Round up to nearest 4K */ |
ab9ad98e | 575 | rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); |
7f12ad74 GR |
576 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
577 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
578 | &rx_ring->dma, GFP_KERNEL); | |
579 | ||
580 | if (!rx_ring->desc) { | |
581 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
582 | rx_ring->size); | |
583 | goto err; | |
584 | } | |
585 | ||
ab9ad98e | 586 | rx_ring->next_to_alloc = 0; |
7f12ad74 GR |
587 | rx_ring->next_to_clean = 0; |
588 | rx_ring->next_to_use = 0; | |
589 | ||
590 | return 0; | |
591 | err: | |
592 | kfree(rx_ring->rx_bi); | |
593 | rx_ring->rx_bi = NULL; | |
594 | return -ENOMEM; | |
595 | } | |
596 | ||
597 | /** | |
598 | * i40e_release_rx_desc - Store the new tail and head values | |
599 | * @rx_ring: ring to bump | |
600 | * @val: new head index | |
601 | **/ | |
602 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
603 | { | |
604 | rx_ring->next_to_use = val; | |
ab9ad98e JB |
605 | |
606 | /* update next to alloc since we have filled the ring */ | |
607 | rx_ring->next_to_alloc = val; | |
608 | ||
7f12ad74 GR |
609 | /* Force memory writes to complete before letting h/w |
610 | * know there are new descriptors to fetch. (Only | |
611 | * applicable for weak-ordered memory model archs, | |
612 | * such as IA-64). | |
613 | */ | |
614 | wmb(); | |
615 | writel(val, rx_ring->tail); | |
616 | } | |
617 | ||
618 | /** | |
ab9ad98e JB |
619 | * i40e_alloc_mapped_page - recycle or make a new page |
620 | * @rx_ring: ring to use | |
621 | * @bi: rx_buffer struct to modify | |
c2e245ab | 622 | * |
ab9ad98e JB |
623 | * Returns true if the page was successfully allocated or |
624 | * reused. | |
a132af24 | 625 | **/ |
ab9ad98e JB |
626 | static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, |
627 | struct i40e_rx_buffer *bi) | |
a132af24 | 628 | { |
ab9ad98e JB |
629 | struct page *page = bi->page; |
630 | dma_addr_t dma; | |
a132af24 | 631 | |
ab9ad98e JB |
632 | /* since we are recycling buffers we should seldom need to alloc */ |
633 | if (likely(page)) { | |
634 | rx_ring->rx_stats.page_reuse_count++; | |
635 | return true; | |
636 | } | |
a132af24 | 637 | |
ab9ad98e JB |
638 | /* alloc new page for storage */ |
639 | page = dev_alloc_page(); | |
640 | if (unlikely(!page)) { | |
641 | rx_ring->rx_stats.alloc_page_failed++; | |
642 | return false; | |
643 | } | |
a132af24 | 644 | |
ab9ad98e JB |
645 | /* map page for use */ |
646 | dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
f16704e5 | 647 | |
ab9ad98e JB |
648 | /* if mapping failed free memory back to system since |
649 | * there isn't much point in holding memory we can't use | |
f16704e5 | 650 | */ |
ab9ad98e JB |
651 | if (dma_mapping_error(rx_ring->dev, dma)) { |
652 | __free_pages(page, 0); | |
653 | rx_ring->rx_stats.alloc_page_failed++; | |
654 | return false; | |
a132af24 MW |
655 | } |
656 | ||
ab9ad98e JB |
657 | bi->dma = dma; |
658 | bi->page = page; | |
659 | bi->page_offset = 0; | |
c2e245ab | 660 | |
ab9ad98e JB |
661 | return true; |
662 | } | |
c2e245ab | 663 | |
ab9ad98e JB |
664 | /** |
665 | * i40e_receive_skb - Send a completed packet up the stack | |
666 | * @rx_ring: rx ring in play | |
667 | * @skb: packet to send up | |
668 | * @vlan_tag: vlan tag for packet | |
669 | **/ | |
670 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
671 | struct sk_buff *skb, u16 vlan_tag) | |
672 | { | |
673 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
c2e245ab | 674 | |
ab9ad98e JB |
675 | if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
676 | (vlan_tag & VLAN_VID_MASK)) | |
677 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
678 | ||
679 | napi_gro_receive(&q_vector->napi, skb); | |
a132af24 MW |
680 | } |
681 | ||
682 | /** | |
ab9ad98e | 683 | * i40evf_alloc_rx_buffers - Replace used receive buffers |
7f12ad74 GR |
684 | * @rx_ring: ring to place buffers on |
685 | * @cleaned_count: number of buffers to replace | |
c2e245ab | 686 | * |
ab9ad98e | 687 | * Returns false if all allocations were successful, true if any fail |
7f12ad74 | 688 | **/ |
ab9ad98e | 689 | bool i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) |
7f12ad74 | 690 | { |
ab9ad98e | 691 | u16 ntu = rx_ring->next_to_use; |
7f12ad74 GR |
692 | union i40e_rx_desc *rx_desc; |
693 | struct i40e_rx_buffer *bi; | |
7f12ad74 GR |
694 | |
695 | /* do nothing if no valid netdev defined */ | |
696 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 697 | return false; |
7f12ad74 | 698 | |
ab9ad98e JB |
699 | rx_desc = I40E_RX_DESC(rx_ring, ntu); |
700 | bi = &rx_ring->rx_bi[ntu]; | |
7f12ad74 | 701 | |
ab9ad98e JB |
702 | do { |
703 | if (!i40e_alloc_mapped_page(rx_ring, bi)) | |
704 | goto no_buffers; | |
7f12ad74 | 705 | |
ab9ad98e JB |
706 | /* Refresh the desc even if buffer_addrs didn't change |
707 | * because each write-back erases this info. | |
708 | */ | |
709 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
a132af24 | 710 | rx_desc->read.hdr_addr = 0; |
7f12ad74 | 711 | |
ab9ad98e JB |
712 | rx_desc++; |
713 | bi++; | |
714 | ntu++; | |
715 | if (unlikely(ntu == rx_ring->count)) { | |
716 | rx_desc = I40E_RX_DESC(rx_ring, 0); | |
717 | bi = rx_ring->rx_bi; | |
718 | ntu = 0; | |
719 | } | |
720 | ||
721 | /* clear the status bits for the next_to_use descriptor */ | |
722 | rx_desc->wb.qword1.status_error_len = 0; | |
723 | ||
724 | cleaned_count--; | |
725 | } while (cleaned_count); | |
726 | ||
727 | if (rx_ring->next_to_use != ntu) | |
728 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
729 | |
730 | return false; | |
731 | ||
7f12ad74 | 732 | no_buffers: |
ab9ad98e JB |
733 | if (rx_ring->next_to_use != ntu) |
734 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
735 | |
736 | /* make sure to come back via polling to try again after | |
737 | * allocation failure | |
738 | */ | |
739 | return true; | |
7f12ad74 GR |
740 | } |
741 | ||
7f12ad74 GR |
742 | /** |
743 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
744 | * @vsi: the VSI we care about | |
745 | * @skb: skb currently being received and modified | |
ab9ad98e JB |
746 | * @rx_desc: the receive descriptor |
747 | * | |
748 | * skb->protocol must be set before this function is called | |
7f12ad74 GR |
749 | **/ |
750 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
751 | struct sk_buff *skb, | |
ab9ad98e | 752 | union i40e_rx_desc *rx_desc) |
7f12ad74 | 753 | { |
ab9ad98e | 754 | struct i40e_rx_ptype_decoded decoded; |
f8a952cb | 755 | bool ipv4, ipv6, tunnel = false; |
ab9ad98e JB |
756 | u32 rx_error, rx_status; |
757 | u8 ptype; | |
758 | u64 qword; | |
759 | ||
760 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
761 | ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; | |
762 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
763 | I40E_RXD_QW1_ERROR_SHIFT; | |
764 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
765 | I40E_RXD_QW1_STATUS_SHIFT; | |
766 | decoded = decode_rx_desc_ptype(ptype); | |
7f12ad74 | 767 | |
7f12ad74 GR |
768 | skb->ip_summed = CHECKSUM_NONE; |
769 | ||
ab9ad98e JB |
770 | skb_checksum_none_assert(skb); |
771 | ||
7f12ad74 | 772 | /* Rx csum enabled and ip headers found? */ |
8a3c91cc JB |
773 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
774 | return; | |
775 | ||
776 | /* did the hardware decode the packet and checksum? */ | |
41a1d04b | 777 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) |
8a3c91cc JB |
778 | return; |
779 | ||
780 | /* both known and outer_ip must be set for the below code to work */ | |
781 | if (!(decoded.known && decoded.outer_ip)) | |
7f12ad74 GR |
782 | return; |
783 | ||
fad57330 AD |
784 | ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && |
785 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); | |
786 | ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && | |
787 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); | |
8a3c91cc JB |
788 | |
789 | if (ipv4 && | |
41a1d04b JB |
790 | (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | |
791 | BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
8a3c91cc JB |
792 | goto checksum_fail; |
793 | ||
ddf1d0d7 | 794 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 795 | if (ipv6 && |
41a1d04b | 796 | rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
8a3c91cc | 797 | /* don't increment checksum err here, non-fatal err */ |
7f12ad74 GR |
798 | return; |
799 | ||
8a3c91cc | 800 | /* there was some L4 error, count error and punt packet to the stack */ |
41a1d04b | 801 | if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) |
8a3c91cc JB |
802 | goto checksum_fail; |
803 | ||
804 | /* handle packets that were not able to be checksummed due | |
805 | * to arrival speed, in this case the stack can compute | |
806 | * the csum. | |
807 | */ | |
41a1d04b | 808 | if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) |
7f12ad74 | 809 | return; |
7f12ad74 | 810 | |
a9c9a81f AD |
811 | /* The hardware supported by this driver does not validate outer |
812 | * checksums for tunneled VXLAN or GENEVE frames. I don't agree | |
813 | * with it but the specification states that you "MAY validate", it | |
814 | * doesn't make it a hard requirement so if we have validated the | |
815 | * inner checksum report CHECKSUM_UNNECESSARY. | |
8a3c91cc | 816 | */ |
f8a952cb JB |
817 | if (decoded.inner_prot & (I40E_RX_PTYPE_INNER_PROT_TCP | |
818 | I40E_RX_PTYPE_INNER_PROT_UDP | | |
819 | I40E_RX_PTYPE_INNER_PROT_SCTP)) | |
820 | tunnel = true; | |
fad57330 | 821 | |
7f12ad74 | 822 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
f8a952cb | 823 | skb->csum_level = tunnel ? 1 : 0; |
8a3c91cc JB |
824 | |
825 | return; | |
826 | ||
827 | checksum_fail: | |
828 | vsi->back->hw_csum_rx_error++; | |
7f12ad74 GR |
829 | } |
830 | ||
831 | /** | |
857942fd | 832 | * i40e_ptype_to_htype - get a hash type |
206812b5 JB |
833 | * @ptype: the ptype value from the descriptor |
834 | * | |
835 | * Returns a hash type to be used by skb_set_hash | |
836 | **/ | |
ab9ad98e | 837 | static inline int i40e_ptype_to_htype(u8 ptype) |
206812b5 JB |
838 | { |
839 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
840 | ||
841 | if (!decoded.known) | |
842 | return PKT_HASH_TYPE_NONE; | |
843 | ||
844 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
845 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
846 | return PKT_HASH_TYPE_L4; | |
847 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
848 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
849 | return PKT_HASH_TYPE_L3; | |
850 | else | |
851 | return PKT_HASH_TYPE_L2; | |
852 | } | |
853 | ||
857942fd ASJ |
854 | /** |
855 | * i40e_rx_hash - set the hash value in the skb | |
856 | * @ring: descriptor ring | |
857 | * @rx_desc: specific descriptor | |
858 | **/ | |
859 | static inline void i40e_rx_hash(struct i40e_ring *ring, | |
860 | union i40e_rx_desc *rx_desc, | |
861 | struct sk_buff *skb, | |
862 | u8 rx_ptype) | |
863 | { | |
864 | u32 hash; | |
ab9ad98e | 865 | const __le64 rss_mask = |
857942fd ASJ |
866 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << |
867 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
868 | ||
869 | if (ring->netdev->features & NETIF_F_RXHASH) | |
870 | return; | |
871 | ||
872 | if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { | |
873 | hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
874 | skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); | |
875 | } | |
876 | } | |
877 | ||
7f12ad74 | 878 | /** |
ab9ad98e JB |
879 | * i40evf_process_skb_fields - Populate skb header fields from Rx descriptor |
880 | * @rx_ring: rx descriptor ring packet is being transacted on | |
881 | * @rx_desc: pointer to the EOP Rx descriptor | |
882 | * @skb: pointer to current skb being populated | |
883 | * @rx_ptype: the packet type decoded by hardware | |
7f12ad74 | 884 | * |
ab9ad98e JB |
885 | * This function checks the ring, descriptor, and packet information in |
886 | * order to populate the hash, checksum, VLAN, protocol, and | |
887 | * other fields within the skb. | |
7f12ad74 | 888 | **/ |
ab9ad98e JB |
889 | static inline |
890 | void i40evf_process_skb_fields(struct i40e_ring *rx_ring, | |
891 | union i40e_rx_desc *rx_desc, struct sk_buff *skb, | |
892 | u8 rx_ptype) | |
7f12ad74 | 893 | { |
ab9ad98e | 894 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); |
7f12ad74 | 895 | |
ab9ad98e JB |
896 | /* modifies the skb - consumes the enet header */ |
897 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
a132af24 | 898 | |
ab9ad98e | 899 | i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); |
a132af24 | 900 | |
ab9ad98e JB |
901 | skb_record_rx_queue(skb, rx_ring->queue_index); |
902 | } | |
a132af24 | 903 | |
ab9ad98e JB |
904 | /** |
905 | * i40e_pull_tail - i40e specific version of skb_pull_tail | |
906 | * @rx_ring: rx descriptor ring packet is being transacted on | |
907 | * @skb: pointer to current skb being adjusted | |
908 | * | |
909 | * This function is an i40e specific version of __pskb_pull_tail. The | |
910 | * main difference between this version and the original function is that | |
911 | * this function can make several assumptions about the state of things | |
912 | * that allow for significant optimizations versus the standard function. | |
913 | * As a result we can do things like drop a frag and maintain an accurate | |
914 | * truesize for the skb. | |
915 | */ | |
916 | static void i40e_pull_tail(struct i40e_ring *rx_ring, struct sk_buff *skb) | |
917 | { | |
918 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
919 | unsigned char *va; | |
920 | unsigned int pull_len; | |
8b6ed9c2 | 921 | |
ab9ad98e JB |
922 | /* it is valid to use page_address instead of kmap since we are |
923 | * working with pages allocated out of the lomem pool per | |
924 | * alloc_page(GFP_ATOMIC) | |
925 | */ | |
926 | va = skb_frag_address(frag); | |
7f12ad74 | 927 | |
ab9ad98e JB |
928 | /* we need the header to contain the greater of either ETH_HLEN or |
929 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
930 | */ | |
931 | pull_len = eth_get_headlen(va, I40E_RX_HDR_SIZE); | |
7f12ad74 | 932 | |
ab9ad98e JB |
933 | /* align pull length to size of long to optimize memcpy performance */ |
934 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
7f12ad74 | 935 | |
ab9ad98e JB |
936 | /* update all of the pointers */ |
937 | skb_frag_size_sub(frag, pull_len); | |
938 | frag->page_offset += pull_len; | |
939 | skb->data_len -= pull_len; | |
940 | skb->tail += pull_len; | |
941 | } | |
7f12ad74 | 942 | |
ab9ad98e JB |
943 | /** |
944 | * i40e_cleanup_headers - Correct empty headers | |
945 | * @rx_ring: rx descriptor ring packet is being transacted on | |
946 | * @skb: pointer to current skb being fixed | |
947 | * | |
948 | * Also address the case where we are pulling data in on pages only | |
949 | * and as such no data is present in the skb header. | |
950 | * | |
951 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
952 | * it is large enough to qualify as a valid Ethernet frame. | |
953 | * | |
954 | * Returns true if an error was encountered and skb was freed. | |
955 | **/ | |
956 | static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) | |
957 | { | |
958 | /* place header in linear portion of buffer */ | |
959 | if (skb_is_nonlinear(skb)) | |
960 | i40e_pull_tail(rx_ring, skb); | |
7f12ad74 | 961 | |
ab9ad98e JB |
962 | /* if eth_skb_pad returns an error the skb was freed */ |
963 | if (eth_skb_pad(skb)) | |
964 | return true; | |
7f12ad74 | 965 | |
ab9ad98e JB |
966 | return false; |
967 | } | |
857942fd | 968 | |
ab9ad98e JB |
969 | /** |
970 | * i40e_reuse_rx_page - page flip buffer and store it back on the ring | |
971 | * @rx_ring: rx descriptor ring to store buffers on | |
972 | * @old_buff: donor buffer to have page reused | |
973 | * | |
974 | * Synchronizes page for reuse by the adapter | |
975 | **/ | |
976 | static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, | |
977 | struct i40e_rx_buffer *old_buff) | |
978 | { | |
979 | struct i40e_rx_buffer *new_buff; | |
980 | u16 nta = rx_ring->next_to_alloc; | |
7f12ad74 | 981 | |
ab9ad98e | 982 | new_buff = &rx_ring->rx_bi[nta]; |
7f12ad74 | 983 | |
ab9ad98e JB |
984 | /* update, and store next to alloc */ |
985 | nta++; | |
986 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
7f12ad74 | 987 | |
ab9ad98e JB |
988 | /* transfer page from old buffer to new buffer */ |
989 | *new_buff = *old_buff; | |
990 | } | |
991 | ||
992 | /** | |
993 | * i40e_page_is_reserved - check if reuse is possible | |
994 | * @page: page struct to check | |
995 | */ | |
996 | static inline bool i40e_page_is_reserved(struct page *page) | |
997 | { | |
998 | return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); | |
999 | } | |
1000 | ||
1001 | /** | |
1002 | * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1003 | * @rx_ring: rx descriptor ring to transact packets on | |
1004 | * @rx_buffer: buffer containing page to add | |
1005 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1006 | * @skb: sk_buff to place the data into | |
1007 | * | |
1008 | * This function will add the data contained in rx_buffer->page to the skb. | |
1009 | * This is done either through a direct copy if the data in the buffer is | |
1010 | * less than the skb header size, otherwise it will just attach the page as | |
1011 | * a frag to the skb. | |
1012 | * | |
1013 | * The function will then update the page offset if necessary and return | |
1014 | * true if the buffer can be reused by the adapter. | |
1015 | **/ | |
1016 | static bool i40e_add_rx_frag(struct i40e_ring *rx_ring, | |
1017 | struct i40e_rx_buffer *rx_buffer, | |
1018 | union i40e_rx_desc *rx_desc, | |
1019 | struct sk_buff *skb) | |
1020 | { | |
1021 | struct page *page = rx_buffer->page; | |
1022 | u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1023 | unsigned int size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> | |
1024 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
1025 | #if (PAGE_SIZE < 8192) | |
1026 | unsigned int truesize = I40E_RXBUFFER_2048; | |
1027 | #else | |
1028 | unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); | |
1029 | unsigned int last_offset = PAGE_SIZE - I40E_RXBUFFER_2048; | |
a132af24 | 1030 | #endif |
7f12ad74 | 1031 | |
ab9ad98e JB |
1032 | /* will the data fit in the skb we allocated? if so, just |
1033 | * copy it as it is pretty small anyway | |
1034 | */ | |
1035 | if ((size <= I40E_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { | |
1036 | unsigned char *va = page_address(page) + rx_buffer->page_offset; | |
7f12ad74 | 1037 | |
ab9ad98e | 1038 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); |
a132af24 | 1039 | |
ab9ad98e JB |
1040 | /* page is not reserved, we can reuse buffer as-is */ |
1041 | if (likely(!i40e_page_is_reserved(page))) | |
1042 | return true; | |
a132af24 | 1043 | |
ab9ad98e JB |
1044 | /* this page cannot be reused so discard it */ |
1045 | __free_pages(page, 0); | |
1046 | return false; | |
1047 | } | |
1048 | ||
1049 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, | |
1050 | rx_buffer->page_offset, size, truesize); | |
1051 | ||
1052 | /* avoid re-using remote pages */ | |
1053 | if (unlikely(i40e_page_is_reserved(page))) | |
1054 | return false; | |
1055 | ||
1056 | #if (PAGE_SIZE < 8192) | |
1057 | /* if we are only owner of page we can reuse it */ | |
1058 | if (unlikely(page_count(page) != 1)) | |
1059 | return false; | |
1060 | ||
1061 | /* flip page offset to other buffer */ | |
1062 | rx_buffer->page_offset ^= truesize; | |
1063 | #else | |
1064 | /* move offset up to the next cache line */ | |
1065 | rx_buffer->page_offset += truesize; | |
1066 | ||
1067 | if (rx_buffer->page_offset > last_offset) | |
1068 | return false; | |
1069 | #endif | |
1070 | ||
1071 | /* Even if we own the page, we are not allowed to use atomic_set() | |
1072 | * This would break get_page_unless_zero() users. | |
1073 | */ | |
1074 | get_page(rx_buffer->page); | |
1075 | ||
1076 | return true; | |
1077 | } | |
1078 | ||
1079 | /** | |
1080 | * i40evf_fetch_rx_buffer - Allocate skb and populate it | |
1081 | * @rx_ring: rx descriptor ring to transact packets on | |
1082 | * @rx_desc: descriptor containing info written by hardware | |
1083 | * | |
1084 | * This function allocates an skb on the fly, and populates it with the page | |
1085 | * data from the current receive descriptor, taking care to set up the skb | |
1086 | * correctly, as well as handling calling the page recycle function if | |
1087 | * necessary. | |
1088 | */ | |
1089 | static inline | |
1090 | struct sk_buff *i40evf_fetch_rx_buffer(struct i40e_ring *rx_ring, | |
1091 | union i40e_rx_desc *rx_desc) | |
1092 | { | |
1093 | struct i40e_rx_buffer *rx_buffer; | |
1094 | struct sk_buff *skb; | |
1095 | struct page *page; | |
1096 | ||
1097 | rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; | |
1098 | page = rx_buffer->page; | |
1099 | prefetchw(page); | |
1100 | ||
1101 | skb = rx_buffer->skb; | |
1102 | ||
1103 | if (likely(!skb)) { | |
1104 | void *page_addr = page_address(page) + rx_buffer->page_offset; | |
1105 | ||
1106 | /* prefetch first cache line of first page */ | |
1107 | prefetch(page_addr); | |
1108 | #if L1_CACHE_BYTES < 128 | |
1109 | prefetch(page_addr + L1_CACHE_BYTES); | |
1110 | #endif | |
1111 | ||
1112 | /* allocate a skb to store the frags */ | |
1113 | skb = __napi_alloc_skb(&rx_ring->q_vector->napi, | |
1114 | I40E_RX_HDR_SIZE, | |
1115 | GFP_ATOMIC | __GFP_NOWARN); | |
1116 | if (unlikely(!skb)) { | |
1117 | rx_ring->rx_stats.alloc_buff_failed++; | |
1118 | return NULL; | |
1119 | } | |
1120 | ||
1121 | /* we will be copying header into skb->data in | |
1122 | * pskb_may_pull so it is in our interest to prefetch | |
1123 | * it now to avoid a possible cache miss | |
1124 | */ | |
1125 | prefetchw(skb->data); | |
1126 | } else { | |
1127 | rx_buffer->skb = NULL; | |
1128 | } | |
1129 | ||
1130 | /* we are reusing so sync this buffer for CPU use */ | |
1131 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1132 | rx_buffer->dma, | |
1133 | rx_buffer->page_offset, | |
1134 | I40E_RXBUFFER_2048, | |
1135 | DMA_FROM_DEVICE); | |
1136 | ||
1137 | /* pull page into skb */ | |
1138 | if (i40e_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { | |
1139 | /* hand second half of page back to the ring */ | |
1140 | i40e_reuse_rx_page(rx_ring, rx_buffer); | |
1141 | rx_ring->rx_stats.page_reuse_count++; | |
1142 | } else { | |
1143 | /* we are not reusing the buffer so unmap it */ | |
1144 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, PAGE_SIZE, | |
1145 | DMA_FROM_DEVICE); | |
1146 | } | |
1147 | ||
1148 | /* clear contents of buffer_info */ | |
1149 | rx_buffer->page = NULL; | |
1150 | ||
1151 | return skb; | |
1152 | } | |
1153 | ||
1154 | /** | |
1155 | * i40e_is_non_eop - process handling of non-EOP buffers | |
1156 | * @rx_ring: Rx ring being processed | |
1157 | * @rx_desc: Rx descriptor for current buffer | |
1158 | * @skb: Current socket buffer containing buffer in progress | |
1159 | * | |
1160 | * This function updates next to clean. If the buffer is an EOP buffer | |
1161 | * this function exits returning false, otherwise it will place the | |
1162 | * sk_buff in the next buffer to be chained and return true indicating | |
1163 | * that this is in fact a non-EOP buffer. | |
1164 | **/ | |
1165 | static bool i40e_is_non_eop(struct i40e_ring *rx_ring, | |
1166 | union i40e_rx_desc *rx_desc, | |
1167 | struct sk_buff *skb) | |
1168 | { | |
1169 | u32 ntc = rx_ring->next_to_clean + 1; | |
1170 | ||
1171 | /* fetch, update, and store next to clean */ | |
1172 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1173 | rx_ring->next_to_clean = ntc; | |
1174 | ||
1175 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
1176 | ||
1177 | /* if we are the last buffer then there is nothing else to do */ | |
1178 | #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) | |
1179 | if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) | |
1180 | return false; | |
1181 | ||
1182 | /* place skb in next buffer to be received */ | |
1183 | rx_ring->rx_bi[ntc].skb = skb; | |
1184 | rx_ring->rx_stats.non_eop_descs++; | |
1185 | ||
1186 | return true; | |
a132af24 MW |
1187 | } |
1188 | ||
1189 | /** | |
ab9ad98e JB |
1190 | * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf |
1191 | * @rx_ring: rx descriptor ring to transact packets on | |
1192 | * @budget: Total limit on number of packets to process | |
1193 | * | |
1194 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1195 | * processing. The advantage to this is that on systems that have | |
1196 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1197 | * it by maintaining the mapping of the page to the system. | |
a132af24 | 1198 | * |
ab9ad98e | 1199 | * Returns amount of work completed |
a132af24 | 1200 | **/ |
ab9ad98e | 1201 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) |
a132af24 MW |
1202 | { |
1203 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
1204 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); | |
c2e245ab | 1205 | bool failure = false; |
a132af24 | 1206 | |
ab9ad98e JB |
1207 | while (likely(total_rx_packets < budget)) { |
1208 | union i40e_rx_desc *rx_desc; | |
a132af24 | 1209 | struct sk_buff *skb; |
ab9ad98e | 1210 | u32 rx_status; |
a132af24 | 1211 | u16 vlan_tag; |
ab9ad98e JB |
1212 | u8 rx_ptype; |
1213 | u64 qword; | |
1214 | ||
7f12ad74 GR |
1215 | /* return some buffers to hardware, one at a time is too slow */ |
1216 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab | 1217 | failure = failure || |
ab9ad98e | 1218 | i40evf_alloc_rx_buffers(rx_ring, cleaned_count); |
7f12ad74 GR |
1219 | cleaned_count = 0; |
1220 | } | |
1221 | ||
ab9ad98e JB |
1222 | rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); |
1223 | ||
7f12ad74 | 1224 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
ab9ad98e JB |
1225 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> |
1226 | I40E_RXD_QW1_PTYPE_SHIFT; | |
7f12ad74 | 1227 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> |
ab9ad98e | 1228 | I40E_RXD_QW1_STATUS_SHIFT; |
a132af24 | 1229 | |
41a1d04b | 1230 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT))) |
a132af24 MW |
1231 | break; |
1232 | ||
ab9ad98e JB |
1233 | /* status_error_len will always be zero for unused descriptors |
1234 | * because it's cleared in cleanup, and overlaps with hdr_addr | |
1235 | * which is always zero because packet split isn't used, if the | |
1236 | * hardware wrote DD then it will be non-zero | |
1237 | */ | |
1238 | if (!rx_desc->wb.qword1.status_error_len) | |
1239 | break; | |
1240 | ||
a132af24 MW |
1241 | /* This memory barrier is needed to keep us from reading |
1242 | * any other fields out of the rx_desc until we know the | |
1243 | * DD bit is set. | |
1244 | */ | |
67317166 | 1245 | dma_rmb(); |
a132af24 | 1246 | |
ab9ad98e JB |
1247 | skb = i40evf_fetch_rx_buffer(rx_ring, rx_desc); |
1248 | if (!skb) | |
1249 | break; | |
a132af24 | 1250 | |
a132af24 MW |
1251 | cleaned_count++; |
1252 | ||
ab9ad98e | 1253 | if (i40e_is_non_eop(rx_ring, rx_desc, skb)) |
a132af24 | 1254 | continue; |
a132af24 | 1255 | |
ab9ad98e JB |
1256 | /* ERR_MASK will only have valid bits if EOP set, and |
1257 | * what we are doing here is actually checking | |
1258 | * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in | |
1259 | * the error field | |
1260 | */ | |
1261 | if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { | |
a132af24 | 1262 | dev_kfree_skb_any(skb); |
a132af24 MW |
1263 | continue; |
1264 | } | |
1265 | ||
ab9ad98e JB |
1266 | if (i40e_cleanup_headers(rx_ring, skb)) |
1267 | continue; | |
1268 | ||
a132af24 MW |
1269 | /* probably a little skewed due to removing CRC */ |
1270 | total_rx_bytes += skb->len; | |
a132af24 | 1271 | |
ab9ad98e JB |
1272 | /* populate checksum, VLAN, and protocol */ |
1273 | i40evf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); | |
a132af24 | 1274 | |
a132af24 | 1275 | |
ab9ad98e JB |
1276 | vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? |
1277 | le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; | |
1278 | ||
a132af24 MW |
1279 | i40e_receive_skb(rx_ring, skb, vlan_tag); |
1280 | ||
ab9ad98e JB |
1281 | /* update budget accounting */ |
1282 | total_rx_packets++; | |
1283 | } | |
7f12ad74 | 1284 | |
7f12ad74 GR |
1285 | u64_stats_update_begin(&rx_ring->syncp); |
1286 | rx_ring->stats.packets += total_rx_packets; | |
1287 | rx_ring->stats.bytes += total_rx_bytes; | |
1288 | u64_stats_update_end(&rx_ring->syncp); | |
1289 | rx_ring->q_vector->rx.total_packets += total_rx_packets; | |
1290 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1291 | ||
ab9ad98e | 1292 | /* guarantee a trip back through this routine if there was a failure */ |
c2e245ab | 1293 | return failure ? budget : total_rx_packets; |
7f12ad74 GR |
1294 | } |
1295 | ||
8f5e39ce JB |
1296 | static u32 i40e_buildreg_itr(const int type, const u16 itr) |
1297 | { | |
1298 | u32 val; | |
1299 | ||
1300 | val = I40E_VFINT_DYN_CTLN1_INTENA_MASK | | |
40d72a50 JB |
1301 | /* Don't clear PBA because that can cause lost interrupts that |
1302 | * came in while we were cleaning/polling | |
1303 | */ | |
8f5e39ce JB |
1304 | (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | |
1305 | (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT); | |
1306 | ||
1307 | return val; | |
1308 | } | |
1309 | ||
1310 | /* a small macro to shorten up some long lines */ | |
1311 | #define INTREG I40E_VFINT_DYN_CTLN1 | |
1312 | ||
de32e3ef CW |
1313 | /** |
1314 | * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt | |
1315 | * @vsi: the VSI we care about | |
1316 | * @q_vector: q_vector for which itr is being updated and interrupt enabled | |
1317 | * | |
1318 | **/ | |
1319 | static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, | |
1320 | struct i40e_q_vector *q_vector) | |
1321 | { | |
1322 | struct i40e_hw *hw = &vsi->back->hw; | |
8f5e39ce JB |
1323 | bool rx = false, tx = false; |
1324 | u32 rxval, txval; | |
de32e3ef | 1325 | int vector; |
de32e3ef CW |
1326 | |
1327 | vector = (q_vector->v_idx + vsi->base_vector); | |
ee2319cf JB |
1328 | |
1329 | /* avoid dynamic calculation if in countdown mode OR if | |
1330 | * all dynamic is disabled | |
1331 | */ | |
8f5e39ce JB |
1332 | rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); |
1333 | ||
ee2319cf JB |
1334 | if (q_vector->itr_countdown > 0 || |
1335 | (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) && | |
1336 | !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) { | |
1337 | goto enable_int; | |
1338 | } | |
1339 | ||
de32e3ef | 1340 | if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) { |
8f5e39ce JB |
1341 | rx = i40e_set_new_dynamic_itr(&q_vector->rx); |
1342 | rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); | |
de32e3ef | 1343 | } |
4eeb1fff | 1344 | |
de32e3ef | 1345 | if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) { |
8f5e39ce JB |
1346 | tx = i40e_set_new_dynamic_itr(&q_vector->tx); |
1347 | txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); | |
1348 | } | |
4eeb1fff | 1349 | |
8f5e39ce JB |
1350 | if (rx || tx) { |
1351 | /* get the higher of the two ITR adjustments and | |
1352 | * use the same value for both ITR registers | |
1353 | * when in adaptive mode (Rx and/or Tx) | |
1354 | */ | |
1355 | u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); | |
1356 | ||
1357 | q_vector->tx.itr = q_vector->rx.itr = itr; | |
1358 | txval = i40e_buildreg_itr(I40E_TX_ITR, itr); | |
1359 | tx = true; | |
1360 | rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); | |
1361 | rx = true; | |
de32e3ef | 1362 | } |
8f5e39ce JB |
1363 | |
1364 | /* only need to enable the interrupt once, but need | |
1365 | * to possibly update both ITR values | |
1366 | */ | |
1367 | if (rx) { | |
1368 | /* set the INTENA_MSK_MASK so that this first write | |
1369 | * won't actually enable the interrupt, instead just | |
1370 | * updating the ITR (it's bit 31 PF and VF) | |
1371 | */ | |
1372 | rxval |= BIT(31); | |
1373 | /* don't check _DOWN because interrupt isn't being enabled */ | |
1374 | wr32(hw, INTREG(vector - 1), rxval); | |
1375 | } | |
1376 | ||
ee2319cf | 1377 | enable_int: |
8f5e39ce JB |
1378 | if (!test_bit(__I40E_DOWN, &vsi->state)) |
1379 | wr32(hw, INTREG(vector - 1), txval); | |
ee2319cf JB |
1380 | |
1381 | if (q_vector->itr_countdown) | |
1382 | q_vector->itr_countdown--; | |
1383 | else | |
1384 | q_vector->itr_countdown = ITR_COUNTDOWN_START; | |
de32e3ef CW |
1385 | } |
1386 | ||
7f12ad74 GR |
1387 | /** |
1388 | * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine | |
1389 | * @napi: napi struct with our devices info in it | |
1390 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1391 | * | |
1392 | * This function will clean all queues associated with a q_vector. | |
1393 | * | |
1394 | * Returns the amount of work done | |
1395 | **/ | |
1396 | int i40evf_napi_poll(struct napi_struct *napi, int budget) | |
1397 | { | |
1398 | struct i40e_q_vector *q_vector = | |
1399 | container_of(napi, struct i40e_q_vector, napi); | |
1400 | struct i40e_vsi *vsi = q_vector->vsi; | |
1401 | struct i40e_ring *ring; | |
1402 | bool clean_complete = true; | |
c29af37f | 1403 | bool arm_wb = false; |
7f12ad74 | 1404 | int budget_per_ring; |
32b3e08f | 1405 | int work_done = 0; |
7f12ad74 GR |
1406 | |
1407 | if (test_bit(__I40E_DOWN, &vsi->state)) { | |
1408 | napi_complete(napi); | |
1409 | return 0; | |
1410 | } | |
1411 | ||
1412 | /* Since the actual Tx work is minimal, we can give the Tx a larger | |
1413 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
1414 | */ | |
c29af37f | 1415 | i40e_for_each_ring(ring, q_vector->tx) { |
a619afe8 | 1416 | if (!i40e_clean_tx_irq(vsi, ring, budget)) { |
f2edaaaa AD |
1417 | clean_complete = false; |
1418 | continue; | |
1419 | } | |
1420 | arm_wb |= ring->arm_wb; | |
0deda868 | 1421 | ring->arm_wb = false; |
c29af37f | 1422 | } |
7f12ad74 | 1423 | |
c67caceb AD |
1424 | /* Handle case where we are called by netpoll with a budget of 0 */ |
1425 | if (budget <= 0) | |
1426 | goto tx_only; | |
1427 | ||
7f12ad74 GR |
1428 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
1429 | * allow the budget to go below 1 because that would exit polling early. | |
1430 | */ | |
1431 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
1432 | ||
a132af24 | 1433 | i40e_for_each_ring(ring, q_vector->rx) { |
ab9ad98e | 1434 | int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); |
32b3e08f JB |
1435 | |
1436 | work_done += cleaned; | |
f2edaaaa AD |
1437 | /* if we clean as many as budgeted, we must not be done */ |
1438 | if (cleaned >= budget_per_ring) | |
1439 | clean_complete = false; | |
a132af24 | 1440 | } |
7f12ad74 GR |
1441 | |
1442 | /* If work not completed, return budget and polling will return */ | |
c29af37f | 1443 | if (!clean_complete) { |
c67caceb | 1444 | tx_only: |
164c9f54 ASJ |
1445 | if (arm_wb) { |
1446 | q_vector->tx.ring[0].tx_stats.tx_force_wb++; | |
ecc6a239 | 1447 | i40e_enable_wb_on_itr(vsi, q_vector); |
164c9f54 | 1448 | } |
7f12ad74 | 1449 | return budget; |
c29af37f | 1450 | } |
7f12ad74 | 1451 | |
8e0764b4 ASJ |
1452 | if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) |
1453 | q_vector->arm_wb_state = false; | |
1454 | ||
7f12ad74 | 1455 | /* Work is done so exit the polling mode and re-enable the interrupt */ |
32b3e08f | 1456 | napi_complete_done(napi, work_done); |
de32e3ef | 1457 | i40e_update_enable_itr(vsi, q_vector); |
7f12ad74 GR |
1458 | return 0; |
1459 | } | |
1460 | ||
1461 | /** | |
3e587cf3 | 1462 | * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW |
7f12ad74 GR |
1463 | * @skb: send buffer |
1464 | * @tx_ring: ring to send buffer on | |
1465 | * @flags: the tx flags to be set | |
1466 | * | |
1467 | * Checks the skb and set up correspondingly several generic transmit flags | |
1468 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
1469 | * | |
1470 | * Returns error code indicate the frame should be dropped upon error and the | |
1471 | * otherwise returns 0 to indicate the flags has been set properly. | |
1472 | **/ | |
3e587cf3 JB |
1473 | static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb, |
1474 | struct i40e_ring *tx_ring, | |
1475 | u32 *flags) | |
7f12ad74 GR |
1476 | { |
1477 | __be16 protocol = skb->protocol; | |
1478 | u32 tx_flags = 0; | |
1479 | ||
31eaaccf GR |
1480 | if (protocol == htons(ETH_P_8021Q) && |
1481 | !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { | |
1482 | /* When HW VLAN acceleration is turned off by the user the | |
1483 | * stack sets the protocol to 8021q so that the driver | |
1484 | * can take any steps required to support the SW only | |
1485 | * VLAN handling. In our case the driver doesn't need | |
1486 | * to take any further steps so just set the protocol | |
1487 | * to the encapsulated ethertype. | |
1488 | */ | |
1489 | skb->protocol = vlan_get_protocol(skb); | |
1490 | goto out; | |
1491 | } | |
1492 | ||
7f12ad74 | 1493 | /* if we have a HW VLAN tag being added, default to the HW one */ |
df8a39de JP |
1494 | if (skb_vlan_tag_present(skb)) { |
1495 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
7f12ad74 GR |
1496 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
1497 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
1498 | } else if (protocol == htons(ETH_P_8021Q)) { | |
1499 | struct vlan_hdr *vhdr, _vhdr; | |
6995b36c | 1500 | |
7f12ad74 GR |
1501 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); |
1502 | if (!vhdr) | |
1503 | return -EINVAL; | |
1504 | ||
1505 | protocol = vhdr->h_vlan_encapsulated_proto; | |
1506 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
1507 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
1508 | } | |
1509 | ||
31eaaccf | 1510 | out: |
7f12ad74 GR |
1511 | *flags = tx_flags; |
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | /** | |
1516 | * i40e_tso - set up the tso context descriptor | |
7f12ad74 | 1517 | * @skb: ptr to the skb we're sending |
7f12ad74 | 1518 | * @hdr_len: ptr to the size of the packet header |
9c883bd3 | 1519 | * @cd_type_cmd_tso_mss: Quad Word 1 |
7f12ad74 GR |
1520 | * |
1521 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
1522 | **/ | |
84b07992 | 1523 | static int i40e_tso(struct sk_buff *skb, u8 *hdr_len, u64 *cd_type_cmd_tso_mss) |
7f12ad74 | 1524 | { |
03f9d6a5 | 1525 | u64 cd_cmd, cd_tso_len, cd_mss; |
c777019a AD |
1526 | union { |
1527 | struct iphdr *v4; | |
1528 | struct ipv6hdr *v6; | |
1529 | unsigned char *hdr; | |
1530 | } ip; | |
c49a7bc3 AD |
1531 | union { |
1532 | struct tcphdr *tcp; | |
5453205c | 1533 | struct udphdr *udp; |
c49a7bc3 AD |
1534 | unsigned char *hdr; |
1535 | } l4; | |
1536 | u32 paylen, l4_offset; | |
7f12ad74 | 1537 | int err; |
7f12ad74 | 1538 | |
e9f6563d SN |
1539 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
1540 | return 0; | |
1541 | ||
7f12ad74 GR |
1542 | if (!skb_is_gso(skb)) |
1543 | return 0; | |
1544 | ||
fe6d4aa4 FR |
1545 | err = skb_cow_head(skb, 0); |
1546 | if (err < 0) | |
1547 | return err; | |
7f12ad74 | 1548 | |
c777019a AD |
1549 | ip.hdr = skb_network_header(skb); |
1550 | l4.hdr = skb_transport_header(skb); | |
85e76d03 | 1551 | |
c777019a AD |
1552 | /* initialize outer IP header fields */ |
1553 | if (ip.v4->version == 4) { | |
1554 | ip.v4->tot_len = 0; | |
1555 | ip.v4->check = 0; | |
c49a7bc3 | 1556 | } else { |
c777019a AD |
1557 | ip.v6->payload_len = 0; |
1558 | } | |
1559 | ||
577389a5 | 1560 | if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | |
1c7b4a23 | 1561 | SKB_GSO_GRE_CSUM | |
7e13318d | 1562 | SKB_GSO_IPXIP4 | |
bf2d1df3 | 1563 | SKB_GSO_IPXIP6 | |
577389a5 | 1564 | SKB_GSO_UDP_TUNNEL | |
5453205c | 1565 | SKB_GSO_UDP_TUNNEL_CSUM)) { |
1c7b4a23 AD |
1566 | if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
1567 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { | |
1568 | l4.udp->len = 0; | |
1569 | ||
5453205c AD |
1570 | /* determine offset of outer transport header */ |
1571 | l4_offset = l4.hdr - skb->data; | |
1572 | ||
1573 | /* remove payload length from outer checksum */ | |
24d41e5e AD |
1574 | paylen = skb->len - l4_offset; |
1575 | csum_replace_by_diff(&l4.udp->check, htonl(paylen)); | |
5453205c AD |
1576 | } |
1577 | ||
c777019a AD |
1578 | /* reset pointers to inner headers */ |
1579 | ip.hdr = skb_inner_network_header(skb); | |
1580 | l4.hdr = skb_inner_transport_header(skb); | |
1581 | ||
1582 | /* initialize inner IP header fields */ | |
1583 | if (ip.v4->version == 4) { | |
1584 | ip.v4->tot_len = 0; | |
1585 | ip.v4->check = 0; | |
1586 | } else { | |
1587 | ip.v6->payload_len = 0; | |
1588 | } | |
7f12ad74 GR |
1589 | } |
1590 | ||
c49a7bc3 AD |
1591 | /* determine offset of inner transport header */ |
1592 | l4_offset = l4.hdr - skb->data; | |
1593 | ||
1594 | /* remove payload length from inner checksum */ | |
24d41e5e AD |
1595 | paylen = skb->len - l4_offset; |
1596 | csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); | |
c49a7bc3 AD |
1597 | |
1598 | /* compute length of segmentation header */ | |
1599 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
7f12ad74 GR |
1600 | |
1601 | /* find the field values */ | |
1602 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
1603 | cd_tso_len = skb->len - *hdr_len; | |
1604 | cd_mss = skb_shinfo(skb)->gso_size; | |
03f9d6a5 AD |
1605 | *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
1606 | (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
1607 | (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
7f12ad74 GR |
1608 | return 1; |
1609 | } | |
1610 | ||
1611 | /** | |
1612 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
1613 | * @skb: send buffer | |
89232c3b | 1614 | * @tx_flags: pointer to Tx flags currently set |
7f12ad74 GR |
1615 | * @td_cmd: Tx descriptor command bits to set |
1616 | * @td_offset: Tx descriptor header offsets to set | |
529f1f65 | 1617 | * @tx_ring: Tx descriptor ring |
7f12ad74 GR |
1618 | * @cd_tunneling: ptr to context desc bits |
1619 | **/ | |
529f1f65 AD |
1620 | static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, |
1621 | u32 *td_cmd, u32 *td_offset, | |
1622 | struct i40e_ring *tx_ring, | |
1623 | u32 *cd_tunneling) | |
7f12ad74 | 1624 | { |
b96b78f2 AD |
1625 | union { |
1626 | struct iphdr *v4; | |
1627 | struct ipv6hdr *v6; | |
1628 | unsigned char *hdr; | |
1629 | } ip; | |
1630 | union { | |
1631 | struct tcphdr *tcp; | |
1632 | struct udphdr *udp; | |
1633 | unsigned char *hdr; | |
1634 | } l4; | |
a3fd9d88 | 1635 | unsigned char *exthdr; |
d1bd743b | 1636 | u32 offset, cmd = 0; |
a3fd9d88 | 1637 | __be16 frag_off; |
b96b78f2 AD |
1638 | u8 l4_proto = 0; |
1639 | ||
529f1f65 AD |
1640 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
1641 | return 0; | |
1642 | ||
b96b78f2 AD |
1643 | ip.hdr = skb_network_header(skb); |
1644 | l4.hdr = skb_transport_header(skb); | |
7f12ad74 | 1645 | |
475b4205 AD |
1646 | /* compute outer L2 header size */ |
1647 | offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
1648 | ||
7f12ad74 | 1649 | if (skb->encapsulation) { |
d1bd743b | 1650 | u32 tunnel = 0; |
a0064728 AD |
1651 | /* define outer network header type */ |
1652 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { | |
475b4205 AD |
1653 | tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
1654 | I40E_TX_CTX_EXT_IP_IPV4 : | |
1655 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
1656 | ||
a0064728 AD |
1657 | l4_proto = ip.v4->protocol; |
1658 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { | |
475b4205 | 1659 | tunnel |= I40E_TX_CTX_EXT_IP_IPV6; |
a3fd9d88 AD |
1660 | |
1661 | exthdr = ip.hdr + sizeof(*ip.v6); | |
a0064728 | 1662 | l4_proto = ip.v6->nexthdr; |
a3fd9d88 AD |
1663 | if (l4.hdr != exthdr) |
1664 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
1665 | &l4_proto, &frag_off); | |
a0064728 AD |
1666 | } |
1667 | ||
1668 | /* define outer transport */ | |
1669 | switch (l4_proto) { | |
45991204 | 1670 | case IPPROTO_UDP: |
475b4205 | 1671 | tunnel |= I40E_TXD_CTX_UDP_TUNNELING; |
89232c3b | 1672 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; |
45991204 | 1673 | break; |
a0064728 | 1674 | case IPPROTO_GRE: |
475b4205 | 1675 | tunnel |= I40E_TXD_CTX_GRE_TUNNELING; |
a0064728 AD |
1676 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; |
1677 | break; | |
577389a5 AD |
1678 | case IPPROTO_IPIP: |
1679 | case IPPROTO_IPV6: | |
1680 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; | |
1681 | l4.hdr = skb_inner_network_header(skb); | |
1682 | break; | |
45991204 | 1683 | default: |
529f1f65 AD |
1684 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
1685 | return -1; | |
1686 | ||
1687 | skb_checksum_help(skb); | |
1688 | return 0; | |
45991204 | 1689 | } |
b96b78f2 | 1690 | |
577389a5 AD |
1691 | /* compute outer L3 header size */ |
1692 | tunnel |= ((l4.hdr - ip.hdr) / 4) << | |
1693 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; | |
1694 | ||
1695 | /* switch IP header pointer from outer to inner header */ | |
1696 | ip.hdr = skb_inner_network_header(skb); | |
1697 | ||
475b4205 AD |
1698 | /* compute tunnel header size */ |
1699 | tunnel |= ((ip.hdr - l4.hdr) / 2) << | |
1700 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
1701 | ||
5453205c AD |
1702 | /* indicate if we need to offload outer UDP header */ |
1703 | if ((*tx_flags & I40E_TX_FLAGS_TSO) && | |
1c7b4a23 | 1704 | !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
5453205c AD |
1705 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) |
1706 | tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; | |
1707 | ||
475b4205 AD |
1708 | /* record tunnel offload values */ |
1709 | *cd_tunneling |= tunnel; | |
1710 | ||
b96b78f2 | 1711 | /* switch L4 header pointer from outer to inner */ |
b96b78f2 | 1712 | l4.hdr = skb_inner_transport_header(skb); |
a0064728 | 1713 | l4_proto = 0; |
7f12ad74 | 1714 | |
a0064728 AD |
1715 | /* reset type as we transition from outer to inner headers */ |
1716 | *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); | |
1717 | if (ip.v4->version == 4) | |
1718 | *tx_flags |= I40E_TX_FLAGS_IPV4; | |
1719 | if (ip.v6->version == 6) | |
89232c3b | 1720 | *tx_flags |= I40E_TX_FLAGS_IPV6; |
7f12ad74 GR |
1721 | } |
1722 | ||
1723 | /* Enable IP checksum offloads */ | |
89232c3b | 1724 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { |
b96b78f2 | 1725 | l4_proto = ip.v4->protocol; |
7f12ad74 GR |
1726 | /* the stack computes the IP header already, the only time we |
1727 | * need the hardware to recompute it is in the case of TSO. | |
1728 | */ | |
475b4205 AD |
1729 | cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
1730 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : | |
1731 | I40E_TX_DESC_CMD_IIPT_IPV4; | |
89232c3b | 1732 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { |
475b4205 | 1733 | cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; |
a3fd9d88 AD |
1734 | |
1735 | exthdr = ip.hdr + sizeof(*ip.v6); | |
1736 | l4_proto = ip.v6->nexthdr; | |
1737 | if (l4.hdr != exthdr) | |
1738 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
1739 | &l4_proto, &frag_off); | |
7f12ad74 | 1740 | } |
b96b78f2 | 1741 | |
475b4205 AD |
1742 | /* compute inner L3 header size */ |
1743 | offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
7f12ad74 GR |
1744 | |
1745 | /* Enable L4 checksum offloads */ | |
b96b78f2 | 1746 | switch (l4_proto) { |
7f12ad74 GR |
1747 | case IPPROTO_TCP: |
1748 | /* enable checksum offloads */ | |
475b4205 AD |
1749 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; |
1750 | offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1751 | break; |
1752 | case IPPROTO_SCTP: | |
1753 | /* enable SCTP checksum offload */ | |
475b4205 AD |
1754 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; |
1755 | offset |= (sizeof(struct sctphdr) >> 2) << | |
1756 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1757 | break; |
1758 | case IPPROTO_UDP: | |
1759 | /* enable UDP checksum offload */ | |
475b4205 AD |
1760 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; |
1761 | offset |= (sizeof(struct udphdr) >> 2) << | |
1762 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1763 | break; |
1764 | default: | |
529f1f65 AD |
1765 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
1766 | return -1; | |
1767 | skb_checksum_help(skb); | |
1768 | return 0; | |
7f12ad74 | 1769 | } |
475b4205 AD |
1770 | |
1771 | *td_cmd |= cmd; | |
1772 | *td_offset |= offset; | |
529f1f65 AD |
1773 | |
1774 | return 1; | |
7f12ad74 GR |
1775 | } |
1776 | ||
1777 | /** | |
1778 | * i40e_create_tx_ctx Build the Tx context descriptor | |
1779 | * @tx_ring: ring to create the descriptor on | |
1780 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
1781 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
1782 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
1783 | **/ | |
1784 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
1785 | const u64 cd_type_cmd_tso_mss, | |
1786 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
1787 | { | |
1788 | struct i40e_tx_context_desc *context_desc; | |
1789 | int i = tx_ring->next_to_use; | |
1790 | ||
ff40dd5d JB |
1791 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
1792 | !cd_tunneling && !cd_l2tag2) | |
7f12ad74 GR |
1793 | return; |
1794 | ||
1795 | /* grab the next descriptor */ | |
1796 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); | |
1797 | ||
1798 | i++; | |
1799 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
1800 | ||
1801 | /* cpu_to_le32 and assign to struct fields */ | |
1802 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
1803 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 1804 | context_desc->rsvd = cpu_to_le16(0); |
7f12ad74 GR |
1805 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
1806 | } | |
1807 | ||
4eeb1fff | 1808 | /** |
3f3f7cb8 | 1809 | * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet |
71da6197 | 1810 | * @skb: send buffer |
71da6197 | 1811 | * |
3f3f7cb8 AD |
1812 | * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire |
1813 | * and so we need to figure out the cases where we need to linearize the skb. | |
1814 | * | |
1815 | * For TSO we need to count the TSO header and segment payload separately. | |
1816 | * As such we need to check cases where we have 7 fragments or more as we | |
1817 | * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for | |
1818 | * the segment payload in the first descriptor, and another 7 for the | |
1819 | * fragments. | |
71da6197 | 1820 | **/ |
2d37490b | 1821 | bool __i40evf_chk_linearize(struct sk_buff *skb) |
71da6197 | 1822 | { |
2d37490b | 1823 | const struct skb_frag_struct *frag, *stale; |
3f3f7cb8 | 1824 | int nr_frags, sum; |
71da6197 | 1825 | |
3f3f7cb8 | 1826 | /* no need to check if number of frags is less than 7 */ |
2d37490b | 1827 | nr_frags = skb_shinfo(skb)->nr_frags; |
3f3f7cb8 | 1828 | if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) |
2d37490b | 1829 | return false; |
71da6197 | 1830 | |
2d37490b AD |
1831 | /* We need to walk through the list and validate that each group |
1832 | * of 6 fragments totals at least gso_size. However we don't need | |
3f3f7cb8 AD |
1833 | * to perform such validation on the last 6 since the last 6 cannot |
1834 | * inherit any data from a descriptor after them. | |
2d37490b | 1835 | */ |
3f3f7cb8 | 1836 | nr_frags -= I40E_MAX_BUFFER_TXD - 2; |
2d37490b AD |
1837 | frag = &skb_shinfo(skb)->frags[0]; |
1838 | ||
1839 | /* Initialize size to the negative value of gso_size minus 1. We | |
1840 | * use this as the worst case scenerio in which the frag ahead | |
1841 | * of us only provides one byte which is why we are limited to 6 | |
1842 | * descriptors for a single transmit as the header and previous | |
1843 | * fragment are already consuming 2 descriptors. | |
1844 | */ | |
3f3f7cb8 | 1845 | sum = 1 - skb_shinfo(skb)->gso_size; |
2d37490b | 1846 | |
3f3f7cb8 AD |
1847 | /* Add size of frags 0 through 4 to create our initial sum */ |
1848 | sum += skb_frag_size(frag++); | |
1849 | sum += skb_frag_size(frag++); | |
1850 | sum += skb_frag_size(frag++); | |
1851 | sum += skb_frag_size(frag++); | |
1852 | sum += skb_frag_size(frag++); | |
2d37490b AD |
1853 | |
1854 | /* Walk through fragments adding latest fragment, testing it, and | |
1855 | * then removing stale fragments from the sum. | |
1856 | */ | |
1857 | stale = &skb_shinfo(skb)->frags[0]; | |
1858 | for (;;) { | |
3f3f7cb8 | 1859 | sum += skb_frag_size(frag++); |
2d37490b AD |
1860 | |
1861 | /* if sum is negative we failed to make sufficient progress */ | |
1862 | if (sum < 0) | |
1863 | return true; | |
1864 | ||
1865 | /* use pre-decrement to avoid processing last fragment */ | |
1866 | if (!--nr_frags) | |
1867 | break; | |
1868 | ||
3f3f7cb8 | 1869 | sum -= skb_frag_size(stale++); |
71da6197 AS |
1870 | } |
1871 | ||
2d37490b | 1872 | return false; |
71da6197 AS |
1873 | } |
1874 | ||
8f6a2b05 JB |
1875 | /** |
1876 | * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions | |
1877 | * @tx_ring: the ring to be checked | |
1878 | * @size: the size buffer we want to assure is available | |
1879 | * | |
1880 | * Returns -EBUSY if a stop is needed, else 0 | |
1881 | **/ | |
4ec441df | 1882 | int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
8f6a2b05 JB |
1883 | { |
1884 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
1885 | /* Memory barrier before checking head and tail */ | |
1886 | smp_mb(); | |
1887 | ||
1888 | /* Check again in a case another CPU has just made room available. */ | |
1889 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
1890 | return -EBUSY; | |
1891 | ||
1892 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
1893 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
1894 | ++tx_ring->tx_stats.restart_queue; | |
1895 | return 0; | |
1896 | } | |
1897 | ||
7f12ad74 | 1898 | /** |
3e587cf3 | 1899 | * i40evf_tx_map - Build the Tx descriptor |
7f12ad74 GR |
1900 | * @tx_ring: ring to send buffer on |
1901 | * @skb: send buffer | |
1902 | * @first: first buffer info buffer to use | |
1903 | * @tx_flags: collected send information | |
1904 | * @hdr_len: size of the packet header | |
1905 | * @td_cmd: the command field in the descriptor | |
1906 | * @td_offset: offset for checksum or crc | |
1907 | **/ | |
3e587cf3 JB |
1908 | static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
1909 | struct i40e_tx_buffer *first, u32 tx_flags, | |
1910 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
7f12ad74 GR |
1911 | { |
1912 | unsigned int data_len = skb->data_len; | |
1913 | unsigned int size = skb_headlen(skb); | |
1914 | struct skb_frag_struct *frag; | |
1915 | struct i40e_tx_buffer *tx_bi; | |
1916 | struct i40e_tx_desc *tx_desc; | |
1917 | u16 i = tx_ring->next_to_use; | |
1918 | u32 td_tag = 0; | |
1919 | dma_addr_t dma; | |
1920 | u16 gso_segs; | |
6a7fded7 ASJ |
1921 | u16 desc_count = 0; |
1922 | bool tail_bump = true; | |
1923 | bool do_rs = false; | |
7f12ad74 GR |
1924 | |
1925 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { | |
1926 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
1927 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
1928 | I40E_TX_FLAGS_VLAN_SHIFT; | |
1929 | } | |
1930 | ||
1931 | if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) | |
1932 | gso_segs = skb_shinfo(skb)->gso_segs; | |
1933 | else | |
1934 | gso_segs = 1; | |
1935 | ||
1936 | /* multiply data chunks by size of headers */ | |
1937 | first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len); | |
1938 | first->gso_segs = gso_segs; | |
1939 | first->skb = skb; | |
1940 | first->tx_flags = tx_flags; | |
1941 | ||
1942 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
1943 | ||
1944 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
1945 | tx_bi = first; | |
1946 | ||
1947 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
5c4654da AD |
1948 | unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
1949 | ||
7f12ad74 GR |
1950 | if (dma_mapping_error(tx_ring->dev, dma)) |
1951 | goto dma_error; | |
1952 | ||
1953 | /* record length, and DMA address */ | |
1954 | dma_unmap_len_set(tx_bi, len, size); | |
1955 | dma_unmap_addr_set(tx_bi, dma, dma); | |
1956 | ||
5c4654da AD |
1957 | /* align size to end of page */ |
1958 | max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); | |
7f12ad74 GR |
1959 | tx_desc->buffer_addr = cpu_to_le64(dma); |
1960 | ||
1961 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
1962 | tx_desc->cmd_type_offset_bsz = | |
1963 | build_ctob(td_cmd, td_offset, | |
5c4654da | 1964 | max_data, td_tag); |
7f12ad74 GR |
1965 | |
1966 | tx_desc++; | |
1967 | i++; | |
6a7fded7 ASJ |
1968 | desc_count++; |
1969 | ||
7f12ad74 GR |
1970 | if (i == tx_ring->count) { |
1971 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
1972 | i = 0; | |
1973 | } | |
1974 | ||
5c4654da AD |
1975 | dma += max_data; |
1976 | size -= max_data; | |
7f12ad74 | 1977 | |
5c4654da | 1978 | max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
7f12ad74 GR |
1979 | tx_desc->buffer_addr = cpu_to_le64(dma); |
1980 | } | |
1981 | ||
1982 | if (likely(!data_len)) | |
1983 | break; | |
1984 | ||
1985 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, | |
1986 | size, td_tag); | |
1987 | ||
1988 | tx_desc++; | |
1989 | i++; | |
6a7fded7 ASJ |
1990 | desc_count++; |
1991 | ||
7f12ad74 GR |
1992 | if (i == tx_ring->count) { |
1993 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
1994 | i = 0; | |
1995 | } | |
1996 | ||
1997 | size = skb_frag_size(frag); | |
1998 | data_len -= size; | |
1999 | ||
2000 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, | |
2001 | DMA_TO_DEVICE); | |
2002 | ||
2003 | tx_bi = &tx_ring->tx_bi[i]; | |
2004 | } | |
2005 | ||
7f12ad74 GR |
2006 | /* set next_to_watch value indicating a packet is present */ |
2007 | first->next_to_watch = tx_desc; | |
2008 | ||
2009 | i++; | |
2010 | if (i == tx_ring->count) | |
2011 | i = 0; | |
2012 | ||
2013 | tx_ring->next_to_use = i; | |
2014 | ||
6a7fded7 ASJ |
2015 | netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev, |
2016 | tx_ring->queue_index), | |
2017 | first->bytecount); | |
4ec441df | 2018 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
6a7fded7 ASJ |
2019 | |
2020 | /* Algorithm to optimize tail and RS bit setting: | |
2021 | * if xmit_more is supported | |
2022 | * if xmit_more is true | |
2023 | * do not update tail and do not mark RS bit. | |
2024 | * if xmit_more is false and last xmit_more was false | |
2025 | * if every packet spanned less than 4 desc | |
2026 | * then set RS bit on 4th packet and update tail | |
2027 | * on every packet | |
2028 | * else | |
2029 | * update tail and set RS bit on every packet. | |
2030 | * if xmit_more is false and last_xmit_more was true | |
2031 | * update tail and set RS bit. | |
6a7fded7 ASJ |
2032 | * |
2033 | * Optimization: wmb to be issued only in case of tail update. | |
2034 | * Also optimize the Descriptor WB path for RS bit with the same | |
2035 | * algorithm. | |
2036 | * | |
2037 | * Note: If there are less than 4 packets | |
2038 | * pending and interrupts were disabled the service task will | |
2039 | * trigger a force WB. | |
2040 | */ | |
2041 | if (skb->xmit_more && | |
2042 | !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, | |
2043 | tx_ring->queue_index))) { | |
2044 | tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; | |
2045 | tail_bump = false; | |
2046 | } else if (!skb->xmit_more && | |
2047 | !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, | |
2048 | tx_ring->queue_index)) && | |
2049 | (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) && | |
2050 | (tx_ring->packet_stride < WB_STRIDE) && | |
2051 | (desc_count < WB_STRIDE)) { | |
2052 | tx_ring->packet_stride++; | |
2053 | } else { | |
2054 | tx_ring->packet_stride = 0; | |
2055 | tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; | |
2056 | do_rs = true; | |
2057 | } | |
2058 | if (do_rs) | |
2059 | tx_ring->packet_stride = 0; | |
2060 | ||
2061 | tx_desc->cmd_type_offset_bsz = | |
2062 | build_ctob(td_cmd, td_offset, size, td_tag) | | |
2063 | cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD : | |
2064 | I40E_TX_DESC_CMD_EOP) << | |
2065 | I40E_TXD_QW1_CMD_SHIFT); | |
2066 | ||
7f12ad74 | 2067 | /* notify HW of packet */ |
6a7fded7 | 2068 | if (!tail_bump) |
489ce7a4 | 2069 | prefetchw(tx_desc + 1); |
7f12ad74 | 2070 | |
6a7fded7 ASJ |
2071 | if (tail_bump) { |
2072 | /* Force memory writes to complete before letting h/w | |
2073 | * know there are new descriptors to fetch. (Only | |
2074 | * applicable for weak-ordered memory model archs, | |
2075 | * such as IA-64). | |
2076 | */ | |
2077 | wmb(); | |
2078 | writel(i, tx_ring->tail); | |
2079 | } | |
2080 | ||
7f12ad74 GR |
2081 | return; |
2082 | ||
2083 | dma_error: | |
2084 | dev_info(tx_ring->dev, "TX DMA map failed\n"); | |
2085 | ||
2086 | /* clear dma mappings for failed tx_bi map */ | |
2087 | for (;;) { | |
2088 | tx_bi = &tx_ring->tx_bi[i]; | |
2089 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); | |
2090 | if (tx_bi == first) | |
2091 | break; | |
2092 | if (i == 0) | |
2093 | i = tx_ring->count; | |
2094 | i--; | |
2095 | } | |
2096 | ||
2097 | tx_ring->next_to_use = i; | |
2098 | } | |
2099 | ||
7f12ad74 GR |
2100 | /** |
2101 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
2102 | * @skb: send buffer | |
2103 | * @tx_ring: ring to send buffer on | |
2104 | * | |
2105 | * Returns NETDEV_TX_OK if sent, else an error code | |
2106 | **/ | |
2107 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
2108 | struct i40e_ring *tx_ring) | |
2109 | { | |
2110 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
2111 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
2112 | struct i40e_tx_buffer *first; | |
2113 | u32 td_offset = 0; | |
2114 | u32 tx_flags = 0; | |
2115 | __be16 protocol; | |
2116 | u32 td_cmd = 0; | |
2117 | u8 hdr_len = 0; | |
4ec441df | 2118 | int tso, count; |
6995b36c | 2119 | |
b74118f0 JB |
2120 | /* prefetch the data, we'll need it later */ |
2121 | prefetch(skb->data); | |
2122 | ||
4ec441df | 2123 | count = i40e_xmit_descriptor_count(skb); |
2d37490b AD |
2124 | if (i40e_chk_linearize(skb, count)) { |
2125 | if (__skb_linearize(skb)) | |
2126 | goto out_drop; | |
5c4654da | 2127 | count = i40e_txd_use_count(skb->len); |
2d37490b AD |
2128 | tx_ring->tx_stats.tx_linearize++; |
2129 | } | |
4ec441df AD |
2130 | |
2131 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
2132 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
2133 | * + 4 desc gap to avoid the cache line where head is, | |
2134 | * + 1 desc for context descriptor, | |
2135 | * otherwise try next time | |
2136 | */ | |
2137 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { | |
2138 | tx_ring->tx_stats.tx_busy++; | |
7f12ad74 | 2139 | return NETDEV_TX_BUSY; |
4ec441df | 2140 | } |
7f12ad74 GR |
2141 | |
2142 | /* prepare the xmit flags */ | |
3e587cf3 | 2143 | if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) |
7f12ad74 GR |
2144 | goto out_drop; |
2145 | ||
2146 | /* obtain protocol of skb */ | |
a12c4158 | 2147 | protocol = vlan_get_protocol(skb); |
7f12ad74 GR |
2148 | |
2149 | /* record the location of the first descriptor for this packet */ | |
2150 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
2151 | ||
2152 | /* setup IPv4/IPv6 offloads */ | |
2153 | if (protocol == htons(ETH_P_IP)) | |
2154 | tx_flags |= I40E_TX_FLAGS_IPV4; | |
2155 | else if (protocol == htons(ETH_P_IPV6)) | |
2156 | tx_flags |= I40E_TX_FLAGS_IPV6; | |
2157 | ||
84b07992 | 2158 | tso = i40e_tso(skb, &hdr_len, &cd_type_cmd_tso_mss); |
7f12ad74 GR |
2159 | |
2160 | if (tso < 0) | |
2161 | goto out_drop; | |
2162 | else if (tso) | |
2163 | tx_flags |= I40E_TX_FLAGS_TSO; | |
2164 | ||
7f12ad74 | 2165 | /* Always offload the checksum, since it's in the data descriptor */ |
529f1f65 AD |
2166 | tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, |
2167 | tx_ring, &cd_tunneling); | |
2168 | if (tso < 0) | |
2169 | goto out_drop; | |
7f12ad74 | 2170 | |
3bc67973 AD |
2171 | skb_tx_timestamp(skb); |
2172 | ||
2173 | /* always enable CRC insertion offload */ | |
2174 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
2175 | ||
7f12ad74 GR |
2176 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, |
2177 | cd_tunneling, cd_l2tag2); | |
2178 | ||
3e587cf3 JB |
2179 | i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len, |
2180 | td_cmd, td_offset); | |
7f12ad74 | 2181 | |
7f12ad74 GR |
2182 | return NETDEV_TX_OK; |
2183 | ||
2184 | out_drop: | |
2185 | dev_kfree_skb_any(skb); | |
2186 | return NETDEV_TX_OK; | |
2187 | } | |
2188 | ||
2189 | /** | |
2190 | * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
2191 | * @skb: send buffer | |
2192 | * @netdev: network interface device structure | |
2193 | * | |
2194 | * Returns NETDEV_TX_OK if sent, else an error code | |
2195 | **/ | |
2196 | netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
2197 | { | |
2198 | struct i40evf_adapter *adapter = netdev_priv(netdev); | |
0dd438d8 | 2199 | struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping]; |
7f12ad74 GR |
2200 | |
2201 | /* hardware can't handle really short frames, hardware padding works | |
2202 | * beyond this point | |
2203 | */ | |
2204 | if (unlikely(skb->len < I40E_MIN_TX_LEN)) { | |
2205 | if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len)) | |
2206 | return NETDEV_TX_OK; | |
2207 | skb->len = I40E_MIN_TX_LEN; | |
2208 | skb_set_tail_pointer(skb, I40E_MIN_TX_LEN); | |
2209 | } | |
2210 | ||
2211 | return i40e_xmit_frame_ring(skb, tx_ring); | |
2212 | } |