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Merge branch 'for-davem' into for-next
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_type.h
CommitLineData
d358aa9a
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
d358aa9a
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
d358aa9a
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_TYPE_H_
28#define _I40E_TYPE_H_
29
30#include "i40e_status.h"
31#include "i40e_osdep.h"
32#include "i40e_register.h"
33#include "i40e_adminq.h"
34#include "i40e_hmc.h"
35#include "i40e_lan_hmc.h"
36
37/* Device IDs */
704599ed 38#define I40E_DEV_ID_SFP_XL710 0x1572
ab60085e
SN		 39#define I40E_DEV_ID_QEMU 0x1574
40#define I40E_DEV_ID_KX_A 0x157F
41#define I40E_DEV_ID_KX_B 0x1580
42#define I40E_DEV_ID_KX_C 0x1581
ab60085e
SN		 43#define I40E_DEV_ID_QSFP_A 0x1583
44#define I40E_DEV_ID_QSFP_B 0x1584
45#define I40E_DEV_ID_QSFP_C 0x1585
1ac1e764 46#define I40E_DEV_ID_10G_BASE_T 0x1586
ae24b409
JB		 47#define I40E_DEV_ID_20G_KR2 0x1587
48#define I40E_DEV_ID_VF 0x154C
ab60085e 49#define I40E_DEV_ID_VF_HV 0x1571
d358aa9a 50
ab60085e
SN		 51#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
52 (d) == I40E_DEV_ID_QSFP_B || \
53 (d) == I40E_DEV_ID_QSFP_C)
d358aa9a 54
4c33f83a
ASJ		 55/* I40E_MASK is a macro used on 32 bit registers */
56#define I40E_MASK(mask, shift) (mask << shift)
57
d358aa9a
GR		 58#define I40E_MAX_VSI_QP 16
59#define I40E_MAX_VF_VSI 3
60#define I40E_MAX_CHAINED_RX_BUFFERS 5
61#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
62
63/* Max default timeout in ms, */
64#define I40E_MAX_NVM_TIMEOUT 18000
65
4f4e17bd
KK		 66/* Switch from ms to the 1usec global time (this is the GTIME resolution) */
67#define I40E_MS_TO_GTIME(time) ((time) * 1000)
d358aa9a
GR		 68
69/* forward declaration */
70struct i40e_hw;
71typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
72
d358aa9a
GR		 73/* Data type manipulation macros. */
74
75#define I40E_DESC_UNUSED(R) \
76 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
77 (R)->next_to_clean - (R)->next_to_use - 1)
78
79/* bitfields for Tx queue mapping in QTX_CTL */
80#define I40E_QTX_CTL_VF_QUEUE 0x0
81#define I40E_QTX_CTL_VM_QUEUE 0x1
82#define I40E_QTX_CTL_PF_QUEUE 0x2
83
84/* debug masks - set these bits in hw->debug_mask to control output */
85enum i40e_debug_mask {
86 I40E_DEBUG_INIT = 0x00000001,
87 I40E_DEBUG_RELEASE = 0x00000002,
88
89 I40E_DEBUG_LINK = 0x00000010,
90 I40E_DEBUG_PHY = 0x00000020,
91 I40E_DEBUG_HMC = 0x00000040,
92 I40E_DEBUG_NVM = 0x00000080,
93 I40E_DEBUG_LAN = 0x00000100,
94 I40E_DEBUG_FLOW = 0x00000200,
95 I40E_DEBUG_DCB = 0x00000400,
96 I40E_DEBUG_DIAG = 0x00000800,
c2e1b596 97 I40E_DEBUG_FD = 0x00001000,
d358aa9a
GR		 98
99 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
100 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
101 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
102 I40E_DEBUG_AQ_COMMAND = 0x06000000,
103 I40E_DEBUG_AQ = 0x0F000000,
104
105 I40E_DEBUG_USER = 0xF0000000,
106
107 I40E_DEBUG_ALL = 0xFFFFFFFF
108};
109
d358aa9a
GR		 110/* These are structs for managing the hardware information and the operations.
111 * The structures of function pointers are filled out at init time when we
112 * know for sure exactly which hardware we're working with. This gives us the
113 * flexibility of using the same main driver code but adapting to slightly
114 * different hardware needs as new parts are developed. For this architecture,
115 * the Firmware and AdminQ are intended to insulate the driver from most of the
116 * future changes, but these structures will also do part of the job.
117 */
118enum i40e_mac_type {
119 I40E_MAC_UNKNOWN = 0,
120 I40E_MAC_X710,
121 I40E_MAC_XL710,
122 I40E_MAC_VF,
123 I40E_MAC_GENERIC,
124};
125
126enum i40e_media_type {
127 I40E_MEDIA_TYPE_UNKNOWN = 0,
128 I40E_MEDIA_TYPE_FIBER,
129 I40E_MEDIA_TYPE_BASET,
130 I40E_MEDIA_TYPE_BACKPLANE,
131 I40E_MEDIA_TYPE_CX4,
132 I40E_MEDIA_TYPE_DA,
133 I40E_MEDIA_TYPE_VIRTUAL
134};
135
136enum i40e_fc_mode {
137 I40E_FC_NONE = 0,
138 I40E_FC_RX_PAUSE,
139 I40E_FC_TX_PAUSE,
140 I40E_FC_FULL,
141 I40E_FC_PFC,
142 I40E_FC_DEFAULT
143};
144
c56999f9
CS		 145enum i40e_set_fc_aq_failures {
146 I40E_SET_FC_AQ_FAIL_NONE = 0,
147 I40E_SET_FC_AQ_FAIL_GET = 1,
148 I40E_SET_FC_AQ_FAIL_SET = 2,
149 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
150 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
151};
152
d358aa9a
GR		 153enum i40e_vsi_type {
154 I40E_VSI_MAIN = 0,
155 I40E_VSI_VMDQ1,
156 I40E_VSI_VMDQ2,
157 I40E_VSI_CTRL,
158 I40E_VSI_FCOE,
159 I40E_VSI_MIRROR,
160 I40E_VSI_SRIOV,
161 I40E_VSI_FDIR,
162 I40E_VSI_TYPE_UNKNOWN
163};
164
165enum i40e_queue_type {
166 I40E_QUEUE_TYPE_RX = 0,
167 I40E_QUEUE_TYPE_TX,
168 I40E_QUEUE_TYPE_PE_CEQ,
169 I40E_QUEUE_TYPE_UNKNOWN
170};
171
172struct i40e_link_status {
173 enum i40e_aq_phy_type phy_type;
174 enum i40e_aq_link_speed link_speed;
175 u8 link_info;
176 u8 an_info;
177 u8 ext_info;
178 u8 loopback;
179 /* is Link Status Event notification to SW enabled */
180 bool lse_enable;
6bb3f23c
NP		 181 u16 max_frame_size;
182 bool crc_enable;
183 u8 pacing;
e827845c 184 u8 requested_speeds;
d358aa9a
GR		 185};
186
187struct i40e_phy_info {
188 struct i40e_link_status link_info;
189 struct i40e_link_status link_info_old;
190 u32 autoneg_advertised;
191 u32 phy_id;
192 u32 module_type;
193 bool get_link_info;
194 enum i40e_media_type media_type;
195};
196
197#define I40E_HW_CAP_MAX_GPIO 30
198/* Capabilities of a PF or a VF or the whole device */
199struct i40e_hw_capabilities {
200 u32 switch_mode;
201#define I40E_NVM_IMAGE_TYPE_EVB 0x0
202#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
203#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
204
205 u32 management_mode;
206 u32 npar_enable;
207 u32 os2bmc;
208 u32 valid_functions;
209 bool sr_iov_1_1;
210 bool vmdq;
211 bool evb_802_1_qbg; /* Edge Virtual Bridging */
212 bool evb_802_1_qbh; /* Bridge Port Extension */
213 bool dcb;
214 bool fcoe;
63d7e5a4 215 bool iscsi; /* Indicates iSCSI enabled */
d358aa9a
GR		 216 bool mfp_mode_1;
217 bool mgmt_cem;
218 bool ieee_1588;
219 bool iwarp;
220 bool fd;
221 u32 fd_filters_guaranteed;
222 u32 fd_filters_best_effort;
223 bool rss;
224 u32 rss_table_size;
225 u32 rss_table_entry_width;
226 bool led[I40E_HW_CAP_MAX_GPIO];
227 bool sdp[I40E_HW_CAP_MAX_GPIO];
228 u32 nvm_image_type;
229 u32 num_flow_director_filters;
230 u32 num_vfs;
231 u32 vf_base_id;
232 u32 num_vsis;
233 u32 num_rx_qp;
234 u32 num_tx_qp;
235 u32 base_queue;
236 u32 num_msix_vectors;
237 u32 num_msix_vectors_vf;
238 u32 led_pin_num;
239 u32 sdp_pin_num;
240 u32 mdio_port_num;
241 u32 mdio_port_mode;
242 u8 rx_buf_chain_len;
243 u32 enabled_tcmap;
244 u32 maxtc;
245};
246
247struct i40e_mac_info {
248 enum i40e_mac_type type;
249 u8 addr[ETH_ALEN];
250 u8 perm_addr[ETH_ALEN];
251 u8 san_addr[ETH_ALEN];
252 u16 max_fcoeq;
253};
254
255enum i40e_aq_resources_ids {
256 I40E_NVM_RESOURCE_ID = 1
257};
258
259enum i40e_aq_resource_access_type {
260 I40E_RESOURCE_READ = 1,
261 I40E_RESOURCE_WRITE
262};
263
264struct i40e_nvm_info {
c509c1de 265 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
d358aa9a
GR		 266 u32 timeout; /* [ms] */
267 u16 sr_size; /* Shadow RAM size in words */
268 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
269 u16 version; /* NVM package version */
270 u32 eetrack; /* NVM data version */
271};
272
cd552cb4
SN		 273/* definitions used in NVM update support */
274
275enum i40e_nvmupd_cmd {
276 I40E_NVMUPD_INVALID,
277 I40E_NVMUPD_READ_CON,
278 I40E_NVMUPD_READ_SNT,
279 I40E_NVMUPD_READ_LCB,
280 I40E_NVMUPD_READ_SA,
281 I40E_NVMUPD_WRITE_ERA,
282 I40E_NVMUPD_WRITE_CON,
283 I40E_NVMUPD_WRITE_SNT,
284 I40E_NVMUPD_WRITE_LCB,
285 I40E_NVMUPD_WRITE_SA,
286 I40E_NVMUPD_CSUM_CON,
287 I40E_NVMUPD_CSUM_SA,
288 I40E_NVMUPD_CSUM_LCB,
289};
290
291enum i40e_nvmupd_state {
292 I40E_NVMUPD_STATE_INIT,
293 I40E_NVMUPD_STATE_READING,
294 I40E_NVMUPD_STATE_WRITING
295};
296
297/* nvm_access definition and its masks/shifts need to be accessible to
298 * application, core driver, and shared code. Where is the right file?
299 */
300#define I40E_NVM_READ 0xB
301#define I40E_NVM_WRITE 0xC
302
303#define I40E_NVM_MOD_PNT_MASK 0xFF
304
305#define I40E_NVM_TRANS_SHIFT 8
306#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
307#define I40E_NVM_CON 0x0
308#define I40E_NVM_SNT 0x1
309#define I40E_NVM_LCB 0x2
310#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
311#define I40E_NVM_ERA 0x4
312#define I40E_NVM_CSUM 0x8
313
314#define I40E_NVM_ADAPT_SHIFT 16
315#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
316
317#define I40E_NVMUPD_MAX_DATA 4096
318#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
319
320struct i40e_nvm_access {
321 u32 command;
322 u32 config;
323 u32 offset; /* in bytes */
324 u32 data_size; /* in bytes */
325 u8 data[1];
326};
327
d358aa9a
GR		 328/* PCI bus types */
329enum i40e_bus_type {
330 i40e_bus_type_unknown = 0,
331 i40e_bus_type_pci,
332 i40e_bus_type_pcix,
333 i40e_bus_type_pci_express,
334 i40e_bus_type_reserved
335};
336
337/* PCI bus speeds */
338enum i40e_bus_speed {
339 i40e_bus_speed_unknown = 0,
340 i40e_bus_speed_33 = 33,
341 i40e_bus_speed_66 = 66,
342 i40e_bus_speed_100 = 100,
343 i40e_bus_speed_120 = 120,
344 i40e_bus_speed_133 = 133,
345 i40e_bus_speed_2500 = 2500,
346 i40e_bus_speed_5000 = 5000,
347 i40e_bus_speed_8000 = 8000,
348 i40e_bus_speed_reserved
349};
350
351/* PCI bus widths */
352enum i40e_bus_width {
353 i40e_bus_width_unknown = 0,
354 i40e_bus_width_pcie_x1 = 1,
355 i40e_bus_width_pcie_x2 = 2,
356 i40e_bus_width_pcie_x4 = 4,
357 i40e_bus_width_pcie_x8 = 8,
358 i40e_bus_width_32 = 32,
359 i40e_bus_width_64 = 64,
360 i40e_bus_width_reserved
361};
362
363/* Bus parameters */
364struct i40e_bus_info {
365 enum i40e_bus_speed speed;
366 enum i40e_bus_width width;
367 enum i40e_bus_type type;
368
369 u16 func;
370 u16 device;
371 u16 lan_id;
372};
373
374/* Flow control (FC) parameters */
375struct i40e_fc_info {
376 enum i40e_fc_mode current_mode; /* FC mode in effect */
377 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
378};
379
380#define I40E_MAX_TRAFFIC_CLASS 8
381#define I40E_MAX_USER_PRIORITY 8
382#define I40E_DCBX_MAX_APPS 32
383#define I40E_LLDPDU_SIZE 1500
384
385/* IEEE 802.1Qaz ETS Configuration data */
386struct i40e_ieee_ets_config {
387 u8 willing;
388 u8 cbs;
389 u8 maxtcs;
390 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
391 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
392 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
393};
394
395/* IEEE 802.1Qaz ETS Recommendation data */
396struct i40e_ieee_ets_recommend {
397 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
398 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
399 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
400};
401
402/* IEEE 802.1Qaz PFC Configuration data */
403struct i40e_ieee_pfc_config {
404 u8 willing;
405 u8 mbc;
406 u8 pfccap;
407 u8 pfcenable;
408};
409
410/* IEEE 802.1Qaz Application Priority data */
411struct i40e_ieee_app_priority_table {
412 u8 priority;
413 u8 selector;
414 u16 protocolid;
415};
416
417struct i40e_dcbx_config {
418 u32 numapps;
419 struct i40e_ieee_ets_config etscfg;
420 struct i40e_ieee_ets_recommend etsrec;
421 struct i40e_ieee_pfc_config pfc;
422 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
423};
424
425/* Port hardware description */
426struct i40e_hw {
427 u8 __iomem *hw_addr;
428 void *back;
429
9fee9db5 430 /* subsystem structs */
d358aa9a
GR		 431 struct i40e_phy_info phy;
432 struct i40e_mac_info mac;
433 struct i40e_bus_info bus;
434 struct i40e_nvm_info nvm;
435 struct i40e_fc_info fc;
436
437 /* pci info */
438 u16 device_id;
439 u16 vendor_id;
440 u16 subsystem_device_id;
441 u16 subsystem_vendor_id;
442 u8 revision_id;
443 u8 port;
444 bool adapter_stopped;
445
446 /* capabilities for entire device and PCI func */
447 struct i40e_hw_capabilities dev_caps;
448 struct i40e_hw_capabilities func_caps;
449
450 /* Flow Director shared filter space */
451 u16 fdir_shared_filter_count;
452
453 /* device profile info */
454 u8 pf_id;
455 u16 main_vsi_seid;
456
9fee9db5
SN		 457 /* for multi-function MACs */
458 u16 partition_id;
459 u16 num_partitions;
460 u16 num_ports;
461
d358aa9a
GR		 462 /* Closest numa node to the device */
463 u16 numa_node;
464
465 /* Admin Queue info */
466 struct i40e_adminq_info aq;
467
cd552cb4
SN		 468 /* state of nvm update process */
469 enum i40e_nvmupd_state nvmupd_state;
470
d358aa9a
GR		 471 /* HMC info */
472 struct i40e_hmc_info hmc; /* HMC info struct */
473
474 /* LLDP/DCBX Status */
475 u16 dcbx_status;
476
477 /* DCBX info */
478 struct i40e_dcbx_config local_dcbx_config;
479 struct i40e_dcbx_config remote_dcbx_config;
480
481 /* debug mask */
482 u32 debug_mask;
483};
484
4bd145be
JK		 485static inline bool i40e_is_vf(struct i40e_hw *hw)
486{
487 return hw->mac.type == I40E_MAC_VF;
488}
e7f2e4b9 489
d358aa9a
GR		 490struct i40e_driver_version {
491 u8 major_version;
492 u8 minor_version;
493 u8 build_version;
494 u8 subbuild_version;
d2466013 495 u8 driver_string[32];
d358aa9a
GR		 496};
497
498/* RX Descriptors */
499union i40e_16byte_rx_desc {
500 struct {
501 __le64 pkt_addr; /* Packet buffer address */
502 __le64 hdr_addr; /* Header buffer address */
503 } read;
504 struct {
505 struct {
506 struct {
507 union {
508 __le16 mirroring_status;
509 __le16 fcoe_ctx_id;
510 } mirr_fcoe;
511 __le16 l2tag1;
512 } lo_dword;
513 union {
514 __le32 rss; /* RSS Hash */
515 __le32 fd_id; /* Flow director filter id */
516 __le32 fcoe_param; /* FCoE DDP Context id */
517 } hi_dword;
518 } qword0;
519 struct {
520 /* ext status/error/pktype/length */
521 __le64 status_error_len;
522 } qword1;
523 } wb; /* writeback */
524};
525
526union i40e_32byte_rx_desc {
527 struct {
528 __le64 pkt_addr; /* Packet buffer address */
529 __le64 hdr_addr; /* Header buffer address */
530 /* bit 0 of hdr_buffer_addr is DD bit */
531 __le64 rsvd1;
532 __le64 rsvd2;
533 } read;
534 struct {
535 struct {
536 struct {
537 union {
538 __le16 mirroring_status;
539 __le16 fcoe_ctx_id;
540 } mirr_fcoe;
541 __le16 l2tag1;
542 } lo_dword;
543 union {
544 __le32 rss; /* RSS Hash */
545 __le32 fcoe_param; /* FCoE DDP Context id */
77e29bc6
ASJ		 546 /* Flow director filter id in case of
547 * Programming status desc WB
548 */
549 __le32 fd_id;
d358aa9a
GR		 550 } hi_dword;
551 } qword0;
552 struct {
553 /* status/error/pktype/length */
554 __le64 status_error_len;
555 } qword1;
556 struct {
557 __le16 ext_status; /* extended status */
558 __le16 rsvd;
559 __le16 l2tag2_1;
560 __le16 l2tag2_2;
561 } qword2;
562 struct {
563 union {
564 __le32 flex_bytes_lo;
565 __le32 pe_status;
566 } lo_dword;
567 union {
568 __le32 flex_bytes_hi;
569 __le32 fd_id;
570 } hi_dword;
571 } qword3;
572 } wb; /* writeback */
573};
574
d358aa9a
GR		 575enum i40e_rx_desc_status_bits {
576 /* Note: These are predefined bit offsets */
577 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
578 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
579 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
580 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
581 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
582 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
583 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
584 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
585 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
586 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
587 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
588 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
589 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
590 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
c2451d7f
JB		 591 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
592 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
d358aa9a
GR		 593};
594
c2451d7f
JB		 595#define I40E_RXD_QW1_STATUS_SHIFT 0
596#define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
597 << I40E_RXD_QW1_STATUS_SHIFT)
598
d358aa9a
GR		 599#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
600#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
601 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
602
603#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
604#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
605 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
606
607enum i40e_rx_desc_fltstat_values {
608 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
609 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
610 I40E_RX_DESC_FLTSTAT_RSV = 2,
611 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
612};
613
614#define I40E_RXD_QW1_ERROR_SHIFT 19
615#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
616
617enum i40e_rx_desc_error_bits {
618 /* Note: These are predefined bit offsets */
619 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
620 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
621 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
622 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
623 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
624 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
625 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
8a3c91cc
JB		 626 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
627 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
d358aa9a
GR		 628};
629
630enum i40e_rx_desc_error_l3l4e_fcoe_masks {
631 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
632 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
633 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
634 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
635 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
636};
637
638#define I40E_RXD_QW1_PTYPE_SHIFT 30
639#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
640
641/* Packet type non-ip values */
642enum i40e_rx_l2_ptype {
643 I40E_RX_PTYPE_L2_RESERVED = 0,
644 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
645 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
646 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
647 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
648 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
649 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
650 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
651 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
652 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
653 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
654 I40E_RX_PTYPE_L2_ARP = 11,
655 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
656 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
657 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
658 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
659 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
660 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
661 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
662 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
663 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
664 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
665 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
666 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
667 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
668 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
669};
670
671struct i40e_rx_ptype_decoded {
672 u32 ptype:8;
673 u32 known:1;
674 u32 outer_ip:1;
675 u32 outer_ip_ver:1;
676 u32 outer_frag:1;
677 u32 tunnel_type:3;
678 u32 tunnel_end_prot:2;
679 u32 tunnel_end_frag:1;
680 u32 inner_prot:4;
681 u32 payload_layer:3;
682};
683
684enum i40e_rx_ptype_outer_ip {
685 I40E_RX_PTYPE_OUTER_L2 = 0,
686 I40E_RX_PTYPE_OUTER_IP = 1
687};
688
689enum i40e_rx_ptype_outer_ip_ver {
690 I40E_RX_PTYPE_OUTER_NONE = 0,
691 I40E_RX_PTYPE_OUTER_IPV4 = 0,
692 I40E_RX_PTYPE_OUTER_IPV6 = 1
693};
694
695enum i40e_rx_ptype_outer_fragmented {
696 I40E_RX_PTYPE_NOT_FRAG = 0,
697 I40E_RX_PTYPE_FRAG = 1
698};
699
700enum i40e_rx_ptype_tunnel_type {
701 I40E_RX_PTYPE_TUNNEL_NONE = 0,
702 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
703 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
704 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
705 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
706};
707
708enum i40e_rx_ptype_tunnel_end_prot {
709 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
710 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
711 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
712};
713
714enum i40e_rx_ptype_inner_prot {
715 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
716 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
717 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
718 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
719 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
720 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
721};
722
723enum i40e_rx_ptype_payload_layer {
724 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
725 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
726 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
727 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
728};
729
730#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
731#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
732 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
733
734#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
735#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
736 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
737
738#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
739#define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
740 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
741
742enum i40e_rx_desc_ext_status_bits {
743 /* Note: These are predefined bit offsets */
744 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
745 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
746 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
747 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
d358aa9a
GR		 748 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
749 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
750 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
751};
752
753enum i40e_rx_desc_pe_status_bits {
754 /* Note: These are predefined bit offsets */
755 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
756 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
757 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
758 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
759 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
760 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
761 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
762 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
763 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
764};
765
766#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
767#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
768
769#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
770#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
771 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
772
773#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
774#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
775 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
776
777enum i40e_rx_prog_status_desc_status_bits {
778 /* Note: These are predefined bit offsets */
779 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
780 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
781};
782
783enum i40e_rx_prog_status_desc_prog_id_masks {
784 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
785 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
786 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
787};
788
789enum i40e_rx_prog_status_desc_error_bits {
790 /* Note: These are predefined bit offsets */
791 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
77e29bc6 792 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
d358aa9a
GR		 793 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
794 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
795};
796
797/* TX Descriptor */
798struct i40e_tx_desc {
799 __le64 buffer_addr; /* Address of descriptor's data buf */
800 __le64 cmd_type_offset_bsz;
801};
802
803#define I40E_TXD_QW1_DTYPE_SHIFT 0
804#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
805
806enum i40e_tx_desc_dtype_value {
807 I40E_TX_DESC_DTYPE_DATA = 0x0,
808 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
809 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
810 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
811 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
812 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
813 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
814 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
815 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
816 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
817};
818
819#define I40E_TXD_QW1_CMD_SHIFT 4
820#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
821
822enum i40e_tx_desc_cmd_bits {
823 I40E_TX_DESC_CMD_EOP = 0x0001,
824 I40E_TX_DESC_CMD_RS = 0x0002,
825 I40E_TX_DESC_CMD_ICRC = 0x0004,
826 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
827 I40E_TX_DESC_CMD_DUMMY = 0x0010,
828 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
829 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
830 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
831 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
832 I40E_TX_DESC_CMD_FCOET = 0x0080,
833 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
834 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
835 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
836 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
837 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
838 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
839 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
840 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
841};
842
843#define I40E_TXD_QW1_OFFSET_SHIFT 16
844#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
845 I40E_TXD_QW1_OFFSET_SHIFT)
846
847enum i40e_tx_desc_length_fields {
848 /* Note: These are predefined bit offsets */
849 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
850 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
851 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
852};
853
854#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
855#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
856 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
857
858#define I40E_TXD_QW1_L2TAG1_SHIFT 48
859#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
860
861/* Context descriptors */
862struct i40e_tx_context_desc {
863 __le32 tunneling_params;
864 __le16 l2tag2;
865 __le16 rsvd;
866 __le64 type_cmd_tso_mss;
867};
868
869#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
870#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
871
872#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
873#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
874
875enum i40e_tx_ctx_desc_cmd_bits {
876 I40E_TX_CTX_DESC_TSO = 0x01,
877 I40E_TX_CTX_DESC_TSYN = 0x02,
878 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
879 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
880 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
881 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
882 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
883 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
884 I40E_TX_CTX_DESC_SWPE = 0x40
885};
886
887#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
888#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
889 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
890
891#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
892#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
893 I40E_TXD_CTX_QW1_MSS_SHIFT)
894
895#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
896#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
897
898#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
899#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
900 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
901
902enum i40e_tx_ctx_desc_eipt_offload {
903 I40E_TX_CTX_EXT_IP_NONE = 0x0,
904 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
905 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
906 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
907};
908
909#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
910#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
911 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
912
913#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
914#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
915
916#define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
917#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
918
919#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
920#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
921 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
922
923#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
924
925#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
926#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
927 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
928
929#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
930#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
931 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
932
933struct i40e_filter_program_desc {
934 __le32 qindex_flex_ptype_vsi;
935 __le32 rsvd;
936 __le32 dtype_cmd_cntindex;
937 __le32 fd_id;
938};
939#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
940#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
941 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
942#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
943#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
944 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
945#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
946#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
947 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
948
949/* Packet Classifier Types for filters */
950enum i40e_filter_pctype {
b2d36c03 951 /* Note: Values 0-30 are reserved for future use */
d358aa9a 952 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
b2d36c03 953 /* Note: Value 32 is reserved for future use */
d358aa9a
GR		 954 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
955 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
956 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
957 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
b2d36c03 958 /* Note: Values 37-40 are reserved for future use */
d358aa9a 959 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
d358aa9a
GR		 960 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
961 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
962 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
963 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
964 /* Note: Value 47 is reserved for future use */
965 I40E_FILTER_PCTYPE_FCOE_OX = 48,
966 I40E_FILTER_PCTYPE_FCOE_RX = 49,
967 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
968 /* Note: Values 51-62 are reserved for future use */
969 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
970};
971
972enum i40e_filter_program_desc_dest {
973 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
974 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
975 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
976};
977
978enum i40e_filter_program_desc_fd_status {
979 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
980 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
981 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
982 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
983};
984
985#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
986#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
987 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
988
989#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
990#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
991 I40E_TXD_FLTR_QW1_CMD_SHIFT)
992
993#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
994#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
995
996enum i40e_filter_program_desc_pcmd {
997 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
998 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
999};
1000
1001#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1002#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1003
1004#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1005#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
1006 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1007
1008#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1009 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1010#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1011 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1012
1013#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1014#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1015 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1016
1017enum i40e_filter_type {
1018 I40E_FLOW_DIRECTOR_FLTR = 0,
1019 I40E_PE_QUAD_HASH_FLTR = 1,
1020 I40E_ETHERTYPE_FLTR,
1021 I40E_FCOE_CTX_FLTR,
1022 I40E_MAC_VLAN_FLTR,
1023 I40E_HASH_FLTR
1024};
1025
1026struct i40e_vsi_context {
1027 u16 seid;
1028 u16 uplink_seid;
1029 u16 vsi_number;
1030 u16 vsis_allocated;
1031 u16 vsis_unallocated;
1032 u16 flags;
1033 u8 pf_num;
1034 u8 vf_num;
1035 u8 connection_type;
1036 struct i40e_aqc_vsi_properties_data info;
1037};
1038
4f4e17bd
KK		 1039struct i40e_veb_context {
1040 u16 seid;
1041 u16 uplink_seid;
1042 u16 veb_number;
1043 u16 vebs_allocated;
1044 u16 vebs_unallocated;
1045 u16 flags;
1046 struct i40e_aqc_get_veb_parameters_completion info;
1047};
1048
d358aa9a
GR		 1049/* Statistics collected by each port, VSI, VEB, and S-channel */
1050struct i40e_eth_stats {
1051 u64 rx_bytes; /* gorc */
1052 u64 rx_unicast; /* uprc */
1053 u64 rx_multicast; /* mprc */
1054 u64 rx_broadcast; /* bprc */
1055 u64 rx_discards; /* rdpc */
d358aa9a
GR		 1056 u64 rx_unknown_protocol; /* rupp */
1057 u64 tx_bytes; /* gotc */
1058 u64 tx_unicast; /* uptc */
1059 u64 tx_multicast; /* mptc */
1060 u64 tx_broadcast; /* bptc */
1061 u64 tx_discards; /* tdpc */
1062 u64 tx_errors; /* tepc */
1063};
1064
1065/* Statistics collected by the MAC */
1066struct i40e_hw_port_stats {
1067 /* eth stats collected by the port */
1068 struct i40e_eth_stats eth;
1069
1070 /* additional port specific stats */
1071 u64 tx_dropped_link_down; /* tdold */
1072 u64 crc_errors; /* crcerrs */
1073 u64 illegal_bytes; /* illerrc */
1074 u64 error_bytes; /* errbc */
1075 u64 mac_local_faults; /* mlfc */
1076 u64 mac_remote_faults; /* mrfc */
1077 u64 rx_length_errors; /* rlec */
1078 u64 link_xon_rx; /* lxonrxc */
1079 u64 link_xoff_rx; /* lxoffrxc */
1080 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1081 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1082 u64 link_xon_tx; /* lxontxc */
1083 u64 link_xoff_tx; /* lxofftxc */
1084 u64 priority_xon_tx[8]; /* pxontxc[8] */
1085 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1086 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1087 u64 rx_size_64; /* prc64 */
1088 u64 rx_size_127; /* prc127 */
1089 u64 rx_size_255; /* prc255 */
1090 u64 rx_size_511; /* prc511 */
1091 u64 rx_size_1023; /* prc1023 */
1092 u64 rx_size_1522; /* prc1522 */
1093 u64 rx_size_big; /* prc9522 */
1094 u64 rx_undersize; /* ruc */
1095 u64 rx_fragments; /* rfc */
1096 u64 rx_oversize; /* roc */
1097 u64 rx_jabber; /* rjc */
1098 u64 tx_size_64; /* ptc64 */
1099 u64 tx_size_127; /* ptc127 */
1100 u64 tx_size_255; /* ptc255 */
1101 u64 tx_size_511; /* ptc511 */
1102 u64 tx_size_1023; /* ptc1023 */
1103 u64 tx_size_1522; /* ptc1522 */
1104 u64 tx_size_big; /* ptc9522 */
1105 u64 mac_short_packet_dropped; /* mspdc */
1106 u64 checksum_error; /* xec */
433c47de
ASJ		 1107 /* flow director stats */
1108 u64 fd_atr_match;
1109 u64 fd_sb_match;
bee5af7e 1110 /* EEE LPI */
10bc478a
GR		 1111 u32 tx_lpi_status;
1112 u32 rx_lpi_status;
bee5af7e
ASJ		 1113 u64 tx_lpi_count; /* etlpic */
1114 u64 rx_lpi_count; /* erlpic */
d358aa9a
GR		 1115};
1116
1117/* Checksum and Shadow RAM pointers */
1118#define I40E_SR_NVM_CONTROL_WORD 0x00
1119#define I40E_SR_EMP_MODULE_PTR 0x0F
4f651a5b 1120#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
d358aa9a
GR		 1121#define I40E_SR_NVM_WAKE_ON_LAN 0x19
1122#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1123#define I40E_SR_NVM_EETRACK_LO 0x2D
1124#define I40E_SR_NVM_EETRACK_HI 0x2E
1125#define I40E_SR_VPD_PTR 0x2F
1126#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1127#define I40E_SR_SW_CHECKSUM_WORD 0x3F
1128
1129/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1130#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1131#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1132#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1133#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1134
1135/* Shadow RAM related */
1136#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1137#define I40E_SR_WORDS_IN_1KB 512
1138/* Checksum should be calculated such that after adding all the words,
1139 * including the checksum word itself, the sum should be 0xBABA.
1140 */
1141#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1142
1143#define I40E_SRRD_SRCTL_ATTEMPTS 100000
1144
1145enum i40e_switch_element_types {
1146 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1147 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1148 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1149 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1150 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1151 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1152 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1153 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1154 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1155};
1156
1157/* Supported EtherType filters */
1158enum i40e_ether_type_index {
1159 I40E_ETHER_TYPE_1588 = 0,
1160 I40E_ETHER_TYPE_FIP = 1,
1161 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1162 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1163 I40E_ETHER_TYPE_LLDP = 4,
1164 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1165 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1166 I40E_ETHER_TYPE_QCN_CNM = 7,
1167 I40E_ETHER_TYPE_8021X = 8,
1168 I40E_ETHER_TYPE_ARP = 9,
1169 I40E_ETHER_TYPE_RSV1 = 10,
1170 I40E_ETHER_TYPE_RSV2 = 11,
1171};
1172
1173/* Filter context base size is 1K */
1174#define I40E_HASH_FILTER_BASE_SIZE 1024
1175/* Supported Hash filter values */
1176enum i40e_hash_filter_size {
1177 I40E_HASH_FILTER_SIZE_1K = 0,
1178 I40E_HASH_FILTER_SIZE_2K = 1,
1179 I40E_HASH_FILTER_SIZE_4K = 2,
1180 I40E_HASH_FILTER_SIZE_8K = 3,
1181 I40E_HASH_FILTER_SIZE_16K = 4,
1182 I40E_HASH_FILTER_SIZE_32K = 5,
1183 I40E_HASH_FILTER_SIZE_64K = 6,
1184 I40E_HASH_FILTER_SIZE_128K = 7,
1185 I40E_HASH_FILTER_SIZE_256K = 8,
1186 I40E_HASH_FILTER_SIZE_512K = 9,
1187 I40E_HASH_FILTER_SIZE_1M = 10,
1188};
1189
1190/* DMA context base size is 0.5K */
1191#define I40E_DMA_CNTX_BASE_SIZE 512
1192/* Supported DMA context values */
1193enum i40e_dma_cntx_size {
1194 I40E_DMA_CNTX_SIZE_512 = 0,
1195 I40E_DMA_CNTX_SIZE_1K = 1,
1196 I40E_DMA_CNTX_SIZE_2K = 2,
1197 I40E_DMA_CNTX_SIZE_4K = 3,
1198 I40E_DMA_CNTX_SIZE_8K = 4,
1199 I40E_DMA_CNTX_SIZE_16K = 5,
1200 I40E_DMA_CNTX_SIZE_32K = 6,
1201 I40E_DMA_CNTX_SIZE_64K = 7,
1202 I40E_DMA_CNTX_SIZE_128K = 8,
1203 I40E_DMA_CNTX_SIZE_256K = 9,
1204};
1205
1206/* Supported Hash look up table (LUT) sizes */
1207enum i40e_hash_lut_size {
1208 I40E_HASH_LUT_SIZE_128 = 0,
1209 I40E_HASH_LUT_SIZE_512 = 1,
1210};
1211
1212/* Structure to hold a per PF filter control settings */
1213struct i40e_filter_control_settings {
1214 /* number of PE Quad Hash filter buckets */
1215 enum i40e_hash_filter_size pe_filt_num;
1216 /* number of PE Quad Hash contexts */
1217 enum i40e_dma_cntx_size pe_cntx_num;
1218 /* number of FCoE filter buckets */
1219 enum i40e_hash_filter_size fcoe_filt_num;
1220 /* number of FCoE DDP contexts */
1221 enum i40e_dma_cntx_size fcoe_cntx_num;
1222 /* size of the Hash LUT */
1223 enum i40e_hash_lut_size hash_lut_size;
1224 /* enable FDIR filters for PF and its VFs */
1225 bool enable_fdir;
1226 /* enable Ethertype filters for PF and its VFs */
1227 bool enable_ethtype;
1228 /* enable MAC/VLAN filters for PF and its VFs */
1229 bool enable_macvlan;
1230};
1231
1232/* Structure to hold device level control filter counts */
1233struct i40e_control_filter_stats {
1234 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1235 u16 etype_used; /* Used perfect EtherType filters */
1236 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1237 u16 etype_free; /* Un-used perfect EtherType filters */
1238};
1239
1240enum i40e_reset_type {
1241 I40E_RESET_POR = 0,
1242 I40E_RESET_CORER = 1,
1243 I40E_RESET_GLOBR = 2,
1244 I40E_RESET_EMPR = 3,
1245};
e157ea30
CW		 1246
1247/* RSS Hash Table Size */
1248#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
d358aa9a 1249#endif /* _I40E_TYPE_H_ */
Linux kernel - Deliverables
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