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i40evf: init code and hardware support
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_type.h
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d358aa9a
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Contact Information:
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 *
22 ******************************************************************************/
23
24#ifndef _I40E_TYPE_H_
25#define _I40E_TYPE_H_
26
27#include "i40e_status.h"
28#include "i40e_osdep.h"
29#include "i40e_register.h"
30#include "i40e_adminq.h"
31#include "i40e_hmc.h"
32#include "i40e_lan_hmc.h"
33
34/* Device IDs */
35#define I40E_SFP_XL710_DEVICE_ID 0x1572
36#define I40E_SFP_X710_DEVICE_ID 0x1573
37#define I40E_QEMU_DEVICE_ID 0x1574
38#define I40E_KX_A_DEVICE_ID 0x157F
39#define I40E_KX_B_DEVICE_ID 0x1580
40#define I40E_KX_C_DEVICE_ID 0x1581
41#define I40E_KX_D_DEVICE_ID 0x1582
42#define I40E_QSFP_A_DEVICE_ID 0x1583
43#define I40E_QSFP_B_DEVICE_ID 0x1584
44#define I40E_QSFP_C_DEVICE_ID 0x1585
45#define I40E_VF_DEVICE_ID 0x154C
46#define I40E_VF_HV_DEVICE_ID 0x1571
47
48#define i40e_is_40G_device(d) ((d) == I40E_QSFP_A_DEVICE_ID || \
49 (d) == I40E_QSFP_B_DEVICE_ID || \
50 (d) == I40E_QSFP_C_DEVICE_ID)
51
52#define I40E_MAX_VSI_QP 16
53#define I40E_MAX_VF_VSI 3
54#define I40E_MAX_CHAINED_RX_BUFFERS 5
55#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
56
57/* Max default timeout in ms, */
58#define I40E_MAX_NVM_TIMEOUT 18000
59
60/* Switch from mc to the 2usec global time (this is the GTIME resolution) */
61#define I40E_MS_TO_GTIME(time) (((time) * 1000) / 2)
62
63/* forward declaration */
64struct i40e_hw;
65typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
66
67#define ETH_ALEN 6
68
69/* Data type manipulation macros. */
70
71#define I40E_DESC_UNUSED(R) \
72 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
73 (R)->next_to_clean - (R)->next_to_use - 1)
74
75/* bitfields for Tx queue mapping in QTX_CTL */
76#define I40E_QTX_CTL_VF_QUEUE 0x0
77#define I40E_QTX_CTL_VM_QUEUE 0x1
78#define I40E_QTX_CTL_PF_QUEUE 0x2
79
80/* debug masks - set these bits in hw->debug_mask to control output */
81enum i40e_debug_mask {
82 I40E_DEBUG_INIT = 0x00000001,
83 I40E_DEBUG_RELEASE = 0x00000002,
84
85 I40E_DEBUG_LINK = 0x00000010,
86 I40E_DEBUG_PHY = 0x00000020,
87 I40E_DEBUG_HMC = 0x00000040,
88 I40E_DEBUG_NVM = 0x00000080,
89 I40E_DEBUG_LAN = 0x00000100,
90 I40E_DEBUG_FLOW = 0x00000200,
91 I40E_DEBUG_DCB = 0x00000400,
92 I40E_DEBUG_DIAG = 0x00000800,
93
94 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
95 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
96 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
97 I40E_DEBUG_AQ_COMMAND = 0x06000000,
98 I40E_DEBUG_AQ = 0x0F000000,
99
100 I40E_DEBUG_USER = 0xF0000000,
101
102 I40E_DEBUG_ALL = 0xFFFFFFFF
103};
104
105/* PCI Bus Info */
106#define I40E_PCI_LINK_WIDTH_1 0x10
107#define I40E_PCI_LINK_WIDTH_2 0x20
108#define I40E_PCI_LINK_WIDTH_4 0x40
109#define I40E_PCI_LINK_WIDTH_8 0x80
110#define I40E_PCI_LINK_SPEED_2500 0x1
111#define I40E_PCI_LINK_SPEED_5000 0x2
112#define I40E_PCI_LINK_SPEED_8000 0x3
113
114/* These are structs for managing the hardware information and the operations.
115 * The structures of function pointers are filled out at init time when we
116 * know for sure exactly which hardware we're working with. This gives us the
117 * flexibility of using the same main driver code but adapting to slightly
118 * different hardware needs as new parts are developed. For this architecture,
119 * the Firmware and AdminQ are intended to insulate the driver from most of the
120 * future changes, but these structures will also do part of the job.
121 */
122enum i40e_mac_type {
123 I40E_MAC_UNKNOWN = 0,
124 I40E_MAC_X710,
125 I40E_MAC_XL710,
126 I40E_MAC_VF,
127 I40E_MAC_GENERIC,
128};
129
130enum i40e_media_type {
131 I40E_MEDIA_TYPE_UNKNOWN = 0,
132 I40E_MEDIA_TYPE_FIBER,
133 I40E_MEDIA_TYPE_BASET,
134 I40E_MEDIA_TYPE_BACKPLANE,
135 I40E_MEDIA_TYPE_CX4,
136 I40E_MEDIA_TYPE_DA,
137 I40E_MEDIA_TYPE_VIRTUAL
138};
139
140enum i40e_fc_mode {
141 I40E_FC_NONE = 0,
142 I40E_FC_RX_PAUSE,
143 I40E_FC_TX_PAUSE,
144 I40E_FC_FULL,
145 I40E_FC_PFC,
146 I40E_FC_DEFAULT
147};
148
149enum i40e_vsi_type {
150 I40E_VSI_MAIN = 0,
151 I40E_VSI_VMDQ1,
152 I40E_VSI_VMDQ2,
153 I40E_VSI_CTRL,
154 I40E_VSI_FCOE,
155 I40E_VSI_MIRROR,
156 I40E_VSI_SRIOV,
157 I40E_VSI_FDIR,
158 I40E_VSI_TYPE_UNKNOWN
159};
160
161enum i40e_queue_type {
162 I40E_QUEUE_TYPE_RX = 0,
163 I40E_QUEUE_TYPE_TX,
164 I40E_QUEUE_TYPE_PE_CEQ,
165 I40E_QUEUE_TYPE_UNKNOWN
166};
167
168struct i40e_link_status {
169 enum i40e_aq_phy_type phy_type;
170 enum i40e_aq_link_speed link_speed;
171 u8 link_info;
172 u8 an_info;
173 u8 ext_info;
174 u8 loopback;
175 /* is Link Status Event notification to SW enabled */
176 bool lse_enable;
177};
178
179struct i40e_phy_info {
180 struct i40e_link_status link_info;
181 struct i40e_link_status link_info_old;
182 u32 autoneg_advertised;
183 u32 phy_id;
184 u32 module_type;
185 bool get_link_info;
186 enum i40e_media_type media_type;
187};
188
189#define I40E_HW_CAP_MAX_GPIO 30
190/* Capabilities of a PF or a VF or the whole device */
191struct i40e_hw_capabilities {
192 u32 switch_mode;
193#define I40E_NVM_IMAGE_TYPE_EVB 0x0
194#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
195#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
196
197 u32 management_mode;
198 u32 npar_enable;
199 u32 os2bmc;
200 u32 valid_functions;
201 bool sr_iov_1_1;
202 bool vmdq;
203 bool evb_802_1_qbg; /* Edge Virtual Bridging */
204 bool evb_802_1_qbh; /* Bridge Port Extension */
205 bool dcb;
206 bool fcoe;
207 bool mfp_mode_1;
208 bool mgmt_cem;
209 bool ieee_1588;
210 bool iwarp;
211 bool fd;
212 u32 fd_filters_guaranteed;
213 u32 fd_filters_best_effort;
214 bool rss;
215 u32 rss_table_size;
216 u32 rss_table_entry_width;
217 bool led[I40E_HW_CAP_MAX_GPIO];
218 bool sdp[I40E_HW_CAP_MAX_GPIO];
219 u32 nvm_image_type;
220 u32 num_flow_director_filters;
221 u32 num_vfs;
222 u32 vf_base_id;
223 u32 num_vsis;
224 u32 num_rx_qp;
225 u32 num_tx_qp;
226 u32 base_queue;
227 u32 num_msix_vectors;
228 u32 num_msix_vectors_vf;
229 u32 led_pin_num;
230 u32 sdp_pin_num;
231 u32 mdio_port_num;
232 u32 mdio_port_mode;
233 u8 rx_buf_chain_len;
234 u32 enabled_tcmap;
235 u32 maxtc;
236};
237
238struct i40e_mac_info {
239 enum i40e_mac_type type;
240 u8 addr[ETH_ALEN];
241 u8 perm_addr[ETH_ALEN];
242 u8 san_addr[ETH_ALEN];
243 u16 max_fcoeq;
244};
245
246enum i40e_aq_resources_ids {
247 I40E_NVM_RESOURCE_ID = 1
248};
249
250enum i40e_aq_resource_access_type {
251 I40E_RESOURCE_READ = 1,
252 I40E_RESOURCE_WRITE
253};
254
255struct i40e_nvm_info {
256 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
257 u64 hw_semaphore_wait; /* - || - */
258 u32 timeout; /* [ms] */
259 u16 sr_size; /* Shadow RAM size in words */
260 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
261 u16 version; /* NVM package version */
262 u32 eetrack; /* NVM data version */
263};
264
265/* PCI bus types */
266enum i40e_bus_type {
267 i40e_bus_type_unknown = 0,
268 i40e_bus_type_pci,
269 i40e_bus_type_pcix,
270 i40e_bus_type_pci_express,
271 i40e_bus_type_reserved
272};
273
274/* PCI bus speeds */
275enum i40e_bus_speed {
276 i40e_bus_speed_unknown = 0,
277 i40e_bus_speed_33 = 33,
278 i40e_bus_speed_66 = 66,
279 i40e_bus_speed_100 = 100,
280 i40e_bus_speed_120 = 120,
281 i40e_bus_speed_133 = 133,
282 i40e_bus_speed_2500 = 2500,
283 i40e_bus_speed_5000 = 5000,
284 i40e_bus_speed_8000 = 8000,
285 i40e_bus_speed_reserved
286};
287
288/* PCI bus widths */
289enum i40e_bus_width {
290 i40e_bus_width_unknown = 0,
291 i40e_bus_width_pcie_x1 = 1,
292 i40e_bus_width_pcie_x2 = 2,
293 i40e_bus_width_pcie_x4 = 4,
294 i40e_bus_width_pcie_x8 = 8,
295 i40e_bus_width_32 = 32,
296 i40e_bus_width_64 = 64,
297 i40e_bus_width_reserved
298};
299
300/* Bus parameters */
301struct i40e_bus_info {
302 enum i40e_bus_speed speed;
303 enum i40e_bus_width width;
304 enum i40e_bus_type type;
305
306 u16 func;
307 u16 device;
308 u16 lan_id;
309};
310
311/* Flow control (FC) parameters */
312struct i40e_fc_info {
313 enum i40e_fc_mode current_mode; /* FC mode in effect */
314 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
315};
316
317#define I40E_MAX_TRAFFIC_CLASS 8
318#define I40E_MAX_USER_PRIORITY 8
319#define I40E_DCBX_MAX_APPS 32
320#define I40E_LLDPDU_SIZE 1500
321
322/* IEEE 802.1Qaz ETS Configuration data */
323struct i40e_ieee_ets_config {
324 u8 willing;
325 u8 cbs;
326 u8 maxtcs;
327 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
328 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
329 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
330};
331
332/* IEEE 802.1Qaz ETS Recommendation data */
333struct i40e_ieee_ets_recommend {
334 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
335 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
336 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
337};
338
339/* IEEE 802.1Qaz PFC Configuration data */
340struct i40e_ieee_pfc_config {
341 u8 willing;
342 u8 mbc;
343 u8 pfccap;
344 u8 pfcenable;
345};
346
347/* IEEE 802.1Qaz Application Priority data */
348struct i40e_ieee_app_priority_table {
349 u8 priority;
350 u8 selector;
351 u16 protocolid;
352};
353
354struct i40e_dcbx_config {
355 u32 numapps;
356 struct i40e_ieee_ets_config etscfg;
357 struct i40e_ieee_ets_recommend etsrec;
358 struct i40e_ieee_pfc_config pfc;
359 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
360};
361
362/* Port hardware description */
363struct i40e_hw {
364 u8 __iomem *hw_addr;
365 void *back;
366
367 /* function pointer structs */
368 struct i40e_phy_info phy;
369 struct i40e_mac_info mac;
370 struct i40e_bus_info bus;
371 struct i40e_nvm_info nvm;
372 struct i40e_fc_info fc;
373
374 /* pci info */
375 u16 device_id;
376 u16 vendor_id;
377 u16 subsystem_device_id;
378 u16 subsystem_vendor_id;
379 u8 revision_id;
380 u8 port;
381 bool adapter_stopped;
382
383 /* capabilities for entire device and PCI func */
384 struct i40e_hw_capabilities dev_caps;
385 struct i40e_hw_capabilities func_caps;
386
387 /* Flow Director shared filter space */
388 u16 fdir_shared_filter_count;
389
390 /* device profile info */
391 u8 pf_id;
392 u16 main_vsi_seid;
393
394 /* Closest numa node to the device */
395 u16 numa_node;
396
397 /* Admin Queue info */
398 struct i40e_adminq_info aq;
399
400 /* HMC info */
401 struct i40e_hmc_info hmc; /* HMC info struct */
402
403 /* LLDP/DCBX Status */
404 u16 dcbx_status;
405
406 /* DCBX info */
407 struct i40e_dcbx_config local_dcbx_config;
408 struct i40e_dcbx_config remote_dcbx_config;
409
410 /* debug mask */
411 u32 debug_mask;
412};
413
414struct i40e_driver_version {
415 u8 major_version;
416 u8 minor_version;
417 u8 build_version;
418 u8 subbuild_version;
419};
420
421/* RX Descriptors */
422union i40e_16byte_rx_desc {
423 struct {
424 __le64 pkt_addr; /* Packet buffer address */
425 __le64 hdr_addr; /* Header buffer address */
426 } read;
427 struct {
428 struct {
429 struct {
430 union {
431 __le16 mirroring_status;
432 __le16 fcoe_ctx_id;
433 } mirr_fcoe;
434 __le16 l2tag1;
435 } lo_dword;
436 union {
437 __le32 rss; /* RSS Hash */
438 __le32 fd_id; /* Flow director filter id */
439 __le32 fcoe_param; /* FCoE DDP Context id */
440 } hi_dword;
441 } qword0;
442 struct {
443 /* ext status/error/pktype/length */
444 __le64 status_error_len;
445 } qword1;
446 } wb; /* writeback */
447};
448
449union i40e_32byte_rx_desc {
450 struct {
451 __le64 pkt_addr; /* Packet buffer address */
452 __le64 hdr_addr; /* Header buffer address */
453 /* bit 0 of hdr_buffer_addr is DD bit */
454 __le64 rsvd1;
455 __le64 rsvd2;
456 } read;
457 struct {
458 struct {
459 struct {
460 union {
461 __le16 mirroring_status;
462 __le16 fcoe_ctx_id;
463 } mirr_fcoe;
464 __le16 l2tag1;
465 } lo_dword;
466 union {
467 __le32 rss; /* RSS Hash */
468 __le32 fcoe_param; /* FCoE DDP Context id */
469 } hi_dword;
470 } qword0;
471 struct {
472 /* status/error/pktype/length */
473 __le64 status_error_len;
474 } qword1;
475 struct {
476 __le16 ext_status; /* extended status */
477 __le16 rsvd;
478 __le16 l2tag2_1;
479 __le16 l2tag2_2;
480 } qword2;
481 struct {
482 union {
483 __le32 flex_bytes_lo;
484 __le32 pe_status;
485 } lo_dword;
486 union {
487 __le32 flex_bytes_hi;
488 __le32 fd_id;
489 } hi_dword;
490 } qword3;
491 } wb; /* writeback */
492};
493
494#define I40E_RXD_QW1_STATUS_SHIFT 0
495#define I40E_RXD_QW1_STATUS_MASK (0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)
496
497enum i40e_rx_desc_status_bits {
498 /* Note: These are predefined bit offsets */
499 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
500 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
501 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
502 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
503 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
504 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
505 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
506 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
507 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
508 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
509 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
510 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
511 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
512 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
513 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18
514};
515
516#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
517#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
518 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
519
520#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
521#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
522 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
523
524enum i40e_rx_desc_fltstat_values {
525 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
526 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
527 I40E_RX_DESC_FLTSTAT_RSV = 2,
528 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
529};
530
531#define I40E_RXD_QW1_ERROR_SHIFT 19
532#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
533
534enum i40e_rx_desc_error_bits {
535 /* Note: These are predefined bit offsets */
536 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
537 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
538 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
539 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
540 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
541 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
542 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
543 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6
544};
545
546enum i40e_rx_desc_error_l3l4e_fcoe_masks {
547 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
548 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
549 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
550 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
551 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
552};
553
554#define I40E_RXD_QW1_PTYPE_SHIFT 30
555#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
556
557/* Packet type non-ip values */
558enum i40e_rx_l2_ptype {
559 I40E_RX_PTYPE_L2_RESERVED = 0,
560 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
561 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
562 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
563 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
564 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
565 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
566 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
567 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
568 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
569 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
570 I40E_RX_PTYPE_L2_ARP = 11,
571 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
572 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
573 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
574 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
575 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
576 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
577 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
578 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
579 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
580 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
581 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
582 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
583 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
584 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
585};
586
587struct i40e_rx_ptype_decoded {
588 u32 ptype:8;
589 u32 known:1;
590 u32 outer_ip:1;
591 u32 outer_ip_ver:1;
592 u32 outer_frag:1;
593 u32 tunnel_type:3;
594 u32 tunnel_end_prot:2;
595 u32 tunnel_end_frag:1;
596 u32 inner_prot:4;
597 u32 payload_layer:3;
598};
599
600enum i40e_rx_ptype_outer_ip {
601 I40E_RX_PTYPE_OUTER_L2 = 0,
602 I40E_RX_PTYPE_OUTER_IP = 1
603};
604
605enum i40e_rx_ptype_outer_ip_ver {
606 I40E_RX_PTYPE_OUTER_NONE = 0,
607 I40E_RX_PTYPE_OUTER_IPV4 = 0,
608 I40E_RX_PTYPE_OUTER_IPV6 = 1
609};
610
611enum i40e_rx_ptype_outer_fragmented {
612 I40E_RX_PTYPE_NOT_FRAG = 0,
613 I40E_RX_PTYPE_FRAG = 1
614};
615
616enum i40e_rx_ptype_tunnel_type {
617 I40E_RX_PTYPE_TUNNEL_NONE = 0,
618 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
619 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
620 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
621 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
622};
623
624enum i40e_rx_ptype_tunnel_end_prot {
625 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
626 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
627 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
628};
629
630enum i40e_rx_ptype_inner_prot {
631 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
632 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
633 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
634 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
635 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
636 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
637};
638
639enum i40e_rx_ptype_payload_layer {
640 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
641 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
642 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
643 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
644};
645
646#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
647#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
648 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
649
650#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
651#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
652 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
653
654#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
655#define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
656 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
657
658enum i40e_rx_desc_ext_status_bits {
659 /* Note: These are predefined bit offsets */
660 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
661 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
662 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
663 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
664 I40E_RX_DESC_EXT_STATUS_FTYPE_SHIFT = 6, /* 3 BITS */
665 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
666 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
667 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
668};
669
670enum i40e_rx_desc_pe_status_bits {
671 /* Note: These are predefined bit offsets */
672 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
673 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
674 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
675 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
676 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
677 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
678 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
679 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
680 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
681};
682
683#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
684#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
685
686#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
687#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
688 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
689
690#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
691#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
692 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
693
694enum i40e_rx_prog_status_desc_status_bits {
695 /* Note: These are predefined bit offsets */
696 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
697 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
698};
699
700enum i40e_rx_prog_status_desc_prog_id_masks {
701 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
702 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
703 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
704};
705
706enum i40e_rx_prog_status_desc_error_bits {
707 /* Note: These are predefined bit offsets */
708 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
709 I40E_RX_PROG_STATUS_DESC_NO_FD_QUOTA_SHIFT = 1,
710 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
711 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
712};
713
714/* TX Descriptor */
715struct i40e_tx_desc {
716 __le64 buffer_addr; /* Address of descriptor's data buf */
717 __le64 cmd_type_offset_bsz;
718};
719
720#define I40E_TXD_QW1_DTYPE_SHIFT 0
721#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
722
723enum i40e_tx_desc_dtype_value {
724 I40E_TX_DESC_DTYPE_DATA = 0x0,
725 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
726 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
727 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
728 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
729 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
730 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
731 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
732 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
733 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
734};
735
736#define I40E_TXD_QW1_CMD_SHIFT 4
737#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
738
739enum i40e_tx_desc_cmd_bits {
740 I40E_TX_DESC_CMD_EOP = 0x0001,
741 I40E_TX_DESC_CMD_RS = 0x0002,
742 I40E_TX_DESC_CMD_ICRC = 0x0004,
743 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
744 I40E_TX_DESC_CMD_DUMMY = 0x0010,
745 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
746 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
747 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
748 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
749 I40E_TX_DESC_CMD_FCOET = 0x0080,
750 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
751 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
752 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
753 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
754 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
755 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
756 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
757 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
758};
759
760#define I40E_TXD_QW1_OFFSET_SHIFT 16
761#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
762 I40E_TXD_QW1_OFFSET_SHIFT)
763
764enum i40e_tx_desc_length_fields {
765 /* Note: These are predefined bit offsets */
766 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
767 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
768 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
769};
770
771#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
772#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
773 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
774
775#define I40E_TXD_QW1_L2TAG1_SHIFT 48
776#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
777
778/* Context descriptors */
779struct i40e_tx_context_desc {
780 __le32 tunneling_params;
781 __le16 l2tag2;
782 __le16 rsvd;
783 __le64 type_cmd_tso_mss;
784};
785
786#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
787#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
788
789#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
790#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
791
792enum i40e_tx_ctx_desc_cmd_bits {
793 I40E_TX_CTX_DESC_TSO = 0x01,
794 I40E_TX_CTX_DESC_TSYN = 0x02,
795 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
796 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
797 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
798 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
799 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
800 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
801 I40E_TX_CTX_DESC_SWPE = 0x40
802};
803
804#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
805#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
806 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
807
808#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
809#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
810 I40E_TXD_CTX_QW1_MSS_SHIFT)
811
812#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
813#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
814
815#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
816#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
817 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
818
819enum i40e_tx_ctx_desc_eipt_offload {
820 I40E_TX_CTX_EXT_IP_NONE = 0x0,
821 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
822 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
823 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
824};
825
826#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
827#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
828 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
829
830#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
831#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
832
833#define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
834#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
835
836#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
837#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
838 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
839
840#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
841
842#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
843#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
844 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
845
846#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
847#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
848 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
849
850struct i40e_filter_program_desc {
851 __le32 qindex_flex_ptype_vsi;
852 __le32 rsvd;
853 __le32 dtype_cmd_cntindex;
854 __le32 fd_id;
855};
856#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
857#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
858 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
859#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
860#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
861 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
862#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
863#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
864 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
865
866/* Packet Classifier Types for filters */
867enum i40e_filter_pctype {
868 /* Note: Values 0-28 are reserved for future use */
869 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
870 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
871 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
872 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN = 32,
873 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
874 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
875 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
876 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
877 /* Note: Values 37-38 are reserved for future use */
878 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
879 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
880 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
881 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN = 42,
882 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
883 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
884 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
885 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
886 /* Note: Value 47 is reserved for future use */
887 I40E_FILTER_PCTYPE_FCOE_OX = 48,
888 I40E_FILTER_PCTYPE_FCOE_RX = 49,
889 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
890 /* Note: Values 51-62 are reserved for future use */
891 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
892};
893
894enum i40e_filter_program_desc_dest {
895 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
896 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
897 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
898};
899
900enum i40e_filter_program_desc_fd_status {
901 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
902 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
903 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
904 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
905};
906
907#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
908#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
909 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
910
911#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
912#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
913 I40E_TXD_FLTR_QW1_CMD_SHIFT)
914
915#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
916#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
917
918enum i40e_filter_program_desc_pcmd {
919 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
920 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
921};
922
923#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
924#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
925
926#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
927#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
928 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
929
930#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
931 I40E_TXD_FLTR_QW1_CMD_SHIFT)
932#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
933 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
934
935#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
936#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
937 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
938
939enum i40e_filter_type {
940 I40E_FLOW_DIRECTOR_FLTR = 0,
941 I40E_PE_QUAD_HASH_FLTR = 1,
942 I40E_ETHERTYPE_FLTR,
943 I40E_FCOE_CTX_FLTR,
944 I40E_MAC_VLAN_FLTR,
945 I40E_HASH_FLTR
946};
947
948struct i40e_vsi_context {
949 u16 seid;
950 u16 uplink_seid;
951 u16 vsi_number;
952 u16 vsis_allocated;
953 u16 vsis_unallocated;
954 u16 flags;
955 u8 pf_num;
956 u8 vf_num;
957 u8 connection_type;
958 struct i40e_aqc_vsi_properties_data info;
959};
960
961/* Statistics collected by each port, VSI, VEB, and S-channel */
962struct i40e_eth_stats {
963 u64 rx_bytes; /* gorc */
964 u64 rx_unicast; /* uprc */
965 u64 rx_multicast; /* mprc */
966 u64 rx_broadcast; /* bprc */
967 u64 rx_discards; /* rdpc */
968 u64 rx_errors; /* repc */
969 u64 rx_missed; /* rmpc */
970 u64 rx_unknown_protocol; /* rupp */
971 u64 tx_bytes; /* gotc */
972 u64 tx_unicast; /* uptc */
973 u64 tx_multicast; /* mptc */
974 u64 tx_broadcast; /* bptc */
975 u64 tx_discards; /* tdpc */
976 u64 tx_errors; /* tepc */
977};
978
979/* Statistics collected by the MAC */
980struct i40e_hw_port_stats {
981 /* eth stats collected by the port */
982 struct i40e_eth_stats eth;
983
984 /* additional port specific stats */
985 u64 tx_dropped_link_down; /* tdold */
986 u64 crc_errors; /* crcerrs */
987 u64 illegal_bytes; /* illerrc */
988 u64 error_bytes; /* errbc */
989 u64 mac_local_faults; /* mlfc */
990 u64 mac_remote_faults; /* mrfc */
991 u64 rx_length_errors; /* rlec */
992 u64 link_xon_rx; /* lxonrxc */
993 u64 link_xoff_rx; /* lxoffrxc */
994 u64 priority_xon_rx[8]; /* pxonrxc[8] */
995 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
996 u64 link_xon_tx; /* lxontxc */
997 u64 link_xoff_tx; /* lxofftxc */
998 u64 priority_xon_tx[8]; /* pxontxc[8] */
999 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1000 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1001 u64 rx_size_64; /* prc64 */
1002 u64 rx_size_127; /* prc127 */
1003 u64 rx_size_255; /* prc255 */
1004 u64 rx_size_511; /* prc511 */
1005 u64 rx_size_1023; /* prc1023 */
1006 u64 rx_size_1522; /* prc1522 */
1007 u64 rx_size_big; /* prc9522 */
1008 u64 rx_undersize; /* ruc */
1009 u64 rx_fragments; /* rfc */
1010 u64 rx_oversize; /* roc */
1011 u64 rx_jabber; /* rjc */
1012 u64 tx_size_64; /* ptc64 */
1013 u64 tx_size_127; /* ptc127 */
1014 u64 tx_size_255; /* ptc255 */
1015 u64 tx_size_511; /* ptc511 */
1016 u64 tx_size_1023; /* ptc1023 */
1017 u64 tx_size_1522; /* ptc1522 */
1018 u64 tx_size_big; /* ptc9522 */
1019 u64 mac_short_packet_dropped; /* mspdc */
1020 u64 checksum_error; /* xec */
1021};
1022
1023/* Checksum and Shadow RAM pointers */
1024#define I40E_SR_NVM_CONTROL_WORD 0x00
1025#define I40E_SR_EMP_MODULE_PTR 0x0F
1026#define I40E_SR_NVM_IMAGE_VERSION 0x18
1027#define I40E_SR_NVM_WAKE_ON_LAN 0x19
1028#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1029#define I40E_SR_NVM_EETRACK_LO 0x2D
1030#define I40E_SR_NVM_EETRACK_HI 0x2E
1031#define I40E_SR_VPD_PTR 0x2F
1032#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1033#define I40E_SR_SW_CHECKSUM_WORD 0x3F
1034
1035/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1036#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1037#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1038#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1039#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1040
1041/* Shadow RAM related */
1042#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1043#define I40E_SR_WORDS_IN_1KB 512
1044/* Checksum should be calculated such that after adding all the words,
1045 * including the checksum word itself, the sum should be 0xBABA.
1046 */
1047#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1048
1049#define I40E_SRRD_SRCTL_ATTEMPTS 100000
1050
1051enum i40e_switch_element_types {
1052 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1053 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1054 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1055 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1056 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1057 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1058 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1059 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1060 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1061};
1062
1063/* Supported EtherType filters */
1064enum i40e_ether_type_index {
1065 I40E_ETHER_TYPE_1588 = 0,
1066 I40E_ETHER_TYPE_FIP = 1,
1067 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1068 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1069 I40E_ETHER_TYPE_LLDP = 4,
1070 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1071 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1072 I40E_ETHER_TYPE_QCN_CNM = 7,
1073 I40E_ETHER_TYPE_8021X = 8,
1074 I40E_ETHER_TYPE_ARP = 9,
1075 I40E_ETHER_TYPE_RSV1 = 10,
1076 I40E_ETHER_TYPE_RSV2 = 11,
1077};
1078
1079/* Filter context base size is 1K */
1080#define I40E_HASH_FILTER_BASE_SIZE 1024
1081/* Supported Hash filter values */
1082enum i40e_hash_filter_size {
1083 I40E_HASH_FILTER_SIZE_1K = 0,
1084 I40E_HASH_FILTER_SIZE_2K = 1,
1085 I40E_HASH_FILTER_SIZE_4K = 2,
1086 I40E_HASH_FILTER_SIZE_8K = 3,
1087 I40E_HASH_FILTER_SIZE_16K = 4,
1088 I40E_HASH_FILTER_SIZE_32K = 5,
1089 I40E_HASH_FILTER_SIZE_64K = 6,
1090 I40E_HASH_FILTER_SIZE_128K = 7,
1091 I40E_HASH_FILTER_SIZE_256K = 8,
1092 I40E_HASH_FILTER_SIZE_512K = 9,
1093 I40E_HASH_FILTER_SIZE_1M = 10,
1094};
1095
1096/* DMA context base size is 0.5K */
1097#define I40E_DMA_CNTX_BASE_SIZE 512
1098/* Supported DMA context values */
1099enum i40e_dma_cntx_size {
1100 I40E_DMA_CNTX_SIZE_512 = 0,
1101 I40E_DMA_CNTX_SIZE_1K = 1,
1102 I40E_DMA_CNTX_SIZE_2K = 2,
1103 I40E_DMA_CNTX_SIZE_4K = 3,
1104 I40E_DMA_CNTX_SIZE_8K = 4,
1105 I40E_DMA_CNTX_SIZE_16K = 5,
1106 I40E_DMA_CNTX_SIZE_32K = 6,
1107 I40E_DMA_CNTX_SIZE_64K = 7,
1108 I40E_DMA_CNTX_SIZE_128K = 8,
1109 I40E_DMA_CNTX_SIZE_256K = 9,
1110};
1111
1112/* Supported Hash look up table (LUT) sizes */
1113enum i40e_hash_lut_size {
1114 I40E_HASH_LUT_SIZE_128 = 0,
1115 I40E_HASH_LUT_SIZE_512 = 1,
1116};
1117
1118/* Structure to hold a per PF filter control settings */
1119struct i40e_filter_control_settings {
1120 /* number of PE Quad Hash filter buckets */
1121 enum i40e_hash_filter_size pe_filt_num;
1122 /* number of PE Quad Hash contexts */
1123 enum i40e_dma_cntx_size pe_cntx_num;
1124 /* number of FCoE filter buckets */
1125 enum i40e_hash_filter_size fcoe_filt_num;
1126 /* number of FCoE DDP contexts */
1127 enum i40e_dma_cntx_size fcoe_cntx_num;
1128 /* size of the Hash LUT */
1129 enum i40e_hash_lut_size hash_lut_size;
1130 /* enable FDIR filters for PF and its VFs */
1131 bool enable_fdir;
1132 /* enable Ethertype filters for PF and its VFs */
1133 bool enable_ethtype;
1134 /* enable MAC/VLAN filters for PF and its VFs */
1135 bool enable_macvlan;
1136};
1137
1138/* Structure to hold device level control filter counts */
1139struct i40e_control_filter_stats {
1140 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1141 u16 etype_used; /* Used perfect EtherType filters */
1142 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1143 u16 etype_free; /* Un-used perfect EtherType filters */
1144};
1145
1146enum i40e_reset_type {
1147 I40E_RESET_POR = 0,
1148 I40E_RESET_CORER = 1,
1149 I40E_RESET_GLOBR = 2,
1150 I40E_RESET_EMPR = 3,
1151};
1152#endif /* _I40E_TYPE_H_ */
Linux kernel - Deliverables
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