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i40evf: Remove unused defines
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_type.h
CommitLineData
d358aa9a
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
af1a2a9c 4 * Copyright(c) 2013 - 2014 Intel Corporation.
d358aa9a
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Contact Information:
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 *
22 ******************************************************************************/
23
24#ifndef _I40E_TYPE_H_
25#define _I40E_TYPE_H_
26
27#include "i40e_status.h"
28#include "i40e_osdep.h"
29#include "i40e_register.h"
30#include "i40e_adminq.h"
31#include "i40e_hmc.h"
32#include "i40e_lan_hmc.h"
33
34/* Device IDs */
ab60085e
SN		 35#define I40E_DEV_ID_SFP_XL710 0x1572
36#define I40E_DEV_ID_SFP_X710 0x1573
37#define I40E_DEV_ID_QEMU 0x1574
38#define I40E_DEV_ID_KX_A 0x157F
39#define I40E_DEV_ID_KX_B 0x1580
40#define I40E_DEV_ID_KX_C 0x1581
41#define I40E_DEV_ID_KX_D 0x1582
42#define I40E_DEV_ID_QSFP_A 0x1583
43#define I40E_DEV_ID_QSFP_B 0x1584
44#define I40E_DEV_ID_QSFP_C 0x1585
45#define I40E_DEV_ID_VF 0x154C
46#define I40E_DEV_ID_VF_HV 0x1571
d358aa9a 47
ab60085e
SN		 48#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
49 (d) == I40E_DEV_ID_QSFP_B || \
50 (d) == I40E_DEV_ID_QSFP_C)
d358aa9a
GR		 51
52#define I40E_MAX_VSI_QP 16
53#define I40E_MAX_VF_VSI 3
54#define I40E_MAX_CHAINED_RX_BUFFERS 5
55#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
56
57/* Max default timeout in ms, */
58#define I40E_MAX_NVM_TIMEOUT 18000
59
60/* Switch from mc to the 2usec global time (this is the GTIME resolution) */
61#define I40E_MS_TO_GTIME(time) (((time) * 1000) / 2)
62
63/* forward declaration */
64struct i40e_hw;
65typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
66
d358aa9a
GR		 67/* Data type manipulation macros. */
68
69#define I40E_DESC_UNUSED(R) \
70 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
71 (R)->next_to_clean - (R)->next_to_use - 1)
72
73/* bitfields for Tx queue mapping in QTX_CTL */
74#define I40E_QTX_CTL_VF_QUEUE 0x0
75#define I40E_QTX_CTL_VM_QUEUE 0x1
76#define I40E_QTX_CTL_PF_QUEUE 0x2
77
78/* debug masks - set these bits in hw->debug_mask to control output */
79enum i40e_debug_mask {
80 I40E_DEBUG_INIT = 0x00000001,
81 I40E_DEBUG_RELEASE = 0x00000002,
82
83 I40E_DEBUG_LINK = 0x00000010,
84 I40E_DEBUG_PHY = 0x00000020,
85 I40E_DEBUG_HMC = 0x00000040,
86 I40E_DEBUG_NVM = 0x00000080,
87 I40E_DEBUG_LAN = 0x00000100,
88 I40E_DEBUG_FLOW = 0x00000200,
89 I40E_DEBUG_DCB = 0x00000400,
90 I40E_DEBUG_DIAG = 0x00000800,
c2e1b596 91 I40E_DEBUG_FD = 0x00001000,
d358aa9a
GR		 92
93 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
94 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
95 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
96 I40E_DEBUG_AQ_COMMAND = 0x06000000,
97 I40E_DEBUG_AQ = 0x0F000000,
98
99 I40E_DEBUG_USER = 0xF0000000,
100
101 I40E_DEBUG_ALL = 0xFFFFFFFF
102};
103
d358aa9a
GR		 104/* These are structs for managing the hardware information and the operations.
105 * The structures of function pointers are filled out at init time when we
106 * know for sure exactly which hardware we're working with. This gives us the
107 * flexibility of using the same main driver code but adapting to slightly
108 * different hardware needs as new parts are developed. For this architecture,
109 * the Firmware and AdminQ are intended to insulate the driver from most of the
110 * future changes, but these structures will also do part of the job.
111 */
112enum i40e_mac_type {
113 I40E_MAC_UNKNOWN = 0,
114 I40E_MAC_X710,
115 I40E_MAC_XL710,
116 I40E_MAC_VF,
117 I40E_MAC_GENERIC,
118};
119
120enum i40e_media_type {
121 I40E_MEDIA_TYPE_UNKNOWN = 0,
122 I40E_MEDIA_TYPE_FIBER,
123 I40E_MEDIA_TYPE_BASET,
124 I40E_MEDIA_TYPE_BACKPLANE,
125 I40E_MEDIA_TYPE_CX4,
126 I40E_MEDIA_TYPE_DA,
127 I40E_MEDIA_TYPE_VIRTUAL
128};
129
130enum i40e_fc_mode {
131 I40E_FC_NONE = 0,
132 I40E_FC_RX_PAUSE,
133 I40E_FC_TX_PAUSE,
134 I40E_FC_FULL,
135 I40E_FC_PFC,
136 I40E_FC_DEFAULT
137};
138
139enum i40e_vsi_type {
140 I40E_VSI_MAIN = 0,
141 I40E_VSI_VMDQ1,
142 I40E_VSI_VMDQ2,
143 I40E_VSI_CTRL,
144 I40E_VSI_FCOE,
145 I40E_VSI_MIRROR,
146 I40E_VSI_SRIOV,
147 I40E_VSI_FDIR,
148 I40E_VSI_TYPE_UNKNOWN
149};
150
151enum i40e_queue_type {
152 I40E_QUEUE_TYPE_RX = 0,
153 I40E_QUEUE_TYPE_TX,
154 I40E_QUEUE_TYPE_PE_CEQ,
155 I40E_QUEUE_TYPE_UNKNOWN
156};
157
158struct i40e_link_status {
159 enum i40e_aq_phy_type phy_type;
160 enum i40e_aq_link_speed link_speed;
161 u8 link_info;
162 u8 an_info;
163 u8 ext_info;
164 u8 loopback;
165 /* is Link Status Event notification to SW enabled */
166 bool lse_enable;
6bb3f23c
NP		 167 u16 max_frame_size;
168 bool crc_enable;
169 u8 pacing;
d358aa9a
GR		 170};
171
172struct i40e_phy_info {
173 struct i40e_link_status link_info;
174 struct i40e_link_status link_info_old;
175 u32 autoneg_advertised;
176 u32 phy_id;
177 u32 module_type;
178 bool get_link_info;
179 enum i40e_media_type media_type;
180};
181
182#define I40E_HW_CAP_MAX_GPIO 30
183/* Capabilities of a PF or a VF or the whole device */
184struct i40e_hw_capabilities {
185 u32 switch_mode;
186#define I40E_NVM_IMAGE_TYPE_EVB 0x0
187#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
188#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
189
190 u32 management_mode;
191 u32 npar_enable;
192 u32 os2bmc;
193 u32 valid_functions;
194 bool sr_iov_1_1;
195 bool vmdq;
196 bool evb_802_1_qbg; /* Edge Virtual Bridging */
197 bool evb_802_1_qbh; /* Bridge Port Extension */
198 bool dcb;
199 bool fcoe;
200 bool mfp_mode_1;
201 bool mgmt_cem;
202 bool ieee_1588;
203 bool iwarp;
204 bool fd;
205 u32 fd_filters_guaranteed;
206 u32 fd_filters_best_effort;
207 bool rss;
208 u32 rss_table_size;
209 u32 rss_table_entry_width;
210 bool led[I40E_HW_CAP_MAX_GPIO];
211 bool sdp[I40E_HW_CAP_MAX_GPIO];
212 u32 nvm_image_type;
213 u32 num_flow_director_filters;
214 u32 num_vfs;
215 u32 vf_base_id;
216 u32 num_vsis;
217 u32 num_rx_qp;
218 u32 num_tx_qp;
219 u32 base_queue;
220 u32 num_msix_vectors;
221 u32 num_msix_vectors_vf;
222 u32 led_pin_num;
223 u32 sdp_pin_num;
224 u32 mdio_port_num;
225 u32 mdio_port_mode;
226 u8 rx_buf_chain_len;
227 u32 enabled_tcmap;
228 u32 maxtc;
229};
230
231struct i40e_mac_info {
232 enum i40e_mac_type type;
233 u8 addr[ETH_ALEN];
234 u8 perm_addr[ETH_ALEN];
235 u8 san_addr[ETH_ALEN];
236 u16 max_fcoeq;
237};
238
239enum i40e_aq_resources_ids {
240 I40E_NVM_RESOURCE_ID = 1
241};
242
243enum i40e_aq_resource_access_type {
244 I40E_RESOURCE_READ = 1,
245 I40E_RESOURCE_WRITE
246};
247
248struct i40e_nvm_info {
249 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
250 u64 hw_semaphore_wait; /* - || - */
251 u32 timeout; /* [ms] */
252 u16 sr_size; /* Shadow RAM size in words */
253 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
254 u16 version; /* NVM package version */
255 u32 eetrack; /* NVM data version */
256};
257
258/* PCI bus types */
259enum i40e_bus_type {
260 i40e_bus_type_unknown = 0,
261 i40e_bus_type_pci,
262 i40e_bus_type_pcix,
263 i40e_bus_type_pci_express,
264 i40e_bus_type_reserved
265};
266
267/* PCI bus speeds */
268enum i40e_bus_speed {
269 i40e_bus_speed_unknown = 0,
270 i40e_bus_speed_33 = 33,
271 i40e_bus_speed_66 = 66,
272 i40e_bus_speed_100 = 100,
273 i40e_bus_speed_120 = 120,
274 i40e_bus_speed_133 = 133,
275 i40e_bus_speed_2500 = 2500,
276 i40e_bus_speed_5000 = 5000,
277 i40e_bus_speed_8000 = 8000,
278 i40e_bus_speed_reserved
279};
280
281/* PCI bus widths */
282enum i40e_bus_width {
283 i40e_bus_width_unknown = 0,
284 i40e_bus_width_pcie_x1 = 1,
285 i40e_bus_width_pcie_x2 = 2,
286 i40e_bus_width_pcie_x4 = 4,
287 i40e_bus_width_pcie_x8 = 8,
288 i40e_bus_width_32 = 32,
289 i40e_bus_width_64 = 64,
290 i40e_bus_width_reserved
291};
292
293/* Bus parameters */
294struct i40e_bus_info {
295 enum i40e_bus_speed speed;
296 enum i40e_bus_width width;
297 enum i40e_bus_type type;
298
299 u16 func;
300 u16 device;
301 u16 lan_id;
302};
303
304/* Flow control (FC) parameters */
305struct i40e_fc_info {
306 enum i40e_fc_mode current_mode; /* FC mode in effect */
307 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
308};
309
310#define I40E_MAX_TRAFFIC_CLASS 8
311#define I40E_MAX_USER_PRIORITY 8
312#define I40E_DCBX_MAX_APPS 32
313#define I40E_LLDPDU_SIZE 1500
314
315/* IEEE 802.1Qaz ETS Configuration data */
316struct i40e_ieee_ets_config {
317 u8 willing;
318 u8 cbs;
319 u8 maxtcs;
320 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
321 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
322 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
323};
324
325/* IEEE 802.1Qaz ETS Recommendation data */
326struct i40e_ieee_ets_recommend {
327 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
328 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
329 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
330};
331
332/* IEEE 802.1Qaz PFC Configuration data */
333struct i40e_ieee_pfc_config {
334 u8 willing;
335 u8 mbc;
336 u8 pfccap;
337 u8 pfcenable;
338};
339
340/* IEEE 802.1Qaz Application Priority data */
341struct i40e_ieee_app_priority_table {
342 u8 priority;
343 u8 selector;
344 u16 protocolid;
345};
346
347struct i40e_dcbx_config {
348 u32 numapps;
349 struct i40e_ieee_ets_config etscfg;
350 struct i40e_ieee_ets_recommend etsrec;
351 struct i40e_ieee_pfc_config pfc;
352 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
353};
354
355/* Port hardware description */
356struct i40e_hw {
357 u8 __iomem *hw_addr;
358 void *back;
359
360 /* function pointer structs */
361 struct i40e_phy_info phy;
362 struct i40e_mac_info mac;
363 struct i40e_bus_info bus;
364 struct i40e_nvm_info nvm;
365 struct i40e_fc_info fc;
366
367 /* pci info */
368 u16 device_id;
369 u16 vendor_id;
370 u16 subsystem_device_id;
371 u16 subsystem_vendor_id;
372 u8 revision_id;
373 u8 port;
374 bool adapter_stopped;
375
376 /* capabilities for entire device and PCI func */
377 struct i40e_hw_capabilities dev_caps;
378 struct i40e_hw_capabilities func_caps;
379
380 /* Flow Director shared filter space */
381 u16 fdir_shared_filter_count;
382
383 /* device profile info */
384 u8 pf_id;
385 u16 main_vsi_seid;
386
387 /* Closest numa node to the device */
388 u16 numa_node;
389
390 /* Admin Queue info */
391 struct i40e_adminq_info aq;
392
393 /* HMC info */
394 struct i40e_hmc_info hmc; /* HMC info struct */
395
396 /* LLDP/DCBX Status */
397 u16 dcbx_status;
398
399 /* DCBX info */
400 struct i40e_dcbx_config local_dcbx_config;
401 struct i40e_dcbx_config remote_dcbx_config;
402
403 /* debug mask */
404 u32 debug_mask;
405};
406
407struct i40e_driver_version {
408 u8 major_version;
409 u8 minor_version;
410 u8 build_version;
411 u8 subbuild_version;
d2466013 412 u8 driver_string[32];
d358aa9a
GR		 413};
414
415/* RX Descriptors */
416union i40e_16byte_rx_desc {
417 struct {
418 __le64 pkt_addr; /* Packet buffer address */
419 __le64 hdr_addr; /* Header buffer address */
420 } read;
421 struct {
422 struct {
423 struct {
424 union {
425 __le16 mirroring_status;
426 __le16 fcoe_ctx_id;
427 } mirr_fcoe;
428 __le16 l2tag1;
429 } lo_dword;
430 union {
431 __le32 rss; /* RSS Hash */
432 __le32 fd_id; /* Flow director filter id */
433 __le32 fcoe_param; /* FCoE DDP Context id */
434 } hi_dword;
435 } qword0;
436 struct {
437 /* ext status/error/pktype/length */
438 __le64 status_error_len;
439 } qword1;
440 } wb; /* writeback */
441};
442
443union i40e_32byte_rx_desc {
444 struct {
445 __le64 pkt_addr; /* Packet buffer address */
446 __le64 hdr_addr; /* Header buffer address */
447 /* bit 0 of hdr_buffer_addr is DD bit */
448 __le64 rsvd1;
449 __le64 rsvd2;
450 } read;
451 struct {
452 struct {
453 struct {
454 union {
455 __le16 mirroring_status;
456 __le16 fcoe_ctx_id;
457 } mirr_fcoe;
458 __le16 l2tag1;
459 } lo_dword;
460 union {
461 __le32 rss; /* RSS Hash */
462 __le32 fcoe_param; /* FCoE DDP Context id */
77e29bc6
ASJ		 463 /* Flow director filter id in case of
464 * Programming status desc WB
465 */
466 __le32 fd_id;
d358aa9a
GR		 467 } hi_dword;
468 } qword0;
469 struct {
470 /* status/error/pktype/length */
471 __le64 status_error_len;
472 } qword1;
473 struct {
474 __le16 ext_status; /* extended status */
475 __le16 rsvd;
476 __le16 l2tag2_1;
477 __le16 l2tag2_2;
478 } qword2;
479 struct {
480 union {
481 __le32 flex_bytes_lo;
482 __le32 pe_status;
483 } lo_dword;
484 union {
485 __le32 flex_bytes_hi;
486 __le32 fd_id;
487 } hi_dword;
488 } qword3;
489 } wb; /* writeback */
490};
491
492#define I40E_RXD_QW1_STATUS_SHIFT 0
493#define I40E_RXD_QW1_STATUS_MASK (0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)
494
495enum i40e_rx_desc_status_bits {
496 /* Note: These are predefined bit offsets */
497 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
498 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
499 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
500 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
501 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
502 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
503 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
504 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
505 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
506 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
507 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
508 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
509 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
510 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
511 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18
512};
513
514#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
515#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
516 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
517
518#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
519#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
520 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
521
522enum i40e_rx_desc_fltstat_values {
523 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
524 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
525 I40E_RX_DESC_FLTSTAT_RSV = 2,
526 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
527};
528
529#define I40E_RXD_QW1_ERROR_SHIFT 19
530#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
531
532enum i40e_rx_desc_error_bits {
533 /* Note: These are predefined bit offsets */
534 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
535 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
536 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
537 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
538 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
539 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
540 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
541 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6
542};
543
544enum i40e_rx_desc_error_l3l4e_fcoe_masks {
545 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
546 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
547 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
548 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
549 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
550};
551
552#define I40E_RXD_QW1_PTYPE_SHIFT 30
553#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
554
555/* Packet type non-ip values */
556enum i40e_rx_l2_ptype {
557 I40E_RX_PTYPE_L2_RESERVED = 0,
558 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
559 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
560 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
561 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
562 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
563 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
564 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
565 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
566 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
567 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
568 I40E_RX_PTYPE_L2_ARP = 11,
569 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
570 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
571 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
572 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
573 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
574 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
575 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
576 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
577 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
578 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
579 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
580 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
581 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
582 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
583};
584
585struct i40e_rx_ptype_decoded {
586 u32 ptype:8;
587 u32 known:1;
588 u32 outer_ip:1;
589 u32 outer_ip_ver:1;
590 u32 outer_frag:1;
591 u32 tunnel_type:3;
592 u32 tunnel_end_prot:2;
593 u32 tunnel_end_frag:1;
594 u32 inner_prot:4;
595 u32 payload_layer:3;
596};
597
598enum i40e_rx_ptype_outer_ip {
599 I40E_RX_PTYPE_OUTER_L2 = 0,
600 I40E_RX_PTYPE_OUTER_IP = 1
601};
602
603enum i40e_rx_ptype_outer_ip_ver {
604 I40E_RX_PTYPE_OUTER_NONE = 0,
605 I40E_RX_PTYPE_OUTER_IPV4 = 0,
606 I40E_RX_PTYPE_OUTER_IPV6 = 1
607};
608
609enum i40e_rx_ptype_outer_fragmented {
610 I40E_RX_PTYPE_NOT_FRAG = 0,
611 I40E_RX_PTYPE_FRAG = 1
612};
613
614enum i40e_rx_ptype_tunnel_type {
615 I40E_RX_PTYPE_TUNNEL_NONE = 0,
616 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
617 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
618 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
619 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
620};
621
622enum i40e_rx_ptype_tunnel_end_prot {
623 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
624 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
625 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
626};
627
628enum i40e_rx_ptype_inner_prot {
629 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
630 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
631 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
632 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
633 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
634 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
635};
636
637enum i40e_rx_ptype_payload_layer {
638 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
639 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
640 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
641 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
642};
643
644#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
645#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
646 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
647
648#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
649#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
650 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
651
652#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
653#define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
654 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
655
656enum i40e_rx_desc_ext_status_bits {
657 /* Note: These are predefined bit offsets */
658 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
659 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
660 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
661 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
662 I40E_RX_DESC_EXT_STATUS_FTYPE_SHIFT = 6, /* 3 BITS */
663 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
664 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
665 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
666};
667
668enum i40e_rx_desc_pe_status_bits {
669 /* Note: These are predefined bit offsets */
670 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
671 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
672 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
673 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
674 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
675 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
676 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
677 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
678 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
679};
680
681#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
682#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
683
684#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
685#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
686 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
687
688#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
689#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
690 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
691
692enum i40e_rx_prog_status_desc_status_bits {
693 /* Note: These are predefined bit offsets */
694 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
695 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
696};
697
698enum i40e_rx_prog_status_desc_prog_id_masks {
699 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
700 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
701 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
702};
703
704enum i40e_rx_prog_status_desc_error_bits {
705 /* Note: These are predefined bit offsets */
706 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
77e29bc6 707 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
d358aa9a
GR		 708 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
709 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
710};
711
712/* TX Descriptor */
713struct i40e_tx_desc {
714 __le64 buffer_addr; /* Address of descriptor's data buf */
715 __le64 cmd_type_offset_bsz;
716};
717
718#define I40E_TXD_QW1_DTYPE_SHIFT 0
719#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
720
721enum i40e_tx_desc_dtype_value {
722 I40E_TX_DESC_DTYPE_DATA = 0x0,
723 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
724 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
725 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
726 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
727 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
728 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
729 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
730 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
731 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
732};
733
734#define I40E_TXD_QW1_CMD_SHIFT 4
735#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
736
737enum i40e_tx_desc_cmd_bits {
738 I40E_TX_DESC_CMD_EOP = 0x0001,
739 I40E_TX_DESC_CMD_RS = 0x0002,
740 I40E_TX_DESC_CMD_ICRC = 0x0004,
741 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
742 I40E_TX_DESC_CMD_DUMMY = 0x0010,
743 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
744 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
745 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
746 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
747 I40E_TX_DESC_CMD_FCOET = 0x0080,
748 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
749 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
750 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
751 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
752 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
753 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
754 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
755 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
756};
757
758#define I40E_TXD_QW1_OFFSET_SHIFT 16
759#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
760 I40E_TXD_QW1_OFFSET_SHIFT)
761
762enum i40e_tx_desc_length_fields {
763 /* Note: These are predefined bit offsets */
764 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
765 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
766 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
767};
768
769#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
770#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
771 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
772
773#define I40E_TXD_QW1_L2TAG1_SHIFT 48
774#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
775
776/* Context descriptors */
777struct i40e_tx_context_desc {
778 __le32 tunneling_params;
779 __le16 l2tag2;
780 __le16 rsvd;
781 __le64 type_cmd_tso_mss;
782};
783
784#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
785#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
786
787#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
788#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
789
790enum i40e_tx_ctx_desc_cmd_bits {
791 I40E_TX_CTX_DESC_TSO = 0x01,
792 I40E_TX_CTX_DESC_TSYN = 0x02,
793 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
794 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
795 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
796 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
797 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
798 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
799 I40E_TX_CTX_DESC_SWPE = 0x40
800};
801
802#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
803#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
804 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
805
806#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
807#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
808 I40E_TXD_CTX_QW1_MSS_SHIFT)
809
810#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
811#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
812
813#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
814#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
815 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
816
817enum i40e_tx_ctx_desc_eipt_offload {
818 I40E_TX_CTX_EXT_IP_NONE = 0x0,
819 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
820 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
821 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
822};
823
824#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
825#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
826 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
827
828#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
829#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
830
831#define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
832#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
833
834#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
835#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
836 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
837
838#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
839
840#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
841#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
842 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
843
844#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
845#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
846 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
847
848struct i40e_filter_program_desc {
849 __le32 qindex_flex_ptype_vsi;
850 __le32 rsvd;
851 __le32 dtype_cmd_cntindex;
852 __le32 fd_id;
853};
854#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
855#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
856 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
857#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
858#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
859 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
860#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
861#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
862 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
863
864/* Packet Classifier Types for filters */
865enum i40e_filter_pctype {
866 /* Note: Values 0-28 are reserved for future use */
867 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
868 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
869 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
870 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN = 32,
871 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
872 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
873 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
874 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
875 /* Note: Values 37-38 are reserved for future use */
876 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
877 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
878 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
879 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN = 42,
880 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
881 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
882 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
883 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
884 /* Note: Value 47 is reserved for future use */
885 I40E_FILTER_PCTYPE_FCOE_OX = 48,
886 I40E_FILTER_PCTYPE_FCOE_RX = 49,
887 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
888 /* Note: Values 51-62 are reserved for future use */
889 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
890};
891
892enum i40e_filter_program_desc_dest {
893 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
894 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
895 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
896};
897
898enum i40e_filter_program_desc_fd_status {
899 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
900 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
901 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
902 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
903};
904
905#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
906#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
907 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
908
909#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
910#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
911 I40E_TXD_FLTR_QW1_CMD_SHIFT)
912
913#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
914#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
915
916enum i40e_filter_program_desc_pcmd {
917 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
918 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
919};
920
921#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
922#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
923
924#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
925#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
926 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
927
928#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
929 I40E_TXD_FLTR_QW1_CMD_SHIFT)
930#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
931 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
932
933#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
934#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
935 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
936
937enum i40e_filter_type {
938 I40E_FLOW_DIRECTOR_FLTR = 0,
939 I40E_PE_QUAD_HASH_FLTR = 1,
940 I40E_ETHERTYPE_FLTR,
941 I40E_FCOE_CTX_FLTR,
942 I40E_MAC_VLAN_FLTR,
943 I40E_HASH_FLTR
944};
945
946struct i40e_vsi_context {
947 u16 seid;
948 u16 uplink_seid;
949 u16 vsi_number;
950 u16 vsis_allocated;
951 u16 vsis_unallocated;
952 u16 flags;
953 u8 pf_num;
954 u8 vf_num;
955 u8 connection_type;
956 struct i40e_aqc_vsi_properties_data info;
957};
958
959/* Statistics collected by each port, VSI, VEB, and S-channel */
960struct i40e_eth_stats {
961 u64 rx_bytes; /* gorc */
962 u64 rx_unicast; /* uprc */
963 u64 rx_multicast; /* mprc */
964 u64 rx_broadcast; /* bprc */
965 u64 rx_discards; /* rdpc */
966 u64 rx_errors; /* repc */
967 u64 rx_missed; /* rmpc */
968 u64 rx_unknown_protocol; /* rupp */
969 u64 tx_bytes; /* gotc */
970 u64 tx_unicast; /* uptc */
971 u64 tx_multicast; /* mptc */
972 u64 tx_broadcast; /* bptc */
973 u64 tx_discards; /* tdpc */
974 u64 tx_errors; /* tepc */
975};
976
977/* Statistics collected by the MAC */
978struct i40e_hw_port_stats {
979 /* eth stats collected by the port */
980 struct i40e_eth_stats eth;
981
982 /* additional port specific stats */
983 u64 tx_dropped_link_down; /* tdold */
984 u64 crc_errors; /* crcerrs */
985 u64 illegal_bytes; /* illerrc */
986 u64 error_bytes; /* errbc */
987 u64 mac_local_faults; /* mlfc */
988 u64 mac_remote_faults; /* mrfc */
989 u64 rx_length_errors; /* rlec */
990 u64 link_xon_rx; /* lxonrxc */
991 u64 link_xoff_rx; /* lxoffrxc */
992 u64 priority_xon_rx[8]; /* pxonrxc[8] */
993 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
994 u64 link_xon_tx; /* lxontxc */
995 u64 link_xoff_tx; /* lxofftxc */
996 u64 priority_xon_tx[8]; /* pxontxc[8] */
997 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
998 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
999 u64 rx_size_64; /* prc64 */
1000 u64 rx_size_127; /* prc127 */
1001 u64 rx_size_255; /* prc255 */
1002 u64 rx_size_511; /* prc511 */
1003 u64 rx_size_1023; /* prc1023 */
1004 u64 rx_size_1522; /* prc1522 */
1005 u64 rx_size_big; /* prc9522 */
1006 u64 rx_undersize; /* ruc */
1007 u64 rx_fragments; /* rfc */
1008 u64 rx_oversize; /* roc */
1009 u64 rx_jabber; /* rjc */
1010 u64 tx_size_64; /* ptc64 */
1011 u64 tx_size_127; /* ptc127 */
1012 u64 tx_size_255; /* ptc255 */
1013 u64 tx_size_511; /* ptc511 */
1014 u64 tx_size_1023; /* ptc1023 */
1015 u64 tx_size_1522; /* ptc1522 */
1016 u64 tx_size_big; /* ptc9522 */
1017 u64 mac_short_packet_dropped; /* mspdc */
1018 u64 checksum_error; /* xec */
bee5af7e
ASJ		 1019 /* EEE LPI */
1020 bool tx_lpi_status;
1021 bool rx_lpi_status;
1022 u64 tx_lpi_count; /* etlpic */
1023 u64 rx_lpi_count; /* erlpic */
d358aa9a
GR		 1024};
1025
1026/* Checksum and Shadow RAM pointers */
1027#define I40E_SR_NVM_CONTROL_WORD 0x00
1028#define I40E_SR_EMP_MODULE_PTR 0x0F
1029#define I40E_SR_NVM_IMAGE_VERSION 0x18
1030#define I40E_SR_NVM_WAKE_ON_LAN 0x19
1031#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1032#define I40E_SR_NVM_EETRACK_LO 0x2D
1033#define I40E_SR_NVM_EETRACK_HI 0x2E
1034#define I40E_SR_VPD_PTR 0x2F
1035#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1036#define I40E_SR_SW_CHECKSUM_WORD 0x3F
1037
1038/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1039#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1040#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1041#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1042#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1043
1044/* Shadow RAM related */
1045#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1046#define I40E_SR_WORDS_IN_1KB 512
1047/* Checksum should be calculated such that after adding all the words,
1048 * including the checksum word itself, the sum should be 0xBABA.
1049 */
1050#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1051
1052#define I40E_SRRD_SRCTL_ATTEMPTS 100000
1053
1054enum i40e_switch_element_types {
1055 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1056 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1057 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1058 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1059 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1060 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1061 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1062 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1063 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1064};
1065
1066/* Supported EtherType filters */
1067enum i40e_ether_type_index {
1068 I40E_ETHER_TYPE_1588 = 0,
1069 I40E_ETHER_TYPE_FIP = 1,
1070 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1071 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1072 I40E_ETHER_TYPE_LLDP = 4,
1073 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1074 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1075 I40E_ETHER_TYPE_QCN_CNM = 7,
1076 I40E_ETHER_TYPE_8021X = 8,
1077 I40E_ETHER_TYPE_ARP = 9,
1078 I40E_ETHER_TYPE_RSV1 = 10,
1079 I40E_ETHER_TYPE_RSV2 = 11,
1080};
1081
1082/* Filter context base size is 1K */
1083#define I40E_HASH_FILTER_BASE_SIZE 1024
1084/* Supported Hash filter values */
1085enum i40e_hash_filter_size {
1086 I40E_HASH_FILTER_SIZE_1K = 0,
1087 I40E_HASH_FILTER_SIZE_2K = 1,
1088 I40E_HASH_FILTER_SIZE_4K = 2,
1089 I40E_HASH_FILTER_SIZE_8K = 3,
1090 I40E_HASH_FILTER_SIZE_16K = 4,
1091 I40E_HASH_FILTER_SIZE_32K = 5,
1092 I40E_HASH_FILTER_SIZE_64K = 6,
1093 I40E_HASH_FILTER_SIZE_128K = 7,
1094 I40E_HASH_FILTER_SIZE_256K = 8,
1095 I40E_HASH_FILTER_SIZE_512K = 9,
1096 I40E_HASH_FILTER_SIZE_1M = 10,
1097};
1098
1099/* DMA context base size is 0.5K */
1100#define I40E_DMA_CNTX_BASE_SIZE 512
1101/* Supported DMA context values */
1102enum i40e_dma_cntx_size {
1103 I40E_DMA_CNTX_SIZE_512 = 0,
1104 I40E_DMA_CNTX_SIZE_1K = 1,
1105 I40E_DMA_CNTX_SIZE_2K = 2,
1106 I40E_DMA_CNTX_SIZE_4K = 3,
1107 I40E_DMA_CNTX_SIZE_8K = 4,
1108 I40E_DMA_CNTX_SIZE_16K = 5,
1109 I40E_DMA_CNTX_SIZE_32K = 6,
1110 I40E_DMA_CNTX_SIZE_64K = 7,
1111 I40E_DMA_CNTX_SIZE_128K = 8,
1112 I40E_DMA_CNTX_SIZE_256K = 9,
1113};
1114
1115/* Supported Hash look up table (LUT) sizes */
1116enum i40e_hash_lut_size {
1117 I40E_HASH_LUT_SIZE_128 = 0,
1118 I40E_HASH_LUT_SIZE_512 = 1,
1119};
1120
1121/* Structure to hold a per PF filter control settings */
1122struct i40e_filter_control_settings {
1123 /* number of PE Quad Hash filter buckets */
1124 enum i40e_hash_filter_size pe_filt_num;
1125 /* number of PE Quad Hash contexts */
1126 enum i40e_dma_cntx_size pe_cntx_num;
1127 /* number of FCoE filter buckets */
1128 enum i40e_hash_filter_size fcoe_filt_num;
1129 /* number of FCoE DDP contexts */
1130 enum i40e_dma_cntx_size fcoe_cntx_num;
1131 /* size of the Hash LUT */
1132 enum i40e_hash_lut_size hash_lut_size;
1133 /* enable FDIR filters for PF and its VFs */
1134 bool enable_fdir;
1135 /* enable Ethertype filters for PF and its VFs */
1136 bool enable_ethtype;
1137 /* enable MAC/VLAN filters for PF and its VFs */
1138 bool enable_macvlan;
1139};
1140
1141/* Structure to hold device level control filter counts */
1142struct i40e_control_filter_stats {
1143 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1144 u16 etype_used; /* Used perfect EtherType filters */
1145 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1146 u16 etype_free; /* Un-used perfect EtherType filters */
1147};
1148
1149enum i40e_reset_type {
1150 I40E_RESET_POR = 0,
1151 I40E_RESET_CORER = 1,
1152 I40E_RESET_GLOBR = 2,
1153 I40E_RESET_EMPR = 3,
1154};
1155#endif /* _I40E_TYPE_H_ */
Linux kernel - Deliverables
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