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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
6e861326 | 4 | Copyright(c) 2007-2012 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* e1000_82575 | |
29 | * e1000_82576 | |
30 | */ | |
31 | ||
82bbcdeb JP |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
9d5c8243 | 34 | #include <linux/types.h> |
2d064c06 | 35 | #include <linux/if_ether.h> |
9d5c8243 AK |
36 | |
37 | #include "e1000_mac.h" | |
38 | #include "e1000_82575.h" | |
f96a8a0b | 39 | #include "e1000_i210.h" |
9d5c8243 AK |
40 | |
41 | static s32 igb_get_invariants_82575(struct e1000_hw *); | |
42 | static s32 igb_acquire_phy_82575(struct e1000_hw *); | |
43 | static void igb_release_phy_82575(struct e1000_hw *); | |
44 | static s32 igb_acquire_nvm_82575(struct e1000_hw *); | |
45 | static void igb_release_nvm_82575(struct e1000_hw *); | |
46 | static s32 igb_check_for_link_82575(struct e1000_hw *); | |
47 | static s32 igb_get_cfg_done_82575(struct e1000_hw *); | |
48 | static s32 igb_init_hw_82575(struct e1000_hw *); | |
49 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); | |
50 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); | |
bb2ac47b AD |
51 | static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *); |
52 | static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16); | |
9d5c8243 | 53 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
bb2ac47b | 54 | static s32 igb_reset_hw_82580(struct e1000_hw *); |
9d5c8243 | 55 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
da02cde1 CW |
56 | static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool); |
57 | static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool); | |
9d5c8243 | 58 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); |
2fb02a26 | 59 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *); |
9d5c8243 AK |
60 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); |
61 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *); | |
62 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); | |
9d5c8243 AK |
63 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, |
64 | u16 *); | |
65 | static s32 igb_get_phy_id_82575(struct e1000_hw *); | |
66 | static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); | |
67 | static bool igb_sgmii_active_82575(struct e1000_hw *); | |
68 | static s32 igb_reset_init_script_82575(struct e1000_hw *); | |
69 | static s32 igb_read_mac_addr_82575(struct e1000_hw *); | |
009bc06e | 70 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); |
99870a73 | 71 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); |
4322e561 CW |
72 | static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); |
73 | static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); | |
4322e561 CW |
74 | static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); |
75 | static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); | |
bb2ac47b AD |
76 | static const u16 e1000_82580_rxpbs_table[] = |
77 | { 36, 72, 144, 1, 2, 4, 8, 16, | |
78 | 35, 70, 140 }; | |
79 | #define E1000_82580_RXPBS_TABLE_SIZE \ | |
80 | (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) | |
81 | ||
4085f746 NN |
82 | /** |
83 | * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO | |
84 | * @hw: pointer to the HW structure | |
85 | * | |
86 | * Called to determine if the I2C pins are being used for I2C or as an | |
87 | * external MDIO interface since the two options are mutually exclusive. | |
88 | **/ | |
89 | static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) | |
90 | { | |
91 | u32 reg = 0; | |
92 | bool ext_mdio = false; | |
93 | ||
94 | switch (hw->mac.type) { | |
95 | case e1000_82575: | |
96 | case e1000_82576: | |
97 | reg = rd32(E1000_MDIC); | |
98 | ext_mdio = !!(reg & E1000_MDIC_DEST); | |
99 | break; | |
100 | case e1000_82580: | |
101 | case e1000_i350: | |
f96a8a0b CW |
102 | case e1000_i210: |
103 | case e1000_i211: | |
4085f746 NN |
104 | reg = rd32(E1000_MDICNFG); |
105 | ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); | |
106 | break; | |
107 | default: | |
108 | break; | |
109 | } | |
110 | return ext_mdio; | |
111 | } | |
112 | ||
9d5c8243 AK |
113 | static s32 igb_get_invariants_82575(struct e1000_hw *hw) |
114 | { | |
115 | struct e1000_phy_info *phy = &hw->phy; | |
116 | struct e1000_nvm_info *nvm = &hw->nvm; | |
117 | struct e1000_mac_info *mac = &hw->mac; | |
c1889bfe | 118 | struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; |
9d5c8243 AK |
119 | u32 eecd; |
120 | s32 ret_val; | |
121 | u16 size; | |
122 | u32 ctrl_ext = 0; | |
123 | ||
124 | switch (hw->device_id) { | |
125 | case E1000_DEV_ID_82575EB_COPPER: | |
126 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
127 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
128 | mac->type = e1000_82575; | |
129 | break; | |
2d064c06 | 130 | case E1000_DEV_ID_82576: |
9eb2341d | 131 | case E1000_DEV_ID_82576_NS: |
747d49ba | 132 | case E1000_DEV_ID_82576_NS_SERDES: |
2d064c06 AD |
133 | case E1000_DEV_ID_82576_FIBER: |
134 | case E1000_DEV_ID_82576_SERDES: | |
c8ea5ea9 | 135 | case E1000_DEV_ID_82576_QUAD_COPPER: |
b894fa26 | 136 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
4703bf73 | 137 | case E1000_DEV_ID_82576_SERDES_QUAD: |
2d064c06 AD |
138 | mac->type = e1000_82576; |
139 | break; | |
bb2ac47b AD |
140 | case E1000_DEV_ID_82580_COPPER: |
141 | case E1000_DEV_ID_82580_FIBER: | |
6493d24f | 142 | case E1000_DEV_ID_82580_QUAD_FIBER: |
bb2ac47b AD |
143 | case E1000_DEV_ID_82580_SERDES: |
144 | case E1000_DEV_ID_82580_SGMII: | |
145 | case E1000_DEV_ID_82580_COPPER_DUAL: | |
308fb39a JG |
146 | case E1000_DEV_ID_DH89XXCC_SGMII: |
147 | case E1000_DEV_ID_DH89XXCC_SERDES: | |
1b5dda33 GJ |
148 | case E1000_DEV_ID_DH89XXCC_BACKPLANE: |
149 | case E1000_DEV_ID_DH89XXCC_SFP: | |
bb2ac47b AD |
150 | mac->type = e1000_82580; |
151 | break; | |
d2ba2ed8 AD |
152 | case E1000_DEV_ID_I350_COPPER: |
153 | case E1000_DEV_ID_I350_FIBER: | |
154 | case E1000_DEV_ID_I350_SERDES: | |
155 | case E1000_DEV_ID_I350_SGMII: | |
156 | mac->type = e1000_i350; | |
157 | break; | |
f96a8a0b CW |
158 | case E1000_DEV_ID_I210_COPPER: |
159 | case E1000_DEV_ID_I210_COPPER_OEM1: | |
160 | case E1000_DEV_ID_I210_COPPER_IT: | |
161 | case E1000_DEV_ID_I210_FIBER: | |
162 | case E1000_DEV_ID_I210_SERDES: | |
163 | case E1000_DEV_ID_I210_SGMII: | |
164 | mac->type = e1000_i210; | |
165 | break; | |
166 | case E1000_DEV_ID_I211_COPPER: | |
167 | mac->type = e1000_i211; | |
168 | break; | |
9d5c8243 AK |
169 | default: |
170 | return -E1000_ERR_MAC_INIT; | |
171 | break; | |
172 | } | |
173 | ||
9d5c8243 AK |
174 | /* Set media type */ |
175 | /* | |
176 | * The 82575 uses bits 22:23 for link mode. The mode can be changed | |
177 | * based on the EEPROM. We cannot rely upon device ID. There | |
178 | * is no distinguishable difference between fiber and internal | |
179 | * SerDes mode on the 82575. There can be an external PHY attached | |
180 | * on the SGMII interface. For this, we'll set sgmii_active to true. | |
181 | */ | |
182 | phy->media_type = e1000_media_type_copper; | |
183 | dev_spec->sgmii_active = false; | |
184 | ||
185 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
2fb02a26 AD |
186 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
187 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
9d5c8243 | 188 | dev_spec->sgmii_active = true; |
2fb02a26 | 189 | break; |
bb2ac47b | 190 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: |
2fb02a26 AD |
191 | case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: |
192 | hw->phy.media_type = e1000_media_type_internal_serdes; | |
2fb02a26 AD |
193 | break; |
194 | default: | |
2fb02a26 | 195 | break; |
9d5c8243 | 196 | } |
2fb02a26 | 197 | |
9d5c8243 AK |
198 | /* Set mta register count */ |
199 | mac->mta_reg_count = 128; | |
200 | /* Set rar entry count */ | |
f96a8a0b CW |
201 | switch (mac->type) { |
202 | case e1000_82576: | |
2d064c06 | 203 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; |
f96a8a0b CW |
204 | break; |
205 | case e1000_82580: | |
bb2ac47b | 206 | mac->rar_entry_count = E1000_RAR_ENTRIES_82580; |
f96a8a0b CW |
207 | break; |
208 | case e1000_i350: | |
d2ba2ed8 | 209 | mac->rar_entry_count = E1000_RAR_ENTRIES_I350; |
f96a8a0b CW |
210 | break; |
211 | default: | |
212 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; | |
213 | break; | |
214 | } | |
bb2ac47b | 215 | /* reset */ |
d2ba2ed8 | 216 | if (mac->type >= e1000_82580) |
bb2ac47b AD |
217 | mac->ops.reset_hw = igb_reset_hw_82580; |
218 | else | |
219 | mac->ops.reset_hw = igb_reset_hw_82575; | |
f96a8a0b CW |
220 | |
221 | if (mac->type >= e1000_i210) { | |
222 | mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; | |
223 | mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; | |
224 | } else { | |
225 | mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; | |
226 | mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; | |
227 | } | |
228 | ||
9d5c8243 AK |
229 | /* Set if part includes ASF firmware */ |
230 | mac->asf_firmware_present = true; | |
231 | /* Set if manageability features are enabled. */ | |
232 | mac->arc_subsystem_valid = | |
233 | (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) | |
234 | ? true : false; | |
f96a8a0b CW |
235 | /* enable EEE on i350 parts and later parts */ |
236 | if (mac->type >= e1000_i350) | |
09b068d4 CW |
237 | dev_spec->eee_disable = false; |
238 | else | |
239 | dev_spec->eee_disable = true; | |
9d5c8243 AK |
240 | /* physical interface link setup */ |
241 | mac->ops.setup_physical_interface = | |
242 | (hw->phy.media_type == e1000_media_type_copper) | |
243 | ? igb_setup_copper_link_82575 | |
2fb02a26 | 244 | : igb_setup_serdes_link_82575; |
9d5c8243 AK |
245 | |
246 | /* NVM initialization */ | |
247 | eecd = rd32(E1000_EECD); | |
9d5c8243 AK |
248 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
249 | E1000_EECD_SIZE_EX_SHIFT); | |
250 | ||
251 | /* | |
252 | * Added to a constant, "size" becomes the left-shift value | |
253 | * for setting word_size. | |
254 | */ | |
255 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
5c3cad75 | 256 | |
925b11f7 CW |
257 | /* |
258 | * Check for invalid size | |
259 | */ | |
260 | if ((hw->mac.type == e1000_82576) && (size > 15)) { | |
261 | pr_notice("The NVM size is not valid, defaulting to 32K\n"); | |
262 | size = 15; | |
263 | } | |
264 | ||
f96a8a0b CW |
265 | nvm->word_size = 1 << size; |
266 | if (hw->mac.type < e1000_i210) { | |
267 | nvm->opcode_bits = 8; | |
268 | nvm->delay_usec = 1; | |
269 | switch (nvm->override) { | |
270 | case e1000_nvm_override_spi_large: | |
271 | nvm->page_size = 32; | |
272 | nvm->address_bits = 16; | |
273 | break; | |
274 | case e1000_nvm_override_spi_small: | |
275 | nvm->page_size = 8; | |
276 | nvm->address_bits = 8; | |
277 | break; | |
278 | default: | |
279 | nvm->page_size = eecd | |
280 | & E1000_EECD_ADDR_BITS ? 32 : 8; | |
281 | nvm->address_bits = eecd | |
282 | & E1000_EECD_ADDR_BITS ? 16 : 8; | |
283 | break; | |
284 | } | |
285 | if (nvm->word_size == (1 << 15)) | |
286 | nvm->page_size = 128; | |
287 | ||
288 | nvm->type = e1000_nvm_eeprom_spi; | |
289 | } else | |
290 | nvm->type = e1000_nvm_flash_hw; | |
291 | ||
4322e561 | 292 | /* NVM Function Pointers */ |
4322e561 CW |
293 | switch (hw->mac.type) { |
294 | case e1000_82580: | |
295 | nvm->ops.validate = igb_validate_nvm_checksum_82580; | |
296 | nvm->ops.update = igb_update_nvm_checksum_82580; | |
f96a8a0b CW |
297 | nvm->ops.acquire = igb_acquire_nvm_82575; |
298 | nvm->ops.release = igb_release_nvm_82575; | |
299 | if (nvm->word_size < (1 << 15)) | |
300 | nvm->ops.read = igb_read_nvm_eerd; | |
301 | else | |
302 | nvm->ops.read = igb_read_nvm_spi; | |
303 | nvm->ops.write = igb_write_nvm_spi; | |
4322e561 CW |
304 | break; |
305 | case e1000_i350: | |
306 | nvm->ops.validate = igb_validate_nvm_checksum_i350; | |
307 | nvm->ops.update = igb_update_nvm_checksum_i350; | |
f96a8a0b CW |
308 | nvm->ops.acquire = igb_acquire_nvm_82575; |
309 | nvm->ops.release = igb_release_nvm_82575; | |
310 | if (nvm->word_size < (1 << 15)) | |
311 | nvm->ops.read = igb_read_nvm_eerd; | |
312 | else | |
313 | nvm->ops.read = igb_read_nvm_spi; | |
314 | nvm->ops.write = igb_write_nvm_spi; | |
315 | break; | |
316 | case e1000_i210: | |
317 | nvm->ops.validate = igb_validate_nvm_checksum_i210; | |
318 | nvm->ops.update = igb_update_nvm_checksum_i210; | |
319 | nvm->ops.acquire = igb_acquire_nvm_i210; | |
320 | nvm->ops.release = igb_release_nvm_i210; | |
321 | nvm->ops.read = igb_read_nvm_srrd_i210; | |
322 | nvm->ops.valid_led_default = igb_valid_led_default_i210; | |
323 | break; | |
324 | case e1000_i211: | |
325 | nvm->ops.acquire = igb_acquire_nvm_i210; | |
326 | nvm->ops.release = igb_release_nvm_i210; | |
327 | nvm->ops.read = igb_read_nvm_i211; | |
328 | nvm->ops.valid_led_default = igb_valid_led_default_i210; | |
329 | nvm->ops.validate = NULL; | |
330 | nvm->ops.update = NULL; | |
331 | nvm->ops.write = NULL; | |
4322e561 CW |
332 | break; |
333 | default: | |
334 | nvm->ops.validate = igb_validate_nvm_checksum; | |
335 | nvm->ops.update = igb_update_nvm_checksum; | |
f96a8a0b CW |
336 | nvm->ops.acquire = igb_acquire_nvm_82575; |
337 | nvm->ops.release = igb_release_nvm_82575; | |
338 | if (nvm->word_size < (1 << 15)) | |
339 | nvm->ops.read = igb_read_nvm_eerd; | |
340 | else | |
341 | nvm->ops.read = igb_read_nvm_spi; | |
342 | nvm->ops.write = igb_write_nvm_spi; | |
343 | break; | |
4322e561 | 344 | } |
9d5c8243 | 345 | |
6b78bb1d CW |
346 | /* if part supports SR-IOV then initialize mailbox parameters */ |
347 | switch (mac->type) { | |
348 | case e1000_82576: | |
349 | case e1000_i350: | |
a0c98605 | 350 | igb_init_mbx_params_pf(hw); |
6b78bb1d CW |
351 | break; |
352 | default: | |
353 | break; | |
354 | } | |
a0c98605 | 355 | |
9d5c8243 AK |
356 | /* setup PHY parameters */ |
357 | if (phy->media_type != e1000_media_type_copper) { | |
358 | phy->type = e1000_phy_none; | |
359 | return 0; | |
360 | } | |
361 | ||
362 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
363 | phy->reset_delay_us = 100; | |
364 | ||
99870a73 AD |
365 | ctrl_ext = rd32(E1000_CTRL_EXT); |
366 | ||
9d5c8243 | 367 | /* PHY function pointers */ |
99870a73 | 368 | if (igb_sgmii_active_82575(hw)) { |
4085f746 | 369 | phy->ops.reset = igb_phy_hw_reset_sgmii_82575; |
99870a73 AD |
370 | ctrl_ext |= E1000_CTRL_I2C_ENA; |
371 | } else { | |
4085f746 | 372 | phy->ops.reset = igb_phy_hw_reset; |
99870a73 AD |
373 | ctrl_ext &= ~E1000_CTRL_I2C_ENA; |
374 | } | |
375 | ||
376 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
377 | igb_reset_mdicnfg_82580(hw); | |
4085f746 NN |
378 | |
379 | if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { | |
380 | phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; | |
381 | phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; | |
f96a8a0b CW |
382 | } else if ((hw->mac.type == e1000_82580) |
383 | || (hw->mac.type == e1000_i350)) { | |
4085f746 NN |
384 | phy->ops.read_reg = igb_read_phy_reg_82580; |
385 | phy->ops.write_reg = igb_write_phy_reg_82580; | |
f96a8a0b CW |
386 | } else if (hw->phy.type >= e1000_phy_i210) { |
387 | phy->ops.read_reg = igb_read_phy_reg_gs40g; | |
388 | phy->ops.write_reg = igb_write_phy_reg_gs40g; | |
9d5c8243 | 389 | } else { |
4085f746 NN |
390 | phy->ops.read_reg = igb_read_phy_reg_igp; |
391 | phy->ops.write_reg = igb_write_phy_reg_igp; | |
9d5c8243 AK |
392 | } |
393 | ||
19e588e7 AD |
394 | /* set lan id */ |
395 | hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> | |
396 | E1000_STATUS_FUNC_SHIFT; | |
397 | ||
9d5c8243 AK |
398 | /* Set phy->phy_addr and phy->id. */ |
399 | ret_val = igb_get_phy_id_82575(hw); | |
400 | if (ret_val) | |
401 | return ret_val; | |
402 | ||
403 | /* Verify phy id and set remaining function pointers */ | |
404 | switch (phy->id) { | |
308fb39a JG |
405 | case I347AT4_E_PHY_ID: |
406 | case M88E1112_E_PHY_ID: | |
9d5c8243 AK |
407 | case M88E1111_I_PHY_ID: |
408 | phy->type = e1000_phy_m88; | |
409 | phy->ops.get_phy_info = igb_get_phy_info_m88; | |
308fb39a JG |
410 | |
411 | if (phy->id == I347AT4_E_PHY_ID || | |
412 | phy->id == M88E1112_E_PHY_ID) | |
413 | phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; | |
414 | else | |
415 | phy->ops.get_cable_length = igb_get_cable_length_m88; | |
416 | ||
f96a8a0b CW |
417 | if (phy->id == I210_I_PHY_ID) { |
418 | phy->ops.get_cable_length = | |
419 | igb_get_cable_length_m88_gen2; | |
420 | phy->ops.set_d0_lplu_state = | |
421 | igb_set_d0_lplu_state_82580; | |
422 | phy->ops.set_d3_lplu_state = | |
423 | igb_set_d3_lplu_state_82580; | |
424 | } | |
9d5c8243 AK |
425 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; |
426 | break; | |
427 | case IGP03E1000_E_PHY_ID: | |
428 | phy->type = e1000_phy_igp_3; | |
429 | phy->ops.get_phy_info = igb_get_phy_info_igp; | |
430 | phy->ops.get_cable_length = igb_get_cable_length_igp_2; | |
431 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; | |
432 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; | |
433 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; | |
434 | break; | |
bb2ac47b | 435 | case I82580_I_PHY_ID: |
d2ba2ed8 | 436 | case I350_I_PHY_ID: |
bb2ac47b AD |
437 | phy->type = e1000_phy_82580; |
438 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580; | |
439 | phy->ops.get_cable_length = igb_get_cable_length_82580; | |
440 | phy->ops.get_phy_info = igb_get_phy_info_82580; | |
da02cde1 CW |
441 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; |
442 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; | |
bb2ac47b | 443 | break; |
f96a8a0b CW |
444 | case I210_I_PHY_ID: |
445 | phy->type = e1000_phy_i210; | |
446 | phy->ops.get_phy_info = igb_get_phy_info_m88; | |
447 | phy->ops.check_polarity = igb_check_polarity_m88; | |
448 | phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; | |
449 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; | |
450 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; | |
451 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; | |
452 | break; | |
9d5c8243 AK |
453 | default: |
454 | return -E1000_ERR_PHY; | |
455 | } | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | /** | |
733596be | 461 | * igb_acquire_phy_82575 - Acquire rights to access PHY |
9d5c8243 AK |
462 | * @hw: pointer to the HW structure |
463 | * | |
464 | * Acquire access rights to the correct PHY. This is a | |
465 | * function pointer entry point called by the api module. | |
466 | **/ | |
467 | static s32 igb_acquire_phy_82575(struct e1000_hw *hw) | |
468 | { | |
008c3422 | 469 | u16 mask = E1000_SWFW_PHY0_SM; |
9d5c8243 | 470 | |
008c3422 AD |
471 | if (hw->bus.func == E1000_FUNC_1) |
472 | mask = E1000_SWFW_PHY1_SM; | |
ede3ef0d NN |
473 | else if (hw->bus.func == E1000_FUNC_2) |
474 | mask = E1000_SWFW_PHY2_SM; | |
475 | else if (hw->bus.func == E1000_FUNC_3) | |
476 | mask = E1000_SWFW_PHY3_SM; | |
9d5c8243 | 477 | |
f96a8a0b | 478 | return hw->mac.ops.acquire_swfw_sync(hw, mask); |
9d5c8243 AK |
479 | } |
480 | ||
481 | /** | |
733596be | 482 | * igb_release_phy_82575 - Release rights to access PHY |
9d5c8243 AK |
483 | * @hw: pointer to the HW structure |
484 | * | |
485 | * A wrapper to release access rights to the correct PHY. This is a | |
486 | * function pointer entry point called by the api module. | |
487 | **/ | |
488 | static void igb_release_phy_82575(struct e1000_hw *hw) | |
489 | { | |
008c3422 AD |
490 | u16 mask = E1000_SWFW_PHY0_SM; |
491 | ||
492 | if (hw->bus.func == E1000_FUNC_1) | |
493 | mask = E1000_SWFW_PHY1_SM; | |
ede3ef0d NN |
494 | else if (hw->bus.func == E1000_FUNC_2) |
495 | mask = E1000_SWFW_PHY2_SM; | |
496 | else if (hw->bus.func == E1000_FUNC_3) | |
497 | mask = E1000_SWFW_PHY3_SM; | |
9d5c8243 | 498 | |
f96a8a0b | 499 | hw->mac.ops.release_swfw_sync(hw, mask); |
9d5c8243 AK |
500 | } |
501 | ||
502 | /** | |
733596be | 503 | * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii |
9d5c8243 AK |
504 | * @hw: pointer to the HW structure |
505 | * @offset: register offset to be read | |
506 | * @data: pointer to the read data | |
507 | * | |
508 | * Reads the PHY register at offset using the serial gigabit media independent | |
509 | * interface and stores the retrieved information in data. | |
510 | **/ | |
511 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
512 | u16 *data) | |
513 | { | |
bf6f7a92 | 514 | s32 ret_val = -E1000_ERR_PARAM; |
9d5c8243 AK |
515 | |
516 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 517 | hw_dbg("PHY Address %u is out of range\n", offset); |
bf6f7a92 | 518 | goto out; |
9d5c8243 AK |
519 | } |
520 | ||
bf6f7a92 AD |
521 | ret_val = hw->phy.ops.acquire(hw); |
522 | if (ret_val) | |
523 | goto out; | |
9d5c8243 | 524 | |
bf6f7a92 | 525 | ret_val = igb_read_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 526 | |
bf6f7a92 AD |
527 | hw->phy.ops.release(hw); |
528 | ||
529 | out: | |
530 | return ret_val; | |
9d5c8243 AK |
531 | } |
532 | ||
533 | /** | |
733596be | 534 | * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii |
9d5c8243 AK |
535 | * @hw: pointer to the HW structure |
536 | * @offset: register offset to write to | |
537 | * @data: data to write at register offset | |
538 | * | |
539 | * Writes the data to PHY register at the offset using the serial gigabit | |
540 | * media independent interface. | |
541 | **/ | |
542 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, | |
543 | u16 data) | |
544 | { | |
bf6f7a92 AD |
545 | s32 ret_val = -E1000_ERR_PARAM; |
546 | ||
9d5c8243 AK |
547 | |
548 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { | |
652fff32 | 549 | hw_dbg("PHY Address %d is out of range\n", offset); |
bf6f7a92 | 550 | goto out; |
9d5c8243 AK |
551 | } |
552 | ||
bf6f7a92 AD |
553 | ret_val = hw->phy.ops.acquire(hw); |
554 | if (ret_val) | |
555 | goto out; | |
9d5c8243 | 556 | |
bf6f7a92 | 557 | ret_val = igb_write_phy_reg_i2c(hw, offset, data); |
9d5c8243 | 558 | |
bf6f7a92 AD |
559 | hw->phy.ops.release(hw); |
560 | ||
561 | out: | |
562 | return ret_val; | |
9d5c8243 AK |
563 | } |
564 | ||
565 | /** | |
733596be | 566 | * igb_get_phy_id_82575 - Retrieve PHY addr and id |
9d5c8243 AK |
567 | * @hw: pointer to the HW structure |
568 | * | |
652fff32 | 569 | * Retrieves the PHY address and ID for both PHY's which do and do not use |
9d5c8243 AK |
570 | * sgmi interface. |
571 | **/ | |
572 | static s32 igb_get_phy_id_82575(struct e1000_hw *hw) | |
573 | { | |
574 | struct e1000_phy_info *phy = &hw->phy; | |
575 | s32 ret_val = 0; | |
576 | u16 phy_id; | |
2fb02a26 | 577 | u32 ctrl_ext; |
4085f746 | 578 | u32 mdic; |
9d5c8243 AK |
579 | |
580 | /* | |
581 | * For SGMII PHYs, we try the list of possible addresses until | |
582 | * we find one that works. For non-SGMII PHYs | |
583 | * (e.g. integrated copper PHYs), an address of 1 should | |
584 | * work. The result of this function should mean phy->phy_addr | |
585 | * and phy->id are set correctly. | |
586 | */ | |
587 | if (!(igb_sgmii_active_82575(hw))) { | |
588 | phy->addr = 1; | |
589 | ret_val = igb_get_phy_id(hw); | |
590 | goto out; | |
591 | } | |
592 | ||
4085f746 NN |
593 | if (igb_sgmii_uses_mdio_82575(hw)) { |
594 | switch (hw->mac.type) { | |
595 | case e1000_82575: | |
596 | case e1000_82576: | |
597 | mdic = rd32(E1000_MDIC); | |
598 | mdic &= E1000_MDIC_PHY_MASK; | |
599 | phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; | |
600 | break; | |
601 | case e1000_82580: | |
602 | case e1000_i350: | |
f96a8a0b CW |
603 | case e1000_i210: |
604 | case e1000_i211: | |
4085f746 NN |
605 | mdic = rd32(E1000_MDICNFG); |
606 | mdic &= E1000_MDICNFG_PHY_MASK; | |
607 | phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; | |
608 | break; | |
609 | default: | |
610 | ret_val = -E1000_ERR_PHY; | |
611 | goto out; | |
612 | break; | |
613 | } | |
614 | ret_val = igb_get_phy_id(hw); | |
615 | goto out; | |
616 | } | |
617 | ||
2fb02a26 AD |
618 | /* Power on sgmii phy if it is disabled */ |
619 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
620 | wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); | |
621 | wrfl(); | |
622 | msleep(300); | |
623 | ||
9d5c8243 AK |
624 | /* |
625 | * The address field in the I2CCMD register is 3 bits and 0 is invalid. | |
626 | * Therefore, we need to test 1-7 | |
627 | */ | |
628 | for (phy->addr = 1; phy->addr < 8; phy->addr++) { | |
629 | ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); | |
630 | if (ret_val == 0) { | |
652fff32 AK |
631 | hw_dbg("Vendor ID 0x%08X read at address %u\n", |
632 | phy_id, phy->addr); | |
9d5c8243 AK |
633 | /* |
634 | * At the time of this writing, The M88 part is | |
635 | * the only supported SGMII PHY product. | |
636 | */ | |
637 | if (phy_id == M88_VENDOR) | |
638 | break; | |
639 | } else { | |
652fff32 | 640 | hw_dbg("PHY address %u was unreadable\n", phy->addr); |
9d5c8243 AK |
641 | } |
642 | } | |
643 | ||
644 | /* A valid PHY type couldn't be found. */ | |
645 | if (phy->addr == 8) { | |
646 | phy->addr = 0; | |
647 | ret_val = -E1000_ERR_PHY; | |
648 | goto out; | |
2fb02a26 AD |
649 | } else { |
650 | ret_val = igb_get_phy_id(hw); | |
9d5c8243 AK |
651 | } |
652 | ||
2fb02a26 AD |
653 | /* restore previous sfp cage power state */ |
654 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
9d5c8243 AK |
655 | |
656 | out: | |
657 | return ret_val; | |
658 | } | |
659 | ||
660 | /** | |
733596be | 661 | * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset |
9d5c8243 AK |
662 | * @hw: pointer to the HW structure |
663 | * | |
664 | * Resets the PHY using the serial gigabit media independent interface. | |
665 | **/ | |
666 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) | |
667 | { | |
668 | s32 ret_val; | |
669 | ||
670 | /* | |
671 | * This isn't a true "hard" reset, but is the only reset | |
672 | * available to us at this time. | |
673 | */ | |
674 | ||
652fff32 | 675 | hw_dbg("Soft resetting SGMII attached PHY...\n"); |
9d5c8243 AK |
676 | |
677 | /* | |
678 | * SFP documentation requires the following to configure the SPF module | |
679 | * to work on SGMII. No further documentation is given. | |
680 | */ | |
a8d2a0c2 | 681 | ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); |
9d5c8243 AK |
682 | if (ret_val) |
683 | goto out; | |
684 | ||
685 | ret_val = igb_phy_sw_reset(hw); | |
686 | ||
687 | out: | |
688 | return ret_val; | |
689 | } | |
690 | ||
691 | /** | |
733596be | 692 | * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state |
9d5c8243 AK |
693 | * @hw: pointer to the HW structure |
694 | * @active: true to enable LPLU, false to disable | |
695 | * | |
696 | * Sets the LPLU D0 state according to the active flag. When | |
697 | * activating LPLU this function also disables smart speed | |
698 | * and vice versa. LPLU will not be activated unless the | |
699 | * device autonegotiation advertisement meets standards of | |
700 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
701 | * This is a function pointer entry point only called by | |
702 | * PHY setup routines. | |
703 | **/ | |
704 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) | |
705 | { | |
706 | struct e1000_phy_info *phy = &hw->phy; | |
707 | s32 ret_val; | |
708 | u16 data; | |
709 | ||
a8d2a0c2 | 710 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
711 | if (ret_val) |
712 | goto out; | |
713 | ||
714 | if (active) { | |
715 | data |= IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 716 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 717 | data); |
9d5c8243 AK |
718 | if (ret_val) |
719 | goto out; | |
720 | ||
721 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 722 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 723 | &data); |
9d5c8243 | 724 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
a8d2a0c2 | 725 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
652fff32 | 726 | data); |
9d5c8243 AK |
727 | if (ret_val) |
728 | goto out; | |
729 | } else { | |
730 | data &= ~IGP02E1000_PM_D0_LPLU; | |
a8d2a0c2 | 731 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
652fff32 | 732 | data); |
9d5c8243 AK |
733 | /* |
734 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
735 | * during Dx states where the power conservation is most | |
736 | * important. During driver activity we should enable | |
737 | * SmartSpeed, so performance is maintained. | |
738 | */ | |
739 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 740 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 741 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
742 | if (ret_val) |
743 | goto out; | |
744 | ||
745 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 746 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 747 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
748 | if (ret_val) |
749 | goto out; | |
750 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 751 | ret_val = phy->ops.read_reg(hw, |
652fff32 | 752 | IGP01E1000_PHY_PORT_CONFIG, &data); |
9d5c8243 AK |
753 | if (ret_val) |
754 | goto out; | |
755 | ||
756 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 757 | ret_val = phy->ops.write_reg(hw, |
652fff32 | 758 | IGP01E1000_PHY_PORT_CONFIG, data); |
9d5c8243 AK |
759 | if (ret_val) |
760 | goto out; | |
761 | } | |
762 | } | |
763 | ||
764 | out: | |
765 | return ret_val; | |
766 | } | |
767 | ||
da02cde1 CW |
768 | /** |
769 | * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state | |
770 | * @hw: pointer to the HW structure | |
771 | * @active: true to enable LPLU, false to disable | |
772 | * | |
773 | * Sets the LPLU D0 state according to the active flag. When | |
774 | * activating LPLU this function also disables smart speed | |
775 | * and vice versa. LPLU will not be activated unless the | |
776 | * device autonegotiation advertisement meets standards of | |
777 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
778 | * This is a function pointer entry point only called by | |
779 | * PHY setup routines. | |
780 | **/ | |
781 | static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) | |
782 | { | |
783 | struct e1000_phy_info *phy = &hw->phy; | |
784 | s32 ret_val = 0; | |
785 | u16 data; | |
786 | ||
787 | data = rd32(E1000_82580_PHY_POWER_MGMT); | |
788 | ||
789 | if (active) { | |
790 | data |= E1000_82580_PM_D0_LPLU; | |
791 | ||
792 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
793 | data &= ~E1000_82580_PM_SPD; | |
794 | } else { | |
795 | data &= ~E1000_82580_PM_D0_LPLU; | |
796 | ||
797 | /* | |
798 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
799 | * during Dx states where the power conservation is most | |
800 | * important. During driver activity we should enable | |
801 | * SmartSpeed, so performance is maintained. | |
802 | */ | |
803 | if (phy->smart_speed == e1000_smart_speed_on) | |
804 | data |= E1000_82580_PM_SPD; | |
805 | else if (phy->smart_speed == e1000_smart_speed_off) | |
806 | data &= ~E1000_82580_PM_SPD; } | |
807 | ||
808 | wr32(E1000_82580_PHY_POWER_MGMT, data); | |
809 | return ret_val; | |
810 | } | |
811 | ||
812 | /** | |
813 | * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3 | |
814 | * @hw: pointer to the HW structure | |
815 | * @active: boolean used to enable/disable lplu | |
816 | * | |
817 | * Success returns 0, Failure returns 1 | |
818 | * | |
819 | * The low power link up (lplu) state is set to the power management level D3 | |
820 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
821 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
822 | * is used during Dx states where the power conservation is most important. | |
823 | * During driver activity, SmartSpeed should be enabled so performance is | |
824 | * maintained. | |
825 | **/ | |
826 | s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) | |
827 | { | |
828 | struct e1000_phy_info *phy = &hw->phy; | |
829 | s32 ret_val = 0; | |
830 | u16 data; | |
831 | ||
832 | data = rd32(E1000_82580_PHY_POWER_MGMT); | |
833 | ||
834 | if (!active) { | |
835 | data &= ~E1000_82580_PM_D3_LPLU; | |
836 | /* | |
837 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
838 | * during Dx states where the power conservation is most | |
839 | * important. During driver activity we should enable | |
840 | * SmartSpeed, so performance is maintained. | |
841 | */ | |
842 | if (phy->smart_speed == e1000_smart_speed_on) | |
843 | data |= E1000_82580_PM_SPD; | |
844 | else if (phy->smart_speed == e1000_smart_speed_off) | |
845 | data &= ~E1000_82580_PM_SPD; | |
846 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
847 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
848 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
849 | data |= E1000_82580_PM_D3_LPLU; | |
850 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
851 | data &= ~E1000_82580_PM_SPD; | |
852 | } | |
853 | ||
854 | wr32(E1000_82580_PHY_POWER_MGMT, data); | |
855 | return ret_val; | |
856 | } | |
857 | ||
9d5c8243 | 858 | /** |
733596be | 859 | * igb_acquire_nvm_82575 - Request for access to EEPROM |
9d5c8243 AK |
860 | * @hw: pointer to the HW structure |
861 | * | |
652fff32 | 862 | * Acquire the necessary semaphores for exclusive access to the EEPROM. |
9d5c8243 AK |
863 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
864 | * Return successful if access grant bit set, else clear the request for | |
865 | * EEPROM access and return -E1000_ERR_NVM (-1). | |
866 | **/ | |
867 | static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) | |
868 | { | |
869 | s32 ret_val; | |
870 | ||
f96a8a0b | 871 | ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); |
9d5c8243 AK |
872 | if (ret_val) |
873 | goto out; | |
874 | ||
875 | ret_val = igb_acquire_nvm(hw); | |
876 | ||
877 | if (ret_val) | |
f96a8a0b | 878 | hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); |
9d5c8243 AK |
879 | |
880 | out: | |
881 | return ret_val; | |
882 | } | |
883 | ||
884 | /** | |
733596be | 885 | * igb_release_nvm_82575 - Release exclusive access to EEPROM |
9d5c8243 AK |
886 | * @hw: pointer to the HW structure |
887 | * | |
888 | * Stop any current commands to the EEPROM and clear the EEPROM request bit, | |
889 | * then release the semaphores acquired. | |
890 | **/ | |
891 | static void igb_release_nvm_82575(struct e1000_hw *hw) | |
892 | { | |
893 | igb_release_nvm(hw); | |
f96a8a0b | 894 | hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); |
9d5c8243 AK |
895 | } |
896 | ||
897 | /** | |
733596be | 898 | * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore |
9d5c8243 AK |
899 | * @hw: pointer to the HW structure |
900 | * @mask: specifies which semaphore to acquire | |
901 | * | |
902 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
903 | * will also specify which port we're acquiring the lock for. | |
904 | **/ | |
905 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
906 | { | |
907 | u32 swfw_sync; | |
908 | u32 swmask = mask; | |
909 | u32 fwmask = mask << 16; | |
910 | s32 ret_val = 0; | |
911 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ | |
912 | ||
913 | while (i < timeout) { | |
914 | if (igb_get_hw_semaphore(hw)) { | |
915 | ret_val = -E1000_ERR_SWFW_SYNC; | |
916 | goto out; | |
917 | } | |
918 | ||
919 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
920 | if (!(swfw_sync & (fwmask | swmask))) | |
921 | break; | |
922 | ||
923 | /* | |
924 | * Firmware currently using resource (fwmask) | |
925 | * or other software thread using resource (swmask) | |
926 | */ | |
927 | igb_put_hw_semaphore(hw); | |
928 | mdelay(5); | |
929 | i++; | |
930 | } | |
931 | ||
932 | if (i == timeout) { | |
652fff32 | 933 | hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
9d5c8243 AK |
934 | ret_val = -E1000_ERR_SWFW_SYNC; |
935 | goto out; | |
936 | } | |
937 | ||
938 | swfw_sync |= swmask; | |
939 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
940 | ||
941 | igb_put_hw_semaphore(hw); | |
942 | ||
943 | out: | |
944 | return ret_val; | |
945 | } | |
946 | ||
947 | /** | |
733596be | 948 | * igb_release_swfw_sync_82575 - Release SW/FW semaphore |
9d5c8243 AK |
949 | * @hw: pointer to the HW structure |
950 | * @mask: specifies which semaphore to acquire | |
951 | * | |
952 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
953 | * will also specify which port we're releasing the lock for. | |
954 | **/ | |
955 | static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) | |
956 | { | |
957 | u32 swfw_sync; | |
958 | ||
959 | while (igb_get_hw_semaphore(hw) != 0); | |
960 | /* Empty */ | |
961 | ||
962 | swfw_sync = rd32(E1000_SW_FW_SYNC); | |
963 | swfw_sync &= ~mask; | |
964 | wr32(E1000_SW_FW_SYNC, swfw_sync); | |
965 | ||
966 | igb_put_hw_semaphore(hw); | |
967 | } | |
968 | ||
969 | /** | |
733596be | 970 | * igb_get_cfg_done_82575 - Read config done bit |
9d5c8243 AK |
971 | * @hw: pointer to the HW structure |
972 | * | |
973 | * Read the management control register for the config done bit for | |
974 | * completion status. NOTE: silicon which is EEPROM-less will fail trying | |
975 | * to read the config done bit, so an error is *ONLY* logged and returns | |
976 | * 0. If we were to return with error, EEPROM-less silicon | |
977 | * would not be able to be reset or change link. | |
978 | **/ | |
979 | static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) | |
980 | { | |
981 | s32 timeout = PHY_CFG_TIMEOUT; | |
982 | s32 ret_val = 0; | |
983 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
984 | ||
985 | if (hw->bus.func == 1) | |
986 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
bb2ac47b AD |
987 | else if (hw->bus.func == E1000_FUNC_2) |
988 | mask = E1000_NVM_CFG_DONE_PORT_2; | |
989 | else if (hw->bus.func == E1000_FUNC_3) | |
990 | mask = E1000_NVM_CFG_DONE_PORT_3; | |
9d5c8243 AK |
991 | |
992 | while (timeout) { | |
993 | if (rd32(E1000_EEMNGCTL) & mask) | |
994 | break; | |
995 | msleep(1); | |
996 | timeout--; | |
997 | } | |
998 | if (!timeout) | |
652fff32 | 999 | hw_dbg("MNG configuration cycle has not completed.\n"); |
9d5c8243 AK |
1000 | |
1001 | /* If EEPROM is not marked present, init the PHY manually */ | |
1002 | if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && | |
1003 | (hw->phy.type == e1000_phy_igp_3)) | |
1004 | igb_phy_init_script_igp3(hw); | |
1005 | ||
1006 | return ret_val; | |
1007 | } | |
1008 | ||
1009 | /** | |
733596be | 1010 | * igb_check_for_link_82575 - Check for link |
9d5c8243 AK |
1011 | * @hw: pointer to the HW structure |
1012 | * | |
1013 | * If sgmii is enabled, then use the pcs register to determine link, otherwise | |
1014 | * use the generic interface for determining link. | |
1015 | **/ | |
1016 | static s32 igb_check_for_link_82575(struct e1000_hw *hw) | |
1017 | { | |
1018 | s32 ret_val; | |
1019 | u16 speed, duplex; | |
1020 | ||
70d92f86 | 1021 | if (hw->phy.media_type != e1000_media_type_copper) { |
9d5c8243 | 1022 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
2d064c06 | 1023 | &duplex); |
5d0932a5 AD |
1024 | /* |
1025 | * Use this flag to determine if link needs to be checked or | |
1026 | * not. If we have link clear the flag so that we do not | |
1027 | * continue to check for link. | |
1028 | */ | |
1029 | hw->mac.get_link_status = !hw->mac.serdes_has_link; | |
1030 | } else { | |
9d5c8243 | 1031 | ret_val = igb_check_for_copper_link(hw); |
5d0932a5 | 1032 | } |
9d5c8243 AK |
1033 | |
1034 | return ret_val; | |
1035 | } | |
70d92f86 | 1036 | |
88a268c1 NN |
1037 | /** |
1038 | * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown | |
1039 | * @hw: pointer to the HW structure | |
1040 | **/ | |
1041 | void igb_power_up_serdes_link_82575(struct e1000_hw *hw) | |
1042 | { | |
1043 | u32 reg; | |
1044 | ||
1045 | ||
1046 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
1047 | !igb_sgmii_active_82575(hw)) | |
1048 | return; | |
1049 | ||
1050 | /* Enable PCS to turn on link */ | |
1051 | reg = rd32(E1000_PCS_CFG0); | |
1052 | reg |= E1000_PCS_CFG_PCS_EN; | |
1053 | wr32(E1000_PCS_CFG0, reg); | |
1054 | ||
1055 | /* Power up the laser */ | |
1056 | reg = rd32(E1000_CTRL_EXT); | |
1057 | reg &= ~E1000_CTRL_EXT_SDP3_DATA; | |
1058 | wr32(E1000_CTRL_EXT, reg); | |
1059 | ||
1060 | /* flush the write to verify completion */ | |
1061 | wrfl(); | |
1062 | msleep(1); | |
1063 | } | |
1064 | ||
9d5c8243 | 1065 | /** |
733596be | 1066 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
9d5c8243 AK |
1067 | * @hw: pointer to the HW structure |
1068 | * @speed: stores the current speed | |
1069 | * @duplex: stores the current duplex | |
1070 | * | |
652fff32 | 1071 | * Using the physical coding sub-layer (PCS), retrieve the current speed and |
9d5c8243 AK |
1072 | * duplex, then store the values in the pointers provided. |
1073 | **/ | |
1074 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, | |
1075 | u16 *duplex) | |
1076 | { | |
1077 | struct e1000_mac_info *mac = &hw->mac; | |
1078 | u32 pcs; | |
1079 | ||
1080 | /* Set up defaults for the return values of this function */ | |
1081 | mac->serdes_has_link = false; | |
1082 | *speed = 0; | |
1083 | *duplex = 0; | |
1084 | ||
1085 | /* | |
1086 | * Read the PCS Status register for link state. For non-copper mode, | |
1087 | * the status register is not accurate. The PCS status register is | |
1088 | * used instead. | |
1089 | */ | |
1090 | pcs = rd32(E1000_PCS_LSTAT); | |
1091 | ||
1092 | /* | |
1093 | * The link up bit determines when link is up on autoneg. The sync ok | |
1094 | * gets set once both sides sync up and agree upon link. Stable link | |
1095 | * can be determined by checking for both link up and link sync ok | |
1096 | */ | |
1097 | if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { | |
1098 | mac->serdes_has_link = true; | |
1099 | ||
1100 | /* Detect and store PCS speed */ | |
1101 | if (pcs & E1000_PCS_LSTS_SPEED_1000) { | |
1102 | *speed = SPEED_1000; | |
1103 | } else if (pcs & E1000_PCS_LSTS_SPEED_100) { | |
1104 | *speed = SPEED_100; | |
1105 | } else { | |
1106 | *speed = SPEED_10; | |
1107 | } | |
1108 | ||
1109 | /* Detect and store PCS duplex */ | |
1110 | if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { | |
1111 | *duplex = FULL_DUPLEX; | |
1112 | } else { | |
1113 | *duplex = HALF_DUPLEX; | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
2d064c06 | 1120 | /** |
2fb02a26 | 1121 | * igb_shutdown_serdes_link_82575 - Remove link during power down |
9d5c8243 | 1122 | * @hw: pointer to the HW structure |
9d5c8243 | 1123 | * |
2d064c06 AD |
1124 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
1125 | * when management pass thru is not enabled. | |
9d5c8243 | 1126 | **/ |
2fb02a26 | 1127 | void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 1128 | { |
2d064c06 AD |
1129 | u32 reg; |
1130 | ||
53c992fa | 1131 | if (hw->phy.media_type != e1000_media_type_internal_serdes && |
2fb02a26 | 1132 | igb_sgmii_active_82575(hw)) |
2d064c06 AD |
1133 | return; |
1134 | ||
53c992fa | 1135 | if (!igb_enable_mng_pass_thru(hw)) { |
2d064c06 AD |
1136 | /* Disable PCS to turn off link */ |
1137 | reg = rd32(E1000_PCS_CFG0); | |
1138 | reg &= ~E1000_PCS_CFG_PCS_EN; | |
1139 | wr32(E1000_PCS_CFG0, reg); | |
1140 | ||
1141 | /* shutdown the laser */ | |
1142 | reg = rd32(E1000_CTRL_EXT); | |
2fb02a26 | 1143 | reg |= E1000_CTRL_EXT_SDP3_DATA; |
2d064c06 AD |
1144 | wr32(E1000_CTRL_EXT, reg); |
1145 | ||
1146 | /* flush the write to verify completion */ | |
1147 | wrfl(); | |
1148 | msleep(1); | |
1149 | } | |
9d5c8243 AK |
1150 | } |
1151 | ||
1152 | /** | |
733596be | 1153 | * igb_reset_hw_82575 - Reset hardware |
9d5c8243 AK |
1154 | * @hw: pointer to the HW structure |
1155 | * | |
1156 | * This resets the hardware into a known state. This is a | |
1157 | * function pointer entry point called by the api module. | |
1158 | **/ | |
1159 | static s32 igb_reset_hw_82575(struct e1000_hw *hw) | |
1160 | { | |
1161 | u32 ctrl, icr; | |
1162 | s32 ret_val; | |
1163 | ||
1164 | /* | |
1165 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
1166 | * on the last TLP read/write transaction when MAC is reset. | |
1167 | */ | |
1168 | ret_val = igb_disable_pcie_master(hw); | |
1169 | if (ret_val) | |
652fff32 | 1170 | hw_dbg("PCI-E Master disable polling has failed.\n"); |
9d5c8243 | 1171 | |
009bc06e AD |
1172 | /* set the completion timeout for interface */ |
1173 | ret_val = igb_set_pcie_completion_timeout(hw); | |
1174 | if (ret_val) { | |
1175 | hw_dbg("PCI-E Set completion timeout has failed.\n"); | |
1176 | } | |
1177 | ||
652fff32 | 1178 | hw_dbg("Masking off all interrupts\n"); |
9d5c8243 AK |
1179 | wr32(E1000_IMC, 0xffffffff); |
1180 | ||
1181 | wr32(E1000_RCTL, 0); | |
1182 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
1183 | wrfl(); | |
1184 | ||
1185 | msleep(10); | |
1186 | ||
1187 | ctrl = rd32(E1000_CTRL); | |
1188 | ||
652fff32 | 1189 | hw_dbg("Issuing a global reset to MAC\n"); |
9d5c8243 AK |
1190 | wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); |
1191 | ||
1192 | ret_val = igb_get_auto_rd_done(hw); | |
1193 | if (ret_val) { | |
1194 | /* | |
1195 | * When auto config read does not complete, do not | |
1196 | * return with an error. This can happen in situations | |
1197 | * where there is no eeprom and prevents getting link. | |
1198 | */ | |
652fff32 | 1199 | hw_dbg("Auto Read Done did not complete\n"); |
9d5c8243 AK |
1200 | } |
1201 | ||
1202 | /* If EEPROM is not present, run manual init scripts */ | |
1203 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
1204 | igb_reset_init_script_82575(hw); | |
1205 | ||
1206 | /* Clear any pending interrupt events. */ | |
1207 | wr32(E1000_IMC, 0xffffffff); | |
1208 | icr = rd32(E1000_ICR); | |
1209 | ||
5ac16659 AD |
1210 | /* Install any alternate MAC address into RAR0 */ |
1211 | ret_val = igb_check_alt_mac_addr(hw); | |
9d5c8243 AK |
1212 | |
1213 | return ret_val; | |
1214 | } | |
1215 | ||
1216 | /** | |
733596be | 1217 | * igb_init_hw_82575 - Initialize hardware |
9d5c8243 AK |
1218 | * @hw: pointer to the HW structure |
1219 | * | |
1220 | * This inits the hardware readying it for operation. | |
1221 | **/ | |
1222 | static s32 igb_init_hw_82575(struct e1000_hw *hw) | |
1223 | { | |
1224 | struct e1000_mac_info *mac = &hw->mac; | |
1225 | s32 ret_val; | |
1226 | u16 i, rar_count = mac->rar_entry_count; | |
1227 | ||
1228 | /* Initialize identification LED */ | |
1229 | ret_val = igb_id_led_init(hw); | |
1230 | if (ret_val) { | |
652fff32 | 1231 | hw_dbg("Error initializing identification LED\n"); |
9d5c8243 AK |
1232 | /* This is not fatal and we should not stop init due to this */ |
1233 | } | |
1234 | ||
1235 | /* Disabling VLAN filtering */ | |
652fff32 | 1236 | hw_dbg("Initializing the IEEE VLAN\n"); |
1128c756 CW |
1237 | if (hw->mac.type == e1000_i350) |
1238 | igb_clear_vfta_i350(hw); | |
1239 | else | |
1240 | igb_clear_vfta(hw); | |
9d5c8243 AK |
1241 | |
1242 | /* Setup the receive address */ | |
5ac16659 AD |
1243 | igb_init_rx_addrs(hw, rar_count); |
1244 | ||
9d5c8243 | 1245 | /* Zero out the Multicast HASH table */ |
652fff32 | 1246 | hw_dbg("Zeroing the MTA\n"); |
9d5c8243 AK |
1247 | for (i = 0; i < mac->mta_reg_count; i++) |
1248 | array_wr32(E1000_MTA, i, 0); | |
1249 | ||
68d480c4 AD |
1250 | /* Zero out the Unicast HASH table */ |
1251 | hw_dbg("Zeroing the UTA\n"); | |
1252 | for (i = 0; i < mac->uta_reg_count; i++) | |
1253 | array_wr32(E1000_UTA, i, 0); | |
1254 | ||
9d5c8243 AK |
1255 | /* Setup link and flow control */ |
1256 | ret_val = igb_setup_link(hw); | |
1257 | ||
1258 | /* | |
1259 | * Clear all of the statistics registers (clear on read). It is | |
1260 | * important that we do this after we have tried to establish link | |
1261 | * because the symbol error count will increment wildly if there | |
1262 | * is no link. | |
1263 | */ | |
1264 | igb_clear_hw_cntrs_82575(hw); | |
9d5c8243 AK |
1265 | return ret_val; |
1266 | } | |
1267 | ||
1268 | /** | |
733596be | 1269 | * igb_setup_copper_link_82575 - Configure copper link settings |
9d5c8243 AK |
1270 | * @hw: pointer to the HW structure |
1271 | * | |
1272 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1273 | * for link, once link is established calls to configure collision distance | |
1274 | * and flow control are called. | |
1275 | **/ | |
1276 | static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) | |
1277 | { | |
12645a19 | 1278 | u32 ctrl; |
9d5c8243 | 1279 | s32 ret_val; |
9d5c8243 AK |
1280 | |
1281 | ctrl = rd32(E1000_CTRL); | |
1282 | ctrl |= E1000_CTRL_SLU; | |
1283 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1284 | wr32(E1000_CTRL, ctrl); | |
1285 | ||
2fb02a26 AD |
1286 | ret_val = igb_setup_serdes_link_82575(hw); |
1287 | if (ret_val) | |
1288 | goto out; | |
1289 | ||
1290 | if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { | |
bb2ac47b AD |
1291 | /* allow time for SFP cage time to power up phy */ |
1292 | msleep(300); | |
1293 | ||
2fb02a26 AD |
1294 | ret_val = hw->phy.ops.reset(hw); |
1295 | if (ret_val) { | |
1296 | hw_dbg("Error resetting the PHY.\n"); | |
1297 | goto out; | |
1298 | } | |
1299 | } | |
9d5c8243 | 1300 | switch (hw->phy.type) { |
f96a8a0b | 1301 | case e1000_phy_i210: |
9d5c8243 | 1302 | case e1000_phy_m88: |
308fb39a JG |
1303 | if (hw->phy.id == I347AT4_E_PHY_ID || |
1304 | hw->phy.id == M88E1112_E_PHY_ID) | |
1305 | ret_val = igb_copper_link_setup_m88_gen2(hw); | |
1306 | else | |
1307 | ret_val = igb_copper_link_setup_m88(hw); | |
9d5c8243 AK |
1308 | break; |
1309 | case e1000_phy_igp_3: | |
1310 | ret_val = igb_copper_link_setup_igp(hw); | |
9d5c8243 | 1311 | break; |
bb2ac47b AD |
1312 | case e1000_phy_82580: |
1313 | ret_val = igb_copper_link_setup_82580(hw); | |
1314 | break; | |
9d5c8243 AK |
1315 | default: |
1316 | ret_val = -E1000_ERR_PHY; | |
1317 | break; | |
1318 | } | |
1319 | ||
1320 | if (ret_val) | |
1321 | goto out; | |
1322 | ||
81fadd81 | 1323 | ret_val = igb_setup_copper_link(hw); |
9d5c8243 AK |
1324 | out: |
1325 | return ret_val; | |
1326 | } | |
1327 | ||
1328 | /** | |
70d92f86 | 1329 | * igb_setup_serdes_link_82575 - Setup link for serdes |
9d5c8243 AK |
1330 | * @hw: pointer to the HW structure |
1331 | * | |
70d92f86 AD |
1332 | * Configure the physical coding sub-layer (PCS) link. The PCS link is |
1333 | * used on copper connections where the serialized gigabit media independent | |
1334 | * interface (sgmii), or serdes fiber is being used. Configures the link | |
1335 | * for auto-negotiation or forces speed/duplex. | |
9d5c8243 | 1336 | **/ |
2fb02a26 | 1337 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) |
9d5c8243 | 1338 | { |
bb2ac47b AD |
1339 | u32 ctrl_ext, ctrl_reg, reg; |
1340 | bool pcs_autoneg; | |
2c670b5b CW |
1341 | s32 ret_val = E1000_SUCCESS; |
1342 | u16 data; | |
2fb02a26 AD |
1343 | |
1344 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && | |
1345 | !igb_sgmii_active_82575(hw)) | |
2c670b5b CW |
1346 | return ret_val; |
1347 | ||
9d5c8243 AK |
1348 | |
1349 | /* | |
1350 | * On the 82575, SerDes loopback mode persists until it is | |
1351 | * explicitly turned off or a power cycle is performed. A read to | |
1352 | * the register does not indicate its status. Therefore, we ensure | |
1353 | * loopback mode is disabled during initialization. | |
1354 | */ | |
1355 | wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); | |
1356 | ||
2fb02a26 | 1357 | /* power on the sfp cage if present */ |
bb2ac47b AD |
1358 | ctrl_ext = rd32(E1000_CTRL_EXT); |
1359 | ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; | |
1360 | wr32(E1000_CTRL_EXT, ctrl_ext); | |
2fb02a26 AD |
1361 | |
1362 | ctrl_reg = rd32(E1000_CTRL); | |
1363 | ctrl_reg |= E1000_CTRL_SLU; | |
1364 | ||
1365 | if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { | |
1366 | /* set both sw defined pins */ | |
1367 | ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; | |
1368 | ||
1369 | /* Set switch control to serdes energy detect */ | |
1370 | reg = rd32(E1000_CONNSW); | |
1371 | reg |= E1000_CONNSW_ENRGSRC; | |
1372 | wr32(E1000_CONNSW, reg); | |
1373 | } | |
1374 | ||
1375 | reg = rd32(E1000_PCS_LCTL); | |
1376 | ||
bb2ac47b AD |
1377 | /* default pcs_autoneg to the same setting as mac autoneg */ |
1378 | pcs_autoneg = hw->mac.autoneg; | |
2fb02a26 | 1379 | |
bb2ac47b AD |
1380 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
1381 | case E1000_CTRL_EXT_LINK_MODE_SGMII: | |
1382 | /* sgmii mode lets the phy handle forcing speed/duplex */ | |
1383 | pcs_autoneg = true; | |
1384 | /* autoneg time out should be disabled for SGMII mode */ | |
2fb02a26 | 1385 | reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); |
bb2ac47b AD |
1386 | break; |
1387 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: | |
1388 | /* disable PCS autoneg and support parallel detect only */ | |
1389 | pcs_autoneg = false; | |
1390 | default: | |
2c670b5b CW |
1391 | if (hw->mac.type == e1000_82575 || |
1392 | hw->mac.type == e1000_82576) { | |
1393 | ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); | |
1394 | if (ret_val) { | |
1395 | printk(KERN_DEBUG "NVM Read Error\n\n"); | |
1396 | return ret_val; | |
1397 | } | |
1398 | ||
1399 | if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) | |
1400 | pcs_autoneg = false; | |
1401 | } | |
1402 | ||
bb2ac47b AD |
1403 | /* |
1404 | * non-SGMII modes only supports a speed of 1000/Full for the | |
1405 | * link so it is best to just force the MAC and let the pcs | |
1406 | * link either autoneg or be forced to 1000/Full | |
1407 | */ | |
2fb02a26 AD |
1408 | ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | |
1409 | E1000_CTRL_FD | E1000_CTRL_FRCDPX; | |
bb2ac47b AD |
1410 | |
1411 | /* set speed of 1000/Full if speed/duplex is forced */ | |
1412 | reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; | |
1413 | break; | |
921aa749 AD |
1414 | } |
1415 | ||
2fb02a26 | 1416 | wr32(E1000_CTRL, ctrl_reg); |
9d5c8243 AK |
1417 | |
1418 | /* | |
1419 | * New SerDes mode allows for forcing speed or autonegotiating speed | |
1420 | * at 1gb. Autoneg should be default set by most drivers. This is the | |
1421 | * mode that will be compatible with older link partners and switches. | |
1422 | * However, both are supported by the hardware and some drivers/tools. | |
1423 | */ | |
9d5c8243 AK |
1424 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | |
1425 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); | |
1426 | ||
2fb02a26 AD |
1427 | /* |
1428 | * We force flow control to prevent the CTRL register values from being | |
1429 | * overwritten by the autonegotiated flow control values | |
1430 | */ | |
1431 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; | |
1432 | ||
bb2ac47b | 1433 | if (pcs_autoneg) { |
9d5c8243 | 1434 | /* Set PCS register for autoneg */ |
bb2ac47b | 1435 | reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ |
70d92f86 | 1436 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ |
bb2ac47b | 1437 | hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); |
9d5c8243 | 1438 | } else { |
bb2ac47b | 1439 | /* Set PCS register for forced link */ |
d68caec6 | 1440 | reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ |
bb2ac47b AD |
1441 | |
1442 | hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); | |
9d5c8243 | 1443 | } |
726c09e7 | 1444 | |
9d5c8243 AK |
1445 | wr32(E1000_PCS_LCTL, reg); |
1446 | ||
2fb02a26 AD |
1447 | if (!igb_sgmii_active_82575(hw)) |
1448 | igb_force_mac_fc(hw); | |
9d5c8243 | 1449 | |
2c670b5b | 1450 | return ret_val; |
9d5c8243 AK |
1451 | } |
1452 | ||
1453 | /** | |
733596be | 1454 | * igb_sgmii_active_82575 - Return sgmii state |
9d5c8243 AK |
1455 | * @hw: pointer to the HW structure |
1456 | * | |
1457 | * 82575 silicon has a serialized gigabit media independent interface (sgmii) | |
1458 | * which can be enabled for use in the embedded applications. Simply | |
1459 | * return the current state of the sgmii interface. | |
1460 | **/ | |
1461 | static bool igb_sgmii_active_82575(struct e1000_hw *hw) | |
1462 | { | |
c1889bfe | 1463 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
c1889bfe | 1464 | return dev_spec->sgmii_active; |
9d5c8243 AK |
1465 | } |
1466 | ||
1467 | /** | |
733596be | 1468 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
9d5c8243 AK |
1469 | * @hw: pointer to the HW structure |
1470 | * | |
1471 | * Inits recommended HW defaults after a reset when there is no EEPROM | |
1472 | * detected. This is only for the 82575. | |
1473 | **/ | |
1474 | static s32 igb_reset_init_script_82575(struct e1000_hw *hw) | |
1475 | { | |
1476 | if (hw->mac.type == e1000_82575) { | |
652fff32 | 1477 | hw_dbg("Running reset init script for 82575\n"); |
9d5c8243 AK |
1478 | /* SerDes configuration via SERDESCTRL */ |
1479 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); | |
1480 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); | |
1481 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); | |
1482 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); | |
1483 | ||
1484 | /* CCM configuration via CCMCTL register */ | |
1485 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); | |
1486 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); | |
1487 | ||
1488 | /* PCIe lanes configuration */ | |
1489 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); | |
1490 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); | |
1491 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); | |
1492 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); | |
1493 | ||
1494 | /* PCIe PLL Configuration */ | |
1495 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); | |
1496 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); | |
1497 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); | |
1498 | } | |
1499 | ||
1500 | return 0; | |
1501 | } | |
1502 | ||
1503 | /** | |
733596be | 1504 | * igb_read_mac_addr_82575 - Read device MAC address |
9d5c8243 AK |
1505 | * @hw: pointer to the HW structure |
1506 | **/ | |
1507 | static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) | |
1508 | { | |
1509 | s32 ret_val = 0; | |
1510 | ||
22896639 AD |
1511 | /* |
1512 | * If there's an alternate MAC address place it in RAR0 | |
1513 | * so that it will override the Si installed default perm | |
1514 | * address. | |
1515 | */ | |
1516 | ret_val = igb_check_alt_mac_addr(hw); | |
1517 | if (ret_val) | |
1518 | goto out; | |
1519 | ||
1520 | ret_val = igb_read_mac_addr(hw); | |
9d5c8243 | 1521 | |
22896639 | 1522 | out: |
9d5c8243 AK |
1523 | return ret_val; |
1524 | } | |
1525 | ||
88a268c1 NN |
1526 | /** |
1527 | * igb_power_down_phy_copper_82575 - Remove link during PHY power down | |
1528 | * @hw: pointer to the HW structure | |
1529 | * | |
1530 | * In the case of a PHY power down to save power, or to turn off link during a | |
1531 | * driver unload, or wake on lan is not enabled, remove the link. | |
1532 | **/ | |
1533 | void igb_power_down_phy_copper_82575(struct e1000_hw *hw) | |
1534 | { | |
1535 | /* If the management interface is not enabled, then power down */ | |
1536 | if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) | |
1537 | igb_power_down_phy_copper(hw); | |
88a268c1 NN |
1538 | } |
1539 | ||
9d5c8243 | 1540 | /** |
733596be | 1541 | * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters |
9d5c8243 AK |
1542 | * @hw: pointer to the HW structure |
1543 | * | |
1544 | * Clears the hardware counters by reading the counter registers. | |
1545 | **/ | |
1546 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) | |
1547 | { | |
9d5c8243 AK |
1548 | igb_clear_hw_cntrs_base(hw); |
1549 | ||
cc9073bb AD |
1550 | rd32(E1000_PRC64); |
1551 | rd32(E1000_PRC127); | |
1552 | rd32(E1000_PRC255); | |
1553 | rd32(E1000_PRC511); | |
1554 | rd32(E1000_PRC1023); | |
1555 | rd32(E1000_PRC1522); | |
1556 | rd32(E1000_PTC64); | |
1557 | rd32(E1000_PTC127); | |
1558 | rd32(E1000_PTC255); | |
1559 | rd32(E1000_PTC511); | |
1560 | rd32(E1000_PTC1023); | |
1561 | rd32(E1000_PTC1522); | |
1562 | ||
1563 | rd32(E1000_ALGNERRC); | |
1564 | rd32(E1000_RXERRC); | |
1565 | rd32(E1000_TNCRS); | |
1566 | rd32(E1000_CEXTERR); | |
1567 | rd32(E1000_TSCTC); | |
1568 | rd32(E1000_TSCTFC); | |
1569 | ||
1570 | rd32(E1000_MGTPRC); | |
1571 | rd32(E1000_MGTPDC); | |
1572 | rd32(E1000_MGTPTC); | |
1573 | ||
1574 | rd32(E1000_IAC); | |
1575 | rd32(E1000_ICRXOC); | |
1576 | ||
1577 | rd32(E1000_ICRXPTC); | |
1578 | rd32(E1000_ICRXATC); | |
1579 | rd32(E1000_ICTXPTC); | |
1580 | rd32(E1000_ICTXATC); | |
1581 | rd32(E1000_ICTXQEC); | |
1582 | rd32(E1000_ICTXQMTC); | |
1583 | rd32(E1000_ICRXDMTC); | |
1584 | ||
1585 | rd32(E1000_CBTMPC); | |
1586 | rd32(E1000_HTDPMC); | |
1587 | rd32(E1000_CBRMPC); | |
1588 | rd32(E1000_RPTHC); | |
1589 | rd32(E1000_HGPTC); | |
1590 | rd32(E1000_HTCBDPC); | |
1591 | rd32(E1000_HGORCL); | |
1592 | rd32(E1000_HGORCH); | |
1593 | rd32(E1000_HGOTCL); | |
1594 | rd32(E1000_HGOTCH); | |
1595 | rd32(E1000_LENERRS); | |
9d5c8243 AK |
1596 | |
1597 | /* This register should not be read in copper configurations */ | |
2fb02a26 AD |
1598 | if (hw->phy.media_type == e1000_media_type_internal_serdes || |
1599 | igb_sgmii_active_82575(hw)) | |
cc9073bb | 1600 | rd32(E1000_SCVPC); |
9d5c8243 AK |
1601 | } |
1602 | ||
662d7205 AD |
1603 | /** |
1604 | * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable | |
1605 | * @hw: pointer to the HW structure | |
1606 | * | |
1607 | * After rx enable if managability is enabled then there is likely some | |
1608 | * bad data at the start of the fifo and possibly in the DMA fifo. This | |
1609 | * function clears the fifos and flushes any packets that came in as rx was | |
1610 | * being enabled. | |
1611 | **/ | |
1612 | void igb_rx_fifo_flush_82575(struct e1000_hw *hw) | |
1613 | { | |
1614 | u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; | |
1615 | int i, ms_wait; | |
1616 | ||
1617 | if (hw->mac.type != e1000_82575 || | |
1618 | !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) | |
1619 | return; | |
1620 | ||
1621 | /* Disable all RX queues */ | |
1622 | for (i = 0; i < 4; i++) { | |
1623 | rxdctl[i] = rd32(E1000_RXDCTL(i)); | |
1624 | wr32(E1000_RXDCTL(i), | |
1625 | rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); | |
1626 | } | |
1627 | /* Poll all queues to verify they have shut down */ | |
1628 | for (ms_wait = 0; ms_wait < 10; ms_wait++) { | |
1629 | msleep(1); | |
1630 | rx_enabled = 0; | |
1631 | for (i = 0; i < 4; i++) | |
1632 | rx_enabled |= rd32(E1000_RXDCTL(i)); | |
1633 | if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) | |
1634 | break; | |
1635 | } | |
1636 | ||
1637 | if (ms_wait == 10) | |
1638 | hw_dbg("Queue disable timed out after 10ms\n"); | |
1639 | ||
1640 | /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all | |
1641 | * incoming packets are rejected. Set enable and wait 2ms so that | |
1642 | * any packet that was coming in as RCTL.EN was set is flushed | |
1643 | */ | |
1644 | rfctl = rd32(E1000_RFCTL); | |
1645 | wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); | |
1646 | ||
1647 | rlpml = rd32(E1000_RLPML); | |
1648 | wr32(E1000_RLPML, 0); | |
1649 | ||
1650 | rctl = rd32(E1000_RCTL); | |
1651 | temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); | |
1652 | temp_rctl |= E1000_RCTL_LPE; | |
1653 | ||
1654 | wr32(E1000_RCTL, temp_rctl); | |
1655 | wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); | |
1656 | wrfl(); | |
1657 | msleep(2); | |
1658 | ||
1659 | /* Enable RX queues that were previously enabled and restore our | |
1660 | * previous state | |
1661 | */ | |
1662 | for (i = 0; i < 4; i++) | |
1663 | wr32(E1000_RXDCTL(i), rxdctl[i]); | |
1664 | wr32(E1000_RCTL, rctl); | |
1665 | wrfl(); | |
1666 | ||
1667 | wr32(E1000_RLPML, rlpml); | |
1668 | wr32(E1000_RFCTL, rfctl); | |
1669 | ||
1670 | /* Flush receive errors generated by workaround */ | |
1671 | rd32(E1000_ROC); | |
1672 | rd32(E1000_RNBC); | |
1673 | rd32(E1000_MPC); | |
1674 | } | |
1675 | ||
009bc06e AD |
1676 | /** |
1677 | * igb_set_pcie_completion_timeout - set pci-e completion timeout | |
1678 | * @hw: pointer to the HW structure | |
1679 | * | |
1680 | * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, | |
1681 | * however the hardware default for these parts is 500us to 1ms which is less | |
1682 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
1683 | * increase the value to either 10ms to 200ms for capability version 1 config, | |
1684 | * or 16ms to 55ms for version 2. | |
1685 | **/ | |
1686 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) | |
1687 | { | |
1688 | u32 gcr = rd32(E1000_GCR); | |
1689 | s32 ret_val = 0; | |
1690 | u16 pcie_devctl2; | |
1691 | ||
1692 | /* only take action if timeout value is defaulted to 0 */ | |
1693 | if (gcr & E1000_GCR_CMPL_TMOUT_MASK) | |
1694 | goto out; | |
1695 | ||
1696 | /* | |
1697 | * if capababilities version is type 1 we can write the | |
1698 | * timeout of 10ms to 200ms through the GCR register | |
1699 | */ | |
1700 | if (!(gcr & E1000_GCR_CAP_VER2)) { | |
1701 | gcr |= E1000_GCR_CMPL_TMOUT_10ms; | |
1702 | goto out; | |
1703 | } | |
1704 | ||
1705 | /* | |
1706 | * for version 2 capabilities we need to write the config space | |
1707 | * directly in order to set the completion timeout value for | |
1708 | * 16ms to 55ms | |
1709 | */ | |
1710 | ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1711 | &pcie_devctl2); | |
1712 | if (ret_val) | |
1713 | goto out; | |
1714 | ||
1715 | pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; | |
1716 | ||
1717 | ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, | |
1718 | &pcie_devctl2); | |
1719 | out: | |
1720 | /* disable completion timeout resend */ | |
1721 | gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; | |
1722 | ||
1723 | wr32(E1000_GCR, gcr); | |
1724 | return ret_val; | |
1725 | } | |
1726 | ||
13800469 GR |
1727 | /** |
1728 | * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing | |
1729 | * @hw: pointer to the hardware struct | |
1730 | * @enable: state to enter, either enabled or disabled | |
1731 | * @pf: Physical Function pool - do not set anti-spoofing for the PF | |
1732 | * | |
1733 | * enables/disables L2 switch anti-spoofing functionality. | |
1734 | **/ | |
1735 | void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) | |
1736 | { | |
1737 | u32 dtxswc; | |
1738 | ||
1739 | switch (hw->mac.type) { | |
1740 | case e1000_82576: | |
1741 | case e1000_i350: | |
1742 | dtxswc = rd32(E1000_DTXSWC); | |
1743 | if (enable) { | |
1744 | dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | | |
1745 | E1000_DTXSWC_VLAN_SPOOF_MASK); | |
1746 | /* The PF can spoof - it has to in order to | |
1747 | * support emulation mode NICs */ | |
1748 | dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); | |
1749 | } else { | |
1750 | dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | | |
1751 | E1000_DTXSWC_VLAN_SPOOF_MASK); | |
1752 | } | |
1753 | wr32(E1000_DTXSWC, dtxswc); | |
1754 | break; | |
1755 | default: | |
1756 | break; | |
1757 | } | |
1758 | } | |
1759 | ||
4ae196df AD |
1760 | /** |
1761 | * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback | |
1762 | * @hw: pointer to the hardware struct | |
1763 | * @enable: state to enter, either enabled or disabled | |
1764 | * | |
1765 | * enables/disables L2 switch loopback functionality. | |
1766 | **/ | |
1767 | void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) | |
1768 | { | |
ca2e3e7e AA |
1769 | u32 dtxswc; |
1770 | ||
1771 | switch (hw->mac.type) { | |
1772 | case e1000_82576: | |
1773 | dtxswc = rd32(E1000_DTXSWC); | |
1774 | if (enable) | |
1775 | dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1776 | else | |
1777 | dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1778 | wr32(E1000_DTXSWC, dtxswc); | |
1779 | break; | |
1780 | case e1000_i350: | |
1781 | dtxswc = rd32(E1000_TXSWC); | |
1782 | if (enable) | |
1783 | dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1784 | else | |
1785 | dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; | |
1786 | wr32(E1000_TXSWC, dtxswc); | |
1787 | break; | |
1788 | default: | |
1789 | /* Currently no other hardware supports loopback */ | |
1790 | break; | |
1791 | } | |
4ae196df | 1792 | |
4ae196df | 1793 | |
4ae196df AD |
1794 | } |
1795 | ||
1796 | /** | |
1797 | * igb_vmdq_set_replication_pf - enable or disable vmdq replication | |
1798 | * @hw: pointer to the hardware struct | |
1799 | * @enable: state to enter, either enabled or disabled | |
1800 | * | |
1801 | * enables/disables replication of packets across multiple pools. | |
1802 | **/ | |
1803 | void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) | |
1804 | { | |
1805 | u32 vt_ctl = rd32(E1000_VT_CTL); | |
1806 | ||
1807 | if (enable) | |
1808 | vt_ctl |= E1000_VT_CTL_VM_REPL_EN; | |
1809 | else | |
1810 | vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; | |
1811 | ||
1812 | wr32(E1000_VT_CTL, vt_ctl); | |
1813 | } | |
1814 | ||
bb2ac47b AD |
1815 | /** |
1816 | * igb_read_phy_reg_82580 - Read 82580 MDI control register | |
1817 | * @hw: pointer to the HW structure | |
1818 | * @offset: register offset to be read | |
1819 | * @data: pointer to the read data | |
1820 | * | |
1821 | * Reads the MDI control register in the PHY at offset and stores the | |
1822 | * information read to data. | |
1823 | **/ | |
1824 | static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) | |
1825 | { | |
bb2ac47b AD |
1826 | s32 ret_val; |
1827 | ||
1828 | ||
1829 | ret_val = hw->phy.ops.acquire(hw); | |
1830 | if (ret_val) | |
1831 | goto out; | |
1832 | ||
bb2ac47b AD |
1833 | ret_val = igb_read_phy_reg_mdic(hw, offset, data); |
1834 | ||
1835 | hw->phy.ops.release(hw); | |
1836 | ||
1837 | out: | |
1838 | return ret_val; | |
1839 | } | |
1840 | ||
1841 | /** | |
1842 | * igb_write_phy_reg_82580 - Write 82580 MDI control register | |
1843 | * @hw: pointer to the HW structure | |
1844 | * @offset: register offset to write to | |
1845 | * @data: data to write to register at offset | |
1846 | * | |
1847 | * Writes data to MDI control register in the PHY at offset. | |
1848 | **/ | |
1849 | static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) | |
1850 | { | |
bb2ac47b AD |
1851 | s32 ret_val; |
1852 | ||
1853 | ||
1854 | ret_val = hw->phy.ops.acquire(hw); | |
1855 | if (ret_val) | |
1856 | goto out; | |
1857 | ||
bb2ac47b AD |
1858 | ret_val = igb_write_phy_reg_mdic(hw, offset, data); |
1859 | ||
1860 | hw->phy.ops.release(hw); | |
1861 | ||
1862 | out: | |
1863 | return ret_val; | |
1864 | } | |
1865 | ||
08451e25 NN |
1866 | /** |
1867 | * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits | |
1868 | * @hw: pointer to the HW structure | |
1869 | * | |
1870 | * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on | |
1871 | * the values found in the EEPROM. This addresses an issue in which these | |
1872 | * bits are not restored from EEPROM after reset. | |
1873 | **/ | |
1874 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) | |
1875 | { | |
1876 | s32 ret_val = 0; | |
1877 | u32 mdicnfg; | |
1b5dda33 | 1878 | u16 nvm_data = 0; |
08451e25 NN |
1879 | |
1880 | if (hw->mac.type != e1000_82580) | |
1881 | goto out; | |
1882 | if (!igb_sgmii_active_82575(hw)) | |
1883 | goto out; | |
1884 | ||
1885 | ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + | |
1886 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | |
1887 | &nvm_data); | |
1888 | if (ret_val) { | |
1889 | hw_dbg("NVM Read Error\n"); | |
1890 | goto out; | |
1891 | } | |
1892 | ||
1893 | mdicnfg = rd32(E1000_MDICNFG); | |
1894 | if (nvm_data & NVM_WORD24_EXT_MDIO) | |
1895 | mdicnfg |= E1000_MDICNFG_EXT_MDIO; | |
1896 | if (nvm_data & NVM_WORD24_COM_MDIO) | |
1897 | mdicnfg |= E1000_MDICNFG_COM_MDIO; | |
1898 | wr32(E1000_MDICNFG, mdicnfg); | |
1899 | out: | |
1900 | return ret_val; | |
1901 | } | |
1902 | ||
bb2ac47b AD |
1903 | /** |
1904 | * igb_reset_hw_82580 - Reset hardware | |
1905 | * @hw: pointer to the HW structure | |
1906 | * | |
1907 | * This resets function or entire device (all ports, etc.) | |
1908 | * to a known state. | |
1909 | **/ | |
1910 | static s32 igb_reset_hw_82580(struct e1000_hw *hw) | |
1911 | { | |
1912 | s32 ret_val = 0; | |
1913 | /* BH SW mailbox bit in SW_FW_SYNC */ | |
1914 | u16 swmbsw_mask = E1000_SW_SYNCH_MB; | |
1915 | u32 ctrl, icr; | |
1916 | bool global_device_reset = hw->dev_spec._82575.global_device_reset; | |
1917 | ||
1918 | ||
1919 | hw->dev_spec._82575.global_device_reset = false; | |
1920 | ||
1921 | /* Get current control state. */ | |
1922 | ctrl = rd32(E1000_CTRL); | |
1923 | ||
1924 | /* | |
1925 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
1926 | * on the last TLP read/write transaction when MAC is reset. | |
1927 | */ | |
1928 | ret_val = igb_disable_pcie_master(hw); | |
1929 | if (ret_val) | |
1930 | hw_dbg("PCI-E Master disable polling has failed.\n"); | |
1931 | ||
1932 | hw_dbg("Masking off all interrupts\n"); | |
1933 | wr32(E1000_IMC, 0xffffffff); | |
1934 | wr32(E1000_RCTL, 0); | |
1935 | wr32(E1000_TCTL, E1000_TCTL_PSP); | |
1936 | wrfl(); | |
1937 | ||
1938 | msleep(10); | |
1939 | ||
1940 | /* Determine whether or not a global dev reset is requested */ | |
1941 | if (global_device_reset && | |
f96a8a0b | 1942 | hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) |
bb2ac47b AD |
1943 | global_device_reset = false; |
1944 | ||
1945 | if (global_device_reset && | |
1946 | !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) | |
1947 | ctrl |= E1000_CTRL_DEV_RST; | |
1948 | else | |
1949 | ctrl |= E1000_CTRL_RST; | |
1950 | ||
1951 | wr32(E1000_CTRL, ctrl); | |
064b4330 | 1952 | wrfl(); |
bb2ac47b AD |
1953 | |
1954 | /* Add delay to insure DEV_RST has time to complete */ | |
1955 | if (global_device_reset) | |
1956 | msleep(5); | |
1957 | ||
1958 | ret_val = igb_get_auto_rd_done(hw); | |
1959 | if (ret_val) { | |
1960 | /* | |
1961 | * When auto config read does not complete, do not | |
1962 | * return with an error. This can happen in situations | |
1963 | * where there is no eeprom and prevents getting link. | |
1964 | */ | |
1965 | hw_dbg("Auto Read Done did not complete\n"); | |
1966 | } | |
1967 | ||
1968 | /* If EEPROM is not present, run manual init scripts */ | |
1969 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) | |
1970 | igb_reset_init_script_82575(hw); | |
1971 | ||
1972 | /* clear global device reset status bit */ | |
1973 | wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); | |
1974 | ||
1975 | /* Clear any pending interrupt events. */ | |
1976 | wr32(E1000_IMC, 0xffffffff); | |
1977 | icr = rd32(E1000_ICR); | |
1978 | ||
08451e25 NN |
1979 | ret_val = igb_reset_mdicnfg_82580(hw); |
1980 | if (ret_val) | |
1981 | hw_dbg("Could not reset MDICNFG based on EEPROM\n"); | |
1982 | ||
bb2ac47b AD |
1983 | /* Install any alternate MAC address into RAR0 */ |
1984 | ret_val = igb_check_alt_mac_addr(hw); | |
1985 | ||
1986 | /* Release semaphore */ | |
1987 | if (global_device_reset) | |
f96a8a0b | 1988 | hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); |
bb2ac47b AD |
1989 | |
1990 | return ret_val; | |
1991 | } | |
1992 | ||
1993 | /** | |
1994 | * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size | |
1995 | * @data: data received by reading RXPBS register | |
1996 | * | |
1997 | * The 82580 uses a table based approach for packet buffer allocation sizes. | |
1998 | * This function converts the retrieved value into the correct table value | |
1999 | * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 | |
2000 | * 0x0 36 72 144 1 2 4 8 16 | |
2001 | * 0x8 35 70 140 rsv rsv rsv rsv rsv | |
2002 | */ | |
2003 | u16 igb_rxpbs_adjust_82580(u32 data) | |
2004 | { | |
2005 | u16 ret_val = 0; | |
2006 | ||
2007 | if (data < E1000_82580_RXPBS_TABLE_SIZE) | |
2008 | ret_val = e1000_82580_rxpbs_table[data]; | |
2009 | ||
2010 | return ret_val; | |
2011 | } | |
2012 | ||
4322e561 CW |
2013 | /** |
2014 | * igb_validate_nvm_checksum_with_offset - Validate EEPROM | |
2015 | * checksum | |
2016 | * @hw: pointer to the HW structure | |
2017 | * @offset: offset in words of the checksum protected region | |
2018 | * | |
2019 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
2020 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
2021 | **/ | |
bed45a6e ET |
2022 | static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, |
2023 | u16 offset) | |
4322e561 CW |
2024 | { |
2025 | s32 ret_val = 0; | |
2026 | u16 checksum = 0; | |
2027 | u16 i, nvm_data; | |
2028 | ||
2029 | for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { | |
2030 | ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); | |
2031 | if (ret_val) { | |
2032 | hw_dbg("NVM Read Error\n"); | |
2033 | goto out; | |
2034 | } | |
2035 | checksum += nvm_data; | |
2036 | } | |
2037 | ||
2038 | if (checksum != (u16) NVM_SUM) { | |
2039 | hw_dbg("NVM Checksum Invalid\n"); | |
2040 | ret_val = -E1000_ERR_NVM; | |
2041 | goto out; | |
2042 | } | |
2043 | ||
2044 | out: | |
2045 | return ret_val; | |
2046 | } | |
2047 | ||
2048 | /** | |
2049 | * igb_update_nvm_checksum_with_offset - Update EEPROM | |
2050 | * checksum | |
2051 | * @hw: pointer to the HW structure | |
2052 | * @offset: offset in words of the checksum protected region | |
2053 | * | |
2054 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
2055 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
2056 | * value to the EEPROM. | |
2057 | **/ | |
bed45a6e | 2058 | static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) |
4322e561 CW |
2059 | { |
2060 | s32 ret_val; | |
2061 | u16 checksum = 0; | |
2062 | u16 i, nvm_data; | |
2063 | ||
2064 | for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { | |
2065 | ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); | |
2066 | if (ret_val) { | |
2067 | hw_dbg("NVM Read Error while updating checksum.\n"); | |
2068 | goto out; | |
2069 | } | |
2070 | checksum += nvm_data; | |
2071 | } | |
2072 | checksum = (u16) NVM_SUM - checksum; | |
2073 | ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, | |
2074 | &checksum); | |
2075 | if (ret_val) | |
2076 | hw_dbg("NVM Write Error while updating checksum.\n"); | |
2077 | ||
2078 | out: | |
2079 | return ret_val; | |
2080 | } | |
2081 | ||
2082 | /** | |
2083 | * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum | |
2084 | * @hw: pointer to the HW structure | |
2085 | * | |
2086 | * Calculates the EEPROM section checksum by reading/adding each word of | |
2087 | * the EEPROM and then verifies that the sum of the EEPROM is | |
2088 | * equal to 0xBABA. | |
2089 | **/ | |
2090 | static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) | |
2091 | { | |
2092 | s32 ret_val = 0; | |
2093 | u16 eeprom_regions_count = 1; | |
2094 | u16 j, nvm_data; | |
2095 | u16 nvm_offset; | |
2096 | ||
2097 | ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); | |
2098 | if (ret_val) { | |
2099 | hw_dbg("NVM Read Error\n"); | |
2100 | goto out; | |
2101 | } | |
2102 | ||
2103 | if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { | |
34a0326e | 2104 | /* if checksums compatibility bit is set validate checksums |
4322e561 CW |
2105 | * for all 4 ports. */ |
2106 | eeprom_regions_count = 4; | |
2107 | } | |
2108 | ||
2109 | for (j = 0; j < eeprom_regions_count; j++) { | |
2110 | nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); | |
2111 | ret_val = igb_validate_nvm_checksum_with_offset(hw, | |
2112 | nvm_offset); | |
2113 | if (ret_val != 0) | |
2114 | goto out; | |
2115 | } | |
2116 | ||
2117 | out: | |
2118 | return ret_val; | |
2119 | } | |
2120 | ||
2121 | /** | |
2122 | * igb_update_nvm_checksum_82580 - Update EEPROM checksum | |
2123 | * @hw: pointer to the HW structure | |
2124 | * | |
2125 | * Updates the EEPROM section checksums for all 4 ports by reading/adding | |
2126 | * each word of the EEPROM up to the checksum. Then calculates the EEPROM | |
2127 | * checksum and writes the value to the EEPROM. | |
2128 | **/ | |
2129 | static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) | |
2130 | { | |
2131 | s32 ret_val; | |
2132 | u16 j, nvm_data; | |
2133 | u16 nvm_offset; | |
2134 | ||
2135 | ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); | |
2136 | if (ret_val) { | |
2137 | hw_dbg("NVM Read Error while updating checksum" | |
2138 | " compatibility bit.\n"); | |
2139 | goto out; | |
2140 | } | |
2141 | ||
2142 | if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { | |
2143 | /* set compatibility bit to validate checksums appropriately */ | |
2144 | nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; | |
2145 | ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, | |
2146 | &nvm_data); | |
2147 | if (ret_val) { | |
2148 | hw_dbg("NVM Write Error while updating checksum" | |
2149 | " compatibility bit.\n"); | |
2150 | goto out; | |
2151 | } | |
2152 | } | |
2153 | ||
2154 | for (j = 0; j < 4; j++) { | |
2155 | nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); | |
2156 | ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); | |
2157 | if (ret_val) | |
2158 | goto out; | |
2159 | } | |
2160 | ||
2161 | out: | |
2162 | return ret_val; | |
2163 | } | |
2164 | ||
2165 | /** | |
2166 | * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum | |
2167 | * @hw: pointer to the HW structure | |
2168 | * | |
2169 | * Calculates the EEPROM section checksum by reading/adding each word of | |
2170 | * the EEPROM and then verifies that the sum of the EEPROM is | |
2171 | * equal to 0xBABA. | |
2172 | **/ | |
2173 | static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) | |
2174 | { | |
2175 | s32 ret_val = 0; | |
2176 | u16 j; | |
2177 | u16 nvm_offset; | |
2178 | ||
2179 | for (j = 0; j < 4; j++) { | |
2180 | nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); | |
2181 | ret_val = igb_validate_nvm_checksum_with_offset(hw, | |
2182 | nvm_offset); | |
2183 | if (ret_val != 0) | |
2184 | goto out; | |
2185 | } | |
2186 | ||
2187 | out: | |
2188 | return ret_val; | |
2189 | } | |
2190 | ||
2191 | /** | |
2192 | * igb_update_nvm_checksum_i350 - Update EEPROM checksum | |
2193 | * @hw: pointer to the HW structure | |
2194 | * | |
2195 | * Updates the EEPROM section checksums for all 4 ports by reading/adding | |
2196 | * each word of the EEPROM up to the checksum. Then calculates the EEPROM | |
2197 | * checksum and writes the value to the EEPROM. | |
2198 | **/ | |
2199 | static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) | |
2200 | { | |
2201 | s32 ret_val = 0; | |
2202 | u16 j; | |
2203 | u16 nvm_offset; | |
2204 | ||
2205 | for (j = 0; j < 4; j++) { | |
2206 | nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); | |
2207 | ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); | |
2208 | if (ret_val != 0) | |
2209 | goto out; | |
2210 | } | |
2211 | ||
2212 | out: | |
2213 | return ret_val; | |
2214 | } | |
34a0326e | 2215 | |
09b068d4 CW |
2216 | /** |
2217 | * igb_set_eee_i350 - Enable/disable EEE support | |
2218 | * @hw: pointer to the HW structure | |
2219 | * | |
2220 | * Enable/disable EEE based on setting in dev_spec structure. | |
2221 | * | |
2222 | **/ | |
2223 | s32 igb_set_eee_i350(struct e1000_hw *hw) | |
2224 | { | |
2225 | s32 ret_val = 0; | |
2226 | u32 ipcnfg, eeer, ctrl_ext; | |
2227 | ||
2228 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
2229 | if ((hw->mac.type != e1000_i350) || | |
2230 | (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK)) | |
2231 | goto out; | |
2232 | ipcnfg = rd32(E1000_IPCNFG); | |
2233 | eeer = rd32(E1000_EEER); | |
2234 | ||
2235 | /* enable or disable per user setting */ | |
2236 | if (!(hw->dev_spec._82575.eee_disable)) { | |
2237 | ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | | |
2238 | E1000_IPCNFG_EEE_100M_AN); | |
2239 | eeer |= (E1000_EEER_TX_LPI_EN | | |
2240 | E1000_EEER_RX_LPI_EN | | |
2241 | E1000_EEER_LPI_FC); | |
2242 | ||
2243 | } else { | |
2244 | ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | | |
2245 | E1000_IPCNFG_EEE_100M_AN); | |
2246 | eeer &= ~(E1000_EEER_TX_LPI_EN | | |
2247 | E1000_EEER_RX_LPI_EN | | |
2248 | E1000_EEER_LPI_FC); | |
2249 | } | |
2250 | wr32(E1000_IPCNFG, ipcnfg); | |
2251 | wr32(E1000_EEER, eeer); | |
2252 | out: | |
2253 | ||
2254 | return ret_val; | |
2255 | } | |
4322e561 | 2256 | |
9d5c8243 | 2257 | static struct e1000_mac_operations e1000_mac_ops_82575 = { |
9d5c8243 AK |
2258 | .init_hw = igb_init_hw_82575, |
2259 | .check_for_link = igb_check_for_link_82575, | |
2d064c06 | 2260 | .rar_set = igb_rar_set, |
9d5c8243 AK |
2261 | .read_mac_addr = igb_read_mac_addr_82575, |
2262 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, | |
2263 | }; | |
2264 | ||
2265 | static struct e1000_phy_operations e1000_phy_ops_82575 = { | |
a8d2a0c2 | 2266 | .acquire = igb_acquire_phy_82575, |
9d5c8243 | 2267 | .get_cfg_done = igb_get_cfg_done_82575, |
a8d2a0c2 | 2268 | .release = igb_release_phy_82575, |
9d5c8243 AK |
2269 | }; |
2270 | ||
2271 | static struct e1000_nvm_operations e1000_nvm_ops_82575 = { | |
312c75ae AD |
2272 | .acquire = igb_acquire_nvm_82575, |
2273 | .read = igb_read_nvm_eerd, | |
2274 | .release = igb_release_nvm_82575, | |
2275 | .write = igb_write_nvm_spi, | |
9d5c8243 AK |
2276 | }; |
2277 | ||
2278 | const struct e1000_info e1000_82575_info = { | |
2279 | .get_invariants = igb_get_invariants_82575, | |
2280 | .mac_ops = &e1000_mac_ops_82575, | |
2281 | .phy_ops = &e1000_phy_ops_82575, | |
2282 | .nvm_ops = &e1000_nvm_ops_82575, | |
2283 | }; | |
2284 |